Commit message (Expand) | Author | Age | Files | Lines | |
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* | + Aarch64: completed LSE support for all interlocked operations | florian | 2021-04-16 | 1 | -0/+38 |
* | + Aarch64: use LSE if available for atomic intrinsics | florian | 2021-04-03 | 1 | -1/+36 |
* | * AArch64: added SIMD instructions (only plain ARMv8-A for now) | jonas | 2020-10-15 | 1 | -3/+3 |
* | * llvm sometimes uses the AArch64 framepointer register as a regvar in the | jonas | 2020-01-29 | 1 | -0/+7 |
* | o AArch64: | florian | 2019-10-11 | 1 | -4/+17 |
* | + support for software floating point exception handling on AArch64 (-CE) | florian | 2019-09-01 | 1 | -1/+67 |
* | * switched to using the stack pointer as base register for the temp allocator | jonas | 2015-02-23 | 1 | -6/+0 |
* | + aarch64 fpu init, atomic routines and memory barriers | jonas | 2015-02-23 | 1 | -0/+328 |