Add reg tests to LPC55S69 project (#989)

* Update LPCXpresso55S69 SDK to 2.13.1

* Enable print from non-secure side

* Add register tests

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

55 files changed, 9537 insertions, 7479 deletions

diff --git a/.github/scripts/core_checker.py b/.github/scripts/core_checker.py
index aae02ab25..471f24835 100755
--- a/.github/scripts/core_checker.py
+++ b/.github/scripts/core_checker.py
@@ -261,6 +261,7 @@ FREERTOS_IGNORED_PATTERNS = [
     r'.*CMSIS.*',
     r'.*/Nordic_Code/*',
     r'.*/ST_Code/*',
+    r'.*/NXP_Code/*',
     r'.*/makefile',
     r'.*/Makefile',
     r'.*/printf-stdarg\.c.*',
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/.gitignore b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/.gitignore
new file mode 100644
index 000000000..242758392
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/.gitignore
@@ -0,0 +1,6 @@
+# IDE autogenerated files.
+.settings/
+*.launch
+
+# Build Artifacts
+Debug/
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_armcc.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_armcc.h
deleted file mode 100644
index da9d654e1..000000000
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_armcc.h
+++ /dev/null
@@ -1,894 +0,0 @@
-/**************************************************************************//**

- * @file     cmsis_armcc.h

- * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file

- * @version  V5.1.0

- * @date     08. May 2019

- ******************************************************************************/

-/*

- * Copyright (c) 2009-2019 Arm Limited. All rights reserved.

- *

- * SPDX-License-Identifier: Apache-2.0

- *

- * Licensed under the Apache License, Version 2.0 (the License); you may

- * not use this file except in compliance with the License.

- * You may obtain a copy of the License at

- *

- * www.apache.org/licenses/LICENSE-2.0

- *

- * Unless required by applicable law or agreed to in writing, software

- * distributed under the License is distributed on an AS IS BASIS, WITHOUT

- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

- * See the License for the specific language governing permissions and

- * limitations under the License.

- */

-

-#ifndef __CMSIS_ARMCC_H

-#define __CMSIS_ARMCC_H

-

-

-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)

-  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"

-#endif

-

-/* CMSIS compiler control architecture macros */

-#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \

-     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )

-  #define __ARM_ARCH_6M__           1

-#endif

-

-#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))

-  #define __ARM_ARCH_7M__           1

-#endif

-

-#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))

-  #define __ARM_ARCH_7EM__          1

-#endif

-

-  /* __ARM_ARCH_8M_BASE__  not applicable */

-  /* __ARM_ARCH_8M_MAIN__  not applicable */

-

-/* CMSIS compiler control DSP macros */

-#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )

-  #define __ARM_FEATURE_DSP         1

-#endif

-

-/* CMSIS compiler specific defines */

-#ifndef   __ASM

-  #define __ASM                                  __asm

-#endif

-#ifndef   __INLINE

-  #define __INLINE                               __inline

-#endif

-#ifndef   __STATIC_INLINE

-  #define __STATIC_INLINE                        static __inline

-#endif

-#ifndef   __STATIC_FORCEINLINE                 

-  #define __STATIC_FORCEINLINE                   static __forceinline

-#endif           

-#ifndef   __NO_RETURN

-  #define __NO_RETURN                            __declspec(noreturn)

-#endif

-#ifndef   __USED

-  #define __USED                                 __attribute__((used))

-#endif

-#ifndef   __WEAK

-  #define __WEAK                                 __attribute__((weak))

-#endif

-#ifndef   __PACKED

-  #define __PACKED                               __attribute__((packed))

-#endif

-#ifndef   __PACKED_STRUCT

-  #define __PACKED_STRUCT                        __packed struct

-#endif

-#ifndef   __PACKED_UNION

-  #define __PACKED_UNION                         __packed union

-#endif

-#ifndef   __UNALIGNED_UINT32        /* deprecated */

-  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))

-#endif

-#ifndef   __UNALIGNED_UINT16_WRITE

-  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))

-#endif

-#ifndef   __UNALIGNED_UINT16_READ

-  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))

-#endif

-#ifndef   __UNALIGNED_UINT32_WRITE

-  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))

-#endif

-#ifndef   __UNALIGNED_UINT32_READ

-  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))

-#endif

-#ifndef   __ALIGNED

-  #define __ALIGNED(x)                           __attribute__((aligned(x)))

-#endif

-#ifndef   __RESTRICT

-  #define __RESTRICT                             __restrict

-#endif

-#ifndef   __COMPILER_BARRIER

-  #define __COMPILER_BARRIER()                   __memory_changed()

-#endif

-

-/* #########################  Startup and Lowlevel Init  ######################## */

-

-#ifndef __PROGRAM_START

-#define __PROGRAM_START           __main

-#endif

-

-#ifndef __INITIAL_SP

-#define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit

-#endif

-

-#ifndef __STACK_LIMIT

-#define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base

-#endif

-

-#ifndef __VECTOR_TABLE

-#define __VECTOR_TABLE            __Vectors

-#endif

-

-#ifndef __VECTOR_TABLE_ATTRIBUTE

-#define __VECTOR_TABLE_ATTRIBUTE  __attribute((used, section("RESET")))

-#endif

-

-/* ###########################  Core Function Access  ########################### */

-/** \ingroup  CMSIS_Core_FunctionInterface

-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions

-  @{

- */

-

-/**

-  \brief   Enable IRQ Interrupts

-  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.

-           Can only be executed in Privileged modes.

- */

-/* intrinsic void __enable_irq();     */

-

-

-/**

-  \brief   Disable IRQ Interrupts

-  \details Disables IRQ interrupts by setting the I-bit in the CPSR.

-           Can only be executed in Privileged modes.

- */

-/* intrinsic void __disable_irq();    */

-

-/**

-  \brief   Get Control Register

-  \details Returns the content of the Control Register.

-  \return               Control Register value

- */

-__STATIC_INLINE uint32_t __get_CONTROL(void)

-{

-  register uint32_t __regControl         __ASM("control");

-  return(__regControl);

-}

-

-

-/**

-  \brief   Set Control Register

-  \details Writes the given value to the Control Register.

-  \param [in]    control  Control Register value to set

- */

-__STATIC_INLINE void __set_CONTROL(uint32_t control)

-{

-  register uint32_t __regControl         __ASM("control");

-  __regControl = control;

-}

-

-

-/**

-  \brief   Get IPSR Register

-  \details Returns the content of the IPSR Register.

-  \return               IPSR Register value

- */

-__STATIC_INLINE uint32_t __get_IPSR(void)

-{

-  register uint32_t __regIPSR          __ASM("ipsr");

-  return(__regIPSR);

-}

-

-

-/**

-  \brief   Get APSR Register

-  \details Returns the content of the APSR Register.

-  \return               APSR Register value

- */

-__STATIC_INLINE uint32_t __get_APSR(void)

-{

-  register uint32_t __regAPSR          __ASM("apsr");

-  return(__regAPSR);

-}

-

-

-/**

-  \brief   Get xPSR Register

-  \details Returns the content of the xPSR Register.

-  \return               xPSR Register value

- */

-__STATIC_INLINE uint32_t __get_xPSR(void)

-{

-  register uint32_t __regXPSR          __ASM("xpsr");

-  return(__regXPSR);

-}

-

-

-/**

-  \brief   Get Process Stack Pointer

-  \details Returns the current value of the Process Stack Pointer (PSP).

-  \return               PSP Register value

- */

-__STATIC_INLINE uint32_t __get_PSP(void)

-{

-  register uint32_t __regProcessStackPointer  __ASM("psp");

-  return(__regProcessStackPointer);

-}

-

-

-/**

-  \brief   Set Process Stack Pointer

-  \details Assigns the given value to the Process Stack Pointer (PSP).

-  \param [in]    topOfProcStack  Process Stack Pointer value to set

- */

-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)

-{

-  register uint32_t __regProcessStackPointer  __ASM("psp");

-  __regProcessStackPointer = topOfProcStack;

-}

-

-

-/**

-  \brief   Get Main Stack Pointer

-  \details Returns the current value of the Main Stack Pointer (MSP).

-  \return               MSP Register value

- */

-__STATIC_INLINE uint32_t __get_MSP(void)

-{

-  register uint32_t __regMainStackPointer     __ASM("msp");

-  return(__regMainStackPointer);

-}

-

-

-/**

-  \brief   Set Main Stack Pointer

-  \details Assigns the given value to the Main Stack Pointer (MSP).

-  \param [in]    topOfMainStack  Main Stack Pointer value to set

- */

-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)

-{

-  register uint32_t __regMainStackPointer     __ASM("msp");

-  __regMainStackPointer = topOfMainStack;

-}

-

-

-/**

-  \brief   Get Priority Mask

-  \details Returns the current state of the priority mask bit from the Priority Mask Register.

-  \return               Priority Mask value

- */

-__STATIC_INLINE uint32_t __get_PRIMASK(void)

-{

-  register uint32_t __regPriMask         __ASM("primask");

-  return(__regPriMask);

-}

-

-

-/**

-  \brief   Set Priority Mask

-  \details Assigns the given value to the Priority Mask Register.

-  \param [in]    priMask  Priority Mask

- */

-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)

-{

-  register uint32_t __regPriMask         __ASM("primask");

-  __regPriMask = (priMask);

-}

-

-

-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \

-     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )

-

-/**

-  \brief   Enable FIQ

-  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.

-           Can only be executed in Privileged modes.

- */

-#define __enable_fault_irq                __enable_fiq

-

-

-/**

-  \brief   Disable FIQ

-  \details Disables FIQ interrupts by setting the F-bit in the CPSR.

-           Can only be executed in Privileged modes.

- */

-#define __disable_fault_irq               __disable_fiq

-

-

-/**

-  \brief   Get Base Priority

-  \details Returns the current value of the Base Priority register.

-  \return               Base Priority register value

- */

-__STATIC_INLINE uint32_t  __get_BASEPRI(void)

-{

-  register uint32_t __regBasePri         __ASM("basepri");

-  return(__regBasePri);

-}

-

-

-/**

-  \brief   Set Base Priority

-  \details Assigns the given value to the Base Priority register.

-  \param [in]    basePri  Base Priority value to set

- */

-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)

-{

-  register uint32_t __regBasePri         __ASM("basepri");

-  __regBasePri = (basePri & 0xFFU);

-}

-

-

-/**

-  \brief   Set Base Priority with condition

-  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,

-           or the new value increases the BASEPRI priority level.

-  \param [in]    basePri  Base Priority value to set

- */

-__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)

-{

-  register uint32_t __regBasePriMax      __ASM("basepri_max");

-  __regBasePriMax = (basePri & 0xFFU);

-}

-

-

-/**

-  \brief   Get Fault Mask

-  \details Returns the current value of the Fault Mask register.

-  \return               Fault Mask register value

- */

-__STATIC_INLINE uint32_t __get_FAULTMASK(void)

-{

-  register uint32_t __regFaultMask       __ASM("faultmask");

-  return(__regFaultMask);

-}

-

-

-/**

-  \brief   Set Fault Mask

-  \details Assigns the given value to the Fault Mask register.

-  \param [in]    faultMask  Fault Mask value to set

- */

-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)

-{

-  register uint32_t __regFaultMask       __ASM("faultmask");

-  __regFaultMask = (faultMask & (uint32_t)1U);

-}

-

-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \

-           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */

-

-

-/**

-  \brief   Get FPSCR

-  \details Returns the current value of the Floating Point Status/Control register.

-  \return               Floating Point Status/Control register value

- */

-__STATIC_INLINE uint32_t __get_FPSCR(void)

-{

-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \

-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )

-  register uint32_t __regfpscr         __ASM("fpscr");

-  return(__regfpscr);

-#else

-   return(0U);

-#endif

-}

-

-

-/**

-  \brief   Set FPSCR

-  \details Assigns the given value to the Floating Point Status/Control register.

-  \param [in]    fpscr  Floating Point Status/Control value to set

- */

-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)

-{

-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \

-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )

-  register uint32_t __regfpscr         __ASM("fpscr");

-  __regfpscr = (fpscr);

-#else

-  (void)fpscr;

-#endif

-}

-

-

-/*@} end of CMSIS_Core_RegAccFunctions */

-

-

-/* ##########################  Core Instruction Access  ######################### */

-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface

-  Access to dedicated instructions

-  @{

-*/

-

-/**

-  \brief   No Operation

-  \details No Operation does nothing. This instruction can be used for code alignment purposes.

- */

-#define __NOP                             __nop

-

-

-/**

-  \brief   Wait For Interrupt

-  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.

- */

-#define __WFI                             __wfi

-

-

-/**

-  \brief   Wait For Event

-  \details Wait For Event is a hint instruction that permits the processor to enter

-           a low-power state until one of a number of events occurs.

- */

-#define __WFE                             __wfe

-

-

-/**

-  \brief   Send Event

-  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.

- */

-#define __SEV                             __sev

-

-

-/**

-  \brief   Instruction Synchronization Barrier

-  \details Instruction Synchronization Barrier flushes the pipeline in the processor,

-           so that all instructions following the ISB are fetched from cache or memory,

-           after the instruction has been completed.

- */

-#define __ISB() do {\

-                   __schedule_barrier();\

-                   __isb(0xF);\

-                   __schedule_barrier();\

-                } while (0U)

-

-/**

-  \brief   Data Synchronization Barrier

-  \details Acts as a special kind of Data Memory Barrier.

-           It completes when all explicit memory accesses before this instruction complete.

- */

-#define __DSB() do {\

-                   __schedule_barrier();\

-                   __dsb(0xF);\

-                   __schedule_barrier();\

-                } while (0U)

-

-/**

-  \brief   Data Memory Barrier

-  \details Ensures the apparent order of the explicit memory operations before

-           and after the instruction, without ensuring their completion.

- */

-#define __DMB() do {\

-                   __schedule_barrier();\

-                   __dmb(0xF);\

-                   __schedule_barrier();\

-                } while (0U)

-

-                  

-/**

-  \brief   Reverse byte order (32 bit)

-  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.

-  \param [in]    value  Value to reverse

-  \return               Reversed value

- */

-#define __REV                             __rev

-

-

-/**

-  \brief   Reverse byte order (16 bit)

-  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.

-  \param [in]    value  Value to reverse

-  \return               Reversed value

- */

-#ifndef __NO_EMBEDDED_ASM

-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)

-{

-  rev16 r0, r0

-  bx lr

-}

-#endif

-

-

-/**

-  \brief   Reverse byte order (16 bit)

-  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.

-  \param [in]    value  Value to reverse

-  \return               Reversed value

- */

-#ifndef __NO_EMBEDDED_ASM

-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)

-{

-  revsh r0, r0

-  bx lr

-}

-#endif

-

-

-/**

-  \brief   Rotate Right in unsigned value (32 bit)

-  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.

-  \param [in]    op1  Value to rotate

-  \param [in]    op2  Number of Bits to rotate

-  \return               Rotated value

- */

-#define __ROR                             __ror

-

-

-/**

-  \brief   Breakpoint

-  \details Causes the processor to enter Debug state.

-           Debug tools can use this to investigate system state when the instruction at a particular address is reached.

-  \param [in]    value  is ignored by the processor.

-                 If required, a debugger can use it to store additional information about the breakpoint.

- */

-#define __BKPT(value)                       __breakpoint(value)

-

-

-/**

-  \brief   Reverse bit order of value

-  \details Reverses the bit order of the given value.

-  \param [in]    value  Value to reverse

-  \return               Reversed value

- */

-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \

-     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )

-  #define __RBIT                          __rbit

-#else

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)

-{

-  uint32_t result;

-  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */

-

-  result = value;                      /* r will be reversed bits of v; first get LSB of v */

-  for (value >>= 1U; value != 0U; value >>= 1U)

-  {

-    result <<= 1U;

-    result |= value & 1U;

-    s--;

-  }

-  result <<= s;                        /* shift when v's highest bits are zero */

-  return result;

-}

-#endif

-

-

-/**

-  \brief   Count leading zeros

-  \details Counts the number of leading zeros of a data value.

-  \param [in]  value  Value to count the leading zeros

-  \return             number of leading zeros in value

- */

-#define __CLZ                             __clz

-

-

-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \

-     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )

-

-/**

-  \brief   LDR Exclusive (8 bit)

-  \details Executes a exclusive LDR instruction for 8 bit value.

-  \param [in]    ptr  Pointer to data

-  \return             value of type uint8_t at (*ptr)

- */

-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)

-  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))

-#else

-  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")

-#endif

-

-

-/**

-  \brief   LDR Exclusive (16 bit)

-  \details Executes a exclusive LDR instruction for 16 bit values.

-  \param [in]    ptr  Pointer to data

-  \return        value of type uint16_t at (*ptr)

- */

-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)

-  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))

-#else

-  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")

-#endif

-

-

-/**

-  \brief   LDR Exclusive (32 bit)

-  \details Executes a exclusive LDR instruction for 32 bit values.

-  \param [in]    ptr  Pointer to data

-  \return        value of type uint32_t at (*ptr)

- */

-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)

-  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))

-#else

-  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")

-#endif

-

-

-/**

-  \brief   STR Exclusive (8 bit)

-  \details Executes a exclusive STR instruction for 8 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

-  \return          0  Function succeeded

-  \return          1  Function failed

- */

-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)

-  #define __STREXB(value, ptr)                                                 __strex(value, ptr)

-#else

-  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")

-#endif

-

-

-/**

-  \brief   STR Exclusive (16 bit)

-  \details Executes a exclusive STR instruction for 16 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

-  \return          0  Function succeeded

-  \return          1  Function failed

- */

-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)

-  #define __STREXH(value, ptr)                                                 __strex(value, ptr)

-#else

-  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")

-#endif

-

-

-/**

-  \brief   STR Exclusive (32 bit)

-  \details Executes a exclusive STR instruction for 32 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

-  \return          0  Function succeeded

-  \return          1  Function failed

- */

-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)

-  #define __STREXW(value, ptr)                                                 __strex(value, ptr)

-#else

-  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")

-#endif

-

-

-/**

-  \brief   Remove the exclusive lock

-  \details Removes the exclusive lock which is created by LDREX.

- */

-#define __CLREX                           __clrex

-

-

-/**

-  \brief   Signed Saturate

-  \details Saturates a signed value.

-  \param [in]  value  Value to be saturated

-  \param [in]    sat  Bit position to saturate to (1..32)

-  \return             Saturated value

- */

-#define __SSAT                            __ssat

-

-

-/**

-  \brief   Unsigned Saturate

-  \details Saturates an unsigned value.

-  \param [in]  value  Value to be saturated

-  \param [in]    sat  Bit position to saturate to (0..31)

-  \return             Saturated value

- */

-#define __USAT                            __usat

-

-

-/**

-  \brief   Rotate Right with Extend (32 bit)

-  \details Moves each bit of a bitstring right by one bit.

-           The carry input is shifted in at the left end of the bitstring.

-  \param [in]    value  Value to rotate

-  \return               Rotated value

- */

-#ifndef __NO_EMBEDDED_ASM

-__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)

-{

-  rrx r0, r0

-  bx lr

-}

-#endif

-

-

-/**

-  \brief   LDRT Unprivileged (8 bit)

-  \details Executes a Unprivileged LDRT instruction for 8 bit value.

-  \param [in]    ptr  Pointer to data

-  \return             value of type uint8_t at (*ptr)

- */

-#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))

-

-

-/**

-  \brief   LDRT Unprivileged (16 bit)

-  \details Executes a Unprivileged LDRT instruction for 16 bit values.

-  \param [in]    ptr  Pointer to data

-  \return        value of type uint16_t at (*ptr)

- */

-#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))

-

-

-/**

-  \brief   LDRT Unprivileged (32 bit)

-  \details Executes a Unprivileged LDRT instruction for 32 bit values.

-  \param [in]    ptr  Pointer to data

-  \return        value of type uint32_t at (*ptr)

- */

-#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))

-

-

-/**

-  \brief   STRT Unprivileged (8 bit)

-  \details Executes a Unprivileged STRT instruction for 8 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

- */

-#define __STRBT(value, ptr)               __strt(value, ptr)

-

-

-/**

-  \brief   STRT Unprivileged (16 bit)

-  \details Executes a Unprivileged STRT instruction for 16 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

- */

-#define __STRHT(value, ptr)               __strt(value, ptr)

-

-

-/**

-  \brief   STRT Unprivileged (32 bit)

-  \details Executes a Unprivileged STRT instruction for 32 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

- */

-#define __STRT(value, ptr)                __strt(value, ptr)

-

-#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \

-           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */

-

-/**

-  \brief   Signed Saturate

-  \details Saturates a signed value.

-  \param [in]  value  Value to be saturated

-  \param [in]    sat  Bit position to saturate to (1..32)

-  \return             Saturated value

- */

-__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)

-{

-  if ((sat >= 1U) && (sat <= 32U))

-  {

-    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);

-    const int32_t min = -1 - max ;

-    if (val > max)

-    {

-      return max;

-    }

-    else if (val < min)

-    {

-      return min;

-    }

-  }

-  return val;

-}

-

-/**

-  \brief   Unsigned Saturate

-  \details Saturates an unsigned value.

-  \param [in]  value  Value to be saturated

-  \param [in]    sat  Bit position to saturate to (0..31)

-  \return             Saturated value

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)

-{

-  if (sat <= 31U)

-  {

-    const uint32_t max = ((1U << sat) - 1U);

-    if (val > (int32_t)max)

-    {

-      return max;

-    }

-    else if (val < 0)

-    {

-      return 0U;

-    }

-  }

-  return (uint32_t)val;

-}

-

-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \

-           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */

-

-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */

-

-

-/* ###################  Compiler specific Intrinsics  ########################### */

-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics

-  Access to dedicated SIMD instructions

-  @{

-*/

-

-#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )

-

-#define __SADD8                           __sadd8

-#define __QADD8                           __qadd8

-#define __SHADD8                          __shadd8

-#define __UADD8                           __uadd8

-#define __UQADD8                          __uqadd8

-#define __UHADD8                          __uhadd8

-#define __SSUB8                           __ssub8

-#define __QSUB8                           __qsub8

-#define __SHSUB8                          __shsub8

-#define __USUB8                           __usub8

-#define __UQSUB8                          __uqsub8

-#define __UHSUB8                          __uhsub8

-#define __SADD16                          __sadd16

-#define __QADD16                          __qadd16

-#define __SHADD16                         __shadd16

-#define __UADD16                          __uadd16

-#define __UQADD16                         __uqadd16

-#define __UHADD16                         __uhadd16

-#define __SSUB16                          __ssub16

-#define __QSUB16                          __qsub16

-#define __SHSUB16                         __shsub16

-#define __USUB16                          __usub16

-#define __UQSUB16                         __uqsub16

-#define __UHSUB16                         __uhsub16

-#define __SASX                            __sasx

-#define __QASX                            __qasx

-#define __SHASX                           __shasx

-#define __UASX                            __uasx

-#define __UQASX                           __uqasx

-#define __UHASX                           __uhasx

-#define __SSAX                            __ssax

-#define __QSAX                            __qsax

-#define __SHSAX                           __shsax

-#define __USAX                            __usax

-#define __UQSAX                           __uqsax

-#define __UHSAX                           __uhsax

-#define __USAD8                           __usad8

-#define __USADA8                          __usada8

-#define __SSAT16                          __ssat16

-#define __USAT16                          __usat16

-#define __UXTB16                          __uxtb16

-#define __UXTAB16                         __uxtab16

-#define __SXTB16                          __sxtb16

-#define __SXTAB16                         __sxtab16

-#define __SMUAD                           __smuad

-#define __SMUADX                          __smuadx

-#define __SMLAD                           __smlad

-#define __SMLADX                          __smladx

-#define __SMLALD                          __smlald

-#define __SMLALDX                         __smlaldx

-#define __SMUSD                           __smusd

-#define __SMUSDX                          __smusdx

-#define __SMLSD                           __smlsd

-#define __SMLSDX                          __smlsdx

-#define __SMLSLD                          __smlsld

-#define __SMLSLDX                         __smlsldx

-#define __SEL                             __sel

-#define __QADD                            __qadd

-#define __QSUB                            __qsub

-

-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \

-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )

-

-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \

-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )

-

-#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \

-                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))

-

-#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */

-/*@} end of group CMSIS_SIMD_intrinsics */

-

-

-#endif /* __CMSIS_ARMCC_H */

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_armclang.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_armclang.h
deleted file mode 100644
index 478f75bb5..000000000
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_armclang.h
+++ /dev/null
@@ -1,1444 +0,0 @@
-/**************************************************************************//**

- * @file     cmsis_armclang.h

- * @brief    CMSIS compiler armclang (Arm Compiler 6) header file

- * @version  V5.2.0

- * @date     08. May 2019

- ******************************************************************************/

-/*

- * Copyright (c) 2009-2019 Arm Limited. All rights reserved.

- *

- * SPDX-License-Identifier: Apache-2.0

- *

- * Licensed under the Apache License, Version 2.0 (the License); you may

- * not use this file except in compliance with the License.

- * You may obtain a copy of the License at

- *

- * www.apache.org/licenses/LICENSE-2.0

- *

- * Unless required by applicable law or agreed to in writing, software

- * distributed under the License is distributed on an AS IS BASIS, WITHOUT

- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

- * See the License for the specific language governing permissions and

- * limitations under the License.

- */

-

-/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */

-

-#ifndef __CMSIS_ARMCLANG_H

-#define __CMSIS_ARMCLANG_H

-

-#pragma clang system_header   /* treat file as system include file */

-

-#ifndef __ARM_COMPAT_H

-#include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */

-#endif

-

-/* CMSIS compiler specific defines */

-#ifndef   __ASM

-  #define __ASM                                  __asm

-#endif

-#ifndef   __INLINE

-  #define __INLINE                               __inline

-#endif

-#ifndef   __STATIC_INLINE

-  #define __STATIC_INLINE                        static __inline

-#endif

-#ifndef   __STATIC_FORCEINLINE

-  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline

-#endif

-#ifndef   __NO_RETURN

-  #define __NO_RETURN                            __attribute__((__noreturn__))

-#endif

-#ifndef   __USED

-  #define __USED                                 __attribute__((used))

-#endif

-#ifndef   __WEAK

-  #define __WEAK                                 __attribute__((weak))

-#endif

-#ifndef   __PACKED

-  #define __PACKED                               __attribute__((packed, aligned(1)))

-#endif

-#ifndef   __PACKED_STRUCT

-  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))

-#endif

-#ifndef   __PACKED_UNION

-  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))

-#endif

-#ifndef   __UNALIGNED_UINT32        /* deprecated */

-  #pragma clang diagnostic push

-  #pragma clang diagnostic ignored "-Wpacked"

-/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */

-  struct __attribute__((packed)) T_UINT32 { uint32_t v; };

-  #pragma clang diagnostic pop

-  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)

-#endif

-#ifndef   __UNALIGNED_UINT16_WRITE

-  #pragma clang diagnostic push

-  #pragma clang diagnostic ignored "-Wpacked"

-/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */

-  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };

-  #pragma clang diagnostic pop

-  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))

-#endif

-#ifndef   __UNALIGNED_UINT16_READ

-  #pragma clang diagnostic push

-  #pragma clang diagnostic ignored "-Wpacked"

-/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */

-  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };

-  #pragma clang diagnostic pop

-  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)

-#endif

-#ifndef   __UNALIGNED_UINT32_WRITE

-  #pragma clang diagnostic push

-  #pragma clang diagnostic ignored "-Wpacked"

-/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */

-  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };

-  #pragma clang diagnostic pop

-  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))

-#endif

-#ifndef   __UNALIGNED_UINT32_READ

-  #pragma clang diagnostic push

-  #pragma clang diagnostic ignored "-Wpacked"

-/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */

-  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };

-  #pragma clang diagnostic pop

-  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)

-#endif

-#ifndef   __ALIGNED

-  #define __ALIGNED(x)                           __attribute__((aligned(x)))

-#endif

-#ifndef   __RESTRICT

-  #define __RESTRICT                             __restrict

-#endif

-#ifndef   __COMPILER_BARRIER

-  #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")

-#endif

-

-/* #########################  Startup and Lowlevel Init  ######################## */

-

-#ifndef __PROGRAM_START

-#define __PROGRAM_START           __main

-#endif

-

-#ifndef __INITIAL_SP

-#define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit

-#endif

-

-#ifndef __STACK_LIMIT

-#define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base

-#endif

-

-#ifndef __VECTOR_TABLE

-#define __VECTOR_TABLE            __Vectors

-#endif

-

-#ifndef __VECTOR_TABLE_ATTRIBUTE

-#define __VECTOR_TABLE_ATTRIBUTE  __attribute((used, section("RESET")))

-#endif

-

-/* ###########################  Core Function Access  ########################### */

-/** \ingroup  CMSIS_Core_FunctionInterface

-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions

-  @{

- */

-

-/**

-  \brief   Enable IRQ Interrupts

-  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.

-           Can only be executed in Privileged modes.

- */

-/* intrinsic void __enable_irq();  see arm_compat.h */

-

-

-/**

-  \brief   Disable IRQ Interrupts

-  \details Disables IRQ interrupts by setting the I-bit in the CPSR.

-           Can only be executed in Privileged modes.

- */

-/* intrinsic void __disable_irq();  see arm_compat.h */

-

-

-/**

-  \brief   Get Control Register

-  \details Returns the content of the Control Register.

-  \return               Control Register value

- */

-__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, control" : "=r" (result) );

-  return(result);

-}

-

-

-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

-/**

-  \brief   Get Control Register (non-secure)

-  \details Returns the content of the non-secure Control Register when in secure mode.

-  \return               non-secure Control Register value

- */

-__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );

-  return(result);

-}

-#endif

-

-

-/**

-  \brief   Set Control Register

-  \details Writes the given value to the Control Register.

-  \param [in]    control  Control Register value to set

- */

-__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)

-{

-  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");

-}

-

-

-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

-/**

-  \brief   Set Control Register (non-secure)

-  \details Writes the given value to the non-secure Control Register when in secure state.

-  \param [in]    control  Control Register value to set

- */

-__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)

-{

-  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");

-}

-#endif

-

-

-/**

-  \brief   Get IPSR Register

-  \details Returns the content of the IPSR Register.

-  \return               IPSR Register value

- */

-__STATIC_FORCEINLINE uint32_t __get_IPSR(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );

-  return(result);

-}

-

-

-/**

-  \brief   Get APSR Register

-  \details Returns the content of the APSR Register.

-  \return               APSR Register value

- */

-__STATIC_FORCEINLINE uint32_t __get_APSR(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );

-  return(result);

-}

-

-

-/**

-  \brief   Get xPSR Register

-  \details Returns the content of the xPSR Register.

-  \return               xPSR Register value

- */

-__STATIC_FORCEINLINE uint32_t __get_xPSR(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );

-  return(result);

-}

-

-

-/**

-  \brief   Get Process Stack Pointer

-  \details Returns the current value of the Process Stack Pointer (PSP).

-  \return               PSP Register value

- */

-__STATIC_FORCEINLINE uint32_t __get_PSP(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, psp"  : "=r" (result) );

-  return(result);

-}

-

-

-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

-/**

-  \brief   Get Process Stack Pointer (non-secure)

-  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.

-  \return               PSP Register value

- */

-__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );

-  return(result);

-}

-#endif

-

-

-/**

-  \brief   Set Process Stack Pointer

-  \details Assigns the given value to the Process Stack Pointer (PSP).

-  \param [in]    topOfProcStack  Process Stack Pointer value to set

- */

-__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)

-{

-  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );

-}

-

-

-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

-/**

-  \brief   Set Process Stack Pointer (non-secure)

-  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.

-  \param [in]    topOfProcStack  Process Stack Pointer value to set

- */

-__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)

-{

-  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );

-}

-#endif

-

-

-/**

-  \brief   Get Main Stack Pointer

-  \details Returns the current value of the Main Stack Pointer (MSP).

-  \return               MSP Register value

- */

-__STATIC_FORCEINLINE uint32_t __get_MSP(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, msp" : "=r" (result) );

-  return(result);

-}

-

-

-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

-/**

-  \brief   Get Main Stack Pointer (non-secure)

-  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.

-  \return               MSP Register value

- */

-__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );

-  return(result);

-}

-#endif

-

-

-/**

-  \brief   Set Main Stack Pointer

-  \details Assigns the given value to the Main Stack Pointer (MSP).

-  \param [in]    topOfMainStack  Main Stack Pointer value to set

- */

-__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)

-{

-  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );

-}

-

-

-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

-/**

-  \brief   Set Main Stack Pointer (non-secure)

-  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.

-  \param [in]    topOfMainStack  Main Stack Pointer value to set

- */

-__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)

-{

-  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );

-}

-#endif

-

-

-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

-/**

-  \brief   Get Stack Pointer (non-secure)

-  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.

-  \return               SP Register value

- */

-__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );

-  return(result);

-}

-

-

-/**

-  \brief   Set Stack Pointer (non-secure)

-  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.

-  \param [in]    topOfStack  Stack Pointer value to set

- */

-__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)

-{

-  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );

-}

-#endif

-

-

-/**

-  \brief   Get Priority Mask

-  \details Returns the current state of the priority mask bit from the Priority Mask Register.

-  \return               Priority Mask value

- */

-__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, primask" : "=r" (result) );

-  return(result);

-}

-

-

-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

-/**

-  \brief   Get Priority Mask (non-secure)

-  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.

-  \return               Priority Mask value

- */

-__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );

-  return(result);

-}

-#endif

-

-

-/**

-  \brief   Set Priority Mask

-  \details Assigns the given value to the Priority Mask Register.

-  \param [in]    priMask  Priority Mask

- */

-__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)

-{

-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");

-}

-

-

-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

-/**

-  \brief   Set Priority Mask (non-secure)

-  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.

-  \param [in]    priMask  Priority Mask

- */

-__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)

-{

-  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");

-}

-#endif

-

-

-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \

-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \

-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )

-/**

-  \brief   Enable FIQ

-  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.

-           Can only be executed in Privileged modes.

- */

-#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */

-

-

-/**

-  \brief   Disable FIQ

-  \details Disables FIQ interrupts by setting the F-bit in the CPSR.

-           Can only be executed in Privileged modes.

- */

-#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */

-

-

-/**

-  \brief   Get Base Priority

-  \details Returns the current value of the Base Priority register.

-  \return               Base Priority register value

- */

-__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, basepri" : "=r" (result) );

-  return(result);

-}

-

-

-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

-/**

-  \brief   Get Base Priority (non-secure)

-  \details Returns the current value of the non-secure Base Priority register when in secure state.

-  \return               Base Priority register value

- */

-__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );

-  return(result);

-}

-#endif

-

-

-/**

-  \brief   Set Base Priority

-  \details Assigns the given value to the Base Priority register.

-  \param [in]    basePri  Base Priority value to set

- */

-__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)

-{

-  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");

-}

-

-

-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

-/**

-  \brief   Set Base Priority (non-secure)

-  \details Assigns the given value to the non-secure Base Priority register when in secure state.

-  \param [in]    basePri  Base Priority value to set

- */

-__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)

-{

-  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");

-}

-#endif

-

-

-/**

-  \brief   Set Base Priority with condition

-  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,

-           or the new value increases the BASEPRI priority level.

-  \param [in]    basePri  Base Priority value to set

- */

-__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)

-{

-  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");

-}

-

-

-/**

-  \brief   Get Fault Mask

-  \details Returns the current value of the Fault Mask register.

-  \return               Fault Mask register value

- */

-__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );

-  return(result);

-}

-

-

-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

-/**

-  \brief   Get Fault Mask (non-secure)

-  \details Returns the current value of the non-secure Fault Mask register when in secure state.

-  \return               Fault Mask register value

- */

-__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );

-  return(result);

-}

-#endif

-

-

-/**

-  \brief   Set Fault Mask

-  \details Assigns the given value to the Fault Mask register.

-  \param [in]    faultMask  Fault Mask value to set

- */

-__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)

-{

-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");

-}

-

-

-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

-/**

-  \brief   Set Fault Mask (non-secure)

-  \details Assigns the given value to the non-secure Fault Mask register when in secure state.

-  \param [in]    faultMask  Fault Mask value to set

- */

-__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)

-{

-  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");

-}

-#endif

-

-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \

-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \

-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */

-

-

-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \

-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )

-

-/**

-  \brief   Get Process Stack Pointer Limit

-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure

-  Stack Pointer Limit register hence zero is returned always in non-secure

-  mode.

-  

-  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).

-  \return               PSPLIM Register value

- */

-__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)

-{

-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \

-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))

-    // without main extensions, the non-secure PSPLIM is RAZ/WI

-  return 0U;

-#else

-  uint32_t result;

-  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );

-  return result;

-#endif

-}

-

-#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))

-/**

-  \brief   Get Process Stack Pointer Limit (non-secure)

-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure

-  Stack Pointer Limit register hence zero is returned always in non-secure

-  mode.

-

-  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.

-  \return               PSPLIM Register value

- */

-__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)

-{

-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))

-  // without main extensions, the non-secure PSPLIM is RAZ/WI

-  return 0U;

-#else

-  uint32_t result;

-  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );

-  return result;

-#endif

-}

-#endif

-

-

-/**

-  \brief   Set Process Stack Pointer Limit

-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure

-  Stack Pointer Limit register hence the write is silently ignored in non-secure

-  mode.

-  

-  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).

-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set

- */

-__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)

-{

-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \

-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))

-  // without main extensions, the non-secure PSPLIM is RAZ/WI

-  (void)ProcStackPtrLimit;

-#else

-  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));

-#endif

-}

-

-

-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))

-/**

-  \brief   Set Process Stack Pointer (non-secure)

-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure

-  Stack Pointer Limit register hence the write is silently ignored in non-secure

-  mode.

-

-  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.

-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set

- */

-__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)

-{

-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))

-  // without main extensions, the non-secure PSPLIM is RAZ/WI

-  (void)ProcStackPtrLimit;

-#else

-  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));

-#endif

-}

-#endif

-

-

-/**

-  \brief   Get Main Stack Pointer Limit

-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure

-  Stack Pointer Limit register hence zero is returned always.

-

-  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).

-  \return               MSPLIM Register value

- */

-__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)

-{

-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \

-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))

-  // without main extensions, the non-secure MSPLIM is RAZ/WI

-  return 0U;

-#else

-  uint32_t result;

-  __ASM volatile ("MRS %0, msplim" : "=r" (result) );

-  return result;

-#endif

-}

-

-

-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))

-/**

-  \brief   Get Main Stack Pointer Limit (non-secure)

-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure

-  Stack Pointer Limit register hence zero is returned always.

-

-  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.

-  \return               MSPLIM Register value

- */

-__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)

-{

-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))

-  // without main extensions, the non-secure MSPLIM is RAZ/WI

-  return 0U;

-#else

-  uint32_t result;

-  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );

-  return result;

-#endif

-}

-#endif

-

-

-/**

-  \brief   Set Main Stack Pointer Limit

-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure

-  Stack Pointer Limit register hence the write is silently ignored.

-

-  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).

-  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set

- */

-__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)

-{

-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \

-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))

-  // without main extensions, the non-secure MSPLIM is RAZ/WI

-  (void)MainStackPtrLimit;

-#else

-  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));

-#endif

-}

-

-

-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))

-/**

-  \brief   Set Main Stack Pointer Limit (non-secure)

-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure

-  Stack Pointer Limit register hence the write is silently ignored.

-

-  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.

-  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set

- */

-__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)

-{

-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))

-  // without main extensions, the non-secure MSPLIM is RAZ/WI

-  (void)MainStackPtrLimit;

-#else

-  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));

-#endif

-}

-#endif

-

-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \

-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */

-

-/**

-  \brief   Get FPSCR

-  \details Returns the current value of the Floating Point Status/Control register.

-  \return               Floating Point Status/Control register value

- */

-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \

-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )

-#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr

-#else

-#define __get_FPSCR()      ((uint32_t)0U)

-#endif

-

-/**

-  \brief   Set FPSCR

-  \details Assigns the given value to the Floating Point Status/Control register.

-  \param [in]    fpscr  Floating Point Status/Control value to set

- */

-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \

-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )

-#define __set_FPSCR      __builtin_arm_set_fpscr

-#else

-#define __set_FPSCR(x)      ((void)(x))

-#endif

-

-

-/*@} end of CMSIS_Core_RegAccFunctions */

-

-

-/* ##########################  Core Instruction Access  ######################### */

-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface

-  Access to dedicated instructions

-  @{

-*/

-

-/* Define macros for porting to both thumb1 and thumb2.

- * For thumb1, use low register (r0-r7), specified by constraint "l"

- * Otherwise, use general registers, specified by constraint "r" */

-#if defined (__thumb__) && !defined (__thumb2__)

-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)

-#define __CMSIS_GCC_RW_REG(r) "+l" (r)

-#define __CMSIS_GCC_USE_REG(r) "l" (r)

-#else

-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)

-#define __CMSIS_GCC_RW_REG(r) "+r" (r)

-#define __CMSIS_GCC_USE_REG(r) "r" (r)

-#endif

-

-/**

-  \brief   No Operation

-  \details No Operation does nothing. This instruction can be used for code alignment purposes.

- */

-#define __NOP          __builtin_arm_nop

-

-/**

-  \brief   Wait For Interrupt

-  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.

- */

-#define __WFI          __builtin_arm_wfi

-

-

-/**

-  \brief   Wait For Event

-  \details Wait For Event is a hint instruction that permits the processor to enter

-           a low-power state until one of a number of events occurs.

- */

-#define __WFE          __builtin_arm_wfe

-

-

-/**

-  \brief   Send Event

-  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.

- */

-#define __SEV          __builtin_arm_sev

-

-

-/**

-  \brief   Instruction Synchronization Barrier

-  \details Instruction Synchronization Barrier flushes the pipeline in the processor,

-           so that all instructions following the ISB are fetched from cache or memory,

-           after the instruction has been completed.

- */

-#define __ISB()        __builtin_arm_isb(0xF)

-

-/**

-  \brief   Data Synchronization Barrier

-  \details Acts as a special kind of Data Memory Barrier.

-           It completes when all explicit memory accesses before this instruction complete.

- */

-#define __DSB()        __builtin_arm_dsb(0xF)

-

-

-/**

-  \brief   Data Memory Barrier

-  \details Ensures the apparent order of the explicit memory operations before

-           and after the instruction, without ensuring their completion.

- */

-#define __DMB()        __builtin_arm_dmb(0xF)

-

-

-/**

-  \brief   Reverse byte order (32 bit)

-  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.

-  \param [in]    value  Value to reverse

-  \return               Reversed value

- */

-#define __REV(value)   __builtin_bswap32(value)

-

-

-/**

-  \brief   Reverse byte order (16 bit)

-  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.

-  \param [in]    value  Value to reverse

-  \return               Reversed value

- */

-#define __REV16(value) __ROR(__REV(value), 16)

-

-

-/**

-  \brief   Reverse byte order (16 bit)

-  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.

-  \param [in]    value  Value to reverse

-  \return               Reversed value

- */

-#define __REVSH(value) (int16_t)__builtin_bswap16(value)

-

-

-/**

-  \brief   Rotate Right in unsigned value (32 bit)

-  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.

-  \param [in]    op1  Value to rotate

-  \param [in]    op2  Number of Bits to rotate

-  \return               Rotated value

- */

-__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)

-{

-  op2 %= 32U;

-  if (op2 == 0U)

-  {

-    return op1;

-  }

-  return (op1 >> op2) | (op1 << (32U - op2));

-}

-

-

-/**

-  \brief   Breakpoint

-  \details Causes the processor to enter Debug state.

-           Debug tools can use this to investigate system state when the instruction at a particular address is reached.

-  \param [in]    value  is ignored by the processor.

-                 If required, a debugger can use it to store additional information about the breakpoint.

- */

-#define __BKPT(value)     __ASM volatile ("bkpt "#value)

-

-

-/**

-  \brief   Reverse bit order of value

-  \details Reverses the bit order of the given value.

-  \param [in]    value  Value to reverse

-  \return               Reversed value

- */

-#define __RBIT            __builtin_arm_rbit

-

-/**

-  \brief   Count leading zeros

-  \details Counts the number of leading zeros of a data value.

-  \param [in]  value  Value to count the leading zeros

-  \return             number of leading zeros in value

- */

-__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)

-{

-  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally

-     __builtin_clz(0) is undefined behaviour, so handle this case specially.

-     This guarantees ARM-compatible results if happening to compile on a non-ARM

-     target, and ensures the compiler doesn't decide to activate any

-     optimisations using the logic "value was passed to __builtin_clz, so it

-     is non-zero".

-     ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a

-     single CLZ instruction.

-   */

-  if (value == 0U)

-  {

-    return 32U;

-  }

-  return __builtin_clz(value);

-}

-

-

-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \

-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \

-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \

-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )

-/**

-  \brief   LDR Exclusive (8 bit)

-  \details Executes a exclusive LDR instruction for 8 bit value.

-  \param [in]    ptr  Pointer to data

-  \return             value of type uint8_t at (*ptr)

- */

-#define __LDREXB        (uint8_t)__builtin_arm_ldrex

-

-

-/**

-  \brief   LDR Exclusive (16 bit)

-  \details Executes a exclusive LDR instruction for 16 bit values.

-  \param [in]    ptr  Pointer to data

-  \return        value of type uint16_t at (*ptr)

- */

-#define __LDREXH        (uint16_t)__builtin_arm_ldrex

-

-

-/**

-  \brief   LDR Exclusive (32 bit)

-  \details Executes a exclusive LDR instruction for 32 bit values.

-  \param [in]    ptr  Pointer to data

-  \return        value of type uint32_t at (*ptr)

- */

-#define __LDREXW        (uint32_t)__builtin_arm_ldrex

-

-

-/**

-  \brief   STR Exclusive (8 bit)

-  \details Executes a exclusive STR instruction for 8 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

-  \return          0  Function succeeded

-  \return          1  Function failed

- */

-#define __STREXB        (uint32_t)__builtin_arm_strex

-

-

-/**

-  \brief   STR Exclusive (16 bit)

-  \details Executes a exclusive STR instruction for 16 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

-  \return          0  Function succeeded

-  \return          1  Function failed

- */

-#define __STREXH        (uint32_t)__builtin_arm_strex

-

-

-/**

-  \brief   STR Exclusive (32 bit)

-  \details Executes a exclusive STR instruction for 32 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

-  \return          0  Function succeeded

-  \return          1  Function failed

- */

-#define __STREXW        (uint32_t)__builtin_arm_strex

-

-

-/**

-  \brief   Remove the exclusive lock

-  \details Removes the exclusive lock which is created by LDREX.

- */

-#define __CLREX             __builtin_arm_clrex

-

-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \

-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \

-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \

-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */

-

-

-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \

-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \

-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )

-

-/**

-  \brief   Signed Saturate

-  \details Saturates a signed value.

-  \param [in]  value  Value to be saturated

-  \param [in]    sat  Bit position to saturate to (1..32)

-  \return             Saturated value

- */

-#define __SSAT             __builtin_arm_ssat

-

-

-/**

-  \brief   Unsigned Saturate

-  \details Saturates an unsigned value.

-  \param [in]  value  Value to be saturated

-  \param [in]    sat  Bit position to saturate to (0..31)

-  \return             Saturated value

- */

-#define __USAT             __builtin_arm_usat

-

-

-/**

-  \brief   Rotate Right with Extend (32 bit)

-  \details Moves each bit of a bitstring right by one bit.

-           The carry input is shifted in at the left end of the bitstring.

-  \param [in]    value  Value to rotate

-  \return               Rotated value

- */

-__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)

-{

-  uint32_t result;

-

-  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

-  return(result);

-}

-

-

-/**

-  \brief   LDRT Unprivileged (8 bit)

-  \details Executes a Unprivileged LDRT instruction for 8 bit value.

-  \param [in]    ptr  Pointer to data

-  \return             value of type uint8_t at (*ptr)

- */

-__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)

-{

-  uint32_t result;

-

-  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );

-  return ((uint8_t) result);    /* Add explicit type cast here */

-}

-

-

-/**

-  \brief   LDRT Unprivileged (16 bit)

-  \details Executes a Unprivileged LDRT instruction for 16 bit values.

-  \param [in]    ptr  Pointer to data

-  \return        value of type uint16_t at (*ptr)

- */

-__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)

-{

-  uint32_t result;

-

-  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );

-  return ((uint16_t) result);    /* Add explicit type cast here */

-}

-

-

-/**

-  \brief   LDRT Unprivileged (32 bit)

-  \details Executes a Unprivileged LDRT instruction for 32 bit values.

-  \param [in]    ptr  Pointer to data

-  \return        value of type uint32_t at (*ptr)

- */

-__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)

-{

-  uint32_t result;

-

-  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );

-  return(result);

-}

-

-

-/**

-  \brief   STRT Unprivileged (8 bit)

-  \details Executes a Unprivileged STRT instruction for 8 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

- */

-__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)

-{

-  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );

-}

-

-

-/**

-  \brief   STRT Unprivileged (16 bit)

-  \details Executes a Unprivileged STRT instruction for 16 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

- */

-__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)

-{

-  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );

-}

-

-

-/**

-  \brief   STRT Unprivileged (32 bit)

-  \details Executes a Unprivileged STRT instruction for 32 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

- */

-__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)

-{

-  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );

-}

-

-#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \

-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \

-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */

-

-/**

-  \brief   Signed Saturate

-  \details Saturates a signed value.

-  \param [in]  value  Value to be saturated

-  \param [in]    sat  Bit position to saturate to (1..32)

-  \return             Saturated value

- */

-__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)

-{

-  if ((sat >= 1U) && (sat <= 32U))

-  {

-    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);

-    const int32_t min = -1 - max ;

-    if (val > max)

-    {

-      return max;

-    }

-    else if (val < min)

-    {

-      return min;

-    }

-  }

-  return val;

-}

-

-/**

-  \brief   Unsigned Saturate

-  \details Saturates an unsigned value.

-  \param [in]  value  Value to be saturated

-  \param [in]    sat  Bit position to saturate to (0..31)

-  \return             Saturated value

- */

-__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)

-{

-  if (sat <= 31U)

-  {

-    const uint32_t max = ((1U << sat) - 1U);

-    if (val > (int32_t)max)

-    {

-      return max;

-    }

-    else if (val < 0)

-    {

-      return 0U;

-    }

-  }

-  return (uint32_t)val;

-}

-

-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \

-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \

-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */

-

-

-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \

-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )

-/**

-  \brief   Load-Acquire (8 bit)

-  \details Executes a LDAB instruction for 8 bit value.

-  \param [in]    ptr  Pointer to data

-  \return             value of type uint8_t at (*ptr)

- */

-__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)

-{

-  uint32_t result;

-

-  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );

-  return ((uint8_t) result);

-}

-

-

-/**

-  \brief   Load-Acquire (16 bit)

-  \details Executes a LDAH instruction for 16 bit values.

-  \param [in]    ptr  Pointer to data

-  \return        value of type uint16_t at (*ptr)

- */

-__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)

-{

-  uint32_t result;

-

-  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );

-  return ((uint16_t) result);

-}

-

-

-/**

-  \brief   Load-Acquire (32 bit)

-  \details Executes a LDA instruction for 32 bit values.

-  \param [in]    ptr  Pointer to data

-  \return        value of type uint32_t at (*ptr)

- */

-__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)

-{

-  uint32_t result;

-

-  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );

-  return(result);

-}

-

-

-/**

-  \brief   Store-Release (8 bit)

-  \details Executes a STLB instruction for 8 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

- */

-__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)

-{

-  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );

-}

-

-

-/**

-  \brief   Store-Release (16 bit)

-  \details Executes a STLH instruction for 16 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

- */

-__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)

-{

-  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );

-}

-

-

-/**

-  \brief   Store-Release (32 bit)

-  \details Executes a STL instruction for 32 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

- */

-__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)

-{

-  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );

-}

-

-

-/**

-  \brief   Load-Acquire Exclusive (8 bit)

-  \details Executes a LDAB exclusive instruction for 8 bit value.

-  \param [in]    ptr  Pointer to data

-  \return             value of type uint8_t at (*ptr)

- */

-#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex

-

-

-/**

-  \brief   Load-Acquire Exclusive (16 bit)

-  \details Executes a LDAH exclusive instruction for 16 bit values.

-  \param [in]    ptr  Pointer to data

-  \return        value of type uint16_t at (*ptr)

- */

-#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex

-

-

-/**

-  \brief   Load-Acquire Exclusive (32 bit)

-  \details Executes a LDA exclusive instruction for 32 bit values.

-  \param [in]    ptr  Pointer to data

-  \return        value of type uint32_t at (*ptr)

- */

-#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex

-

-

-/**

-  \brief   Store-Release Exclusive (8 bit)

-  \details Executes a STLB exclusive instruction for 8 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

-  \return          0  Function succeeded

-  \return          1  Function failed

- */

-#define     __STLEXB                 (uint32_t)__builtin_arm_stlex

-

-

-/**

-  \brief   Store-Release Exclusive (16 bit)

-  \details Executes a STLH exclusive instruction for 16 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

-  \return          0  Function succeeded

-  \return          1  Function failed

- */

-#define     __STLEXH                 (uint32_t)__builtin_arm_stlex

-

-

-/**

-  \brief   Store-Release Exclusive (32 bit)

-  \details Executes a STL exclusive instruction for 32 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

-  \return          0  Function succeeded

-  \return          1  Function failed

- */

-#define     __STLEX                  (uint32_t)__builtin_arm_stlex

-

-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \

-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */

-

-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */

-

-

-/* ###################  Compiler specific Intrinsics  ########################### */

-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics

-  Access to dedicated SIMD instructions

-  @{

-*/

-

-#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))

-

-#define     __SADD8                 __builtin_arm_sadd8

-#define     __QADD8                 __builtin_arm_qadd8

-#define     __SHADD8                __builtin_arm_shadd8

-#define     __UADD8                 __builtin_arm_uadd8

-#define     __UQADD8                __builtin_arm_uqadd8

-#define     __UHADD8                __builtin_arm_uhadd8

-#define     __SSUB8                 __builtin_arm_ssub8

-#define     __QSUB8                 __builtin_arm_qsub8

-#define     __SHSUB8                __builtin_arm_shsub8

-#define     __USUB8                 __builtin_arm_usub8

-#define     __UQSUB8                __builtin_arm_uqsub8

-#define     __UHSUB8                __builtin_arm_uhsub8

-#define     __SADD16                __builtin_arm_sadd16

-#define     __QADD16                __builtin_arm_qadd16

-#define     __SHADD16               __builtin_arm_shadd16

-#define     __UADD16                __builtin_arm_uadd16

-#define     __UQADD16               __builtin_arm_uqadd16

-#define     __UHADD16               __builtin_arm_uhadd16

-#define     __SSUB16                __builtin_arm_ssub16

-#define     __QSUB16                __builtin_arm_qsub16

-#define     __SHSUB16               __builtin_arm_shsub16

-#define     __USUB16                __builtin_arm_usub16

-#define     __UQSUB16               __builtin_arm_uqsub16

-#define     __UHSUB16               __builtin_arm_uhsub16

-#define     __SASX                  __builtin_arm_sasx

-#define     __QASX                  __builtin_arm_qasx

-#define     __SHASX                 __builtin_arm_shasx

-#define     __UASX                  __builtin_arm_uasx

-#define     __UQASX                 __builtin_arm_uqasx

-#define     __UHASX                 __builtin_arm_uhasx

-#define     __SSAX                  __builtin_arm_ssax

-#define     __QSAX                  __builtin_arm_qsax

-#define     __SHSAX                 __builtin_arm_shsax

-#define     __USAX                  __builtin_arm_usax

-#define     __UQSAX                 __builtin_arm_uqsax

-#define     __UHSAX                 __builtin_arm_uhsax

-#define     __USAD8                 __builtin_arm_usad8

-#define     __USADA8                __builtin_arm_usada8

-#define     __SSAT16                __builtin_arm_ssat16

-#define     __USAT16                __builtin_arm_usat16

-#define     __UXTB16                __builtin_arm_uxtb16

-#define     __UXTAB16               __builtin_arm_uxtab16

-#define     __SXTB16                __builtin_arm_sxtb16

-#define     __SXTAB16               __builtin_arm_sxtab16

-#define     __SMUAD                 __builtin_arm_smuad

-#define     __SMUADX                __builtin_arm_smuadx

-#define     __SMLAD                 __builtin_arm_smlad

-#define     __SMLADX                __builtin_arm_smladx

-#define     __SMLALD                __builtin_arm_smlald

-#define     __SMLALDX               __builtin_arm_smlaldx

-#define     __SMUSD                 __builtin_arm_smusd

-#define     __SMUSDX                __builtin_arm_smusdx

-#define     __SMLSD                 __builtin_arm_smlsd

-#define     __SMLSDX                __builtin_arm_smlsdx

-#define     __SMLSLD                __builtin_arm_smlsld

-#define     __SMLSLDX               __builtin_arm_smlsldx

-#define     __SEL                   __builtin_arm_sel

-#define     __QADD                  __builtin_arm_qadd

-#define     __QSUB                  __builtin_arm_qsub

-

-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \

-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )

-

-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \

-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )

-

-__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)

-{

-  int32_t result;

-

-  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );

-  return(result);

-}

-

-#endif /* (__ARM_FEATURE_DSP == 1) */

-/*@} end of group CMSIS_SIMD_intrinsics */

-

-

-#endif /* __CMSIS_ARMCLANG_H */

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_armclang_ltm.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_armclang_ltm.h
deleted file mode 100644
index feec32405..000000000
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_armclang_ltm.h
+++ /dev/null
@@ -1,1891 +0,0 @@
-/**************************************************************************//**
- * @file     cmsis_armclang_ltm.h
- * @brief    CMSIS compiler armclang (Arm Compiler 6) header file
- * @version  V1.2.0
- * @date     08. May 2019
- ******************************************************************************/
-/*
- * Copyright (c) 2018-2019 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
-
-#ifndef __CMSIS_ARMCLANG_H
-#define __CMSIS_ARMCLANG_H
-
-#pragma clang system_header   /* treat file as system include file */
-
-#ifndef __ARM_COMPAT_H
-#include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */
-#endif
-
-/* CMSIS compiler specific defines */
-#ifndef   __ASM
-  #define __ASM                                  __asm
-#endif
-#ifndef   __INLINE
-  #define __INLINE                               __inline
-#endif
-#ifndef   __STATIC_INLINE
-  #define __STATIC_INLINE                        static __inline
-#endif
-#ifndef   __STATIC_FORCEINLINE
-  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline
-#endif
-#ifndef   __NO_RETURN
-  #define __NO_RETURN                            __attribute__((__noreturn__))
-#endif
-#ifndef   __USED
-  #define __USED                                 __attribute__((used))
-#endif
-#ifndef   __WEAK
-  #define __WEAK                                 __attribute__((weak))
-#endif
-#ifndef   __PACKED
-  #define __PACKED                               __attribute__((packed, aligned(1)))
-#endif
-#ifndef   __PACKED_STRUCT
-  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
-#endif
-#ifndef   __PACKED_UNION
-  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
-#endif
-#ifndef   __UNALIGNED_UINT32        /* deprecated */
-  #pragma clang diagnostic push
-  #pragma clang diagnostic ignored "-Wpacked"
-/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
-  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
-  #pragma clang diagnostic pop
-  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-#endif
-#ifndef   __UNALIGNED_UINT16_WRITE
-  #pragma clang diagnostic push
-  #pragma clang diagnostic ignored "-Wpacked"
-/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
-  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
-  #pragma clang diagnostic pop
-  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
-#endif
-#ifndef   __UNALIGNED_UINT16_READ
-  #pragma clang diagnostic push
-  #pragma clang diagnostic ignored "-Wpacked"
-/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
-  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
-  #pragma clang diagnostic pop
-  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-#endif
-#ifndef   __UNALIGNED_UINT32_WRITE
-  #pragma clang diagnostic push
-  #pragma clang diagnostic ignored "-Wpacked"
-/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
-  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
-  #pragma clang diagnostic pop
-  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-#endif
-#ifndef   __UNALIGNED_UINT32_READ
-  #pragma clang diagnostic push
-  #pragma clang diagnostic ignored "-Wpacked"
-/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
-  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
-  #pragma clang diagnostic pop
-  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-#endif
-#ifndef   __ALIGNED
-  #define __ALIGNED(x)                           __attribute__((aligned(x)))
-#endif
-#ifndef   __RESTRICT
-  #define __RESTRICT                             __restrict
-#endif
-#ifndef   __COMPILER_BARRIER
-  #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
-#endif
-
-/* #########################  Startup and Lowlevel Init  ######################## */
-
-#ifndef __PROGRAM_START
-#define __PROGRAM_START           __main
-#endif
-
-#ifndef __INITIAL_SP
-#define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit
-#endif
-
-#ifndef __STACK_LIMIT
-#define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base
-#endif
-
-#ifndef __VECTOR_TABLE
-#define __VECTOR_TABLE            __Vectors
-#endif
-
-#ifndef __VECTOR_TABLE_ATTRIBUTE
-#define __VECTOR_TABLE_ATTRIBUTE  __attribute((used, section("RESET")))
-#endif
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-/**
-  \brief   Enable IRQ Interrupts
-  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-/* intrinsic void __enable_irq();  see arm_compat.h */
-
-
-/**
-  \brief   Disable IRQ Interrupts
-  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-/* intrinsic void __disable_irq();  see arm_compat.h */
-
-
-/**
-  \brief   Get Control Register
-  \details Returns the content of the Control Register.
-  \return               Control Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Control Register (non-secure)
-  \details Returns the content of the non-secure Control Register when in secure mode.
-  \return               non-secure Control Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Control Register
-  \details Writes the given value to the Control Register.
-  \param [in]    control  Control Register value to set
- */
-__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
-{
-  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Control Register (non-secure)
-  \details Writes the given value to the non-secure Control Register when in secure state.
-  \param [in]    control  Control Register value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
-{
-  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
-}
-#endif
-
-
-/**
-  \brief   Get IPSR Register
-  \details Returns the content of the IPSR Register.
-  \return               IPSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Get APSR Register
-  \details Returns the content of the APSR Register.
-  \return               APSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_APSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Get xPSR Register
-  \details Returns the content of the xPSR Register.
-  \return               xPSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Get Process Stack Pointer
-  \details Returns the current value of the Process Stack Pointer (PSP).
-  \return               PSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_PSP(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Process Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
-  \return               PSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Process Stack Pointer
-  \details Assigns the given value to the Process Stack Pointer (PSP).
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Process Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
-}
-#endif
-
-
-/**
-  \brief   Get Main Stack Pointer
-  \details Returns the current value of the Main Stack Pointer (MSP).
-  \return               MSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_MSP(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, msp" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Main Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
-  \return               MSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Main Stack Pointer
-  \details Assigns the given value to the Main Stack Pointer (MSP).
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Main Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
-}
-#endif
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
-  \return               SP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Set Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
-  \param [in]    topOfStack  Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
-{
-  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
-}
-#endif
-
-
-/**
-  \brief   Get Priority Mask
-  \details Returns the current state of the priority mask bit from the Priority Mask Register.
-  \return               Priority Mask value
- */
-__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Priority Mask (non-secure)
-  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
-  \return               Priority Mask value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Priority Mask
-  \details Assigns the given value to the Priority Mask Register.
-  \param [in]    priMask  Priority Mask
- */
-__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Priority Mask (non-secure)
-  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
-  \param [in]    priMask  Priority Mask
- */
-__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
-}
-#endif
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Enable FIQ
-  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */
-
-
-/**
-  \brief   Disable FIQ
-  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */
-
-
-/**
-  \brief   Get Base Priority
-  \details Returns the current value of the Base Priority register.
-  \return               Base Priority register value
- */
-__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Base Priority (non-secure)
-  \details Returns the current value of the non-secure Base Priority register when in secure state.
-  \return               Base Priority register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Base Priority
-  \details Assigns the given value to the Base Priority register.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
-{
-  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Base Priority (non-secure)
-  \details Assigns the given value to the non-secure Base Priority register when in secure state.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
-{
-  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
-}
-#endif
-
-
-/**
-  \brief   Set Base Priority with condition
-  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
-           or the new value increases the BASEPRI priority level.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
-  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
-}
-
-
-/**
-  \brief   Get Fault Mask
-  \details Returns the current value of the Fault Mask register.
-  \return               Fault Mask register value
- */
-__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Fault Mask (non-secure)
-  \details Returns the current value of the non-secure Fault Mask register when in secure state.
-  \return               Fault Mask register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Fault Mask
-  \details Assigns the given value to the Fault Mask register.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Fault Mask (non-secure)
-  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-
-/**
-  \brief   Get Process Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence zero is returned always in non-secure
-  mode.
-  
-  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
-  \return               PSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-    // without main extensions, the non-secure PSPLIM is RAZ/WI
-  return 0U;
-#else
-  uint32_t result;
-  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
-  return result;
-#endif
-}
-
-#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Process Stack Pointer Limit (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence zero is returned always in non-secure
-  mode.
-
-  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
-  \return               PSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
-  // without main extensions, the non-secure PSPLIM is RAZ/WI
-  return 0U;
-#else
-  uint32_t result;
-  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
-  return result;
-#endif
-}
-#endif
-
-
-/**
-  \brief   Set Process Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence the write is silently ignored in non-secure
-  mode.
-  
-  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-  // without main extensions, the non-secure PSPLIM is RAZ/WI
-  (void)ProcStackPtrLimit;
-#else
-  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
-/**
-  \brief   Set Process Stack Pointer (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence the write is silently ignored in non-secure
-  mode.
-
-  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
-  // without main extensions, the non-secure PSPLIM is RAZ/WI
-  (void)ProcStackPtrLimit;
-#else
-  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
-#endif
-}
-#endif
-
-
-/**
-  \brief   Get Main Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence zero is returned always.
-
-  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
-  \return               MSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-  // without main extensions, the non-secure MSPLIM is RAZ/WI
-  return 0U;
-#else
-  uint32_t result;
-  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
-  return result;
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
-/**
-  \brief   Get Main Stack Pointer Limit (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence zero is returned always.
-
-  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
-  \return               MSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
-  // without main extensions, the non-secure MSPLIM is RAZ/WI
-  return 0U;
-#else
-  uint32_t result;
-  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
-  return result;
-#endif
-}
-#endif
-
-
-/**
-  \brief   Set Main Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence the write is silently ignored.
-
-  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
-  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-  // without main extensions, the non-secure MSPLIM is RAZ/WI
-  (void)MainStackPtrLimit;
-#else
-  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
-/**
-  \brief   Set Main Stack Pointer Limit (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence the write is silently ignored.
-
-  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
-  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
-  // without main extensions, the non-secure MSPLIM is RAZ/WI
-  (void)MainStackPtrLimit;
-#else
-  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
-#endif
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-/**
-  \brief   Get FPSCR
-  \details Returns the current value of the Floating Point Status/Control register.
-  \return               Floating Point Status/Control register value
- */
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr
-#else
-#define __get_FPSCR()      ((uint32_t)0U)
-#endif
-
-/**
-  \brief   Set FPSCR
-  \details Assigns the given value to the Floating Point Status/Control register.
-  \param [in]    fpscr  Floating Point Status/Control value to set
- */
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-#define __set_FPSCR      __builtin_arm_set_fpscr
-#else
-#define __set_FPSCR(x)      ((void)(x))
-#endif
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constraint "l"
- * Otherwise, use general registers, specified by constraint "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/**
-  \brief   No Operation
-  \details No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP          __builtin_arm_nop
-
-/**
-  \brief   Wait For Interrupt
-  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
- */
-#define __WFI          __builtin_arm_wfi
-
-
-/**
-  \brief   Wait For Event
-  \details Wait For Event is a hint instruction that permits the processor to enter
-           a low-power state until one of a number of events occurs.
- */
-#define __WFE          __builtin_arm_wfe
-
-
-/**
-  \brief   Send Event
-  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV          __builtin_arm_sev
-
-
-/**
-  \brief   Instruction Synchronization Barrier
-  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
-           so that all instructions following the ISB are fetched from cache or memory,
-           after the instruction has been completed.
- */
-#define __ISB()        __builtin_arm_isb(0xF)
-
-/**
-  \brief   Data Synchronization Barrier
-  \details Acts as a special kind of Data Memory Barrier.
-           It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB()        __builtin_arm_dsb(0xF)
-
-
-/**
-  \brief   Data Memory Barrier
-  \details Ensures the apparent order of the explicit memory operations before
-           and after the instruction, without ensuring their completion.
- */
-#define __DMB()        __builtin_arm_dmb(0xF)
-
-
-/**
-  \brief   Reverse byte order (32 bit)
-  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#define __REV(value)   __builtin_bswap32(value)
-
-
-/**
-  \brief   Reverse byte order (16 bit)
-  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#define __REV16(value) __ROR(__REV(value), 16)
-
-
-/**
-  \brief   Reverse byte order (16 bit)
-  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#define __REVSH(value) (int16_t)__builtin_bswap16(value)
-
-
-/**
-  \brief   Rotate Right in unsigned value (32 bit)
-  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-  \param [in]    op1  Value to rotate
-  \param [in]    op2  Number of Bits to rotate
-  \return               Rotated value
- */
-__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
-  op2 %= 32U;
-  if (op2 == 0U)
-  {
-    return op1;
-  }
-  return (op1 >> op2) | (op1 << (32U - op2));
-}
-
-
-/**
-  \brief   Breakpoint
-  \details Causes the processor to enter Debug state.
-           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-  \param [in]    value  is ignored by the processor.
-                 If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)     __ASM volatile ("bkpt "#value)
-
-
-/**
-  \brief   Reverse bit order of value
-  \details Reverses the bit order of the given value.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#define __RBIT            __builtin_arm_rbit
-
-/**
-  \brief   Count leading zeros
-  \details Counts the number of leading zeros of a data value.
-  \param [in]  value  Value to count the leading zeros
-  \return             number of leading zeros in value
- */
-__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
-{
-  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
-     __builtin_clz(0) is undefined behaviour, so handle this case specially.
-     This guarantees ARM-compatible results if happening to compile on a non-ARM
-     target, and ensures the compiler doesn't decide to activate any
-     optimisations using the logic "value was passed to __builtin_clz, so it
-     is non-zero".
-     ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
-     single CLZ instruction.
-   */
-  if (value == 0U)
-  {
-    return 32U;
-  }
-  return __builtin_clz(value);
-}
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-/**
-  \brief   LDR Exclusive (8 bit)
-  \details Executes a exclusive LDR instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-#define __LDREXB        (uint8_t)__builtin_arm_ldrex
-
-
-/**
-  \brief   LDR Exclusive (16 bit)
-  \details Executes a exclusive LDR instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-#define __LDREXH        (uint16_t)__builtin_arm_ldrex
-
-
-/**
-  \brief   LDR Exclusive (32 bit)
-  \details Executes a exclusive LDR instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-#define __LDREXW        (uint32_t)__builtin_arm_ldrex
-
-
-/**
-  \brief   STR Exclusive (8 bit)
-  \details Executes a exclusive STR instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define __STREXB        (uint32_t)__builtin_arm_strex
-
-
-/**
-  \brief   STR Exclusive (16 bit)
-  \details Executes a exclusive STR instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define __STREXH        (uint32_t)__builtin_arm_strex
-
-
-/**
-  \brief   STR Exclusive (32 bit)
-  \details Executes a exclusive STR instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define __STREXW        (uint32_t)__builtin_arm_strex
-
-
-/**
-  \brief   Remove the exclusive lock
-  \details Removes the exclusive lock which is created by LDREX.
- */
-#define __CLREX             __builtin_arm_clrex
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-
-/**
-  \brief   Signed Saturate
-  \details Saturates a signed value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (1..32)
-  \return             Saturated value
- */
-#define __SSAT             __builtin_arm_ssat
-
-
-/**
-  \brief   Unsigned Saturate
-  \details Saturates an unsigned value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (0..31)
-  \return             Saturated value
- */
-#define __USAT             __builtin_arm_usat
-
-
-/**
-  \brief   Rotate Right with Extend (32 bit)
-  \details Moves each bit of a bitstring right by one bit.
-           The carry input is shifted in at the left end of the bitstring.
-  \param [in]    value  Value to rotate
-  \return               Rotated value
- */
-__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-}
-
-
-/**
-  \brief   LDRT Unprivileged (8 bit)
-  \details Executes a Unprivileged LDRT instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
-{
-  uint32_t result;
-
-  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
-  return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDRT Unprivileged (16 bit)
-  \details Executes a Unprivileged LDRT instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
-{
-  uint32_t result;
-
-  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
-  return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDRT Unprivileged (32 bit)
-  \details Executes a Unprivileged LDRT instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
-{
-  uint32_t result;
-
-  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
-  return(result);
-}
-
-
-/**
-  \brief   STRT Unprivileged (8 bit)
-  \details Executes a Unprivileged STRT instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
-{
-  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   STRT Unprivileged (16 bit)
-  \details Executes a Unprivileged STRT instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
-{
-  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   STRT Unprivileged (32 bit)
-  \details Executes a Unprivileged STRT instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
-{
-  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
-}
-
-#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-/**
-  \brief   Signed Saturate
-  \details Saturates a signed value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (1..32)
-  \return             Saturated value
- */
-__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
-{
-  if ((sat >= 1U) && (sat <= 32U))
-  {
-    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
-    const int32_t min = -1 - max ;
-    if (val > max)
-    {
-      return max;
-    }
-    else if (val < min)
-    {
-      return min;
-    }
-  }
-  return val;
-}
-
-/**
-  \brief   Unsigned Saturate
-  \details Saturates an unsigned value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (0..31)
-  \return             Saturated value
- */
-__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
-{
-  if (sat <= 31U)
-  {
-    const uint32_t max = ((1U << sat) - 1U);
-    if (val > (int32_t)max)
-    {
-      return max;
-    }
-    else if (val < 0)
-    {
-      return 0U;
-    }
-  }
-  return (uint32_t)val;
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-/**
-  \brief   Load-Acquire (8 bit)
-  \details Executes a LDAB instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
-{
-  uint32_t result;
-
-  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
-  return ((uint8_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire (16 bit)
-  \details Executes a LDAH instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
-{
-  uint32_t result;
-
-  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
-  return ((uint16_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire (32 bit)
-  \details Executes a LDA instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
-{
-  uint32_t result;
-
-  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
-  return(result);
-}
-
-
-/**
-  \brief   Store-Release (8 bit)
-  \details Executes a STLB instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
-{
-  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Store-Release (16 bit)
-  \details Executes a STLH instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
-{
-  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Store-Release (32 bit)
-  \details Executes a STL instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
-{
-  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Load-Acquire Exclusive (8 bit)
-  \details Executes a LDAB exclusive instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
-
-
-/**
-  \brief   Load-Acquire Exclusive (16 bit)
-  \details Executes a LDAH exclusive instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
-
-
-/**
-  \brief   Load-Acquire Exclusive (32 bit)
-  \details Executes a LDA exclusive instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
-
-
-/**
-  \brief   Store-Release Exclusive (8 bit)
-  \details Executes a STLB exclusive instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
-
-
-/**
-  \brief   Store-Release Exclusive (16 bit)
-  \details Executes a STLH exclusive instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
-
-
-/**
-  \brief   Store-Release Exclusive (32 bit)
-  \details Executes a STL exclusive instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define     __STLEX                  (uint32_t)__builtin_arm_stlex
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
-
-__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({                          \
-  int32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-#define __USAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
-{
-  int32_t result;
-
-  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
-{
-  int32_t result;
-
-  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
-
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
-
-__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
-  int32_t result;
-
-  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#endif /* (__ARM_FEATURE_DSP == 1) */
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#endif /* __CMSIS_ARMCLANG_H */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_gcc.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_gcc.h
index 1e08e7e80..045aaf19d 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_gcc.h
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_gcc.h
@@ -1,11 +1,11 @@
 /**************************************************************************//**

  * @file     cmsis_gcc.h

  * @brief    CMSIS compiler GCC header file

- * @version  V5.2.0

- * @date     08. May 2019

+ * @version  V5.4.1

+ * @date     27. May 2021

  ******************************************************************************/

 /*

- * Copyright (c) 2009-2019 Arm Limited. All rights reserved.

+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.

  *

  * SPDX-License-Identifier: Apache-2.0

  *

@@ -46,9 +46,9 @@
 #ifndef   __STATIC_INLINE

   #define __STATIC_INLINE                        static inline

 #endif

-#ifndef   __STATIC_FORCEINLINE                 

+#ifndef   __STATIC_FORCEINLINE

   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline

-#endif                                           

+#endif

 #ifndef   __NO_RETURN

   #define __NO_RETURN                            __attribute__((__noreturn__))

 #endif

@@ -126,23 +126,23 @@
   \details This default implementations initialized all data and additional bss

            sections relying on .copy.table and .zero.table specified properly

            in the used linker script.

-  

+

  */

 __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)

 {

   extern void _start(void) __NO_RETURN;

-  

+

   typedef struct {

     uint32_t const* src;

     uint32_t* dest;

     uint32_t  wlen;

   } __copy_table_t;

-  

+

   typedef struct {

     uint32_t* dest;

     uint32_t  wlen;

   } __zero_table_t;

-  

+

   extern const __copy_table_t __copy_table_start__;

   extern const __copy_table_t __copy_table_end__;

   extern const __zero_table_t __zero_table_start__;

@@ -153,16 +153,16 @@ __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
       pTable->dest[i] = pTable->src[i];

     }

   }

- 

+

   for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {

     for(uint32_t i=0u; i<pTable->wlen; ++i) {

       pTable->dest[i] = 0u;

     }

   }

- 

+

   _start();

 }

-  

+

 #define __PROGRAM_START           __cmsis_start

 #endif

 

@@ -179,702 +179,27 @@ __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
 #endif

 

 #ifndef __VECTOR_TABLE_ATTRIBUTE

-#define __VECTOR_TABLE_ATTRIBUTE  __attribute((used, section(".vectors")))

-#endif

-

-/* ###########################  Core Function Access  ########################### */

-/** \ingroup  CMSIS_Core_FunctionInterface

-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions

-  @{

- */

-

-/**

-  \brief   Enable IRQ Interrupts

-  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.

-           Can only be executed in Privileged modes.

- */

-__STATIC_FORCEINLINE void __enable_irq(void)

-{

-  __ASM volatile ("cpsie i" : : : "memory");

-}

-

-

-/**

-  \brief   Disable IRQ Interrupts

-  \details Disables IRQ interrupts by setting the I-bit in the CPSR.

-           Can only be executed in Privileged modes.

- */

-__STATIC_FORCEINLINE void __disable_irq(void)

-{

-  __ASM volatile ("cpsid i" : : : "memory");

-}

-

-

-/**

-  \brief   Get Control Register

-  \details Returns the content of the Control Register.

-  \return               Control Register value

- */

-__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, control" : "=r" (result) );

-  return(result);

-}

-

-

-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

-/**

-  \brief   Get Control Register (non-secure)

-  \details Returns the content of the non-secure Control Register when in secure mode.

-  \return               non-secure Control Register value

- */

-__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );

-  return(result);

-}

-#endif

-

-

-/**

-  \brief   Set Control Register

-  \details Writes the given value to the Control Register.

-  \param [in]    control  Control Register value to set

- */

-__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)

-{

-  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");

-}

-

-

-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

-/**

-  \brief   Set Control Register (non-secure)

-  \details Writes the given value to the non-secure Control Register when in secure state.

-  \param [in]    control  Control Register value to set

- */

-__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)

-{

-  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");

-}

-#endif

-

-

-/**

-  \brief   Get IPSR Register

-  \details Returns the content of the IPSR Register.

-  \return               IPSR Register value

- */

-__STATIC_FORCEINLINE uint32_t __get_IPSR(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );

-  return(result);

-}

-

-

-/**

-  \brief   Get APSR Register

-  \details Returns the content of the APSR Register.

-  \return               APSR Register value

- */

-__STATIC_FORCEINLINE uint32_t __get_APSR(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );

-  return(result);

-}

-

-

-/**

-  \brief   Get xPSR Register

-  \details Returns the content of the xPSR Register.

-  \return               xPSR Register value

- */

-__STATIC_FORCEINLINE uint32_t __get_xPSR(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );

-  return(result);

-}

-

-

-/**

-  \brief   Get Process Stack Pointer

-  \details Returns the current value of the Process Stack Pointer (PSP).

-  \return               PSP Register value

- */

-__STATIC_FORCEINLINE uint32_t __get_PSP(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, psp"  : "=r" (result) );

-  return(result);

-}

-

-

-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

-/**

-  \brief   Get Process Stack Pointer (non-secure)

-  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.

-  \return               PSP Register value

- */

-__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );

-  return(result);

-}

-#endif

-

-

-/**

-  \brief   Set Process Stack Pointer

-  \details Assigns the given value to the Process Stack Pointer (PSP).

-  \param [in]    topOfProcStack  Process Stack Pointer value to set

- */

-__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)

-{

-  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );

-}

-

-

-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

-/**

-  \brief   Set Process Stack Pointer (non-secure)

-  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.

-  \param [in]    topOfProcStack  Process Stack Pointer value to set

- */

-__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)

-{

-  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );

-}

-#endif

-

-

-/**

-  \brief   Get Main Stack Pointer

-  \details Returns the current value of the Main Stack Pointer (MSP).

-  \return               MSP Register value

- */

-__STATIC_FORCEINLINE uint32_t __get_MSP(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, msp" : "=r" (result) );

-  return(result);

-}

-

-

-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

-/**

-  \brief   Get Main Stack Pointer (non-secure)

-  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.

-  \return               MSP Register value

- */

-__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );

-  return(result);

-}

-#endif

-

-

-/**

-  \brief   Set Main Stack Pointer

-  \details Assigns the given value to the Main Stack Pointer (MSP).

-  \param [in]    topOfMainStack  Main Stack Pointer value to set

- */

-__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)

-{

-  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );

-}

-

-

-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

-/**

-  \brief   Set Main Stack Pointer (non-secure)

-  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.

-  \param [in]    topOfMainStack  Main Stack Pointer value to set

- */

-__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)

-{

-  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );

-}

-#endif

-

-

-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

-/**

-  \brief   Get Stack Pointer (non-secure)

-  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.

-  \return               SP Register value

- */

-__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );

-  return(result);

-}

-

-

-/**

-  \brief   Set Stack Pointer (non-secure)

-  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.

-  \param [in]    topOfStack  Stack Pointer value to set

- */

-__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)

-{

-  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );

-}

-#endif

-

-

-/**

-  \brief   Get Priority Mask

-  \details Returns the current state of the priority mask bit from the Priority Mask Register.

-  \return               Priority Mask value

- */

-__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");

-  return(result);

-}

-

-

-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

-/**

-  \brief   Get Priority Mask (non-secure)

-  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.

-  \return               Priority Mask value

- */

-__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");

-  return(result);

-}

-#endif

-

-

-/**

-  \brief   Set Priority Mask

-  \details Assigns the given value to the Priority Mask Register.

-  \param [in]    priMask  Priority Mask

- */

-__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)

-{

-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");

-}

-

-

-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

-/**

-  \brief   Set Priority Mask (non-secure)

-  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.

-  \param [in]    priMask  Priority Mask

- */

-__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)

-{

-  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");

-}

-#endif

-

-

-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \

-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \

-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )

-/**

-  \brief   Enable FIQ

-  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.

-           Can only be executed in Privileged modes.

- */

-__STATIC_FORCEINLINE void __enable_fault_irq(void)

-{

-  __ASM volatile ("cpsie f" : : : "memory");

-}

-

-

-/**

-  \brief   Disable FIQ

-  \details Disables FIQ interrupts by setting the F-bit in the CPSR.

-           Can only be executed in Privileged modes.

- */

-__STATIC_FORCEINLINE void __disable_fault_irq(void)

-{

-  __ASM volatile ("cpsid f" : : : "memory");

-}

-

-

-/**

-  \brief   Get Base Priority

-  \details Returns the current value of the Base Priority register.

-  \return               Base Priority register value

- */

-__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, basepri" : "=r" (result) );

-  return(result);

-}

-

-

-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

-/**

-  \brief   Get Base Priority (non-secure)

-  \details Returns the current value of the non-secure Base Priority register when in secure state.

-  \return               Base Priority register value

- */

-__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );

-  return(result);

-}

-#endif

-

-

-/**

-  \brief   Set Base Priority

-  \details Assigns the given value to the Base Priority register.

-  \param [in]    basePri  Base Priority value to set

- */

-__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)

-{

-  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");

-}

-

-

-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

-/**

-  \brief   Set Base Priority (non-secure)

-  \details Assigns the given value to the non-secure Base Priority register when in secure state.

-  \param [in]    basePri  Base Priority value to set

- */

-__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)

-{

-  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");

-}

-#endif

-

-

-/**

-  \brief   Set Base Priority with condition

-  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,

-           or the new value increases the BASEPRI priority level.

-  \param [in]    basePri  Base Priority value to set

- */

-__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)

-{

-  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");

-}

-

-

-/**

-  \brief   Get Fault Mask

-  \details Returns the current value of the Fault Mask register.

-  \return               Fault Mask register value

- */

-__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );

-  return(result);

-}

-

-

-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

-/**

-  \brief   Get Fault Mask (non-secure)

-  \details Returns the current value of the non-secure Fault Mask register when in secure state.

-  \return               Fault Mask register value

- */

-__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );

-  return(result);

-}

-#endif

-

-

-/**

-  \brief   Set Fault Mask

-  \details Assigns the given value to the Fault Mask register.

-  \param [in]    faultMask  Fault Mask value to set

- */

-__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)

-{

-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");

-}

-

-

-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

-/**

-  \brief   Set Fault Mask (non-secure)

-  \details Assigns the given value to the non-secure Fault Mask register when in secure state.

-  \param [in]    faultMask  Fault Mask value to set

- */

-__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)

-{

-  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");

-}

-#endif

-

-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \

-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \

-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */

-

-

-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \

-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )

-

-/**

-  \brief   Get Process Stack Pointer Limit

-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure

-  Stack Pointer Limit register hence zero is returned always in non-secure

-  mode.

-  

-  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).

-  \return               PSPLIM Register value

- */

-__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)

-{

-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \

-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))

-    // without main extensions, the non-secure PSPLIM is RAZ/WI

-  return 0U;

-#else

-  uint32_t result;

-  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );

-  return result;

-#endif

-}

-

-#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))

-/**

-  \brief   Get Process Stack Pointer Limit (non-secure)

-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure

-  Stack Pointer Limit register hence zero is returned always.

-

-  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.

-  \return               PSPLIM Register value

- */

-__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)

-{

-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))

-  // without main extensions, the non-secure PSPLIM is RAZ/WI

-  return 0U;

-#else

-  uint32_t result;

-  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );

-  return result;

-#endif

-}

-#endif

-

-

-/**

-  \brief   Set Process Stack Pointer Limit

-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure

-  Stack Pointer Limit register hence the write is silently ignored in non-secure

-  mode.

-  

-  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).

-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set

- */

-__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)

-{

-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \

-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))

-  // without main extensions, the non-secure PSPLIM is RAZ/WI

-  (void)ProcStackPtrLimit;

-#else

-  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));

+#define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section(".vectors")))

 #endif

-}

-

-

-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))

-/**

-  \brief   Set Process Stack Pointer (non-secure)

-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure

-  Stack Pointer Limit register hence the write is silently ignored.

 

-  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.

-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set

- */

-__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)

-{

-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))

-  // without main extensions, the non-secure PSPLIM is RAZ/WI

-  (void)ProcStackPtrLimit;

-#else

-  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));

+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)

+#ifndef __STACK_SEAL

+#define __STACK_SEAL              __StackSeal

 #endif

-}

-#endif

-

-

-/**

-  \brief   Get Main Stack Pointer Limit

-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure

-  Stack Pointer Limit register hence zero is returned always in non-secure

-  mode.

 

-  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).

-  \return               MSPLIM Register value

- */

-__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)

-{

-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \

-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))

-  // without main extensions, the non-secure MSPLIM is RAZ/WI

-  return 0U;

-#else

-  uint32_t result;

-  __ASM volatile ("MRS %0, msplim" : "=r" (result) );

-  return result;

-#endif

-}

-

-

-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))

-/**

-  \brief   Get Main Stack Pointer Limit (non-secure)

-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure

-  Stack Pointer Limit register hence zero is returned always.

-

-  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.

-  \return               MSPLIM Register value

- */

-__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)

-{

-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))

-  // without main extensions, the non-secure MSPLIM is RAZ/WI

-  return 0U;

-#else

-  uint32_t result;

-  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );

-  return result;

-#endif

-}

-#endif

-

-

-/**

-  \brief   Set Main Stack Pointer Limit

-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure

-  Stack Pointer Limit register hence the write is silently ignored in non-secure

-  mode.

-

-  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).

-  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set

- */

-__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)

-{

-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \

-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))

-  // without main extensions, the non-secure MSPLIM is RAZ/WI

-  (void)MainStackPtrLimit;

-#else

-  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));

+#ifndef __TZ_STACK_SEAL_SIZE

+#define __TZ_STACK_SEAL_SIZE      8U

 #endif

-}

-

-

-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))

-/**

-  \brief   Set Main Stack Pointer Limit (non-secure)

-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure

-  Stack Pointer Limit register hence the write is silently ignored.

 

-  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.

-  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set

- */

-__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)

-{

-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))

-  // without main extensions, the non-secure MSPLIM is RAZ/WI

-  (void)MainStackPtrLimit;

-#else

-  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));

+#ifndef __TZ_STACK_SEAL_VALUE

+#define __TZ_STACK_SEAL_VALUE     0xFEF5EDA5FEF5EDA5ULL

 #endif

-}

-#endif

-

-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \

-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */

-

 

-/**

-  \brief   Get FPSCR

-  \details Returns the current value of the Floating Point Status/Control register.

-  \return               Floating Point Status/Control register value

- */

-__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)

-{

-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \

-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )

-#if __has_builtin(__builtin_arm_get_fpscr) 

-// Re-enable using built-in when GCC has been fixed

-// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)

-  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */

-  return __builtin_arm_get_fpscr();

-#else

-  uint32_t result;

 

-  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );

-  return(result);

-#endif

-#else

-  return(0U);

-#endif

+__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {

+  *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;

 }

-

-

-/**

-  \brief   Set FPSCR

-  \details Assigns the given value to the Floating Point Status/Control register.

-  \param [in]    fpscr  Floating Point Status/Control value to set

- */

-__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)

-{

-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \

-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )

-#if __has_builtin(__builtin_arm_set_fpscr)

-// Re-enable using built-in when GCC has been fixed

-// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)

-  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */

-  __builtin_arm_set_fpscr(fpscr);

-#else

-  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");

-#endif

-#else

-  (void)fpscr;

 #endif

-}

-

-

-/*@} end of CMSIS_Core_RegAccFunctions */

 

 

 /* ##########################  Core Instruction Access  ######################### */

@@ -906,7 +231,7 @@ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
   \brief   Wait For Interrupt

   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.

  */

-#define __WFI()                             __ASM volatile ("wfi")

+#define __WFI()                             __ASM volatile ("wfi":::"memory")

 

 

 /**

@@ -914,7 +239,7 @@ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
   \details Wait For Event is a hint instruction that permits the processor to enter

            a low-power state until one of a number of events occurs.

  */

-#define __WFE()                             __ASM volatile ("wfe")

+#define __WFE()                             __ASM volatile ("wfe":::"memory")

 

 

 /**

@@ -971,7 +296,7 @@ __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
 #else

   uint32_t result;

 

-  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

+  __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

   return result;

 #endif

 }

@@ -987,7 +312,7 @@ __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
 {

   uint32_t result;

 

-  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

+  __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

   return result;

 }

 

@@ -1005,7 +330,7 @@ __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
 #else

   int16_t result;

 

-  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

+  __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

   return result;

 #endif

 }

@@ -1052,7 +377,7 @@ __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
 #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \

      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \

      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )

-   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );

+   __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) );

 #else

   uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */

 

@@ -1233,11 +558,11 @@ __STATIC_FORCEINLINE void __CLREX(void)
   \param [in]  ARG2  Bit position to saturate to (1..32)

   \return             Saturated value

  */

-#define __SSAT(ARG1,ARG2) \

+#define __SSAT(ARG1, ARG2) \

 __extension__ \

 ({                          \

   int32_t __RES, __ARG1 = (ARG1); \

-  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \

+  __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \

   __RES; \

  })

 

@@ -1249,11 +574,11 @@ __extension__ \
   \param [in]  ARG2  Bit position to saturate to (0..31)

   \return             Saturated value

  */

-#define __USAT(ARG1,ARG2) \

- __extension__ \

+#define __USAT(ARG1, ARG2) \

+__extension__ \

 ({                          \

   uint32_t __RES, __ARG1 = (ARG1); \

-  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \

+  __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \

   __RES; \

  })

 

@@ -1438,7 +763,7 @@ __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
 {

     uint32_t result;

 

-   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );

+   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );

    return ((uint8_t) result);

 }

 

@@ -1453,7 +778,7 @@ __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
 {

     uint32_t result;

 

-   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );

+   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );

    return ((uint16_t) result);

 }

 

@@ -1468,7 +793,7 @@ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
 {

     uint32_t result;

 

-   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );

+   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );

    return(result);

 }

 

@@ -1481,7 +806,7 @@ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
  */

 __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)

 {

-   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );

+   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );

 }

 

 

@@ -1493,7 +818,7 @@ __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
  */

 __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)

 {

-   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );

+   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );

 }

 

 

@@ -1505,7 +830,7 @@ __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
  */

 __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)

 {

-   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );

+   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );

 }

 

 

@@ -1519,7 +844,7 @@ __STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
 {

     uint32_t result;

 

-   __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );

+   __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );

    return ((uint8_t) result);

 }

 

@@ -1534,7 +859,7 @@ __STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
 {

     uint32_t result;

 

-   __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );

+   __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );

    return ((uint16_t) result);

 }

 

@@ -1549,7 +874,7 @@ __STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
 {

     uint32_t result;

 

-   __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );

+   __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );

    return(result);

 }

 

@@ -1566,7 +891,7 @@ __STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
 {

    uint32_t result;

 

-   __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );

+   __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );

    return(result);

 }

 

@@ -1583,7 +908,7 @@ __STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
 {

    uint32_t result;

 

-   __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );

+   __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );

    return(result);

 }

 

@@ -1600,7 +925,7 @@ __STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
 {

    uint32_t result;

 

-   __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );

+   __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );

    return(result);

 }

 

@@ -1610,6 +935,703 @@ __STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */

 

 

+/* ###########################  Core Function Access  ########################### */

+/** \ingroup  CMSIS_Core_FunctionInterface

+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions

+  @{

+ */

+

+/**

+  \brief   Enable IRQ Interrupts

+  \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.

+           Can only be executed in Privileged modes.

+ */

+__STATIC_FORCEINLINE void __enable_irq(void)

+{

+  __ASM volatile ("cpsie i" : : : "memory");

+}

+

+

+/**

+  \brief   Disable IRQ Interrupts

+  \details Disables IRQ interrupts by setting special-purpose register PRIMASK.

+           Can only be executed in Privileged modes.

+ */

+__STATIC_FORCEINLINE void __disable_irq(void)

+{

+  __ASM volatile ("cpsid i" : : : "memory");

+}

+

+

+/**

+  \brief   Get Control Register

+  \details Returns the content of the Control Register.

+  \return               Control Register value

+ */

+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, control" : "=r" (result) );

+  return(result);

+}

+

+

+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

+/**

+  \brief   Get Control Register (non-secure)

+  \details Returns the content of the non-secure Control Register when in secure mode.

+  \return               non-secure Control Register value

+ */

+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );

+  return(result);

+}

+#endif

+

+

+/**

+  \brief   Set Control Register

+  \details Writes the given value to the Control Register.

+  \param [in]    control  Control Register value to set

+ */

+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)

+{

+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");

+  __ISB();

+}

+

+

+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

+/**

+  \brief   Set Control Register (non-secure)

+  \details Writes the given value to the non-secure Control Register when in secure state.

+  \param [in]    control  Control Register value to set

+ */

+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)

+{

+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");

+  __ISB();

+}

+#endif

+

+

+/**

+  \brief   Get IPSR Register

+  \details Returns the content of the IPSR Register.

+  \return               IPSR Register value

+ */

+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );

+  return(result);

+}

+

+

+/**

+  \brief   Get APSR Register

+  \details Returns the content of the APSR Register.

+  \return               APSR Register value

+ */

+__STATIC_FORCEINLINE uint32_t __get_APSR(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );

+  return(result);

+}

+

+

+/**

+  \brief   Get xPSR Register

+  \details Returns the content of the xPSR Register.

+  \return               xPSR Register value

+ */

+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );

+  return(result);

+}

+

+

+/**

+  \brief   Get Process Stack Pointer

+  \details Returns the current value of the Process Stack Pointer (PSP).

+  \return               PSP Register value

+ */

+__STATIC_FORCEINLINE uint32_t __get_PSP(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );

+  return(result);

+}

+

+

+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

+/**

+  \brief   Get Process Stack Pointer (non-secure)

+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.

+  \return               PSP Register value

+ */

+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );

+  return(result);

+}

+#endif

+

+

+/**

+  \brief   Set Process Stack Pointer

+  \details Assigns the given value to the Process Stack Pointer (PSP).

+  \param [in]    topOfProcStack  Process Stack Pointer value to set

+ */

+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)

+{

+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );

+}

+

+

+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

+/**

+  \brief   Set Process Stack Pointer (non-secure)

+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.

+  \param [in]    topOfProcStack  Process Stack Pointer value to set

+ */

+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)

+{

+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );

+}

+#endif

+

+

+/**

+  \brief   Get Main Stack Pointer

+  \details Returns the current value of the Main Stack Pointer (MSP).

+  \return               MSP Register value

+ */

+__STATIC_FORCEINLINE uint32_t __get_MSP(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, msp" : "=r" (result) );

+  return(result);

+}

+

+

+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

+/**

+  \brief   Get Main Stack Pointer (non-secure)

+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.

+  \return               MSP Register value

+ */

+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );

+  return(result);

+}

+#endif

+

+

+/**

+  \brief   Set Main Stack Pointer

+  \details Assigns the given value to the Main Stack Pointer (MSP).

+  \param [in]    topOfMainStack  Main Stack Pointer value to set

+ */

+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)

+{

+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );

+}

+

+

+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

+/**

+  \brief   Set Main Stack Pointer (non-secure)

+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.

+  \param [in]    topOfMainStack  Main Stack Pointer value to set

+ */

+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)

+{

+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );

+}

+#endif

+

+

+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

+/**

+  \brief   Get Stack Pointer (non-secure)

+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.

+  \return               SP Register value

+ */

+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );

+  return(result);

+}

+

+

+/**

+  \brief   Set Stack Pointer (non-secure)

+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.

+  \param [in]    topOfStack  Stack Pointer value to set

+ */

+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)

+{

+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );

+}

+#endif

+

+

+/**

+  \brief   Get Priority Mask

+  \details Returns the current state of the priority mask bit from the Priority Mask Register.

+  \return               Priority Mask value

+ */

+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, primask" : "=r" (result) );

+  return(result);

+}

+

+

+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

+/**

+  \brief   Get Priority Mask (non-secure)

+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.

+  \return               Priority Mask value

+ */

+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );

+  return(result);

+}

+#endif

+

+

+/**

+  \brief   Set Priority Mask

+  \details Assigns the given value to the Priority Mask Register.

+  \param [in]    priMask  Priority Mask

+ */

+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)

+{

+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");

+}

+

+

+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

+/**

+  \brief   Set Priority Mask (non-secure)

+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.

+  \param [in]    priMask  Priority Mask

+ */

+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)

+{

+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");

+}

+#endif

+

+

+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \

+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \

+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )

+/**

+  \brief   Enable FIQ

+  \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.

+           Can only be executed in Privileged modes.

+ */

+__STATIC_FORCEINLINE void __enable_fault_irq(void)

+{

+  __ASM volatile ("cpsie f" : : : "memory");

+}

+

+

+/**

+  \brief   Disable FIQ

+  \details Disables FIQ interrupts by setting special-purpose register FAULTMASK.

+           Can only be executed in Privileged modes.

+ */

+__STATIC_FORCEINLINE void __disable_fault_irq(void)

+{

+  __ASM volatile ("cpsid f" : : : "memory");

+}

+

+

+/**

+  \brief   Get Base Priority

+  \details Returns the current value of the Base Priority register.

+  \return               Base Priority register value

+ */

+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );

+  return(result);

+}

+

+

+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

+/**

+  \brief   Get Base Priority (non-secure)

+  \details Returns the current value of the non-secure Base Priority register when in secure state.

+  \return               Base Priority register value

+ */

+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );

+  return(result);

+}

+#endif

+

+

+/**

+  \brief   Set Base Priority

+  \details Assigns the given value to the Base Priority register.

+  \param [in]    basePri  Base Priority value to set

+ */

+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)

+{

+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");

+}

+

+

+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

+/**

+  \brief   Set Base Priority (non-secure)

+  \details Assigns the given value to the non-secure Base Priority register when in secure state.

+  \param [in]    basePri  Base Priority value to set

+ */

+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)

+{

+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");

+}

+#endif

+

+

+/**

+  \brief   Set Base Priority with condition

+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,

+           or the new value increases the BASEPRI priority level.

+  \param [in]    basePri  Base Priority value to set

+ */

+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)

+{

+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");

+}

+

+

+/**

+  \brief   Get Fault Mask

+  \details Returns the current value of the Fault Mask register.

+  \return               Fault Mask register value

+ */

+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );

+  return(result);

+}

+

+

+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

+/**

+  \brief   Get Fault Mask (non-secure)

+  \details Returns the current value of the non-secure Fault Mask register when in secure state.

+  \return               Fault Mask register value

+ */

+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );

+  return(result);

+}

+#endif

+

+

+/**

+  \brief   Set Fault Mask

+  \details Assigns the given value to the Fault Mask register.

+  \param [in]    faultMask  Fault Mask value to set

+ */

+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)

+{

+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");

+}

+

+

+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

+/**

+  \brief   Set Fault Mask (non-secure)

+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.

+  \param [in]    faultMask  Fault Mask value to set

+ */

+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)

+{

+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");

+}

+#endif

+

+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \

+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \

+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */

+

+

+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \

+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )

+

+/**

+  \brief   Get Process Stack Pointer Limit

+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure

+  Stack Pointer Limit register hence zero is returned always in non-secure

+  mode.

+

+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).

+  \return               PSPLIM Register value

+ */

+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)

+{

+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \

+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))

+    // without main extensions, the non-secure PSPLIM is RAZ/WI

+  return 0U;

+#else

+  uint32_t result;

+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );

+  return result;

+#endif

+}

+

+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))

+/**

+  \brief   Get Process Stack Pointer Limit (non-secure)

+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure

+  Stack Pointer Limit register hence zero is returned always.

+

+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.

+  \return               PSPLIM Register value

+ */

+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)

+{

+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))

+  // without main extensions, the non-secure PSPLIM is RAZ/WI

+  return 0U;

+#else

+  uint32_t result;

+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );

+  return result;

+#endif

+}

+#endif

+

+

+/**

+  \brief   Set Process Stack Pointer Limit

+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure

+  Stack Pointer Limit register hence the write is silently ignored in non-secure

+  mode.

+

+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).

+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set

+ */

+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)

+{

+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \

+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))

+  // without main extensions, the non-secure PSPLIM is RAZ/WI

+  (void)ProcStackPtrLimit;

+#else

+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));

+#endif

+}

+

+

+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))

+/**

+  \brief   Set Process Stack Pointer (non-secure)

+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure

+  Stack Pointer Limit register hence the write is silently ignored.

+

+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.

+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set

+ */

+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)

+{

+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))

+  // without main extensions, the non-secure PSPLIM is RAZ/WI

+  (void)ProcStackPtrLimit;

+#else

+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));

+#endif

+}

+#endif

+

+

+/**

+  \brief   Get Main Stack Pointer Limit

+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure

+  Stack Pointer Limit register hence zero is returned always in non-secure

+  mode.

+

+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).

+  \return               MSPLIM Register value

+ */

+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)

+{

+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \

+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))

+  // without main extensions, the non-secure MSPLIM is RAZ/WI

+  return 0U;

+#else

+  uint32_t result;

+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );

+  return result;

+#endif

+}

+

+

+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))

+/**

+  \brief   Get Main Stack Pointer Limit (non-secure)

+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure

+  Stack Pointer Limit register hence zero is returned always.

+

+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.

+  \return               MSPLIM Register value

+ */

+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)

+{

+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))

+  // without main extensions, the non-secure MSPLIM is RAZ/WI

+  return 0U;

+#else

+  uint32_t result;

+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );

+  return result;

+#endif

+}

+#endif

+

+

+/**

+  \brief   Set Main Stack Pointer Limit

+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure

+  Stack Pointer Limit register hence the write is silently ignored in non-secure

+  mode.

+

+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).

+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set

+ */

+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)

+{

+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \

+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))

+  // without main extensions, the non-secure MSPLIM is RAZ/WI

+  (void)MainStackPtrLimit;

+#else

+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));

+#endif

+}

+

+

+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))

+/**

+  \brief   Set Main Stack Pointer Limit (non-secure)

+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure

+  Stack Pointer Limit register hence the write is silently ignored.

+

+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.

+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set

+ */

+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)

+{

+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))

+  // without main extensions, the non-secure MSPLIM is RAZ/WI

+  (void)MainStackPtrLimit;

+#else

+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));

+#endif

+}

+#endif

+

+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \

+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */

+

+

+/**

+  \brief   Get FPSCR

+  \details Returns the current value of the Floating Point Status/Control register.

+  \return               Floating Point Status/Control register value

+ */

+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)

+{

+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \

+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )

+#if __has_builtin(__builtin_arm_get_fpscr)

+// Re-enable using built-in when GCC has been fixed

+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)

+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */

+  return __builtin_arm_get_fpscr();

+#else

+  uint32_t result;

+

+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );

+  return(result);

+#endif

+#else

+  return(0U);

+#endif

+}

+

+

+/**

+  \brief   Set FPSCR

+  \details Assigns the given value to the Floating Point Status/Control register.

+  \param [in]    fpscr  Floating Point Status/Control value to set

+ */

+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)

+{

+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \

+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )

+#if __has_builtin(__builtin_arm_set_fpscr)

+// Re-enable using built-in when GCC has been fixed

+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)

+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */

+  __builtin_arm_set_fpscr(fpscr);

+#else

+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");

+#endif

+#else

+  (void)fpscr;

+#endif

+}

+

+

+/*@} end of CMSIS_Core_RegAccFunctions */

+

+

 /* ###################  Compiler specific Intrinsics  ########################### */

 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics

   Access to dedicated SIMD instructions

@@ -1630,7 +1652,7 @@ __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
 {

   uint32_t result;

 

-  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

   return(result);

 }

 

@@ -1638,7 +1660,7 @@ __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
 {

   uint32_t result;

 

-  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

   return(result);

 }

 

@@ -1654,7 +1676,7 @@ __STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
 {

   uint32_t result;

 

-  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

   return(result);

 }

 

@@ -1662,7 +1684,7 @@ __STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
 {

   uint32_t result;

 

-  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

   return(result);

 }

 

@@ -1679,7 +1701,7 @@ __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
 {

   uint32_t result;

 

-  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

   return(result);

 }

 

@@ -1687,7 +1709,7 @@ __STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
 {

   uint32_t result;

 

-  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

   return(result);

 }

 

@@ -1703,7 +1725,7 @@ __STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
 {

   uint32_t result;

 

-  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

   return(result);

 }

 

@@ -1711,7 +1733,7 @@ __STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
 {

   uint32_t result;

 

-  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

   return(result);

 }

 

@@ -1728,7 +1750,7 @@ __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
 {

   uint32_t result;

 

-  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

   return(result);

 }

 

@@ -1736,7 +1758,7 @@ __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
 {

   uint32_t result;

 

-  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

   return(result);

 }

 

@@ -1752,7 +1774,7 @@ __STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
 {

   uint32_t result;

 

-  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

   return(result);

 }

 

@@ -1760,7 +1782,7 @@ __STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
 {

   uint32_t result;

 

-  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

   return(result);

 }

 

@@ -1776,7 +1798,7 @@ __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
 {

   uint32_t result;

 

-  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

   return(result);

 }

 

@@ -1784,7 +1806,7 @@ __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
 {

   uint32_t result;

 

-  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

   return(result);

 }

 

@@ -1800,7 +1822,7 @@ __STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
 {

   uint32_t result;

 

-  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

   return(result);

 }

 

@@ -1808,7 +1830,7 @@ __STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
 {

   uint32_t result;

 

-  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

   return(result);

 }

 

@@ -1824,7 +1846,7 @@ __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
 {

   uint32_t result;

 

-  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

   return(result);

 }

 

@@ -1832,7 +1854,7 @@ __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
 {

   uint32_t result;

 

-  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

   return(result);

 }

 

@@ -1848,7 +1870,7 @@ __STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
 {

   uint32_t result;

 

-  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

   return(result);

 }

 

@@ -1856,7 +1878,7 @@ __STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
 {

   uint32_t result;

 

-  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

   return(result);

 }

 

@@ -1872,7 +1894,7 @@ __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
 {

   uint32_t result;

 

-  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

   return(result);

 }

 

@@ -1880,7 +1902,7 @@ __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
 {

   uint32_t result;

 

-  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

   return(result);

 }

 

@@ -1896,7 +1918,7 @@ __STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
 {

   uint32_t result;

 

-  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

   return(result);

 }

 

@@ -1904,7 +1926,7 @@ __STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
 {

   uint32_t result;

 

-  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

   return(result);

 }

 

@@ -1912,7 +1934,7 @@ __STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
 {

   uint32_t result;

 

-  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

   return(result);

 }

 

@@ -1920,21 +1942,23 @@ __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
 {

   uint32_t result;

 

-  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

+  __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

   return(result);

 }

 

-#define __SSAT16(ARG1,ARG2) \

+#define __SSAT16(ARG1, ARG2) \

+__extension__ \

 ({                          \

   int32_t __RES, __ARG1 = (ARG1); \

-  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \

+  __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \

   __RES; \

  })

 

-#define __USAT16(ARG1,ARG2) \

+#define __USAT16(ARG1, ARG2) \

+__extension__ \

 ({                          \

   uint32_t __RES, __ARG1 = (ARG1); \

-  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \

+  __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \

   __RES; \

  })

 

@@ -1942,7 +1966,7 @@ __STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
 {

   uint32_t result;

 

-  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));

+  __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));

   return(result);

 }

 

@@ -1950,7 +1974,7 @@ __STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
 {

   uint32_t result;

 

-  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

   return(result);

 }

 

@@ -1958,18 +1982,41 @@ __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
 {

   uint32_t result;

 

-  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));

+  __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));

   return(result);

 }

 

+__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate)

+{

+  uint32_t result;

+  if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) {

+    __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) );

+  } else {

+    result = __SXTB16(__ROR(op1, rotate)) ;

+  }

+  return result;

+}

+

 __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)

 {

   uint32_t result;

 

-  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

   return(result);

 }

 

+__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate)

+{

+  uint32_t result;

+  if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) {

+    __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate));

+  } else {

+    result = __SXTAB16(op1, __ROR(op2, rotate));

+  }

+  return result;

+}

+

+

 __STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)

 {

   uint32_t result;

@@ -2126,8 +2173,9 @@ __STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
   return(result);

 }

 

-#if 0

+

 #define __PKHBT(ARG1,ARG2,ARG3) \

+__extension__ \

 ({                          \

   uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \

   __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \

@@ -2135,6 +2183,7 @@ __STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
  })

 

 #define __PKHTB(ARG1,ARG2,ARG3) \

+__extension__ \

 ({                          \

   uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \

   if (ARG3 == 0) \

@@ -2143,19 +2192,13 @@ __STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
     __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \

   __RES; \

  })

-#endif

-

-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \

-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )

 

-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \

-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )

 

 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)

 {

  int32_t result;

 

- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );

+ __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );

  return(result);

 }

 

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_iccarm.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_iccarm.h
deleted file mode 100644
index 7af75628a..000000000
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_iccarm.h
+++ /dev/null
@@ -1,964 +0,0 @@
-/**************************************************************************//**

- * @file     cmsis_iccarm.h

- * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file

- * @version  V5.1.0

- * @date     08. May 2019

- ******************************************************************************/

-

-//------------------------------------------------------------------------------

-//

-// Copyright (c) 2017-2019 IAR Systems

-// Copyright (c) 2017-2019 Arm Limited. All rights reserved. 

-//

-// Licensed under the Apache License, Version 2.0 (the "License")

-// you may not use this file except in compliance with the License.

-// You may obtain a copy of the License at

-//     http://www.apache.org/licenses/LICENSE-2.0

-//

-// Unless required by applicable law or agreed to in writing, software

-// distributed under the License is distributed on an "AS IS" BASIS,

-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

-// See the License for the specific language governing permissions and

-// limitations under the License.

-//

-//------------------------------------------------------------------------------

-

-

-#ifndef __CMSIS_ICCARM_H__

-#define __CMSIS_ICCARM_H__

-

-#ifndef __ICCARM__

-  #error This file should only be compiled by ICCARM

-#endif

-

-#pragma system_include

-

-#define __IAR_FT _Pragma("inline=forced") __intrinsic

-

-#if (__VER__ >= 8000000)

-  #define __ICCARM_V8 1

-#else

-  #define __ICCARM_V8 0

-#endif

-

-#ifndef __ALIGNED

-  #if __ICCARM_V8

-    #define __ALIGNED(x) __attribute__((aligned(x)))

-  #elif (__VER__ >= 7080000)

-    /* Needs IAR language extensions */

-    #define __ALIGNED(x) __attribute__((aligned(x)))

-  #else

-    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.

-    #define __ALIGNED(x)

-  #endif

-#endif

-

-

-/* Define compiler macros for CPU architecture, used in CMSIS 5.

- */

-#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__

-/* Macros already defined */

-#else

-  #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)

-    #define __ARM_ARCH_8M_MAIN__ 1

-  #elif defined(__ARM8M_BASELINE__)

-    #define __ARM_ARCH_8M_BASE__ 1

-  #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'

-    #if __ARM_ARCH == 6

-      #define __ARM_ARCH_6M__ 1

-    #elif __ARM_ARCH == 7

-      #if __ARM_FEATURE_DSP

-        #define __ARM_ARCH_7EM__ 1

-      #else

-        #define __ARM_ARCH_7M__ 1

-      #endif

-    #endif /* __ARM_ARCH */

-  #endif /* __ARM_ARCH_PROFILE == 'M' */

-#endif

-

-/* Alternativ core deduction for older ICCARM's */

-#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \

-    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)

-  #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)

-    #define __ARM_ARCH_6M__ 1

-  #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)

-    #define __ARM_ARCH_7M__ 1

-  #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)

-    #define __ARM_ARCH_7EM__  1

-  #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)

-    #define __ARM_ARCH_8M_BASE__ 1

-  #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)

-    #define __ARM_ARCH_8M_MAIN__ 1

-  #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)

-    #define __ARM_ARCH_8M_MAIN__ 1

-  #else

-    #error "Unknown target."

-  #endif

-#endif

-

-

-

-#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1

-  #define __IAR_M0_FAMILY  1

-#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1

-  #define __IAR_M0_FAMILY  1

-#else

-  #define __IAR_M0_FAMILY  0

-#endif

-

-

-#ifndef __ASM

-  #define __ASM __asm

-#endif

-

-#ifndef   __COMPILER_BARRIER

-  #define __COMPILER_BARRIER() __ASM volatile("":::"memory")

-#endif

-

-#ifndef __INLINE

-  #define __INLINE inline

-#endif

-

-#ifndef   __NO_RETURN

-  #if __ICCARM_V8

-    #define __NO_RETURN __attribute__((__noreturn__))

-  #else

-    #define __NO_RETURN _Pragma("object_attribute=__noreturn")

-  #endif

-#endif

-

-#ifndef   __PACKED

-  #if __ICCARM_V8

-    #define __PACKED __attribute__((packed, aligned(1)))

-  #else

-    /* Needs IAR language extensions */

-    #define __PACKED __packed

-  #endif

-#endif

-

-#ifndef   __PACKED_STRUCT

-  #if __ICCARM_V8

-    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))

-  #else

-    /* Needs IAR language extensions */

-    #define __PACKED_STRUCT __packed struct

-  #endif

-#endif

-

-#ifndef   __PACKED_UNION

-  #if __ICCARM_V8

-    #define __PACKED_UNION union __attribute__((packed, aligned(1)))

-  #else

-    /* Needs IAR language extensions */

-    #define __PACKED_UNION __packed union

-  #endif

-#endif

-

-#ifndef   __RESTRICT

-  #if __ICCARM_V8

-    #define __RESTRICT            __restrict

-  #else

-    /* Needs IAR language extensions */

-    #define __RESTRICT            restrict

-  #endif

-#endif

-

-#ifndef   __STATIC_INLINE

-  #define __STATIC_INLINE       static inline

-#endif

-

-#ifndef   __FORCEINLINE

-  #define __FORCEINLINE         _Pragma("inline=forced")

-#endif

-

-#ifndef   __STATIC_FORCEINLINE

-  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE

-#endif

-

-#ifndef __UNALIGNED_UINT16_READ

-#pragma language=save

-#pragma language=extended

-__IAR_FT uint16_t __iar_uint16_read(void const *ptr)

-{

-  return *(__packed uint16_t*)(ptr);

-}

-#pragma language=restore

-#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)

-#endif

-

-

-#ifndef __UNALIGNED_UINT16_WRITE

-#pragma language=save

-#pragma language=extended

-__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)

-{

-  *(__packed uint16_t*)(ptr) = val;;

-}

-#pragma language=restore

-#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)

-#endif

-

-#ifndef __UNALIGNED_UINT32_READ

-#pragma language=save

-#pragma language=extended

-__IAR_FT uint32_t __iar_uint32_read(void const *ptr)

-{

-  return *(__packed uint32_t*)(ptr);

-}

-#pragma language=restore

-#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)

-#endif

-

-#ifndef __UNALIGNED_UINT32_WRITE

-#pragma language=save

-#pragma language=extended

-__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)

-{

-  *(__packed uint32_t*)(ptr) = val;;

-}

-#pragma language=restore

-#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)

-#endif

-

-#ifndef __UNALIGNED_UINT32   /* deprecated */

-#pragma language=save

-#pragma language=extended

-__packed struct  __iar_u32 { uint32_t v; };

-#pragma language=restore

-#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)

-#endif

-

-#ifndef   __USED

-  #if __ICCARM_V8

-    #define __USED __attribute__((used))

-  #else

-    #define __USED _Pragma("__root")

-  #endif

-#endif

-

-#ifndef   __WEAK

-  #if __ICCARM_V8

-    #define __WEAK __attribute__((weak))

-  #else

-    #define __WEAK _Pragma("__weak")

-  #endif

-#endif

-

-#ifndef __PROGRAM_START

-#define __PROGRAM_START           __iar_program_start

-#endif

-

-#ifndef __INITIAL_SP

-#define __INITIAL_SP              CSTACK$$Limit

-#endif

-

-#ifndef __STACK_LIMIT

-#define __STACK_LIMIT             CSTACK$$Base

-#endif

-

-#ifndef __VECTOR_TABLE

-#define __VECTOR_TABLE            __vector_table

-#endif

-

-#ifndef __VECTOR_TABLE_ATTRIBUTE

-#define __VECTOR_TABLE_ATTRIBUTE  @".intvec"

-#endif

-

-#ifndef __ICCARM_INTRINSICS_VERSION__

-  #define __ICCARM_INTRINSICS_VERSION__  0

-#endif

-

-#if __ICCARM_INTRINSICS_VERSION__ == 2

-

-  #if defined(__CLZ)

-    #undef __CLZ

-  #endif

-  #if defined(__REVSH)

-    #undef __REVSH

-  #endif

-  #if defined(__RBIT)

-    #undef __RBIT

-  #endif

-  #if defined(__SSAT)

-    #undef __SSAT

-  #endif

-  #if defined(__USAT)

-    #undef __USAT

-  #endif

-

-  #include "iccarm_builtin.h"

-

-  #define __disable_fault_irq __iar_builtin_disable_fiq

-  #define __disable_irq       __iar_builtin_disable_interrupt

-  #define __enable_fault_irq  __iar_builtin_enable_fiq

-  #define __enable_irq        __iar_builtin_enable_interrupt

-  #define __arm_rsr           __iar_builtin_rsr

-  #define __arm_wsr           __iar_builtin_wsr

-

-

-  #define __get_APSR()                (__arm_rsr("APSR"))

-  #define __get_BASEPRI()             (__arm_rsr("BASEPRI"))

-  #define __get_CONTROL()             (__arm_rsr("CONTROL"))

-  #define __get_FAULTMASK()           (__arm_rsr("FAULTMASK"))

-

-  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \

-       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )

-    #define __get_FPSCR()             (__arm_rsr("FPSCR"))

-    #define __set_FPSCR(VALUE)        (__arm_wsr("FPSCR", (VALUE)))

-  #else

-    #define __get_FPSCR()             ( 0 )

-    #define __set_FPSCR(VALUE)        ((void)VALUE)

-  #endif

-

-  #define __get_IPSR()                (__arm_rsr("IPSR"))

-  #define __get_MSP()                 (__arm_rsr("MSP"))

-  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \

-       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))

-    // without main extensions, the non-secure MSPLIM is RAZ/WI

-    #define __get_MSPLIM()            (0U)

-  #else

-    #define __get_MSPLIM()            (__arm_rsr("MSPLIM"))

-  #endif

-  #define __get_PRIMASK()             (__arm_rsr("PRIMASK"))

-  #define __get_PSP()                 (__arm_rsr("PSP"))

-

-  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \

-       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))

-    // without main extensions, the non-secure PSPLIM is RAZ/WI

-    #define __get_PSPLIM()            (0U)

-  #else

-    #define __get_PSPLIM()            (__arm_rsr("PSPLIM"))

-  #endif

-

-  #define __get_xPSR()                (__arm_rsr("xPSR"))

-

-  #define __set_BASEPRI(VALUE)        (__arm_wsr("BASEPRI", (VALUE)))

-  #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr("BASEPRI_MAX", (VALUE)))

-  #define __set_CONTROL(VALUE)        (__arm_wsr("CONTROL", (VALUE)))

-  #define __set_FAULTMASK(VALUE)      (__arm_wsr("FAULTMASK", (VALUE)))

-  #define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))

-

-  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \

-       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))

-    // without main extensions, the non-secure MSPLIM is RAZ/WI

-    #define __set_MSPLIM(VALUE)       ((void)(VALUE))

-  #else

-    #define __set_MSPLIM(VALUE)       (__arm_wsr("MSPLIM", (VALUE)))

-  #endif

-  #define __set_PRIMASK(VALUE)        (__arm_wsr("PRIMASK", (VALUE)))

-  #define __set_PSP(VALUE)            (__arm_wsr("PSP", (VALUE)))

-  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \

-       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))

-    // without main extensions, the non-secure PSPLIM is RAZ/WI

-    #define __set_PSPLIM(VALUE)       ((void)(VALUE))

-  #else

-    #define __set_PSPLIM(VALUE)       (__arm_wsr("PSPLIM", (VALUE)))

-  #endif

-

-  #define __TZ_get_CONTROL_NS()       (__arm_rsr("CONTROL_NS"))

-  #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr("CONTROL_NS", (VALUE)))

-  #define __TZ_get_PSP_NS()           (__arm_rsr("PSP_NS"))

-  #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr("PSP_NS", (VALUE)))

-  #define __TZ_get_MSP_NS()           (__arm_rsr("MSP_NS"))

-  #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr("MSP_NS", (VALUE)))

-  #define __TZ_get_SP_NS()            (__arm_rsr("SP_NS"))

-  #define __TZ_set_SP_NS(VALUE)       (__arm_wsr("SP_NS", (VALUE)))

-  #define __TZ_get_PRIMASK_NS()       (__arm_rsr("PRIMASK_NS"))

-  #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr("PRIMASK_NS", (VALUE)))

-  #define __TZ_get_BASEPRI_NS()       (__arm_rsr("BASEPRI_NS"))

-  #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))

-  #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))

-  #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))

-

-  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \

-       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))

-    // without main extensions, the non-secure PSPLIM is RAZ/WI

-    #define __TZ_get_PSPLIM_NS()      (0U)

-    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))

-  #else

-    #define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))

-    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))

-  #endif

-

-  #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))

-  #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))

-

-  #define __NOP     __iar_builtin_no_operation

-

-  #define __CLZ     __iar_builtin_CLZ

-  #define __CLREX   __iar_builtin_CLREX

-

-  #define __DMB     __iar_builtin_DMB

-  #define __DSB     __iar_builtin_DSB

-  #define __ISB     __iar_builtin_ISB

-

-  #define __LDREXB  __iar_builtin_LDREXB

-  #define __LDREXH  __iar_builtin_LDREXH

-  #define __LDREXW  __iar_builtin_LDREX

-

-  #define __RBIT    __iar_builtin_RBIT

-  #define __REV     __iar_builtin_REV

-  #define __REV16   __iar_builtin_REV16

-

-  __IAR_FT int16_t __REVSH(int16_t val)

-  {

-    return (int16_t) __iar_builtin_REVSH(val);

-  }

-

-  #define __ROR     __iar_builtin_ROR

-  #define __RRX     __iar_builtin_RRX

-

-  #define __SEV     __iar_builtin_SEV

-

-  #if !__IAR_M0_FAMILY

-    #define __SSAT    __iar_builtin_SSAT

-  #endif

-

-  #define __STREXB  __iar_builtin_STREXB

-  #define __STREXH  __iar_builtin_STREXH

-  #define __STREXW  __iar_builtin_STREX

-

-  #if !__IAR_M0_FAMILY

-    #define __USAT    __iar_builtin_USAT

-  #endif

-

-  #define __WFE     __iar_builtin_WFE

-  #define __WFI     __iar_builtin_WFI

-

-  #if __ARM_MEDIA__

-    #define __SADD8   __iar_builtin_SADD8

-    #define __QADD8   __iar_builtin_QADD8

-    #define __SHADD8  __iar_builtin_SHADD8

-    #define __UADD8   __iar_builtin_UADD8

-    #define __UQADD8  __iar_builtin_UQADD8

-    #define __UHADD8  __iar_builtin_UHADD8

-    #define __SSUB8   __iar_builtin_SSUB8

-    #define __QSUB8   __iar_builtin_QSUB8

-    #define __SHSUB8  __iar_builtin_SHSUB8

-    #define __USUB8   __iar_builtin_USUB8

-    #define __UQSUB8  __iar_builtin_UQSUB8

-    #define __UHSUB8  __iar_builtin_UHSUB8

-    #define __SADD16  __iar_builtin_SADD16

-    #define __QADD16  __iar_builtin_QADD16

-    #define __SHADD16 __iar_builtin_SHADD16

-    #define __UADD16  __iar_builtin_UADD16

-    #define __UQADD16 __iar_builtin_UQADD16

-    #define __UHADD16 __iar_builtin_UHADD16

-    #define __SSUB16  __iar_builtin_SSUB16

-    #define __QSUB16  __iar_builtin_QSUB16

-    #define __SHSUB16 __iar_builtin_SHSUB16

-    #define __USUB16  __iar_builtin_USUB16

-    #define __UQSUB16 __iar_builtin_UQSUB16

-    #define __UHSUB16 __iar_builtin_UHSUB16

-    #define __SASX    __iar_builtin_SASX

-    #define __QASX    __iar_builtin_QASX

-    #define __SHASX   __iar_builtin_SHASX

-    #define __UASX    __iar_builtin_UASX

-    #define __UQASX   __iar_builtin_UQASX

-    #define __UHASX   __iar_builtin_UHASX

-    #define __SSAX    __iar_builtin_SSAX

-    #define __QSAX    __iar_builtin_QSAX

-    #define __SHSAX   __iar_builtin_SHSAX

-    #define __USAX    __iar_builtin_USAX

-    #define __UQSAX   __iar_builtin_UQSAX

-    #define __UHSAX   __iar_builtin_UHSAX

-    #define __USAD8   __iar_builtin_USAD8

-    #define __USADA8  __iar_builtin_USADA8

-    #define __SSAT16  __iar_builtin_SSAT16

-    #define __USAT16  __iar_builtin_USAT16

-    #define __UXTB16  __iar_builtin_UXTB16

-    #define __UXTAB16 __iar_builtin_UXTAB16

-    #define __SXTB16  __iar_builtin_SXTB16

-    #define __SXTAB16 __iar_builtin_SXTAB16

-    #define __SMUAD   __iar_builtin_SMUAD

-    #define __SMUADX  __iar_builtin_SMUADX

-    #define __SMMLA   __iar_builtin_SMMLA

-    #define __SMLAD   __iar_builtin_SMLAD

-    #define __SMLADX  __iar_builtin_SMLADX

-    #define __SMLALD  __iar_builtin_SMLALD

-    #define __SMLALDX __iar_builtin_SMLALDX

-    #define __SMUSD   __iar_builtin_SMUSD

-    #define __SMUSDX  __iar_builtin_SMUSDX

-    #define __SMLSD   __iar_builtin_SMLSD

-    #define __SMLSDX  __iar_builtin_SMLSDX

-    #define __SMLSLD  __iar_builtin_SMLSLD

-    #define __SMLSLDX __iar_builtin_SMLSLDX

-    #define __SEL     __iar_builtin_SEL

-    #define __QADD    __iar_builtin_QADD

-    #define __QSUB    __iar_builtin_QSUB

-    #define __PKHBT   __iar_builtin_PKHBT

-    #define __PKHTB   __iar_builtin_PKHTB

-  #endif

-

-#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */

-

-  #if __IAR_M0_FAMILY

-   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */

-    #define __CLZ  __cmsis_iar_clz_not_active

-    #define __SSAT __cmsis_iar_ssat_not_active

-    #define __USAT __cmsis_iar_usat_not_active

-    #define __RBIT __cmsis_iar_rbit_not_active

-    #define __get_APSR  __cmsis_iar_get_APSR_not_active

-  #endif

-

-

-  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \

-         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))

-    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active

-    #define __set_FPSCR __cmsis_iar_set_FPSR_not_active

-  #endif

-

-  #ifdef __INTRINSICS_INCLUDED

-  #error intrinsics.h is already included previously!

-  #endif

-

-  #include <intrinsics.h>

-

-  #if __IAR_M0_FAMILY

-   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */

-    #undef __CLZ

-    #undef __SSAT

-    #undef __USAT

-    #undef __RBIT

-    #undef __get_APSR

-

-    __STATIC_INLINE uint8_t __CLZ(uint32_t data)

-    {

-      if (data == 0U) { return 32U; }

-

-      uint32_t count = 0U;

-      uint32_t mask = 0x80000000U;

-

-      while ((data & mask) == 0U)

-      {

-        count += 1U;

-        mask = mask >> 1U;

-      }

-      return count;

-    }

-

-    __STATIC_INLINE uint32_t __RBIT(uint32_t v)

-    {

-      uint8_t sc = 31U;

-      uint32_t r = v;

-      for (v >>= 1U; v; v >>= 1U)

-      {

-        r <<= 1U;

-        r |= v & 1U;

-        sc--;

-      }

-      return (r << sc);

-    }

-

-    __STATIC_INLINE  uint32_t __get_APSR(void)

-    {

-      uint32_t res;

-      __asm("MRS      %0,APSR" : "=r" (res));

-      return res;

-    }

-

-  #endif

-

-  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \

-         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))

-    #undef __get_FPSCR

-    #undef __set_FPSCR

-    #define __get_FPSCR()       (0)

-    #define __set_FPSCR(VALUE)  ((void)VALUE)

-  #endif

-

-  #pragma diag_suppress=Pe940

-  #pragma diag_suppress=Pe177

-

-  #define __enable_irq    __enable_interrupt

-  #define __disable_irq   __disable_interrupt

-  #define __NOP           __no_operation

-

-  #define __get_xPSR      __get_PSR

-

-  #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)

-

-    __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)

-    {

-      return __LDREX((unsigned long *)ptr);

-    }

-

-    __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)

-    {

-      return __STREX(value, (unsigned long *)ptr);

-    }

-  #endif

-

-

-  /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */

-  #if (__CORTEX_M >= 0x03)

-

-    __IAR_FT uint32_t __RRX(uint32_t value)

-    {

-      uint32_t result;

-      __ASM("RRX      %0, %1" : "=r"(result) : "r" (value) : "cc");

-      return(result);

-    }

-

-    __IAR_FT void __set_BASEPRI_MAX(uint32_t value)

-    {

-      __asm volatile("MSR      BASEPRI_MAX,%0"::"r" (value));

-    }

-

-

-    #define __enable_fault_irq  __enable_fiq

-    #define __disable_fault_irq __disable_fiq

-

-

-  #endif /* (__CORTEX_M >= 0x03) */

-

-  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)

-  {

-    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));

-  }

-

-  #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \

-       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )

-

-   __IAR_FT uint32_t __get_MSPLIM(void)

-    {

-      uint32_t res;

-    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \

-         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))

-      // without main extensions, the non-secure MSPLIM is RAZ/WI

-      res = 0U;

-    #else

-      __asm volatile("MRS      %0,MSPLIM" : "=r" (res));

-    #endif

-      return res;

-    }

-

-    __IAR_FT void   __set_MSPLIM(uint32_t value)

-    {

-    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \

-         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))

-      // without main extensions, the non-secure MSPLIM is RAZ/WI

-      (void)value;

-    #else

-      __asm volatile("MSR      MSPLIM,%0" :: "r" (value));

-    #endif

-    }

-

-    __IAR_FT uint32_t __get_PSPLIM(void)

-    {

-      uint32_t res;

-    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \

-         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))

-      // without main extensions, the non-secure PSPLIM is RAZ/WI

-      res = 0U;

-    #else

-      __asm volatile("MRS      %0,PSPLIM" : "=r" (res));

-    #endif

-      return res;

-    }

-

-    __IAR_FT void   __set_PSPLIM(uint32_t value)

-    {

-    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \

-         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))

-      // without main extensions, the non-secure PSPLIM is RAZ/WI

-      (void)value;

-    #else

-      __asm volatile("MSR      PSPLIM,%0" :: "r" (value));

-    #endif

-    }

-

-    __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)

-    {

-      uint32_t res;

-      __asm volatile("MRS      %0,CONTROL_NS" : "=r" (res));

-      return res;

-    }

-

-    __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)

-    {

-      __asm volatile("MSR      CONTROL_NS,%0" :: "r" (value));

-    }

-

-    __IAR_FT uint32_t   __TZ_get_PSP_NS(void)

-    {

-      uint32_t res;

-      __asm volatile("MRS      %0,PSP_NS" : "=r" (res));

-      return res;

-    }

-

-    __IAR_FT void   __TZ_set_PSP_NS(uint32_t value)

-    {

-      __asm volatile("MSR      PSP_NS,%0" :: "r" (value));

-    }

-

-    __IAR_FT uint32_t   __TZ_get_MSP_NS(void)

-    {

-      uint32_t res;

-      __asm volatile("MRS      %0,MSP_NS" : "=r" (res));

-      return res;

-    }

-

-    __IAR_FT void   __TZ_set_MSP_NS(uint32_t value)

-    {

-      __asm volatile("MSR      MSP_NS,%0" :: "r" (value));

-    }

-

-    __IAR_FT uint32_t   __TZ_get_SP_NS(void)

-    {

-      uint32_t res;

-      __asm volatile("MRS      %0,SP_NS" : "=r" (res));

-      return res;

-    }

-    __IAR_FT void   __TZ_set_SP_NS(uint32_t value)

-    {

-      __asm volatile("MSR      SP_NS,%0" :: "r" (value));

-    }

-

-    __IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)

-    {

-      uint32_t res;

-      __asm volatile("MRS      %0,PRIMASK_NS" : "=r" (res));

-      return res;

-    }

-

-    __IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)

-    {

-      __asm volatile("MSR      PRIMASK_NS,%0" :: "r" (value));

-    }

-

-    __IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)

-    {

-      uint32_t res;

-      __asm volatile("MRS      %0,BASEPRI_NS" : "=r" (res));

-      return res;

-    }

-

-    __IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)

-    {

-      __asm volatile("MSR      BASEPRI_NS,%0" :: "r" (value));

-    }

-

-    __IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)

-    {

-      uint32_t res;

-      __asm volatile("MRS      %0,FAULTMASK_NS" : "=r" (res));

-      return res;

-    }

-

-    __IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)

-    {

-      __asm volatile("MSR      FAULTMASK_NS,%0" :: "r" (value));

-    }

-

-    __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)

-    {

-      uint32_t res;

-    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \

-         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))

-      // without main extensions, the non-secure PSPLIM is RAZ/WI

-      res = 0U;

-    #else

-      __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));

-    #endif

-      return res;

-    }

-

-    __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)

-    {

-    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \

-         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))

-      // without main extensions, the non-secure PSPLIM is RAZ/WI

-      (void)value;

-    #else

-      __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));

-    #endif

-    }

-

-    __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)

-    {

-      uint32_t res;

-      __asm volatile("MRS      %0,MSPLIM_NS" : "=r" (res));

-      return res;

-    }

-

-    __IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)

-    {

-      __asm volatile("MSR      MSPLIM_NS,%0" :: "r" (value));

-    }

-

-  #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */

-

-#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */

-

-#define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))

-

-#if __IAR_M0_FAMILY

-  __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)

-  {

-    if ((sat >= 1U) && (sat <= 32U))

-    {

-      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);

-      const int32_t min = -1 - max ;

-      if (val > max)

-      {

-        return max;

-      }

-      else if (val < min)

-      {

-        return min;

-      }

-    }

-    return val;

-  }

-

-  __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)

-  {

-    if (sat <= 31U)

-    {

-      const uint32_t max = ((1U << sat) - 1U);

-      if (val > (int32_t)max)

-      {

-        return max;

-      }

-      else if (val < 0)

-      {

-        return 0U;

-      }

-    }

-    return (uint32_t)val;

-  }

-#endif

-

-#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */

-

-  __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)

-  {

-    uint32_t res;

-    __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");

-    return ((uint8_t)res);

-  }

-

-  __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)

-  {

-    uint32_t res;

-    __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");

-    return ((uint16_t)res);

-  }

-

-  __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)

-  {

-    uint32_t res;

-    __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");

-    return res;

-  }

-

-  __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)

-  {

-    __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");

-  }

-

-  __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)

-  {

-    __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");

-  }

-

-  __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)

-  {

-    __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");

-  }

-

-#endif /* (__CORTEX_M >= 0x03) */

-

-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \

-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )

-

-

-  __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)

-  {

-    uint32_t res;

-    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");

-    return ((uint8_t)res);

-  }

-

-  __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)

-  {

-    uint32_t res;

-    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");

-    return ((uint16_t)res);

-  }

-

-  __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)

-  {

-    uint32_t res;

-    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");

-    return res;

-  }

-

-  __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)

-  {

-    __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");

-  }

-

-  __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)

-  {

-    __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");

-  }

-

-  __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)

-  {

-    __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");

-  }

-

-  __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)

-  {

-    uint32_t res;

-    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");

-    return ((uint8_t)res);

-  }

-

-  __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)

-  {

-    uint32_t res;

-    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");

-    return ((uint16_t)res);

-  }

-

-  __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)

-  {

-    uint32_t res;

-    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");

-    return res;

-  }

-

-  __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)

-  {

-    uint32_t res;

-    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");

-    return res;

-  }

-

-  __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)

-  {

-    uint32_t res;

-    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");

-    return res;

-  }

-

-  __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)

-  {

-    uint32_t res;

-    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");

-    return res;

-  }

-

-#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */

-

-#undef __IAR_FT

-#undef __IAR_M0_FAMILY

-#undef __ICCARM_V8

-

-#pragma diag_default=Pe940

-#pragma diag_default=Pe177

-

-#endif /* __CMSIS_ICCARM_H__ */

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_version.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_version.h
index 3174cf60b..a196dfd4e 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_version.h
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_version.h
@@ -1,8 +1,8 @@
 /**************************************************************************//**

  * @file     cmsis_version.h

  * @brief    CMSIS Core(M) Version definitions

- * @version  V5.0.3

- * @date     24. June 2019

+ * @version  V5.0.4

+ * @date     23. July 2019

  ******************************************************************************/

 /*

  * Copyright (c) 2009-2019 ARM Limited. All rights reserved.

@@ -33,7 +33,7 @@
 

 /*  CMSIS Version definitions */

 #define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */

-#define __CM_CMSIS_VERSION_SUB   ( 3U)                                      /*!< [15:0]  CMSIS Core(M) sub version */

+#define __CM_CMSIS_VERSION_SUB   ( 4U)                                      /*!< [15:0]  CMSIS Core(M) sub version */

 #define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \

                                    __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */

 #endif

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/core_cm33.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/core_cm33.h
index 2f1d98e21..4dbde81b4 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/core_cm33.h
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/core_cm33.h
@@ -1,11 +1,11 @@
 /**************************************************************************//**

  * @file     core_cm33.h

  * @brief    CMSIS Cortex-M33 Core Peripheral Access Layer Header File

- * @version  V5.1.0

- * @date     12. November 2018

+ * @version  V5.2.2

+ * @date     04. June 2021

  ******************************************************************************/

 /*

- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.

+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.

  *

  * SPDX-License-Identifier: Apache-2.0

  *

@@ -23,9 +23,11 @@
  */

 

 #if   defined ( __ICCARM__ )

-  #pragma system_include         /* treat file as system include file for MISRA check */

+  #pragma system_include                        /* treat file as system include file for MISRA check */

 #elif defined (__clang__)

-  #pragma clang system_header   /* treat file as system include file */

+  #pragma clang system_header                   /* treat file as system include file */

+#elif defined ( __GNUC__ )

+  #pragma GCC diagnostic ignored "-Wpedantic"   /* disable pedantic warning due to unnamed structs/unions */

 #endif

 

 #ifndef __CORE_CM33_H_GENERIC

@@ -248,6 +250,11 @@
     #warning "__DSP_PRESENT not defined in device header file; using default!"

   #endif

 

+  #ifndef __VTOR_PRESENT

+    #define __VTOR_PRESENT             1U

+    #warning "__VTOR_PRESENT not defined in device header file; using default!"

+  #endif

+

   #ifndef __NVIC_PRIO_BITS

     #define __NVIC_PRIO_BITS          3U

     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"

@@ -538,6 +545,7 @@ typedef struct
   __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */

   __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */

   __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */

+  __OM  uint32_t BPIALL;                 /*!< Offset: 0x278 ( /W)  Branch Predictor Invalidate All */

 } SCB_Type;

 

 /* SCB CPUID Register Definitions */

@@ -738,22 +746,22 @@ typedef struct
 #define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */

 

 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */

-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */

+#define SCB_CFSR_MMARVALID_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 7U)                 /*!< SCB CFSR (MMFSR): MMARVALID Position */

 #define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */

 

-#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */

+#define SCB_CFSR_MLSPERR_Pos               (SCB_CFSR_MEMFAULTSR_Pos + 5U)                 /*!< SCB CFSR (MMFSR): MLSPERR Position */

 #define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */

 

-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */

+#define SCB_CFSR_MSTKERR_Pos               (SCB_CFSR_MEMFAULTSR_Pos + 4U)                 /*!< SCB CFSR (MMFSR): MSTKERR Position */

 #define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */

 

-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */

+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 3U)                 /*!< SCB CFSR (MMFSR): MUNSTKERR Position */

 #define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */

 

-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */

+#define SCB_CFSR_DACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 1U)                 /*!< SCB CFSR (MMFSR): DACCVIOL Position */

 #define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */

 

-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */

+#define SCB_CFSR_IACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 0U)                 /*!< SCB CFSR (MMFSR): IACCVIOL Position */

 #define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */

 

 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */

@@ -1668,8 +1676,9 @@ typedef struct
   __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */

   __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */

   __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */

-  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */

-  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */

+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and VFP Feature Register 0 */

+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and VFP Feature Register 1 */

+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and VFP Feature Register 2 */

 } FPU_Type;

 

 /* Floating-Point Context Control Register Definitions */

@@ -1741,7 +1750,7 @@ typedef struct
 #define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */

 #define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */

 

-/* Media and FP Feature Register 0 Definitions */

+/* Media and VFP Feature Register 0 Definitions */

 #define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */

 #define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */

 

@@ -1766,7 +1775,7 @@ typedef struct
 #define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */

 #define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */

 

-/* Media and FP Feature Register 1 Definitions */

+/* Media and VFP Feature Register 1 Definitions */

 #define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */

 #define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */

 

@@ -1779,9 +1788,13 @@ typedef struct
 #define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */

 #define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */

 

-/*@} end of group CMSIS_FPU */

+/* Media and VFP Feature Register 2 Definitions */

+#define FPU_MVFR2_FPMisc_Pos                4U                                            /*!< MVFR2: FPMisc bits Position */

+#define FPU_MVFR2_FPMisc_Msk               (0xFUL << FPU_MVFR2_FPMisc_Pos)                /*!< MVFR2: FPMisc bits Mask */

 

+/*@} end of group CMSIS_FPU */

 

+/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */

 /**

   \ingroup  CMSIS_core_register

   \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)

@@ -1790,7 +1803,7 @@ typedef struct
  */

 

 /**

-  \brief  Structure type to access the Core Debug Register (CoreDebug).

+  \brief  \deprecated Structure type to access the Core Debug Register (CoreDebug).

  */

 typedef struct

 {

@@ -1798,126 +1811,356 @@ typedef struct
   __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */

   __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */

   __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */

-        uint32_t RESERVED4[1U];

+        uint32_t RESERVED0[1U];

   __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */

   __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */

 } CoreDebug_Type;

 

 /* Debug Halting Control and Status Register Definitions */

-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */

-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */

+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */

+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */

 

-#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */

-#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */

+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */

+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */

 

-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */

-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */

+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */

+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */

 

-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */

-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */

+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */

+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */

 

-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */

-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */

+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */

+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */

 

-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */

-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */

+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */

+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */

 

-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */

-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */

+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< \deprecated CoreDebug DHCSR: S_HALT Position */

+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */

 

-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */

-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */

+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */

+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */

 

-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */

-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */

+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */

+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */

 

-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */

-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */

+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */

+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */

 

-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */

-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */

+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< \deprecated CoreDebug DHCSR: C_STEP Position */

+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */

 

-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */

-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */

+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< \deprecated CoreDebug DHCSR: C_HALT Position */

+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */

 

-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */

-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */

+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */

+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */

 

 /* Debug Core Register Selector Register Definitions */

-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */

-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */

+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< \deprecated CoreDebug DCRSR: REGWnR Position */

+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */

 

-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */

-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */

+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< \deprecated CoreDebug DCRSR: REGSEL Position */

+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */

 

 /* Debug Exception and Monitor Control Register Definitions */

-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */

-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */

+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< \deprecated CoreDebug DEMCR: TRCENA Position */

+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */

 

-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */

-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */

+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */

+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */

 

-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */

-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */

+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */

+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */

 

-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */

-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */

+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */

+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */

 

-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */

-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */

+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< \deprecated CoreDebug DEMCR: MON_EN Position */

+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */

 

-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */

-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */

+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */

+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */

 

-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */

-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */

+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */

+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */

 

-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */

-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */

+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */

+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */

 

-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */

-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */

+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */

+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */

 

-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */

-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */

+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */

+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */

 

-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */

-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */

+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */

+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */

 

-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */

-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */

+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */

+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */

 

-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */

-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */

+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */

+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */

 

 /* Debug Authentication Control Register Definitions */

-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */

-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */

+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */

+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */

 

-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */

-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */

+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */

+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */

 

-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */

-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */

+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */

+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */

 

-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */

-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */

+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */

+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */

 

 /* Debug Security Control and Status Register Definitions */

-#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */

-#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */

+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< \deprecated CoreDebug DSCSR: CDS Position */

+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< \deprecated CoreDebug DSCSR: CDS Mask */

 

-#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */

-#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */

+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */

+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */

 

-#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */

-#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */

+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */

+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */

 

 /*@} end of group CMSIS_CoreDebug */

 

 

 /**

   \ingroup    CMSIS_core_register

+  \defgroup CMSIS_DCB       Debug Control Block

+  \brief    Type definitions for the Debug Control Block Registers

+  @{

+ */

+

+/**

+  \brief  Structure type to access the Debug Control Block Registers (DCB).

+ */

+typedef struct

+{

+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */

+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */

+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */

+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */

+        uint32_t RESERVED0[1U];

+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */

+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */

+} DCB_Type;

+

+/* DHCSR, Debug Halting Control and Status Register Definitions */

+#define DCB_DHCSR_DBGKEY_Pos               16U                                            /*!< DCB DHCSR: Debug key Position */

+#define DCB_DHCSR_DBGKEY_Msk               (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)             /*!< DCB DHCSR: Debug key Mask */

+

+#define DCB_DHCSR_S_RESTART_ST_Pos         26U                                            /*!< DCB DHCSR: Restart sticky status Position */

+#define DCB_DHCSR_S_RESTART_ST_Msk         (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)          /*!< DCB DHCSR: Restart sticky status Mask */

+

+#define DCB_DHCSR_S_RESET_ST_Pos           25U                                            /*!< DCB DHCSR: Reset sticky status Position */

+#define DCB_DHCSR_S_RESET_ST_Msk           (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)            /*!< DCB DHCSR: Reset sticky status Mask */

+

+#define DCB_DHCSR_S_RETIRE_ST_Pos          24U                                            /*!< DCB DHCSR: Retire sticky status Position */

+#define DCB_DHCSR_S_RETIRE_ST_Msk          (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)           /*!< DCB DHCSR: Retire sticky status Mask */

+

+#define DCB_DHCSR_S_SDE_Pos                20U                                            /*!< DCB DHCSR: Secure debug enabled Position */

+#define DCB_DHCSR_S_SDE_Msk                (0x1UL << DCB_DHCSR_S_SDE_Pos)                 /*!< DCB DHCSR: Secure debug enabled Mask */

+

+#define DCB_DHCSR_S_LOCKUP_Pos             19U                                            /*!< DCB DHCSR: Lockup status Position */

+#define DCB_DHCSR_S_LOCKUP_Msk             (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)              /*!< DCB DHCSR: Lockup status Mask */

+

+#define DCB_DHCSR_S_SLEEP_Pos              18U                                            /*!< DCB DHCSR: Sleeping status Position */

+#define DCB_DHCSR_S_SLEEP_Msk              (0x1UL << DCB_DHCSR_S_SLEEP_Pos)               /*!< DCB DHCSR: Sleeping status Mask */

+

+#define DCB_DHCSR_S_HALT_Pos               17U                                            /*!< DCB DHCSR: Halted status Position */

+#define DCB_DHCSR_S_HALT_Msk               (0x1UL << DCB_DHCSR_S_HALT_Pos)                /*!< DCB DHCSR: Halted status Mask */

+

+#define DCB_DHCSR_S_REGRDY_Pos             16U                                            /*!< DCB DHCSR: Register ready status Position */

+#define DCB_DHCSR_S_REGRDY_Msk             (0x1UL << DCB_DHCSR_S_REGRDY_Pos)              /*!< DCB DHCSR: Register ready status Mask */

+

+#define DCB_DHCSR_C_SNAPSTALL_Pos           5U                                            /*!< DCB DHCSR: Snap stall control Position */

+#define DCB_DHCSR_C_SNAPSTALL_Msk          (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)           /*!< DCB DHCSR: Snap stall control Mask */

+

+#define DCB_DHCSR_C_MASKINTS_Pos            3U                                            /*!< DCB DHCSR: Mask interrupts control Position */

+#define DCB_DHCSR_C_MASKINTS_Msk           (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)            /*!< DCB DHCSR: Mask interrupts control Mask */

+

+#define DCB_DHCSR_C_STEP_Pos                2U                                            /*!< DCB DHCSR: Step control Position */

+#define DCB_DHCSR_C_STEP_Msk               (0x1UL << DCB_DHCSR_C_STEP_Pos)                /*!< DCB DHCSR: Step control Mask */

+

+#define DCB_DHCSR_C_HALT_Pos                1U                                            /*!< DCB DHCSR: Halt control Position */

+#define DCB_DHCSR_C_HALT_Msk               (0x1UL << DCB_DHCSR_C_HALT_Pos)                /*!< DCB DHCSR: Halt control Mask */

+

+#define DCB_DHCSR_C_DEBUGEN_Pos             0U                                            /*!< DCB DHCSR: Debug enable control Position */

+#define DCB_DHCSR_C_DEBUGEN_Msk            (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)         /*!< DCB DHCSR: Debug enable control Mask */

+

+/* DCRSR, Debug Core Register Select Register Definitions */

+#define DCB_DCRSR_REGWnR_Pos               16U                                            /*!< DCB DCRSR: Register write/not-read Position */

+#define DCB_DCRSR_REGWnR_Msk               (0x1UL << DCB_DCRSR_REGWnR_Pos)                /*!< DCB DCRSR: Register write/not-read Mask */

+

+#define DCB_DCRSR_REGSEL_Pos                0U                                            /*!< DCB DCRSR: Register selector Position */

+#define DCB_DCRSR_REGSEL_Msk               (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)           /*!< DCB DCRSR: Register selector Mask */

+

+/* DCRDR, Debug Core Register Data Register Definitions */

+#define DCB_DCRDR_DBGTMP_Pos                0U                                            /*!< DCB DCRDR: Data temporary buffer Position */

+#define DCB_DCRDR_DBGTMP_Msk               (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)     /*!< DCB DCRDR: Data temporary buffer Mask */

+

+/* DEMCR, Debug Exception and Monitor Control Register Definitions */

+#define DCB_DEMCR_TRCENA_Pos               24U                                            /*!< DCB DEMCR: Trace enable Position */

+#define DCB_DEMCR_TRCENA_Msk               (0x1UL << DCB_DEMCR_TRCENA_Pos)                /*!< DCB DEMCR: Trace enable Mask */

+

+#define DCB_DEMCR_MONPRKEY_Pos             23U                                            /*!< DCB DEMCR: Monitor pend req key Position */

+#define DCB_DEMCR_MONPRKEY_Msk             (0x1UL << DCB_DEMCR_MONPRKEY_Pos)              /*!< DCB DEMCR: Monitor pend req key Mask */

+

+#define DCB_DEMCR_UMON_EN_Pos              21U                                            /*!< DCB DEMCR: Unprivileged monitor enable Position */

+#define DCB_DEMCR_UMON_EN_Msk              (0x1UL << DCB_DEMCR_UMON_EN_Pos)               /*!< DCB DEMCR: Unprivileged monitor enable Mask */

+

+#define DCB_DEMCR_SDME_Pos                 20U                                            /*!< DCB DEMCR: Secure DebugMonitor enable Position */

+#define DCB_DEMCR_SDME_Msk                 (0x1UL << DCB_DEMCR_SDME_Pos)                  /*!< DCB DEMCR: Secure DebugMonitor enable Mask */

+

+#define DCB_DEMCR_MON_REQ_Pos              19U                                            /*!< DCB DEMCR: Monitor request Position */

+#define DCB_DEMCR_MON_REQ_Msk              (0x1UL << DCB_DEMCR_MON_REQ_Pos)               /*!< DCB DEMCR: Monitor request Mask */

+

+#define DCB_DEMCR_MON_STEP_Pos             18U                                            /*!< DCB DEMCR: Monitor step Position */

+#define DCB_DEMCR_MON_STEP_Msk             (0x1UL << DCB_DEMCR_MON_STEP_Pos)              /*!< DCB DEMCR: Monitor step Mask */

+

+#define DCB_DEMCR_MON_PEND_Pos             17U                                            /*!< DCB DEMCR: Monitor pend Position */

+#define DCB_DEMCR_MON_PEND_Msk             (0x1UL << DCB_DEMCR_MON_PEND_Pos)              /*!< DCB DEMCR: Monitor pend Mask */

+

+#define DCB_DEMCR_MON_EN_Pos               16U                                            /*!< DCB DEMCR: Monitor enable Position */

+#define DCB_DEMCR_MON_EN_Msk               (0x1UL << DCB_DEMCR_MON_EN_Pos)                /*!< DCB DEMCR: Monitor enable Mask */

+

+#define DCB_DEMCR_VC_SFERR_Pos             11U                                            /*!< DCB DEMCR: Vector Catch SecureFault Position */

+#define DCB_DEMCR_VC_SFERR_Msk             (0x1UL << DCB_DEMCR_VC_SFERR_Pos)              /*!< DCB DEMCR: Vector Catch SecureFault Mask */

+

+#define DCB_DEMCR_VC_HARDERR_Pos           10U                                            /*!< DCB DEMCR: Vector Catch HardFault errors Position */

+#define DCB_DEMCR_VC_HARDERR_Msk           (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)            /*!< DCB DEMCR: Vector Catch HardFault errors Mask */

+

+#define DCB_DEMCR_VC_INTERR_Pos             9U                                            /*!< DCB DEMCR: Vector Catch interrupt errors Position */

+#define DCB_DEMCR_VC_INTERR_Msk            (0x1UL << DCB_DEMCR_VC_INTERR_Pos)             /*!< DCB DEMCR: Vector Catch interrupt errors Mask */

+

+#define DCB_DEMCR_VC_BUSERR_Pos             8U                                            /*!< DCB DEMCR: Vector Catch BusFault errors Position */

+#define DCB_DEMCR_VC_BUSERR_Msk            (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)             /*!< DCB DEMCR: Vector Catch BusFault errors Mask */

+

+#define DCB_DEMCR_VC_STATERR_Pos            7U                                            /*!< DCB DEMCR: Vector Catch state errors Position */

+#define DCB_DEMCR_VC_STATERR_Msk           (0x1UL << DCB_DEMCR_VC_STATERR_Pos)            /*!< DCB DEMCR: Vector Catch state errors Mask */

+

+#define DCB_DEMCR_VC_CHKERR_Pos             6U                                            /*!< DCB DEMCR: Vector Catch check errors Position */

+#define DCB_DEMCR_VC_CHKERR_Msk            (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)             /*!< DCB DEMCR: Vector Catch check errors Mask */

+

+#define DCB_DEMCR_VC_NOCPERR_Pos            5U                                            /*!< DCB DEMCR: Vector Catch NOCP errors Position */

+#define DCB_DEMCR_VC_NOCPERR_Msk           (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)            /*!< DCB DEMCR: Vector Catch NOCP errors Mask */

+

+#define DCB_DEMCR_VC_MMERR_Pos              4U                                            /*!< DCB DEMCR: Vector Catch MemManage errors Position */

+#define DCB_DEMCR_VC_MMERR_Msk             (0x1UL << DCB_DEMCR_VC_MMERR_Pos)              /*!< DCB DEMCR: Vector Catch MemManage errors Mask */

+

+#define DCB_DEMCR_VC_CORERESET_Pos          0U                                            /*!< DCB DEMCR: Vector Catch Core reset Position */

+#define DCB_DEMCR_VC_CORERESET_Msk         (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)      /*!< DCB DEMCR: Vector Catch Core reset Mask */

+

+/* DAUTHCTRL, Debug Authentication Control Register Definitions */

+#define DCB_DAUTHCTRL_INTSPNIDEN_Pos        3U                                            /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */

+#define DCB_DAUTHCTRL_INTSPNIDEN_Msk       (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)        /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */

+

+#define DCB_DAUTHCTRL_SPNIDENSEL_Pos        2U                                            /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */

+#define DCB_DAUTHCTRL_SPNIDENSEL_Msk       (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)        /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */

+

+#define DCB_DAUTHCTRL_INTSPIDEN_Pos         1U                                            /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */

+#define DCB_DAUTHCTRL_INTSPIDEN_Msk        (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)         /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */

+

+#define DCB_DAUTHCTRL_SPIDENSEL_Pos         0U                                            /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */

+#define DCB_DAUTHCTRL_SPIDENSEL_Msk        (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)     /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */

+

+/* DSCSR, Debug Security Control and Status Register Definitions */

+#define DCB_DSCSR_CDSKEY_Pos               17U                                            /*!< DCB DSCSR: CDS write-enable key Position */

+#define DCB_DSCSR_CDSKEY_Msk               (0x1UL << DCB_DSCSR_CDSKEY_Pos)                /*!< DCB DSCSR: CDS write-enable key Mask */

+

+#define DCB_DSCSR_CDS_Pos                  16U                                            /*!< DCB DSCSR: Current domain Secure Position */

+#define DCB_DSCSR_CDS_Msk                  (0x1UL << DCB_DSCSR_CDS_Pos)                   /*!< DCB DSCSR: Current domain Secure Mask */

+

+#define DCB_DSCSR_SBRSEL_Pos                1U                                            /*!< DCB DSCSR: Secure banked register select Position */

+#define DCB_DSCSR_SBRSEL_Msk               (0x1UL << DCB_DSCSR_SBRSEL_Pos)                /*!< DCB DSCSR: Secure banked register select Mask */

+

+#define DCB_DSCSR_SBRSELEN_Pos              0U                                            /*!< DCB DSCSR: Secure banked register select enable Position */

+#define DCB_DSCSR_SBRSELEN_Msk             (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)          /*!< DCB DSCSR: Secure banked register select enable Mask */

+

+/*@} end of group CMSIS_DCB */

+

+

+

+/**

+  \ingroup  CMSIS_core_register

+  \defgroup CMSIS_DIB       Debug Identification Block

+  \brief    Type definitions for the Debug Identification Block Registers

+  @{

+ */

+

+/**

+  \brief  Structure type to access the Debug Identification Block Registers (DIB).

+ */

+typedef struct

+{

+  __OM  uint32_t DLAR;                   /*!< Offset: 0x000 ( /W)  SCS Software Lock Access Register */

+  __IM  uint32_t DLSR;                   /*!< Offset: 0x004 (R/ )  SCS Software Lock Status Register */

+  __IM  uint32_t DAUTHSTATUS;            /*!< Offset: 0x008 (R/ )  Debug Authentication Status Register */

+  __IM  uint32_t DDEVARCH;               /*!< Offset: 0x00C (R/ )  SCS Device Architecture Register */

+  __IM  uint32_t DDEVTYPE;               /*!< Offset: 0x010 (R/ )  SCS Device Type Register */

+} DIB_Type;

+

+/* DLAR, SCS Software Lock Access Register Definitions */

+#define DIB_DLAR_KEY_Pos                    0U                                            /*!< DIB DLAR: KEY Position */

+#define DIB_DLAR_KEY_Msk                   (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */)        /*!< DIB DLAR: KEY Mask */

+

+/* DLSR, SCS Software Lock Status Register Definitions */

+#define DIB_DLSR_nTT_Pos                    2U                                            /*!< DIB DLSR: Not thirty-two bit Position */

+#define DIB_DLSR_nTT_Msk                   (0x1UL << DIB_DLSR_nTT_Pos )                   /*!< DIB DLSR: Not thirty-two bit Mask */

+

+#define DIB_DLSR_SLK_Pos                    1U                                            /*!< DIB DLSR: Software Lock status Position */

+#define DIB_DLSR_SLK_Msk                   (0x1UL << DIB_DLSR_SLK_Pos )                   /*!< DIB DLSR: Software Lock status Mask */

+

+#define DIB_DLSR_SLI_Pos                    0U                                            /*!< DIB DLSR: Software Lock implemented Position */

+#define DIB_DLSR_SLI_Msk                   (0x1UL /*<< DIB_DLSR_SLI_Pos*/)                /*!< DIB DLSR: Software Lock implemented Mask */

+

+/* DAUTHSTATUS, Debug Authentication Status Register Definitions */

+#define DIB_DAUTHSTATUS_SNID_Pos            6U                                            /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */

+#define DIB_DAUTHSTATUS_SNID_Msk           (0x3UL << DIB_DAUTHSTATUS_SNID_Pos )           /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */

+

+#define DIB_DAUTHSTATUS_SID_Pos             4U                                            /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */

+#define DIB_DAUTHSTATUS_SID_Msk            (0x3UL << DIB_DAUTHSTATUS_SID_Pos )            /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */

+

+#define DIB_DAUTHSTATUS_NSNID_Pos           2U                                            /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */

+#define DIB_DAUTHSTATUS_NSNID_Msk          (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos )          /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */

+

+#define DIB_DAUTHSTATUS_NSID_Pos            0U                                            /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */

+#define DIB_DAUTHSTATUS_NSID_Msk           (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/)        /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */

+

+/* DDEVARCH, SCS Device Architecture Register Definitions */

+#define DIB_DDEVARCH_ARCHITECT_Pos         21U                                            /*!< DIB DDEVARCH: Architect Position */

+#define DIB_DDEVARCH_ARCHITECT_Msk         (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos )       /*!< DIB DDEVARCH: Architect Mask */

+

+#define DIB_DDEVARCH_PRESENT_Pos           20U                                            /*!< DIB DDEVARCH: DEVARCH Present Position */

+#define DIB_DDEVARCH_PRESENT_Msk           (0x1FUL << DIB_DDEVARCH_PRESENT_Pos )          /*!< DIB DDEVARCH: DEVARCH Present Mask */

+

+#define DIB_DDEVARCH_REVISION_Pos          16U                                            /*!< DIB DDEVARCH: Revision Position */

+#define DIB_DDEVARCH_REVISION_Msk          (0xFUL << DIB_DDEVARCH_REVISION_Pos )          /*!< DIB DDEVARCH: Revision Mask */

+

+#define DIB_DDEVARCH_ARCHVER_Pos           12U                                            /*!< DIB DDEVARCH: Architecture Version Position */

+#define DIB_DDEVARCH_ARCHVER_Msk           (0xFUL << DIB_DDEVARCH_ARCHVER_Pos )           /*!< DIB DDEVARCH: Architecture Version Mask */

+

+#define DIB_DDEVARCH_ARCHPART_Pos           0U                                            /*!< DIB DDEVARCH: Architecture Part Position */

+#define DIB_DDEVARCH_ARCHPART_Msk          (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/)     /*!< DIB DDEVARCH: Architecture Part Mask */

+

+/* DDEVTYPE, SCS Device Type Register Definitions */

+#define DIB_DDEVTYPE_SUB_Pos                4U                                            /*!< DIB DDEVTYPE: Sub-type Position */

+#define DIB_DDEVTYPE_SUB_Msk               (0xFUL << DIB_DDEVTYPE_SUB_Pos )               /*!< DIB DDEVTYPE: Sub-type Mask */

+

+#define DIB_DDEVTYPE_MAJOR_Pos              0U                                            /*!< DIB DDEVTYPE: Major type Position */

+#define DIB_DDEVTYPE_MAJOR_Msk             (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/)          /*!< DIB DDEVTYPE: Major type Mask */

+

+

+/*@} end of group CMSIS_DIB */

+

+

+/**

+  \ingroup    CMSIS_core_register

   \defgroup   CMSIS_core_bitfield     Core register bit field macros

   \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).

   @{

@@ -1954,7 +2197,9 @@ typedef struct
   #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */

   #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */

   #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */

-  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */

+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< \deprecated Core Debug Base Address */

+  #define DCB_BASE            (0xE000EDF0UL)                             /*!< DCB Base Address */

+  #define DIB_BASE            (0xE000EFB0UL)                             /*!< DIB Base Address */

   #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */

   #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */

   #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */

@@ -1966,7 +2211,9 @@ typedef struct
   #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */

   #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */

   #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */

-  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */

+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< \deprecated Core Debug configuration struct */

+  #define DCB                 ((DCB_Type       *)     DCB_BASE         ) /*!< DCB configuration struct */

+  #define DIB                 ((DIB_Type       *)     DIB_BASE         ) /*!< DIB configuration struct */

 

   #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)

     #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */

@@ -1983,7 +2230,9 @@ typedef struct
 

 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)

   #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */

-  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */

+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< \deprecated Core Debug Base Address           (non-secure address space) */

+  #define DCB_BASE_NS         (0xE002EDF0UL)                             /*!< DCB Base Address                  (non-secure address space) */

+  #define DIB_BASE_NS         (0xE002EFB0UL)                             /*!< DIB Base Address                  (non-secure address space) */

   #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */

   #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */

   #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */

@@ -1992,7 +2241,9 @@ typedef struct
   #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */

   #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */

   #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */

-  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */

+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct   (non-secure address space) */

+  #define DCB_NS              ((DCB_Type       *)     DCB_BASE_NS      ) /*!< DCB configuration struct          (non-secure address space) */

+  #define DIB_NS              ((DIB_Type       *)     DIB_BASE_NS      ) /*!< DIB configuration struct          (non-secure address space) */

 

   #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)

     #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */

@@ -2064,7 +2315,7 @@ typedef struct
 

 /* Special LR values for Secure/Non-Secure call handling and exception handling                                               */

 

-/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ 

+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */

 #define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */

 

 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */

@@ -2079,7 +2330,7 @@ typedef struct
 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */

 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */

 #define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */

-#else 

+#else

 #define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */

 #endif

 

@@ -2749,6 +3000,110 @@ __STATIC_INLINE void TZ_SAU_Disable(void)
 

 

 

+/* ##################################    Debug Control function  ############################################ */

+/**

+  \ingroup  CMSIS_Core_FunctionInterface

+  \defgroup CMSIS_Core_DCBFunctions Debug Control Functions

+  \brief    Functions that access the Debug Control Block.

+  @{

+ */

+

+

+/**

+  \brief   Set Debug Authentication Control Register

+  \details writes to Debug Authentication Control register.

+  \param [in]  value  value to be writen.

+ */

+__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)

+{

+    __DSB();

+    __ISB();

+    DCB->DAUTHCTRL = value;

+    __DSB();

+    __ISB();

+}

+

+

+/**

+  \brief   Get Debug Authentication Control Register

+  \details Reads Debug Authentication Control register.

+  \return             Debug Authentication Control Register.

+ */

+__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)

+{

+    return (DCB->DAUTHCTRL);

+}

+

+

+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)

+/**

+  \brief   Set Debug Authentication Control Register (non-secure)

+  \details writes to non-secure Debug Authentication Control register when in secure state.

+  \param [in]  value  value to be writen

+ */

+__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)

+{

+    __DSB();

+    __ISB();

+    DCB_NS->DAUTHCTRL = value;

+    __DSB();

+    __ISB();

+}

+

+

+/**

+  \brief   Get Debug Authentication Control Register (non-secure)

+  \details Reads non-secure Debug Authentication Control register when in secure state.

+  \return             Debug Authentication Control Register.

+ */

+__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)

+{

+    return (DCB_NS->DAUTHCTRL);

+}

+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */

+

+/*@} end of CMSIS_Core_DCBFunctions */

+

+

+

+

+/* ##################################    Debug Identification function  ############################################ */

+/**

+  \ingroup  CMSIS_Core_FunctionInterface

+  \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions

+  \brief    Functions that access the Debug Identification Block.

+  @{

+ */

+

+

+/**

+  \brief   Get Debug Authentication Status Register

+  \details Reads Debug Authentication Status register.

+  \return             Debug Authentication Status Register.

+ */

+__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)

+{

+    return (DIB->DAUTHSTATUS);

+}

+

+

+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)

+/**

+  \brief   Get Debug Authentication Status Register (non-secure)

+  \details Reads non-secure Debug Authentication Status register when in secure state.

+  \return             Debug Authentication Status Register.

+ */

+__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)

+{

+    return (DIB_NS->DAUTHSTATUS);

+}

+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */

+

+/*@} end of CMSIS_Core_DCBFunctions */

+

+

+

+

 /* ##################################    SysTick function  ############################################ */

 /**

   \ingroup  CMSIS_Core_FunctionInterface

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/mpu_armv8.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/mpu_armv8.h
index 2fe28b687..b6ff9a9b4 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/mpu_armv8.h
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/mpu_armv8.h
@@ -1,11 +1,11 @@
 /******************************************************************************

  * @file     mpu_armv8.h

  * @brief    CMSIS MPU API for Armv8-M and Armv8.1-M MPU

- * @version  V5.1.0

- * @date     08. March 2019

+ * @version  V5.1.3

+ * @date     03. February 2021

  ******************************************************************************/

 /*

- * Copyright (c) 2017-2019 Arm Limited. All rights reserved.

+ * Copyright (c) 2017-2021 Arm Limited. All rights reserved.

  *

  * SPDX-License-Identifier: Apache-2.0

  *

@@ -44,7 +44,7 @@
 * \param WA Write Allocation: Set to 1 to use cache allocation on write miss.

 */

 #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \

-  (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))

+  ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))

 

 /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */

 #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)

@@ -62,7 +62,7 @@
 * \param O Outer memory attributes

 * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes

 */

-#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))

+#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))

 

 /** \brief Normal memory non-shareable  */

 #define ARM_MPU_SH_NON   (0U)

@@ -77,7 +77,7 @@
 * \param RO Read-Only: Set to 1 for read-only memory.

 * \param NP Non-Privileged: Set to 1 for non-privileged memory.

 */

-#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))

+#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))

 

 /** \brief Region Base Address Register value

 * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.

@@ -87,18 +87,18 @@
 * \oaram XN eXecute Never: Set to 1 for a non-executable memory region.

 */

 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \

-  ((BASE & MPU_RBAR_BASE_Msk) | \

-  ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \

+  (((BASE) & MPU_RBAR_BASE_Msk) | \

+  (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \

   ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \

-  ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))

+  (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))

 

 /** \brief Region Limit Address Register value

 * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.

 * \param IDX The attribute index to be associated with this memory region.

 */

 #define ARM_MPU_RLAR(LIMIT, IDX) \

-  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \

-  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \

+  (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \

+  (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \

   (MPU_RLAR_EN_Msk))

 

 #if defined(MPU_RLAR_PXN_Pos)

@@ -109,9 +109,9 @@
 * \param IDX The attribute index to be associated with this memory region.

 */

 #define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \

-  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \

-  ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \

-  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \

+  (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \

+  (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \

+  (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \

   (MPU_RLAR_EN_Msk))

   

 #endif

@@ -129,6 +129,7 @@ typedef struct {
 */

 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)

 {

+  __DMB();

   MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;

 #ifdef SCB_SHCSR_MEMFAULTENA_Msk

   SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;

@@ -146,6 +147,8 @@ __STATIC_INLINE void ARM_MPU_Disable(void)
   SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;

 #endif

   MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;

+  __DSB();

+  __ISB();

 }

 

 #ifdef MPU_NS

@@ -154,6 +157,7 @@ __STATIC_INLINE void ARM_MPU_Disable(void)
 */

 __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)

 {

+  __DMB();

   MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;

 #ifdef SCB_SHCSR_MEMFAULTENA_Msk

   SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;

@@ -171,6 +175,8 @@ __STATIC_INLINE void ARM_MPU_Disable_NS(void)
   SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;

 #endif

   MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;

+  __DSB();

+  __ISB();

 }

 #endif

 

@@ -275,7 +281,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t
 }

 #endif

 

-/** Memcopy with strictly ordered memory access, e.g. for register targets.

+/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx()

 * \param dst Destination data is copied to.

 * \param src Source data is copied from.

 * \param len Amount of data words to be copied.

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/board/board.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/board/board.h
index 4014da036..c3439ed99 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/board/board.h
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/board/board.h
@@ -115,6 +115,11 @@
 #define BOARD_SW3_IRQ_HANDLER       PIN_INT1_IRQHandler

 #define BOARD_SW3_GPIO_PININT_INDEX 1

 

+/* USB PHY condfiguration */

+#define BOARD_USB_PHY_D_CAL     (0x05U)

+#define BOARD_USB_PHY_TXCAL45DP (0x0AU)

+#define BOARD_USB_PHY_TXCAL45DM (0x0AU)

+

 /* Board led color mapping */

 #define LOGIC_LED_ON  0U

 #define LOGIC_LED_OFF 1U

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/lists/fsl_component_generic_list.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/lists/fsl_component_generic_list.c
index 6184631f7..e09f38996 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/lists/fsl_component_generic_list.c
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/lists/fsl_component_generic_list.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2019, 2022 NXP
  * All rights reserved.
  *
  *
@@ -21,8 +21,8 @@
     OSA_ENTER_CRITICAL()
 #define LIST_EXIT_CRITICAL() OSA_EXIT_CRITICAL()
 #else
-#define LIST_ENTER_CRITICAL()
-#define LIST_EXIT_CRITICAL()
+#define LIST_ENTER_CRITICAL() uint32_t regPrimask = DisableGlobalIRQ();
+#define LIST_EXIT_CRITICAL()  EnableGlobalIRQ(regPrimask);
 #endif
 #else
 #define LIST_ENTER_CRITICAL() uint32_t regPrimask = DisableGlobalIRQ();
@@ -63,7 +63,7 @@ static list_status_t LIST_Error_Check(list_handle_t list, list_element_handle_t
 *************************************************************************************
 ********************************************************************************** */
 /*! *********************************************************************************
- * \brief     Initialises the list descriptor.
+ * \brief     Initializes the list descriptor.
  *
  * \param[in] list - LIST_ handle to init.
  *            max - Maximum number of elements in list. 0 for unlimited.
@@ -81,7 +81,7 @@ void LIST_Init(list_handle_t list, uint32_t max)
 {
     list->head = NULL;
     list->tail = NULL;
-    list->max  = (uint16_t)max;
+    list->max  = max;
     list->size = 0;
 }
 
@@ -489,5 +489,5 @@ uint32_t LIST_GetSize(list_handle_t list)
  ********************************************************************************** */
 uint32_t LIST_GetAvailableSize(list_handle_t list)
 {
-    return ((uint32_t)list->max - (uint32_t)list->size); /*Gets the number of free places in the list*/
+    return (list->max - list->size); /*Gets the number of free places in the list*/
 }
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/lists/fsl_component_generic_list.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/lists/fsl_component_generic_list.h
index 312aa8a96..aa468e2eb 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/lists/fsl_component_generic_list.h
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/lists/fsl_component_generic_list.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018-2020 NXP
+ * Copyright 2018-2020, 2022 NXP
  * All rights reserved.
  *
  *
@@ -9,7 +9,13 @@
 #ifndef _GENERIC_LIST_H_
 #define _GENERIC_LIST_H_
 
+#ifndef SDK_COMPONENT_DEPENDENCY_FSL_COMMON
+#define SDK_COMPONENT_DEPENDENCY_FSL_COMMON (1U)
+#endif
+#if (defined(SDK_COMPONENT_DEPENDENCY_FSL_COMMON) && (SDK_COMPONENT_DEPENDENCY_FSL_COMMON > 0U))
 #include "fsl_common.h"
+#else
+#endif
 /*!
  * @addtogroup GenericList
  * @{
@@ -36,6 +42,7 @@
  * Public type definitions
  ***********************************************************************************/
 /*! @brief The list status */
+#if (defined(SDK_COMPONENT_DEPENDENCY_FSL_COMMON) && (SDK_COMPONENT_DEPENDENCY_FSL_COMMON > 0U))
 typedef enum _list_status
 {
     kLIST_Ok             = kStatus_Success,                   /*!< Success */
@@ -45,14 +52,25 @@ typedef enum _list_status
     kLIST_OrphanElement  = MAKE_STATUS(kStatusGroup_LIST, 4), /*!< Orphan Element */
     kLIST_NotSupport     = MAKE_STATUS(kStatusGroup_LIST, 5), /*!< Not Support  */
 } list_status_t;
+#else
+typedef enum _list_status
+{
+    kLIST_Ok             = 0, /*!< Success */
+    kLIST_DuplicateError = 1, /*!< Duplicate Error */
+    kLIST_Full           = 2, /*!< FULL */
+    kLIST_Empty          = 3, /*!< Empty */
+    kLIST_OrphanElement  = 4, /*!< Orphan Element */
+    kLIST_NotSupport     = 5, /*!< Not Support  */
+} list_status_t;
+#endif
 
 /*! @brief The list structure*/
 typedef struct list_label
 {
     struct list_element_tag *head; /*!< list head */
     struct list_element_tag *tail; /*!< list tail */
-    uint16_t size;                 /*!< list size */
-    uint16_t max;                  /*!< list max number of elements */
+    uint32_t size;                 /*!< list size */
+    uint32_t max;                  /*!< list max number of elements */
 } list_label_t, *list_handle_t;
 #if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
 /*! @brief The list element*/
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/uart/fsl_adapter_uart.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/uart/fsl_adapter_uart.h
index 7d8bc4441..f8350014c 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/uart/fsl_adapter_uart.h
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/uart/fsl_adapter_uart.h
@@ -58,14 +58,20 @@
 #define HAL_UART_ADAPTER_LOWPOWER (0U)
 #endif /* HAL_UART_ADAPTER_LOWPOWER */
 
+/*! @brief Enable or disable uart hardware FIFO mode (1 - enable, 0 - disable) */
 #ifndef HAL_UART_ADAPTER_FIFO
-#define HAL_UART_ADAPTER_FIFO (0U)
+#define HAL_UART_ADAPTER_FIFO (1U)
 #endif /* HAL_UART_ADAPTER_FIFO */
 
 #ifndef HAL_UART_DMA_ENABLE
 #define HAL_UART_DMA_ENABLE (0U)
 #endif /* HAL_UART_DMA_ENABLE */
 
+/*! @brief Enable or disable uart DMA adapter int mode (1 - enable, 0 - disable) */
+#ifndef HAL_UART_DMA_INIT_ENABLE
+#define HAL_UART_DMA_INIT_ENABLE (1U)
+#endif /* HAL_SPI_MASTER_DMA_INIT_ENABLE */
+
 /*! @brief Definition of uart dma adapter software idleline detection timeout value in ms. */
 #ifndef HAL_UART_DMA_IDLELINE_TIMEOUT
 #define HAL_UART_DMA_IDLELINE_TIMEOUT (1U)
@@ -73,10 +79,10 @@
 
 /*! @brief Definition of uart adapter handle size. */
 #if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
-#define HAL_UART_HANDLE_SIZE       (92U + HAL_UART_ADAPTER_LOWPOWER * 16U + HAL_UART_DMA_ENABLE * 4)
-#define HAL_UART_BLOCK_HANDLE_SIZE (8U + HAL_UART_ADAPTER_LOWPOWER * 16U + HAL_UART_DMA_ENABLE * 4)
+#define HAL_UART_HANDLE_SIZE       (92U + HAL_UART_ADAPTER_LOWPOWER * 16U + HAL_UART_DMA_ENABLE * 4U)
+#define HAL_UART_BLOCK_HANDLE_SIZE (8U + HAL_UART_ADAPTER_LOWPOWER * 16U + HAL_UART_DMA_ENABLE * 4U)
 #else
-#define HAL_UART_HANDLE_SIZE (8U + HAL_UART_ADAPTER_LOWPOWER * 16U + HAL_UART_DMA_ENABLE * 4)
+#define HAL_UART_HANDLE_SIZE (8U + HAL_UART_ADAPTER_LOWPOWER * 16U + HAL_UART_DMA_ENABLE * 4U)
 #endif
 
 /*! @brief Definition of uart dma adapter handle size. */
@@ -148,15 +154,6 @@ typedef enum _hal_uart_parity_mode
     kHAL_UartParityOdd      = 0x3U, /*!< Parity odd enabled */
 } hal_uart_parity_mode_t;
 
-#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
-/*! @brief UART Block Mode. */
-typedef enum _hal_uart_block_mode
-{
-    kHAL_UartNonBlockMode = 0x0U, /*!< Uart NonBlock Mode */
-    kHAL_UartBlockMode    = 0x1U, /*!< Uart Block Mode */
-} hal_uart_block_mode_t;
-#endif /* UART_ADAPTER_NON_BLOCKING_MODE */
-
 /*! @brief UART stop bit count. */
 typedef enum _hal_uart_stop_bit_count
 {
@@ -178,9 +175,6 @@ typedef struct _hal_uart_config
     uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information please refer to the
                            SOC corresponding RM.
                            Invalid instance value will cause initialization failure. */
-#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
-    hal_uart_block_mode_t mode; /*!< Uart  block mode */
-#endif                          /* UART_ADAPTER_NON_BLOCKING_MODE */
 #if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
     uint8_t txFifoWatermark;
     uint8_t rxFifoWatermark;
@@ -200,21 +194,38 @@ typedef enum _hal_uart_dma_status
     kStatus_HAL_UartDmaError    = (1U << 6U),
 } hal_uart_dma_status_t;
 
+typedef struct _dma_mux_configure_t
+{
+    union
+    {
+        struct
+        {
+            uint8_t dma_mux_instance;
+            uint32_t rx_request;
+            uint32_t tx_request;
+        } dma_dmamux_configure;
+    };
+} dma_mux_configure_t;
+typedef struct _dma_channel_mux_configure_t
+{
+    union
+    {
+        struct
+        {
+            uint32_t dma_rx_channel_mux;
+            uint32_t dma_tx_channel_mux;
+        } dma_dmamux_configure;
+    };
+} dma_channel_mux_configure_t;
+
 typedef struct _hal_uart_dma_config_t
 {
     uint8_t uart_instance;
     uint8_t dma_instance;
     uint8_t rx_channel;
     uint8_t tx_channel;
-#if defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT
-    uint8_t dma_mux_instance;
-    dma_request_source_t rx_request;
-    dma_request_source_t tx_request;
-#endif
-#if defined(FSL_FEATURE_EDMA_HAS_CHANNEL_MUX) && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX
-    uint32_t dma_rx_channel_mux;
-    uint32_t dma_tx_channel_mux;
-#endif
+    void *dma_mux_configure;
+    void *dma_channel_mux_configure;
 } hal_uart_dma_config_t;
 #endif /* HAL_UART_DMA_ENABLE */
 
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/LPC55S69_cm33_core0.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/LPC55S69_cm33_core0.h
index dce5553ea..62dfd435f 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/LPC55S69_cm33_core0.h
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/LPC55S69_cm33_core0.h
@@ -11,13 +11,13 @@
 **

 **     Reference manual:    LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3  16 May 2019

 **     Version:             rev. 1.1, 2019-05-16

-**     Build:               b210603

+**     Build:               b220718

 **

 **     Abstract:

 **         CMSIS Peripheral Access Layer for LPC55S69_cm33_core0

 **

 **     Copyright 1997-2016 Freescale Semiconductor, Inc.

-**     Copyright 2016-2021 NXP

+**     Copyright 2016-2022 NXP

 **     All rights reserved.

 **

 **     SPDX-License-Identifier: BSD-3-Clause

@@ -1364,7 +1364,7 @@ typedef struct {
 

 

 /* ADC - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral ADC0 base address */

   #define ADC0_BASE                                (0x500A0000u)

   /** Peripheral ADC0 base address */

@@ -3764,256 +3764,256 @@ typedef struct {
 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK (0x1U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT (0U)

 /*! SYS_IRQ - Watchdog Timer, Brown Out Detectors and Flash Controller interrupts

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK (0x2U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT (1U)

 /*! SDMA0_IRQ - System DMA 0 (non-secure) interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK (0x4U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT (2U)

 /*! GPIO_GLOBALINT0_IRQ - GPIO Group 0 interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK (0x8U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT (3U)

 /*! GPIO_GLOBALINT1_IRQ - GPIO Group 1 interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK (0x10U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT (4U)

 /*! GPIO_INT0_IRQ0 - Pin interrupt 0 or pattern match engine slice 0 interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK (0x20U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT (5U)

 /*! GPIO_INT0_IRQ1 - Pin interrupt 1 or pattern match engine slice 1 interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK (0x40U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT (6U)

 /*! GPIO_INT0_IRQ2 - Pin interrupt 2 or pattern match engine slice 2 interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK (0x80U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT (7U)

 /*! GPIO_INT0_IRQ3 - Pin interrupt 3 or pattern match engine slice 3 interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK (0x100U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT (8U)

 /*! UTICK_IRQ - Micro Tick Timer interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK (0x200U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT (9U)

 /*! MRT_IRQ - Multi-Rate Timer interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK (0x400U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT (10U)

 /*! CTIMER0_IRQ - Standard counter/timer 0 interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK (0x800U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT (11U)

 /*! CTIMER1_IRQ - Standard counter/timer 1 interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK (0x1000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT (12U)

 /*! SCT_IRQ - SCTimer/PWM interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK (0x2000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT (13U)

 /*! CTIMER3_IRQ - Standard counter/timer 3 interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK (0x4000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT (14U)

 /*! FLEXCOMM0_IRQ - Flexcomm 0 interrupt (USART, SPI, I2C, I2S).

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK (0x8000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT (15U)

 /*! FLEXCOMM1_IRQ - Flexcomm 1 interrupt (USART, SPI, I2C, I2S).

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK (0x10000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT (16U)

 /*! FLEXCOMM2_IRQ - Flexcomm 2 interrupt (USART, SPI, I2C, I2S).

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK (0x20000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT (17U)

 /*! FLEXCOMM3_IRQ - Flexcomm 3 interrupt (USART, SPI, I2C, I2S).

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK (0x40000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT (18U)

 /*! FLEXCOMM4_IRQ - Flexcomm 4 interrupt (USART, SPI, I2C, I2S).

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK (0x80000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT (19U)

 /*! FLEXCOMM5_IRQ - Flexcomm 5 interrupt (USART, SPI, I2C, I2S).

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK (0x100000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT (20U)

 /*! FLEXCOMM6_IRQ - Flexcomm 6 interrupt (USART, SPI, I2C, I2S).

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK (0x200000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT (21U)

 /*! FLEXCOMM7_IRQ - Flexcomm 7 interrupt (USART, SPI, I2C, I2S).

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK (0x400000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT (22U)

 /*! ADC_IRQ - General Purpose ADC interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK (0x800000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT (23U)

 /*! RESERVED0 - Reserved. Read value is undefined, only zero should be written.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_MASK (0x1000000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_SHIFT (24U)

 /*! ACMP_IRQ - Analog Comparator interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK (0x2000000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT (25U)

 /*! RESERVED1 - Reserved. Read value is undefined, only zero should be written.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK (0x4000000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT (26U)

 /*! RESERVED2 - Reserved. Read value is undefined, only zero should be written.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK (0x8000000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT (27U)

 /*! USB0_NEEDCLK - USB Full Speed Controller Clock request interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK (0x10000000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT (28U)

 /*! USB0_IRQ - USB Full Speed Controller interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK (0x20000000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT (29U)

 /*! RTC_IRQ - RTC_LITE0_ALARM_IRQ, RTC_LITE0_WAKEUP_IRQ

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK (0x40000000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT (30U)

 /*! RESERVED3 - Reserved. Read value is undefined, only zero should be written.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK (0x80000000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT (31U)

 /*! MAILBOX_IRQ - Mailbox interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK)

 /*! @} */

@@ -4024,224 +4024,224 @@ typedef struct {
 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK (0x1U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT (0U)

 /*! GPIO_INT0_IRQ4 - Pin interrupt 4 or pattern match engine slice 4 interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK (0x2U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT (1U)

 /*! GPIO_INT0_IRQ5 - Pin interrupt 5 or pattern match engine slice 5 interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK (0x4U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT (2U)

 /*! GPIO_INT0_IRQ6 - Pin interrupt 6 or pattern match engine slice 6 interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK (0x8U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT (3U)

 /*! GPIO_INT0_IRQ7 - Pin interrupt 7 or pattern match engine slice 7 interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK (0x10U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT (4U)

 /*! CTIMER2_IRQ - Standard counter/timer 2 interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK (0x20U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT (5U)

 /*! CTIMER4_IRQ - Standard counter/timer 4 interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK (0x40U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT (6U)

 /*! OS_EVENT_TIMER_IRQ - OS Event Timer and OS Event Timer Wakeup interrupts

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK (0x80U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT (7U)

 /*! RESERVED0 - Reserved. Read value is undefined, only zero should be written.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK (0x100U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT (8U)

 /*! RESERVED1 - Reserved. Read value is undefined, only zero should be written.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK (0x200U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT (9U)

 /*! RESERVED2 - Reserved. Read value is undefined, only zero should be written.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK (0x400U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT (10U)

 /*! SDIO_IRQ - SDIO Controller interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK (0x800U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT (11U)

 /*! RESERVED3 - Reserved. Read value is undefined, only zero should be written.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK (0x1000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT (12U)

 /*! RESERVED4 - Reserved. Read value is undefined, only zero should be written.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK (0x2000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT (13U)

 /*! RESERVED5 - Reserved. Read value is undefined, only zero should be written.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_MASK (0x4000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_SHIFT (14U)

 /*! USB1_PHY_IRQ - USB High Speed PHY Controller interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK (0x8000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT (15U)

 /*! USB1_IRQ - USB High Speed Controller interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK (0x10000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT (16U)

 /*! USB1_NEEDCLK - USB High Speed Controller Clock request interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK (0x20000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT (17U)

 /*! SEC_HYPERVISOR_CALL_IRQ - Secure fault Hyper Visor call interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK (0x40000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT (18U)

 /*! SEC_GPIO_INT0_IRQ0 - Secure Pin interrupt 0 or pattern match engine slice 0 interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK (0x80000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT (19U)

 /*! SEC_GPIO_INT0_IRQ1 - Secure Pin interrupt 1 or pattern match engine slice 1 interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK (0x100000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT (20U)

 /*! PLU_IRQ - Programmable Look-Up Controller interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK (0x200000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT (21U)

 /*! SEC_VIO_IRQ - Security Violation interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK (0x400000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT (22U)

 /*! SHA_IRQ - HASH-AES interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK (0x800000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT (23U)

 /*! CASPER_IRQ - CASPER interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_MASK (0x1000000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_SHIFT (24U)

 /*! PUFKEY_IRQ - PUF interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK (0x2000000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT (25U)

 /*! PQ_IRQ - Power Quad interrupt.

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK (0x4000000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT (26U)

 /*! SDMA1_IRQ - System DMA 1 (Secure) interrupt

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK)

 

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK (0x8000000U)

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT (27U)

 /*! LSPI_HS_IRQ - High Speed SPI interrupt

- *  0b0..

- *  0b1..

+ *  0b0..Interrupt is blocked to CPU1.

+ *  0b1..Interrupt is readable by CPU1.

  */

 #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK)

 /*! @} */

@@ -4649,7 +4649,7 @@ typedef struct {
 #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U)

 /*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix.

  *  0b10..Disable check.

- *  0b01..Restricted mode.

+ *  0b01..Enabled (restricted mode)

  */

 #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK)

 

@@ -4657,7 +4657,7 @@ typedef struct {
 #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U)

 /*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix.

  *  0b10..Disable check.

- *  0b01..Restricted mode.

+ *  0b01..Enabled (restricted mode)

  */

 #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK)

 

@@ -4665,7 +4665,7 @@ typedef struct {
 #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U)

 /*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix.

  *  0b10..Disable check.

- *  0b01..Restricted mode.

+ *  0b01..Enabled (restricted mode)

  */

 #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK)

 

@@ -4709,7 +4709,7 @@ typedef struct {
 

 

 /* AHB_SECURE_CTRL - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral AHB_SECURE_CTRL base address */

   #define AHB_SECURE_CTRL_BASE                     (0x500AC000u)

   /** Peripheral AHB_SECURE_CTRL base address */

@@ -4753,24 +4753,29 @@ typedef struct {
 

 /** ANACTRL - Register Layout Typedef */

 typedef struct {

-       uint8_t RESERVED_0[4];

+  __IO uint32_t ANALOG_CTRL_CFG;                   /**< Various Analog blocks configuration (like FRO 192MHz trimmings source ...), offset: 0x0 */

   __I  uint32_t ANALOG_CTRL_STATUS;                /**< Analog Macroblock Identity registers, Flash Status registers, offset: 0x4 */

-       uint8_t RESERVED_1[4];

+       uint8_t RESERVED_0[4];

   __IO uint32_t FREQ_ME_CTRL;                      /**< Frequency Measure function control register, offset: 0xC */

   __IO uint32_t FRO192M_CTRL;                      /**< 192MHz Free Running OScillator (FRO) Control register, offset: 0x10 */

   __I  uint32_t FRO192M_STATUS;                    /**< 192MHz Free Running OScillator (FRO) Status register, offset: 0x14 */

-       uint8_t RESERVED_2[8];

+  __IO uint32_t ADC_CTRL;                          /**< General Purpose ADC VBAT Divider branch control, offset: 0x18 */

+       uint8_t RESERVED_1[4];

   __IO uint32_t XO32M_CTRL;                        /**< High speed Crystal Oscillator Control register, offset: 0x20 */

   __I  uint32_t XO32M_STATUS;                      /**< High speed Crystal Oscillator Status register, offset: 0x24 */

-       uint8_t RESERVED_3[8];

+       uint8_t RESERVED_2[8];

   __IO uint32_t BOD_DCDC_INT_CTRL;                 /**< Brown Out Detectors (BoDs) & DCDC interrupts generation control register, offset: 0x30 */

   __I  uint32_t BOD_DCDC_INT_STATUS;               /**< BoDs & DCDC interrupts status register, offset: 0x34 */

-       uint8_t RESERVED_4[8];

+       uint8_t RESERVED_3[8];

   __IO uint32_t RINGO0_CTRL;                       /**< First Ring Oscillator module control register., offset: 0x40 */

   __IO uint32_t RINGO1_CTRL;                       /**< Second Ring Oscillator module control register., offset: 0x44 */

   __IO uint32_t RINGO2_CTRL;                       /**< Third Ring Oscillator module control register., offset: 0x48 */

-       uint8_t RESERVED_5[180];

+       uint8_t RESERVED_4[100];

+  __IO uint32_t LDO_XO32M;                         /**< High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register, offset: 0xB0 */

+  __IO uint32_t AUX_BIAS;                          /**< AUX_BIAS, offset: 0xB4 */

+       uint8_t RESERVED_5[72];

   __IO uint32_t USBHS_PHY_CTRL;                    /**< USB High Speed Phy Control, offset: 0x100 */

+  __IO uint32_t USBHS_PHY_TRIM;                    /**< USB High Speed Phy Trim values, offset: 0x104 */

 } ANACTRL_Type;

 

 /* ----------------------------------------------------------------------------

@@ -4782,6 +4787,18 @@ typedef struct {
  * @{

  */

 

+/*! @name ANALOG_CTRL_CFG - Various Analog blocks configuration (like FRO 192MHz trimmings source ...) */

+/*! @{ */

+

+#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK (0x1U)

+#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT (0U)

+/*! FRO192M_TRIM_SRC - FRO192M trimming and 'Enable' source.

+ *  0b0..FRO192M trimming and 'Enable' comes from eFUSE.

+ *  0b1..FRO192M trimming and 'Enable' comes from FRO192M_CTRL registers.

+ */

+#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT)) & ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK)

+/*! @} */

+

 /*! @name ANALOG_CTRL_STATUS - Analog Macroblock Identity registers, Flash Status registers */

 /*! @{ */

 

@@ -4866,6 +4883,12 @@ typedef struct {
  *  0b1..96 MHz clock is enabled.

  */

 #define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(x)     (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK)

+

+#define ANACTRL_FRO192M_CTRL_WRTRIM_MASK         (0x80000000U)

+#define ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT        (31U)

+/*! WRTRIM - This must be written to 1 to modify the BIAS_TRIM and TEMP_TRIM fields.

+ */

+#define ANACTRL_FRO192M_CTRL_WRTRIM(x)           (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_WRTRIM_MASK)

 /*! @} */

 

 /*! @name FRO192M_STATUS - 192MHz Free Running OScillator (FRO) Status register */

@@ -4889,9 +4912,39 @@ typedef struct {
 #define ANACTRL_FRO192M_STATUS_ATB_VCTRL(x)      (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT)) & ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK)

 /*! @} */

 

+/*! @name ADC_CTRL - General Purpose ADC VBAT Divider branch control */

+/*! @{ */

+

+#define ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK      (0x1U)

+#define ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT     (0U)

+/*! VBATDIVENABLE - Switch On/Off VBAT divider branch.

+ *  0b0..VBAT divider branch is disabled.

+ *  0b1..VBAT divider branch is enabled.

+ */

+#define ANACTRL_ADC_CTRL_VBATDIVENABLE(x)        (((uint32_t)(((uint32_t)(x)) << ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT)) & ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK)

+/*! @} */

+

 /*! @name XO32M_CTRL - High speed Crystal Oscillator Control register */

 /*! @{ */

 

+#define ANACTRL_XO32M_CTRL_SLAVE_MASK            (0x10U)

+#define ANACTRL_XO32M_CTRL_SLAVE_SHIFT           (4U)

+/*! SLAVE - Xo in slave mode.

+ */

+#define ANACTRL_XO32M_CTRL_SLAVE(x)              (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_SLAVE_SHIFT)) & ANACTRL_XO32M_CTRL_SLAVE_MASK)

+

+#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK       (0x7F00U)

+#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT      (8U)

+/*! OSC_CAP_IN - Tune capa banks of High speed Crystal Oscillator input pin

+ */

+#define ANACTRL_XO32M_CTRL_OSC_CAP_IN(x)         (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK)

+

+#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK      (0x3F8000U)

+#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT     (15U)

+/*! OSC_CAP_OUT - Tune capa banks of High speed Crystal Oscillator output pin

+ */

+#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT(x)        (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK)

+

 #define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK (0x400000U)

 #define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT (22U)

 /*! ACBUF_PASS_ENABLE - Bypass enable of XO AC buffer enable in pll and top level.

@@ -4910,7 +4963,7 @@ typedef struct {
 

 #define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK (0x1000000U)

 #define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT (24U)

-/*! ENABLE_SYSTEM_CLK_OUT - Enable XO 32 MHz output to CPU system.

+/*! ENABLE_SYSTEM_CLK_OUT - Enable High speed Crystal oscillator output to CPU system.

  *  0b0..High speed Crystal oscillator output to CPU system is disabled.

  *  0b1..High speed Crystal oscillator output to CPU system is enabled.

  */

@@ -5344,6 +5397,100 @@ typedef struct {
 #define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ(x)    (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK)

 /*! @} */

 

+/*! @name LDO_XO32M - High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register */

+/*! @{ */

+

+#define ANACTRL_LDO_XO32M_BYPASS_MASK            (0x2U)

+#define ANACTRL_LDO_XO32M_BYPASS_SHIFT           (1U)

+/*! BYPASS - Activate LDO bypass.

+ *  0b0..Disable bypass mode (for normal operations).

+ *  0b1..Activate LDO bypass.

+ */

+#define ANACTRL_LDO_XO32M_BYPASS(x)              (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_BYPASS_SHIFT)) & ANACTRL_LDO_XO32M_BYPASS_MASK)

+

+#define ANACTRL_LDO_XO32M_HIGHZ_MASK             (0x4U)

+#define ANACTRL_LDO_XO32M_HIGHZ_SHIFT            (2U)

+/*! HIGHZ - .

+ *  0b0..Output in High normal state.

+ *  0b1..Output in High Impedance state.

+ */

+#define ANACTRL_LDO_XO32M_HIGHZ(x)               (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_HIGHZ_SHIFT)) & ANACTRL_LDO_XO32M_HIGHZ_MASK)

+

+#define ANACTRL_LDO_XO32M_VOUT_MASK              (0x38U)

+#define ANACTRL_LDO_XO32M_VOUT_SHIFT             (3U)

+/*! VOUT - Sets the LDO output level.

+ *  0b000..0.750 V.

+ *  0b001..0.775 V.

+ *  0b010..0.800 V.

+ *  0b011..0.825 V.

+ *  0b100..0.850 V.

+ *  0b101..0.875 V.

+ *  0b110..0.900 V.

+ *  0b111..0.925 V.

+ */

+#define ANACTRL_LDO_XO32M_VOUT(x)                (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_VOUT_SHIFT)) & ANACTRL_LDO_XO32M_VOUT_MASK)

+

+#define ANACTRL_LDO_XO32M_IBIAS_MASK             (0xC0U)

+#define ANACTRL_LDO_XO32M_IBIAS_SHIFT            (6U)

+/*! IBIAS - Adjust the biasing current.

+ */

+#define ANACTRL_LDO_XO32M_IBIAS(x)               (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_IBIAS_SHIFT)) & ANACTRL_LDO_XO32M_IBIAS_MASK)

+

+#define ANACTRL_LDO_XO32M_STABMODE_MASK          (0x300U)

+#define ANACTRL_LDO_XO32M_STABMODE_SHIFT         (8U)

+/*! STABMODE - Stability configuration.

+ */

+#define ANACTRL_LDO_XO32M_STABMODE(x)            (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_STABMODE_SHIFT)) & ANACTRL_LDO_XO32M_STABMODE_MASK)

+/*! @} */

+

+/*! @name AUX_BIAS - AUX_BIAS */

+/*! @{ */

+

+#define ANACTRL_AUX_BIAS_VREF1VENABLE_MASK       (0x2U)

+#define ANACTRL_AUX_BIAS_VREF1VENABLE_SHIFT      (1U)

+/*! VREF1VENABLE - Control output of 1V reference voltage.

+ *  0b0..Output of 1V reference voltage buffer is bypassed.

+ *  0b1..Output of 1V reference voltage is enabled.

+ */

+#define ANACTRL_AUX_BIAS_VREF1VENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VENABLE_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VENABLE_MASK)

+

+#define ANACTRL_AUX_BIAS_ITRIM_MASK              (0x7CU)

+#define ANACTRL_AUX_BIAS_ITRIM_SHIFT             (2U)

+/*! ITRIM - current trimming control word.

+ */

+#define ANACTRL_AUX_BIAS_ITRIM(x)                (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIM_SHIFT)) & ANACTRL_AUX_BIAS_ITRIM_MASK)

+

+#define ANACTRL_AUX_BIAS_PTATITRIM_MASK          (0xF80U)

+#define ANACTRL_AUX_BIAS_PTATITRIM_SHIFT         (7U)

+/*! PTATITRIM - current trimming control word for ptat current.

+ */

+#define ANACTRL_AUX_BIAS_PTATITRIM(x)            (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_PTATITRIM_SHIFT)) & ANACTRL_AUX_BIAS_PTATITRIM_MASK)

+

+#define ANACTRL_AUX_BIAS_VREF1VTRIM_MASK         (0x1F000U)

+#define ANACTRL_AUX_BIAS_VREF1VTRIM_SHIFT        (12U)

+/*! VREF1VTRIM - voltage trimming control word.

+ */

+#define ANACTRL_AUX_BIAS_VREF1VTRIM(x)           (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VTRIM_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VTRIM_MASK)

+

+#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM_MASK    (0xE0000U)

+#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM_SHIFT   (17U)

+/*! VREF1VCURVETRIM - Control bit to configure trimming state of mirror.

+ */

+#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM(x)      (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VCURVETRIM_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VCURVETRIM_MASK)

+

+#define ANACTRL_AUX_BIAS_ITRIMCTRL0_MASK         (0x100000U)

+#define ANACTRL_AUX_BIAS_ITRIMCTRL0_SHIFT        (20U)

+/*! ITRIMCTRL0 - Control bit to configure trimming state of mirror.

+ */

+#define ANACTRL_AUX_BIAS_ITRIMCTRL0(x)           (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIMCTRL0_SHIFT)) & ANACTRL_AUX_BIAS_ITRIMCTRL0_MASK)

+

+#define ANACTRL_AUX_BIAS_ITRIMCTRL1_MASK         (0x200000U)

+#define ANACTRL_AUX_BIAS_ITRIMCTRL1_SHIFT        (21U)

+/*! ITRIMCTRL1 - Control bit to configure trimming state of mirror.

+ */

+#define ANACTRL_AUX_BIAS_ITRIMCTRL1(x)           (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIMCTRL1_SHIFT)) & ANACTRL_AUX_BIAS_ITRIMCTRL1_MASK)

+/*! @} */

+

 /*! @name USBHS_PHY_CTRL - USB High Speed Phy Control */

 /*! @{ */

 

@@ -5360,6 +5507,52 @@ typedef struct {
 #define ANACTRL_USBHS_PHY_CTRL_usb_id_ext(x)     (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK)

 /*! @} */

 

+/*! @name USBHS_PHY_TRIM - USB High Speed Phy Trim values */

+/*! @{ */

+

+#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_MASK (0x3U)

+#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_SHIFT (0U)

+/*! trim_usb_reg_env_tail_adj_vd - Adjusts time constant of HS RX squelch (envelope) comparator.

+ */

+#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_MASK)

+

+#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_MASK (0x3CU)

+#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_SHIFT (2U)

+/*! trim_usbphy_tx_d_cal - .

+ */

+#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_MASK)

+

+#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_MASK (0x7C0U)

+#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_SHIFT (6U)

+/*! trim_usbphy_tx_cal45dp - .

+ */

+#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_MASK)

+

+#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_MASK (0xF800U)

+#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_SHIFT (11U)

+/*! trim_usbphy_tx_cal45dm - .

+ */

+#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_MASK)

+

+#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_MASK (0x30000U)

+#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_SHIFT (16U)

+/*! trim_usb2_refbias_tst - .

+ */

+#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_MASK)

+

+#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_MASK (0x1C0000U)

+#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_SHIFT (18U)

+/*! trim_usb2_refbias_vbgadj - .

+ */

+#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_MASK)

+

+#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_MASK (0xE00000U)

+#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_SHIFT (21U)

+/*! trim_pll_ctrl0_div_sel - .

+ */

+#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_MASK)

+/*! @} */

+

 

 /*!

  * @}

@@ -5367,7 +5560,7 @@ typedef struct {
 

 

 /* ANACTRL - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral ANACTRL base address */

   #define ANACTRL_BASE                             (0x50013000u)

   /** Peripheral ANACTRL base address */

@@ -5454,7 +5647,7 @@ typedef struct {
  */

 #define CASPER_CTRL0_ABBPAIR(x)                  (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABBPAIR_SHIFT)) & CASPER_CTRL0_ABBPAIR_MASK)

 

-#define CASPER_CTRL0_ABOFF_MASK                  (0x4U)

+#define CASPER_CTRL0_ABOFF_MASK                  (0x1FFCU)

 #define CASPER_CTRL0_ABOFF_SHIFT                 (2U)

 /*! ABOFF - Word or DWord Offset of AB values, with B at [2]=0 and A at [2]=1 as far as the code

  *    sees (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed

@@ -5745,7 +5938,7 @@ typedef struct {
 

 

 /* CASPER - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral CASPER base address */

   #define CASPER_BASE                              (0x500A5000u)

   /** Peripheral CASPER base address */

@@ -5883,7 +6076,7 @@ typedef struct {
 

 

 /* CRC - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral CRC_ENGINE base address */

   #define CRC_ENGINE_BASE                          (0x50095000u)

   /** Peripheral CRC_ENGINE base address */

@@ -6456,7 +6649,7 @@ typedef struct {
 

 

 /* CTIMER - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral CTIMER0 base address */

   #define CTIMER0_BASE                             (0x50008000u)

   /** Peripheral CTIMER0 base address */

@@ -6533,6 +6726,11 @@ typedef struct {
 #endif

 /** Interrupt vectors for the CTIMER peripheral type */

 #define CTIMER_IRQS                              { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn }

+/* Backward compatibility for bitfield SHADOW */

+#define CTIMER_MSR_MATCH_SHADOW_MASK   CTIMER_MSR_SHADOW_MASK

+#define CTIMER_MSR_MATCH_SHADOW_SHIFT   CTIMER_MSR_SHADOW_SHIFT

+#define CTIMER_MSR_MATCH_SHADOW   CTIMER_MSR_SHADOW

+

 

 /*!

  * @}

@@ -6645,7 +6843,7 @@ typedef struct {
 

 

 /* DBGMAILBOX - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral DBGMAILBOX base address */

   #define DBGMAILBOX_BASE                          (0x5009C000u)

   /** Peripheral DBGMAILBOX base address */

@@ -7194,7 +7392,7 @@ typedef struct {
 

 

 /* DMA - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral DMA0 base address */

   #define DMA0_BASE                                (0x50082000u)

   /** Peripheral DMA0 base address */

@@ -7548,7 +7746,7 @@ typedef struct {
 

 

 /* FLASH - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral FLASH base address */

   #define FLASH_BASE                               (0x50034000u)

   /** Peripheral FLASH base address */

@@ -7592,45 +7790,45 @@ typedef struct {
 

 /** FLASH_CFPA - Register Layout Typedef */

 typedef struct {

-  __IO uint32_t HEADER;                            /**< ., offset: 0x0 */

-  __IO uint32_t VERSION;                           /**< ., offset: 0x4 */

+  __IO uint32_t HEADER;                            /**< , offset: 0x0 */

+  __IO uint32_t VERSION;                           /**< , offset: 0x4 */

   __IO uint32_t S_FW_VERSION;                      /**< Secure firmware version (Monotonic counter), offset: 0x8 */

   __IO uint32_t NS_FW_VERSION;                     /**< Non-Secure firmware version (Monotonic counter), offset: 0xC */

   __IO uint32_t IMAGE_KEY_REVOKE;                  /**< Image key revocation ID (Monotonic counter), offset: 0x10 */

        uint8_t RESERVED_0[4];

-  __IO uint32_t ROTKH_REVOKE;                      /**< ., offset: 0x18 */

-  __IO uint32_t VENDOR_USAGE;                      /**< ., offset: 0x1C */

+  __IO uint32_t ROTKH_REVOKE;                      /**< , offset: 0x18 */

+  __IO uint32_t VENDOR_USAGE;                      /**< , offset: 0x1C */

   __IO uint32_t DCFG_CC_SOCU_PIN;                  /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x20 */

   __IO uint32_t DCFG_CC_SOCU_DFLT;                 /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x24 */

   __IO uint32_t ENABLE_FA_MODE;                    /**< Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode., offset: 0x28 */

   __IO uint32_t CMPA_PROG_IN_PROGRESS;             /**< CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area., offset: 0x2C */

   union {                                          /* offset: 0x30 */

-    __IO uint32_t PRINCE_REGION0_IV_CODE[14];        /**< ., array offset: 0x30, array step: 0x4 */

+    __IO uint32_t PRINCE_REGION0_IV_CODE[14];        /**< , array offset: 0x30, array step: 0x4 */

     struct {                                         /* offset: 0x30 */

-      __IO uint32_t PRINCE_REGION0_IV_HEADER0;         /**< ., offset: 0x30 */

-      __IO uint32_t PRINCE_REGION0_IV_HEADER1;         /**< ., offset: 0x34 */

-      __IO uint32_t PRINCE_REGION0_IV_BODY[12];        /**< ., array offset: 0x38, array step: 0x4 */

+      __IO uint32_t PRINCE_REGION0_IV_HEADER0;         /**< , offset: 0x30 */

+      __IO uint32_t PRINCE_REGION0_IV_HEADER1;         /**< , offset: 0x34 */

+      __IO uint32_t PRINCE_REGION0_IV_BODY[12];        /**< , array offset: 0x38, array step: 0x4 */

     } PRINCE_REGION0_IV_CODE_CORE;

   };

   union {                                          /* offset: 0x68 */

-    __IO uint32_t PRINCE_REGION1_IV_CODE[14];        /**< ., array offset: 0x68, array step: 0x4 */

+    __IO uint32_t PRINCE_REGION1_IV_CODE[14];        /**< , array offset: 0x68, array step: 0x4 */

     struct {                                         /* offset: 0x68 */

-      __IO uint32_t PRINCE_REGION1_IV_HEADER0;         /**< ., offset: 0x68 */

-      __IO uint32_t PRINCE_REGION1_IV_HEADER1;         /**< ., offset: 0x6C */

-      __IO uint32_t PRINCE_REGION1_IV_BODY[12];        /**< ., array offset: 0x70, array step: 0x4 */

+      __IO uint32_t PRINCE_REGION1_IV_HEADER0;         /**< , offset: 0x68 */

+      __IO uint32_t PRINCE_REGION1_IV_HEADER1;         /**< , offset: 0x6C */

+      __IO uint32_t PRINCE_REGION1_IV_BODY[12];        /**< , array offset: 0x70, array step: 0x4 */

     } PRINCE_REGION1_IV_CODE_CORE;

   };

   union {                                          /* offset: 0xA0 */

-    __IO uint32_t PRINCE_REGION2_IV_CODE[14];        /**< ., array offset: 0xA0, array step: 0x4 */

+    __IO uint32_t PRINCE_REGION2_IV_CODE[14];        /**< , array offset: 0xA0, array step: 0x4 */

     struct {                                         /* offset: 0xA0 */

-      __IO uint32_t PRINCE_REGION2_IV_HEADER0;         /**< ., offset: 0xA0 */

-      __IO uint32_t PRINCE_REGION2_IV_HEADER1;         /**< ., offset: 0xA4 */

-      __IO uint32_t PRINCE_REGION2_IV_BODY[12];        /**< ., array offset: 0xA8, array step: 0x4 */

+      __IO uint32_t PRINCE_REGION2_IV_HEADER0;         /**< , offset: 0xA0 */

+      __IO uint32_t PRINCE_REGION2_IV_HEADER1;         /**< , offset: 0xA4 */

+      __IO uint32_t PRINCE_REGION2_IV_BODY[12];        /**< , array offset: 0xA8, array step: 0x4 */

     } PRINCE_REGION2_IV_CODE_CORE;

   };

        uint8_t RESERVED_1[40];

   __IO uint32_t CUSTOMER_DEFINED[56];              /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */

-  __IO uint32_t SHA256_DIGEST[8];                  /**< SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */

+  __IO uint32_t SHA256_DIGEST[8];                  /**< SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */

 } FLASH_CFPA_Type;

 

 /* ----------------------------------------------------------------------------

@@ -7642,23 +7840,19 @@ typedef struct {
  * @{

  */

 

-/*! @name HEADER - . */

+/*! @name HEADER -  */

 /*! @{ */

 

 #define FLASH_CFPA_HEADER_FIELD_MASK             (0xFFFFFFFFU)

 #define FLASH_CFPA_HEADER_FIELD_SHIFT            (0U)

-/*! FIELD - .

- */

 #define FLASH_CFPA_HEADER_FIELD(x)               (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_HEADER_FIELD_SHIFT)) & FLASH_CFPA_HEADER_FIELD_MASK)

 /*! @} */

 

-/*! @name VERSION - . */

+/*! @name VERSION -  */

 /*! @{ */

 

 #define FLASH_CFPA_VERSION_FIELD_MASK            (0xFFFFFFFFU)

 #define FLASH_CFPA_VERSION_FIELD_SHIFT           (0U)

-/*! FIELD - .

- */

 #define FLASH_CFPA_VERSION_FIELD(x)              (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VERSION_FIELD_SHIFT)) & FLASH_CFPA_VERSION_FIELD_MASK)

 /*! @} */

 

@@ -7667,8 +7861,6 @@ typedef struct {
 

 #define FLASH_CFPA_S_FW_VERSION_FIELD_MASK       (0xFFFFFFFFU)

 #define FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT      (0U)

-/*! FIELD - .

- */

 #define FLASH_CFPA_S_FW_VERSION_FIELD(x)         (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_S_FW_VERSION_FIELD_MASK)

 /*! @} */

 

@@ -7677,8 +7869,6 @@ typedef struct {
 

 #define FLASH_CFPA_NS_FW_VERSION_FIELD_MASK      (0xFFFFFFFFU)

 #define FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT     (0U)

-/*! FIELD - .

- */

 #define FLASH_CFPA_NS_FW_VERSION_FIELD(x)        (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_NS_FW_VERSION_FIELD_MASK)

 /*! @} */

 

@@ -7687,12 +7877,10 @@ typedef struct {
 

 #define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK   (0xFFFFFFFFU)

 #define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT  (0U)

-/*! FIELD - .

- */

 #define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD(x)     (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT)) & FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK)

 /*! @} */

 

-/*! @name ROTKH_REVOKE - . */

+/*! @name ROTKH_REVOKE -  */

 /*! @{ */

 

 #define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK    (0x3U)

@@ -7720,7 +7908,7 @@ typedef struct {
 #define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN(x)      (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_MASK)

 /*! @} */

 

-/*! @name VENDOR_USAGE - . */

+/*! @name VENDOR_USAGE -  */

 /*! @{ */

 

 #define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK (0xFFFFU)

@@ -7927,8 +8115,6 @@ typedef struct {
 

 #define FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK     (0xFFFFFFFFU)

 #define FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT    (0U)

-/*! FIELD - .

- */

 #define FLASH_CFPA_ENABLE_FA_MODE_FIELD(x)       (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT)) & FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK)

 /*! @} */

 

@@ -7937,179 +8123,141 @@ typedef struct {
 

 #define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK (0xFFFFFFFFU)

 #define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT (0U)

-/*! FIELD - .

- */

 #define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT)) & FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK)

 /*! @} */

 

-/*! @name PRINCE_REGION0_IV_CODE - . */

+/*! @name PRINCE_REGION0_IV_CODE -  */

 /*! @{ */

 

 #define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK (0xFFFFFFFFU)

 #define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT (0U)

-/*! FIELD - .

- */

 #define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK)

 /*! @} */

 

 /* The count of FLASH_CFPA_PRINCE_REGION0_IV_CODE */

 #define FLASH_CFPA_PRINCE_REGION0_IV_CODE_COUNT  (14U)

 

-/*! @name PRINCE_REGION0_IV_HEADER0 - . */

+/*! @name PRINCE_REGION0_IV_HEADER0 -  */

 /*! @{ */

 

 #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU)

 #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT (0U)

-/*! FIELD - .

- */

 #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK)

 /*! @} */

 

-/*! @name PRINCE_REGION0_IV_HEADER1 - . */

+/*! @name PRINCE_REGION0_IV_HEADER1 -  */

 /*! @{ */

 

 #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK (0x3U)

 #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT (0U)

-/*! TYPE - .

- */

 #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK)

 

 #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK (0xF00U)

 #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT (8U)

-/*! INDEX - .

- */

 #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK)

 

 #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK (0x3F000000U)

 #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT (24U)

-/*! SIZE - .

- */

 #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK)

 /*! @} */

 

-/*! @name PRINCE_REGION0_IV_BODY - . */

+/*! @name PRINCE_REGION0_IV_BODY -  */

 /*! @{ */

 

 #define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK (0xFFFFFFFFU)

 #define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT (0U)

-/*! FIELD - .

- */

 #define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK)

 /*! @} */

 

 /* The count of FLASH_CFPA_PRINCE_REGION0_IV_BODY */

 #define FLASH_CFPA_PRINCE_REGION0_IV_BODY_COUNT  (12U)

 

-/*! @name PRINCE_REGION1_IV_CODE - . */

+/*! @name PRINCE_REGION1_IV_CODE -  */

 /*! @{ */

 

 #define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK (0xFFFFFFFFU)

 #define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT (0U)

-/*! FIELD - .

- */

 #define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK)

 /*! @} */

 

 /* The count of FLASH_CFPA_PRINCE_REGION1_IV_CODE */

 #define FLASH_CFPA_PRINCE_REGION1_IV_CODE_COUNT  (14U)

 

-/*! @name PRINCE_REGION1_IV_HEADER0 - . */

+/*! @name PRINCE_REGION1_IV_HEADER0 -  */

 /*! @{ */

 

 #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU)

 #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT (0U)

-/*! FIELD - .

- */

 #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK)

 /*! @} */

 

-/*! @name PRINCE_REGION1_IV_HEADER1 - . */

+/*! @name PRINCE_REGION1_IV_HEADER1 -  */

 /*! @{ */

 

 #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK (0x3U)

 #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT (0U)

-/*! TYPE - .

- */

 #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK)

 

 #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK (0xF00U)

 #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT (8U)

-/*! INDEX - .

- */

 #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK)

 

 #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK (0x3F000000U)

 #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT (24U)

-/*! SIZE - .

- */

 #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK)

 /*! @} */

 

-/*! @name PRINCE_REGION1_IV_BODY - . */

+/*! @name PRINCE_REGION1_IV_BODY -  */

 /*! @{ */

 

 #define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK (0xFFFFFFFFU)

 #define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT (0U)

-/*! FIELD - .

- */

 #define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK)

 /*! @} */

 

 /* The count of FLASH_CFPA_PRINCE_REGION1_IV_BODY */

 #define FLASH_CFPA_PRINCE_REGION1_IV_BODY_COUNT  (12U)

 

-/*! @name PRINCE_REGION2_IV_CODE - . */

+/*! @name PRINCE_REGION2_IV_CODE -  */

 /*! @{ */

 

 #define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK (0xFFFFFFFFU)

 #define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT (0U)

-/*! FIELD - .

- */

 #define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK)

 /*! @} */

 

 /* The count of FLASH_CFPA_PRINCE_REGION2_IV_CODE */

 #define FLASH_CFPA_PRINCE_REGION2_IV_CODE_COUNT  (14U)

 

-/*! @name PRINCE_REGION2_IV_HEADER0 - . */

+/*! @name PRINCE_REGION2_IV_HEADER0 -  */

 /*! @{ */

 

 #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU)

 #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT (0U)

-/*! FIELD - .

- */

 #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK)

 /*! @} */

 

-/*! @name PRINCE_REGION2_IV_HEADER1 - . */

+/*! @name PRINCE_REGION2_IV_HEADER1 -  */

 /*! @{ */

 

 #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK (0x3U)

 #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT (0U)

-/*! TYPE - .

- */

 #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK)

 

 #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK (0xF00U)

 #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT (8U)

-/*! INDEX - .

- */

 #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK)

 

 #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK (0x3F000000U)

 #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT (24U)

-/*! SIZE - .

- */

 #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK)

 /*! @} */

 

-/*! @name PRINCE_REGION2_IV_BODY - . */

+/*! @name PRINCE_REGION2_IV_BODY -  */

 /*! @{ */

 

 #define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK (0xFFFFFFFFU)

 #define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT (0U)

-/*! FIELD - .

- */

 #define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK)

 /*! @} */

 

@@ -8121,21 +8269,17 @@ typedef struct {
 

 #define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK   (0xFFFFFFFFU)

 #define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT  (0U)

-/*! FIELD - .

- */

 #define FLASH_CFPA_CUSTOMER_DEFINED_FIELD(x)     (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK)

 /*! @} */

 

 /* The count of FLASH_CFPA_CUSTOMER_DEFINED */

 #define FLASH_CFPA_CUSTOMER_DEFINED_COUNT        (56U)

 

-/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] */

+/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224] */

 /*! @{ */

 

 #define FLASH_CFPA_SHA256_DIGEST_FIELD_MASK      (0xFFFFFFFFU)

 #define FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT     (0U)

-/*! FIELD - .

- */

 #define FLASH_CFPA_SHA256_DIGEST_FIELD(x)        (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CFPA_SHA256_DIGEST_FIELD_MASK)

 /*! @} */

 

@@ -8149,7 +8293,7 @@ typedef struct {
 

 

 /* FLASH_CFPA - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral FLASH_CFPA0 base address */

   #define FLASH_CFPA0_BASE                         (0x1009E000u)

   /** Peripheral FLASH_CFPA0 base address */

@@ -8217,25 +8361,25 @@ typedef struct {
 

 /** FLASH_CMPA - Register Layout Typedef */

 typedef struct {

-  __IO uint32_t BOOT_CFG;                          /**< ., offset: 0x0 */

-  __IO uint32_t SPI_FLASH_CFG;                     /**< ., offset: 0x4 */

-  __IO uint32_t USB_ID;                            /**< ., offset: 0x8 */

-  __IO uint32_t SDIO_CFG;                          /**< ., offset: 0xC */

-  __IO uint32_t CC_SOCU_PIN;                       /**< ., offset: 0x10 */

-  __IO uint32_t CC_SOCU_DFLT;                      /**< ., offset: 0x14 */

-  __IO uint32_t VENDOR_USAGE;                      /**< ., offset: 0x18 */

-  __IO uint32_t SECURE_BOOT_CFG;                   /**< ., offset: 0x1C */

-  __IO uint32_t PRINCE_BASE_ADDR;                  /**< ., offset: 0x20 */

+  __IO uint32_t BOOT_CFG;                          /**< , offset: 0x0 */

+  __IO uint32_t SPI_FLASH_CFG;                     /**< , offset: 0x4 */

+  __IO uint32_t USB_ID;                            /**< , offset: 0x8 */

+  __IO uint32_t SDIO_CFG;                          /**< , offset: 0xC */

+  __IO uint32_t CC_SOCU_PIN;                       /**< , offset: 0x10 */

+  __IO uint32_t CC_SOCU_DFLT;                      /**< , offset: 0x14 */

+  __IO uint32_t VENDOR_USAGE;                      /**< , offset: 0x18 */

+  __IO uint32_t SECURE_BOOT_CFG;                   /**< Secure boot configuration flags., offset: 0x1C */

+  __IO uint32_t PRINCE_BASE_ADDR;                  /**< , offset: 0x20 */

   __IO uint32_t PRINCE_SR_0;                       /**< Region 0, sub-region enable, offset: 0x24 */

   __IO uint32_t PRINCE_SR_1;                       /**< Region 1, sub-region enable, offset: 0x28 */

   __IO uint32_t PRINCE_SR_2;                       /**< Region 2, sub-region enable, offset: 0x2C */

   __IO uint32_t XTAL_32KHZ_CAPABANK_TRIM;          /**< Xtal 32kHz capabank triming., offset: 0x30 */

   __IO uint32_t XTAL_16MHZ_CAPABANK_TRIM;          /**< Xtal 16MHz capabank triming., offset: 0x34 */

        uint8_t RESERVED_0[24];

-  __IO uint32_t ROTKH[8];                          /**< ROTKH0 for Root of Trust Keys Table hash[255:224] ROTKH1 for Root of Trust Keys Table hash[223:192] ROTKH2 for Root of Trust Keys Table hash[191:160] ROTKH3 for Root of Trust Keys Table hash[159:128] ROTKH4 for Root of Trust Keys Table hash[127:96] ROTKH5 for Root of Trust Keys Table hash[95:64] ROTKH6 for Root of Trust Keys Table hash[63:32] ROTKH7 for Root of Trust Keys Table hash[31:0], array offset: 0x50, array step: 0x4 */

+  __IO uint32_t ROTKH[8];                          /**< ROTKH0 for Root of Trust Keys Table hash[255:224]..ROTKH7 for Root of Trust Keys Table hash[31:0], array offset: 0x50, array step: 0x4 */

        uint8_t RESERVED_1[144];

   __IO uint32_t CUSTOMER_DEFINED[56];              /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */

-  __IO uint32_t SHA256_DIGEST[8];                  /**< SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */

+  __IO uint32_t SHA256_DIGEST[8];                  /**< SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */

 } FLASH_CMPA_Type;

 

 /* ----------------------------------------------------------------------------

@@ -8247,16 +8391,17 @@ typedef struct {
  * @{

  */

 

-/*! @name BOOT_CFG - . */

+/*! @name BOOT_CFG -  */

 /*! @{ */

 

 #define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK (0x70U)

 #define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT (4U)

 /*! DEFAULT_ISP_MODE - Default ISP mode:

  *  0b000..Auto ISP

- *  0b001..USB_HID_MSC

- *  0b010..SPI Slave ISP

- *  0b011..I2C Slave ISP

+ *  0b001..USB_HID_ISP

+ *  0b010..UART ISP

+ *  0b011..SPI Slave ISP

+ *  0b100..I2C Slave ISP

  *  0b111..Disable ISP fall through

  */

 #define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE(x)  (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT)) & FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK)

@@ -8279,7 +8424,7 @@ typedef struct {
 #define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN(x)  (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK)

 /*! @} */

 

-/*! @name SPI_FLASH_CFG - . */

+/*! @name SPI_FLASH_CFG -  */

 /*! @{ */

 

 #define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK (0x1FU)

@@ -8289,33 +8434,27 @@ typedef struct {
 #define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT)) & FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK)

 /*! @} */

 

-/*! @name USB_ID - . */

+/*! @name USB_ID -  */

 /*! @{ */

 

 #define FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK     (0xFFFFU)

 #define FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT    (0U)

-/*! USB_VENDOR_ID - .

- */

 #define FLASH_CMPA_USB_ID_USB_VENDOR_ID(x)       (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK)

 

 #define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK    (0xFFFF0000U)

 #define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT   (16U)

-/*! USB_PRODUCT_ID - .

- */

 #define FLASH_CMPA_USB_ID_USB_PRODUCT_ID(x)      (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK)

 /*! @} */

 

-/*! @name SDIO_CFG - . */

+/*! @name SDIO_CFG -  */

 /*! @{ */

 

 #define FLASH_CMPA_SDIO_CFG_FIELD_MASK           (0xFFFFFFFFU)

 #define FLASH_CMPA_SDIO_CFG_FIELD_SHIFT          (0U)

-/*! FIELD - .

- */

 #define FLASH_CMPA_SDIO_CFG_FIELD(x)             (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SDIO_CFG_FIELD_SHIFT)) & FLASH_CMPA_SDIO_CFG_FIELD_MASK)

 /*! @} */

 

-/*! @name CC_SOCU_PIN - . */

+/*! @name CC_SOCU_PIN -  */

 /*! @{ */

 

 #define FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK        (0x1U)

@@ -8411,7 +8550,7 @@ typedef struct {
 #define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE(x)  (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK)

 /*! @} */

 

-/*! @name CC_SOCU_DFLT - . */

+/*! @name CC_SOCU_DFLT -  */

 /*! @{ */

 

 #define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK       (0x1U)

@@ -8501,7 +8640,7 @@ typedef struct {
 #define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK)

 /*! @} */

 

-/*! @name VENDOR_USAGE - . */

+/*! @name VENDOR_USAGE -  */

 /*! @{ */

 

 #define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK (0xFFFF0000U)

@@ -8511,49 +8650,76 @@ typedef struct {
 #define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE(x)  (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT)) & FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK)

 /*! @} */

 

-/*! @name SECURE_BOOT_CFG - . */

+/*! @name SECURE_BOOT_CFG - Secure boot configuration flags. */

 /*! @{ */

 

 #define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK    (0x3U)

 #define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT   (0U)

-/*! RSA4K - Use RSA4096 keys only. 00- RSA2048 keys 01, 10, 11 - RSA4096 keys

+/*! RSA4K - Use RSA4096 keys only.

+ *  0b00..Allow RSA2048 and higher

+ *  0b01..RSA4096 only

+ *  0b10..RSA4096 only

+ *  0b11..RSA4096 only

  */

 #define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K(x)      (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK)

 

-#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_MASK (0xCU)

-#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_SHIFT (2U)

-/*! DICE_ENC_NXP_CFG - Include NXP area in DICE computation. 00 - not included 01, 10, 11 - included

+#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_MASK (0xCU)

+#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_SHIFT (2U)

+/*! DICE_INC_NXP_CFG - Include NXP area in DICE computation.

+ *  0b00..not included

+ *  0b01..included

+ *  0b10..included

+ *  0b11..included

  */

-#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_MASK)

+#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_MASK)

 

 #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK (0x30U)

 #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT (4U)

-/*! DICE_CUST_CFG - Include Customer factory area (including keys) in DICE computation. 00 - not included 01, 10, 11 - included

+/*! DICE_CUST_CFG - Include Customer factory area (including keys) in DICE computation.

+ *  0b00..not included

+ *  0b01..included

+ *  0b10..included

+ *  0b11..included

  */

 #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK)

 

 #define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK (0xC0U)

 #define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT (6U)

-/*! SKIP_DICE - Skip DICE computation. 00 - Enable DICE 01,10,11 - Disable DICE

+/*! SKIP_DICE - Skip DICE computation

+ *  0b00..Enable DICE

+ *  0b01..Disable DICE

+ *  0b10..Disable DICE

+ *  0b11..Disable DICE

  */

 #define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE(x)  (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK)

 

 #define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK (0x300U)

 #define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT (8U)

-/*! TZM_IMAGE_TYPE - TrustZone-M mode. 00 - TZM mode in image header. 01 - Disable TZ-M. Boots to

- *    NonSecure. 10 - TZ-M enable boots to secure mode. 11 - Preset TZM checker from image header.

+/*! TZM_IMAGE_TYPE - TrustZone-M mode

+ *  0b00..TZ-M image mode is taken from application image header

+ *  0b01..TZ-M disabled image, boots to non-secure mode

+ *  0b10..TZ-M enabled image, boots to secure mode

+ *  0b11..TZ-M enabled image with TZ-M preset, boot to secure mode TZ-M pre-configured by data from application image header

  */

 #define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK)

 

 #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK (0xC00U)

 #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT (10U)

-/*! BLOCK_SET_KEY - Block PUF key code generation. 00 - Enable Key code generation 01, 10, 11 - Disable key code generation

+/*! BLOCK_SET_KEY - Block PUF key code generation

+ *  0b00..Allow PUF Key Code generation

+ *  0b01..Disable PUF Key Code generation

+ *  0b10..Disable PUF Key Code generation

+ *  0b11..Disable PUF Key Code generation

  */

 #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK)

 

 #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK (0x3000U)

 #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT (12U)

-/*! BLOCK_ENROLL - Block PUF enrollement. 00 - Enable enrollment mode 01, 10, 11 - Disable further enrollmnet

+/*! BLOCK_ENROLL - Block PUF enrollement

+ *  0b00..Allow PUF enroll operation

+ *  0b01..Disable PUF enroll operation

+ *  0b10..Disable PUF enroll operation

+ *  0b11..Disable PUF enroll operation

  */

 #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK)

 

@@ -8565,69 +8731,83 @@ typedef struct {
 

 #define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK (0xC0000000U)

 #define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT (30U)

-/*! SEC_BOOT_EN - Secure boot enable. 00 - Plain image (internal flash with or without CRC) 01, 10,

- *    11 - Boot signed images. (internal flash, RSA signed)

+/*! SEC_BOOT_EN - Secure boot enable

+ *  0b00..Plain image (internal flash with or without CRC)

+ *  0b01..Boot signed images. (internal flash, RSA signed)

+ *  0b10..Boot signed images. (internal flash, RSA signed)

+ *  0b11..Boot signed images. (internal flash, RSA signed)

  */

 #define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK)

 /*! @} */

 

-/*! @name PRINCE_BASE_ADDR - . */

+/*! @name PRINCE_BASE_ADDR -  */

 /*! @{ */

 

 #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK (0xFU)

 #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT (0U)

-/*! ADDR0_PRG - Programmable portion of the base address of region 0.

+/*! ADDR0_PRG - Programmable portion of the base address of region 0

  */

 #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK)

 

 #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK (0xF0U)

 #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT (4U)

-/*! ADDR1_PRG - Programmable portion of the base address of region 1.

+/*! ADDR1_PRG - Programmable portion of the base address of region 1

  */

 #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK)

 

 #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK (0xF00U)

 #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT (8U)

-/*! ADDR2_PRG - Programmable portion of the base address of region 2.

+/*! ADDR2_PRG - Programmable portion of the base address of region 2

  */

 #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK)

 

-#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK (0x30000U)

-#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT (16U)

-/*! LOCK_REG0 - Lock PRINCE region0 settings. 00 - Region is not locked. 01, 10, 11 - Region is locked.

+#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK (0xC0000U)

+#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT (18U)

+/*! LOCK_REG0 - Lock PRINCE region0 settings

+ *  0b00..Region is not locked

+ *  0b01..Region is locked

+ *  0b10..Region is locked

+ *  0b11..Region is locked

  */

 #define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK)

 

-#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK (0xC0000U)

-#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT (18U)

-/*! LOCK_REG1 - Lock PRINCE region1 settings. 00 - Region is not locked. 01, 10, 11 - Region is locked.

+#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK (0x300000U)

+#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT (20U)

+/*! LOCK_REG1 - Lock PRINCE region1 settings

+ *  0b00..Region is not locked

+ *  0b01..Region is locked

+ *  0b10..Region is locked

+ *  0b11..Region is locked

  */

 #define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK)

 

-#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_MASK (0x300000U)

-#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_SHIFT (20U)

-/*! LOCK_REG2 - Lock PRINCE region2 settings. 00 - Region is not locked. 01, 10, 11 - Region is locked.

- */

-#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_MASK)

-

 #define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK (0x3000000U)

 #define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT (24U)

-/*! REG0_ERASE_CHECK_EN - For PRINCE region0 enable checking whether all encrypted pages are erased

- *    together. 00 - Check is disabled. 01, 10, 11 - Check is enabled.

+/*! REG0_ERASE_CHECK_EN - For PRINCE region0 enable checking whether all encrypted pages are erased together

+ *  0b00..Region is disabled

+ *  0b01..Region is enabled

+ *  0b10..Region is enabled

+ *  0b11..Region is enabled

  */

 #define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK)

 

 #define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK (0xC000000U)

 #define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT (26U)

-/*! REG1_ERASE_CHECK_EN - For PRINCE region1 enable checking whether all encrypted pages are erased

- *    together. 00 - Check is disabled. 01, 10, 11 - Check is enabled.

+/*! REG1_ERASE_CHECK_EN - For PRINCE region1 enable checking whether all encrypted pages are erased together

+ *  0b00..Region is disabled

+ *  0b01..Region is enabled

+ *  0b10..Region is enabled

+ *  0b11..Region is enabled

  */

 #define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK)

 

 #define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK (0x30000000U)

 #define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT (28U)

-/*! REG2_ERASE_CHECK_EN - For PRINCE region2 enable checking whether all encrypted pages are erased

- *    together. 00 - Check is disabled. 01, 10, 11 - Check is enabled.

+/*! REG2_ERASE_CHECK_EN - For PRINCE region2 enable checking whether all encrypted pages are erased together

+ *  0b00..Region is disabled

+ *  0b01..Region is enabled

+ *  0b10..Region is enabled

+ *  0b11..Region is enabled

  */

 #define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK)

 /*! @} */

@@ -8637,8 +8817,6 @@ typedef struct {
 

 #define FLASH_CMPA_PRINCE_SR_0_FIELD_MASK        (0xFFFFFFFFU)

 #define FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT       (0U)

-/*! FIELD - .

- */

 #define FLASH_CMPA_PRINCE_SR_0_FIELD(x)          (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_0_FIELD_MASK)

 /*! @} */

 

@@ -8647,8 +8825,6 @@ typedef struct {
 

 #define FLASH_CMPA_PRINCE_SR_1_FIELD_MASK        (0xFFFFFFFFU)

 #define FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT       (0U)

-/*! FIELD - .

- */

 #define FLASH_CMPA_PRINCE_SR_1_FIELD(x)          (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_1_FIELD_MASK)

 /*! @} */

 

@@ -8657,8 +8833,6 @@ typedef struct {
 

 #define FLASH_CMPA_PRINCE_SR_2_FIELD_MASK        (0xFFFFFFFFU)

 #define FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT       (0U)

-/*! FIELD - .

- */

 #define FLASH_CMPA_PRINCE_SR_2_FIELD(x)          (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_2_FIELD_MASK)

 /*! @} */

 

@@ -8667,7 +8841,9 @@ typedef struct {
 

 #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U)

 #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U)

-/*! TRIM_VALID - 0 : Capa Bank trimmings not valid. Default trimmings value are used. 1 : Capa Bank trimmings valid.

+/*! TRIM_VALID - XTAL 32kHz capa bank trimmings

+ *  0b0..Capa Bank trimmings not valid. Default trimmings value are used

+ *  0b1..Capa Bank trimmings valid

  */

 #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK)

 

@@ -8695,7 +8871,9 @@ typedef struct {
 

 #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U)

 #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U)

-/*! TRIM_VALID - 0 : Capa Bank trimmings not valid. Default trimmings value are used. 1 : Capa Bank trimmings valid.

+/*! TRIM_VALID - XTAL 16MHz capa bank trimmings

+ *  0b0..Capa Bank trimmings not valid. Default trimmings value are used

+ *  0b1..Capa Bank trimmings valid

  */

 #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK)

 

@@ -8718,13 +8896,11 @@ typedef struct {
 #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK)

 /*! @} */

 

-/*! @name ROTKH - ROTKH0 for Root of Trust Keys Table hash[255:224] ROTKH1 for Root of Trust Keys Table hash[223:192] ROTKH2 for Root of Trust Keys Table hash[191:160] ROTKH3 for Root of Trust Keys Table hash[159:128] ROTKH4 for Root of Trust Keys Table hash[127:96] ROTKH5 for Root of Trust Keys Table hash[95:64] ROTKH6 for Root of Trust Keys Table hash[63:32] ROTKH7 for Root of Trust Keys Table hash[31:0] */

+/*! @name ROTKH - ROTKH0 for Root of Trust Keys Table hash[255:224]..ROTKH7 for Root of Trust Keys Table hash[31:0] */

 /*! @{ */

 

 #define FLASH_CMPA_ROTKH_FIELD_MASK              (0xFFFFFFFFU)

 #define FLASH_CMPA_ROTKH_FIELD_SHIFT             (0U)

-/*! FIELD - .

- */

 #define FLASH_CMPA_ROTKH_FIELD(x)                (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_ROTKH_FIELD_SHIFT)) & FLASH_CMPA_ROTKH_FIELD_MASK)

 /*! @} */

 

@@ -8736,21 +8912,17 @@ typedef struct {
 

 #define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK   (0xFFFFFFFFU)

 #define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT  (0U)

-/*! FIELD - .

- */

 #define FLASH_CMPA_CUSTOMER_DEFINED_FIELD(x)     (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK)

 /*! @} */

 

 /* The count of FLASH_CMPA_CUSTOMER_DEFINED */

 #define FLASH_CMPA_CUSTOMER_DEFINED_COUNT        (56U)

 

-/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] */

+/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224] */

 /*! @{ */

 

 #define FLASH_CMPA_SHA256_DIGEST_FIELD_MASK      (0xFFFFFFFFU)

 #define FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT     (0U)

-/*! FIELD - .

- */

 #define FLASH_CMPA_SHA256_DIGEST_FIELD(x)        (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CMPA_SHA256_DIGEST_FIELD_MASK)

 /*! @} */

 

@@ -8764,7 +8936,7 @@ typedef struct {
 

 

 /* FLASH_CMPA - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral FLASH_CMPA base address */

   #define FLASH_CMPA_BASE                          (0x1009E400u)

   /** Peripheral FLASH_CMPA base address */

@@ -9260,7 +9432,7 @@ typedef struct {
 

 

 /* FLASH_KEY_STORE - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral FLASH_KEY_STORE base address */

   #define FLASH_KEY_STORE_BASE                     (0x1009E600u)

   /** Peripheral FLASH_KEY_STORE base address */

@@ -9417,7 +9589,7 @@ typedef struct {
 

 

 /* FLEXCOMM - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral FLEXCOMM0 base address */

   #define FLEXCOMM0_BASE                           (0x50086000u)

   /** Peripheral FLEXCOMM0 base address */

@@ -9641,7 +9813,7 @@ typedef struct {
 

 

 /* GINT - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral GINT0 base address */

   #define GINT0_BASE                               (0x50002000u)

   /** Peripheral GINT0 base address */

@@ -9925,7 +10097,7 @@ typedef struct {
 

 

 /* GPIO - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral GPIO base address */

   #define GPIO_BASE                                (0x5008C000u)

   /** Peripheral GPIO base address */

@@ -10439,7 +10611,7 @@ typedef struct {
 

 

 /* HASHCRYPT - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral HASHCRYPT base address */

   #define HASHCRYPT_BASE                           (0x500A4000u)

   /** Peripheral HASHCRYPT base address */

@@ -11325,7 +11497,7 @@ typedef struct {
 

 

 /* I2C - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral I2C0 base address */

   #define I2C0_BASE                                (0x50086000u)

   /** Peripheral I2C0 base address */

@@ -11478,7 +11650,8 @@ typedef struct {
        uint8_t RESERVED_6[8];

   __I  uint32_t FIFORDNOPOP;                       /**< FIFO data read with no FIFO pop., offset: 0xE40 */

   __I  uint32_t FIFORD48HNOPOP;                    /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */

-       uint8_t RESERVED_7[436];

+  __I  uint32_t FIFOSIZE;                          /**< FIFO size register, offset: 0xE48 */

+       uint8_t RESERVED_7[432];

   __I  uint32_t ID;                                /**< I2S Module identification, offset: 0xFFC */

 } I2S_Type;

 

@@ -12088,6 +12261,16 @@ typedef struct {
 #define I2S_FIFORD48HNOPOP_RXDATA(x)             (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK)

 /*! @} */

 

+/*! @name FIFOSIZE - FIFO size register */

+/*! @{ */

+

+#define I2S_FIFOSIZE_FIFOSIZE_MASK               (0x1FU)

+#define I2S_FIFOSIZE_FIFOSIZE_SHIFT              (0U)

+/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries.

+ */

+#define I2S_FIFOSIZE_FIFOSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSIZE_FIFOSIZE_SHIFT)) & I2S_FIFOSIZE_FIFOSIZE_MASK)

+/*! @} */

+

 /*! @name ID - I2S Module identification */

 /*! @{ */

 

@@ -12123,7 +12306,7 @@ typedef struct {
 

 

 /* I2S - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral I2S0 base address */

   #define I2S0_BASE                                (0x50086000u)

   /** Peripheral I2S0 base address */

@@ -12536,9 +12719,15 @@ typedef struct {
 

 #define INPUTMUX_FREQMEAS_REF_CLKIN_MASK         (0x1FU)

 #define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT        (0U)

-/*! CLKIN - Clock source number (decimal value) for frequency measure function target clock: 0 =

- *    CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock

- *    (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4

+/*! CLKIN - Clock source number (decimal value) for frequency measure function reference clock:

+ *  0b00000..External main crystal oscilator (Clock_in).

+ *  0b00001..FRO 12MHz clock.

+ *  0b00010..FRO 96MHz clock.

+ *  0b00011..Watchdog oscillator / FRO1MHz clock.

+ *  0b00100..32 kHz oscillator (32k_clk) clock.

+ *  0b00101..main clock (main_clock).

+ *  0b00110..FREQME_GPIO_CLK_A.

+ *  0b00111..FREQME_GPIO_CLK_B.

  */

 #define INPUTMUX_FREQMEAS_REF_CLKIN(x)           (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK)

 /*! @} */

@@ -12548,9 +12737,15 @@ typedef struct {
 

 #define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK      (0x1FU)

 #define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT     (0U)

-/*! CLKIN - Clock source number (decimal value) for frequency measure function target clock: 0 =

- *    CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock

- *    (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4

+/*! CLKIN - Clock source number (decimal value) for frequency measure function target clock:

+ *  0b00000..External main crystal oscilator (Clock_in).

+ *  0b00001..FRO 12MHz clock.

+ *  0b00010..FRO 96MHz clock.

+ *  0b00011..Watchdog oscillator / FRO1MHz clock.

+ *  0b00100..32 kHz oscillator (32k_clk) clock.

+ *  0b00101..main clock (main_clock).

+ *  0b00110..FREQME_GPIO_CLK_A.

+ *  0b00111..FREQME_GPIO_CLK_B.

  */

 #define INPUTMUX_FREQMEAS_TARGET_CLKIN(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK)

 /*! @} */

@@ -12820,7 +13015,7 @@ typedef struct {
 

 

 /* INPUTMUX - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral INPUTMUX base address */

   #define INPUTMUX_BASE                            (0x50006000u)

   /** Peripheral INPUTMUX base address */

@@ -12998,7 +13193,7 @@ typedef struct {
 

 

 /* IOCON - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral IOCON base address */

   #define IOCON_BASE                               (0x50001000u)

   /** Peripheral IOCON base address */

@@ -13117,7 +13312,7 @@ typedef struct {
 

 

 /* MAILBOX - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral MAILBOX base address */

   #define MAILBOX_BASE                             (0x5008B000u)

   /** Peripheral MAILBOX base address */

@@ -13364,7 +13559,7 @@ typedef struct {
 

 

 /* MRT - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral MRT0 base address */

   #define MRT0_BASE                                (0x5000D000u)

   /** Peripheral MRT0 base address */

@@ -13530,7 +13725,7 @@ typedef struct {
 

 

 /* OSTIMER - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral OSTIMER base address */

   #define OSTIMER_BASE                             (0x5002D000u)

   /** Peripheral OSTIMER base address */

@@ -14111,7 +14306,7 @@ typedef struct {
 

 

 /* PINT - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral PINT base address */

   #define PINT_BASE                                (0x50004000u)

   /** Peripheral PINT base address */

@@ -14359,7 +14554,7 @@ typedef struct {
 

 

 /* PLU - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral PLU base address */

   #define PLU_BASE                                 (0x5003D000u)

   /** Peripheral PLU base address */

@@ -14403,27 +14598,41 @@ typedef struct {
 

 /** PMC - Register Layout Typedef */

 typedef struct {

-       uint8_t RESERVED_0[8];

+       uint8_t RESERVED_0[4];

+  __I  uint32_t STATUS;                            /**< Power Management Controller FSM (Finite State Machines) status, offset: 0x4 */

   __IO uint32_t RESETCTRL;                         /**< Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x8 */

-       uint8_t RESERVED_1[36];

+       uint8_t RESERVED_1[4];

+  __IO uint32_t DCDC0;                             /**< DCDC (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x10 */

+  __IO uint32_t DCDC1;                             /**< DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x14 */

+       uint8_t RESERVED_2[4];

+  __IO uint32_t LDOPMU;                            /**< Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x1C */

+       uint8_t RESERVED_3[16];

   __IO uint32_t BODVBAT;                           /**< VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset], offset: 0x30 */

-       uint8_t RESERVED_2[28];

+       uint8_t RESERVED_4[12];

+  __IO uint32_t REFFASTWKUP;                       /**< Analog References fast wake-up Control register [Reset by: PoR], offset: 0x40 */

+       uint8_t RESERVED_5[8];

+  __IO uint32_t XTAL32K;                           /**< 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x4C */

   __IO uint32_t COMP;                              /**< Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x50 */

-       uint8_t RESERVED_3[20];

+       uint8_t RESERVED_6[16];

+  __IO uint32_t WAKEUPIOCTRL;                      /**< Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset], offset: 0x64 */

   __IO uint32_t WAKEIOCAUSE;                       /**< Allows to identify the Wake-up I/O source from Deep Power Down mode, offset: 0x68 */

-       uint8_t RESERVED_4[8];

+       uint8_t RESERVED_7[8];

   __IO uint32_t STATUSCLK;                         /**< FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x74 */

-       uint8_t RESERVED_5[12];

+       uint8_t RESERVED_8[12];

   __IO uint32_t AOREG1;                            /**< General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset], offset: 0x84 */

-       uint8_t RESERVED_6[16];

+       uint8_t RESERVED_9[8];

+  __IO uint32_t MISCCTRL;                          /**< Dummy Control bus to PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x90 */

+       uint8_t RESERVED_10[4];

   __IO uint32_t RTCOSC32K;                         /**< RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x98 */

-  __IO uint32_t OSTIMERr;                          /**< OS Timer control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x9C */

-       uint8_t RESERVED_7[24];

+  __IO uint32_t OSTIMERr;                          /**< OS Timer control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x9C, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'OSTIMER' */

+       uint8_t RESERVED_11[24];

   __IO uint32_t PDRUNCFG0;                         /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xB8 */

-       uint8_t RESERVED_8[4];

+       uint8_t RESERVED_12[4];

   __O  uint32_t PDRUNCFGSET0;                      /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC0 */

-       uint8_t RESERVED_9[4];

+       uint8_t RESERVED_13[4];

   __O  uint32_t PDRUNCFGCLR0;                      /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC8 */

+       uint8_t RESERVED_14[8];

+  __IO uint32_t SRAMCTRL;                          /**< All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset], offset: 0xD4 */

 } PMC_Type;

 

 /* ----------------------------------------------------------------------------

@@ -14435,6 +14644,20 @@ typedef struct {
  * @{

  */

 

+/*! @name STATUS - Power Management Controller FSM (Finite State Machines) status */

+/*! @{ */

+

+#define PMC_STATUS_BOOTMODE_MASK                 (0xC0000U)

+#define PMC_STATUS_BOOTMODE_SHIFT                (18U)

+/*! BOOTMODE - Latest IC Boot cause:.

+ *  0b00..Latest IC boot was a Full power cycle boot sequence (PoR, Pin Reset, Brown Out Detectors Reset, Software Reset).

+ *  0b01..Latest IC boot was from DEEP SLEEP low power mode.

+ *  0b10..Latest IC boot was from POWER DOWN low power mode.

+ *  0b11..Latest IC boot was from DEEP POWER DOWN low power mode.

+ */

+#define PMC_STATUS_BOOTMODE(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_BOOTMODE_SHIFT)) & PMC_STATUS_BOOTMODE_MASK)

+/*! @} */

+

 /*! @name RESETCTRL - Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */

 /*! @{ */

 

@@ -14454,6 +14677,14 @@ typedef struct {
  */

 #define PMC_RESETCTRL_BODVBATRESETENABLE(x)      (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT)) & PMC_RESETCTRL_BODVBATRESETENABLE_MASK)

 

+#define PMC_RESETCTRL_BODCORERESETENABLE_MASK    (0x4U)

+#define PMC_RESETCTRL_BODCORERESETENABLE_SHIFT   (2U)

+/*! BODCORERESETENABLE - BOD CORE reset enable.

+ *  0b0..BOD CORE reset is disable.

+ *  0b1..BOD CORE reset is enable.

+ */

+#define PMC_RESETCTRL_BODCORERESETENABLE(x)      (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODCORERESETENABLE_SHIFT)) & PMC_RESETCTRL_BODCORERESETENABLE_MASK)

+

 #define PMC_RESETCTRL_SWRRESETENABLE_MASK        (0x8U)

 #define PMC_RESETCTRL_SWRRESETENABLE_SHIFT       (3U)

 /*! SWRRESETENABLE - Software reset enable.

@@ -14463,6 +14694,239 @@ typedef struct {
 #define PMC_RESETCTRL_SWRRESETENABLE(x)          (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_SWRRESETENABLE_SHIFT)) & PMC_RESETCTRL_SWRRESETENABLE_MASK)

 /*! @} */

 

+/*! @name DCDC0 - DCDC (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */

+/*! @{ */

+

+#define PMC_DCDC0_RC_MASK                        (0x3FU)

+#define PMC_DCDC0_RC_SHIFT                       (0U)

+/*! RC - Constant On-Time calibration.

+ */

+#define PMC_DCDC0_RC(x)                          (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_RC_SHIFT)) & PMC_DCDC0_RC_MASK)

+

+#define PMC_DCDC0_ICOMP_MASK                     (0xC0U)

+#define PMC_DCDC0_ICOMP_SHIFT                    (6U)

+/*! ICOMP - Select the type of ZCD comparator.

+ */

+#define PMC_DCDC0_ICOMP(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ICOMP_SHIFT)) & PMC_DCDC0_ICOMP_MASK)

+

+#define PMC_DCDC0_ISEL_MASK                      (0x300U)

+#define PMC_DCDC0_ISEL_SHIFT                     (8U)

+/*! ISEL - Alter Internal biasing currents.

+ */

+#define PMC_DCDC0_ISEL(x)                        (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ISEL_SHIFT)) & PMC_DCDC0_ISEL_MASK)

+

+#define PMC_DCDC0_ICENABLE_MASK                  (0x400U)

+#define PMC_DCDC0_ICENABLE_SHIFT                 (10U)

+/*! ICENABLE - Selection of auto scaling of COT period with variations in VDD.

+ */

+#define PMC_DCDC0_ICENABLE(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ICENABLE_SHIFT)) & PMC_DCDC0_ICENABLE_MASK)

+

+#define PMC_DCDC0_TMOS_MASK                      (0xF800U)

+#define PMC_DCDC0_TMOS_SHIFT                     (11U)

+/*! TMOS - One-shot generator reference current trimming signal.

+ */

+#define PMC_DCDC0_TMOS(x)                        (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_TMOS_SHIFT)) & PMC_DCDC0_TMOS_MASK)

+

+#define PMC_DCDC0_DISABLEISENSE_MASK             (0x10000U)

+#define PMC_DCDC0_DISABLEISENSE_SHIFT            (16U)

+/*! DISABLEISENSE - Disable Current sensing.

+ */

+#define PMC_DCDC0_DISABLEISENSE(x)               (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_DISABLEISENSE_SHIFT)) & PMC_DCDC0_DISABLEISENSE_MASK)

+

+#define PMC_DCDC0_VOUT_MASK                      (0x1E0000U)

+#define PMC_DCDC0_VOUT_SHIFT                     (17U)

+/*! VOUT - Set output regulation voltage.

+ *  0b0000..0.95 V.

+ *  0b0001..0.975 V.

+ *  0b0010..1 V.

+ *  0b0011..1.025 V.

+ *  0b0100..1.05 V.

+ *  0b0101..1.075 V.

+ *  0b0110..1.1 V.

+ *  0b0111..1.125 V.

+ *  0b1000..1.15 V.

+ *  0b1001..1.175 V.

+ *  0b1010..1.2 V.

+ */

+#define PMC_DCDC0_VOUT(x)                        (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_VOUT_SHIFT)) & PMC_DCDC0_VOUT_MASK)

+

+#define PMC_DCDC0_SLICINGENABLE_MASK             (0x200000U)

+#define PMC_DCDC0_SLICINGENABLE_SHIFT            (21U)

+/*! SLICINGENABLE - Enable staggered switching of power switches.

+ */

+#define PMC_DCDC0_SLICINGENABLE(x)               (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_SLICINGENABLE_SHIFT)) & PMC_DCDC0_SLICINGENABLE_MASK)

+

+#define PMC_DCDC0_INDUCTORCLAMPENABLE_MASK       (0x400000U)

+#define PMC_DCDC0_INDUCTORCLAMPENABLE_SHIFT      (22U)

+/*! INDUCTORCLAMPENABLE - Enable shorting of Inductor during PFM idle time.

+ */

+#define PMC_DCDC0_INDUCTORCLAMPENABLE(x)         (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_INDUCTORCLAMPENABLE_SHIFT)) & PMC_DCDC0_INDUCTORCLAMPENABLE_MASK)

+

+#define PMC_DCDC0_VOUT_PWD_MASK                  (0x7800000U)

+#define PMC_DCDC0_VOUT_PWD_SHIFT                 (23U)

+/*! VOUT_PWD - Set output regulation voltage during Deep Sleep.

+ */

+#define PMC_DCDC0_VOUT_PWD(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_VOUT_PWD_SHIFT)) & PMC_DCDC0_VOUT_PWD_MASK)

+/*! @} */

+

+/*! @name DCDC1 - DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */

+/*! @{ */

+

+#define PMC_DCDC1_RTRIMOFFET_MASK                (0xFU)

+#define PMC_DCDC1_RTRIMOFFET_SHIFT               (0U)

+/*! RTRIMOFFET - Adjust the offset voltage of BJT based comparator.

+ */

+#define PMC_DCDC1_RTRIMOFFET(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_RTRIMOFFET_SHIFT)) & PMC_DCDC1_RTRIMOFFET_MASK)

+

+#define PMC_DCDC1_RSENSETRIM_MASK                (0xF0U)

+#define PMC_DCDC1_RSENSETRIM_SHIFT               (4U)

+/*! RSENSETRIM - Adjust Max inductor peak current limiting.

+ */

+#define PMC_DCDC1_RSENSETRIM(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_RSENSETRIM_SHIFT)) & PMC_DCDC1_RSENSETRIM_MASK)

+

+#define PMC_DCDC1_DTESTENABLE_MASK               (0x100U)

+#define PMC_DCDC1_DTESTENABLE_SHIFT              (8U)

+/*! DTESTENABLE - Enable Digital test signals.

+ */

+#define PMC_DCDC1_DTESTENABLE(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_DTESTENABLE_SHIFT)) & PMC_DCDC1_DTESTENABLE_MASK)

+

+#define PMC_DCDC1_SETCURVE_MASK                  (0x600U)

+#define PMC_DCDC1_SETCURVE_SHIFT                 (9U)

+/*! SETCURVE - Bandgap calibration parameter.

+ */

+#define PMC_DCDC1_SETCURVE(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_SETCURVE_SHIFT)) & PMC_DCDC1_SETCURVE_MASK)

+

+#define PMC_DCDC1_SETDC_MASK                     (0x7800U)

+#define PMC_DCDC1_SETDC_SHIFT                    (11U)

+/*! SETDC - Bandgap calibration parameter.

+ */

+#define PMC_DCDC1_SETDC(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_SETDC_SHIFT)) & PMC_DCDC1_SETDC_MASK)

+

+#define PMC_DCDC1_DTESTSEL_MASK                  (0x38000U)

+#define PMC_DCDC1_DTESTSEL_SHIFT                 (15U)

+/*! DTESTSEL - Select the output signal for test.

+ */

+#define PMC_DCDC1_DTESTSEL(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_DTESTSEL_SHIFT)) & PMC_DCDC1_DTESTSEL_MASK)

+

+#define PMC_DCDC1_ISCALEENABLE_MASK              (0x40000U)

+#define PMC_DCDC1_ISCALEENABLE_SHIFT             (18U)

+/*! ISCALEENABLE - Modify COT behavior.

+ */

+#define PMC_DCDC1_ISCALEENABLE(x)                (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_ISCALEENABLE_SHIFT)) & PMC_DCDC1_ISCALEENABLE_MASK)

+

+#define PMC_DCDC1_FORCEBYPASS_MASK               (0x80000U)

+#define PMC_DCDC1_FORCEBYPASS_SHIFT              (19U)

+/*! FORCEBYPASS - Force bypass mode.

+ */

+#define PMC_DCDC1_FORCEBYPASS(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_FORCEBYPASS_SHIFT)) & PMC_DCDC1_FORCEBYPASS_MASK)

+

+#define PMC_DCDC1_TRIMAUTOCOT_MASK               (0xF00000U)

+#define PMC_DCDC1_TRIMAUTOCOT_SHIFT              (20U)

+/*! TRIMAUTOCOT - Change the scaling ratio of the feedforward compensation.

+ */

+#define PMC_DCDC1_TRIMAUTOCOT(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TRIMAUTOCOT_SHIFT)) & PMC_DCDC1_TRIMAUTOCOT_MASK)

+

+#define PMC_DCDC1_FORCEFULLCYCLE_MASK            (0x1000000U)

+#define PMC_DCDC1_FORCEFULLCYCLE_SHIFT           (24U)

+/*! FORCEFULLCYCLE - Force full PFM PMOS and NMOS cycle.

+ */

+#define PMC_DCDC1_FORCEFULLCYCLE(x)              (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_FORCEFULLCYCLE_SHIFT)) & PMC_DCDC1_FORCEFULLCYCLE_MASK)

+

+#define PMC_DCDC1_LCENABLE_MASK                  (0x2000000U)

+#define PMC_DCDC1_LCENABLE_SHIFT                 (25U)

+/*! LCENABLE - Change the range of the peak detector of current inside the inductor.

+ */

+#define PMC_DCDC1_LCENABLE(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_LCENABLE_SHIFT)) & PMC_DCDC1_LCENABLE_MASK)

+

+#define PMC_DCDC1_TOFF_MASK                      (0x7C000000U)

+#define PMC_DCDC1_TOFF_SHIFT                     (26U)

+/*! TOFF - Constant Off-Time calibration input.

+ */

+#define PMC_DCDC1_TOFF(x)                        (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TOFF_SHIFT)) & PMC_DCDC1_TOFF_MASK)

+

+#define PMC_DCDC1_TOFFENABLE_MASK                (0x80000000U)

+#define PMC_DCDC1_TOFFENABLE_SHIFT               (31U)

+/*! TOFFENABLE - Enable Constant Off-Time feature.

+ */

+#define PMC_DCDC1_TOFFENABLE(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TOFFENABLE_SHIFT)) & PMC_DCDC1_TOFFENABLE_MASK)

+/*! @} */

+

+/*! @name LDOPMU - Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */

+/*! @{ */

+

+#define PMC_LDOPMU_VADJ_MASK                     (0x1FU)

+#define PMC_LDOPMU_VADJ_SHIFT                    (0U)

+/*! VADJ - Sets the Always-On domain LDO output level.

+ *  0b00000..1.22 V.

+ *  0b00001..0.7 V.

+ *  0b00010..0.725 V.

+ *  0b00011..0.75 V.

+ *  0b00100..0.775 V.

+ *  0b00101..0.8 V.

+ *  0b00110..0.825 V.

+ *  0b00111..0.85 V.

+ *  0b01000..0.875 V.

+ *  0b01001..0.9 V.

+ *  0b01010..0.96 V.

+ *  0b01011..0.97 V.

+ *  0b01100..0.98 V.

+ *  0b01101..0.99 V.

+ *  0b01110..1 V.

+ *  0b01111..1.01 V.

+ *  0b10000..1.02 V.

+ *  0b10001..1.03 V.

+ *  0b10010..1.04 V.

+ *  0b10011..1.05 V.

+ *  0b10100..1.06 V.

+ *  0b10101..1.07 V.

+ *  0b10110..1.08 V.

+ *  0b10111..1.09 V.

+ *  0b11000..1.1 V.

+ *  0b11001..1.11 V.

+ *  0b11010..1.12 V.

+ *  0b11011..1.13 V.

+ *  0b11100..1.14 V.

+ *  0b11101..1.15 V.

+ *  0b11110..1.16 V.

+ *  0b11111..1.22 V.

+ */

+#define PMC_LDOPMU_VADJ(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_SHIFT)) & PMC_LDOPMU_VADJ_MASK)

+

+#define PMC_LDOPMU_VADJ_PWD_MASK                 (0x3E0U)

+#define PMC_LDOPMU_VADJ_PWD_SHIFT                (5U)

+/*! VADJ_PWD - Sets the Always-On domain LDO output level in all power down modes.

+ */

+#define PMC_LDOPMU_VADJ_PWD(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_PWD_SHIFT)) & PMC_LDOPMU_VADJ_PWD_MASK)

+

+#define PMC_LDOPMU_VADJ_BOOST_MASK               (0x7C00U)

+#define PMC_LDOPMU_VADJ_BOOST_SHIFT              (10U)

+/*! VADJ_BOOST - Sets the Always-On domain LDO Boost output level.

+ */

+#define PMC_LDOPMU_VADJ_BOOST(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_BOOST_SHIFT)) & PMC_LDOPMU_VADJ_BOOST_MASK)

+

+#define PMC_LDOPMU_VADJ_BOOST_PWD_MASK           (0xF8000U)

+#define PMC_LDOPMU_VADJ_BOOST_PWD_SHIFT          (15U)

+/*! VADJ_BOOST_PWD - Sets the Always-On domain LDO Boost output level in all power down modes.

+ */

+#define PMC_LDOPMU_VADJ_BOOST_PWD(x)             (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_BOOST_PWD_SHIFT)) & PMC_LDOPMU_VADJ_BOOST_PWD_MASK)

+

+#define PMC_LDOPMU_BOOST_ENA_MASK                (0x1000000U)

+#define PMC_LDOPMU_BOOST_ENA_SHIFT               (24U)

+/*! BOOST_ENA - Control the LDO AO boost mode in ACTIVE mode.

+ *  0b0..LDO AO Boost Mode is disable.

+ *  0b1..LDO AO Boost Mode is enable.

+ */

+#define PMC_LDOPMU_BOOST_ENA(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_BOOST_ENA_SHIFT)) & PMC_LDOPMU_BOOST_ENA_MASK)

+

+#define PMC_LDOPMU_BOOST_ENA_PWD_MASK            (0x2000000U)

+#define PMC_LDOPMU_BOOST_ENA_PWD_SHIFT           (25U)

+/*! BOOST_ENA_PWD - Control the LDO AO boost mode in the different low power modes (DEEP SLEEP, POWERDOWN, and DEEP POWER DOWN).

+ *  0b0..LDO AO Boost Mode is disable.

+ *  0b1..LDO AO Boost Mode is enable.

+ */

+#define PMC_LDOPMU_BOOST_ENA_PWD(x)              (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_BOOST_ENA_PWD_SHIFT)) & PMC_LDOPMU_BOOST_ENA_PWD_MASK)

+/*! @} */

+

 /*! @name BODVBAT - VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset] */

 /*! @{ */

 

@@ -14515,6 +14979,94 @@ typedef struct {
 #define PMC_BODVBAT_HYST(x)                      (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_HYST_SHIFT)) & PMC_BODVBAT_HYST_MASK)

 /*! @} */

 

+/*! @name REFFASTWKUP - Analog References fast wake-up Control register [Reset by: PoR] */

+/*! @{ */

+

+#define PMC_REFFASTWKUP_LPWKUP_MASK              (0x1U)

+#define PMC_REFFASTWKUP_LPWKUP_SHIFT             (0U)

+/*! LPWKUP - Analog References fast wake-up in case of wake-up from a low power mode (DEEP SLEEP, POWER DOWN and DEEP POWER DOWN): .

+ *  0b0..Analog References fast wake-up feature is disabled in case of wake-up from any Low power mode.

+ *  0b1..Analog References fast wake-up feature is enabled in case of wake-up from any Low power mode.

+ */

+#define PMC_REFFASTWKUP_LPWKUP(x)                (((uint32_t)(((uint32_t)(x)) << PMC_REFFASTWKUP_LPWKUP_SHIFT)) & PMC_REFFASTWKUP_LPWKUP_MASK)

+

+#define PMC_REFFASTWKUP_HWWKUP_MASK              (0x2U)

+#define PMC_REFFASTWKUP_HWWKUP_SHIFT             (1U)

+/*! HWWKUP - Analog References fast wake-up in case of Hardware Pin reset: .

+ *  0b0..Analog References fast wake-up feature is disabled in case of Hardware Pin reset.

+ *  0b1..Analog References fast wake-up feature is enabled in case of Hardware Pin reset.

+ */

+#define PMC_REFFASTWKUP_HWWKUP(x)                (((uint32_t)(((uint32_t)(x)) << PMC_REFFASTWKUP_HWWKUP_SHIFT)) & PMC_REFFASTWKUP_HWWKUP_MASK)

+/*! @} */

+

+/*! @name XTAL32K - 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset] */

+/*! @{ */

+

+#define PMC_XTAL32K_IREF_MASK                    (0x6U)

+#define PMC_XTAL32K_IREF_SHIFT                   (1U)

+/*! IREF - reference output current selection inputs.

+ */

+#define PMC_XTAL32K_IREF(x)                      (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IREF_SHIFT)) & PMC_XTAL32K_IREF_MASK)

+

+#define PMC_XTAL32K_TEST_MASK                    (0x8U)

+#define PMC_XTAL32K_TEST_SHIFT                   (3U)

+/*! TEST - Oscillator Test Mode.

+ */

+#define PMC_XTAL32K_TEST(x)                      (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_TEST_SHIFT)) & PMC_XTAL32K_TEST_MASK)

+

+#define PMC_XTAL32K_IBIAS_MASK                   (0x30U)

+#define PMC_XTAL32K_IBIAS_SHIFT                  (4U)

+/*! IBIAS - bias current selection inputs.

+ */

+#define PMC_XTAL32K_IBIAS(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IBIAS_SHIFT)) & PMC_XTAL32K_IBIAS_MASK)

+

+#define PMC_XTAL32K_AMPL_MASK                    (0xC0U)

+#define PMC_XTAL32K_AMPL_SHIFT                   (6U)

+/*! AMPL - oscillator amplitude selection inputs.

+ */

+#define PMC_XTAL32K_AMPL(x)                      (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_AMPL_SHIFT)) & PMC_XTAL32K_AMPL_MASK)

+

+#define PMC_XTAL32K_CAPBANKIN_MASK               (0x7F00U)

+#define PMC_XTAL32K_CAPBANKIN_SHIFT              (8U)

+/*! CAPBANKIN - Capa bank setting input.

+ */

+#define PMC_XTAL32K_CAPBANKIN(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKIN_SHIFT)) & PMC_XTAL32K_CAPBANKIN_MASK)

+

+#define PMC_XTAL32K_CAPBANKOUT_MASK              (0x3F8000U)

+#define PMC_XTAL32K_CAPBANKOUT_SHIFT             (15U)

+/*! CAPBANKOUT - Capa bank setting output.

+ */

+#define PMC_XTAL32K_CAPBANKOUT(x)                (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKOUT_SHIFT)) & PMC_XTAL32K_CAPBANKOUT_MASK)

+

+#define PMC_XTAL32K_CAPTESTSTARTSRCSEL_MASK      (0x400000U)

+#define PMC_XTAL32K_CAPTESTSTARTSRCSEL_SHIFT     (22U)

+/*! CAPTESTSTARTSRCSEL - Source selection for xo32k_captest_start_ao_set.

+ *  0b0..Sourced from CAPTESTSTART.

+ *  0b1..Sourced from calibration.

+ */

+#define PMC_XTAL32K_CAPTESTSTARTSRCSEL(x)        (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTSTARTSRCSEL_SHIFT)) & PMC_XTAL32K_CAPTESTSTARTSRCSEL_MASK)

+

+#define PMC_XTAL32K_CAPTESTSTART_MASK            (0x800000U)

+#define PMC_XTAL32K_CAPTESTSTART_SHIFT           (23U)

+/*! CAPTESTSTART - Start test.

+ */

+#define PMC_XTAL32K_CAPTESTSTART(x)              (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTSTART_SHIFT)) & PMC_XTAL32K_CAPTESTSTART_MASK)

+

+#define PMC_XTAL32K_CAPTESTENABLE_MASK           (0x1000000U)

+#define PMC_XTAL32K_CAPTESTENABLE_SHIFT          (24U)

+/*! CAPTESTENABLE - Enable signal for cap test.

+ */

+#define PMC_XTAL32K_CAPTESTENABLE(x)             (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTENABLE_SHIFT)) & PMC_XTAL32K_CAPTESTENABLE_MASK)

+

+#define PMC_XTAL32K_CAPTESTOSCINSEL_MASK         (0x2000000U)

+#define PMC_XTAL32K_CAPTESTOSCINSEL_SHIFT        (25U)

+/*! CAPTESTOSCINSEL - Select the input for test.

+ *  0b0..Oscillator output pin (osc_out).

+ *  0b1..Oscillator input pin (osc_in).

+ */

+#define PMC_XTAL32K_CAPTESTOSCINSEL(x)           (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTOSCINSEL_SHIFT)) & PMC_XTAL32K_CAPTESTOSCINSEL_MASK)

+/*! @} */

+

 /*! @name COMP - Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */

 /*! @{ */

 

@@ -14574,17 +15126,121 @@ typedef struct {
 

 #define PMC_COMP_FILTERCGF_SAMPLEMODE_MASK       (0x30000U)

 #define PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT      (16U)

-/*! FILTERCGF_SAMPLEMODE - Filter Sample mode.

+/*! FILTERCGF_SAMPLEMODE - Control the filtering of the Analog Comparator output.

+ *  0b00..Bypass mode.

+ *  0b01..Filter 1 clock period.

+ *  0b10..Filter 2 clock period.

+ *  0b11..Filter 3 clock period.

  */

 #define PMC_COMP_FILTERCGF_SAMPLEMODE(x)         (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT)) & PMC_COMP_FILTERCGF_SAMPLEMODE_MASK)

 

 #define PMC_COMP_FILTERCGF_CLKDIV_MASK           (0x1C0000U)

 #define PMC_COMP_FILTERCGF_CLKDIV_SHIFT          (18U)

-/*! FILTERCGF_CLKDIV - Filter Clock div .

+/*! FILTERCGF_CLKDIV - Filter Clock divider.

+ *  0b000..Filter clock period duration equals 1 Analog Comparator clock period.

+ *  0b001..Filter clock period duration equals 2 Analog Comparator clock period.

+ *  0b010..Filter clock period duration equals 4 Analog Comparator clock period.

+ *  0b011..Filter clock period duration equals 8 Analog Comparator clock period.

+ *  0b100..Filter clock period duration equals 16 Analog Comparator clock period.

+ *  0b101..Filter clock period duration equals 32 Analog Comparator clock period.

+ *  0b110..Filter clock period duration equals 64 Analog Comparator clock period.

+ *  0b111..Filter clock period duration equals 128 Analog Comparator clock period.

  */

 #define PMC_COMP_FILTERCGF_CLKDIV(x)             (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_CLKDIV_SHIFT)) & PMC_COMP_FILTERCGF_CLKDIV_MASK)

 /*! @} */

 

+/*! @name WAKEUPIOCTRL - Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset] */

+/*! @{ */

+

+#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_MASK  (0x1U)

+#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_SHIFT (0U)

+/*! RISINGEDGEWAKEUP0 - Enable / disable detection of rising edge events on Wake Up 0 pin in Deep Power Down modes:.

+ *  0b0..Rising edge detection is disable.

+ *  0b1..Rising edge detection is enable.

+ */

+#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0(x)    (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_MASK)

+

+#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_MASK (0x2U)

+#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_SHIFT (1U)

+/*! FALLINGEDGEWAKEUP0 - Enable / disable detection of falling edge events on Wake Up 0 pin in Deep Power Down modes:.

+ *  0b0..Falling edge detection is disable.

+ *  0b1..Falling edge detection is enable.

+ */

+#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0(x)   (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_MASK)

+

+#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_MASK  (0x4U)

+#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_SHIFT (2U)

+/*! RISINGEDGEWAKEUP1 - Enable / disable detection of rising edge events on Wake Up 1 pin in Deep Power Down modes:.

+ *  0b0..Rising edge detection is disable.

+ *  0b1..Rising edge detection is enable.

+ */

+#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1(x)    (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_MASK)

+

+#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_MASK (0x8U)

+#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_SHIFT (3U)

+/*! FALLINGEDGEWAKEUP1 - Enable / disable detection of falling edge events on Wake Up 1 pin in Deep Power Down modes:.

+ *  0b0..Falling edge detection is disable.

+ *  0b1..Falling edge detection is enable.

+ */

+#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1(x)   (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_MASK)

+

+#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_MASK  (0x10U)

+#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_SHIFT (4U)

+/*! RISINGEDGEWAKEUP2 - Enable / disable detection of rising edge events on Wake Up 2 pin in Deep Power Down modes:.

+ *  0b0..Rising edge detection is disable.

+ *  0b1..Rising edge detection is enable.

+ */

+#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2(x)    (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_MASK)

+

+#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_MASK (0x20U)

+#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_SHIFT (5U)

+/*! FALLINGEDGEWAKEUP2 - Enable / disable detection of falling edge events on Wake Up 2 pin in Deep Power Down modes:.

+ *  0b0..Falling edge detection is disable.

+ *  0b1..Falling edge detection is enable.

+ */

+#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2(x)   (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_MASK)

+

+#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_MASK  (0x40U)

+#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_SHIFT (6U)

+/*! RISINGEDGEWAKEUP3 - Enable / disable detection of rising edge events on Wake Up 3 pin in Deep Power Down modes:.

+ *  0b0..Rising edge detection is disable.

+ *  0b1..Rising edge detection is enable.

+ */

+#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3(x)    (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_MASK)

+

+#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_MASK (0x80U)

+#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_SHIFT (7U)

+/*! FALLINGEDGEWAKEUP3 - Enable / disable detection of falling edge events on Wake Up 3 pin in Deep Power Down modes:.

+ *  0b0..Falling edge detection is disable.

+ *  0b1..Falling edge detection is enable.

+ */

+#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3(x)   (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_MASK)

+

+#define PMC_WAKEUPIOCTRL_MODEWAKEUP0_MASK        (0x100U)

+#define PMC_WAKEUPIOCTRL_MODEWAKEUP0_SHIFT       (8U)

+/*! MODEWAKEUP0 - Configure wake up I/O 0 in Deep Power Down mode

+ */

+#define PMC_WAKEUPIOCTRL_MODEWAKEUP0(x)          (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP0_MASK)

+

+#define PMC_WAKEUPIOCTRL_MODEWAKEUP1_MASK        (0x200U)

+#define PMC_WAKEUPIOCTRL_MODEWAKEUP1_SHIFT       (9U)

+/*! MODEWAKEUP1 - Configure wake up I/O 1 in Deep Power Down mode

+ */

+#define PMC_WAKEUPIOCTRL_MODEWAKEUP1(x)          (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP1_MASK)

+

+#define PMC_WAKEUPIOCTRL_MODEWAKEUP2_MASK        (0x400U)

+#define PMC_WAKEUPIOCTRL_MODEWAKEUP2_SHIFT       (10U)

+/*! MODEWAKEUP2 - Configure wake up I/O 2 in Deep Power Down mode

+ */

+#define PMC_WAKEUPIOCTRL_MODEWAKEUP2(x)          (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP2_MASK)

+

+#define PMC_WAKEUPIOCTRL_MODEWAKEUP3_MASK        (0x800U)

+#define PMC_WAKEUPIOCTRL_MODEWAKEUP3_SHIFT       (11U)

+/*! MODEWAKEUP3 - Configure wake up I/O 3 in Deep Power Down mode

+ */

+#define PMC_WAKEUPIOCTRL_MODEWAKEUP3(x)          (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP3_MASK)

+/*! @} */

+

 /*! @name WAKEIOCAUSE - Allows to identify the Wake-up I/O source from Deep Power Down mode */

 /*! @{ */

 

@@ -14633,8 +15289,8 @@ typedef struct {
 #define PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK     (0x4U)

 #define PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT    (2U)

 /*! XTAL32KOSCFAILURE - XTAL32 KHZ oscillator oscillation failure detection indicator.

- *  0b0..No oscillation failure has been detetced since the last time this bit has been cleared..

- *  0b1..At least one oscillation failure has been detetced since the last time this bit has been cleared..

+ *  0b0..No oscillation failure has been detetced since the last time this bit has been cleared.

+ *  0b1..At least one oscillation failure has been detetced since the last time this bit has been cleared.

  */

 #define PMC_STATUSCLK_XTAL32KOSCFAILURE(x)       (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT)) & PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK)

 /*! @} */

@@ -14703,6 +15359,84 @@ typedef struct {
 #define PMC_AOREG1_BOOTERRORCOUNTER(x)           (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BOOTERRORCOUNTER_SHIFT)) & PMC_AOREG1_BOOTERRORCOUNTER_MASK)

 /*! @} */

 

+/*! @name MISCCTRL - Dummy Control bus to PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */

+/*! @{ */

+

+#define PMC_MISCCTRL_LDODEEPSLEEPREF_MASK        (0x1U)

+#define PMC_MISCCTRL_LDODEEPSLEEPREF_SHIFT       (0U)

+/*! LDODEEPSLEEPREF - Select LDO Deep Sleep reference source.

+ *  0b0..LDO DEEP Sleep uses Flash buffer biasing as reference.

+ *  0b1..LDO DEEP Sleep uses Band Gap 0.8V as reference.

+ */

+#define PMC_MISCCTRL_LDODEEPSLEEPREF(x)          (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LDODEEPSLEEPREF_SHIFT)) & PMC_MISCCTRL_LDODEEPSLEEPREF_MASK)

+

+#define PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK        (0x2U)

+#define PMC_MISCCTRL_LDOMEMHIGHZMODE_SHIFT       (1U)

+/*! LDOMEMHIGHZMODE - Control the activation of LDO MEM High Z mode.

+ *  0b0..LDO MEM High Z mode is disabled.

+ *  0b1..LDO MEM High Z mode is enabled.

+ */

+#define PMC_MISCCTRL_LDOMEMHIGHZMODE(x)          (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LDOMEMHIGHZMODE_SHIFT)) & PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK)

+

+#define PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK       (0x4U)

+#define PMC_MISCCTRL_LOWPWR_FLASH_BUF_SHIFT      (2U)

+#define PMC_MISCCTRL_LOWPWR_FLASH_BUF(x)         (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LOWPWR_FLASH_BUF_SHIFT)) & PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK)

+

+#define PMC_MISCCTRL_MISCCTRL_3_8_MASK           (0xF8U)

+#define PMC_MISCCTRL_MISCCTRL_3_8_SHIFT          (3U)

+/*! MISCCTRL_3_8 - Reserved.

+ */

+#define PMC_MISCCTRL_MISCCTRL_3_8(x)             (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MISCCTRL_3_8_SHIFT)) & PMC_MISCCTRL_MISCCTRL_3_8_MASK)

+

+#define PMC_MISCCTRL_MODEWAKEUP0_MASK            (0x100U)

+#define PMC_MISCCTRL_MODEWAKEUP0_SHIFT           (8U)

+/*! MODEWAKEUP0 - Configure wake up I/O 0 in Deep Power Down mode

+ */

+#define PMC_MISCCTRL_MODEWAKEUP0(x)              (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP0_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP0_MASK)

+

+#define PMC_MISCCTRL_MODEWAKEUP1_MASK            (0x200U)

+#define PMC_MISCCTRL_MODEWAKEUP1_SHIFT           (9U)

+/*! MODEWAKEUP1 - Configure wake up I/O 1 in Deep Power Down mode

+ */

+#define PMC_MISCCTRL_MODEWAKEUP1(x)              (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP1_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP1_MASK)

+

+#define PMC_MISCCTRL_MODEWAKEUP2_MASK            (0x400U)

+#define PMC_MISCCTRL_MODEWAKEUP2_SHIFT           (10U)

+/*! MODEWAKEUP2 - Configure wake up I/O 2 in Deep Power Down mode

+ */

+#define PMC_MISCCTRL_MODEWAKEUP2(x)              (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP2_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP2_MASK)

+

+#define PMC_MISCCTRL_MODEWAKEUP3_MASK            (0x800U)

+#define PMC_MISCCTRL_MODEWAKEUP3_SHIFT           (11U)

+/*! MODEWAKEUP3 - Configure wake up I/O 3 in Deep Power Down mode

+ */

+#define PMC_MISCCTRL_MODEWAKEUP3(x)              (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP3_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP3_MASK)

+

+#define PMC_MISCCTRL_DISABLE_BLEED_MASK          (0x1000U)

+#define PMC_MISCCTRL_DISABLE_BLEED_SHIFT         (12U)

+/*! DISABLE_BLEED - Controls LDO MEM bleed current. This field is expected to be controlled by the

+ *    Low Power Software only in DEEP SLEEP low power mode.

+ *  0b0..LDO_MEM bleed current is enabled.

+ *  0b1..LDO_MEM bleed current is disabled. Should be set before entering in Deep Sleep low power mode and cleared

+ *       after wake up from Deep SLeep low power mode.

+ */

+#define PMC_MISCCTRL_DISABLE_BLEED(x)            (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_DISABLE_BLEED_SHIFT)) & PMC_MISCCTRL_DISABLE_BLEED_MASK)

+

+#define PMC_MISCCTRL_MISCCTRL_13_14_MASK         (0x6000U)

+#define PMC_MISCCTRL_MISCCTRL_13_14_SHIFT        (13U)

+/*! MISCCTRL_13_14 - Reserved.

+ */

+#define PMC_MISCCTRL_MISCCTRL_13_14(x)           (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MISCCTRL_13_14_SHIFT)) & PMC_MISCCTRL_MISCCTRL_13_14_MASK)

+

+#define PMC_MISCCTRL_WAKUPIO_RST_MASK            (0x8000U)

+#define PMC_MISCCTRL_WAKUPIO_RST_SHIFT           (15U)

+/*! WAKUPIO_RST - WAKEUP IO event detector reset control.

+ *  0b1..Wakeup IO is reset.

+ *  0b0..Wakeup IO is not reset.

+ */

+#define PMC_MISCCTRL_WAKUPIO_RST(x)              (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_WAKUPIO_RST_SHIFT)) & PMC_MISCCTRL_WAKUPIO_RST_MASK)

+/*! @} */

+

 /*! @name RTCOSC32K - RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset] */

 /*! @{ */

 

@@ -14802,9 +15536,9 @@ typedef struct {
 

 #define PMC_PDRUNCFG0_PDEN_XTAL32M_MASK          (0x100U)

 #define PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT         (8U)

-/*! PDEN_XTAL32M - Controls power to crystal 32 MHz.

- *  0b0..Crystal 32MHz is powered.

- *  0b1..Crystal 32MHz is powered down.

+/*! PDEN_XTAL32M - Controls power to high speed crystal.

+ *  0b0..High speed crystal is powered.

+ *  0b1..High speed crystal is powered down.

  */

 #define PMC_PDRUNCFG0_PDEN_XTAL32M(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32M_MASK)

 

@@ -14866,9 +15600,9 @@ typedef struct {
 

 #define PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK         (0x100000U)

 #define PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT        (20U)

-/*! PDEN_LDOXO32M - Controls power to crystal 32 MHz LDO.

- *  0b0..crystal 32 MHz LDO is powered.

- *  0b1..crystal 32 MHz LDO is powered down.

+/*! PDEN_LDOXO32M - Controls power to high speed crystal LDO.

+ *  0b0..High speed crystal LDO is powered.

+ *  0b1..High speed crystal LDO is powered down.

  */

 #define PMC_PDRUNCFG0_PDEN_LDOXO32M(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK)

 

@@ -14909,6 +15643,38 @@ typedef struct {
 #define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0(x)         (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT)) & PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK)

 /*! @} */

 

+/*! @name SRAMCTRL - All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] */

+/*! @{ */

+

+#define PMC_SRAMCTRL_SMB_MASK                    (0x3U)

+#define PMC_SRAMCTRL_SMB_SHIFT                   (0U)

+/*! SMB - Source Biasing voltage.

+ *  0b00..Low leakage.

+ *  0b01..Medium leakage.

+ *  0b10..Highest leakage.

+ *  0b11..Disable.

+ */

+#define PMC_SRAMCTRL_SMB(x)                      (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_SMB_SHIFT)) & PMC_SRAMCTRL_SMB_MASK)

+

+#define PMC_SRAMCTRL_RM_MASK                     (0x1CU)

+#define PMC_SRAMCTRL_RM_SHIFT                    (2U)

+/*! RM - Read Margin control settings.

+ */

+#define PMC_SRAMCTRL_RM(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_RM_SHIFT)) & PMC_SRAMCTRL_RM_MASK)

+

+#define PMC_SRAMCTRL_WM_MASK                     (0xE0U)

+#define PMC_SRAMCTRL_WM_SHIFT                    (5U)

+/*! WM - Write Margin control settings.

+ */

+#define PMC_SRAMCTRL_WM(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_WM_SHIFT)) & PMC_SRAMCTRL_WM_MASK)

+

+#define PMC_SRAMCTRL_WRME_MASK                   (0x100U)

+#define PMC_SRAMCTRL_WRME_SHIFT                  (8U)

+/*! WRME - Write read margin enable.

+ */

+#define PMC_SRAMCTRL_WRME(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_WRME_SHIFT)) & PMC_SRAMCTRL_WRME_MASK)

+/*! @} */

+

 

 /*!

  * @}

@@ -14916,7 +15682,7 @@ typedef struct {
 

 

 /* PMC - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral PMC base address */

   #define PMC_BASE                                 (0x50020000u)

   /** Peripheral PMC base address */

@@ -15393,7 +16159,7 @@ typedef struct {
 

 

 /* POWERQUAD - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral POWERQUAD base address */

   #define POWERQUAD_BASE                           (0x500A6000u)

   /** Peripheral POWERQUAD base address */

@@ -15677,7 +16443,7 @@ typedef struct {
 

 

 /* PRINCE - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral PRINCE base address */

   #define PRINCE_BASE                              (0x50035000u)

   /** Peripheral PRINCE base address */

@@ -16447,7 +17213,7 @@ typedef struct {
 

 

 /* PUF - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral PUF base address */

   #define PUF_BASE                                 (0x5003B000u)

   /** Peripheral PUF base address */

@@ -16637,7 +17403,7 @@ typedef struct {
 

 

 /* RNG - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral RNG base address */

   #define RNG_BASE                                 (0x5003A000u)

   /** Peripheral RNG base address */

@@ -16869,7 +17635,7 @@ typedef struct {
 

 

 /* RTC - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral RTC base address */

   #define RTC_BASE                                 (0x5002C000u)

   /** Peripheral RTC base address */

@@ -18547,7 +19313,7 @@ typedef struct {
 

 

 /* SCT - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral SCT0 base address */

   #define SCT0_BASE                                (0x50085000u)

   /** Peripheral SCT0 base address */

@@ -19732,7 +20498,7 @@ typedef struct {
 

 

 /* SDIF - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral SDIF base address */

   #define SDIF_BASE                                (0x5009B000u)

   /** Peripheral SDIF base address */

@@ -19801,7 +20567,9 @@ typedef struct {
   __I  uint32_t FIFORD;                            /**< FIFO read data., offset: 0xE30 */

        uint8_t RESERVED_6[12];

   __I  uint32_t FIFORDNOPOP;                       /**< FIFO data read with no FIFO pop., offset: 0xE40 */

-       uint8_t RESERVED_7[440];

+       uint8_t RESERVED_7[4];

+  __I  uint32_t FIFOSIZE;                          /**< FIFO size register, offset: 0xE48 */

+       uint8_t RESERVED_8[432];

   __I  uint32_t ID;                                /**< Peripheral identification register., offset: 0xFFC */

 } SPI_Type;

 

@@ -20549,6 +21317,16 @@ typedef struct {
 #define SPI_FIFORDNOPOP_SOT(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK)

 /*! @} */

 

+/*! @name FIFOSIZE - FIFO size register */

+/*! @{ */

+

+#define SPI_FIFOSIZE_FIFOSIZE_MASK               (0x1FU)

+#define SPI_FIFOSIZE_FIFOSIZE_SHIFT              (0U)

+/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries.

+ */

+#define SPI_FIFOSIZE_FIFOSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSIZE_FIFOSIZE_SHIFT)) & SPI_FIFOSIZE_FIFOSIZE_MASK)

+/*! @} */

+

 /*! @name ID - Peripheral identification register. */

 /*! @{ */

 

@@ -20584,7 +21362,7 @@ typedef struct {
 

 

 /* SPI - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral SPI0 base address */

   #define SPI0_BASE                                (0x50086000u)

   /** Peripheral SPI0 base address */

@@ -20858,7 +21636,7 @@ typedef struct {
   __IO uint32_t USB1NEEDCLKCTRL;                   /**< USB1 need clock control, offset: 0x424 */

   __I  uint32_t USB1NEEDCLKSTAT;                   /**< USB1 need clock status, offset: 0x428 */

        uint8_t RESERVED_28[52];

-  __O  uint32_t SDIOCLKCTRL;                       /**< SDIO CCLKIN phase and delay control, offset: 0x460 */

+  __IO uint32_t SDIOCLKCTRL;                       /**< SDIO CCLKIN phase and delay control, offset: 0x460 */

        uint8_t RESERVED_29[252];

   __IO uint32_t PLL1CTRL;                          /**< PLL1 550m control, offset: 0x560 */

   __I  uint32_t PLL1STAT;                          /**< PLL1 550m status, offset: 0x564 */

@@ -20872,29 +21650,31 @@ typedef struct {
   __IO uint32_t PLL0PDEC;                          /**< PLL0 550m P divider, offset: 0x58C */

   __IO uint32_t PLL0SSCG0;                         /**< PLL0 Spread Spectrum Wrapper control register 0, offset: 0x590 */

   __IO uint32_t PLL0SSCG1;                         /**< PLL0 Spread Spectrum Wrapper control register 1, offset: 0x594 */

-       uint8_t RESERVED_31[616];

+       uint8_t RESERVED_31[364];

+  __IO uint32_t FUNCRETENTIONCTRL;                 /**< Functional retention control register, offset: 0x704 */

+       uint8_t RESERVED_32[248];

   __IO uint32_t CPUCTRL;                           /**< CPU Control for multiple processors, offset: 0x800 */

   __IO uint32_t CPBOOT;                            /**< Coprocessor Boot Address, offset: 0x804 */

-       uint8_t RESERVED_32[4];

+       uint8_t RESERVED_33[4];

   __I  uint32_t CPSTAT;                            /**< CPU Status, offset: 0x80C */

-       uint8_t RESERVED_33[520];

+       uint8_t RESERVED_34[520];

   __IO uint32_t CLOCK_CTRL;                        /**< Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures, offset: 0xA18 */

-       uint8_t RESERVED_34[244];

+       uint8_t RESERVED_35[244];

   __IO uint32_t COMP_INT_CTRL;                     /**< Comparator Interrupt control, offset: 0xB10 */

   __I  uint32_t COMP_INT_STATUS;                   /**< Comparator Interrupt status, offset: 0xB14 */

-       uint8_t RESERVED_35[748];

+       uint8_t RESERVED_36[748];

   __IO uint32_t AUTOCLKGATEOVERRIDE;               /**< Control automatic clock gating, offset: 0xE04 */

   __IO uint32_t GPIOPSYNC;                         /**< Enable bypass of the first stage of synchonization inside GPIO_INT module, offset: 0xE08 */

-       uint8_t RESERVED_36[404];

+       uint8_t RESERVED_37[404];

   __IO uint32_t DEBUG_LOCK_EN;                     /**< Control write access to security registers., offset: 0xFA0 */

   __IO uint32_t DEBUG_FEATURES;                    /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control., offset: 0xFA4 */

   __IO uint32_t DEBUG_FEATURES_DP;                 /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register., offset: 0xFA8 */

-       uint8_t RESERVED_37[16];

+       uint8_t RESERVED_38[16];

   __O  uint32_t KEY_BLOCK;                         /**< block quiddikey/PUF all index., offset: 0xFBC */

   __IO uint32_t DEBUG_AUTH_BEACON;                 /**< Debug authentication BEACON register, offset: 0xFC0 */

-       uint8_t RESERVED_38[16];

+       uint8_t RESERVED_39[16];

   __IO uint32_t CPUCFG;                            /**< CPUs configuration register, offset: 0xFD4 */

-       uint8_t RESERVED_39[32];

+       uint8_t RESERVED_40[32];

   __I  uint32_t DEVICE_ID0;                        /**< Device ID, offset: 0xFF8 */

   __I  uint32_t DIEID;                             /**< Chip revision ID and Number, offset: 0xFFC */

 } SYSCON_Type;

@@ -23976,6 +24756,30 @@ typedef struct {
 #define SYSCON_PLL0SSCG1_SEL_EXT(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)) & SYSCON_PLL0SSCG1_SEL_EXT_MASK)

 /*! @} */

 

+/*! @name FUNCRETENTIONCTRL - Functional retention control register */

+/*! @{ */

+

+#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_MASK (0x1U)

+#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_SHIFT (0U)

+/*! FUNCRETENA - functional retention in power down only.

+ *  0b1..enable functional retention.

+ *  0b0..disable functional retention.

+ */

+#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_MASK)

+

+#define SYSCON_FUNCRETENTIONCTRL_RET_START_MASK  (0x3FFEU)

+#define SYSCON_FUNCRETENTIONCTRL_RET_START_SHIFT (1U)

+/*! RET_START - Start address divided by 4 inside SRAMX bank.

+ */

+#define SYSCON_FUNCRETENTIONCTRL_RET_START(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_RET_START_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_RET_START_MASK)

+

+#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK  (0xFFC000U)

+#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH_SHIFT (14U)

+/*! RET_LENTH - lenth of Scan chains to save.

+ */

+#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_RET_LENTH_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK)

+/*! @} */

+

 /*! @name CPUCTRL - CPU Control for multiple processors */

 /*! @{ */

 

@@ -24508,7 +25312,7 @@ typedef struct {
 

 

 /* SYSCON - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral SYSCON base address */

   #define SYSCON_BASE                              (0x50000000u)

   /** Peripheral SYSCON base address */

@@ -24753,7 +25557,7 @@ typedef struct {
 

 

 /* SYSCTL - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral SYSCTL base address */

   #define SYSCTL_BASE                              (0x50023000u)

   /** Peripheral SYSCTL base address */

@@ -24821,7 +25625,9 @@ typedef struct {
   __I  uint32_t FIFORD;                            /**< FIFO read data., offset: 0xE30 */

        uint8_t RESERVED_5[12];

   __I  uint32_t FIFORDNOPOP;                       /**< FIFO data read with no FIFO pop., offset: 0xE40 */

-       uint8_t RESERVED_6[440];

+       uint8_t RESERVED_6[4];

+  __I  uint32_t FIFOSIZE;                          /**< FIFO size register, offset: 0xE48 */

+       uint8_t RESERVED_7[432];

   __I  uint32_t ID;                                /**< Peripheral identification register., offset: 0xFFC */

 } USART_Type;

 

@@ -25738,6 +26544,16 @@ typedef struct {
 #define USART_FIFORDNOPOP_RXNOISE(x)             (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK)

 /*! @} */

 

+/*! @name FIFOSIZE - FIFO size register */

+/*! @{ */

+

+#define USART_FIFOSIZE_FIFOSIZE_MASK             (0x1FU)

+#define USART_FIFOSIZE_FIFOSIZE_SHIFT            (0U)

+/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries.

+ */

+#define USART_FIFOSIZE_FIFOSIZE(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOSIZE_FIFOSIZE_SHIFT)) & USART_FIFOSIZE_FIFOSIZE_MASK)

+/*! @} */

+

 /*! @name ID - Peripheral identification register. */

 /*! @{ */

 

@@ -25773,7 +26589,7 @@ typedef struct {
 

 

 /* USART - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral USART0 base address */

   #define USART0_BASE                              (0x50086000u)

   /** Peripheral USART0 base address */

@@ -26398,7 +27214,7 @@ typedef struct {
 

 

 /* USB - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral USB0 base address */

   #define USB0_BASE                                (0x50084000u)

   /** Peripheral USB0 base address */

@@ -27111,7 +27927,7 @@ typedef struct {
 

 

 /* USBFSH - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral USBFSH base address */

   #define USBFSH_BASE                              (0x500A2000u)

   /** Peripheral USBFSH base address */

@@ -27296,7 +28112,13 @@ typedef struct {
 

 #define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK     (0xE0000000U)

 #define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT    (29U)

-/*! PHY_TEST_MODE - This field is written by firmware to put the PHY into a test mode as defined by the USB2.0 specification

+/*! PHY_TEST_MODE - This field is written by firmware to put the PHY into a test mode as defined by the USB2.0 specification.

+ *  0b000..Test mode disabled.

+ *  0b001..Test_J.

+ *  0b010..Test_K.

+ *  0b011..Test_SE0_NAK.

+ *  0b100..Test_Packet.

+ *  0b101..Test_Force_Enable.

  */

 #define USBHSD_DEVCMDSTAT_PHY_TEST_MODE(x)       (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT)) & USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK)

 /*! @} */

@@ -27561,7 +28383,7 @@ typedef struct {
 

 

 /* USBHSD - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral USBHSD base address */

   #define USBHSD_BASE                              (0x50094000u)

   /** Peripheral USBHSD base address */

@@ -28092,7 +28914,7 @@ typedef struct {
 

 

 /* USBHSH - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral USBHSH base address */

   #define USBHSH_BASE                              (0x500A3000u)

   /** Peripheral USBHSH base address */

@@ -28167,7 +28989,7 @@ typedef struct {
   __IO uint32_t USB1_VBUS_DETECT_CLR;              /**< USB PHY VBUS Detect Control Register, offset: 0xC8 */

   __IO uint32_t USB1_VBUS_DETECT_TOG;              /**< USB PHY VBUS Detect Control Register, offset: 0xCC */

        uint8_t RESERVED_2[48];

-  __IO uint32_t ANACTRLr;                          /**< USB PHY Analog Control Register, offset: 0x100 */

+  __IO uint32_t ANACTRLr;                          /**< USB PHY Analog Control Register, offset: 0x100, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'ANACTRL' */

   __IO uint32_t ANACTRL_SET;                       /**< USB PHY Analog Control Register, offset: 0x104 */

   __IO uint32_t ANACTRL_CLR;                       /**< USB PHY Analog Control Register, offset: 0x108 */

   __IO uint32_t ANACTRL_TOG;                       /**< USB PHY Analog Control Register, offset: 0x10C */

@@ -29909,7 +30731,7 @@ typedef struct {
 

 

 /* USBPHY - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral USBPHY base address */

   #define USBPHY_BASE                              (0x50038000u)

   /** Peripheral USBPHY base address */

@@ -30113,7 +30935,7 @@ typedef struct {
 

 

 /* UTICK - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral UTICK0 base address */

   #define UTICK0_BASE                              (0x5000E000u)

   /** Peripheral UTICK0 base address */

@@ -30280,7 +31102,7 @@ typedef struct {
 

 

 /* WWDT - Peripheral instance base addresses */

-#if (__ARM_FEATURE_CMSE & 0x2)

+#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))

   /** Peripheral WWDT base address */

   #define WWDT_BASE                                (0x5000C000u)

   /** Peripheral WWDT base address */

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/LPC55S69_cm33_core0_features.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/LPC55S69_cm33_core0_features.h
index 0f6415e6e..bcf164cf2 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/LPC55S69_cm33_core0_features.h
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/LPC55S69_cm33_core0_features.h
@@ -1,13 +1,13 @@
 /*

 ** ###################################################################

 **     Version:             rev. 1.1, 2019-05-16

-**     Build:               b210318

+**     Build:               b220725

 **

 **     Abstract:

 **         Chip specific module features.

 **

 **     Copyright 2016 Freescale Semiconductor, Inc.

-**     Copyright 2016-2021 NXP

+**     Copyright 2016-2022 NXP

 **     All rights reserved.

 **

 **     SPDX-License-Identifier: BSD-3-Clause

@@ -61,6 +61,8 @@
 #define FSL_FEATURE_SOC_LPADC_COUNT (1)

 /* @brief MAILBOX availability on the SoC. */

 #define FSL_FEATURE_SOC_MAILBOX_COUNT (1)

+/* @brief MPU availability on the SoC. */

+#define FSL_FEATURE_SOC_MPU_COUNT (1)

 /* @brief MRT availability on the SoC. */

 #define FSL_FEATURE_SOC_MRT_COUNT (1)

 /* @brief OSTIMER availability on the SoC. */

@@ -138,6 +140,20 @@
 #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0)

 /* @brief Has offset trim (register OFSTRIM). */

 #define FSL_FEATURE_LPADC_HAS_OFSTRIM (1)

+/* @brief Has Trigger status register. */

+#define FSL_FEATURE_LPADC_HAS_TSTAT (1)

+/* @brief Has power select (bitfield CFG[PWRSEL]). */

+#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1)

+/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */

+#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0)

+/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */

+#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0)

+/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */

+#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0)

+/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */

+#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0)

+/* @brief Conversion averaged bitfiled width. */

+#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3)

 /* @brief Has internal temperature sensor. */

 #define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1)

 /* @brief Temperature sensor parameter A (slope). */

@@ -149,6 +165,15 @@
 /* @brief the buffer size of temperature sensor. */

 #define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (4U)

 

+/* ANALOGCTRL module features */

+

+/* @brief Has PLL_USB_OUT_BIT_FIELD bitfile in XO32M_CTRL reigster. */

+#define FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD (1)

+/* @brief Has XO32M_ADC_CLK_MODE bitfile in DUMMY_CTRL reigster. */

+#define FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD (0)

+/* @brief Has auxiliary bias(register AUX_BIAS). */

+#define FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG (1)

+

 /* CASPER module features */

 

 /* @brief Base address of the CASPER dedicated RAM */

@@ -160,7 +185,18 @@
 

 /* CTIMER module features */

 

-/* No feature definitions */

+/* @brief CTIMER has no capture channel. */

+#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0)

+/* @brief CTIMER has no capture 2 interrupt. */

+#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0)

+/* @brief CTIMER capture 3 interrupt. */

+#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1)

+/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */

+#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0)

+/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */

+#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1)

+/* @brief CTIMER Has register MSR */

+#define FSL_FEATURE_CTIMER_HAS_MSR (1)

 

 /* DMA module features */

 

@@ -242,6 +278,11 @@
 /* @brief I2S has DMIC interconnection */

 #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0)

 

+/* GINT module features */

+

+/* @brief The count of th port which are supported in GINT. */

+#define FSL_FEATURE_GINT_PORT_COUNT (2)

+

 /* HASHCRYPT module features */

 

 /* @brief the address of alias offset */

@@ -334,6 +375,11 @@
 /* @brief Number of connected outputs */

 #define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2)

 

+/* SPI module features */

+

+/* @brief SSEL pin count. */

+#define FSL_FEATURE_SPI_SSEL_COUNT (4)

+

 /* SYSCON module features */

 

 /* @brief Flash page size in bytes */

@@ -341,7 +387,7 @@
 /* @brief Flash sector size in bytes */

 #define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)

 /* @brief Flash size in bytes */

-#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (622592)

+#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (645120)

 /* @brief Has Power Down mode */

 #define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1)

 /* @brief CCM_ANALOG availability on the SoC.  */

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/system_LPC55S69_cm33_core0.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/system_LPC55S69_cm33_core0.c
index 7211d10eb..2e004a3d5 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/system_LPC55S69_cm33_core0.c
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/system_LPC55S69_cm33_core0.c
@@ -11,7 +11,7 @@
 **

 **     Reference manual:    LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3  16 May 2019

 **     Version:             rev. 1.1, 2019-05-16

-**     Build:               b200418

+**     Build:               b220117

 **

 **     Abstract:

 **         Provides a system configuration function and a global variable that

@@ -19,7 +19,7 @@
 **         the oscillator (PLL) that is part of the microcontroller device.

 **

 **     Copyright 2016 Freescale Semiconductor, Inc.

-**     Copyright 2016-2020 NXP

+**     Copyright 2016-2022 NXP

 **     All rights reserved.

 **

 **     SPDX-License-Identifier: BSD-3-Clause

@@ -116,7 +116,7 @@ static float findPll0MMult(void)
                        (float)(uint32_t)(1UL << PLL_SSCG_MD_INT_P));

         mMult       = (float)mMult_int + mMult_fract;

     }

-    if (mMult == 0.0F)

+    if (0ULL == ((uint64_t)mMult))

     {

         mMult = 1.0F;

     }

@@ -238,7 +238,7 @@ uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
    -- SystemInit()

    ---------------------------------------------------------------------------- */

 

-__attribute__((weak)) void SystemInit (void) {

+__attribute__ ((weak)) void SystemInit (void) {

 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))

   SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access in Secure mode */

   #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/system_LPC55S69_cm33_core0.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/system_LPC55S69_cm33_core0.h
index e53f426b2..e38b8fdf9 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/system_LPC55S69_cm33_core0.h
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/system_LPC55S69_cm33_core0.h
@@ -11,7 +11,7 @@
 **

 **     Reference manual:    LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3  16 May 2019

 **     Version:             rev. 1.1, 2019-05-16

-**     Build:               b200418

+**     Build:               b220117

 **

 **     Abstract:

 **         Provides a system configuration function and a global variable that

@@ -19,7 +19,7 @@
 **         the oscillator (PLL) that is part of the microcontroller device.

 **

 **     Copyright 2016 Freescale Semiconductor, Inc.

-**     Copyright 2016-2020 NXP

+**     Copyright 2016-2022 NXP

 **     All rights reserved.

 **

 **     SPDX-License-Identifier: BSD-3-Clause

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_clock.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_clock.c
index 117d27eda..730943b9d 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_clock.c
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_clock.c
@@ -1,5 +1,5 @@
 /*

- * Copyright 2017 - 2020 , NXP

+ * Copyright 2017 - 2021 , NXP

  * All rights reserved.

  *

  * SPDX-License-Identifier: BSD-3-Clause

@@ -127,7 +127,7 @@ void CLOCK_AttachClk(clock_attach_id_t connection)
                 sel = GET_ID_ITEM_SEL(item);

                 if (mux == CM_RTCOSC32KCLKSEL)

                 {

-                    PMC->RTCOSC32K |= sel;

+                    PMC->RTCOSC32K = (PMC->RTCOSC32K & ~PMC_RTCOSC32K_SEL_MASK) | PMC_RTCOSC32K_SEL(sel);

                 }

                 else

                 {

@@ -388,7 +388,7 @@ void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq)
 /* Set EXT OSC Clk */

 /**

  * brief   Initialize the external osc clock to given frequency.

- * Crystal oscillator with an operating frequency of 12 MHz to 32 MHz. 

+ * Crystal oscillator with an operating frequency of 12 MHz to 32 MHz.

  * Option for external clock input (bypass mode) for clock frequencies of up to 25 MHz.

  * param   iFreq   : Desired frequency (must be equal to exact rate in Hz)

  * return  returns success or fail status.

@@ -848,12 +848,14 @@ uint32_t CLOCK_GetFlexCommInputClock(uint32_t id)
 /* Get FLEXCOMM Clk */

 uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id)

 {

-    uint32_t freq = 0U;

-    uint32_t temp;

-

-    freq = CLOCK_GetFlexCommInputClock(id);

-    temp = SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_MULT_MASK;

-    return freq / (1U + (temp) / ((SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_DIV_MASK) + 1U));

+    uint32_t freq   = 0U;

+    uint32_t frgMul = 0U;

+    uint32_t frgDiv = 0U;

+

+    freq   = CLOCK_GetFlexCommInputClock(id);

+    frgMul = (SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_MULT_MASK) >> 8U;

+    frgDiv = SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_DIV_MASK;

+    return (uint32_t)(((uint64_t)freq * ((uint64_t)frgDiv + 1ULL)) / (frgMul + frgDiv + 1UL));

 }

 

 /* Get HS_LPSI Clk */

@@ -1159,7 +1161,7 @@ static float findPll0MMult(void)
                        (float)(uint32_t)(1UL << PLL0_SSCG_MD_INT_P));

         mMult       = (float)mMult_int + mMult_fract;

     }

-    if (mMult == 0.0F)

+    if (0ULL == ((uint64_t)mMult))

     {

         mMult = 1.0F;

     }

@@ -1882,7 +1884,8 @@ bool CLOCK_EnableUsbfs0DeviceClock(clock_usbfs_src_t src, uint32_t freq)
         /* Turn ON FRO HF */

         POWER_DisablePD(kPDRUNCFG_PD_FRO192M);

         /* Enable FRO 96MHz output */

-        ANACTRL->FRO192M_CTRL = ANACTRL->FRO192M_CTRL | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK | ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK;

+        ANACTRL->FRO192M_CTRL =

+            ANACTRL->FRO192M_CTRL | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK | ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK;

         /* Select FRO 96 or 48 MHz */

         CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);

     }

@@ -2093,3 +2096,11 @@ bool CLOCK_EnableUsbhs0HostClock(clock_usbhs_src_t src, uint32_t freq)
 

     return true;

 }

+

+/*! @brief Enable the OSTIMER 32k clock.

+ *  @return  Nothing

+ */

+void CLOCK_EnableOstimer32kClock(void)

+{

+    PMC->OSTIMERr |= PMC_OSTIMER_CLOCKENABLE_MASK;

+}

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_clock.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_clock.h
index f70c55990..be1a8fc38 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_clock.h
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_clock.h
@@ -1492,6 +1492,11 @@ bool CLOCK_EnableUsbhs0DeviceClock(clock_usbhs_src_t src, uint32_t freq);
  */

 bool CLOCK_EnableUsbhs0HostClock(clock_usbhs_src_t src, uint32_t freq);

 

+/*! @brief Enable the OSTIMER 32k clock.

+ *  @return  Nothing

+ */

+void CLOCK_EnableOstimer32kClock(void);

+

 #if defined(__cplusplus)

 }

 #endif /* __cplusplus */

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common.c
index aa1394d05..f7483b9f1 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common.c
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common.c
@@ -21,13 +21,14 @@ typedef struct _mem_align_control_block
 #define FSL_COMPONENT_ID "platform.drivers.common"

 #endif

 

+#if !((defined(__DSC__) && defined(__CW__)))

 void *SDK_Malloc(size_t size, size_t alignbytes)

 {

     mem_align_cb_t *p_cb = NULL;

     uint32_t alignedsize;

 

     /* Check overflow. */

-    alignedsize = SDK_SIZEALIGN(size, alignbytes);

+    alignedsize = (uint32_t)(unsigned int)SDK_SIZEALIGN(size, alignbytes);

     if (alignedsize < size)

     {

         return NULL;

@@ -38,15 +39,15 @@ void *SDK_Malloc(size_t size, size_t alignbytes)
         return NULL;

     }

 

-    alignedsize += alignbytes + sizeof(mem_align_cb_t);

+    alignedsize += alignbytes + (uint32_t)sizeof(mem_align_cb_t);

 

     union

     {

         void *pointer_value;

-        uint32_t unsigned_value;

+        uintptr_t unsigned_value;

     } p_align_addr, p_addr;

 

-    p_addr.pointer_value = malloc(alignedsize);

+    p_addr.pointer_value = malloc((size_t)alignedsize);

 

     if (p_addr.pointer_value == NULL)

     {

@@ -67,7 +68,7 @@ void SDK_Free(void *ptr)
     union

     {

         void *pointer_value;

-        uint32_t unsigned_value;

+        uintptr_t unsigned_value;

     } p_free;

     p_free.pointer_value = ptr;

     mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U);

@@ -81,3 +82,4 @@ void SDK_Free(void *ptr)
 

     free(p_free.pointer_value);

 }

+#endif

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common.h
index 09a668e05..7662c0cc9 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common.h
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common.h
@@ -1,6 +1,6 @@
 /*

  * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.

- * Copyright 2016-2021 NXP

+ * Copyright 2016-2022 NXP

  * All rights reserved.

  *

  * SPDX-License-Identifier: BSD-3-Clause

@@ -40,142 +40,163 @@
  ******************************************************************************/

 

 /*! @brief Construct a status code value from a group and code number. */

-#define MAKE_STATUS(group, code) ((((group)*100) + (code)))

+#define MAKE_STATUS(group, code) ((((group)*100L) + (code)))

 

-/*! @brief Construct the version number for drivers. */

-#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))

+/*! @brief Construct the version number for drivers.

+ *

+ * The driver version is a 32-bit number, for both 32-bit platforms(such as Cortex M)

+ * and 16-bit platforms(such as DSC).

+ *

+ * @verbatim

+

+   | Unused    || Major Version || Minor Version ||  Bug Fix    |

+   31        25  24           17  16            9  8            0

+

+   @endverbatim

+ */

+#define MAKE_VERSION(major, minor, bugfix) (((major)*65536L) + ((minor)*256L) + (bugfix))

 

 /*! @name Driver version */

 /*@{*/

 /*! @brief common driver version. */

-#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))

+#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))

 /*@}*/

 

 /* Debug console type definition. */

-#define DEBUG_CONSOLE_DEVICE_TYPE_NONE          0U      /*!< No debug console.             */

-#define DEBUG_CONSOLE_DEVICE_TYPE_UART          1U      /*!< Debug console based on UART.   */

-#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART        2U      /*!< Debug console based on LPUART. */

-#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI         3U      /*!< Debug console based on LPSCI.  */

-#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC        4U      /*!< Debug console based on USBCDC. */

-#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM      5U      /*!< Debug console based on FLEXCOMM. */

-#define DEBUG_CONSOLE_DEVICE_TYPE_IUART         6U      /*!< Debug console based on i.MX UART. */

-#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART        7U      /*!< Debug console based on LPC_VUSART. */

-#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART    8U      /*!< Debug console based on LPC_USART. */

-#define DEBUG_CONSOLE_DEVICE_TYPE_SWO           9U      /*!< Debug console based on SWO. */

-#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI          10U     /*!< Debug console based on QSCI. */

+#define DEBUG_CONSOLE_DEVICE_TYPE_NONE       0U  /*!< No debug console.             */

+#define DEBUG_CONSOLE_DEVICE_TYPE_UART       1U  /*!< Debug console based on UART.   */

+#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART     2U  /*!< Debug console based on LPUART. */

+#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI      3U  /*!< Debug console based on LPSCI.  */

+#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC     4U  /*!< Debug console based on USBCDC. */

+#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM   5U  /*!< Debug console based on FLEXCOMM. */

+#define DEBUG_CONSOLE_DEVICE_TYPE_IUART      6U  /*!< Debug console based on i.MX UART. */

+#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART     7U  /*!< Debug console based on LPC_VUSART. */

+#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U  /*!< Debug console based on LPC_USART. */

+#define DEBUG_CONSOLE_DEVICE_TYPE_SWO        9U  /*!< Debug console based on SWO. */

+#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI       10U /*!< Debug console based on QSCI. */

 

 /*! @brief Status group numbers. */

 enum _status_groups

 {

-    kStatusGroup_Generic = 0,                 /*!< Group number for generic status codes. */

-    kStatusGroup_FLASH = 1,                   /*!< Group number for FLASH status codes. */

-    kStatusGroup_LPSPI = 4,                   /*!< Group number for LPSPI status codes. */

-    kStatusGroup_FLEXIO_SPI = 5,              /*!< Group number for FLEXIO SPI status codes. */

-    kStatusGroup_DSPI = 6,                    /*!< Group number for DSPI status codes. */

-    kStatusGroup_FLEXIO_UART = 7,             /*!< Group number for FLEXIO UART status codes. */

-    kStatusGroup_FLEXIO_I2C = 8,              /*!< Group number for FLEXIO I2C status codes. */

-    kStatusGroup_LPI2C = 9,                   /*!< Group number for LPI2C status codes. */

-    kStatusGroup_UART = 10,                   /*!< Group number for UART status codes. */

-    kStatusGroup_I2C = 11,                    /*!< Group number for UART status codes. */

-    kStatusGroup_LPSCI = 12,                  /*!< Group number for LPSCI status codes. */

-    kStatusGroup_LPUART = 13,                 /*!< Group number for LPUART status codes. */

-    kStatusGroup_SPI = 14,                    /*!< Group number for SPI status code.*/

-    kStatusGroup_XRDC = 15,                   /*!< Group number for XRDC status code.*/

-    kStatusGroup_SEMA42 = 16,                 /*!< Group number for SEMA42 status code.*/

-    kStatusGroup_SDHC = 17,                   /*!< Group number for SDHC status code */

-    kStatusGroup_SDMMC = 18,                  /*!< Group number for SDMMC status code */

-    kStatusGroup_SAI = 19,                    /*!< Group number for SAI status code */

-    kStatusGroup_MCG = 20,                    /*!< Group number for MCG status codes. */

-    kStatusGroup_SCG = 21,                    /*!< Group number for SCG status codes. */

-    kStatusGroup_SDSPI = 22,                  /*!< Group number for SDSPI status codes. */

-    kStatusGroup_FLEXIO_I2S = 23,             /*!< Group number for FLEXIO I2S status codes */

-    kStatusGroup_FLEXIO_MCULCD = 24,          /*!< Group number for FLEXIO LCD status codes */

-    kStatusGroup_FLASHIAP = 25,               /*!< Group number for FLASHIAP status codes */

-    kStatusGroup_FLEXCOMM_I2C = 26,           /*!< Group number for FLEXCOMM I2C status codes */

-    kStatusGroup_I2S = 27,                    /*!< Group number for I2S status codes */

-    kStatusGroup_IUART = 28,                  /*!< Group number for IUART status codes */

-    kStatusGroup_CSI = 29,                    /*!< Group number for CSI status codes */

-    kStatusGroup_MIPI_DSI = 30,               /*!< Group number for MIPI DSI status codes */

-    kStatusGroup_SDRAMC = 35,                 /*!< Group number for SDRAMC status codes. */

-    kStatusGroup_POWER = 39,                  /*!< Group number for POWER status codes. */

-    kStatusGroup_ENET = 40,                   /*!< Group number for ENET status codes. */

-    kStatusGroup_PHY = 41,                    /*!< Group number for PHY status codes. */

-    kStatusGroup_TRGMUX = 42,                 /*!< Group number for TRGMUX status codes. */

-    kStatusGroup_SMARTCARD = 43,              /*!< Group number for SMARTCARD status codes. */

-    kStatusGroup_LMEM = 44,                   /*!< Group number for LMEM status codes. */

-    kStatusGroup_QSPI = 45,                   /*!< Group number for QSPI status codes. */

-    kStatusGroup_DMA = 50,                    /*!< Group number for DMA status codes. */

-    kStatusGroup_EDMA = 51,                   /*!< Group number for EDMA status codes. */

-    kStatusGroup_DMAMGR = 52,                 /*!< Group number for DMAMGR status codes. */

-    kStatusGroup_FLEXCAN = 53,                /*!< Group number for FlexCAN status codes. */

-    kStatusGroup_LTC = 54,                    /*!< Group number for LTC status codes. */

-    kStatusGroup_FLEXIO_CAMERA = 55,          /*!< Group number for FLEXIO CAMERA status codes. */

-    kStatusGroup_LPC_SPI = 56,                /*!< Group number for LPC_SPI status codes. */

-    kStatusGroup_LPC_USART = 57,              /*!< Group number for LPC_USART status codes. */

-    kStatusGroup_DMIC = 58,                   /*!< Group number for DMIC status codes. */

-    kStatusGroup_SDIF = 59,                   /*!< Group number for SDIF status codes.*/

-    kStatusGroup_SPIFI = 60,                  /*!< Group number for SPIFI status codes. */

-    kStatusGroup_OTP = 61,                    /*!< Group number for OTP status codes. */

-    kStatusGroup_MCAN = 62,                   /*!< Group number for MCAN status codes. */

-    kStatusGroup_CAAM = 63,                   /*!< Group number for CAAM status codes. */

-    kStatusGroup_ECSPI = 64,                  /*!< Group number for ECSPI status codes. */

-    kStatusGroup_USDHC = 65,                  /*!< Group number for USDHC status codes.*/

-    kStatusGroup_LPC_I2C = 66,                /*!< Group number for LPC_I2C status codes.*/

-    kStatusGroup_DCP = 67,                    /*!< Group number for DCP status codes.*/

-    kStatusGroup_MSCAN = 68,                  /*!< Group number for MSCAN status codes.*/

-    kStatusGroup_ESAI = 69,                   /*!< Group number for ESAI status codes. */

-    kStatusGroup_FLEXSPI = 70,                /*!< Group number for FLEXSPI status codes. */

-    kStatusGroup_MMDC = 71,                   /*!< Group number for MMDC status codes. */

-    kStatusGroup_PDM = 72,                    /*!< Group number for MIC status codes. */

-    kStatusGroup_SDMA = 73,                   /*!< Group number for SDMA status codes. */

-    kStatusGroup_ICS = 74,                    /*!< Group number for ICS status codes. */

-    kStatusGroup_SPDIF = 75,                  /*!< Group number for SPDIF status codes. */

-    kStatusGroup_LPC_MINISPI = 76,            /*!< Group number for LPC_MINISPI status codes. */

-    kStatusGroup_HASHCRYPT = 77,              /*!< Group number for Hashcrypt status codes */

-    kStatusGroup_LPC_SPI_SSP = 78,            /*!< Group number for LPC_SPI_SSP status codes. */

-    kStatusGroup_I3C = 79,                    /*!< Group number for I3C status codes */

-    kStatusGroup_LPC_I2C_1 = 97,              /*!< Group number for LPC_I2C_1 status codes. */

-    kStatusGroup_NOTIFIER = 98,               /*!< Group number for NOTIFIER status codes. */

-    kStatusGroup_DebugConsole = 99,           /*!< Group number for debug console status codes. */

-    kStatusGroup_SEMC = 100,                  /*!< Group number for SEMC status codes. */

+    kStatusGroup_Generic               = 0,   /*!< Group number for generic status codes. */

+    kStatusGroup_FLASH                 = 1,   /*!< Group number for FLASH status codes. */

+    kStatusGroup_LPSPI                 = 4,   /*!< Group number for LPSPI status codes. */

+    kStatusGroup_FLEXIO_SPI            = 5,   /*!< Group number for FLEXIO SPI status codes. */

+    kStatusGroup_DSPI                  = 6,   /*!< Group number for DSPI status codes. */

+    kStatusGroup_FLEXIO_UART           = 7,   /*!< Group number for FLEXIO UART status codes. */

+    kStatusGroup_FLEXIO_I2C            = 8,   /*!< Group number for FLEXIO I2C status codes. */

+    kStatusGroup_LPI2C                 = 9,   /*!< Group number for LPI2C status codes. */

+    kStatusGroup_UART                  = 10,  /*!< Group number for UART status codes. */

+    kStatusGroup_I2C                   = 11,  /*!< Group number for UART status codes. */

+    kStatusGroup_LPSCI                 = 12,  /*!< Group number for LPSCI status codes. */

+    kStatusGroup_LPUART                = 13,  /*!< Group number for LPUART status codes. */

+    kStatusGroup_SPI                   = 14,  /*!< Group number for SPI status code.*/

+    kStatusGroup_XRDC                  = 15,  /*!< Group number for XRDC status code.*/

+    kStatusGroup_SEMA42                = 16,  /*!< Group number for SEMA42 status code.*/

+    kStatusGroup_SDHC                  = 17,  /*!< Group number for SDHC status code */

+    kStatusGroup_SDMMC                 = 18,  /*!< Group number for SDMMC status code */

+    kStatusGroup_SAI                   = 19,  /*!< Group number for SAI status code */

+    kStatusGroup_MCG                   = 20,  /*!< Group number for MCG status codes. */

+    kStatusGroup_SCG                   = 21,  /*!< Group number for SCG status codes. */

+    kStatusGroup_SDSPI                 = 22,  /*!< Group number for SDSPI status codes. */

+    kStatusGroup_FLEXIO_I2S            = 23,  /*!< Group number for FLEXIO I2S status codes */

+    kStatusGroup_FLEXIO_MCULCD         = 24,  /*!< Group number for FLEXIO LCD status codes */

+    kStatusGroup_FLASHIAP              = 25,  /*!< Group number for FLASHIAP status codes */

+    kStatusGroup_FLEXCOMM_I2C          = 26,  /*!< Group number for FLEXCOMM I2C status codes */

+    kStatusGroup_I2S                   = 27,  /*!< Group number for I2S status codes */

+    kStatusGroup_IUART                 = 28,  /*!< Group number for IUART status codes */

+    kStatusGroup_CSI                   = 29,  /*!< Group number for CSI status codes */

+    kStatusGroup_MIPI_DSI              = 30,  /*!< Group number for MIPI DSI status codes */

+    kStatusGroup_SDRAMC                = 35,  /*!< Group number for SDRAMC status codes. */

+    kStatusGroup_POWER                 = 39,  /*!< Group number for POWER status codes. */

+    kStatusGroup_ENET                  = 40,  /*!< Group number for ENET status codes. */

+    kStatusGroup_PHY                   = 41,  /*!< Group number for PHY status codes. */

+    kStatusGroup_TRGMUX                = 42,  /*!< Group number for TRGMUX status codes. */

+    kStatusGroup_SMARTCARD             = 43,  /*!< Group number for SMARTCARD status codes. */

+    kStatusGroup_LMEM                  = 44,  /*!< Group number for LMEM status codes. */

+    kStatusGroup_QSPI                  = 45,  /*!< Group number for QSPI status codes. */

+    kStatusGroup_DMA                   = 50,  /*!< Group number for DMA status codes. */

+    kStatusGroup_EDMA                  = 51,  /*!< Group number for EDMA status codes. */

+    kStatusGroup_DMAMGR                = 52,  /*!< Group number for DMAMGR status codes. */

+    kStatusGroup_FLEXCAN               = 53,  /*!< Group number for FlexCAN status codes. */

+    kStatusGroup_LTC                   = 54,  /*!< Group number for LTC status codes. */

+    kStatusGroup_FLEXIO_CAMERA         = 55,  /*!< Group number for FLEXIO CAMERA status codes. */

+    kStatusGroup_LPC_SPI               = 56,  /*!< Group number for LPC_SPI status codes. */

+    kStatusGroup_LPC_USART             = 57,  /*!< Group number for LPC_USART status codes. */

+    kStatusGroup_DMIC                  = 58,  /*!< Group number for DMIC status codes. */

+    kStatusGroup_SDIF                  = 59,  /*!< Group number for SDIF status codes.*/

+    kStatusGroup_SPIFI                 = 60,  /*!< Group number for SPIFI status codes. */

+    kStatusGroup_OTP                   = 61,  /*!< Group number for OTP status codes. */

+    kStatusGroup_MCAN                  = 62,  /*!< Group number for MCAN status codes. */

+    kStatusGroup_CAAM                  = 63,  /*!< Group number for CAAM status codes. */

+    kStatusGroup_ECSPI                 = 64,  /*!< Group number for ECSPI status codes. */

+    kStatusGroup_USDHC                 = 65,  /*!< Group number for USDHC status codes.*/

+    kStatusGroup_LPC_I2C               = 66,  /*!< Group number for LPC_I2C status codes.*/

+    kStatusGroup_DCP                   = 67,  /*!< Group number for DCP status codes.*/

+    kStatusGroup_MSCAN                 = 68,  /*!< Group number for MSCAN status codes.*/

+    kStatusGroup_ESAI                  = 69,  /*!< Group number for ESAI status codes. */

+    kStatusGroup_FLEXSPI               = 70,  /*!< Group number for FLEXSPI status codes. */

+    kStatusGroup_MMDC                  = 71,  /*!< Group number for MMDC status codes. */

+    kStatusGroup_PDM                   = 72,  /*!< Group number for MIC status codes. */

+    kStatusGroup_SDMA                  = 73,  /*!< Group number for SDMA status codes. */

+    kStatusGroup_ICS                   = 74,  /*!< Group number for ICS status codes. */

+    kStatusGroup_SPDIF                 = 75,  /*!< Group number for SPDIF status codes. */

+    kStatusGroup_LPC_MINISPI           = 76,  /*!< Group number for LPC_MINISPI status codes. */

+    kStatusGroup_HASHCRYPT             = 77,  /*!< Group number for Hashcrypt status codes */

+    kStatusGroup_LPC_SPI_SSP           = 78,  /*!< Group number for LPC_SPI_SSP status codes. */

+    kStatusGroup_I3C                   = 79,  /*!< Group number for I3C status codes */

+    kStatusGroup_LPC_I2C_1             = 97,  /*!< Group number for LPC_I2C_1 status codes. */

+    kStatusGroup_NOTIFIER              = 98,  /*!< Group number for NOTIFIER status codes. */

+    kStatusGroup_DebugConsole          = 99,  /*!< Group number for debug console status codes. */

+    kStatusGroup_SEMC                  = 100, /*!< Group number for SEMC status codes. */

     kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */

-    kStatusGroup_IAP = 102,                   /*!< Group number for IAP status codes */

-    kStatusGroup_SFA = 103,                   /*!< Group number for SFA status codes*/

-    kStatusGroup_SPC = 104,                   /*!< Group number for SPC status codes. */

-    kStatusGroup_PUF = 105,                   /*!< Group number for PUF status codes. */

-    kStatusGroup_TOUCH_PANEL = 106,           /*!< Group number for touch panel status codes */

-

-    kStatusGroup_HAL_GPIO = 121,              /*!< Group number for HAL GPIO status codes. */

-    kStatusGroup_HAL_UART = 122,              /*!< Group number for HAL UART status codes. */

-    kStatusGroup_HAL_TIMER = 123,             /*!< Group number for HAL TIMER status codes. */

-    kStatusGroup_HAL_SPI = 124,               /*!< Group number for HAL SPI status codes. */

-    kStatusGroup_HAL_I2C = 125,               /*!< Group number for HAL I2C status codes. */

-    kStatusGroup_HAL_FLASH = 126,             /*!< Group number for HAL FLASH status codes. */

-    kStatusGroup_HAL_PWM = 127,               /*!< Group number for HAL PWM status codes. */

-    kStatusGroup_HAL_RNG = 128,               /*!< Group number for HAL RNG status codes. */

-    kStatusGroup_TIMERMANAGER = 135,          /*!< Group number for TiMER MANAGER status codes. */

-    kStatusGroup_SERIALMANAGER = 136,         /*!< Group number for SERIAL MANAGER status codes. */

-    kStatusGroup_LED = 137,                   /*!< Group number for LED status codes. */

-    kStatusGroup_BUTTON = 138,                /*!< Group number for BUTTON status codes. */

-    kStatusGroup_EXTERN_EEPROM = 139,         /*!< Group number for EXTERN EEPROM status codes. */

-    kStatusGroup_SHELL = 140,                 /*!< Group number for SHELL status codes. */

-    kStatusGroup_MEM_MANAGER = 141,           /*!< Group number for MEM MANAGER status codes. */

-    kStatusGroup_LIST = 142,                  /*!< Group number for List status codes. */

-    kStatusGroup_OSA = 143,                   /*!< Group number for OSA status codes. */

-    kStatusGroup_COMMON_TASK = 144,           /*!< Group number for Common task status codes. */

-    kStatusGroup_MSG = 145,                   /*!< Group number for messaging status codes. */

-    kStatusGroup_SDK_OCOTP = 146,             /*!< Group number for OCOTP status codes. */

-    kStatusGroup_SDK_FLEXSPINOR = 147,        /*!< Group number for FLEXSPINOR status codes.*/

-    kStatusGroup_CODEC = 148,                 /*!< Group number for codec status codes. */

-    kStatusGroup_ASRC = 149,                  /*!< Group number for codec status ASRC. */

-    kStatusGroup_OTFAD = 150,                 /*!< Group number for codec status codes. */

-    kStatusGroup_SDIOSLV = 151,               /*!< Group number for SDIOSLV status codes. */

-    kStatusGroup_MECC = 152,                  /*!< Group number for MECC status codes. */

-    kStatusGroup_ENET_QOS = 153,              /*!< Group number for ENET_QOS status codes. */

-    kStatusGroup_LOG = 154,                   /*!< Group number for LOG status codes. */

-    kStatusGroup_I3CBUS = 155,                /*!< Group number for I3CBUS status codes. */

-    kStatusGroup_QSCI = 156,                  /*!< Group number for QSCI status codes. */

-    kStatusGroup_SNT = 157,                   /*!< Group number for SNT status codes. */

+    kStatusGroup_IAP                   = 102, /*!< Group number for IAP status codes */

+    kStatusGroup_SFA                   = 103, /*!< Group number for SFA status codes*/

+    kStatusGroup_SPC                   = 104, /*!< Group number for SPC status codes. */

+    kStatusGroup_PUF                   = 105, /*!< Group number for PUF status codes. */

+    kStatusGroup_TOUCH_PANEL           = 106, /*!< Group number for touch panel status codes */

+    kStatusGroup_VBAT                  = 107, /*!< Group number for VBAT status codes */

+

+    kStatusGroup_HAL_GPIO       = 121, /*!< Group number for HAL GPIO status codes. */

+    kStatusGroup_HAL_UART       = 122, /*!< Group number for HAL UART status codes. */

+    kStatusGroup_HAL_TIMER      = 123, /*!< Group number for HAL TIMER status codes. */

+    kStatusGroup_HAL_SPI        = 124, /*!< Group number for HAL SPI status codes. */

+    kStatusGroup_HAL_I2C        = 125, /*!< Group number for HAL I2C status codes. */

+    kStatusGroup_HAL_FLASH      = 126, /*!< Group number for HAL FLASH status codes. */

+    kStatusGroup_HAL_PWM        = 127, /*!< Group number for HAL PWM status codes. */

+    kStatusGroup_HAL_RNG        = 128, /*!< Group number for HAL RNG status codes. */

+    kStatusGroup_HAL_I2S        = 129, /*!< Group number for HAL I2S status codes. */

+    kStatusGroup_TIMERMANAGER   = 135, /*!< Group number for TiMER MANAGER status codes. */

+    kStatusGroup_SERIALMANAGER  = 136, /*!< Group number for SERIAL MANAGER status codes. */

+    kStatusGroup_LED            = 137, /*!< Group number for LED status codes. */

+    kStatusGroup_BUTTON         = 138, /*!< Group number for BUTTON status codes. */

+    kStatusGroup_EXTERN_EEPROM  = 139, /*!< Group number for EXTERN EEPROM status codes. */

+    kStatusGroup_SHELL          = 140, /*!< Group number for SHELL status codes. */

+    kStatusGroup_MEM_MANAGER    = 141, /*!< Group number for MEM MANAGER status codes. */

+    kStatusGroup_LIST           = 142, /*!< Group number for List status codes. */

+    kStatusGroup_OSA            = 143, /*!< Group number for OSA status codes. */

+    kStatusGroup_COMMON_TASK    = 144, /*!< Group number for Common task status codes. */

+    kStatusGroup_MSG            = 145, /*!< Group number for messaging status codes. */

+    kStatusGroup_SDK_OCOTP      = 146, /*!< Group number for OCOTP status codes. */

+    kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/

+    kStatusGroup_CODEC          = 148, /*!< Group number for codec status codes. */

+    kStatusGroup_ASRC           = 149, /*!< Group number for codec status ASRC. */

+    kStatusGroup_OTFAD          = 150, /*!< Group number for codec status codes. */

+    kStatusGroup_SDIOSLV        = 151, /*!< Group number for SDIOSLV status codes. */

+    kStatusGroup_MECC           = 152, /*!< Group number for MECC status codes. */

+    kStatusGroup_ENET_QOS       = 153, /*!< Group number for ENET_QOS status codes. */

+    kStatusGroup_LOG            = 154, /*!< Group number for LOG status codes. */

+    kStatusGroup_I3CBUS         = 155, /*!< Group number for I3CBUS status codes. */

+    kStatusGroup_QSCI           = 156, /*!< Group number for QSCI status codes. */

+    kStatusGroup_SNT            = 157, /*!< Group number for SNT status codes. */

+    kStatusGroup_QUEUEDSPI      = 158, /*!< Group number for QSPI status codes. */

+    kStatusGroup_POWER_MANAGER  = 159, /*!< Group number for POWER_MANAGER status codes. */

+    kStatusGroup_IPED           = 160, /*!< Group number for IPED status codes. */

+    kStatusGroup_CSS_PKC        = 161, /*!< Group number for CSS PKC status codes. */

+    kStatusGroup_HOSTIF         = 162, /*!< Group number for HOSTIF status codes. */

+    kStatusGroup_CLIF           = 163, /*!< Group number for CLIF status codes. */

+    kStatusGroup_BMA            = 164, /*!< Group number for BMA status codes. */

+    kStatusGroup_NETC           = 165, /*!< Group number for NETC status codes. */

 };

 

 /*! \public

@@ -183,14 +204,17 @@ enum _status_groups
  */

 enum

 {

-    kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0),  /*!< Generic status for Success. */

-    kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1),      /*!< Generic status for Fail. */

-    kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2),    /*!< Generic status for read only failure. */

-    kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3),   /*!< Generic status for out of range access. */

-    kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),   /*!< Generic status for invalid argument check. */

-    kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5),   /*!< Generic status for timeout. */

-    kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6),   /*!< Generic status for no transfer in progress. */

-    kStatus_Busy = MAKE_STATUS(kStatusGroup_Generic, 7),   /*!< Generic status for module is busy. */

+    kStatus_Success         = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< Generic status for Success. */

+    kStatus_Fail            = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< Generic status for Fail. */

+    kStatus_ReadOnly        = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< Generic status for read only failure. */

+    kStatus_OutOfRange      = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< Generic status for out of range access. */

+    kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< Generic status for invalid argument check. */

+    kStatus_Timeout         = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Generic status for timeout. */

+    kStatus_NoTransferInProgress =

+        MAKE_STATUS(kStatusGroup_Generic, 6),            /*!< Generic status for no transfer in progress. */

+    kStatus_Busy = MAKE_STATUS(kStatusGroup_Generic, 7), /*!< Generic status for module is busy. */

+    kStatus_NoData =

+        MAKE_STATUS(kStatusGroup_Generic, 8), /*!< Generic status for no data is found for the operation. */

 };

 

 /*! @brief Type used for all status and error return values. */

@@ -233,7 +257,7 @@ typedef int32_t status_t;
  */

 /* @{ */

 #if defined(__GNUC__) && !defined(__ARMCC_VERSION)

-#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__ ((fallthrough))

+#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__((fallthrough))

 #else

 #define SUPPRESS_FALL_THROUGH_WARNING()

 #endif

@@ -247,6 +271,7 @@ typedef int32_t status_t;
 extern "C" {

 #endif

 

+#if !((defined(__DSC__) && defined(__CW__)))

 /*!

  * @brief Allocate memory with given alignment and aligned size.

  *

@@ -264,15 +289,16 @@ void *SDK_Malloc(size_t size, size_t alignbytes);
  * @param ptr The memory to be release.

  */

 void SDK_Free(void *ptr);

+#endif

 

 /*!

-* @brief Delay at least for some time.

-*  Please note that, this API uses while loop for delay, different run-time environments make the time not precise,

-*  if precise delay count was needed, please implement a new delay function with hardware timer.

-*

-* @param delayTime_us  Delay time in unit of microsecond.

-* @param coreClock_Hz  Core clock frequency with Hz.

-*/

+ * @brief Delay at least for some time.

+ *  Please note that, this API uses while loop for delay, different run-time environments make the time not precise,

+ *  if precise delay count was needed, please implement a new delay function with hardware timer.

+ *

+ * @param delayTime_us  Delay time in unit of microsecond.

+ * @param coreClock_Hz  Core clock frequency with Hz.

+ */

 void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz);

 

 #if defined(__cplusplus)

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common_arm.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common_arm.c
index e77a265ce..241005e92 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common_arm.c
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common_arm.c
@@ -116,9 +116,9 @@ void DisableDeepSleepIRQ(IRQn_Type interrupt)
 #endif /* FSL_FEATURE_POWERLIB_EXTEND */
 #endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
 
-#if defined(SDK_DELAY_USE_DWT) && defined(DWT)
+#if defined(DWT)
 /* Use WDT. */
-static void enableCpuCycleCounter(void)
+void MSDK_EnableCpuCycleCounter(void)
 {
     /* Make sure the DWT trace fucntion is enabled. */
     if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR))
@@ -136,11 +136,13 @@ static void enableCpuCycleCounter(void)
     }
 }
 
-static uint32_t getCpuCycleCount(void)
+uint32_t MSDK_GetCpuCycleCount(void)
 {
     return DWT->CYCCNT;
 }
-#else                 /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */
+#endif /* defined(DWT) */
+
+#if !(defined(SDK_DELAY_USE_DWT) && defined(DWT))
 /* Use software loop. */
 #if defined(__CC_ARM) /* This macro is arm v5 specific */
 /* clang-format off */
@@ -152,6 +154,20 @@ loop
     BNE  loop
     BX   LR
 }
+#elif defined(__ARM_ARCH_8A__) /* This macro is ARMv8-A specific */
+static void DelayLoop(uint32_t count)
+{
+    __ASM volatile("    MOV    X0, %0" : : "r"(count));
+    __ASM volatile(
+        "loop:                          \n"
+        "    SUB    X0, X0, #1          \n"
+        "    CMP    X0, #0              \n"
+
+        "    BNE    loop                \n"
+        :
+        :
+        : "r0");
+}
 /* clang-format on */
 #elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__)
 /* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler,
@@ -198,21 +214,21 @@ void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz)
 
 #if defined(SDK_DELAY_USE_DWT) && defined(DWT) /* Use DWT for better accuracy */
 
-        enableCpuCycleCounter();
+        MSDK_EnableCpuCycleCounter();
         /* Calculate the count ticks. */
-        count += getCpuCycleCount();
+        count += MSDK_GetCpuCycleCount();
 
         if (count > UINT32_MAX)
         {
             count -= UINT32_MAX;
             /* Wait for cyccnt overflow. */
-            while (count < getCpuCycleCount())
+            while (count < MSDK_GetCpuCycleCount())
             {
             }
         }
 
         /* Wait for cyccnt reach count value. */
-        while (count > getCpuCycleCount())
+        while (count > MSDK_GetCpuCycleCount())
         {
         }
 #else
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common_arm.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common_arm.h
index 8b28aa888..1da9dff8d 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common_arm.h
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common_arm.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2021 NXP
+ * Copyright 2016-2022 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -214,69 +214,82 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin
     _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits);
 }
 
-#define SDK_ATOMIC_LOCAL_ADD(addr, val) \
-        ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd1Byte((volatile uint8_t*)(volatile void*)(addr), (val)) : \
-        ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd2Byte((volatile uint16_t*)(volatile void*)(addr), (val)) : \
-        _SDK_AtomicLocalAdd4Byte((volatile uint32_t *)(volatile void*)(addr), (val))))
-
-#define SDK_ATOMIC_LOCAL_SET(addr, bits) \
-        ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalSet1Byte((volatile uint8_t*)(volatile void*)(addr), (bits)) : \
-        ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSet2Byte((volatile uint16_t*)(volatile void*)(addr), (bits)) : \
-        _SDK_AtomicLocalSet4Byte((volatile uint32_t *)(volatile void*)(addr), (bits))))
-
-#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \
-        ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalClear1Byte((volatile uint8_t*)(volatile void*)(addr), (bits)) : \
-        ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalClear2Byte((volatile uint16_t*)(volatile void*)(addr), (bits)) : \
-        _SDK_AtomicLocalClear4Byte((volatile uint32_t *)(volatile void*)(addr), (bits))))
-
-#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \
-        ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalToggle1Byte((volatile uint8_t*)(volatile void*)(addr), (bits)) : \
-        ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalToggle2Byte((volatile uint16_t*)(volatile void*)(addr), (bits)) : \
-        _SDK_AtomicLocalToggle4Byte((volatile uint32_t *)(volatile void*)(addr), (bits))))
-
-#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \
-        ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalClearAndSet1Byte((volatile uint8_t*)(volatile void*)(addr), (clearBits), (setBits)) : \
-        ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalClearAndSet2Byte((volatile uint16_t*)(volatile void*)(addr), (clearBits), (setBits)) : \
-        _SDK_AtomicLocalClearAndSet4Byte((volatile uint32_t *)(volatile void*)(addr), (clearBits), (setBits))))
+#define SDK_ATOMIC_LOCAL_ADD(addr, val)                                                                                        \
+    ((1UL == sizeof(*(addr))) ?                                                                                                \
+         _SDK_AtomicLocalAdd1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(val)) :                               \
+         ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \
+                                     _SDK_AtomicLocalAdd4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val))))
+
+#define SDK_ATOMIC_LOCAL_SET(addr, bits)                                                                                        \
+    ((1UL == sizeof(*(addr))) ?                                                                                                 \
+         _SDK_AtomicLocalSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) :                               \
+         ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \
+                                     _SDK_AtomicLocalSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits))))
+
+#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits)                                                                 \
+    ((1UL == sizeof(*(addr))) ?                                                                            \
+         _SDK_AtomicLocalClear1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) :        \
+         ((2UL == sizeof(*(addr))) ?                                                                       \
+              _SDK_AtomicLocalClear2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \
+              _SDK_AtomicLocalClear4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits))))
+
+#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits)                                                                 \
+    ((1UL == sizeof(*(addr))) ?                                                                             \
+         _SDK_AtomicLocalToggle1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) :        \
+         ((2UL == sizeof(*(addr))) ?                                                                        \
+              _SDK_AtomicLocalToggle2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \
+              _SDK_AtomicLocalToggle4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits))))
+
+#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits)                                                                           \
+    ((1UL == sizeof(*(addr))) ?                                                                                                            \
+         _SDK_AtomicLocalClearAndSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(clearBits), (uint8_t)(setBits)) :         \
+         ((2UL == sizeof(*(addr))) ?                                                                                                       \
+              _SDK_AtomicLocalClearAndSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(clearBits), (uint16_t)(setBits)) : \
+              _SDK_AtomicLocalClearAndSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(clearBits), (uint32_t)(setBits))))
 #else
 
-#define SDK_ATOMIC_LOCAL_ADD(addr, val)       \
-    do {                                      \
-        uint32_t s_atomicOldInt;              \
-        s_atomicOldInt = DisableGlobalIRQ();  \
-        *(addr) += (val);                     \
-        EnableGlobalIRQ(s_atomicOldInt);      \
+#define SDK_ATOMIC_LOCAL_ADD(addr, val)      \
+    do                                       \
+    {                                        \
+        uint32_t s_atomicOldInt;             \
+        s_atomicOldInt = DisableGlobalIRQ(); \
+        *(addr) += (val);                    \
+        EnableGlobalIRQ(s_atomicOldInt);     \
     } while (0)
 
-#define SDK_ATOMIC_LOCAL_SET(addr, bits)      \
-    do {                                      \
-        uint32_t s_atomicOldInt;              \
-        s_atomicOldInt = DisableGlobalIRQ();  \
-        *(addr) |= (bits);                    \
-        EnableGlobalIRQ(s_atomicOldInt);      \
+#define SDK_ATOMIC_LOCAL_SET(addr, bits)     \
+    do                                       \
+    {                                        \
+        uint32_t s_atomicOldInt;             \
+        s_atomicOldInt = DisableGlobalIRQ(); \
+        *(addr) |= (bits);                   \
+        EnableGlobalIRQ(s_atomicOldInt);     \
     } while (0)
 
-#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits)    \
-    do {                                      \
-        uint32_t s_atomicOldInt;              \
-        s_atomicOldInt = DisableGlobalIRQ();  \
-        *(addr) &= ~(bits);                   \
-        EnableGlobalIRQ(s_atomicOldInt);      \
+#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits)   \
+    do                                       \
+    {                                        \
+        uint32_t s_atomicOldInt;             \
+        s_atomicOldInt = DisableGlobalIRQ(); \
+        *(addr) &= ~(bits);                  \
+        EnableGlobalIRQ(s_atomicOldInt);     \
     } while (0)
 
-#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits)   \
-    do {                                      \
-        uint32_t s_atomicOldInt;              \
-        s_atomicOldInt = DisableGlobalIRQ();  \
-        *(addr) ^= (bits);                    \
-        EnableGlobalIRQ(s_atomicOldInt);      \
+#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits)  \
+    do                                       \
+    {                                        \
+        uint32_t s_atomicOldInt;             \
+        s_atomicOldInt = DisableGlobalIRQ(); \
+        *(addr) ^= (bits);                   \
+        EnableGlobalIRQ(s_atomicOldInt);     \
     } while (0)
 
 #define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \
-    do {                                                         \
+    do                                                           \
+    {                                                            \
         uint32_t s_atomicOldInt;                                 \
         s_atomicOldInt = DisableGlobalIRQ();                     \
-        *(addr) = (*(addr) & ~(clearBits)) | (setBits);          \
+        *(addr)        = (*(addr) & ~(clearBits)) | (setBits);   \
         EnableGlobalIRQ(s_atomicOldInt);                         \
     } while (0)
 
@@ -288,12 +301,12 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin
 /*! Macro to convert a microsecond period to raw count value */
 #define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U)
 /*! Macro to convert a raw count value to microsecond */
-#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count) * 1000000U / (clockFreqInHz))
+#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000000U / (clockFreqInHz))
 
 /*! Macro to convert a millisecond period to raw count value */
 #define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U)
 /*! Macro to convert a raw count value to millisecond */
-#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count) * 1000U / (clockFreqInHz))
+#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000U / (clockFreqInHz))
 /* @} */
 
 /*! @name ISR exit barrier
@@ -322,7 +335,7 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin
  */
 _Pragma("diag_suppress=Pm120")
 #define SDK_PRAGMA(x) _Pragma(#x)
-_Pragma("diag_error=Pm120")
+    _Pragma("diag_error=Pm120")
 /*! Macro to define a variable with alignbytes alignment */
 #define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
 #elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
@@ -351,25 +364,27 @@ _Pragma("diag_error=Pm120")
 
 /*! @name Non-cacheable region definition macros */
 /* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
- * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables,
- * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables
- * will be initialized to zero in system startup.
+ * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable
+ * variables, please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them,
+ * these zero-inited variables will be initialized to zero in system startup.
  */
 /* @{ */
 
-#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
+#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && \
+     defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
 
 #if (defined(__ICCARM__))
-#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"
+#define AT_NONCACHEABLE_SECTION(var)                   var @"NonCacheable"
 #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
-#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init"
-#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init"
+#define AT_NONCACHEABLE_SECTION_INIT(var)              var @"NonCacheable.init"
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
+    SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init"
 
-#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION))
 #define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
 #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
     __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var
-#if(defined(__CC_ARM))
+#if (defined(__CC_ARM))
 #define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var
 #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
     __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var
@@ -379,7 +394,7 @@ _Pragma("diag_error=Pm120")
     __attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var
 #endif
 
-#elif(defined(__GNUC__))
+#elif (defined(__GNUC__))
 /* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
  * in your projects to make sure the non-cacheable section variables will be initialized in system startup.
  */
@@ -395,9 +410,9 @@ _Pragma("diag_error=Pm120")
 
 #else
 
-#define AT_NONCACHEABLE_SECTION(var) var
-#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_ALIGN(var, alignbytes)
-#define AT_NONCACHEABLE_SECTION_INIT(var) var
+#define AT_NONCACHEABLE_SECTION(var)                        var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes)      SDK_ALIGN(var, alignbytes)
+#define AT_NONCACHEABLE_SECTION_INIT(var)                   var
 #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_ALIGN(var, alignbytes)
 
 #endif
@@ -408,43 +423,39 @@ _Pragma("diag_error=Pm120")
  * @name Time sensitive region
  * @{
  */
-#if (defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE)
-
 #if (defined(__ICCARM__))
 #define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess"
-#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess"
-#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#define AT_QUICKACCESS_SECTION_DATA(var)  var @"DataQuickAccess"
+#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \
+    SDK_PRAGMA(data_alignment = alignbytes) var @"DataQuickAccess"
+#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION))
 #define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func
-#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
-#elif(defined(__GNUC__))
+#define AT_QUICKACCESS_SECTION_DATA(var)  __attribute__((section("DataQuickAccess"))) var
+#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \
+    __attribute__((section("DataQuickAccess"))) __attribute__((aligned(alignbytes))) var
+#elif (defined(__GNUC__))
 #define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func
-#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
+#define AT_QUICKACCESS_SECTION_DATA(var)  __attribute__((section("DataQuickAccess"))) var
+#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \
+    __attribute__((section("DataQuickAccess"))) var __attribute__((aligned(alignbytes)))
 #else
 #error Toolchain not supported.
 #endif /* defined(__ICCARM__) */
 
-#else /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */
-
-#define AT_QUICKACCESS_SECTION_CODE(func) func
-#define AT_QUICKACCESS_SECTION_DATA(func) func
-
-#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */
-/* @} */
-
 /*! @name Ram Function */
 #if (defined(__ICCARM__))
 #define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction"
-#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION))
 #define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
-#elif(defined(__GNUC__))
+#elif (defined(__GNUC__))
 #define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
 #else
 #error Toolchain not supported.
 #endif /* defined(__ICCARM__) */
 /* @} */
 
-#if defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
-void DefaultISR(void);
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+        void DefaultISR(void);
 #endif
 
 /*
@@ -558,6 +569,144 @@ static inline status_t DisableIRQ(IRQn_Type interrupt)
 }
 
 /*!
+ * @brief Enable the IRQ, and also set the interrupt priority.
+ *
+ * Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
+ * to NVIC first then routed to core.
+ *
+ * This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
+ *
+ * @param interrupt The IRQ to Enable.
+ * @param priNum Priority number set to interrupt controller register.
+ * @retval kStatus_Success Interrupt priority set successfully
+ * @retval kStatus_Fail Failed to set the interrupt priority.
+ */
+static inline status_t EnableIRQWithPriority(IRQn_Type interrupt, uint8_t priNum)
+{
+    status_t status = kStatus_Success;
+
+    if (NotAvail_IRQn == interrupt)
+    {
+        status = kStatus_Fail;
+    }
+
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
+    else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+    {
+        status = kStatus_Fail;
+    }
+#endif
+
+    else
+    {
+#if defined(__GIC_PRIO_BITS)
+        GIC_SetPriority(interrupt, priNum);
+        GIC_EnableIRQ(interrupt);
+#else
+        NVIC_SetPriority(interrupt, priNum);
+        NVIC_EnableIRQ(interrupt);
+#endif
+    }
+
+    return status;
+}
+
+/*!
+ * @brief Set the IRQ priority.
+ *
+ * Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
+ * to NVIC first then routed to core.
+ *
+ * This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
+ *
+ * @param interrupt The IRQ to set.
+ * @param priNum Priority number set to interrupt controller register.
+ *
+ * @retval kStatus_Success Interrupt priority set successfully
+ * @retval kStatus_Fail Failed to set the interrupt priority.
+ */
+static inline status_t IRQ_SetPriority(IRQn_Type interrupt, uint8_t priNum)
+{
+    status_t status = kStatus_Success;
+
+    if (NotAvail_IRQn == interrupt)
+    {
+        status = kStatus_Fail;
+    }
+
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
+    else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+    {
+        status = kStatus_Fail;
+    }
+#endif
+
+    else
+    {
+#if defined(__GIC_PRIO_BITS)
+        GIC_SetPriority(interrupt, priNum);
+#else
+        NVIC_SetPriority(interrupt, priNum);
+#endif
+    }
+
+    return status;
+}
+
+/*!
+ * @brief Clear the pending IRQ flag.
+ *
+ * Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
+ * to NVIC first then routed to core.
+ *
+ * This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
+ *
+ * @param interrupt The flag which IRQ to clear.
+ *
+ * @retval kStatus_Success Interrupt priority set successfully
+ * @retval kStatus_Fail Failed to set the interrupt priority.
+ */
+static inline status_t IRQ_ClearPendingIRQ(IRQn_Type interrupt)
+{
+    status_t status = kStatus_Success;
+
+    if (NotAvail_IRQn == interrupt)
+    {
+        status = kStatus_Fail;
+    }
+
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
+    else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+    {
+        status = kStatus_Fail;
+    }
+#endif
+
+    else
+    {
+#if defined(__GIC_PRIO_BITS)
+        GIC_ClearPendingIRQ(interrupt);
+#else
+        NVIC_ClearPendingIRQ(interrupt);
+#endif
+    }
+
+    return status;
+}
+
+/*!
  * @brief Disable the global IRQ
  *
  * Disable the global interrupt and return the current primask register. User is required to provided the primask
@@ -567,19 +716,18 @@ static inline status_t DisableIRQ(IRQn_Type interrupt)
  */
 static inline uint32_t DisableGlobalIRQ(void)
 {
-#if defined(CPSR_I_Msk)
-    uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
-
-    __disable_irq();
+    uint32_t mask;
 
-    return cpsr;
+#if defined(CPSR_I_Msk)
+    mask = __get_CPSR() & CPSR_I_Msk;
+#elif defined(DAIF_I_BIT)
+    mask = __get_DAIF() & DAIF_I_BIT;
 #else
-    uint32_t regPrimask = __get_PRIMASK();
-
+    mask = __get_PRIMASK();
+#endif
     __disable_irq();
 
-    return regPrimask;
-#endif
+    return mask;
 }
 
 /*!
@@ -596,6 +744,11 @@ static inline void EnableGlobalIRQ(uint32_t primask)
 {
 #if defined(CPSR_I_Msk)
     __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
+#elif defined(DAIF_I_BIT)
+    if (0UL == primask)
+    {
+        __enable_irq();
+    }
 #else
     __set_PRIMASK(primask);
 #endif
@@ -651,6 +804,20 @@ void DisableDeepSleepIRQ(IRQn_Type interrupt);
 #endif /* FSL_FEATURE_POWERLIB_EXTEND */
 #endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
 
+#if defined(DWT)
+/*!
+ * @brief Enable the counter to get CPU cycles.
+ */
+void MSDK_EnableCpuCycleCounter(void);
+
+/*!
+ * @brief Get the current CPU cycle count.
+ *
+ * @return Current CPU cycle count.
+ */
+uint32_t MSDK_GetCpuCycleCount(void);
+#endif
+
 #if defined(__cplusplus)
 }
 #endif /* __cplusplus*/
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_power.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_power.c
index ccc1ad471..41561f4d6 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_power.c
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_power.c
@@ -13,7 +13,1819 @@
 #endif

 

 /*******************************************************************************

- * Code

+ * Variables

  ******************************************************************************/

 

-/* Empty file since implementation is in header file and power library */

+/*******************************************************************************

+ * Definitions

+ ******************************************************************************/

+/** @brief  Low Power main structure */

+typedef enum

+{

+    VD_AON       = 0x0, /*!< Digital Always On power domain */

+    VD_MEM       = 0x1, /*!< Memories (SRAM) power domain   */

+    VD_DCDC      = 0x2, /*!< Core logic power domain        */

+    VD_DEEPSLEEP = 0x3  /*!< Core logic power domain        */

+} LPC_POWER_DOMAIN_T;

+

+/**

+ * @brief LDO_FLASH_NV & LDO_USB voltage settings

+ */

+typedef enum _v_flashnv

+{

+    V_LDOFLASHNV_1P650 = 0, /*!< 0.95  V */

+    V_LDOFLASHNV_1P700 = 1, /*!< 0.975 V */

+    V_LDOFLASHNV_1P750 = 2, /*!< 1     V */

+    V_LDOFLASHNV_0P800 = 3, /*!< 1.025 V */

+    V_LDOFLASHNV_1P850 = 4, /*!< 1.050 V */

+    V_LDOFLASHNV_1P900 = 5, /*!< 1.075 V */

+    V_LDOFLASHNV_1P950 = 6, /*!< 1.1   V */

+    V_LDOFLASHNV_2P000 = 7  /*!< 1.125 V */

+} v_flashnv_t;

+

+/** @brief  Low Power main structure */

+typedef struct

+{                              /*     */

+    __IO uint32_t CFG;         /*!< Low Power Mode Configuration, and miscallenous options  */

+    __IO uint32_t PDCTRL0;     /*!< Power Down control : controls power of various modules

+                                 in the different Low power modes, including ROM */

+    __IO uint32_t SRAMRETCTRL; /*!< Power Down control : controls power SRAM instances

+                                 in the different Low power modes */

+    __IO uint32_t CPURETCTRL;  /*!< CPU0 retention control : controls CPU retention parameters in POWER DOWN modes */

+    __IO uint64_t VOLTAGE;     /*!< Voltage control in Low Power Modes */

+    __IO uint64_t WAKEUPSRC;   /*!< Wake up sources control for sleepcon */

+    __IO uint64_t WAKEUPINT;   /*!< Wake up sources control for ARM */

+    __IO uint32_t HWWAKE;      /*!< Interrupt that can postpone power down modes

+                                 in case an interrupt is pending when the processor request deepsleep */

+    __IO uint32_t WAKEUPIOSRC; /*!< Wake up I/O sources in DEEP POWER DOWN mode */

+    __IO uint32_t TIMERCFG;    /*!< Wake up timers configuration */

+    __IO uint32_t TIMERCOUNT;  /*!< Wake up Timer count*/

+    __IO uint32_t POWERCYCLE;  /*!< Cancels entry in Low Power mode if set with 0xDEADABBA (might be used by some

+                                 interrupt handlers)*/

+} LPC_LOWPOWER_T;

+

+/*   */

+#define LOWPOWER_POWERCYCLE_CANCELLED 0xDEADABBAUL /*!<    */

+

+/**

+ * @brief SRAM Low Power Modes

+ */

+#define LOWPOWER_SRAM_LPMODE_MASK      (0xFUL)

+#define LOWPOWER_SRAM_LPMODE_ACTIVE    (0x6UL) /*!< SRAM functional mode                                */

+#define LOWPOWER_SRAM_LPMODE_SLEEP     (0xFUL) /*!< SRAM Sleep mode (Data retention, fast wake up)      */

+#define LOWPOWER_SRAM_LPMODE_DEEPSLEEP (0x8UL) /*!< SRAM Deep Sleep mode (Data retention, slow wake up) */

+#define LOWPOWER_SRAM_LPMODE_SHUTDOWN  (0x9UL) /*!< SRAM Shut Down mode (no data retention)             */

+#define LOWPOWER_SRAM_LPMODE_POWERUP   (0xAUL) /*!< SRAM is powering up                                 */

+

+/**

+ * @brief Wake up timers configuration in Low Power Modes

+ */

+#define LOWPOWER_TIMERCFG_CTRL_INDEX   0

+#define LOWPOWER_TIMERCFG_CTRL_MASK    (0x1UL << LOWPOWER_TIMERCFG_CTRL_INDEX)

+#define LOWPOWER_TIMERCFG_TIMER_INDEX  1

+#define LOWPOWER_TIMERCFG_TIMER_MASK   (0x7UL << LOWPOWER_TIMERCFG_TIMER_INDEX)

+#define LOWPOWER_TIMERCFG_OSC32K_INDEX 4

+#define LOWPOWER_TIMERCFG_OSC32K_MASK  (0x1UL << LOWPOWER_TIMERCFG_OSC32K_INDEX)

+

+#define LOWPOWER_TIMERCFG_CTRL_DISABLE 0 /*!< Wake Timer Disable */

+#define LOWPOWER_TIMERCFG_CTRL_ENABLE  1 /*!< Wake Timer Enable  */

+

+/**

+ * @brief Primary Wake up timers configuration in Low Power Modes

+ */

+#define LOWPOWER_TIMERCFG_TIMER_RTC1KHZ 0 /*!< 1 KHz Real Time Counter (RTC) used as wake up source */

+#define LOWPOWER_TIMERCFG_TIMER_RTC1HZ  1 /*!< 1 Hz Real Time Counter (RTC) used as wake up source  */

+#define LOWPOWER_TIMERCFG_TIMER_OSTIMER 2 /*!< OS Event Timer used as wake up source                */

+

+#define LOWPOWER_TIMERCFG_OSC32K_FRO32KHZ  0 /*!< Wake up Timers uses FRO 32 KHz as clock source      */

+#define LOWPOWER_TIMERCFG_OSC32K_XTAL32KHZ 1 /*!< Wake up Timers uses Chrystal 32 KHz as clock source */

+

+//! @brief Interface for lowpower functions

+typedef struct LowpowerDriverInterface

+{

+    void (*power_cycle_cpu_and_flash)(void);

+    void (*set_lowpower_mode)(LPC_LOWPOWER_T *p_lowpower_cfg);

+} lowpower_driver_interface_t;

+

+/**<  DCDC Power Profiles */

+typedef enum

+{

+    DCDC_POWER_PROFILE_LOW,    /**<  LOW (for CPU frequencies below DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ) */

+    DCDC_POWER_PROFILE_MEDIUM, /**<  MEDIUM (for CPU frequencies between DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ and

+                                  DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ) */

+    DCDC_POWER_PROFILE_HIGH,   /**<  HIGH (for CPU frequencies between DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ and

+                                  DCDC_POWER_PROFILE_HIGH_MAX_FREQ_HZ) */

+} lowpower_dcdc_power_profile_enum;

+

+/**<  Manufacturing Process Corners */

+typedef enum

+{

+    PROCESS_CORNER_SSS,    /**< Slow Corner Process */

+    PROCESS_CORNER_NNN,    /**< Nominal Corner Process */

+    PROCESS_CORNER_FFF,    /**< Fast Corner Process */

+    PROCESS_CORNER_OTHERS, /**< SFN, SNF, NFS, Poly Res ... Corner Process */

+} lowpower_process_corner_enum;

+

+/**

+ * @brief DCDC voltage settings

+ */

+typedef enum _v_dcdc

+{

+    V_DCDC_0P950 = 0, /*!< 0.95  V */

+    V_DCDC_0P975 = 1, /*!< 0.975 V */

+    V_DCDC_1P000 = 2, /*!< 1     V */

+    V_DCDC_1P025 = 3, /*!< 1.025 V */

+    V_DCDC_1P050 = 4, /*!< 1.050 V */

+    V_DCDC_1P075 = 5, /*!< 1.075 V */

+    V_DCDC_1P100 = 6, /*!< 1.1   V */

+    V_DCDC_1P125 = 7, /*!< 1.125 V */

+    V_DCDC_1P150 = 8, /*!< 1.150 V */

+    V_DCDC_1P175 = 9, /*!< 1.175 V */

+    V_DCDC_1P200 = 10 /*!< 1.2   V */

+} v_dcdc_t;

+

+/**

+ * @brief Deep Sleep LDO voltage settings

+ */

+typedef enum _v_deepsleep

+{

+    V_DEEPSLEEP_0P900 = 0, /*!< 0.9   V */

+    V_DEEPSLEEP_0P925 = 1, /*!< 0.925 V */

+    V_DEEPSLEEP_0P950 = 2, /*!< 0.95  V */

+    V_DEEPSLEEP_0P975 = 3, /*!< 0.975 V */

+    V_DEEPSLEEP_1P000 = 4, /*!< 1.000 V */

+    V_DEEPSLEEP_1P025 = 5, /*!< 1.025 V */

+    V_DEEPSLEEP_1P050 = 6, /*!< 1.050 V */

+    V_DEEPSLEEP_1P075 = 7  /*!< 1.075 V */

+} v_deepsleep_t;

+

+/**

+ * @brief Always On and Memories LDO voltage settings

+ */

+typedef enum _v_ao

+{

+    V_AO_0P700 = 1,  /*!< 0.7   V */

+    V_AO_0P725 = 2,  /*!< 0.725 V */

+    V_AO_0P750 = 3,  /*!< 0.75  V */

+    V_AO_0P775 = 4,  /*!< 0.775 V */

+    V_AO_0P800 = 5,  /*!< 0.8   V */

+    V_AO_0P825 = 6,  /*!< 0.825 V */

+    V_AO_0P850 = 7,  /*!< 0.85  V */

+    V_AO_0P875 = 8,  /*!< 0.875 V */

+    V_AO_0P900 = 9,  /*!< 0.9   V */

+    V_AO_0P960 = 10, /*!< 0.96  V */

+    V_AO_0P970 = 11, /*!< 0.97  V */

+    V_AO_0P980 = 12, /*!< 0.98  V */

+    V_AO_0P990 = 13, /*!< 0.99  V */

+    V_AO_1P000 = 14, /*!< 1     V */

+    V_AO_1P010 = 15, /*!< 1.01  V */

+    V_AO_1P020 = 16, /*!< 1.02  V */

+    V_AO_1P030 = 17, /*!< 1.03  V */

+    V_AO_1P040 = 18, /*!< 1.04  V */

+    V_AO_1P050 = 19, /*!< 1.05  V */

+    V_AO_1P060 = 20, /*!< 1.06  V */

+    V_AO_1P070 = 21, /*!< 1.07  V */

+    V_AO_1P080 = 22, /*!< 1.08  V */

+    V_AO_1P090 = 23, /*!< 1.09  V */

+    V_AO_1P100 = 24, /*!< 1.1   V */

+    V_AO_1P110 = 25, /*!< 1.11  V */

+    V_AO_1P120 = 26, /*!< 1.12  V */

+    V_AO_1P130 = 27, /*!< 1.13  V */

+    V_AO_1P140 = 28, /*!< 1.14  V */

+    V_AO_1P150 = 29, /*!< 1.15  V */

+    V_AO_1P160 = 30, /*!< 1.16  V */

+    V_AO_1P220 = 31  /*!< 1.22  V */

+} v_ao_t;

+

+/* Low Power modes  */

+#define LOWPOWER_CFG_LPMODE_INDEX          0

+#define LOWPOWER_CFG_LPMODE_MASK           (0x3UL << LOWPOWER_CFG_LPMODE_INDEX)

+#define LOWPOWER_CFG_SELCLOCK_INDEX        2

+#define LOWPOWER_CFG_SELCLOCK_MASK         (0x1UL << LOWPOWER_CFG_SELCLOCK_INDEX)

+#define LOWPOWER_CFG_SELMEMSUPPLY_INDEX    3

+#define LOWPOWER_CFG_SELMEMSUPPLY_MASK     (0x1UL << LOWPOWER_CFG_SELMEMSUPPLY_INDEX)

+#define LOWPOWER_CFG_MEMLOWPOWERMODE_INDEX 4

+#define LOWPOWER_CFG_MEMLOWPOWERMODE_MASK  (0x1UL << LOWPOWER_CFG_MEMLOWPOWERMODE_INDEX)

+#define LOWPOWER_CFG_LDODEEPSLEEPREF_INDEX 5

+#define LOWPOWER_CFG_LDODEEPSLEEPREF_MASK  (0x1UL << LOWPOWER_CFG_LDODEEPSLEEPREF_INDEX)

+

+#define LOWPOWER_CFG_LPMODE_ACTIVE        0 /*!< ACTIVE mode          */

+#define LOWPOWER_CFG_LPMODE_DEEPSLEEP     1 /*!< DEEP SLEEP mode      */

+#define LOWPOWER_CFG_LPMODE_POWERDOWN     2 /*!< POWER DOWN mode      */

+#define LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN 3 /*!< DEEP POWER DOWN mode */

+#define LOWPOWER_CFG_LPMODE_SLEEP         4 /*!< SLEEP mode */

+

+#define LOWPOWER_CFG_SELCLOCK_1MHZ 0 /*!< The 1 MHz clock is used during the configuration of the PMC */

+#define LOWPOWER_CFG_SELCLOCK_12MHZ \

+    1 /*!< The 12 MHz clock is used during the configuration of the PMC (to speed up PMC configuration process)*/

+

+#define LOWPOWER_CFG_SELMEMSUPPLY_LDOMEM 0 /*!< In DEEP SLEEP power mode, the Memories are supplied by the LDO_MEM */

+#define LOWPOWER_CFG_SELMEMSUPPLY_LDODEEPSLEEP \

+    1 /*!< In DEEP SLEEP power mode, the Memories are supplied by the LDO_DEEP_SLEEP (or DCDC) */

+

+#define LOWPOWER_CFG_MEMLOWPOWERMODE_SOURCEBIASING                                                                     \

+    0 /*!< All SRAM instances use "Source Biasing" as low power mode technic (it is recommended to set LDO_MEM as high \

+         as possible -- 1.1V typical -- during low power mode) */

+#define LOWPOWER_CFG_MEMLOWPOWERMODE_VOLTAGESCALING                                                                    \

+    1 /*!< All SRAM instances use "Voltage Scaling" as low power mode technic (it is recommended to set LDO_MEM as low \

+         as possible -- down to 0.7V -- during low power mode) */

+

+#define LOWPOWER_CFG_LDODEEPSLEEPREF_FLASHBUFFER 0 /*!< LDO DEEP SLEEP uses Flash Buffer as reference  */

+#define LOWPOWER_CFG_LDODEEPSLEEPREF_BANDGAG0P8V 1 /*!< LDO DEEP SLEEP uses Band Gap 0.8V as reference */

+

+/* CPU Retention Control*/

+#define LOWPOWER_CPURETCTRL_ENA_INDEX           0

+#define LOWPOWER_CPURETCTRL_ENA_MASK            (0x1UL << LOWPOWER_CPURETCTRL_ENA_INDEX)

+#define LOWPOWER_CPURETCTRL_MEMBASE_INDEX       1

+#define LOWPOWER_CPURETCTRL_MEMBASE_MASK        (0x1FFFUL << LOWPOWER_CPURETCTRL_MEMBASE_INDEX)

+#define LOWPOWER_CPURETCTRL_RETDATALENGTH_INDEX 14

+#define LOWPOWER_CPURETCTRL_RETDATALENGTH_MASK  (0x3FFUL << LOWPOWER_CPURETCTRL_RETDATALENGTH_INDEX)

+

+/* Voltgae setting*/

+#define DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ \

+    (100000000U) /* Maximum System Frequency allowed with DCDC Power Profile LOW */

+#define DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ \

+    (130000000U) /* Maximum System Frequency allowed with DCDC Power Profile MEDIUM */

+#define DCDC_POWER_PROFILE_HIGH_MAX_FREQ_HZ \

+    (150000000U)                       /* Maximum System Frequency allowed with DCDC Power Profile HIGH */

+#define PROCESS_NNN_AVG_HZ (19300000U) /* Average Ring OScillator value for Nominal (NNN) Manufacturing Process */

+#define PROCESS_NNN_STD_HZ \

+    (400000U) /* Standard Deviation Ring OScillator value for Nominal (NNN) Manufacturing Process */

+#define PROCESS_NNN_LIMITS \

+    (6U) /* Nominal (NNN) Manufacturing Process Ring Oscillator values limit (with respect to the Average value) */

+#define PROCESS_NNN_MIN_HZ \

+    (PROCESS_NNN_AVG_HZ -  \

+     (PROCESS_NNN_LIMITS * \

+      PROCESS_NNN_STD_HZ)) /* Minimum Ring OScillator value for Nominal (NNN) Manufacturing Process */

+#define PROCESS_NNN_MAX_HZ \

+    (PROCESS_NNN_AVG_HZ +  \

+     (PROCESS_NNN_LIMITS * \

+      PROCESS_NNN_STD_HZ))         /* Maximum Ring OScillator value for Nominal (NNN) Manufacturing Process */

+#define VOLTAGE_SSS_LOW_MV (1075U) /* Voltage Settings for : Process=SSS, DCDC Power Profile=LOW */

+#define VOLTAGE_SSS_MED_MV (1150U) /* Voltage Settings for : Process=SSS, DCDC Power Profile=MEDIUM */

+#define VOLTAGE_SSS_HIG_MV (1200U) /* Voltage Settings for : Process=SSS, DCDC Power Profile=HIGH */

+#define VOLTAGE_NNN_LOW_MV (1000U) /* Voltage Settings for : Process=NNN, DCDC Power Profile=LOW */

+#define VOLTAGE_NNN_MED_MV (1100U) /* Voltage Settings for : Process=NNN, DCDC Power Profile=MEDIUM */

+#define VOLTAGE_NNN_HIG_MV (1150U) /* Voltage Settings for : Process=NNN, DCDC Power Profile=HIGH */

+#define VOLTAGE_FFF_LOW_MV (1000U) /* Voltage Settings for : Process=FFF, DCDC Power Profile=LOW */

+#define VOLTAGE_FFF_MED_MV (1025U) /* Voltage Settings for : Process=FFF, DCDC Power Profile=MEDIUM */

+#define VOLTAGE_FFF_HIG_MV (1050U) /* Voltage Settings for : Process=FFF, DCDC Power Profile=HIGH */

+

+/**

+ * @brief LDO Voltage control in Low Power Modes

+ */

+#define LOWPOWER_VOLTAGE_LDO_PMU_INDEX        0

+#define LOWPOWER_VOLTAGE_LDO_PMU_MASK         (0x1FULL << LOWPOWER_VOLTAGE_LDO_PMU_INDEX)

+#define LOWPOWER_VOLTAGE_LDO_MEM_INDEX        5

+#define LOWPOWER_VOLTAGE_LDO_MEM_MASK         (0x1FULL << LOWPOWER_VOLTAGE_LDO_MEM_INDEX)

+#define LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX 10

+#define LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_MASK  (0x7ULL << LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX)

+#define LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX  19

+#define LOWPOWER_VOLTAGE_LDO_PMU_BOOST_MASK   (0x1FULL << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX)

+#define LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX  24

+#define LOWPOWER_VOLTAGE_LDO_MEM_BOOST_MASK   (0x1FULL << LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX)

+#define LOWPOWER_VOLTAGE_DCDC_INDEX           29

+#define LOWPOWER_VOLTAGE_DCDC_MASK            (0xFULL << LOWPOWER_VOLTAGE_DCDC_INDEX)

+

+/*! @brief set and clear bit MACRO's. */

+#define U32_SET_BITS(P, B) ((*(uint32_t *)P) |= (B))

+#define U32_CLR_BITS(P, B) ((*(uint32_t *)P) &= ~(B))

+/* Return values from Config (N-2) page of flash */

+#define GET_16MXO_TRIM() (*(uint32_t *)0x9FCC8)

+#define GET_32KXO_TRIM() (*(uint32_t *)0x9FCCC)

+

+#define CPU_RETENTION_RAMX_STORAGE_START_ADDR (0x04006000)

+

+#define XO_SLAVE_EN (1)

+/*******************************************************************************

+ * Codes

+ ******************************************************************************/

+

+/*******************************************************************************

+ * LOCAL FUNCTIONS PROTOTYPES

+ ******************************************************************************/

+static void lf_get_deepsleep_core_supply_cfg(uint32_t exclude_from_pd, uint32_t *dcdc_voltage);

+static uint32_t lf_set_ldo_ao_ldo_mem_voltage(uint32_t p_lp_mode, uint32_t p_dcdc_voltage);

+static uint32_t lf_wakeup_io_ctrl(uint32_t p_wakeup_io_ctrl);

+static uint8_t CLOCK_u8OscCapConvert(uint8_t u8OscCap, uint8_t u8CapBankDiscontinuity);

+

+static void lowpower_set_dcdc_power_profile(lowpower_dcdc_power_profile_enum dcdc_power_profile);

+static lowpower_process_corner_enum lowpower_get_part_process_corner(void);

+static void lowpower_set_voltage_for_process(lowpower_dcdc_power_profile_enum dcdc_power_profile);

+

+/**

+ * @brief   Configures and enters in low power mode

+ * @param   p_lowpower_cfg: pointer to a structure that contains all low power mode parameters

+ * @return  Nothing

+ *

+ *          !!! IMPORTANT NOTES :

+ *           1 - CPU Interrupt Enable registers are updated with p_lowpower_cfg->WAKEUPINT. They are NOT restored by the

+ * API.

+ *           2 - The Non Maskable Interrupt (NMI) should be disable before calling this API (otherwise, there is a risk

+ * of Dead Lock).

+ *           3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip

+ * reset)

+ */

+static void POWER_EnterLowPower(LPC_LOWPOWER_T *p_lowpower_cfg);

+

+/**

+ * @brief

+ * @param

+ * @return

+ */

+static void lf_set_dcdc_power_profile_low(void)

+{

+#define DCDC_POWER_PROFILE_LOW_0_ADDRS (0x9FCE0U)

+#define DCDC_POWER_PROFILE_LOW_1_ADDRS (0x9FCE4U)

+

+    uint32_t dcdcTrimValue0 = (*((volatile unsigned int *)(DCDC_POWER_PROFILE_LOW_0_ADDRS)));

+    uint32_t dcdcTrimValue1 = (*((volatile unsigned int *)(DCDC_POWER_PROFILE_LOW_1_ADDRS)));

+

+    if (0UL != (dcdcTrimValue0 & 0x1UL))

+    {

+        PMC->DCDC0 = dcdcTrimValue0 >> 1;

+        PMC->DCDC1 = dcdcTrimValue1;

+    }

+}

+

+/**

+ * @brief   Configures and enters in low power mode

+ * @param           : p_lowpower_cfg

+ * @return  Nothing

+ */

+static void POWER_EnterLowPower(LPC_LOWPOWER_T *p_lowpower_cfg)

+{

+    lowpower_driver_interface_t *s_lowpowerDriver;

+    /* Judging the core and call the corresponding API base address*/

+    if (0UL == Chip_GetVersion())

+    {

+        s_lowpowerDriver = (lowpower_driver_interface_t *)(0x130010d4UL);

+    }

+    else

+    {

+        s_lowpowerDriver = (lowpower_driver_interface_t *)(0x13001204UL);

+    }

+    /* PMC clk set to 12 MHZ */

+    p_lowpower_cfg->CFG |= (uint32_t)LOWPOWER_CFG_SELCLOCK_12MHZ << LOWPOWER_CFG_SELCLOCK_INDEX;

+

+    /* Enable Analog References fast wake-up in case of wake-up from a low power mode (DEEP SLEEP, POWER DOWN and DEEP

+     * POWER DOWN) and Hardware Pin reset */

+    PMC->REFFASTWKUP = (PMC->REFFASTWKUP & (~PMC_REFFASTWKUP_LPWKUP_MASK) & (~PMC_REFFASTWKUP_HWWKUP_MASK)) |

+                       PMC_REFFASTWKUP_LPWKUP(1) | PMC_REFFASTWKUP_HWWKUP(1);

+

+    /* SRAM uses Voltage Scaling in all Low Power modes */

+    PMC->SRAMCTRL = (PMC->SRAMCTRL & (~PMC_SRAMCTRL_SMB_MASK)) | PMC_SRAMCTRL_SMB(3);

+

+    /* CPU Retention configuration : preserve the value of FUNCRETENTIONCTRL.RET_LENTH which is a Hardware defined

+     * parameter. */

+    p_lowpower_cfg->CPURETCTRL = (SYSCON->FUNCRETENTIONCTRL & SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK) |

+                                 (p_lowpower_cfg->CPURETCTRL & (~SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK));

+

+    /* Switch System Clock to FRO12Mhz (the configuration before calling this function will not be restored back) */

+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                      /* Switch main clock to FRO12MHz */

+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);              /* Main clock divided by 1 */

+    SYSCON->FMCCR = (SYSCON->FMCCR & 0xFFFF0000UL) | 0x201AUL; /* Adjust FMC waiting time cycles */

+    lf_set_dcdc_power_profile_low(); /* Align DCDC Power profile with the 12 MHz clock (DCDC Power Profile LOW) */

+

+    (*(s_lowpowerDriver->set_lowpower_mode))(p_lowpower_cfg);

+

+    /* Restore the configuration of the MISCCTRL Register : LOWPWR_FLASH_BUF = 0, LDOMEMBLEEDDSLP = 0, LDOMEMHIGHZMODE =

+     * 0 */

+    PMC->MISCCTRL &= (~PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK) & (~PMC_MISCCTRL_DISABLE_BLEED_MASK) &

+                     (~PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK);

+}

+

+/**

+ * @brief   Shut off the Flash and execute the _WFI(), then power up the Flash after wake-up event

+ * @param   None

+ * @return  Nothing

+ */

+void POWER_CycleCpuAndFlash(void)

+{

+    /* Judging the core and call the corresponding API base address*/

+    lowpower_driver_interface_t *s_lowpowerDriver;

+    if (0UL == Chip_GetVersion())

+    {

+        s_lowpowerDriver = (lowpower_driver_interface_t *)(0x130010d4UL);

+    }

+    else

+    {

+        s_lowpowerDriver = (lowpower_driver_interface_t *)(0x13001204UL);

+    }

+    (*(s_lowpowerDriver->power_cycle_cpu_and_flash))();

+};

+

+/**

+ * brief    PMC Deep Sleep function call

+ * return   nothing

+ */

+void POWER_EnterDeepSleep(uint32_t exclude_from_pd,

+                          uint32_t sram_retention_ctrl,

+                          uint64_t wakeup_interrupts,

+                          uint32_t hardware_wake_ctrl)

+{

+    LPC_LOWPOWER_T lv_low_power_mode_cfg; /* Low Power Mode configuration structure */

+    uint32_t cpu0_nmi_enable;

+    uint32_t cpu0_int_enable_0;

+    uint32_t cpu0_int_enable_1;

+    uint32_t dcdc_voltage;

+    uint32_t pmc_reset_ctrl;

+    /* Clear Low Power Mode configuration variable */

+    (void)memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T));

+

+    /* Configure Low Power Mode configuration variable */

+    lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_DEEPSLEEP

+                                 << LOWPOWER_CFG_LPMODE_INDEX; /* DEEPSLEEP mode */

+

+    lf_get_deepsleep_core_supply_cfg(exclude_from_pd, &dcdc_voltage);

+

+    if (((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_USB1_PHY) != 0UL) &&

+        ((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_LDOUSBHS) != 0UL))

+    {

+        /* USB High Speed is required as wake-up source in Deep Sleep mode: make sure LDO FLASH NV stays powered during

+         * deep-sleep */

+        exclude_from_pd = exclude_from_pd | (uint32_t)kPDRUNCFG_PD_LDOFLASHNV;

+    }

+

+    /* DCDC will be always used during Deep Sleep (instead of LDO Deep Sleep); Make sure LDO MEM & Analog references

+     * will stay powered, Shut down ROM */

+    lv_low_power_mode_cfg.PDCTRL0 = (~exclude_from_pd & ~(uint32_t)kPDRUNCFG_PD_DCDC & ~(uint32_t)kPDRUNCFG_PD_LDOMEM &

+                                     ~(uint32_t)kPDRUNCFG_PD_BIAS) |

+                                    (uint32_t)kPDRUNCFG_PD_LDODEEPSLEEP | (uint32_t)kPDRUNCFG_PD_ROM;

+

+    /* Voltage control in DeepSleep Low Power Modes */

+    /* The Memories Voltage settings below are for voltage scaling */

+    lv_low_power_mode_cfg.VOLTAGE = lf_set_ldo_ao_ldo_mem_voltage(LOWPOWER_CFG_LPMODE_POWERDOWN, dcdc_voltage);

+

+    /* SRAM retention control during POWERDOWN */

+    lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl;

+

+    /* CPU Wake up & Interrupt sources control */

+    lv_low_power_mode_cfg.WAKEUPINT = wakeup_interrupts;

+    lv_low_power_mode_cfg.WAKEUPSRC = wakeup_interrupts;

+

+    /* Interrupts that allow DMA transfers with Flexcomm without waking up the Processor */

+    if (0UL != (hardware_wake_ctrl & (LOWPOWER_HWWAKE_PERIPHERALS | LOWPOWER_HWWAKE_SDMA0 | LOWPOWER_HWWAKE_SDMA1)))

+    {

+        lv_low_power_mode_cfg.HWWAKE = (hardware_wake_ctrl & ~LOWPOWER_HWWAKE_FORCED) | LOWPOWER_HWWAKE_ENABLE_FRO192M;

+    }

+

+    cpu0_nmi_enable = SYSCON->NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK; /* Save the configuration of the NMI Register */

+    SYSCON->NMISRC &= ~SYSCON_NMISRC_NMIENCPU0_MASK;                 /* Disable NMI of CPU0 */

+

+    /* Save the configuration of the CPU interrupt enable Registers (because they are overwritten inside the low power

+     * API */

+    cpu0_int_enable_0 = NVIC->ISER[0];

+    cpu0_int_enable_1 = NVIC->ISER[1];

+

+    pmc_reset_ctrl = PMC->RESETCTRL;

+    if (0UL != (pmc_reset_ctrl & PMC_RESETCTRL_BODCORERESETENABLE_MASK))

+    {

+        /* BoD CORE reset is activated, so make sure BoD Core won't be shutdown */

+        lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_BODCORE;

+    }

+    if (0UL != (pmc_reset_ctrl & PMC_RESETCTRL_BODVBATRESETENABLE_MASK))

+    {

+        /* BoD VBAT reset is activated, so make sure BoD VBAT won't be shutdown */

+        lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_BODVBAT;

+    }

+

+    /* Enter low power mode */

+    POWER_EnterLowPower(&lv_low_power_mode_cfg);

+

+    /* Restore the configuration of the NMI Register */

+    SYSCON->NMISRC |= cpu0_nmi_enable;

+

+    /* Restore the configuration of the CPU interrupt enable Registers (because they have been overwritten inside the

+     * low power API */

+    NVIC->ISER[0] = cpu0_int_enable_0;

+    NVIC->ISER[1] = cpu0_int_enable_1;

+}

+

+/**

+ * brief    PMC power Down function call

+ * return   nothing

+ */

+void POWER_EnterPowerDown(uint32_t exclude_from_pd,

+                          uint32_t sram_retention_ctrl,

+                          uint64_t wakeup_interrupts,

+                          uint32_t cpu_retention_ctrl)

+{

+    LPC_LOWPOWER_T lv_low_power_mode_cfg; /* Low Power Mode configuration structure */

+    uint32_t cpu0_nmi_enable;

+    uint32_t cpu0_int_enable_0;

+    uint32_t cpu0_int_enable_1;

+    uint64_t wakeup_src_int;

+    uint32_t pmc_reset_ctrl;

+

+    uint32_t analog_ctrl_regs[12]; /* To store Analog Controller Regristers */

+

+    /* Clear Low Power Mode configuration variable */

+    (void)memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T));

+

+    /* Configure Low Power Mode configuration variable */

+    lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_POWERDOWN

+                                 << LOWPOWER_CFG_LPMODE_INDEX; /* POWER DOWN mode */

+

+    /* Only FRO32K, XTAL32K, COMP, BIAS and LDO_MEM can be stay powered during POWERDOWN (valid from application point

+     * of view; Hardware allows BODVBAT, LDODEEPSLEEP and FRO1M to stay powered, that's why they are excluded below) */

+    lv_low_power_mode_cfg.PDCTRL0 = (~exclude_from_pd) | (uint32_t)kPDRUNCFG_PD_BODVBAT | (uint32_t)kPDRUNCFG_PD_FRO1M |

+                                    (uint32_t)kPDRUNCFG_PD_LDODEEPSLEEP;

+

+    /* SRAM retention control during POWERDOWN */

+    lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl;

+

+    /* Sanity check: If retention is required for any of SRAM instances, make sure LDO MEM will stay powered */

+    if ((sram_retention_ctrl & 0x7FFFUL) != 0UL)

+    {

+        lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_LDOMEM;

+    }

+

+    /* Voltage control in Low Power Modes */

+    /* The Memories Voltage settings below are for voltage scaling */

+    lv_low_power_mode_cfg.VOLTAGE = lf_set_ldo_ao_ldo_mem_voltage(LOWPOWER_CFG_LPMODE_POWERDOWN, 0);

+

+    /* CPU0 retention Ctrl.

+     * For the time being, we do not allow customer to relocate the CPU retention area in SRAMX, meaning that the

+     * retention area range is [0x0400_6000 - 0x0400_6600] (beginning of RAMX2) If required by customer,

+     * cpu_retention_ctrl[13:1] will be used for that to modify the default retention area

+     */

+    lv_low_power_mode_cfg.CPURETCTRL =

+        (cpu_retention_ctrl & LOWPOWER_CPURETCTRL_ENA_MASK) |

+        ((((uint32_t)CPU_RETENTION_RAMX_STORAGE_START_ADDR >> 2UL) << LOWPOWER_CPURETCTRL_MEMBASE_INDEX) &

+         LOWPOWER_CPURETCTRL_MEMBASE_MASK);

+    if (0UL != (cpu_retention_ctrl & 0x1UL))

+    {

+        /* CPU retention is required: store Analog Controller Registers */

+        analog_ctrl_regs[0]  = ANACTRL->FRO192M_CTRL;

+        analog_ctrl_regs[1]  = ANACTRL->ANALOG_CTRL_CFG;

+        analog_ctrl_regs[2]  = ANACTRL->ADC_CTRL;

+        analog_ctrl_regs[3]  = ANACTRL->XO32M_CTRL;

+        analog_ctrl_regs[4]  = ANACTRL->BOD_DCDC_INT_CTRL;

+        analog_ctrl_regs[5]  = ANACTRL->RINGO0_CTRL;

+        analog_ctrl_regs[6]  = ANACTRL->RINGO1_CTRL;

+        analog_ctrl_regs[7]  = ANACTRL->RINGO2_CTRL;

+        analog_ctrl_regs[8]  = ANACTRL->LDO_XO32M;

+        analog_ctrl_regs[9]  = ANACTRL->AUX_BIAS;

+        analog_ctrl_regs[10] = ANACTRL->USBHS_PHY_CTRL;

+        analog_ctrl_regs[11] = ANACTRL->USBHS_PHY_TRIM;

+    }

+

+    /* CPU Wake up & Interrupt sources control : only WAKEUP_GPIO_GLOBALINT0, WAKEUP_GPIO_GLOBALINT1, WAKEUP_FLEXCOMM3,

+     * WAKEUP_ACMP_CAPT, WAKEUP_RTC_LITE_ALARM_WAKEUP, WAKEUP_OS_EVENT_TIMER, WAKEUP_ALLWAKEUPIOS */

+    wakeup_src_int = (uint64_t)(WAKEUP_GPIO_GLOBALINT0 | WAKEUP_GPIO_GLOBALINT1 | WAKEUP_FLEXCOMM3 | WAKEUP_ACMP_CAPT |

+                                WAKEUP_RTC_LITE_ALARM_WAKEUP | WAKEUP_OS_EVENT_TIMER | WAKEUP_ALLWAKEUPIOS);

+    lv_low_power_mode_cfg.WAKEUPINT = wakeup_interrupts & wakeup_src_int;

+    lv_low_power_mode_cfg.WAKEUPSRC = wakeup_interrupts & wakeup_src_int;

+

+    cpu0_nmi_enable = SYSCON->NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK; /* Save the configuration of the NMI Register */

+    SYSCON->NMISRC &= ~SYSCON_NMISRC_NMIENCPU0_MASK;                 /* Disable NMI of CPU0 */

+

+    /* Save the configuration of the CPU interrupt enable Registers (because they are overwritten inside the low power

+     * API */

+    cpu0_int_enable_0 = NVIC->ISER[0];

+    cpu0_int_enable_1 = NVIC->ISER[1];

+

+    pmc_reset_ctrl = PMC->RESETCTRL;

+    /* Disable BoD VBAT and BoD Core resets */

+    PMC->RESETCTRL =

+        pmc_reset_ctrl & (~(PMC_RESETCTRL_BODVBATRESETENABLE_MASK | PMC_RESETCTRL_BODCORERESETENABLE_MASK));

+

+    /* Enter low power mode */

+    POWER_EnterLowPower(&lv_low_power_mode_cfg);

+

+    /*** We'll reach this point in case of POWERDOWN with CPU retention or if the POWERDOWN has not been taken (for

+      instance because an interrupt is pending). In case of CPU retention, assumption is that the SRAM containing the

+      stack used to call this function shall be preserved during low power ***/

+

+    /* Restore the configuration of the NMI Register */

+    SYSCON->NMISRC |= cpu0_nmi_enable;

+

+    /* Restore PMC RESETCTRL register */

+    PMC->RESETCTRL = pmc_reset_ctrl;

+

+    /* Restore the configuration of the CPU interrupt enable Registers (because they have been overwritten inside the

+     * low power API */

+    NVIC->ISER[0] = cpu0_int_enable_0;

+    NVIC->ISER[1] = cpu0_int_enable_1;

+

+    if (0UL != (cpu_retention_ctrl & 0x1UL))

+    {

+        /* Restore Analog Controller Registers */

+        ANACTRL->FRO192M_CTRL      = analog_ctrl_regs[0] | ANACTRL_FRO192M_CTRL_WRTRIM_MASK;

+        ANACTRL->ANALOG_CTRL_CFG   = analog_ctrl_regs[1];

+        ANACTRL->ADC_CTRL          = analog_ctrl_regs[2];

+        ANACTRL->XO32M_CTRL        = analog_ctrl_regs[3];

+        ANACTRL->BOD_DCDC_INT_CTRL = analog_ctrl_regs[4];

+        ANACTRL->RINGO0_CTRL       = analog_ctrl_regs[5];

+        ANACTRL->RINGO1_CTRL       = analog_ctrl_regs[6];

+        ANACTRL->RINGO2_CTRL       = analog_ctrl_regs[7];

+        ANACTRL->LDO_XO32M         = analog_ctrl_regs[8];

+        ANACTRL->AUX_BIAS          = analog_ctrl_regs[9];

+        ANACTRL->USBHS_PHY_CTRL    = analog_ctrl_regs[10];

+        ANACTRL->USBHS_PHY_TRIM    = analog_ctrl_regs[11];

+    }

+}

+

+/**

+ * brief    PMC Deep Sleep Power Down function call

+ * return   nothing

+ */

+void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd,

+                              uint32_t sram_retention_ctrl,

+                              uint64_t wakeup_interrupts,

+                              uint32_t wakeup_io_ctrl)

+{

+    LPC_LOWPOWER_T lv_low_power_mode_cfg; /* Low Power Mode configuration structure */

+    uint32_t cpu0_nmi_enable;

+    uint32_t cpu0_int_enable_0;

+    uint32_t cpu0_int_enable_1;

+    uint32_t pmc_reset_ctrl;

+

+    /* Clear Low Power Mode configuration variable */

+    (void)memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T));

+

+    /* Configure Low Power Mode configuration variable */

+    lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN

+                                 << LOWPOWER_CFG_LPMODE_INDEX; /* DEEP POWER DOWN mode */

+

+    /* Only FRO32K, XTAL32K and LDO_MEM can be stay powered during DEEPPOWERDOWN (valid from application point of view;

+     * Hardware allows BODVBAT, BIAS FRO1M and COMP to stay powered, that's why they are excluded below) */

+    lv_low_power_mode_cfg.PDCTRL0 = (~exclude_from_pd) | (uint32_t)kPDRUNCFG_PD_BIAS | (uint32_t)kPDRUNCFG_PD_BODVBAT |

+                                    (uint32_t)kPDRUNCFG_PD_FRO1M | (uint32_t)kPDRUNCFG_PD_COMP;

+

+    /* SRAM retention control during DEEPPOWERDOWN */

+    sram_retention_ctrl =

+        sram_retention_ctrl &

+        (~(LOWPOWER_SRAMRETCTRL_RETEN_RAMX0 | LOWPOWER_SRAMRETCTRL_RETEN_RAMX1 | LOWPOWER_SRAMRETCTRL_RETEN_RAM00));

+

+    /* SRAM retention control during DEEPPOWERDOWN */

+    lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl;

+

+    /* Sanity check: If retention is required for any of SRAM instances, make sure LDO MEM will stay powered */

+    if ((sram_retention_ctrl & 0x7FFFUL) != 0UL)

+    {

+        lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_LDOMEM;

+    }

+

+    /* Voltage control in Low Power Modes */

+    /* The Memories Voltage settings below are for voltage scaling */

+    lv_low_power_mode_cfg.VOLTAGE = lf_set_ldo_ao_ldo_mem_voltage(LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN, 0);

+

+    lv_low_power_mode_cfg.WAKEUPINT =

+        wakeup_interrupts & (WAKEUP_RTC_LITE_ALARM_WAKEUP |

+                             WAKEUP_OS_EVENT_TIMER); /* CPU Wake up sources control : only WAKEUP_RTC_LITE_ALARM_WAKEUP,

+                                                        WAKEUP_OS_EVENT_TIMER */

+    lv_low_power_mode_cfg.WAKEUPSRC =

+        wakeup_interrupts &

+        (WAKEUP_RTC_LITE_ALARM_WAKEUP | WAKEUP_OS_EVENT_TIMER |

+         WAKEUP_ALLWAKEUPIOS); /*!< Hardware Wake up sources control: : only WAKEUP_RTC_LITE_ALARM_WAKEUP,

+                                  WAKEUP_OS_EVENT_TIMER and WAKEUP_ALLWAKEUPIOS */

+

+    /* Wake up I/O sources */

+    lv_low_power_mode_cfg.WAKEUPIOSRC = lf_wakeup_io_ctrl(wakeup_io_ctrl);

+

+    cpu0_nmi_enable = SYSCON->NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK; /* Save the configuration of the NMI Register */

+    SYSCON->NMISRC &= ~SYSCON_NMISRC_NMIENCPU0_MASK;                 /* Disable NMI of CPU0 */

+

+    /* Save the configuration of the CPU interrupt enable Registers */

+    cpu0_int_enable_0 = NVIC->ISER[0];

+    cpu0_int_enable_1 = NVIC->ISER[1];

+

+    /* Save the configuration of the PMC RESETCTRL register */

+    pmc_reset_ctrl = PMC->RESETCTRL;

+    /* Disable BoD VBAT and BoD Core resets */

+    PMC->RESETCTRL =

+        pmc_reset_ctrl & (~(PMC_RESETCTRL_BODVBATRESETENABLE_MASK | PMC_RESETCTRL_BODCORERESETENABLE_MASK));

+

+    /* Disable LDO MEM bleed current */

+    // PMC->MISCCTRL |= PMC_MISCCTRL_DISABLE_BLEED_MASK;

+

+    /* Enter low power mode */

+    POWER_EnterLowPower(&lv_low_power_mode_cfg);

+

+    /* Restore the configuration of the NMI Register */

+    SYSCON->NMISRC |= cpu0_nmi_enable;

+

+    /* Restore PMC RESETCTRL register */

+    PMC->RESETCTRL = pmc_reset_ctrl;

+

+    /* Restore the configuration of the CPU interrupt enable Registers */

+    NVIC->ISER[0] = cpu0_int_enable_0;

+    NVIC->ISER[1] = cpu0_int_enable_1;

+}

+

+/**

+ * brief    PMC Sleep function call

+ * return   nothing

+ */

+void POWER_EnterSleep(void)

+{

+    uint32_t pmsk;

+    pmsk = __get_PRIMASK();

+    __disable_irq();

+    SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;

+    __WFI();

+    __set_PRIMASK(pmsk);

+}

+

+/**

+ * @brief   Get Digital Core logic supply source to be used during Deep Sleep.

+ * @param [in]  exclude_from_pd: COmpoenents NOT to be powered down during Deep Sleep

+ * @param [out] core_supply: 0 = LDO DEEPSLEEP will be used / 1 = DCDC will be used

+ * @param [out] dcdc_voltage: as defined by V_DCDC_* in fsl_power.h

+

+ * @return  Nothing

+ */

+static void lf_get_deepsleep_core_supply_cfg(uint32_t exclude_from_pd, uint32_t *dcdc_voltage)

+{

+    *dcdc_voltage = (uint32_t)V_DCDC_0P950; /* Default value */

+

+    if (((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_USB1_PHY) != 0UL) &&

+        ((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_LDOUSBHS) != 0UL))

+    {

+        /* USB High Speed is required as wake-up source in Deep Sleep mode */

+        PMC->MISCCTRL |= PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK; /* Force flash buffer in low power mode */

+        *dcdc_voltage =

+            (uint32_t)V_DCDC_1P000; /* Set DCDC voltage to be 1.000 V (USB HS IP cannot work below 0.990 V) */

+    }

+}

+

+/**

+ * @brief

+ * @param

+ * @return

+ */

+static uint32_t lf_set_ldo_ao_ldo_mem_voltage(uint32_t p_lp_mode, uint32_t p_dcdc_voltage)

+{

+#define FLASH_NMPA_LDO_AO_ADDRS                (0x9FCF4U)

+#define FLASH_NMPA_LDO_AO_DSLP_TRIM_VALID_MASK (0x100U)

+#define FLASH_NMPA_LDO_AO_DSLP_TRIM_MASK       (0x3E00U)

+#define FLASH_NMPA_LDO_AO_DSLP_TRIM_SHIFT      (9U)

+#define FLASH_NMPA_LDO_AO_PDWN_TRIM_VALID_MASK (0x10000U)

+#define FLASH_NMPA_LDO_AO_PDWN_TRIM_MASK       (0x3E0000U)

+#define FLASH_NMPA_LDO_AO_PDWN_TRIM_SHIFT      (17U)

+#define FLASH_NMPA_LDO_AO_DPDW_TRIM_VALID_MASK (0x1000000U)

+#define FLASH_NMPA_LDO_AO_DPDW_TRIM_MASK       (0x3E000000U)

+#define FLASH_NMPA_LDO_AO_DPDW_TRIM_SHIFT      (25U)

+

+    uint32_t ldo_ao_trim, voltage;

+    uint32_t lv_v_ldo_pmu, lv_v_ldo_pmu_boost;

+

+    ldo_ao_trim = (*((volatile unsigned int *)(FLASH_NMPA_LDO_AO_ADDRS)));

+

+    switch (p_lp_mode)

+    {

+        case LOWPOWER_CFG_LPMODE_DEEPSLEEP:

+        {

+            if ((ldo_ao_trim & FLASH_NMPA_LDO_AO_DSLP_TRIM_VALID_MASK) != 0UL)

+            {

+                /* Apply settings coming from Flash */

+                lv_v_ldo_pmu = (ldo_ao_trim & FLASH_NMPA_LDO_AO_DSLP_TRIM_MASK) >> FLASH_NMPA_LDO_AO_DSLP_TRIM_SHIFT;

+                lv_v_ldo_pmu_boost = lv_v_ldo_pmu - 2UL; /* - 50 mV */

+            }

+            else

+            {

+                /* Apply default settings */

+                lv_v_ldo_pmu       = (uint32_t)V_AO_0P900;

+                lv_v_ldo_pmu_boost = (uint32_t)V_AO_0P850;

+            }

+        }

+        break;

+

+        case LOWPOWER_CFG_LPMODE_POWERDOWN:

+        {

+            if ((ldo_ao_trim & FLASH_NMPA_LDO_AO_PDWN_TRIM_VALID_MASK) != 0UL)

+            {

+                /* Apply settings coming from Flash */

+                lv_v_ldo_pmu = (ldo_ao_trim & FLASH_NMPA_LDO_AO_PDWN_TRIM_MASK) >> FLASH_NMPA_LDO_AO_PDWN_TRIM_SHIFT;

+                lv_v_ldo_pmu_boost = lv_v_ldo_pmu - 2UL; /* - 50 mV */

+            }

+            else

+            {

+                /* Apply default settings */

+                lv_v_ldo_pmu       = (uint32_t)V_AO_0P800;

+                lv_v_ldo_pmu_boost = (uint32_t)V_AO_0P750;

+            }

+        }

+        break;

+

+        case LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN:

+        {

+            if ((ldo_ao_trim & FLASH_NMPA_LDO_AO_DPDW_TRIM_VALID_MASK) != 0UL)

+            {

+                /* Apply settings coming from Flash */

+                lv_v_ldo_pmu = (ldo_ao_trim & FLASH_NMPA_LDO_AO_DPDW_TRIM_MASK) >> FLASH_NMPA_LDO_AO_DPDW_TRIM_SHIFT;

+                lv_v_ldo_pmu_boost = lv_v_ldo_pmu - 2UL; /* - 50 mV */

+            }

+            else

+            {

+                /* Apply default settings */

+                lv_v_ldo_pmu       = (uint32_t)V_AO_0P800;

+                lv_v_ldo_pmu_boost = (uint32_t)V_AO_0P750;

+            }

+        }

+        break;

+

+        default:

+            /* Should never reach this point */

+            lv_v_ldo_pmu       = (uint32_t)V_AO_1P100;

+            lv_v_ldo_pmu_boost = (uint32_t)V_AO_1P050;

+            break;

+    }

+

+    /* The Memories Voltage settings below are for voltage scaling */

+    voltage =

+        (lv_v_ldo_pmu << LOWPOWER_VOLTAGE_LDO_PMU_INDEX) |               /*  */

+        (lv_v_ldo_pmu_boost << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX) |   /*  */

+        ((uint32_t)V_AO_0P750 << LOWPOWER_VOLTAGE_LDO_MEM_INDEX) |       /* Set to 0.75V (voltage Scaling) */

+        ((uint32_t)V_AO_0P700 << LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX) | /* Set to 0.7V  (voltage Scaling) */

+        ((uint32_t)V_DEEPSLEEP_0P900

+         << LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX) |    /* Set to 0.90 V (Not used because LDO_DEEP_SLEEP is disabled)*/

+        (p_dcdc_voltage << LOWPOWER_VOLTAGE_DCDC_INDEX) /*  */

+        ;

+

+    return (voltage);

+}

+

+/**

+ * @brief

+ * @param

+ * @return

+ */

+static uint32_t lf_wakeup_io_ctrl(uint32_t p_wakeup_io_ctrl)

+{

+    uint32_t wake_up_type;

+    uint32_t misc_ctrl_reg;

+    uint8_t use_external_pullupdown = 0;

+

+    /* Configure Pull up & Pull down based on the required wake-up edge */

+    CLOCK_EnableClock(kCLOCK_Iocon);

+

+    misc_ctrl_reg = 0UL;

+

+    /* Wake-up I/O 0 */

+    wake_up_type            = (p_wakeup_io_ctrl & 0x3UL) >> LOWPOWER_WAKEUPIOSRC_PIO0_INDEX;

+    use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_MASK) >>

+                                        LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX);

+

+    if (use_external_pullupdown == 0UL)

+    {

+        if ((wake_up_type == 1UL) || (wake_up_type == 3UL))

+        {

+            /* Rising edge and both rising and falling edges */

+            IOCON->PIO[1][1] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */

+            misc_ctrl_reg |= LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK;

+            p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK;

+        }

+        else

+        {

+            if (wake_up_type == 2UL)

+            {

+                /* Falling edge only */

+                IOCON->PIO[1][1] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */

+                misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK;

+                p_wakeup_io_ctrl |= LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK;

+            }

+            else

+            {

+                /* Wake-up I/O is disabled : set it as required by the user */

+                if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK) != 0UL)

+                {

+                    /* Wake-up I/O is configured as Plain Input */

+                    p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK;

+                }

+                else

+                {

+                    /* Wake-up I/O is configured as pull-up or pull-down */

+                    misc_ctrl_reg |= (~p_wakeup_io_ctrl) & LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK;

+                }

+            }

+        }

+    }

+    else

+    {

+        /* MISCCTRL[8]:WAKEUPIOCTRL[8]:00 -no pullup,pulldown, 10 - pulldown, 01 - pullup, 11 - reserved */

+        p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK;

+        misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK;

+    }

+

+    /* Wake-up I/O 1 */

+    wake_up_type            = (p_wakeup_io_ctrl & 0xCUL) >> LOWPOWER_WAKEUPIOSRC_PIO1_INDEX;

+    use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_MASK) >>

+                                        LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX);

+

+    if (use_external_pullupdown == 0UL)

+    {

+        if ((wake_up_type == 1UL) || (wake_up_type == 3UL))

+        {

+            /* Rising edge  and both rising and falling edges */

+            IOCON->PIO[0][28] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */

+            misc_ctrl_reg |= LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK;

+            p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK;

+        }

+        else

+        {

+            if (wake_up_type == 2UL)

+            {

+                /* Falling edge only */

+                IOCON->PIO[0][28] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */

+                misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK;

+                p_wakeup_io_ctrl |= LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK;

+            }

+            else

+            {

+                /* Wake-up I/O is disabled : set it as required by the user */

+                if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK) != 0UL)

+                {

+                    /* Wake-up I/O is configured as Plain Input */

+                    p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK;

+                }

+                else

+                {

+                    /* Wake-up I/O is configured as pull-up or pull-down */

+                    misc_ctrl_reg |= (~p_wakeup_io_ctrl) & LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK;

+                }

+            }

+        }

+    }

+    else

+    {

+        /* MISCCTRL[9]:WAKEUPIOCTRL[9]:00 -no pullup,pulldown, 10 - pulldown, 01 - pullup, 11 - reserved */

+        p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK;

+        misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK;

+    }

+

+    /* Wake-up I/O 2 */

+    wake_up_type            = (p_wakeup_io_ctrl & 0x30UL) >> LOWPOWER_WAKEUPIOSRC_PIO2_INDEX;

+    use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_MASK) >>

+                                        LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX);

+

+    if (use_external_pullupdown == 0UL)

+    {

+        if ((wake_up_type == 1UL) || (wake_up_type == 3UL))

+        {

+            /* Rising edge  and both rising and falling edges */

+            IOCON->PIO[1][18] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */

+            misc_ctrl_reg |= LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK;

+            p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK;

+        }

+        else

+        {

+            if (wake_up_type == 2UL)

+            {

+                /* Falling edge only */

+                IOCON->PIO[1][18] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */

+                misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK;

+                p_wakeup_io_ctrl |= LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK;

+            }

+            else

+            {

+                /* Wake-up I/O is disabled : set it as required by the user */

+                if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK) != 0UL)

+                {

+                    /* Wake-up I/O is configured as Plain Input */

+                    p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK;

+                }

+                else

+                {

+                    /* Wake-up I/O is configured as pull-up or pull-down */

+                    misc_ctrl_reg |= (~p_wakeup_io_ctrl) & LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK;

+                }

+            }

+        }

+    }

+    else

+    {

+        /* MISCCTRL[10]:WAKEUPIOCTRL[10]:00 -no pullup,pulldown, 10 - pulldown, 01 - pullup, 11 - reserved */

+        p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK;

+        misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK;

+    }

+

+    /* Wake-up I/O 3 */

+    wake_up_type            = (p_wakeup_io_ctrl & 0xC0UL) >> LOWPOWER_WAKEUPIOSRC_PIO3_INDEX;

+    use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_MASK) >>

+                                        LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX);

+

+    if (use_external_pullupdown == 0UL)

+    {

+        if ((wake_up_type == 1UL) || (wake_up_type == 3UL))

+        {

+            /* Rising edge  and both rising and falling edges */

+            IOCON->PIO[1][30] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */

+            misc_ctrl_reg |= LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK;

+            p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK;

+        }

+        else

+        {

+            if (wake_up_type == 2UL)

+            {

+                /* Falling edge only */

+                IOCON->PIO[1][30] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */

+                misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK;

+                p_wakeup_io_ctrl |= LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK;

+            }

+            else

+            {

+                /* Wake-up I/O is disabled : set it as required by the user */

+                if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK) != 0UL)

+                {

+                    /* Wake-up I/O is configured as Plain Input */

+                    p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK;

+                }

+                else

+                {

+                    /* Wake-up I/O is configured as pull-up or pull-down */

+                    misc_ctrl_reg |= (~p_wakeup_io_ctrl) & LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK;

+                }

+            }

+        }

+    }

+    else

+    {

+        /* MISCCTRL[11]:WAKEUPIOCTRL[11]:00 -no pullup,pulldown, 10 - pulldown, 01 - pullup, 11 - reserved */

+        p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK;

+        misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK;

+    }

+

+    PMC->MISCCTRL     = (PMC->MISCCTRL & 0xFFFFF0FFUL) | misc_ctrl_reg;

+    PMC->WAKEUPIOCTRL = p_wakeup_io_ctrl & 0xFFFUL;

+

+    /*

+     * Defined according to :

+     * - LOWPOWER_WAKEUPIOSRC_<DISABLE,RISING,FALLING,RISING_FALLING> in fsl_power.h

+     * - LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_<...> in fsl_power.h

+     */

+    return (p_wakeup_io_ctrl & 0xFFFUL);

+}

+

+/**

+ * @brief

+ * @param

+ * @return

+ */

+static uint8_t CLOCK_u8OscCapConvert(uint8_t u8OscCap, uint8_t u8CapBankDiscontinuity)

+{

+    /* Compensate for discontinuity in the capacitor banks */

+    if (u8OscCap < 64U)

+    {

+        if (u8OscCap >= u8CapBankDiscontinuity)

+        {

+            u8OscCap -= u8CapBankDiscontinuity;

+        }

+        else

+        {

+            u8OscCap = 0U;

+        }

+    }

+    else

+    {

+        if (u8OscCap <= (127U - u8CapBankDiscontinuity))

+        {

+            u8OscCap += u8CapBankDiscontinuity;

+        }

+        else

+        {

+            u8OscCap = 127U;

+        }

+    }

+    return u8OscCap;

+}

+

+/**

+ * @brief             Described in fsl_common.h

+ * @param

+ * @return

+ */

+static void lowpower_set_system_voltage(uint32_t system_voltage_mv)

+{

+    /*

+     * Set system voltage

+     */

+    uint32_t lv_ldo_ao       = (uint32_t)V_AO_1P100;   /* <ldo_ao> */

+    uint32_t lv_ldo_ao_boost = (uint32_t)V_AO_1P150;   /* <ldo_ao_boost> */

+    uint32_t lv_dcdc         = (uint32_t)V_DCDC_1P100; /* <dcdc> */

+

+    if (system_voltage_mv <= 950UL)

+    {

+        lv_dcdc         = (uint32_t)V_DCDC_0P950;

+        lv_ldo_ao       = (uint32_t)V_AO_0P960;

+        lv_ldo_ao_boost = (uint32_t)V_AO_1P010;

+    }

+    else if (system_voltage_mv <= 975UL)

+    {

+        lv_dcdc         = (uint32_t)V_DCDC_0P975;

+        lv_ldo_ao       = (uint32_t)V_AO_0P980;

+        lv_ldo_ao_boost = (uint32_t)V_AO_1P030;

+    }

+    else if (system_voltage_mv <= 1000UL)

+    {

+        lv_dcdc         = (uint32_t)V_DCDC_1P000;

+        lv_ldo_ao       = (uint32_t)V_AO_1P000;

+        lv_ldo_ao_boost = (uint32_t)V_AO_1P050;

+    }

+    else if (system_voltage_mv <= 1025UL)

+    {

+        lv_dcdc         = (uint32_t)V_DCDC_1P025;

+        lv_ldo_ao       = (uint32_t)V_AO_1P030;

+        lv_ldo_ao_boost = (uint32_t)V_AO_1P080;

+    }

+    else if (system_voltage_mv <= 1050UL)

+    {

+        lv_dcdc         = (uint32_t)V_DCDC_1P050;

+        lv_ldo_ao       = (uint32_t)V_AO_1P060;

+        lv_ldo_ao_boost = (uint32_t)V_AO_1P110;

+    }

+    else if (system_voltage_mv <= 1075UL)

+    {

+        lv_dcdc         = (uint32_t)V_DCDC_1P075;

+        lv_ldo_ao       = (uint32_t)V_AO_1P080;

+        lv_ldo_ao_boost = (uint32_t)V_AO_1P130;

+    }

+    else if (system_voltage_mv <= 1100UL)

+    {

+        lv_dcdc         = (uint32_t)V_DCDC_1P100;

+        lv_ldo_ao       = (uint32_t)V_AO_1P100;

+        lv_ldo_ao_boost = (uint32_t)V_AO_1P150;

+    }

+    else if (system_voltage_mv <= 1125UL)

+    {

+        lv_dcdc         = (uint32_t)V_DCDC_1P125;

+        lv_ldo_ao       = (uint32_t)V_AO_1P130;

+        lv_ldo_ao_boost = (uint32_t)V_AO_1P160;

+    }

+    else if (system_voltage_mv <= 1150UL)

+    {

+        lv_dcdc         = (uint32_t)V_DCDC_1P150;

+        lv_ldo_ao       = (uint32_t)V_AO_1P160;

+        lv_ldo_ao_boost = (uint32_t)V_AO_1P220;

+    }

+    else if (system_voltage_mv <= 1175UL)

+    {

+        lv_dcdc         = (uint32_t)V_DCDC_1P175;

+        lv_ldo_ao       = (uint32_t)V_AO_1P160;

+        lv_ldo_ao_boost = (uint32_t)V_AO_1P220;

+    }

+    else

+    {

+        lv_dcdc         = (uint32_t)V_DCDC_1P200;

+        lv_ldo_ao       = (uint32_t)V_AO_1P160;

+        lv_ldo_ao_boost = (uint32_t)V_AO_1P220;

+    }

+

+    /* Set up LDO Always-On voltages */

+    PMC->LDOPMU = (PMC->LDOPMU & (~PMC_LDOPMU_VADJ_MASK) & (~PMC_LDOPMU_VADJ_BOOST_MASK)) | PMC_LDOPMU_VADJ(lv_ldo_ao) |

+                  PMC_LDOPMU_VADJ_BOOST(lv_ldo_ao_boost);

+

+    /* Set up DCDC voltage */

+    PMC->DCDC0 = (PMC->DCDC0 & (~PMC_DCDC0_VOUT_MASK)) | PMC_DCDC0_VOUT(lv_dcdc);

+}

+

+/**

+ * @brief   Described in fsl_common.h

+ * @param

+ * @return

+ */

+static void lowpower_set_dcdc_power_profile(lowpower_dcdc_power_profile_enum dcdc_power_profile)

+{

+#define FLASH_NMPA_BASE                              (0x9FC00u)

+#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ADDRS    (FLASH_NMPA_BASE + 0xE0U) // (0x9FCE0U)

+#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_ADDRS    (FLASH_NMPA_BASE + 0xE4U) // (0x9FCE4U)

+#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ADDRS (FLASH_NMPA_BASE + 0xE8U) // (0x9FCE8U)

+#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_ADDRS (FLASH_NMPA_BASE + 0xECU) // (0x9FCECU)

+#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ADDRS   (FLASH_NMPA_BASE + 0xD8U) // (0x9FCD8U)

+#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_ADDRS   (FLASH_NMPA_BASE + 0xDCU) // (0x9FCDCU)

+

+    const uint32_t PMC_DCDC0_DEFAULT = 0x010C4E68;

+    const uint32_t PMC_DCDC1_DEFAULT = 0x01803A98;

+

+    uint32_t dcdcTrimValue0;

+    uint32_t dcdcTrimValue1;

+

+    switch (dcdc_power_profile)

+    {

+        case DCDC_POWER_PROFILE_LOW:

+            /* Low */

+            dcdcTrimValue0 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ADDRS)));

+            dcdcTrimValue1 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_ADDRS)));

+

+            if (0UL != (dcdcTrimValue0 & 0x1UL))

+            {

+                dcdcTrimValue0 = dcdcTrimValue0 >> 1;

+

+                PMC->DCDC0 = dcdcTrimValue0;

+                PMC->DCDC1 = dcdcTrimValue1;

+#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1))

+                PRINTF(

+                    "\nINFO : DCDC Power Profile set to "

+                    "LOW"

+                    "\n");

+#endif

+            }

+            break;

+

+        case DCDC_POWER_PROFILE_MEDIUM:

+            /* Medium */

+            dcdcTrimValue0 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ADDRS)));

+            dcdcTrimValue1 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_ADDRS)));

+

+            if (0UL != (dcdcTrimValue0 & 0x1UL))

+            {

+                dcdcTrimValue0 = dcdcTrimValue0 >> 1;

+

+                PMC->DCDC0 = dcdcTrimValue0;

+                PMC->DCDC1 = dcdcTrimValue1;

+#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1))

+                PRINTF(

+                    "\nINFO : DCDC Power Profile set to "

+                    "MEDIUM"

+                    "\n");

+#endif

+            }

+            break;

+

+        case DCDC_POWER_PROFILE_HIGH:

+            /* High */

+            dcdcTrimValue0 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ADDRS)));

+            dcdcTrimValue1 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_ADDRS)));

+

+            if (0UL != (dcdcTrimValue0 & 0x1UL))

+            {

+                dcdcTrimValue0 = dcdcTrimValue0 >> 1;

+

+                PMC->DCDC0 = dcdcTrimValue0;

+                PMC->DCDC1 = dcdcTrimValue1;

+#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1))

+                PRINTF(

+                    "\nINFO : DCDC Power Profile set to "

+                    "HIGH"

+                    "\n");

+#endif

+            }

+            break;

+

+        default:

+            /* Low */

+            PMC->DCDC0 = PMC_DCDC0_DEFAULT;

+            PMC->DCDC1 = PMC_DCDC1_DEFAULT;

+#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1))

+            PRINTF(

+                "\nINFO : DCDC Power Profile set to "

+                "LOW"

+                "\n");

+#endif

+            break;

+    }

+}

+

+/**

+ * @brief

+ * @param

+ * @return

+ */

+static lowpower_process_corner_enum lowpower_get_part_process_corner(void)

+{

+#define FLASH_NMPA_PVT_MONITOR_0_RINGO_ADDRS (FLASH_NMPA_BASE + 0x130U)

+#define FLASH_NMPA_PVT_MONITOR_1_RINGO_ADDRS (FLASH_NMPA_BASE + 0x140U)

+

+    lowpower_process_corner_enum part_process_corner;

+    uint32_t pvt_ringo_hz;

+    uint32_t pvt_ringo_0 = (*((volatile unsigned int *)(FLASH_NMPA_PVT_MONITOR_0_RINGO_ADDRS)));

+    uint32_t pvt_ringo_1 = (*((volatile unsigned int *)(FLASH_NMPA_PVT_MONITOR_1_RINGO_ADDRS)));

+

+    /*

+     * Check that the PVT Monitors Trimmings in flash are valid.

+     */

+    if (0UL != (pvt_ringo_0 & 0x1UL))

+    {

+        /* PVT Trimmings in Flash are valid */

+        pvt_ringo_0 = pvt_ringo_0 >> 1;

+    }

+    else

+    {

+        /* PVT Trimmings in Flash are NOT valid (average value assumed) */

+        pvt_ringo_0 = PROCESS_NNN_AVG_HZ;

+    }

+

+    if (0UL != (pvt_ringo_1 & 0x1UL))

+    {

+        /* PVT Trimmings in Flash are valid */

+        pvt_ringo_1 = pvt_ringo_1 >> 1;

+    }

+    else

+    {

+        /* PVT Trimmings in Flash are NOT valid (average value assumed) */

+        pvt_ringo_1 = PROCESS_NNN_AVG_HZ;

+    }

+

+    if (pvt_ringo_1 <= pvt_ringo_0)

+    {

+        pvt_ringo_hz = pvt_ringo_1;

+    }

+    else

+    {

+        pvt_ringo_hz = pvt_ringo_0;

+    }

+

+    /*

+     * Determine the process corner based on the value of the Ring Oscillator frequency

+     */

+    if (pvt_ringo_hz <= PROCESS_NNN_MIN_HZ)

+    {

+        /* SSS Process Corner */

+        part_process_corner = PROCESS_CORNER_SSS;

+#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1))

+        PRINTF(

+            "\nINFO : Process Corner : "

+            "SSS"

+            "\n");

+#endif

+    }

+    else

+    {

+        if (pvt_ringo_hz <= PROCESS_NNN_MAX_HZ)

+        {

+            /* NNN Process Corner */

+            part_process_corner = PROCESS_CORNER_NNN;

+#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1))

+            PRINTF(

+                "\nINFO : Process Corner : "

+                "NNN"

+                "\n");

+#endif

+        }

+        else

+        {

+            /* FFF Process Corner */

+            part_process_corner = PROCESS_CORNER_FFF;

+#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1))

+            PRINTF(

+                "\nINFO : Process Corner : "

+                "FFF"

+                "\n");

+#endif

+        }

+    }

+

+    return (part_process_corner);

+}

+

+/**

+ * @brief   Described in fsl_common.h

+ * @param

+ * @return

+ */

+static void lowpower_set_voltage_for_process(lowpower_dcdc_power_profile_enum dcdc_power_profile)

+{

+    /* Get Sample Process Corner */

+    lowpower_process_corner_enum part_process_corner = lowpower_get_part_process_corner();

+

+    switch (part_process_corner)

+    {

+        case PROCESS_CORNER_SSS:

+            /* Slow Corner */

+            {

+                switch (dcdc_power_profile)

+                {

+                    case DCDC_POWER_PROFILE_MEDIUM:

+                        /* Medium */

+                        lowpower_set_system_voltage(VOLTAGE_SSS_MED_MV);

+                        break;

+

+                    case DCDC_POWER_PROFILE_HIGH:

+                        /* High */

+                        lowpower_set_system_voltage(VOLTAGE_SSS_HIG_MV);

+                        break;

+

+                    default:

+                        /* DCDC_POWER_PROFILE_LOW */

+                        lowpower_set_system_voltage(VOLTAGE_SSS_LOW_MV);

+                        break;

+                } // switch(dcdc_power_profile)

+            }

+            break;

+

+        case PROCESS_CORNER_FFF:

+            /* Fast Corner */

+            {

+                switch (dcdc_power_profile)

+                {

+                    case DCDC_POWER_PROFILE_MEDIUM:

+                        /* Medium */

+                        lowpower_set_system_voltage(VOLTAGE_FFF_MED_MV);

+                        break;

+

+                    case DCDC_POWER_PROFILE_HIGH:

+                        /* High */

+                        lowpower_set_system_voltage(VOLTAGE_FFF_HIG_MV);

+                        break;

+

+                    default:

+                        /* DCDC_POWER_PROFILE_LOW */

+                        lowpower_set_system_voltage(VOLTAGE_FFF_LOW_MV);

+                        break;

+                } // switch(dcdc_power_profile)

+            }

+            break;

+

+        default:

+            /* Nominal (NNN) and all others Process Corners : assume Nominal Corner */

+            {

+                switch (dcdc_power_profile)

+                {

+                    case DCDC_POWER_PROFILE_MEDIUM:

+                        /* Medium */

+                        lowpower_set_system_voltage(VOLTAGE_NNN_MED_MV);

+                        break;

+

+                    case DCDC_POWER_PROFILE_HIGH:

+                        /* High */

+                        lowpower_set_system_voltage(VOLTAGE_NNN_HIG_MV);

+                        break;

+

+                    default:

+                        /* DCDC_POWER_PROFILE_LOW */

+                        lowpower_set_system_voltage(VOLTAGE_NNN_LOW_MV);

+                        break;

+                } // switch(dcdc_power_profile)

+                break;

+            }

+    } // switch(part_process_corner)

+}

+

+/**

+ * @brief             Described in fsl_common.h

+ * @param

+ * @return

+ */

+void POWER_SetVoltageForFreq(uint32_t system_freq_hz)

+{

+    if (system_freq_hz <= DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ)

+    {

+        /* [0 Hz - DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ Hz] */

+        lowpower_set_dcdc_power_profile(DCDC_POWER_PROFILE_LOW); /* DCDC VOUT = 1.05 V by default */

+        lowpower_set_voltage_for_process(DCDC_POWER_PROFILE_LOW);

+    }

+    else

+    {

+        if (system_freq_hz <= DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ)

+        {

+            /* ]DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ Hz - DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ Hz] */

+            lowpower_set_dcdc_power_profile(DCDC_POWER_PROFILE_MEDIUM); /* DCDC VOUT = 1.15 V by default */

+            lowpower_set_voltage_for_process(DCDC_POWER_PROFILE_MEDIUM);

+        }

+        else

+        {

+            /* > DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ Hz */

+            lowpower_set_dcdc_power_profile(DCDC_POWER_PROFILE_HIGH); /* DCDC VOUT = 1.2 V by default */

+            lowpower_set_voltage_for_process(DCDC_POWER_PROFILE_HIGH);

+        }

+    }

+}

+

+void POWER_Xtal16mhzCapabankTrim(int32_t pi32_16MfXtalIecLoadpF_x100,

+                                 int32_t pi32_16MfXtalPPcbParCappF_x100,

+                                 int32_t pi32_16MfXtalNPcbParCappF_x100)

+{

+    uint32_t u32XOTrimValue;

+    uint8_t u8IECXinCapCal6pF, u8IECXinCapCal8pF, u8IECXoutCapCal6pF, u8IECXoutCapCal8pF, u8XOSlave;

+    int32_t iaXin_x4, ibXin, iaXout_x4, ibXout;

+    int32_t iXOCapInpF_x100, iXOCapOutpF_x100;

+    uint8_t u8XOCapInCtrl, u8XOCapOutCtrl;

+    uint32_t u32RegVal;

+    int32_t i32Tmp;

+

+    /* Enable and set LDO, if not already done */

+    POWER_SetXtal16mhzLdo();

+    /* Get Cal values from Flash */

+    u32XOTrimValue = GET_16MXO_TRIM();

+    /* Check validity and apply */

+    if ((0UL != (u32XOTrimValue & 1UL)) && (0UL != ((u32XOTrimValue >> 15UL) & 1UL)))

+    {

+        /* These fields are 7 bits, unsigned */

+        u8IECXinCapCal6pF  = (uint8_t)((u32XOTrimValue >> 1UL) & 0x7fUL);

+        u8IECXinCapCal8pF  = (uint8_t)((u32XOTrimValue >> 8UL) & 0x7fUL);

+        u8IECXoutCapCal6pF = (uint8_t)((u32XOTrimValue >> 16UL) & 0x7fUL);

+        u8IECXoutCapCal8pF = (uint8_t)((u32XOTrimValue >> 23UL) & 0x7fUL);

+        /* This field is 1 bit */

+        u8XOSlave = (uint8_t)((u32XOTrimValue >> 30UL) & 0x1UL);

+        /* Linear fit coefficients calculation */

+        iaXin_x4  = (int)u8IECXinCapCal8pF - (int)u8IECXinCapCal6pF;

+        ibXin     = (int)u8IECXinCapCal6pF - iaXin_x4 * 3;

+        iaXout_x4 = (int)u8IECXoutCapCal8pF - (int)u8IECXoutCapCal6pF;

+        ibXout    = (int)u8IECXoutCapCal6pF - iaXout_x4 * 3;

+    }

+    else

+    {

+        iaXin_x4  = 20;  // gain in LSB/pF

+        ibXin     = -9;  // offset in LSB

+        iaXout_x4 = 20;  // gain in LSB/pF

+        ibXout    = -13; // offset in LSB

+        u8XOSlave = 0;

+    }

+    /* In & out load cap calculation with derating */

+    iXOCapInpF_x100 = 2 * pi32_16MfXtalIecLoadpF_x100 - pi32_16MfXtalNPcbParCappF_x100 +

+                      39 * ((int32_t)XO_SLAVE_EN - (int32_t)u8XOSlave) - 15;

+    iXOCapOutpF_x100 = 2 * pi32_16MfXtalIecLoadpF_x100 - pi32_16MfXtalPPcbParCappF_x100 - 21;

+    /* In & out XO_OSC_CAP_Code_CTRL calculation, with rounding */

+    i32Tmp         = ((iXOCapInpF_x100 * iaXin_x4 + ibXin * 400) + 200) / 400;

+    u8XOCapInCtrl  = (uint8_t)i32Tmp;

+    i32Tmp         = ((iXOCapOutpF_x100 * iaXout_x4 + ibXout * 400) + 200) / 400;

+    u8XOCapOutCtrl = (uint8_t)i32Tmp;

+    /* Read register and clear fields to be written */

+    u32RegVal = ANACTRL->XO32M_CTRL;

+    u32RegVal &= ~(ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK | ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK);

+    /* Configuration of 32 MHz XO output buffers */

+#if (XO_SLAVE_EN == 0)

+    u32RegVal &= ~(ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK);

+#else

+    u32RegVal |= ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK;

+#endif

+    /* XO_OSC_CAP_Code_CTRL to XO_OSC_CAP_Code conversion */

+    u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT;

+    u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT;

+    /* Write back to register */

+    ANACTRL->XO32M_CTRL = u32RegVal;

+}

+

+void POWER_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100,

+                                 int32_t pi32_32kfXtalPPcbParCappF_x100,

+                                 int32_t pi32_32kfXtalNPcbParCappF_x100)

+{

+    uint32_t u32XOTrimValue;

+    uint8_t u8IECXinCapCal6pF, u8IECXinCapCal8pF, u8IECXoutCapCal6pF, u8IECXoutCapCal8pF;

+    int32_t iaXin_x4, ibXin, iaXout_x4, ibXout;

+    int32_t iXOCapInpF_x100, iXOCapOutpF_x100;

+    uint8_t u8XOCapInCtrl, u8XOCapOutCtrl;

+    uint32_t u32RegVal;

+    int32_t i32Tmp;

+    /* Get Cal values from Flash */

+    u32XOTrimValue = GET_32KXO_TRIM();

+    /* check validity and apply */

+    if ((0UL != (u32XOTrimValue & 1UL)) && (0UL != ((u32XOTrimValue >> 15UL) & 1UL)))

+    {

+        /* These fields are 7 bits, unsigned */

+        u8IECXinCapCal6pF  = (uint8_t)((u32XOTrimValue >> 1UL) & 0x7fUL);

+        u8IECXinCapCal8pF  = (uint8_t)((u32XOTrimValue >> 8UL) & 0x7fUL);

+        u8IECXoutCapCal6pF = (uint8_t)((u32XOTrimValue >> 16UL) & 0x7fUL);

+        u8IECXoutCapCal8pF = (uint8_t)((u32XOTrimValue >> 23UL) & 0x7fUL);

+        /* Linear fit coefficients calculation */

+        iaXin_x4  = (int)u8IECXinCapCal8pF - (int)u8IECXinCapCal6pF;

+        ibXin     = (int)u8IECXinCapCal6pF - iaXin_x4 * 3;

+        iaXout_x4 = (int)u8IECXoutCapCal8pF - (int)u8IECXoutCapCal6pF;

+        ibXout    = (int)u8IECXoutCapCal6pF - iaXout_x4 * 3;

+    }

+    else

+    {

+        iaXin_x4  = 16; // gain in LSB/pF

+        ibXin     = 12; // offset in LSB

+        iaXout_x4 = 16; // gain in LSB/pF

+        ibXout    = 11; // offset in LSB

+    }

+

+    /* In & out load cap calculation with derating */

+    iXOCapInpF_x100  = 2 * pi32_32kfXtalIecLoadpF_x100 - pi32_32kfXtalNPcbParCappF_x100 - 130;

+    iXOCapOutpF_x100 = 2 * pi32_32kfXtalIecLoadpF_x100 - pi32_32kfXtalPPcbParCappF_x100 - 41;

+

+    /* In & out XO_OSC_CAP_Code_CTRL calculation, with rounding */

+    i32Tmp         = ((iXOCapInpF_x100 * iaXin_x4 + ibXin * 400) + 200) / 400;

+    u8XOCapInCtrl  = (uint8_t)i32Tmp;

+    i32Tmp         = ((iXOCapOutpF_x100 * iaXout_x4 + ibXout * 400) + 200) / 400;

+    u8XOCapOutCtrl = (uint8_t)i32Tmp;

+

+    /* Read register and clear fields to be written */

+    u32RegVal = PMC->XTAL32K;

+    u32RegVal &= ~(PMC_XTAL32K_CAPBANKIN_MASK | PMC_XTAL32K_CAPBANKOUT_MASK);

+

+    /* XO_OSC_CAP_Code_CTRL to XO_OSC_CAP_Code conversion */

+    u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 23) << PMC_XTAL32K_CAPBANKIN_SHIFT;

+    u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 23) << PMC_XTAL32K_CAPBANKOUT_SHIFT;

+

+    /* Write back to register */

+    PMC->XTAL32K = u32RegVal;

+}

+

+void POWER_SetXtal16mhzLdo(void)

+{

+    uint32_t temp;

+    const uint32_t u32Mask =

+        (ANACTRL_LDO_XO32M_VOUT_MASK | ANACTRL_LDO_XO32M_IBIAS_MASK | ANACTRL_LDO_XO32M_STABMODE_MASK);

+

+    const uint32_t u32Value =

+        (ANACTRL_LDO_XO32M_VOUT(0x5) | ANACTRL_LDO_XO32M_IBIAS(0x2) | ANACTRL_LDO_XO32M_STABMODE(0x1));

+

+    /* Enable & set-up XTAL 32 MHz clock LDO */

+    temp = ANACTRL->LDO_XO32M;

+

+    if ((temp & u32Mask) != u32Value)

+    {

+        temp &= ~u32Mask;

+

+        /*

+         * Enable the XTAL32M LDO

+         * Adjust the output voltage level, 0x5 for 1.1V

+         * Adjust the biasing current, 0x2 value

+         * Stability configuration, 0x1 default mode

+         */

+        temp |= u32Value;

+

+        ANACTRL->LDO_XO32M = temp;

+

+        /* Delay for LDO to be up */

+        // CLOCK_uDelay(20);

+    }

+

+    /* Enable LDO XO32M */

+    PMC->PDRUNCFGCLR0 = PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK;

+}

+

+/**

+ * @brief   Return some key information related to the device reset causes / wake-up sources, for all power modes.

+ * @param   p_reset_cause   : the device reset cause, according to the definition of power_device_reset_cause_t type.

+ * @param   p_boot_mode     : the device boot mode, according to the definition of power_device_boot_mode_t type.

+ * @param   p_wakeupio_cause: the wake-up pin sources, according to the definition of register PMC->WAKEIOCAUSE[3:0].

+

+ * @return  Nothing

+ *

+ *         !!!  IMPORTANT ERRATA - IMPORTANT ERRATA - IMPORTANT ERRATA     !!!

+ *         !!!   valid ONLY for LPC55S69 (not for LPC55S16 and LPC55S06)   !!!

+ *         !!!   when FALLING EDGE DETECTION is enabled on wake-up pins:   !!!

+ *         - 1. p_wakeupio_cause is NOT ACCURATE

+ *         - 2. Spurious kRESET_CAUSE_DPDRESET_WAKEUPIO* event is reported when

+ *              several wake-up sources are enabled during DEEP-POWER-DOWN

+ *              (like enabling wake-up on RTC and Falling edge wake-up pins)

+ *

+ */

+void POWER_GetWakeUpCause(power_device_reset_cause_t *p_reset_cause,

+                          power_device_boot_mode_t *p_boot_mode,

+                          uint32_t *p_wakeupio_cause)

+{

+    uint32_t reset_cause_reg;

+    uint32_t boot_mode_reg;

+

+#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \

+     defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \

+     defined(LPC5514_SERIES) || defined(LPC5512_SERIES))

+    reset_cause_reg = (PMC->AOREG1) & 0x3FF0UL;

+#else /* LPC55S69/28 */

+    reset_cause_reg = (PMC->AOREG1) & 0x1FF0UL;

+#endif

+

+    /*

+     * Prioritize interrupts source with respect to their critical level

+     */

+#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \

+     defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \

+     defined(LPC5514_SERIES) || defined(LPC5512_SERIES))

+    if (0UL != (reset_cause_reg & PMC_AOREG1_CDOGRESET_MASK))

+    { /* Code Watchdog Reset */

+        *p_reset_cause    = kRESET_CAUSE_CDOGRESET;

+        *p_boot_mode      = kBOOT_MODE_POWER_UP;

+        *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */

+    }

+    else

+#endif

+    {

+        if (0UL != (reset_cause_reg & PMC_AOREG1_WDTRESET_MASK))

+        { /* Watchdog Timer Reset */

+            *p_reset_cause    = kRESET_CAUSE_WDTRESET;

+            *p_boot_mode      = kBOOT_MODE_POWER_UP;

+            *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */

+        }

+        else

+        {

+            if (0UL != (reset_cause_reg & PMC_AOREG1_SYSTEMRESET_MASK))

+            { /* ARM System Reset */

+                *p_reset_cause    = kRESET_CAUSE_ARMSYSTEMRESET;

+                *p_boot_mode      = kBOOT_MODE_POWER_UP;

+                *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */

+            }

+            else

+            {

+                boot_mode_reg = (PMC->STATUS & PMC_STATUS_BOOTMODE_MASK) >> PMC_STATUS_BOOTMODE_SHIFT;

+

+                if (boot_mode_reg == 0UL) /* POWER-UP: Power On Reset, Pin reset, Brown Out Detectors, Software Reset */

+                {

+                    *p_boot_mode      = kBOOT_MODE_POWER_UP; /* All non wake-up from a Low Power mode */

+                    *p_wakeupio_cause = 0;                   /* Device has not been waked-up by any wake-up pins */

+

+                    /*

+                     * Prioritise Reset causes, starting from the strongest (Power On Reset)

+                     */

+                    if (0UL != (reset_cause_reg & PMC_AOREG1_POR_MASK))

+                    { /* Power On Reset */

+                        *p_reset_cause = kRESET_CAUSE_POR;

+                    }

+                    else

+                    {

+                        if (0UL != (reset_cause_reg & PMC_AOREG1_BODRESET_MASK))

+                        { /* Brown-out Detector reset (either BODVBAT or BODCORE) */

+                            *p_reset_cause = kRESET_CAUSE_BODRESET;

+                        }

+                        else

+                        {

+                            if (0UL != (reset_cause_reg & PMC_AOREG1_PADRESET_MASK))

+                            { /* Hardware Pin Reset */

+                                *p_reset_cause = kRESET_CAUSE_PADRESET;

+                            }

+                            else

+                            {

+                                if (0UL != (reset_cause_reg & PMC_AOREG1_SWRRESET_MASK))

+                                { /* Software triggered Reset */

+                                    *p_reset_cause = kRESET_CAUSE_SWRRESET;

+                                }

+                                else

+                                { /* Unknown Reset Cause */

+                                    *p_reset_cause = kRESET_CAUSE_NOT_DETERMINISTIC;

+                                }

+                            }

+                        }

+                    }

+

+#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \

+     defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \

+     defined(LPC5514_SERIES) || defined(LPC5512_SERIES))

+                    /* Transfer the control of the 4 wake-up pins to IOCON (instead of the Power Management Controller

+                     */

+                    PMC->WAKEUPIOCTRL = PMC->WAKEUPIOCTRL & (~PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK);

+#endif

+                }

+                else /* DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN */

+                {

+                    /*

+                     * 1- First, save wakeup_io_cause register ...

+                     */

+                    *p_wakeupio_cause = PMC->WAKEIOCAUSE;

+

+                    if (boot_mode_reg == 3UL) /* DEEP-POWER-DOWN */

+                    {

+                        *p_boot_mode = kBOOT_MODE_LP_DEEP_POWER_DOWN;

+

+                        switch (((reset_cause_reg >> PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT) & 0x7UL))

+                        {

+                            case 1:

+                                *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO;

+                                break;

+                            case 2:

+                                *p_reset_cause = kRESET_CAUSE_DPDRESET_RTC;

+                                break;

+                            case 3:

+                                *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC;

+                                break;

+                            case 4:

+                                *p_reset_cause = kRESET_CAUSE_DPDRESET_OSTIMER;

+                                break;

+                            case 5:

+                                *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO_OSTIMER;

+                                break;

+                            case 6:

+                                *p_reset_cause = kRESET_CAUSE_DPDRESET_RTC_OSTIMER;

+                                break;

+                            case 7:

+                                *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC_OSTIMER;

+                                break;

+                            default:

+                                /* Unknown Reset Cause */

+                                *p_reset_cause = kRESET_CAUSE_NOT_DETERMINISTIC;

+                                break;

+                        }

+

+#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \

+     defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \

+     defined(LPC5514_SERIES) || defined(LPC5512_SERIES))

+                        /*

+                         * 2- Next, transfer the control of the 4 wake-up pins

+                         * to IOCON (instead of the Power Management Controller)

+                         */

+                        PMC->WAKEUPIOCTRL = PMC->WAKEUPIOCTRL & (~PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK);

+#endif

+                    }

+                    else /* DEEP-SLEEP and POWER-DOWN */

+                    {

+                        *p_reset_cause = kRESET_CAUSE_NOT_RELEVANT;

+

+                        /*

+                         * The control of the 4 wake-up pins is already in IOCON,

+                         * so there is nothing special to do.

+                         */

+

+                        if (boot_mode_reg == 1UL) /* DEEP-SLEEP */

+                        {

+                            *p_boot_mode = kBOOT_MODE_LP_DEEP_SLEEP;

+                        }

+                        else /* POWER-DOWN */

+                        {

+                            *p_boot_mode = kBOOT_MODE_LP_POWER_DOWN;

+

+                        } /* if ( boot_mode_reg == 1 ) DEEP-SLEEP */

+

+                    } /* if ( boot_mode == 3 )  DEEP-POWER-DOWN */

+

+                } /* if ( boot_mode == 0 )  POWER-UP */

+

+            } /* if ( reset_cause_reg & PMC_AOREG1_CDOGRESET_MASK ) */

+

+        } /* if ( reset_cause_reg & PMC_AOREG1_WDTRESET_MASK ) */

+

+    } /* if ( reset_cause_reg & PMC_AOREG1_SYSTEMRESET_MASK ) */

+}

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_power.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_power.h
index f972918b9..c37cbcf49 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_power.h
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_power.h
@@ -540,13 +540,6 @@ void POWER_EnterSleep(void);
  */

 void POWER_SetVoltageForFreq(uint32_t system_freq_hz);

 

-/*!

- * @brief Power Library API to return the library version.

- *

- * @return version number of the power library

- */

-uint32_t POWER_GetLibVersion(void);

-

 /**

  * @brief   Sets board-specific trim values for 16MHz XTAL

  * @param   pi32_16MfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120

@@ -588,14 +581,6 @@ extern void POWER_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100,
 extern void POWER_SetXtal16mhzLdo(void);

 

 /**

- * @brief   Set up 16-MHz XTAL Trimmings

- * @param       amp Amplitude

- * @param       gm  Transconductance

- * @return  none

- */

-extern void POWER_SetXtal16mhzTrim(uint32_t amp, uint32_t gm);

-

-/**

  * @brief   Return some key information related to the device reset causes / wake-up sources, for all power modes.

  * @param   p_reset_cause   : the device reset cause, according to the definition of power_device_reset_cause_t type.

  * @param   p_boot_mode     : the device boot mode, according to the definition of power_device_boot_mode_t type.

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_reset.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_reset.h
index bd6b2da56..9bde6707f 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_reset.h
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_reset.h
@@ -26,8 +26,8 @@
 

 /*! @name Driver version */

 /*@{*/

-/*! @brief reset driver version 2.0.2. */

-#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))

+/*! @brief reset driver version 2.0.3. */

+#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))

 /*@}*/

 

 /*!

@@ -233,6 +233,22 @@ typedef enum _SYSCON_RSTn
     {                            \

         kOSTIMER0_RST_SHIFT_RSTn \

     } /* Reset bits for OSTIMER peripheral */

+#define POWERQUAD_RSTS            \

+    {                             \

+        kPOWERQUAD_RST_SHIFT_RSTn \

+    } /* Reset bits for Powerquad peripheral */

+#define CASPER_RSTS            \

+    {                          \

+        kCASPER_RST_SHIFT_RSTn \

+    } /* Reset bits for Casper peripheral */

+#define HASHCRYPT_RSTS            \

+    {                             \

+        kHASHCRYPT_RST_SHIFT_RSTn \

+    } /* Reset bits for Hashcrypt peripheral */

+#define PUF_RSTS            \

+    {                       \

+        kPUF_RST_SHIFT_RSTn \

+    } /* Reset bits for PUF peripheral */

 typedef SYSCON_RSTn_t reset_ip_name_t;

 

 /*******************************************************************************

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_usart.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_usart.c
index e1b2fd2c4..7e84d0cb4 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_usart.c
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_usart.c
@@ -1,6 +1,6 @@
 /*

  * Copyright (c) 2016, Freescale Semiconductor, Inc.

- * Copyright 2016-2021 NXP

+ * Copyright 2016-2022 NXP

  * All rights reserved.

  *

  * SPDX-License-Identifier: BSD-3-Clause

@@ -229,6 +229,9 @@ status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t src
         /* enable trigger interrupt */

         base->FIFOTRIG |= USART_FIFOTRIG_RXLVLENA_MASK;

     }

+#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG

+    USART_SetRxTimeoutConfig(base, (usart_rx_timeout_config *)&(config->rxTimeout));

+#endif

     /* setup configuration and enable USART */

     base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) |

                 USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) |

@@ -281,6 +284,9 @@ void USART_Deinit(USART_Type *base)
                          USART_FIFOINTENCLR_RXLVL_MASK;

     base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK | USART_FIFOCFG_DMARX_MASK);

     base->CFG &= ~(USART_CFG_ENABLE_MASK);

+#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG

+    base->FIFORXTIMEOUTCFG = 0U;

+#endif

 }

 

 /*!

@@ -321,7 +327,84 @@ void USART_GetDefaultConfig(usart_config_t *config)
     config->enableContinuousSCLK      = false;

     config->clockPolarity             = kUSART_RxSampleOnFallingEdge;

     config->enableHardwareFlowControl = false;

+#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG

+    config->rxTimeout.enable                = false;

+    config->rxTimeout.resetCounterOnEmpty   = true;

+    config->rxTimeout.resetCounterOnReceive = true;

+    config->rxTimeout.counter               = 0U;

+    config->rxTimeout.prescaler             = 0U;

+#endif

 }

+#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG

+/*!

+ * brief Calculate the USART instance RX timeout prescaler and counter.

+ *

+ * This function for calculate the USART RXFIFO timeout config. This function is used to calculate

+ * suitable prescaler and counter for target_us.

+ * Example below shows how to use this API to configure USART.

+ * code

+ *   usart_config_t config;

+ *   config.rxWatermark                     = kUSART_RxFifo2;

+ *   config.rxTimeout.enable                = true;

+ *   config.rxTimeout.resetCounterOnEmpty   = true;

+ *   config.rxTimeout.resetCounterOnReceive = true;

+ *   USART_CalcTimeoutConfig(200, &config.rxTimeout.prescaler, &config.rxTimeout.counter,

+ *                                    CLOCK_GetFreq(kCLOCK_BusClk));

+ * endcode

+ * param target_us  Time for rx timeout unit us.

+ * param rxTimeoutPrescaler The prescaler to be setted after function.

+ * param rxTimeoutcounter The counter to be setted after function.

+ * param srcClock_Hz The clockSrc for rx timeout.

+ */

+void USART_CalcTimeoutConfig(uint32_t target_us,

+                             uint8_t *rxTimeoutPrescaler,

+                             uint32_t *rxTimeoutcounter,

+                             uint32_t srcClock_Hz)

+{

+    uint16_t counter   = 0U;

+    uint32_t perscalar = 0U, calculate_us = 0U, us_diff = 0U, min_diff = 0xffffffffUL;

+    /* find the suitable value */

+    for (perscalar = 0U; perscalar < 256U; perscalar++)

+    {

+        counter      = target_us * (srcClock_Hz / 1000000UL) / (16U * (perscalar + 1U));

+        calculate_us = 16U * (perscalar + 1U) * counter / (srcClock_Hz / 1000000UL);

+        us_diff      = (calculate_us > target_us) ? (calculate_us - target_us) : (target_us - calculate_us);

+        if (us_diff == 0U)

+        {

+            *rxTimeoutPrescaler = perscalar;

+            *rxTimeoutcounter   = counter;

+            break;

+        }

+        else

+        {

+            if (min_diff > us_diff)

+            {

+                min_diff            = us_diff;

+                *rxTimeoutPrescaler = perscalar;

+                *rxTimeoutcounter   = counter;

+            }

+        }

+    }

+}

+/*!

+ * brief Sets the USART instance RX timeout config.

+ *

+ * This function configures the USART RXFIFO timeout config. This function is used to config

+ * the USART RXFIFO timeout config after the USART module is initialized by the USART_Init.

+ *

+ * param base USART peripheral base address.

+ * param config pointer to receive timeout configuration structure.

+ */

+void USART_SetRxTimeoutConfig(USART_Type *base, usart_rx_timeout_config *config)

+{

+    base->FIFORXTIMEOUTCFG = 0U;

+    base->FIFORXTIMEOUTCFG = USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COW(~config->resetCounterOnReceive) |

+                             USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COE(~config->resetCounterOnEmpty) |

+                             USART_FIFORXTIMEOUTCFG_RXTIMEOUT_EN(config->enable) |

+                             USART_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE(config->counter) |

+                             USART_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER(config->prescaler);

+}

+#endif

 

 /*!

  * brief Sets the USART instance baud rate.

@@ -342,7 +425,7 @@ void USART_GetDefaultConfig(usart_config_t *config)
 status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz)

 {

     uint32_t best_diff = (uint32_t)-1, best_osrval = 0xf, best_brgval = (uint32_t)-1;

-    uint32_t osrval, brgval, diff, baudrate;

+    uint32_t osrval, brgval, diff, baudrate, allowed_error;

 

     /* check arguments */

     assert(!((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz)));

@@ -362,12 +445,21 @@ status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t src
     }

     else

     {

+        /* Actual baud rate must be within 3% of desired baud rate based on the calculated OSR and BRG value */

+        allowed_error = ((baudrate_Bps / 100U) * 3U);

         /*

          * Smaller values of OSR can make the sampling position within a data bit less accurate and may

          * potentially cause more noise errors or incorrect data.

          */

-        for (osrval = best_osrval; osrval >= 8U; osrval--)

+        for (osrval = best_osrval; (osrval >= 4U); osrval--)

         {

+            /* Break if the best baudrate's diff is in the allowed error range and the osrval is below 8,

+               only use lower osrval if the baudrate cannot be obtained with an osrval of 8 or above. */

+            if ((osrval <= 8U) && (best_diff <= allowed_error))

+            {

+                break;

+            }

+

             brgval = (((srcClock_Hz * 10U) / ((osrval + 1U) * baudrate_Bps)) - 5U) / 10U;

             if (brgval > 0xFFFFU)

             {

@@ -387,7 +479,7 @@ status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t src
          * based on the best calculated OSR and BRG value */

         baudrate = srcClock_Hz / ((best_osrval + 1U) * (best_brgval + 1U));

         diff     = (baudrate_Bps < baudrate) ? (baudrate - baudrate_Bps) : (baudrate_Bps - baudrate);

-        if (diff > ((baudrate_Bps / 100U) * 3U))

+        if (diff > allowed_error)

         {

             return kStatus_USART_BaudrateNotSupport;

         }

@@ -708,13 +800,9 @@ status_t USART_TransferCreateHandle(USART_Type *base,
  * all data is written to the TX register in the IRQ handler, the USART driver calls the callback

  * function and passes the ref kStatus_USART_TxIdle as status parameter.

  *

- * note The kStatus_USART_TxIdle is passed to the upper layer when all data is written

- * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX,

- * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished.

- *

  * param base USART peripheral base address.

  * param handle USART handle pointer.

- * param xfer USART transfer structure. See  #usart_transfer_t.

+ * param xfer USART transfer structure. See #usart_transfer_t.

  * retval kStatus_Success Successfully start the data transmission.

  * retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet.

  * retval kStatus_InvalidArgument Invalid argument.

@@ -1039,6 +1127,56 @@ void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle)
             handle->callback(base, handle, kStatus_USART_RxError, handle->userData);

         }

     }

+    /* TX under run, happens when slave is in synchronous mode and the data is not written in tx register in time. */

+    if ((base->FIFOSTAT & USART_FIFOSTAT_TXERR_MASK) != 0U)

+    {

+        /* Clear tx error state. */

+        base->FIFOSTAT |= USART_FIFOSTAT_TXERR_MASK;

+        /* Trigger callback. */

+        if (handle->callback != NULL)

+        {

+            handle->callback(base, handle, kStatus_USART_TxError, handle->userData);

+        }

+    }

+    /* If noise error. */

+    if ((base->STAT & USART_STAT_RXNOISEINT_MASK) != 0U)

+    {

+        /* Clear rx error state. */

+        base->STAT |= USART_STAT_RXNOISEINT_MASK;

+        /* clear rxFIFO */

+        base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;

+        /* Trigger callback. */

+        if (handle->callback != NULL)

+        {

+            handle->callback(base, handle, kStatus_USART_NoiseError, handle->userData);

+        }

+    }

+    /* If framing error. */

+    if ((base->STAT & USART_STAT_FRAMERRINT_MASK) != 0U)

+    {

+        /* Clear rx error state. */

+        base->STAT |= USART_STAT_FRAMERRINT_MASK;

+        /* clear rxFIFO */

+        base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;

+        /* Trigger callback. */

+        if (handle->callback != NULL)

+        {

+            handle->callback(base, handle, kStatus_USART_FramingError, handle->userData);

+        }

+    }

+    /* If parity error. */

+    if ((base->STAT & USART_STAT_PARITYERRINT_MASK) != 0U)

+    {

+        /* Clear rx error state. */

+        base->STAT |= USART_STAT_PARITYERRINT_MASK;

+        /* clear rxFIFO */

+        base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;

+        /* Trigger callback. */

+        if (handle->callback != NULL)

+        {

+            handle->callback(base, handle, kStatus_USART_ParityError, handle->userData);

+        }

+    }

     while ((receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U)) ||

            (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U)))

     {

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_usart.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_usart.h
index 726ed1c22..3aa3cae0f 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_usart.h
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_usart.h
@@ -1,6 +1,6 @@
 /*

  * Copyright (c) 2016, Freescale Semiconductor, Inc.

- * Copyright 2016-2021 NXP

+ * Copyright 2016-2022NXP

  * All rights reserved.

  *

  * SPDX-License-Identifier: BSD-3-Clause

@@ -22,15 +22,22 @@
 /*! @name Driver version */

 /*@{*/

 /*! @brief USART driver version. */

-#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 5, 1))

+#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 7, 0))

 /*@}*/

 

 #define USART_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_TXLVL_MASK) >> USART_FIFOTRIG_TXLVL_SHIFT)

 #define USART_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_RXLVL_MASK) >> USART_FIFOTRIG_RXLVL_SHIFT)

 

-/*! @brief Retry times for waiting flag. */

+/*! @brief Retry times for waiting flag.

+ *

+ * Defining to zero means to keep waiting for the flag until it is assert/deassert in blocking transfer,

+ * otherwise the program will wait until the UART_RETRY_TIMES counts down to 0,

+ * if the flag still remains unchanged then program will return kStatus_USART_Timeout.

+ * It is not advised to use this macro in formal application to prevent any hardware error

+ * because the actual wait period is affected by the compiler and optimization.

+ */

 #ifndef UART_RETRY_TIMES

-#define UART_RETRY_TIMES 0U /* Defining to zero means to keep waiting for the flag until it is assert/deassert. */

+#define UART_RETRY_TIMES 0U

 #endif

 

 /*! @brief Error codes for the USART driver. */

@@ -48,7 +55,9 @@ enum
     kStatus_USART_ParityError         = MAKE_STATUS(kStatusGroup_LPC_USART, 12), /*!< USART parity error. */

     kStatus_USART_BaudrateNotSupport =

         MAKE_STATUS(kStatusGroup_LPC_USART, 13), /*!< Baudrate is not support in current clock source */

+#if UART_RETRY_TIMES

     kStatus_USART_Timeout = MAKE_STATUS(kStatusGroup_LPC_USART, 14), /*!< USART time out. */

+#endif

 };

 

 /*! @brief USART synchronous mode. */

@@ -123,6 +132,28 @@ enum _usart_interrupt_enable
     kUSART_RxErrorInterruptEnable = (USART_FIFOINTENSET_RXERR_MASK),

     kUSART_TxLevelInterruptEnable = (USART_FIFOINTENSET_TXLVL_MASK),

     kUSART_RxLevelInterruptEnable = (USART_FIFOINTENSET_RXLVL_MASK),

+    kUSART_TxIdleInterruptEnable  = (USART_INTENSET_TXIDLEEN_MASK << 16U), /*!< Transmitter idle. */

+    kUSART_CtsChangeInterruptEnable =

+        (USART_INTENSET_DELTACTSEN_MASK << 16U), /*!< Change in the state of the CTS input. */

+    kUSART_RxBreakChangeInterruptEnable =

+        (USART_INTENSET_DELTARXBRKEN_MASK),                              /*!< Break condition asserted or deasserted. */

+    kUSART_RxStartInterruptEnable       = (USART_INTENSET_STARTEN_MASK), /*!< Rx start bit detected. */

+    kUSART_FramingErrorInterruptEnable  = (USART_INTENSET_FRAMERREN_MASK),   /*!< Framing error detected. */

+    kUSART_ParityErrorInterruptEnable   = (USART_INTENSET_PARITYERREN_MASK), /*!< Parity error detected. */

+    kUSART_NoiseErrorInterruptEnable    = (USART_INTENSET_RXNOISEEN_MASK),   /*!< Noise error detected. */

+    kUSART_AutoBaudErrorInterruptEnable = (USART_INTENSET_ABERREN_MASK),     /*!< Auto baudrate error detected. */

+#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG

+    kUSART_RxTimeoutInterruptEnable = (USART_FIFOINTENSET_RXTIMEOUT_MASK), /*!< Receive timeout detected. */

+#endif

+    kUSART_AllInterruptEnables =

+        kUSART_TxErrorInterruptEnable | kUSART_RxErrorInterruptEnable | kUSART_TxLevelInterruptEnable |

+        kUSART_RxLevelInterruptEnable | kUSART_TxIdleInterruptEnable | kUSART_CtsChangeInterruptEnable |

+        kUSART_RxBreakChangeInterruptEnable | kUSART_RxStartInterruptEnable | kUSART_FramingErrorInterruptEnable |

+        kUSART_ParityErrorInterruptEnable | kUSART_NoiseErrorInterruptEnable |

+#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG

+        kUSART_RxTimeoutInterruptEnable |

+#endif

+        kUSART_AutoBaudErrorInterruptEnable,

 };

 

 /*!

@@ -132,14 +163,49 @@ enum _usart_interrupt_enable
  */

 enum _usart_flags

 {

-    kUSART_TxError            = (USART_FIFOSTAT_TXERR_MASK),      /*!< TEERR bit, sets if TX buffer is error */

-    kUSART_RxError            = (USART_FIFOSTAT_RXERR_MASK),      /*!< RXERR bit, sets if RX buffer is error */

-    kUSART_TxFifoEmptyFlag    = (USART_FIFOSTAT_TXEMPTY_MASK),    /*!< TXEMPTY bit, sets if TX buffer is empty */

-    kUSART_TxFifoNotFullFlag  = (USART_FIFOSTAT_TXNOTFULL_MASK),  /*!< TXNOTFULL bit, sets if TX buffer is not full */

-    kUSART_RxFifoNotEmptyFlag = (USART_FIFOSTAT_RXNOTEMPTY_MASK), /*!< RXNOEMPTY bit, sets if RX buffer is not empty */

-    kUSART_RxFifoFullFlag     = (USART_FIFOSTAT_RXFULL_MASK),     /*!< RXFULL bit, sets if RX buffer is full */

+    kUSART_TxError            = (USART_FIFOSTAT_TXERR_MASK),       /*!< TEERR bit, sets if TX buffer is error */

+    kUSART_RxError            = (USART_FIFOSTAT_RXERR_MASK),       /*!< RXERR bit, sets if RX buffer is error */

+    kUSART_TxFifoEmptyFlag    = (USART_FIFOSTAT_TXEMPTY_MASK),     /*!< TXEMPTY bit, sets if TX buffer is empty */

+    kUSART_TxFifoNotFullFlag  = (USART_FIFOSTAT_TXNOTFULL_MASK),   /*!< TXNOTFULL bit, sets if TX buffer is not full */

+    kUSART_RxFifoNotEmptyFlag = (USART_FIFOSTAT_RXNOTEMPTY_MASK),  /*!< RXNOEMPTY bit, sets if RX buffer is not empty */

+    kUSART_RxFifoFullFlag     = (USART_FIFOSTAT_RXFULL_MASK),      /*!< RXFULL bit, sets if RX buffer is full */

+    kUSART_RxIdleFlag         = (USART_STAT_RXIDLE_MASK << 16U),   /*!< Receiver idle. */

+    kUSART_TxIdleFlag         = (USART_STAT_TXIDLE_MASK << 16U),   /*!< Transmitter idle. */

+    kUSART_CtsAssertFlag      = (USART_STAT_CTS_MASK << 16U),      /*!< CTS signal high. */

+    kUSART_CtsChangeFlag      = (USART_STAT_DELTACTS_MASK << 16U), /*!< CTS signal changed interrupt status. */

+    kUSART_BreakDetectFlag = (USART_STAT_RXBRK_MASK), /*!< Break detected. Self cleared when rx pin goes high again. */

+    kUSART_BreakDetectChangeFlag = (USART_STAT_DELTARXBRK_MASK), /*!< Break detect change interrupt flag. A change in

+                                                                    the state of receiver break detection. */

+    kUSART_RxStartFlag       = (USART_STAT_START_MASK),          /*!< Rx start bit detected interrupt flag. */

+    kUSART_FramingErrorFlag  = (USART_STAT_FRAMERRINT_MASK),     /*!< Framing error interrupt flag. */

+    kUSART_ParityErrorFlag   = (USART_STAT_PARITYERRINT_MASK),   /*!< parity error interrupt flag. */

+    kUSART_NoiseErrorFlag    = (USART_STAT_RXNOISEINT_MASK),     /*!< Noise error interrupt flag. */

+    kUSART_AutobaudErrorFlag = (USART_STAT_ABERR_MASK), /*!< Auto baudrate error interrupt flag, caused by the baudrate

+                                                           counter timeout before the end of start bit. */

+#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG

+    kUSART_RxTimeoutFlag = (USART_FIFOSTAT_RXTIMEOUT_MASK), /*!< RXTIMEOUT bit, sets if RX FIFO Timeout. */

+#endif

+    kUSART_AllClearFlags = kUSART_TxError | kUSART_RxError | kUSART_CtsChangeFlag | kUSART_BreakDetectChangeFlag |

+                           kUSART_RxStartFlag | kUSART_FramingErrorFlag | kUSART_ParityErrorFlag |

+#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG

+                           kUSART_RxTimeoutFlag |

+#endif

+                           kUSART_NoiseErrorFlag | kUSART_AutobaudErrorFlag,

 };

 

+#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG

+/*! @brief USART receive timeout configuration structure. */

+typedef struct _usart_rx_timeout_config

+{

+    bool enable;                /*!< Enable RX timeout */

+    bool resetCounterOnEmpty;   /*!< Enable RX timeout counter reset when RX FIFO becames empty. */

+    bool resetCounterOnReceive; /*!< Enable RX timeout counter reset when RX FIFO receives data from the transmitter

+                                   side. */

+    uint32_t counter;           /*!< RX timeout counter*/

+    uint8_t prescaler;          /*!< RX timeout prescaler*/

+} usart_rx_timeout_config;

+#endif

+

 /*! @brief USART configuration structure. */

 typedef struct _usart_config

 {

@@ -157,6 +223,9 @@ typedef struct _usart_config
     usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */

     usart_sync_mode_t syncMode; /*!< Transfer mode select - asynchronous, synchronous master, synchronous slave. */

     usart_clock_polarity_t clockPolarity; /*!< Selects the clock polarity and sampling edge in synchronous mode. */

+#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG

+    usart_rx_timeout_config rxTimeout; /*!< rx timeout configuration */

+#endif

 } usart_config_t;

 

 /*! @brief USART transfer structure. */

@@ -247,7 +316,41 @@ uint32_t USART_GetInstance(USART_Type *base);
  * @retval kStatus_Success Status USART initialize succeed

  */

 status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz);

-

+#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG

+/*!

+ * @brief Calculate the USART instance RX timeout prescaler and counter.

+ *

+ * This function for calculate the USART RXFIFO timeout config. This function is used to calculate

+ * suitable prescaler and counter for target_us.

+ * @code

+ *   usart_config_t config;

+ *   config.rxWatermark                     = kUSART_RxFifo2;

+ *   config.rxTimeout.enable                = true;

+ *   config.rxTimeout.resetCounterOnEmpty   = true;

+ *   config.rxTimeout.resetCounterOnReceive = true;

+ *   USART_CalcTimeoutConfig(200U, &config.rxTimeout.prescaler, &config.rxTimeout.counter,

+ *                                    CLOCK_GetFreq(kCLOCK_BusClk));

+ * @endcode

+ * @param target_us  Time for rx timeout unit us.

+ * @param rxTimeoutPrescaler The prescaler to be setted after function.

+ * @param rxTimeoutcounter The counter to be setted after function.

+ * @param srcClock_Hz The clockSrc for rx timeout.

+ */

+void USART_CalcTimeoutConfig(uint32_t target_us,

+                             uint8_t *rxTimeoutPrescaler,

+                             uint32_t *rxTimeoutcounter,

+                             uint32_t srcClock_Hz);

+/*!

+ * @brief Sets the USART instance RX timeout config.

+ *

+ * This function configures the USART RXFIFO timeout config. This function is used to config

+ * the USART RXFIFO timeout config after the USART module is initialized by the USART_Init.

+ *

+ * @param base USART peripheral base address.

+ * @param config pointer to receive timeout configuration structure.

+ */

+void USART_SetRxTimeoutConfig(USART_Type *base, usart_rx_timeout_config *config);

+#endif

 /*!

  * @brief Deinitializes a USART instance.

  *

@@ -389,7 +492,7 @@ static inline void USART_EnableMatchAddress(USART_Type *base, bool match)
  */

 static inline uint32_t USART_GetStatusFlags(USART_Type *base)

 {

-    return base->FIFOSTAT;

+    return (base->FIFOSTAT & 0xFF0000FFUL) | (base->STAT & 0xFFUL) << 16U | (base->STAT & 0xFFFF00UL);

 }

 

 /*!

@@ -409,6 +512,9 @@ static inline uint32_t USART_GetStatusFlags(USART_Type *base)
  */

 static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask)

 {

+    mask &= (uint32_t)kUSART_AllClearFlags;

+    /* Clear the clearable status in STAT register. */

+    base->STAT = (mask & 0xFFFF00UL) | ((mask & 0xFF0000UL) >> 16U);

     /* Only TXERR, RXERR fields support write. Remaining fields should be set to zero */

     base->FIFOSTAT = mask & (USART_FIFOSTAT_TXERR_MASK | USART_FIFOSTAT_RXERR_MASK);

 }

@@ -419,7 +525,6 @@ static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask)
  * @name Interrupts

  * @{

  */

-

 /*!

  * @brief Enables USART interrupts according to the provided mask.

  *

@@ -435,7 +540,9 @@ static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask)
  */

 static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask)

 {

-    base->FIFOINTENSET = mask & 0xFUL;

+    mask &= (uint32_t)kUSART_AllInterruptEnables;

+    base->INTENSET     = (mask & 0x1FF00UL) | ((mask & 0xFF0000UL) >> 16U);

+    base->FIFOINTENSET = mask & 0xF00000FUL;

 }

 

 /*!

@@ -453,6 +560,8 @@ static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask)
  */

 static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask)

 {

+    mask &= (uint32_t)kUSART_AllInterruptEnables;

+    base->INTENCLR     = (mask & 0x1FF00UL) | ((mask & 0xFF0000UL) >> 16U);

     base->FIFOINTENCLR = mask & 0xFUL;

 }

 

@@ -465,7 +574,7 @@ static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask)
  */

 static inline uint32_t USART_GetEnabledInterrupts(USART_Type *base)

 {

-    return base->FIFOINTENSET;

+    return (base->INTENSET & 0x1FF00UL) | ((base->INTENSET & 0xFFUL) << 16UL) | (base->FIFOINTENSET & 0xFUL);

 }

 

 /*!

@@ -711,10 +820,6 @@ status_t USART_TransferCreateHandle(USART_Type *base,
  * all data is written to the TX register in the IRQ handler, the USART driver calls the callback

  * function and passes the @ref kStatus_USART_TxIdle as status parameter.

  *

- * @note The kStatus_USART_TxIdle is passed to the upper layer when all data is written

- * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX,

- * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished.

- *

  * @param base USART peripheral base address.

  * @param handle USART handle pointer.

  * @param xfer USART transfer structure. See  #usart_transfer_t.

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/libs/libpower_hardabi.a b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/libs/libpower_hardabi.a
deleted file mode 100644
index 92d25dfc5..000000000
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/libs/libpower_hardabi.a
+++ /dev/null
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/libs/libpower_hardabi_s.a b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/libs/libpower_hardabi_s.a
deleted file mode 100644
index b0adb7d3e..000000000
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/libs/libpower_hardabi_s.a
+++ /dev/null
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/libs/libpower_softabi.a b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/libs/libpower_softabi.a
deleted file mode 100644
index 7df8627e6..000000000
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/libs/libpower_softabi.a
+++ /dev/null
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/libs/libpower_softabi_s.a b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/libs/libpower_softabi_s.a
deleted file mode 100644
index 79b7e6e61..000000000
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/libs/libpower_softabi_s.a
+++ /dev/null
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/source/semihost_hardfault.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/source/semihost_hardfault.c
index 0ac5d0cbb..9143a67d3 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/source/semihost_hardfault.c
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/source/semihost_hardfault.c
@@ -4,7 +4,7 @@
 //                  to hang application when debugger not connected.
 //
 // ****************************************************************************
-// Copyright 2017-2021 NXP
+// Copyright 2017-2023 NXP
 // All rights reserved.
 //
 // NXP Confidential. This software is owned or controlled by NXP and may only be
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/utilities/fsl_assert.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/utilities/fsl_assert.c
index 1b295c501..aaa53238c 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/utilities/fsl_assert.c
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/utilities/fsl_assert.c
@@ -46,5 +46,21 @@ void __assert_func(const char *file, int line, const char *func, const char *fai
     }

 }

 #endif /* defined(__REDLIB__) */

+#else  /* (defined(__CC_ARM) || (defined(__ICCARM__)) || (defined(__ARMCC_VERSION)) */

+

+#if (defined(__DSC__) && defined(__CW__))

+

+void __msl_assertion_failed(char const *failedExpr, char const *file, char const *func, int line)

+{

+    PRINTF("\r\nASSERT ERROR\r\n");

+    PRINTF("  File      : %s\r\n", file);

+    PRINTF("  Function  : %s\r\n", func); /*compiler not support func name yet*/

+    PRINTF("  Line      : %u\r\n", (uint32_t)line);

+    PRINTF("  failedExpr: %s\r\n", failedExpr);

+    asm(DEBUGHLT);

+}

+

+#endif /* (defined(__DSC__) && defined (__CW__)) */

+

 #endif /* (defined(__CC_ARM) || (defined(__ICCARM__)) || (defined(__ARMCC_VERSION)) */

 #endif /* NDEBUG */

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/utilities/fsl_debug_console.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/utilities/fsl_debug_console.c
index 0c4213036..86ac37b30 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/utilities/fsl_debug_console.c
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/utilities/fsl_debug_console.c
@@ -1,5 +1,5 @@
 /*

- * Copyright 2017-2018, 2020 NXP

+ * Copyright 2017-2018, 2020, 2022NXP

  * All rights reserved.

  *

  *

@@ -15,6 +15,7 @@
 #include <math.h>

 #include "fsl_debug_console.h"

 #include "fsl_adapter_uart.h"

+#include "fsl_str.h"

 

 /*! @brief Keil: suppress ellipsis warning in va_arg usage below. */

 #if defined(__CC_ARM)

@@ -43,63 +44,24 @@ typedef struct DebugConsoleState
     hal_uart_status_t (*getChar)(hal_uart_handle_t handle,

                                  uint8_t *data,

                                  size_t length); /*!< get char function pointer */

-    serial_port_type_t type;                     /*!< The initialized port of the debug console. */

+    serial_port_type_t serial_port_type;         /*!< The initialized port of the debug console. */

 } debug_console_state_t;

 

 /*! @brief Type of KSDK printf function pointer. */

 typedef int (*PUTCHAR_FUNC)(int a);

 

-#if PRINTF_ADVANCED_ENABLE

-/*! @brief Specification modifier flags for printf. */

-enum _debugconsole_printf_flag

-{

-    kPRINTF_Minus             = 0x01U,  /*!< Minus FLag. */

-    kPRINTF_Plus              = 0x02U,  /*!< Plus Flag. */

-    kPRINTF_Space             = 0x04U,  /*!< Space Flag. */

-    kPRINTF_Zero              = 0x08U,  /*!< Zero Flag. */

-    kPRINTF_Pound             = 0x10U,  /*!< Pound Flag. */

-    kPRINTF_LengthChar        = 0x20U,  /*!< Length: Char Flag. */

-    kPRINTF_LengthShortInt    = 0x40U,  /*!< Length: Short Int Flag. */

-    kPRINTF_LengthLongInt     = 0x80U,  /*!< Length: Long Int Flag. */

-    kPRINTF_LengthLongLongInt = 0x100U, /*!< Length: Long Long Int Flag. */

-};

-#endif /* PRINTF_ADVANCED_ENABLE */

-

-/*! @brief Specification modifier flags for scanf. */

-enum _debugconsole_scanf_flag

-{

-    kSCANF_Suppress   = 0x2U,    /*!< Suppress Flag. */

-    kSCANF_DestMask   = 0x7cU,   /*!< Destination Mask. */

-    kSCANF_DestChar   = 0x4U,    /*!< Destination Char Flag. */

-    kSCANF_DestString = 0x8U,    /*!< Destination String FLag. */

-    kSCANF_DestSet    = 0x10U,   /*!< Destination Set Flag. */

-    kSCANF_DestInt    = 0x20U,   /*!< Destination Int Flag. */

-    kSCANF_DestFloat  = 0x30U,   /*!< Destination Float Flag. */

-    kSCANF_LengthMask = 0x1f00U, /*!< Length Mask Flag. */

-#if SCANF_ADVANCED_ENABLE

-    kSCANF_LengthChar        = 0x100U, /*!< Length Char Flag. */

-    kSCANF_LengthShortInt    = 0x200U, /*!< Length ShortInt Flag. */

-    kSCANF_LengthLongInt     = 0x400U, /*!< Length LongInt Flag. */

-    kSCANF_LengthLongLongInt = 0x800U, /*!< Length LongLongInt Flag. */

-#endif                                 /* SCANF_ADVANCED_ENABLE */

-#if SCANF_FLOAT_ENABLE

-    kSCANF_LengthLongLongDouble = 0x1000U, /*!< Length LongLongDuoble Flag. */

-#endif                                     /*SCANF_FLOAT_ENABLE */

-    kSCANF_TypeSinged = 0x2000U,           /*!< TypeSinged Flag. */

-};

-

 /*******************************************************************************

  * Variables

  ******************************************************************************/

+#if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART))

 /*! @brief Debug UART state information. */

 static debug_console_state_t s_debugConsole;

-

+#endif

 /*******************************************************************************

  * Prototypes

  ******************************************************************************/

-#if SDK_DEBUGCONSOLE

+#if (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK))

 static int DbgConsole_PrintfFormattedData(PUTCHAR_FUNC func_ptr, const char *fmt, va_list ap);

-static int DbgConsole_ScanfFormattedData(const char *line_ptr, char *format, va_list args_ptr);

 #endif /* SDK_DEBUGCONSOLE */

 

 /*******************************************************************************

@@ -120,7 +82,7 @@ status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t
     }

 

     /* Set debug console to initialized to avoid duplicated initialized operation. */

-    s_debugConsole.type = device;

+    s_debugConsole.serial_port_type = device;

 

     usrtConfig.srcClock_Hz  = clkSrcFreq;

     usrtConfig.baudRate_Bps = baudRate;

@@ -147,34 +109,45 @@ status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t
 /* See fsl_debug_console.h for documentation of this function. */

 status_t DbgConsole_Deinit(void)

 {

-    if (kSerialPort_None == s_debugConsole.type)

+    if (kSerialPort_None == s_debugConsole.serial_port_type)

     {

         return kStatus_Success;

     }

 

     (void)HAL_UartDeinit((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0]);

 

-    s_debugConsole.type = kSerialPort_None;

+    s_debugConsole.serial_port_type = kSerialPort_None;

 

     return kStatus_Success;

 }

 #endif /* DEBUGCONSOLE_REDIRECT_TO_SDK */

 

-#if SDK_DEBUGCONSOLE

+#if (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK))

 /* See fsl_debug_console.h for documentation of this function. */

 int DbgConsole_Printf(const char *fmt_s, ...)

 {

     va_list ap;

-    int result;

+    int result = 0;

+

+    va_start(ap, fmt_s);

+    result = DbgConsole_Vprintf(fmt_s, ap);

+    va_end(ap);

+

+    return result;

+}

+

+/* See fsl_debug_console.h for documentation of this function. */

+int DbgConsole_Vprintf(const char *fmt_s, va_list formatStringArg)

+{

+    int result = 0;

 

     /* Do nothing if the debug UART is not initialized. */

-    if (kSerialPort_None == s_debugConsole.type)

+    if (kSerialPort_None == s_debugConsole.serial_port_type)

     {

         return -1;

     }

-    va_start(ap, fmt_s);

-    result = DbgConsole_PrintfFormattedData(DbgConsole_Putchar, fmt_s, ap);

-    va_end(ap);

+

+    result = DbgConsole_PrintfFormattedData(DbgConsole_Putchar, fmt_s, formatStringArg);

 

     return result;

 }

@@ -183,7 +156,7 @@ int DbgConsole_Printf(const char *fmt_s, ...)
 int DbgConsole_Putchar(int ch)

 {

     /* Do nothing if the debug UART is not initialized. */

-    if (kSerialPort_None == s_debugConsole.type)

+    if (kSerialPort_None == s_debugConsole.serial_port_type)

     {

         return -1;

     }

@@ -193,7 +166,7 @@ int DbgConsole_Putchar(int ch)
 }

 

 /* See fsl_debug_console.h for documentation of this function. */

-int DbgConsole_Scanf(char *fmt_ptr, ...)

+int DbgConsole_Scanf(char *fmt_s, ...)

 {

     /* Plus one to store end of string char */

     char temp_buf[IO_MAXLINE + 1];

@@ -202,11 +175,11 @@ int DbgConsole_Scanf(char *fmt_ptr, ...)
     char result;

 

     /* Do nothing if the debug UART is not initialized. */

-    if (kSerialPort_None == s_debugConsole.type)

+    if (kSerialPort_None == s_debugConsole.serial_port_type)

     {

         return -1;

     }

-    va_start(ap, fmt_ptr);

+    va_start(ap, fmt_s);

     temp_buf[0] = '\0';

 

     i = 0;

@@ -245,7 +218,7 @@ int DbgConsole_Scanf(char *fmt_ptr, ...)
     {

         temp_buf[i + 1] = '\0';

     }

-    result = (char)DbgConsole_ScanfFormattedData(temp_buf, fmt_ptr, ap);

+    result = (char)StrFormatScanf(temp_buf, fmt_s, ap);

     va_end(ap);

 

     return (int)result;

@@ -256,7 +229,7 @@ int DbgConsole_Getchar(void)
 {

     char ch;

     /* Do nothing if the debug UART is not initialized. */

-    if (kSerialPort_None == s_debugConsole.type)

+    if (kSerialPort_None == s_debugConsole.serial_port_type)

     {

         return -1;

     }

@@ -271,27 +244,6 @@ int DbgConsole_Getchar(void)
 

 /*************Code for process formatted data*******************************/

 /*!

- * @brief Scanline function which ignores white spaces.

- *

- * @param[in]   s The address of the string pointer to update.

- * @return      String without white spaces.

- */

-static uint32_t DbgConsole_ScanIgnoreWhiteSpace(const char **s)

-{

-    uint8_t count = 0;

-    char c;

-

-    c = **s;

-    while ((c == ' ') || (c == '\t') || (c == '\n') || (c == '\r') || (c == '\v') || (c == '\f'))

-    {

-        count++;

-        (*s)++;

-        c = **s;

-    }

-    return count;

-}

-

-/*!

  * @brief This function puts padding character.

  *

  * @param[in] c         Padding character.

@@ -326,21 +278,23 @@ static void DbgConsole_PrintfPaddingCharacter(
 static int32_t DbgConsole_ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps)

 {

 #if PRINTF_ADVANCED_ENABLE

-    int64_t a;

-    int64_t b;

-    int64_t c;

-

-    uint64_t ua;

-    uint64_t ub;

-    uint64_t uc;

+    long long int a;

+    long long int b;

+    long long int c;

+

+    unsigned long long int ua;

+    unsigned long long int ub;

+    unsigned long long int uc;

+    unsigned long long int uc_param;

 #else

-    int32_t a;

-    int32_t b;

-    int32_t c;

-

-    uint32_t ua;

-    uint32_t ub;

-    uint32_t uc;

+    int a;

+    int b;

+    int c;

+

+    unsigned int ua;

+    unsigned int ub;

+    unsigned int uc;

+    unsigned int uc_param;

 #endif /* PRINTF_ADVANCED_ENABLE */

 

     int32_t nlen;

@@ -354,12 +308,43 @@ static int32_t DbgConsole_ConvertRadixNumToString(char *numstr, void *nump, int3
     neg = 0;

 #endif

 

+#if PRINTF_ADVANCED_ENABLE

+    a        = 0;

+    b        = 0;

+    c        = 0;

+    ua       = 0ULL;

+    ub       = 0ULL;

+    uc       = 0ULL;

+    uc_param = 0ULL;

+#else

+    a        = 0;

+    b        = 0;

+    c        = 0;

+    ua       = 0U;

+    ub       = 0U;

+    uc       = 0U;

+    uc_param = 0U;

+#endif /* PRINTF_ADVANCED_ENABLE */

+

+    (void)a;

+    (void)b;

+    (void)c;

+    (void)ua;

+    (void)ub;

+    (void)uc;

+    (void)uc_param;

+    (void)neg;

+    /*

+     * Fix MISRA issue: CID 15985711 (#15 of 15): MISRA C-2012 Control Flow Expressions (MISRA C-2012 Rule 14.3)

+     * misra_c_2012_rule_14_3_violation: Execution cannot reach this statement: a = *((int *)nump);

+     */

+#if PRINTF_ADVANCED_ENABLE

     if (0 != neg)

     {

 #if PRINTF_ADVANCED_ENABLE

-        a = *(int64_t *)nump;

+        a = *(long long int *)nump;

 #else

-        a = *(int32_t *)nump;

+        a = *(int *)nump;

 #endif /* PRINTF_ADVANCED_ENABLE */

         if (a == 0)

         {

@@ -370,23 +355,27 @@ static int32_t DbgConsole_ConvertRadixNumToString(char *numstr, void *nump, int3
         while (a != 0)

         {

 #if PRINTF_ADVANCED_ENABLE

-            b = (int64_t)a / (int64_t)radix;

-            c = (int64_t)a - ((int64_t)b * (int64_t)radix);

+            b = (long long int)a / (long long int)radix;

+            c = (long long int)a - ((long long int)b * (long long int)radix);

             if (c < 0)

             {

-                c = (int64_t)'0' - c;

+                uc       = (unsigned long long int)c;

+                uc_param = ~uc;

+                c        = (long long int)uc_param + 1 + (long long int)'0';

             }

 #else

-            b = a / radix;

-            c = a - (b * radix);

+            b = (int)a / (int)radix;

+            c = (int)a - ((int)b * (int)radix);

             if (c < 0)

             {

-                c = (int32_t)'0' - c;

+                uc       = (unsigned int)c;

+                uc_param = ~uc;

+                c        = (int)uc_param + 1 + (int)'0';

             }

 #endif /* PRINTF_ADVANCED_ENABLE */

             else

             {

-                c = c + '0';

+                c = c + (int)'0';

             }

             a        = b;

             *nstrp++ = (char)c;

@@ -394,11 +383,12 @@ static int32_t DbgConsole_ConvertRadixNumToString(char *numstr, void *nump, int3
         }

     }

     else

+#endif /* PRINTF_ADVANCED_ENABLE */

     {

 #if PRINTF_ADVANCED_ENABLE

-        ua = *(uint64_t *)nump;

+        ua = *(unsigned long long int *)nump;

 #else

-        ua = *(uint32_t *)nump;

+        ua = *(unsigned int *)nump;

 #endif /* PRINTF_ADVANCED_ENABLE */

         if (ua == 0U)

         {

@@ -409,20 +399,20 @@ static int32_t DbgConsole_ConvertRadixNumToString(char *numstr, void *nump, int3
         while (ua != 0U)

         {

 #if PRINTF_ADVANCED_ENABLE

-            ub = (uint64_t)ua / (uint64_t)radix;

-            uc = (uint64_t)ua - ((uint64_t)ub * (uint64_t)radix);

+            ub = (unsigned long long int)ua / (unsigned long long int)radix;

+            uc = (unsigned long long int)ua - ((unsigned long long int)ub * (unsigned long long int)radix);

 #else

-            ub = ua / (uint32_t)radix;

-            uc = ua - (ub * (uint32_t)radix);

+            ub = ua / (unsigned int)radix;

+            uc = ua - (ub * (unsigned int)radix);

 #endif /* PRINTF_ADVANCED_ENABLE */

 

             if (uc < 10U)

             {

-                uc = uc + '0';

+                uc = uc + (unsigned int)'0';

             }

             else

             {

-                uc = uc - 10U + (use_caps ? 'A' : 'a');

+                uc = uc - 10U + (unsigned int)(use_caps ? 'A' : 'a');

             }

             ua       = ub;

             *nstrp++ = (char)uc;

@@ -496,7 +486,7 @@ static int32_t DbgConsole_ConvertFloatRadixNumToString(char *numstr,
     for (i = 0; i < precision_width; i++)

     {

         fb = fa / (double)radix;

-        dc = (fa - (double)(int64_t)fb * (double)radix);

+        dc = (fa - (double)(long long int)fb * (double)radix);

         c  = (int32_t)dc;

         if (c < 0)

         {

@@ -548,8 +538,8 @@ static int32_t DbgConsole_ConvertFloatRadixNumToString(char *numstr,
  * (*func_ptr)(c);

  *

  * @param[in] func_ptr  Function to put character out.

- * @param[in] fmt_ptr   Format string for printf.

- * @param[in] args_ptr  Arguments to printf.

+ * @param[in] fmt       Format string for printf.

+ * @param[in] ap        Arguments to printf.

  *

  * @return Number of characters

  */

@@ -577,12 +567,12 @@ static int DbgConsole_PrintfFormattedData(PUTCHAR_FUNC func_ptr, const char *fmt
     uint32_t flags_used;

     char schar;

     bool dschar;

-    int64_t ival;

-    uint64_t uval = 0;

+    long long int ival;

+    unsigned long long int uval = 0;

     bool valid_precision_width;

 #else

-    int32_t ival;

-    uint32_t uval = 0;

+    int ival;

+    unsigned int uval = 0;

 #endif /* PRINTF_ADVANCED_ENABLE */

 

 #if PRINTF_FLOAT_ENABLE

@@ -660,7 +650,7 @@ static int DbgConsole_PrintfFormattedData(PUTCHAR_FUNC func_ptr, const char *fmt
 #if PRINTF_ADVANCED_ENABLE

             else if (c == '*')

             {

-                field_width = (uint32_t)va_arg(ap, uint32_t);

+                field_width = (uint32_t)va_arg(ap, unsigned int);

             }

 #endif /* PRINTF_ADVANCED_ENABLE */

             else

@@ -695,7 +685,7 @@ static int DbgConsole_PrintfFormattedData(PUTCHAR_FUNC func_ptr, const char *fmt
 #if PRINTF_ADVANCED_ENABLE

                 else if (c == '*')

                 {

-                    precision_width       = (uint32_t)va_arg(ap, uint32_t);

+                    precision_width       = (uint32_t)va_arg(ap, unsigned int);

                     valid_precision_width = true;

                 }

 #endif /* PRINTF_ADVANCED_ENABLE */

@@ -740,6 +730,24 @@ static int DbgConsole_PrintfFormattedData(PUTCHAR_FUNC func_ptr, const char *fmt
                     flags_used |= (uint32_t)kPRINTF_LengthLongLongInt;

                 }

                 break;

+            case 'z':

+                if (sizeof(size_t) == sizeof(uint32_t))

+                {

+                    flags_used |= (uint32_t)kPRINTF_LengthLongInt;

+                }

+                else if (sizeof(size_t) == (2U * sizeof(uint32_t)))

+                {

+                    flags_used |= (uint32_t)kPRINTF_LengthLongLongInt;

+                }

+                else if (sizeof(size_t) == sizeof(uint16_t))

+                {

+                    flags_used |= (uint32_t)kPRINTF_LengthShortInt;

+                }

+                else

+                {

+                    /* MISRA C-2012 Rule 15.7 */

+                }

+                break;

             default:

                 /* we've gone one char too far */

                 --p;

@@ -757,12 +765,16 @@ static int DbgConsole_PrintfFormattedData(PUTCHAR_FUNC func_ptr, const char *fmt
 #if PRINTF_ADVANCED_ENABLE

                     if (0U != (flags_used & (uint32_t)kPRINTF_LengthLongLongInt))

                     {

-                        ival = (int64_t)va_arg(ap, int64_t);

+                        ival = (long long int)va_arg(ap, long long int);

+                    }

+                    else if (0U != (flags_used & (uint32_t)kPRINTF_LengthLongInt))

+                    {

+                        ival = (long int)va_arg(ap, long int);

                     }

                     else

 #endif /* PRINTF_ADVANCED_ENABLE */

                     {

-                        ival = (int32_t)va_arg(ap, int32_t);

+                        ival = (int)va_arg(ap, int);

                     }

                     vlen  = DbgConsole_ConvertRadixNumToString(vstr, &ival, 1, 10, use_caps);

                     vstrp = &vstr[vlen];

@@ -903,12 +915,16 @@ static int DbgConsole_PrintfFormattedData(PUTCHAR_FUNC func_ptr, const char *fmt
 #if PRINTF_ADVANCED_ENABLE

                     if (0U != (flags_used & (uint32_t)kPRINTF_LengthLongLongInt))

                     {

-                        uval = (uint64_t)va_arg(ap, uint64_t);

+                        uval = (unsigned long long int)va_arg(ap, unsigned long long int);

+                    }

+                    else if (0U != (flags_used & (uint32_t)kPRINTF_LengthLongInt))

+                    {

+                        uval = (unsigned long int)va_arg(ap, unsigned long int);

                     }

                     else

 #endif /* PRINTF_ADVANCED_ENABLE */

                     {

-                        uval = (uint32_t)va_arg(ap, uint32_t);

+                        uval = (unsigned int)va_arg(ap, unsigned int);

                     }

                     vlen  = DbgConsole_ConvertRadixNumToString(vstr, &uval, 0, 16, use_caps);

                     vstrp = &vstr[vlen];

@@ -959,15 +975,36 @@ static int DbgConsole_PrintfFormattedData(PUTCHAR_FUNC func_ptr, const char *fmt
                 }

                 if ((c == 'o') || (c == 'b') || (c == 'p') || (c == 'u'))

                 {

-#if PRINTF_ADVANCED_ENABLE

-                    if (0U != (flags_used & (uint32_t)kPRINTF_LengthLongLongInt))

+                    if ('p' == c)

                     {

-                        uval = (uint64_t)va_arg(ap, uint64_t);

+                        /*

+                         * Fix MISRA issue: CID 16209727 (#15 of 15): MISRA C-2012 Pointer Type Conversions (MISRA

+                         * C-2012 Rule 11.6)

+                         * 1. misra_c_2012_rule_11_6_violation: The expression va_arg (ap, void *) of type void * is

+                         * cast to type unsigned int.

+                         *

+                         * Orignal code: uval = (unsigned int)va_arg(ap, void *);

+                         */

+                        void *pval;

+                        pval = (void *)va_arg(ap, void *);

+                        (void)memcpy((void *)&uval, (void *)&pval, sizeof(void *));

                     }

                     else

-#endif /* PRINTF_ADVANCED_ENABLE */

                     {

-                        uval = (uint32_t)va_arg(ap, uint32_t);

+#if PRINTF_ADVANCED_ENABLE

+                        if (0U != (flags_used & (uint32_t)kPRINTF_LengthLongLongInt))

+                        {

+                            uval = (unsigned long long int)va_arg(ap, unsigned long long int);

+                        }

+                        else if (0U != (flags_used & (uint32_t)kPRINTF_LengthLongInt))

+                        {

+                            uval = (unsigned long int)va_arg(ap, unsigned long int);

+                        }

+                        else

+#endif /* PRINTF_ADVANCED_ENABLE */

+                        {

+                            uval = (unsigned int)va_arg(ap, unsigned int);

+                        }

                     }

                     switch (c)

                     {

@@ -1024,7 +1061,7 @@ static int DbgConsole_PrintfFormattedData(PUTCHAR_FUNC func_ptr, const char *fmt
             }

             else if (c == 'c')

             {

-                cval = (int32_t)va_arg(ap, uint32_t);

+                cval = (int32_t)va_arg(ap, unsigned int);

                 (void)func_ptr(cval);

                 count++;

             }

@@ -1092,496 +1129,9 @@ static int DbgConsole_PrintfFormattedData(PUTCHAR_FUNC func_ptr, const char *fmt
         }

         p++;

     }

-    return count;

+    return (int)count;

 }

 

-/*!

- * @brief Converts an input line of ASCII characters based upon a provided

- * string format.

- *

- * @param[in] line_ptr The input line of ASCII data.

- * @param[in] format   Format first points to the format string.

- * @param[in] args_ptr The list of parameters.

- *

- * @return Number of input items converted and assigned.

- * @retval IO_EOF When line_ptr is empty string "".

- */

-static int DbgConsole_ScanfFormattedData(const char *line_ptr, char *format, va_list args_ptr)

-{

-    uint8_t base;

-    int8_t neg;

-    /* Identifier for the format string. */

-    char *c = format;

-    char temp;

-    char *buf;

-    /* Flag telling the conversion specification. */

-    uint32_t flag = 0;

-    /* Filed width for the matching input streams. */

-    uint32_t field_width;

-    /* How many arguments are assigned except the suppress. */

-    uint32_t nassigned = 0;

-    bool match_failure = false;

-    /* How many characters are read from the input streams. */

-    uint32_t n_decode = 0;

-

-    int32_t val;

-

-    const char *s;

-    /* Identifier for the input string. */

-    const char *p = line_ptr;

-

-#if SCANF_FLOAT_ENABLE

-    double fnum = 0.0;

-#endif /* SCANF_FLOAT_ENABLE */

-

-    /* Return EOF error before any conversion. */

-    if (*p == '\0')

-    {

-        return -1;

-    }

-

-    /* Decode directives. */

-    while (('\0' != (*c)) && ('\0' != (*p)))

-    {

-        /* Ignore all white-spaces in the format strings. */

-        if (0U != DbgConsole_ScanIgnoreWhiteSpace((const char **)(void *)&c))

-        {

-            n_decode += DbgConsole_ScanIgnoreWhiteSpace(&p);

-        }

-        else if ((*c != '%') || ((*c == '%') && (*(c + 1) == '%')))

-        {

-            /* Ordinary characters. */

-            c++;

-            if (*p == *c)

-            {

-                n_decode++;

-                p++;

-                c++;

-            }

-            else

-            {

-                /* Match failure. Misalignment with C99, the unmatched characters need to be pushed back to stream.

-                 * However, it is deserted now. */

-                break;

-            }

-        }

-        else

-        {

-            /* convernsion specification */

-            c++;

-            /* Reset. */

-            flag        = 0;

-            field_width = 0;

-            base        = 0;

-

-            /* Loop to get full conversion specification. */

-            while (('\0' != *c) && (0U == (flag & (uint32_t)kSCANF_DestMask)))

-            {

-                switch (*c)

-                {

-#if SCANF_ADVANCED_ENABLE

-                    case '*':

-                        if (0U != (flag & (uint32_t)kSCANF_Suppress))

-                        {

-                            /* Match failure. */

-                            match_failure = true;

-                            break;

-                        }

-                        flag |= (uint32_t)kSCANF_Suppress;

-                        c++;

-                        break;

-                    case 'h':

-                        if (0U != (flag & (uint32_t)kSCANF_LengthMask))

-                        {

-                            /* Match failure. */

-                            match_failure = true;

-                            break;

-                        }

-

-                        if (c[1] == 'h')

-                        {

-                            flag |= (uint32_t)kSCANF_LengthChar;

-                            c++;

-                        }

-                        else

-                        {

-                            flag |= (uint32_t)kSCANF_LengthShortInt;

-                        }

-                        c++;

-                        break;

-                    case 'l':

-                        if (0U != (flag & (uint32_t)kSCANF_LengthMask))

-                        {

-                            /* Match failure. */

-                            match_failure = true;

-                            break;

-                        }

-

-                        if (c[1] == 'l')

-                        {

-                            flag |= (uint32_t)kSCANF_LengthLongLongInt;

-                            c++;

-                        }

-                        else

-                        {

-                            flag |= (uint32_t)kSCANF_LengthLongInt;

-                        }

-                        c++;

-                        break;

-#endif /* SCANF_ADVANCED_ENABLE */

-#if SCANF_FLOAT_ENABLE

-                    case 'L':

-                        if (flag & (uint32_t)kSCANF_LengthMask)

-                        {

-                            /* Match failure. */

-                            match_failure = true;

-                            break;

-                        }

-                        flag |= (uint32_t)kSCANF_LengthLongLongDouble;

-                        c++;

-                        break;

-#endif /* SCANF_FLOAT_ENABLE */

-                    case '0':

-                    case '1':

-                    case '2':

-                    case '3':

-                    case '4':

-                    case '5':

-                    case '6':

-                    case '7':

-                    case '8':

-                    case '9':

-                        if (0U != field_width)

-                        {

-                            /* Match failure. */

-                            match_failure = true;

-                            break;

-                        }

-                        do

-                        {

-                            field_width = field_width * 10U + ((uint32_t)*c - (uint32_t)'0');

-                            c++;

-                        } while ((*c >= '0') && (*c <= '9'));

-                        break;

-                    case 'd':

-                        base = 10;

-                        flag |= (uint32_t)kSCANF_TypeSinged;

-                        flag |= (uint32_t)kSCANF_DestInt;

-                        c++;

-                        break;

-                    case 'u':

-                        base = 10;

-                        flag |= (uint32_t)kSCANF_DestInt;

-                        c++;

-                        break;

-                    case 'o':

-                        base = 8;

-                        flag |= (uint32_t)kSCANF_DestInt;

-                        c++;

-                        break;

-                    case 'x':

-                    case 'X':

-                        base = 16;

-                        flag |= (uint32_t)kSCANF_DestInt;

-                        c++;

-                        break;

-                    case 'i':

-                        base = 0;

-                        flag |= (uint32_t)kSCANF_DestInt;

-                        c++;

-                        break;

-#if SCANF_FLOAT_ENABLE

-                    case 'a':

-                    case 'A':

-                    case 'e':

-                    case 'E':

-                    case 'f':

-                    case 'F':

-                    case 'g':

-                    case 'G':

-                        flag |= kSCANF_DestFloat;

-                        c++;

-                        break;

-#endif /* SCANF_FLOAT_ENABLE */

-                    case 'c':

-                        flag |= (uint32_t)kSCANF_DestChar;

-                        if (0U == field_width)

-                        {

-                            field_width = 1;

-                        }

-                        c++;

-                        break;

-                    case 's':

-                        flag |= (uint32_t)kSCANF_DestString;

-                        c++;

-                        break;

-                    default:

-                        /* Match failure. */

-                        match_failure = true;

-                        break;

-                }

-

-                /* Match failure. */

-                if (match_failure)

-                {

-                    return (int)nassigned;

-                }

-            }

-

-            if (0U == (flag & (uint32_t)kSCANF_DestMask))

-            {

-                /* Format strings are exhausted. */

-                return (int)nassigned;

-            }

-

-            if (0U == field_width)

-            {

-                /* Large than length of a line. */

-                field_width = 99;

-            }

-

-            /* Matching strings in input streams and assign to argument. */

-            switch (flag & (uint32_t)kSCANF_DestMask)

-            {

-                case (uint32_t)kSCANF_DestChar:

-                    s   = (const char *)p;

-                    buf = va_arg(args_ptr, char *);

-                    while (((field_width--) > 0U) && ('\0' != *p))

-                    {

-                        if (0U == (flag & (uint32_t)kSCANF_Suppress))

-                        {

-                            *buf++ = *p++;

-                        }

-                        else

-                        {

-                            p++;

-                        }

-                        n_decode++;

-                    }

-

-                    if ((0U == (flag & (uint32_t)kSCANF_Suppress)) && (s != p))

-                    {

-                        nassigned++;

-                    }

-                    break;

-                case (uint32_t)kSCANF_DestString:

-                    n_decode += DbgConsole_ScanIgnoreWhiteSpace(&p);

-                    s   = p;

-                    buf = va_arg(args_ptr, char *);

-                    while ((field_width-- > 0U) && (*p != '\0') && (*p != ' ') && (*p != '\t') && (*p != '\n') &&

-                           (*p != '\r') && (*p != '\v') && (*p != '\f'))

-                    {

-                        if (0U != (flag & (uint32_t)kSCANF_Suppress))

-                        {

-                            p++;

-                        }

-                        else

-                        {

-                            *buf++ = *p++;

-                        }

-                        n_decode++;

-                    }

-

-                    if ((0U == (flag & (uint32_t)kSCANF_Suppress)) && (s != p))

-                    {

-                        /* Add NULL to end of string. */

-                        *buf = '\0';

-                        nassigned++;

-                    }

-                    break;

-                case (uint32_t)kSCANF_DestInt:

-                    n_decode += DbgConsole_ScanIgnoreWhiteSpace(&p);

-                    s   = p;

-                    val = 0;

-                    if ((base == 0U) || (base == 16U))

-                    {

-                        if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X')))

-                        {

-                            base = 16U;

-                            if (field_width >= 1U)

-                            {

-                                p += 2;

-                                n_decode += 2U;

-                                field_width -= 2U;

-                            }

-                        }

-                    }

-

-                    if (base == 0U)

-                    {

-                        if (s[0] == '0')

-                        {

-                            base = 8U;

-                        }

-                        else

-                        {

-                            base = 10U;

-                        }

-                    }

-

-                    neg = 1;

-                    switch (*p)

-                    {

-                        case '-':

-                            neg = -1;

-                            n_decode++;

-                            p++;

-                            field_width--;

-                            break;

-                        case '+':

-                            neg = 1;

-                            n_decode++;

-                            p++;

-                            field_width--;

-                            break;

-                        default:

-                            /* MISRA C-2012 Rule 16.4 */

-                            break;

-                    }

-

-                    while ((field_width-- > 0U) && (*p > '\0'))

-                    {

-                        if ((*p <= '9') && (*p >= '0'))

-                        {

-                            temp = *p - '0' + (char)0;

-                        }

-                        else if ((*p <= 'f') && (*p >= 'a'))

-                        {

-                            temp = *p - 'a' + (char)10;

-                        }

-                        else if ((*p <= 'F') && (*p >= 'A'))

-                        {

-                            temp = *p - 'A' + (char)10;

-                        }

-                        else

-                        {

-                            temp = (char)base;

-                        }

-

-                        if ((uint8_t)temp >= base)

-                        {

-                            break;

-                        }

-                        else

-                        {

-                            val = (int32_t)base * val + (int32_t)temp;

-                        }

-                        p++;

-                        n_decode++;

-                    }

-                    val *= neg;

-                    if (0U == (flag & (uint32_t)kSCANF_Suppress))

-                    {

-#if SCANF_ADVANCED_ENABLE

-                        switch (flag & (uint32_t)kSCANF_LengthMask)

-                        {

-                            case (uint32_t)kSCANF_LengthChar:

-                                if (0U != (flag & (uint32_t)kSCANF_TypeSinged))

-                                {

-                                    *va_arg(args_ptr, signed char *) = (signed char)val;

-                                }

-                                else

-                                {

-                                    *va_arg(args_ptr, unsigned char *) = (unsigned char)val;

-                                }

-                                break;

-                            case (uint32_t)kSCANF_LengthShortInt:

-                                if (0U != (flag & (uint32_t)kSCANF_TypeSinged))

-                                {

-                                    *va_arg(args_ptr, signed short *) = (signed short)val;

-                                }

-                                else

-                                {

-                                    *va_arg(args_ptr, unsigned short *) = (unsigned short)val;

-                                }

-                                break;

-                            case (uint32_t)kSCANF_LengthLongInt:

-                                if (0U != (flag & (uint32_t)kSCANF_TypeSinged))

-                                {

-                                    *va_arg(args_ptr, signed long int *) = (signed long int)val;

-                                }

-                                else

-                                {

-                                    *va_arg(args_ptr, unsigned long int *) = (unsigned long int)val;

-                                }

-                                break;

-                            case (uint32_t)kSCANF_LengthLongLongInt:

-                                if (0U != (flag & (uint32_t)kSCANF_TypeSinged))

-                                {

-                                    *va_arg(args_ptr, signed long long int *) = (signed long long int)val;

-                                }

-                                else

-                                {

-                                    *va_arg(args_ptr, unsigned long long int *) = (unsigned long long int)val;

-                                }

-                                break;

-                            default:

-                                /* The default type is the type int. */

-                                if (0U != (flag & (uint32_t)kSCANF_TypeSinged))

-                                {

-                                    *va_arg(args_ptr, signed int *) = (signed int)val;

-                                }

-                                else

-                                {

-                                    *va_arg(args_ptr, unsigned int *) = (unsigned int)val;

-                                }

-                                break;

-                        }

-#else

-                        /* The default type is the type int. */

-                        if (0U != (flag & (uint32_t)kSCANF_TypeSinged))

-                        {

-                            *va_arg(args_ptr, signed int *) = (signed int)val;

-                        }

-                        else

-                        {

-                            *va_arg(args_ptr, unsigned int *) = (unsigned int)val;

-                        }

-#endif /* SCANF_ADVANCED_ENABLE */

-                        nassigned++;

-                    }

-                    break;

-#if SCANF_FLOAT_ENABLE

-                case (uint32_t)kSCANF_DestFloat:

-                    n_decode += DbgConsole_ScanIgnoreWhiteSpace(&p);

-                    fnum = strtod(p, (char **)&s);

-

-                    if ((fnum >= HUGE_VAL) || (fnum <= -HUGE_VAL))

-                    {

-                        break;

-                    }

-

-                    n_decode += (int)(s) - (int)(p);

-                    p = s;

-                    if (0U == (flag & (uint32_t)kSCANF_Suppress))

-                    {

-                        if (0U != (flag & (uint32_t)kSCANF_LengthLongLongDouble))

-                        {

-                            *va_arg(args_ptr, double *) = fnum;

-                        }

-                        else

-                        {

-                            *va_arg(args_ptr, float *) = (float)fnum;

-                        }

-                        nassigned++;

-                    }

-                    break;

-#endif /* SCANF_FLOAT_ENABLE */

-                default:

-                    /* Match failure. */

-                    match_failure = true;

-                    break;

-            }

-

-            /* Match failure. */

-            if (match_failure)

-            {

-                return (int)nassigned;

-            }

-        }

-    }

-    return (int)nassigned;

-}

 #endif /* SDK_DEBUGCONSOLE */

 

 /*************Code to support toolchain's printf, scanf *******************************/

@@ -1607,7 +1157,7 @@ size_t __write(int handle, const unsigned char *buffer, size_t size)
          */

         ret = (size_t)-1;

     }

-    else if (kSerialPort_None == s_debugConsole.type)

+    else if (kSerialPort_None == s_debugConsole.serial_port_type)

     {

         /* Do nothing if the debug UART is not initialized. */

         ret = (size_t)-1;

@@ -1631,7 +1181,7 @@ size_t __read(int handle, unsigned char *buffer, size_t size)
     {

         ret = ((size_t)-1);

     }

-    else if (kSerialPort_None == s_debugConsole.type)

+    else if (kSerialPort_None == s_debugConsole.serial_port_type)

     {

         /* Do nothing if the debug UART is not initialized. */

         ret = ((size_t)-1);

@@ -1665,7 +1215,7 @@ int __attribute__((weak)) __sys_write(int handle, char *buffer, int size)
     }

 

     /* Do nothing if the debug UART is not initialized. */

-    if (kSerialPort_None == s_debugConsole.type)

+    if (kSerialPort_None == s_debugConsole.serial_port_type)

     {

         return -1;

     }

@@ -1680,7 +1230,7 @@ int __attribute__((weak)) __sys_readc(void)
 {

     char tmp;

     /* Do nothing if the debug UART is not initialized. */

-    if (kSerialPort_None == s_debugConsole.type)

+    if (kSerialPort_None == s_debugConsole.serial_port_type)

     {

         return -1;

     }

@@ -1716,7 +1266,7 @@ FILE __stdin;
 int fputc(int ch, FILE *f)

 {

     /* Do nothing if the debug UART is not initialized. */

-    if (kSerialPort_None == s_debugConsole.type)

+    if (kSerialPort_None == s_debugConsole.serial_port_type)

     {

         return -1;

     }

@@ -1731,7 +1281,7 @@ int fgetc(FILE *f)
 {

     char ch;

     /* Do nothing if the debug UART is not initialized. */

-    if (kSerialPort_None == s_debugConsole.type)

+    if (kSerialPort_None == s_debugConsole.serial_port_type)

     {

         return -1;

     }

@@ -1789,7 +1339,7 @@ int __attribute__((weak)) _write_r(void *ptr, int handle, char *buffer, int size
     }

 

     /* Do nothing if the debug UART is not initialized. */

-    if (kSerialPort_None == s_debugConsole.type)

+    if (kSerialPort_None == s_debugConsole.serial_port_type)

     {

         return -1;

     }

@@ -1810,7 +1360,7 @@ int __attribute__((weak)) _read_r(void *ptr, int handle, char *buffer, int size)
     }

 

     /* Do nothing if the debug UART is not initialized. */

-    if (kSerialPort_None == s_debugConsole.type)

+    if (kSerialPort_None == s_debugConsole.serial_port_type)

     {

         return -1;

     }

@@ -1842,7 +1392,7 @@ int __attribute__((weak)) _write(int handle, char *buffer, int size)
     }

 

     /* Do nothing if the debug UART is not initialized. */

-    if (kSerialPort_None == s_debugConsole.type)

+    if (kSerialPort_None == s_debugConsole.serial_port_type)

     {

         return -1;

     }

@@ -1863,7 +1413,7 @@ int __attribute__((weak)) _read(int handle, char *buffer, int size)
     }

 

     /* Do nothing if the debug UART is not initialized. */

-    if (kSerialPort_None == s_debugConsole.type)

+    if (kSerialPort_None == s_debugConsole.serial_port_type)

     {

         return -1;

     }

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/utilities/fsl_debug_console.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/utilities/fsl_debug_console.h
index d3f8b562a..5710d3a70 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/utilities/fsl_debug_console.h
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/utilities/fsl_debug_console.h
@@ -1,5 +1,5 @@
 /*

- * Copyright 2017-2018, 2020 NXP

+ * Copyright 2017-2018, 2020, 2022 NXP

  * All rights reserved.

  *

  *

@@ -24,8 +24,8 @@
 

 #include "fsl_common.h"

 

-/*

- * @addtogroup debugconsole

+/*!

+ * @addtogroup debugconsolelite

  * @{

  */

 

@@ -45,6 +45,8 @@
 

 #if defined(SDK_DEBUGCONSOLE) && !(SDK_DEBUGCONSOLE)

 #include <stdio.h>

+#else

+#include <stdarg.h>

 #endif

 

 /*! @brief Definition to printf the float number. */

@@ -74,10 +76,14 @@
  *  if SDK_DEBUGCONSOLE defined to 2,it represents disable debugconsole function.

  */

 #if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE /* Disable debug console */

-#define PRINTF

-#define SCANF

-#define PUTCHAR

-#define GETCHAR

+static inline int DbgConsole_Disabled(void)

+{

+    return -1;

+}

+#define PRINTF(...)  DbgConsole_Disabled()

+#define SCANF(...)   DbgConsole_Disabled()

+#define PUTCHAR(...) DbgConsole_Disabled()

+#define GETCHAR()    DbgConsole_Disabled()

 #elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK /* Select printf, scanf, putchar, getchar of SDK version. */

 #define PRINTF  DbgConsole_Printf

 #define SCANF   DbgConsole_Scanf

@@ -90,13 +96,33 @@
 #define PUTCHAR putchar

 #define GETCHAR getchar

 #endif /* SDK_DEBUGCONSOLE */

+/*! @} */

 

+/*! @brief serial port type

+ *

+ *  The serial port type aligned with the definition in serial manager, but please note

+ *  only kSerialPort_Uart can be supported in debug console lite.

+ */

+#ifndef _SERIAL_PORT_T_

+#define _SERIAL_PORT_T_

 typedef enum _serial_port_type

 {

     kSerialPort_None = 0U, /*!< Serial port is none */

     kSerialPort_Uart = 1U, /*!< Serial port UART */

+    kSerialPort_UsbCdc,    /*!< Serial port USB CDC */

+    kSerialPort_Swo,       /*!< Serial port SWO */

+    kSerialPort_Virtual,   /*!< Serial port Virtual */

+    kSerialPort_Rpmsg,     /*!< Serial port RPMSG */

+    kSerialPort_UartDma,   /*!< Serial port UART DMA*/

+    kSerialPort_SpiMaster, /*!< Serial port SPIMASTER*/

+    kSerialPort_SpiSlave,  /*!< Serial port SPISLAVE*/

 } serial_port_type_t;

+#endif

 

+/*!

+ * @addtogroup debugconsolelite

+ * @{

+ */

 /*******************************************************************************

  * Prototypes

  ******************************************************************************/

@@ -171,7 +197,7 @@ static inline status_t DbgConsole_Deinit(void)
 

 #endif /* ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) */

 

-#if SDK_DEBUGCONSOLE

+#if (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK))

 /*!

  * @brief Writes formatted output to the standard output stream.

  *

@@ -183,6 +209,17 @@ static inline status_t DbgConsole_Deinit(void)
 int DbgConsole_Printf(const char *fmt_s, ...);

 

 /*!

+ * @brief Writes formatted output to the standard output stream.

+ *

+ * Call this function to write a formatted output to the standard output stream.

+ *

+ * @param   fmt_s Format control string.

+ * @param   formatStringArg Format arguments.

+ * @return  Returns the number of characters printed or a negative value if an error occurs.

+ */

+int DbgConsole_Vprintf(const char *fmt_s, va_list formatStringArg);

+

+/*!

  * @brief Writes a character to stdout.

  *

  * Call this function to write a character to stdout.

@@ -197,10 +234,10 @@ int DbgConsole_Putchar(int ch);
  *

  * Call this function to read formatted data from the standard input stream.

  *

- * @param   fmt_ptr Format control string.

+ * @param   fmt_s Format control string.

  * @return  Returns the number of fields successfully converted and assigned.

  */

-int DbgConsole_Scanf(char *fmt_ptr, ...);

+int DbgConsole_Scanf(char *fmt_s, ...);

 

 /*!

  * @brief Reads a character from standard input.

@@ -220,5 +257,4 @@ int DbgConsole_Getchar(void);
 #endif /* __cplusplus */

 

 /*! @} */

-

 #endif /* _FSL_DEBUGCONSOLE_H_ */

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/utilities/fsl_str.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/utilities/fsl_str.c
new file mode 100644
index 000000000..5733c9523
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/utilities/fsl_str.c
@@ -0,0 +1,1618 @@
+/*
+ * Copyright 2017, 2020, 2022 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <math.h>
+#include <stdarg.h>
+#include <stdlib.h>
+#include <errno.h> /* MISRA C-2012 Rule 22.9 */
+#include "fsl_str.h"
+#include "fsl_debug_console.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief The overflow value.*/
+#ifndef HUGE_VAL
+#define HUGE_VAL (99.e99)
+#endif /* HUGE_VAL */
+
+#ifndef MAX_FIELD_WIDTH
+#define MAX_FIELD_WIDTH 99U
+#endif
+
+/*! @brief Keil: suppress ellipsis warning in va_arg usage below. */
+#if defined(__CC_ARM)
+#pragma diag_suppress 1256
+#endif /* __CC_ARM */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Scanline function which ignores white spaces.
+ *
+ * @param[in]   s The address of the string pointer to update.
+ * @return      String without white spaces.
+ */
+static uint32_t ScanIgnoreWhiteSpace(const char **s);
+
+/*!
+ * @brief Converts a radix number to a string and return its length.
+ *
+ * @param[in] numstr    Converted string of the number.
+ * @param[in] nump      Pointer to the number.
+ * @param[in] neg       Polarity of the number.
+ * @param[in] radix     The radix to be converted to.
+ * @param[in] use_caps  Used to identify %x/X output format.
+
+ * @return Length of the converted string.
+ */
+static int32_t ConvertRadixNumToString(char *numstr, void *nump, unsigned int neg, unsigned int radix, bool use_caps);
+
+#if (defined(PRINTF_FLOAT_ENABLE) && (PRINTF_FLOAT_ENABLE  > 0))
+/*!
+ * @brief Converts a floating radix number to a string and return its length.
+ *
+ * @param[in] numstr            Converted string of the number.
+ * @param[in] nump              Pointer to the number.
+ * @param[in] radix             The radix to be converted to.
+ * @param[in] precision_width   Specify the precision width.
+
+ * @return Length of the converted string.
+ */
+static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width);
+
+#endif /* PRINTF_FLOAT_ENABLE */
+
+/*************Code for process formatted data*******************************/
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
+static uint8_t PrintGetSignChar(long long int ival, uint32_t flags_used, char *schar)
+{
+    uint8_t len = 1U;
+    if (ival < 0)
+    {
+        *schar = '-';
+    }
+    else
+    {
+        if (0U != (flags_used & (uint32_t)kPRINTF_Plus))
+        {
+            *schar = '+';
+        }
+        else if (0U != (flags_used & (uint32_t)kPRINTF_Space))
+        {
+            *schar = ' ';
+        }
+        else
+        {
+            *schar = '\0';
+            len    = 0U;
+        }
+    }
+    return len;
+}
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+static uint32_t PrintGetWidth(const char **p, va_list *ap)
+{
+    uint32_t field_width = 0;
+    uint8_t done         = 0U;
+    char c;
+
+    while (0U == done)
+    {
+        c = *(++(*p));
+        if ((c >= '0') && (c <= '9'))
+        {
+            (field_width) = ((field_width)*10U) + ((uint32_t)c - (uint32_t)'0');
+        }
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+        else if (c == '*')
+        {
+            (field_width) = (uint32_t)va_arg(*ap, uint32_t);
+        }
+#endif /* PRINTF_ADVANCED_ENABLE */
+        else
+        {
+            /* We've gone one char too far. */
+            --(*p);
+            done = 1U;
+        }
+    }
+    return field_width;
+}
+
+static uint32_t PrintGetPrecision(const char **s, va_list *ap, bool *valid_precision_width)
+{
+    const char *p            = *s;
+    uint32_t precision_width = 6U;
+    uint8_t done             = 0U;
+
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+    if (NULL != valid_precision_width)
+    {
+        *valid_precision_width = false;
+    }
+#endif /* PRINTF_ADVANCED_ENABLE */
+    if (*++p == '.')
+    {
+        /* Must get precision field width, if present. */
+        precision_width = 0U;
+        done            = 0U;
+        while (0U == done)
+        {
+            char c = *++p;
+            if ((c >= '0') && (c <= '9'))
+            {
+                precision_width = (precision_width * 10U) + ((uint32_t)c - (uint32_t)'0');
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+                if (NULL != valid_precision_width)
+                {
+                    *valid_precision_width = true;
+                }
+#endif /* PRINTF_ADVANCED_ENABLE */
+            }
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+            else if (c == '*')
+            {
+                precision_width = (uint32_t)va_arg(*ap, uint32_t);
+                if (NULL != valid_precision_width)
+                {
+                    *valid_precision_width = true;
+                }
+            }
+#endif /* PRINTF_ADVANCED_ENABLE */
+            else
+            {
+                /* We've gone one char too far. */
+                --p;
+                done = 1U;
+            }
+        }
+    }
+    else
+    {
+        /* We've gone one char too far. */
+        --p;
+    }
+    *s = p;
+    return precision_width;
+}
+
+static uint32_t PrintIsobpu(const char c)
+{
+    uint32_t ret = 0U;
+    if ((c == 'o') || (c == 'b') || (c == 'p') || (c == 'u'))
+    {
+        ret = 1U;
+    }
+    return ret;
+}
+
+static uint32_t PrintIsdi(const char c)
+{
+    uint32_t ret = 0U;
+    if ((c == 'd') || (c == 'i'))
+    {
+        ret = 1U;
+    }
+    return ret;
+}
+
+static void PrintOutputdifFobpu(uint32_t flags_used,
+                                uint32_t field_width,
+                                uint32_t vlen,
+                                char schar,
+                                char *vstrp,
+                                printfCb cb,
+                                char *buf,
+                                int32_t *count)
+{
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+    /* Do the ZERO pad. */
+    if (0U != (flags_used & (uint32_t)kPRINTF_Zero))
+    {
+        if ('\0' != schar)
+        {
+            cb(buf, count, schar, 1);
+            schar = '\0';
+        }
+        cb(buf, count, '0', (int)field_width - (int)vlen);
+        vlen = field_width;
+    }
+    else
+    {
+        if (0U == (flags_used & (uint32_t)kPRINTF_Minus))
+        {
+            cb(buf, count, ' ', (int)field_width - (int)vlen);
+            if ('\0' != schar)
+            {
+                cb(buf, count, schar, 1);
+                schar = '\0';
+            }
+        }
+    }
+    /* The string was built in reverse order, now display in correct order. */
+    if ('\0' != schar)
+    {
+        cb(buf, count, schar, 1);
+    }
+#else
+    cb(buf, count, ' ', (int)field_width - (int)vlen);
+#endif /* PRINTF_ADVANCED_ENABLE */
+    while ('\0' != (*vstrp))
+    {
+        cb(buf, count, *vstrp--, 1);
+    }
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+    if (0U != (flags_used & (uint32_t)kPRINTF_Minus))
+    {
+        cb(buf, count, ' ', (int)field_width - (int)vlen);
+    }
+#endif /* PRINTF_ADVANCED_ENABLE */
+}
+
+static void PrintOutputxX(uint32_t flags_used,
+                          uint32_t field_width,
+                          uint32_t vlen,
+                          bool use_caps,
+                          char *vstrp,
+                          printfCb cb,
+                          char *buf,
+                          int32_t *count)
+{
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+    uint8_t dschar = 0;
+    if (0U != (flags_used & (uint32_t)kPRINTF_Zero))
+    {
+        if (0U != (flags_used & (uint32_t)kPRINTF_Pound))
+        {
+            cb(buf, count, '0', 1);
+            cb(buf, count, (use_caps ? 'X' : 'x'), 1);
+            dschar = 1U;
+        }
+        cb(buf, count, '0', (int)field_width - (int)vlen);
+        vlen = field_width;
+    }
+    else
+    {
+        if (0U == (flags_used & (uint32_t)kPRINTF_Minus))
+        {
+            if (0U != (flags_used & (uint32_t)kPRINTF_Pound))
+            {
+                vlen += 2U;
+            }
+            cb(buf, count, ' ', (int)field_width - (int)vlen);
+            if (0U != (flags_used & (uint32_t)kPRINTF_Pound))
+            {
+                cb(buf, count, '0', 1);
+                cb(buf, count, (use_caps ? 'X' : 'x'), 1);
+                dschar = 1U;
+            }
+        }
+    }
+
+    if ((0U != (flags_used & (uint32_t)kPRINTF_Pound)) && (0U == dschar))
+    {
+        cb(buf, count, '0', 1);
+        cb(buf, count, (use_caps ? 'X' : 'x'), 1);
+        vlen += 2U;
+    }
+#else
+    cb(buf, count, ' ', (int)field_width - (int)vlen);
+#endif /* PRINTF_ADVANCED_ENABLE */
+    while ('\0' != (*vstrp))
+    {
+        cb(buf, count, *vstrp--, 1);
+    }
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+    if (0U != (flags_used & (uint32_t)kPRINTF_Minus))
+    {
+        cb(buf, count, ' ', (int)field_width - (int)vlen);
+    }
+#endif /* PRINTF_ADVANCED_ENABLE */
+}
+
+static uint32_t PrintIsfF(const char c)
+{
+    uint32_t ret = 0U;
+    if ((c == 'f') || (c == 'F'))
+    {
+        ret = 1U;
+    }
+    return ret;
+}
+
+static uint32_t PrintIsxX(const char c)
+{
+    uint32_t ret = 0U;
+    if ((c == 'x') || (c == 'X'))
+    {
+        ret = 1U;
+    }
+    return ret;
+}
+
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+static uint32_t PrintCheckFlags(const char **s)
+{
+    const char *p = *s;
+    /* First check for specification modifier flags. */
+    uint32_t flags_used = 0U;
+    bool done           = false;
+    while (false == done)
+    {
+        switch (*++p)
+        {
+            case '-':
+                flags_used |= (uint32_t)kPRINTF_Minus;
+                break;
+            case '+':
+                flags_used |= (uint32_t)kPRINTF_Plus;
+                break;
+            case ' ':
+                flags_used |= (uint32_t)kPRINTF_Space;
+                break;
+            case '0':
+                flags_used |= (uint32_t)kPRINTF_Zero;
+                break;
+            case '#':
+                flags_used |= (uint32_t)kPRINTF_Pound;
+                break;
+            default:
+                /* We've gone one char too far. */
+                --p;
+                done = true;
+                break;
+        }
+    }
+    *s = p;
+    return flags_used;
+}
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+/*
+ * Check for the length modifier.
+ */
+static uint32_t PrintGetLengthFlag(const char **s)
+{
+    const char *p = *s;
+    /* First check for specification modifier flags. */
+    uint32_t flags_used = 0U;
+
+    switch (/* c = */ *++p)
+    {
+        case 'h':
+            if (*++p != 'h')
+            {
+                flags_used |= (uint32_t)kPRINTF_LengthShortInt;
+                --p;
+            }
+            else
+            {
+                flags_used |= (uint32_t)kPRINTF_LengthChar;
+            }
+            break;
+        case 'l':
+            if (*++p != 'l')
+            {
+                flags_used |= (uint32_t)kPRINTF_LengthLongInt;
+                --p;
+            }
+            else
+            {
+                flags_used |= (uint32_t)kPRINTF_LengthLongLongInt;
+            }
+            break;
+        case 'z':
+            if (sizeof(size_t) == sizeof(uint32_t))
+            {
+                flags_used |= (uint32_t)kPRINTF_LengthLongInt;
+            }
+            else if (sizeof(size_t) == (2U * sizeof(uint32_t)))
+            {
+                flags_used |= (uint32_t)kPRINTF_LengthLongLongInt;
+            }
+            else if (sizeof(size_t) == sizeof(uint16_t))
+            {
+                flags_used |= (uint32_t)kPRINTF_LengthShortInt;
+            }
+            else
+            {
+                /* MISRA C-2012 Rule 15.7 */
+            }
+            break;
+        default:
+            /* we've gone one char too far */
+            --p;
+            break;
+    }
+    *s = p;
+    return flags_used;
+}
+#else
+static void PrintFilterLengthFlag(const char **s)
+{
+    const char *p = *s;
+    char ch;
+
+    do
+    {
+        ch = *++p;
+    } while ((ch == 'h') || (ch == 'l'));
+
+    *s = --p;
+}
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+static uint8_t PrintGetRadixFromobpu(const char c)
+{
+    uint8_t radix;
+
+    if (c == 'o')
+    {
+        radix = 8U;
+    }
+    else if (c == 'b')
+    {
+        radix = 2U;
+    }
+    else if (c == 'p')
+    {
+        radix = 16U;
+    }
+    else
+    {
+        radix = 10U;
+    }
+    return radix;
+}
+
+static uint32_t ScanIsWhiteSpace(const char c)
+{
+    uint32_t ret = 0U;
+    if ((c == ' ') || (c == '\t') || (c == '\n') || (c == '\r') || (c == '\v') || (c == '\f'))
+    {
+        ret = 1U;
+    }
+    return ret;
+}
+
+static uint32_t ScanIgnoreWhiteSpace(const char **s)
+{
+    uint32_t count = 0U;
+    char c;
+
+    c = **s;
+    while (1U == ScanIsWhiteSpace(c))
+    {
+        count++;
+        (*s)++;
+        c = **s;
+    }
+    return count;
+}
+
+static int32_t ConvertRadixNumToString(char *numstr, void *nump, unsigned int neg, unsigned int radix, bool use_caps)
+{
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+    long long int a;
+    long long int b;
+    long long int c;
+
+    unsigned long long int ua;
+    unsigned long long int ub;
+    unsigned long long int uc;
+    unsigned long long int uc_param;
+#else
+    int a;
+    int b;
+    int c;
+
+    unsigned int ua;
+    unsigned int ub;
+    unsigned int uc;
+    unsigned int uc_param;
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+    int32_t nlen;
+    char *nstrp;
+
+    nlen     = 0;
+    nstrp    = numstr;
+    *nstrp++ = '\0';
+
+#if !(defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0u))
+    neg = 0U;
+#endif
+
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+    a        = 0;
+    b        = 0;
+    c        = 0;
+    ua       = 0ULL;
+    ub       = 0ULL;
+    uc       = 0ULL;
+    uc_param = 0ULL;
+#else
+    a = 0;
+    b = 0;
+    c = 0;
+    ua = 0U;
+    ub = 0U;
+    uc = 0U;
+    uc_param = 0U;
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+    (void)a;
+    (void)b;
+    (void)c;
+    (void)ua;
+    (void)ub;
+    (void)uc;
+    (void)uc_param;
+    (void)neg;
+    /*
+     * Fix MISRA issue: CID 15972928 (#15 of 15): MISRA C-2012 Control Flow Expressions (MISRA C-2012 Rule 14.3)
+     * misra_c_2012_rule_14_3_violation: Execution cannot reach this statement: a = *((int *)nump);
+     */
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+    if (0U != neg)
+    {
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+        a = *(long long int *)nump;
+#else
+        a = *(int *)nump;
+#endif /* PRINTF_ADVANCED_ENABLE */
+        if (a == 0)
+        {
+            *nstrp = '0';
+            ++nlen;
+            return nlen;
+        }
+        while (a != 0)
+        {
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+            b = (long long int)a / (long long int)radix;
+            c = (long long int)a - ((long long int)b * (long long int)radix);
+            if (c < 0)
+            {
+                uc       = (unsigned long long int)c;
+                uc_param = ~uc;
+                c        = (long long int)uc_param + 1 + (long long int)'0';
+            }
+#else
+            b = (int)a / (int)radix;
+            c = (int)a - ((int)b * (int)radix);
+            if (c < 0)
+            {
+                uc       = (unsigned int)c;
+                uc_param = ~uc;
+                c        = (int)uc_param + 1 + (int)'0';
+            }
+#endif /* PRINTF_ADVANCED_ENABLE */
+            else
+            {
+                c = c + (int)'0';
+            }
+            a        = b;
+            *nstrp++ = (char)c;
+            ++nlen;
+        }
+    }
+    else
+#endif /* PRINTF_ADVANCED_ENABLE */
+    {
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+        ua = *(unsigned long long int *)nump;
+#else
+        ua = *(unsigned int *)nump;
+#endif /* PRINTF_ADVANCED_ENABLE */
+        if (ua == 0U)
+        {
+            *nstrp = '0';
+            ++nlen;
+            return nlen;
+        }
+        while (ua != 0U)
+        {
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+            ub = (unsigned long long int)ua / (unsigned long long int)radix;
+            uc = (unsigned long long int)ua - ((unsigned long long int)ub * (unsigned long long int)radix);
+#else
+            ub = ua / (unsigned int)radix;
+            uc = ua - (ub * (unsigned int)radix);
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+            if (uc < 10U)
+            {
+                uc = uc + (unsigned int)'0';
+            }
+            else
+            {
+                uc = uc - 10U + (unsigned int)(use_caps ? 'A' : 'a');
+            }
+            ua       = ub;
+            *nstrp++ = (char)uc;
+            ++nlen;
+        }
+    }
+    return nlen;
+}
+
+#if (defined(PRINTF_FLOAT_ENABLE) && (PRINTF_FLOAT_ENABLE > 0U))
+static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width)
+{
+    int32_t a;
+    int32_t b;
+    int32_t c;
+    int32_t i;
+    uint32_t uc;
+    double fa;
+    double dc;
+    double fb;
+    double r;
+    double fractpart;
+    double intpart;
+
+    int32_t nlen;
+    char *nstrp;
+    nlen     = 0;
+    nstrp    = numstr;
+    *nstrp++ = '\0';
+    r        = *(double *)nump;
+    if (0.0 == r)
+    {
+        *nstrp = '0';
+        ++nlen;
+        return nlen;
+    }
+    fractpart = modf((double)r, (double *)&intpart);
+    /* Process fractional part. */
+    for (i = 0; i < (int32_t)precision_width; i++)
+    {
+        fractpart *= (double)radix;
+    }
+    if (r >= (double)0.0)
+    {
+        fa = fractpart + (double)0.5;
+        if (fa >= pow((double)10, (double)precision_width))
+        {
+            intpart++;
+        }
+    }
+    else
+    {
+        fa = fractpart - (double)0.5;
+        if (fa <= -pow((double)10, (double)precision_width))
+        {
+            intpart--;
+        }
+    }
+    for (i = 0; i < (int32_t)precision_width; i++)
+    {
+        fb = fa / (double)radix;
+        dc = (fa - (double)(long long int)fb * (double)radix);
+        c  = (int32_t)dc;
+        if (c < 0)
+        {
+            uc = (uint32_t)c;
+            uc = ~uc;
+            c  = (int32_t)uc;
+            c += (int32_t)1;
+            c += (int32_t)'0';
+        }
+        else
+        {
+            c = c + '0';
+        }
+        fa       = fb;
+        *nstrp++ = (char)c;
+        ++nlen;
+    }
+    *nstrp++ = (char)'.';
+    ++nlen;
+    a = (int32_t)intpart;
+    if (a == 0)
+    {
+        *nstrp++ = '0';
+        ++nlen;
+    }
+    else
+    {
+        while (a != 0)
+        {
+            b = (int32_t)a / (int32_t)radix;
+            c = (int32_t)a - ((int32_t)b * (int32_t)radix);
+            if (c < 0)
+            {
+                uc = (uint32_t)c;
+                uc = ~uc;
+                c  = (int32_t)uc;
+                c += (int32_t)1;
+                c += (int32_t)'0';
+            }
+            else
+            {
+                c = c + '0';
+            }
+            a        = b;
+            *nstrp++ = (char)c;
+            ++nlen;
+        }
+    }
+    return nlen;
+}
+#endif /* PRINTF_FLOAT_ENABLE */
+
+/*!
+ * brief This function outputs its parameters according to a formatted string.
+ *
+ * note I/O is performed by calling given function pointer using following
+ * (*func_ptr)(c);
+ *
+ * param[in] fmt   Format string for printf.
+ * param[in] ap    Arguments to printf.
+ * param[in] buf  pointer to the buffer
+ * param cb print callback function pointer
+ *
+ * return Number of characters to be print
+ */
+int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb)
+{
+    /* va_list ap; */
+    const char *p;
+    char c;
+
+    char vstr[33];
+    char *vstrp  = NULL;
+    int32_t vlen = 0;
+
+    int32_t count = 0;
+
+    uint32_t field_width;
+    uint32_t precision_width;
+    char *sval;
+    int32_t cval;
+    bool use_caps;
+    unsigned int radix = 0;
+
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+    uint32_t flags_used;
+    char schar;
+    long long int ival;
+    unsigned long long int uval = 0;
+#define STR_FORMAT_PRINTF_UVAL_TYPE unsigned long long int
+#define STR_FORMAT_PRINTF_IVAL_TYPE long long int
+    bool valid_precision_width;
+#else
+    int ival;
+    unsigned int uval = 0;
+#define STR_FORMAT_PRINTF_UVAL_TYPE unsigned int
+#define STR_FORMAT_PRINTF_IVAL_TYPE int
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+#if (defined(PRINTF_FLOAT_ENABLE) && (PRINTF_FLOAT_ENABLE > 0))
+    double fval;
+#endif /* PRINTF_FLOAT_ENABLE */
+
+    /* Start parsing apart the format string and display appropriate formats and data. */
+    p = fmt;
+    while (true)
+    {
+        if ('\0' == *p)
+        {
+            break;
+        }
+        c = *p;
+        /*
+         * All formats begin with a '%' marker.  Special chars like
+         * '\n' or '\t' are normally converted to the appropriate
+         * character by the __compiler__.  Thus, no need for this
+         * routine to account for the '\' character.
+         */
+        if (c != '%')
+        {
+            cb(buf, &count, c, 1);
+            p++;
+            /* By using 'continue', the next iteration of the loop is used, skipping the code that follows. */
+            continue;
+        }
+
+        use_caps = true;
+
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+        /* First check for specification modifier flags. */
+        flags_used = PrintCheckFlags(&p);
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+        /* Next check for minimum field width. */
+        field_width = PrintGetWidth(&p, &ap);
+
+        /* Next check for the width and precision field separator. */
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+        precision_width = PrintGetPrecision(&p, &ap, &valid_precision_width);
+#else
+        precision_width = PrintGetPrecision(&p, &ap, NULL);
+        (void)precision_width;
+#endif
+
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+        /* Check for the length modifier. */
+        flags_used |= PrintGetLengthFlag(&p);
+#else
+        /* Filter length modifier. */
+        PrintFilterLengthFlag(&p);
+#endif
+
+        /* Now we're ready to examine the format. */
+        c = *++p;
+        {
+            if (1U == PrintIsdi(c))
+            {
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+                if (0U != (flags_used & (uint32_t)kPRINTF_LengthLongLongInt))
+                {
+                    ival = (long long int)va_arg(ap, long long int);
+                }
+                else if (0U != (flags_used & (uint32_t)kPRINTF_LengthLongInt))
+                {
+                    ival = (long long int)va_arg(ap, long int);
+                }
+                else
+#endif /* PRINTF_ADVANCED_ENABLE */
+                {
+                    ival = (STR_FORMAT_PRINTF_IVAL_TYPE)va_arg(ap, int);
+                }
+
+                vlen  = ConvertRadixNumToString((char *)vstr, (void *)&ival, 1, 10, use_caps);
+                vstrp = &vstr[vlen];
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+                vlen += (int)PrintGetSignChar(ival, flags_used, &schar);
+                PrintOutputdifFobpu(flags_used, field_width, (unsigned int)vlen, schar, vstrp, cb, buf, &count);
+#else
+                PrintOutputdifFobpu(0U, field_width, (unsigned int)vlen, '\0', vstrp, cb, buf, &count);
+#endif
+            }
+            else if (1U == PrintIsfF(c))
+            {
+#if (defined(PRINTF_FLOAT_ENABLE) && (PRINTF_FLOAT_ENABLE > 0))
+                fval  = (double)va_arg(ap, double);
+                vlen  = ConvertFloatRadixNumToString(vstr, &fval, 10, precision_width);
+                vstrp = &vstr[vlen];
+
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+                vlen += (int32_t)PrintGetSignChar(((fval < 0.0) ? ((long long int)-1) : ((long long int)fval)),
+                                                  flags_used, &schar);
+                PrintOutputdifFobpu(flags_used, field_width, (unsigned int)vlen, schar, vstrp, cb, buf, &count);
+#else
+                PrintOutputdifFobpu(0, field_width, (unsigned int)vlen, '\0', vstrp, cb, buf, &count);
+#endif
+
+#else
+                (void)va_arg(ap, double);
+#endif /* PRINTF_FLOAT_ENABLE */
+            }
+            else if (1U == PrintIsxX(c))
+            {
+                if (c == 'x')
+                {
+                    use_caps = false;
+                }
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+                if (0U != (flags_used & (unsigned int)kPRINTF_LengthLongLongInt))
+                {
+                    uval = (unsigned long long int)va_arg(ap, unsigned long long int);
+                }
+                else if (0U != (flags_used & (unsigned int)kPRINTF_LengthLongInt))
+                {
+                    uval = (unsigned long long int)va_arg(ap, unsigned long int);
+                }
+                else
+#endif /* PRINTF_ADVANCED_ENABLE */
+                {
+                    uval = (STR_FORMAT_PRINTF_UVAL_TYPE)va_arg(ap, unsigned int);
+                }
+
+                vlen  = ConvertRadixNumToString((char *)vstr, (void *)&uval, 0, 16, use_caps);
+                vstrp = &vstr[vlen];
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+                PrintOutputxX(flags_used, field_width, (unsigned int)vlen, use_caps, vstrp, cb, buf, &count);
+#else
+                PrintOutputxX(0U, field_width, (uint32_t)vlen, use_caps, vstrp, cb, buf, &count);
+#endif
+            }
+            else if (1U == PrintIsobpu(c))
+            {
+                if ('p' == c)
+                {
+                    /*
+                     * Fix MISRA issue: CID 17205581 (#15 of 15): MISRA C-2012 Pointer Type Conversions (MISRA C-2012
+                     * Rule 11.6) 1.misra_c_2012_rule_11_6_violation: The expression va_arg (ap, void *) of type void *
+                     * is cast to type uint32_t.
+                     *
+                     * Orignal code: uval = (STR_FORMAT_PRINTF_UVAL_TYPE)(uint32_t)va_arg(ap, void *);
+                     */
+                    void *pval;
+                    pval = (void *)va_arg(ap, void *);
+                    (void)memcpy((void *)&uval, (void *)&pval, sizeof(void *));
+                }
+                else
+                {
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+                    if (0U != (flags_used & (unsigned int)kPRINTF_LengthLongLongInt))
+                    {
+                        uval = (unsigned long long int)va_arg(ap, unsigned long long int);
+                    }
+                    else if (0U != (flags_used & (unsigned int)kPRINTF_LengthLongInt))
+                    {
+                        uval = (unsigned long long int)va_arg(ap, unsigned long int);
+                    }
+                    else
+                    {
+#endif /* PRINTF_ADVANCED_ENABLE */
+                        uval = (STR_FORMAT_PRINTF_UVAL_TYPE)va_arg(ap, unsigned int);
+                    }
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+                }
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+                radix = PrintGetRadixFromobpu(c);
+
+                vlen  = ConvertRadixNumToString((char *)vstr, (void *)&uval, 0, radix, use_caps);
+                vstrp = &vstr[vlen];
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+                PrintOutputdifFobpu(flags_used, field_width, (unsigned int)vlen, '\0', vstrp, cb, buf, &count);
+#else
+                PrintOutputdifFobpu(0U, field_width, (uint32_t)vlen, '\0', vstrp, cb, buf, &count);
+#endif
+            }
+            else if (c == 'c')
+            {
+                cval = (int32_t)va_arg(ap, int);
+                cb(buf, &count, cval, 1);
+            }
+            else if (c == 's')
+            {
+                sval = (char *)va_arg(ap, char *);
+                if (NULL != sval)
+                {
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+                    if (valid_precision_width)
+                    {
+                        vlen = (int)precision_width;
+                    }
+                    else
+                    {
+                        vlen = (int)strlen(sval);
+                    }
+#else
+                    vlen = (int32_t)strlen(sval);
+#endif /* PRINTF_ADVANCED_ENABLE */
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+                    if (0U == (flags_used & (unsigned int)kPRINTF_Minus))
+#endif /* PRINTF_ADVANCED_ENABLE */
+                    {
+                        cb(buf, &count, ' ', (int)field_width - (int)vlen);
+                    }
+
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+                    if (valid_precision_width)
+                    {
+                        while (('\0' != *sval) && (vlen > 0))
+                        {
+                            cb(buf, &count, *sval++, 1);
+                            vlen--;
+                        }
+                        /* In case that vlen sval is shorter than vlen */
+                        vlen = (int)precision_width - vlen;
+                    }
+                    else
+                    {
+#endif /* PRINTF_ADVANCED_ENABLE */
+                        while ('\0' != (*sval))
+                        {
+                            cb(buf, &count, *sval++, 1);
+                        }
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+                    }
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+                    if (0U != (flags_used & (unsigned int)kPRINTF_Minus))
+                    {
+                        cb(buf, &count, ' ', (int)field_width - vlen);
+                    }
+#endif /* PRINTF_ADVANCED_ENABLE */
+                }
+            }
+            else
+            {
+                cb(buf, &count, c, 1);
+            }
+        }
+        p++;
+    }
+
+    return (int)count;
+}
+
+#if (defined(SCANF_FLOAT_ENABLE) && (SCANF_FLOAT_ENABLE > 0))
+static uint8_t StrFormatScanIsFloat(char *c)
+{
+    uint8_t ret = 0U;
+    if (('a' == (*c)) || ('A' == (*c)) || ('e' == (*c)) || ('E' == (*c)) || ('f' == (*c)) || ('F' == (*c)) ||
+        ('g' == (*c)) || ('G' == (*c)))
+    {
+        ret = 1U;
+    }
+    return ret;
+}
+#endif
+
+static uint8_t StrFormatScanIsFormatStarting(char *c)
+{
+    uint8_t ret = 1U;
+    if ((*c != '%'))
+    {
+        ret = 0U;
+    }
+    else if (*(c + 1) == '%')
+    {
+        ret = 0U;
+    }
+    else
+    {
+        /*MISRA rule 15.7*/
+    }
+
+    return ret;
+}
+
+static uint8_t StrFormatScanGetBase(uint8_t base, const char *s)
+{
+    if (base == 0U)
+    {
+        if (s[0] == '0')
+        {
+            if ((s[1] == 'x') || (s[1] == 'X'))
+            {
+                base = 16;
+            }
+            else
+            {
+                base = 8;
+            }
+        }
+        else
+        {
+            base = 10;
+        }
+    }
+    return base;
+}
+
+static uint8_t StrFormatScanCheckSymbol(const char *p, int8_t *neg)
+{
+    uint8_t len;
+    switch (*p)
+    {
+        case '-':
+            *neg = -1;
+            len  = 1;
+            break;
+        case '+':
+            *neg = 1;
+            len  = 1;
+            break;
+        default:
+            *neg = 1;
+            len  = 0;
+            break;
+    }
+    return len;
+}
+
+static uint8_t StrFormatScanFillInteger(uint32_t flag, va_list *args_ptr, int32_t val)
+{
+#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0))
+    if (0U != (flag & (uint32_t)kSCANF_Suppress))
+    {
+        return 0u;
+    }
+
+    switch (flag & (uint32_t)kSCANF_LengthMask)
+    {
+        case (uint32_t)kSCANF_LengthChar:
+            if (0U != (flag & (uint32_t)kSCANF_TypeSinged))
+            {
+                *va_arg(*args_ptr, signed char *) = (signed char)val;
+            }
+            else
+            {
+                *va_arg(*args_ptr, unsigned char *) = (unsigned char)val;
+            }
+            break;
+        case (uint32_t)kSCANF_LengthShortInt:
+            if (0U != (flag & (uint32_t)kSCANF_TypeSinged))
+            {
+                *va_arg(*args_ptr, signed short *) = (signed short)val;
+            }
+            else
+            {
+                *va_arg(*args_ptr, unsigned short *) = (unsigned short)val;
+            }
+            break;
+        case (uint32_t)kSCANF_LengthLongInt:
+            if (0U != (flag & (uint32_t)kSCANF_TypeSinged))
+            {
+                *va_arg(*args_ptr, signed long int *) = (signed long int)val;
+            }
+            else
+            {
+                *va_arg(*args_ptr, unsigned long int *) = (unsigned long int)val;
+            }
+            break;
+        case (uint32_t)kSCANF_LengthLongLongInt:
+            if (0U != (flag & (uint32_t)kSCANF_TypeSinged))
+            {
+                *va_arg(*args_ptr, signed long long int *) = (signed long long int)val;
+            }
+            else
+            {
+                *va_arg(*args_ptr, unsigned long long int *) = (unsigned long long int)val;
+            }
+            break;
+        default:
+            /* The default type is the type int. */
+            if (0U != (flag & (uint32_t)kSCANF_TypeSinged))
+            {
+                *va_arg(*args_ptr, signed int *) = (signed int)val;
+            }
+            else
+            {
+                *va_arg(*args_ptr, unsigned int *) = (unsigned int)val;
+            }
+            break;
+    }
+#else
+    /* The default type is the type int. */
+    if (0U != (flag & (uint32_t)kSCANF_TypeSinged))
+    {
+        *va_arg(*args_ptr, signed int *) = (signed int)val;
+    }
+    else
+    {
+        *va_arg(*args_ptr, unsigned int *) = (unsigned int)val;
+    }
+#endif /* SCANF_ADVANCED_ENABLE */
+
+    return 1u;
+}
+
+#if (defined(SCANF_FLOAT_ENABLE) && (SCANF_FLOAT_ENABLE > 0))
+static uint8_t StrFormatScanFillFloat(uint32_t flag, va_list *args_ptr, double fnum)
+{
+#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0))
+    if (0U != (flag & (uint32_t)kSCANF_Suppress))
+    {
+        return 0u;
+    }
+    else
+#endif /* SCANF_ADVANCED_ENABLE */
+    {
+        if (0U != (flag & (uint32_t)kSCANF_LengthLongLongDouble))
+        {
+            *va_arg(*args_ptr, double *) = fnum;
+        }
+        else
+        {
+            *va_arg(*args_ptr, float *) = (float)fnum;
+        }
+        return 1u;
+    }
+}
+#endif /* SCANF_FLOAT_ENABLE */
+
+static uint8_t StrFormatScanfStringHandling(char **str, uint32_t *flag, uint32_t *field_width, uint8_t *base)
+{
+    uint8_t exitPending = 0U;
+    char *c             = *str;
+
+    /* Loop to get full conversion specification. */
+    while (('\0' != (*c)) && (0U == (*flag & (uint32_t)kSCANF_DestMask)))
+    {
+#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0))
+        if ('*' == (*c))
+        {
+            if (0U != ((*flag) & (uint32_t)kSCANF_Suppress))
+            {
+                /* Match failure. */
+                exitPending = 1U;
+            }
+            else
+            {
+                (*flag) |= (uint32_t)kSCANF_Suppress;
+            }
+        }
+        else if ('h' == (*c))
+        {
+            if (0U != ((*flag) & (uint32_t)kSCANF_LengthMask))
+            {
+                /* Match failure. */
+                exitPending = 1U;
+            }
+            else
+            {
+                if (c[1] == 'h')
+                {
+                    (*flag) |= (uint32_t)kSCANF_LengthChar;
+                    c++;
+                }
+                else
+                {
+                    (*flag) |= (uint32_t)kSCANF_LengthShortInt;
+                }
+            }
+        }
+        else if ('l' == (*c))
+        {
+            if (0U != ((*flag) & (uint32_t)kSCANF_LengthMask))
+            {
+                /* Match failure. */
+                exitPending = 1U;
+            }
+            else
+            {
+                if (c[1] == 'l')
+                {
+                    (*flag) |= (uint32_t)kSCANF_LengthLongLongInt;
+                    c++;
+                }
+                else
+                {
+                    (*flag) |= (uint32_t)kSCANF_LengthLongInt;
+                }
+            }
+        }
+        else
+#endif /* SCANF_ADVANCED_ENABLE */
+#if (defined(SCANF_FLOAT_ENABLE) && (SCANF_FLOAT_ENABLE > 0))
+            if ('L' == (*c))
+        {
+            if (0U != ((*flag) & (uint32_t)kSCANF_LengthMask))
+            {
+                /* Match failure. */
+                exitPending = 1U;
+            }
+            else
+            {
+                (*flag) |= (uint32_t)kSCANF_LengthLongLongDouble;
+            }
+        }
+        else
+#endif /* SCANF_FLOAT_ENABLE */
+            if (((*c) >= '0') && ((*c) <= '9'))
+        {
+            {
+                char *p;
+                errno          = 0;
+                (*field_width) = strtoul(c, &p, 10);
+                if (0 != errno)
+                {
+                    *field_width = 0U;
+                }
+                c = p - 1;
+            }
+        }
+        else if ('d' == (*c))
+        {
+            (*base) = 10U;
+            (*flag) |= (uint32_t)kSCANF_TypeSinged;
+            (*flag) |= (uint32_t)kSCANF_DestInt;
+        }
+        else if ('u' == (*c))
+        {
+            (*base) = 10U;
+            (*flag) |= (uint32_t)kSCANF_DestInt;
+        }
+        else if ('o' == (*c))
+        {
+            (*base) = 8U;
+            (*flag) |= (uint32_t)kSCANF_DestInt;
+        }
+        else if (('x' == (*c)))
+        {
+            (*base) = 16U;
+            (*flag) |= (uint32_t)kSCANF_DestInt;
+        }
+        else if ('X' == (*c))
+        {
+            (*base) = 16U;
+            (*flag) |= (uint32_t)kSCANF_DestInt;
+        }
+        else if ('i' == (*c))
+        {
+            (*base) = 0U;
+            (*flag) |= (uint32_t)kSCANF_DestInt;
+        }
+#if (defined(SCANF_FLOAT_ENABLE) && (SCANF_FLOAT_ENABLE > 0))
+        else if (1U == StrFormatScanIsFloat(c))
+        {
+            (*flag) |= (uint32_t)kSCANF_DestFloat;
+        }
+#endif /* SCANF_FLOAT_ENABLE */
+        else if ('c' == (*c))
+        {
+            (*flag) |= (uint32_t)kSCANF_DestChar;
+            if (MAX_FIELD_WIDTH == (*field_width))
+            {
+                (*field_width) = 1;
+            }
+        }
+        else if ('s' == (*c))
+        {
+            (*flag) |= (uint32_t)kSCANF_DestString;
+        }
+        else
+        {
+            exitPending = 1U;
+        }
+
+        if (1U == exitPending)
+        {
+            break;
+        }
+        else
+        {
+            c++;
+        }
+    }
+    *str = c;
+    return exitPending;
+}
+
+/*!
+ * brief Converts an input line of ASCII characters based upon a provided
+ * string format.
+ *
+ * param[in] line_ptr The input line of ASCII data.
+ * param[in] format   Format first points to the format string.
+ * param[in] args_ptr The list of parameters.
+ *
+ * return Number of input items converted and assigned.
+ * retval IO_EOF When line_ptr is empty string "".
+ */
+int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr)
+{
+    uint8_t base;
+    int8_t neg;
+    /* Identifier for the format string. */
+    char *c = format;
+    char *buf;
+    /* Flag telling the conversion specification. */
+    uint32_t flag = 0;
+    /* Filed width for the matching input streams. */
+    uint32_t field_width;
+    /* How many arguments are assigned except the suppress. */
+    uint32_t nassigned = 0;
+    /* How many characters are read from the input streams. */
+    uint32_t n_decode = 0;
+
+    int32_t val;
+
+    uint8_t added;
+
+    uint8_t exitPending = 0;
+
+    const char *s;
+#if (defined(SCANF_FLOAT_ENABLE) && (SCANF_FLOAT_ENABLE > 0))
+    char *s_temp; /* MISRA C-2012 Rule 11.3 */
+#endif
+
+    /* Identifier for the input string. */
+    const char *p = line_ptr;
+
+#if (defined(SCANF_FLOAT_ENABLE) && (SCANF_FLOAT_ENABLE > 0))
+    double fnum = 0.0;
+#endif /* SCANF_FLOAT_ENABLE */
+    /* Return EOF error before any conversion. */
+    if (*p == '\0')
+    {
+        return -1;
+    }
+
+    /* Decode directives. */
+    while (('\0' != (*c)) && ('\0' != (*p)))
+    {
+        /* Ignore all white-spaces in the format strings. */
+        if (0U != ScanIgnoreWhiteSpace((const char **)((void *)&c)))
+        {
+            n_decode += ScanIgnoreWhiteSpace(&p);
+        }
+        else if (0U == StrFormatScanIsFormatStarting(c))
+        {
+            /* Ordinary characters. */
+            c++;
+            if (*p == *c)
+            {
+                n_decode++;
+                p++;
+                c++;
+            }
+            else
+            {
+                /* Match failure. Misalignment with C99, the unmatched characters need to be pushed back to stream.
+                 * However, it is deserted now. */
+                break;
+            }
+        }
+        else
+        {
+            /* convernsion specification */
+            c++;
+            /* Reset. */
+            flag        = 0;
+            field_width = MAX_FIELD_WIDTH;
+            base        = 0;
+            added       = 0U;
+
+            exitPending = StrFormatScanfStringHandling(&c, &flag, &field_width, &base);
+
+            if (1U == exitPending)
+            {
+                /* Format strings are exhausted. */
+                break;
+            }
+
+            /* Matching strings in input streams and assign to argument. */
+            if ((flag & (uint32_t)kSCANF_DestMask) == (uint32_t)kSCANF_DestChar)
+            {
+                s   = (const char *)p;
+                buf = va_arg(args_ptr, char *);
+                while ((0U != (field_width--))
+#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0U))
+                       && ('\0' != (*p))
+#endif
+                )
+                {
+#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0))
+                    if (0U != (flag & (uint32_t)kSCANF_Suppress))
+                    {
+                        p++;
+                    }
+                    else
+#endif
+                    {
+                        *buf++ = *p++;
+#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0))
+                        added = 1u;
+#endif
+                    }
+                    n_decode++;
+                }
+
+#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0))
+                if (1u == added)
+#endif
+                {
+                    nassigned++;
+                }
+            }
+            else if ((flag & (uint32_t)kSCANF_DestMask) == (uint32_t)kSCANF_DestString)
+            {
+                n_decode += ScanIgnoreWhiteSpace(&p);
+                s   = p;
+                buf = va_arg(args_ptr, char *);
+                while ((0U != (field_width--)) && (*p != '\0') && (0U == ScanIsWhiteSpace(*p)))
+                {
+#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0))
+                    if (0U != (flag & (uint32_t)kSCANF_Suppress))
+                    {
+                        p++;
+                    }
+                    else
+#endif
+                    {
+                        *buf++ = *p++;
+#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0))
+                        added = 1u;
+#endif
+                    }
+                    n_decode++;
+                }
+
+#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0))
+                if (1u == added)
+#endif
+                {
+                    /* Add NULL to end of string. */
+                    *buf = '\0';
+                    nassigned++;
+                }
+            }
+            else if ((flag & (uint32_t)kSCANF_DestMask) == (uint32_t)kSCANF_DestInt)
+            {
+                n_decode += ScanIgnoreWhiteSpace(&p);
+                s    = p;
+                val  = 0;
+                base = StrFormatScanGetBase(base, s);
+
+                added = StrFormatScanCheckSymbol(p, &neg);
+                n_decode += added;
+                p += added;
+                field_width -= added;
+
+                s = p;
+                if (strlen(p) > field_width)
+                {
+                    char temp[12];
+                    char *tempEnd;
+                    (void)memcpy(temp, p, sizeof(temp) - 1U);
+                    temp[sizeof(temp) - 1U] = '\0';
+                    errno                   = 0;
+                    val                     = (int32_t)strtoul(temp, &tempEnd, (int)base);
+                    if (0 != errno)
+                    {
+                        break;
+                    }
+                    p = p + (tempEnd - temp);
+                }
+                else
+                {
+                    char *tempEnd;
+                    val   = 0;
+                    errno = 0;
+                    val   = (int32_t)strtoul(p, &tempEnd, (int)base);
+                    if (0 != errno)
+                    {
+                        break;
+                    }
+                    p = tempEnd;
+                }
+                n_decode += (uintptr_t)p - (uintptr_t)s;
+
+                val *= neg;
+
+                nassigned += StrFormatScanFillInteger(flag, &args_ptr, val);
+            }
+#if (defined(SCANF_FLOAT_ENABLE) && (SCANF_FLOAT_ENABLE > 0U))
+            else if ((flag & (uint32_t)kSCANF_DestMask) == (uint32_t)kSCANF_DestFloat)
+            {
+                n_decode += ScanIgnoreWhiteSpace(&p);
+                fnum  = 0.0;
+                errno = 0;
+
+                fnum = strtod(p, (char **)&s_temp);
+                s    = s_temp; /* MISRA C-2012 Rule 11.3 */
+
+                /* MISRA C-2012 Rule 22.9 */
+                if (0 != errno)
+                {
+                    break;
+                }
+
+                if ((fnum < HUGE_VAL) && (fnum > -HUGE_VAL))
+                {
+                    n_decode = (uint32_t)n_decode + (uint32_t)s - (uint32_t)p;
+                    p        = s;
+                    nassigned += StrFormatScanFillFloat(flag, &args_ptr, fnum);
+                }
+            }
+#endif /* SCANF_FLOAT_ENABLE */
+            else
+            {
+                break;
+            }
+        }
+    }
+    return (int)nassigned;
+}
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/utilities/fsl_str.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/utilities/fsl_str.h
new file mode 100644
index 000000000..fb6ab5164
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/utilities/fsl_str.h
@@ -0,0 +1,105 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _FSL_STR_H
+#define _FSL_STR_H
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup debugconsole
+ * @{
+ */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0))
+/*! @brief Specification modifier flags for printf. */
+enum _debugconsole_printf_flag
+{
+    kPRINTF_Minus             = 0x01U,  /*!< Minus FLag. */
+    kPRINTF_Plus              = 0x02U,  /*!< Plus Flag. */
+    kPRINTF_Space             = 0x04U,  /*!< Space Flag. */
+    kPRINTF_Zero              = 0x08U,  /*!< Zero Flag. */
+    kPRINTF_Pound             = 0x10U,  /*!< Pound Flag. */
+    kPRINTF_LengthChar        = 0x20U,  /*!< Length: Char Flag. */
+    kPRINTF_LengthShortInt    = 0x40U,  /*!< Length: Short Int Flag. */
+    kPRINTF_LengthLongInt     = 0x80U,  /*!< Length: Long Int Flag. */
+    kPRINTF_LengthLongLongInt = 0x100U, /*!< Length: Long Long Int Flag. */
+};
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+/*! @brief Specification modifier flags for scanf. */
+enum _debugconsole_scanf_flag
+{
+    kSCANF_Suppress   = 0x2U,    /*!< Suppress Flag. */
+    kSCANF_DestMask   = 0x7cU,   /*!< Destination Mask. */
+    kSCANF_DestChar   = 0x4U,    /*!< Destination Char Flag. */
+    kSCANF_DestString = 0x8U,    /*!< Destination String FLag. */
+    kSCANF_DestSet    = 0x10U,   /*!< Destination Set Flag. */
+    kSCANF_DestInt    = 0x20U,   /*!< Destination Int Flag. */
+    kSCANF_DestFloat  = 0x30U,   /*!< Destination Float Flag. */
+    kSCANF_LengthMask = 0x1f00U, /*!< Length Mask Flag. */
+#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0))
+    kSCANF_LengthChar        = 0x100U, /*!< Length Char Flag. */
+    kSCANF_LengthShortInt    = 0x200U, /*!< Length ShortInt Flag. */
+    kSCANF_LengthLongInt     = 0x400U, /*!< Length LongInt Flag. */
+    kSCANF_LengthLongLongInt = 0x800U, /*!< Length LongLongInt Flag. */
+#endif                                 /* SCANF_ADVANCED_ENABLE */
+#if (defined(SCANF_FLOAT_ENABLE) && (SCANF_FLOAT_ENABLE > 0))
+    kSCANF_LengthLongLongDouble = 0x1000U, /*!< Length LongLongDuoble Flag. */
+#endif                                     /*PRINTF_FLOAT_ENABLE */
+    kSCANF_TypeSinged = 0x2000U,           /*!< TypeSinged Flag. */
+};
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @brief A function pointer which is used when format printf log.
+ */
+typedef void (*printfCb)(char *buf, int32_t *indicator, char val, int len);
+
+/*!
+ * @brief This function outputs its parameters according to a formatted string.
+ *
+ * @note I/O is performed by calling given function pointer using following
+ * (*func_ptr)(c);
+ *
+ * @param[in] fmt   Format string for printf.
+ * @param[in] ap  Arguments to printf.
+ * @param[in] buf  pointer to the buffer
+ * @param cb print callbck function pointer
+ *
+ * @return Number of characters to be print
+ */
+int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb);
+
+/*!
+ * @brief Converts an input line of ASCII characters based upon a provided
+ * string format.
+ *
+ * @param[in] line_ptr The input line of ASCII data.
+ * @param[in] format   Format first points to the format string.
+ * @param[in] args_ptr The list of parameters.
+ *
+ * @return Number of input items converted and assigned.
+ * @retval IO_EOF When line_ptr is empty string "".
+ */
+int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* _FSL_STR_H */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Config/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Config/FreeRTOSConfig.h
index aceab43ec..a1348de26 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Config/FreeRTOSConfig.h
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Config/FreeRTOSConfig.h
@@ -43,7 +43,7 @@
  * https://www.FreeRTOS.org/a00110.html

  *----------------------------------------------------------*/

 

-extern uint32_t SystemCoreClock;

+#include "clock_config.h"

 

 /* Cortex M33 port configuration. */

 #define configENABLE_MPU								1

@@ -59,7 +59,7 @@ extern uint32_t SystemCoreClock;
 #define configUSE_16_BIT_TICKS							0 /* Only for 8 and 16-bit hardware. */

 

 /* Constants that describe the hardware and memory usage. */

-#define configCPU_CLOCK_HZ								SystemCoreClock

+#define configCPU_CLOCK_HZ								BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK

 #define configMINIMAL_STACK_SIZE						( ( uint16_t ) 128 )

 #define configMINIMAL_SECURE_STACK_SIZE					( 1024 )

 #define configMAX_TASK_NAME_LEN							( 12 )

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.cproject b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.cproject
index 1b54a4f41..e5ea92f11 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.cproject
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.cproject
@@ -114,6 +114,7 @@
 								<option id="gnu.c.compiler.option.preprocessor.undef.symbol.1876509684" name="Undefined symbols (-U)" superClass="gnu.c.compiler.option.preprocessor.undef.symbol" useByScannerDiscovery="false"/>

 								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="gnu.c.compiler.option.include.paths.88237135" name="Include paths (-I)" superClass="gnu.c.compiler.option.include.paths" useByScannerDiscovery="false" valueType="includePath">

 									<listOptionValue builtIn="false" value="../../Config"/>

+									<listOptionValue builtIn="false" value="../../Secure"/>

 									<listOptionValue builtIn="false" value="../../../../NXP_Code"/>

 									<listOptionValue builtIn="false" value="../../../../NXP_Code/board"/>

 									<listOptionValue builtIn="false" value="../../../../NXP_Code/source"/>

@@ -126,6 +127,8 @@
 									<listOptionValue builtIn="false" value="../../../../NXP_Code/component/lists"/>

 									<listOptionValue builtIn="false" value="../../../../../../Demo/Common/ARMv8M/mpu_demo"/>

 									<listOptionValue builtIn="false" value="../../../../../../Demo/Common/ARMv8M/tz_demo"/>

+									<listOptionValue builtIn="false" value="../../../../../../Demo/Common/ARMv8M/reg_tests/GCC/ARM_CM33/non_secure"/>

+									<listOptionValue builtIn="false" value="../../../../../../Demo/Common/ARMv8M/reg_tests/GCC/ARM_CM33/secure"/>

 									<listOptionValue builtIn="false" value="../../../../../../Source/include"/>

 									<listOptionValue builtIn="false" value="../../../../../../Source/portable/GCC/ARM_CM33/secure"/>

 									<listOptionValue builtIn="false" value="../../../../../../Source/portable/GCC/ARM_CM33/non_secure"/>

@@ -267,7 +270,7 @@
 								<option id="com.crt.advproject.link.cpp.inimplib.742756957" name="Input Secure Gateway Import Library" superClass="com.crt.advproject.link.cpp.inimplib"/>

 							</tool>

 							<tool id="com.crt.advproject.link.exe.debug.1811316497" name="MCU Linker" superClass="com.crt.advproject.link.exe.debug">

-								<option id="com.crt.advproject.link.gcc.hdrlib.339215003" name="Library" superClass="com.crt.advproject.link.gcc.hdrlib" useByScannerDiscovery="false" value="com.crt.advproject.gcc.link.hdrlib.newlibnano.semihost" valueType="enumerated"/>

+								<option id="com.crt.advproject.link.gcc.hdrlib.339215003" name="Library" superClass="com.crt.advproject.link.gcc.hdrlib" useByScannerDiscovery="false" value="com.crt.advproject.gcc.link.hdrlib.newlibnano.nohost" valueType="enumerated"/>

 								<option id="com.crt.advproject.link.fpu.1049328981" name="Floating point" superClass="com.crt.advproject.link.fpu" useByScannerDiscovery="false" value="com.crt.advproject.link.fpu.fpv5sp.hard" valueType="enumerated"/>

 								<option id="com.crt.advproject.link.thumb.1038394022" name="Thumb mode" superClass="com.crt.advproject.link.thumb" useByScannerDiscovery="false" value="true" valueType="boolean"/>

 								<option id="com.crt.advproject.link.memory.load.image.1608049889" name="Plain load image" superClass="com.crt.advproject.link.memory.load.image" useByScannerDiscovery="false" value="false;" valueType="string"/>

@@ -283,12 +286,8 @@
 								<option id="gnu.c.link.option.nostdlibs.2064853265" name="No startup or default libs (-nostdlib)" superClass="gnu.c.link.option.nostdlibs" useByScannerDiscovery="false" value="true" valueType="boolean"/>

 								<option id="gnu.c.link.option.strip.1473230449" name="Omit all symbol information (-s)" superClass="gnu.c.link.option.strip" useByScannerDiscovery="false"/>

 								<option id="gnu.c.link.option.noshared.754737421" name="No shared libraries (-static)" superClass="gnu.c.link.option.noshared" useByScannerDiscovery="false"/>

-								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="gnu.c.link.option.libs.2063466722" name="Libraries (-l)" superClass="gnu.c.link.option.libs" useByScannerDiscovery="false" valueType="libs">

-									<listOptionValue builtIn="false" value="power_hardabi"/>

-								</option>

-								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="gnu.c.link.option.paths.826148184" name="Library search path (-L)" superClass="gnu.c.link.option.paths" useByScannerDiscovery="false" valueType="libPaths">

-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/NXP_Code/libs}&quot;"/>

-								</option>

+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="gnu.c.link.option.libs.2063466722" name="Libraries (-l)" superClass="gnu.c.link.option.libs" useByScannerDiscovery="false" valueType="libs"/>

+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="gnu.c.link.option.paths.826148184" name="Library search path (-L)" superClass="gnu.c.link.option.paths" useByScannerDiscovery="false" valueType="libPaths"/>

 								<option id="gnu.c.link.option.ldflags.625929291" name="Linker flags" superClass="gnu.c.link.option.ldflags" useByScannerDiscovery="false"/>

 								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="gnu.c.link.option.other.683921352" name="Other options (-Xlinker [option])" superClass="gnu.c.link.option.other" useByScannerDiscovery="false" valueType="stringList">

 									<listOptionValue builtIn="false" value="-Map=&quot;${BuildArtifactFileBaseName}.map&quot;"/>

@@ -344,11 +343,12 @@
 						</toolChain>

 					</folderInfo>

 					<sourceEntries>

-						<entry flags="LOCAL|VALUE_WORKSPACE_PATH" kind="sourcePath" name="Config"/>

-						<entry flags="LOCAL|VALUE_WORKSPACE_PATH" kind="sourcePath" name="Demos"/>

-						<entry flags="LOCAL|VALUE_WORKSPACE_PATH" kind="sourcePath" name="FreeRTOS"/>

-						<entry flags="LOCAL|VALUE_WORKSPACE_PATH" kind="sourcePath" name="NXP_Code"/>

-						<entry flags="LOCAL|VALUE_WORKSPACE_PATH" kind="sourcePath" name="User"/>

+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Config"/>

+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Demos"/>

+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="FreeRTOS"/>

+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="NXP_Code"/>

+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="User"/>

+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="reg_tests"/>

 					</sourceEntries>

 				</configuration>

 			</storageModule>

@@ -405,6 +405,10 @@
 &lt;/infoList&gt;&#13;

 &lt;/TargetConfig&gt;</projectStorage>

 	</storageModule>

-	<storageModule moduleId="refreshScope"/>

+	<storageModule moduleId="refreshScope" versionNumber="2">

+		<configuration configurationName="Debug">

+			<resource resourceType="PROJECT" workspacePath="/FreeRTOSDemo_ns"/>

+		</configuration>

+	</storageModule>

 	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>

 </cproject>
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.project b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.project
index 9fed40c07..5373cd7ec 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.project
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.project
@@ -58,6 +58,11 @@
 			<locationURI>virtual:/virtual</locationURI>

 		</link>

 		<link>

+			<name>reg_tests</name>

+			<type>2</type>

+			<locationURI>DEMO_ROOT/Common/ARMv8M/reg_tests</locationURI>

+		</link>

+		<link>

 			<name>Demos/mpu_demo.c</name>

 			<type>1</type>

 			<locationURI>PARENT-4-PROJECT_LOC/Common/ARMv8M/mpu_demo/mpu_demo.c</locationURI>

@@ -82,10 +87,15 @@
 			<type>1</type>

 			<locationURI>PROJECT_LOC/main_ns.c</locationURI>

 		</link>

+		<link>

+			<name>User/res_tests.c</name>

+			<type>1</type>

+			<locationURI>PROJECT_LOC/res_tests.c</locationURI>

+		</link>

 	</linkedResources>

 	<filteredResources>

 		<filter>

-			<id>1557021723682</id>

+			<id>1681724631111</id>

 			<name></name>

 			<type>6</type>

 			<matcher>

@@ -94,7 +104,7 @@
 			</matcher>

 		</filter>

 		<filter>

-			<id>1557021723695</id>

+			<id>1681724631147</id>

 			<name></name>

 			<type>6</type>

 			<matcher>

@@ -103,6 +113,15 @@
 			</matcher>

 		</filter>

 		<filter>

+			<id>1681721788469</id>

+			<name>reg_tests</name>

+			<type>9</type>

+			<matcher>

+				<id>org.eclipse.ui.ide.multiFilter</id>

+				<arguments>1.0-name-matches-false-false-GCC</arguments>

+			</matcher>

+		</filter>

+		<filter>

 			<id>1554600764705</id>

 			<name>FreeRTOS/portable</name>

 			<type>9</type>

@@ -139,6 +158,15 @@
 			</matcher>

 		</filter>

 		<filter>

+			<id>1681721804811</id>

+			<name>reg_tests/GCC</name>

+			<type>9</type>

+			<matcher>

+				<id>org.eclipse.ui.ide.multiFilter</id>

+				<arguments>1.0-name-matches-false-false-ARM_CM33</arguments>

+			</matcher>

+		</filter>

+		<filter>

 			<id>1553579192808</id>

 			<name>FreeRTOS/portable/GCC</name>

 			<type>9</type>

@@ -157,6 +185,15 @@
 			</matcher>

 		</filter>

 		<filter>

+			<id>1681721822064</id>

+			<name>reg_tests/GCC/ARM_CM33</name>

+			<type>9</type>

+			<matcher>

+				<id>org.eclipse.ui.ide.multiFilter</id>

+				<arguments>1.0-name-matches-false-false-non_secure</arguments>

+			</matcher>

+		</filter>

+		<filter>

 			<id>1553579213167</id>

 			<name>FreeRTOS/portable/GCC/ARM_CM33</name>

 			<type>9</type>

@@ -166,4 +203,10 @@
 			</matcher>

 		</filter>

 	</filteredResources>

+	<variableList>

+		<variable>

+			<name>DEMO_ROOT</name>

+			<value>$%7BPARENT-4-PROJECT_LOC%7D</value>

+		</variable>

+	</variableList>

 </projectDescription>

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/main_ns.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/main_ns.c
index 8dd3d3c10..7967a3c68 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/main_ns.c
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/main_ns.c
@@ -34,10 +34,12 @@
 #include "pin_mux.h"

 #include "board.h"

 #include "clock_config.h"

+#include "fsl_power.h"

 

 /* Demo includes. */

 #include "tz_demo.h"

 #include "mpu_demo.h"

+#include "reg_tests.h"

 /*-----------------------------------------------------------*/

 

 /**

@@ -46,6 +48,11 @@
 static void prvCreateTasks( void );

 

 /**

+ * @brief Setup hardware.

+ */

+static void prvSetupHardware( void );

+

+/**

  * @brief Application-specific implementation of the SystemInit() weak

  * function.

  */

@@ -66,6 +73,9 @@ void MemManage_Handler( void ) __attribute__ ( ( naked ) );
 /* Non-Secure main. */

 int main( void )

 {

+	/* Setup hardware. */

+	prvSetupHardware();

+

 	/* Create tasks. */

 	prvCreateTasks();

 

@@ -90,6 +100,15 @@ static void prvCreateTasks( void )
 	/* Create tasks for the TZ Demo. */

 	vStartTZDemo();

 

+	/* Create tasks for reg tests. */

+	vStartRegTests();

+}

+/*-----------------------------------------------------------*/

+

+static void prvSetupHardware( void )

+{

+	/* Set BOD VBAT level to 1.65V. */

+	POWER_SetBodVbatLevel( kPOWER_BodVbatLevel1650mv, kPOWER_BodHystLevel50mv, false );

 }

 /*-----------------------------------------------------------*/

 

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/reg_tests.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/reg_tests.c
new file mode 100644
index 000000000..831ec6479
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/reg_tests.c
@@ -0,0 +1,446 @@
+/*
+ * FreeRTOS V202212.00
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Reg test includes. */
+#include "reg_tests.h"
+#include "reg_test_asm.h"
+#include "secure_reg_test_asm.h"
+
+/* Printf includes. */
+#include "nsc_printf.h"
+
+/*
+ * Functions that implement reg test tasks.
+ */
+static void prvRegTest1_Task( void * pvParameters );
+static void prvRegTest2_Task( void * pvParameters );
+static void prvRegTest3_Task( void * pvParameters );
+static void prvRegTest4_Task( void * pvParameters );
+static void prvRegTest_Secure_Task( void * pvParameters );
+static void prvRegTest_NonSecureCallback_Task( void * pvParameters );
+/*
+ * Check task periodically checks that reg tests tasks
+ * are running fine.
+ */
+static void prvCheckTask( void * pvParameters );
+/*-----------------------------------------------------------*/
+
+/*
+ * Priority of the check task.
+ */
+#define CHECK_TASK_PRIORITY                 ( configMAX_PRIORITIES - 1 )
+
+/*
+ * Frequency of check task.
+ */
+#define NO_ERROR_CHECK_TASK_PERIOD          ( pdMS_TO_TICKS( 5000UL ) )
+#define ERROR_CHECK_TASK_PERIOD             ( pdMS_TO_TICKS( 200UL ) )
+
+/*
+ * Parameters passed to reg test tasks.
+ */
+#define REG_TEST_1_TASK_PARAMETER                   ( ( void * ) 0x12345678 )
+#define REG_TEST_2_TASK_PARAMETER                   ( ( void * ) 0x87654321 )
+#define REG_TEST_3_TASK_PARAMETER                   ( ( void * ) 0x12348765 )
+#define REG_TEST_4_TASK_PARAMETER                   ( ( void * ) 0x43215678 )
+#define REG_TEST_SECURE_TASK_PARAMETER              ( ( void * ) 0x1234ABCD )
+#define REG_TEST_NON_SECURE_CALLBACK_TASK_PARAMETER ( ( void * ) 0xABCD1234 )
+/*-----------------------------------------------------------*/
+
+/*
+ * The following variables are used to communicate the status of the register
+ * test tasks to the check task. If the variables keep incrementing, then the
+ * register test tasks have not discovered any errors. If a variable stops
+ * incrementing, then an error has been found.
+ */
+volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;
+volatile unsigned long ulRegTest3LoopCounter = 0UL, ulRegTest4LoopCounter = 0UL;
+volatile unsigned long ulRegTestSecureLoopCounter = 0UL;
+volatile unsigned long ulRegTestNonSecureCallbackLoopCounter = 0UL;
+
+/**
+ * Counter to keep a count of how may times the check task loop has detected
+ * error.
+ */
+volatile unsigned long ulCheckTaskLoops = 0UL;
+/*-----------------------------------------------------------*/
+
+void vStartRegTests( void )
+{
+static StackType_t xRegTest1TaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) );
+static StackType_t xRegTest2TaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) );
+static StackType_t xRegTest3TaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) );
+static StackType_t xRegTest4TaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) );
+static StackType_t xRegTestSecureTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) );
+static StackType_t xRegTestNonSecureCallbackTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) );
+static StackType_t xCheckTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) );
+
+TaskParameters_t xRegTest1TaskParameters =
+{
+    .pvTaskCode      = prvRegTest1_Task,
+    .pcName          = "RegTest1",
+    .usStackDepth    = configMINIMAL_STACK_SIZE,
+    .pvParameters    = REG_TEST_1_TASK_PARAMETER,
+    .uxPriority      = tskIDLE_PRIORITY | portPRIVILEGE_BIT,
+    .puxStackBuffer  = xRegTest1TaskStack,
+    .xRegions        =  {
+                            { 0, 0, 0 },
+                            { 0, 0, 0 },
+                            { 0, 0, 0 }
+                        }
+};
+TaskParameters_t xRegTest2TaskParameters =
+{
+    .pvTaskCode      = prvRegTest2_Task,
+    .pcName          = "RegTest2",
+    .usStackDepth    = configMINIMAL_STACK_SIZE,
+    .pvParameters    = REG_TEST_2_TASK_PARAMETER,
+    .uxPriority      = tskIDLE_PRIORITY | portPRIVILEGE_BIT,
+    .puxStackBuffer  = xRegTest2TaskStack,
+    .xRegions        =  {
+                            { 0, 0, 0 },
+                            { 0, 0, 0 },
+                            { 0, 0, 0 }
+                        }
+};
+TaskParameters_t xRegTest3TaskParameters =
+{
+    .pvTaskCode      = prvRegTest3_Task,
+    .pcName          = "RegTest3",
+    .usStackDepth    = configMINIMAL_STACK_SIZE,
+    .pvParameters    = REG_TEST_3_TASK_PARAMETER,
+    .uxPriority      = tskIDLE_PRIORITY | portPRIVILEGE_BIT,
+    .puxStackBuffer  = xRegTest3TaskStack,
+    .xRegions        =  {
+                            { 0, 0, 0 },
+                            { 0, 0, 0 },
+                            { 0, 0, 0 }
+                        }
+};
+TaskParameters_t xRegTest4TaskParameters =
+{
+    .pvTaskCode      = prvRegTest4_Task,
+    .pcName          = "RegTest4",
+    .usStackDepth    = configMINIMAL_STACK_SIZE,
+    .pvParameters    = REG_TEST_4_TASK_PARAMETER,
+    .uxPriority      = tskIDLE_PRIORITY | portPRIVILEGE_BIT,
+    .puxStackBuffer  = xRegTest4TaskStack,
+    .xRegions        =  {
+                            { 0, 0, 0 },
+                            { 0, 0, 0 },
+                            { 0, 0, 0 }
+                        }
+};
+TaskParameters_t xRegTestSecureTaskParameters =
+{
+    .pvTaskCode      = prvRegTest_Secure_Task,
+    .pcName          = "RegTestSecure",
+    .usStackDepth    = configMINIMAL_STACK_SIZE,
+    .pvParameters    = REG_TEST_SECURE_TASK_PARAMETER,
+    .uxPriority      = tskIDLE_PRIORITY | portPRIVILEGE_BIT,
+    .puxStackBuffer  = xRegTestSecureTaskStack,
+    .xRegions        =  {
+                            { 0, 0, 0 },
+                            { 0, 0, 0 },
+                            { 0, 0, 0 }
+                        }
+};
+TaskParameters_t xRegTestNonSecureCallbackTaskParameters =
+{
+    .pvTaskCode      = prvRegTest_NonSecureCallback_Task,
+    .pcName          = "RegTestNonSecureCallback",
+    .usStackDepth    = configMINIMAL_STACK_SIZE,
+    .pvParameters    = REG_TEST_NON_SECURE_CALLBACK_TASK_PARAMETER,
+    .uxPriority      = tskIDLE_PRIORITY | portPRIVILEGE_BIT,
+    .puxStackBuffer  = xRegTestNonSecureCallbackTaskStack,
+    .xRegions        =  {
+                            { 0, 0, 0 },
+                            { 0, 0, 0 },
+                            { 0, 0, 0 }
+                        }
+};
+
+TaskParameters_t xCheckTaskParameters =
+{
+    .pvTaskCode      = prvCheckTask,
+    .pcName          = "Check",
+    .usStackDepth    = configMINIMAL_STACK_SIZE,
+    .pvParameters    = NULL,
+    .uxPriority      = ( CHECK_TASK_PRIORITY | portPRIVILEGE_BIT ),
+    .puxStackBuffer  = xCheckTaskStack,
+    .xRegions        =  {
+                            { 0, 0, 0 },
+                            { 0, 0, 0 },
+                            { 0, 0, 0 }
+                        }
+};
+
+    xTaskCreateRestricted( &( xRegTest1TaskParameters ), NULL );
+    xTaskCreateRestricted( &( xRegTest2TaskParameters ), NULL );
+    xTaskCreateRestricted( &( xRegTest3TaskParameters ), NULL );
+    xTaskCreateRestricted( &( xRegTest4TaskParameters ), NULL );
+    xTaskCreateRestricted( &( xRegTestSecureTaskParameters ), NULL );
+    xTaskCreateRestricted( &( xRegTestNonSecureCallbackTaskParameters ), NULL );
+    xTaskCreateRestricted( &( xCheckTaskParameters ), NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvRegTest1_Task( void * pvParameters )
+{
+    /* Although the reg tests are written in assembly, its entry
+     * point is written in C for convenience of checking that the
+     * task parameter is being passed in correctly. */
+    if( pvParameters == REG_TEST_1_TASK_PARAMETER )
+    {
+        /* Start the part of the test that is written in assembler. */
+        vRegTest1Asm_NonSecure();
+    }
+
+    /* The following line will only execute if the task parameter
+     * is found to be incorrect. The check task will detect that
+     * the reg test loop counter is not being incremented and flag
+     * an error. */
+    vTaskDelete( NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvRegTest2_Task( void * pvParameters )
+{
+    /* Although the reg tests are written in assembly, its entry
+     * point is written in C for convenience of checking that the
+     * task parameter is being passed in correctly. */
+    if( pvParameters == REG_TEST_2_TASK_PARAMETER )
+    {
+        /* Start the part of the test that is written in assembler. */
+        vRegTest2Asm_NonSecure();
+    }
+
+    /* The following line will only execute if the task parameter
+     * is found to be incorrect. The check task will detect that
+     * the reg test loop counter is not being incremented and flag
+     * an error. */
+    vTaskDelete( NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvRegTest3_Task( void * pvParameters )
+{
+    /* Although the reg tests are written in assembly, its entry
+     * point is written in C for convenience of checking that the
+     * task parameter is being passed in correctly. */
+    if( pvParameters == REG_TEST_3_TASK_PARAMETER )
+    {
+        /* Start the part of the test that is written in assembler. */
+        vRegTest3Asm_NonSecure();
+    }
+
+    /* The following line will only execute if the task parameter
+     * is found to be incorrect. The check task will detect that
+     * the reg test loop counter is not being incremented and flag
+     * an error. */
+    vTaskDelete( NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvRegTest4_Task( void * pvParameters )
+{
+    /* Although the reg tests are written in assembly, its entry
+     * point is written in C for convenience of checking that the
+     * task parameter is being passed in correctly. */
+    if( pvParameters == REG_TEST_4_TASK_PARAMETER )
+    {
+        /* Start the part of the test that is written in assembler. */
+        vRegTest4Asm_NonSecure();
+    }
+
+    /* The following line will only execute if the task parameter
+     * is found to be incorrect. The check task will detect that
+     * the reg test loop counter is not being incremented and flag
+     * an error. */
+    vTaskDelete( NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvRegTest_Secure_Task( void * pvParameters )
+{
+    /* This task is going to call secure side functions. */
+    portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE );
+
+    /* Although the reg tests are written in assembly, its entry
+     * point is written in C for convenience of checking that the
+     * task parameter is being passed in correctly. */
+    if( pvParameters == REG_TEST_SECURE_TASK_PARAMETER )
+    {
+        for( ;; )
+        {
+            /* Call the secure side function. This function populates registers
+             * with known values, then forces a context switch while on the
+             * secure side and then verifies that the contents of the registers
+             * are intact. This ensure that the context restoring mechanism
+             * works properly when the interrupted task was in the middle of a
+             * call to a secure side function. */
+            vRegTestAsm_Secure();
+
+            ulRegTestSecureLoopCounter += 1;
+        }
+    }
+
+    /* The following line will only execute if the task parameter
+     * is found to be incorrect. The check task will detect that
+     * the reg test loop counter is not being incremented and flag
+     * an error. */
+    vTaskDelete( NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvRegTest_NonSecureCallback_Task( void * pvParameters )
+{
+    /* This task is going to call secure side functions. */
+    portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE );
+
+    /* Although the reg tests are written in assembly, its entry
+     * point is written in C for convenience of checking that the
+     * task parameter is being passed in correctly. */
+    if( pvParameters == REG_TEST_NON_SECURE_CALLBACK_TASK_PARAMETER )
+    {
+        for( ;; )
+        {
+            /* Call the secure side function. This function calls the provided
+             * non-secure callback which in-turn populates registers with
+             * known values, then forces a context switch while on the
+             * non-secure side and then verifies that the contents of the
+             * registers are intact. This ensure that the context restoring
+             * mechanism works properly when the interrupted task was in the
+             * middle of a non-secure callback from the secure side. */
+            vRegTest_NonSecureCallback( vRegTestAsm_NonSecureCallback );
+
+            ulRegTestNonSecureCallbackLoopCounter += 1;
+        }
+    }
+
+    /* The following line will only execute if the task parameter
+     * is found to be incorrect. The check task will detect that
+     * the reg test loop counter is not being incremented and flag
+     * an error. */
+    vTaskDelete( NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckTask( void * pvParameters )
+{
+TickType_t xDelayPeriod = NO_ERROR_CHECK_TASK_PERIOD;
+TickType_t xLastExecutionTime;
+unsigned long ulErrorFound = pdFALSE;
+static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;
+static unsigned long ulLastRegTest3Value = 0, ulLastRegTest4Value = 0;
+static unsigned long ulLastRegTestSecureValue = 0, ulLastRegTestNonSecureCallbackValue = 0;
+
+    /* This task is going to call secure side functions for
+     * printing messages. */
+    portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE );
+
+    /* Just to stop compiler warnings. */
+    ( void ) pvParameters;
+
+    /* Initialize xLastExecutionTime so the first call to vTaskDelayUntil()
+     * works correctly. */
+    xLastExecutionTime = xTaskGetTickCount();
+
+    /* Cycle for ever, delaying then checking all the other tasks are still
+     * operating without error.  The onboard LED is toggled on each iteration.
+     * If an error is detected then the delay period is decreased from
+     * mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD.  This has
+     * the effect of increasing the rate at which the onboard LED toggles, and
+     * in so doing gives visual feedback of the system status. */
+    for( ;; )
+    {
+        /* Delay until it is time to execute again. */
+        vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod );
+
+        /* Check that the register test 1 task is still running. */
+        if( ulLastRegTest1Value == ulRegTest1LoopCounter )
+        {
+            ulErrorFound |= 1UL << 0UL;
+        }
+        ulLastRegTest1Value = ulRegTest1LoopCounter;
+
+        /* Check that the register test 2 task is still running. */
+        if( ulLastRegTest2Value == ulRegTest2LoopCounter )
+        {
+            ulErrorFound |= 1UL << 1UL;
+        }
+        ulLastRegTest2Value = ulRegTest2LoopCounter;
+
+        /* Check that the register test 3 task is still running. */
+        if( ulLastRegTest3Value == ulRegTest3LoopCounter )
+        {
+            ulErrorFound |= 1UL << 2UL;
+        }
+        ulLastRegTest3Value = ulRegTest3LoopCounter;
+
+        /* Check that the register test 4 task is still running. */
+        if( ulLastRegTest4Value == ulRegTest4LoopCounter )
+        {
+            ulErrorFound |= 1UL << 3UL;
+        }
+        ulLastRegTest4Value = ulRegTest4LoopCounter;
+
+        /* Check that the register test secure task is still running. */
+        if( ulLastRegTestSecureValue == ulRegTestSecureLoopCounter )
+        {
+            ulErrorFound |= 1UL << 4UL;
+        }
+        ulLastRegTestSecureValue = ulRegTestSecureLoopCounter;
+
+        /* Check that the register test non-secure callback task is
+         * still running. */
+        if( ulLastRegTestNonSecureCallbackValue == ulRegTestNonSecureCallbackLoopCounter )
+        {
+            ulErrorFound |= 1UL << 5UL;
+        }
+        ulLastRegTestNonSecureCallbackValue = ulRegTestNonSecureCallbackLoopCounter;
+
+        if( ulErrorFound != pdFALSE )
+        {
+            /* An error has been detected in one of the tasks. */
+            xDelayPeriod = ERROR_CHECK_TASK_PERIOD;
+
+            NSC_Printf( "ERROR detected!\r\n" );
+
+            /* Increment error detection count. */
+            ulCheckTaskLoops++;
+        }
+        else
+        {
+            NSC_Printf( "No errors.\r\n" );
+        }
+    }
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/reg_tests.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/reg_tests.h
new file mode 100644
index 000000000..0837aad72
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/reg_tests.h
@@ -0,0 +1,35 @@
+/*
+ * FreeRTOS V202212.00
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef REG_TESTS_H
+#define REG_TESTS_H
+
+/**
+ * @brief Creates all the tasks for reg tests.
+ */
+void vStartRegTests( void );
+
+#endif /* REG_TESTS_H */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/.cproject b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/.cproject
index 29dede49e..349cc5d2a 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/.cproject
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/.cproject
@@ -102,12 +102,12 @@
 									<listOptionValue builtIn="false" value="MCUXPRESSO_SDK"/>

 									<listOptionValue builtIn="false" value="CPU_LPC55S69JBD100"/>

 									<listOptionValue builtIn="false" value="CPU_LPC55S69JBD100_cm33"/>

-									<listOptionValue builtIn="false" value="SDK_DEBUGCONSOLE=1"/>

 									<listOptionValue builtIn="false" value="CR_INTEGER_PRINTF"/>

 									<listOptionValue builtIn="false" value="__MCUXPRESSO"/>

 									<listOptionValue builtIn="false" value="__USE_CMSIS"/>

 									<listOptionValue builtIn="false" value="DEBUG"/>

 									<listOptionValue builtIn="false" value="__NEWLIB__"/>

+									<listOptionValue builtIn="false" value="SDK_DEBUGCONSOLE=1"/>

 								</option>

 								<option id="gnu.c.compiler.option.preprocessor.undef.symbol.904667201" name="Undefined symbols (-U)" superClass="gnu.c.compiler.option.preprocessor.undef.symbol" useByScannerDiscovery="false"/>

 								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="gnu.c.compiler.option.include.paths.927386374" name="Include paths (-I)" superClass="gnu.c.compiler.option.include.paths" useByScannerDiscovery="false" valueType="includePath">

@@ -277,12 +277,8 @@
 								<option id="gnu.c.link.option.nostdlibs.1676046096" name="No startup or default libs (-nostdlib)" superClass="gnu.c.link.option.nostdlibs" useByScannerDiscovery="false" value="true" valueType="boolean"/>

 								<option id="gnu.c.link.option.strip.1271951104" name="Omit all symbol information (-s)" superClass="gnu.c.link.option.strip" useByScannerDiscovery="false"/>

 								<option id="gnu.c.link.option.noshared.257939592" name="No shared libraries (-static)" superClass="gnu.c.link.option.noshared" useByScannerDiscovery="false"/>

-								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="gnu.c.link.option.libs.919983000" name="Libraries (-l)" superClass="gnu.c.link.option.libs" useByScannerDiscovery="false" valueType="libs">

-									<listOptionValue builtIn="false" value="power_hardabi_s"/>

-								</option>

-								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="gnu.c.link.option.paths.2126623716" name="Library search path (-L)" superClass="gnu.c.link.option.paths" useByScannerDiscovery="false" valueType="libPaths">

-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/NXP_Code/libs}&quot;"/>

-								</option>

+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="gnu.c.link.option.libs.919983000" name="Libraries (-l)" superClass="gnu.c.link.option.libs" useByScannerDiscovery="false" valueType="libs"/>

+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="gnu.c.link.option.paths.2126623716" name="Library search path (-L)" superClass="gnu.c.link.option.paths" useByScannerDiscovery="false" valueType="libPaths"/>

 								<option id="gnu.c.link.option.ldflags.778846229" name="Linker flags" superClass="gnu.c.link.option.ldflags" useByScannerDiscovery="false"/>

 								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="gnu.c.link.option.other.1387107219" name="Other options (-Xlinker [option])" superClass="gnu.c.link.option.other" useByScannerDiscovery="false" valueType="stringList">

 									<listOptionValue builtIn="false" value="-Map=&quot;${BuildArtifactFileBaseName}.map&quot;"/>

@@ -308,7 +304,7 @@
 								<option id="com.crt.advproject.link.crpenable.797389321" name="Enable automatic placement of Code Read Protection field in image" superClass="com.crt.advproject.link.crpenable" useByScannerDiscovery="false"/>

 								<option id="com.crt.advproject.link.flashconfigenable.908777484" name="Enable automatic placement of Flash Configuration field in image" superClass="com.crt.advproject.link.flashconfigenable" useByScannerDiscovery="false" value="true" valueType="boolean"/>

 								<option id="com.crt.advproject.link.ecrp.1277431163" name="Enhanced CRP" superClass="com.crt.advproject.link.ecrp" useByScannerDiscovery="false"/>

-								<option id="com.crt.advproject.link.gcc.hdrlib.2097369956" name="Library" superClass="com.crt.advproject.link.gcc.hdrlib" useByScannerDiscovery="false" value="com.crt.advproject.gcc.link.hdrlib.newlibnano.semihost" valueType="enumerated"/>

+								<option id="com.crt.advproject.link.gcc.hdrlib.2097369956" name="Library" superClass="com.crt.advproject.link.gcc.hdrlib" useByScannerDiscovery="false" value="com.crt.advproject.gcc.link.hdrlib.newlibnano.nohost" valueType="enumerated"/>

 								<option id="com.crt.advproject.link.gcc.nanofloat.1164185150" name="Enable printf float " superClass="com.crt.advproject.link.gcc.nanofloat" useByScannerDiscovery="false"/>

 								<option id="com.crt.advproject.link.gcc.nanofloat.scanf.603353586" name="Enable scanf float " superClass="com.crt.advproject.link.gcc.nanofloat.scanf" useByScannerDiscovery="false"/>

 								<option id="com.crt.advproject.link.toram.266119221" name="Link application to RAM" superClass="com.crt.advproject.link.toram" useByScannerDiscovery="false"/>

@@ -337,14 +333,25 @@
 							</tool>

 						</toolChain>

 					</folderInfo>

+					<folderInfo id="com.crt.advproject.config.exe.debug.650465968.1580633237" name="/" resourcePath="reg_tests">

+						<toolChain id="com.crt.advproject.toolchain.exe.debug.1643158192" name="NXP MCU Tools" superClass="com.crt.advproject.toolchain.exe.debug" unusedChildren="">

+							<tool id="com.crt.advproject.cpp.exe.debug.1303225074" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.debug.248036726"/>

+							<tool id="com.crt.advproject.gcc.exe.debug.806639634" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.debug.1827685058"/>

+							<tool id="com.crt.advproject.gas.exe.debug.2004350830" name="MCU Assembler" superClass="com.crt.advproject.gas.exe.debug.355931849"/>

+							<tool id="com.crt.advproject.link.cpp.exe.debug.141362876" name="MCU C++ Linker" superClass="com.crt.advproject.link.cpp.exe.debug.767850316"/>

+							<tool id="com.crt.advproject.link.exe.debug.558086384" name="MCU Linker" superClass="com.crt.advproject.link.exe.debug.1425769789"/>

+							<tool id="com.crt.advproject.tool.debug.debug.404468304" name="MCU Debugger" superClass="com.crt.advproject.tool.debug.debug.1632770985"/>

+						</toolChain>

+					</folderInfo>

 					<sourceEntries>

-						<entry flags="LOCAL|VALUE_WORKSPACE_PATH" kind="sourcePath" name="Config"/>

-						<entry flags="LOCAL|VALUE_WORKSPACE_PATH" kind="sourcePath" name="NSCFunctions"/>

-						<entry flags="LOCAL|VALUE_WORKSPACE_PATH" kind="sourcePath" name="NXP_Code"/>

-						<entry flags="LOCAL|VALUE_WORKSPACE_PATH" kind="sourcePath" name="SecureContext"/>

-						<entry flags="LOCAL|VALUE_WORKSPACE_PATH" kind="sourcePath" name="SecureHeap"/>

-						<entry flags="LOCAL|VALUE_WORKSPACE_PATH" kind="sourcePath" name="SecureInit"/>

-						<entry flags="LOCAL|VALUE_WORKSPACE_PATH" kind="sourcePath" name="User"/>

+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Config"/>

+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="NSCFunctions"/>

+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="NXP_Code"/>

+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="SecureContext"/>

+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="SecureHeap"/>

+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="SecureInit"/>

+						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="User"/>

+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="reg_tests"/>

 					</sourceEntries>

 				</configuration>

 			</storageModule>

@@ -367,7 +374,7 @@
 	<storageModule moduleId="com.nxp.mcuxpresso.core.datamodels">

 		<sdkName>SDK_2.x_LPCXpresso55S69</sdkName>

 		<sdkExample>FreeRTOSDemo_s</sdkExample>

-		<sdkVersion>2.10.0</sdkVersion>

+		<sdkVersion>2.13.1</sdkVersion>

 		<sdkComponents>platform.drivers.clock.LPC55S69;platform.drivers.power_s.LPC55S69;platform.drivers.common.LPC55S69;utility.debug_console_lite.LPC55S69;platform.utilities.assert_lite.LPC55S69;platform.drivers.lpc_iocon.LPC55S69;platform.drivers.reset.LPC55S69;platform.devices.LPC55S69_CMSIS.LPC55S69;platform.devices.LPC55S69_startup.LPC55S69;platform.drivers.flexcomm_usart.LPC55S69;platform.drivers.flexcomm.LPC55S69;platform.drivers.lpc_gpio.LPC55S69;component.usart_adapter.LPC55S69;component.lists.LPC55S69;CMSIS_Include_core_cm.LPC55S69;platform.utilities.misc_utilities.LPC55S69;platform.devices.LPC55S69_system.LPC55S69;FreeRTOSDemo_s;</sdkComponents>

 		<boardId>lpcxpresso55s69</boardId>

 		<package>LPC55S69JBD100</package>

@@ -384,7 +391,7 @@
 &lt;name&gt;LPC55S69&lt;/name&gt;&#13;

 &lt;family&gt;LPC55S6x&lt;/family&gt;&#13;

 &lt;vendor&gt;NXP&lt;/vendor&gt;&#13;

-&lt;memory can_program="true" id="Flash" is_ro="true" size="608" type="Flash"/&gt;&#13;

+&lt;memory can_program="true" id="Flash" is_ro="true" size="630" type="Flash"/&gt;&#13;

 &lt;memory id="RAM" size="304" type="RAM"/&gt;&#13;

 &lt;memoryInstance derived_from="Flash" driver="LPC55xx_S.cfx" edited="true" id="PROGRAM_FLASH" location="0x10000000" size="0xfe00"/&gt;&#13;

 &lt;memoryInstance derived_from="Flash" edited="true" id="SG_veneer_table" location="0x1000fe00" size="0x200"/&gt;&#13;

@@ -402,6 +409,10 @@
 &lt;/infoList&gt;&#13;

 &lt;/TargetConfig&gt;</projectStorage>

 	</storageModule>

-	<storageModule moduleId="refreshScope"/>

+	<storageModule moduleId="refreshScope" versionNumber="2">

+		<configuration configurationName="Debug">

+			<resource resourceType="PROJECT" workspacePath="/FreeRTOSDemo_s"/>

+		</configuration>

+	</storageModule>

 	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>

 </cproject>
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/.project b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/.project
index fe69cfc62..b4c624902 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/.project
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/.project
@@ -67,6 +67,11 @@
 			<locationURI>virtual:/virtual</locationURI>

 		</link>

 		<link>

+			<name>reg_tests</name>

+			<type>2</type>

+			<locationURI>DEMO_ROOT/Common/ARMv8M/reg_tests</locationURI>

+		</link>

+		<link>

 			<name>NSCFunctions/nsc_functions.c</name>

 			<type>1</type>

 			<locationURI>PARENT-4-PROJECT_LOC/Common/ARMv8M/tz_demo/nsc_functions.c</locationURI>

@@ -122,6 +127,16 @@
 			<locationURI>PROJECT_LOC/main_s.c</locationURI>

 		</link>

 		<link>

+			<name>User/nsc_printf.c</name>

+			<type>1</type>

+			<locationURI>PROJECT_LOC/nsc_printf.c</locationURI>

+		</link>

+		<link>

+			<name>User/nsc_printf.h</name>

+			<type>1</type>

+			<locationURI>PROJECT_LOC/nsc_printf.h</locationURI>

+		</link>

+		<link>

 			<name>User/tzm_config.c</name>

 			<type>1</type>

 			<locationURI>PROJECT_LOC/tzm_config.c</locationURI>

@@ -151,5 +166,38 @@
 				<arguments>1.0-name-matches-false-false-*.h</arguments>

 			</matcher>

 		</filter>

+		<filter>

+			<id>1681721632460</id>

+			<name>reg_tests</name>

+			<type>9</type>

+			<matcher>

+				<id>org.eclipse.ui.ide.multiFilter</id>

+				<arguments>1.0-name-matches-false-false-GCC</arguments>

+			</matcher>

+		</filter>

+		<filter>

+			<id>1681721650651</id>

+			<name>reg_tests/GCC</name>

+			<type>9</type>

+			<matcher>

+				<id>org.eclipse.ui.ide.multiFilter</id>

+				<arguments>1.0-name-matches-false-false-ARM_CM33</arguments>

+			</matcher>

+		</filter>

+		<filter>

+			<id>1681721666490</id>

+			<name>reg_tests/GCC/ARM_CM33</name>

+			<type>9</type>

+			<matcher>

+				<id>org.eclipse.ui.ide.multiFilter</id>

+				<arguments>1.0-name-matches-false-false-secure</arguments>

+			</matcher>

+		</filter>

 	</filteredResources>

+	<variableList>

+		<variable>

+			<name>DEMO_ROOT</name>

+			<value>$%7BPARENT-4-PROJECT_LOC%7D</value>

+		</variable>

+	</variableList>

 </projectDescription>

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/main_s.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/main_s.c
index de37dc43f..abe5b7d85 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/main_s.c
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/main_s.c
@@ -35,6 +35,7 @@
 #include "tzm_config.h"

 #include "pin_mux.h"

 #include "clock_config.h"

+#include "fsl_power.h"

 

 #if ( __ARM_FEATURE_CMSE & 1 ) == 0

 	#error "Need ARMv8-M security extensions"

@@ -70,7 +71,8 @@ void SystemInitHook( void );
 /* Secure main(). */

 int main(void)

 {

-	PRINTF( "Booting Secure World.\r\n" );

+	/* Set BOD VBAT level to 1.65V. */

+	POWER_SetBodVbatLevel( kPOWER_BodVbatLevel1650mv, kPOWER_BodHystLevel50mv, false );

 

 	/* Attach main clock divide to FLEXCOMM0 (debug console). */

 	CLOCK_AttachClk( BOARD_DEBUG_UART_CLK_ATTACH );

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/nsc_printf.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/nsc_printf.c
new file mode 100644
index 000000000..d3d04719f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/nsc_printf.c
@@ -0,0 +1,78 @@
+/*
+ * FreeRTOS V202212.00
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* ARM includes. */
+#include <arm_cmse.h>
+
+/* Interface includes. */
+#include "nsc_printf.h"
+
+/* FreeRTOS includes. */
+#include "secure_port_macros.h"
+
+/* Device includes. */
+#include "fsl_debug_console.h"
+/*-----------------------------------------------------------*/
+
+/* Maximum length of the string that the non-secure code
+ * can print. */
+#define MAX_ALLOWED_STRING_LENGTH   0x400
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void NSC_Printf( char const *str )
+{
+    uint32_t isInvalidSting = 0;
+    size_t stringLength;
+
+    /* Check whether the string is null terminated. */
+    stringLength = strnlen( str, MAX_ALLOWED_STRING_LENGTH );
+
+    if( ( stringLength == MAX_ALLOWED_STRING_LENGTH ) &&
+        ( str[ stringLength ] != '\0') )
+    {
+        PRINTF( "[ERROR] [NSC_Printf] String too long or not null terminated!\r\n" );
+        isInvalidSting = 1;
+    }
+
+    if( isInvalidSting == 0 )
+    {
+        /* Check whether the string is located in non-secure memory. */
+        if( cmse_check_address_range( ( void * ) str,
+                                      stringLength,
+                                      ( CMSE_NONSECURE | CMSE_MPU_READ ) ) == NULL )
+        {
+            PRINTF( "[ERROR] [NSC_Printf] String is not located in non-secure memory!\r\n" );
+            isInvalidSting = 1;
+        }
+    }
+
+    /* Print the string if it is a valid string. */
+    if( isInvalidSting == 0 )
+    {
+        PRINTF( str );
+    }
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/nsc_printf.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/nsc_printf.h
new file mode 100644
index 000000000..1362b4556
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/nsc_printf.h
@@ -0,0 +1,37 @@
+/*
+ * FreeRTOS V202212.00
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef NSC_PRINTF_H
+#define NSC_PRINTF_H
+
+/**
+ * @brief Non-Secure callable printf function.
+ *
+ * @param str The string to print.
+ */
+void NSC_Printf( char const *str );
+
+#endif /* NSC_PRINTF_H */
diff --git a/FreeRTOS/Demo/Common/ARMv8M/reg_tests/GCC/ARM_CM33/non_secure/reg_test_asm.c b/FreeRTOS/Demo/Common/ARMv8M/reg_tests/GCC/ARM_CM33/non_secure/reg_test_asm.c
new file mode 100644
index 000000000..6b276ca29
--- /dev/null
+++ b/FreeRTOS/Demo/Common/ARMv8M/reg_tests/GCC/ARM_CM33/non_secure/reg_test_asm.c
@@ -0,0 +1,1220 @@
+/*
+ * FreeRTOS V202212.00
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*
+ * "Reg tests" - These tests fill the registers with known values, then check
+ * that each register maintains its expected value for the lifetime of the
+ * task.  Each task uses a different set of values.  The reg test tasks execute
+ * with a very low priority, so get preempted very frequently.  A register
+ * containing an unexpected value is indicative of an error in the context
+ * switching mechanism.
+ */
+
+#include "reg_test_asm.h"
+/*-----------------------------------------------------------*/
+
+void vRegTest1Asm_NonSecure( void ) /* __attribute__(( naked )) */
+{
+    __asm volatile
+    (
+        ".extern ulRegTest1LoopCounter                              \n"
+        ".syntax unified                                            \n"
+        "                                                           \n"
+        "    /* Fill the core registers with known values. */       \n"
+        "    movs r0,  #100                                         \n"
+        "    movs r1,  #101                                         \n"
+        "    movs r2,  #102                                         \n"
+        "    movs r3,  #103                                         \n"
+        "    movs r4,  #104                                         \n"
+        "    movs r5,  #105                                         \n"
+        "    movs r6,  #106                                         \n"
+        "    movs r7,  #107                                         \n"
+        "    mov  r8,  #108                                         \n"
+        "    mov  r9,  #109                                         \n"
+        "    mov  r10, #110                                         \n"
+        "    mov  r11, #111                                         \n"
+        "    mov  r12, #112                                         \n"
+        "                                                           \n"
+        "    /* Fill the FPU registers with known values. */        \n"
+        "    vmov.f32 s1,  #1.5                                     \n"
+        "    vmov.f32 s2,  #2.5                                     \n"
+        "    vmov.f32 s3,  #3.5                                     \n"
+        "    vmov.f32 s4,  #4.5                                     \n"
+        "    vmov.f32 s5,  #5.5                                     \n"
+        "    vmov.f32 s6,  #6.5                                     \n"
+        "    vmov.f32 s7,  #7.5                                     \n"
+        "    vmov.f32 s8,  #8.5                                     \n"
+        "    vmov.f32 s9,  #9.5                                     \n"
+        "    vmov.f32 s10, #10.5                                    \n"
+        "    vmov.f32 s11, #11.5                                    \n"
+        "    vmov.f32 s12, #12.5                                    \n"
+        "    vmov.f32 s13, #13.5                                    \n"
+        "    vmov.f32 s14, #14.5                                    \n"
+        "    vmov.f32 s15, #1.0                                     \n"
+        "    vmov.f32 s16, #2.0                                     \n"
+        "    vmov.f32 s17, #3.0                                     \n"
+        "    vmov.f32 s18, #4.0                                     \n"
+        "    vmov.f32 s19, #5.0                                     \n"
+        "    vmov.f32 s20, #6.0                                     \n"
+        "    vmov.f32 s21, #7.0                                     \n"
+        "    vmov.f32 s22, #8.0                                     \n"
+        "    vmov.f32 s23, #9.0                                     \n"
+        "    vmov.f32 s24, #10.0                                    \n"
+        "    vmov.f32 s25, #11.0                                    \n"
+        "    vmov.f32 s26, #12.0                                    \n"
+        "    vmov.f32 s27, #13.0                                    \n"
+        "    vmov.f32 s28, #14.0                                    \n"
+        "    vmov.f32 s29, #1.5                                     \n"
+        "    vmov.f32 s30, #2.5                                     \n"
+        "    vmov.f32 s31, #3.5                                     \n"
+        "                                                           \n"
+        "reg1_loop:                                                 \n"
+        "                                                           \n"
+        " /* Verify that core registers contain correct values. */  \n"
+        "    cmp r0, #100                                           \n"
+        "    bne reg1_error_loop                                    \n"
+        "    cmp r1, #101                                           \n"
+        "    bne reg1_error_loop                                    \n"
+        "    cmp r2, #102                                           \n"
+        "    bne reg1_error_loop                                    \n"
+        "    cmp r3, #103                                           \n"
+        "    bne reg1_error_loop                                    \n"
+        "    cmp r4, #104                                           \n"
+        "    bne reg1_error_loop                                    \n"
+        "    cmp r5, #105                                           \n"
+        "    bne reg1_error_loop                                    \n"
+        "    cmp r6, #106                                           \n"
+        "    bne reg1_error_loop                                    \n"
+        "    cmp r7, #107                                           \n"
+        "    bne reg1_error_loop                                    \n"
+        "    cmp r8, #108                                           \n"
+        "    bne reg1_error_loop                                    \n"
+        "    cmp r9, #109                                           \n"
+        "    bne reg1_error_loop                                    \n"
+        "    cmp r10, #110                                          \n"
+        "    bne reg1_error_loop                                    \n"
+        "    cmp r11, #111                                          \n"
+        "    bne reg1_error_loop                                    \n"
+        "    cmp r12, #112                                          \n"
+        "    bne reg1_error_loop                                    \n"
+        "                                                           \n"
+        " /* Verify that FPU registers contain correct values. */   \n"
+        "    vmov.f32 s0, #1.5                                      \n" /* s0 = 1.5. */
+        "    vcmp.f32 s1, s0                                        \n" /* Compare s0 and s1. */
+        "    vmrs     APSR_nzcv, FPSCR                              \n" /* Copy floating point flags (FPSCR flags) to ASPR flags - needed for next bne to work. */
+        "    bne      reg1_error_loop                               \n"
+        "    vmov.f32 s0, #2.5                                      \n"
+        "    vcmp.f32 s2, s0                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg1_error_loop                               \n"
+        "    vmov.f32 s0, #3.5                                      \n"
+        "    vcmp.f32 s3, s0                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg1_error_loop                               \n"
+        "    vmov.f32 s0, #4.5                                      \n"
+        "    vcmp.f32 s4, s0                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg1_error_loop                               \n"
+        "    vmov.f32 s0, #5.5                                      \n"
+        "    vcmp.f32 s5, s0                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg1_error_loop                               \n"
+        "    vmov.f32 s0, #6.5                                      \n"
+        "    vcmp.f32 s6, s0                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg1_error_loop                               \n"
+        "    vmov.f32 s0, #7.5                                      \n"
+        "    vcmp.f32 s7, s0                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg1_error_loop                               \n"
+        "    vmov.f32 s0, #8.5                                      \n"
+        "    vcmp.f32 s8, s0                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg1_error_loop                               \n"
+        "    vmov.f32 s0, #9.5                                      \n"
+        "    vcmp.f32 s9, s0                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg1_error_loop                               \n"
+        "    vmov.f32 s0, #10.5                                     \n"
+        "    vcmp.f32 s10, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg1_error_loop                               \n"
+        "    vmov.f32 s0, #11.5                                     \n"
+        "    vcmp.f32 s11, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg1_error_loop                               \n"
+        "    vmov.f32 s0, #12.5                                     \n"
+        "    vcmp.f32 s12, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg1_error_loop                               \n"
+        "    vmov.f32 s0, #13.5                                     \n"
+        "    vcmp.f32 s13, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg1_error_loop                               \n"
+        "    vmov.f32 s0, #14.5                                     \n"
+        "    vcmp.f32 s14, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg1_error_loop                               \n"
+        "    vmov.f32 s0, #1.0                                      \n"
+        "    vcmp.f32 s15, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg1_error_loop                               \n"
+        "    vmov.f32 s0, #2.0                                      \n"
+        "    vcmp.f32 s16, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg1_error_loop                               \n"
+        "    vmov.f32 s0, #3.0                                      \n"
+        "    vcmp.f32 s17, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg1_error_loop                               \n"
+        "    vmov.f32 s0, #4.0                                      \n"
+        "    vcmp.f32 s18, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg1_error_loop                               \n"
+        "    vmov.f32 s0, #5.0                                      \n"
+        "    vcmp.f32 s19, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg1_error_loop                               \n"
+        "    vmov.f32 s0, #6.0                                      \n"
+        "    vcmp.f32 s20, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg1_error_loop                               \n"
+        "    vmov.f32 s0, #7.0                                      \n"
+        "    vcmp.f32 s21, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg1_error_loop                               \n"
+        "    vmov.f32 s0, #8.0                                      \n"
+        "    vcmp.f32 s22, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg1_error_loop                               \n"
+        "    vmov.f32 s0, #9.0                                      \n"
+        "    vcmp.f32 s23, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg1_error_loop                               \n"
+        "    vmov.f32 s0, #10.0                                     \n"
+        "    vcmp.f32 s24, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg1_error_loop                               \n"
+        "    vmov.f32 s0, #11.0                                     \n"
+        "    vcmp.f32 s25, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg1_error_loop                               \n"
+        "    vmov.f32 s0, #12.0                                     \n"
+        "    vcmp.f32 s26, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg1_error_loop                               \n"
+        "    vmov.f32 s0, #13.0                                     \n"
+        "    vcmp.f32 s27, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg1_error_loop                               \n"
+        "    vmov.f32 s0, #14.0                                     \n"
+        "    vcmp.f32 s28, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg1_error_loop                               \n"
+        "    vmov.f32 s0, #1.5                                      \n"
+        "    vcmp.f32 s29, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg1_error_loop                               \n"
+        "    vmov.f32 s0, #2.5                                      \n"
+        "    vcmp.f32 s30, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg1_error_loop                               \n"
+        "    vmov.f32 s0, #3.5                                      \n"
+        "    vcmp.f32 s31, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg1_error_loop                               \n"
+        "                                                           \n"
+        "    /* Everything passed, inc the loop counter. */         \n"
+        "    push { r0, r1 }                                        \n"
+        "    ldr  r0, =ulRegTest1LoopCounter                        \n"
+        "    ldr  r1, [r0]                                          \n"
+        "    adds r1, r1, #1                                        \n"
+        "    str  r1, [r0]                                          \n"
+        "                                                           \n"
+        "    /* Yield to increase test coverage. */                 \n"
+        "    movs r0, #0x01                                         \n"
+        "    ldr  r1, =0xe000ed04                                   \n" /* NVIC_ICSR. */
+        "    lsls r0, #28                                           \n" /* Shift to PendSV bit. */
+        "    str  r0, [r1]                                          \n"
+        "    dsb                                                    \n"
+        "    pop  { r0, r1 }                                        \n"
+        "                                                           \n"
+        "    /* Start again. */                                     \n"
+        "    b reg1_loop                                            \n"
+        "                                                           \n"
+        "reg1_error_loop:                                           \n"
+        "    /* If this line is hit then there was an error in      \n"
+        "     * a core register value. The loop ensures the         \n"
+        "     * loop counter stops incrementing. */                 \n"
+        "    b reg1_error_loop                                      \n"
+        "    nop                                                    \n"
+        ".ltorg                                                     \n"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vRegTest2Asm_NonSecure( void ) /* __attribute__(( naked )) */
+{
+    __asm volatile
+    (
+        ".extern ulRegTest2LoopCounter                              \n"
+        ".syntax unified                                            \n"
+        "                                                           \n"
+        "    /* Fill the core registers with known values. */       \n"
+        "    movs r0, #0                                            \n"
+        "    movs r1, #1                                            \n"
+        "    movs r2, #2                                            \n"
+        "    movs r3, #3                                            \n"
+        "    movs r4, #4                                            \n"
+        "    movs r5, #5                                            \n"
+        "    movs r6, #6                                            \n"
+        "    movs r7, #7                                            \n"
+        "    mov  r8, #8                                            \n"
+        "    mov  r9, #9                                            \n"
+        "    movs r10, #10                                          \n"
+        "    movs r11, #11                                          \n"
+        "    movs r12, #12                                          \n"
+        "                                                           \n"
+        "    /* Fill the FPU registers with known values. */        \n"
+        "    vmov.f32 s1,  #1.0                                     \n"
+        "    vmov.f32 s2,  #2.0                                     \n"
+        "    vmov.f32 s3,  #3.0                                     \n"
+        "    vmov.f32 s4,  #4.0                                     \n"
+        "    vmov.f32 s5,  #5.0                                     \n"
+        "    vmov.f32 s6,  #6.0                                     \n"
+        "    vmov.f32 s7,  #7.0                                     \n"
+        "    vmov.f32 s8,  #8.0                                     \n"
+        "    vmov.f32 s9,  #9.0                                     \n"
+        "    vmov.f32 s10, #10.0                                    \n"
+        "    vmov.f32 s11, #11.0                                    \n"
+        "    vmov.f32 s12, #12.0                                    \n"
+        "    vmov.f32 s13, #13.0                                    \n"
+        "    vmov.f32 s14, #14.0                                    \n"
+        "    vmov.f32 s15, #1.5                                     \n"
+        "    vmov.f32 s16, #2.5                                     \n"
+        "    vmov.f32 s17, #3.5                                     \n"
+        "    vmov.f32 s18, #4.5                                     \n"
+        "    vmov.f32 s19, #5.5                                     \n"
+        "    vmov.f32 s20, #6.5                                     \n"
+        "    vmov.f32 s21, #7.5                                     \n"
+        "    vmov.f32 s22, #8.5                                     \n"
+        "    vmov.f32 s23, #9.5                                     \n"
+        "    vmov.f32 s24, #10.5                                    \n"
+        "    vmov.f32 s25, #11.5                                    \n"
+        "    vmov.f32 s26, #12.5                                    \n"
+        "    vmov.f32 s27, #13.5                                    \n"
+        "    vmov.f32 s28, #14.5                                    \n"
+        "    vmov.f32 s29, #1.0                                     \n"
+        "    vmov.f32 s30, #2.0                                     \n"
+        "    vmov.f32 s31, #3.0                                     \n"
+        "                                                           \n"
+        "reg2_loop:                                                 \n"
+        "                                                           \n"
+        " /* Verify that core registers contain correct values. */  \n"
+        "    cmp  r0, #0                                            \n"
+        "    bne  reg2_error_loop                                   \n"
+        "    cmp  r1, #1                                            \n"
+        "    bne  reg2_error_loop                                   \n"
+        "    cmp  r2, #2                                            \n"
+        "    bne  reg2_error_loop                                   \n"
+        "    cmp  r3, #3                                            \n"
+        "    bne  reg2_error_loop                                   \n"
+        "    cmp  r4, #4                                            \n"
+        "    bne  reg2_error_loop                                   \n"
+        "    cmp  r5, #5                                            \n"
+        "    bne  reg2_error_loop                                   \n"
+        "    cmp  r6, #6                                            \n"
+        "    bne  reg2_error_loop                                   \n"
+        "    cmp  r7, #7                                            \n"
+        "    bne  reg2_error_loop                                   \n"
+        "    cmp  r8, #8                                            \n"
+        "    bne  reg2_error_loop                                   \n"
+        "    cmp  r9, #9                                            \n"
+        "    bne  reg2_error_loop                                   \n"
+        "    cmp  r10, #10                                          \n"
+        "    bne  reg2_error_loop                                   \n"
+        "    cmp  r11, #11                                          \n"
+        "    bne  reg2_error_loop                                   \n"
+        "    cmp  r12, #12                                          \n"
+        "    bne  reg2_error_loop                                   \n"
+        "                                                           \n"
+        " /* Verify that FPU registers contain correct values. */   \n"
+        "    vmov.f32 s0, #1.0                                      \n"
+        "    vcmp.f32 s1, s0                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg2_error_loop                               \n"
+        "    vmov.f32 s0, #2.0                                      \n"
+        "    vcmp.f32 s2, s0                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg2_error_loop                               \n"
+        "    vmov.f32 s0, #3.0                                      \n"
+        "    vcmp.f32 s3, s0                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg2_error_loop                               \n"
+        "    vmov.f32 s0, #4.0                                      \n"
+        "    vcmp.f32 s4, s0                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg2_error_loop                               \n"
+        "    vmov.f32 s0, #5.0                                      \n"
+        "    vcmp.f32 s5, s0                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg2_error_loop                               \n"
+        "    vmov.f32 s0, #6.0                                      \n"
+        "    vcmp.f32 s6, s0                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg2_error_loop                               \n"
+        "    vmov.f32 s0, #7.0                                      \n"
+        "    vcmp.f32 s7, s0                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg2_error_loop                               \n"
+        "    vmov.f32 s0, #8.0                                      \n"
+        "    vcmp.f32 s8, s0                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg2_error_loop                               \n"
+        "    vmov.f32 s0, #9.0                                      \n"
+        "    vcmp.f32 s9, s0                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg2_error_loop                               \n"
+        "    vmov.f32 s0, #10.0                                     \n"
+        "    vcmp.f32 s10, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg2_error_loop                               \n"
+        "    vmov.f32 s0, #11.0                                     \n"
+        "    vcmp.f32 s11, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg2_error_loop                               \n"
+        "    vmov.f32 s0, #12.0                                     \n"
+        "    vcmp.f32 s12, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg2_error_loop                               \n"
+        "    vmov.f32 s0, #13.0                                     \n"
+        "    vcmp.f32 s13, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg2_error_loop                               \n"
+        "    vmov.f32 s0, #14.0                                     \n"
+        "    vcmp.f32 s14, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg2_error_loop                               \n"
+        "    vmov.f32 s0, #1.5                                      \n"
+        "    vcmp.f32 s15, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg2_error_loop                               \n"
+        "    vmov.f32 s0, #2.5                                      \n"
+        "    vcmp.f32 s16, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg2_error_loop                               \n"
+        "    vmov.f32 s0, #3.5                                      \n"
+        "    vcmp.f32 s17, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg2_error_loop                               \n"
+        "    vmov.f32 s0, #4.5                                      \n"
+        "    vcmp.f32 s18, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg2_error_loop                               \n"
+        "    vmov.f32 s0, #5.5                                      \n"
+        "    vcmp.f32 s19, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg2_error_loop                               \n"
+        "    vmov.f32 s0, #6.5                                      \n"
+        "    vcmp.f32 s20, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg2_error_loop                               \n"
+        "    vmov.f32 s0, #7.5                                      \n"
+        "    vcmp.f32 s21, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg2_error_loop                               \n"
+        "    vmov.f32 s0, #8.5                                      \n"
+        "    vcmp.f32 s22, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg2_error_loop                               \n"
+        "    vmov.f32 s0, #9.5                                      \n"
+        "    vcmp.f32 s23, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg2_error_loop                               \n"
+        "    vmov.f32 s0, #10.5                                     \n"
+        "    vcmp.f32 s24, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg2_error_loop                               \n"
+        "    vmov.f32 s0, #11.5                                     \n"
+        "    vcmp.f32 s25, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg2_error_loop                               \n"
+        "    vmov.f32 s0, #12.5                                     \n"
+        "    vcmp.f32 s26, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg2_error_loop                               \n"
+        "    vmov.f32 s0, #13.5                                     \n"
+        "    vcmp.f32 s27, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg2_error_loop                               \n"
+        "    vmov.f32 s0, #14.5                                     \n"
+        "    vcmp.f32 s28, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg2_error_loop                               \n"
+        "    vmov.f32 s0, #1.0                                      \n"
+        "    vcmp.f32 s29, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg2_error_loop                               \n"
+        "    vmov.f32 s0, #2.0                                      \n"
+        "    vcmp.f32 s30, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg2_error_loop                               \n"
+        "    vmov.f32 s0, #3.0                                      \n"
+        "    vcmp.f32 s31, s0                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg2_error_loop                               \n"
+        "                                                           \n"
+        "    /* Everything passed, inc the loop counter. */         \n"
+        "    push { r0, r1 }                                        \n"
+        "    ldr  r0, =ulRegTest2LoopCounter                        \n"
+        "    ldr  r1, [r0]                                          \n"
+        "    adds r1, r1, #1                                        \n"
+        "    str  r1, [r0]                                          \n"
+        "    pop  { r0, r1 }                                        \n"
+        "                                                           \n"
+        "    /* Start again. */                                     \n"
+        "    b reg2_loop                                            \n"
+        "                                                           \n"
+        "reg2_error_loop:                                           \n"
+        "    /* If this line is hit then there was an error in      \n"
+        "     * a core register value. The loop ensures the         \n"
+        "     * loop counter stops incrementing. */                 \n"
+        "    b reg2_error_loop                                      \n"
+        "    nop                                                    \n"
+        ".ltorg                                                     \n"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vRegTest3Asm_NonSecure( void ) /* __attribute__(( naked )) */
+{
+    __asm volatile
+    (
+        ".extern ulRegTest3LoopCounter                              \n"
+        ".syntax unified                                            \n"
+        "                                                           \n"
+        "    /* Fill the core registers with known values. */       \n"
+        "    movs r0,  #100                                         \n"
+        "    movs r1,  #101                                         \n"
+        "    movs r2,  #102                                         \n"
+        "    movs r3,  #103                                         \n"
+        "    movs r4,  #104                                         \n"
+        "    movs r5,  #105                                         \n"
+        "    movs r6,  #106                                         \n"
+        "    movs r7,  #107                                         \n"
+        "    mov  r8,  #108                                         \n"
+        "    mov  r9,  #109                                         \n"
+        "    mov  r10, #110                                         \n"
+        "    mov  r11, #111                                         \n"
+        "    mov  r12, #112                                         \n"
+        "                                                           \n"
+        "    /* Fill the FPU registers with known values. */        \n"
+        "    vmov.f32 s0,  #1.5                                     \n"
+        "    vmov.f32 s2,  #2.0                                     \n"
+        "    vmov.f32 s3,  #3.5                                     \n"
+        "    vmov.f32 s4,  #4.0                                     \n"
+        "    vmov.f32 s5,  #5.5                                     \n"
+        "    vmov.f32 s6,  #6.0                                     \n"
+        "    vmov.f32 s7,  #7.5                                     \n"
+        "    vmov.f32 s8,  #8.0                                     \n"
+        "    vmov.f32 s9,  #9.5                                     \n"
+        "    vmov.f32 s10, #10.0                                    \n"
+        "    vmov.f32 s11, #11.5                                    \n"
+        "    vmov.f32 s12, #12.0                                    \n"
+        "    vmov.f32 s13, #13.5                                    \n"
+        "    vmov.f32 s14, #14.0                                    \n"
+        "    vmov.f32 s15, #1.5                                     \n"
+        "    vmov.f32 s16, #2.0                                     \n"
+        "    vmov.f32 s17, #3.5                                     \n"
+        "    vmov.f32 s18, #4.0                                     \n"
+        "    vmov.f32 s19, #5.5                                     \n"
+        "    vmov.f32 s20, #6.0                                     \n"
+        "    vmov.f32 s21, #7.5                                     \n"
+        "    vmov.f32 s22, #8.0                                     \n"
+        "    vmov.f32 s23, #9.5                                     \n"
+        "    vmov.f32 s24, #10.0                                    \n"
+        "    vmov.f32 s25, #11.5                                    \n"
+        "    vmov.f32 s26, #12.0                                    \n"
+        "    vmov.f32 s27, #13.5                                    \n"
+        "    vmov.f32 s28, #14.0                                    \n"
+        "    vmov.f32 s29, #1.5                                     \n"
+        "    vmov.f32 s30, #2.0                                     \n"
+        "    vmov.f32 s31, #3.5                                     \n"
+        "                                                           \n"
+        "reg3_loop:                                                 \n"
+        "                                                           \n"
+        " /* Verify that core registers contain correct values. */  \n"
+        "    cmp r0, #100                                           \n"
+        "    bne reg3_error_loop                                    \n"
+        "    cmp r1, #101                                           \n"
+        "    bne reg3_error_loop                                    \n"
+        "    cmp r2, #102                                           \n"
+        "    bne reg3_error_loop                                    \n"
+        "    cmp r3, #103                                           \n"
+        "    bne reg3_error_loop                                    \n"
+        "    cmp r4, #104                                           \n"
+        "    bne reg3_error_loop                                    \n"
+        "    cmp r5, #105                                           \n"
+        "    bne reg3_error_loop                                    \n"
+        "    cmp r6, #106                                           \n"
+        "    bne reg3_error_loop                                    \n"
+        "    cmp r7, #107                                           \n"
+        "    bne reg3_error_loop                                    \n"
+        "    cmp r8, #108                                           \n"
+        "    bne reg3_error_loop                                    \n"
+        "    cmp r9, #109                                           \n"
+        "    bne reg3_error_loop                                    \n"
+        "    cmp r10, #110                                          \n"
+        "    bne reg3_error_loop                                    \n"
+        "    cmp r11, #111                                          \n"
+        "    bne reg3_error_loop                                    \n"
+        "    cmp r12, #112                                          \n"
+        "    bne reg3_error_loop                                    \n"
+        "                                                           \n"
+        " /* Verify that FPU registers contain correct values. */   \n"
+        "    vmov.f32 s1, #1.5                                      \n"
+        "    vcmp.f32 s0, s1                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg3_error_loop                               \n"
+        "    vmov.f32 s1, #2.0                                      \n"
+        "    vcmp.f32 s2, s1                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg3_error_loop                               \n"
+        "    vmov.f32 s1, #3.5                                      \n"
+        "    vcmp.f32 s3, s1                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg3_error_loop                               \n"
+        "    vmov.f32 s1, #4.0                                      \n"
+        "    vcmp.f32 s4, s1                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg3_error_loop                               \n"
+        "    vmov.f32 s1, #5.5                                      \n"
+        "    vcmp.f32 s5, s1                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg3_error_loop                               \n"
+        "    vmov.f32 s1, #6.0                                      \n"
+        "    vcmp.f32 s6, s1                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg3_error_loop                               \n"
+        "    vmov.f32 s1, #7.5                                      \n"
+        "    vcmp.f32 s7, s1                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg3_error_loop                               \n"
+        "    vmov.f32 s1, #8.0                                      \n"
+        "    vcmp.f32 s8, s1                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg3_error_loop                               \n"
+        "    vmov.f32 s1, #9.5                                      \n"
+        "    vcmp.f32 s9, s1                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg3_error_loop                               \n"
+        "    vmov.f32 s1, #10.0                                     \n"
+        "    vcmp.f32 s10, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg3_error_loop                               \n"
+        "    vmov.f32 s1, #11.5                                     \n"
+        "    vcmp.f32 s11, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg3_error_loop                               \n"
+        "    vmov.f32 s1, #12.0                                     \n"
+        "    vcmp.f32 s12, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg3_error_loop                               \n"
+        "    vmov.f32 s1, #13.5                                     \n"
+        "    vcmp.f32 s13, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg3_error_loop                               \n"
+        "    vmov.f32 s1, #14.0                                     \n"
+        "    vcmp.f32 s14, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg3_error_loop                               \n"
+        "    vmov.f32 s1, #1.5                                      \n"
+        "    vcmp.f32 s15, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg3_error_loop                               \n"
+        "    vmov.f32 s1, #2.0                                      \n"
+        "    vcmp.f32 s16, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg3_error_loop                               \n"
+        "    vmov.f32 s1, #3.5                                      \n"
+        "    vcmp.f32 s17, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg3_error_loop                               \n"
+        "    vmov.f32 s1, #4.0                                      \n"
+        "    vcmp.f32 s18, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg3_error_loop                               \n"
+        "    vmov.f32 s1, #5.5                                      \n"
+        "    vcmp.f32 s19, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg3_error_loop                               \n"
+        "    vmov.f32 s1, #6.0                                      \n"
+        "    vcmp.f32 s20, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg3_error_loop                               \n"
+        "    vmov.f32 s1, #7.5                                      \n"
+        "    vcmp.f32 s21, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg3_error_loop                               \n"
+        "    vmov.f32 s1, #8.0                                      \n"
+        "    vcmp.f32 s22, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg3_error_loop                               \n"
+        "    vmov.f32 s1, #9.5                                      \n"
+        "    vcmp.f32 s23, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg3_error_loop                               \n"
+        "    vmov.f32 s1, #10.0                                     \n"
+        "    vcmp.f32 s24, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg3_error_loop                               \n"
+        "    vmov.f32 s1, #11.5                                     \n"
+        "    vcmp.f32 s25, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg3_error_loop                               \n"
+        "    vmov.f32 s1, #12.0                                     \n"
+        "    vcmp.f32 s26, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg3_error_loop                               \n"
+        "    vmov.f32 s1, #13.5                                     \n"
+        "    vcmp.f32 s27, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg3_error_loop                               \n"
+        "    vmov.f32 s1, #14.0                                     \n"
+        "    vcmp.f32 s28, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg3_error_loop                               \n"
+        "    vmov.f32 s1, #1.5                                      \n"
+        "    vcmp.f32 s29, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg3_error_loop                               \n"
+        "    vmov.f32 s1, #2.0                                      \n"
+        "    vcmp.f32 s30, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg3_error_loop                               \n"
+        "    vmov.f32 s1, #3.5                                      \n"
+        "    vcmp.f32 s31, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg3_error_loop                               \n"
+        "                                                           \n"
+        "    /* Everything passed, inc the loop counter. */         \n"
+        "    push { r0, r1 }                                        \n"
+        "    ldr  r0, =ulRegTest3LoopCounter                        \n"
+        "    ldr  r1, [r0]                                          \n"
+        "    adds r1, r1, #1                                        \n"
+        "    str  r1, [r0]                                          \n"
+        "                                                           \n"
+        "    /* Yield to increase test coverage. */                 \n"
+        "    movs r0, #0x01                                         \n"
+        "    ldr  r1, =0xe000ed04                                   \n" /* NVIC_ICSR. */
+        "    lsls r0, #28                                           \n" /* Shift to PendSV bit. */
+        "    str  r0, [r1]                                          \n"
+        "    dsb                                                    \n"
+        "    pop  { r0, r1 }                                        \n"
+        "                                                           \n"
+        "    /* Start again. */                                     \n"
+        "    b reg3_loop                                            \n"
+        "                                                           \n"
+        "reg3_error_loop:                                           \n"
+        "    /* If this line is hit then there was an error in      \n"
+        "     * a core register value. The loop ensures the         \n"
+        "     * loop counter stops incrementing. */                 \n"
+        "    b reg3_error_loop                                      \n"
+        "    nop                                                    \n"
+        ".ltorg                                                     \n"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vRegTest4Asm_NonSecure( void ) /* __attribute__(( naked )) */
+{
+    __asm volatile
+    (
+        ".extern ulRegTest4LoopCounter                              \n"
+        ".syntax unified                                            \n"
+        "                                                           \n"
+        "    /* Fill the core registers with known values. */       \n"
+        "    movs r0, #0                                            \n"
+        "    movs r1, #1                                            \n"
+        "    movs r2, #2                                            \n"
+        "    movs r3, #3                                            \n"
+        "    movs r4, #4                                            \n"
+        "    movs r5, #5                                            \n"
+        "    movs r6, #6                                            \n"
+        "    movs r7, #7                                            \n"
+        "    mov  r8, #8                                            \n"
+        "    mov  r9, #9                                            \n"
+        "    movs r10, #10                                          \n"
+        "    movs r11, #11                                          \n"
+        "    movs r12, #12                                          \n"
+        "                                                           \n"
+        "    /* Fill the FPU registers with known values. */        \n"
+        "    vmov.f32 s0,  #1.5                                     \n"
+        "    vmov.f32 s2,  #2.0                                     \n"
+        "    vmov.f32 s3,  #3.0                                     \n"
+        "    vmov.f32 s4,  #4.5                                     \n"
+        "    vmov.f32 s5,  #5.0                                     \n"
+        "    vmov.f32 s6,  #6.0                                     \n"
+        "    vmov.f32 s7,  #7.5                                     \n"
+        "    vmov.f32 s8,  #8.0                                     \n"
+        "    vmov.f32 s9,  #9.0                                     \n"
+        "    vmov.f32 s10, #10.5                                    \n"
+        "    vmov.f32 s11, #11.0                                    \n"
+        "    vmov.f32 s12, #12.0                                    \n"
+        "    vmov.f32 s13, #13.5                                    \n"
+        "    vmov.f32 s14, #14.0                                    \n"
+        "    vmov.f32 s15, #1.0                                     \n"
+        "    vmov.f32 s16, #2.5                                     \n"
+        "    vmov.f32 s17, #3.0                                     \n"
+        "    vmov.f32 s18, #4.0                                     \n"
+        "    vmov.f32 s19, #5.5                                     \n"
+        "    vmov.f32 s20, #6.0                                     \n"
+        "    vmov.f32 s21, #7.0                                     \n"
+        "    vmov.f32 s22, #8.5                                     \n"
+        "    vmov.f32 s23, #9.0                                     \n"
+        "    vmov.f32 s24, #10.0                                    \n"
+        "    vmov.f32 s25, #11.5                                    \n"
+        "    vmov.f32 s26, #12.0                                    \n"
+        "    vmov.f32 s27, #13.0                                    \n"
+        "    vmov.f32 s28, #14.5                                    \n"
+        "    vmov.f32 s29, #1.0                                     \n"
+        "    vmov.f32 s30, #2.0                                     \n"
+        "    vmov.f32 s31, #3.5                                     \n"
+        "                                                           \n"
+        "reg4_loop:                                                 \n"
+        "                                                           \n"
+        " /* Verify that core registers contain correct values. */  \n"
+        "    cmp  r0, #0                                            \n"
+        "    bne  reg4_error_loop                                   \n"
+        "    cmp  r1, #1                                            \n"
+        "    bne  reg4_error_loop                                   \n"
+        "    cmp  r2, #2                                            \n"
+        "    bne  reg4_error_loop                                   \n"
+        "    cmp  r3, #3                                            \n"
+        "    bne  reg4_error_loop                                   \n"
+        "    cmp  r4, #4                                            \n"
+        "    bne  reg4_error_loop                                   \n"
+        "    cmp  r5, #5                                            \n"
+        "    bne  reg4_error_loop                                   \n"
+        "    cmp  r6, #6                                            \n"
+        "    bne  reg4_error_loop                                   \n"
+        "    cmp  r7, #7                                            \n"
+        "    bne  reg4_error_loop                                   \n"
+        "    cmp  r8, #8                                            \n"
+        "    bne  reg4_error_loop                                   \n"
+        "    cmp  r9, #9                                            \n"
+        "    bne  reg4_error_loop                                   \n"
+        "    cmp  r10, #10                                          \n"
+        "    bne  reg4_error_loop                                   \n"
+        "    cmp  r11, #11                                          \n"
+        "    bne  reg4_error_loop                                   \n"
+        "    cmp  r12, #12                                          \n"
+        "    bne  reg4_error_loop                                   \n"
+        "                                                           \n"
+        " /* Verify that FPU registers contain correct values. */   \n"
+        "    vmov.f32 s1, #1.5                                      \n"
+        "    vcmp.f32 s0, s1                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg4_error_loop                               \n"
+        "    vmov.f32 s1, #2.0                                      \n"
+        "    vcmp.f32 s2, s1                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg4_error_loop                               \n"
+        "    vmov.f32 s1, #3.0                                      \n"
+        "    vcmp.f32 s3, s1                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg4_error_loop                               \n"
+        "    vmov.f32 s1, #4.5                                      \n"
+        "    vcmp.f32 s4, s1                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg4_error_loop                               \n"
+        "    vmov.f32 s1, #5.0                                      \n"
+        "    vcmp.f32 s5, s1                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg4_error_loop                               \n"
+        "    vmov.f32 s1, #6.0                                      \n"
+        "    vcmp.f32 s6, s1                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg4_error_loop                               \n"
+        "    vmov.f32 s1, #7.5                                      \n"
+        "    vcmp.f32 s7, s1                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg4_error_loop                               \n"
+        "    vmov.f32 s1, #8.0                                      \n"
+        "    vcmp.f32 s8, s1                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg4_error_loop                               \n"
+        "    vmov.f32 s1, #9.0                                      \n"
+        "    vcmp.f32 s9, s1                                        \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg4_error_loop                               \n"
+        "    vmov.f32 s1, #10.5                                     \n"
+        "    vcmp.f32 s10, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg4_error_loop                               \n"
+        "    vmov.f32 s1, #11.0                                     \n"
+        "    vcmp.f32 s11, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg4_error_loop                               \n"
+        "    vmov.f32 s1, #12.0                                     \n"
+        "    vcmp.f32 s12, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg4_error_loop                               \n"
+        "    vmov.f32 s1, #13.5                                     \n"
+        "    vcmp.f32 s13, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg4_error_loop                               \n"
+        "    vmov.f32 s1, #14.0                                     \n"
+        "    vcmp.f32 s14, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg4_error_loop                               \n"
+        "    vmov.f32 s1, #1.0                                      \n"
+        "    vcmp.f32 s15, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg4_error_loop                               \n"
+        "    vmov.f32 s1, #2.5                                      \n"
+        "    vcmp.f32 s16, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg4_error_loop                               \n"
+        "    vmov.f32 s1, #3.0                                      \n"
+        "    vcmp.f32 s17, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg4_error_loop                               \n"
+        "    vmov.f32 s1, #4.0                                      \n"
+        "    vcmp.f32 s18, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg4_error_loop                               \n"
+        "    vmov.f32 s1, #5.5                                      \n"
+        "    vcmp.f32 s19, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg4_error_loop                               \n"
+        "    vmov.f32 s1, #6.0                                      \n"
+        "    vcmp.f32 s20, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg4_error_loop                               \n"
+        "    vmov.f32 s1, #7.0                                      \n"
+        "    vcmp.f32 s21, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg4_error_loop                               \n"
+        "    vmov.f32 s1, #8.5                                      \n"
+        "    vcmp.f32 s22, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg4_error_loop                               \n"
+        "    vmov.f32 s1, #9.0                                      \n"
+        "    vcmp.f32 s23, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg4_error_loop                               \n"
+        "    vmov.f32 s1, #10.0                                     \n"
+        "    vcmp.f32 s24, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg4_error_loop                               \n"
+        "    vmov.f32 s1, #11.5                                     \n"
+        "    vcmp.f32 s25, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg4_error_loop                               \n"
+        "    vmov.f32 s1, #12.0                                     \n"
+        "    vcmp.f32 s26, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg4_error_loop                               \n"
+        "    vmov.f32 s1, #13.0                                     \n"
+        "    vcmp.f32 s27, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg4_error_loop                               \n"
+        "    vmov.f32 s1, #14.5                                     \n"
+        "    vcmp.f32 s28, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg4_error_loop                               \n"
+        "    vmov.f32 s1, #1.0                                      \n"
+        "    vcmp.f32 s29, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg4_error_loop                               \n"
+        "    vmov.f32 s1, #2.0                                      \n"
+        "    vcmp.f32 s30, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg4_error_loop                               \n"
+        "    vmov.f32 s1, #3.5                                      \n"
+        "    vcmp.f32 s31, s1                                       \n"
+        "    vmrs     APSR_nzcv, FPSCR                              \n"
+        "    bne      reg4_error_loop                               \n"
+        "                                                           \n"
+        "    /* Everything passed, inc the loop counter. */         \n"
+        "    push { r0, r1 }                                        \n"
+        "    ldr  r0, =ulRegTest4LoopCounter                        \n"
+        "    ldr  r1, [r0]                                          \n"
+        "    adds r1, r1, #1                                        \n"
+        "    str  r1, [r0]                                          \n"
+        "    pop  { r0, r1 }                                        \n"
+        "                                                           \n"
+        "    /* Start again. */                                     \n"
+        "    b reg4_loop                                            \n"
+        "                                                           \n"
+        "reg4_error_loop:                                           \n"
+        "    /* If this line is hit then there was an error in      \n"
+        "     * a core register value. The loop ensures the         \n"
+        "     * loop counter stops incrementing. */                 \n"
+        "    b reg4_error_loop                                      \n"
+        "    nop                                                    \n"
+        ".ltorg                                                     \n"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vRegTestAsm_NonSecureCallback( void )
+{
+    __asm volatile
+    (
+        ".syntax unified                                                \n"
+        "                                                               \n"
+        "    /* Store callee saved registers. */                        \n"
+        "    push { r4-r12 }                                            \n"
+        "                                                               \n"
+        "    /* Fill the core registers with known values. */           \n"
+        "    movs r0, #150                                              \n"
+        "    movs r1, #151                                              \n"
+        "    movs r2, #152                                              \n"
+        "    movs r3, #153                                              \n"
+        "    movs r4, #154                                              \n"
+        "    movs r5, #155                                              \n"
+        "    movs r6, #156                                              \n"
+        "    movs r7, #157                                              \n"
+        "    movs r8, #158                                              \n"
+        "    movs r9, #159                                              \n"
+        "    movs r10, #160                                             \n"
+        "    movs r11, #161                                             \n"
+        "    movs r12, #162                                             \n"
+        "                                                               \n"
+        "    /* Fill the FPU registers with known values. */            \n"
+        "    vmov.f32 s0,  #1.0                                         \n"
+        "    vmov.f32 s2,  #2.5                                         \n"
+        "    vmov.f32 s3,  #3.5                                         \n"
+        "    vmov.f32 s4,  #4.0                                         \n"
+        "    vmov.f32 s5,  #5.5                                         \n"
+        "    vmov.f32 s6,  #6.5                                         \n"
+        "    vmov.f32 s7,  #7.0                                         \n"
+        "    vmov.f32 s8,  #8.5                                         \n"
+        "    vmov.f32 s9,  #9.5                                         \n"
+        "    vmov.f32 s10, #10.0                                        \n"
+        "    vmov.f32 s11, #11.5                                        \n"
+        "    vmov.f32 s12, #12.5                                        \n"
+        "    vmov.f32 s13, #13.0                                        \n"
+        "    vmov.f32 s14, #14.5                                        \n"
+        "    vmov.f32 s15, #1.5                                         \n"
+        "    vmov.f32 s16, #2.0                                         \n"
+        "    vmov.f32 s17, #3.5                                         \n"
+        "    vmov.f32 s18, #4.5                                         \n"
+        "    vmov.f32 s19, #5.0                                         \n"
+        "    vmov.f32 s20, #6.5                                         \n"
+        "    vmov.f32 s21, #7.5                                         \n"
+        "    vmov.f32 s22, #8.0                                         \n"
+        "    vmov.f32 s23, #9.5                                         \n"
+        "    vmov.f32 s24, #10.5                                        \n"
+        "    vmov.f32 s25, #11.0                                        \n"
+        "    vmov.f32 s26, #12.5                                        \n"
+        "    vmov.f32 s27, #13.5                                        \n"
+        "    vmov.f32 s28, #14.0                                        \n"
+        "    vmov.f32 s29, #1.5                                         \n"
+        "    vmov.f32 s30, #2.5                                         \n"
+        "    vmov.f32 s31, #3.0                                         \n"
+        "                                                               \n"
+        "    /* Force a context switch by pending sv. */                \n"
+        "    push { r0, r1 }                                            \n"
+        "    movs r0, #0x01                                             \n"
+        "    ldr  r1, =0xe000ed04                                       \n" /* NVIC_ICSR. */
+        "    lsls r0, #28                                               \n" /* Shift to PendSV bit. */
+        "    str  r0, [r1]                                              \n"
+        "    dsb                                                        \n"
+        "    pop  { r0, r1 }                                            \n"
+        "                                                               \n"
+        "    /* Verify that core registers contain correct values. */   \n"
+        "    cmp  r0, #150                                              \n"
+        "    bne  reg_nscb_error_loop                                   \n"
+        "    cmp  r1, #151                                              \n"
+        "    bne  reg_nscb_error_loop                                   \n"
+        "    cmp  r2, #152                                              \n"
+        "    bne  reg_nscb_error_loop                                   \n"
+        "    cmp  r3, #153                                              \n"
+        "    bne  reg_nscb_error_loop                                   \n"
+        "    cmp  r4, #154                                              \n"
+        "    bne  reg_nscb_error_loop                                   \n"
+        "    cmp  r5, #155                                              \n"
+        "    bne  reg_nscb_error_loop                                   \n"
+        "    cmp  r6, #156                                              \n"
+        "    bne  reg_nscb_error_loop                                   \n"
+        "    cmp  r7, #157                                              \n"
+        "    bne  reg_nscb_error_loop                                   \n"
+        "    cmp  r8, #158                                              \n"
+        "    bne  reg_nscb_error_loop                                   \n"
+        "    cmp  r9, #159                                              \n"
+        "    bne  reg_nscb_error_loop                                   \n"
+        "    cmp  r10, #160                                             \n"
+        "    bne  reg_nscb_error_loop                                   \n"
+        "    cmp  r11, #161                                             \n"
+        "    bne  reg_nscb_error_loop                                   \n"
+        "    cmp  r12, #162                                             \n"
+        "    bne  reg_nscb_error_loop                                   \n"
+        "                                                               \n"
+        "    /* Verify that FPU registers contain correct values. */    \n"
+        "    vmov.f32 s1, #1.0                                          \n"
+        "    vcmp.f32 s0, s1                                            \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      reg_nscb_error_loop                               \n"
+        "    vmov.f32 s1, #2.5                                          \n"
+        "    vcmp.f32 s2, s1                                            \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      reg_nscb_error_loop                               \n"
+        "    vmov.f32 s1, #3.5                                          \n"
+        "    vcmp.f32 s3, s1                                            \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      reg_nscb_error_loop                               \n"
+        "    vmov.f32 s1, #4.0                                          \n"
+        "    vcmp.f32 s4, s1                                            \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      reg_nscb_error_loop                               \n"
+        "    vmov.f32 s1, #5.5                                          \n"
+        "    vcmp.f32 s5, s1                                            \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      reg_nscb_error_loop                               \n"
+        "    vmov.f32 s1, #6.5                                          \n"
+        "    vcmp.f32 s6, s1                                            \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      reg_nscb_error_loop                               \n"
+        "    vmov.f32 s1, #7.0                                          \n"
+        "    vcmp.f32 s7, s1                                            \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      reg_nscb_error_loop                               \n"
+        "    vmov.f32 s1, #8.5                                          \n"
+        "    vcmp.f32 s8, s1                                            \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      reg_nscb_error_loop                               \n"
+        "    vmov.f32 s1, #9.5                                          \n"
+        "    vcmp.f32 s9, s1                                            \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      reg_nscb_error_loop                               \n"
+        "    vmov.f32 s1, #10.0                                         \n"
+        "    vcmp.f32 s10, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      reg_nscb_error_loop                               \n"
+        "    vmov.f32 s1, #11.5                                         \n"
+        "    vcmp.f32 s11, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      reg_nscb_error_loop                               \n"
+        "    vmov.f32 s1, #12.5                                         \n"
+        "    vcmp.f32 s12, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      reg_nscb_error_loop                               \n"
+        "    vmov.f32 s1, #13.0                                         \n"
+        "    vcmp.f32 s13, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      reg_nscb_error_loop                               \n"
+        "    vmov.f32 s1, #14.5                                         \n"
+        "    vcmp.f32 s14, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      reg_nscb_error_loop                               \n"
+        "    vmov.f32 s1, #1.5                                          \n"
+        "    vcmp.f32 s15, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      reg_nscb_error_loop                               \n"
+        "    vmov.f32 s1, #2.0                                          \n"
+        "    vcmp.f32 s16, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      reg_nscb_error_loop                               \n"
+        "    vmov.f32 s1, #3.5                                          \n"
+        "    vcmp.f32 s17, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      reg_nscb_error_loop                               \n"
+        "    vmov.f32 s1, #4.5                                          \n"
+        "    vcmp.f32 s18, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      reg_nscb_error_loop                               \n"
+        "    vmov.f32 s1, #5.0                                          \n"
+        "    vcmp.f32 s19, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      reg_nscb_error_loop                               \n"
+        "    vmov.f32 s1, #6.5                                          \n"
+        "    vcmp.f32 s20, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      reg_nscb_error_loop                               \n"
+        "    vmov.f32 s1, #7.5                                          \n"
+        "    vcmp.f32 s21, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      reg_nscb_error_loop                               \n"
+        "    vmov.f32 s1, #8.0                                          \n"
+        "    vcmp.f32 s22, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      reg_nscb_error_loop                               \n"
+        "    vmov.f32 s1, #9.5                                          \n"
+        "    vcmp.f32 s23, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      reg_nscb_error_loop                               \n"
+        "    vmov.f32 s1, #10.5                                         \n"
+        "    vcmp.f32 s24, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      reg_nscb_error_loop                               \n"
+        "    vmov.f32 s1, #11.0                                         \n"
+        "    vcmp.f32 s25, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      reg_nscb_error_loop                               \n"
+        "    vmov.f32 s1, #12.5                                         \n"
+        "    vcmp.f32 s26, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      reg_nscb_error_loop                               \n"
+        "    vmov.f32 s1, #13.5                                         \n"
+        "    vcmp.f32 s27, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      reg_nscb_error_loop                               \n"
+        "    vmov.f32 s1, #14.0                                         \n"
+        "    vcmp.f32 s28, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      reg_nscb_error_loop                               \n"
+        "    vmov.f32 s1, #1.5                                          \n"
+        "    vcmp.f32 s29, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      reg_nscb_error_loop                               \n"
+        "    vmov.f32 s1, #2.5                                          \n"
+        "    vcmp.f32 s30, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      reg_nscb_error_loop                               \n"
+        "    vmov.f32 s1, #3.0                                          \n"
+        "    vcmp.f32 s31, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      reg_nscb_error_loop                               \n"
+        "                                                               \n"
+        "    /* Everything passed, finish. */                           \n"
+        "    b reg_nscb_success                                         \n"
+        "                                                               \n"
+        "reg_nscb_error_loop:                                           \n"
+        "    /* If this line is hit then there was an error in          \n"
+        "     * a core register value. The loop ensures the             \n"
+        "     * loop counter stops incrementing. */                     \n"
+        "    b reg_nscb_error_loop                                      \n"
+        "    nop                                                        \n"
+        "                                                               \n"
+        "reg_nscb_success:                                              \n"
+        "    /* Restore callee saved registers. */                      \n"
+        "    pop { r4-r12 }                                             \n"
+    );
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Demo/Common/ARMv8M/reg_tests/GCC/ARM_CM33/non_secure/reg_test_asm.h b/FreeRTOS/Demo/Common/ARMv8M/reg_tests/GCC/ARM_CM33/non_secure/reg_test_asm.h
new file mode 100644
index 000000000..e6e7f57d3
--- /dev/null
+++ b/FreeRTOS/Demo/Common/ARMv8M/reg_tests/GCC/ARM_CM33/non_secure/reg_test_asm.h
@@ -0,0 +1,48 @@
+/*
+ * FreeRTOS V202212.00
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef REG_TEST_ASM_H
+#define REG_TEST_ASM_H
+
+/**
+ * @brief Functions that implement reg tests in assembly.
+ *
+ * These are called from the FreeRTOS tasks on the non-secure side.
+ */
+void vRegTest1Asm_NonSecure( void ) __attribute__( ( naked ) );
+void vRegTest2Asm_NonSecure( void ) __attribute__( ( naked ) );
+void vRegTest3Asm_NonSecure( void ) __attribute__( ( naked ) );
+void vRegTest4Asm_NonSecure( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Function that implements reg tests in assembly.
+ *
+ * This is passed as function pointer to the secure side and called
+ * from the secure side.
+ */
+void vRegTestAsm_NonSecureCallback( void );
+
+#endif /* REG_TEST_ASM_H */
diff --git a/FreeRTOS/Demo/Common/ARMv8M/reg_tests/GCC/ARM_CM33/secure/secure_reg_test_asm.c b/FreeRTOS/Demo/Common/ARMv8M/reg_tests/GCC/ARM_CM33/secure/secure_reg_test_asm.c
new file mode 100644
index 000000000..171703180
--- /dev/null
+++ b/FreeRTOS/Demo/Common/ARMv8M/reg_tests/GCC/ARM_CM33/secure/secure_reg_test_asm.c
@@ -0,0 +1,289 @@
+/*
+ * FreeRTOS V202212.00
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+#include <arm_cmse.h>
+
+/* Interface includes. */
+#include "secure_reg_test_asm.h"
+
+/* FreeRTOS includes. */
+#include "secure_port_macros.h"
+
+/* typedef for non-secure callback function. */
+typedef RegTestCallback_t NonSecureRegTestCallback_t __attribute__( ( cmse_nonsecure_call ) );
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void vRegTestAsm_Secure( void )
+{
+    __asm volatile
+    (
+        ".syntax unified                                                \n"
+        "                                                               \n"
+        "    /* Store callee saved registers. */                        \n"
+        "    push { r4-r12 }                                            \n"
+        "                                                               \n"
+        "    /* Fill the core registers with known values. */           \n"
+        "    movs r0, #200                                              \n"
+        "    movs r1, #201                                              \n"
+        "    movs r1, #201                                              \n"
+        "    movs r2, #202                                              \n"
+        "    movs r3, #203                                              \n"
+        "    movs r4, #204                                              \n"
+        "    movs r5, #205                                              \n"
+        "    movs r6, #206                                              \n"
+        "    movs r7, #207                                              \n"
+        "    movs r8, #208                                              \n"
+        "    movs r9, #209                                              \n"
+        "    movs r10, #210                                             \n"
+        "    movs r11, #211                                             \n"
+        "    movs r12, #212                                             \n"
+        "                                                               \n"
+        "    /* Fill the FPU registers with known values. */            \n"
+        "    vmov.f32 s0,  #1.0                                         \n"
+        "    vmov.f32 s2,  #2.0                                         \n"
+        "    vmov.f32 s3,  #3.5                                         \n"
+        "    vmov.f32 s4,  #4.5                                         \n"
+        "    vmov.f32 s5,  #5.0                                         \n"
+        "    vmov.f32 s6,  #6.0                                         \n"
+        "    vmov.f32 s7,  #7.5                                         \n"
+        "    vmov.f32 s8,  #8.5                                         \n"
+        "    vmov.f32 s9,  #9.0                                         \n"
+        "    vmov.f32 s10, #10.0                                        \n"
+        "    vmov.f32 s11, #11.5                                        \n"
+        "    vmov.f32 s12, #12.5                                        \n"
+        "    vmov.f32 s13, #13.0                                        \n"
+        "    vmov.f32 s14, #14.0                                        \n"
+        "    vmov.f32 s15, #1.5                                         \n"
+        "    vmov.f32 s16, #2.5                                         \n"
+        "    vmov.f32 s17, #3.0                                         \n"
+        "    vmov.f32 s18, #4.0                                         \n"
+        "    vmov.f32 s19, #5.5                                         \n"
+        "    vmov.f32 s20, #6.5                                         \n"
+        "    vmov.f32 s21, #7.0                                         \n"
+        "    vmov.f32 s22, #8.0                                         \n"
+        "    vmov.f32 s23, #9.5                                         \n"
+        "    vmov.f32 s24, #10.5                                        \n"
+        "    vmov.f32 s25, #11.0                                        \n"
+        "    vmov.f32 s26, #12.0                                        \n"
+        "    vmov.f32 s27, #13.5                                        \n"
+        "    vmov.f32 s28, #14.5                                        \n"
+        "    vmov.f32 s29, #1.0                                         \n"
+        "    vmov.f32 s30, #2.0                                         \n"
+        "    vmov.f32 s31, #3.5                                         \n"
+        "                                                               \n"
+        "    /* Force a context switch by pending non-secure sv. */     \n"
+        "    push { r0, r1 }                                            \n"
+        "    movs r0, #0x01                                             \n"
+        "    ldr  r1, =0xe002ed04                                       \n" /* NVIC_ICSR_NS. */
+        "    lsls r0, #28                                               \n" /* Shift to PendSV bit. */
+        "    str  r0, [r1]                                              \n"
+        "    dsb                                                        \n"
+        "    pop  { r0, r1 }                                            \n"
+        "                                                               \n"
+        "    /* Verify that core registers contain correct values. */   \n"
+        "    cmp  r0, #200                                              \n"
+        "    bne  secure_reg_test_error_loop                            \n"
+        "    cmp  r1, #201                                              \n"
+        "    bne  secure_reg_test_error_loop                            \n"
+        "    cmp  r2, #202                                              \n"
+        "    bne  secure_reg_test_error_loop                            \n"
+        "    cmp  r3, #203                                              \n"
+        "    bne  secure_reg_test_error_loop                            \n"
+        "    cmp  r4, #204                                              \n"
+        "    bne  secure_reg_test_error_loop                            \n"
+        "    cmp  r5, #205                                              \n"
+        "    bne  secure_reg_test_error_loop                            \n"
+        "    cmp  r6, #206                                              \n"
+        "    bne  secure_reg_test_error_loop                            \n"
+        "    cmp  r7, #207                                              \n"
+        "    bne  secure_reg_test_error_loop                            \n"
+        "    cmp  r8, #208                                              \n"
+        "    bne  secure_reg_test_error_loop                            \n"
+        "    cmp  r9, #209                                              \n"
+        "    bne  secure_reg_test_error_loop                            \n"
+        "    cmp  r10, #210                                             \n"
+        "    bne  secure_reg_test_error_loop                            \n"
+        "    cmp  r11, #211                                             \n"
+        "    bne  secure_reg_test_error_loop                            \n"
+        "    cmp  r12, #212                                             \n"
+        "    bne  secure_reg_test_error_loop                            \n"
+        "                                                               \n"
+        "    /* Verify that FPU registers contain correct values. */    \n"
+        "    vmov.f32 s1, #1.0                                          \n"
+        "    vcmp.f32 s0, s1                                            \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      secure_reg_test_error_loop                        \n"
+        "    vmov.f32 s1, #2.0                                          \n"
+        "    vcmp.f32 s2, s1                                            \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      secure_reg_test_error_loop                        \n"
+        "    vmov.f32 s1, #3.5                                          \n"
+        "    vcmp.f32 s3, s1                                            \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      secure_reg_test_error_loop                        \n"
+        "    vmov.f32 s1, #4.5                                          \n"
+        "    vcmp.f32 s4, s1                                            \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      secure_reg_test_error_loop                        \n"
+        "    vmov.f32 s1, #5.0                                          \n"
+        "    vcmp.f32 s5, s1                                            \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      secure_reg_test_error_loop                        \n"
+        "    vmov.f32 s1, #6.0                                          \n"
+        "    vcmp.f32 s6, s1                                            \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      secure_reg_test_error_loop                        \n"
+        "    vmov.f32 s1, #7.5                                          \n"
+        "    vcmp.f32 s7, s1                                            \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      secure_reg_test_error_loop                        \n"
+        "    vmov.f32 s1, #8.5                                          \n"
+        "    vcmp.f32 s8, s1                                            \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      secure_reg_test_error_loop                        \n"
+        "    vmov.f32 s1, #9.0                                          \n"
+        "    vcmp.f32 s9, s1                                            \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      secure_reg_test_error_loop                        \n"
+        "    vmov.f32 s1, #10.0                                         \n"
+        "    vcmp.f32 s10, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      secure_reg_test_error_loop                        \n"
+        "    vmov.f32 s1, #11.5                                         \n"
+        "    vcmp.f32 s11, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      secure_reg_test_error_loop                        \n"
+        "    vmov.f32 s1, #12.5                                         \n"
+        "    vcmp.f32 s12, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      secure_reg_test_error_loop                        \n"
+        "    vmov.f32 s1, #13.0                                         \n"
+        "    vcmp.f32 s13, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      secure_reg_test_error_loop                        \n"
+        "    vmov.f32 s1, #14.0                                         \n"
+        "    vcmp.f32 s14, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      secure_reg_test_error_loop                        \n"
+        "    vmov.f32 s1, #1.5                                          \n"
+        "    vcmp.f32 s15, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      secure_reg_test_error_loop                        \n"
+        "    vmov.f32 s1, #2.5                                          \n"
+        "    vcmp.f32 s16, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      secure_reg_test_error_loop                        \n"
+        "    vmov.f32 s1, #3.0                                          \n"
+        "    vcmp.f32 s17, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      secure_reg_test_error_loop                        \n"
+        "    vmov.f32 s1, #4.0                                          \n"
+        "    vcmp.f32 s18, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      secure_reg_test_error_loop                        \n"
+        "    vmov.f32 s1, #5.5                                          \n"
+        "    vcmp.f32 s19, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      secure_reg_test_error_loop                        \n"
+        "    vmov.f32 s1, #6.5                                          \n"
+        "    vcmp.f32 s20, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      secure_reg_test_error_loop                        \n"
+        "    vmov.f32 s1, #7.0                                          \n"
+        "    vcmp.f32 s21, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      secure_reg_test_error_loop                        \n"
+        "    vmov.f32 s1, #8.0                                          \n"
+        "    vcmp.f32 s22, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      secure_reg_test_error_loop                        \n"
+        "    vmov.f32 s1, #9.5                                          \n"
+        "    vcmp.f32 s23, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      secure_reg_test_error_loop                        \n"
+        "    vmov.f32 s1, #10.5                                         \n"
+        "    vcmp.f32 s24, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      secure_reg_test_error_loop                        \n"
+        "    vmov.f32 s1, #11.0                                         \n"
+        "    vcmp.f32 s25, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      secure_reg_test_error_loop                        \n"
+        "    vmov.f32 s1, #12.0                                         \n"
+        "    vcmp.f32 s26, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      secure_reg_test_error_loop                        \n"
+        "    vmov.f32 s1, #13.5                                         \n"
+        "    vcmp.f32 s27, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      secure_reg_test_error_loop                        \n"
+        "    vmov.f32 s1, #14.5                                         \n"
+        "    vcmp.f32 s28, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      secure_reg_test_error_loop                        \n"
+        "    vmov.f32 s1, #1.0                                          \n"
+        "    vcmp.f32 s29, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      secure_reg_test_error_loop                        \n"
+        "    vmov.f32 s1, #2.0                                          \n"
+        "    vcmp.f32 s30, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      secure_reg_test_error_loop                        \n"
+        "    vmov.f32 s1, #3.5                                          \n"
+        "    vcmp.f32 s31, s1                                           \n"
+        "    vmrs     APSR_nzcv, FPSCR                                  \n"
+        "    bne      secure_reg_test_error_loop                        \n"
+        "                                                               \n"
+        "    /* Everything passed, finish. */                           \n"
+        "    b secure_reg_test_success                                  \n"
+        "                                                               \n"
+        "secure_reg_test_error_loop:                                    \n"
+        "    /* If this line is hit then there was an error in          \n"
+        "     * a core register value. The loop ensures the             \n"
+        "     * loop counter stops incrementing. */                     \n"
+        "    b secure_reg_test_error_loop                               \n"
+        "    nop                                                        \n"
+        "                                                               \n"
+        "secure_reg_test_success:                                       \n"
+        "    /* Restore callee saved registers. */                      \n"
+        "    pop { r4-r12 }                                             \n"
+    );
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void vRegTest_NonSecureCallback( RegTestCallback_t pxRegTestCallback )
+{
+    NonSecureRegTestCallback_t pxNonSecureRegTestCallback;
+
+    /* Return function pointer with cleared LSB. */
+    pxNonSecureRegTestCallback = ( NonSecureRegTestCallback_t ) cmse_nsfptr_create( pxRegTestCallback );
+
+    /* Invoke the callback which runs reg tests. */
+    pxNonSecureRegTestCallback();
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Demo/Common/ARMv8M/reg_tests/GCC/ARM_CM33/secure/secure_reg_test_asm.h b/FreeRTOS/Demo/Common/ARMv8M/reg_tests/GCC/ARM_CM33/secure/secure_reg_test_asm.h
new file mode 100644
index 000000000..3b59c88d2
--- /dev/null
+++ b/FreeRTOS/Demo/Common/ARMv8M/reg_tests/GCC/ARM_CM33/secure/secure_reg_test_asm.h
@@ -0,0 +1,49 @@
+/*
+ * FreeRTOS V202212.00
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef SECURE_REG_TEST_ASM_H
+#define SECURE_REG_TEST_ASM_H
+
+/* Callback function pointer definition. */
+typedef void ( * RegTestCallback_t )( void );
+
+/**
+ * @brief Function that implements reg tests for the secure side.
+ *
+ * This function is exported as "non-secure callable" and is called
+ * from a FreeRTOS task on the non-secure side.
+ */
+void vRegTestAsm_Secure( void );
+
+/**
+ * @brief Invokes the supplied reg test callback on the non-secure side.
+ *
+ * This function is exported as "non-secure callable" and is called
+ * from a FreeRTOS task on the non-secure side..
+ */
+void vRegTest_NonSecureCallback( RegTestCallback_t pxRegTestCallback );
+
+#endif /* SECURE_REG_TEST_ASM_H */
diff --git a/lexicon.txt b/lexicon.txt
index 90040ec07..aa2c768ce 100644
--- a/lexicon.txt
+++ b/lexicon.txt
@@ -2626,6 +2626,7 @@ subsquent
 succeds
 suicidaltasks
 summarise
+sv
 svc
 svr
 sw