1 files changed, 75 insertions, 2 deletions
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/FreeRTOSDemo_ns.sct b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/FreeRTOSDemo_ns.sct
index bf9373b06..387a8745c 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/FreeRTOSDemo_ns.sct
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/FreeRTOSDemo_ns.sct
@@ -1,3 +1,9 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc
+; command above MUST be in first line (no comment above!)
+
+;Note: Add '-mcmse' to first line if your software model is "Secure Mode".
+;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse
+
 ; NOTE: ARMv8-M MPU requires that each region must start on a 32 byte aligned
 ; address and the size of a region must be a multiple of 32 bytes.
 ;
@@ -19,7 +25,58 @@
 ; |  Unprivileged Data  |
 ;  ---------------------
 
-LR_APP 0x00200000 ; load region
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE      0x00200000
+#define __ROM_SIZE      0x00200000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>
+;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE      0x20200000
+#define __RAM_SIZE      0x00020000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE    0x00000200
+#define __HEAP_SIZE     0x00000C00
+
+/*
+;------------- <<< end of configuration section >>> ---------------------------
+*/
+
+
+/*----------------------------------------------------------------------------
+  User Stack & Heap boundary definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */
+#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */
+
+/* ----------------------------------------------------------------------------
+  Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE   ( 8 )
+#else
+#define __STACKSEAL_SIZE   ( 0 )
+#endif
+
+LR_APP __ROM_BASE __ROM_SIZE ; load region
 {
     ER_IROM_NS_PRIVILEGED +0 ALIGN 32
     {
@@ -50,7 +107,7 @@ LR_APP 0x00200000 ; load region
     {
     }
 
-    ER_IRAM_NS_PRIVILEGED 0x20200000 ALIGN 32
+    ER_IRAM_NS_PRIVILEGED __RAM_BASE ALIGN 32
     {
         *(privileged_data)
     }
@@ -67,4 +124,20 @@ LR_APP 0x00200000 ; load region
     ER_IRAM_NS_UNPRIVILEGED_ALIGN +0 ALIGN 32 EMPTY 0x0
     {
     }
+
+#if __HEAP_SIZE > 0
+	ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE ; Reserve empty region for heap
+	{
+	}
+#endif
+
+	ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE ; Reserve empty region for stack
+	{
+	}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+	STACKSEAL +0 EMPTY __STACKSEAL_SIZE ; Reserve empty region for stack seal immediately after stack
+	{
+	}
+#endif
 }