Final V8.2.1 release ready for tagging:

+ Added MSP432 (ARM Cortex-M4F MSP430!) demos for IAR, Keil and CCS. + Renamed directory containing demo for STM32F7 ARM Cortex-M7. + Renamed directory containing demo for SAMV71 ARM Cortex-M7. + Introduced xTaskNotifyAndQuery(). git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2338 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
author: rtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2> 2015-03-24 15:24:49 +0000
committer: rtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2> 2015-03-24 15:24:49 +0000
commit: 6a044a9948792ca7c04735a3acc6895155395cea (patch)
tree: b5eeb477555eb4eb3a23998e459e75a26e2b8404
parent: f1eee1f450212c4525b896633b3c501b192877dc (diff)
download: freertos-6a044a9948792ca7c04735a3acc6895155395cea.tar.gz
647 files changed, 67785 insertions, 977 deletions
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/.ccsproject b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/.ccsproject
new file mode 100644
index 000000000..e69ed0069
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/.ccsproject
@@ -0,0 +1,16 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<?ccsproject version="1.0"?>
+<projectOptions>
+	<deviceVariant value="MSP432P401R"/>
+	<deviceFamily value="MSP432"/>
+	<deviceEndianness value="little"/>
+	<codegenToolVersion value="5.2.1"/>
+	<isElfFormat value="true"/>
+	<connection value="common/targetdb/connections/TIXDSET_Connection.xml"/>
+	<linkerCommandFile value="msp432p401r.cmd"/>
+	<rts value="libc.a"/>
+	<createSlaveProjects value=""/>
+	<ignoreDefaultDeviceSettings value="true"/>
+	<templateProperties value="id=OutOfBox_MSP432P401R.projectspec.OutOfBox_MSP432P401R,"/>
+	<isTargetManual value="true"/>
+</projectOptions>
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/.cproject b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/.cproject
new file mode 100644
index 000000000..2a946487e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/.cproject
@@ -0,0 +1,281 @@
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diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/.project b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/.project
new file mode 100644
index 000000000..99c7bb65e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/.project
@@ -0,0 +1,341 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>RTOSDemo</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>com.ti.ccstudio.core.ccsNature</nature>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>FreeRTOS_Source</name>
+			<type>2</type>
+			<locationURI>FREERTOS_ROOT/FreeRTOS/Source</locationURI>
+		</link>
+		<link>
+			<name>Full_Demo/FreeRTOS+CLI</name>
+			<type>2</type>
+			<locationURI>FREERTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI</locationURI>
+		</link>
+		<link>
+			<name>Full_Demo/Sample-CLI-commands.c</name>
+			<type>1</type>
+			<locationURI>FREERTOS_ROOT/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/Sample-CLI-commands.c</locationURI>
+		</link>
+		<link>
+			<name>Full_Demo/Standard_Demo_Tasks</name>
+			<type>2</type>
+			<locationURI>FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal</locationURI>
+		</link>
+		<link>
+			<name>Full_Demo/UARTCommandConsole.c</name>
+			<type>1</type>
+			<locationURI>FREERTOS_ROOT/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/UARTCommandConsole.c</locationURI>
+		</link>
+		<link>
+			<name>Full_Demo/Standard_Demo_Tasks/include</name>
+			<type>2</type>
+			<locationURI>FREERTOS_ROOT/FreeRTOS/Demo/Common/include</locationURI>
+		</link>
+	</linkedResources>
+	<filteredResources>
+		<filter>
+			<id>1427193581265</id>
+			<name></name>
+			<type>10</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-settings</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1427193581275</id>
+			<name></name>
+			<type>10</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-IAR_*</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1427193581275</id>
+			<name></name>
+			<type>10</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-Keil_*</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1424106057421</id>
+			<name>Full_Demo</name>
+			<type>6</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-RegTest.s</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1424106057432</id>
+			<name>Full_Demo</name>
+			<type>6</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-RegTest.c</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1424443780710</id>
+			<name>driverlib</name>
+			<type>5</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-cpu.c</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1424443780715</id>
+			<name>driverlib</name>
+			<type>5</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-true-false-cs.c</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1424443780721</id>
+			<name>driverlib</name>
+			<type>5</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-gpio.c</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1424443780726</id>
+			<name>driverlib</name>
+			<type>5</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-interrupt.c</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1424443780730</id>
+			<name>driverlib</name>
+			<type>5</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-pcm.c</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1424443780734</id>
+			<name>driverlib</name>
+			<type>5</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-uart.c</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1424443780739</id>
+			<name>driverlib</name>
+			<type>5</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-wdt_a.c</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1424443780744</id>
+			<name>driverlib</name>
+			<type>5</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-fpu.c</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1424443780748</id>
+			<name>driverlib</name>
+			<type>5</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-timer32.c</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1423578948112</id>
+			<name>system</name>
+			<type>9</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-CCS</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1422884503134</id>
+			<name>FreeRTOS_Source/portable</name>
+			<type>9</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-MemMang</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1422884503144</id>
+			<name>FreeRTOS_Source/portable</name>
+			<type>9</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-CCS</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1424443942773</id>
+			<name>Full_Demo/Standard_Demo_Tasks</name>
+			<type>5</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-sp_flop.c</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1424443942777</id>
+			<name>Full_Demo/Standard_Demo_Tasks</name>
+			<type>5</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-semtest.c</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1424443942782</id>
+			<name>Full_Demo/Standard_Demo_Tasks</name>
+			<type>5</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-true-false-countsem.c</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1424443942787</id>
+			<name>Full_Demo/Standard_Demo_Tasks</name>
+			<type>5</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-GenQTest.c</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1424443942791</id>
+			<name>Full_Demo/Standard_Demo_Tasks</name>
+			<type>5</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-recmutex.c</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1424443942796</id>
+			<name>Full_Demo/Standard_Demo_Tasks</name>
+			<type>5</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-serial.c</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1424443942801</id>
+			<name>Full_Demo/Standard_Demo_Tasks</name>
+			<type>5</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-TimerDemo.c</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1424443942806</id>
+			<name>Full_Demo/Standard_Demo_Tasks</name>
+			<type>5</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-IntQueue.c</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1424443942810</id>
+			<name>Full_Demo/Standard_Demo_Tasks</name>
+			<type>5</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-EventGroupsDemo.c</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1424443942817</id>
+			<name>Full_Demo/Standard_Demo_Tasks</name>
+			<type>5</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-TaskNotify.c</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1424443942823</id>
+			<name>Full_Demo/Standard_Demo_Tasks</name>
+			<type>5</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-IntSemTest.c</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1422884525067</id>
+			<name>FreeRTOS_Source/portable/CCS</name>
+			<type>9</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-ARM_CM4F</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1422884633479</id>
+			<name>FreeRTOS_Source/portable/MemMang</name>
+			<type>5</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-heap_4.c</arguments>
+			</matcher>
+		</filter>
+	</filteredResources>
+	<variableList>
+		<variable>
+			<name>FREERTOS_ROOT</name>
+			<value>$%7BPARENT-3-PROJECT_LOC%7D</value>
+		</variable>
+		<variable>
+			<name>MSPWAREDLIB_ROOT</name>
+			<value>file:/C:/DevTools/ti/msp430/MSP430ware_1_97_00_47/examples/boards/MSP-EXP432P401R/MSP-EXP432P401R_Software_Examples/Source/OutOfBox_MSP432P401R/driverlib/MSP432P4xx</value>
+		</variable>
+	</variableList>
+</projectDescription>
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/.settings/org.eclipse.cdt.codan.core.prefs b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/.settings/org.eclipse.cdt.codan.core.prefs
new file mode 100644
index 000000000..98b635027
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/.settings/org.eclipse.cdt.codan.core.prefs
@@ -0,0 +1,3 @@
+eclipse.preferences.version=1
+inEditor=false
+onBuild=false
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/.settings/org.eclipse.cdt.debug.core.prefs b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/.settings/org.eclipse.cdt.debug.core.prefs
new file mode 100644
index 000000000..58d4fb29d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/.settings/org.eclipse.cdt.debug.core.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+org.eclipse.cdt.debug.core.toggleBreakpointModel=com.ti.ccstudio.debug.CCSBreakpointMarker
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/.settings/org.eclipse.core.resources.prefs b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/.settings/org.eclipse.core.resources.prefs
new file mode 100644
index 000000000..890c0c140
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/.settings/org.eclipse.core.resources.prefs
@@ -0,0 +1,28 @@
+eclipse.preferences.version=1
+encoding//Debug/FreeRTOS_Source/portable/CCS/ARM_CM4F/subdir_rules.mk=UTF-8
+encoding//Debug/FreeRTOS_Source/portable/CCS/ARM_CM4F/subdir_vars.mk=UTF-8
+encoding//Debug/FreeRTOS_Source/portable/MemMang/subdir_rules.mk=UTF-8
+encoding//Debug/FreeRTOS_Source/portable/MemMang/subdir_vars.mk=UTF-8
+encoding//Debug/FreeRTOS_Source/subdir_rules.mk=UTF-8
+encoding//Debug/FreeRTOS_Source/subdir_vars.mk=UTF-8
+encoding//Debug/Full_Demo/FreeRTOS+CLI/subdir_rules.mk=UTF-8
+encoding//Debug/Full_Demo/FreeRTOS+CLI/subdir_vars.mk=UTF-8
+encoding//Debug/Full_Demo/Standard_Demo_Tasks/subdir_rules.mk=UTF-8
+encoding//Debug/Full_Demo/Standard_Demo_Tasks/subdir_vars.mk=UTF-8
+encoding//Debug/Full_Demo/subdir_rules.mk=UTF-8
+encoding//Debug/Full_Demo/subdir_vars.mk=UTF-8
+encoding//Debug/Objects/subdir_rules.mk=UTF-8
+encoding//Debug/Objects/subdir_vars.mk=UTF-8
+encoding//Debug/SimplyBlinkyDemo/subdir_rules.mk=UTF-8
+encoding//Debug/SimplyBlinkyDemo/subdir_vars.mk=UTF-8
+encoding//Debug/SystemFiles_CCS/subdir_rules.mk=UTF-8
+encoding//Debug/SystemFiles_CCS/subdir_vars.mk=UTF-8
+encoding//Debug/driverlib/subdir_rules.mk=UTF-8
+encoding//Debug/driverlib/subdir_vars.mk=UTF-8
+encoding//Debug/makefile=UTF-8
+encoding//Debug/objects.mk=UTF-8
+encoding//Debug/sources.mk=UTF-8
+encoding//Debug/subdir_rules.mk=UTF-8
+encoding//Debug/subdir_vars.mk=UTF-8
+encoding//Debug/system/CCS/subdir_rules.mk=UTF-8
+encoding//Debug/system/CCS/subdir_vars.mk=UTF-8
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/FreeRTOSConfig.h
new file mode 100644
index 000000000..e72cfcf99
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/FreeRTOSConfig.h
@@ -0,0 +1,227 @@
+/*
+    FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+    ***NOTE*** The exception to the GPL is included to allow you to distribute
+    a combined work that includes FreeRTOS without being obliged to provide the
+    source code for proprietary components outside of the FreeRTOS kernel.
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
+    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+    more details. You should have received a copy of the GNU General Public
+    License and the FreeRTOS license exception along with FreeRTOS; if not it
+    can be viewed here: http://www.freertos.org/a00114.html and also obtained
+    by writing to Richard Barry, contact details for whom are available on the
+    FreeRTOS WEB site.
+
+    1 tab == 4 spaces!
+
+    http://www.FreeRTOS.org - Documentation, latest information, license and
+    contact details.
+
+    http://www.SafeRTOS.com - A version that is certified for use in safety
+    critical systems.
+
+    http://www.OpenRTOS.com - Commercial support, development, porting,
+    licensing and training services.
+*/
+
+
+/******************************************************************************
+	See http://www.freertos.org/a00110.html for an explanation of the
+	definitions contained in this file.
+******************************************************************************/
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+
+/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,
+or 0 to run the more comprehensive test and demo application.
+
+The comprehensive demo uses FreeRTOS+CLI to create a simple command line 
+interface through a UART.
+
+The blinky demo uses FreeRTOS's tickless idle mode to reduce power consumption.
+See the notes on the web page below regarding the difference in power saving 
+that can be achieved between using the generic tickless implementation (as used 
+by the blinky demo) and a tickless implementation that is tailored specifically 
+to the MSP432.
+ 
+See http://www.FreeRTOS.org/TI_MSP432_Free_RTOS_Demo.html for instructions. */
+#define configCREATE_SIMPLE_TICKLESS_DEMO	0
+
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ * http://www.freertos.org/a00110.html
+ *----------------------------------------------------------*/
+
+/* Constants related to the behaviour or the scheduler. */
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION	1
+#define configUSE_PREEMPTION					1
+#define configUSE_TIME_SLICING					1
+#define configMAX_PRIORITIES					( 5 )
+#define configIDLE_SHOULD_YIELD					1
+#define configUSE_16_BIT_TICKS					0 /* Only for 8 and 16-bit hardware. */
+
+/* Constants that describe the hardware and memory usage. */
+#define configCPU_CLOCK_HZ						MAP_CS_getMCLK()
+#define configMINIMAL_STACK_SIZE				( ( uint16_t ) 100 )
+#define configMAX_TASK_NAME_LEN					( 12 )
+
+/* Note heap_5.c is used so this only defines the part of the heap that is in
+the first block of RAM on the LPC device.  See the initialisation of the heap
+in main.c. */
+#define configTOTAL_HEAP_SIZE					( ( size_t ) ( 50 * 1024 ) )
+
+/* Constants that build features in or out. */
+#define configUSE_MUTEXES						1
+#define configUSE_TICKLESS_IDLE					1
+#define configUSE_APPLICATION_TASK_TAG			0
+#define configUSE_NEWLIB_REENTRANT 				0
+#define configUSE_CO_ROUTINES 					0
+#define configUSE_COUNTING_SEMAPHORES 			1
+#define configUSE_RECURSIVE_MUTEXES				1
+#define configUSE_QUEUE_SETS					0
+#define configUSE_TASK_NOTIFICATIONS			1
+
+/* Constants that define which hook (callback) functions should be used. */
+#define configUSE_IDLE_HOOK						1
+#define configUSE_TICK_HOOK						1
+#define configUSE_MALLOC_FAILED_HOOK			1
+
+/* Constants provided for debugging and optimisation assistance. */
+#define configCHECK_FOR_STACK_OVERFLOW			2
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
+#define configQUEUE_REGISTRY_SIZE				0
+
+/* Software timer definitions. */
+#define configUSE_TIMERS						1
+#define configTIMER_TASK_PRIORITY				( 3 )
+#define configTIMER_QUEUE_LENGTH				5
+#define configTIMER_TASK_STACK_DEPTH			( configMINIMAL_STACK_SIZE  )
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function.  NOTE:  Setting an INCLUDE_ parameter to 0 is only
+necessary if the linker does not automatically remove functions that are not
+referenced anyway. */
+#define INCLUDE_vTaskPrioritySet				1
+#define INCLUDE_uxTaskPriorityGet				1
+#define INCLUDE_vTaskDelete						1
+#define INCLUDE_vTaskCleanUpResources			0
+#define INCLUDE_vTaskSuspend					1
+#define INCLUDE_vTaskDelayUntil					1
+#define INCLUDE_vTaskDelay						1
+#define INCLUDE_uxTaskGetStackHighWaterMark		0
+#define INCLUDE_pcTaskGetTaskName				1
+#define INCLUDE_xTaskGetIdleTaskHandle			0
+#define INCLUDE_eTaskGetState					1
+#define INCLUDE_xTaskResumeFromISR				0
+#define INCLUDE_xTaskGetCurrentTaskHandle		1
+#define INCLUDE_xTaskGetSchedulerState			0
+#define INCLUDE_xSemaphoreGetMutexHolder		0
+#define INCLUDE_xTimerPendFunctionCall			1
+
+/* This demo makes use of one or more example stats formatting functions.  These
+format the raw data provided by the uxTaskGetSystemState() function in to human
+readable ASCII form.  See the notes in the implementation of vTaskList() within
+FreeRTOS/Source/tasks.c for limitations. */
+#define configUSE_STATS_FORMATTING_FUNCTIONS	1
+
+/* Dimensions a buffer that can be used by the FreeRTOS+CLI command
+interpreter.  See the FreeRTOS+CLI documentation for more information:
+http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_CLI/ */
+#define configCOMMAND_INT_MAX_OUTPUT_SIZE		2048
+
+
+/* Cortex-M3/4 interrupt priority configuration follows...................... */
+
+/* Use the system definition, if there is one. */
+#ifdef __NVIC_PRIO_BITS
+	#define configPRIO_BITS       __NVIC_PRIO_BITS
+#else
+	#define configPRIO_BITS       3     /* 8 priority levels */
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority"
+function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			0x07
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	5
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
+standard names - can't be used with CCS due to limitations in the assemblers
+pre-processing. */
+#ifndef __TI_COMPILER_VERSION__
+	#define xPortPendSVHandler 	PendSV_Handler
+	#define vPortSVCHandler 	SVC_Handler
+	#define xPortSysTickHandler	SysTick_Handler
+#endif
+
+/* The trace facility is turned on to make some functions available for use in
+CLI commands. */
+#define configUSE_TRACE_FACILITY	1
+
+/* Some board specifics.   The LED is on P1.0, configure the pin as output. */
+#define configTOGGLE_LED() 		GPIO_toggleOutputOnPin( GPIO_PORT_P1, GPIO_PIN0 )
+
+/* The #ifdef guards against the file being included from IAR assembly files. */
+#ifndef __IASMARM__
+
+	/* TI driver library includes. */
+	#include <driverlib.h>
+
+	void vPreSleepProcessing( uint32_t ulExpectedIdleTime );
+	#define configPRE_SLEEP_PROCESSING( x ) vPreSleepProcessing( x )
+
+	#if configCREATE_SIMPLE_TICKLESS_DEMO == 1
+
+		/* Constants related to the generation of run time stats.  Run time stats
+		are gathered in the full demo, not the blinky demo. */
+		#define configGENERATE_RUN_TIME_STATS			0
+		#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()
+		#define portGET_RUN_TIME_COUNTER_VALUE()		0
+
+		/* The blinky demo can use a slow tick rate to save power. */
+		#define configTICK_RATE_HZ						( ( TickType_t ) 100 )
+
+	#else
+
+		/* Constants related to the generation of run time stats.  Run time stats
+		are gathered in the full demo, not the blinky demo. */
+		void vConfigureTimerForRunTimeStats( void );
+		uint32_t ulGetRunTimeCounterValue( void );
+		#define configGENERATE_RUN_TIME_STATS	1
+		#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vConfigureTimerForRunTimeStats()
+		#define portGET_RUN_TIME_COUNTER_VALUE() ulGetRunTimeCounterValue()
+
+		/* Some of the tests in the full demo expecte a 1ms tick rate. */
+		#define configTICK_RATE_HZ						( ( TickType_t ) 1000 )
+
+	#endif /* configCREATE_SIMPLE_TICKLESS_DEMO */
+#endif /* __IASMARM__ */
+
+#endif /* FREERTOS_CONFIG_H */
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/IntQueueTimer.c
new file mode 100644
index 000000000..4dc996d18
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/IntQueueTimer.c
@@ -0,0 +1,135 @@
+/*
+    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/*
+ * This file initialises the two timers available in the Timer32 peripheral.
+ *
+ * Channels 0 and 1 provide the interrupts that are used with the IntQ
+ * standard demo tasks, which test interrupt nesting and using queues from
+ * interrupts.
+ */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* Demo includes. */
+#include "IntQueueTimer.h"
+#include "IntQueue.h"
+
+/* The frequencies at which the two timers expire are slightly offset to ensure
+they don't remain synchronised. */
+#define tmrTIMER_0_FREQUENCY	( 2000UL )
+#define tmrTIMER_1_FREQUENCY	( 2003UL )
+
+/* The interrupts use the FreeRTOS API so must be at or below the max syscall
+interrupt priority.  Counter-intuitively, the higher the numeric number the
+lower the logical priority. http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+#define tmrLOWER_PRIORITY		( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define tmrHIGHER_PRIORITY		( configMAX_SYSCALL_INTERRUPT_PRIORITY + 1 )
+/*-----------------------------------------------------------*/
+
+/* Handlers for the two timer peripherals - two channels are used in the TC0
+timer. */
+void vT32_0_Handler( void );
+void vT32_1_Handler( void );
+
+/*-----------------------------------------------------------*/
+
+void vInitialiseTimerForIntQueueTest( void )
+{
+    /* Configure the timer channels. */
+	MAP_Timer32_initModule( TIMER32_0_MODULE, TIMER32_PRESCALER_1, TIMER32_32BIT, TIMER32_PERIODIC_MODE );
+	MAP_Timer32_setCount( TIMER32_0_MODULE, CS_getMCLK() / tmrTIMER_0_FREQUENCY );
+	MAP_Timer32_enableInterrupt( TIMER32_0_MODULE );
+	MAP_Timer32_startTimer( TIMER32_0_MODULE, false );
+	MAP_Interrupt_setPriority( INT_T32_INT1, tmrLOWER_PRIORITY );
+	MAP_Interrupt_enableInterrupt( INT_T32_INT1 );
+
+	MAP_Timer32_initModule( TIMER32_1_MODULE, TIMER32_PRESCALER_1, TIMER32_32BIT, TIMER32_PERIODIC_MODE );
+	MAP_Timer32_setCount( TIMER32_1_MODULE, CS_getMCLK() / tmrTIMER_1_FREQUENCY );
+	MAP_Timer32_enableInterrupt( TIMER32_1_MODULE );
+	MAP_Timer32_startTimer( TIMER32_1_MODULE, false );
+	MAP_Interrupt_setPriority( INT_T32_INT2, tmrHIGHER_PRIORITY );
+	MAP_Interrupt_enableInterrupt( INT_T32_INT2 );
+}
+/*-----------------------------------------------------------*/
+
+void vT32_0_Handler( void )
+{
+    MAP_Timer32_clearInterruptFlag( TIMER32_0_MODULE );
+	portYIELD_FROM_ISR( xFirstTimerHandler() );
+}
+/*-----------------------------------------------------------*/
+
+void vT32_1_Handler( void )
+{
+    MAP_Timer32_clearInterruptFlag( TIMER32_1_MODULE );
+	portYIELD_FROM_ISR( xSecondTimerHandler() );
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/IntQueueTimer.h
index 528e6fdfb..528e6fdfb 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/Full_Demo/IntQueueTimer.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/IntQueueTimer.h
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/RegTest.asm b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/RegTest.asm
new file mode 100644
index 000000000..0b6cd78e8
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/RegTest.asm
@@ -0,0 +1,454 @@
+;/*
+;    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
+;    All rights reserved
+;
+;    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+;
+;    This file is part of the FreeRTOS distribution.
+;
+;    FreeRTOS is free software; you can redistribute it and/or modify it under
+;    the terms of the GNU General Public License (version 2) as published by the
+;    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+;
+;    ***************************************************************************
+;    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+;    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+;    >>!   obliged to provide the source code for proprietary components     !<<
+;    >>!   outside of the FreeRTOS kernel.                                   !<<
+;    ***************************************************************************
+;
+;    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+;    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+;    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+;    link: http://www.freertos.org/a00114.html
+;
+;    ***************************************************************************
+;     *                                                                       *
+;     *    FreeRTOS provides completely free yet professionally developed,    *
+;     *    robust, strictly quality controlled, supported, and cross          *
+;     *    platform software that is more than just the market leader, it     *
+;     *    is the industry's de facto standard.                               *
+;     *                                                                       *
+;     *    Help yourself get started quickly while simultaneously helping     *
+;     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+;     *    tutorial book, reference manual, or both:                          *
+;     *    http://www.FreeRTOS.org/Documentation                              *
+;     *                                                                       *
+;    ***************************************************************************
+;
+;    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+;    the FAQ page "My application does not run, what could be wrong?".  Have you
+;    defined configASSERT()?
+;
+;    http://www.FreeRTOS.org/support - In return for receiving this top quality
+;    embedded software for free we request you assist our global community by
+;    participating in the support forum.
+;
+;    http://www.FreeRTOS.org/training - Investing in training allows your team to
+;    be as productive as possible as early as possible.  Now you can receive
+;    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+;    Ltd, and the world's leading authority on the world's leading RTOS.
+;
+;    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+;    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+;    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+;
+;    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+;    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+;
+;    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+;    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+;    licenses offer ticketed support, indemnification and commercial middleware.
+;
+;    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+;    engineered and independently SIL3 certified version for use in safety and
+;    mission critical applications that require provable dependability.
+;
+;    1 tab == 4 spaces!
+;*/
+
+
+	.thumb
+
+	.ref ulRegTest1LoopCounter
+	.ref ulRegTest2LoopCounter
+
+	.def vRegTest1Implementation
+	.def vRegTest2Implementation
+
+ulRegTest1LoopCounterConst:	.word	ulRegTest1LoopCounter
+ulRegTest2LoopCounterConst:	.word	ulRegTest2LoopCounter
+ulNVIC_INT_CTRL:			.word 	0xe000ed04
+;/*-----------------------------------------------------------*/
+	.align 4
+vRegTest1Implementation: .asmfunc
+
+	;/* Fill the core registers with known values. */
+	mov r0, #100
+	mov r1, #101
+	mov r2, #102
+	mov r3, #103
+	mov	r4, #104
+	mov	r5, #105
+	mov	r6, #106
+	mov r7, #107
+	mov	r8, #108
+	mov	r9, #109
+	mov	r10, #110
+	mov	r11, #111
+	mov r12, #112
+
+	;/* Fill the VFP registers with known values. */
+	vmov d0, r0, r1
+	vmov d1, r2, r3
+	vmov d2, r4, r5
+	vmov d3, r6, r7
+	vmov d4, r8, r9
+	vmov d5, r10, r11
+	vmov d6, r0, r1
+	vmov d7, r2, r3
+	vmov d8, r4, r5
+	vmov d9, r6, r7
+	vmov d10, r8, r9
+	vmov d11, r10, r11
+	vmov d12, r0, r1
+	vmov d13, r2, r3
+	vmov d14, r4, r5
+	vmov d15, r6, r7
+
+reg1_loop:
+	;/* Check all the VFP registers still contain the values set above.
+	;First save registers that are clobbered by the test. */
+	push { r0-r1 }
+
+	vmov r0, r1, d0
+	cmp r0, #100
+	bne reg1_error_loopf
+	cmp r1, #101
+	bne reg1_error_loopf
+	vmov r0, r1, d1
+	cmp r0, #102
+	bne reg1_error_loopf
+	cmp r1, #103
+	bne reg1_error_loopf
+	vmov r0, r1, d2
+	cmp r0, #104
+	bne reg1_error_loopf
+	cmp r1, #105
+	bne reg1_error_loopf
+	vmov r0, r1, d3
+	cmp r0, #106
+	bne reg1_error_loopf
+	cmp r1, #107
+	bne reg1_error_loopf
+	vmov r0, r1, d4
+	cmp r0, #108
+	bne reg1_error_loopf
+	cmp r1, #109
+	bne reg1_error_loopf
+	vmov r0, r1, d5
+	cmp r0, #110
+	bne reg1_error_loopf
+	cmp r1, #111
+	bne reg1_error_loopf
+	vmov r0, r1, d6
+	cmp r0, #100
+	bne reg1_error_loopf
+	cmp r1, #101
+	bne reg1_error_loopf
+	vmov r0, r1, d7
+	cmp r0, #102
+	bne reg1_error_loopf
+	cmp r1, #103
+	bne reg1_error_loopf
+	vmov r0, r1, d8
+	cmp r0, #104
+	bne reg1_error_loopf
+	cmp r1, #105
+	bne reg1_error_loopf
+	vmov r0, r1, d9
+	cmp r0, #106
+	bne reg1_error_loopf
+	cmp r1, #107
+	bne reg1_error_loopf
+	vmov r0, r1, d10
+	cmp r0, #108
+	bne reg1_error_loopf
+	cmp r1, #109
+	bne reg1_error_loopf
+	vmov r0, r1, d11
+	cmp r0, #110
+	bne reg1_error_loopf
+	cmp r1, #111
+	bne reg1_error_loopf
+	vmov r0, r1, d12
+	cmp r0, #100
+	bne reg1_error_loopf
+	cmp r1, #101
+	bne reg1_error_loopf
+	vmov r0, r1, d13
+	cmp r0, #102
+	bne reg1_error_loopf
+	cmp r1, #103
+	bne reg1_error_loopf
+	vmov r0, r1, d14
+	cmp r0, #104
+	bne reg1_error_loopf
+	cmp r1, #105
+	bne reg1_error_loopf
+	vmov r0, r1, d15
+	cmp r0, #106
+	bne reg1_error_loopf
+	cmp r1, #107
+	bne reg1_error_loopf
+
+	;/* Restore the registers that were clobbered by the test. */
+	pop {r0-r1}
+
+	;/* VFP register test passed.  Jump to the core register test. */
+	b reg1_loopf_pass
+
+reg1_error_loopf:
+	;/* If this line is hit then a VFP register value was found to be
+	;incorrect. */
+	b reg1_error_loopf
+
+reg1_loopf_pass:
+
+	cmp	r0, #100
+	bne	reg1_error_loop
+	cmp	r1, #101
+	bne	reg1_error_loop
+	cmp	r2, #102
+	bne	reg1_error_loop
+	cmp r3, #103
+	bne	reg1_error_loop
+	cmp	r4, #104
+	bne	reg1_error_loop
+	cmp	r5, #105
+	bne	reg1_error_loop
+	cmp	r6, #106
+	bne	reg1_error_loop
+	cmp	r7, #107
+	bne	reg1_error_loop
+	cmp	r8, #108
+	bne	reg1_error_loop
+	cmp	r9, #109
+	bne	reg1_error_loop
+	cmp	r10, #110
+	bne	reg1_error_loop
+	cmp	r11, #111
+	bne	reg1_error_loop
+	cmp	r12, #112
+	bne	reg1_error_loop
+
+	;/* Everything passed, increment the loop counter. */
+	push { r0-r1 }
+	ldr	r0, ulRegTest1LoopCounterConst
+	ldr r1, [r0]
+	adds r1, r1, #1
+	str r1, [r0]
+	pop { r0-r1 }
+
+	;/* Start again. */
+	b reg1_loop
+
+reg1_error_loop:
+	;/* If this line is hit then there was an error in a core register value.
+	;The loop ensures the loop counter stops incrementing. */
+	b reg1_error_loop
+	.endasmfunc
+
+;/*-----------------------------------------------------------*/
+
+	.align 4
+vRegTest2Implementation: .asmfunc
+
+	;/* Set all the core registers to known values. */
+	mov r0, #-1
+	mov r1, #1
+	mov r2, #2
+	mov r3, #3
+	mov	r4, #4
+	mov	r5, #5
+	mov	r6, #6
+	mov r7, #7
+	mov	r8, #8
+	mov	r9, #9
+	mov	r10, #10
+	mov	r11, #11
+	mov r12, #12
+
+	;/* Set all the VFP to known values. */
+	vmov d0, r0, r1
+	vmov d1, r2, r3
+	vmov d2, r4, r5
+	vmov d3, r6, r7
+	vmov d4, r8, r9
+	vmov d5, r10, r11
+	vmov d6, r0, r1
+	vmov d7, r2, r3
+	vmov d8, r4, r5
+	vmov d9, r6, r7
+	vmov d10, r8, r9
+	vmov d11, r10, r11
+	vmov d12, r0, r1
+	vmov d13, r2, r3
+	vmov d14, r4, r5
+	vmov d15, r6, r7
+
+reg2_loop:
+
+	;/* Check all the VFP registers still contain the values set above.
+	;First save registers that are clobbered by the test. */
+	push { r0-r1 }
+
+	vmov r0, r1, d0
+	cmp r0, #-1
+	bne reg2_error_loopf
+	cmp r1, #1
+	bne reg2_error_loopf
+	vmov r0, r1, d1
+	cmp r0, #2
+	bne reg2_error_loopf
+	cmp r1, #3
+	bne reg2_error_loopf
+	vmov r0, r1, d2
+	cmp r0, #4
+	bne reg2_error_loopf
+	cmp r1, #5
+	bne reg2_error_loopf
+	vmov r0, r1, d3
+	cmp r0, #6
+	bne reg2_error_loopf
+	cmp r1, #7
+	bne reg2_error_loopf
+	vmov r0, r1, d4
+	cmp r0, #8
+	bne reg2_error_loopf
+	cmp r1, #9
+	bne reg2_error_loopf
+	vmov r0, r1, d5
+	cmp r0, #10
+	bne reg2_error_loopf
+	cmp r1, #11
+	bne reg2_error_loopf
+	vmov r0, r1, d6
+	cmp r0, #-1
+	bne reg2_error_loopf
+	cmp r1, #1
+	bne reg2_error_loopf
+	vmov r0, r1, d7
+	cmp r0, #2
+	bne reg2_error_loopf
+	cmp r1, #3
+	bne reg2_error_loopf
+	vmov r0, r1, d8
+	cmp r0, #4
+	bne reg2_error_loopf
+	cmp r1, #5
+	bne reg2_error_loopf
+	vmov r0, r1, d9
+	cmp r0, #6
+	bne reg2_error_loopf
+	cmp r1, #7
+	bne reg2_error_loopf
+	vmov r0, r1, d10
+	cmp r0, #8
+	bne reg2_error_loopf
+	cmp r1, #9
+	bne reg2_error_loopf
+	vmov r0, r1, d11
+	cmp r0, #10
+	bne reg2_error_loopf
+	cmp r1, #11
+	bne reg2_error_loopf
+	vmov r0, r1, d12
+	cmp r0, #-1
+	bne reg2_error_loopf
+	cmp r1, #1
+	bne reg2_error_loopf
+	vmov r0, r1, d13
+	cmp r0, #2
+	bne reg2_error_loopf
+	cmp r1, #3
+	bne reg2_error_loopf
+	vmov r0, r1, d14
+	cmp r0, #4
+	bne reg2_error_loopf
+	cmp r1, #5
+	bne reg2_error_loopf
+	vmov r0, r1, d15
+	cmp r0, #6
+	bne reg2_error_loopf
+	cmp r1, #7
+	bne reg2_error_loopf
+
+	;/* Restore the registers that were clobbered by the test. */
+	pop {r0-r1}
+
+	;/* VFP register test passed.  Jump to the core register test. */
+	b reg2_loopf_pass
+
+reg2_error_loopf
+	;/* If this line is hit then a VFP register value was found to be
+	;incorrect. */
+	b reg2_error_loopf
+
+reg2_loopf_pass
+
+	cmp	r0, #-1
+	bne	reg2_error_loop
+	cmp	r1, #1
+	bne	reg2_error_loop
+	cmp	r2, #2
+	bne	reg2_error_loop
+	cmp r3, #3
+	bne	reg2_error_loop
+	cmp	r4, #4
+	bne	reg2_error_loop
+	cmp	r5, #5
+	bne	reg2_error_loop
+	cmp	r6, #6
+	bne	reg2_error_loop
+	cmp	r7, #7
+	bne	reg2_error_loop
+	cmp	r8, #8
+	bne	reg2_error_loop
+	cmp	r9, #9
+	bne	reg2_error_loop
+	cmp	r10, #10
+	bne	reg2_error_loop
+	cmp	r11, #11
+	bne	reg2_error_loop
+	cmp	r12, #12
+	bne	reg2_error_loop
+
+	;/* Increment the loop counter to indicate this test is still functioning
+	;correctly. */
+	push { r0-r1 }
+	ldr	r0, ulRegTest2LoopCounterConst
+	ldr r1, [r0]
+	adds r1, r1, #1
+	str r1, [r0]
+
+	;/* Yield to increase test coverage. */
+	movs r0, #0x01
+	ldr r1, ulNVIC_INT_CTRL
+	lsl r0, r0, #28 ;/* Shift to PendSV bit */
+	str r0, [r1]
+	dsb
+
+	pop { r0-r1 }
+
+	;/* Start again. */
+	b reg2_loop
+
+reg2_error_loop:
+	;/* If this line is hit then there was an error in a core register value.
+	;This loop ensures the loop counter variable stops incrementing. */
+	b reg2_error_loop
+
+;/*-----------------------------------------------------------*/
+
+	.end
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/RegTest.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/RegTest.c
new file mode 100644
index 000000000..b90eacf29
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/RegTest.c
@@ -0,0 +1,525 @@
+/*
+    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+
+__asm vRegTest1Implementation( void )
+{
+	PRESERVE8
+	IMPORT ulRegTest1LoopCounter
+
+	/* Fill the core registers with known values. */
+	mov r0, #100
+	mov r1, #101
+	mov r2, #102
+	mov r3, #103
+	mov	r4, #104
+	mov	r5, #105
+	mov	r6, #106
+	mov r7, #107
+	mov	r8, #108
+	mov	r9, #109
+	mov	r10, #110
+	mov	r11, #111
+	mov r12, #112
+
+	/* Fill the VFP registers with known values. */
+	vmov d0, r0, r1
+	vmov d1, r2, r3
+	vmov d2, r4, r5
+	vmov d3, r6, r7
+	vmov d4, r8, r9
+	vmov d5, r10, r11
+	vmov d6, r0, r1
+	vmov d7, r2, r3
+	vmov d8, r4, r5
+	vmov d9, r6, r7
+	vmov d10, r8, r9
+	vmov d11, r10, r11
+	vmov d12, r0, r1
+	vmov d13, r2, r3
+	vmov d14, r4, r5
+	vmov d15, r6, r7
+
+reg1_loop
+	/* Check all the VFP registers still contain the values set above.
+	First save registers that are clobbered by the test. */
+	push { r0-r1 }
+	
+	vmov r0, r1, d0
+	cmp r0, #100
+	bne reg1_error_loopf
+	cmp r1, #101
+	bne reg1_error_loopf
+	vmov r0, r1, d1
+	cmp r0, #102
+	bne reg1_error_loopf
+	cmp r1, #103
+	bne reg1_error_loopf
+	vmov r0, r1, d2
+	cmp r0, #104
+	bne reg1_error_loopf
+	cmp r1, #105
+	bne reg1_error_loopf
+	vmov r0, r1, d3
+	cmp r0, #106
+	bne reg1_error_loopf
+	cmp r1, #107
+	bne reg1_error_loopf
+	vmov r0, r1, d4
+	cmp r0, #108
+	bne reg1_error_loopf
+	cmp r1, #109
+	bne reg1_error_loopf
+	vmov r0, r1, d5
+	cmp r0, #110
+	bne reg1_error_loopf
+	cmp r1, #111
+	bne reg1_error_loopf
+	vmov r0, r1, d6
+	cmp r0, #100
+	bne reg1_error_loopf
+	cmp r1, #101
+	bne reg1_error_loopf
+	vmov r0, r1, d7
+	cmp r0, #102
+	bne reg1_error_loopf
+	cmp r1, #103
+	bne reg1_error_loopf
+	vmov r0, r1, d8
+	cmp r0, #104
+	bne reg1_error_loopf
+	cmp r1, #105
+	bne reg1_error_loopf
+	vmov r0, r1, d9
+	cmp r0, #106
+	bne reg1_error_loopf
+	cmp r1, #107
+	bne reg1_error_loopf
+	vmov r0, r1, d10
+	cmp r0, #108
+	bne reg1_error_loopf
+	cmp r1, #109
+	bne reg1_error_loopf
+	vmov r0, r1, d11
+	cmp r0, #110
+	bne reg1_error_loopf
+	cmp r1, #111
+	bne reg1_error_loopf
+	vmov r0, r1, d12
+	cmp r0, #100
+	bne reg1_error_loopf
+	cmp r1, #101
+	bne reg1_error_loopf
+	vmov r0, r1, d13
+	cmp r0, #102
+	bne reg1_error_loopf
+	cmp r1, #103
+	bne reg1_error_loopf
+	vmov r0, r1, d14
+	cmp r0, #104
+	bne reg1_error_loopf
+	cmp r1, #105
+	bne reg1_error_loopf
+	vmov r0, r1, d15
+	cmp r0, #106
+	bne reg1_error_loopf
+	cmp r1, #107
+	bne reg1_error_loopf
+	
+	/* Restore the registers that were clobbered by the test. */
+	pop {r0-r1}
+	
+	/* VFP register test passed.  Jump to the core register test. */
+	b reg1_loopf_pass
+
+reg1_error_loopf
+	/* If this line is hit then a VFP register value was found to be
+	incorrect. */
+	b reg1_error_loopf
+
+reg1_loopf_pass
+
+	cmp	r0, #100
+	bne	reg1_error_loop
+	cmp	r1, #101
+	bne	reg1_error_loop
+	cmp	r2, #102
+	bne	reg1_error_loop
+	cmp r3, #103
+	bne	reg1_error_loop
+	cmp	r4, #104
+	bne	reg1_error_loop
+	cmp	r5, #105
+	bne	reg1_error_loop
+	cmp	r6, #106
+	bne	reg1_error_loop
+	cmp	r7, #107
+	bne	reg1_error_loop
+	cmp	r8, #108
+	bne	reg1_error_loop
+	cmp	r9, #109
+	bne	reg1_error_loop
+	cmp	r10, #110
+	bne	reg1_error_loop
+	cmp	r11, #111
+	bne	reg1_error_loop
+	cmp	r12, #112
+	bne	reg1_error_loop
+	
+	/* Everything passed, increment the loop counter. */
+	push { r0-r1 }
+	ldr	r0, =ulRegTest1LoopCounter
+	ldr r1, [r0]
+	adds r1, r1, #1
+	str r1, [r0]
+	pop { r0-r1 }
+	
+	/* Start again. */
+	b reg1_loop
+
+reg1_error_loop
+	/* If this line is hit then there was an error in a core register value.
+	The loop ensures the loop counter stops incrementing. */
+	b reg1_error_loop
+	nop
+}
+/*-----------------------------------------------------------*/
+
+__asm vRegTest2Implementation( void )
+{
+	PRESERVE8
+	IMPORT ulRegTest2LoopCounter
+
+	/* Set all the core registers to known values. */
+	mov r0, #-1
+	mov r1, #1
+	mov r2, #2
+	mov r3, #3
+	mov	r4, #4
+	mov	r5, #5
+	mov	r6, #6
+	mov r7, #7
+	mov	r8, #8
+	mov	r9, #9
+	mov	r10, #10
+	mov	r11, #11
+	mov r12, #12
+
+	/* Set all the VFP to known values. */
+	vmov d0, r0, r1
+	vmov d1, r2, r3
+	vmov d2, r4, r5
+	vmov d3, r6, r7
+	vmov d4, r8, r9
+	vmov d5, r10, r11
+	vmov d6, r0, r1
+	vmov d7, r2, r3
+	vmov d8, r4, r5
+	vmov d9, r6, r7
+	vmov d10, r8, r9
+	vmov d11, r10, r11
+	vmov d12, r0, r1
+	vmov d13, r2, r3
+	vmov d14, r4, r5
+	vmov d15, r6, r7
+
+reg2_loop
+	
+	/* Check all the VFP registers still contain the values set above.
+	First save registers that are clobbered by the test. */
+	push { r0-r1 }
+	
+	vmov r0, r1, d0
+	cmp r0, #-1
+	bne reg2_error_loopf
+	cmp r1, #1
+	bne reg2_error_loopf
+	vmov r0, r1, d1
+	cmp r0, #2
+	bne reg2_error_loopf
+	cmp r1, #3
+	bne reg2_error_loopf
+	vmov r0, r1, d2
+	cmp r0, #4
+	bne reg2_error_loopf
+	cmp r1, #5
+	bne reg2_error_loopf
+	vmov r0, r1, d3
+	cmp r0, #6
+	bne reg2_error_loopf
+	cmp r1, #7
+	bne reg2_error_loopf
+	vmov r0, r1, d4
+	cmp r0, #8
+	bne reg2_error_loopf
+	cmp r1, #9
+	bne reg2_error_loopf
+	vmov r0, r1, d5
+	cmp r0, #10
+	bne reg2_error_loopf
+	cmp r1, #11
+	bne reg2_error_loopf
+	vmov r0, r1, d6
+	cmp r0, #-1
+	bne reg2_error_loopf
+	cmp r1, #1
+	bne reg2_error_loopf
+	vmov r0, r1, d7
+	cmp r0, #2
+	bne reg2_error_loopf
+	cmp r1, #3
+	bne reg2_error_loopf
+	vmov r0, r1, d8
+	cmp r0, #4
+	bne reg2_error_loopf
+	cmp r1, #5
+	bne reg2_error_loopf
+	vmov r0, r1, d9
+	cmp r0, #6
+	bne reg2_error_loopf
+	cmp r1, #7
+	bne reg2_error_loopf
+	vmov r0, r1, d10
+	cmp r0, #8
+	bne reg2_error_loopf
+	cmp r1, #9
+	bne reg2_error_loopf
+	vmov r0, r1, d11
+	cmp r0, #10
+	bne reg2_error_loopf
+	cmp r1, #11
+	bne reg2_error_loopf
+	vmov r0, r1, d12
+	cmp r0, #-1
+	bne reg2_error_loopf
+	cmp r1, #1
+	bne reg2_error_loopf
+	vmov r0, r1, d13
+	cmp r0, #2
+	bne reg2_error_loopf
+	cmp r1, #3
+	bne reg2_error_loopf
+	vmov r0, r1, d14
+	cmp r0, #4
+	bne reg2_error_loopf
+	cmp r1, #5
+	bne reg2_error_loopf
+	vmov r0, r1, d15
+	cmp r0, #6
+	bne reg2_error_loopf
+	cmp r1, #7
+	bne reg2_error_loopf
+	
+	/* Restore the registers that were clobbered by the test. */
+	pop {r0-r1}
+	
+	/* VFP register test passed.  Jump to the core register test. */
+	b reg2_loopf_pass
+
+reg2_error_loopf
+	/* If this line is hit then a VFP register value was found to be
+	incorrect. */
+	b reg2_error_loopf
+
+reg2_loopf_pass
+
+	cmp	r0, #-1
+	bne	reg2_error_loop
+	cmp	r1, #1
+	bne	reg2_error_loop
+	cmp	r2, #2
+	bne	reg2_error_loop
+	cmp r3, #3
+	bne	reg2_error_loop
+	cmp	r4, #4
+	bne	reg2_error_loop
+	cmp	r5, #5
+	bne	reg2_error_loop
+	cmp	r6, #6
+	bne	reg2_error_loop
+	cmp	r7, #7
+	bne	reg2_error_loop
+	cmp	r8, #8
+	bne	reg2_error_loop
+	cmp	r9, #9
+	bne	reg2_error_loop
+	cmp	r10, #10
+	bne	reg2_error_loop
+	cmp	r11, #11
+	bne	reg2_error_loop
+	cmp	r12, #12
+	bne	reg2_error_loop
+	
+	/* Increment the loop counter to indicate this test is still functioning
+	correctly. */
+	push { r0-r1 }
+	ldr	r0, =ulRegTest2LoopCounter
+	ldr r1, [r0]
+	adds r1, r1, #1
+	str r1, [r0]
+	
+	/* Yield to increase test coverage. */
+	movs r0, #0x01
+	ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */
+	lsl r0, r0, #28 /* Shift to PendSV bit */
+	str r0, [r1]
+	dsb
+	
+	pop { r0-r1 }
+	
+	/* Start again. */
+	b reg2_loop
+
+reg2_error_loop
+	/* If this line is hit then there was an error in a core register value.
+	This loop ensures the loop counter variable stops incrementing. */
+	b reg2_error_loop
+}
+/*-----------------------------------------------------------*/
+
+__asm vRegTestClearFlopRegistersToParameterValue( unsigned long ulValue	)
+{
+	PRESERVE8
+
+	/* Clobber the auto saved registers. */
+	vmov d0, r0, r0
+	vmov d1, r0, r0
+	vmov d2, r0, r0
+	vmov d3, r0, r0
+	vmov d4, r0, r0
+	vmov d5, r0, r0
+	vmov d6, r0, r0
+	vmov d7, r0, r0
+	bx lr
+}
+/*-----------------------------------------------------------*/
+
+__asm ulRegTestCheckFlopRegistersContainParameterValue( unsigned long ulValue )
+{
+	PRESERVE8
+
+	vmov r1, s0
+	cmp r0, r1
+	bne return_error
+	vmov r1, s1
+	cmp r0, r1
+	bne return_error
+	vmov r1, s2
+	cmp r0, r1
+	bne return_error
+	vmov r1, s3
+	cmp r0, r1
+	bne return_error
+	vmov r1, s4
+	cmp r0, r1
+	bne return_error
+	vmov r1, s5
+	cmp r0, r1
+	bne return_error
+	vmov r1, s6
+	cmp r0, r1
+	bne return_error
+	vmov r1, s7
+	cmp r0, r1
+	bne return_error
+	vmov r1, s8
+	cmp r0, r1
+	bne return_error
+	vmov r1, s9
+	cmp r0, r1
+	bne return_error
+	vmov r1, s10
+	cmp r0, r1
+	bne return_error
+	vmov r1, s11
+	cmp r0, r1
+	bne return_error
+	vmov r1, s12
+	cmp r0, r1
+	bne return_error
+	vmov r1, s13
+	cmp r0, r1
+	bne return_error
+	vmov r1, s14
+	cmp r0, r1
+	bne return_error
+	vmov r1, s15
+	cmp r0, r1
+	bne return_error
+	
+return_pass
+	mov r0, #1
+	bx lr
+
+return_error
+	mov r0, #0
+	bx lr
+}
+
+	
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/RegTest.s b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/RegTest.s
new file mode 100644
index 000000000..00e16e8df
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/RegTest.s
@@ -0,0 +1,528 @@
+/*
+    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+#include <FreeRTOSConfig.h>
+
+
+	RSEG    CODE:CODE(2)
+	thumb
+
+	EXTERN ulRegTest1LoopCounter
+	EXTERN ulRegTest2LoopCounter
+
+	PUBLIC vRegTest1Implementation
+	PUBLIC vRegTest2Implementation
+
+/*-----------------------------------------------------------*/
+
+vRegTest1Implementation
+
+	/* Fill the core registers with known values. */
+	mov r0, #100
+	mov r1, #101
+	mov r2, #102
+	mov r3, #103
+	mov	r4, #104
+	mov	r5, #105
+	mov	r6, #106
+	mov r7, #107
+	mov	r8, #108
+	mov	r9, #109
+	mov	r10, #110
+	mov	r11, #111
+	mov r12, #112
+
+	/* Fill the VFP registers with known values. */
+	vmov d0, r0, r1
+	vmov d1, r2, r3
+	vmov d2, r4, r5
+	vmov d3, r6, r7
+	vmov d4, r8, r9
+	vmov d5, r10, r11
+	vmov d6, r0, r1
+	vmov d7, r2, r3
+	vmov d8, r4, r5
+	vmov d9, r6, r7
+	vmov d10, r8, r9
+	vmov d11, r10, r11
+	vmov d12, r0, r1
+	vmov d13, r2, r3
+	vmov d14, r4, r5
+	vmov d15, r6, r7
+
+reg1_loop:
+	/* Check all the VFP registers still contain the values set above.
+	First save registers that are clobbered by the test. */
+	push { r0-r1 }
+
+	vmov r0, r1, d0
+	cmp r0, #100
+	bne reg1_error_loopf
+	cmp r1, #101
+	bne reg1_error_loopf
+	vmov r0, r1, d1
+	cmp r0, #102
+	bne reg1_error_loopf
+	cmp r1, #103
+	bne reg1_error_loopf
+	vmov r0, r1, d2
+	cmp r0, #104
+	bne reg1_error_loopf
+	cmp r1, #105
+	bne reg1_error_loopf
+	vmov r0, r1, d3
+	cmp r0, #106
+	bne reg1_error_loopf
+	cmp r1, #107
+	bne reg1_error_loopf
+	vmov r0, r1, d4
+	cmp r0, #108
+	bne reg1_error_loopf
+	cmp r1, #109
+	bne reg1_error_loopf
+	vmov r0, r1, d5
+	cmp r0, #110
+	bne reg1_error_loopf
+	cmp r1, #111
+	bne reg1_error_loopf
+	vmov r0, r1, d6
+	cmp r0, #100
+	bne reg1_error_loopf
+	cmp r1, #101
+	bne reg1_error_loopf
+	vmov r0, r1, d7
+	cmp r0, #102
+	bne reg1_error_loopf
+	cmp r1, #103
+	bne reg1_error_loopf
+	vmov r0, r1, d8
+	cmp r0, #104
+	bne reg1_error_loopf
+	cmp r1, #105
+	bne reg1_error_loopf
+	vmov r0, r1, d9
+	cmp r0, #106
+	bne reg1_error_loopf
+	cmp r1, #107
+	bne reg1_error_loopf
+	vmov r0, r1, d10
+	cmp r0, #108
+	bne reg1_error_loopf
+	cmp r1, #109
+	bne reg1_error_loopf
+	vmov r0, r1, d11
+	cmp r0, #110
+	bne reg1_error_loopf
+	cmp r1, #111
+	bne reg1_error_loopf
+	vmov r0, r1, d12
+	cmp r0, #100
+	bne reg1_error_loopf
+	cmp r1, #101
+	bne reg1_error_loopf
+	vmov r0, r1, d13
+	cmp r0, #102
+	bne reg1_error_loopf
+	cmp r1, #103
+	bne reg1_error_loopf
+	vmov r0, r1, d14
+	cmp r0, #104
+	bne reg1_error_loopf
+	cmp r1, #105
+	bne reg1_error_loopf
+	vmov r0, r1, d15
+	cmp r0, #106
+	bne reg1_error_loopf
+	cmp r1, #107
+	bne reg1_error_loopf
+
+	/* Restore the registers that were clobbered by the test. */
+	pop {r0-r1}
+
+	/* VFP register test passed.  Jump to the core register test. */
+	b reg1_loopf_pass
+
+reg1_error_loopf
+	/* If this line is hit then a VFP register value was found to be
+	incorrect. */
+	b reg1_error_loopf
+
+reg1_loopf_pass
+
+	cmp	r0, #100
+	bne	reg1_error_loop
+	cmp	r1, #101
+	bne	reg1_error_loop
+	cmp	r2, #102
+	bne	reg1_error_loop
+	cmp r3, #103
+	bne	reg1_error_loop
+	cmp	r4, #104
+	bne	reg1_error_loop
+	cmp	r5, #105
+	bne	reg1_error_loop
+	cmp	r6, #106
+	bne	reg1_error_loop
+	cmp	r7, #107
+	bne	reg1_error_loop
+	cmp	r8, #108
+	bne	reg1_error_loop
+	cmp	r9, #109
+	bne	reg1_error_loop
+	cmp	r10, #110
+	bne	reg1_error_loop
+	cmp	r11, #111
+	bne	reg1_error_loop
+	cmp	r12, #112
+	bne	reg1_error_loop
+
+	/* Everything passed, increment the loop counter. */
+	push { r0-r1 }
+	ldr	r0, =ulRegTest1LoopCounter
+	ldr r1, [r0]
+	adds r1, r1, #1
+	str r1, [r0]
+	pop { r0-r1 }
+
+	/* Start again. */
+	b reg1_loop
+
+reg1_error_loop:
+	/* If this line is hit then there was an error in a core register value.
+	The loop ensures the loop counter stops incrementing. */
+	b reg1_error_loop
+
+/*-----------------------------------------------------------*/
+
+
+vRegTest2Implementation
+
+	/* Set all the core registers to known values. */
+	mov r0, #-1
+	mov r1, #1
+	mov r2, #2
+	mov r3, #3
+	mov	r4, #4
+	mov	r5, #5
+	mov	r6, #6
+	mov r7, #7
+	mov	r8, #8
+	mov	r9, #9
+	mov	r10, #10
+	mov	r11, #11
+	mov r12, #12
+
+	/* Set all the VFP to known values. */
+	vmov d0, r0, r1
+	vmov d1, r2, r3
+	vmov d2, r4, r5
+	vmov d3, r6, r7
+	vmov d4, r8, r9
+	vmov d5, r10, r11
+	vmov d6, r0, r1
+	vmov d7, r2, r3
+	vmov d8, r4, r5
+	vmov d9, r6, r7
+	vmov d10, r8, r9
+	vmov d11, r10, r11
+	vmov d12, r0, r1
+	vmov d13, r2, r3
+	vmov d14, r4, r5
+	vmov d15, r6, r7
+
+reg2_loop:
+
+	/* Check all the VFP registers still contain the values set above.
+	First save registers that are clobbered by the test. */
+	push { r0-r1 }
+
+	vmov r0, r1, d0
+	cmp r0, #-1
+	bne reg2_error_loopf
+	cmp r1, #1
+	bne reg2_error_loopf
+	vmov r0, r1, d1
+	cmp r0, #2
+	bne reg2_error_loopf
+	cmp r1, #3
+	bne reg2_error_loopf
+	vmov r0, r1, d2
+	cmp r0, #4
+	bne reg2_error_loopf
+	cmp r1, #5
+	bne reg2_error_loopf
+	vmov r0, r1, d3
+	cmp r0, #6
+	bne reg2_error_loopf
+	cmp r1, #7
+	bne reg2_error_loopf
+	vmov r0, r1, d4
+	cmp r0, #8
+	bne reg2_error_loopf
+	cmp r1, #9
+	bne reg2_error_loopf
+	vmov r0, r1, d5
+	cmp r0, #10
+	bne reg2_error_loopf
+	cmp r1, #11
+	bne reg2_error_loopf
+	vmov r0, r1, d6
+	cmp r0, #-1
+	bne reg2_error_loopf
+	cmp r1, #1
+	bne reg2_error_loopf
+	vmov r0, r1, d7
+	cmp r0, #2
+	bne reg2_error_loopf
+	cmp r1, #3
+	bne reg2_error_loopf
+	vmov r0, r1, d8
+	cmp r0, #4
+	bne reg2_error_loopf
+	cmp r1, #5
+	bne reg2_error_loopf
+	vmov r0, r1, d9
+	cmp r0, #6
+	bne reg2_error_loopf
+	cmp r1, #7
+	bne reg2_error_loopf
+	vmov r0, r1, d10
+	cmp r0, #8
+	bne reg2_error_loopf
+	cmp r1, #9
+	bne reg2_error_loopf
+	vmov r0, r1, d11
+	cmp r0, #10
+	bne reg2_error_loopf
+	cmp r1, #11
+	bne reg2_error_loopf
+	vmov r0, r1, d12
+	cmp r0, #-1
+	bne reg2_error_loopf
+	cmp r1, #1
+	bne reg2_error_loopf
+	vmov r0, r1, d13
+	cmp r0, #2
+	bne reg2_error_loopf
+	cmp r1, #3
+	bne reg2_error_loopf
+	vmov r0, r1, d14
+	cmp r0, #4
+	bne reg2_error_loopf
+	cmp r1, #5
+	bne reg2_error_loopf
+	vmov r0, r1, d15
+	cmp r0, #6
+	bne reg2_error_loopf
+	cmp r1, #7
+	bne reg2_error_loopf
+
+	/* Restore the registers that were clobbered by the test. */
+	pop {r0-r1}
+
+	/* VFP register test passed.  Jump to the core register test. */
+	b reg2_loopf_pass
+
+reg2_error_loopf
+	/* If this line is hit then a VFP register value was found to be
+	incorrect. */
+	b reg2_error_loopf
+
+reg2_loopf_pass
+
+	cmp	r0, #-1
+	bne	reg2_error_loop
+	cmp	r1, #1
+	bne	reg2_error_loop
+	cmp	r2, #2
+	bne	reg2_error_loop
+	cmp r3, #3
+	bne	reg2_error_loop
+	cmp	r4, #4
+	bne	reg2_error_loop
+	cmp	r5, #5
+	bne	reg2_error_loop
+	cmp	r6, #6
+	bne	reg2_error_loop
+	cmp	r7, #7
+	bne	reg2_error_loop
+	cmp	r8, #8
+	bne	reg2_error_loop
+	cmp	r9, #9
+	bne	reg2_error_loop
+	cmp	r10, #10
+	bne	reg2_error_loop
+	cmp	r11, #11
+	bne	reg2_error_loop
+	cmp	r12, #12
+	bne	reg2_error_loop
+
+	/* Increment the loop counter to indicate this test is still functioning
+	correctly. */
+	push { r0-r1 }
+	ldr	r0, =ulRegTest2LoopCounter
+	ldr r1, [r0]
+	adds r1, r1, #1
+	str r1, [r0]
+
+	/* Yield to increase test coverage. */
+	movs r0, #0x01
+	ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */
+	lsl r0, r0, #28 /* Shift to PendSV bit */
+	str r0, [r1]
+	dsb
+
+	pop { r0-r1 }
+
+	/* Start again. */
+	b reg2_loop
+
+reg2_error_loop:
+	/* If this line is hit then there was an error in a core register value.
+	This loop ensures the loop counter variable stops incrementing. */
+	b reg2_error_loop
+
+/*-----------------------------------------------------------*/
+
+vRegTestClearFlopRegistersToParameterValue
+
+	/* Clobber the auto saved registers. */
+	vmov d0, r0, r0
+	vmov d1, r0, r0
+	vmov d2, r0, r0
+	vmov d3, r0, r0
+	vmov d4, r0, r0
+	vmov d5, r0, r0
+	vmov d6, r0, r0
+	vmov d7, r0, r0
+	bx lr
+
+/*-----------------------------------------------------------*/
+
+ulRegTestCheckFlopRegistersContainParameterValue
+
+	vmov r1, s0
+	cmp r0, r1
+	bne return_error
+	vmov r1, s1
+	cmp r0, r1
+	bne return_error
+	vmov r1, s2
+	cmp r0, r1
+	bne return_error
+	vmov r1, s3
+	cmp r0, r1
+	bne return_error
+	vmov r1, s4
+	cmp r0, r1
+	bne return_error
+	vmov r1, s5
+	cmp r0, r1
+	bne return_error
+	vmov r1, s6
+	cmp r0, r1
+	bne return_error
+	vmov r1, s7
+	cmp r0, r1
+	bne return_error
+	vmov r1, s8
+	cmp r0, r1
+	bne return_error
+	vmov r1, s9
+	cmp r0, r1
+	bne return_error
+	vmov r1, s10
+	cmp r0, r1
+	bne return_error
+	vmov r1, s11
+	cmp r0, r1
+	bne return_error
+	vmov r1, s12
+	cmp r0, r1
+	bne return_error
+	vmov r1, s13
+	cmp r0, r1
+	bne return_error
+	vmov r1, s14
+	cmp r0, r1
+	bne return_error
+	vmov r1, s15
+	cmp r0, r1
+	bne return_error
+
+return_pass
+	mov r0, #1
+	bx lr
+
+return_error
+	mov r0, #0
+	bx lr
+
+	END
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/RunTimeStatsTimer.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/RunTimeStatsTimer.c
new file mode 100644
index 000000000..4bbd762df
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/RunTimeStatsTimer.c
@@ -0,0 +1,126 @@
+/*
+    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+
+/* Utility functions to implement run time stats on Cortex-M CPUs.  The collected
+run time data can be viewed through the CLI interface.  See the following URL for
+more information on run time stats:
+http://www.freertos.org/rtos-run-time-stats.html */
+
+/* Addresses of registers in the Cortex-M debug hardware. */
+#define rtsDWT_CYCCNT 			( *( ( unsigned long * ) 0xE0001004 ) )
+#define rtsDWT_CONTROL 			( *( ( unsigned long * ) 0xE0001000 ) )
+#define rtsSCB_DEMCR 			( *( ( unsigned long * ) 0xE000EDFC ) )
+#define rtsTRCENA_BIT			( 0x01000000UL )
+#define rtsCOUNTER_ENABLE_BIT	( 0x01UL )
+
+/* Simple shift divide for scaling to avoid an overflow occurring too soon. */
+#define runtimeSHIFT_13				13
+#define runtimeOVERFLOW_BIT_13		( 1UL << ( 32UL - runtimeSHIFT_13 ) )
+static const uint32_t ulPrescaleBits = runtimeSHIFT_13;
+static const uint32_t ulOverflowBit = runtimeOVERFLOW_BIT_13;
+
+/*-----------------------------------------------------------*/
+
+void vConfigureTimerForRunTimeStats( void )
+{
+	/* Enable TRCENA. */
+	rtsSCB_DEMCR = rtsSCB_DEMCR | rtsTRCENA_BIT;
+
+	/* Reset counter. */
+	rtsDWT_CYCCNT = 0;
+
+	/* Enable counter. */
+	rtsDWT_CONTROL = rtsDWT_CONTROL | rtsCOUNTER_ENABLE_BIT;
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulGetRunTimeCounterValue( void )
+{
+static unsigned long ulLastCounterValue = 0UL, ulOverflows = 0;
+unsigned long ulValueNow;
+
+	ulValueNow = rtsDWT_CYCCNT;
+
+	/* Has the value overflowed since it was last read. */
+	if( ulValueNow < ulLastCounterValue )
+	{
+		ulOverflows += ulOverflowBit;
+	}
+	ulLastCounterValue = ulValueNow;
+
+	/* There is no prescale on the counter, so simulate in software. */
+	ulValueNow = ( ulValueNow >> ulPrescaleBits ) + ulOverflows;
+
+	return ulValueNow;
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/main_full.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/main_full.c
new file mode 100644
index 000000000..8d3c93473
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/main_full.c
@@ -0,0 +1,490 @@
+/*
+    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+
+/******************************************************************************
+ * NOTE 1:  This project provides two demo applications.  A simple blinky
+ * style project, and a more comprehensive test and demo application.  The
+ * configCREATE_SIMPLE_TICKLESS_DEMO setting in FreeRTOSConfig.h is used to
+ * select between the two.  See the notes on using
+ * configCREATE_SIMPLY_BLINKY_DEMO_ONLY in main.c.  This file implements the
+ * comprehensive version.
+ *
+ * NOTE 2:  This file only contains the source code that is specific to the
+ * full demo.  Generic functions, such FreeRTOS hook functions, and functions
+ * required to configure the hardware, are defined in main.c.
+ *
+ * See http://www.FreeRTOS.org/TI_MSP432_Free_RTOS_Demo.html for instructions.
+ *
+ ******************************************************************************
+ *
+ * main_full() creates all the demo application tasks and software timers, then
+ * starts the scheduler.  The web documentation provides more details of the
+ * standard demo application tasks, which provide no particular functionality,
+ * but do provide a good example of how to use the FreeRTOS API.
+ *
+ * In addition to the standard demo tasks, the following tasks and tests are
+ * defined and/or created within this file:
+ *
+ * FreeRTOS+CLI command console.  The command console is access through the
+ * UART at 19200 baud.  For reasons of robustness testing the UART driver is
+ * deliberately written to be inefficient and should not be used as a template
+ * for a production driver.  Type "help" to see a list of registered commands.
+ * The FreeRTOS+CLI license is different to the FreeRTOS license, see
+ * http://www.FreeRTOS.org/cli for license and usage details.
+ *
+ * "Reg test" tasks - These fill both the core and floating point registers with
+ * known values, then check that each register maintains its expected value for
+ * the lifetime of the task.  Each task uses a different set of values.  The reg
+ * test tasks execute with a very low priority, so get preempted very
+ * frequently.  A register containing an unexpected value is indicative of an
+ * error in the context switching mechanism.
+ *
+ * "Check" task - The check task period is initially set to three seconds.  The
+ * task checks that all the standard demo tasks, and the register check tasks,
+ * are not only still executing, but are executing without reporting any errors.
+ * If the check task discovers that a task has either stalled, or reported an
+ * error, then it changes its own execution period from the initial three
+ * seconds, to just 200ms.  The check task also toggles an LED each time it is
+ * called.  This provides a visual indication of the system status:  If the LED
+ * toggles every three seconds, then no issues have been discovered.  If the LED
+ * toggles every 200ms, then an issue has been discovered with at least one
+ * task.
+ */
+
+/* Standard includes. */
+#include <stdio.h>
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "semphr.h"
+
+/* Standard demo application includes. */
+#include "flop.h"
+#include "semtest.h"
+#include "countsem.h"
+#include "GenQTest.h"
+#include "recmutex.h"
+#include "partest.h"
+#include "serial.h"
+#include "TimerDemo.h"
+#include "IntQueue.h"
+#include "EventGroupsDemo.h"
+#include "TaskNotify.h"
+#include "IntSemTest.h"
+
+/* Priorities for the demo application tasks. */
+#define mainSEM_TEST_PRIORITY				( tskIDLE_PRIORITY + 1UL )
+#define mainBLOCK_Q_PRIORITY				( tskIDLE_PRIORITY + 2UL )
+#define mainCREATOR_TASK_PRIORITY			( tskIDLE_PRIORITY + 3UL )
+#define mainFLOP_TASK_PRIORITY				( tskIDLE_PRIORITY )
+#define mainUART_COMMAND_CONSOLE_STACK_SIZE	( configMINIMAL_STACK_SIZE * 2UL )
+#define mainCOM_TEST_TASK_PRIORITY			( tskIDLE_PRIORITY + 2 )
+#define mainCHECK_TASK_PRIORITY				( configMAX_PRIORITIES - 1 )
+#define mainQUEUE_OVERWRITE_PRIORITY		( tskIDLE_PRIORITY )
+
+/* The priority used by the UART command console task. */
+#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY	( configMAX_PRIORITIES - 2 )
+
+/* A block time of zero simply means "don't block". */
+#define mainDONT_BLOCK						( 0UL )
+
+/* The period after which the check timer will expire, in ms, provided no errors
+have been reported by any of the standard demo tasks.  ms are converted to the
+equivalent in ticks using the portTICK_PERIOD_MS constant. */
+#define mainNO_ERROR_CHECK_TASK_PERIOD		( pdMS_TO_TICKS( 3000UL ) )
+
+/* The period at which the check timer will expire, in ms, if an error has been
+reported in one of the standard demo tasks.  ms are converted to the equivalent
+in ticks using the portTICK_PERIOD_MS constant. */
+#define mainERROR_CHECK_TASK_PERIOD 		( pdMS_TO_TICKS( 200UL ) )
+
+/* Parameters that are passed into the register check tasks solely for the
+purpose of ensuring parameters are passed into tasks correctly. */
+#define mainREG_TEST_TASK_1_PARAMETER		( ( void * ) 0x12345678 )
+#define mainREG_TEST_TASK_2_PARAMETER		( ( void * ) 0x87654321 )
+
+/* The base period used by the timer test tasks. */
+#define mainTIMER_TEST_PERIOD				( 50 )
+
+/* Dimensions the queue in which characters received from the UART are
+placed. */
+#define mainRX_QUEUE_LENGTH					10
+
+/*-----------------------------------------------------------*/
+
+
+/*
+ * The check task, as described at the top of this file.
+ */
+static void prvCheckTask( void *pvParameters );
+
+/*
+ * Register check tasks, and the tasks used to write over and check the contents
+ * of the FPU registers, as described at the top of this file.  The nature of
+ * these files necessitates that they are written in an assembly file, but the
+ * entry points are kept in the C file for the convenience of checking the task
+ * parameter.
+ */
+static void prvRegTestTaskEntry1( void *pvParameters );
+extern void vRegTest1Implementation( void );
+static void prvRegTestTaskEntry2( void *pvParameters );
+extern void vRegTest2Implementation( void );
+
+/*
+ * Register commands that can be used with FreeRTOS+CLI.  The commands are
+ * defined in CLI-Commands.c and File-Related-CLI-Command.c respectively.
+ */
+extern void vRegisterSampleCLICommands( void );
+
+/*
+ * The task that manages the FreeRTOS+CLI input and output.
+ */
+extern void vUARTCommandConsoleStart( uint16_t usStackSize, UBaseType_t uxPriority );
+
+/*
+ * When the full demo is build the idle hook is used to create some timers that
+ * cannot be created in main() because the timer demo tasks need the entire
+ * command queue.
+ */
+void vFullDemoIdleHook( void );
+
+/*
+ * The full demo configures the clocks for maximum frequency, wheras the blinky
+ * demo uses a slower clock as it also uses low power features.
+ */
+static void prvConfigureClocks( void );
+
+/*-----------------------------------------------------------*/
+
+/* The following two variables are used to communicate the status of the
+register check tasks to the check task.  If the variables keep incrementing,
+then the register check tasks has not discovered any errors.  If a variable
+stops incrementing, then an error has been found. */
+volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;
+
+/*-----------------------------------------------------------*/
+
+void main_full( void )
+{
+	/* This demo sets the clock to its maximum.  The blinky demo uses as slower
+ 	clock as it uses low power features.  */
+	prvConfigureClocks();
+
+	/* Init the serial port for use by the CLI.  The baud rate parameter is not
+	used so set to 0 to make this obvious. */
+	xSerialPortInitMinimal( 0, mainRX_QUEUE_LENGTH );
+
+	/* Start all the other standard demo/test tasks.  They have not particular
+	functionality, but do demonstrate how to use the FreeRTOS API and test the
+	kernel port. */
+	vStartInterruptQueueTasks();
+
+	vStartCountingSemaphoreTasks();
+	vStartGenericQueueTasks( tskIDLE_PRIORITY );
+	vStartRecursiveMutexTasks();
+	vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
+	vStartTimerDemoTask( mainTIMER_TEST_PERIOD );
+	vStartEventGroupTasks();
+	vStartTaskNotifyTask();
+	vStartInterruptSemaphoreTasks();
+
+	/* Note - the set of standard demo tasks contains two versions of
+	vStartMathTasks.c.  One is defined in flop.c, and uses double precision
+	floating point numbers and variables.  The other is defined in sp_flop.c,
+	and uses single precision floating point numbers and variables.  sp_flop.
+	c should be included in this project. */
+	vStartMathTasks( mainFLOP_TASK_PRIORITY );
+
+	/* Start the tasks that implements the command console on the UART, as
+	described above. */
+	vUARTCommandConsoleStart( mainUART_COMMAND_CONSOLE_STACK_SIZE, mainUART_COMMAND_CONSOLE_TASK_PRIORITY );
+
+	/* Register the standard CLI commands. */
+	vRegisterSampleCLICommands();
+
+	/* Create the register check tasks, as described at the top of this	file */
+	xTaskCreate( prvRegTestTaskEntry1, "Reg1", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_1_PARAMETER, tskIDLE_PRIORITY, NULL );
+	xTaskCreate( prvRegTestTaskEntry2, "Reg2", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL );
+
+	/* Create the task that performs the 'check' functionality,	as described at
+	the top of this file. */
+	xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
+
+	/* Start the scheduler. */
+	vTaskStartScheduler();
+
+	/* If all is well, the scheduler will now be running, and the following
+	line will never be reached.  If the following line does execute, then
+	there was either insufficient FreeRTOS heap memory available for the idle
+	and/or timer tasks to be created, or vTaskStartScheduler() was called from
+	User mode.  See the memory management section on the FreeRTOS web site for
+	more details on the FreeRTOS heap http://www.freertos.org/a00111.html.  The
+	mode from which main() is called is set in the C start up code and must be
+	a privileged mode (not user mode). */
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckTask( void *pvParameters )
+{
+TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD;
+TickType_t xLastExecutionTime;
+static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;
+unsigned long ulErrorFound = pdFALSE;
+
+	/* Just to stop compiler warnings. */
+	( void ) pvParameters;
+
+	/* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()
+	works correctly. */
+	xLastExecutionTime = xTaskGetTickCount();
+
+	/* Cycle for ever, delaying then checking all the other tasks are still
+	operating without error.  The onboard LED is toggled on each iteration.
+	If an error is detected then the delay period is decreased from
+	mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD.  This has the
+	effect of increasing the rate at which the onboard LED toggles, and in so
+	doing gives visual feedback of the system status. */
+	for( ;; )
+	{
+		/* Delay until it is time to execute again. */
+		vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod );
+
+		/* Check all the demo tasks to ensure that they are all still running,
+		and that none have detected an error. */
+		if( xAreIntQueueTasksStillRunning() != pdTRUE )
+		{
+			ulErrorFound |= 1UL << 0UL;
+		}
+
+		if( xAreMathsTaskStillRunning() != pdTRUE )
+		{
+			ulErrorFound |= 1UL << 1UL;
+		}
+
+		if( xAreGenericQueueTasksStillRunning() != pdTRUE )
+		{
+			ulErrorFound |= 1UL << 5UL;
+		}
+
+		if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
+		{
+			ulErrorFound |= 1UL << 6UL;
+		}
+
+		if( xAreSemaphoreTasksStillRunning() != pdTRUE )
+		{
+			ulErrorFound |= 1UL << 8UL;
+		}
+
+		if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE )
+		{
+			ulErrorFound |= 1UL << 10UL;
+		}
+
+		if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE )
+		{
+			ulErrorFound |= 1UL << 14UL;
+		}
+
+		if( xAreTimerDemoTasksStillRunning( ( TickType_t ) mainNO_ERROR_CHECK_TASK_PERIOD ) != pdPASS )
+		{
+			ulErrorFound |= 1UL << 9UL;
+		}
+
+		if( xAreEventGroupTasksStillRunning() != pdPASS )
+		{
+			ulErrorFound |= 1UL << 12UL;
+		}
+
+		if( xAreTaskNotificationTasksStillRunning() != pdTRUE )
+		{
+			ulErrorFound |= 1UL << 13UL;
+		}
+
+		/* Check that the register test 1 task is still running. */
+		if( ulLastRegTest1Value == ulRegTest1LoopCounter )
+		{
+			ulErrorFound |= 1UL << 15UL;
+		}
+		ulLastRegTest1Value = ulRegTest1LoopCounter;
+
+		/* Check that the register test 2 task is still running. */
+		if( ulLastRegTest2Value == ulRegTest2LoopCounter )
+		{
+			ulErrorFound |= 1UL << 16UL;
+		}
+		ulLastRegTest2Value = ulRegTest2LoopCounter;
+
+		/* Toggle the check LED to give an indication of the system status.  If
+		the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then
+		everything is ok.  A faster toggle indicates an error. */
+		configTOGGLE_LED();
+
+		if( ulErrorFound != pdFALSE )
+		{
+			/* An error has been detected in one of the tasks - flash the LED
+			at a higher frequency to give visible feedback that something has
+			gone wrong (it might just be that the loop back connector required
+			by the comtest tasks has not been fitted). */
+			xDelayPeriod = mainERROR_CHECK_TASK_PERIOD;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvRegTestTaskEntry1( void *pvParameters )
+{
+	/* Although the regtest task is written in assembler, its entry point is
+	written in C for convenience of checking the task parameter is being passed
+	in correctly. */
+	if( pvParameters == mainREG_TEST_TASK_1_PARAMETER )
+	{
+		/* Start the part of the test that is written in assembler. */
+		vRegTest1Implementation();
+	}
+
+	/* The following line will only execute if the task parameter is found to
+	be incorrect.  The check timer will detect that the regtest loop counter is
+	not being incremented and flag an error. */
+	vTaskDelete( NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvRegTestTaskEntry2( void *pvParameters )
+{
+	/* Although the regtest task is written in assembler, its entry point is
+	written in C for convenience of checking the task parameter is being passed
+	in correctly. */
+	if( pvParameters == mainREG_TEST_TASK_2_PARAMETER )
+	{
+		/* Start the part of the test that is written in assembler. */
+		vRegTest2Implementation();
+	}
+
+	/* The following line will only execute if the task parameter is found to
+	be incorrect.  The check timer will detect that the regtest loop counter is
+	not being incremented and flag an error. */
+	vTaskDelete( NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvConfigureClocks( void )
+{
+	/* The full demo configures the clocks for maximum frequency, wheras the
+	blinky demo uses a slower clock as it also uses low power features.  Maximum
+	freqency also needs more voltage.
+
+	From the datashee:  For AM_LDO_VCORE1 and AM_DCDC_VCORE1 modes, the maximum
+	CPU operating frequency is 48 MHz and maximum input clock frequency for
+	peripherals is 24 MHz. */
+	PCM_setCoreVoltageLevel( PCM_VCORE1 );
+	CS_setDCOCenteredFrequency( CS_DCO_FREQUENCY_48 );
+	CS_initClockSignal( CS_HSMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 );
+	CS_initClockSignal( CS_SMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 );
+	CS_initClockSignal( CS_MCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 );
+	CS_initClockSignal( CS_ACLK, CS_REFOCLK_SELECT, CS_CLOCK_DIVIDER_1 );
+}
+/*-----------------------------------------------------------*/
+
+#if( configCREATE_SIMPLE_TICKLESS_DEMO == 0 )
+
+	void vApplicationTickHook( void )
+	{
+		/* This function will be called by each tick interrupt if
+		configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h.  User code can be
+		added here, but the tick hook is called from an interrupt context, so
+		code must not attempt to block, and only the interrupt safe FreeRTOS API
+		functions can be used (those that end in FromISR()). */
+
+		/* The full demo includes a software timer demo/test that requires
+		prodding periodically from the tick interrupt. */
+		vTimerPeriodicISRTests();
+
+		/* Call the periodic event group from ISR demo. */
+		vPeriodicEventGroupsProcessing();
+
+		/* Use task notifications from an interrupt. */
+		xNotifyTaskFromISR();
+
+		/* Use mutexes from interrupts. */
+		vInterruptSemaphorePeriodicTest();
+	}
+
+#endif
+/*-----------------------------------------------------------*/
+
+
+
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/serial.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/serial.c
new file mode 100644
index 000000000..9dd99f309
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/serial.c
@@ -0,0 +1,307 @@
+/*
+    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/*
+	BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER.
+
+	Note1:  This driver is used specifically to provide an interface to the
+	FreeRTOS+CLI command interpreter.  It is *not* intended to be a generic
+	serial port driver.  Nor is it intended to be used as an example of an
+	efficient implementation.  In particular, a queue is used to buffer
+	received characters, which is fine in this case as key presses arrive
+	slowly, but a DMA and/or RAM buffer should be used in place of the queue in
+	applications that expect higher throughput.
+
+	Note2:  This driver does not attempt to handle UART errors.
+*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "semphr.h"
+
+/* Demo application includes. */
+#include "serial.h"
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The UART interrupt handler.
+ */
+void vUART_Handler( void );
+
+/*-----------------------------------------------------------*/
+
+/* The queue into which received key presses are placed.  NOTE THE COMMENTS AT
+THE TOP OF THIS FILE REGARDING THE USE OF QUEUES FOR THIS PURPOSE. */
+static QueueHandle_t xRxQueue = NULL;
+
+/* Variables used in the Tx interrupt to send a string. */
+static volatile const signed char *pcStringStart = NULL, *pcStringEnd = NULL;
+static volatile TaskHandle_t xTransmittingTask = NULL;
+
+static EUSCI_A0_Type * const pxUARTA0 = ( EUSCI_A0_Type * ) EUSCI_A0_MODULE;
+
+/* UART Configuration for 19200 baud.  Value generated using the tool provided
+on the following page:
+http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSP430BaudRateConverter/index.html
+ */
+const eUSCI_UART_Config xUARTConfig =
+{
+	EUSCI_A_UART_CLOCKSOURCE_SMCLK,	/* SMCLK Clock Source. */
+	156,							/* BRDIV */
+	4,								/* UCxBRF */
+	0,								/* UCxBRS */
+	EUSCI_A_UART_NO_PARITY,			/* No Parity. */
+	EUSCI_A_UART_LSB_FIRST,			/* MSB First. */
+	EUSCI_A_UART_ONE_STOP_BIT,		/* One stop bit. */
+	EUSCI_A_UART_MODE,				/* UART mode. */
+	EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION /* Low Frequency Mode. */
+};
+
+/*
+ * See the serial2.h header file.
+ */
+xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned long uxQueueLength )
+{
+	/* Create the queue used to hold received characters.  NOTE THE COMMENTS AT
+	THE TOP OF THIS FILE REGARDING THE USE OF QUEUES FOR THIS PURPSOE. */
+	xRxQueue = xQueueCreate( uxQueueLength, sizeof( char ) );
+	configASSERT( xRxQueue );
+
+	/* Use the library functions to initialise and enable the UART. */
+	MAP_UART_initModule( EUSCI_A0_MODULE, &xUARTConfig );
+	MAP_UART_enableModule( EUSCI_A0_MODULE );
+	MAP_UART_clearInterruptFlag( EUSCI_A0_MODULE, EUSCI_A_UART_RECEIVE_INTERRUPT | EUSCI_A_UART_TRANSMIT_INTERRUPT );
+	MAP_UART_enableInterrupt( EUSCI_A0_MODULE, EUSCI_A_UART_RECEIVE_INTERRUPT );
+
+	/* The interrupt handler uses the FreeRTOS API function so its priority must
+	be at or below the configured maximum system call interrupt priority.
+	configKERNEL_INTERRUPT_PRIORITY is the priority used by the RTOS tick and
+	(should) always be set to the minimum priority. */
+	MAP_Interrupt_setPriority( INT_EUSCIA0, configKERNEL_INTERRUPT_PRIORITY );
+	MAP_Interrupt_enableInterrupt( INT_EUSCIA0 );
+
+	/* Only one UART is supported so the handle is not used. */
+	return ( xComPortHandle ) 0;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, TickType_t xBlockTime )
+{
+BaseType_t xReturn;
+
+	/* Only a single port is supported. */
+	( void ) pxPort;
+
+	/* Obtain a received character from the queue - entering the Blocked state
+	(so not consuming any processing time) to wait for a character if one is not
+	already available. */
+	xReturn = xQueueReceive( xRxQueue, pcRxedChar, xBlockTime );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength )
+{
+const TickType_t xMaxWaitTime = pdMS_TO_TICKS( 20UL * ( uint32_t ) usStringLength );
+
+	/* Only a single port is supported. */
+	( void ) pxPort;
+
+	/* Note there is no mutual exclusion at the driver level.  If more than one
+	task is using the serial port then mutual exclusion should be provided where
+	this function is called. */
+
+	/* Ensure notifications are not already waiting. */
+	( void ) ulTaskNotifyTake( pdTRUE, 0 );
+
+	/* Remember which task is sending the byte. */
+	xTransmittingTask = xTaskGetCurrentTaskHandle();
+
+	/* Mark the start and end of the data being sent. */
+	pcStringStart = pcString;
+	pcStringEnd = pcStringStart + usStringLength;
+
+	/* Start to send the first byte. */
+	pxUARTA0->rTXBUF.r = ( uint_fast8_t ) *pcString;
+
+	/* Enable the interrupt then wait for the byte to be sent.  The interrupt
+	will be disabled again in the ISR. */
+	MAP_UART_enableInterrupt( EUSCI_A0_MODULE, EUSCI_A_UART_TRANSMIT_INTERRUPT );
+	ulTaskNotifyTake( pdTRUE, xMaxWaitTime );
+}
+/*-----------------------------------------------------------*/
+
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, TickType_t xBlockTime )
+{
+const TickType_t xMaxWaitTime = pdMS_TO_TICKS( 20UL );
+
+	/* Only a single port is supported. */
+	( void ) pxPort;
+
+	/* Note there is no mutual exclusion at the driver level.  If more than one
+	task is using the serial port then mutual exclusion should be provided where
+	this function is called. */
+
+	/* Ensure notifications are not already waiting. */
+	( void ) ulTaskNotifyTake( pdTRUE, 0 );
+
+	/* Remember which task is sending the byte. */
+	xTransmittingTask = xTaskGetCurrentTaskHandle();
+
+	/* Mark the start and end of the data being sent - in this case just a
+	single byte. */
+	pcStringStart = &cOutChar;
+	pcStringEnd = pcStringStart + sizeof( cOutChar );
+
+	/* Start to send the byte. */
+	pxUARTA0->rTXBUF.r = ( uint_fast8_t ) cOutChar;
+
+	/* Enable the interrupt then wait for the byte to be sent.  The interrupt
+	will be disabled again in the ISR. */
+	MAP_UART_enableInterrupt( EUSCI_A0_MODULE, EUSCI_A_UART_TRANSMIT_INTERRUPT );
+	ulTaskNotifyTake( pdTRUE, xMaxWaitTime );
+
+	return pdPASS;
+}
+/*-----------------------------------------------------------*/
+
+void vSerialClose(xComPortHandle xPort)
+{
+	/* Not supported as not required by the demo application. */
+	( void ) xPort;
+}
+/*-----------------------------------------------------------*/
+
+void vUART_Handler( void )
+{
+uint8_t ucChar;
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+uint_fast8_t xInterruptStatus;
+
+	xInterruptStatus = MAP_UART_getEnabledInterruptStatus( EUSCI_A0_MODULE );
+
+	if( ( xInterruptStatus & EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG ) != 0x00 )
+	{
+		/* Obtain the character. */
+		ucChar = MAP_UART_receiveData( EUSCI_A0_MODULE );
+
+		/* Send the character to the queue.  Note the comments at the top of this
+		file with regards to the inefficiency of this method for anything other than
+		very low bandwidth communications.
+
+		If writing to the queue unblocks a task, and the unblocked task	has a
+		priority above the currently running task (the task that this interrupt
+		interrupted), then xHigherPriorityTaskWoken will be set	to pdTRUE inside the
+		xQueueSendFromISR() function.  xHigherPriorityTaskWoken is then passed to
+		portYIELD_FROM_ISR() at	the end of this interrupt handler to request a
+		context switch so the interrupt returns directly to the (higher priority)
+		unblocked task. */
+		xQueueSendFromISR( xRxQueue, &ucChar, &xHigherPriorityTaskWoken );
+	}
+
+	if( ( xInterruptStatus & EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG ) != 0x00 )
+	{
+		/* Are there more characters to transmit? */
+		pcStringStart++;
+		if( ( uint32_t ) pcStringStart < ( uint32_t ) pcStringEnd )
+		{
+			/* This is probably quite a heavy wait function just for writing to
+			the Tx register.  An optimised design would probably replace this
+			with a simple register write. */
+			pxUARTA0->rTXBUF.r = ( uint_fast8_t ) *pcStringStart;
+		}
+		else
+		{
+			/* No more characters to send.  Disable the interrupt and notify the
+			task, if the task is waiting. */
+			MAP_UART_disableInterrupt( EUSCI_A0_MODULE, EUSCI_A_UART_TRANSMIT_INTERRUPT );
+			if( xTransmittingTask != NULL )
+			{
+				vTaskNotifyGiveFromISR( xTransmittingTask, &xHigherPriorityTaskWoken );
+				xTransmittingTask = NULL;
+			}
+		}
+	}
+
+
+	/* portYIELD_FROM_ISR() will request a context switch if executing this
+	interrupt handler caused a task to leave the blocked state, and the task
+	that left the blocked state has a higher priority than the currently running
+	task (the task this interrupt interrupted).  See the comment above the calls
+	to xSemaphoreGiveFromISR() and xQueueSendFromISR() within this function. */
+	portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+
+
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.ewd b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.ewd
new file mode 100644
index 000000000..a8bc11b8e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.ewd
@@ -0,0 +1,2741 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+  <fileVersion>2</fileVersion>
+  <configuration>
+    <name>IAR_Debug</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>26</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\TexasInstruments\MSP432P401R.svd</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>7.40.1.8463</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>JLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>7.40.1.8463</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\TexasInstruments\FlashMSP432P401R.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDebuggerExtraOption</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCAllMTBOptions</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCMulticoreNrOfCores</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCMulticoreMaster</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCMulticorePort</name>
+          <state>53461</state>
+        </option>
+        <option>
+          <name>OCMulticoreWorkspace</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCMulticoreSlaveProject</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCMulticoreSlaveConfiguration</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>CMSISDAP_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CMSISDAPAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CMSISDAPResetList</name>
+          <version>1</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CMSISDAPHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>CMSISDAPHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>CMSISDAPDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CMSISDAPInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPMultiCPUEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPMultiCPUNumber</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProbeCfgOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProbeConfig</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CMSISDAPProbeConfigRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPSelectedCPUBehaviour</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ICpuName</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCJetEmuParams</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>_call_main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>6</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>1</version>
+          <state>10</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProbeCfgOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProbeConfig</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IjetProbeConfigRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiCPUEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiCPUNumber</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSelectedCPUBehaviour</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ICpuName</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCJetEmuParams</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPreferETB</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetTraceSettingsList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetTraceSizeList</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>FlashBoardPathSlave</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>15</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>1000</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>1000</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkDeviceName</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>###Uninitialized###</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>###Uninitialized###</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state>C:\ti\ccs_base</state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>2</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state>Browse to your board file</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>Release</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>0</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>26</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>7.10.1.6733</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>ARMSIM_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDebuggerExtraOption</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCAllMTBOptions</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCMulticoreNrOfCores</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCMulticoreMaster</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCMulticorePort</name>
+          <state>53461</state>
+        </option>
+        <option>
+          <name>OCMulticoreWorkspace</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCMulticoreSlaveProject</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCMulticoreSlaveConfiguration</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>CMSISDAP_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CMSISDAPAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CMSISDAPResetList</name>
+          <version>1</version>
+          <state>10</state>
+        </option>
+        <option>
+          <name>CMSISDAPHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>CMSISDAPHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>CMSISDAPDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CMSISDAPInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPMultiCPUEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPMultiCPUNumber</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProbeCfgOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProbeConfig</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CMSISDAPProbeConfigRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CMSISDAPSelectedCPUBehaviour</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ICpuName</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCJetEmuParams</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>_call_main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>6</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>1</version>
+          <state>10</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProbeCfgOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProbeConfig</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IjetProbeConfigRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiCPUEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiCPUNumber</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSelectedCPUBehaviour</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ICpuName</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCJetEmuParams</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPreferETB</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetTraceSettingsList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetTraceSizeList</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>FlashBoardPathSlave</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>15</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>1000</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>1000</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>5</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkDeviceName</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>###Uninitialized###</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>###Uninitialized###</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>2</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+</project>
+
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.ewp b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.ewp
new file mode 100644
index 000000000..28e396cc4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.ewp
@@ -0,0 +1,2086 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+  <fileVersion>2</fileVersion>
+  <configuration>
+    <name>IAR_Debug</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>General</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <version>22</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>ExePath</name>
+          <state>IAR_Debug\Exe</state>
+        </option>
+        <option>
+          <name>ObjPath</name>
+          <state>IAR_Debug\Obj</state>
+        </option>
+        <option>
+          <name>ListPath</name>
+          <state>IAR_Debug\List</state>
+        </option>
+        <option>
+          <name>Variant</name>
+          <version>21</version>
+          <state>40</state>
+        </option>
+        <option>
+          <name>GEndianMode</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>Input variant</name>
+          <version>3</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Input description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>Output variant</name>
+          <version>2</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Output description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>GOutputBinary</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FPU</name>
+          <version>3</version>
+          <state>5</state>
+        </option>
+        <option>
+          <name>OGCoreOrChip</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelect</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RTDescription</name>
+          <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
+        </option>
+        <option>
+          <name>OGProductVersion</name>
+          <state>5.10.0.159</state>
+        </option>
+        <option>
+          <name>OGLastSavedByProductVersion</name>
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+        </option>
+        <option>
+          <name>IlinkTreatAsWarn</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsErr</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkWarningsAreErrors</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkUseExtraOptions</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkLowLevelInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAutoLibEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAdditionalLibs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkOverrideProgramEntryLabel</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabelSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabel</name>
+          <state></state>
+        </option>
+        <option>
+          <name>DoFill</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FillerByte</name>
+          <state>0xFF</state>
+        </option>
+        <option>
+          <name>FillerStart</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>FillerEnd</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>CrcSize</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcAlign</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcPoly</name>
+          <state>0x11021</state>
+        </option>
+        <option>
+          <name>CrcCompl</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcBitOrder</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcInitialValue</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>DoCrc</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkBufferedTerminalOutput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcFullSize</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIElfToolPostProcess</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptInline</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsAllow</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackAnalysisEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackControlFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CrcAlgorithm</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcUnitSize</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkThreadsSlave</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARCHIVE</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>IarchiveInputs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IarchiveOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+  </configuration>
+  <group>
+    <name>DriverLibrary</name>
+    <file>
+      <name>$PROJ_DIR$\driverlib\cpu.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\driverlib\cs.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\driverlib\fpu.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\driverlib\gpio.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\driverlib\interrupt.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\driverlib\pcm.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\driverlib\timer32.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\driverlib\uart.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\driverlib\wdt_a.c</name>
+    </file>
+  </group>
+  <group>
+    <name>FreeRTOS_Source</name>
+    <group>
+      <name>include</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\Source\include\event_groups.h</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\Source\include\FreeRTOS.h</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\Source\include\projdefs.h</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\Source\include\queue.h</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\Source\include\semphr.h</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\Source\include\task.h</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\Source\include\timers.h</name>
+      </file>
+    </group>
+    <group>
+      <name>Portable</name>
+      <group>
+        <name>IAR</name>
+        <group>
+          <name>Cortex-M4F</name>
+          <file>
+            <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM4F\port.c</name>
+          </file>
+          <file>
+            <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM4F\portasm.s</name>
+          </file>
+          <file>
+            <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM4F\portmacro.h</name>
+          </file>
+        </group>
+      </group>
+      <group>
+        <name>MemMang</name>
+        <file>
+          <name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_4.c</name>
+        </file>
+      </group>
+    </group>
+    <file>
+      <name>$PROJ_DIR$\..\..\Source\event_groups.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\Source\list.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\Source\queue.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\Source\tasks.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\Source\timers.c</name>
+    </file>
+  </group>
+  <group>
+    <name>Full_Demo</name>
+    <group>
+      <name>FreeRTOS+CLI</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-CLI\FreeRTOS_CLI.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-CLI\FreeRTOS_CLI.h</name>
+      </file>
+    </group>
+    <group>
+      <name>Standard Demo Tasks</name>
+      <file>
+        <name>$PROJ_DIR$\..\Common\Minimal\BlockQ.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\Common\Minimal\countsem.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\Common\Minimal\EventGroupsDemo.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\Common\Minimal\GenQTest.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\Common\Minimal\IntQueue.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\Common\Minimal\IntSemTest.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\Common\Minimal\recmutex.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\Common\Minimal\semtest.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\Common\Minimal\sp_flop.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\Common\Minimal\TaskNotify.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\Common\Minimal\TimerDemo.c</name>
+      </file>
+    </group>
+    <file>
+      <name>$PROJ_DIR$\Full_Demo\IntQueueTimer.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\Full_Demo\main_full.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\Full_Demo\RegTest.s</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\Full_Demo\RunTimeStatsTimer.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\FreeRTOS-Plus\Demo\Common\FreeRTOS_Plus_CLI_Demos\Sample-CLI-commands.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\Full_Demo\serial.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\FreeRTOS-Plus\Demo\Common\FreeRTOS_Plus_CLI_Demos\UARTCommandConsole.c</name>
+    </file>
+  </group>
+  <group>
+    <name>Simply Blinky Demo</name>
+    <file>
+      <name>$PROJ_DIR$\SimplyBlinkyDemo\main_blinky.c</name>
+    </file>
+  </group>
+  <group>
+    <name>System</name>
+    <file>
+      <name>$PROJ_DIR$\system\IAR\msp432_startup_ewarm.c</name>
+    </file>
+  </group>
+  <file>
+    <name>$PROJ_DIR$\FreeRTOSConfig.h</name>
+  </file>
+  <file>
+    <name>$PROJ_DIR$\main.c</name>
+  </file>
+</project>
+
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.ewt b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.ewt
new file mode 100644
index 000000000..e678aeab8
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.ewt
@@ -0,0 +1,358 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+  <fileVersion>2</fileVersion>
+  <configuration>
+    <name>Debug</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>RuntimeChecking</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>GenRtcDebugHeap</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenRtcEnableBoundsChecking</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenRtcCheckPtrsNonInstrMem</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GenRtcTrackPointerBounds</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GenRtcCheckAccesses</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GenRtcGenerateEntries</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenRtcNrTrackedPointers</name>
+          <state>1000</state>
+        </option>
+        <option>
+          <name>GenRtcIntOverflow</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenRtcIncUnsigned</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenRtcIntConversion</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenRtcInclExplicit</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenRtcIntShiftOverflow</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenRtcInclUnsignedShiftOverflow</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenRtcUnhandledCase</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenRtcDivByZero</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenRtcEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenRtcCheckPtrsNonInstrFunc</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+  </configuration>
+  <configuration>
+    <name>Release</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>0</debug>
+    <settings>
+      <name>RuntimeChecking</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>GenRtcDebugHeap</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenRtcEnableBoundsChecking</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenRtcCheckPtrsNonInstrMem</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GenRtcTrackPointerBounds</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GenRtcCheckAccesses</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GenRtcGenerateEntries</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenRtcNrTrackedPointers</name>
+          <state>1000</state>
+        </option>
+        <option>
+          <name>GenRtcIntOverflow</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenRtcIncUnsigned</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenRtcIntConversion</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenRtcInclExplicit</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenRtcIntShiftOverflow</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenRtcInclUnsignedShiftOverflow</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenRtcUnhandledCase</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenRtcDivByZero</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenRtcEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenRtcCheckPtrsNonInstrFunc</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+  </configuration>
+  <group>
+    <name>DriverLibrary</name>
+    <file>
+      <name>$PROJ_DIR$\driverlib\cpu.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\driverlib\cs.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\driverlib\fpu.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\driverlib\gpio.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\driverlib\interrupt.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\driverlib\pcm.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\driverlib\timer32.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\driverlib\uart.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\driverlib\wdt_a.c</name>
+    </file>
+  </group>
+  <group>
+    <name>FreeRTOS_Source</name>
+    <group>
+      <name>include</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\Source\include\event_groups.h</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\Source\include\FreeRTOS.h</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\Source\include\projdefs.h</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\Source\include\queue.h</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\Source\include\semphr.h</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\Source\include\task.h</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\Source\include\timers.h</name>
+      </file>
+    </group>
+    <group>
+      <name>Portable</name>
+      <group>
+        <name>IAR</name>
+        <group>
+          <name>Cortex-M4F</name>
+          <file>
+            <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM4F\port.c</name>
+          </file>
+          <file>
+            <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM4F\portasm.s</name>
+          </file>
+          <file>
+            <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM4F\portmacro.h</name>
+          </file>
+        </group>
+      </group>
+      <group>
+        <name>MemMang</name>
+        <file>
+          <name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_4.c</name>
+        </file>
+      </group>
+    </group>
+    <file>
+      <name>$PROJ_DIR$\..\..\Source\event_groups.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\Source\list.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\Source\queue.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\Source\tasks.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\Source\timers.c</name>
+    </file>
+  </group>
+  <group>
+    <name>Full_Demo</name>
+    <group>
+      <name>FreeRTOS+CLI</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-CLI\FreeRTOS_CLI.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-CLI\FreeRTOS_CLI.h</name>
+      </file>
+    </group>
+    <group>
+      <name>Standard Demo Tasks</name>
+      <file>
+        <name>$PROJ_DIR$\..\Common\Minimal\BlockQ.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\Common\Minimal\countsem.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\Common\Minimal\EventGroupsDemo.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\Common\Minimal\GenQTest.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\Common\Minimal\IntQueue.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\Common\Minimal\IntSemTest.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\Common\Minimal\recmutex.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\Common\Minimal\semtest.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\Common\Minimal\sp_flop.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\Common\Minimal\TaskNotify.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\Common\Minimal\TimerDemo.c</name>
+      </file>
+    </group>
+    <file>
+      <name>$PROJ_DIR$\Full_Demo\IntQueueTimer.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\Full_Demo\main_full.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\Full_Demo\RegTest.s</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\Full_Demo\RunTimeStatsTimer.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\FreeRTOS-Plus\Demo\Common\FreeRTOS_Plus_CLI_Demos\Sample-CLI-commands.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\Full_Demo\serial.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\FreeRTOS-Plus\Demo\Common\FreeRTOS_Plus_CLI_Demos\UARTCommandConsole.c</name>
+    </file>
+  </group>
+  <group>
+    <name>Simply Blinky Demo</name>
+    <file>
+      <name>$PROJ_DIR$\SimplyBlinkyDemo\main_blinky.c</name>
+    </file>
+  </group>
+  <group>
+    <name>System</name>
+    <file>
+      <name>$PROJ_DIR$\system\IAR\msp432_startup_ewarm.c</name>
+    </file>
+  </group>
+  <file>
+    <name>$PROJ_DIR$\FreeRTOSConfig.h</name>
+  </file>
+  <file>
+    <name>$PROJ_DIR$\main.c</name>
+  </file>
+</project>
+
+
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/RTOSDemo.eww b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.eww
index 239a9381e..239a9381e 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/RTOSDemo.eww
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.eww
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.uvoptx b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.uvoptx
new file mode 100644
index 000000000..867b22eb4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.uvoptx
@@ -0,0 +1,800 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>Target 1</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\Listings\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
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+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>4</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
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+        <tRwatch>1</tRwatch>
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+        <tRtrace>1</tRtrace>
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+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>CMSIS_AGDI</Key>
+          <Name>-X"XDS-ICDI (02.02.03.02) with CMSIS-DAP" -U00000001 -O175 -S8 -C0 -P00 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(0) -FO7 -FD1000000 -FC8000 -FN2 -FF0MSP432P4xx_MainFlash256kB.FLM -FS00 -FL040000 -FP0($$Device:MSP432P401R$Flash\MSP432P4xx_MainFlash256kB.FLM) -FF1MSP432P4xx_InfoFlash.FLM -FS1200000 -FL14000 -FP1($$Device:MSP432P401R$Flash\MSP432P4xx_InfoFlash.FLM)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
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+          <Key>ARMRTXEVENTFLAGS</Key>
+          <Name>-L70 -Z18 -C0 -M0 -T1</Name>
+        </SetRegEntry>
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+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
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+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>JL2CM3</Key>
+          <Name>-U59101789 -O47 -S5 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD1000000 -FC8000 -FN2 -FF0MSP432P4xx_MainFlash256kB.FLM -FS00 -FL040000 -FP0($$Device:MSP432P401R$Flash\MSP432P4xx_MainFlash256kB.FLM) -FF1MSP432P4xx_InfoFlash.FLM -FS1200000 -FL14000 -FP1($$Device:MSP432P401R$Flash\MSP432P4xx_InfoFlash.FLM)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
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+          <Key>UL2CM3</Key>
+          <Name>-UM0149MEE -O175 -S8 -C0 -P00 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD1000000 -FC8000 -FN2 -FF0MSP432P4xx_MainFlash256kB.FLM -FS00 -FL040000 -FP0($$Device:MSP432P401R$Flash\MSP432P4xx_MainFlash256kB.FLM) -FF1MSP432P4xx_InfoFlash.FLM -FS1200000 -FL14000 -FP1($$Device:MSP432P401R$Flash\MSP432P4xx_InfoFlash.FLM)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
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+          <WinNumber>1</WinNumber>
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+          <ItemText>ulx,0x0A</ItemText>
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+      </Tracepoint>
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+        <periodic>1</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
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+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <DebugDescription>
+        <Enable>1</Enable>
+        <EnableLog>0</EnableLog>
+        <Protocol>1</Protocol>
+        <DbgClock>10000000</DbgClock>
+      </DebugDescription>
+    </TargetOption>
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diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.uvprojx b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.uvprojx
new file mode 100644
index 000000000..6f4945c88
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.uvprojx
@@ -0,0 +1,675 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>Target 1</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>MSP432P401R</Device>
+          <Vendor>Texas Instruments</Vendor>
+          <PackID>TI.MSP432.1.0.0</PackID>
+          <Cpu>IROM(0x00000000,0x00040000) IROM2(0x00200000,0x00004000) IRAM(0x20000000,0x00010000) IRAM2(0x01000000,0x00010000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD01000000 -FC8000 -FN2 -FF0MSP432P4xx_MainFlash256kB -FS00 -FL040000 -FF1MSP432P4xx_InfoFlash -FS1200000 -FL14000 -FP0($$Device:MSP432P401R$Flash\MSP432P4xx_MainFlash256kB.FLM) -FP1($$Device:MSP432P401R$Flash\MSP432P4xx_InfoFlash.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:MSP432P401R$Device\Include\msp.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:MSP432P401R$SVD\MSP432P401R.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
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+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Keil_Debug\</OutputDirectory>
+          <OutputName>RTOSDemo</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\Listings\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
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+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
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+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
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+            <UserProg1Name></UserProg1Name>
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+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
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+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
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+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
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+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
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+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
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+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
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+          </OPTHX>
+          <Simulator>
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+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
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+          </Simulator>
+          <Target>
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+            <RestoreBreakpoints>1</RestoreBreakpoints>
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+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
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+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
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+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
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+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x10000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x200000</StartAddress>
+                <Size>0x4000</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x1000000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>0</uC99>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>keil __MSP432P401R__</Define>
+              <Undefine></Undefine>
+              <IncludePath>.\driverlib;..\CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil;.\Full_Demo;..\Common\include;..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-CLI;..\..\Source\include;..\..\Source\portable\RVDS\ARM_CM4F</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>system</GroupName>
+          <Files>
+            <File>
+              <FileName>startup_MSP432P4.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>.\system\Keil\startup_MSP432P4.s</FilePath>
+            </File>
+            <File>
+              <FileName>system_MSP432P4.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\system\Keil\system_MSP432P4.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>main</GroupName>
+          <Files>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>FreeRTOSConfig.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\FreeRTOSConfig.h</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Simple Blinky Demo</GroupName>
+          <Files>
+            <File>
+              <FileName>main_blinky.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\SimplyBlinkyDemo\main_blinky.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>FreeRTOS Source</GroupName>
+          <Files>
+            <File>
+              <FileName>event_groups.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\Source\event_groups.c</FilePath>
+            </File>
+            <File>
+              <FileName>list.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\Source\list.c</FilePath>
+            </File>
+            <File>
+              <FileName>queue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\Source\queue.c</FilePath>
+            </File>
+            <File>
+              <FileName>tasks.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\Source\tasks.c</FilePath>
+            </File>
+            <File>
+              <FileName>timers.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\Source\timers.c</FilePath>
+            </File>
+            <File>
+              <FileName>heap_4.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\Source\portable\MemMang\heap_4.c</FilePath>
+            </File>
+            <File>
+              <FileName>port.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\Source\portable\RVDS\ARM_CM4F\port.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Full Demo</GroupName>
+          <Files>
+            <File>
+              <FileName>main_full.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Full_Demo\main_full.c</FilePath>
+            </File>
+            <File>
+              <FileName>RunTimeStatsTimer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Full_Demo\RunTimeStatsTimer.c</FilePath>
+            </File>
+            <File>
+              <FileName>serial.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Full_Demo\serial.c</FilePath>
+            </File>
+            <File>
+              <FileName>BlockQ.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\BlockQ.c</FilePath>
+            </File>
+            <File>
+              <FileName>countsem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\countsem.c</FilePath>
+            </File>
+            <File>
+              <FileName>EventGroupsDemo.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\EventGroupsDemo.c</FilePath>
+            </File>
+            <File>
+              <FileName>GenQTest.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\GenQTest.c</FilePath>
+            </File>
+            <File>
+              <FileName>IntSemTest.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\IntSemTest.c</FilePath>
+            </File>
+            <File>
+              <FileName>recmutex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\recmutex.c</FilePath>
+            </File>
+            <File>
+              <FileName>semtest.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\semtest.c</FilePath>
+            </File>
+            <File>
+              <FileName>sp_flop.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\sp_flop.c</FilePath>
+            </File>
+            <File>
+              <FileName>TaskNotify.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\TaskNotify.c</FilePath>
+            </File>
+            <File>
+              <FileName>TimerDemo.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\TimerDemo.c</FilePath>
+            </File>
+            <File>
+              <FileName>FreeRTOS_CLI.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-CLI\FreeRTOS_CLI.c</FilePath>
+            </File>
+            <File>
+              <FileName>Sample-CLI-commands.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\FreeRTOS-Plus\Demo\Common\FreeRTOS_Plus_CLI_Demos\Sample-CLI-commands.c</FilePath>
+            </File>
+            <File>
+              <FileName>UARTCommandConsole.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\FreeRTOS-Plus\Demo\Common\FreeRTOS_Plus_CLI_Demos\UARTCommandConsole.c</FilePath>
+            </File>
+            <File>
+              <FileName>RegTest.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Full_Demo\RegTest.c</FilePath>
+            </File>
+            <File>
+              <FileName>IntQueueTimer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Full_Demo\IntQueueTimer.c</FilePath>
+            </File>
+            <File>
+              <FileName>IntQueue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\IntQueue.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Driver Library</GroupName>
+          <Files>
+            <File>
+              <FileName>cpu.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\driverlib\cpu.c</FilePath>
+            </File>
+            <File>
+              <FileName>cs.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\driverlib\cs.c</FilePath>
+            </File>
+            <File>
+              <FileName>gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\driverlib\gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>interrupt.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\driverlib\interrupt.c</FilePath>
+            </File>
+            <File>
+              <FileName>pcm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\driverlib\pcm.c</FilePath>
+            </File>
+            <File>
+              <FileName>uart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\driverlib\uart.c</FilePath>
+            </File>
+            <File>
+              <FileName>wdt_a.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\driverlib\wdt_a.c</FilePath>
+            </File>
+            <File>
+              <FileName>sysctl.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\driverlib\sysctl.c</FilePath>
+            </File>
+            <File>
+              <FileName>fpu.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\driverlib\fpu.c</FilePath>
+            </File>
+            <File>
+              <FileName>timer32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\driverlib\timer32.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="3.40.0" condition="CMSIS Core">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.2.0"/>
+        <targetInfos>
+          <targetInfo name="Target 1"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files>
+      <file attr="config" category="source" name="Device\Source\startup_MSP432P4.s">
+        <instance index="0" removed="1">RTE\Device\MSP432P401R\startup_MSP432P4.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="TI" Cversion="1.0.0" condition="MSP432 CMSIS-CORE"/>
+        <package license="license.txt" name="MSP432" schemaVersion="1.2" vendor="TI" version="1.0.0"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="source" name="Device\Source\system_MSP432P4.c">
+        <instance index="0" removed="1">RTE\Device\MSP432P401R\system_MSP432P4.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="TI" Cversion="1.0.0" condition="MSP432 CMSIS-CORE"/>
+        <package license="license.txt" name="MSP432" schemaVersion="1.2" vendor="TI" version="1.0.0"/>
+        <targetInfos/>
+      </file>
+    </files>
+  </RTE>
+
+</Project>
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/SimplyBlinkyDemo/main_blinky.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/SimplyBlinkyDemo/main_blinky.c
new file mode 100644
index 000000000..dd1f035c8
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/SimplyBlinkyDemo/main_blinky.c
@@ -0,0 +1,308 @@
+/*
+    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/******************************************************************************
+ * NOTE 1:  This project provides two demo applications.  A simple blinky style
+ * project, and a more comprehensive test and demo application.  The
+ * configCREATE_SIMPLE_TICKLESS_DEMO setting in FreeRTOSConfig.h is used to
+ * select between the two.  See the notes on using
+ * configCREATE_SIMPLE_TICKLESS_DEMO in main.c.  This file implements the
+ * simply blinky style version.
+ *
+ * The blinky demo uses FreeRTOS's tickless idle mode to reduce power 
+ * consumption.  See the notes on the web page below regarding the difference
+ * in power saving that can be achieved between using the generic tickless
+ * implementation (as used by the blinky demo) and a tickless implementation
+ * that is tailored specifically to the MSP432.
+ * 
+ * See http://www.FreeRTOS.org/TI_MSP432_Free_RTOS_Demo.html for instructions.
+ *
+ * NOTE 2:  This file only contains the source code that is specific to the
+ * basic demo.  Generic functions, such FreeRTOS hook functions, and functions
+ * required to configure the hardware, are defined in main.c.
+ ******************************************************************************
+ *
+ * main_blinky() creates one queue, and two tasks.  It then starts the
+ * scheduler.
+ *
+ * The Queue Send Task:
+ * The queue send task is implemented by the prvQueueSendTask() function in
+ * this file.  prvQueueSendTask() sits in a loop that causes it to repeatedly
+ * block for 200 milliseconds, before sending the value 100 to the queue that
+ * was created within main_blinky().  Once the value is sent, the task loops
+ * back around to block for another 200 milliseconds.
+ *
+ * The Queue Receive Task:
+ * The queue receive task is implemented by the prvQueueReceiveTask() function
+ * in this file.  prvQueueReceiveTask() sits in a loop where it repeatedly
+ * blocks on attempts to read data from the queue that was created within
+ * main_blinky().  When data is received, the task checks the value of the
+ * data, and if the value equals the expected 100, toggles the LED.  The 'block
+ * time' parameter passed to the queue receive function specifies that the
+ * task should be held in the Blocked state indefinitely to wait for data to
+ * be available on the queue.  The queue receive task will only leave the
+ * Blocked state when the queue send task writes to the queue.  As the queue
+ * send task writes to the queue every 200 milliseconds, the queue receive
+ * task leaves the Blocked state every 200 milliseconds, and therefore toggles
+ * the LED every 200 milliseconds.
+ */
+
+/* Standard includes. */
+#include <stdio.h>
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+
+/* Priorities at which the tasks are created. */
+#define mainQUEUE_RECEIVE_TASK_PRIORITY		( tskIDLE_PRIORITY + 2 )
+#define	mainQUEUE_SEND_TASK_PRIORITY		( tskIDLE_PRIORITY + 1 )
+
+/* The rate at which data is sent to the queue.  The 200ms value is converted
+to ticks using the portTICK_PERIOD_MS constant. */
+#define mainQUEUE_SEND_FREQUENCY_MS			( pdMS_TO_TICKS( 1000UL ) )
+
+/* The number of items the queue can hold.  This is 1 as the receive task
+will remove items as they are added, meaning the send task should always find
+the queue empty. */
+#define mainQUEUE_LENGTH					( 1 )
+
+/* Values passed to the two tasks just to check the task parameter
+functionality. */
+#define mainQUEUE_SEND_PARAMETER			( 0x1111UL )
+#define mainQUEUE_RECEIVE_PARAMETER			( 0x22UL )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The tasks as described in the comments at the top of this file.
+ */
+static void prvQueueReceiveTask( void *pvParameters );
+static void prvQueueSendTask( void *pvParameters );
+
+/*
+ * Called by main() to create the simply blinky style application if
+ * configCREATE_SIMPLE_TICKLESS_DEMO is set to 1.
+ */
+void main_blinky( void );
+
+/*
+ * The full demo configures the clocks for maximum frequency, wheras this blinky
+ * demo uses a slower clock as it also uses low power features.
+ */
+static void prvConfigureClocks( void );
+
+/*-----------------------------------------------------------*/
+
+/* The queue used by both tasks. */
+static QueueHandle_t xQueue = NULL;
+
+/*-----------------------------------------------------------*/
+
+void main_blinky( void )
+{
+	/* See http://www.FreeRTOS.org/TI_MSP432_Free_RTOS_Demo.html for 
+	instructions and notes regarding the difference in power saving that can be 
+	achieved between using the generic tickless RTOS implementation (as used by 
+	the blinky demo) and a tickless RTOS implementation that is tailored 
+	specifically to the MSP432. */
+
+	/* The full demo configures the clocks for maximum frequency, wheras this
+	blinky demo uses a slower clock as it also uses low power features. */
+	prvConfigureClocks();
+
+	/* Create the queue. */
+	xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) );
+
+	if( xQueue != NULL )
+	{
+		/* Start the two tasks as described in the comments at the top of this
+		file. */
+		xTaskCreate( prvQueueReceiveTask,					/* The function that implements the task. */
+					"Rx", 									/* The text name assigned to the task - for debug only as it is not used by the kernel. */
+					configMINIMAL_STACK_SIZE, 				/* The size of the stack to allocate to the task. */
+					( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */
+					mainQUEUE_RECEIVE_TASK_PRIORITY, 		/* The priority assigned to the task. */
+					NULL );									/* The task handle is not required, so NULL is passed. */
+
+		xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL );
+
+		/* Start the tasks and timer running. */
+		vTaskStartScheduler();
+	}
+
+	/* If all is well, the scheduler will now be running, and the following
+	line will never be reached.  If the following line does execute, then
+	there was insufficient FreeRTOS heap memory available for the idle and/or
+	timer tasks	to be created.  See the memory management section on the
+	FreeRTOS web site for more details. */
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+static void prvQueueSendTask( void *pvParameters )
+{
+TickType_t xNextWakeTime;
+const unsigned long ulValueToSend = 100UL;
+
+	/* Check the task parameter is as expected. */
+	configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER );
+
+	/* Initialise xNextWakeTime - this only needs to be done once. */
+	xNextWakeTime = xTaskGetTickCount();
+
+	for( ;; )
+	{
+		/* Place this task in the blocked state until it is time to run again.
+		The block time is specified in ticks, the constant used converts ticks
+		to ms.  While in the Blocked state this task will not consume any CPU
+		time. */
+		vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );
+
+		/* Send to the queue - causing the queue receive task to unblock and
+		toggle the LED.  0 is used as the block time so the sending operation
+		will not block - it shouldn't need to block as the queue should always
+		be empty at this point in the code. */
+		xQueueSend( xQueue, &ulValueToSend, 0U );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvQueueReceiveTask( void *pvParameters )
+{
+unsigned long ulReceivedValue;
+static const TickType_t xShortBlock = pdMS_TO_TICKS( 50 );
+
+	/* Check the task parameter is as expected. */
+	configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER );
+
+	for( ;; )
+	{
+		/* Wait until something arrives in the queue - this task will block
+		indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
+		FreeRTOSConfig.h. */
+		xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
+
+		/*  To get here something must have been received from the queue, but
+		is it the expected value?  If it is, toggle the LED. */
+		if( ulReceivedValue == 100UL )
+		{
+			/* Blip the LED for a short while so as not to use too much
+			power. */
+			configTOGGLE_LED();
+			vTaskDelay( xShortBlock );
+			configTOGGLE_LED();
+			ulReceivedValue = 0U;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvConfigureClocks( void )
+{
+	/* The full demo configures the clocks for maximum frequency, wheras this
+	blinky demo uses a slower clock as it also uses low power features.
+
+	From the datashee:  For AM_LDO_VCORE0 and AM_DCDC_VCORE0 modes, the maximum
+	CPU operating frequency is 24 MHz and maximum input clock frequency for
+	peripherals is 12 MHz. */
+	CS_setDCOCenteredFrequency( CS_DCO_FREQUENCY_3 );
+	CS_initClockSignal( CS_HSMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 );
+	CS_initClockSignal( CS_SMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 );
+	CS_initClockSignal( CS_MCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 );
+	CS_initClockSignal( CS_ACLK, CS_REFOCLK_SELECT, CS_CLOCK_DIVIDER_1 );
+
+	/* The lower frequency allows the use of CVORE level 0. */
+	PCM_setCoreVoltageLevel( PCM_VCORE0 );
+}
+/*-----------------------------------------------------------*/
+
+void vPreSleepProcessing( uint32_t ulExpectedIdleTime )
+{
+
+}
+/*-----------------------------------------------------------*/
+
+#if( configCREATE_SIMPLE_TICKLESS_DEMO == 1 )
+
+	void vApplicationTickHook( void )
+	{
+		/* This function will be called by each tick interrupt if
+		configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h.  User code can be
+		added here, but the tick hook is called from an interrupt context, so
+		code must not attempt to block, and only the interrupt safe FreeRTOS API
+		functions can be used (those that end in FromISR()). */
+
+		/* Only the full demo uses the tick hook so there is no code is
+		executed here. */
+	}
+
+#endif
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/adc14.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/adc14.c
new file mode 100644
index 000000000..c39f1e5e7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/adc14.c
@@ -0,0 +1,748 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+/* Standard Includes */
+#include <stdint.h>
+#include <stdbool.h>
+
+/* DriverLib Includes */
+#include <adc14.h>
+#include <debug.h>
+#include <interrupt.h>
+
+/* Statics */
+static volatile uint32_t* const _ctlRegs[32] =
+{ &ADC14->rMCTL0.r, &ADC14->rMCTL1.r, &ADC14->rMCTL2.r, &ADC14->rMCTL3.r,
+        &ADC14->rMCTL4.r, &ADC14->rMCTL5.r, &ADC14->rMCTL6.r, &ADC14->rMCTL7.r,
+        &ADC14->rMCTL8.r, &ADC14->rMCTL9.r, &ADC14->rMCTL10.r,
+        &ADC14->rMCTL11.r, &ADC14->rMCTL12.r, &ADC14->rMCTL13.r,
+        &ADC14->rMCTL14.r, &ADC14->rMCTL15.r, &ADC14->rMCTL16.r,
+        &ADC14->rMCTL17.r, &ADC14->rMCTL18.r, &ADC14->rMCTL19.r,
+        &ADC14->rMCTL20.r, &ADC14->rMCTL21.r, &ADC14->rMCTL22.r,
+        &ADC14->rMCTL23.r, &ADC14->rMCTL24.r, &ADC14->rMCTL25.r,
+        &ADC14->rMCTL26.r, &ADC14->rMCTL27.r, &ADC14->rMCTL28.r,
+        &ADC14->rMCTL29.r, &ADC14->rMCTL30.r, &ADC14->rMCTL31.r };
+
+static uint_fast8_t _getIndexForMemRegister(uint32_t reg)
+{
+    switch (reg)
+    {
+    case ADC_MEM0:
+        return 0;
+    case ADC_MEM1:
+        return 1;
+    case ADC_MEM2:
+        return 2;
+    case ADC_MEM3:
+        return 3;
+    case ADC_MEM4:
+        return 4;
+    case ADC_MEM5:
+        return 5;
+    case ADC_MEM6:
+        return 6;
+    case ADC_MEM7:
+        return 7;
+    case ADC_MEM8:
+        return 8;
+    case ADC_MEM9:
+        return 9;
+    case ADC_MEM10:
+        return 10;
+    case ADC_MEM11:
+        return 11;
+    case ADC_MEM12:
+        return 12;
+    case ADC_MEM13:
+        return 13;
+    case ADC_MEM14:
+        return 14;
+    case ADC_MEM15:
+        return 15;
+    case ADC_MEM16:
+        return 16;
+    case ADC_MEM17:
+        return 17;
+    case ADC_MEM18:
+        return 18;
+    case ADC_MEM19:
+        return 19;
+    case ADC_MEM20:
+        return 20;
+    case ADC_MEM21:
+        return 21;
+    case ADC_MEM22:
+        return 22;
+    case ADC_MEM23:
+        return 23;
+    case ADC_MEM24:
+        return 24;
+    case ADC_MEM25:
+        return 25;
+    case ADC_MEM26:
+        return 26;
+    case ADC_MEM27:
+        return 27;
+    case ADC_MEM28:
+        return 28;
+    case ADC_MEM29:
+        return 29;
+    case ADC_MEM30:
+        return 30;
+    case ADC_MEM31:
+        return 31;
+    default:
+        ASSERT(false);
+        return ADC_INVALID_MEM;
+
+    }
+}
+
+//*****************************************************************************
+//
+//!
+//! Returns a boolean value that tells if conversion is active/running or is
+//! not acMSP432 ted.
+//!
+//! Originally a public function, but moved to static. External customers should
+//! use the ADC14_isBusy function.
+//!
+//! \return true if conversion is active, false otherwise
+//
+//*****************************************************************************
+static bool ADCIsConversionRunning(void)
+{
+    return BITBAND_PERI(ADC14->rCTL0.r, ADC14BUSY_OFS);
+}
+
+void ADC14_enableModule(void)
+{
+    BITBAND_PERI(ADC14->rCTL0.r, ADC14ON_OFS) = 1;
+}
+
+bool ADC14_disableModule(void)
+{
+    if (ADCIsConversionRunning())
+        return false;
+
+    BITBAND_PERI(ADC14->rCTL0.r, ADC14ON_OFS) = 0;
+
+    return true;
+}
+
+bool ADC14_enableSampleTimer(uint32_t multiSampleConvert)
+{
+    if (ADCIsConversionRunning())
+        return false;
+
+    BITBAND_PERI(ADC14->rCTL0.r, ADC14SHP_OFS) = 1;
+
+    if (multiSampleConvert == ADC_MANUAL_ITERATION)
+    {
+        BITBAND_PERI(ADC14->rCTL0.r, ADC14MSC_OFS) = 0;
+    } else
+    {
+        BITBAND_PERI(ADC14->rCTL0.r, ADC14MSC_OFS) = 1;
+    }
+
+    return true;
+}
+
+bool ADC14_disableSampleTimer(void)
+{
+    if (ADCIsConversionRunning())
+        return false;
+
+    BITBAND_PERI(ADC14->rCTL0.r, ADC14SHP_OFS) = 0;
+
+    return true;
+}
+
+bool ADC14_initModule(uint32_t clockSource, uint32_t clockPredivider,
+        uint32_t clockDivider, uint32_t internalChannelMask)
+{
+    ASSERT(
+            clockSource == ADC_CLOCKSOURCE_ADCOSC
+            || clockSource == ADC_CLOCKSOURCE_SYSOSC
+            || clockSource == ADC_CLOCKSOURCE_ACLK
+            || clockSource == ADC_CLOCKSOURCE_MCLK
+            || clockSource == ADC_CLOCKSOURCE_SMCLK
+            || clockSource == ADC_CLOCKSOURCE_HSMCLK);
+
+    ASSERT(
+            clockPredivider == ADC_PREDIVIDER_1
+            || clockPredivider == ADC_PREDIVIDER_4
+            || clockPredivider == ADC_PREDIVIDER_32
+            || clockPredivider == ADC_PREDIVIDER_64);
+
+    ASSERT(
+            clockDivider == ADC_DIVIDER_1 || clockDivider == ADC_DIVIDER_2
+            || clockDivider == ADC_DIVIDER_3
+            || clockDivider == ADC_DIVIDER_4
+            || clockDivider == ADC_DIVIDER_5
+            || clockDivider == ADC_DIVIDER_6
+            || clockDivider == ADC_DIVIDER_7
+            || clockDivider == ADC_DIVIDER_8);
+
+    ASSERT(
+            !(internalChannelMask
+                    & ~(ADC_MAPINTCH3 | ADC_MAPINTCH2 | ADC_MAPINTCH1
+                            | ADC_MAPINTCH0 | ADC_TEMPSENSEMAP | ADC_BATTMAP)));
+
+    if (ADCIsConversionRunning())
+        return false;
+
+    ADC14->rCTL0.r = (ADC14->rCTL0.r
+            & ~(ADC14PDIV_M | ADC14DIV_M | ADC14SSEL_M))
+            | clockDivider | clockPredivider | clockSource;
+
+    ADC14->rCTL1.r = (ADC14->rCTL1.r
+            & ~(ADC_MAPINTCH3 | ADC_MAPINTCH2 | ADC_MAPINTCH1 | ADC_MAPINTCH0
+                    | ADC_TEMPSENSEMAP | ADC_BATTMAP)) | internalChannelMask;
+
+    return true;
+}
+
+void ADC14_setResolution(uint32_t resolution)
+{
+    ASSERT(
+            resolution == ADC_8BIT || resolution == ADC_10BIT
+            || resolution == ADC_12BIT || resolution == ADC_14BIT);
+
+    ADC14->rCTL1.r = (ADC14->rCTL1.r & ~ADC14RES_M) |  resolution;
+}
+
+uint_fast32_t ADC14_getResolution(void)
+{
+    return ADC14->rCTL1.r & ADC14RES_M;
+}
+
+bool ADC14_setSampleHoldTrigger(uint32_t source, bool invertSignal)
+{
+
+    ASSERT(
+            source == ADC_TRIGGER_ADCSC || source == ADC_TRIGGER_SOURCE1
+            || source == ADC_TRIGGER_SOURCE2
+            || source == ADC_TRIGGER_SOURCE3
+            || source == ADC_TRIGGER_SOURCE4
+            || source == ADC_TRIGGER_SOURCE5
+            || source == ADC_TRIGGER_SOURCE6
+            || source == ADC_TRIGGER_SOURCE7);
+
+    if (ADCIsConversionRunning())
+        return false;
+
+    if (invertSignal)
+    {
+        ADC14->rCTL0.r = (ADC14->rCTL0.r
+                & ~(ADC14ISSH | ADC14SHS_M)) | source
+                | ADC14ISSH;
+    } else
+    {
+        ADC14->rCTL0.r = (ADC14->rCTL0.r
+                & ~(ADC14ISSH | ADC14SHS_M)) | source;
+    }
+
+    return true;
+}
+
+bool ADC14_setSampleHoldTime(uint32_t firstPulseWidth,
+        uint32_t secondPulseWidth)
+{
+    ASSERT(
+            firstPulseWidth == ADC_PULSE_WIDTH_4
+            || firstPulseWidth == ADC_PULSE_WIDTH_8
+            || firstPulseWidth == ADC_PULSE_WIDTH_16
+            || firstPulseWidth == ADC_PULSE_WIDTH_32
+            || firstPulseWidth == ADC_PULSE_WIDTH_64
+            || firstPulseWidth == ADC_PULSE_WIDTH_96
+            || firstPulseWidth == ADC_PULSE_WIDTH_128
+            || firstPulseWidth == ADC_PULSE_WIDTH_192);
+
+    ASSERT(
+            secondPulseWidth == ADC_PULSE_WIDTH_4
+            || secondPulseWidth == ADC_PULSE_WIDTH_8
+            || secondPulseWidth == ADC_PULSE_WIDTH_16
+            || secondPulseWidth == ADC_PULSE_WIDTH_32
+            || secondPulseWidth == ADC_PULSE_WIDTH_64
+            || secondPulseWidth == ADC_PULSE_WIDTH_96
+            || secondPulseWidth == ADC_PULSE_WIDTH_128
+            || secondPulseWidth == ADC_PULSE_WIDTH_192);
+
+    if (ADCIsConversionRunning())
+        return false;
+
+    ADC14->rCTL0.r = (ADC14->rCTL0.r
+            & ~(ADC14SHT0_M | ADC14SHT1_M)) | secondPulseWidth
+            | (firstPulseWidth >> 4);
+
+    return true;
+}
+
+bool ADC14_configureMultiSequenceMode(uint32_t memoryStart, uint32_t memoryEnd,
+bool repeatMode)
+{
+    uint32_t ii;
+
+    ASSERT(
+            _getIndexForMemRegister(memoryStart) != ADC_INVALID_MEM
+            && _getIndexForMemRegister(memoryEnd) != ADC_INVALID_MEM);
+
+    if (ADCIsConversionRunning())
+        return false;
+
+    /* Clearing out any lingering EOS */
+    for (ii = 0; ii < 32; ii++)
+    {
+        BITBAND_PERI(*(_ctlRegs[ii]), ADC14EOS_OFS) = 0;
+    }
+
+    /* Setting Start/Stop locations */
+    BITBAND_PERI(
+            (*(_ctlRegs[_getIndexForMemRegister(memoryEnd)])),
+            ADC14EOS_OFS) = 1;
+
+    ADC14->rCTL1.r = (ADC14->rCTL1.r & ~(ADC14CSTARTADD_M))
+                    | (_getIndexForMemRegister(memoryStart) << 16);
+
+    /* Setting multiple sample mode */
+    if (!repeatMode)
+    {
+        ADC14->rCTL0.r = (ADC14->rCTL0.r & ~(ADC14CONSEQ_M))
+                | (ADC14CONSEQ_1);
+    } else
+    {
+        ADC14->rCTL0.r = (ADC14->rCTL0.r & ~(ADC14CONSEQ_M))
+                | (ADC14CONSEQ_3);
+    }
+
+    return true;
+}
+
+bool ADC14_configureSingleSampleMode(uint32_t memoryDestination,
+bool repeatMode)
+{
+    ASSERT(_getIndexForMemRegister(memoryDestination) != 32);
+
+    if (ADCIsConversionRunning())
+        return false;
+
+    /* Setting the destination register */
+    ADC14->rCTL1.r = (ADC14->rCTL1.r & ~(ADC14CSTARTADD_M))
+            | (_getIndexForMemRegister(memoryDestination) << 16);
+
+    /* Setting single sample mode */
+    if (!repeatMode)
+    {
+        ADC14->rCTL0.r = (ADC14->rCTL0.r & ~(ADC14CONSEQ_M))
+                | (ADC14CONSEQ_0);
+    } else
+    {
+        ADC14->rCTL0.r = (ADC14->rCTL0.r & ~(ADC14CONSEQ_M))
+                | (ADC14CONSEQ_2);
+    }
+
+    return true;
+}
+
+bool ADC14_enableConversion(void)
+{
+    if (ADCIsConversionRunning() || !BITBAND_PERI(ADC14->rCTL0.r, ADC14ON_OFS))
+        return false;
+
+    ADC14->rCTL0.r |= (ADC14ENC);
+
+    return true;
+}
+
+bool ADC14_toggleConversionTrigger(void)
+{
+    if (!BITBAND_PERI(ADC14->rCTL0.r, ADC14ON_OFS))
+        return false;
+
+    if (BITBAND_PERI(ADC14->rCTL0.r, ADC14SC_OFS))
+    {
+        BITBAND_PERI(ADC14->rCTL0.r, ADC14SC_OFS) = 0;
+    } else
+    {
+        BITBAND_PERI(ADC14->rCTL0.r, ADC14SC_OFS) = 1;
+    }
+
+    return true;
+}
+
+void ADC14_disableConversion(void)
+{
+    ADC14->rCTL0.r &= ~(ADC14SC | ADC14ENC);
+}
+
+bool ADC14_isBusy(void)
+{
+    return BITBAND_PERI(ADC14->rCTL0.r, ADC14BUSY_OFS);
+}
+
+bool ADC14_configureConversionMemory(uint32_t memorySelect, uint32_t refSelect,
+        uint32_t channelSelect, bool differntialMode)
+{
+    uint32_t currentReg, ii;
+    uint32_t *curReg;
+
+    /* Initialization */
+    ii = 1;
+    currentReg = 0x01;
+
+    if (ADCIsConversionRunning())
+        return false;
+
+    while (memorySelect != 0)
+    {
+        if (!(memorySelect & ii))
+        {
+            ii = ii << 1;
+            continue;
+        }
+
+        currentReg = memorySelect & ii;
+        memorySelect &= ~ii;
+        ii = ii << 1;
+
+        curReg = (uint32_t*) _ctlRegs[_getIndexForMemRegister(currentReg)];
+
+        if (differntialMode)
+        {
+            (*curReg) = ((*curReg)
+                    & ~(ADC14VRSEL_M | ADC14INCH_M
+                            | ADC14DIF))
+                    | (channelSelect | refSelect | ADC14DIF);
+        } else
+        {
+            (*curReg) = ((*curReg)
+                    & ~(ADC14VRSEL_M | ADC14INCH_M
+                            | ADC14DIF)) | (channelSelect | refSelect);
+        }
+
+    }
+
+    return true;
+}
+
+bool ADC14_enableComparatorWindow(uint32_t memorySelect, uint32_t windowSelect)
+{
+    uint32_t currentReg, ii;
+    uint32_t *curRegPoint;
+
+    /* Initialization */
+    ii = 1;
+    currentReg = 0x01;
+
+    if (ADCIsConversionRunning())
+        return false;
+
+    while (memorySelect != 0)
+    {
+        if (!(memorySelect & ii))
+        {
+            ii = ii << 1;
+            continue;
+        }
+
+        currentReg = memorySelect & ii;
+        memorySelect &= ~ii;
+        ii = ii << 1;
+
+        curRegPoint =
+                (uint32_t*) _ctlRegs[_getIndexForMemRegister(currentReg)];
+
+        if (windowSelect == ADC_COMP_WINDOW0)
+        {
+            (*curRegPoint) = ((*curRegPoint)
+                    & ~(ADC14WINC | ADC14WINCTH))
+                    | (ADC14WINC);
+        } else if (windowSelect == ADC_COMP_WINDOW1)
+        {
+            (*curRegPoint) |= ADC14WINC | ADC14WINCTH;
+        }
+
+    }
+
+    return true;
+}
+
+bool ADC14_disableComparatorWindow(uint32_t memorySelect)
+{
+    uint32_t currentReg, ii;
+
+    /* Initialization */
+    ii = 1;
+    currentReg = 0x01;
+
+    if (ADCIsConversionRunning())
+        return false;
+
+    while (memorySelect != 0)
+    {
+        if (!(memorySelect & ii))
+        {
+            ii = ii << 1;
+            continue;
+        }
+
+        currentReg = memorySelect & ii;
+        memorySelect &= ~ii;
+        ii = ii << 1;
+
+        (*(_ctlRegs[_getIndexForMemRegister(currentReg)])) &=
+                ~ADC14WINC;
+
+    }
+
+    return true;
+}
+
+bool ADC14_setComparatorWindowValue(uint32_t window, int16_t low, int16_t high)
+{
+    if (ADCIsConversionRunning())
+        return false;
+
+    if (window == ADC_COMP_WINDOW0)
+    {
+        ADC14->rHI0.r = (high);
+        ADC14->rLO0.r = (low);
+
+    } else if (window == ADC_COMP_WINDOW1)
+    {
+        ADC14->rHI1.r = (high);
+        ADC14->rLO1.r = (low);
+
+    } else
+    {
+        ASSERT(false);
+    }
+
+    return true;
+}
+
+bool ADC14_setResultFormat(uint32_t resultFormat)
+{
+    if (ADCIsConversionRunning())
+        return false;
+
+    if (resultFormat == ADC_UNSIGNED_BINARY)
+    {
+        BITBAND_PERI(ADC14->rCTL1.r, ADC14DF_OFS) = 0;
+    } else if (resultFormat == ADC_SIGNED_BINARY)
+    {
+        BITBAND_PERI(ADC14->rCTL1.r, ADC14DF_OFS) = 1;
+    } else
+    {
+        ASSERT(false);
+    }
+
+    return true;
+}
+
+uint_fast16_t ADC14_getResult(uint32_t memorySelect)
+{
+    return *((uint16_t*) (_ctlRegs[_getIndexForMemRegister(memorySelect)]
+            + 0x80));
+}
+
+void ADC14_getMultiSequenceResult(uint16_t* res)
+{
+    uint32_t *startAddr, *curAddr;
+    uint32_t ii;
+
+    startAddr = (uint32_t*) _ctlRegs[(ADC14->rCTL1.r & ADC14CSTARTADD_M)
+            >> 16];
+
+    curAddr = startAddr;
+
+    for (ii = 0; ii < 32; ii++)
+    {
+        res[ii] = *(((uint16_t*) curAddr) + 0x80);
+
+        if (BITBAND_PERI((*curAddr), ADC14EOS_OFS))
+            break;
+
+        if (curAddr == _ctlRegs[31])
+            curAddr = (uint32_t*) _ctlRegs[0];
+        else
+            curAddr += 0x04;
+    }
+
+}
+
+void ADC14_getResultArray(uint32_t memoryStart, uint32_t memoryEnd,
+        uint16_t* res)
+{
+    uint32_t ii = 0;
+    uint32_t *firstPoint, *secondPoint;
+
+    bool foundEnd = false;
+
+    ASSERT(
+            _getIndexForMemRegister(memoryStart) != ADC_INVALID_MEM
+            && _getIndexForMemRegister(memoryEnd) != ADC_INVALID_MEM);
+
+    firstPoint = (uint32_t*) _ctlRegs[_getIndexForMemRegister(memoryStart)];
+    secondPoint = (uint32_t*) _ctlRegs[_getIndexForMemRegister(memoryEnd)];
+
+    while (!foundEnd)
+    {
+        if (firstPoint == secondPoint)
+        {
+            foundEnd = true;
+        }
+
+        res[ii] = *(((uint16_t*) firstPoint) + 0x80);
+
+        if (firstPoint == _ctlRegs[31])
+            firstPoint = (uint32_t*) _ctlRegs[0];
+        else
+            firstPoint += 0x04;
+    }
+}
+
+bool ADC14_enableReferenceBurst(void)
+{
+    if (ADCIsConversionRunning())
+        return false;
+
+    BITBAND_PERI(ADC14->rCTL1.r, ADC14REFBURST_OFS) = 1;
+
+    return true;
+}
+
+bool ADC14_disableReferenceBurst(void)
+{
+    if (ADCIsConversionRunning())
+        return false;
+
+    BITBAND_PERI(ADC14->rCTL1.r, ADC14REFBURST_OFS) = 0;
+
+    return true;
+}
+
+bool ADC14_setPowerMode(uint32_t adcPowerMode)
+{
+    if (ADCIsConversionRunning())
+        return false;
+
+    switch (adcPowerMode)
+    {
+    case ADC_UNRESTRICTED_POWER_MODE:
+        ADC14->rCTL1.r = (ADC14->rCTL1.r & ~(ADC14PWRMD_M))
+                | (ADC14PWRMD_0);
+        break;
+    case ADC_ULTRA_LOW_POWER_MODE:
+        ADC14->rCTL1.r = (ADC14->rCTL1.r & ~(ADC14PWRMD_M))
+                | (ADC14PWRMD_2);
+        break;
+    default:
+        ASSERT(false);
+        return false;
+    }
+
+    return true;
+}
+
+void ADC14_enableInterrupt(uint_fast64_t mask)
+{
+    uint32_t stat = mask & 0xFFFFFFFF;
+
+    ADC14->rIER0.r |= stat;
+    stat = (mask >> 32);
+    ADC14->rIER1.r |= (stat);
+}
+
+void ADC14_disableInterrupt(uint_fast64_t mask)
+{
+    uint32_t stat = mask & 0xFFFFFFFF;
+
+    ADC14->rIER0.r &= ~stat;
+    stat = (mask >> 32);
+    ADC14->rIER1.r &= ~(stat);
+}
+
+uint_fast64_t ADC14_getInterruptStatus(void)
+{
+    uint_fast64_t status = ADC14->rIFGR1.r;
+    return ((status << 32) | ADC14->rIFGR0.r);
+}
+
+uint_fast64_t ADC14_getEnabledInterruptStatus(void)
+{
+    uint_fast64_t stat = ADC14->rIER1.r;
+
+    return ADC14_getInterruptStatus() & ((stat << 32) | ADC14->rIER0.r);
+
+}
+
+void ADC14_clearInterruptFlag(uint_fast64_t mask)
+{
+    uint32_t stat = mask & 0xFFFFFFFF;
+
+    ADC14->rCLRIFGR0.r |= stat;
+    stat = (mask >> 32);
+    ADC14->rCLRIFGR1.r |= (stat);
+}
+
+void ADC14_registerInterrupt(void (*intHandler)(void))
+{
+    //
+    // Register the interrupt handler, returning an error if an error occurs.
+    //
+    Interrupt_registerInterrupt(INT_ADC14, intHandler);
+
+    //
+    // Enable the ADC interrupt.
+    //
+    Interrupt_enableInterrupt(INT_ADC14);
+}
+
+void ADC14_unregisterInterrupt(void)
+{
+    //
+    // Disable the interrupt.
+    //
+    Interrupt_disableInterrupt(INT_ADC14);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    Interrupt_unregisterInterrupt(INT_ADC14);
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/adc14.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/adc14.h
new file mode 100644
index 000000000..d17446e54
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/adc14.h
@@ -0,0 +1,1076 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef ADC14_H_
+#define ADC14_H_
+
+//*****************************************************************************
+//
+//!
+//! \addtogroup adc14_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <msp.h>
+#include <stdbool.h>
+
+//*****************************************************************************
+//
+// Control specific variables
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//The following are values that can be passed to ADC14_initModule
+//
+//*****************************************************************************
+#define ADC_CLOCKSOURCE_ADCOSC   (ADC14SSEL_0)
+#define ADC_CLOCKSOURCE_SYSOSC   (ADC14SSEL_1)
+#define ADC_CLOCKSOURCE_ACLK     (ADC14SSEL_2)
+#define ADC_CLOCKSOURCE_MCLK     (ADC14SSEL_3)
+#define ADC_CLOCKSOURCE_SMCLK    (ADC14SSEL_4)
+#define ADC_CLOCKSOURCE_HSMCLK   (ADC14SSEL_5)
+
+#define ADC_PREDIVIDER_1         (ADC14PDIV_0)
+#define ADC_PREDIVIDER_4         (ADC14PDIV_1)
+#define ADC_PREDIVIDER_32        (ADC14PDIV_2)
+#define ADC_PREDIVIDER_64        (ADC14PDIV_3)
+
+#define ADC_DIVIDER_1            (ADC14DIV_0)
+#define ADC_DIVIDER_2            (ADC14DIV_1)
+#define ADC_DIVIDER_3            (ADC14DIV_2)
+#define ADC_DIVIDER_4            (ADC14DIV_3)
+#define ADC_DIVIDER_5            (ADC14DIV_4)
+#define ADC_DIVIDER_6            (ADC14DIV_5)
+#define ADC_DIVIDER_7            (ADC14DIV_6)
+#define ADC_DIVIDER_8            (ADC14DIV_7)
+
+#define ADC_MAPINTCH3            (ADC14CH3MAP)
+#define ADC_MAPINTCH2            (ADC14CH2MAP)
+#define ADC_MAPINTCH1            (ADC14CH1MAP)
+#define ADC_MAPINTCH0            (ADC14CH0MAP)
+#define ADC_TEMPSENSEMAP         (ADC14TCMAP)
+#define ADC_BATTMAP              (ADC14BATMAP)
+#define ADC_NOROUTE               0
+
+#define ADC_8BIT                 ADC14RES_0
+#define ADC_10BIT                ADC14RES_1
+#define ADC_12BIT                ADC14RES_2
+#define ADC_14BIT                ADC14RES_3
+
+#define ADC_TRIGGER_ADCSC        ADC14SHS_0
+#define ADC_TRIGGER_SOURCE1      ADC14SHS_1
+#define ADC_TRIGGER_SOURCE2      ADC14SHS_2
+#define ADC_TRIGGER_SOURCE3      ADC14SHS_3
+#define ADC_TRIGGER_SOURCE4      ADC14SHS_4
+#define ADC_TRIGGER_SOURCE5      ADC14SHS_5
+#define ADC_TRIGGER_SOURCE6      ADC14SHS_6
+#define ADC_TRIGGER_SOURCE7      ADC14SHS_7
+
+#define ADC_PULSE_WIDTH_4        ADC14SHT1_0
+#define ADC_PULSE_WIDTH_8        ADC14SHT1_1
+#define ADC_PULSE_WIDTH_16       ADC14SHT1_2
+#define ADC_PULSE_WIDTH_32       ADC14SHT1_3
+#define ADC_PULSE_WIDTH_64       ADC14SHT1_4
+#define ADC_PULSE_WIDTH_96       ADC14SHT1_5
+#define ADC_PULSE_WIDTH_128      ADC14SHT1_6
+#define ADC_PULSE_WIDTH_192      ADC14SHT1_7
+
+#define ADC_NONDIFFERENTIAL_INPUTS false
+#define ADC_DIFFERENTIAL_INPUTS true
+
+#define ADC_MEM0                 0x00000001
+#define ADC_MEM1                 0x00000002
+#define ADC_MEM2                 0x00000004
+#define ADC_MEM3                 0x00000008
+#define ADC_MEM4                 0x00000010
+#define ADC_MEM5                 0x00000020
+#define ADC_MEM6                 0x00000040
+#define ADC_MEM7                 0x00000080
+#define ADC_MEM8                 0x00000100
+#define ADC_MEM9                 0x00000200
+#define ADC_MEM10                0x00000400
+#define ADC_MEM11                0x00000800
+#define ADC_MEM12                0x00001000
+#define ADC_MEM13                0x00002000
+#define ADC_MEM14                0x00004000
+#define ADC_MEM15                0x00008000
+#define ADC_MEM16                0x00010000
+#define ADC_MEM17                0x00020000
+#define ADC_MEM18                0x00040000
+#define ADC_MEM19                0x00080000
+#define ADC_MEM20                0x00100000
+#define ADC_MEM21                0x00200000
+#define ADC_MEM22                0x00400000
+#define ADC_MEM23                0x00800000
+#define ADC_MEM24                0x01000000
+#define ADC_MEM25                0x02000000
+#define ADC_MEM26                0x04000000
+#define ADC_MEM27                0x08000000
+#define ADC_MEM28                0x10000000
+#define ADC_MEM29                0x20000000
+#define ADC_MEM30                0x40000000
+#define ADC_MEM31                0x80000000
+
+#define ADC_VREFPOS_AVCC_VREFNEG_VSS       (ADC14VRSEL_0)
+#define ADC_VREFPOS_INTBUF_VREFNEG_VSS     (ADC14VRSEL_1)
+#define ADC_VREFPOS_EXTPOS_VREFNEG_EXTNEG  (ADC14VRSEL_14)
+#define ADC_VREFPOS_EXTBUF_VREFNEG_EXTNEG  (ADC14VRSEL_15)
+
+#define ADC_INPUT_A0              (ADC14INCH_0)
+#define ADC_INPUT_A1              (ADC14INCH_1)
+#define ADC_INPUT_A2              (ADC14INCH_2)
+#define ADC_INPUT_A3              (ADC14INCH_3)
+#define ADC_INPUT_A4              (ADC14INCH_4)
+#define ADC_INPUT_A5              (ADC14INCH_5)
+#define ADC_INPUT_A6              (ADC14INCH_6)
+#define ADC_INPUT_A7              (ADC14INCH_7)
+#define ADC_INPUT_A8              (ADC14INCH_8)
+#define ADC_INPUT_A9              (ADC14INCH_9)
+#define ADC_INPUT_A10             (ADC14INCH_10)
+#define ADC_INPUT_A11             (ADC14INCH_11)
+#define ADC_INPUT_A12             (ADC14INCH_12)
+#define ADC_INPUT_A13             (ADC14INCH_13)
+#define ADC_INPUT_A14             (ADC14INCH_14)
+#define ADC_INPUT_A15             (ADC14INCH_15)
+#define ADC_INPUT_A16             (ADC14INCH_16)
+#define ADC_INPUT_A17             (ADC14INCH_17)
+#define ADC_INPUT_A18             (ADC14INCH_18)
+#define ADC_INPUT_A19             (ADC14INCH_19)
+#define ADC_INPUT_A20             (ADC14INCH_20)
+#define ADC_INPUT_A21             (ADC14INCH_21)
+#define ADC_INPUT_A22             (ADC14INCH_22)
+#define ADC_INPUT_A23             (ADC14INCH_23)
+#define ADC_INPUT_A24             (ADC14INCH_24)
+#define ADC_INPUT_A25             (ADC14INCH_25)
+#define ADC_INPUT_A26             (ADC14INCH_26)
+#define ADC_INPUT_A27             (ADC14INCH_27)
+#define ADC_INPUT_A28             (ADC14INCH_28)
+#define ADC_INPUT_A29             (ADC14INCH_29)
+#define ADC_INPUT_A30             (ADC14INCH_30)
+#define ADC_INPUT_A31             (ADC14INCH_31)
+
+#define ADC_COMP_WINDOW0          0x00
+#define ADC_COMP_WINDOW1          0x01
+
+#define ADC_SIGNED_BINARY         0x00
+#define ADC_UNSIGNED_BINARY       0x01
+
+#define ADC_MANUAL_ITERATION       0x00
+#define ADC_AUTOMATIC_ITERATION    ADC14MSC
+
+#define ADC_UNRESTRICTED_POWER_MODE   ADC14PWRMD_0
+#define ADC_ULTRA_LOW_POWER_MODE      ADC14PWRMD_2
+
+
+#define ADC_INT0 ADC14IE0
+#define ADC_INT1 ADC14IE1
+#define ADC_INT2 ADC14IE2
+#define ADC_INT3 ADC14IE3
+#define ADC_INT4 ADC14IE4
+#define ADC_INT5 ADC14IE5
+#define ADC_INT6 ADC14IE6
+#define ADC_INT7 ADC14IE7
+#define ADC_INT8 ADC14IE8
+#define ADC_INT9 ADC14IE9
+#define ADC_INT10 ADC14IE10
+#define ADC_INT11 ADC14IE11
+#define ADC_INT12 ADC14IE12
+#define ADC_INT13 ADC14IE13
+#define ADC_INT14 ADC14IE14
+#define ADC_INT15 ADC14IE15
+#define ADC_INT16 ADC14IE16
+#define ADC_INT17 ADC14IE17
+#define ADC_INT18 ADC14IE18
+#define ADC_INT19 ADC14IE19
+#define ADC_INT20 ADC14IE20
+#define ADC_INT21 ADC14IE21
+#define ADC_INT22 ADC14IE22
+#define ADC_INT23 ADC14IE23
+#define ADC_INT24 ADC14IE24
+#define ADC_INT25 ADC14IE25
+#define ADC_INT26 ADC14IE26
+#define ADC_INT27 ADC14IE27
+#define ADC_INT28 ADC14IE28
+#define ADC_INT29 ADC14IE29
+#define ADC_INT30 ADC14IE30
+#define ADC_INT31 ADC14IE31
+#define ADC_IN_INT 0x0000000200000000
+#define ADC_LO_INT 0x0000000400000000
+#define ADC_HI_INT 0x0000000800000000
+#define ADC_OV_INT 0x0000001000000000
+#define ADC_TOV_INT 0x0000002000000000
+#define ADC_RDY_INT 0x0000004000000000
+
+#define ADC_INVALID_MEM   32
+
+//*****************************************************************************
+//
+//Prototypes for the APIs.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//!
+//! Enables the ADC block.
+//!
+//! This will enable operation of the ADC block.
+//!
+//! \return none.
+//
+//*****************************************************************************
+extern void ADC14_enableModule(void);
+
+//*****************************************************************************
+//
+//!
+//! Disables the ADC block.
+//!
+//! This will disable operation of the ADC block.
+//!
+//! \return false if user is trying to disable during active conversion
+//
+//*****************************************************************************
+extern bool ADC14_disableModule(void);
+
+//*****************************************************************************
+//
+//!
+//! Initializes the ADC module and sets up the clock system divider/pre-divider.
+//! This initialization function will also configure the internal/external
+//! signal mapping.
+//!
+//! \note A call to this function while active ADC conversion is happening
+//! is an invalid case and will result in a false value being returned.
+//!
+//! \param clockSource The clock source to use for the ADC module.
+//!                 - \b ADC_CLOCKSOURCE_ADCOSC [DEFAULT]
+//!                 - \b ADC_CLOCKSOURCE_SYSOSC
+//!                 - \b ADC_CLOCKSOURCE_ACLK
+//!                 - \b ADC_CLOCKSOURCE_MCLK
+//!                 - \b ADC_CLOCKSOURCE_SMCLK
+//!                 - \b ADC_CLOCKSOURCE_HSMCLK
+//!
+//! \param clockPredivider Divides the given clock source before feeding it
+//!         into the main clock divider.
+//!             Valid values are:
+//!                 - \b ADC_PREDIVIDER_1 [DEFAULT]
+//!                 - \b ADC_PREDIVIDER_4
+//!                 - \b ADC_PREDIVIDER_32
+//!                 - \b ADC_PREDIVIDER_64
+//!
+//! \param clockDivider Divides the pre-divided clock source
+//!         Valid values are
+//!             - \b ADC_DIVIDER_1 [Default value]
+//!             - \b ADC_DIVIDER_2
+//!             - \b ADC_DIVIDER_3
+//!             - \b ADC_DIVIDER_4
+//!             - \b ADC_DIVIDER_5
+//!             - \b ADC_DIVIDER_6
+//!             - \b ADC_DIVIDER_7
+//!             - \b ADC_DIVIDER_8
+//!
+//! \param internalChannelMask
+//!  Configures the internal/external pin mappings
+//!  for the ADC modules. This setting determines if the given ADC channel or
+//!  component is mapped to an external pin (default), or routed to an internal
+//!  component. This parameter is a bit mask where a logical high value will
+//!  switch the component to the internal routing. For a list of internal
+//!  routings, please refer to the device specific data sheet.
+//!  Valid values are a logical OR of the following values:
+//!         - \b ADC_MAPINTCH3
+//!         - \b ADC_MAPINTCH2
+//!         - \b ADC_MAPINTCH1
+//!         - \b ADC_MAPINTCH0
+//!         - \b ADC_TEMPSENSEMAP
+//!         - \b ADC_BATTMAP
+//!         - \n ADC_NOROUTE
+//! If internalChannelMask is not desired, pass ADC_NOROUTE in lieu of this
+//!  parameter.
+//!
+//! \return false if the initialization fails due to an in progress conversion
+//!
+//!
+//
+//*****************************************************************************
+extern bool ADC14_initModule(uint32_t clockSource, uint32_t clockPredivider,
+        uint32_t clockDivider, uint32_t internalChannelMask);
+
+//*****************************************************************************
+//
+//!
+//! Sets the resolution of the ADC module. The default resolution is 12-bit,
+//! however for power consumption concerns this can be limited to a lower
+//! resolution
+//!
+//! \param resolution Resolution of the ADC module
+//!         - \b ADC_8BIT (10 clock cycle conversion time)
+//!         - \b ADC_10BIT (12 clock cycle conversion time)
+//!         - \b ADC_12BIT (14 clock cycle conversion time)
+//!         - \b ADC_14BIT (16 clock cycle conversion time)[DEFAULT]
+//!
+//! \return none
+//
+//*****************************************************************************
+extern void ADC14_setResolution(uint32_t resolution);
+
+//*****************************************************************************
+//
+//!
+//! Gets the resolution of the ADC module.
+//!
+//! \return Resolution of the ADC module
+//!         - \b ADC_8BIT (10 clock cycle conversion time)
+//!         - \b ADC_10BIT (12 clock cycle conversion time)
+//!         - \b ADC_12BIT (14 clock cycle conversion time)
+//!         - \b ADC_14BIT (16 clock cycle conversion time)
+//
+//*****************************************************************************
+extern uint_fast32_t ADC14_getResolution(void);
+
+//*****************************************************************************
+//
+//!
+//! Sets the source for the trigger of the ADC module. By default, this value
+//! is configured to a software source (the ADCSC bit), however depending on
+//! the specific device the trigger can be set to different sources (for
+//! example, a timer output). These sources vary from part to part and the
+//! user should refer to the device specific datasheet.
+//!
+//! \param source Trigger source for sampling. Possible values include:
+//!         - \b ADC_TRIGGER_ADCSC [DEFAULT]
+//!         - \b ADC_TRIGGER_SOURCE1
+//!         - \b ADC_TRIGGER_SOURCE2
+//!         - \b ADC_TRIGGER_SOURCE3
+//!         - \b ADC_TRIGGER_SOURCE4
+//!         - \b ADC_TRIGGER_SOURCE5
+//!         - \b ADC_TRIGGER_SOURCE6
+//!         - \b ADC_TRIGGER_SOURCE7
+//! \param invertSignal When set to true, will invert the trigger signal to a
+//!         falling edge. When false, will use a rising edge.
+//!
+//! \return false if setting fails due to an in progress conversion
+//
+//*****************************************************************************
+extern bool ADC14_setSampleHoldTrigger(uint32_t source, bool invertSignal);
+
+//*****************************************************************************
+//
+//!
+//! Sets the sample/hold time for the specified memory register range. The
+//! duration of time required for a sample differs depending on the user's
+//! hardware configuration.
+//!
+//! There are two values in the ADCC module. The first value controls
+//! ADC memory locations ADC_MEMORY_0 through ADC_MEMORY_7 and
+//! ADC_MEMORY_24 through ADC_MEMORY_31, while the second value
+//! controls memory locations ADC_MEMORY_8 through ADC_MEMORY_23.
+//!
+//! \param firstPulseWidth Pulse width of the first pulse in ADCCLK cycles
+//!     Possible values must be one of the following:
+//!         - \b ADC_PULSE_WIDTH_4 [DEFAULT]
+//!         - \b ADC_PULSE_WIDTH_8
+//!         - \b ADC_PULSE_WIDTH_16
+//!         - \b ADC_PULSE_WIDTH_32
+//!         - \b ADC_PULSE_WIDTH_64
+//!         - \b ADC_PULSE_WIDTH_96
+//!         - \b ADC_PULSE_WIDTH_128
+//!         - \b ADC_PULSE_WIDTH_192
+//! \param secondPulseWidth Pulse width of the second pulse in ADCCLK
+//!     cycles. Possible values must be one of the following:
+//!         - \b ADC_PULSE_WIDTH_4 [DEFAULT]
+//!         - \b ADC_PULSE_WIDTH_8
+//!         - \b ADC_PULSE_WIDTH_16
+//!         - \b ADC_PULSE_WIDTH_32
+//!         - \b ADC_PULSE_WIDTH_64
+//!         - \b ADC_PULSE_WIDTH_96
+//!         - \b ADC_PULSE_WIDTH_128
+//!         - \b ADC_PULSE_WIDTH_192
+//!
+//! \return false if setting fails due to an in progress conversion
+//
+//*****************************************************************************
+extern bool ADC14_setSampleHoldTime(uint32_t firstPulseWidth,
+        uint32_t secondPulseWidth);
+
+//*****************************************************************************
+//
+//!
+//! Configures the ADC module to use a multiple memory sample scheme. This
+//! means that multiple samples will consecutively take place and be stored in
+//! multiple memory locations. The first sample/conversion will be placed in
+//! memoryStart, while the last sample will be stored in memoryEnd.
+//! Each memory location should be configured individually using the
+//! ADC14_configureConversionMemory function.
+//!
+//! The ADC module can be started in "repeat" mode which will cause the
+//! ADC module to resume sampling once the initial sample/conversion set is
+//! executed.  For multi-sample mode, this means that the sampling of the
+//! entire memory provided.
+//!
+//! \param memoryStart Memory location to store first sample/conversion
+//!         value. Possible values include:
+//!         - \b ADC_MEM0 through \b ADC_MEM31
+//! \param memoryEnd Memory location to store last sample.
+//!     Possible values include:
+//!         - \b ADC_MEM0 through \b ADC_MEM31
+//! \param repeatMode Specifies whether or not to repeat the conversion/sample
+//!         cycle after the first round of sample/conversions. Valid values
+//!         are true or false.
+//!
+//! \return false if setting fails due to an in progress conversion
+//
+//*****************************************************************************
+extern bool ADC14_configureMultiSequenceMode(uint32_t memoryStart,
+        uint32_t memoryEnd, bool repeatMode);
+
+//*****************************************************************************
+//
+//!
+//! Configures the ADC module to use a a single ADC memory location for
+//! sampling/conversion. This is used when only one channel might be needed for
+//! conversion, or where using a multiple sampling scheme is not important.
+//!
+//! The ADC module can be started in "repeat" mode which will cause the
+//! ADC module to resume sampling once the initial sample/conversion set is
+//! executed. In single sample mode, this will cause the ADC module to
+//! continuously sample into the memory destination provided.
+
+//! \param memoryDestination Memory location to store sample/conversion
+//!         value. Possible values include:
+//!         - \b ADC_MEM0 through \b ADC_MEM31
+//!
+//! \param repeatMode Specifies whether or not to repeat the conversion/sample
+//!         cycle after the first round of sample/conversions
+//!
+//! \return false if setting fails due to an in progress conversion
+//
+//*****************************************************************************
+extern bool ADC14_configureSingleSampleMode(uint32_t memoryDestination,
+        bool repeatMode);
+
+//*****************************************************************************
+//
+//!
+//! Enables conversion of ADC data. Note that this only enables conversion.
+//! To trigger the conversion, you will have to call the
+//! ADC14_toggleConversionTrigger or use the source trigger configured in
+//! ADC14_setSampleHoldTrigger.
+//!
+//! \return false if setting fails due to an in progress conversion
+//
+//*****************************************************************************
+extern bool ADC14_enableConversion(void);
+
+//*****************************************************************************
+//
+//!
+//! Halts conversion conversion of the ADC module. Note that the software bit
+//! for triggering conversions will also be cleared with this function.
+//!
+//! If multi-sequence conversion mode was enabled, the position of the last
+//! completed conversion can be retrieved using ADCLastConversionMemoryGet
+//!
+//! \return none
+//
+//*****************************************************************************
+extern void ADC14_disableConversion(void);
+
+//*****************************************************************************
+//
+//!
+//! Toggles the trigger for conversion of the ADC module by toggling the
+//! trigger software bit. Note that this will cause the ADC to start
+//! conversion regardless if the software bit was set as the trigger using
+//! ADC14_setSampleHoldTrigger.
+//!
+//! \return false if setting fails due to an in progress conversion
+//
+//*****************************************************************************
+extern bool ADC14_toggleConversionTrigger(void);
+
+//*****************************************************************************
+//
+//!
+//! Returns a boolean value that tells if a conversion/sample is in progress
+//!
+//! Originally a public function, but moved to static. External customers should
+//! use the ADC14_isBusy function.
+//!
+//! \return true if conversion is active, false otherwise
+//
+//*****************************************************************************
+extern bool ADC14_isBusy(void);
+
+//*****************************************************************************
+//
+//!
+//! Configures an individual memory location for the ADC module.
+//!
+//! \param memorySelect is the individual ADC memory location to
+//!     configure. If multiple memory locations want to be configured with the
+//!     same configuration, this value can be logically ORed together with other
+//!     values.
+//!         - \b ADC_MEM0 through \b ADC_MEM31
+//! \param refSelect is the voltage reference to use for the selected
+//!         memory spot. Possible values include:
+//!         - \b ADC_VREFPOS_AVCC_VREFNEG_VSS [DEFAULT]
+//!         - \b ADC_VREFPOS_INTBUF_VREFNEG_VSS
+//!         - \b ADC_VREFPOS_EXTPOS_VREFNEG_EXTNEG
+//!         - \b ADC_VREFPOS_EXTBUF_VREFNEG_EXTNEG
+//! \param channelSelect selects the channel to be used for ADC sampling.
+//!         Note if differential mode is enabled, the value sampled will be
+//!         equal to the difference between the corresponding even/odd memory
+//!         locations. Possible values are:
+//!         - \b ADC_INPUT_A0 through \b ADC_INPUT_A31
+//!
+//! \param differntialMode selects if the channel selected by the
+//!     channelSelect will be configured in differential mode. If this
+//!     parameter is given for false, the configured channel will be paired
+//!     with its neighbor in differential mode. for example, if channel A0 or A1
+//!     is selected, the channel configured will be the difference between A0
+//!     and A1. If A2 or A3 are selected, the channel configured will be the
+//!     difference between A2 and A3 (and so on). Users can enter true or false,
+//!     or one ofl the following values:
+//!         - ADC_NONDIFFERENTIAL_INPUTS
+//!         - ADC_DIFFERENTIAL_INPUTS
+//!
+//!
+//! \return false if setting fails due to an in progress conversion
+//!
+//
+//*****************************************************************************
+extern bool ADC14_configureConversionMemory(uint32_t memorySelect,
+        uint32_t refSelect, uint32_t channelSelect, bool differntialMode);
+
+//*****************************************************************************
+//
+//!
+//! Enables the specified mask of memory channels to use the specified
+//! comparator window. THe ADCC module has two different comparator windows
+//! that can be set with this function.
+//!
+//! \param memorySelect is the mask of memory locations to enable the
+//!         comparator window for. This can be a bitwise OR of the following
+//!         values:
+//!         - \b ADC_MEM0 through \b ADC_MEM31
+//! \param windowSelect Memory location to store sample/conversion
+//!         value. Possible values include:
+//!         \b ADCOMP_WINDOW0 [DEFAULT]
+//!         \b ADCOMP_WINDOW1
+//!
+//! \return false if setting fails due to an in progress conversion
+//
+//*****************************************************************************
+extern bool ADC14_enableComparatorWindow(uint32_t memorySelect,
+        uint32_t windowSelect);
+
+//*****************************************************************************
+//
+//!
+//! Disables the comparator window on the specified memory channels
+//!
+//! \param memorySelect is the mask of memory locations to disable the
+//!         comparator window for. This can be a bitwise OR of the following
+//!         values:
+//!         - \b ADC_MEM0 through \b ADC_MEM31
+//!
+//! \return false if setting fails due to an in progress conversion
+//
+//*****************************************************************************
+extern bool ADC14_disableComparatorWindow(uint32_t memorySelect);
+
+//*****************************************************************************
+//
+//!
+//! Sets the lower and upper limits of the specified window comparator. Note
+//! that this function will truncate values based of the resolution/data
+//! format configured. If the ADC is operating in 10-bit mode, and a 12-bit
+//! value is passed into this function the most significant 2 bits will be
+//! truncated.
+//!
+//! The parameters provided to this function for the upper and lower threshold
+//! depend on the current resolution for the ADC. For example, if configured
+//! in 12-bit mode, a 12-bit resolution is the maximum that can be provided
+//! for the window. If in 2's complement mode, Bit 15 is used as the MSB.
+//!
+//! \param window Memory location to store sample/conversion
+//!         value. Possible values include:
+//!         \b ADC_COMP_WINDOW0 [DEFAULT]
+//!         \b ADC_COMP_WINDOW1
+//! \param low is the lower limit of the window comparator
+//! \param high is the upper limit of the window comparator
+//!
+//! \return false if setting fails due to an in progress conversion
+//!
+//
+//*****************************************************************************
+extern bool ADC14_setComparatorWindowValue(uint32_t window, int16_t low,
+        int16_t high);
+
+//*****************************************************************************
+//
+//!
+//! Switches between a binary unsigned data format and a signed 2's complement
+//! data format.
+//!
+//! \param resultFormat Format for result to conversion results.
+//!         Possible values include:
+//!         \b ADC_UNSIGNED_BINARY [DEFAULT]
+//!         \b ADC_SIGNED_BINARY
+//!
+//! \return false if setting fails due to an in progress conversion
+//!
+//
+//*****************************************************************************
+extern bool ADC14_setResultFormat(uint32_t resultFormat);
+
+//*****************************************************************************
+//
+//!
+//! Returns the conversion result for the specified memory channel in the format
+//! assigned by the ADC14_setResultFormat (unsigned binary by default) function.
+//!
+//! \param memorySelect is the memory location to get the conversion result.
+//!     Valid values are:
+//!         - \b ADC_MEM0 through \b ADC_MEM31
+//! \return conversion result of specified memory channel
+//!
+//
+//*****************************************************************************
+extern uint_fast16_t ADC14_getResult(uint32_t memorySelect);
+
+//*****************************************************************************
+//
+//!
+//! Returns the conversion results of the currently configured multi-sequence
+//! conversion. If a multi-sequence conversion has not happened, this value
+//! is unreliable. Note that it is up to the user to verify the integrity of
+//! and proper size of the array being passed. If there are 16 multi-sequence
+//! results, and an array with only 4 elements allocated is passed, invalid
+//! memory settings will occur
+//!
+//! \param res conversion result of the last multi-sequence sample
+//! in an array of unsigned 16-bit integers
+//!
+//! \return None
+//!
+//
+//*****************************************************************************
+extern void ADC14_getMultiSequenceResult(uint16_t* res);
+
+//*****************************************************************************
+//
+//!
+//! Returns the conversion results of the specified ADC memory locations.
+//! Note that it is up to the user to verify the integrity of
+//! and proper size of the array being passed. If there are 16 multi-sequence
+//! results, and an array with only 4 elements allocated is passed, invalid
+//! memory settings will occur. This function is inclusive.
+//!
+//! \param memoryStart is the memory location to get the conversion result.
+//!     Valid values are:
+//!         - \b ADC_MEM0 through \b ADC_MEM31
+//!
+//! \param memoryEnd is the memory location to get the conversion result.
+//!     Valid values are:
+//!         - \b ADC_MEM0 through \b ADC_MEM31
+//! \param res conversion result of the last multi-sequence sample
+//! in an array of unsigned 16-bit integers
+//!
+//! \return None
+//!
+//
+//*****************************************************************************
+extern void ADC14_getResultArray(uint32_t memoryStart, uint32_t memoryEnd,
+        uint16_t* res);
+
+//*****************************************************************************
+//
+//!
+//! Enables the "on-demand" activity of the voltage reference register. If this
+//! setting is enabled, the internal voltage reference buffer will only be
+//! updated during a sample or conversion cycle. This is used to optimize
+//! power consumption.
+//!
+//! \return false if setting fails due to an in progress conversion
+//!
+//
+//*****************************************************************************
+extern bool ADC14_enableReferenceBurst(void);
+
+//*****************************************************************************
+//
+//!
+//! Disables the "on-demand" activity of the voltage reference register.
+//!
+//! \return false if setting fails due to an in progress conversion
+//!
+//
+//*****************************************************************************
+extern bool ADC14_disableReferenceBurst(void);
+
+//*****************************************************************************
+//
+//!
+//! Sets the power mode of the ADC module. A more aggressive power mode will
+//! restrict the number of samples per second for sampling while optimizing
+//! power consumption. Ideally, if power consumption is a concern, this value
+//! should be set to the most restrictive setting that satisfies your sampling
+//! requirement.
+//!
+//! \param adcPowerMode is the power mode to set. Valid values are:
+//!         - \b ADC_UNRESTRICTED_POWER_MODE (no restriction)
+//!         - \b ADC_LOW_POWER_MODE (500ksps restriction)
+//!         - \b ADC_ULTRA_LOW_POWER_MODE (200ksps restriction)
+//!         - \b ADC_EXTREME_LOW_POWER_MODE (50ksps restriction)
+//!
+//! \return false if setting fails due to an in progress conversion
+//!
+//
+//*****************************************************************************
+extern bool ADC14_setPowerMode(uint32_t powerMode);
+
+//*****************************************************************************
+//
+//!
+//! Enables SAMPCON to be sourced from the sampling timer and to configures
+//! multi sample and conversion mode.
+//! \param multiSampleConvert - Switches between manual and automatic
+//!         iteration when using the sample timer. Valid values are:
+//! - \b ADC_MANUAL_ITERATION The user will have to manually set the SHI signal
+//!         ( usually by  ADC14_toggleConversionTrigger ) at the end
+//!         of each sample/conversion cycle.
+//! - \b ADC_AUTOMATIC_ITERATION  After one sample/convert is finished, the ADC
+//!         module will automatically continue on to the next sample
+//!
+//! \return false if the initialization fails due to an in progress conversion
+//
+//*****************************************************************************
+extern bool ADC14_enableSampleTimer(uint32_t multiSampleConvert);
+
+//*****************************************************************************
+//
+//!
+//! Disables SAMPCON from being sourced from the sample timer.
+//!
+//! \return false if the initialization fails due to an in progress conversion
+//
+//*****************************************************************************
+extern bool ADC14_disableSampleTimer(void);
+
+//*****************************************************************************
+//
+//!
+//! Enables the indicated ADCC interrupt sources. The ADC_INT0
+//! through ADC_INT31 parameters correspond to a completion event of the
+//! corresponding memory location. For example, when the ADC_MEM0 location
+//! finishes a conversion cycle, the ADC_INT0 interrupt will be set.
+//!
+//! \param mask is the bit mask of interrupts to enable.
+//!        Valid values are a bitwise OR of the following values:
+//!        - \b ADC_INT0 through ADC_INT31
+//!        - \b ADC_IN_INT - Interrupt enable for a conversion in the result
+//!                          register is either greater than the ADCLO or
+//!                          lower than the ADCHI threshold.
+//!        - \b ADC_LO_INT - Interrupt enable for the falling short of the
+//!                          lower limit interrupt of the window comparator for
+//!                          the result register.
+//!        - \b ADC_HI_INT - Interrupt enable for the exceeding the upper
+//!                          limit of the window comparator for the result
+//!                          register.
+//!        - \b ADC_OV_INT - Interrupt enable for a conversion that is about
+//!                          to save to a memory buffer that has not been read
+//!                          out yet.
+//!        - \b ADC_TOV_INT -Interrupt enable for a conversion that is about
+//!                          to start before the previous conversion has been
+//!                          completed.
+//!        - \b ADC_RDY_INT -Interrupt enable for the local buffered reference
+//!                          ready signal.
+//!
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void ADC14_enableInterrupt(uint_fast64_t mask);
+
+//*****************************************************************************
+//
+//!
+//! Disables the indicated ADCC interrupt sources.  Only the sources that
+//! are enabled can be reflected to the processor interrupt; disabled sources
+//! have no effect on the processor. The ADC_INT0 through ADC_INT31
+//! parameters correspond to a completion event of the corresponding memory
+//! location. For example, when the ADC_MEM0 location finishes a conversion
+//! cycle, the ADC_INT0 interrupt will be set.
+//!
+//! \param mask is the bit mask of interrupts to disable.
+//!        Valid values are a bitwise OR of the following values:
+//!        - \b ADC_INT0 through ADC_INT31
+//!        - \b ADC_IN_INT - Interrupt enable for a conversion in the result
+//!                          register is either greater than the ADCLO or
+//!                          lower than the ADCHI threshold.
+//!        - \b ADC_LO_INT - Interrupt enable for the falling short of the
+//!                          lower limit interrupt of the window comparator for
+//!                          the result register.
+//!        - \b ADC_HI_INT - Interrupt enable for the exceeding the upper
+//!                          limit of the window comparator for the result
+//!                          register.
+//!        - \b ADC_OV_INT - Interrupt enable for a conversion that is about
+//!                          to save to a memory buffer that has not been read
+//!                          out yet.
+//!        - \b ADC_TOV_INT -Interrupt enable for a conversion that is about
+//!                          to start before the previous conversion has been
+//!                          completed.
+//!        - \b ADC_RDY_INT -Interrupt enable for the local buffered reference
+//!                          ready signal.
+//!
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void ADC14_disableInterrupt(uint_fast64_t mask);
+
+//*****************************************************************************
+//
+//!
+//! Returns the status of a the ADC interrupt register. The ADC_INT0
+//! through ADC_INT31 parameters correspond to a completion event of the
+//! corresponding memory location. For example, when the ADC_MEM0 location
+//! finishes a conversion cycle, the ADC_INT0 interrupt will be set.
+//!
+//! \return The interrupt status. Value is a bitwise OR of the following values:
+//!        - \b ADC_INT0 through ADC_INT31
+//!        - \b ADC_IN_INT - Interrupt enable for a conversion in the result
+//!                          register is either greater than the ADCLO or
+//!                          lower than the ADCHI threshold.
+//!        - \b ADC_LO_INT - Interrupt enable for the falling short of the
+//!                          lower limit interrupt of the window comparator for
+//!                          the result register.
+//!        - \b ADC_HI_INT - Interrupt enable for the exceeding the upper
+//!                          limit of the window comparator for the result
+//!                          register.
+//!        - \b ADC_OV_INT - Interrupt enable for a conversion that is about
+//!                          to save to a memory buffer that has not been read
+//!                          out yet.
+//!        - \b ADC_TOV_INT -Interrupt enable for a conversion that is about
+//!                          to start before the previous conversion has been
+//!                          completed.
+//!        - \b ADC_RDY_INT -Interrupt enable for the local buffered reference
+//!                          ready signal.
+//!
+//!
+//
+//*****************************************************************************
+extern uint_fast64_t ADC14_getInterruptStatus(void);
+
+//*****************************************************************************
+//
+//!
+//! Returns the status of a the ADC interrupt register masked with the
+//! enabled interrupts. This function is useful to call in ISRs to get a list
+//! of pending interrupts that are actually enabled and could have caused the
+//! ISR. The ADC_INT0 through ADC_INT31 parameters correspond to a
+//! completion event of the corresponding memory location. For example,
+//! when the ADC_MEM0 location finishes a conversion cycle, the ADC_INT0
+// !interrupt will be set.
+//!
+//! \return The interrupt status. Value is a bitwise OR of the following values:
+//!        - \b ADC_INT0 through ADC_INT31
+//!        - \b ADC_IN_INT - Interrupt enable for a conversion in the result
+//!                          register is either greater than the ADCLO or
+//!                          lower than the ADCHI threshold.
+//!        - \b ADC_LO_INT - Interrupt enable for the falling short of the
+//!                          lower limit interrupt of the window comparator for
+//!                          the result register.
+//!        - \b ADC_HI_INT - Interrupt enable for the exceeding the upper
+//!                          limit of the window comparator for the result
+//!                          register.
+//!        - \b ADC_OV_INT - Interrupt enable for a conversion that is about
+//!                          to save to a memory buffer that has not been read
+//!                          out yet.
+//!        - \b ADC_TOV_INT -Interrupt enable for a conversion that is about
+//!                          to start before the previous conversion has been
+//!                          completed.
+//!        - \b ADC_RDY_INT -Interrupt enable for the local buffered reference
+//!                          ready signal.
+//!
+//!
+//
+//*****************************************************************************
+extern uint_fast64_t ADC14_getEnabledInterruptStatus(void);
+
+//*****************************************************************************
+//
+//!
+//! Clears the indicated ADCC interrupt sources.
+//!
+//! \param mask is the bit mask of interrupts to clear. The ADC_INT0
+//! through ADC_INT31 parameters correspond to a completion event of the
+//! corresponding memory location. For example, when the ADC_MEM0 location
+//! finishes a conversion cycle, the ADC_INT0 interrupt will be set.
+//!        Valid values are a bitwise OR of the following values:
+//!        - \b ADC_INT0 through ADC_INT31
+//!        - \b ADC_IN_INT - Interrupt enable for a conversion in the result
+//!                          register is either greater than the ADCLO or
+//!                          lower than the ADCHI threshold.
+//!        - \b ADC_LO_INT - Interrupt enable for the falling short of the
+//!                          lower limit interrupt of the window comparator for
+//!                          the result register.
+//!        - \b ADC_HI_INT - Interrupt enable for the exceeding the upper
+//!                          limit of the window comparator for the result
+//!                          register.
+//!        - \b ADC_OV_INT - Interrupt enable for a conversion that is about
+//!                          to save to a memory buffer that has not been read
+//!                          out yet.
+//!        - \b ADC_TOV_INT -Interrupt enable for a conversion that is about
+//!                          to start before the previous conversion has been
+//!                          completed.
+//!        - \b ADC_RDY_INT -Interrupt enable for the local buffered reference
+//!                          ready signal.
+//!
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void ADC14_clearInterruptFlag(uint_fast64_t mask);
+
+//*****************************************************************************
+//
+//!
+//! Registers an interrupt handler for the ADC interrupt.
+//!
+//! \param intHandler is a pointer to the function to be called when the ADC
+//!  interrupt occurs.
+//!
+//! This function registers the handler to be called when an ADC
+//! interrupt occurs. This function enables the global interrupt in the
+//! interrupt controller; specific ADC14 interrupts must be enabled
+//! via ADC14_enableInterrupt().  It is the interrupt handler's responsibility
+//! to clear the interrupt source via ADC14_clearInterruptFlag().
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void ADC14_registerInterrupt(void (*intHandler)(void));
+
+//*****************************************************************************
+//
+//!
+//! Unregisters the interrupt handler for the ADCC module.
+//!
+//! This function unregisters the handler to be called when an ADCC
+//! interrupt occurs.  This function also masks off the interrupt in the
+//! interrupt controller so that the interrupt handler no longer is called.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void ADC14_unregisterInterrupt(void);
+
+/* Defines for future devices that might have multiple instances */
+#define ADC14_enableModuleMultipleInstance(a) ADC14_enableModule()
+#define ADC14_disableModuleMultipleInstance(a) ADC14_disableModule()
+#define ADC14_initModuleMultipleInstance(a,b,c,d,e) ADC14_initModule(b,c,d,e)
+#define ADC14_setResolutionMutlipleInstance(a,b) ADC14_setResolution(b)
+#define ADC14_getResolutionMutlipleInstance(a) ADC14_getResolution()
+#define ADC14_setSampleHoldTriggerMultipleInstance(a,b,c) ADC14_setSampleHoldTrigger(b,c)
+#define ADC14_setSampleHoldTimeMultipleInstance(a,b,c) ADC14_setSampleHoldTime(b,c)
+#define ADC14_configureMultiSequenceModeMultipleInstance(a,b,c,d) ADC14_configureMultiSequenceMode(b,c,d)
+#define ADC14_configureSingleSampleModeMultipleInstance(a,b,c) ADC14_configureSingleSampleMode(b,c)
+#define ADC14_enableConversionMultipleInstance(a,b) ADC14_enableConversion(b)
+#define ADC14_disableConversionMultipleInstance(a) ADC14_disableConversion()
+#define ADC14_toggleConversionTriggerMultipleInstance(a) ADC14_toggleConversionTrigger()
+#define ADC14_isBusyMultipleInstance(a) ADC14_isBusy()
+#define ADC14_configureConversionMemoryMultipleInstance(a,b,c,d,e) ADC14_enableModule(b,c,d,e)
+#define ADC14_enableComparatorWindowMultipleInstance(a,b,c) ADC14_enableComparatorWindow(b,c)
+#define ADC14_disableComparatorWindowMultipleInstance(a,b) ADC14_disableComparatorWindow(b)
+#define ADC14_setComparatorWindowValueMultipleInstance(a,b,c,d) ADC14_setComparatorWindowValue(b,c,d)
+#define ADC14_setResultFormatMultipleInstance(a,b) ADC14_setResultFormat(b)
+#define ADC14_getResultMultipleInstance(a,b) ADC14_getResult(b)
+#define ADC14_getMultiSequenceResultMultipleInstance(a,b) ADC14_getMultiSequenceResult(b)
+#define ADC14_getResultArrayMultipleInstance(a,b,c,d) ADC14_getResultArray(b,c,d)
+#define ADC14_enableReferenceBurstMultipleInstance(a) ADC14_enableReferenceBurst()
+#define ADC14_disableReferenceBurstMultipleInstance(a) ADC14_disableReferenceBurst()
+#define ADC14_setPowerModeMultipleInstance(a,b) ADC14_setPowerMode(b)
+#define ADC14_enableSampleTimerMultipleInstance(a,b) ADC14_enableSampleTimer(b)
+#define ADC14_disableSampleTimerMultipleInstance(a) ADC14_disableSampleTimer()
+#define ADC14_enableInterruptMultipleInstance(a,b) ADC14_enableInterrupt(b)
+#define ADC14_disableInterruptMultipleInstance(a,b) ADC14_disableInterrupt(b)
+#define ADC14_getInterruptStatusMultipleInstance(a) ADC14_getInterruptStatus()
+#define ADC14_getEnabledInterruptStatusMultipleInstance(a) ADC14_getEnabledInterruptStatus()
+#define ADC14_clearInterruptFlagMultipleInstance(a,b) ADC14_clearInterruptFlag(b)
+#define ADC14_registerInterruptMultipleInstance(a,b) ADC14_registerInterrupt(b)
+#define ADC14_unregisterInterruptMultipleInstance(a) ADC14_unregisterInterrupt()
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif /* ADC14_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/aes256.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/aes256.c
new file mode 100644
index 000000000..1abc241ea
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/aes256.c
@@ -0,0 +1,355 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#include <aes256.h>
+#include <interrupt.h>
+#include <debug.h>
+
+bool AES256_setCipherKey(uint32_t moduleInstance, const uint8_t * cipherKey,
+        uint_fast16_t keyLength)
+{
+    uint8_t i;
+    uint16_t sCipherKey;
+
+    AES256_CMSIS(moduleInstance)->rCTL0.r |= 0;
+
+    switch (keyLength)
+    {
+    case AES256_KEYLENGTH_128BIT:
+        AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__128BIT;
+        break;
+
+    case AES256_KEYLENGTH_192BIT:
+        AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__192BIT;
+        break;
+
+    case AES256_KEYLENGTH_256BIT:
+        AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__256BIT;
+        break;
+    default:
+        return false;
+    }
+
+    keyLength = keyLength / 8;
+
+    for (i = 0; i < keyLength; i = i + 2)
+    {
+        sCipherKey = (uint16_t) (cipherKey[i]);
+        sCipherKey = sCipherKey | ((uint16_t) (cipherKey[i + 1]) << 8);
+        AES256_CMSIS(moduleInstance)->rKEY.r = sCipherKey;
+    }
+
+    // Wait until key is written
+    while (!BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESKEYWR_OFS))
+        ;
+
+    return true;
+}
+
+void AES256_encryptData(uint32_t moduleInstance, const uint8_t * data,
+        uint8_t * encryptedData)
+{
+    uint8_t i;
+    uint16_t tempData = 0;
+    uint16_t tempVariable = 0;
+
+    // Set module to encrypt mode
+    AES256_CMSIS(moduleInstance)->rCTL0.r &= ~AESOP_M;
+
+    // Write data to encrypt to module
+    for (i = 0; i < 16; i = i + 2)
+    {
+        tempVariable = (uint16_t) (data[i]);
+        tempVariable = tempVariable | ((uint16_t) (data[i + 1]) << 8);
+        AES256_CMSIS(moduleInstance)->rDIN.r = tempVariable;
+    }
+
+    // Key that is already written shall be used
+    // Encryption is initialized by setting AESKEYWR to 1
+    BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESKEYWR_OFS) = 1;
+
+    // Wait unit finished ~167 MCLK
+    while (BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESBUSY_OFS))
+        ;
+
+    // Write encrypted data back to variable
+    for (i = 0; i < 16; i = i + 2)
+    {
+        tempData = AES256_CMSIS(moduleInstance)->rDOUT.r;
+        *(encryptedData + i) = (uint8_t) tempData;
+        *(encryptedData + i + 1) = (uint8_t) (tempData >> 8);
+    }
+}
+
+void AES256_decryptData(uint32_t moduleInstance, const uint8_t * data,
+        uint8_t * decryptedData)
+{
+    uint8_t i;
+    uint16_t tempData = 0;
+    uint16_t tempVariable = 0;
+
+    // Set module to decrypt mode
+    AES256_CMSIS(moduleInstance)->rCTL0.r |= (AESOP_3);
+
+    // Write data to decrypt to module
+    for (i = 0; i < 16; i = i + 2)
+    {
+        tempVariable = (uint16_t) (data[i + 1] << 8);
+        tempVariable = tempVariable | ((uint16_t) (data[i]));
+        AES256_CMSIS(moduleInstance)->rDIN.r = tempVariable;
+    }
+
+    // Key that is already written shall be used
+    // Now decryption starts
+    BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESKEYWR_OFS) = 1;
+
+    // Wait unit finished ~167 MCLK
+    while (BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESBUSY_OFS))
+        ;
+
+    // Write encrypted data back to variable
+    for (i = 0; i < 16; i = i + 2)
+    {
+        tempData = AES256_CMSIS(moduleInstance)->rDOUT.r;
+        *(decryptedData + i) = (uint8_t) tempData;
+        *(decryptedData + i + 1) = (uint8_t) (tempData >> 8);
+    }
+}
+
+bool AES256_setDecipherKey(uint32_t moduleInstance, const uint8_t * cipherKey,
+        uint_fast16_t keyLength)
+{
+    uint8_t i;
+    uint16_t tempVariable = 0;
+
+    // Set module to decrypt mode
+    AES256_CMSIS(moduleInstance)->rCTL0.r =
+            (AES256_CMSIS(moduleInstance)->rCTL0.r & ~AESOP_M) | AESOP1;
+
+    switch (keyLength)
+    {
+    case AES256_KEYLENGTH_128BIT:
+        AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__128BIT;
+        break;
+
+    case AES256_KEYLENGTH_192BIT:
+        AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__192BIT;
+        break;
+
+    case AES256_KEYLENGTH_256BIT:
+        AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__256BIT;
+        break;
+
+    default:
+        return false;
+    }
+
+    keyLength = keyLength / 8;
+
+    // Write cipher key to key register
+    for (i = 0; i < keyLength; i = i + 2)
+    {
+        tempVariable = (uint16_t) (cipherKey[i]);
+        tempVariable = tempVariable | ((uint16_t) (cipherKey[i + 1]) << 8);
+        AES256_CMSIS(moduleInstance)->rKEY.r = tempVariable;
+    }
+
+    // Wait until key is processed ~52 MCLK
+    while (BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESBUSY_OFS))
+        ;
+
+    return true;
+}
+
+void AES256_clearInterruptFlag(uint32_t moduleInstance)
+{
+    BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r,AESRDYIFG_OFS) = 0;
+}
+
+uint32_t AES256_getInterruptFlagStatus(uint32_t moduleInstance)
+{
+    return BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r, AESRDYIFG_OFS);
+}
+
+void AES256_enableInterrupt(uint32_t moduleInstance)
+{
+    BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r,AESRDYIE_OFS) = 1;
+}
+
+void AES256_disableInterrupt(uint32_t moduleInstance)
+{
+    BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r,AESRDYIE_OFS) = 0;
+}
+
+void AES256_reset(uint32_t moduleInstance)
+{
+    BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r,AESSWRST_OFS) = 1;
+}
+
+void AES256_startEncryptData(uint32_t moduleInstance, const uint8_t * data)
+{
+    uint8_t i;
+    uint16_t tempVariable = 0;
+
+    // Set module to encrypt mode
+    AES256_CMSIS(moduleInstance)->rCTL0.r &= ~AESOP_M;
+
+    // Write data to encrypt to module
+    for (i = 0; i < 16; i = i + 2)
+    {
+        tempVariable = (uint16_t) (data[i]);
+        tempVariable = tempVariable | ((uint16_t) (data[i + 1]) << 8);
+        AES256_CMSIS(moduleInstance)->rDIN.r = tempVariable;
+    }
+
+    // Key that is already written shall be used
+    // Encryption is initialized by setting AESKEYWR to 1
+    BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESKEYWR_OFS) = 1;
+}
+
+void AES256_startDecryptData(uint32_t moduleInstance, const uint8_t * data)
+{
+    uint8_t i;
+    uint16_t tempVariable = 0;
+
+    // Set module to decrypt mode
+    AES256_CMSIS(moduleInstance)->rCTL0.r |= (AESOP_3);
+
+    // Write data to decrypt to module
+    for (i = 0; i < 16; i = i + 2)
+    {
+        tempVariable = (uint16_t) (data[i + 1] << 8);
+        tempVariable = tempVariable | ((uint16_t) (data[i]));
+        AES256_CMSIS(moduleInstance)->rDIN.r = tempVariable;
+    }
+
+    // Key that is already written shall be used
+    // Now decryption starts
+    BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESKEYWR_OFS) = 1;
+}
+
+bool AES256_startSetDecipherKey(uint32_t moduleInstance,
+        const uint8_t * cipherKey, uint_fast16_t keyLength)
+{
+    uint8_t i;
+    uint16_t tempVariable = 0;
+
+    AES256_CMSIS(moduleInstance)->rCTL0.r =
+            (AES256_CMSIS(moduleInstance)->rCTL0.r & ~AESOP_M) | AESOP1;
+
+    switch (keyLength)
+    {
+    case AES256_KEYLENGTH_128BIT:
+        AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__128BIT;
+        break;
+
+    case AES256_KEYLENGTH_192BIT:
+        AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__192BIT;
+        break;
+
+    case AES256_KEYLENGTH_256BIT:
+        AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__256BIT;
+        break;
+
+    default:
+        return false;
+    }
+
+    keyLength = keyLength / 8;
+
+    // Write cipher key to key register
+    for (i = 0; i < keyLength; i = i + 2)
+    {
+        tempVariable = (uint16_t) (cipherKey[i]);
+        tempVariable = tempVariable | ((uint16_t) (cipherKey[i + 1]) << 8);
+        AES256_CMSIS(moduleInstance)->rKEY.r = tempVariable;
+    }
+
+    return true;
+}
+
+bool AES256_getDataOut(uint32_t moduleInstance, uint8_t *outputData)
+{
+    uint8_t i;
+    uint16_t tempData = 0;
+
+    // If module is busy, exit and return failure
+    if (BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESBUSY_OFS))
+        return false;
+
+    // Write encrypted data back to variable
+    for (i = 0; i < 16; i = i + 2)
+    {
+        tempData = AES256_CMSIS(moduleInstance)->rDOUT.r;
+        *(outputData + i) = (uint8_t) tempData;
+        *(outputData + i + 1) = (uint8_t) (tempData >> 8);
+    }
+
+    return true;
+}
+
+bool AES256_isBusy(uint32_t moduleInstance)
+{
+    return BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESBUSY_OFS);
+}
+
+void AES256_clearErrorFlag(uint32_t moduleInstance)
+{
+    BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r, AESERRFG_OFS) = 0;
+}
+
+uint32_t AES256_getErrorFlagStatus(uint32_t moduleInstance)
+{
+    return BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r, AESERRFG_OFS);
+}
+
+void AES256_registerInterrupt(uint32_t moduleInstance, void (*intHandler)(void))
+{
+    Interrupt_registerInterrupt(INT_AES256, intHandler);
+    Interrupt_enableInterrupt(INT_AES256);
+}
+
+void AES256_unregisterInterrupt(uint32_t moduleInstance)
+{
+    Interrupt_disableInterrupt(INT_AES256);
+    Interrupt_unregisterInterrupt(INT_AES256);
+}
+
+uint32_t AES256_getInterruptStatus(uint32_t moduleInstance)
+{
+    return AES256_getInterruptFlagStatus(moduleInstance);
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/aes256.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/aes256.h
new file mode 100644
index 000000000..1bdca8a9f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/aes256.h
@@ -0,0 +1,451 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef AES256_H_
+#define AES256_H_
+
+//*****************************************************************************
+//
+//! \addtogroup aes256_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <msp.h>
+
+/* Module Defines and macro for easy access */
+#define AES256_CMSIS(x) ((AES256_Type *) x)
+
+//*****************************************************************************
+//
+// The following are deprecated values. Please refer to documentation for the
+// correct values to use.
+//
+//*****************************************************************************
+#define Key_128BIT                                                          128
+#define Key_192BIT                                                          192
+#define Key_256BIT                                                          256
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the keyLength parameter for
+// functions: AES256_setCipherKey(), AES256_setDecipherKey(), and
+// AES256_startSetDecipherKey().
+//
+//*****************************************************************************
+#define AES256_KEYLENGTH_128BIT                                             128
+#define AES256_KEYLENGTH_192BIT                                             192
+#define AES256_KEYLENGTH_256BIT                                             256
+
+//*****************************************************************************
+//
+// The following are values that can be passed toThe following are values that
+// can be returned by the AES256_getErrorFlagStatus() function.
+//
+//*****************************************************************************
+#define AES256_ERROR_OCCURRED                                          AESERRFG
+#define AES256_NO_ERROR                                                    0x00
+
+//*****************************************************************************
+//
+// The following are values that can be passed toThe following are values that
+// can be returned by the AES256_isBusy() function.
+//
+//*****************************************************************************
+#define AES256_BUSY                                                     AESBUSY
+#define AES256_NOT_BUSY                                                    0x00
+
+//*****************************************************************************
+//
+// The following are values that can be passed toThe following are values that
+// can be returned by the AES256_getInterruptFlagStatus() function.
+//
+//*****************************************************************************
+#define AES256_READY_INTERRUPT                                             0x01
+#define AES256_NOTREADY_INTERRUPT                                          0x00
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \brief Loads a 128, 192 or 256 bit cipher key to AES256 module.
+//!
+//! \param moduleInstance is the base address of the AES256 module.
+//! \param cipherKey is a pointer to an uint8_t array with a length of 16 bytes
+//!        that contains a 128 bit cipher key.
+//! \param keyLength is the length of the key.
+//!        Valid values are:
+//!        - \b AES256_KEYLENGTH_128BIT
+//!        - \b AES256_KEYLENGTH_192BIT
+//!        - \b AES256_KEYLENGTH_256BIT
+//!
+//! \return true if set correctly, false otherwise
+//
+//*****************************************************************************
+extern bool AES256_setCipherKey(uint32_t moduleInstance,
+        const uint8_t *cipherKey, uint_fast16_t keyLength);
+
+//*****************************************************************************
+//
+//! \brief Encrypts a block of data using the AES256 module.
+//!
+//! The cipher key that is used for encryption should be loaded in advance by
+//! using function AES256_setCipherKey()
+//!
+//! \param moduleInstance is the base address of the AES256 module.
+//! \param data is a pointer to an uint8_t array with a length of 16 bytes that
+//!        contains data to be encrypted.
+//! \param encryptedData is a pointer to an uint8_t array with a length of 16
+//!        bytes in that the encrypted data will be written.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void AES256_encryptData(uint32_t moduleInstance, const uint8_t *data,
+        uint8_t *encryptedData);
+
+//*****************************************************************************
+//
+//! \brief Decrypts a block of data using the AES256 module.
+//!
+//! This function requires a pregenerated decryption key. A key can be loaded
+//! and pregenerated by using function AES256_setDecipherKey() or
+//! AES256_startSetDecipherKey(). The decryption takes 167 MCLK.
+//!
+//! \param moduleInstance is the base address of the AES256 module.
+//! \param data is a pointer to an uint8_t array with a length of 16 bytes that
+//!        contains encrypted data to be decrypted.
+//! \param decryptedData is a pointer to an uint8_t array with a length of 16
+//!        bytes in that the decrypted data will be written.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void AES256_decryptData(uint32_t moduleInstance, const uint8_t *data,
+        uint8_t *decryptedData);
+
+//*****************************************************************************
+//
+//! \brief Sets the decipher key.
+//!
+//! The API AES256_startSetDecipherKey or AES256_setDecipherKey must be invoked
+//! before invoking AES256_startDecryptData.
+//!
+//! \param moduleInstance is the base address of the AES256 module.
+//! \param cipherKey is a pointer to an uint8_t array with a length of 16 bytes
+//!        that contains a 128 bit cipher key.
+//! \param keyLength is the length of the key.
+//!        Valid values are:
+//!        - \b AES256_KEYLENGTH_128BIT
+//!        - \b AES256_KEYLENGTH_192BIT
+//!        - \b AES256_KEYLENGTH_256BIT
+//!
+//! \return true if set, false otherwise
+//
+//*****************************************************************************
+extern bool AES256_setDecipherKey(uint32_t moduleInstance,
+        const uint8_t *cipherKey, uint_fast16_t keyLength);
+
+//*****************************************************************************
+//
+//! \brief Clears the AES256 ready interrupt flag.
+//!
+//! \param moduleInstance is the base address of the AES256 module.
+//!
+//! Modified bits are \b AESRDYIFG of \b AESACTL0 register.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void AES256_clearInterruptFlag(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! \brief Gets the AES256 ready interrupt flag status.
+//!
+//! \param moduleInstance is the base address of the AES256 module.
+//!
+//! \return One of the following:
+//!         - \b AES256_READY_INTERRUPT
+//!         - \b AES256_NOTREADY_INTERRUPT
+//!         \n indicating the status of the AES256 ready status
+//
+//*****************************************************************************
+extern uint32_t AES256_getInterruptFlagStatus(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! \brief Enables AES256 ready interrupt.
+//!
+//! \param moduleInstance is the base address of the AES256 module.
+//!
+//! Modified bits are \b AESRDYIE of \b AESACTL0 register.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void AES256_enableInterrupt(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! \brief Disables AES256 ready interrupt.
+//!
+//! \param moduleInstance is the base address of the AES256 module.
+//!
+//! Modified bits are \b AESRDYIE of \b AESACTL0 register.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void AES256_disableInterrupt(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! \brief Resets AES256 Module immediately.
+//!
+//! \param moduleInstance is the base address of the AES256 module.
+//!
+//! Modified bits are \b AESSWRST of \b AESACTL0 register.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void AES256_reset(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! \brief Starts an encryption process on the AES256 module.
+//!
+//! The cipher key that is used for decryption should be loaded in advance by
+//! using function AES256_setCipherKey(). This is a non-blocking equivalent pf
+//! AES256_encryptData(). It is recommended to use the interrupt functionality
+//! to check for procedure completion then use the AES256_getDataOut() API to
+//! retrieve the encrypted data.
+//!
+//! \param moduleInstance is the base address of the AES256 module.
+//! \param data is a pointer to an uint8_t array with a length of 16 bytes that
+//!        contains data to be encrypted.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void AES256_startEncryptData(uint32_t moduleInstance,
+        const uint8_t *data);
+
+//*****************************************************************************
+//
+//! \brief Decypts a block of data using the AES256 module.
+//!
+//! This is the non-blocking equivalant of AES256_decryptData(). This function
+//! requires a pregenerated decryption key. A key can be loaded and
+//! pregenerated by using function AES256_setDecipherKey() or
+//! AES256_startSetDecipherKey(). The decryption takes 167 MCLK. It is
+//! recommended to use interrupt to check for procedure completion then use the
+//! AES256_getDataOut() API to retrieve the decrypted data.
+//!
+//! \param moduleInstance is the base address of the AES256 module.
+//! \param data is a pointer to an uint8_t array with a length of 16 bytes that
+//!        contains encrypted data to be decrypted.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void AES256_startDecryptData(uint32_t moduleInstance,
+        const uint8_t *data);
+
+//*****************************************************************************
+//
+//! \brief Sets the decipher key
+//!
+//! The API AES256_startSetDecipherKey() or AES256_setDecipherKey() must be
+//! invoked before invoking AES256_startDecryptData.
+//!
+//! \param moduleInstance is the base address of the AES256 module.
+//! \param cipherKey is a pointer to an uint8_t array with a length of 16 bytes
+//!        that contains a 128 bit cipher key.
+//! \param keyLength is the length of the key.
+//!        Valid values are:
+//!        - \b AES256_KEYLENGTH_128BIT
+//!        - \b AES256_KEYLENGTH_192BIT
+//!        - \b AES256_KEYLENGTH_256BIT
+//!
+//! \return true if set correctly, false otherwise
+//
+//*****************************************************************************
+extern bool AES256_startSetDecipherKey(uint32_t moduleInstance,
+        const uint8_t *cipherKey, uint_fast16_t keyLength);
+
+//*****************************************************************************
+//
+//! \brief Reads back the output data from AES256 module.
+//!
+//! This function is meant to use after an encryption or decryption process
+//! that was started and finished by initiating an interrupt by use of
+//! AES256_startEncryptData or AES256_startDecryptData functions.
+//!
+//! \param moduleInstance is the base address of the AES256 module.
+//! \param outputData is a pointer to an uint8_t array with a length of 16
+//!        bytes in that the data will be written.
+//!
+//! \return true if data is valid, otherwise false
+//
+//*****************************************************************************
+extern bool AES256_getDataOut(uint32_t moduleInstance,
+        uint8_t *outputData);
+
+//*****************************************************************************
+//
+//! \brief Gets the AES256 module busy status.
+//!
+//! \param moduleInstance is the base address of the AES256 module.
+//!
+//! \return true if busy, false otherwise
+//
+//*****************************************************************************
+extern bool AES256_isBusy(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! \brief Clears the AES256 error flag.
+//!
+//! \param moduleInstance is the base address of the AES256 module.
+//!
+//! Modified bits are \b AESERRFG of \b AESACTL0 register.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void AES256_clearErrorFlag(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! \brief Gets the AES256 error flag status.
+//!
+//! \param moduleInstance is the base address of the AES256 module.
+//!
+//! \return One of the following:
+//!         - \b AES256_ERROR_OCCURRED
+//!         - \b AES256_NO_ERROR
+//!         \n indicating the error flag status
+//
+//*****************************************************************************
+extern uint32_t AES256_getErrorFlagStatus(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the AES interrupt.
+//!
+//! \param moduleInstance Instance of the AES256 module
+//!
+//! \param intHandler is a pointer to the function to be called when the
+//! AES interrupt occurs.
+//!
+//! This function registers the handler to be called when a AES
+//! interrupt occurs. This function enables the global interrupt in the
+//! interrupt controller; specific AES interrupts must be enabled
+//! via AES256_enableInterrupt().  It is the interrupt handler's responsibility
+//! to clear the interrupt source via AES256_clearInterrupt().
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void AES256_registerInterrupt(uint32_t moduleInstance,
+        void (*intHandler)(void));
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the AES interrupt
+//!
+//! \param moduleInstance Instance of the AES256 module
+//!
+//! This function unregisters the handler to be called when AES
+//! interrupt occurs.  This function also masks off the interrupt in the
+//! interrupt controller so that the interrupt handler no longer is called.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void AES256_unregisterInterrupt(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Returns the current interrupt flag for the peripheral.
+//!
+//! \param moduleInstance Instance of the AES256 module
+//!
+//! \return The currently triggered interrupt flag for the module.
+//
+//*****************************************************************************
+extern uint32_t AES256_getInterruptStatus(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif /* AES256_H_ */
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/comp_e.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/comp_e.c
new file mode 100644
index 000000000..2ab133ce5
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/comp_e.c
@@ -0,0 +1,316 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#include <comp_e.h>
+#include <interrupt.h>
+#include <debug.h>
+
+static uint16_t __getRegisterSettingForInput(uint32_t input)
+{
+    switch (input)
+    {
+    case COMP_E_INPUT0:
+        return CEIPSEL_0;
+    case COMP_E_INPUT1:
+        return CEIPSEL_1;
+    case COMP_E_INPUT2:
+        return CEIPSEL_2;
+    case COMP_E_INPUT3:
+        return CEIPSEL_3;
+    case COMP_E_INPUT4:
+        return CEIPSEL_4;
+    case COMP_E_INPUT5:
+        return CEIPSEL_5;
+    case COMP_E_INPUT6:
+        return CEIPSEL_6;
+    case COMP_E_INPUT7:
+        return CEIPSEL_7;
+    case COMP_E_INPUT8:
+        return CEIPSEL_8;
+    case COMP_E_INPUT9:
+        return CEIPSEL_9;
+    case COMP_E_INPUT10:
+        return CEIPSEL_10;
+    case COMP_E_INPUT11:
+        return CEIPSEL_11;
+    case COMP_E_INPUT12:
+        return CEIPSEL_12;
+    case COMP_E_INPUT13:
+        return CEIPSEL_13;
+    case COMP_E_INPUT14:
+        return CEIPSEL_14;
+    case COMP_E_INPUT15:
+        return CEIPSEL_15;
+    case COMP_E_VREF:
+        return COMP_E_VREF;
+    default:
+        ASSERT(false);
+        return 0x11;
+    }
+
+}
+
+bool COMP_E_initModule(uint32_t comparator, const COMP_E_Config *config)
+{
+    uint_fast8_t positiveTerminalInput = __getRegisterSettingForInput(
+            config->positiveTerminalInput);
+    uint_fast8_t negativeTerminalInput = __getRegisterSettingForInput(
+            config->negativeTerminalInput);
+    bool retVal = true;
+
+    ASSERT(positiveTerminalInput < 0x10); ASSERT(negativeTerminalInput < 0x10);
+    ASSERT(positiveTerminalInput != negativeTerminalInput);
+    ASSERT(
+            config->outputFilterEnableAndDelayLevel
+            <= COMP_E_FILTEROUTPUT_DLYLVL4);
+
+    /* Reset COMPE Control 1 & Interrupt Registers for initialization */
+    COMP_E_CMSIS(comparator)->rCTL0.r = 0;
+    COMP_E_CMSIS(comparator)->rINT.r = 0;
+
+    // Set the Positive Terminal
+    if (COMP_E_VREF != positiveTerminalInput)
+    {
+        // Enable Positive Terminal Input Mux and Set to the appropriate input
+        COMP_E_CMSIS(comparator)->rCTL0.r |= CEIPEN + positiveTerminalInput;
+
+        // Disable the input buffer
+        COMP_E_CMSIS(comparator)->rCTL3.r |= (1 << positiveTerminalInput);
+    } else
+    {
+        //  Reset and Set COMPE Control 2 Register
+        BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL2.r,CERSEL_OFS) = 0;
+    }
+
+    // Set the Negative Terminal
+    if (COMP_E_VREF != negativeTerminalInput)
+    {
+        // Enable Negative Terminal Input Mux and Set  to the appropriate input
+        COMP_E_CMSIS(comparator)->rCTL0.r |= CEIMEN
+                + (negativeTerminalInput << 8);
+
+        // Disable the input buffer
+        COMP_E_CMSIS(comparator)->rCTL3.r |= (1 << negativeTerminalInput);
+    } else
+    {
+        // Reset and Set COMPE Control 2 Register
+        BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL2.r, CERSEL_OFS) = 1;
+    }
+
+    // Reset and Set COMPE Control 1 Register
+    COMP_E_CMSIS(comparator)->rCTL1.r = config->powerMode
+            + config->outputFilterEnableAndDelayLevel
+            + config->invertedOutputPolarity;
+
+    return retVal;
+}
+
+void COMP_E_setReferenceVoltage(uint32_t comparator,
+        uint_fast16_t supplyVoltageReferenceBase,
+        uint_fast16_t lowerLimitSupplyVoltageFractionOf32,
+        uint_fast16_t upperLimitSupplyVoltageFractionOf32)
+{
+    ASSERT(supplyVoltageReferenceBase <= COMP_E_VREFBASE2_5V);
+    ASSERT(upperLimitSupplyVoltageFractionOf32 <= 32);
+    ASSERT(lowerLimitSupplyVoltageFractionOf32 <= 32); ASSERT(
+            upperLimitSupplyVoltageFractionOf32
+            >= lowerLimitSupplyVoltageFractionOf32);
+
+    BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CEMRVS_OFS) = 0;
+    COMP_E_CMSIS(comparator)->rCTL2.r &= CERSEL;
+
+    // Set Voltage Source(Vcc | Vref, resistor ladder or not)
+    if (COMP_E_REFERENCE_AMPLIFIER_DISABLED == supplyVoltageReferenceBase)
+    {
+        COMP_E_CMSIS(comparator)->rCTL2.r |= CERS_1;
+    } else if (lowerLimitSupplyVoltageFractionOf32 == 32)
+    {
+        COMP_E_CMSIS(comparator)->rCTL2.r |= CERS_3;
+    } else
+    {
+        COMP_E_CMSIS(comparator)->rCTL2.r |= CERS_2;
+    }
+
+    // Set COMPE Control 2 Register
+    COMP_E_CMSIS(comparator)->rCTL2.r |= supplyVoltageReferenceBase
+            + ((upperLimitSupplyVoltageFractionOf32 - 1) << 8)
+            + (lowerLimitSupplyVoltageFractionOf32 - 1);
+}
+
+void COMP_E_setReferenceAccuracy(uint32_t comparator,
+        uint_fast16_t referenceAccuracy)
+{
+    ASSERT(
+            (referenceAccuracy == COMP_E_ACCURACY_STATIC)
+            || (referenceAccuracy == COMP_E_ACCURACY_CLOCKED));
+
+    if (referenceAccuracy)
+        BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL2.r, CEREFACC_OFS) = 1;
+    else
+        BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL2.r, CEREFACC_OFS) = 0;
+
+}
+
+void COMP_E_setPowerMode(uint32_t comparator, uint_fast16_t powerMode)
+{
+    COMP_E_CMSIS(comparator)->rCTL1.r = (COMP_E_CMSIS(comparator)->rCTL1.r
+            & ~(CEPWRMD_M)) | powerMode;
+}
+
+void COMP_E_enableModule(uint32_t comparator)
+{
+    BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CEON_OFS) = 1;
+}
+
+void COMP_E_disableModule(uint32_t comparator)
+{
+    BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CEON_OFS) = 0;
+}
+
+void COMP_E_shortInputs(uint32_t comparator)
+{
+    BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CESHORT_OFS) = 1;
+}
+
+void COMP_E_unshortInputs(uint32_t comparator)
+{
+    BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CESHORT_OFS) = 0;
+}
+
+void COMP_E_disableInputBuffer(uint32_t comparator, uint_fast16_t inputPort)
+{
+    ASSERT(inputPort <= COMP_E_INPUT15);
+
+    COMP_E_CMSIS(comparator)->rCTL3.r |= (inputPort);
+}
+
+void COMP_E_enableInputBuffer(uint32_t comparator, uint_fast16_t inputPort)
+{
+    ASSERT(inputPort <= COMP_E_INPUT15);
+
+    COMP_E_CMSIS(comparator)->rCTL3.r &= ~(inputPort);
+}
+
+void COMP_E_swapIO(uint32_t comparator)
+{
+    COMP_E_CMSIS(comparator)->rCTL1.r ^= CEEX; // Toggle CEEX bit
+}
+
+uint8_t COMP_E_outputValue(uint32_t comparator)
+{
+    return COMP_E_CMSIS(comparator)->rCTL1.r & CEOUT;
+}
+
+void COMP_E_enableInterrupt(uint32_t comparator, uint_fast16_t mask)
+{
+    // Set the Interrupt enable bit
+    COMP_E_CMSIS(comparator)->rINT.r |= mask;
+}
+
+uint_fast16_t COMP_E_getEnabledInterruptStatus(uint32_t comparator)
+{
+    return COMP_E_getInterruptStatus(comparator) &
+    COMP_E_CMSIS(comparator)->rINT.r;
+}
+
+void COMP_E_disableInterrupt(uint32_t comparator, uint_fast16_t mask)
+{
+    COMP_E_CMSIS(comparator)->rINT.r &= ~(mask);
+}
+
+void COMP_E_clearInterruptFlag(uint32_t comparator, uint_fast16_t mask)
+{
+    COMP_E_CMSIS(comparator)->rINT.r &= ~(mask);
+}
+
+uint_fast16_t COMP_E_getInterruptStatus(uint32_t comparator)
+{
+    return (COMP_E_CMSIS(comparator)->rINT.r & (COMP_E_OUTPUT_INTERRUPT_FLAG |
+    COMP_E_INTERRUPT_FLAG_INVERTED_POLARITY |
+    COMP_E_INTERRUPT_FLAG_READY));
+}
+
+void COMP_E_setInterruptEdgeDirection(uint32_t comparator,
+        uint_fast8_t edgeDirection)
+{
+    ASSERT(edgeDirection <= COMP_E_RISINGEDGE);
+
+    // Set the edge direction that will trigger an interrupt
+    if (COMP_E_RISINGEDGE == edgeDirection)
+        BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CEIES_OFS) = 1;
+    else if (COMP_E_FALLINGEDGE == edgeDirection)
+        BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CEIES_OFS) = 0;
+}
+
+void COMP_E_toggleInterruptEdgeDirection(uint32_t comparator)
+{
+    COMP_E_CMSIS(comparator)->rCTL1.r ^= CEIES;
+}
+
+void COMP_E_registerInterrupt(uint32_t comparator, void (*intHandler)(void))
+{
+    switch (comparator)
+    {
+    case COMP_E0_MODULE:
+        Interrupt_registerInterrupt(INT_COMP_E0, intHandler);
+        Interrupt_enableInterrupt(INT_COMP_E0);
+        break;
+    case COMP_E1_MODULE:
+        Interrupt_registerInterrupt(INT_COMP_E1, intHandler);
+        Interrupt_enableInterrupt(INT_COMP_E1);
+        break;
+    default:
+        ASSERT(false);
+    }
+}
+
+void COMP_E_unregisterInterrupt(uint32_t comparator)
+{
+    switch (comparator)
+    {
+    case COMP_E0_MODULE:
+        Interrupt_disableInterrupt(INT_COMP_E0);
+        Interrupt_unregisterInterrupt(INT_COMP_E0);
+        break;
+    case COMP_E1_MODULE:
+        Interrupt_disableInterrupt(INT_COMP_E1);
+        Interrupt_unregisterInterrupt(INT_COMP_E1);
+        break;
+    default:
+        ASSERT(false);
+    }
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/comp_e.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/comp_e.h
new file mode 100644
index 000000000..d250d6253
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/comp_e.h
@@ -0,0 +1,733 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef COMP_E_H_
+#define COMP_E_H_
+
+//*****************************************************************************
+//
+//! \addtogroup comp_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <msp.h>
+
+/* Module defines for Comp */
+#define COMP_E_CMSIS(x) ((COMP_E0_Type *) x)
+
+#define COMP_E_FILTEROUTPUT_OFF                                            0x00
+#define COMP_E_FILTEROUTPUT_DLYLVL1                            (CEF + CEFDLY_0)
+#define COMP_E_FILTEROUTPUT_DLYLVL2                            (CEF + CEFDLY_1)
+#define COMP_E_FILTEROUTPUT_DLYLVL3                            (CEF + CEFDLY_2)
+#define COMP_E_FILTEROUTPUT_DLYLVL4                            (CEF + CEFDLY_3)
+
+#define COMP_E_INPUT0                                                    (0x01)
+#define COMP_E_INPUT1                                                    (0x02)
+#define COMP_E_INPUT2                                                    (0x04)
+#define COMP_E_INPUT3                                                    (0x08)
+#define COMP_E_INPUT4                                                    (0x10)
+#define COMP_E_INPUT5                                                    (0x20)
+#define COMP_E_INPUT6                                                    (0x40)
+#define COMP_E_INPUT7                                                    (0x80)
+#define COMP_E_INPUT8                                                   (0x100)
+#define COMP_E_INPUT9                                                   (0x200)
+#define COMP_E_INPUT10                                                  (0x400)
+#define COMP_E_INPUT11                                                  (0x800)
+#define COMP_E_INPUT12                                                 (0x1000)
+#define COMP_E_INPUT13                                                 (0x2000)
+#define COMP_E_INPUT14                                                 (0x4000)
+#define COMP_E_INPUT15                                                 (0x8000)
+#define COMP_E_VREF                                                      (0x9F)
+
+#define COMP_E_NORMALOUTPUTPOLARITY                               (!(CEOUTPOL))
+#define COMP_E_INVERTEDOUTPUTPOLARITY                                (CEOUTPOL)
+
+#define COMP_E_REFERENCE_AMPLIFIER_DISABLED                          (CEREFL_0)
+#define COMP_E_VREFBASE1_2V                                          (CEREFL_1)
+#define COMP_E_VREFBASE2_0V                                          (CEREFL_2)
+#define COMP_E_VREFBASE2_5V                                          (CEREFL_3)
+
+#define COMP_E_ACCURACY_STATIC                                      (!CEREFACC)
+#define COMP_E_ACCURACY_CLOCKED                                      (CEREFACC)
+
+#define COMP_E_HIGH_SPEED_MODE                                      (CEPWRMD_0)
+#define COMP_E_NORMAL_MODE                                          (CEPWRMD_1)
+#define COMP_E_ULTRA_LOW_POWER_MODE                                 (CEPWRMD_2)
+
+#define COMP_E_OUTPUT_INTERRUPT                                          (CEIE)
+#define COMP_E_INVERTED_POLARITY_INTERRUPT                              (CEIIE)
+#define COMP_E_READY_INTERRUPT                                        (CERDYIE)
+
+#define COMP_E_OUTPUT_INTERRUPT_FLAG                                    (CEIFG)
+#define COMP_E_INTERRUPT_FLAG_INVERTED_POLARITY                        (CEIIFG)
+#define COMP_E_INTERRUPT_FLAG_READY                                  (CERDYIFG)
+
+#define COMP_E_FALLINGEDGE                                           (!(CEIES))
+#define COMP_E_RISINGEDGE                                               (CEIES)
+
+#define COMP_E_LOW                                                        (0x0)
+#define COMP_E_HIGH                                                     (CEOUT)
+
+//*****************************************************************************
+//
+//! \typedef COMP_E_Config
+//! \brief Type definition for \link _COMP_E_Config \endlink structure
+//!
+//! \struct _COMP_E_Config
+//! \brief Configuration structure for Comparator module. See 
+//!        \link COMP_E_initModule \endlink for parameter documentation.
+//
+//*****************************************************************************
+typedef struct _COMP_E_Config
+{
+    uint_fast16_t positiveTerminalInput;
+    uint_fast16_t negativeTerminalInput;
+    uint_fast8_t outputFilterEnableAndDelayLevel;
+    uint_fast8_t invertedOutputPolarity;
+    uint_fast16_t powerMode;
+} COMP_E_Config;
+
+//*****************************************************************************
+//
+//! Initializes the Comparator Module.
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0
+//!         - \b COMP_E1
+//! \param config Configuration structure for the Comparator module
+//!
+//! <hr>
+//! <b>Configuration options for \link COMP_E_Config \endlink structure.</b>
+//! <hr>
+//!
+//! \param positiveTerminalInput selects the input to the positive terminal.
+//!        Valid values are
+//!        - \b COMP_E_INPUT0 [Default]
+//!        - \b COMP_E_INPUT1
+//!        - \b COMP_E_INPUT2
+//!        - \b COMP_E_INPUT3
+//!        - \b COMP_E_INPUT4
+//!        - \b COMP_E_INPUT5
+//!        - \b COMP_E_INPUT6
+//!        - \b COMP_E_INPUT7
+//!        - \b COMP_E_INPUT8
+//!        - \b COMP_E_INPUT9
+//!        - \b COMP_E_INPUT10
+//!        - \b COMP_E_INPUT11
+//!        - \b COMP_E_INPUT12
+//!        - \b COMP_E_INPUT13
+//!        - \b COMP_E_INPUT14
+//!        - \b COMP_E_INPUT15
+//!        - \b COMP_E_VREF
+//!        \n Modified bits are \b CEIPSEL and \b CEIPEN of \b CECTL0 register,
+//!        \b CERSEL of \b CECTL2 register, and CEPDx of \b CECTL3 register.
+//! \param negativeTerminalInput selects the input to the negative terminal.
+//!        \n Valid values are:
+//!        - \b COMP_E_INPUT0 [Default]
+//!        - \b COMP_E_INPUT1
+//!        - \b COMP_E_INPUT2
+//!        - \b COMP_E_INPUT3
+//!        - \b COMP_E_INPUT4
+//!        - \b COMP_E_INPUT5
+//!        - \b COMP_E_INPUT6
+//!        - \b COMP_E_INPUT7
+//!        - \b COMP_E_INPUT8
+//!        - \b COMP_E_INPUT9
+//!        - \b COMP_E_INPUT10
+//!        - \b COMP_E_INPUT11
+//!        - \b COMP_E_INPUT12
+//!        - \b COMP_E_INPUT13
+//!        - \b COMP_E_INPUT14
+//!        - \b COMP_E_INPUT15
+//!        - \b COMP_E_VREF
+//!        \n Modified bits are \b CEIMSEL and \b CEIMEN of \b CECTL0 register,
+//!        \b CERSEL of \b CECTL2 register, and CEPDx of \b CECTL3 register.
+//! \param outputFilterEnableAndDelayLevel controls the output filter delay
+//!       state, which is either off or enabled with a specified delay level.
+//!        \n Valid values are
+//!        - \b COMP_E_FILTEROUTPUT_OFF [Default]
+//!        - \b COMP_E_FILTEROUTPUT_DLYLVL1
+//!        - \b COMP_E_FILTEROUTPUT_DLYLVL2
+//!        - \b COMP_E_FILTEROUTPUT_DLYLVL3
+//!        - \b COMP_E_FILTEROUTPUT_DLYLVL4
+//!        \n This parameter is device specific and delay levels should be found
+//!        in the device's datasheet.
+//!        \n Modified bits are \b CEF and \b CEFDLY of \b CECTL1 register.
+//! \param invertedOutputPolarity controls if the output will be inverted or
+//!        not. Valid values are
+//!        - \b COMP_E_NORMALOUTPUTPOLARITY - indicates the output should be
+//!             normal. [Default]
+//!        - \b COMP_E_INVERTEDOUTPUTPOLARITY -  the output should be inverted.
+//!        \n Modified bits are \b CEOUTPOL of \b CECTL1 register.
+//! \param powerMode controls the power mode of the module
+//!        - \b COMP_E_HIGH_SPEED_MODE [default]
+//!        - \b COMP_E_NORMAL_MODE
+//!        - \b COMP_E_ULTRA_LOW_POWER_MODE
+//! Upon successful initialization of the Comparator module, this function will
+//! have reset all necessary register bits and set the given options in the
+//! registers. To actually use the comparator module, the COMP_E_enableModule()
+//! function must be explicitly called before use.
+//! If a Reference Voltage is set to a terminal, the Voltage should be set
+//! using the COMP_E_setReferenceVoltage() function.
+//!
+//! \return true or false of the initialization process.
+//
+//*****************************************************************************
+extern bool COMP_E_initModule(uint32_t comparator, const COMP_E_Config *config);
+
+//*****************************************************************************
+//
+//! Generates a Reference Voltage to the terminal selected during
+//! initialization.
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0
+//!         - \b COMP_E1
+//! \param supplyVoltageReferenceBase decides the source and max amount of
+//!       Voltage that can be used as a reference.
+//!        Valid values are
+//!        - \b COMP_E_REFERENCE_AMPLIFIER_DISABLED
+//!        - \b COMP_E_VREFBASE1_2V
+//!        - \b COMP_E_VREFBASE2_0V
+//!        - \b COMP_E_VREFBASE2_5V
+//! \param upperLimitSupplyVoltageFractionOf32 is the numerator of the
+//!       equation to generate the reference voltage for the upper limit
+//!       reference voltage. Valid values are between 0 and 32.
+//! \param lowerLimitSupplyVoltageFractionOf32 is the numerator of the
+//!       equation to generate the reference voltage for the lower limit
+//!       reference voltage. Valid values are between 0 and 32.
+//!  <br>Modified bits are \b CEREF0 of \b CECTL2 register.
+//!
+//! Use this function to generate a voltage to serve as a reference to the
+//! terminal selected at initialization. The voltage is determined by the
+//! equation: Vbase * (Numerator / 32). If the upper and lower limit voltage
+//! numerators are equal, then a static reference is defined, whereas they are
+//! different then a hysteresis effect is generated.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void COMP_E_setReferenceVoltage(uint32_t comparator,
+        uint_fast16_t supplyVoltageReferenceBase,
+        uint_fast16_t lowerLimitSupplyVoltageFractionOf32,
+        uint_fast16_t upperLimitSupplyVoltageFractionOf32);
+
+//*****************************************************************************
+//
+//! Sets the reference accuracy
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0
+//!         - \b COMP_E1
+//! \param referenceAccuracy is the reference accuracy setting of the
+//!      comparator. Clocked is for low power/low accuracy.
+//!      Valid values are
+//!      - \b COMP_E_ACCURACY_STATIC
+//!      - \b COMP_E_ACCURACY_CLOCKED
+//!      <br>Modified bits are \b CEREFACC of \b CECTL2 register.
+//!
+//! The reference accuracy is set to the desired setting. Clocked is better for
+//!  low power operations but has a lower accuracy.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void COMP_E_setReferenceAccuracy(uint32_t comparator,
+        uint_fast16_t referenceAccuracy);
+
+//*****************************************************************************
+//
+//! Sets the power mode
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0
+//!         - \b COMP_E1
+//! \param powerMode decides the power mode
+//!        Valid values are
+//!        - \b COMP_E_HIGH_SPEED_MODE
+//!        - \b COMP_E_NORMAL_MODE
+//!        - \b COMP_E_ULTRA_LOW_POWER_MODE
+//!        <br>Modified bits are \b CEPWRMD of \b CECTL1 register.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void COMP_E_setPowerMode(uint32_t comparator, uint_fast16_t powerMode);
+
+//*****************************************************************************
+//
+//! Turns on the Comparator module.
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0
+//!         - \b COMP_E1
+//!
+//! This function sets the bit that enables the operation of the
+//! Comparator module.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void COMP_E_enableModule(uint32_t comparator);
+
+//*****************************************************************************
+//
+//! Turns off the Comparator module.
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0
+//!         - \b COMP_E1
+//!
+//! This function clears the CEON bit disabling the operation of the Comparator
+//! module, saving from excess power consumption.
+//!
+//! Modified bits are \b CEON of \b CECTL1 register.
+//! \return NONE
+//
+//*****************************************************************************
+extern void COMP_E_disableModule(uint32_t comparator);
+
+//*****************************************************************************
+//
+//! Shorts the two input pins chosen during initialization.
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0
+//!         - \b COMP_E1
+//!
+//! This function sets the bit that shorts the devices attached to the input
+//! pins chosen from the initialization of the comparator.
+//!
+//! Modified bits are \b CESHORT of \b CECTL1 register.
+//! \return NONE
+//
+//*****************************************************************************
+extern void COMP_E_shortInputs(uint32_t comparator);
+
+//*****************************************************************************
+//
+//! Disables the short of the two input pins chosen during initialization.
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0
+//!         - \b COMP_E1
+//!
+//! This function clears the bit that shorts the devices attached to the input
+//! pins chosen from the initialization of the comparator.
+//!
+//! Modified bits are \b CESHORT of \b CECTL1 register.
+//! \return NONE
+//
+//*****************************************************************************
+extern void COMP_E_unshortInputs(uint32_t comparator);
+
+//*****************************************************************************
+//
+//! Disables the input buffer of the selected input port to effectively allow
+//! for analog signals.
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         -  \b COMP_E0
+//!         - \b COMP_E1
+//! \param inputPort is the port in which the input buffer will be disabled.
+//!        Valid values are a logical OR of the following:
+//!        - \b COMP_E_INPUT0 [Default]
+//!        - \b COMP_E_INPUT1
+//!        - \b COMP_E_INPUT2
+//!        - \b COMP_E_INPUT3
+//!        - \b COMP_E_INPUT4
+//!        - \b COMP_E_INPUT5
+//!        - \b COMP_E_INPUT6
+//!        - \b COMP_E_INPUT7
+//!        - \b COMP_E_INPUT8
+//!        - \b COMP_E_INPUT9
+//!        - \b COMP_E_INPUT10
+//!        - \b COMP_E_INPUT11
+//!        - \b COMP_E_INPUT12
+//!        - \b COMP_E_INPUT13
+//!        - \b COMP_E_INPUT14
+//!        - \b COMP_E_INPUT15
+//!       <br> Modified bits are \b CEPDx of \b CECTL3 register.
+//!
+//! This function sets the bit to disable the buffer for the specified input
+//! port to allow for analog signals from any of the comparator input pins. This
+//! bit is automatically set when the input is initialized to be used with the
+//! comparator module. This function should be used whenever an analog input is
+//! connected to one of these pins to prevent parasitic voltage from causing
+//! unexpected results.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void COMP_E_disableInputBuffer(uint32_t comparator,
+        uint_fast16_t inputPort);
+
+//*****************************************************************************
+//
+//! Enables the input buffer of the selected input port to allow for digital
+//! signals.
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0
+//!         - \b COMP_E1
+//! \param inputPort is the port in which the input buffer will be enabled.
+//!        Valid values are a logical OR of the following:
+//!        - \b COMP_E_INPUT0 [Default]
+//!        - \b COMP_E_INPUT1
+//!        - \b COMP_E_INPUT2
+//!        - \b COMP_E_INPUT3
+//!        - \b COMP_E_INPUT4
+//!        - \b COMP_E_INPUT5
+//!        - \b COMP_E_INPUT6
+//!        - \b COMP_E_INPUT7
+//!        - \b COMP_E_INPUT8
+//!        - \b COMP_E_INPUT9
+//!        - \b COMP_E_INPUT10
+//!        - \b COMP_E_INPUT11
+//!        - \b COMP_E_INPUT12
+//!        - \b COMP_E_INPUT13
+//!        - \b COMP_E_INPUT14
+//!        - \b COMP_E_INPUT15
+//!      <br> Modified bits are \b CEPDx of \b CECTL3 register.
+//!
+//! This function clears the bit to enable the buffer for the specified input
+//! port to allow for digital signals from any of the comparator input pins.
+//! This should not be reset if there is an analog signal connected to the
+//! specified input pin to prevent from unexpected results.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void COMP_E_enableInputBuffer(uint32_t comparator,
+        uint_fast16_t inputPort);
+
+//*****************************************************************************
+//
+//! Toggles the bit that swaps which terminals the inputs go to, while also
+//! inverting the output of the comparator.
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \ bCOMP_E0
+//!         - \ bCOMP_E1
+//!
+//! This function toggles the bit that controls which input goes to which
+//! terminal. After initialization, this bit is set to 0, after toggling it once
+//! the inputs are routed to the opposite terminal and the output is inverted.
+//!
+//! Modified bits are \b CEEX of \b CECTL1 register.
+//! \return NONE
+//
+//*****************************************************************************
+extern void COMP_E_swapIO(uint32_t comparator);
+
+//*****************************************************************************
+//
+//! Returns the output value of the Comparator module.
+//!
+//! \param comparator is the instance of the Comparator module. Valid parameters
+//! vary from part to part, but can include:
+//!         - \b COMP_E0
+//!         - \b COMP_E1
+//!
+//! Returns the output value of the Comparator module.
+//!
+//! \return COMP_E_HIGH or COMP_E_LOW as the output value of the Comparator
+//!          module.
+//
+//*****************************************************************************
+extern uint8_t COMP_E_outputValue(uint32_t comparator);
+
+//*****************************************************************************
+//
+//! Enables selected Comparator interrupt sources.
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0
+//!         - \b COMP_E1
+//! \param mask is the bit mask of the interrupt sources to be enabled.
+//!        Mask value is the logical OR of any of the following
+//!        - \b COMP_E_OUTPUT_INTERRUPT - Output interrupt
+//!        - \b COMP_E_INVERTED_POLARITY_INTERRUPT - Output interrupt inverted
+//!                                                 polarity
+//!        - \b COMP_E_READY_INTERRUPT - Ready interrupt
+//!
+//! Enables the indicated Comparator interrupt sources.  Only the sources that
+//! are enabled can be reflected to the processor interrupt; disabled sources
+//! have no effect on the processor. The default trigger for the non-inverted
+//! interrupt is a rising edge of the output, this can be changed with the
+//! interruptSetEdgeDirection() function.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void COMP_E_enableInterrupt(uint32_t comparator, uint_fast16_t mask);
+
+//*****************************************************************************
+//
+//! Disables selected Comparator interrupt sources.
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0
+//!         - \b COMP_E1
+//! \param mask is the bit mask of the interrupt sources to be disabled.
+//!        Mask value is the logical OR of any of the following
+//!        - \b COMP_E_OUTPUT_INTERRUPT - Output interrupt
+//!        - \b COMP_E_INVERTED_POLARITY_INTERRUPT - Output interrupt inverted
+//!                                                 polarity
+//!        - \b COMP_E_READY_INTERRUPT - Ready interrupt
+//!
+//! Disables the indicated Comparator interrupt sources.  Only the sources that
+//! are enabled can be reflected to the processor interrupt; disabled sources
+//! have no effect on the processor.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void COMP_E_disableInterrupt(uint32_t comparator, uint_fast16_t mask);
+
+//*****************************************************************************
+//
+//! Clears Comparator interrupt flags.
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0
+//!         - \b COMP_E1
+//! \param mask is a bit mask of the interrupt sources to be cleared.
+//!        Mask value is the logical OR of any of the following
+//!        - \b COMP_E_INTERRUPT_FLAG - Output interrupt flag
+//!        - \b COMP_E_INTERRUPT_FLAG_INVERTED_POLARITY - Output interrupt flag
+//!                                                     inverted polarity
+//!        - \b COMP_E_INTERRUPT_FLAG_READY - Ready interrupt flag
+//!
+//! The Comparator interrupt source is cleared, so that it no longer asserts.
+//! The highest interrupt flag is automatically cleared when an interrupt vector
+//! generator is used.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void COMP_E_clearInterruptFlag(uint32_t comparator, uint_fast16_t mask);
+
+//*****************************************************************************
+//
+//! Gets the current Comparator interrupt status.
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0
+//!         - \b COMP_E1
+//!
+//! This returns the interrupt status for the Comparator module based on which
+//! flag is passed.
+//!
+//! \return The current interrupt flag status for the corresponding mask.
+//
+//*****************************************************************************
+extern uint_fast16_t COMP_E_getInterruptStatus(uint32_t comparator);
+
+//*****************************************************************************
+//
+//! Enables selected Comparator interrupt sources masked with the enabled
+//! interrupts. This function is useful to call in ISRs to get a list
+//! of pending interrupts that are actually enabled and could have caused the
+//! ISR.
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0
+//!         - \b COMP_E1
+//!
+//! Enables the indicated Comparator interrupt sources.  Only the sources that
+//! are enabled can be reflected to the processor interrupt; disabled sources
+//! have no effect on the processor. The default trigger for the non-inverted
+//! interrupt is a rising edge of the output, this can be changed with the
+//! COMP_E_setInterruptEdgeDirection() function.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern uint_fast16_t COMP_E_getEnabledInterruptStatus(uint32_t comparator);
+
+//*****************************************************************************
+//
+//! Explicitly sets the edge direction that would trigger an interrupt.
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0
+//!         - \b COMP_E1
+//! \param edgeDirection determines which direction the edge would have to go
+//!       to generate an interrupt based on the non-inverted interrupt flag.
+//!        Valid values are
+//!        - \b COMP_E_FALLINGEDGE - sets the bit to generate an interrupt when
+//!             the output of the comparator falls from HIGH to LOW if the
+//!             normal interrupt bit is set(and LOW to HIGH if the inverted
+//!             interrupt enable bit is set). [Default]
+//!        - \b COMP_E_RISINGEDGE - sets the bit to generate an interrupt when the
+//!             output of the comparator rises from LOW to HIGH if the normal
+//!             interrupt bit is set(and HIGH to LOW if the inverted interrupt
+//!             enable bit is set).
+//!        <br>Modified bits are \b CEIES of \b CECTL1 register.
+//!
+//! This function will set which direction the output will have to go, whether
+//! rising or falling, to generate an interrupt based on a non-inverted
+//! interrupt.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void COMP_E_setInterruptEdgeDirection(uint32_t comparator,
+        uint_fast8_t edgeDirection);
+
+//*****************************************************************************
+//
+//! Toggles the edge direction that would trigger an interrupt.
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0
+//!         - \b COMP_E1
+//!
+//! This function will toggle which direction the output will have to go,
+//! whether rising or falling, to generate an interrupt based on a non-inverted
+//! interrupt. If the direction was rising, it is now falling, if it was
+//! falling, it is now rising.
+//!
+//! Modified bits are \b CEIES of \b CECTL1 register.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void COMP_E_toggleInterruptEdgeDirection(uint32_t comparator);
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the Comparator E interrupt.
+//!
+//! \param intHandler is a pointer to the function to be called when the
+//! Comparator interrupt occurs.
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0
+//!         - \b COMP_E1
+//!
+//! This function registers the handler to be called when a Comparator
+//! interrupt occurs. This function enables the global interrupt in the
+//! interrupt controller; specific Comparator interrupts must be enabled
+//! via COMP_E_enableInterrupt().  It is the interrupt handler's responsibility to
+//! clear the interrupt source via COMP_E_clearInterruptFlag().
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void COMP_E_registerInterrupt(uint32_t comparator,
+        void (*intHandler)(void));
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the Comparator E interrupt
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0
+//!         - \b COMP_E1
+//!
+//! This function unregisters the handler to be called when Comparator E
+//! interrupt occurs.  This function also masks off the interrupt in the
+//! interrupt controller so that the interrupt handler no longer is called.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void COMP_E_unregisterInterrupt(uint32_t comparator);
+
+/* Backwards Compatibility Layer */
+#define COMP_E_enable(a) COMP_E_enableModule(a)
+#define COMP_E_disable(a) COMP_E_disableModule(a)
+#define COMP_E_IOSwap(a) COMP_E_swapIO(a)
+#define COMP_E_interruptToggleEdgeDirection(a) COMP_E_toggleInterruptEdgeDirection(a)
+#define COMP_E_clearInterrupt(a,b) COMP_E_clearInterruptFlag(a,b)
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+
+#endif /* COMP_E_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cpu.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cpu.c
new file mode 100644
index 000000000..1e70e5195
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cpu.c
@@ -0,0 +1,430 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#include <cpu.h>
+#include <msp.h>
+#include <stdint.h>
+
+//*****************************************************************************
+//
+// Wrapper function for the CPSID instruction.  Returns the state of PRIMASK
+// on entry.
+//
+//*****************************************************************************
+#if defined(gcc)
+uint32_t __attribute__((naked)) CPU_cpsid(void)
+{
+    uint32_t ret;
+
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+            "    cpsid   i\n"
+            "    bx      lr\n"
+            : "=r" (ret));
+
+    //
+    // The return is handled in the inline assembly, but the compiler will
+    // still complain if there is not an explicit return here (despite the fact
+    // that this does not result in any code being produced because of the
+    // naked attribute).
+    //
+    return(ret);
+}
+#endif
+#if defined(ewarm)
+uint32_t CPU_cpsid(void)
+{
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+            "    cpsid   i\n");
+
+    //
+    // "Warning[Pe940]: missing return statement at end of non-void function"
+    // is suppressed here to avoid putting a "bx lr" in the inline assembly
+    // above and a superfluous return statement here.
+    //
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#endif
+#if defined(keil)
+__asm uint32_t CPU_cpsid(void)
+{
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    mrs r0, PRIMASK;
+    cpsid i;
+    bx lr
+}
+#endif
+#if defined(ccs)
+uint32_t CPU_cpsid(void)
+{
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+            "    cpsid   i\n"
+            "    bx      lr\n");
+
+    //
+    // The following keeps the compiler happy, because it wants to see a
+    // return value from this function.  It will generate code to return
+    // a zero.  However, the real return is the "bx lr" above, so the
+    // return(0) is never executed and the function returns with the value
+    // you expect in R0.
+    //
+    return(0);
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function returning the state of PRIMASK (indicating whether
+// interrupts are enabled or disabled).
+//
+//*****************************************************************************
+#if defined(gcc)
+uint32_t __attribute__((naked)) CPU_primask(void)
+{
+    uint32_t ret;
+
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+            "    bx      lr\n"
+            : "=r" (ret));
+
+    //
+    // The return is handled in the inline assembly, but the compiler will
+    // still complain if there is not an explicit return here (despite the fact
+    // that this does not result in any code being produced because of the
+    // naked attribute).
+    //
+    return(ret);
+}
+#endif
+#if defined(ewarm)
+uint32_t CPU_primask(void)
+{
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n");
+
+    //
+    // "Warning[Pe940]: missing return statement at end of non-void function"
+    // is suppressed here to avoid putting a "bx lr" in the inline assembly
+    // above and a superfluous return statement here.
+    //
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#endif
+#if defined(keil)
+__asm uint32_t CPU_primask(void)
+{
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    mrs r0, PRIMASK;
+    bx lr
+}
+#endif
+#if defined(ccs)
+uint32_t CPU_primask(void)
+{
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+            "    bx      lr\n");
+
+    //
+    // The following keeps the compiler happy, because it wants to see a
+    // return value from this function.  It will generate code to return
+    // a zero.  However, the real return is the "bx lr" above, so the
+    // return(0) is never executed and the function returns with the value
+    // you expect in R0.
+    //
+    return(0);
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function for the CPSIE instruction.  Returns the state of PRIMASK
+// on entry.
+//
+//*****************************************************************************
+#if defined(gcc)
+uint32_t __attribute__((naked)) CPU_cpsie(void)
+{
+    uint32_t ret;
+
+    //
+    // Read PRIMASK and enable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+            "    cpsie   i\n"
+            "    bx      lr\n"
+            : "=r" (ret));
+
+    //
+    // The return is handled in the inline assembly, but the compiler will
+    // still complain if there is not an explicit return here (despite the fact
+    // that this does not result in any code being produced because of the
+    // naked attribute).
+    //
+    return(ret);
+}
+#endif
+#if defined(ewarm)
+uint32_t CPU_cpsie(void)
+{
+    //
+    // Read PRIMASK and enable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+            "    cpsie   i\n");
+
+    //
+    // "Warning[Pe940]: missing return statement at end of non-void function"
+    // is suppressed here to avoid putting a "bx lr" in the inline assembly
+    // above and a superfluous return statement here.
+    //
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#endif
+#if defined(keil)
+__asm uint32_t CPU_cpsie(void)
+{
+    //
+    // Read PRIMASK and enable interrupts.
+    //
+    mrs r0, PRIMASK;
+    cpsie i;
+    bx lr
+}
+#endif
+#if defined(ccs)
+uint32_t CPU_cpsie(void)
+{
+    //
+    // Read PRIMASK and enable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+            "    cpsie   i\n"
+            "    bx      lr\n");
+
+    //
+    // The following keeps the compiler happy, because it wants to see a
+    // return value from this function.  It will generate code to return
+    // a zero.  However, the real return is the "bx lr" above, so the
+    // return(0) is never executed and the function returns with the value
+    // you expect in R0.
+    //
+    return(0);
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function for the CPUWFI instruction.
+//
+//*****************************************************************************
+#if defined(gcc)
+void __attribute__((naked)) CPU_wfi(void)
+{
+    //
+    // Wait for the next interrupt.
+    //
+    __asm("    wfi\n"
+            "    bx      lr\n");
+}
+#endif
+#if defined(ewarm)
+void CPU_wfi(void)
+{
+    //
+    // Wait for the next interrupt.
+    //
+    __asm("    wfi\n");
+}
+#endif
+#if defined(keil)
+__asm void CPU_wfi(void)
+{
+    //
+    // Wait for the next interrupt.
+    //
+    wfi;
+    bx lr
+}
+#endif
+#if defined(ccs)
+void CPU_wfi(void)
+{
+    //
+    // Wait for the next interrupt.
+    //
+    __asm("    wfi\n");
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function for writing the BASEPRI register.
+//
+//*****************************************************************************
+#if defined(gcc)
+void __attribute__((naked)) CPU_basepriSet(uint32_t newBasepri)
+{
+    //
+    // Set the BASEPRI register
+    //
+    __asm("    msr     BASEPRI, r0\n"
+            "    bx      lr\n");
+}
+#endif
+#if defined(ewarm)
+void CPU_basepriSet(uint32_t newBasepri)
+{
+    //
+    // Set the BASEPRI register
+    //
+    __asm("    msr     BASEPRI, r0\n");
+}
+#endif
+#if defined(keil)
+__asm void CPU_basepriSet(uint32_t newBasepri)
+{
+    //
+    // Set the BASEPRI register
+    //
+    msr BASEPRI, r0;
+    bx lr
+}
+#endif
+#if defined(ccs)
+void CPU_basepriSet(uint32_t newBasepri)
+{
+    //
+    // Set the BASEPRI register
+    //
+    __asm("    msr     BASEPRI, r0\n");
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function for reading the BASEPRI register.
+//
+//*****************************************************************************
+#if defined(gcc)
+uint32_t __attribute__((naked)) CPU_basepriGet(void)
+{
+    uint32_t ret;
+
+    //
+    // Read BASEPRI
+    //
+    __asm("    mrs     r0, BASEPRI\n"
+            "    bx      lr\n"
+            : "=r" (ret));
+
+    //
+    // The return is handled in the inline assembly, but the compiler will
+    // still complain if there is not an explicit return here (despite the fact
+    // that this does not result in any code being produced because of the
+    // naked attribute).
+    //
+    return(ret);
+}
+#endif
+#if defined(ewarm)
+uint32_t CPU_basepriGet(void)
+{
+    //
+    // Read BASEPRI
+    //
+    __asm("    mrs     r0, BASEPRI\n");
+
+    //
+    // "Warning[Pe940]: missing return statement at end of non-void function"
+    // is suppressed here to avoid putting a "bx lr" in the inline assembly
+    // above and a superfluous return statement here.
+    //
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#endif
+#if defined(keil)
+__asm uint32_t CPU_basepriGet(void)
+{
+    //
+    // Read BASEPRI
+    //
+    mrs r0, BASEPRI;
+    bx lr
+}
+#endif
+#if defined(ccs)
+uint32_t CPU_basepriGet(void)
+{
+    //
+    // Read BASEPRI
+    //
+    __asm("    mrs     r0, BASEPRI\n"
+            "    bx      lr\n");
+
+    //
+    // The following keeps the compiler happy, because it wants to see a
+    // return value from this function.  It will generate code to return
+    // a zero.  However, the real return is the "bx lr" above, so the
+    // return(0) is never executed and the function returns with the value
+    // you expect in R0.
+    //
+    return(0);
+}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cpu.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cpu.h
new file mode 100644
index 000000000..8ac6875c8
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cpu.h
@@ -0,0 +1,76 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __CPU_H__
+#define __CPU_H__
+
+#include <stdint.h>
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Prototypes.
+//
+//*****************************************************************************
+extern uint32_t CPU_cpsid(void);
+extern uint32_t CPU_cpsie(void);
+extern uint32_t CPU_primask(void);
+extern void CPU_wfi(void);
+extern uint32_t CPU_basepriGet(void);
+extern void CPU_basepriSet(uint32_t newBasepri);
+
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __CPU_H__
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/crc32.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/crc32.c
new file mode 100644
index 000000000..8db29b402
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/crc32.c
@@ -0,0 +1,144 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#include "crc32.h"
+#include <msp.h>
+#include <debug.h>
+
+void CRC32_setSeed(uint32_t seed, uint_fast8_t crcType)
+{
+    ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
+
+    if (CRC16_MODE == crcType)
+        CRC32->rCRC16INIRES = seed;
+    else
+    {
+        CRC32->rCRC32INIRES_HI = ((seed & 0xFFFF0000) >> 16);
+        CRC32->rCRC32INIRES_LO = (seed & 0xFFFF);
+    }
+}
+
+void CRC32_set8BitData(uint8_t dataIn, uint_fast8_t crcType)
+{
+    ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
+
+    if (CRC16_MODE == crcType)
+        HWREG8(CRC32_BASE + OFS_CRC16DI) = dataIn;
+    else
+        HWREG8(CRC32_BASE + OFS_CRC32DI) = dataIn;
+}
+
+void CRC32_set16BitData(uint16_t dataIn, uint_fast8_t crcType)
+{
+    ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
+
+    if (CRC16_MODE == crcType)
+        CRC32->rCRC16DI = dataIn;
+    else
+        CRC32->rCRC32DI = dataIn;
+}
+
+void CRC32_set32BitData(uint32_t dataIn)
+{
+    //CRC32->rCRC32DI = dataIn & 0xFFFF;
+    //CRC32->rCRC32DI = (uint16_t) ((dataIn & 0xFFFF0000) >> 16);
+
+    HWREG16(CRC32_BASE + OFS_CRC32DI) = dataIn & 0xFFFF;
+    HWREG16(CRC32_BASE + OFS_CRC32DI) = (uint16_t)(
+            (dataIn & 0xFFFF0000) >> 16);
+}
+
+void CRC32_set8BitDataReversed(uint8_t dataIn, uint_fast8_t crcType)
+{
+    ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
+
+    if (CRC16_MODE == crcType)
+        HWREG8(CRC32_BASE + OFS_CRC16DIRB) = dataIn;
+    else
+        HWREG8(CRC32_BASE + OFS_CRC32DIRB) = dataIn;
+}
+
+void CRC32_set16BitDataReversed(uint16_t dataIn, uint_fast8_t crcType)
+{
+    ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
+
+    if (CRC16_MODE == crcType)
+        CRC32->rCRC16DIRB = dataIn;
+    else
+        CRC32->rCRC32DIRB = dataIn;
+}
+
+void CRC32_set32BitDataReversed(uint32_t dataIn)
+{
+    HWREG16(CRC32_BASE + OFS_CRC32DIRB) = dataIn & 0xFFFF;
+    HWREG16(CRC32_BASE + OFS_CRC32DIRB) = (uint16_t)(
+            (dataIn & 0xFFFF0000) >> 16);
+    //CRC32->rCRC32DIRB = dataIn & 0xFFFF;
+    //CRC32->rCRC32DIRB = (uint16_t) ((dataIn & 0xFFFF0000) >> 16);
+}
+
+uint32_t CRC32_getResult(uint_fast8_t crcType)
+{
+    uint32_t result;
+    ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
+
+    if (CRC16_MODE == crcType)
+        return CRC32->rCRC16INIRES;
+    else
+    {
+        result = CRC32->rCRC32INIRES_HI;
+        result = (result << 16);
+        result |= CRC32->rCRC32INIRES_LO;
+        return (result);
+    }
+}
+
+uint32_t CRC32_getResultReversed(uint_fast8_t crcType)
+{
+    uint32_t result;
+    ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
+
+    if (CRC16_MODE == crcType)
+        return CRC32->rCRC16RESR;
+    else
+    {
+        result = CRC32->rCRC32RESR_HI;
+        result = (result << 16);
+        result |= CRC32->rCRC32RESR_LO;
+        return (result);
+    }
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/crc32.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/crc32.h
new file mode 100644
index 000000000..e385e7a70
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/crc32.h
@@ -0,0 +1,235 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef _CRC_32_H
+
+//*****************************************************************************
+//
+//! \addtogroup crc32_api
+//! @{
+//
+//*****************************************************************************
+
+#include <stdint.h>
+
+#define CRC16_MODE 0x00
+#define CRC32_MODE 0x01
+
+//*****************************************************************************
+//
+//! Sets the seed for the CRC.
+//!
+//! \param seed is the seed for the CRC to start generating a signature from.
+//!        Modified bits are \b CRC16INIRESL0 of \b CRC16INIRESL0 register.
+//!            \b CRC32INIRESL0 of \b CRC32INIRESL0 register
+//! \param crcType selects between CRC32 and CRC16
+//!            Valid values are \b CRC16_MODE and \b CRC32_MODE
+//!
+//! This function sets the seed for the CRC to begin generating a signature with
+//! the given seed and all passed data. Using this function resets the CRC32
+//! signature.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void CRC32_setSeed(uint32_t seed, uint_fast8_t crcType);
+
+//*****************************************************************************
+//
+//! Sets the 8 Bit data to add into the CRC module to generate a new signature.
+//!
+//! \param dataIn is the data to be added, through the CRC module, to the
+//!       signature.
+//!        Modified bits are \b CRC16DIB0 of \b CRC16DIB0 register.
+//!                            \b CRC32DIB0 of \b CRC32DIB0 register.
+//! \param crcType selects between CRC32 and CRC16
+//!            Valid values are \b CRC16_MODE and \b CRC32_MODE
+//!
+//! This function sets the given data into the CRC module to generate the new
+//! signature from the current signature and new data. Bit 0 is
+//!    treated as LSB.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void CRC32_set8BitData(uint8_t dataIn, uint_fast8_t crcType);
+
+//*****************************************************************************
+//
+//! Sets the 16 Bit data to add into the CRC module to generate a new signature.
+//!
+//! \param dataIn is the data to be added, through the CRC module, to the
+//!       signature.
+//!        Modified bits are \b CRC16DIW0 of \b CRC16DIW0 register.
+//!                          \b CRC32DIW0 of \b CRC32DIW0 register.
+//! \param crcType selects between CRC32 and CRC16
+//!            Valid values are \b CRC16_MODE and \b CRC32_MODE
+//!
+//! This function sets the given data into the CRC module to generate the new
+//! signature from the current signature and new data. Bit 0 is
+//!    treated as LSB
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void CRC32_set16BitData(uint16_t dataIn, uint_fast8_t crcType);
+
+//*****************************************************************************
+//
+//! Sets the 32 Bit data to add into the CRC module to generate a new signature.
+//!    Available only for CRC32_MODE and not for CRC16_MODE
+//! \param dataIn is the data to be added, through the CRC module, to the
+//!       signature.
+//!        Modified bits are \b CRC32DIL0 of \b CRC32DIL0 register.
+//!
+//! This function sets the given data into the CRC module to generate the new
+//! signature from the current signature and new data. Bit 0 is
+//!    treated as LSB
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void CRC32_set32BitData(uint32_t dataIn);
+
+//*****************************************************************************
+//
+//! Translates the data by reversing the bits in each 8 bit data and then sets
+//! this data to add into the CRC module to generate a new signature.
+//!
+//! \param dataIn is the data to be added, through the CRC module, to the
+//!       signature.
+//!        Modified bits are \b CRC16DIRBB0 of \b CRC16DIRBB0 register.
+//!                             \b CRC32DIRBB0 of \b CRC32DIRBB0 register.
+//! \param crcType selects between CRC32 and CRC16
+//!            Valid values are \b CRC16_MODE and \b CRC32_MODE
+//!
+//! This function first reverses the bits in each byte of the data and then
+//! generates the new signature from the current signature and new translated
+//! data. Bit 0 is treated as MSB.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void CRC32_set8BitDataReversed(uint8_t dataIn, uint_fast8_t crcType);
+
+//*****************************************************************************
+//
+//! Translates the data by reversing the bits in each 16 bit data and then
+//!    sets this data to add into the CRC module to generate a new signature.
+//!
+//! \param dataIn is the data to be added, through the CRC module, to the
+//!       signature.
+//!        Modified bits are \b CRC16DIRBW0 of \b CRC16DIRBW0 register.
+//!                             \b CRC32DIRBW0 of \b CRC32DIRBW0 register.
+//! \param crcType selects between CRC32 and CRC16
+//!            Valid values are \b CRC16_MODE and \b CRC32_MODE
+//!
+//! This function first reverses the bits in each byte of the data and then
+//! generates the new signature from the current signature and new translated
+//! data.  Bit 0 is treated as MSB.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void CRC32_set16BitDataReversed(uint16_t dataIn, uint_fast8_t crcType);
+
+//*****************************************************************************
+//
+//! Translates the data by reversing the bits in each 32 Bit Data and then
+//!    sets this data to add into the CRC module to generate a new signature.
+//!    Available only for CRC32 mode and not for CRC16 mode
+//! \param dataIn is the data to be added, through the CRC module, to the
+//!       signature.
+//!        Modified bits are \b CRC32DIRBL0 of \b CRC32DIRBL0 register.
+//!
+//! This function first reverses the bits in each byte of the data and then
+//! generates the new signature from the current signature and new translated
+//! data.  Bit 0 is treated as MSB.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void CRC32_set32BitDataReversed(uint32_t dataIn);
+
+//*****************************************************************************
+//
+//! Returns the value of CRC Signature Result.
+//!
+//! \param crcType selects between CRC32 and CRC16
+//!            Valid values are \b CRC16_MODE and \b CRC32_MODE
+//!
+//! This function returns the value of the signature result generated by the CRC.
+//! Bit 0 is treated as LSB.
+//! \return uint32_t Result
+//
+//*****************************************************************************
+extern uint32_t CRC32_getResult(uint_fast8_t crcType);
+
+//*****************************************************************************
+//
+//! Returns the bit-wise reversed format of the 32 bit Signature Result.
+//!
+//! \param crcType selects between CRC32 and CRC16
+//!            Valid values are \b CRC16_MODE and \b CRC32_MODE
+//!
+//! This function returns the bit-wise reversed format of the Signature Result.
+//! Bit 0 is treated as MSB.
+//!
+//! \return uint32_t Result
+//
+//*****************************************************************************
+extern uint32_t CRC32_getResultReversed(uint_fast8_t crcType);
+
+/* Defines for future devices that might have multiple instances */
+#define CRC32_setSeedMultipleInstance(a,b,c) CRC32_setSeed(b,c)
+#define CRC32_set8BitDataMultipleInstance(a,b,c)  CRC32_set8BitData(b,c)
+#define CRC32_set16BitDataMultipleInstance(a,b,c) CRC32_set16BitData(b,c)
+#define CRC32_set32BitDataMultipleInstance(a,b) CRC32_set32BitData(b)
+#define CRC32_set8BitDataReversedMultipleInstance(a,b,c) CRC32_set8BitDataReversed(b,c)
+#define CRC32_set16BitDataReversedMultipleInstance(a,b,c) CRC32_set16BitDataReversed(b,c)
+#define CRC32_set32BitDataReversedMultipleInstance(a,b) CRC32_set32BitDataReversed(b)
+#define CRC32_getResultMultipleInstance(a,b) CRC32_getResult()
+#define CRC32_getResultReversedMultipleInstance(a,b) CRC32_getResultReversed(b)
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cs.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cs.c
new file mode 100644
index 000000000..40fa250ae
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cs.c
@@ -0,0 +1,914 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+/* Standard Includes */
+#include <stdint.h>
+
+/* DriverLib Includes */
+#include <cs.h>
+#include <debug.h>
+#include <sysctl.h>
+#include <interrupt.h>
+
+/* Statics */
+static uint32_t hfxtFreq;
+static uint32_t lfxtFreq;
+
+#ifdef DEBUG
+
+bool _CSIsClockDividerValid(uint8_t divider)
+{
+    return ((divider == CS_CLOCK_DIVIDER_1) || (divider == CS_CLOCK_DIVIDER_2)
+            || (divider == CS_CLOCK_DIVIDER_4) || (divider == CS_CLOCK_DIVIDER_8)
+            || (divider == CS_CLOCK_DIVIDER_16) || (divider == CS_CLOCK_DIVIDER_32)
+            || (divider == CS_CLOCK_DIVIDER_64) || (divider == CS_CLOCK_DIVIDER_128));
+}
+
+#endif
+
+static uint32_t _CSGetHFXTFrequency()
+{
+    if (hfxtFreq >= CS_1MHZ && hfxtFreq <= CS_4MHZ)
+        return HFXTFREQ_0;
+    else if (hfxtFreq > CS_4MHZ && hfxtFreq <= CS_8MHZ)
+        return HFXTFREQ_1;
+    else if (hfxtFreq > CS_8MHZ && hfxtFreq <= CS_16MHZ)
+        return HFXTFREQ_2;
+    else if (hfxtFreq > CS_16MHZ && hfxtFreq <= CS_24MHZ)
+        return HFXTFREQ_3;
+    else if (hfxtFreq > CS_24MHZ && hfxtFreq <= CS_32MHZ)
+        return HFXTFREQ_4;
+    else if (hfxtFreq > CS_32MHZ && hfxtFreq <= CS_40MHZ)
+        return HFXTFREQ_5;
+    else if (hfxtFreq > CS_40MHZ && hfxtFreq <= CS_48MHZ)
+        return HFXTFREQ_5;
+    else
+    {
+        ASSERT(false);
+        return 0;
+    }
+
+}
+
+static uint32_t _CSGetDividerValue(uint32_t wDivider)
+{
+    switch (wDivider)
+    {
+    case CS_CLOCK_DIVIDER_1:
+        return 1;
+    case CS_CLOCK_DIVIDER_2:
+        return 2;
+    case CS_CLOCK_DIVIDER_4:
+        return 4;
+    case CS_CLOCK_DIVIDER_8:
+        return 8;
+    case CS_CLOCK_DIVIDER_16:
+        return 16;
+    case CS_CLOCK_DIVIDER_32:
+        return 32;
+    case CS_CLOCK_DIVIDER_64:
+        return 64;
+    case CS_CLOCK_DIVIDER_128:
+        return 128;
+    default:
+        ASSERT(false);
+        return 1;
+    }
+}
+
+static uint32_t _CSComputeCLKFrequency(uint32_t wClockSource, uint32_t wDivider)
+{
+    uint8_t bDivider;
+
+    bDivider = _CSGetDividerValue(wDivider);
+
+    switch (wClockSource)
+    {
+    case CS_LFXTCLK_SELECT:
+    {
+        if (BITBAND_PERI(CS->rIFG.r, LFXTIFG_OFS))
+        {
+            CS_clearInterruptFlag(CS_LFXT_FAULT);
+
+            if (BITBAND_PERI(CS->rIFG.r, LFXTIFG_OFS))
+            {
+                if (BITBAND_PERI(CS->rCLKEN.r, REFOFSEL_OFS))
+                    return (128000 / bDivider);
+                else
+                    return (32000 / bDivider);
+            }
+        }
+        return lfxtFreq / bDivider;
+    }
+    case CS_HFXTCLK_SELECT:
+    {
+        if (BITBAND_PERI(CS->rIFG.r, HFXTIFG_OFS))
+        {
+            CS_clearInterruptFlag(CS_HFXT_FAULT);
+
+            if (BITBAND_PERI(CS->rIFG.r, HFXTIFG_OFS))
+            {
+                if (BITBAND_PERI(CS->rCLKEN.r, REFOFSEL_OFS))
+                    return (128000 / bDivider);
+                else
+                    return (32000 / bDivider);
+            }
+        }
+        return hfxtFreq / bDivider;
+    }
+    case CS_VLOCLK_SELECT:
+        return CS_VLOCLK_FREQUENCY / bDivider;
+    case CS_REFOCLK_SELECT:
+    {
+        if (BITBAND_PERI(CS->rCLKEN.r, REFOFSEL_OFS))
+            return (128000 / bDivider);
+        else
+            return (32000 / bDivider);
+    }
+    case CS_DCOCLK_SELECT:
+        return (CS_getDCOFrequency() / bDivider);
+    case CS_MODOSC_SELECT:
+        return CS_MODCLK_FREQUENCY / bDivider;
+    default:
+        ASSERT(false);
+        return 0;
+    }
+}
+
+//******************************************************************************
+// Internal function for getting DCO nominal frequency
+//******************************************************************************
+static uint32_t _CSGetDOCFrequency(void)
+{
+    uint32_t dcoFreq;
+
+    switch (CS->rCTL0.r & DCORSEL_M)
+    {
+    case DCORSEL_0:
+        dcoFreq = 1500000;
+        break;
+    case DCORSEL_1:
+        dcoFreq = 3000000;
+        break;
+    case DCORSEL_2:
+        dcoFreq = 6000000;
+        break;
+    case DCORSEL_3:
+        dcoFreq = 12000000;
+        break;
+    case DCORSEL_4:
+        dcoFreq = 24000000;
+        break;
+    case DCORSEL_5:
+        dcoFreq = 48000000;
+        break;
+    default:
+        dcoFreq = 0;
+    }
+
+    return (dcoFreq);
+}
+
+void CS_setExternalClockSourceFrequency(uint32_t lfxt_XT_CLK_frequency,
+        uint32_t hfxt_XT_CLK_frequency)
+{
+    hfxtFreq = hfxt_XT_CLK_frequency;
+    lfxtFreq = lfxt_XT_CLK_frequency;
+}
+
+void CS_initClockSignal(uint32_t selectedClockSignal, uint32_t clockSource,
+        uint32_t clockSourceDivider)
+{
+    ASSERT(_CSIsClockDividerValid(clockSourceDivider));
+
+    /* Unlocking the CS Module */
+    CS->rKEY.r = CS_KEY;
+
+    switch (selectedClockSignal)
+    {
+    case CS_ACLK:
+    {
+        /* Making sure that the clock signal for ACLK isn't set to anything
+         * invalid
+         */
+        ASSERT(
+                (selectedClockSignal != CS_DCOCLK_SELECT)
+                && (selectedClockSignal != CS_MODOSC_SELECT)
+                && (selectedClockSignal != CS_HFXTCLK_SELECT));
+
+        /* Waiting for the clock source ready bit to be valid before
+         * changing */
+        while (!BITBAND_PERI(CS->rSTAT.r, ACLK_READY_OFS))
+            ;
+
+        /* Setting the divider and source */
+        CS->rCTL1.r = ((clockSourceDivider >> CS_ACLK_DIV_BITPOS)
+                | (clockSource << CS_ACLK_SRC_BITPOS))
+                | (CS->rCTL1.r & ~(SELA_M | DIVA_M));
+
+        /* Waiting for ACLK to be ready again */
+        while (!BITBAND_PERI(CS->rSTAT.r, ACLK_READY_OFS))
+            ;
+
+        break;
+    }
+    case CS_MCLK:
+    {
+
+        /* Waiting for the clock source ready bit to be valid before
+         * changing */
+        while (!BITBAND_PERI(CS->rSTAT.r, MCLK_READY_OFS))
+            ;
+
+        CS->rCTL1.r = ((clockSourceDivider >> CS_MCLK_DIV_BITPOS)
+                | (clockSource << CS_MCLK_SRC_BITPOS))
+                | (CS->rCTL1.r & ~(SELM_M | DIVM_M));
+
+        /* Waiting for MCLK to be ready */
+        while (!BITBAND_PERI(CS->rSTAT.r, MCLK_READY_OFS))
+            ;
+
+        break;
+    }
+    case CS_SMCLK:
+    {
+        /* Waiting for the clock source ready bit to be valid before
+         * changing */
+        while (!BITBAND_PERI(CS->rSTAT.r, SMCLK_READY_OFS))
+            ;
+
+        CS->rCTL1.r = ((clockSourceDivider >> CS_SMCLK_DIV_BITPOS)
+                | (clockSource << CS_HSMCLK_SRC_BITPOS))
+                | (CS->rCTL1.r & ~(DIVS_M | SELS_M));
+
+        /* Waiting for SMCLK to be ready */
+        while (!BITBAND_PERI(CS->rSTAT.r, SMCLK_READY_OFS))
+            ;
+
+        break;
+    }
+    case CS_HSMCLK:
+    {
+        /* Waiting for the clock source ready bit to be valid before
+         * changing */
+        while (!BITBAND_PERI(CS->rSTAT.r, HSMCLK_READY_OFS))
+            ;
+
+        CS->rCTL1.r = ((clockSourceDivider >> CS_HSMCLK_DIV_BITPOS)
+                | (clockSource << CS_HSMCLK_SRC_BITPOS))
+                | (CS->rCTL1.r & ~(DIVHS_M | SELS_M));
+
+        /* Waiting for HSMCLK to be ready */
+        while (!BITBAND_PERI(CS->rSTAT.r, HSMCLK_READY_OFS))
+            ;
+
+        break;
+    }
+    case CS_BCLK:
+    {
+
+        /* Waiting for the clock source ready bit to be valid before
+         * changing */
+        while (!BITBAND_PERI(CS->rSTAT.r, BCLK_READY_OFS))
+            ;
+
+        /* Setting the clock source and then returning
+         * (cannot divide CLK)
+         */
+        if (clockSource == CS_LFXTCLK_SELECT)
+            BITBAND_PERI(CS->rCTL1.r, SELB_OFS) = 0;
+        else if (clockSource == CS_REFOCLK_SELECT)
+            BITBAND_PERI(CS->rCTL1.r, SELB_OFS) = 1;
+        else
+            ASSERT(false);
+
+        /* Waiting for BCLK to be ready */
+        while (!BITBAND_PERI(CS->rSTAT.r, BCLK_READY_OFS))
+            ;
+
+        break;
+    }
+    default:
+    {
+        /* Should never get here */
+        ASSERT(false);
+    }
+    }
+
+    /* Locking the module */
+    BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
+}
+
+void CS_startHFXT(bool bypassMode)
+{
+    CS_startHFXTWithTimeout(bypassMode, 0);
+}
+
+void CS_startHFXTWithTimeout(bool bypassMode, uint32_t timeout)
+{
+    uint32_t wHFFreqRange;
+    uint8_t bNMIStatus;
+    bool boolTimeout;
+
+    /* Unlocking the CS Module */
+    CS->rKEY.r = CS_KEY;
+
+    /* Saving status and temporarily disabling NMIs for UCS faults */
+    bNMIStatus = SysCtl_getNMISourceStatus() & SYSCTL_CS_SRC;
+    SysCtl_disableNMISource(SYSCTL_CS_SRC);
+
+    /* Determining which frequency range to use */
+    wHFFreqRange = _CSGetHFXTFrequency();
+    boolTimeout = (timeout == 0) ? false : true;
+
+    /* Setting to maximum drive strength  */
+    BITBAND_PERI(CS->rCTL2.r, HFXTDRIVE_OFS) = 1;
+    CS->rCTL2.r = (CS->rCTL2.r & (~HFXTFREQ_M)) | (wHFFreqRange);
+
+    if (bypassMode)
+    {
+        BITBAND_PERI(CS->rCTL2.r, HFXTBYPASS_OFS) = 1;
+    } else
+    {
+        BITBAND_PERI(CS->rCTL2.r, HFXTBYPASS_OFS) = 0;
+    }
+
+    /* Starting and Waiting for frequency stabilization */
+    BITBAND_PERI(CS->rCTL2.r, HFXT_EN_OFS) = 1;
+    while (BITBAND_PERI(CS->rIFG.r, HFXTIFG_OFS))
+    {
+        if (boolTimeout && ((--timeout) == 0))
+            break;
+
+        BITBAND_PERI(CS->rCLRIFG.r,CLR_HFXTIFG_OFS) = 1;
+    }
+
+    /* Setting the drive strength */
+    if (!bypassMode)
+    {
+        if (wHFFreqRange != HFXTFREQ_0)
+            BITBAND_PERI(CS->rCTL2.r, HFXTDRIVE_OFS) = 1;
+        else
+            BITBAND_PERI(CS->rCTL2.r, HFXTDRIVE_OFS) = 0;
+    }
+
+    /* Locking the module */
+    BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
+
+    /* Enabling the NMI state */
+    SysCtl_enableNMISource(bNMIStatus);
+
+}
+
+void CS_startLFXT(uint32_t xtDrive)
+{
+    CS_startLFXTWithTimeout(xtDrive, 0);
+}
+
+void CS_startLFXTWithTimeout(uint32_t xtDrive, uint32_t timeout)
+{
+    uint8_t bNMIStatus;
+    bool boolBypassMode, boolTimeout;
+
+    ASSERT(lfxtFreq != 0)
+    ASSERT(
+            (xtDrive == CS_LFXT_DRIVE0) || (xtDrive == CS_LFXT_DRIVE1)
+            || (xtDrive == CS_LFXT_DRIVE2)
+            || (xtDrive == CS_LFXT_DRIVE3)
+            || (xtDrive == CS_LFXT_BYPASS));
+
+    /* Unlocking the CS Module */
+    CS->rKEY.r = CS_KEY;
+
+    /* Saving status and temporarily disabling NMIs for UCS faults */
+    bNMIStatus = SysCtl_getNMISourceStatus() & SYSCTL_CS_SRC;
+    SysCtl_disableNMISource(SYSCTL_CS_SRC);
+    boolBypassMode = (xtDrive == CS_LFXT_BYPASS) ? true : false;
+    boolTimeout = (timeout == 0) ? false : true;
+
+    /* Setting to maximum drive strength  */
+    if (boolBypassMode)
+    {
+        BITBAND_PERI(CS->rCTL2.r, LFXTBYPASS_OFS) = 1;
+    } else
+    {
+        CS->rCTL2.r |= (CS_LFXT_DRIVE3);
+        BITBAND_PERI(CS->rCTL2.r, LFXTBYPASS_OFS) = 0;
+    }
+
+    /* Waiting for frequency stabilization */
+    BITBAND_PERI(CS->rCTL2.r, LFXT_EN_OFS) = 1;
+
+    while (BITBAND_PERI(CS->rIFG.r, LFXTIFG_OFS))
+    {
+        if (boolTimeout && ((--timeout) == 0))
+            break;
+
+        BITBAND_PERI(CS->rCLRIFG.r,CLR_LFXTIFG_OFS) = 1;
+    }
+
+    /* Setting the drive strength */
+    if (!boolBypassMode)
+    {
+        CS->rCTL2.r = ((CS->rCTL2.r & ~CS_LFXT_DRIVE3) | xtDrive);
+    }
+
+    /* Locking the module */
+    BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
+
+    /* Enabling the NMI state */
+    SysCtl_enableNMISource(bNMIStatus);
+}
+
+void CS_enableClockRequest(uint32_t selectClock)
+{
+    ASSERT(
+            selectClock == CS_ACLK || selectClock == CS_HSMCLK
+            || selectClock == CS_SMCLK || selectClock == CS_MCLK);
+
+    /* Unlocking the module */
+    CS->rKEY.r = CS_KEY;
+
+    CS->rCLKEN.r |= selectClock;
+
+    /* Locking the module */
+    BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
+}
+
+void CS_disableClockRequest(uint32_t selectClock)
+{
+    ASSERT(
+            selectClock == CS_ACLK || selectClock == CS_HSMCLK
+            || selectClock == CS_SMCLK || selectClock == CS_MCLK);
+
+    /* Unlocking the module */
+    CS->rKEY.r = CS_KEY;
+
+    CS->rCLKEN.r &= ~selectClock;
+
+    /* Locking the module */
+    BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
+}
+
+void CS_setReferenceOscillatorFrequency(uint8_t referenceFrequency)
+{
+    ASSERT(
+            referenceFrequency == CS_REFO_32KHZ
+            || referenceFrequency == CS_REFO_128KHZ);
+
+    /* Unlocking the module */
+    CS->rKEY.r = CS_KEY;
+
+    BITBAND_PERI(CS->rCLKEN.r, REFOFSEL_OFS) = referenceFrequency;
+
+    /* Locking the module */
+    BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
+}
+
+void CS_enableDCOExternalResistor(void)
+{
+    /* Unlocking the module */
+    CS->rKEY.r = CS_KEY;
+
+    BITBAND_PERI(CS->rCTL0.r,DCORES_OFS) = 1;
+
+    /* Locking the module */
+    BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
+}
+
+void CS_setDCOExternalResistorCalibration(uint_fast8_t uiCalData)
+{
+    CS->rDCOERCAL.r = (uiCalData);
+}
+
+void CS_disableDCOExternalResistor(void)
+{
+    /* Unlocking the module */
+    CS->rKEY.r = CS_KEY;
+
+    BITBAND_PERI(CS->rCTL0.r,DCORES_OFS) = 0;
+
+    /* Locking the module */
+    BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
+}
+
+void CS_setDCOCenteredFrequency(uint32_t dcoFreq)
+{
+    ASSERT(
+            dcoFreq == CS_DCO_FREQUENCY_1_5 || dcoFreq == CS_DCO_FREQUENCY_3
+            || dcoFreq == CS_DCO_FREQUENCY_6
+            || dcoFreq == CS_DCO_FREQUENCY_12
+            || dcoFreq == CS_DCO_FREQUENCY_24
+            || dcoFreq == CS_DCO_FREQUENCY_48);
+
+    /* Unlocking the CS Module */
+    CS->rKEY.r = CS_KEY;
+
+    /* Resetting Tuning Parameters and Setting the frequency */
+    CS->rCTL0.r = ((CS->rCTL0.r & ~DCORSEL_M) | dcoFreq);
+
+    /* Locking the CS Module */
+    BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
+}
+
+void CS_tuneDCOFrequency(int16_t tuneParameter)
+{
+    CS->rKEY.r = CS_KEY;
+
+    if (tuneParameter < 0)
+    {
+         CS->rCTL0.r = ((CS->rCTL0.r & ~DCOTUNE_M) | (tuneParameter & DCOTUNE_M)
+                 | 0x1000);
+    } 
+    else
+    {
+        CS->rCTL0.r =
+                ((CS->rCTL0.r & ~DCOTUNE_M) | (tuneParameter & DCOTUNE_M));
+
+    }
+     
+     BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
+}
+
+uint32_t CS_getDCOFrequency(void)
+{
+    float dcoConst;
+    int32_t calVal;
+    uint32_t centeredFreq;
+    int16_t dcoTune;
+
+    dcoTune = CS->rCTL0.b.bDCOTUNE;
+    centeredFreq = _CSGetDOCFrequency();
+
+    if (dcoTune == 0)
+        return (uint32_t) centeredFreq;
+
+    /* Checking to see if we need to do signed conversion */
+    if (dcoTune & 0x1000)
+    {
+        dcoTune = dcoTune | 0xF000;
+    }
+    
+    /* DCORSEL = 5, in final silicon this will have a different calibration
+        value, but currently DCORSEL5 calibration is not populated 
+    if (centeredFreq == 48000000)
+    {
+         External Resistor 
+        if (BITBAND_PERI(CS->rCTL0.r, DCORES_OFS))
+        {
+            dcoConst = *((float *) &TLV->rDCOER_CONSTK_RSEL5);
+            calVal = TLV->rDCOER_FCAL_RSEL5;
+        }
+        Internal Resistor 
+        else
+        {
+            dcoConst = *((float *) &TLV->rDCOIR_CONSTK_RSEL5);
+            calVal = TLV->rDCOIR_FCAL_RSEL5;
+        }
+    }
+     DCORSEL = 4 
+    else
+    {*/
+        /* External Resistor */
+        if (BITBAND_PERI(CS->rCTL0.r, DCORES_OFS))
+        {
+            dcoConst = *((float *) &TLV->rDCOER_CONSTK_RSEL04);
+            calVal = TLV->rDCOER_FCAL_RSEL04;
+        }
+        /* Internal Resistor */
+        else
+        {
+            dcoConst = *((float *) &TLV->rDCOIR_CONSTK_RSEL04);
+            calVal = TLV->rDCOIR_FCAL_RSEL04;
+        }
+    /*}*/
+
+    return (uint32_t) ((centeredFreq)
+            / (1
+                    - ((dcoConst * dcoTune)
+                            / (8 * (1 + dcoConst * (768 - calVal))))));
+}
+
+void CS_setDCOFrequency(uint32_t dcoFrequency)
+{
+    int32_t nomFreq, calVal, dcoSigned;
+    int16_t dcoTune;
+    float dcoConst;
+ // bool rsel5 = false;
+    dcoSigned = (int32_t) dcoFrequency;
+
+    if (dcoFrequency < 2000000)
+    {
+        nomFreq = CS_15MHZ;
+        CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_1_5);
+    } else if (dcoFrequency < 4000000)
+    {
+        nomFreq = CS_3MHZ;
+        CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_3);
+    } else if (dcoFrequency < 8000000)
+    {
+        nomFreq = CS_6MHZ;
+        CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_6);
+    } else if (dcoFrequency < 16000000)
+    {
+        nomFreq = CS_12MHZ;
+        CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_12);
+    } else if (dcoFrequency < 32000000)
+    {
+        nomFreq = CS_24MHZ;
+        CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_24);
+    } else if (dcoFrequency < 640000001)
+    {
+        nomFreq = CS_48MHZ;
+        CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_48);
+      //  rsel5 = true;
+    } else
+    {
+        ASSERT(false);
+        return;
+    }
+    
+    if(dcoFrequency == nomFreq)
+    {
+       CS_tuneDCOFrequency(0);
+       return;
+    }
+
+    /* DCORSEL = 5, in final silicon this will have a different calibration
+        value, but currently DCORSEL5 calibration is not populated 
+    if (rsel5)
+    {
+        External Resistor 
+        if (BITBAND_PERI(CS->rCTL0.r, DCORES_OFS))
+        {
+            dcoConst = *((float *) &TLV->rDCOER_CONSTK_RSEL5);
+            calVal = TLV->rDCOER_FCAL_RSEL5;
+        }
+        Internal Resistor
+        else
+        {
+            dcoConst = *((float *) &TLV->rDCOIR_CONSTK_RSEL5);
+            calVal = TLV->rDCOIR_FCAL_RSEL5;
+        }
+    }
+    DCORSEL = 4
+    else
+    {*/
+        /* External Resistor */
+        if (BITBAND_PERI(CS->rCTL0.r, DCORES_OFS))
+        {
+            dcoConst = *((float *) &TLV->rDCOER_CONSTK_RSEL04);
+            calVal = TLV->rDCOER_FCAL_RSEL04;
+        }
+        /* Internal Resistor */
+        else
+        {
+            dcoConst = *((float *) &TLV->rDCOIR_CONSTK_RSEL04);
+            calVal = TLV->rDCOIR_FCAL_RSEL04;
+        }
+    /*}*/
+
+    dcoTune = (int16_t) (((dcoSigned - nomFreq)
+            * (1.0 + dcoConst * (768.0 - calVal)) * 8.0)
+            / (dcoSigned * dcoConst));
+
+    CS_tuneDCOFrequency(dcoTune);
+
+}
+
+uint32_t CS_getBCLK(void)
+{
+    if (BITBAND_PERI(CS->rCTL1.r, SELB_OFS))
+        return _CSComputeCLKFrequency(CS_REFOCLK_SELECT, CS_CLOCK_DIVIDER_1);
+    else
+        return _CSComputeCLKFrequency(CS_LFXTCLK_SELECT, CS_CLOCK_DIVIDER_1);
+}
+
+uint32_t CS_getHSMCLK(void)
+{
+    uint32_t wSource, wDivider;
+
+    wSource = (CS->rCTL1.r & SELS_M) >> CS_HSMCLK_SRC_BITPOS;
+    wDivider = ((CS->rCTL1.r & DIVHS_M) << CS_HSMCLK_DIV_BITPOS);
+
+    return _CSComputeCLKFrequency(wSource, wDivider);
+}
+
+uint32_t CS_getACLK(void)
+{
+    uint32_t wSource, wDivider;
+
+    wSource = (CS->rCTL1.r & SELA_M) >> CS_ACLK_SRC_BITPOS;
+    wDivider = ((CS->rCTL1.r & DIVA_M) << CS_ACLK_DIV_BITPOS);
+
+    return _CSComputeCLKFrequency(wSource, wDivider);
+}
+
+uint32_t CS_getSMCLK(void)
+{
+    uint32_t wDivider, wSource;
+
+    wSource = (CS->rCTL1.r & SELS_M) >> CS_HSMCLK_SRC_BITPOS;
+    wDivider = ((CS->rCTL1.r & DIVS_M));
+
+    return _CSComputeCLKFrequency(wSource, wDivider);
+
+}
+
+uint32_t CS_getMCLK(void)
+{
+    uint32_t wSource, wDivider;
+
+    wSource = (CS->rCTL1.r & SELM_M) << CS_MCLK_SRC_BITPOS;
+    wDivider = ((CS->rCTL1.r & DIVM_M) << CS_MCLK_DIV_BITPOS);
+
+    return _CSComputeCLKFrequency(wSource, wDivider);
+}
+
+void CS_enableFaultCounter(uint_fast8_t counterSelect)
+{
+    ASSERT(counterSelect == CS_HFXT_FAULT_COUNTER ||
+            counterSelect == CS_HFXT_FAULT_COUNTER);
+
+    /* Unlocking the module */
+    CS->rKEY.r = CS_KEY;
+
+    if (counterSelect == CS_HFXT_FAULT_COUNTER)
+    {
+        BITBAND_PERI(CS->rCTL3.r, FCNTHF_EN_OFS) = 1;
+    } else
+    {
+        BITBAND_PERI(CS->rCTL3.r, FCNTLF_EN_OFS) = 1;
+    }
+
+    /* Locking the module */
+    BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
+}
+
+void CS_disableFaultCounter(uint_fast8_t counterSelect)
+{
+    ASSERT(counterSelect == CS_HFXT_FAULT_COUNTER ||
+            counterSelect == CS_HFXT_FAULT_COUNTER);
+
+    /* Unlocking the module */
+    CS->rKEY.r = CS_KEY;
+
+    if (counterSelect == CS_HFXT_FAULT_COUNTER)
+    {
+        BITBAND_PERI(CS->rCTL3.r, FCNTHF_EN_OFS) = 0;
+    } else
+    {
+        BITBAND_PERI(CS->rCTL3.r, FCNTLF_EN_OFS) = 0;
+    }
+
+    /* Locking the module */
+    BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
+}
+
+void CS_resetFaultCounter(uint_fast8_t counterSelect)
+{
+    ASSERT(counterSelect == CS_HFXT_FAULT_COUNTER ||
+            counterSelect == CS_HFXT_FAULT_COUNTER);
+
+    /* Unlocking the module */
+    CS->rKEY.r = CS_KEY;
+
+    if (counterSelect == CS_HFXT_FAULT_COUNTER)
+    {
+        BITBAND_PERI(CS->rCTL3.r, RFCNTHF_OFS) = 1;
+    } else
+    {
+        BITBAND_PERI(CS->rCTL3.r, RFCNTLF_OFS) = 1;
+    }
+
+    /* Locking the module */
+    BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
+}
+
+void CS_startFaultCounter(uint_fast8_t counterSelect, uint_fast8_t countValue)
+{
+    ASSERT(counterSelect == CS_HFXT_FAULT_COUNTER ||
+            counterSelect == CS_HFXT_FAULT_COUNTER);
+
+    ASSERT(countValue == CS_FAULT_COUNTER_4096_CYCLES ||
+            countValue == CS_FAULT_COUNTER_8192_CYCLES ||
+            countValue == CS_FAULT_COUNTER_16384_CYCLES ||
+            countValue == CS_FAULT_COUNTER_32768_CYCLES);
+
+    /* Unlocking the module */
+    CS->rKEY.r = CS_KEY;
+
+    if (counterSelect == CS_HFXT_FAULT_COUNTER)
+    {
+        CS->rCTL3.r = ((CS->rCTL3.r & ~FCNTHF_M) | (countValue << 4));
+    } else
+    {
+        CS->rCTL3.r = ((CS->rCTL3.r & ~FCNTLF_M) | (countValue));
+    }
+
+    /* Locking the module */
+    BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
+}
+
+void CS_enableInterrupt(uint32_t flags)
+{
+    /* Unlocking the module */
+    CS->rKEY.r = CS_KEY;
+
+    CS->rIE.r |= flags;
+
+    /* Locking the module */
+    BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
+}
+
+void CS_disableInterrupt(uint32_t flags)
+{
+    /* Unlocking the module */
+    CS->rKEY.r = CS_KEY;
+
+    CS->rIE.r &= ~flags;
+
+    /* Locking the module */
+    BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
+}
+
+uint32_t CS_getInterruptStatus(void)
+{
+    return CS->rIFG.r;
+}
+
+uint32_t CS_getEnabledInterruptStatus(void)
+{
+    return CS_getInterruptStatus() & CS->rIE.r;
+}
+
+void CS_clearInterruptFlag(uint32_t flags)
+{
+    /* Unlocking the module */
+    CS->rKEY.r = CS_KEY;
+
+    CS->rCLRIFG.r |= flags;
+
+    /* Locking the module */
+    BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
+}
+
+void CS_registerInterrupt(void (*intHandler)(void))
+{
+    //
+    // Register the interrupt handler, returning an error if an error occurs.
+    //
+    Interrupt_registerInterrupt(INT_CS, intHandler);
+
+    //
+    // Enable the system control interrupt.
+    //
+    Interrupt_enableInterrupt(INT_CS);
+}
+
+void CS_unregisterInterrupt(void)
+{
+    //
+    // Disable the interrupt.
+    //
+    Interrupt_disableInterrupt(INT_CS);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    Interrupt_unregisterInterrupt(INT_CS);
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cs.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cs.h
new file mode 100644
index 000000000..b152240b0
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cs.h
@@ -0,0 +1,843 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __CS_H__
+#define __CS_H__
+
+//*****************************************************************************
+//
+//! \addtogroup cs_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <msp.h>
+
+//*****************************************************************************
+//
+// Control specific variables
+//
+//*****************************************************************************
+#define CS_CLOCK_DIVIDER_1 DIVS_0
+#define CS_CLOCK_DIVIDER_2 DIVS_1
+#define CS_CLOCK_DIVIDER_4 DIVS_2
+#define CS_CLOCK_DIVIDER_8 DIVS_3
+#define CS_CLOCK_DIVIDER_16 DIVS_4
+#define CS_CLOCK_DIVIDER_32 DIVS_5
+#define CS_CLOCK_DIVIDER_64 DIVS_6
+#define CS_CLOCK_DIVIDER_128 DIVS_7
+
+#define CS_LFXTCLK_SELECT   SELM_0
+#define CS_HFXTCLK_SELECT   SELM_5
+#define CS_VLOCLK_SELECT    SELM_1
+#define CS_REFOCLK_SELECT   SELM_2
+#define CS_DCOCLK_SELECT    SELM_3
+#define CS_MODOSC_SELECT    SELM_4
+
+#define CS_KEY 0x695A
+
+/* Number of positions to shift for divider calculation */
+#define CS_ACLK_DIV_BITPOS 0x04
+#define CS_MCLK_DIV_BITPOS 0x0C
+#define CS_SMCLK_DIV_BITPOS 0x00
+#define CS_HSMCLK_DIV_BITPOS 0x08
+
+/* Number of positions to shift for source calculation */
+#define CS_ACLK_SRC_BITPOS 0x08
+#define CS_MCLK_SRC_BITPOS 0x00
+#define CS_SMCLK_SRC_BITPOS 0x04
+#define CS_HSMCLK_SRC_BITPOS 0x04
+
+/* REFO Clock Values */
+#define CS_REFO_32KHZ 0x00
+#define CS_REFO_128KHZ 0x01
+
+/* Frequency Values */
+#define CS_VLOCLK_FREQUENCY 10000
+#define CS_MODCLK_FREQUENCY 24000000
+
+/* Interrupts */
+#define CS_LFXT_FAULT   LFXTIE
+#define CS_HFXT_FAULT   HFXTIE
+#define CS_DCOMIN_FAULT   DCOMINIE
+#define CS_DCOMAX_FAULT   DCOMAXIE
+#define CS_DCORESISTOR_FAULT   DCORIE
+#define CS_STARTCOUNT_LFXT_FAULT   FCNTLFIE
+#define CS_STARTCOUNT_HFXT_FAULT   FCNTHFIE
+#define CS_PLL_OUTOFLOCK   PLLOOLIE
+#define CS_PLL_OUTOFSIGNAL   PLLLOSIE
+#define CS_PLL_OUTOFRANGE   PLLOORIE
+#define CS_REFCNT_PERIOD_COUNTER   CALIE
+
+#define CS_HFXT_DRIVE0 CS_CTL2_HFXTDRIVE_0
+#define CS_HFXT_DRIVE1 CS_CTL2_HFXTDRIVE_1
+#define CS_HFXT_BYPASS CS_CTL2_HFXTBYPASS
+
+#define CS_LFXT_DRIVE0 LFXTDRIVE_0
+#define CS_LFXT_DRIVE1 LFXTDRIVE_1
+#define CS_LFXT_DRIVE2 LFXTDRIVE_2
+#define CS_LFXT_DRIVE3 LFXTDRIVE_3
+#define CS_LFXT_BYPASS LFXTBYPASS
+
+#define CS_ACLK ACLK_EN
+#define CS_MCLK MCLK_EN
+#define CS_SMCLK SMCLK_EN
+#define CS_HSMCLK HSMCLK_EN
+#define CS_BCLK BCLK_READY
+
+#define CS_LFXTCLK  0x01
+
+#define CS_1MHZ 1000000
+#define CS_15MHZ 1500000
+#define CS_3MHZ 3000000
+#define CS_4MHZ 4000000
+#define CS_6MHZ 6000000
+#define CS_8MHZ 8000000
+#define CS_12MHZ 12000000
+#define CS_16MHZ 16000000
+#define CS_24MHZ 24000000
+#define CS_32MHZ 32000000
+#define CS_40MHZ 40000000
+#define CS_48MHZ 48000000
+
+#define CS_DCO_FREQUENCY_1_5 DCORSEL_0
+#define CS_DCO_FREQUENCY_3 DCORSEL_1
+#define CS_DCO_FREQUENCY_6 DCORSEL_2
+#define CS_DCO_FREQUENCY_12 DCORSEL_3
+#define CS_DCO_FREQUENCY_24 DCORSEL_4
+#define CS_DCO_FREQUENCY_48 DCORSEL_5
+
+#define CS_HFXT_FAULT_COUNTER 0x01
+#define CS_LFXT_FAULT_COUNTER 0x02
+
+#define CS_FAULT_COUNTER_4096_CYCLES FCNTLF_0
+#define CS_FAULT_COUNTER_8192_CYCLES FCNTLF_1
+#define CS_FAULT_COUNTER_16384_CYCLES FCNTLF_2
+#define CS_FAULT_COUNTER_32768_CYCLES FCNTLF_3
+
+//******************************************************************************
+//
+//! This function sets the external clock sources LFXT and HFXT crystal
+//! oscillator frequency values. This function must be called if an external
+//! crystal LFXT or HFXT is used and the user intends to call
+//! CS_getSMCLK, CS_getMCLK, CS_getBCLK,  CS_getHSMCLK, CS_getACLK and
+//! any of the HFXT oscillator control functions
+//!
+//! \param lfxt_XT_CLK_frequency is the LFXT crystal frequencies in Hz
+//! \param hfxt_XT_CLK_frequency is the HFXT crystal frequencies in Hz
+//!
+//! \return None
+//
+//******************************************************************************
+extern void CS_setExternalClockSourceFrequency(uint32_t lfxt_XT_CLK_frequency,
+        uint32_t hfxt_XT_CLK_frequency);
+
+//******************************************************************************
+//
+//! This function initializes each of the clock signals. The user must ensure
+//! that this function is called for each clock signal. If not, the default
+//! state is assumed for the particular clock signal. Refer to DriverLib
+//! documentation for CS module or Device Family User's Guide for details of
+//! default clock signal states. 
+//!
+//! Note that this function is blocking and will wait on the appropriate bit
+//! to be set in the CSSTAT READY register to be set before setting the clock
+//! source
+//!
+//! HFXTCLK is not available for BCLK or ACLK.
+//!
+//! \param selectedClockSignal Clock signal to initialize.
+//!           - \b CS_ACLK,
+//!           - \b CS_MCLK,
+//!           - \b CS_HSMCLK
+//!           - \b CS_SMCLK
+//!           - \b CS_BCLK  [clockSourceDivider is ignored for this parameter]
+//! \param clockSource  Clock source for the selectedClockSignal signal.
+//!            - \b CS_LFXTCLK_SELECT,
+//!            - \b CS_HFXTCLK_SELECT,
+//!            - \b CS_VLOCLK_SELECT,     [Not available for BCLK]
+//!            - \b CS_DCOCLK_SELECT,     [Not available for ACLK, BCLK]
+//!            - \b CS_REFOCLK_SELECT,
+//!            - \b CS_MODOSC_SELECT      [Not available for ACLK, BCLK]
+//! \param clockSourceDivider - selected the clock divider to calculate
+//!         clock signal from clock source. This parameter is ignored when
+//!         setting BLCK. Valid values are:
+//!           - \b CS_CLOCK_DIVIDER_1,
+//!           - \b CS_CLOCK_DIVIDER_2,
+//!           - \b CS_CLOCK_DIVIDER_4,
+//!           - \b CS_CLOCK_DIVIDER_8,
+//!           - \b CS_CLOCK_DIVIDER_16,
+//!           - \b CS_CLOCK_DIVIDER_32,
+//!           - \b CS_CLOCK_DIVIDER_64,
+//!           - \b CS_CLOCK_DIVIDER_128
+//!
+//! \return NONE
+//
+//******************************************************************************
+extern void CS_initClockSignal(uint32_t selectedClockSignal,
+        uint32_t clockSource, uint32_t clockSourceDivider);
+
+//******************************************************************************
+//
+//! Initializes the HFXT crystal oscillator, which supports crystal frequencies
+//! between 0 MHz and 48 MHz, depending on the selected drive strength. Loops
+//! until all oscillator fault flags are cleared, with no timeout. See the
+//! device-specific data sheet for appropriate drive settings. NOTE: User must
+//! call CS_setExternalClockSourceFrequency to set frequency of external clocks
+//! before calling this function.
+//!
+//! \param bypassMode When this variable is set, the oscillator will start
+//! in bypass mode and the signal can be generated by a digital square wave.
+//!
+//!
+//! \return NONE
+//
+//******************************************************************************
+extern void CS_startHFXT(bool bypassMode);
+
+//******************************************************************************
+//
+//! Initializes the HFXT crystal oscillator, which supports crystal frequencies
+//! between 0 MHz and 48 MHz, depending on the selected drive strength. Loops
+//! until all oscillator fault flags are cleared, with no timeout. See the
+//! device-specific data sheet for appropriate drive settings. NOTE: User must
+//! call CS_setExternalClockSourceFrequency to set frequency of external clocks
+//! before calling this function. This function has a timeout associated with
+//! stabilizing the oscillator.
+//!
+//! \param bypassMode When this variable is set, the oscillator will start
+//! in bypass mode and the signal can be generated by a digital square wave.
+//!
+//! \param timeout is the count value that gets decremented every time the loop
+//!         that clears oscillator fault flags gets executed.
+//!
+//! \return NONE
+//
+//******************************************************************************
+extern void CS_startHFXTWithTimeout(bool bypassMode, uint32_t timeout);
+
+//******************************************************************************
+//
+//! Initializes the LFXT crystal oscillator, which supports crystal frequencies
+//! up to 50kHz, depending on the selected drive strength. Loops
+//! until all oscillator fault flags are cleared, with no timeout. See the
+//! device-specific data sheet for appropriate drive settings. NOTE: User must
+//! call CS_setExternalClockSourceFrequency to set frequency of external clocks
+//! before calling this function.
+//!
+//! \param xtDrive is the target drive strength for the LFXT crystal
+//!                  oscillator.
+//!      Valid values are:
+//!         - \b CS_LFXT_DRIVE0,
+//!         - \b CS_LFXT_DRIVE1,
+//!         - \b CS_LFXT_DRIVE2,
+//!         - \b CS_LFXT_DRIVE3,  [Default Value]
+//!         - \b CS_LFXT_BYPASS
+//!
+//! \note When CS_LFXT_BYPASS is passed as a parameter the oscillator will start
+//! in bypass mode and the signal can be generated by a digital square wave.
+//!
+//!
+//! \return NONE
+//
+//******************************************************************************
+extern void CS_startLFXT(uint32_t xtDrive);
+
+//******************************************************************************
+//
+//! Initializes the LFXT crystal oscillator, which supports crystal frequencies
+//! up to 50kHz, depending on the selected drive strength. Loops
+//! until all oscillator fault flags are cleared. See the
+//! device-specific data sheet for appropriate drive settings. NOTE: User must
+//! call CS_setExternalClockSourceFrequency to set frequency of external clocks
+//! before calling this function. This function has a timeout associated with
+//! stabilizing the oscillator.
+//!
+//! \param xtDrive is the target drive strength for the LFXT crystal
+//!                  oscillator.
+//!      Valid values are:
+//!         - \b CS_LFXT_DRIVE0,
+//!         - \b CS_LFXT_DRIVE1,
+//!         - \b CS_LFXT_DRIVE2,
+//!         - \b CS_LFXT_DRIVE3,  [Default Value]
+//!         - \b CS_LFXT_BYPASS
+//!
+//! \note When CS_LFXT_BYPASS is passed as a parameter the oscillator will
+//! start in bypass mode and the signal can be generated by a digital square
+//! wave.
+//!
+//! \param timeout is the count value that gets decremented every time the loop
+//!         that clears oscillator fault flags gets executed.
+//!
+//! \return NONE
+//
+//******************************************************************************
+extern void CS_startLFXTWithTimeout(uint32_t xtDrive, uint32_t timeout);
+
+//******************************************************************************
+//
+//! Selects between the frequency of the internal REFO clock source
+//!
+//! \param referenceFrequency selects between the valid frequencies:
+//!        - \b CS_REFO_32KHZ,
+//!        - \b CS_REFO_128KHZ,
+//!
+//! \return NONE
+//
+//******************************************************************************
+extern void CS_setReferenceOscillatorFrequency(uint8_t referenceFrequency);
+
+//******************************************************************************
+//
+//! Enables conditional module requests
+//!
+//! \param selectClock selects specific request enables. Valid values are
+//!        are a logical OR of the following values:
+//!        - \b CS_ACLK,
+//!        - \b CS_HSMCLK,
+//!        - \b CS_SMCLK,
+//!        - \b CS_MCLK
+//!
+//! \return NONE
+//
+//******************************************************************************
+extern void CS_enableClockRequest(uint32_t selectClock);
+
+//******************************************************************************
+//
+//! Disables conditional module requests
+//!
+//! \param selectClock selects specific request disables. Valid values are
+//!        are a logical OR of the following values:
+//!        - \b CS_ACLK,
+//!        - \b CS_HSMCLK,
+//!        - \b CS_SMCLK,
+//!        - \b CS_MCLK
+//!
+//! \return NONE
+//
+//******************************************************************************
+extern void CS_disableClockRequest(uint32_t selectClock);
+
+//******************************************************************************
+//
+//! Get the current ACLK frequency.
+//!
+//! If a oscillator fault is set, the frequency returned will be based on the
+//! fail safe mechanism of CS module. The user of this API must ensure that
+//! \link CS_setExternalClockSourceFrequency() \endlink API was invoked before
+//! in case LFXT is being used.
+//!
+//! \return Current ACLK frequency in Hz
+//
+//******************************************************************************
+extern uint32_t CS_getACLK(void);
+
+//******************************************************************************
+//
+//! Get the current SMCLK frequency.
+//!
+//! If a oscillator fault is set, the frequency returned will be based on the
+//! fail safe mechanism of CS module. The user of this API must ensure that
+//! CS_setExternalClockSourceFrequency API was invoked before in case LFXT or
+//! HFXT is being used.
+//!
+//! \return Current SMCLK frequency in Hz
+//
+//******************************************************************************
+extern uint32_t CS_getSMCLK(void);
+
+//******************************************************************************
+//
+//! Get the current MCLK frequency.
+//!
+//! If a oscillator fault is set, the frequency returned will be based on the
+//! fail safe mechanism of CS module. The user of this API must ensure that
+//! CS_setExternalClockSourceFrequency API was invoked before in case LFXT or
+//! HFXT is being used.
+//!
+//! \return Current MCLK frequency in Hz
+//
+//******************************************************************************
+extern uint32_t CS_getMCLK(void);
+
+//******************************************************************************
+//
+//! Get the current BCLK frequency.
+//!
+//! If a oscillator fault is set, the frequency returned will be based on the
+//! fail safe mechanism of CS module. The user of this API must ensure that
+//! \link CS_setExternalClockSourceFrequency \endlink API was invoked before in
+//! case LFXT or HFXT is being used.
+//!
+//! \return Current BCLK frequency in Hz
+//
+//******************************************************************************
+extern uint32_t CS_getBCLK(void);
+
+//******************************************************************************
+//
+//! Get the current HSMCLK frequency.
+//!
+//! If a oscillator fault is set, the frequency returned will be based on the
+//! fail safe mechanism of CS module. The user of this API must ensure that
+//! \link CS_setExternalClockSourceFrequency \endlink API was invoked before in
+//! case LFXT or HFXT is being used.
+//!
+//! \return Current HSMCLK frequency in Hz
+//
+//******************************************************************************
+extern uint32_t CS_getHSMCLK(void);
+
+//******************************************************************************
+//
+//! Sets the centered frequency of DCO operation.  Each frequency represents
+//! the centred frequency of a particular frequency range. Further tuning can
+//! be achieved by using the CS_tuneDCOFrequency function. Note that setting
+//! the nominal frequency will reset the tuning parameters.
+//!
+//! \param dcoFreq selects between the valid frequencies:
+//!        - \b CS_DCO_FREQUENCY_1_5, [1MHz to 2MHz]
+//!        - \b CS_DCO_FREQUENCY_3,   [2MHz to 4MHz]
+//!        - \b CS_DCO_FREQUENCY_6,   [4MHz to 8MHz]
+//!        - \b CS_DCO_FREQUENCY_12,  [8MHz to 16MHz]
+//!        - \b CS_DCO_FREQUENCY_24,  [16MHz to 32MHz]
+//!        - \b CS_DCO_FREQUENCY_48   [32MHz to 64MHz]
+//!
+//! \return NONE
+//
+//******************************************************************************
+extern void CS_setDCOCenteredFrequency(uint32_t dcoFreq);
+
+//******************************************************************************
+//
+//! Automatically sets/tunes the DCO to the given frequency. Any valid value
+//! up to max frequency in the spec can be given to this function and the API
+//! will do its best to determine the correct tuning parameter.
+//!
+//! \note The frequency ranges that can be custom tuned on early release MSP432
+//! devices is limited. For further details on supported tunable frequencies,
+//! please refer to the device errata sheet or data sheet.
+//!
+//! \param dcoFrequency Frequency in Hz that the user wants to set the DCO to.
+//!
+//! \note This function uses floating point math to calculate the DCO tuning
+//!         parameter. If efficiency is a concern, the user should use the
+//!         \link FPU_enableModule \endlink function (if available) to enable
+//!         the floating point co-processor.
+//!
+//! \return None
+//
+//******************************************************************************
+extern void CS_setDCOFrequency(uint32_t dcoFrequency);
+
+//******************************************************************************
+//
+//! Tunes the DCO to a specific frequency. Tuning of the DCO is based off of the
+//! following equation in the user's guide:
+//!
+//! See the user's guide for more detailed information about DCO tuning.
+//!
+//! \note This function is not currently available on pre-release MSP432 devices.
+//!  On early release versions of MSP432, the DCO calibration information has not been
+//!  populated making the DCO only able to operate at the pre-calibrated centered 
+//!  frequencies accessible by the \link CS_setDCOCenteredFrequency \endlink
+//!  function. While this function will be added on the final devices being released,
+//!  for early silicon please default to the pre-calibrated DCO center frequencies.
+//!
+//! \param tuneParameter Tuning parameter in 2's Compliment representation.
+//!  Can be negative or positive.
+//!
+//! \return NONE
+//
+//******************************************************************************
+extern void CS_tuneDCOFrequency(int16_t tuneParameter);
+
+//******************************************************************************
+//
+//! Enables the external resistor for DCO operation
+//!
+//! \return NONE
+//
+//******************************************************************************
+extern void CS_enableDCOExternalResistor(void);
+
+//******************************************************************************
+//
+//! Disables the external resistor for DCO operation
+//!
+//! \return NONE
+//
+//******************************************************************************
+extern void CS_disableDCOExternalResistor(void);
+
+//******************************************************************************
+//
+//! Sets the calibration value for the DCO when using the external resistor
+//! mode. This value is used for tuning the DCO to custom frequencies. By
+//! default, the value in the CS module is populated by the calibration
+//! data of the suggested external resistor (see device datasheet).
+//!
+//! \param uiCalData is the calibration data constant for the external resistor.
+//!
+//! \return None
+//
+//******************************************************************************
+extern void CS_setDCOExternalResistorCalibration(uint_fast8_t uiCalData);
+
+//******************************************************************************
+//
+//! Gets the current tuned DCO frequency. If no tuning has been done, this
+//! returns the nominal DCO frequency of the current DCO range. Note that this
+//! function will grab any constant/calibration data from the DDDS table
+//! without any user interaction needed.
+//!
+//! \note This function uses floating point math to calculate the DCO tuning
+//!         parameter. If efficiency is a concern, the user should use the
+//!         \link FPU_enableModule \endlink function (if available) to enable
+//!         the floating point co-processor.
+//!
+//! \return Current DCO frequency in Hz
+//
+//******************************************************************************
+extern uint32_t CS_getDCOFrequency(void);
+
+//******************************************************************************
+//
+//! Automatically sets/tunes the DCO to the given frequency. Any valid value
+//! up to (and including) 64Mhz can be given to this function and the API
+//! will do its best to determine the correct tuning parameter.
+//!
+//!
+//! \note This function is not currently available on pre-release MSP432 devices.
+//!  On early release versions of MSP432, the DCO calibration information has not been
+//!  populated making the DCO only able to operate at the pre-calibrated centered 
+//!  frequencies accessible by the \link CS_setDCOCenteredFrequency \endlink
+//!  function. While this function will be added on the final devices being released,
+//!  for early silicon please default to the pre-calibrated DCO center frequencies.
+//!
+//! \param dcoFrequency Frequency in Hz (1500000 - 64000000) that the user wants
+//!         to set the DCO to.
+//!
+//! \note This function uses floating point math to calculate the DCO tuning
+//!         parameter. If efficiency is a concern, the user should use the
+//!         \link FPU_enableModule \endlink function (if available) to enable
+//!         the floating point co-processor.
+//!
+//! \return None
+//
+//******************************************************************************
+extern void CS_setDCOFrequency(uint32_t dcoFrequency);
+
+//******************************************************************************
+//
+//! Enables the fault counter for the CS module. This function can enable
+//! either the HFXT fault counter or the LFXT fault counter.
+//!
+//! \param counterSelect selects the fault counter to enable
+//!        - \b CS_HFXT_FAULT_COUNTER
+//!        - \b CS_LFXT_FAULT_COUNTER
+//!
+//! \return NONE
+//
+//******************************************************************************
+extern void CS_enableFaultCounter(uint_fast8_t counterSelect);
+
+//******************************************************************************
+//
+//! Disables the fault counter for the CS module. This function can disable
+//! either the HFXT fault counter or the LFXT fault counter.
+//!
+//! \param counterSelect selects the fault counter to disable
+//!        - \b CS_HFXT_FAULT_COUNTER
+//!        - \b CS_LFXT_FAULT_COUNTER
+//!
+//! \return NONE
+//
+//******************************************************************************
+extern void CS_disableFaultCounter(uint_fast8_t counterSelect);
+
+//******************************************************************************
+//
+//! Resets the fault counter for the CS module. This function can reset
+//! either the HFXT fault counter or the LFXT fault counter.
+//!
+//! \param counterSelect selects the fault counter to reset
+//!        - \b CS_HFXT_FAULT_COUNTER
+//!        - \b CS_LFXT_FAULT_COUNTER
+//!
+//! \return NONE
+//
+//******************************************************************************
+extern void CS_resetFaultCounter(uint_fast8_t counterSelect);
+
+//******************************************************************************
+//
+//! Sets the count for the start value of the fault counter. This function can
+//! be used to set either the HFXT count or the LFXT count.
+//!
+//! \param counterSelect selects the fault counter to reset
+//!        - \b CS_HFXT_FAULT_COUNTER
+//!        - \b CS_LFXT_FAULT_COUNTER
+//! \param countValue selects the cycles to set the fault counter to
+//!        - \b CS_FAULT_COUNTER_4096_CYCLES
+//!        - \b CS_FAULT_COUNTER_8192_CYCLES
+//!        - \b CS_FAULT_COUNTER_16384_CYCLES
+//!        - \b CS_FAULT_COUNTER_32768_CYCLES
+//!
+//! \return NONE
+//
+//******************************************************************************
+extern void CS_startFaultCounter(uint_fast8_t counterSelect,
+        uint_fast8_t countValue);
+
+//*****************************************************************************
+//
+//! Enables individual clock control interrupt sources.
+//!
+//! \param flags is a bit mask of the interrupt sources to be enabled.  Must
+//! be a logical OR of:
+//!                     - \b CS_LFXT_FAULT,
+//!                     - \b CS_HFXT_FAULT,
+//!                     - \b CS_DCOMIN_FAULT,
+//!                     - \b CS_DCOMAX_FAULT,
+//!                     - \b CS_DCORESISTOR_FAULT,
+//!                     - \b CS_STARTCOUNT_LFXT_FAULT,
+//!                     - \b CS_STARTCOUNT_HFXT_FAULT,
+//!                     - \b CS_PLL_OUTOFLOCK,
+//!                     - \b CS_PLL_OUTOFSIGNAL,
+//!                     - \b CS_PLL_OUTOFRANGE,
+//!                     - \b CS_REFCNT_PERIOD_COUNTER
+//!
+//! This function enables the indicated clock system interrupt sources.  Only
+//! the sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! \note The interrupt sources vary based on the part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void CS_enableInterrupt(uint32_t flags);
+
+//*****************************************************************************
+//
+//! Disables individual clock system interrupt sources.
+//!
+//! \param flags is a bit mask of the interrupt sources to be disabled.  Must
+//! be a logical OR of:
+//!                     - \b CS_LFXT_FAULT,
+//!                     - \b CS_HFXT_FAULT,
+//!                     - \b CS_DCOMIN_FAULT,
+//!                     - \b CS_DCOMAX_FAULT,
+//!                     - \b CS_DCORESISTOR_FAULT,
+//!                     - \b CS_STARTCOUNT_LFXT_FAULT,
+//!                     - \b CS_STARTCOUNT_HFXT_FAULT,
+//!                     - \b CS_PLL_OUTOFLOCK,
+//!                     - \b CS_PLL_OUTOFSIGNAL,
+//!                     - \b CS_PLL_OUTOFRANGE,
+//!                     - \b CS_REFCNT_PERIOD_COUNTER
+//!
+//! \note The interrupt sources vary based on the part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void CS_disableInterrupt(uint32_t flags);
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status masked with the enabled interrupts.
+//! This function is useful to call in ISRs to get a list of pending interrupts
+//! that are actually enabled and could have caused the ISR.
+//!
+//! \return The current interrupt status, enumerated as a bit field of
+//!                     - \b CS_LFXT_FAULT,
+//!                     - \b CS_HFXT_FAULT,
+//!                     - \b CS_DCOMIN_FAULT,
+//!                     - \b CS_DCOMAX_FAULT,
+//!                     - \b CS_DCORESISTOR_FAULT,
+//!                     - \b CS_STARTCOUNT_LFXT_FAULT,
+//!                     - \b CS_STARTCOUNT_HFXT_FAULT,
+//!                     - \b CS_PLL_OUTOFLOCK,
+//!                     - \b CS_PLL_OUTOFSIGNAL,
+//!                     - \b CS_PLL_OUTOFRANGE,
+//!                     - \b CS_REFCNT_PERIOD_COUNTER
+//!
+//! \note The interrupt sources vary based on the part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//
+//*****************************************************************************
+extern uint32_t CS_getEnabledInterruptStatus(void);
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \return The current interrupt status, enumerated as a bit field of:
+//!                     - \b CS_LFXT_FAULT,
+//!                     - \b CS_HFXT_FAULT,
+//!                     - \b CS_DCOMIN_FAULT,
+//!                     - \b CS_DCOMAX_FAULT,
+//!                     - \b CS_DCORESISTOR_FAULT,
+//!                     - \b CS_STARTCOUNT_LFXT_FAULT,
+//!                     - \b CS_STARTCOUNT_HFXT_FAULT,
+//!                     - \b CS_PLL_OUTOFLOCK,
+//!                     - \b CS_PLL_OUTOFSIGNAL,
+//!                     - \b CS_PLL_OUTOFRANGE,
+//!                     - \b CS_REFCNT_PERIOD_COUNTER
+//!
+//! \note The interrupt sources vary based on the part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//
+//*****************************************************************************
+extern uint32_t CS_getInterruptStatus(void);
+
+//*****************************************************************************
+//
+//! Clears clock system interrupt sources.
+//!
+//! \param flags is a bit mask of the interrupt sources to be cleared.  Must
+//! be a logical OR of:
+//!                     - \b CS_LFXT_FAULT,
+//!                     - \b CS_HFXT_FAULT,
+//!                     - \b CS_DCOMIN_FAULT,
+//!                     - \b CS_DCOMAX_FAULT,
+//!                     - \b CS_DCORESISTOR_FAULT,
+//!                     - \b CS_STARTCOUNT_LFXT_FAULT,
+//!                     - \b CS_STARTCOUNT_HFXT_FAULT,
+//!                     - \b CS_PLL_OUTOFLOCK,
+//!                     - \b CS_PLL_OUTOFSIGNAL,
+//!                     - \b CS_PLL_OUTOFRANGE,
+//!                     - \b CS_REFCNT_PERIOD_COUNTER
+//!
+//! The specified clock system interrupt sources are cleared, so that they no
+//! longer assert.  This function must be called in the interrupt handler to
+//! keep it from being called again immediately upon exit.
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared.  Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \note The interrupt sources vary based on the part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void CS_clearInterruptFlag(uint32_t flags);
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the clock system interrupt.
+//!
+//! \param intHandler is a pointer to the function to be called when the clock
+//! system interrupt occurs.
+//!
+//! This function registers the handler to be called when a clock system
+//! interrupt occurs. This function enables the global interrupt in the
+//! interrupt controller; specific clock system interrupts must be enabled
+//! via CS_enableInterrupt().  It is the interrupt handler's responsibility to
+//! clear the interrupt source via CS_clearInterruptFlag().
+//!
+//! Clock System can generate interrupts when
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void CS_registerInterrupt(void (*intHandler)(void));
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the clock system.
+//!
+//! This function unregisters the handler to be called when a clock system
+//! interrupt occurs.  This function also masks off the interrupt in the
+//! interrupt controller so that the interrupt handler no longer is called.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void CS_unregisterInterrupt(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/debug.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/debug.h
new file mode 100644
index 000000000..65c566e93
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/debug.h
@@ -0,0 +1,76 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __DEBUG_H__
+#define __DEBUG_H__
+
+//*****************************************************************************
+//
+// Prototype for the function that is called when an invalid argument is passed
+// to an API.  This is only used when doing a DEBUG build.
+//
+//*****************************************************************************
+extern void __error__(char *pcFilename, unsigned long line);
+
+//*****************************************************************************
+//
+// The ASSERT macro, which does the actual assertion checking.  Typically, this
+// will be for procedure arguments.
+//
+//*****************************************************************************
+#ifdef DEBUG
+#define ASSERT(expr) {                                      \
+                         if(!(expr))                        \
+                         {                                  \
+                             __error__(__FILE__, __LINE__); \
+                         }                                  \
+                     }
+#else
+#define ASSERT(expr)
+#endif
+
+#ifdef DEBUG
+#define assert(expr) {                                      \
+                         if(!(expr))                        \
+                         {                                  \
+                             __error__(__FILE__, __LINE__); \
+                         }                                  \
+                     }
+#else
+#define assert(expr)
+#endif
+
+#endif // __DEBUG_H__
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/dma.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/dma.c
new file mode 100644
index 000000000..deada5486
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/dma.c
@@ -0,0 +1,850 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#include <stdint.h>
+
+#include <debug.h>
+#include <interrupt.h>
+#include <dma.h>
+
+void DMA_enableModule(void)
+{
+    //
+    // Set the master enable bit in the config register.
+    //
+    DMA->rCFG.r = DMA_CFG_;
+}
+
+void DMA_disableModule(void)
+{
+    //
+    // Clear the master enable bit in the config register.
+    //
+    DMA->rCFG.r = 0;
+}
+
+uint32_t DMA_getErrorStatus(void)
+{
+    //
+    // Return the DMA error status.
+    //
+    return DMA->rERRCLR.r;
+}
+
+void DMA_clearErrorStatus(void)
+{
+    //
+    // Clear the DMA error interrupt.
+    //
+    DMA->rERRCLR.r = 1;
+}
+
+void DMA_enableChannel(uint32_t channelNum)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((channelNum & 0xffff) < 8);
+
+    //
+    // Set the bit for this channel in the enable set register.
+    //
+    DMA->rENASET = 1 << (channelNum & 0x0F);
+}
+
+void DMA_disableChannel(uint32_t channelNum)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((channelNum & 0xffff) < 8);
+
+    //
+    // Set the bit for this channel in the enable clear register.
+    //
+    DMA->rENACLR = 1 << (channelNum & 0x0F);
+}
+
+bool DMA_isChannelEnabled(uint32_t channelNum)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((channelNum & 0xffff) < 8);
+
+    //
+    // AND the specified channel bit with the enable register and return the
+    // result.
+    //
+    return ((DMA->rENASET & (1 << (channelNum & 0x0F))) ? true : false);
+}
+
+void DMA_setControlBase(void *controlTable)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(((uint32_t) controlTable & ~0x3FF) == (uint32_t) controlTable);
+    ASSERT((uint32_t) controlTable >= 0x20000000);
+
+    //
+    // Program the base address into the register.
+    //
+    DMA->rCTLBASE.r = (uint32_t) controlTable;
+}
+
+void* DMA_getControlBase(void)
+{
+    //
+    // Read the current value of the control base register and return it to
+    // the caller.
+    //
+    return ((void *) DMA->rCTLBASE.r);
+}
+
+void* DMA_getControlAlternateBase(void)
+{
+    //
+    // Read the current value of the control base register and return it to
+    // the caller.
+    //
+    return ((void *) DMA->rATLBASE);
+}
+
+void DMA_requestChannel(uint32_t channelNum)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((channelNum & 0xffff) < 8);
+
+    //
+    // Set the bit for this channel in the software DMA request register.
+    //
+    DMA->rSWREQ = 1 << (channelNum & 0x0F);
+}
+
+void DMA_enableChannelAttribute(uint32_t channelNum, uint32_t attr)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((channelNum & 0xffff) < 8);
+    ASSERT(
+            (attr
+                    & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT
+                            | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK))
+            == 0);
+
+    //
+    // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
+    // passed as the channelNum parameter, extract just the channel number
+    // from this parameter.
+    //
+    channelNum &= 0x0F;
+
+    //
+    // Set the useburst bit for this channel if set in config.
+    //
+    if (attr & UDMA_ATTR_USEBURST)
+    {
+        DMA->rUSEBURSTSET = 1 << channelNum;
+    }
+
+    //
+    // Set the alternate control select bit for this channel,
+    // if set in config.
+    //
+    if (attr & UDMA_ATTR_ALTSELECT)
+    {
+        DMA->rALTSET = 1 << channelNum;
+    }
+
+    //
+    // Set the high priority bit for this channel, if set in config.
+    //
+    if (attr & UDMA_ATTR_HIGH_PRIORITY)
+    {
+        DMA->rPRIOSET = 1 << channelNum;
+    }
+
+    //
+    // Set the request mask bit for this channel, if set in config.
+    //
+    if (attr & UDMA_ATTR_REQMASK)
+    {
+        DMA->rREQMASKSET = 1 << channelNum;
+    }
+}
+
+void DMA_disableChannelAttribute(uint32_t channelNum, uint32_t attr)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((channelNum & 0xffff) < 8);
+    ASSERT(
+            (attr
+                    & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT
+                            | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK))
+            == 0);
+
+    //
+    // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
+    // passed as the channelNum parameter, extract just the channel number
+    // from this parameter.
+    //
+    channelNum &= 0x0F;
+
+    //
+    // Clear the useburst bit for this channel if set in config.
+    //
+    if (attr & UDMA_ATTR_USEBURST)
+    {
+        DMA->rUSEBURSTCLR = 1 << channelNum;
+    }
+
+    //
+    // Clear the alternate control select bit for this channel, if set in
+    // config.
+    //
+    if (attr & UDMA_ATTR_ALTSELECT)
+    {
+        DMA->rALTCLR = 1 << channelNum;
+    }
+
+    //
+    // Clear the high priority bit for this channel, if set in config.
+    //
+    if (attr & UDMA_ATTR_HIGH_PRIORITY)
+    {
+        DMA->rPRIOCLR = 1 << channelNum;
+    }
+
+    //
+    // Clear the request mask bit for this channel, if set in config.
+    //
+    if (attr & UDMA_ATTR_REQMASK)
+    {
+        DMA->rREQMASKCLR = 1 << channelNum;
+    }
+}
+
+uint32_t DMA_getChannelAttribute(uint32_t channelNum)
+{
+    uint32_t attr = 0;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((channelNum & 0xffff) < 8);
+
+    //
+    // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
+    // passed as the channelNum parameter, extract just the channel number
+    // from this parameter.
+    //
+    channelNum &= 0x0F;
+
+    //
+    // Check to see if useburst bit is set for this channel.
+    //
+    if (DMA->rUSEBURSTSET & (1 << channelNum))
+    {
+        attr |= UDMA_ATTR_USEBURST;
+    }
+
+    //
+    // Check to see if the alternate control bit is set for this channel.
+    //
+    if (DMA->rALTSET & (1 << channelNum))
+    {
+        attr |= UDMA_ATTR_ALTSELECT;
+    }
+
+    //
+    // Check to see if the high priority bit is set for this channel.
+    //
+    if (DMA->rPRIOSET & (1 << channelNum))
+    {
+        attr |= UDMA_ATTR_HIGH_PRIORITY;
+    }
+
+    //
+    // Check to see if the request mask bit is set for this channel.
+    //
+    if (DMA->rREQMASKSET & (1 << channelNum))
+    {
+        attr |= UDMA_ATTR_REQMASK;
+    }
+
+    //
+    // Return the configuration flags.
+    //
+    return (attr);
+}
+
+void DMA_setChannelControl(uint32_t channelStructIndex, uint32_t control)
+{
+    DMA_ControlTable *pCtl;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((channelStructIndex & 0xffff) < 64);
+    ASSERT(DMA->rCTLBASE != 0);
+
+    //
+    // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
+    // passed as the channelStructIndex parameter, extract just the channel
+    // index from this parameter.
+    //
+    channelStructIndex &= 0x3f;
+
+    //
+    // Get the base address of the control table.
+    //
+    pCtl = (DMA_ControlTable *) DMA->rCTLBASE.r;
+
+    //
+    // Get the current control word value and mask off the fields to be
+    // changed, then OR in the new settings.
+    //
+    pCtl[channelStructIndex].control = ((pCtl[channelStructIndex].control
+            & ~(UDMA_CHCTL_DSTINC_M | UDMA_CHCTL_DSTSIZE_M | UDMA_CHCTL_SRCINC_M
+                    | UDMA_CHCTL_SRCSIZE_M | UDMA_CHCTL_ARBSIZE_M
+                    | UDMA_CHCTL_NXTUSEBURST)) | control);
+}
+
+void DMA_setChannelTransfer(uint32_t channelStructIndex, uint32_t mode,
+        void *srcAddr, void *dstAddr, uint32_t transferSize)
+{
+    DMA_ControlTable *controlTable;
+    uint32_t control;
+    uint32_t increment;
+    uint32_t bufferBytes;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((channelStructIndex & 0xffff) < 64);
+    ASSERT(DMA->rCTLBASE != 0);
+    ASSERT(mode <= UDMA_MODE_PER_SCATTER_GATHER);
+    ASSERT((transferSize != 0) && (transferSize <= 1024));
+
+    //
+    // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
+    // passed as the channelStructIndex parameter, extract just the channel
+    // index from this parameter.
+    //
+    channelStructIndex &= 0x3f;
+
+    //
+    // Get the base address of the control table.
+    //
+    controlTable = (DMA_ControlTable *) DMA->rCTLBASE.r;
+
+    //
+    // Get the current control word value and mask off the mode and size
+    // fields.
+    //
+    control = (controlTable[channelStructIndex].control
+            & ~(UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M));
+
+    //
+    // Adjust the mode if the alt control structure is selected.
+    //
+    if (channelStructIndex & UDMA_ALT_SELECT)
+    {
+        if ((mode == UDMA_MODE_MEM_SCATTER_GATHER)
+                || (mode == UDMA_MODE_PER_SCATTER_GATHER))
+        {
+            mode |= UDMA_MODE_ALT_SELECT;
+        }
+    }
+
+    //
+    // Set the transfer size and mode in the control word (but don't write the
+    // control word yet as it could kick off a transfer).
+    //
+    control |= mode | ((transferSize - 1) << 4);
+
+    //
+    // Get the address increment value for the source, from the control word.
+    //
+    increment = (control & UDMA_CHCTL_SRCINC_M);
+
+    //
+    // Compute the ending source address of the transfer.  If the source
+    // increment is set to none, then the ending address is the same as the
+    // beginning.
+    //
+    if (increment != UDMA_SRC_INC_NONE)
+    {
+        increment = increment >> 26;
+        bufferBytes = transferSize << increment;
+        srcAddr = (void *) ((uint32_t) srcAddr + bufferBytes - 1);
+    }
+
+    //
+    // Load the source ending address into the control block.
+    //
+    controlTable[channelStructIndex].srcEndAddr = srcAddr;
+
+    //
+    // Get the address increment value for the destination, from the control
+    // word.
+    //
+    increment = control & UDMA_CHCTL_DSTINC_M;
+
+    //
+    // Compute the ending destination address of the transfer.  If the
+    // destination increment is set to none, then the ending address is the
+    // same as the beginning.
+    //
+    if (increment != UDMA_DST_INC_NONE)
+    {
+        //
+        // There is a special case if this is setting up a scatter-gather
+        // transfer.  The destination pointer must point to the end of
+        // the alternate structure for this channel instead of calculating
+        // the end of the buffer in the normal way.
+        //
+        if ((mode == UDMA_MODE_MEM_SCATTER_GATHER)
+                || (mode == UDMA_MODE_PER_SCATTER_GATHER))
+        {
+            dstAddr = (void *) &controlTable[channelStructIndex
+                    | UDMA_ALT_SELECT].spare;
+        }
+        //
+        // Not a scatter-gather transfer, calculate end pointer normally.
+        //
+        else
+        {
+            increment = increment >> 30;
+            bufferBytes = transferSize << increment;
+            dstAddr = (void *) ((uint32_t) dstAddr + bufferBytes - 1);
+        }
+    }
+
+    //
+    // Load the destination ending address into the control block.
+    //
+    controlTable[channelStructIndex].dstEndAddr = dstAddr;
+
+    //
+    // Write the new control word value.
+    //
+    controlTable[channelStructIndex].control = control;
+}
+
+void DMA_setChannelScatterGather(uint32_t channelNum, uint32_t taskCount,
+        void *taskList, uint32_t isPeriphSG)
+{
+    DMA_ControlTable *controlTable;
+    DMA_ControlTable *pTaskTable;
+
+    //
+    // Check the parameters
+    //
+    ASSERT((channelNum & 0xffff) < 8);
+    ASSERT(DMA->rCTLBASE != 0);
+    ASSERT(taskList != 0);
+    ASSERT(taskCount <= 1024);
+    ASSERT(taskCount != 0);
+
+    //
+    // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
+    // passed as the channelNum parameter, extract just the channel number
+    // from this parameter.
+    //
+    channelNum &= 0x0F;
+
+    //
+    // Get the base address of the control table.
+    //
+    controlTable = (DMA_ControlTable *) DMA->rCTLBASE.r;
+
+    //
+    // Get a handy pointer to the task list
+    //
+    pTaskTable = (DMA_ControlTable *) taskList;
+
+    //
+    // Compute the ending address for the source pointer.  This address is the
+    // last element of the last task in the task table
+    //
+    controlTable[channelNum].srcEndAddr = &pTaskTable[taskCount - 1].spare;
+
+    //
+    // Compute the ending address for the destination pointer.  This address
+    // is the end of the alternate structure for this channel.
+    //
+    controlTable[channelNum].dstEndAddr = &controlTable[channelNum
+            | UDMA_ALT_SELECT].spare;
+
+    //
+    // Compute the control word.  Most configurable items are fixed for
+    // scatter-gather.  Item and increment sizes are all 32-bit and arb
+    // size must be 4.  The count is the number of items in the task list
+    // times 4 (4 words per task).
+    //
+    controlTable[channelNum].control = (UDMA_CHCTL_DSTINC_32
+            | UDMA_CHCTL_DSTSIZE_32 | UDMA_CHCTL_SRCINC_32
+            | UDMA_CHCTL_SRCSIZE_32 | UDMA_CHCTL_ARBSIZE_4
+            | (((taskCount * 4) - 1) << UDMA_CHCTL_XFERSIZE_S)
+            | (isPeriphSG ?
+            UDMA_CHCTL_XFERMODE_PER_SG :
+                            UDMA_CHCTL_XFERMODE_MEM_SG));
+
+    //
+    // Scatter-gather operations can leave the alt bit set.  So if doing
+    // back to back scatter-gather transfers, the second attempt may not
+    // work correctly because the alt bit is set.  Therefore, clear the
+    // alt bit here to ensure that it is always cleared before a new SG
+    // transfer is started.
+    //
+    DMA->rALTCLR = 1 << channelNum;
+}
+
+uint32_t DMA_getChannelSize(uint32_t channelStructIndex)
+{
+    DMA_ControlTable *controlTable;
+    uint32_t control;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((channelStructIndex & 0xffff) < 16);
+    ASSERT(DMA->rCTLBASE != 0);
+
+    //
+    // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
+    // passed as the channelStructIndex parameter, extract just the channel
+    // index from this parameter.
+    //
+    channelStructIndex &= 0x3f;
+
+    //
+    // Get the base address of the control table.
+    //
+    controlTable = (DMA_ControlTable *) DMA->rCTLBASE.r;
+
+    //
+    // Get the current control word value and mask off all but the size field
+    // and the mode field.
+    //
+    control = (controlTable[channelStructIndex].control
+            & (UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M));
+
+    //
+    // If the size field and mode field are 0 then the transfer is finished
+    // and there are no more items to transfer
+    //
+    if (control == 0)
+    {
+        return (0);
+    }
+
+    //
+    // Otherwise, if either the size field or more field is non-zero, then
+    // not all the items have been transferred.
+    //
+    else
+    {
+        //
+        // Shift the size field and add one, then return to user.
+        //
+        return ((control >> 4) + 1);
+    }
+}
+
+uint32_t DMA_getChannelMode(uint32_t channelStructIndex)
+{
+    DMA_ControlTable *controlTable;
+    uint32_t control;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((channelStructIndex & 0xffff) < 64);
+    ASSERT(DMA->rCTLBASE != 0);
+
+    //
+    // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
+    // passed as the channelStructIndex parameter, extract just the channel
+    // index from this parameter.
+    //
+    channelStructIndex &= 0x3f;
+
+    //
+    // Get the base address of the control table.
+    //
+    controlTable = (DMA_ControlTable *) DMA->rCTLBASE.r;
+
+    //
+    // Get the current control word value and mask off all but the mode field.
+    //
+    control =
+            (controlTable[channelStructIndex].control & UDMA_CHCTL_XFERMODE_M);
+
+    //
+    // Check if scatter/gather mode, and if so, mask off the alt bit.
+    //
+    if (((control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_MEM_SCATTER_GATHER)
+            || ((control & ~UDMA_MODE_ALT_SELECT)
+                    == UDMA_MODE_PER_SCATTER_GATHER))
+    {
+        control &= ~UDMA_MODE_ALT_SELECT;
+    }
+
+    //
+    // Return the mode to the caller.
+    //
+    return (control);
+}
+
+void DMA_assignChannel(uint32_t mapping)
+{
+    switch (mapping)
+    {
+    case DMA_CH0_RESERVED0:
+    case DMA_CH0_EUSCIA0TX:
+    case DMA_CH0_EUSCIB0TX0:
+    case DMA_CH0_EUSCIB3TX1:
+    case DMA_CH0_EUSCIB2TX2:
+    case DMA_CH0_EUSCIB1TX3:
+    case DMA_CH0_TIMERA0CCR0:
+    case DMA_CH0_AESTRIGGER0:
+        DMA->rCH0_SRCCFG.r = (mapping >> 24) & 0x1F;
+        break;
+    case DMA_CH1_RESERVED0:
+    case DMA_CH1_EUSCIA0RX:
+    case DMA_CH1_EUSCIB0RX0:
+    case DMA_CH1_EUSCIB3RX1:
+    case DMA_CH1_EUSCIB2RX2:
+    case DMA_CH1_EUSCIB1RX3:
+    case DMA_CH1_TIMERA0CCR2:
+    case DMA_CH1_AESTRIGGER1:
+        DMA->rCH1_SRCCFG.r = (mapping >> 24) & 0x1F;
+        break;
+    case DMA_CH2_RESERVED0:
+    case DMA_CH2_EUSCIA1TX:
+    case DMA_CH2_EUSCIB1TX0:
+    case DMA_CH2_EUSCIB0TX1:
+    case DMA_CH2_EUSCIB3TX2:
+    case DMA_CH2_EUSCIB2TX3:
+    case DMA_CH2_TIMERA1CCR0:
+    case DMA_CH2_AESTRIGGER2:
+        DMA->rCH2_SRCCFG.r = (mapping >> 24) & 0x1F;
+        break;
+    case DMA_CH3_RESERVED0:
+    case DMA_CH3_EUSCIA1RX:
+    case DMA_CH3_EUSCIB1RX0:
+    case DMA_CH3_EUSCIB0RX1:
+    case DMA_CH3_EUSCIB3RX2:
+    case DMA_CH3_EUSCIB2RX3:
+    case DMA_CH3_TIMERA1CCR2:
+    case DMA_CH3_RESERVED1:
+        DMA->rCH3_SRCCFG.r = (mapping >> 24) & 0x1F;
+        break;
+    case DMA_CH4_RESERVED0:
+    case DMA_CH4_EUSCIA2TX:
+    case DMA_CH4_EUSCIB2TX0:
+    case DMA_CH4_EUSCIB1TX1:
+    case DMA_CH4_EUSCIB0TX2:
+    case DMA_CH4_EUSCIB3TX3:
+    case DMA_CH4_TIMERA2CCR0:
+    case DMA_CH4_RESERVED1:
+        DMA->rCH4_SRCCFG.r = (mapping >> 24) & 0x1F;
+        break;
+    case DMA_CH5_RESERVED0:
+    case DMA_CH5_EUSCIA2RX:
+    case DMA_CH5_EUSCIB2RX0:
+    case DMA_CH5_EUSCIB1RX1:
+    case DMA_CH5_EUSCIB0RX2:
+    case DMA_CH5_EUSCIB3RX3:
+    case DMA_CH5_TIMERA2CCR2:
+    case DMA_CH5_RESERVED1:
+        DMA->rCH5_SRCCFG.r = (mapping >> 24) & 0x1F;
+        break;
+    case DMA_CH6_RESERVED0:
+    case DMA_CH6_EUSCIA3TX:
+    case DMA_CH6_EUSCIB3TX0:
+    case DMA_CH6_EUSCIB2TX1:
+    case DMA_CH6_EUSCIB1TX2:
+    case DMA_CH6_EUSCIB0TX3:
+    case DMA_CH6_TIMERA3CCR0:
+    case DMA_CH6_EXTERNALPIN:
+        DMA->rCH6_SRCCFG.r = (mapping >> 24) & 0x1F;
+        break;
+    case DMA_CH7_RESERVED0:
+    case DMA_CH7_EUSCIA3RX:
+    case DMA_CH7_EUSCIB3RX0:
+    case DMA_CH7_EUSCIB2RX1:
+    case DMA_CH7_EUSCIB1RX2:
+    case DMA_CH7_EUSCIB0RX3:
+    case DMA_CH7_TIMERA3CCR2:
+    case DMA_CH7_ADC12C:
+        DMA->rCH7_SRCCFG.r = (mapping >> 24) & 0x1F;
+        break;
+    default:
+        ASSERT(false);
+    }
+
+}
+
+void DMA_assignInterrupt(uint32_t interruptNumber, uint32_t channel)
+{
+    ASSERT(
+            interruptNumber == DMA_INT1 || interruptNumber == DMA_INT2
+            || interruptNumber == DMA_INT3);
+
+    if (interruptNumber == DMA_INT1)
+    {
+        DMA->rINT1_SRCCFG.r = (DMA->rINT1_SRCCFG.r & ~DMA_INT1_SRCCFG_INT_SRC_M)
+                | channel;
+    } else if (interruptNumber == DMA_INT2)
+    {
+        DMA->rINT2_SRCCFG.r = (DMA->rINT2_SRCCFG.r & ~DMA_INT1_SRCCFG_INT_SRC_M)
+                | channel;
+    } else if (interruptNumber == DMA_INT3)
+    {
+        DMA->rINT3_SRCCFG.r = (DMA->rINT3_SRCCFG.r & ~DMA_INT1_SRCCFG_INT_SRC_M)
+                | channel;
+    }
+
+    /* Enabling the assigned interrupt */
+    DMA_enableInterrupt(interruptNumber);
+}
+
+void DMA_requestSoftwareTransfer(uint32_t channel)
+{
+    DMA->rSW_CHTRIG.r |= (1 << channel);
+}
+
+uint32_t DMA_getInterruptStatus(void)
+{
+    return DMA->rINT0_SRCFLG.r;
+}
+
+void DMA_clearInterruptFlag(uint32_t channel)
+{
+    DMA->rINT0_CLRFLG.r |= (1 << channel);
+}
+
+void DMA_enableInterrupt(uint32_t interruptNumber)
+{
+    ASSERT(
+            (interruptNumber == DMA_INT0) || (interruptNumber == DMA_INT1)
+            || (interruptNumber == DMA_INT2)
+            || (interruptNumber == DMA_INT3));
+
+    if (interruptNumber == DMA_INT1)
+    {
+        DMA->rINT1_SRCCFG.r |= DMA_INT1_SRCCFG_EN;
+    } else if (interruptNumber == DMA_INT2)
+    {
+        DMA->rINT2_SRCCFG.r |= DMA_INT2_SRCCFG_EN;
+    } else if (interruptNumber == DMA_INT3)
+    {
+        DMA->rINT3_SRCCFG.r |= DMA_INT3_SRCCFG_EN;
+    }
+
+}
+
+void DMA_disableInterrupt(uint32_t interruptNumber)
+{
+    ASSERT(
+            (interruptNumber == DMA_INT0) || (interruptNumber == DMA_INT1)
+            || (interruptNumber == DMA_INT2)
+            || (interruptNumber == DMA_INT3));
+
+    if (interruptNumber == DMA_INT1)
+    {
+        DMA->rINT1_SRCCFG.r &= ~DMA_INT1_SRCCFG_EN;
+    } else if (interruptNumber == DMA_INT2)
+    {
+        DMA->rINT2_SRCCFG.r &= ~DMA_INT2_SRCCFG_EN;
+    } else if (interruptNumber == DMA_INT3)
+    {
+        DMA->rINT3_SRCCFG.r &= ~DMA_INT3_SRCCFG_EN;
+    }
+}
+
+void DMA_registerInterrupt(uint32_t interruptNumber, void (*intHandler)(void))
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(intHandler);
+    ASSERT(
+            (interruptNumber == DMA_INT0) || (interruptNumber == DMA_INT1)
+            || (interruptNumber == DMA_INT2)
+            || (interruptNumber == DMA_INT3)
+            || (interruptNumber == DMA_INTERR));
+
+    //
+    // Register the interrupt handler.
+    //
+    Interrupt_registerInterrupt(interruptNumber, intHandler);
+
+    //
+    // Enable the memory management fault.
+    //
+    Interrupt_enableInterrupt(interruptNumber);
+
+}
+
+void DMA_unregisterInterrupt(uint32_t interruptNumber)
+{
+    ASSERT(
+            (interruptNumber == DMA_INT0) || (interruptNumber == DMA_INT1)
+            || (interruptNumber == DMA_INT2)
+            || (interruptNumber == DMA_INT3)
+            || (interruptNumber == DMA_INTERR));
+
+    //
+    // Disable the interrupt.
+    //
+    Interrupt_disableInterrupt(interruptNumber);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    Interrupt_unregisterInterrupt(interruptNumber);
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/dma.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/dma.h
new file mode 100644
index 000000000..52ed5e25a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/dma.h
@@ -0,0 +1,1010 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __DMA_H__
+#define __DMA_H__
+
+//*****************************************************************************
+//
+//! \addtogroup dma_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <msp.h>
+
+//*****************************************************************************
+//
+// A structure that defines an entry in the channel control table.  These
+// fields are used by the DMA controller and normally it is not necessary for
+// software to directly read or write fields in the table.
+//
+//*****************************************************************************
+typedef struct _DMA_ControlTable
+{
+    //
+    // The ending source address of the data transfer.
+    //
+    volatile void *srcEndAddr;
+
+    //
+    // The ending destination address of the data transfer.
+    //
+    volatile void *dstEndAddr;
+
+    //
+    // The channel control mode.
+    //
+    volatile uint32_t control;
+
+    //
+    // An unused location.
+    //
+    volatile uint32_t spare;
+} DMA_ControlTable;
+
+//*****************************************************************************
+//
+//! A helper macro for building scatter-gather task table entries.
+//!
+//! This macro is intended to be used to help populate a table of DMA tasks
+//! for a scatter-gather transfer.  This macro will calculate the values for
+//! the fields of a task structure entry based on the input parameters.
+//!
+//! There are specific requirements for the values of each parameter.  No
+//! checking is done so it is up to the caller to ensure that correct values
+//! are used for the parameters.
+//!
+//! The \b transferCount parameter is the number of items that will be
+//! transferred by this task.  It must be in the range 1-1024.
+//!
+//! The \b itemSize parameter is the bit size of the transfer data.  It must
+//! be one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or \b UDMA_SIZE_32.
+//!
+//! The \e srcIncrement parameter is the increment size for the source data.
+//! It must be one of \b UDMA_SRC_INC_8, \b UDMA_SRC_INC_16,
+//! \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE.
+//!
+//! The \b srcAddr parameter is a void pointer to the beginning of the source
+//! data.
+//!
+//! The \b dstIncrement parameter is the increment size for the destination
+//! data.  It must be one of \b UDMA_DST_INC_8, \b UDMA_DST_INC_16,
+//! \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE.
+//!
+//! The \b dstAddr parameter is a void pointer to the beginning of the
+//! location where the data will be transferred.
+//!
+//! The \b arbSize parameter is the arbitration size for the transfer, and
+//! must be one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, and so on
+//! up to \b UDMA_ARB_1024.  This is used to select the arbitration size in
+//! powers of 2, from 1 to 1024.
+//!
+//! The \e mode parameter is the mode to use for this transfer task.  It
+//! must be one of \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO,
+//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER.  Note
+//! that normally all tasks will be one of the scatter-gather modes while the
+//! last task is a task list will be AUTO or BASIC.
+//!
+//! This macro is intended to be used to initialize individual entries of
+//! a structure of DMA_ControlTable type, like this:
+//!
+//! \code{.c}
+//!     DMA_ControlTable MyTaskList[] =
+//!     {
+//!         DMA_TaskStructEntry(Task1Count, UDMA_SIZE_8,
+//!                             UDMA_SRC_INC_8, MySourceBuf,
+//!                             UDMA_DST_INC_8, MyDestBuf,
+//!                             UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER),
+//!         DMA_TaskStructEntry(Task2Count, ... ),
+//!     }
+//! \endcode
+//!
+//! \param transferCount is the count of items to transfer for this task.
+//! \param itemSize is the bit size of the items to transfer for this task.
+//! \param srcIncrement is the bit size increment for source data.
+//! \param srcAddr is the starting address of the data to transfer.
+//! \param dstIncrement is the bit size increment for destination data.
+//! \param dstAddr is the starting address of the destination data.
+//! \param arbSize is the arbitration size to use for the transfer task.
+//! \param mode is the transfer mode for this task.
+//!
+//! \return Nothing; this is not a function.
+//
+//*****************************************************************************
+#define DMA_TaskStructEntry(transferCount,                                     \
+                            itemSize,                                          \
+                            srcIncrement,                                      \
+                            srcAddr,                                           \
+                            dstIncrement,                                      \
+                            dstAddr,                                           \
+                            arbSize,                                           \
+                            mode)                                              \
+    {                                                                          \
+        (((srcIncrement) == UDMA_SRC_INC_NONE) ? (void *)(srcAddr) :           \
+            ((void *)(&((uint8_t *)(srcAddr))[((transferCount) <<              \
+                                         ((srcIncrement) >> 26)) - 1]))),      \
+            (((dstIncrement) == UDMA_DST_INC_NONE) ? (void *)(dstAddr) :       \
+            ((void *)(&((uint8_t *)(dstAddr))[((transferCount) <<              \
+                                         ((dstIncrement) >> 30)) - 1]))),      \
+        (srcIncrement) | (dstIncrement) | (itemSize) | (arbSize) |             \
+        (((transferCount) - 1) << 4) |                                         \
+        ((((mode) == UDMA_MODE_MEM_SCATTER_GATHER) ||                          \
+          ((mode) == UDMA_MODE_PER_SCATTER_GATHER)) ?                          \
+                (mode) | UDMA_MODE_ALT_SELECT : (mode)), 0                     \
+    }
+
+//*****************************************************************************
+//
+// Flags that can be passed to DMA_enableChannelAttribute(),
+// DMA_disableChannelAttribute(), and returned from DMA_getChannelAttribute().
+//
+//*****************************************************************************
+#define UDMA_ATTR_USEBURST      0x00000001
+#define UDMA_ATTR_ALTSELECT     0x00000002
+#define UDMA_ATTR_HIGH_PRIORITY 0x00000004
+#define UDMA_ATTR_REQMASK       0x00000008
+#define UDMA_ATTR_ALL           0x0000000F
+
+//*****************************************************************************
+//
+// DMA control modes that can be passed to DMAModeSet() and returned
+// DMAModeGet().
+//
+//*****************************************************************************
+#define UDMA_MODE_STOP          0x00000000
+#define UDMA_MODE_BASIC         0x00000001
+#define UDMA_MODE_AUTO          0x00000002
+#define UDMA_MODE_PINGPONG      0x00000003
+#define UDMA_MODE_MEM_SCATTER_GATHER                                          \
+                                0x00000004
+#define UDMA_MODE_PER_SCATTER_GATHER                                          \
+                                0x00000006
+#define UDMA_MODE_ALT_SELECT    0x00000001
+
+//*****************************************************************************
+//
+// Channel configuration values that can be passed to DMAControlSet().
+//
+//*****************************************************************************
+#define UDMA_DST_INC_8          0x00000000
+#define UDMA_DST_INC_16         0x40000000
+#define UDMA_DST_INC_32         0x80000000
+#define UDMA_DST_INC_NONE       0xc0000000
+#define UDMA_SRC_INC_8          0x00000000
+#define UDMA_SRC_INC_16         0x04000000
+#define UDMA_SRC_INC_32         0x08000000
+#define UDMA_SRC_INC_NONE       0x0c000000
+#define UDMA_SIZE_8             0x00000000
+#define UDMA_SIZE_16            0x11000000
+#define UDMA_SIZE_32            0x22000000
+#define UDMA_DST_PROT_PRIV      0x00200000
+#define UDMA_SRC_PROT_PRIV      0x00040000
+#define UDMA_ARB_1              0x00000000
+#define UDMA_ARB_2              0x00004000
+#define UDMA_ARB_4              0x00008000
+#define UDMA_ARB_8              0x0000c000
+#define UDMA_ARB_16             0x00010000
+#define UDMA_ARB_32             0x00014000
+#define UDMA_ARB_64             0x00018000
+#define UDMA_ARB_128            0x0001c000
+#define UDMA_ARB_256            0x00020000
+#define UDMA_ARB_512            0x00024000
+#define UDMA_ARB_1024           0x00028000
+#define UDMA_NEXT_USEBURST      0x00000008
+
+//*****************************************************************************
+//
+// Flags to be OR'd with the channel ID to indicate if the primary or alternate
+// control structure should be used.
+//
+//*****************************************************************************
+#define UDMA_PRI_SELECT         0x00000000
+#define UDMA_ALT_SELECT         0x00000008
+
+//*****************************************************************************
+//
+// Values that can be passed to DMA_assignChannel() to select peripheral
+// mapping for each channel.  The channels named RESERVED may be assigned
+// to a peripheral in future parts.
+//
+//*****************************************************************************
+//
+// Channel 0
+//
+#define DMA_CH0_RESERVED0          0x00000000
+#define DMA_CH0_EUSCIA0TX          0x01000000
+#define DMA_CH0_EUSCIB0TX0         0x02000000
+#define DMA_CH0_EUSCIB3TX1         0x03000000
+#define DMA_CH0_EUSCIB2TX2         0x04000000
+#define DMA_CH0_EUSCIB1TX3         0x05000000
+#define DMA_CH0_TIMERA0CCR0        0x06000000
+#define DMA_CH0_AESTRIGGER0        0x07000000
+
+//
+// Channel 1
+//
+#define DMA_CH1_RESERVED0          0x00000001
+#define DMA_CH1_EUSCIA0RX          0x01000001
+#define DMA_CH1_EUSCIB0RX0         0x02000001
+#define DMA_CH1_EUSCIB3RX1         0x03000001
+#define DMA_CH1_EUSCIB2RX2         0x04000001
+#define DMA_CH1_EUSCIB1RX3         0x05000001
+#define DMA_CH1_TIMERA0CCR2        0x06000001
+#define DMA_CH1_AESTRIGGER1        0x07000001
+
+//
+// Channel 2
+//
+#define DMA_CH2_RESERVED0          0x00000002
+#define DMA_CH2_EUSCIA1TX          0x01000002
+#define DMA_CH2_EUSCIB1TX0         0x02000002
+#define DMA_CH2_EUSCIB0TX1         0x03000002
+#define DMA_CH2_EUSCIB3TX2         0x04000002
+#define DMA_CH2_EUSCIB2TX3         0x05000002
+#define DMA_CH2_TIMERA1CCR0        0x06000002
+#define DMA_CH2_AESTRIGGER2        0x07000002
+
+//
+// Channel 3
+//
+#define DMA_CH3_RESERVED0          0x00000003
+#define DMA_CH3_EUSCIA1RX          0x01000003
+#define DMA_CH3_EUSCIB1RX0         0x02000003
+#define DMA_CH3_EUSCIB0RX1         0x03000003
+#define DMA_CH3_EUSCIB3RX2         0x04000003
+#define DMA_CH3_EUSCIB2RX3         0x05000003
+#define DMA_CH3_TIMERA1CCR2        0x06000003
+#define DMA_CH3_RESERVED1          0x07000003
+
+//
+// Channel 4
+//
+#define DMA_CH4_RESERVED0          0x00000004
+#define DMA_CH4_EUSCIA2TX          0x01000004
+#define DMA_CH4_EUSCIB2TX0         0x02000004
+#define DMA_CH4_EUSCIB1TX1         0x03000004
+#define DMA_CH4_EUSCIB0TX2         0x04000004
+#define DMA_CH4_EUSCIB3TX3         0x05000004
+#define DMA_CH4_TIMERA2CCR0        0x06000004
+#define DMA_CH4_RESERVED1          0x07000004
+
+//
+// Channel 5
+//
+#define DMA_CH5_RESERVED0          0x00000005
+#define DMA_CH5_EUSCIA2RX          0x01000005
+#define DMA_CH5_EUSCIB2RX0         0x02000005
+#define DMA_CH5_EUSCIB1RX1         0x03000005
+#define DMA_CH5_EUSCIB0RX2         0x04000005
+#define DMA_CH5_EUSCIB3RX3         0x05000005
+#define DMA_CH5_TIMERA2CCR2        0x06000005
+#define DMA_CH5_RESERVED1          0x07000005
+
+//
+// Channel 6
+//
+#define DMA_CH6_RESERVED0          0x00000006
+#define DMA_CH6_EUSCIA3TX          0x01000006
+#define DMA_CH6_EUSCIB3TX0         0x02000006
+#define DMA_CH6_EUSCIB2TX1         0x03000006
+#define DMA_CH6_EUSCIB1TX2         0x04000006
+#define DMA_CH6_EUSCIB0TX3         0x05000006
+#define DMA_CH6_TIMERA3CCR0        0x06000006
+#define DMA_CH6_EXTERNALPIN        0x07000006
+
+//
+// Channel 7
+//
+#define DMA_CH7_RESERVED0          0x00000007
+#define DMA_CH7_EUSCIA3RX          0x01000007
+#define DMA_CH7_EUSCIB3RX0         0x02000007
+#define DMA_CH7_EUSCIB2RX1         0x03000007
+#define DMA_CH7_EUSCIB1RX2         0x04000007
+#define DMA_CH7_EUSCIB0RX3         0x05000007
+#define DMA_CH7_TIMERA3CCR2        0x06000007
+#define DMA_CH7_ADC12C             0x07000007
+
+//
+//  Different interrupt handlers to pass into DMA_registerInterrupt and
+//   DMA_unregisterInterrupt and other Int functions
+//
+#define DMA_INT0   INT_DMA_INT0
+#define DMA_INT1   INT_DMA_INT1
+#define DMA_INT2   INT_DMA_INT2
+#define DMA_INT3   INT_DMA_INT3
+#define DMA_INTERR INT_DMA_ERR
+
+#define DMA_CHANNEL_0       0
+#define DMA_CHANNEL_1       1
+#define DMA_CHANNEL_2       2
+#define DMA_CHANNEL_3       3
+#define DMA_CHANNEL_4       4
+#define DMA_CHANNEL_5       5
+#define DMA_CHANNEL_6       6
+#define DMA_CHANNEL_7       7
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! Enables the DMA controller for use.
+//!
+//! This function enables the DMA controller.  The DMA controller must be
+//! enabled before it can be configured and used.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void DMA_enableModule(void);
+
+//*****************************************************************************
+//
+//! Disables the DMA controller for use.
+//!
+//! This function disables the DMA controller.  Once disabled, the DMA
+//! controller cannot operate until re-enabled with DMA_enableModule().
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void DMA_disableModule(void);
+
+//*****************************************************************************
+//
+//! Gets the DMA error status.
+//!
+//! This function returns the DMA error status.  It should be called from
+//! within the DMA error interrupt handler to determine if a DMA error
+//! occurred.
+//!
+//! \return Returns non-zero if a DMA error is pending.
+//
+//*****************************************************************************
+extern uint32_t DMA_getErrorStatus(void);
+
+//*****************************************************************************
+//
+//! Clears the DMA error interrupt.
+//!
+//! This function clears a pending DMA error interrupt.  This function should
+//! be called from within the DMA error interrupt handler to clear the
+//! interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void DMA_clearErrorStatus(void);
+
+//*****************************************************************************
+//
+//! Enables a DMA channel for operation.
+//!
+//! \param channelNum is the channel number to enable.
+//!
+//! This function enables a specific DMA channel for use.  This function must
+//! be used to enable a channel before it can be used to perform a DMA
+//! transfer.
+//!
+//! When a DMA transfer is completed, the channel is automatically disabled by
+//! the DMA controller.  Therefore, this function should be called prior to
+//! starting up any new transfer.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void DMA_enableChannel(uint32_t channelNum);
+
+//*****************************************************************************
+//
+//! Disables a DMA channel for operation.
+//!
+//! \param channelNum is the channel number to disable.
+//!
+//! This function disables a specific DMA channel.  Once disabled, a channel
+//! cannot respond to DMA transfer requests until re-enabled via
+//! DMA_enableChannel().
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void DMA_disableChannel(uint32_t channelNum);
+
+//*****************************************************************************
+//
+//! Checks if a DMA channel is enabled for operation.
+//!
+//! \param channelNum is the channel number to check.
+//!
+//! This function checks to see if a specific DMA channel is enabled.  This
+//! function can be used to check the status of a transfer, as the channel is
+//! automatically disabled at the end of a transfer.
+//!
+//! \return Returns \b true if the channel is enabled, \b false if disabled.
+//
+//*****************************************************************************
+extern bool DMA_isChannelEnabled(uint32_t channelNum);
+
+//*****************************************************************************
+//
+//! Sets the base address for the channel control table.
+//!
+//! \param controlTable is a pointer to the 1024-byte-aligned base address
+//! of the DMA channel control table.
+//!
+//! This function configures the base address of the channel control table.
+//! This table resides in system memory and holds control information for each
+//! DMA channel.  The table must be aligned on a 1024-byte boundary.  The base
+//! address must be configured before any of the channel functions can be used.
+//!
+//! The size of the channel control table depends on the number of DMA
+//! channels and the transfer modes that are used.  Refer to the introductory
+//! text and the microcontroller datasheet for more information about the
+//! channel control table.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void DMA_setControlBase(void *controlTable);
+
+//*****************************************************************************
+//
+//! Gets the base address for the channel control table.
+//!
+//! This function gets the base address of the channel control table.  This
+//! table resides in system memory and holds control information for each DMA
+//! channel.
+//!
+//! \return Returns a pointer to the base address of the channel control table.
+//
+//*****************************************************************************
+extern void* DMA_getControlBase(void);
+
+//*****************************************************************************
+//
+//! Gets the base address for the channel control table alternate structures.
+//!
+//! This function gets the base address of the second half of the channel
+//! control table that holds the alternate control structures for each channel.
+//!
+//! \return Returns a pointer to the base address of the second half of the
+//! channel control table.
+//
+//*****************************************************************************
+extern void* DMA_getControlAlternateBase(void);
+
+//*****************************************************************************
+//
+//! Requests a DMA channel to start a transfer.
+//!
+//! \param channelNum is the channel number on which to request a DMA
+//! transfer.
+//!
+//! This function allows software to request a DMA channel to begin a
+//! transfer.  This function could be used for performing a memory-to-memory
+//! transfer, or if for some reason a transfer needs to be initiated by
+//! software instead of the peripheral associated with that channel.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void DMA_requestChannel(uint32_t channelNum);
+
+//*****************************************************************************
+//
+//! Enables attributes of a DMA channel.
+//!
+//! \param channelNum is the channel to configure.
+//! \param attr is a combination of attributes for the channel.
+//!
+//! This function is used to enable attributes of a DMA channel.
+//!
+//! The \e attr parameter is the logical OR of any of the following:
+//!
+//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst
+//!   mode.
+//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure
+//!   for this channel (it is very unlikely that this flag should be used).
+//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority.
+//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the
+//!   peripheral for this channel.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void DMA_enableChannelAttribute(uint32_t channelNum, uint32_t attr);
+
+//*****************************************************************************
+//
+//! Disables attributes of a DMA channel.
+//!
+//! \param channelNum is the channel to configure.
+//! \param attr is a combination of attributes for the channel.
+//!
+//! This function is used to disable attributes of a DMA channel.
+//!
+//! The \e attr parameter is the logical OR of any of the following:
+//!
+//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst
+//!   mode.
+//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure
+//!   for this channel.
+//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority.
+//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the
+//!   peripheral for this channel.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void DMA_disableChannelAttribute(uint32_t channelNum, uint32_t attr);
+
+//*****************************************************************************
+//
+//! Gets the enabled attributes of a DMA channel.
+//!
+//! \param channelNum is the channel to configure.
+//!
+//! This function returns a combination of flags representing the attributes of
+//! the DMA channel.
+//!
+//! \return Returns the logical OR of the attributes of the DMA channel, which
+//! can be any of the following:
+//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst
+//!   mode.
+//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure
+//!   for this channel.
+//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority.
+//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the
+//!   peripheral for this channel.
+//
+//*****************************************************************************
+extern uint32_t DMA_getChannelAttribute(uint32_t channelNum);
+
+//*****************************************************************************
+//
+//! Sets the control parameters for a DMA channel control structure.
+//!
+//! \param channelStructIndex is the logical OR of the DMA channel number
+//! with \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT.
+//! \param control is logical OR of several control values to set the control
+//! parameters for the channel.
+//!
+//! This function is used to set control parameters for a DMA transfer.  These
+//! parameters are typically not changed often.
+//!
+//! The \e channelStructIndex parameter should be the logical OR of the
+//! channel number with one of \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to
+//! choose whether the primary or alternate data structure is used.
+//!
+//! The \e control parameter is the logical OR of five values: the data size,
+//! the source address increment, the destination address increment, the
+//! arbitration size, and the use burst flag.  The choices available for each
+//! of these values is described below.
+//!
+//! Choose the data size from one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or
+//! \b UDMA_SIZE_32 to select a data size of 8, 16, or 32 bits.
+//!
+//! Choose the source address increment from one of \b UDMA_SRC_INC_8,
+//! \b UDMA_SRC_INC_16, \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE to select
+//! an address increment of 8-bit bytes, 16-bit half-words, 32-bit words, or
+//! to select non-incrementing.
+//!
+//! Choose the destination address increment from one of \b UDMA_DST_INC_8,
+//! \b UDMA_DST_INC_16, \b UDMA_DST_INC_32, or \b UDMA_SRC_INC_8 to select
+//! an address increment of 8-bit bytes, 16-bit half-words, 32-bit words, or
+//! to select non-incrementing.
+//!
+//! The arbitration size determines how many items are transferred before
+//! the DMA controller re-arbitrates for the bus.  Choose the arbitration size
+//! from one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, \b UDMA_ARB_8,
+//! through \b UDMA_ARB_1024 to select the arbitration size from 1 to 1024
+//! items, in powers of 2.
+//!
+//! The value \b UDMA_NEXT_USEBURST is used to force the channel to only
+//! respond to burst requests at the tail end of a scatter-gather transfer.
+//!
+//! \note The address increment cannot be smaller than the data size.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void DMA_setChannelControl(uint32_t channelStructIndex,
+        uint32_t control);
+
+//*****************************************************************************
+//
+//! Sets the transfer parameters for a DMA channel control structure.
+//!
+//! \param channelStructIndex is the logical OR of the DMA channel number
+//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT.
+//! \param mode is the type of DMA transfer.
+//! \param srcAddr is the source address for the transfer.
+//! \param dstAddr is the destination address for the transfer.
+//! \param transferSize is the number of data items to transfer.
+//!
+//! This function is used to configure the parameters for a DMA transfer.
+//! These parameters are typically changed often.  The function
+//! DMA_setChannelControl() MUST be called at least once for this channel prior
+//! to calling this function.
+//!
+//! The \e channelStructIndex parameter should be the logical OR of the
+//! channel number with one of \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to
+//! choose whether the primary or alternate data structure is used.
+//!
+//! The \e mode parameter should be one of the following values:
+//!
+//! - \b UDMA_MODE_STOP stops the DMA transfer.  The controller sets the mode
+//!   to this value at the end of a transfer.
+//! - \b UDMA_MODE_BASIC to perform a basic transfer based on request.
+//! - \b UDMA_MODE_AUTO to perform a transfer that always completes once
+//!   started even if the request is removed.
+//! - \b UDMA_MODE_PINGPONG to set up a transfer that switches between the
+//!   primary and alternate control structures for the channel.  This mode
+//!   allows use of ping-pong buffering for DMA transfers.
+//! - \b UDMA_MODE_MEM_SCATTER_GATHER to set up a memory scatter-gather
+//!   transfer.
+//! - \b UDMA_MODE_PER_SCATTER_GATHER to set up a peripheral scatter-gather
+//!   transfer.
+//!
+//! The \e srcAddr and \e dstAddr parameters are pointers to the first
+//! location of the data to be transferred.  These addresses should be aligned
+//! according to the item size.  The compiler takes care of this alignment if
+//! the pointers are pointing to storage of the appropriate data type.
+//!
+//! The \e transferSize parameter is the number of data items, not the number
+//! of bytes.
+//!
+//! The two scatter-gather modes, memory and peripheral, are actually different
+//! depending on whether the primary or alternate control structure is
+//! selected.  This function looks for the \b UDMA_PRI_SELECT and
+//! \b UDMA_ALT_SELECT flag along with the channel number and sets the
+//! scatter-gather mode as appropriate for the primary or alternate control
+//! structure.
+//!
+//! The channel must also be enabled using DMA_enableChannel() after calling
+//! this function.  The transfer does not begin until the channel has been
+//! configured and enabled.  Note that the channel is automatically disabled
+//! after the transfer is completed, meaning that DMA_enableChannel() must be
+//! called again after setting up the next transfer.
+//!
+//! \note Great care must be taken to not modify a channel control structure
+//! that is in use or else the results are unpredictable, including the
+//! possibility of undesired data transfers to or from memory or peripherals.
+//! For BASIC and AUTO modes, it is safe to make changes when the channel is
+//! disabled, or the DMA_getChannelMode() returns \b UDMA_MODE_STOP.  For
+//! PINGPONG or one of the SCATTER_GATHER modes, it is safe to modify the
+//! primary or alternate control structure only when the other is being used.
+//! The DMA_getChannelMode() function returns \b UDMA_MODE_STOP when a
+//! channel control structure is inactive and safe to modify.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void DMA_setChannelTransfer(uint32_t channelStructIndex, uint32_t mode,
+        void *srcAddr, void *dstAddr, uint32_t transferSize);
+
+//*****************************************************************************
+//
+//! Configures a DMA channel for scatter-gather mode.
+//!
+//! \param channelNum is the DMA channel number.
+//! \param taskCount is the number of scatter-gather tasks to execute.
+//! \param taskList is a pointer to the beginning of the scatter-gather
+//! task list.
+//! \param isPeriphSG is a flag to indicate it is a peripheral scatter-gather
+//! transfer (else it is memory scatter-gather transfer)
+//!
+//! This function is used to configure a channel for scatter-gather mode.
+//! The caller must have already set up a task list and must pass a pointer to
+//! the start of the task list as the \e taskList parameter.  The
+//! \e taskCount parameter is the count of tasks in the task list, not the
+//! size of the task list.  The flag \e bIsPeriphSG should be used to indicate
+//! if scatter-gather should be configured for peripheral or memory
+//! operation.
+//!
+//! \sa DMA_TaskStructEntry
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void DMA_setChannelScatterGather(uint32_t channelNum, uint32_t taskCount,
+        void *taskList, uint32_t isPeriphSG);
+
+//*****************************************************************************
+//
+//! Gets the current transfer size for a DMA channel control structure.
+//!
+//! \param channelStructIndex is the logical OR of the DMA channel number
+//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT.
+//!
+//! This function is used to get the DMA transfer size for a channel.  The
+//! transfer size is the number of items to transfer, where the size of an item
+//! might be 8, 16, or 32 bits.  If a partial transfer has already occurred,
+//! then the number of remaining items is returned.  If the transfer is
+//! complete, then 0 is returned.
+//!
+//! \return Returns the number of items remaining to transfer.
+//
+//*****************************************************************************
+extern uint32_t DMA_getChannelSize(uint32_t channelStructIndex);
+
+//*****************************************************************************
+//
+//! Gets the transfer mode for a DMA channel control structure.
+//!
+//! \param channelStructIndex is the logical OR of the DMA channel number
+//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT.
+//!
+//! This function is used to get the transfer mode for the DMA channel and
+//! to query the status of a transfer on a channel.  When the transfer is
+//! complete the mode is \b UDMA_MODE_STOP.
+//!
+//! \return Returns the transfer mode of the specified channel and control
+//! structure, which is one of the following values: \b UDMA_MODE_STOP,
+//! \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO, \b UDMA_MODE_PINGPONG,
+//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER.
+//
+//*****************************************************************************
+extern uint32_t DMA_getChannelMode(uint32_t channelStructIndex);
+
+//*****************************************************************************
+//
+//! Assigns a peripheral mapping for a DMA channel.
+//!
+//! \param mapping is a macro specifying the peripheral assignment for
+//! a channel.
+//!
+//! This function assigns a peripheral mapping to a DMA channel.  It is
+//! used to select which peripheral is used for a DMA channel.  The parameter
+//! \e mapping should be one of the macros named \b UDMA_CHn_tttt from the
+//! header file \e dma.h.  For example, to assign DMA channel 0 to the
+//! eUSCI AO RX channel, the parameter should be the macro
+//! \b UDMA_CH1_EUSCIA0RX.
+//!
+//! Please consult the data sheet for a table showing all the
+//! possible peripheral assignments for the DMA channels for a particular
+//! device.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void DMA_assignChannel(uint32_t mapping);
+
+//*****************************************************************************
+//
+//! Initializes a software transfer of the corresponding DMA channel. This is
+//! done if the user wants to force a DMA on the specified channel without the
+//! hardware precondition. Specific channels can be configured using the
+//! DMA_assignChannel function.
+//!
+//! \param channel is the channel to trigger the interrupt
+//!
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void DMA_requestSoftwareTransfer(uint32_t channel);
+
+//*****************************************************************************
+//
+//! Assigns a specific DMA channel to the corresponding interrupt handler. For
+//! MSP432 devices, there are three configurable interrupts, and one master
+//! interrupt. This function will assign a specific DMA channel to the
+//! provided configurable DMA interrupt.
+//!
+//! Note that once a channel is assigned to a configurable interrupt, it will be
+//! masked in hardware from the master DMA interrupt (interruptNumber zero). This
+//! function can also be used in conjunction with the DMAIntTrigger function
+//! to provide the feature to software trigger specific channel interrupts.
+//!
+//! \param interruptNumber is the configurable interrupt to assign the given
+//! channel. Valid values are:
+//! - \b DMA_INT1 the first configurable DMA interrupt handler
+//! - \b DMA_INT2 the second configurable DMA interrupt handler
+//! - \b DMA_INT3 the third configurable DMA interrupt handler
+//!
+//! \param channel is the channel to assign the interrupt
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void DMA_assignInterrupt(uint32_t interruptNumber, uint32_t channel);
+
+//*****************************************************************************
+//
+//! Enables the specified interrupt for the DMA controller. Note for interrupts
+//! one through three, specific channels have to be mapped to the interrupt
+//! using the DMA_assignInterrupt function.
+//!
+//! \param interruptNumber identifies which DMA interrupt is to be enabled.
+//! This interrupt should be one of the following:
+//!
+//! - \b DMA_INT0 the master DMA interrupt handler
+//! - \b DMA_INT1 the first configurable DMA interrupt handler
+//! - \b DMA_INT2 the second configurable DMA interrupt handler
+//! - \b DMA_INT3 the third configurable DMA interrupt handler
+//! - \b DMA_INTERR the third configurable DMA interrupt handler
+//!
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void DMA_enableInterrupt(uint32_t interruptNumber);
+
+//*****************************************************************************
+//
+//! Disables the specified interrupt for the DMA controller.
+//!
+//! \param interruptNumber identifies which DMA interrupt is to be disabled.
+//! This interrupt should be one of the following:
+//!
+//! - \b DMA_INT0 the master DMA interrupt handler
+//! - \b DMA_INT1 the first configurable DMA interrupt handler
+//! - \b DMA_INT2 the second configurable DMA interrupt handler
+//! - \b DMA_INT3 the third configurable DMA interrupt handler
+//! - \b DMA_INTERR the third configurable DMA interrupt handler
+//!
+//!  Note for interrupts that are associated with a specific DMA channel
+//! (DMA_INT1 - DMA_INT3), this function will also enable that specific
+//! channel for interrupts.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void DMA_disableInterrupt(uint32_t interruptNumber);
+
+//*****************************************************************************
+//
+//! Gets the DMA controller channel interrupt status for interrupt zero.
+//!
+//! This function is used to get the interrupt status of the DMA controller.
+//! The returned value is a 32-bit bit mask that indicates which channels are
+//! requesting an interrupt.  This function can be used from within an
+//! interrupt handler to determine or confirm which DMA channel has requested
+//! an interrupt.
+//!
+//! Note that this will only apply to interrupt zero for the DMA
+//! controller as only one interrupt can be associated with interrupts one
+//! through three. If an interrupt is assigned to an interrupt other
+//! than interrupt zero, it will be masked by this function.
+//!
+//! \return Returns a 32-bit mask which indicates requesting DMA channels.
+//! There is a bit for each channel and a 1 indicates that the channel
+//! is requesting an interrupt.  Multiple bits can be set.
+//
+//*****************************************************************************
+extern uint32_t DMA_getInterruptStatus(void);
+
+//*****************************************************************************
+//
+//! Clears the DMA controller channel interrupt mask for interrupt zero.
+//!
+//! \param channel is the channel interrupt to clear.
+//!
+//! This function is used to clear  the interrupt status of the DMA controller.
+//! Note that only interrupts that weren't assigned to DMA interrupts one
+//! through three using the DMA_assignInterrupt function will be affected by
+//! thisfunctions. For other DMA interrupts, only one channel can be associated
+//! and therefore clearing in unnecessary.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void DMA_clearInterruptFlag(uint32_t intChannel);
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the DMA controller.
+//!
+//! \param interruptNumber identifies which DMA interrupt is to be registered.
+//! \param intHandler is a pointer to the function to be called when the
+//! interrupt is called.
+//!
+//! This function registers and enables the handler to be called when the DMA
+//! controller generates an interrupt.  The \e interrupt parameter should be
+//! one of the following:
+//!
+//! - \b DMA_INT0 the master DMA interrupt handler
+//! - \b DMA_INT1 the first configurable DMA interrupt handler
+//! - \b DMA_INT2 the second configurable DMA interrupt handler
+//! - \b DMA_INT3 the third configurable DMA interrupt handler
+//! - \b DMA_INTERR the third configurable DMA interrupt handler
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void DMA_registerInterrupt(uint32_t intChannel, 
+                                    void (*intHandler)(void));
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the DMA controller.
+//!
+//! \param interruptNumber identifies which DMA interrupt to unregister.
+//!
+//! This function disables and unregisters the handler to be called for the
+//! specified DMA interrupt.  The \e interrupt parameter should be one of
+//! \b the parameters as documented for the function
+//! DMA_registerInterrupt().
+//!
+//! Note fore interrupts that are associated with a specific DMA channel
+//! (DMA_INT1 - DMA_INT3), this function will also disable that specific
+//! channel for interrupts.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//!  registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void DMA_unregisterInterrupt(uint32_t intChannel);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif // __UDMA_H__
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/driverlib.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/driverlib.h
new file mode 100644
index 000000000..0aa0daff7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/driverlib.h
@@ -0,0 +1,70 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __DRIVERLIB__H_
+#define __DRIVERLIB__H_
+
+#include "adc14.h"
+#include "aes256.h"
+#include "comp_e.h"
+#include "cpu.h"
+#include "crc32.h"
+#include "cs.h"
+#include "dma.h"
+#include "eusci.h"
+#include "flash.h"
+#include "fpu.h"
+#include "gpio.h"
+#include "i2c.h"
+#include "interrupt.h"
+#include "mpu.h"
+#include "pcm.h"
+#include "pmap.h"
+#include "pss.h"
+#include "ref_a.h"
+#include "reset.h"
+#include "rom.h"
+#include "rom_map.h"
+#include "rtc_c.h"
+#include "spi.h"
+#include "sysctl.h"
+#include "systick.h"
+#include "timer32.h"
+#include "timer_a.h"
+#include "uart.h"
+#include "wdt_a.h"
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/eusci.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/eusci.h
new file mode 100644
index 000000000..6850d89c6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/eusci.h
@@ -0,0 +1,45 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef EUSCI_H_
+#define EUSCI_H_
+
+#include <msp.h>
+
+#define EUSCI_A_CMSIS(x) ((EUSCI_A0_Type *) x)
+#define EUSCI_B_CMSIS(x) ((EUSCI_B0_Type *) x)
+
+#endif /* EUSCI_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/flash.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/flash.c
new file mode 100644
index 000000000..f9fca70a0
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/flash.c
@@ -0,0 +1,792 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+/* Standard Includes */
+#include <stdint.h>
+
+/* DriverLib Includes */
+#include <flash.h>
+#include <debug.h>
+#include <interrupt.h>
+#include <msp.h>
+#include <cpu.h>
+#include <rom.h>
+#include <sysctl.h>
+
+/* Statics */
+static const uint32_t MAX_PROGRAM_TRIES = 5;
+static const uint32_t MAX_ERASE_TRIES = 50;
+
+static uint32_t getUserFlashSector(uint32_t addr)
+{
+    if (addr > 0x1ffff)
+    {
+        addr = addr - 0x20000;
+    }
+
+    switch (addr)
+    {
+    case 0:
+        return FLASH_SECTOR0;
+    case 0x1000:
+        return FLASH_SECTOR1;
+    case 0x2000:
+        return FLASH_SECTOR2;
+    case 0x3000:
+        return FLASH_SECTOR3;
+    case 0x4000:
+        return FLASH_SECTOR4;
+    case 0x5000:
+        return FLASH_SECTOR5;
+    case 0x6000:
+        return FLASH_SECTOR6;
+    case 0x7000:
+        return FLASH_SECTOR7;
+    case 0x8000:
+        return FLASH_SECTOR8;
+    case 0x9000:
+        return FLASH_SECTOR9;
+    case 0xA000:
+        return FLASH_SECTOR10;
+    case 0xB000:
+        return FLASH_SECTOR11;
+    case 0xC000:
+        return FLASH_SECTOR12;
+    case 0xD000:
+        return FLASH_SECTOR13;
+    case 0xE000:
+        return FLASH_SECTOR14;
+    case 0xF000:
+        return FLASH_SECTOR15;
+    case 0x10000:
+        return FLASH_SECTOR16;
+    case 0x11000:
+        return FLASH_SECTOR17;
+    case 0x12000:
+        return FLASH_SECTOR18;
+    case 0x13000:
+        return FLASH_SECTOR19;
+    case 0x14000:
+        return FLASH_SECTOR20;
+    case 0x15000:
+        return FLASH_SECTOR21;
+    case 0x16000:
+        return FLASH_SECTOR22;
+    case 0x17000:
+        return FLASH_SECTOR23;
+    case 0x18000:
+        return FLASH_SECTOR24;
+    case 0x19000:
+        return FLASH_SECTOR25;
+    case 0x1A000:
+        return FLASH_SECTOR26;
+    case 0x1B000:
+        return FLASH_SECTOR27;
+    case 0x1C000:
+        return FLASH_SECTOR28;
+    case 0x1D000:
+        return FLASH_SECTOR29;
+    case 0x1E000:
+        return FLASH_SECTOR30;
+    case 0x1F000:
+        return FLASH_SECTOR31;
+    default:
+        ASSERT(false);
+        return 0;
+    }
+}
+
+static bool _FlashCtl_Program8(uint32_t src, uint32_t dest)
+{
+    uint32_t ii;
+
+    /* Enabling the correct verification settings  */
+    FlashCtl_setProgramVerification(FLASH_REGPRE | FLASH_REGPOST);
+    FlashCtl_clearProgramVerification(FLASH_BURSTPOST | FLASH_BURSTPRE);
+
+    for(ii=0;ii<MAX_PROGRAM_TRIES;ii++)
+    {
+        /* Clearing flags */
+        FLCTL->rCLRIFG.r |= (FLASH_PROGRAM_ERROR | FLASH_POSTVERIFY_FAILED
+                | FLASH_PREVERIFY_FAILED | FLASH_WRDPRGM_COMPLETE);
+
+        HWREG8(dest) = HWREG8(src);
+
+        while (!(FlashCtl_getInterruptStatus() & FLASH_WRDPRGM_COMPLETE))
+        {
+            __no_operation();
+        }
+
+        if ((BITBAND_PERI(FLCTL->rIFG.r, FLCTL_IFG_PRG_ERR_OFS))
+                || (BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r,
+                        FLCTL_PRG_CTLSTAT_VER_PRE_OFS)
+                        && BITBAND_PERI(FLCTL->rIFG.r,
+                                FLCTL_IFG_AVPRE_OFS))
+                || (BITBAND_PERI(FLCTL->rIFG.r, FLCTL_IFG_AVPST_OFS)))
+        {
+            if(BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_VER_PRE_OFS))
+            {
+                FlashCtl_clearProgramVerification(FLASH_REGPRE);
+            }
+        }
+        else
+        {
+            return true;
+        }
+    }
+
+    return false;
+
+}
+
+static bool _FlashCtl_Program32(uint32_t src, uint32_t dest)
+{
+    uint32_t ii;
+
+    /* Enabling the correct verification settings  */
+    FlashCtl_setProgramVerification(FLASH_REGPRE | FLASH_REGPOST);
+    FlashCtl_clearProgramVerification(FLASH_BURSTPOST | FLASH_BURSTPRE);
+
+    for(ii=0;ii<MAX_PROGRAM_TRIES;ii++)
+    {
+        /* Clearing flags */
+        FLCTL->rCLRIFG.r |= (FLASH_PROGRAM_ERROR | FLASH_POSTVERIFY_FAILED
+                | FLASH_PREVERIFY_FAILED | FLASH_WRDPRGM_COMPLETE);
+
+        HWREG32(dest) = HWREG32(src);
+
+        while (!(FlashCtl_getInterruptStatus() & FLASH_WRDPRGM_COMPLETE))
+        {
+            __no_operation();
+        }
+
+        if ((BITBAND_PERI(FLCTL->rIFG.r, FLCTL_IFG_PRG_ERR_OFS))
+                || (BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r,
+                        FLCTL_PRG_CTLSTAT_VER_PRE_OFS)
+                        && BITBAND_PERI(FLCTL->rIFG.r,
+                                FLCTL_IFG_AVPRE_OFS))
+                || (BITBAND_PERI(FLCTL->rIFG.r, FLCTL_IFG_AVPST_OFS)))
+        {
+            if(BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_VER_PRE_OFS))
+            {
+                FlashCtl_clearProgramVerification(FLASH_REGPRE);
+            }
+        }
+        else
+        {
+            return true;
+        }
+    }
+
+    return false;
+
+}
+
+void FlashCtl_enableReadBuffering(uint_fast8_t memoryBank,
+        uint_fast8_t accessMethod)
+{
+    if (memoryBank == FLASH_BANK0 && accessMethod == FLASH_DATA_READ)
+        BITBAND_PERI(FLCTL->rBANK0_RDCTL.r, FLCTL_BANK0_RDCTL_BUFD_OFS) = 1;
+    else if (memoryBank == FLASH_BANK1 && accessMethod == FLASH_DATA_READ)
+        BITBAND_PERI(FLCTL->rBANK1_RDCTL.r, FLCTL_BANK1_RDCTL_BUFD_OFS) = 1;
+    else if (memoryBank == FLASH_BANK0
+            && accessMethod == FLASH_INSTRUCTION_FETCH)
+        BITBAND_PERI(FLCTL->rBANK0_RDCTL.r, FLCTL_BANK0_RDCTL_BUFI_OFS) = 1;
+    else if (memoryBank == FLASH_BANK1
+            && accessMethod == FLASH_INSTRUCTION_FETCH)
+        BITBAND_PERI(FLCTL->rBANK1_RDCTL.r, FLCTL_BANK1_RDCTL_BUFI_OFS) = 1;
+    else
+        ASSERT(false);
+}
+
+void FlashCtl_disableReadBuffering(uint_fast8_t memoryBank,
+        uint_fast8_t accessMethod)
+{
+    if (memoryBank == FLASH_BANK0 && accessMethod == FLASH_DATA_READ)
+        BITBAND_PERI(FLCTL->rBANK0_RDCTL.r, FLCTL_BANK0_RDCTL_BUFD_OFS) = 0;
+    else if (memoryBank == FLASH_BANK1 && accessMethod == FLASH_DATA_READ)
+        BITBAND_PERI(FLCTL->rBANK1_RDCTL.r, FLCTL_BANK1_RDCTL_BUFD_OFS) = 0;
+    else if (memoryBank == FLASH_BANK0
+            && accessMethod == FLASH_INSTRUCTION_FETCH)
+        BITBAND_PERI(FLCTL->rBANK0_RDCTL.r, FLCTL_BANK0_RDCTL_BUFI_OFS) = 0;
+    else if (memoryBank == FLASH_BANK1
+            && accessMethod == FLASH_INSTRUCTION_FETCH)
+        BITBAND_PERI(FLCTL->rBANK1_RDCTL.r, FLCTL_BANK1_RDCTL_BUFI_OFS) = 0;
+    else
+        ASSERT(false);
+}
+
+bool FlashCtl_unprotectSector(uint_fast8_t memorySpace, uint32_t sectorMask)
+{
+    switch (memorySpace)
+    {
+    case FLASH_MAIN_MEMORY_SPACE_BANK0:
+        FLCTL->rBANK0_MAIN_WEPROT.r &= ~sectorMask;
+        break;
+    case FLASH_MAIN_MEMORY_SPACE_BANK1:
+        FLCTL->rBANK1_MAIN_WEPROT.r &= ~sectorMask;
+        break;
+    case FLASH_INFO_MEMORY_SPACE_BANK0:
+        ASSERT(sectorMask <= 0x04);
+        FLCTL->rBANK0_INFO_WEPROT.r &= ~sectorMask;
+        break;
+    case FLASH_INFO_MEMORY_SPACE_BANK1:
+        ASSERT(sectorMask <= 0x04);
+        FLCTL->rBANK1_INFO_WEPROT.r &= ~sectorMask;
+        break;
+
+    default:
+        ASSERT(false);
+
+    }
+
+    return !FlashCtl_isSectorProtected(memorySpace, sectorMask);
+}
+
+bool FlashCtl_protectSector(uint_fast8_t memorySpace, uint32_t sectorMask)
+{
+    switch (memorySpace)
+    {
+    case FLASH_MAIN_MEMORY_SPACE_BANK0:
+        FLCTL->rBANK0_MAIN_WEPROT.r |= sectorMask;
+        break;
+    case FLASH_MAIN_MEMORY_SPACE_BANK1:
+        FLCTL->rBANK1_MAIN_WEPROT.r |= sectorMask;
+        break;
+    case FLASH_INFO_MEMORY_SPACE_BANK0:
+        ASSERT(sectorMask <= 0x04);
+        FLCTL->rBANK0_INFO_WEPROT.r |= sectorMask;
+        break;
+    case FLASH_INFO_MEMORY_SPACE_BANK1:
+        ASSERT(sectorMask <= 0x04);
+        FLCTL->rBANK1_INFO_WEPROT.r |= sectorMask;
+        break;
+
+    default:
+        ASSERT(false);
+
+    }
+
+    return FlashCtl_isSectorProtected(memorySpace, sectorMask);
+}
+
+bool FlashCtl_isSectorProtected(uint_fast8_t memorySpace, uint32_t sector)
+{
+    switch (memorySpace)
+    {
+    case FLASH_MAIN_MEMORY_SPACE_BANK0:
+        return FLCTL->rBANK0_MAIN_WEPROT.r & sector;
+    case FLASH_MAIN_MEMORY_SPACE_BANK1:
+        return FLCTL->rBANK1_MAIN_WEPROT.r & sector;
+    case FLASH_INFO_MEMORY_SPACE_BANK0:
+        ASSERT(sector <= 0x04);
+        return FLCTL->rBANK0_INFO_WEPROT.r & sector;
+    case FLASH_INFO_MEMORY_SPACE_BANK1:
+        ASSERT(sector <= 0x04);
+        return FLCTL->rBANK1_INFO_WEPROT.r & sector;
+    default:
+        return false;
+    }
+}
+
+bool FlashCtl_verifyMemory(void* verifyAddr, uint32_t length,
+        uint_fast8_t pattern)
+{
+    uint32_t memoryPattern, addr, otpOffset;
+    uint_fast8_t memoryType;
+
+    ASSERT(pattern == FLASH_0_PATTERN || pattern == FLASH_1_PATTERN);
+
+    addr = (uint32_t) verifyAddr;
+    memoryPattern = (pattern == FLASH_1_PATTERN) ? 0xFFFFFFFF : 0;
+    memoryType = (addr > __MAIN_MEMORY_END__) ? FLASH_INFO_SPACE : FLASH_MAIN_SPACE;
+
+    /* Taking care of byte accesses */
+    while ((addr & 0x03) && (length > 0))
+    {
+        if (HWREG8(addr++) != ((uint8_t) memoryPattern))
+            return false;
+        length--;
+    }
+
+    /* Making sure we are aligned by 128-bit address */
+    while (((addr & 0x0F)) && (length > 3))
+    {
+        if (HWREG32(addr) != memoryPattern)
+            return false;
+
+        addr = addr + 4;
+        length = length - 4;
+    }
+
+    /* Burst Verify */
+    if (length > 63)
+    {
+
+        /* Setting/clearing INFO flash flags as appropriate */
+        if (addr > __MAIN_MEMORY_END__)
+        {
+            FLCTL->rRDBRST_CTLSTAT.r = (FLCTL->rRDBRST_CTLSTAT.r
+                    & ~FLCTL_RDBRST_CTLSTAT_MEM_TYPE_M)
+                    | FLCTL_RDBRST_CTLSTAT_MEM_TYPE_1;
+            otpOffset = 0x00200000;
+        } else
+        {
+            FLCTL->rRDBRST_CTLSTAT.r = (FLCTL->rRDBRST_CTLSTAT.r
+                    & ~FLCTL_RDBRST_CTLSTAT_MEM_TYPE_M)
+                    | FLCTL_RDBRST_CTLSTAT_MEM_TYPE_0;
+            otpOffset = __MAIN_MEMORY_START__;
+        }
+
+        /* Clearing any lingering fault flags  and preparing burst verify*/
+        BITBAND_PERI(FLCTL->rRDBRST_CTLSTAT.r, FLCTL_RDBRST_CTLSTAT_CLR_STAT_OFS) =
+                1;
+        FLCTL->rRDBRST_FAILCNT.r = 0;
+        FLCTL->rRDBRST_STARTADDR.r = addr - otpOffset;
+        FLCTL->rRDBRST_LEN.r = (length & 0xFFFFFFF0);
+        addr += FLCTL->rRDBRST_LEN.r;
+        length = length & 0xF;
+
+        /* Starting Burst Verify */
+        FLCTL->rRDBRST_CTLSTAT.r = (FLCTL_RDBRST_CTLSTAT_STOP_FAIL | pattern
+                | memoryType | FLCTL_RDBRST_CTLSTAT_START);
+
+        /* While the burst read hasn't finished */
+        while ((FLCTL->rRDBRST_CTLSTAT.r & FLCTL_RDBRST_CTLSTAT_BRST_STAT_M)
+                != FLCTL_RDBRST_CTLSTAT_BRST_STAT_3)
+        {
+            __no_operation();
+        }
+
+        /* Checking  for a verification/access error/failure */
+        if (BITBAND_PERI(FLCTL->rRDBRST_CTLSTAT.r,
+                FLCTL_RDBRST_CTLSTAT_CMP_ERR_OFS)
+                || BITBAND_PERI(FLCTL->rRDBRST_CTLSTAT.r,
+                        FLCTL_RDBRST_CTLSTAT_ADDR_ERR_OFS)
+                || FLCTL->rRDBRST_FAILCNT.r)
+        {
+            /* Clearing the Read Burst flag and returning */
+            BITBAND_PERI(FLCTL->rRDBRST_CTLSTAT.r, FLCTL_RDBRST_CTLSTAT_CLR_STAT_OFS) =
+                    1;
+            return false;
+        }
+
+        /* Clearing the Read Burst flag */
+        BITBAND_PERI(FLCTL->rRDBRST_CTLSTAT.r, FLCTL_RDBRST_CTLSTAT_CLR_STAT_OFS) =
+                1;
+
+    }
+
+    /* Remaining Words */
+    while (length > 3)
+    {
+        if (HWREG32(addr) != memoryPattern)
+            return false;
+
+        addr = addr + 4;
+        length = length - 4;
+    }
+
+    /* Remaining Bytes */
+    while (length > 0)
+    {
+        if (HWREG8(addr++) != ((uint8_t) memoryPattern))
+            return false;
+        length--;
+    }
+
+    return true;
+}
+
+bool FlashCtl_setReadMode(uint32_t flashBank, uint32_t readMode)
+{
+
+    if (FLCTL->rPOWER_STAT.r & FLCTL_POWER_STAT_RD_2T)
+        return false;
+
+    if (flashBank == FLASH_BANK0)
+    {
+        FLCTL->rBANK0_RDCTL.r = (FLCTL->rBANK0_RDCTL.r
+                & ~FLCTL_BANK0_RDCTL_RD_MODE_M) | readMode;
+        while (FLCTL->rBANK0_RDCTL.b.bRD_MODE != readMode)
+            ;
+    } else if (flashBank == FLASH_BANK1)
+    {
+        FLCTL->rBANK1_RDCTL.r = (FLCTL->rBANK1_RDCTL.r
+                & ~FLCTL_BANK1_RDCTL_RD_MODE_M) | readMode;
+        while (FLCTL->rBANK1_RDCTL.b.bRD_MODE != readMode)
+            ;
+    } else
+    {
+        ASSERT(false);
+        return false;
+    }
+
+    return true;
+}
+
+uint32_t FlashCtl_getReadMode(uint32_t flashBank)
+{
+    if (flashBank == FLASH_BANK0)
+    {
+        return FLCTL->rBANK0_RDCTL.b.bRD_MODE;
+    } else if (flashBank == FLASH_BANK1)
+    {
+        return FLCTL->rBANK1_RDCTL.b.bRD_MODE;
+    } else
+    {
+        ASSERT(false);
+        return 0;
+    }
+}
+
+bool FlashCtl_performMassErase(void)
+{
+    uint32_t userFlash, ii, jj, sector;
+
+    /* Trying a mass erase in ROM first. If it fails (should be rare), going
+     * through and erasing each sector one-by-one
+     */
+    if (!FlashInternal_performMassErase(true))
+    {
+        userFlash = SysCtl_getFlashSize() / 2;
+
+        for (ii = __MAIN_MEMORY_START__; ii < userFlash; ii += 4096)
+        {
+            sector = getUserFlashSector(ii);
+
+            if (!((FLCTL->rBANK0_MAIN_WEPROT.r) & sector))
+            {
+                for (jj = 1; jj < MAX_ERASE_TRIES; jj++)
+                {
+                    if (FlashInternal_eraseSector(ii, true))
+                    {
+                        break;
+                    }
+                }
+
+                if (jj == MAX_ERASE_TRIES)
+                    return false;
+            }
+
+            if (!(FLCTL->rBANK1_MAIN_WEPROT.r & sector))
+            {
+                for (jj = 1; jj < MAX_ERASE_TRIES; jj++)
+                {
+                    if (FlashInternal_eraseSector(ii + userFlash, true))
+                    {
+                        break;
+                    }
+                }
+
+                if (jj == MAX_ERASE_TRIES)
+                    return false;
+            }
+
+            if (sector < FLCTL_BANK0_MAIN_WEPROT_PROT2)
+            {
+                if (!(FLCTL->rBANK0_INFO_WEPROT.r & sector))
+                {
+                    for (jj = 1; jj < MAX_ERASE_TRIES; jj++)
+                    {
+                        if (FlashInternal_eraseSector(ii + __BSL_MEMORY_START__,
+                        true))
+                        {
+                            break;
+                        }
+                    }
+
+                    if (jj == MAX_ERASE_TRIES)
+                        return false;
+                }
+
+                if (!(FLCTL->rBANK1_INFO_WEPROT.r & sector))
+                {
+
+                    for (jj = 1; jj < MAX_ERASE_TRIES; jj++)
+                    {
+
+                        if (FlashInternal_eraseSector(
+                                ii + __BSL_MEMORY_START__ + 0x2000, true))
+                        {
+                            break;
+                        }
+                    }
+
+                    if (jj == MAX_ERASE_TRIES)
+                        return false;
+                }
+
+            }
+        }
+    }
+
+    return true;
+}
+
+bool FlashCtl_eraseSector(uint32_t addr)
+{
+    uint32_t ii;
+
+    for(ii=0;ii<MAX_ERASE_TRIES;ii++)
+    {
+        if(FlashInternal_eraseSector(addr, true))
+        {
+            return true;
+        }
+    }
+
+    return false;
+}
+
+bool FlashCtl_programMemory(void* src, void* dest, uint32_t length)
+{
+    uint32_t destAddr, srcAddr;
+    bool res;
+
+    /* Casting to integers */
+    srcAddr = (uint32_t)src;
+    destAddr = (uint32_t)dest;
+
+    /* Enabling word programming */
+    FlashCtl_enableWordProgramming(FLASH_IMMEDIATE_WRITE_MODE);
+
+    /* Assume failure */
+    res = false;
+
+    /* Taking care of byte accesses */
+    while ((destAddr & 0x03) && length > 0)
+    {
+        if(!_FlashCtl_Program8(srcAddr,destAddr))
+        {
+            goto FlashProgramCleanUp;
+        }
+        else
+        {
+            srcAddr++;
+            destAddr++;
+            length--;
+        }
+    }
+
+    /* Taking care of word accesses */
+    while ((destAddr & 0x0F) && (length > 3))
+    {
+        if (!_FlashCtl_Program32(srcAddr, destAddr))
+        {
+            goto FlashProgramCleanUp;
+        }
+        else
+        {
+            srcAddr += 4;
+            destAddr += 4;
+            length -= 4;
+        }
+    }
+
+    /* Remaining byte accesses */
+    while (length > 0)
+    {
+        if(!_FlashCtl_Program8(srcAddr,destAddr))
+        {
+            goto FlashProgramCleanUp;
+        }
+        else
+        {
+            srcAddr++;
+            destAddr++;
+            length--;
+        }
+    }
+
+    /* If we got this far that means that we succeeded  */
+    res = true;
+
+FlashProgramCleanUp:
+    FlashCtl_disableWordProgramming();
+    return res;
+
+}
+
+void FlashCtl_setProgramVerification(uint32_t verificationSetting)
+{
+    if ((verificationSetting & FLASH_BURSTPOST))
+        BITBAND_PERI(FLCTL->rPRGBRST_CTLSTAT.r, FLCTL_PRGBRST_CTLSTAT_AUTO_PST_OFS) =
+                1;
+
+    if ((verificationSetting & FLASH_BURSTPRE))
+        BITBAND_PERI(FLCTL->rPRGBRST_CTLSTAT.r, FLCTL_PRGBRST_CTLSTAT_AUTO_PRE_OFS) =
+                1;
+
+    if ((verificationSetting & FLASH_REGPRE))
+        BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_VER_PRE_OFS) = 1;
+
+    if ((verificationSetting & FLASH_REGPOST))
+        BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_VER_PST_OFS) = 1;
+}
+
+void FlashCtl_clearProgramVerification(uint32_t verificationSetting)
+{
+    if ((verificationSetting & FLASH_BURSTPOST))
+        BITBAND_PERI(FLCTL->rPRGBRST_CTLSTAT.r, FLCTL_PRGBRST_CTLSTAT_AUTO_PST_OFS) =
+                0;
+
+    if ((verificationSetting & FLASH_BURSTPRE))
+        BITBAND_PERI(FLCTL->rPRGBRST_CTLSTAT.r, FLCTL_PRGBRST_CTLSTAT_AUTO_PRE_OFS) =
+                0;
+
+    if ((verificationSetting & FLASH_REGPRE))
+        BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_VER_PRE_OFS) = 0;
+
+    if ((verificationSetting & FLASH_REGPOST))
+        BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_VER_PST_OFS) = 0;
+
+}
+
+void FlashCtl_enableWordProgramming(uint32_t mode)
+{
+    if (mode == FLASH_IMMEDIATE_WRITE_MODE)
+    {
+        BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_ENABLE_OFS) = 1;
+        BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_MODE_OFS) = 0;
+
+    } else if (mode == FLASH_COLLATED_WRITE_MODE)
+    {
+        BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_ENABLE_OFS) = 1;
+        BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_MODE_OFS) = 1;
+    }
+}
+
+void FlashCtl_disableWordProgramming(void)
+{
+    BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_ENABLE_OFS) = 0;
+}
+
+uint32_t FlashCtl_isWordProgrammingEnabled(void)
+{
+    if (!BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_ENABLE_OFS))
+    {
+        return 0;
+    } else if (BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_MODE_OFS))
+        return FLASH_COLLATED_WRITE_MODE;
+    else
+        return FLASH_IMMEDIATE_WRITE_MODE;
+}
+
+void FlashCtl_setWaitState(uint32_t flashBank, uint32_t waitState)
+{
+    if (flashBank == FLASH_BANK0)
+    {
+        FLCTL->rBANK0_RDCTL.r =
+                (FLCTL->rBANK0_RDCTL.r & ~FLCTL_BANK0_RDCTL_WAIT_M)
+                        | (waitState << 12);
+    } else if (flashBank == FLASH_BANK1)
+    {
+        FLCTL->rBANK1_RDCTL.r =
+                (FLCTL->rBANK1_RDCTL.r & ~FLCTL_BANK1_RDCTL_WAIT_M)
+                        | (waitState << 12);
+    } else
+    {
+        ASSERT(false);
+    }
+}
+
+uint32_t FlashCtl_getWaitState(uint32_t flashBank)
+{
+    if (flashBank == FLASH_BANK0)
+    {
+        return FLCTL->rBANK0_RDCTL.b.bWAIT;
+    } else if (flashBank == FLASH_BANK1)
+    {
+        return FLCTL->rBANK1_RDCTL.b.bWAIT;
+    } else
+    {
+        ASSERT(false);
+        return 0;
+    }
+}
+
+void FlashCtl_enableInterrupt(uint32_t flags)
+{
+    FLCTL->rIE.r |= flags;
+}
+
+void FlashCtl_disableInterrupt(uint32_t flags)
+{
+    FLCTL->rIE.r &= ~flags;
+}
+
+uint32_t FlashCtl_getInterruptStatus(void)
+{
+    return FLCTL->rIFG.r;
+}
+
+uint32_t FlashCtl_getEnabledInterruptStatus(void)
+{
+    return FlashCtl_getInterruptStatus() & FLCTL->rIE.r;
+}
+
+void FlashCtl_clearInterruptFlag(uint32_t flags)
+{
+    FLCTL->rCLRIFG.r |= flags;
+}
+
+void FlashCtl_registerInterrupt(void (*intHandler)(void))
+{
+    //
+    // Register the interrupt handler, returning an error if an error occurs.
+    //
+    Interrupt_registerInterrupt(INT_FLCTL, intHandler);
+
+    //
+    // Enable the system control interrupt.
+    //
+    Interrupt_enableInterrupt(INT_FLCTL);
+}
+
+void FlashCtl_unregisterInterrupt(void)
+{
+    //
+    // Disable the interrupt.
+    //
+    Interrupt_disableInterrupt(INT_FLCTL);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    Interrupt_unregisterInterrupt(INT_FLCTL);
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/flash.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/flash.h
new file mode 100644
index 000000000..41d50ae0b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/flash.h
@@ -0,0 +1,813 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __FLASH_H__
+#define __FLASH_H__
+
+//*****************************************************************************
+//
+//! \addtogroup flash_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <msp.h>
+#include <stdbool.h>
+
+//*****************************************************************************
+//
+// Control specific variables
+//
+//*****************************************************************************
+#define FLASH_BURST_PRG_BIT 0x03
+
+/* Interrupts */
+#define FLASH_PROGRAM_ERROR         FLCTL_IFG_PRG_ERR
+#define FLASH_BENCHMARK_INT         FLCTL_IFG_BMRK
+#define FLASH_ERASE_COMPLETE        FLCTL_IFG_ERASE
+#define FLASH_BRSTPRGM_COMPLETE     FLCTL_IFG_PRGB
+#define FLASH_WRDPRGM_COMPLETE      FLCTL_IFG_PRG
+#define FLASH_POSTVERIFY_FAILED     FLCTL_IFG_AVPST
+#define FLASH_PREVERIFY_FAILED      FLCTL_IFG_AVPRE
+#define FLASH_BRSTRDCMP_COMPLETE    FLCTL_IFG_RDBRST
+
+#define FLASH_NORMAL_READ_MODE            FLCTL_BANK0_RDCTL_RD_MODE_0
+#define FLASH_MARGIN0_READ_MODE           FLCTL_BANK0_RDCTL_RD_MODE_1
+#define FLASH_MARGIN1_READ_MODE           FLCTL_BANK0_RDCTL_RD_MODE_2
+#define FLASH_PROGRAM_VERIFY_READ_MODE    FLCTL_BANK0_RDCTL_RD_MODE_3
+#define FLASH_ERASE_VERIFY_READ_MODE      FLCTL_BANK0_RDCTL_RD_MODE_4
+#define FLASH_LEAKAGE_VERIFY_READ_MODE    FLCTL_BANK0_RDCTL_RD_MODE_5
+#define FLASH_MARGIN0B_READ_MODE          FLCTL_BANK0_RDCTL_RD_MODE_9
+#define FLASH_MARGIN1B_READ_MODE          FLCTL_BANK0_RDCTL_RD_MODE_10
+
+#define FLASH_PRGBRSTCTLSTAT_BURSTSTATUS_COMPLETE 0x70000
+
+#define FLASH_BANK0                 0x00
+#define FLASH_BANK1                 0x01
+#define FLASH_DATA_READ             0x00
+#define FLASH_INSTRUCTION_FETCH     0x01
+
+#define FLASH_MAIN_MEMORY_SPACE_BANK0     0x01
+#define FLASH_MAIN_MEMORY_SPACE_BANK1     0x02
+#define FLASH_INFO_MEMORY_SPACE_BANK0      0x03
+#define FLASH_INFO_MEMORY_SPACE_BANK1      0x04
+
+#define FLASH_MAIN_SPACE    FLCTL_RDBRST_CTLSTAT_MEM_TYPE_0
+#define FLASH_INFO_SPACE    FLCTL_RDBRST_CTLSTAT_MEM_TYPE_1
+#define FLASH_1_PATTERN FLCTL_RDBRST_CTLSTAT_DATA_CMP
+#define FLASH_0_PATTERN 0x00
+
+#define FLASH_SECTOR0               FLCTL_BANK0_MAIN_WEPROT_PROT0
+#define FLASH_SECTOR1               FLCTL_BANK0_MAIN_WEPROT_PROT1
+#define FLASH_SECTOR2               FLCTL_BANK0_MAIN_WEPROT_PROT2
+#define FLASH_SECTOR3               FLCTL_BANK0_MAIN_WEPROT_PROT3
+#define FLASH_SECTOR4               FLCTL_BANK0_MAIN_WEPROT_PROT4
+#define FLASH_SECTOR5               FLCTL_BANK0_MAIN_WEPROT_PROT5
+#define FLASH_SECTOR6               FLCTL_BANK0_MAIN_WEPROT_PROT6
+#define FLASH_SECTOR7               FLCTL_BANK0_MAIN_WEPROT_PROT7
+#define FLASH_SECTOR8               FLCTL_BANK0_MAIN_WEPROT_PROT8
+#define FLASH_SECTOR9               FLCTL_BANK0_MAIN_WEPROT_PROT9
+#define FLASH_SECTOR10              FLCTL_BANK0_MAIN_WEPROT_PROT10
+#define FLASH_SECTOR11              FLCTL_BANK0_MAIN_WEPROT_PROT11
+#define FLASH_SECTOR12              FLCTL_BANK0_MAIN_WEPROT_PROT12
+#define FLASH_SECTOR13              FLCTL_BANK0_MAIN_WEPROT_PROT13
+#define FLASH_SECTOR14              FLCTL_BANK0_MAIN_WEPROT_PROT14
+#define FLASH_SECTOR15              FLCTL_BANK0_MAIN_WEPROT_PROT15
+#define FLASH_SECTOR16              FLCTL_BANK0_MAIN_WEPROT_PROT16
+#define FLASH_SECTOR17              FLCTL_BANK0_MAIN_WEPROT_PROT17
+#define FLASH_SECTOR18              FLCTL_BANK0_MAIN_WEPROT_PROT18
+#define FLASH_SECTOR19              FLCTL_BANK0_MAIN_WEPROT_PROT19
+#define FLASH_SECTOR20              FLCTL_BANK0_MAIN_WEPROT_PROT20
+#define FLASH_SECTOR21              FLCTL_BANK0_MAIN_WEPROT_PROT21
+#define FLASH_SECTOR22              FLCTL_BANK0_MAIN_WEPROT_PROT22
+#define FLASH_SECTOR23              FLCTL_BANK0_MAIN_WEPROT_PROT23
+#define FLASH_SECTOR24              FLCTL_BANK0_MAIN_WEPROT_PROT24
+#define FLASH_SECTOR25              FLCTL_BANK0_MAIN_WEPROT_PROT25
+#define FLASH_SECTOR26              FLCTL_BANK0_MAIN_WEPROT_PROT26
+#define FLASH_SECTOR27              FLCTL_BANK0_MAIN_WEPROT_PROT27
+#define FLASH_SECTOR28              FLCTL_BANK0_MAIN_WEPROT_PROT28
+#define FLASH_SECTOR29              FLCTL_BANK0_MAIN_WEPROT_PROT29
+#define FLASH_SECTOR30              FLCTL_BANK0_MAIN_WEPROT_PROT30
+#define FLASH_SECTOR31              FLCTL_BANK0_MAIN_WEPROT_PROT31
+
+#define FLASH_NOVER     0
+#define FLASH_BURSTPOST FLCTL_PRGBRST_CTLSTAT_AUTO_PST
+#define FLASH_BURSTPRE FLCTL_PRGBRST_CTLSTAT_AUTO_PRE
+#define FLASH_REGPRE FLCTL_PRG_CTLSTAT_VER_PRE
+#define FLASH_REGPOST FLCTL_PRG_CTLSTAT_VER_PST
+#define FLASH_FULLVER (FLCTL_PRGBRST_CTLSTAT_AUTO_PST |                        \
+                    FLCTL_PRGBRST_CTLSTAT_AUTO_PRE | FLCTL_PRG_CTLSTAT_VER_PRE \
+                    | FLCTL_PRG_CTLSTAT_VER_PST)
+
+#define FLASH_COLLATED_WRITE_MODE  0x01
+#define FLASH_IMMEDIATE_WRITE_MODE 0x02
+
+#define FlashInternal_eraseSector                                              \
+        ((bool (*)(uint32_t addr,                                              \
+                   bool verify))ROM_FLASHCTLTABLE[9])
+
+#define FlashInternal_performMassErase                                         \
+        ((bool (*)(bool verify))ROM_FLASHCTLTABLE[8])
+
+
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+//*****************************************************************************
+//
+//! Enables read buffering on accesses to a specified bank of flash memory
+//!
+//! \param memoryBank is the value of the memory bank to enable read
+//!  buffering. Must be only one of the following values:
+//!  - \b FLASH_BANK0,
+//!  - \b FLASH_BANK1
+//!
+//! \param accessMethod is the value of the access type to enable read
+//!  buffering. Must be only one of the following values:
+//!  - \b FLASH_DATA_READ,
+//!  - \b FLASH_INSTRUCTION_FETCH
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FlashCtl_enableReadBuffering(uint_fast8_t memoryBank,
+        uint_fast8_t accessMethod);
+
+//*****************************************************************************
+//
+//! Disables read buffering on accesses to a specified bank of flash memory
+//!
+//! \param memoryBank is the value of the memory bank to disable read
+//!  buffering. Must be only one of the following values:
+//!  - \b FLASH_BANK0,
+//!  - \b FLASH_BANK1
+//!
+//! \param accessMethod is the value of the access type to disable read
+//!  buffering. Must ne only one of the following values:
+//!  - \b FLASH_DATA_READ,
+//!  - \b FLASH_INSTRUCTION_FETCH
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FlashCtl_disableReadBuffering(uint_fast8_t memoryBank,
+        uint_fast8_t accessMethod);
+
+//*****************************************************************************
+//
+//! Disables program protection on the given sector mask. This setting can be
+//! applied on a sector-wise bases on a given memory space (INFO or MAIN).
+//!
+//! \param memorySpace is the value of the memory bank to disable program
+//!  protection. Must be only one of the following values:
+//!  - \b FLASH_MAIN_MEMORY_SPACE_BANK0,
+//!  - \b FLASH_MAIN_MEMORY_SPACE_BANK1,
+//!  - \b FLASH_INFO_MEMORY_SPACE_BANK0,
+//!  - \b FLASH_INFO_MEMORY_SPACE_BANK1
+//!
+//! \param sectorMask is a bit mask of the sectors to disable program
+//!  protection. Must be a bitfield of the following values:
+//!  - \b FLASH_SECTOR0,
+//!  - \b FLASH_SECTOR1,
+//!  - \b FLASH_SECTOR2,
+//!  - \b FLASH_SECTOR3,
+//!  - \b FLASH_SECTOR4,
+//!  - \b FLASH_SECTOR5,
+//!  - \b FLASH_SECTOR6,
+//!  - \b FLASH_SECTOR7,
+//!  - \b FLASH_SECTOR8,
+//!  - \b FLASH_SECTOR9,
+//!  - \b FLASH_SECTOR10,
+//!  - \b FLASH_SECTOR11,
+//!  - \b FLASH_SECTOR12,
+//!  - \b FLASH_SECTOR13,
+//!  - \b FLASH_SECTOR14,
+//!  - \b FLASH_SECTOR15,
+//!  - \b FLASH_SECTOR16,
+//!  - \b FLASH_SECTOR17,
+//!  - \b FLASH_SECTOR18,
+//!  - \b FLASH_SECTOR19,
+//!  - \b FLASH_SECTOR20,
+//!  - \b FLASH_SECTOR21,
+//!  - \b FLASH_SECTOR22,
+//!  - \b FLASH_SECTOR23,
+//!  - \b FLASH_SECTOR24,
+//!  - \b FLASH_SECTOR25,
+//!  - \b FLASH_SECTOR26,
+//!  - \b FLASH_SECTOR27,
+//!  - \b FLASH_SECTOR28,
+//!  - \b FLASH_SECTOR29,
+//!  - \b FLASH_SECTOR30,
+//!  - \b FLASH_SECTOR31
+//!
+//!  \note Flash sector sizes are 4KB and the number of sectors may vary
+//!  depending on the specific device. Also, for INFO memory space, only sectors
+//!  \b FLASH_SECTOR0 and \b FLASH_SECTOR1 will exist.
+//!
+//! \return true if sector protection disabled false otherwise.
+//
+//*****************************************************************************
+extern bool FlashCtl_unprotectSector(uint_fast8_t memorySpace,
+        uint32_t sectorMask);
+
+//*****************************************************************************
+//
+//! Enables program protection on the given sector mask. This setting can be
+//! applied on a sector-wise bases on a given memory space (INFO or MAIN).
+//!
+//! \param memorySpace is the value of the memory bank to enable program
+//!  protection. Must be only one of the following values:
+//!  - \b FLASH_MAIN_MEMORY_SPACE_BANK0,
+//!  - \b FLASH_MAIN_MEMORY_SPACE_BANK1,
+//!  - \b FLASH_INFO_MEMORY_SPACE_BANK0,
+//!  - \b FLASH_INFO_MEMORY_SPACE_BANK1
+//!
+//! \param sectorMask is a bit mask of the sectors to enable program
+//!  protection. Must be a bitfield of the following values:
+//!  - \b FLASH_SECTOR0,
+//!  - \b FLASH_SECTOR1,
+//!  - \b FLASH_SECTOR2,
+//!  - \b FLASH_SECTOR3,
+//!  - \b FLASH_SECTOR4,
+//!  - \b FLASH_SECTOR5,
+//!  - \b FLASH_SECTOR6,
+//!  - \b FLASH_SECTOR7,
+//!  - \b FLASH_SECTOR8,
+//!  - \b FLASH_SECTOR9,
+//!  - \b FLASH_SECTOR10,
+//!  - \b FLASH_SECTOR11,
+//!  - \b FLASH_SECTOR12,
+//!  - \b FLASH_SECTOR13,
+//!  - \b FLASH_SECTOR14,
+//!  - \b FLASH_SECTOR15,
+//!  - \b FLASH_SECTOR16,
+//!  - \b FLASH_SECTOR17,
+//!  - \b FLASH_SECTOR18,
+//!  - \b FLASH_SECTOR19,
+//!  - \b FLASH_SECTOR20,
+//!  - \b FLASH_SECTOR21,
+//!  - \b FLASH_SECTOR22,
+//!  - \b FLASH_SECTOR23,
+//!  - \b FLASH_SECTOR24,
+//!  - \b FLASH_SECTOR25,
+//!  - \b FLASH_SECTOR26,
+//!  - \b FLASH_SECTOR27,
+//!  - \b FLASH_SECTOR28,
+//!  - \b FLASH_SECTOR29,
+//!  - \b FLASH_SECTOR30,
+//!  - \b FLASH_SECTOR31
+//!
+//!  \note Flash sector sizes are 4KB and the number of sectors may vary
+//!  depending on the specific device. Also, for INFO memory space, only sectors
+//!  \b FLASH_SECTOR0 and \b FLASH_SECTOR1 will exist.
+//!
+//! \return true if sector protection enabled false otherwise.
+//
+//*****************************************************************************
+extern bool FlashCtl_protectSector(uint_fast8_t memorySpace,
+        uint32_t sectorMask);
+
+//*****************************************************************************
+//
+//! Returns the sector protection for given sector mask and memory space
+//!
+//! \param memorySpace is the value of the memory bank to check for program
+//!  protection. Must be only one of the following values:
+//!  - \b FLASH_MAIN_MEMORY_SPACE_BANK0,
+//!  - \b FLASH_MAIN_MEMORY_SPACE_BANK1,
+//!  - \b FLASH_INFO_MEMORY_SPACE_BANK0,
+//!  - \b FLASH_INFO_MEMORY_SPACE_BANK1
+//!
+//! \param sector is the sector to check for program protection.
+//!  Must be one of the following values:
+//!  - \b FLASH_SECTOR0,
+//!  - \b FLASH_SECTOR1,
+//!  - \b FLASH_SECTOR2,
+//!  - \b FLASH_SECTOR3,
+//!  - \b FLASH_SECTOR4,
+//!  - \b FLASH_SECTOR5,
+//!  - \b FLASH_SECTOR6,
+//!  - \b FLASH_SECTOR7,
+//!  - \b FLASH_SECTOR8,
+//!  - \b FLASH_SECTOR9,
+//!  - \b FLASH_SECTOR10,
+//!  - \b FLASH_SECTOR11,
+//!  - \b FLASH_SECTOR12,
+//!  - \b FLASH_SECTOR13,
+//!  - \b FLASH_SECTOR14,
+//!  - \b FLASH_SECTOR15,
+//!  - \b FLASH_SECTOR16,
+//!  - \b FLASH_SECTOR17,
+//!  - \b FLASH_SECTOR18,
+//!  - \b FLASH_SECTOR19,
+//!  - \b FLASH_SECTOR20,
+//!  - \b FLASH_SECTOR21,
+//!  - \b FLASH_SECTOR22,
+//!  - \b FLASH_SECTOR23,
+//!  - \b FLASH_SECTOR24,
+//!  - \b FLASH_SECTOR25,
+//!  - \b FLASH_SECTOR26,
+//!  - \b FLASH_SECTOR27,
+//!  - \b FLASH_SECTOR28,
+//!  - \b FLASH_SECTOR29,
+//!  - \b FLASH_SECTOR30,
+//!  - \b FLASH_SECTOR31
+//!
+//!  Note that flash sector sizes are 4KB and the number of sectors may vary
+//!  depending on the specific device. Also, for INFO memory space, only sectors
+//!  FLASH_SECTOR0 and FLASH_SECTOR1 will exist.
+//!
+//! \return true if sector protection enabled false otherwise.
+//
+//*****************************************************************************
+extern bool FlashCtl_isSectorProtected(uint_fast8_t memorySpace,
+        uint32_t sector);
+
+//*****************************************************************************
+//
+//! Verifies a given segment of memory based off either a high (1) or low (0)
+//! state.
+//!
+//! \param verifyAddr Start address where verification will begin
+//!
+//! \param length Length in bytes to verify based off the pattern
+//!
+//! \param pattern The pattern which verification will check versus. This can
+//!  either be a low pattern (each register will be checked versus a pattern
+//!  of 32 zeros, or a high pattern (each register will be checked versus a
+//!  pattern of 32 ones). Valid values are: FLASH_0_PATTERN, FLASH_1_PATTERN
+//!
+//!  Note that there are no sector/boundary restrictions for this function,
+//!  however it is encouraged to proved a start address aligned on 32-bit
+//!  boundaries.  Providing an unaligned address will result in unaligned data
+//!  accesses and detriment efficiency.
+//!
+//! Note that this function is blocking and will not exit until operation has
+//! either completed or failed due to an error.
+//!
+//! \return true if memory verification is successful, false otherwise.
+//
+//*****************************************************************************
+extern bool FlashCtl_verifyMemory(void* verifyAddr, uint32_t length,
+        uint_fast8_t pattern);
+
+//*****************************************************************************
+//
+//!  Performs a mass erase on all unprotected flash sectors. Protected sectors
+//!  are ignored.
+//!
+//! \note This function is blocking and will not exit until operation has
+//! either completed or failed due to an error.
+//!
+//! \return true if mass erase completes successfully, false otherwise
+//
+//*****************************************************************************
+extern bool FlashCtl_performMassErase(void);
+
+//*****************************************************************************
+//
+//! Erases a sector of MAIN or INFO flash memory.
+//!
+//! \param addr The start of the sector to erase. Note that with flash,
+//!         the minimum allowed size that can be erased is a flash sector
+//!         (which is 4KB on the MSP432 family). If an address is provided to
+//!         this function which is not on a 4KB boundary, the entire sector
+//!         will still be erased.
+//!
+//! Note that this function is blocking and will not exit until operation has
+//! either completed or failed due to an error.
+//!
+//! \return true if sector erase is successful, false otherwise.
+//
+//*****************************************************************************
+extern bool FlashCtl_eraseSector(uint32_t addr);
+
+//*****************************************************************************
+//
+//! Program a portion of flash memory with the provided data
+//!
+//! \param src Pointer to the data source to program into flash
+//!
+//! \param dest Pointer to the destination in flash to program
+//!
+//! \param length Length in bytes to program
+//!
+//!  \note There are no sector/boundary restrictions for this function,
+//!  however it is encouraged to proved a start address aligned on 32-bit
+//!  boundaries.  Providing an unaligned address will result in unaligned data
+//!  accesses and detriment efficiency.
+//!
+//! Note that this function is blocking and will not exit until operation has
+//! either completed or failed due to an error.
+//!
+//! \return Whether or not the program succeeded
+//
+//*****************************************************************************
+extern bool FlashCtl_programMemory(void* src, void* dest, uint32_t length);
+
+//*****************************************************************************
+//
+//! Setups pre/post verification of burst and regular flash programming
+//! instructions. Note that this API is for advanced users that are programming
+//! their own flash drivers. The program/erase APIs are not affected by this
+//! setting and take care of the verification requirements.
+//!
+//! \param verificationSetting Verification setting to set. This value can
+//!  be a bitwise OR of the following values:
+//!     - \b FLASH_BURSTPOST,
+//!     - \b FLASH_BURSTPRE,
+//!     - \b FLASH_REGPRE,
+//!     - \b FLASH_REGPOST
+//!     - \b FLASH_NOVER No verification enabled
+//!     - \b FLASH_FULLVER Full verification enabled
+//!
+//! \return none
+//
+//*****************************************************************************
+extern void FlashCtl_setProgramVerification(uint32_t verificationSetting);
+
+//*****************************************************************************
+//
+//! Clears pre/post verification of burst and regular flash programming
+//! instructions. Note that this API is for advanced users that are programming
+//! their own flash drivers. The program/erase APIs are not affected by this
+//! setting and take care of the verification requirements.
+//!
+//! \param verificationSetting Verification setting to clear. This value can
+//!  be a bitwise OR of the following values:
+//!     - \b FLASH_BURSTPOST,
+//!     - \b FLASH_BURSTPRE,
+//!     - \b FLASH_REGPRE,
+//!     - \b FLASH_REGPOST
+//!     - \b FLASH_NOVER No verification enabled
+//!     - \b FLASH_FULLVER Full verification enabled
+//!
+//! \return none
+//
+//*****************************************************************************
+extern void FlashCtl_clearProgramVerification(uint32_t verificationSetting);
+
+//*****************************************************************************
+//
+//! Enables  word programming of flash memory.
+//!
+//! This function will enable word programming of the flash memory and set the
+//! mode of behavior when the flash write occurs.
+//!
+//! \param mode The mode specifies the behavior of the flash controller when
+//!        programming words to flash. In \b FLASH_IMMEDIATE_WRITE_MODE, the
+//!        program operation happens immediately on the write to flash while
+//!        in \b FLASH_COLLATED_WRITE_MODE the write will be delayed until a full
+//!        128-bits have been collated. Possible values include:
+//!             - \b FLASH_IMMEDIATE_WRITE_MODE
+//!             - \b FLASH_COLLATED_WRITE_MODE
+//!
+//!
+//! Refer to the user's guide for further documentation.
+//!
+//! \return none
+//
+//*****************************************************************************
+extern void FlashCtl_enableWordProgramming(uint32_t mode);
+
+//*****************************************************************************
+//
+//! Disables  word programming of flash memory.
+//!
+//! Refer to FlashCtl_enableWordProgramming and the user's guide for description
+//! on the difference between full word and immediate programming
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FlashCtl_disableWordProgramming(void);
+
+//*****************************************************************************
+//
+//! Returns if word programming mode is enabled (and if it is, the specific mode)
+//!
+//! Refer to FlashCtl_enableWordProgramming and the user's guide for description
+//! on the difference between full word and immediate programming
+//!
+//! \return a zero value if word programming is disabled,
+//!             - \b FLASH_IMMEDIATE_WRITE_MODE
+//!             - \b FLASH_COLLATED_WRITE_MODE
+//!
+//
+//*****************************************************************************
+extern uint32_t FlashCtl_isWordProgrammingEnabled(void);
+
+//*****************************************************************************
+//
+//!  Sets the flash read mode to be used by default flash read operations.
+//!  Note that the proper wait states must be set prior to entering this
+//!   function.
+//!
+//! \param flashBank Flash bank to set read mode for. Valid values are:
+//!         - \b FLASH_BANK0
+//!         - \b FLASH_BANK1
+//!
+//! \param readMode The read mode to set. Valid values are:
+//!  - \b FLASH_NORMAL_READ_MODE,
+//!  - \b FLASH_MARGIN0_READ_MODE,
+//!  - \b FLASH_MARGIN1_READ_MODE,
+//!  - \b FLASH_PROGRAM_VERIFY_READ_MODE,
+//!  - \b FLASH_ERASE_VERIFY_READ_MODE,
+//!  - \b FLASH_LEAKAGE_VERIFY_READ_MODE,
+//!  - \b FLASH_MARGIN0B_READ_MODE,
+//!  - \b FLASH_MARGIN1B_READ_MODE
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern bool FlashCtl_setReadMode(uint32_t flashBank, uint32_t readMode);
+
+//*****************************************************************************
+//
+//!  Gets the flash read mode to be used by default flash read operations.
+//!
+//! \param flashBank Flash bank to set read mode for. Valid values are:
+//!         - \b FLASH_BANK0
+//!         - \b FLASH_BANK1
+//!
+//! \return Returns the read mode to set. Valid values are:
+//!  - \b FLASH_NORMAL_READ_MODE,
+//!  - \b FLASH_MARGIN0_READ_MODE,
+//!  - \b FLASH_MARGIN1_READ_MODE,
+//!  - \b FLASH_PROGRAM_VERIFY_READ_MODE,
+//!  - \b FLASH_ERASE_VERIFY_READ_MODE,
+//!  - \b FLASH_LEAKAGE_VERIFY_READ_MODE,
+//!  - \b FLASH_MARGIN0B_READ_MODE,
+//!  - \b FLASH_MARGIN1B_READ_MODE
+//!
+//
+//*****************************************************************************
+extern uint32_t FlashCtl_getReadMode(uint32_t flashBank);
+
+//*****************************************************************************
+//
+//! Changes the number of wait states that are used by the flash controller
+//! for read operations. When changing frequency ranges of the clock, this
+//! functions must be used in order to allow for readable flash memory.
+//!
+//! \param waitState The number of wait states to set. Note that only
+//!     bits 0-3 are used.
+//!
+//! \param flashBank Flash bank to set wait state for. Valid values are:
+//!         - \b FLASH_BANK0
+//!         - \b FLASH_BANK1
+//!
+//
+//*****************************************************************************
+extern void FlashCtl_setWaitState(uint32_t bank, uint32_t waitState);
+
+//*****************************************************************************
+//
+//! Returns the set number of flash wait states for the given flash bank.
+//!
+//! \param flashBank Flash bank to set wait state for. Valid values are:
+//!         - \b FLASH_BANK0
+//!         - \b FLASH_BANK1
+//!
+//! \return The wait state setting for the specified flash bank
+//
+//*****************************************************************************
+extern uint32_t FlashCtl_getWaitState(uint32_t bank);
+
+//*****************************************************************************
+//
+//! Enables individual flash control interrupt sources.
+//!
+//! \param flags is a bit mask of the interrupt sources to be enabled.  Must
+//! be a logical OR of:
+//!         - \b FLASH_PROGRAM_ERROR,
+//!         - \b FLASH_BENCHMARK_INT,
+//!         - \b FLASH_ERASE_COMPLETE,
+//!         - \b FLASH_BRSTPRGM_COMPLETE,
+//!         - \b FLASH_WRDPRGM_COMPLETE,
+//!         - \b FLASH_POSTVERIFY_FAILED,
+//!         - \b FLASH_PREVERIFY_FAILED,
+//!         - \b FLASH_BRSTRDCMP_COMPLETE
+//!
+//! This function enables the indicated flash system interrupt sources.  Only
+//! the sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! \note The interrupt sources vary based on the part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FlashCtl_enableInterrupt(uint32_t flags);
+
+//*****************************************************************************
+//
+//! Disables individual flash system interrupt sources.
+//!
+//! \param flags is a bit mask of the interrupt sources to be disabled.  Must
+//! be a logical OR of:
+//!         - \b FLASH_PROGRAM_ERROR,
+//!         - \b FLASH_BENCHMARK_INT,
+//!         - \b FLASH_ERASE_COMPLETE,
+//!         - \b FLASH_BRSTPRGM_COMPLETE,
+//!         - \b FLASH_WRDPRGM_COMPLETE,
+//!         - \b FLASH_POSTVERIFY_FAILED,
+//!         - \b FLASH_PREVERIFY_FAILED,
+//!         - \b FLASH_BRSTRDCMP_COMPLETE
+//!
+//! This function disables the indicated flash system interrupt sources.
+//! Only the sources that are enabled can be reflected to the processor
+//! interrupt; disabled sources have no effect on the processor.
+//!
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FlashCtl_disableInterrupt(uint32_t flags);
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status masked with the enabled interrupts.
+//! This function is useful to call in ISRs to get a list
+//! of pending interrupts that are actually enabled and could have caused the
+//! ISR.
+//!
+//! \return The current interrupt status, enumerated as a bit field of
+//!         - \b FLASH_PROGRAM_ERROR,
+//!         - \b FLASH_BENCHMARK_INT,
+//!         - \b FLASH_ERASE_COMPLETE,
+//!         - \b FLASH_BRSTPRGM_COMPLETE,
+//!         - \b FLASH_WRDPRGM_COMPLETE,
+//!         - \b FLASH_POSTVERIFY_FAILED,
+//!         - \b FLASH_PREVERIFY_FAILED,
+//!         - \b FLASH_BRSTRDCMP_COMPLETE
+//!
+//! \note The interrupt sources vary based on the part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//
+//*****************************************************************************
+extern uint32_t FlashCtl_getEnabledInterruptStatus(void);
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \return The current interrupt status, enumerated as a bit field of:
+//!         - \b FLASH_PROGRAM_ERROR,
+//!         - \b FLASH_BENCHMARK_INT,
+//!         - \b FLASH_ERASE_COMPLETE,
+//!         - \b FLASH_BRSTPRGM_COMPLETE,
+//!         - \b FLASH_WRDPRGM_COMPLETE,
+//!         - \b FLASH_POSTVERIFY_FAILED,
+//!         - \b FLASH_PREVERIFY_FAILED,
+//!         - \b FLASH_BRSTRDCMP_COMPLETE
+//!
+//! \note The interrupt sources vary based on the part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//
+//*****************************************************************************
+extern uint32_t FlashCtl_getInterruptStatus(void);
+
+//*****************************************************************************
+//
+//! Clears flash system interrupt sources.
+//!
+//! \param flags is a bit mask of the interrupt sources to be cleared.  Must
+//! be a logical OR of:
+//!         - \b FLASH_PROGRAM_ERROR,
+//!         - \b FLASH_BENCHMARK_INT,
+//!         - \b FLASH_ERASE_COMPLETE,
+//!         - \b FLASH_BRSTPRGM_COMPLETE,
+//!         - \b FLASH_WRDPRGM_COMPLETE,
+//!         - \b FLASH_POSTVERIFY_FAILED,
+//!         - \b FLASH_PREVERIFY_FAILED,
+//!         - \b FLASH_BRSTRDCMP_COMPLETE
+//!
+//! The specified flash system interrupt sources are cleared, so that they no
+//! longer assert.  This function must be called in the interrupt handler to
+//! keep it from being called again immediately upon exit.
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared.  Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \note The interrupt sources vary based on the part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FlashCtl_clearInterruptFlag(uint32_t flags);
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for flash clock system interrupt.
+//!
+//! \param intHandler is a pointer to the function to be called when the clock
+//! system interrupt occurs.
+//!
+//! This function registers the handler to be called when a clock system
+//! interrupt occurs. This function enables the global interrupt in the
+//! interrupt controller; specific flash controller interrupts must be enabled
+//! via FlashCtl_enableInterrupt().  It is the interrupt handler's
+//! responsibility to clear the interrupt source via
+//! FlashCtl_clearInterruptFlag().
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FlashCtl_registerInterrupt(void (*intHandler)(void));
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the flash system.
+//!
+//! This function unregisters the handler to be called when a clock system
+//! interrupt occurs.  This function also masks off the interrupt in the
+//! interrupt controller so that the interrupt handler no longer is called.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FlashCtl_unregisterInterrupt(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif // __FLASH_H__
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/fpu.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/fpu.c
new file mode 100644
index 000000000..176fdd19c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/fpu.c
@@ -0,0 +1,115 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#include <fpu.h>
+
+void FPU_enableModule(void)
+{
+    //
+    // Enable the coprocessors used by the floating-point unit.
+    //
+    SCB->CPACR = ((SCB->CPACR & ~(SCB_CPACR_CP11_M | SCB_CPACR_CP10_M))
+            | SCB_CPACR_CP11_M | SCB_CPACR_CP10_M);
+}
+
+void FPU_disableModule(void)
+{
+    //
+    // Disable the coprocessors used by the floating-point unit.
+    //
+    SCB->CPACR = ((SCB->CPACR & ~(SCB_CPACR_CP10_M | SCB_CPACR_CP11_M)));
+}
+
+void FPU_enableStacking(void)
+{
+    //
+    // Enable automatic state preservation for the floating-point unit, and
+    // disable lazy state preservation (meaning that the floating-point state
+    // is always stacked when floating-point instructions are used).
+    //
+    FPU->FPCCR = (FPU->FPCCR & ~FPU_FPCCR_LSPEN) | FPU_FPCCR_ASPEN;
+}
+
+void FPU_enableLazyStacking(void)
+{
+    //
+    // Enable automatic and lazy state preservation for the floating-point
+    // unit.
+    //
+    FPU->FPCCR |= FPU_FPCCR_ASPEN | FPU_FPCCR_LSPEN;
+}
+
+void FPU_disableStacking(void)
+{
+    //
+    // Disable automatic and lazy state preservation for the floating-point
+    // unit.
+    //
+    FPU->FPCCR &= ~(FPU_FPCCR_ASPEN | FPU_FPCCR_LSPEN);
+}
+
+void FPU_setHalfPrecisionMode(uint32_t mode)
+{
+    //
+    // Set the half-precision floating-point format.
+    //
+    FPU->FPDSCR = (FPU->FPDSCR & ~(FPU_FPDSCR_AHP_Msk)) | mode;
+}
+
+void FPU_setNaNMode(uint32_t mode)
+{
+    //
+    // Set the NaN mode.
+    //
+    FPU->FPDSCR = (FPU->FPDSCR & ~(FPU_FPDSCR_DN_Msk)) | mode;
+}
+
+void FPU_setFlushToZeroMode(uint32_t mode)
+{
+    //
+    // Set the flush-to-zero mode.
+    //
+    FPU->FPDSCR = (FPU->FPDSCR & ~(FPU_FPDSCR_FZ_Msk)) | mode;
+}
+
+void FPU_setRoundingMode(uint32_t mode)
+{
+    //
+    // Set the rounding mode.
+    //
+    FPU->FPDSCR = (FPU->FPDSCR & ~(FPU_FPDSCR_RMode_Msk)) | mode;
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/fpu.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/fpu.h
new file mode 100644
index 000000000..f9698bbec
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/fpu.h
@@ -0,0 +1,285 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __FPU_H__
+#define __FPU_H__
+
+//*****************************************************************************
+//
+//!
+//! \addtogroup fpu_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <msp.h>
+
+//*****************************************************************************
+//
+// Values that can be passed to FPUHalfPrecisionSet as the mode parameter.
+//
+//*****************************************************************************
+#define FPU_HALF_IEEE           0x00000000
+#define FPU_HALF_ALTERNATE      0x04000000
+
+//*****************************************************************************
+//
+// Values that can be passed to FPU_setNaNMode as the mode parameter.
+//
+//*****************************************************************************
+#define FPU_NAN_PROPAGATE       0x00000000
+#define FPU_NAN_DEFAULT         0x02000000
+
+//*****************************************************************************
+//
+// Values that can be passed to FPU_setFlushToZeroMode as the mode parameter.
+//
+//*****************************************************************************
+#define FPU_FLUSH_TO_ZERO_DIS   0x00000000
+#define FPU_FLUSH_TO_ZERO_EN    0x01000000
+
+//*****************************************************************************
+//
+// Values that can be passed to FPU_setRoundingMode as the mode parameter.
+//
+//*****************************************************************************
+#define FPU_ROUND_NEAREST       0x00000000
+#define FPU_ROUND_POS_INF       0x00400000
+#define FPU_ROUND_NEG_INF       0x00800000
+#define FPU_ROUND_ZERO          0x00c00000
+
+//*****************************************************************************
+//
+//! Enables the floating-point unit.
+//!
+//! This function enables the floating-point unit, allowing the floating-point
+//! instructions to be executed.  This function must be called prior to
+//! performing any hardware floating-point operations; failure to do so results
+//! in a NOCP usage fault.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FPU_enableModule(void);
+
+//*****************************************************************************
+//
+//! Disables the floating-point unit.
+//!
+//! This function disables the floating-point unit, preventing floating-point
+//! instructions from executing (generating a NOCP usage fault instead).
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FPU_disableModule(void);
+
+//*****************************************************************************
+//
+//! Enables the stacking of floating-point registers.
+//!
+//! This function enables the stacking of floating-point registers s0-s15 when
+//! an interrupt is handled.  When enabled, space is reserved on the stack for
+//! the floating-point context and the floating-point state is saved into this
+//! stack space.  Upon return from the interrupt, the floating-point context is
+//! restored.
+//!
+//! If the floating-point registers are not stacked, floating-point
+//! instructions cannot be safely executed in an interrupt handler because the
+//! values of s0-s15 are not likely to be preserved for the interrupted code.
+//! On the other hand, stacking the floating-point registers increases the
+//! stacking operation from 8 words to 26 words, also increasing the interrupt
+//! response latency.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FPU_enableStacking(void);
+
+//*****************************************************************************
+//
+//! Enables the lazy stacking of floating-point registers.
+//!
+//! This function enables the lazy stacking of floating-point registers s0-s15
+//! when an interrupt is handled.  When lazy stacking is enabled, space is
+//! reserved on the stack for the floating-point context, but the
+//! floating-point state is not saved.  If a floating-point instruction is
+//! executed from within the interrupt context, the floating-point context is
+//! first saved into the space reserved on the stack.  On completion of the
+//! interrupt handler, the floating-point context is only restored if it was
+//! saved (as the result of executing a floating-point instruction).
+//!
+//! This method provides a compromise between fast interrupt response (because
+//! the floating-point state is not saved on interrupt entry) and the ability
+//! to use floating-point in interrupt handlers (because the floating-point
+//! state is saved if floating-point instructions are used).
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FPU_enableLazyStacking(void);
+
+//*****************************************************************************
+//
+//! Disables the stacking of floating-point registers.
+//!
+//! This function disables the stacking of floating-point registers s0-s15 when
+//! an interrupt is handled.  When floating-point context stacking is disabled,
+//! floating-point operations performed in an interrupt handler destroy the
+//! floating-point context of the main thread of execution.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FPU_disableStacking(void);
+
+//*****************************************************************************
+//
+//! Selects the format of half-precision floating-point values.
+//!
+//! \param mode is the format for half-precision floating-point value, which
+//! is either \b FPU_HALF_IEEE or \b FPU_HALF_ALTERNATE.
+//!
+//! This function selects between the IEEE half-precision floating-point
+//! representation and the Cortex-M processor alternative representation.  The
+//! alternative representation has a larger range but does not have a way to
+//! encode infinity (positive or negative) or NaN (quiet or signalling).  The
+//! default setting is the IEEE format.
+//!
+//! \note Unless this function is called prior to executing any floating-point
+//! instructions, the default mode is used.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FPU_setHalfPrecisionMode(uint32_t mode);
+
+//*****************************************************************************
+//
+//! Selects the NaN mode.
+//!
+//! \param mode is the mode for NaN results; which is 
+//! either \b FPU_NAN_PROPAGATE or \b FPU_NAN_DEFAULT.
+//!
+//! This function selects the handling of NaN results during floating-point
+//! computations.  NaNs can either propagate (the default), or they can return
+//! the default NaN.
+//!
+//! \note Unless this function is called prior to executing any floating-point
+//! instructions, the default mode is used.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FPU_setNaNMode(uint32_t mode);
+
+//*****************************************************************************
+//
+//! Selects the flush-to-zero mode.
+//!
+//! \param mode is the flush-to-zero mode; which is either
+//! \b FPU_FLUSH_TO_ZERO_DIS or \b FPU_FLUSH_TO_ZERO_EN.
+//!
+//! This function enables or disables the flush-to-zero mode of the
+//! floating-point unit.  When disabled (the default), the floating-point unit
+//! is fully IEEE compliant.  When enabled, values close to zero are treated as
+//! zero, greatly improving the execution speed at the expense of some accuracy
+//! (as well as IEEE compliance).
+//!
+//! \note Unless this function is called prior to executing any floating-point
+//! instructions, the default mode is used.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FPU_setFlushToZeroMode(uint32_t mode);
+
+//*****************************************************************************
+//
+//! Selects the rounding mode for floating-point results.
+//!
+//! \param mode is the rounding mode.
+//!
+//! This function selects the rounding mode for floating-point results.  After
+//! a floating-point operation, the result is rounded toward the specified
+//! value.  The default mode is \b FPU_ROUND_NEAREST.
+//!
+//! The following rounding modes are available (as specified by \e mode):
+//!
+//! - \b FPU_ROUND_NEAREST - round toward the nearest value
+//! - \b FPU_ROUND_POS_INF - round toward positive infinity
+//! - \b FPU_ROUND_NEG_INF - round toward negative infinity
+//! - \b FPU_ROUND_ZERO - round toward zero
+//!
+//! \note Unless this function is called prior to executing any floating-point
+//! instructions, the default mode is used.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FPU_setRoundingMode(uint32_t mode);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+
+#endif // __FPU_H__
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/gpio.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/gpio.c
new file mode 100644
index 000000000..9ecfb79db
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/gpio.c
@@ -0,0 +1,356 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+/* Standard Includes */
+#include <stdint.h>
+
+/* DriverLib Includes */
+#include <gpio.h>
+#include <debug.h>
+#include <interrupt.h>
+
+static const uint32_t GPIO_PORT_TO_INT[] =
+{ 0x00,
+INT_PORT1,
+INT_PORT2,
+INT_PORT3,
+INT_PORT4,
+INT_PORT5,
+INT_PORT6 };
+
+static const uint32_t GPIO_PORT_TO_BASE[] =
+{   0x00,
+		0x40004C00,
+		0x40004C01,
+		0x40004C20,
+		0x40004C21,
+		0x40004C40,
+		0x40004C41,
+		0x40004C60,
+		0x40004C61,
+		0x40004C80,
+		0x40004C81,
+		0x40004D20
+    };
+
+void GPIO_setAsOutputPin(uint_fast8_t selectedPort, uint_fast16_t selectedPins)
+{
+    uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
+
+    HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;
+    HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;
+    HWREG16(baseAddress + OFS_PADIR) |= selectedPins;
+
+    return;
+}
+
+void GPIO_setAsInputPin(uint_fast8_t selectedPort, uint_fast16_t selectedPins)
+{
+
+    uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
+
+    HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;
+    HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;
+    HWREG16(baseAddress + OFS_PADIR) &= ~selectedPins;
+    HWREG16(baseAddress + OFS_PAREN) &= ~selectedPins;
+}
+
+
+void GPIO_setAsPeripheralModuleFunctionOutputPin(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins, uint_fast8_t mode)
+{
+
+    uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
+
+    HWREG16(baseAddress + OFS_PADIR) |= selectedPins;
+    switch (mode)
+    {
+    case GPIO_PRIMARY_MODULE_FUNCTION:
+        HWREG16(baseAddress + OFS_PASEL0) |= selectedPins;
+        HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;
+        break;
+    case GPIO_SECONDARY_MODULE_FUNCTION:
+        HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;
+        HWREG16(baseAddress + OFS_PASEL1) |= selectedPins;
+        break;
+    case GPIO_TERTIARY_MODULE_FUNCTION:
+        HWREG16(baseAddress + OFS_PASEL0) |= selectedPins;
+        HWREG16(baseAddress + OFS_PASEL1) |= selectedPins;
+        break;
+    }
+}
+
+
+void GPIO_setAsPeripheralModuleFunctionInputPin(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins, uint_fast8_t mode)
+{
+    uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
+
+    HWREG16(baseAddress + OFS_PADIR) &= ~selectedPins;
+    switch (mode)
+    {
+    case GPIO_PRIMARY_MODULE_FUNCTION:
+        HWREG16(baseAddress + OFS_PASEL0) |= selectedPins;
+        HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;
+        break;
+    case GPIO_SECONDARY_MODULE_FUNCTION:
+        HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;
+        HWREG16(baseAddress + OFS_PASEL1) |= selectedPins;
+        break;
+    case GPIO_TERTIARY_MODULE_FUNCTION:
+        HWREG16(baseAddress + OFS_PASEL0) |= selectedPins;
+        HWREG16(baseAddress + OFS_PASEL1) |= selectedPins;
+        break;
+    }
+}
+
+
+void GPIO_setOutputHighOnPin(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins)
+{
+
+    uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
+
+    HWREG16(baseAddress + OFS_PAOUT) |= selectedPins;
+}
+
+
+void GPIO_setOutputLowOnPin(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins)
+{
+
+    uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
+
+    HWREG16(baseAddress + OFS_PAOUT) &= ~selectedPins;
+}
+
+
+void GPIO_toggleOutputOnPin(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins)
+{
+
+    uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
+
+    HWREG16(baseAddress + OFS_PAOUT) ^= selectedPins;
+}
+
+
+void GPIO_setAsInputPinWithPullDownResistor(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins)
+{
+
+    uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
+
+    HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;
+    HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;
+
+    HWREG16(baseAddress + OFS_PADIR) &= ~selectedPins;
+    HWREG16(baseAddress + OFS_PAREN) |= selectedPins;
+    HWREG16(baseAddress + OFS_PAOUT) &= ~selectedPins;
+}
+
+
+void GPIO_setAsInputPinWithPullUpResistor(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins)
+{
+
+    uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
+
+    HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;
+    HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;
+    HWREG16(baseAddress + OFS_PADIR) &= ~selectedPins;
+    HWREG16(baseAddress + OFS_PAREN) |= selectedPins;
+    HWREG16(baseAddress + OFS_PAOUT) |= selectedPins;
+}
+
+
+uint8_t GPIO_getInputPinValue(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins)
+{
+        uint16_t inputPinValue;
+    uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
+
+    inputPinValue = HWREG16(baseAddress + OFS_PAIN) & (selectedPins);
+
+    if (inputPinValue > 0)
+        return GPIO_INPUT_PIN_HIGH;
+    return GPIO_INPUT_PIN_LOW;
+}
+
+
+void GPIO_enableInterrupt(uint_fast8_t selectedPort, uint_fast16_t selectedPins)
+{
+
+    uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
+
+    HWREG16(baseAddress + OFS_PAIE) |= selectedPins;
+}
+
+
+void GPIO_disableInterrupt(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins)
+{
+
+    uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
+
+    HWREG16(baseAddress + OFS_PAIE) &= ~selectedPins;
+}
+
+
+uint_fast16_t GPIO_getInterruptStatus(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins)
+{
+
+    uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
+
+    return HWREG16(baseAddress + OFS_PAIFG) & selectedPins;
+}
+
+
+void GPIO_clearInterruptFlag(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins)
+{
+
+    uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
+
+
+    HWREG16(baseAddress + OFS_PAIFG) &= ~selectedPins;
+}
+
+
+void GPIO_interruptEdgeSelect(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins, uint_fast8_t edgeSelect)
+{
+
+    uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
+
+
+    if (GPIO_LOW_TO_HIGH_TRANSITION == edgeSelect)
+        HWREG16(baseAddress + OFS_PAIES) &= ~selectedPins;
+    else
+        HWREG16(baseAddress + OFS_PAIES) |= selectedPins;
+}
+
+uint_fast16_t GPIO_getEnabledInterruptStatus(uint_fast8_t selectedPort)
+{
+    uint_fast16_t pendingInts;
+    uint32_t baseAddr;
+
+    pendingInts = GPIO_getInterruptStatus(selectedPort, 0xFFFF);
+    baseAddr = GPIO_PORT_TO_BASE[selectedPort];
+
+    ASSERT(baseAddr != 0xFFFF);
+
+    switch (selectedPort)
+    {
+    case GPIO_PORT_P1:
+    case GPIO_PORT_P3:
+    case GPIO_PORT_P5:
+    case GPIO_PORT_P7:
+    case GPIO_PORT_P9:
+        return (HWREG8(baseAddr + OFS_P1IE) & pendingInts);
+    case GPIO_PORT_P2:
+    case GPIO_PORT_P4:
+    case GPIO_PORT_P6:
+    case GPIO_PORT_P8:
+    case GPIO_PORT_P10:
+        return (HWREG8(baseAddr + OFS_P2IE) & pendingInts);
+    case GPIO_PORT_PJ:
+        return (HWREG16(baseAddr + OFS_PAIE) & pendingInts);
+    default:
+        return 0;
+    }
+}
+
+
+void GPIO_setDriveStrengthHigh(uint_fast8_t selectedPort,
+        uint_fast8_t selectedPins)
+{
+    uint32_t baseAddr;
+
+    baseAddr = GPIO_PORT_TO_BASE[selectedPort];
+
+    HWREG8(baseAddr + OFS_PADS) |= selectedPins;
+
+}
+
+void GPIO_setDriveStrengthLow(uint_fast8_t selectedPort,
+        uint_fast8_t selectedPins)
+{
+    uint32_t baseAddr;
+
+    baseAddr = GPIO_PORT_TO_BASE[selectedPort];
+
+    HWREG8(baseAddr + OFS_PADS) &= ~selectedPins;
+
+}
+
+void GPIO_registerInterrupt(uint_fast8_t selectedPort, void (*intHandler)(void))
+{
+    uint32_t wPortInt;
+
+    wPortInt = GPIO_PORT_TO_INT[selectedPort];
+
+    //
+    // Register the interrupt handler, returning an error if an error occurs.
+    //
+    Interrupt_registerInterrupt(wPortInt, intHandler);
+
+    //
+    // Enable the system control interrupt.
+    //
+    Interrupt_enableInterrupt(wPortInt);
+}
+
+
+void GPIO_unregisterInterrupt(uint_fast8_t selectedPort)
+{
+    uint32_t wPortInt;
+
+    wPortInt = GPIO_PORT_TO_INT[selectedPort];
+
+    //
+    // Disable the interrupt.
+    //
+    Interrupt_disableInterrupt(wPortInt);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    Interrupt_unregisterInterrupt(wPortInt);
+}
+
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/gpio.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/gpio.h
new file mode 100644
index 000000000..7a33a4996
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/gpio.h
@@ -0,0 +1,1018 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __GPIO_H__
+#define __GPIO_H__
+
+//*****************************************************************************
+//
+//! \addtogroup gpio_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <msp.h>
+#include <stdint.h>
+
+#define GPIO_PORT_P1                                                          1
+#define GPIO_PORT_P2                                                          2
+#define GPIO_PORT_P3                                                          3
+#define GPIO_PORT_P4                                                          4
+#define GPIO_PORT_P5                                                          5
+#define GPIO_PORT_P6                                                          6
+#define GPIO_PORT_P7                                                          7
+#define GPIO_PORT_P8                                                          8
+#define GPIO_PORT_P9                                                          9
+#define GPIO_PORT_P10                                                         10
+#define GPIO_PORT_PJ                                                         11
+
+#define GPIO_PIN0                                                      (0x0001)
+#define GPIO_PIN1                                                      (0x0002)
+#define GPIO_PIN2                                                      (0x0004)
+#define GPIO_PIN3                                                      (0x0008)
+#define GPIO_PIN4                                                      (0x0010)
+#define GPIO_PIN5                                                      (0x0020)
+#define GPIO_PIN6                                                      (0x0040)
+#define GPIO_PIN7                                                      (0x0080)
+#define GPIO_PIN8                                                      (0x0100)
+#define GPIO_PIN9                                                      (0x0200)
+#define GPIO_PIN10                                                     (0x0400)
+#define GPIO_PIN11                                                     (0x0800)
+#define GPIO_PIN12                                                     (0x1000)
+#define GPIO_PIN13                                                     (0x2000)
+#define GPIO_PIN14                                                     (0x4000)
+#define GPIO_PIN15                                                     (0x8000)
+#define PIN_ALL8                                                       (0xFF)
+#define PIN_ALL16                                                      (0xFFFF)
+
+#define GPIO_PRIMARY_MODULE_FUNCTION                                     (0x01)
+#define GPIO_SECONDARY_MODULE_FUNCTION                                   (0x02)
+#define GPIO_TERTIARY_MODULE_FUNCTION                                     (0x03)
+
+#define GPIO_HIGH_TO_LOW_TRANSITION                                      (0x01)
+#define GPIO_LOW_TO_HIGH_TRANSITION                                      (0x00)
+
+#define GPIO_INPUT_PIN_HIGH                                              (0x01)
+#define GPIO_INPUT_PIN_LOW                                               (0x00)
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \brief This function configures the selected Pin as output pin
+//!
+//! This function selected pins on a selected port as output pins.
+//!
+//! \param selectedPort is the selected port.
+//!        Valid values are:
+//!        - \b GPIO_PORT_P1
+//!        - \b GPIO_PORT_P2
+//!        - \b GPIO_PORT_P3
+//!        - \b GPIO_PORT_P4
+//!        - \b GPIO_PORT_P5
+//!        - \b GPIO_PORT_P6
+//!        - \b GPIO_PORT_P7
+//!        - \b GPIO_PORT_P8
+//!        - \b GPIO_PORT_P9
+//!        - \b GPIO_PORT_P10
+//!        - \b GPIO_PORT_P11
+//!        - \b GPIO_PORT_PJ
+//! \param selectedPins is the specified pin in the selected port.
+//!        Mask value is the logical OR of any of the following:
+//!        - \b GPIO_PIN0
+//!        - \b GPIO_PIN1
+//!        - \b GPIO_PIN2
+//!        - \b GPIO_PIN3
+//!        - \b GPIO_PIN4
+//!        - \b GPIO_PIN5
+//!        - \b GPIO_PIN6
+//!        - \b GPIO_PIN7
+//!        - \b GPIO_PIN8
+//!        - \b GPIO_PIN9
+//!        - \b GPIO_PIN10
+//!        - \b GPIO_PIN11
+//!        - \b GPIO_PIN12
+//!        - \b GPIO_PIN13
+//!        - \b GPIO_PIN14
+//!        - \b GPIO_PIN15
+//!
+//! Modified bits of \b PxDIR register and bits of \b PxSEL register.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void GPIO_setAsOutputPin(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins);
+
+//*****************************************************************************
+//
+//! \brief This function configures the selected Pin as input pin
+//!
+//! This function selected pins on a selected port as input pins.
+//!
+//! \param selectedPort is the selected port.
+//!        Valid values are:
+//!        - \b GPIO_PORT_P1
+//!        - \b GPIO_PORT_P2
+//!        - \b GPIO_PORT_P3
+//!        - \b GPIO_PORT_P4
+//!        - \b GPIO_PORT_P5
+//!        - \b GPIO_PORT_P6
+//!        - \b GPIO_PORT_P7
+//!        - \b GPIO_PORT_P8
+//!        - \b GPIO_PORT_P9
+//!        - \b GPIO_PORT_P10
+//!        - \b GPIO_PORT_P11
+//!        - \b GPIO_PORT_PJ
+//! \param selectedPins is the specified pin in the selected port.
+//!        Mask value is the logical OR of any of the following:
+//!        - \b GPIO_PIN0
+//!        - \b GPIO_PIN1
+//!        - \b GPIO_PIN2
+//!        - \b GPIO_PIN3
+//!        - \b GPIO_PIN4
+//!        - \b GPIO_PIN5
+//!        - \b GPIO_PIN6
+//!        - \b GPIO_PIN7
+//!        - \b GPIO_PIN8
+//!        - \b GPIO_PIN9
+//!        - \b GPIO_PIN10
+//!        - \b GPIO_PIN11
+//!        - \b GPIO_PIN12
+//!        - \b GPIO_PIN13
+//!        - \b GPIO_PIN14
+//!        - \b GPIO_PIN15
+//!
+//! Modified bits of \b PxDIR register, bits of \b PxREN register and bits of
+//! \b PxSEL register.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void GPIO_setAsInputPin(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins);
+
+//*****************************************************************************
+//
+//! \brief This function configures the peripheral module function in the
+//! output direction for the selected pin for either primary, secondary or
+//! ternary module function modes
+//!
+//! This function configures the peripheral module function in the output
+//! direction for the selected pin for either primary, secondary or ternary
+//! module function modes. Accepted values for mode are
+//! GPIO_PRIMARY_MODULE_FUNCTION, GPIO_SECONDARY_MODULE_FUNCTION, and
+//! GPIO_TERTIARY_MODULE_FUNCTION
+//!
+//! \param selectedPort is the selected port.
+//!        Valid values are:
+//!        - \b GPIO_PORT_P1
+//!        - \b GPIO_PORT_P2
+//!        - \b GPIO_PORT_P3
+//!        - \b GPIO_PORT_P4
+//!        - \b GPIO_PORT_P5
+//!        - \b GPIO_PORT_P6
+//!        - \b GPIO_PORT_P7
+//!        - \b GPIO_PORT_P8
+//!        - \b GPIO_PORT_P9
+//!        - \b GPIO_PORT_P10
+//!        - \b GPIO_PORT_P11
+//!        - \b GPIO_PORT_PJ
+//! \param selectedPins is the specified pin in the selected port.
+//!        Mask value is the logical OR of any of the following:
+//!        - \b GPIO_PIN0
+//!        - \b GPIO_PIN1
+//!        - \b GPIO_PIN2
+//!        - \b GPIO_PIN3
+//!        - \b GPIO_PIN4
+//!        - \b GPIO_PIN5
+//!        - \b GPIO_PIN6
+//!        - \b GPIO_PIN7
+//!        - \b GPIO_PIN8
+//!        - \b GPIO_PIN9
+//!        - \b GPIO_PIN10
+//!        - \b GPIO_PIN11
+//!        - \b GPIO_PIN12
+//!        - \b GPIO_PIN13
+//!        - \b GPIO_PIN14
+//!        - \b GPIO_PIN15
+//! \param mode is the specified mode that the pin should be configured for the
+//!        module function.
+//!        Valid values are:
+//!        - \b GPIO_PRIMARY_MODULE_FUNCTION
+//!        - \b GPIO_SECONDARY_MODULE_FUNCTION
+//!        - \b GPIO_TERTIARY_MODULE_FUNCTION
+//!
+//! Modified bits of \b PxDIR register and bits of \b PxSEL register.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void GPIO_setAsPeripheralModuleFunctionOutputPin(
+        uint_fast8_t selectedPort, uint_fast16_t selectedPins,
+        uint_fast8_t mode);
+
+//*****************************************************************************
+//
+//! \brief This function configures the peripheral module function in the input
+//! direction for the selected pin for either primary, secondary or ternary
+//! module function modes.
+//!
+//! This function configures the peripheral module function in the input
+//! direction for the selected pin for either primary, secondary or ternary
+//! module function modes. Accepted values for mode are
+//! GPIO_PRIMARY_MODULE_FUNCTION, GPIO_SECONDARY_MODULE_FUNCTION, and
+//! GPIO_TERTIARY_MODULE_FUNCTION
+//!
+//! \param selectedPort is the selected port.
+//!        Valid values are:
+//!        - \b GPIO_PORT_P1
+//!        - \b GPIO_PORT_P2
+//!        - \b GPIO_PORT_P3
+//!        - \b GPIO_PORT_P4
+//!        - \b GPIO_PORT_P5
+//!        - \b GPIO_PORT_P6
+//!        - \b GPIO_PORT_P7
+//!        - \b GPIO_PORT_P8
+//!        - \b GPIO_PORT_P9
+//!        - \b GPIO_PORT_P10
+//!        - \b GPIO_PORT_P11
+//!        - \b GPIO_PORT_PJ
+//! \param selectedPins is the specified pin in the selected port.
+//!        Mask value is the logical OR of any of the following:
+//!        - \b GPIO_PIN0
+//!        - \b GPIO_PIN1
+//!        - \b GPIO_PIN2
+//!        - \b GPIO_PIN3
+//!        - \b GPIO_PIN4
+//!        - \b GPIO_PIN5
+//!        - \b GPIO_PIN6
+//!        - \b GPIO_PIN7
+//!        - \b GPIO_PIN8
+//!        - \b GPIO_PIN9
+//!        - \b GPIO_PIN10
+//!        - \b GPIO_PIN11
+//!        - \b GPIO_PIN12
+//!        - \b GPIO_PIN13
+//!        - \b GPIO_PIN14
+//!        - \b GPIO_PIN15
+//! \param mode is the specified mode that the pin should be configured for the
+//!        module function.
+//!        Valid values are:
+//!        - \b GPIO_PRIMARY_MODULE_FUNCTION
+//!        - \b GPIO_SECONDARY_MODULE_FUNCTION
+//!        - \b GPIO_TERTIARY_MODULE_FUNCTION
+//!
+//! Modified bits of \b PxDIR register and bits of \b PxSEL register.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void GPIO_setAsPeripheralModuleFunctionInputPin(
+        uint_fast8_t selectedPort, uint_fast16_t selectedPins,
+        uint_fast8_t mode);
+
+//*****************************************************************************
+//
+//! \brief This function sets output HIGH on the selected Pin
+//!
+//! This function sets output HIGH on the selected port's pin.
+//!
+//! \param selectedPort is the selected port.
+//!        Valid values are:
+//!        - \b GPIO_PORT_P1
+//!        - \b GPIO_PORT_P2
+//!        - \b GPIO_PORT_P3
+//!        - \b GPIO_PORT_P4
+//!        - \b GPIO_PORT_P5
+//!        - \b GPIO_PORT_P6
+//!        - \b GPIO_PORT_P7
+//!        - \b GPIO_PORT_P8
+//!        - \b GPIO_PORT_P9
+//!        - \b GPIO_PORT_P10
+//!        - \b GPIO_PORT_P11
+//!        - \b GPIO_PORT_PJ
+//! \param selectedPins is the specified pin in the selected port.
+//!        Mask value is the logical OR of any of the following:
+//!        - \b GPIO_PIN0
+//!        - \b GPIO_PIN1
+//!        - \b GPIO_PIN2
+//!        - \b GPIO_PIN3
+//!        - \b GPIO_PIN4
+//!        - \b GPIO_PIN5
+//!        - \b GPIO_PIN6
+//!        - \b GPIO_PIN7
+//!        - \b GPIO_PIN8
+//!        - \b GPIO_PIN9
+//!        - \b GPIO_PIN10
+//!        - \b GPIO_PIN11
+//!        - \b GPIO_PIN12
+//!        - \b GPIO_PIN13
+//!        - \b GPIO_PIN14
+//!        - \b GPIO_PIN15
+//!
+//! Modified bits of \b PxOUT register.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void GPIO_setOutputHighOnPin(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins);
+
+//*****************************************************************************
+//
+//! \brief This function sets output LOW on the selected Pin
+//!
+//! This function sets output LOW on the selected port's pin.
+//!
+//! \param selectedPort is the selected port.
+//!        Valid values are:
+//!        - \b GPIO_PORT_P1
+//!        - \b GPIO_PORT_P2
+//!        - \b GPIO_PORT_P3
+//!        - \b GPIO_PORT_P4
+//!        - \b GPIO_PORT_P5
+//!        - \b GPIO_PORT_P6
+//!        - \b GPIO_PORT_P7
+//!        - \b GPIO_PORT_P8
+//!        - \b GPIO_PORT_P9
+//!        - \b GPIO_PORT_P10
+//!        - \b GPIO_PORT_P11
+//!        - \b GPIO_PORT_PJ
+//! \param selectedPins is the specified pin in the selected port.
+//!        Mask value is the logical OR of any of the following:
+//!        - \b GPIO_PIN0
+//!        - \b GPIO_PIN1
+//!        - \b GPIO_PIN2
+//!        - \b GPIO_PIN3
+//!        - \b GPIO_PIN4
+//!        - \b GPIO_PIN5
+//!        - \b GPIO_PIN6
+//!        - \b GPIO_PIN7
+//!        - \b GPIO_PIN8
+//!        - \b GPIO_PIN9
+//!        - \b GPIO_PIN10
+//!        - \b GPIO_PIN11
+//!        - \b GPIO_PIN12
+//!        - \b GPIO_PIN13
+//!        - \b GPIO_PIN14
+//!        - \b GPIO_PIN15
+//!
+//! Modified bits of \b PxOUT register.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void GPIO_setOutputLowOnPin(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins);
+
+//*****************************************************************************
+//
+//! \brief This function toggles the output on the selected Pin
+//!
+//! This function toggles the output on the selected port's pin.
+//!
+//! \param selectedPort is the selected port.
+//!        Valid values are:
+//!        - \b GPIO_PORT_P1
+//!        - \b GPIO_PORT_P2
+//!        - \b GPIO_PORT_P3
+//!        - \b GPIO_PORT_P4
+//!        - \b GPIO_PORT_P5
+//!        - \b GPIO_PORT_P6
+//!        - \b GPIO_PORT_P7
+//!        - \b GPIO_PORT_P8
+//!        - \b GPIO_PORT_P9
+//!        - \b GPIO_PORT_P10
+//!        - \b GPIO_PORT_P11
+//!        - \b GPIO_PORT_PJ
+//! \param selectedPins is the specified pin in the selected port.
+//!        Mask value is the logical OR of any of the following:
+//!        - \b GPIO_PIN0
+//!        - \b GPIO_PIN1
+//!        - \b GPIO_PIN2
+//!        - \b GPIO_PIN3
+//!        - \b GPIO_PIN4
+//!        - \b GPIO_PIN5
+//!        - \b GPIO_PIN6
+//!        - \b GPIO_PIN7
+//!        - \b GPIO_PIN8
+//!        - \b GPIO_PIN9
+//!        - \b GPIO_PIN10
+//!        - \b GPIO_PIN11
+//!        - \b GPIO_PIN12
+//!        - \b GPIO_PIN13
+//!        - \b GPIO_PIN14
+//!        - \b GPIO_PIN15
+//!
+//! Modified bits of \b PxOUT register.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void GPIO_toggleOutputOnPin(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins);
+
+//*****************************************************************************
+//
+//! \brief This function sets the selected Pin in input Mode with Pull Down
+//! resistor
+//!
+//! This function sets the selected Pin in input Mode with Pull Down resistor.
+//!
+//! \param selectedPort is the selected port.
+//!        Valid values are:
+//!        - \b GPIO_PORT_P1
+//!        - \b GPIO_PORT_P2
+//!        - \b GPIO_PORT_P3
+//!        - \b GPIO_PORT_P4
+//!        - \b GPIO_PORT_P5
+//!        - \b GPIO_PORT_P6
+//!        - \b GPIO_PORT_P7
+//!        - \b GPIO_PORT_P8
+//!        - \b GPIO_PORT_P9
+//!        - \b GPIO_PORT_P10
+//!        - \b GPIO_PORT_P11
+//!        - \b GPIO_PORT_PJ
+//! \param selectedPins is the specified pin in the selected port.
+//!        Mask value is the logical OR of any of the following:
+//!        - \b GPIO_PIN0
+//!        - \b GPIO_PIN1
+//!        - \b GPIO_PIN2
+//!        - \b GPIO_PIN3
+//!        - \b GPIO_PIN4
+//!        - \b GPIO_PIN5
+//!        - \b GPIO_PIN6
+//!        - \b GPIO_PIN7
+//!        - \b GPIO_PIN8
+//!        - \b GPIO_PIN9
+//!        - \b GPIO_PIN10
+//!        - \b GPIO_PIN11
+//!        - \b GPIO_PIN12
+//!        - \b GPIO_PIN13
+//!        - \b GPIO_PIN14
+//!        - \b GPIO_PIN15
+//!
+//! Modified bits of \b PxDIR register, bits of \b PxOUT register and bits of
+//! \b PxREN register.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void GPIO_setAsInputPinWithPullDownResistor(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins);
+
+//*****************************************************************************
+//
+//! \brief This function sets the selected Pin in input Mode with Pull Up
+//! resistor
+//!
+//! This function sets the selected Pin in input Mode with Pull Up resistor.
+//!
+//! \param selectedPort is the selected port.
+//!        Valid values are:
+//!        - \b GPIO_PORT_P1
+//!        - \b GPIO_PORT_P2
+//!        - \b GPIO_PORT_P3
+//!        - \b GPIO_PORT_P4
+//!        - \b GPIO_PORT_P5
+//!        - \b GPIO_PORT_P6
+//!        - \b GPIO_PORT_P7
+//!        - \b GPIO_PORT_P8
+//!        - \b GPIO_PORT_P9
+//!        - \b GPIO_PORT_P10
+//!        - \b GPIO_PORT_P11
+//!        - \b GPIO_PORT_PJ
+//! \param selectedPins is the specified pin in the selected port.
+//!        Mask value is the logical OR of any of the following:
+//!        - \b GPIO_PIN0
+//!        - \b GPIO_PIN1
+//!        - \b GPIO_PIN2
+//!        - \b GPIO_PIN3
+//!        - \b GPIO_PIN4
+//!        - \b GPIO_PIN5
+//!        - \b GPIO_PIN6
+//!        - \b GPIO_PIN7
+//!        - \b GPIO_PIN8
+//!        - \b GPIO_PIN9
+//!        - \b GPIO_PIN10
+//!        - \b GPIO_PIN11
+//!        - \b GPIO_PIN12
+//!        - \b GPIO_PIN13
+//!        - \b GPIO_PIN14
+//!        - \b GPIO_PIN15
+//!
+//! Modified bits of \b PxDIR register, bits of \b PxOUT register and bits of
+//! \b PxREN register.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void GPIO_setAsInputPinWithPullUpResistor(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins);
+
+//*****************************************************************************
+//
+//! \brief This function gets the input value on the selected pin
+//!
+//! This function gets the input value on the selected pin.
+//!
+//! \param selectedPort is the selected port.
+//!        Valid values are:
+//!        - \b GPIO_PORT_P1
+//!        - \b GPIO_PORT_P2
+//!        - \b GPIO_PORT_P3
+//!        - \b GPIO_PORT_P4
+//!        - \b GPIO_PORT_P5
+//!        - \b GPIO_PORT_P6
+//!        - \b GPIO_PORT_P7
+//!        - \b GPIO_PORT_P8
+//!        - \b GPIO_PORT_P9
+//!        - \b GPIO_PORT_P10
+//!        - \b GPIO_PORT_P11
+//!        - \b GPIO_PORT_PJ
+//! \param selectedPins is the specified pin in the selected port.
+//!        Valid values are:
+//!        - \b GPIO_PIN0
+//!        - \b GPIO_PIN1
+//!        - \b GPIO_PIN2
+//!        - \b GPIO_PIN3
+//!        - \b GPIO_PIN4
+//!        - \b GPIO_PIN5
+//!        - \b GPIO_PIN6
+//!        - \b GPIO_PIN7
+//!        - \b GPIO_PIN8
+//!        - \b GPIO_PIN9
+//!        - \b GPIO_PIN10
+//!        - \b GPIO_PIN11
+//!        - \b GPIO_PIN12
+//!        - \b GPIO_PIN13
+//!        - \b GPIO_PIN14
+//!        - \b GPIO_PIN15
+//!
+//! \return One of the following:
+//!         - \b GPIO_INPUT_PIN_HIGH
+//!         - \b GPIO_INPUT_PIN_LOW
+//!         \n indicating the status of the pin
+//
+//*****************************************************************************
+extern uint8_t GPIO_getInputPinValue(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins);
+
+//*****************************************************************************
+//
+//! \brief This function enables the port interrupt on the selected pin
+//!
+//! This function enables the port interrupt on the selected pin. Note that
+//! only Port 1,2, A have this capability.
+//!
+//! \param selectedPort is the selected port.
+//!        Valid values are:
+//!        - \b GPIO_PORT_P1
+//!        - \b GPIO_PORT_P2
+//!        - \b GPIO_PORT_PA
+//! \param selectedPins is the specified pin in the selected port.
+//!        Mask value is the logical OR of any of the following:
+//!        - \b GPIO_PIN0
+//!        - \b GPIO_PIN1
+//!        - \b GPIO_PIN2
+//!        - \b GPIO_PIN3
+//!        - \b GPIO_PIN4
+//!        - \b GPIO_PIN5
+//!        - \b GPIO_PIN6
+//!        - \b GPIO_PIN7
+//!        - \b GPIO_PIN8
+//!        - \b GPIO_PIN9
+//!        - \b GPIO_PIN10
+//!        - \b GPIO_PIN11
+//!        - \b GPIO_PIN12
+//!        - \b GPIO_PIN13
+//!        - \b GPIO_PIN14
+//!        - \b GPIO_PIN15
+//!
+//! Modified bits of \b PxIE register.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void GPIO_enableInterrupt(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins);
+
+//*****************************************************************************
+//
+//! \brief This function disables the port interrupt on the selected pin
+//!
+//! This function disables the port interrupt on the selected pin. Note that
+//! only Port 1,2, A have this capability.
+//!
+//! \param selectedPort is the selected port.
+//!        Valid values are:
+//!        - \b GPIO_PORT_P1
+//!        - \b GPIO_PORT_P2
+//!        - \b GPIO_PORT_PA
+//! \param selectedPins is the specified pin in the selected port.
+//!        Mask value is the logical OR of any of the following:
+//!        - \b GPIO_PIN0
+//!        - \b GPIO_PIN1
+//!        - \b GPIO_PIN2
+//!        - \b GPIO_PIN3
+//!        - \b GPIO_PIN4
+//!        - \b GPIO_PIN5
+//!        - \b GPIO_PIN6
+//!        - \b GPIO_PIN7
+//!        - \b GPIO_PIN8
+//!        - \b GPIO_PIN9
+//!        - \b GPIO_PIN10
+//!        - \b GPIO_PIN11
+//!        - \b GPIO_PIN12
+//!        - \b GPIO_PIN13
+//!        - \b GPIO_PIN14
+//!        - \b GPIO_PIN15
+//!
+//! Modified bits of \b PxIE register.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void GPIO_disableInterrupt(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins);
+
+//*****************************************************************************
+//
+//! \brief This function gets the interrupt status of the selected pin
+//!
+//! This function gets the interrupt status of the selected pin. Note that only
+//! Port 1,2, A have this capability.
+//!
+//! \param selectedPort is the selected port.
+//!        Valid values are:
+//!        - \b GPIO_PORT_P1
+//!        - \b GPIO_PORT_P2
+//!        - \b GPIO_PORT_PA
+//! \param selectedPins is the specified pin in the selected port.
+//!        Mask value is the logical OR of any of the following:
+//!        - \b GPIO_PIN0
+//!        - \b GPIO_PIN1
+//!        - \b GPIO_PIN2
+//!        - \b GPIO_PIN3
+//!        - \b GPIO_PIN4
+//!        - \b GPIO_PIN5
+//!        - \b GPIO_PIN6
+//!        - \b GPIO_PIN7
+//!        - \b GPIO_PIN8
+//!        - \b GPIO_PIN9
+//!        - \b GPIO_PIN10
+//!        - \b GPIO_PIN11
+//!        - \b GPIO_PIN12
+//!        - \b GPIO_PIN13
+//!        - \b GPIO_PIN14
+//!        - \b GPIO_PIN15
+//!
+//! \return Logical OR of any of the following:
+//!         - \b GPIO_PIN0
+//!         - \b GPIO_PIN1
+//!         - \b GPIO_PIN2
+//!         - \b GPIO_PIN3
+//!         - \b GPIO_PIN4
+//!         - \b GPIO_PIN5
+//!         - \b GPIO_PIN6
+//!         - \b GPIO_PIN7
+//!         - \b GPIO_PIN8
+//!         - \b GPIO_PIN9
+//!         - \b GPIO_PIN10
+//!         - \b GPIO_PIN11
+//!         - \b GPIO_PIN12
+//!         - \b GPIO_PIN13
+//!         - \b GPIO_PIN14
+//!         - \b GPIO_PIN15
+//!         \n indicating the interrupt status of the selected pins [Default:
+//!         0]
+//
+//*****************************************************************************
+extern uint_fast16_t GPIO_getInterruptStatus(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins);
+
+//*****************************************************************************
+//
+//! \brief This function clears the interrupt flag on the selected pin
+//!
+//! This function clears the interrupt flag on the selected pin. Note that only
+//! Port 1,2,A have this capability.
+//!
+//! \param selectedPort is the selected port.
+//!        Valid values are:
+//!        - \b GPIO_PORT_P1
+//!        - \b GPIO_PORT_P2
+//!        - \b GPIO_PORT_PA
+//! \param selectedPins is the specified pin in the selected port.
+//!        Mask value is the logical OR of any of the following:
+//!        - \b GPIO_PIN0
+//!        - \b GPIO_PIN1
+//!        - \b GPIO_PIN2
+//!        - \b GPIO_PIN3
+//!        - \b GPIO_PIN4
+//!        - \b GPIO_PIN5
+//!        - \b GPIO_PIN6
+//!        - \b GPIO_PIN7
+//!        - \b GPIO_PIN8
+//!        - \b GPIO_PIN9
+//!        - \b GPIO_PIN10
+//!        - \b GPIO_PIN11
+//!        - \b GPIO_PIN12
+//!        - \b GPIO_PIN13
+//!        - \b GPIO_PIN14
+//!        - \b GPIO_PIN15
+//!
+//! Modified bits of \b PxIFG register.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void GPIO_clearInterruptFlag(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins);
+
+//*****************************************************************************
+//
+//! \brief This function selects on what edge the port interrupt flag should be
+//! set for a transition
+//!
+//! This function selects on what edge the port interrupt flag should be set
+//! for a transition. Values for edgeSelect should be
+//! GPIO_LOW_TO_HIGH_TRANSITION or GPIO_HIGH_TO_LOW_TRANSITION.
+//!
+//! \param selectedPort is the selected port.
+//!        Valid values are:
+//!        - \b GPIO_PORT_P1
+//!        - \b GPIO_PORT_P2
+//!        - \b GPIO_PORT_P3
+//!        - \b GPIO_PORT_P4
+//!        - \b GPIO_PORT_P5
+//!        - \b GPIO_PORT_P6
+//!        - \b GPIO_PORT_P7
+//!        - \b GPIO_PORT_P8
+//!        - \b GPIO_PORT_P9
+//!        - \b GPIO_PORT_P10
+//!        - \b GPIO_PORT_P11
+//!        - \b GPIO_PORT_PJ
+//! \param selectedPins is the specified pin in the selected port.
+//!        Mask value is the logical OR of any of the following:
+//!        - \b GPIO_PIN0
+//!        - \b GPIO_PIN1
+//!        - \b GPIO_PIN2
+//!        - \b GPIO_PIN3
+//!        - \b GPIO_PIN4
+//!        - \b GPIO_PIN5
+//!        - \b GPIO_PIN6
+//!        - \b GPIO_PIN7
+//!        - \b GPIO_PIN8
+//!        - \b GPIO_PIN9
+//!        - \b GPIO_PIN10
+//!        - \b GPIO_PIN11
+//!        - \b GPIO_PIN12
+//!        - \b GPIO_PIN13
+//!        - \b GPIO_PIN14
+//!        - \b GPIO_PIN15
+//! \param edgeSelect specifies what transition sets the interrupt flag
+//!        Valid values are:
+//!        - \b GPIO_HIGH_TO_LOW_TRANSITION
+//!        - \b GPIO_LOW_TO_HIGH_TRANSITION
+//!
+//! Modified bits of \b PxIES register.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void GPIO_interruptEdgeSelect(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins, uint_fast8_t edgeSelect);
+
+//*****************************************************************************
+//
+//! \brief This function gets the interrupt status of the provided PIN and
+//!         masks it with the interrupts that are actually enabled. This is
+//!         useful for inside ISRs where the status of only the enabled
+//!         interrupts needs to be checked.
+//!
+//! \param selectedPort is the selected port.
+//!        Valid values are:
+//!        - \b GPIO_PORT_P1
+//!        - \b GPIO_PORT_P2
+//!        - \b GPIO_PORT_P3
+//!        - \b GPIO_PORT_P4
+//!        - \b GPIO_PORT_P5
+//!        - \b GPIO_PORT_P6
+//!        - \b GPIO_PORT_P7
+//!        - \b GPIO_PORT_P8
+//!        - \b GPIO_PORT_P9
+//!        - \b GPIO_PORT_P10
+//!        - \b GPIO_PORT_P11
+//!        - \b GPIO_PORT_PJ
+//!
+//! \return Logical OR of any of the following:
+//!         - \b GPIO_PIN0
+//!         - \b GPIO_PIN1
+//!         - \b GPIO_PIN2
+//!         - \b GPIO_PIN3
+//!         - \b GPIO_PIN4
+//!         - \b GPIO_PIN5
+//!         - \b GPIO_PIN6
+//!         - \b GPIO_PIN7
+//!         - \b GPIO_PIN8
+//!         - \b GPIO_PIN9
+//!         - \b GPIO_PIN10
+//!         - \b GPIO_PIN11
+//!         - \b GPIO_PIN12
+//!         - \b GPIO_PIN13
+//!         - \b GPIO_PIN14
+//!         - \b GPIO_PIN15,
+//!         - \b PIN_ALL8,
+//!         - \b PIN_ALL16
+//!         \n indicating the interrupt status of the selected pins [Default:
+//!         0]
+//
+//*****************************************************************************
+extern uint_fast16_t GPIO_getEnabledInterruptStatus(uint_fast8_t selectedPort);
+
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the port interrupt.
+//!
+//! \param selectedPort is the port to register the interrupt handler
+//!
+//! \param intHandler is a pointer to the function to be called when the port
+//! interrupt occurs.
+//!
+//! This function registers the handler to be called when a port
+//! interrupt occurs. This function enables the global interrupt in the
+//! interrupt controller; specific GPIO interrupts must be enabled
+//! via GPIO_enableInterrupt().  It is the interrupt handler's responsibility to
+//! clear the interrupt source via GPIO_clearInterruptFlag().
+//!
+//! Clock System can generate interrupts when
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void GPIO_registerInterrupt(uint_fast8_t selectedPort,
+        void (*intHandler)(void));
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the port.
+//!
+//! \param selectedPort is the port to unregister the interrupt handler
+//!
+//! This function unregisters the handler to be called when a port
+//! interrupt occurs.  This function also masks off the interrupt in the
+//! interrupt controller so that the interrupt handler no longer is called.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void GPIO_unregisterInterrupt(uint_fast8_t selectedPort);
+
+//*****************************************************************************
+//
+//! This function sets the drive strength to high for the selected port
+//!
+//!
+//! \param selectedPort is the selected port.
+//!             Valid values are:
+//!             - \b GPIO_PORT_P1,
+//!             - \b GPIO_PORT_P2,
+//!             - \b GPIO_PORT_P3,
+//!             - \b GPIO_PORT_P4,
+//!             - \b GPIO_PORT_P5,
+//!             - \b GPIO_PORT_P6,
+//!             - \b GPIO_PORT_P7,
+//!             - \b GPIO_PORT_P8,
+//!             - \b GPIO_PORT_P9,
+//!             - \b GPIO_PORT_P10,
+//!             - \b GPIO_PORT_PJ
+//! \param selectedPins is the specified pin in the selected port.
+//!             Valid values are:
+//!             - \b GPIO_PIN0,
+//!             - \b GPIO_PIN1,
+//!             - \b GPIO_PIN2,
+//!             - \b GPIO_PIN3,
+//!             - \b GPIO_PIN4,
+//!             - \b GPIO_PIN5,
+//!             - \b GPIO_PIN6,
+//!             - \b GPIO_PIN7,
+//!             - \b GPIO_PIN8,
+//!             - \b PIN_ALL8,
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void GPIO_setDriveStrengthHigh(uint_fast8_t selectedPort,
+        uint_fast8_t selectedPins);
+
+//*****************************************************************************
+//
+//! This function sets the drive strength to low for the selected port
+//!
+//!
+//! \param selectedPort is the selected port.
+//!             Valid values are:
+//!             - \b GPIO_PORT_P1,
+//!             - \b GPIO_PORT_P2,
+//!             - \b GPIO_PORT_P3,
+//!             - \b GPIO_PORT_P4,
+//!             - \b GPIO_PORT_P5,
+//!             - \b GPIO_PORT_P6,
+//!             - \b GPIO_PORT_P7,
+//!             - \b GPIO_PORT_P8,
+//!             - \b GPIO_PORT_P9,
+//!             - \b GPIO_PORT_P10,
+//!             - \b GPIO_PORT_PJ
+//! \param selectedPins is the specified pin in the selected port.
+//!             Valid values are:
+//!             - \b GPIO_PIN0,
+//!             - \b GPIO_PIN1,
+//!             - \b GPIO_PIN2,
+//!             - \b GPIO_PIN3,
+//!             - \b GPIO_PIN4,
+//!             - \b GPIO_PIN5,
+//!             - \b GPIO_PIN6,
+//!             - \b GPIO_PIN7,
+//!             - \b GPIO_PIN8,
+//!             - \b PIN_ALL8,
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void GPIO_setDriveStrengthLow(uint_fast8_t selectedPort,
+        uint_fast8_t selectedPins);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif // __GPIO_H__
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/i2c.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/i2c.c
new file mode 100644
index 000000000..034d7b643
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/i2c.c
@@ -0,0 +1,744 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#include <i2c.h>
+#include <interrupt.h>
+#include <debug.h>
+
+void I2C_initMaster(uint32_t moduleInstance, const eUSCI_I2C_MasterConfig *config)
+{
+    uint16_t preScalarValue;
+
+    ASSERT(
+            (EUSCI_B_I2C_CLOCKSOURCE_ACLK == config->selectClockSource)
+            || (EUSCI_B_I2C_CLOCKSOURCE_SMCLK
+                    == config->selectClockSource));
+
+    ASSERT(
+            (EUSCI_B_I2C_SET_DATA_RATE_400KBPS == config->dataRate)
+            || (EUSCI_B_I2C_SET_DATA_RATE_100KBPS == config->dataRate));
+
+    ASSERT(
+            (EUSCI_B_I2C_NO_AUTO_STOP == config->autoSTOPGeneration)
+            || (EUSCI_B_I2C_SET_BYTECOUNT_THRESHOLD_FLAG
+                    == config->autoSTOPGeneration)
+            || (EUSCI_B_I2C_SEND_STOP_AUTOMATICALLY_ON_BYTECOUNT_THRESHOLD
+                    == config->autoSTOPGeneration));
+
+    /* Disable the USCI module and clears the other bits of control register */
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCSWRST_OFS) = 1;
+
+    /* Configure Automatic STOP condition generation */
+    EUSCI_B_CMSIS(moduleInstance)->rCTLW1.r =
+            (EUSCI_B_CMSIS(moduleInstance)->rCTLW1.r & ~UCASTP_M)
+                    | (config->autoSTOPGeneration);
+
+    /* Byte Count Threshold */
+    EUSCI_B_CMSIS(moduleInstance)->rTBCNT.r = config->byteCounterThreshold;
+
+    /*
+     * Configure as I2C master mode.
+     * UCMST = Master mode
+     * UCMODE_3 = I2C mode
+     * UCSYNC = Synchronous mode
+     */
+    EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r =
+            (EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r & ~UCSSEL_M)
+                    | (config->selectClockSource | UCMST | UCMODE_3 | UCSYNC
+                            | UCSWRST);
+
+    /*
+     * Compute the clock divider that achieves the fastest speed less than or
+     * equal to the desired speed.  The numerator is biased to favor a larger
+     * clock divider so that the resulting clock is always less than or equal
+     * to the desired clock, never greater.
+     */
+    preScalarValue = (uint16_t) (config->i2cClk / config->dataRate);
+
+    EUSCI_B_CMSIS(moduleInstance)->rBRW = preScalarValue;
+}
+
+void I2C_initSlave(uint32_t moduleInstance, uint_fast16_t slaveAddress,
+        uint_fast8_t slaveAddressOffset, uint32_t slaveOwnAddressEnable)
+{
+    ASSERT(
+            (EUSCI_B_I2C_OWN_ADDRESS_OFFSET0 == slaveAddressOffset)
+            || (EUSCI_B_I2C_OWN_ADDRESS_OFFSET1 == slaveAddressOffset)
+            || (EUSCI_B_I2C_OWN_ADDRESS_OFFSET2 == slaveAddressOffset)
+            || (EUSCI_B_I2C_OWN_ADDRESS_OFFSET3 == slaveAddressOffset));
+
+    /* Disable the USCI module */
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCSWRST_OFS) = 1;
+
+    /* Clear USCI master mode */
+    EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r =
+            (EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r & (~UCMST))
+                    | (UCMODE_3 + UCSYNC);
+
+    /* Set up the slave address. */
+    HWREG16(moduleInstance + OFS_UCB0I2COA0 + slaveAddressOffset) = slaveAddress
+            + slaveOwnAddressEnable;
+}
+
+void I2C_enableModule(uint32_t moduleInstance)
+{
+    /* Reset the UCSWRST bit to enable the USCI Module */
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCSWRST_OFS) = 0;
+}
+
+void I2C_disableModule(uint32_t moduleInstance)
+{
+    /* Set the UCSWRST bit to disable the USCI Module */
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCSWRST_OFS) = 1;
+    ;
+}
+
+void I2C_setSlaveAddress(uint32_t moduleInstance, uint_fast16_t slaveAddress)
+{
+    /* Set the address of the slave with which the master will communicate */
+    EUSCI_B_CMSIS(moduleInstance)->rI2CSA.r = (slaveAddress);
+}
+
+void I2C_setMode(uint32_t moduleInstance, uint_fast8_t mode)
+{
+    ASSERT(
+            (EUSCI_B_I2C_TRANSMIT_MODE == mode)
+            || (EUSCI_B_I2C_RECEIVE_MODE == mode));
+
+    EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r =
+            (EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r
+                    & (~EUSCI_B_I2C_TRANSMIT_MODE)) | mode;
+
+}
+
+uint8_t I2C_masterReceiveSingleByte(uint32_t moduleInstance)
+{
+    //Set USCI in Receive mode
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTR_OFS) = 0;
+
+    //Send start
+    EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r |= (UCTXSTT + UCTXSTP);
+
+    //Poll for receive interrupt flag.
+    while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCRXIFG_OFS))
+        ;
+
+    //Send single byte data.
+    return EUSCI_B_CMSIS(moduleInstance)->rRXBUF.b.bRXBUF;
+}
+
+void I2C_slavePutData(uint32_t moduleInstance, uint8_t transmitData)
+{
+    //Send single byte data.
+    EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = transmitData;
+}
+
+uint8_t I2C_slaveGetData(uint32_t moduleInstance)
+{
+    //Read a byte.
+    return EUSCI_B_CMSIS(moduleInstance)->rRXBUF.b.bRXBUF;
+}
+
+uint8_t I2C_isBusBusy(uint32_t moduleInstance)
+{
+    //Return the bus busy status.
+    return EUSCI_B_CMSIS(moduleInstance)->rSTATW.b.bBBUSY;
+}
+
+void I2C_masterSendSingleByte(uint32_t moduleInstance, uint8_t txData)
+{
+    //Store current TXIE status
+    uint16_t txieStatus = EUSCI_B_CMSIS(moduleInstance)->rIE.r & UCTXIE;
+
+    //Disable transmit interrupt enable
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r,UCTXIE_OFS) = 0;
+
+    //Send start condition.
+    EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r |= UCTR + UCTXSTT;
+
+    //Poll for transmit interrupt flag.
+    while (!(EUSCI_B_CMSIS(moduleInstance)->rIFG.r & UCTXIFG))
+        ;
+
+    //Send single byte data.
+    EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData;
+
+    //Poll for transmit interrupt flag.
+    while (!(EUSCI_B_CMSIS(moduleInstance)->rIFG.r & UCTXIFG))
+        ;
+
+    //Send stop condition.
+    EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r |= UCTXSTP;
+
+    //Clear transmit interrupt flag before enabling interrupt again
+    EUSCI_B_CMSIS(moduleInstance)->rIFG.r &= ~(UCTXIFG);
+
+    //Reinstate transmit interrupt enable
+    EUSCI_B_CMSIS(moduleInstance)->rIE.r |= txieStatus;
+}
+
+bool I2C_masterSendSingleByteWithTimeout(uint32_t moduleInstance,
+        uint8_t txData, uint32_t timeout)
+{
+    uint16_t txieStatus;
+    uint32_t timeout2 = timeout;
+
+    ASSERT(timeout > 0);
+
+    //Store current TXIE status
+    txieStatus = EUSCI_B_CMSIS(moduleInstance)->rIE.r & UCTXIE;
+
+    //Disable transmit interrupt enable
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r,UCTXIE_OFS) = 0;
+
+    //Send start condition.
+    EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r |= UCTR + UCTXSTT;
+
+    //Poll for transmit interrupt flag.
+    while ((!(EUSCI_B_CMSIS(moduleInstance)->rIFG.r & UCTXIFG)) && --timeout)
+        ;
+
+    //Check if transfer timed out
+    if (timeout == 0)
+        return false;
+
+    //Send single byte data.
+    EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData;
+
+    //Poll for transmit interrupt flag.
+    while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
+            && --timeout2)
+        ;
+
+    //Check if transfer timed out
+    if (timeout2 == 0)
+        return false;
+
+    //Send stop condition.
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1;
+
+    //Clear transmit interrupt flag before enabling interrupt again
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r,UCTXIFG_OFS) = 0;
+
+    //Reinstate transmit interrupt enable
+    EUSCI_B_CMSIS(moduleInstance)->rIE.r |= txieStatus;
+
+    return true;
+}
+
+void I2C_masterSendMultiByteStart(uint32_t moduleInstance, uint8_t txData)
+{
+    //Store current transmit interrupt enable
+    uint16_t txieStatus = EUSCI_B_CMSIS(moduleInstance)->rIE.r & UCTXIE;
+
+    //Disable transmit interrupt enable
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS) = 0;
+
+    //Send start condition.
+    EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r |= UCTR + UCTXSTT;
+
+    //Poll for transmit interrupt flag.
+    while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
+        ;
+
+    //Send single byte data.
+    EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData;
+
+    //Reinstate transmit interrupt enable
+    EUSCI_B_CMSIS(moduleInstance)->rIE.r |= txieStatus;
+}
+
+bool I2C_masterSendMultiByteStartWithTimeout(uint32_t moduleInstance,
+        uint8_t txData, uint32_t timeout)
+{
+    uint16_t txieStatus;
+
+    ASSERT(timeout > 0);
+
+    //Store current transmit interrupt enable
+    txieStatus = EUSCI_B_CMSIS(moduleInstance)->rIE.r & UCTXIE;
+
+    //Disable transmit interrupt enable
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r,UCTXIE_OFS) = 0;
+
+    //Send start condition.
+    EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r |= UCTR + UCTXSTT;
+
+    //Poll for transmit interrupt flag.
+    while ((!(BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
+            && --timeout))
+        ;
+
+    //Check if transfer timed out
+    if (timeout == 0)
+        return false;
+
+    //Send single byte data.
+    EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData;
+
+    //Reinstate transmit interrupt enable
+    EUSCI_B_CMSIS(moduleInstance)->rIE.r |= txieStatus;
+
+    return true;
+}
+
+void I2C_masterSendMultiByteNext(uint32_t moduleInstance, uint8_t txData)
+{
+    //If interrupts are not used, poll for flags
+    if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
+    {
+        //Poll for transmit interrupt flag.
+        while
+            (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
+            ;
+    }
+
+    //Send single byte data.
+    EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData;
+}
+
+bool I2C_masterSendMultiByteNextWithTimeout(uint32_t moduleInstance,
+        uint8_t txData, uint32_t timeout)
+{
+    ASSERT(timeout > 0);
+
+    //If interrupts are not used, poll for flags
+    if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
+    {
+        //Poll for transmit interrupt flag.
+        while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r,
+                UCTXIFG_OFS)) && --timeout)
+            ;
+
+        //Check if transfer timed out
+        if (timeout == 0)
+            return false;
+    }
+
+    //Send single byte data.
+    EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData;
+
+    return true;
+}
+
+void I2C_masterSendMultiByteFinish(uint32_t moduleInstance, uint8_t txData)
+{
+    //If interrupts are not used, poll for flags
+    if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
+    {
+        //Poll for transmit interrupt flag.
+        while
+            (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
+            ;
+    }
+
+    //Send single byte data.
+    EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData;
+
+    //Poll for transmit interrupt flag.
+    while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
+        ;
+
+    //Send stop condition.
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1;
+}
+
+bool I2C_masterSendMultiByteFinishWithTimeout(uint32_t moduleInstance,
+        uint8_t txData, uint32_t timeout)
+{
+    uint32_t timeout2 = timeout;
+
+    ASSERT(timeout > 0);
+
+    //If interrupts are not used, poll for flags
+    if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
+    {
+        //Poll for transmit interrupt flag.
+        while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r,
+                UCTXIFG_OFS)) && --timeout)
+            ;
+
+        //Check if transfer timed out
+        if (timeout == 0)
+            return false;
+    }
+
+    //Send single byte data.
+    EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData;
+
+    //Poll for transmit interrupt flag.
+    while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
+            && --timeout2)
+        ;
+
+    //Check if transfer timed out
+    if (timeout2 == 0)
+        return false;
+
+    //Send stop condition.
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1;
+
+    return true;
+}
+
+void I2C_masterSendMultiByteStop(uint32_t moduleInstance)
+{
+    //If interrupts are not used, poll for flags
+    if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
+    {
+        //Poll for transmit interrupt flag.
+        while
+            (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
+            ;
+    }
+
+    //Send stop condition.
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1;
+}
+
+bool I2C_masterSendMultiByteStopWithTimeout(uint32_t moduleInstance,
+        uint32_t timeout)
+{
+    ASSERT(timeout > 0);
+
+    //If interrupts are not used, poll for flags
+    if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
+    {
+        //Poll for transmit interrupt flag.
+        while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r,
+                UCTXIFG_OFS)) && --timeout)
+            ;
+
+        //Check if transfer timed out
+        if (timeout == 0)
+            return false;
+    }
+
+    //Send stop condition.
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1;
+
+    return 0x01;
+}
+
+void I2C_masterReceiveStart(uint32_t moduleInstance)
+{
+    //Set USCI in Receive mode
+    EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r =
+            (EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r & (~UCTR)) | UCTXSTT;
+}
+
+uint8_t I2C_masterReceiveMultiByteNext(uint32_t moduleInstance)
+{
+    return EUSCI_B_CMSIS(moduleInstance)->rRXBUF.a.bRXBUF;
+}
+
+uint8_t I2C_masterReceiveMultiByteFinish(uint32_t moduleInstance)
+{
+    //Send stop condition.
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1;
+
+    //Wait for Stop to finish
+    while (BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCTXSTP_OFS))
+    {
+        // Wait for RX buffer
+        while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG, UCRXIFG_OFS))
+            ;
+    }
+
+    /* Capture data from receive buffer after setting stop bit due to
+     MSP430 I2C critical timing. */
+    return EUSCI_B_CMSIS(moduleInstance)->rRXBUF.b.bRXBUF;
+}
+
+bool I2C_masterReceiveMultiByteFinishWithTimeout(uint32_t moduleInstance,
+        uint8_t *txData, uint32_t timeout)
+{
+    uint32_t timeout2 = timeout;
+
+    ASSERT(timeout > 0);
+
+    //Send stop condition.
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1;
+
+    //Wait for Stop to finish
+    while (BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCTXSTP_OFS)
+            && --timeout)
+        ;
+
+    //Check if transfer timed out
+    if (timeout == 0)
+        return false;
+
+    // Wait for RX buffer
+    while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCRXIFG_OFS))
+            && --timeout2)
+        ;
+
+    //Check if transfer timed out
+    if (timeout2 == 0)
+        return false;
+
+    //Capture data from receive buffer after setting stop bit due to
+    //MSP430 I2C critical timing.
+    *txData = (EUSCI_B_CMSIS(moduleInstance)->rRXBUF.b.bRXBUF);
+
+    return true;
+}
+
+void I2C_masterReceiveMultiByteStop(uint32_t moduleInstance)
+{
+    //Send stop condition.
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1;
+}
+
+uint8_t I2C_masterReceiveSingle(uint32_t moduleInstance)
+{
+    //Polling RXIFG0 if RXIE is not enabled
+    if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCRXIE0_OFS))
+    {
+        while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r,
+                UCRXIFG0_OFS))
+            ;
+    }
+
+    //Read a byte.
+    return EUSCI_B_CMSIS(moduleInstance)->rRXBUF.b.bRXBUF;
+}
+
+uint32_t I2C_getReceiveBufferAddressForDMA(uint32_t moduleInstance)
+{
+    return moduleInstance + OFS_UCB0RXBUF;
+}
+
+uint32_t I2C_getTransmitBufferAddressForDMA(uint32_t moduleInstance)
+{
+    return moduleInstance + OFS_UCB0TXBUF;
+}
+
+uint8_t I2C_masterIsStopSent(uint32_t moduleInstance)
+{
+    return BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCTXSTP_OFS);
+}
+
+bool I2C_masterIsStartSent(uint32_t moduleInstance)
+{
+    return BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCTXSTT_OFS);
+}
+
+void I2C_masterSendStart(uint32_t moduleInstance)
+{
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTT_OFS) = 1;
+}
+
+void I2C_enableMultiMasterMode(uint32_t moduleInstance)
+{
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCSWRST_OFS) = 1;
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCMM_OFS) = 1;
+}
+
+void I2C_disableMultiMasterMode(uint32_t moduleInstance)
+{
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCSWRST_OFS) = 1;
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCMM_OFS) = 0;
+}
+
+void I2C_enableInterrupt(uint32_t moduleInstance, uint_fast16_t mask)
+{
+    ASSERT(
+            0x00
+            == (mask
+                    & ~(EUSCI_B_I2C_STOP_INTERRUPT
+                            + EUSCI_B_I2C_START_INTERRUPT
+                            + EUSCI_B_I2C_NAK_INTERRUPT
+                            + EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT
+                            + EUSCI_B_I2C_BIT9_POSITION_INTERRUPT
+                            + EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT
+                            + EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT
+                            + EUSCI_B_I2C_TRANSMIT_INTERRUPT0
+                            + EUSCI_B_I2C_TRANSMIT_INTERRUPT1
+                            + EUSCI_B_I2C_TRANSMIT_INTERRUPT2
+                            + EUSCI_B_I2C_TRANSMIT_INTERRUPT3
+                            + EUSCI_B_I2C_RECEIVE_INTERRUPT0
+                            + EUSCI_B_I2C_RECEIVE_INTERRUPT1
+                            + EUSCI_B_I2C_RECEIVE_INTERRUPT2
+                            + EUSCI_B_I2C_RECEIVE_INTERRUPT3)));
+
+    //Enable the interrupt masked bit
+    EUSCI_B_CMSIS(moduleInstance)->rIE.r |= mask;
+}
+
+void I2C_disableInterrupt(uint32_t moduleInstance, uint_fast16_t mask)
+{
+    ASSERT(
+            0x00
+            == (mask
+                    & ~(EUSCI_B_I2C_STOP_INTERRUPT
+                            + EUSCI_B_I2C_START_INTERRUPT
+                            + EUSCI_B_I2C_NAK_INTERRUPT
+                            + EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT
+                            + EUSCI_B_I2C_BIT9_POSITION_INTERRUPT
+                            + EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT
+                            + EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT
+                            + EUSCI_B_I2C_TRANSMIT_INTERRUPT0
+                            + EUSCI_B_I2C_TRANSMIT_INTERRUPT1
+                            + EUSCI_B_I2C_TRANSMIT_INTERRUPT2
+                            + EUSCI_B_I2C_TRANSMIT_INTERRUPT3
+                            + EUSCI_B_I2C_RECEIVE_INTERRUPT0
+                            + EUSCI_B_I2C_RECEIVE_INTERRUPT1
+                            + EUSCI_B_I2C_RECEIVE_INTERRUPT2
+                            + EUSCI_B_I2C_RECEIVE_INTERRUPT3)));
+
+    //Disable the interrupt masked bit
+    EUSCI_B_CMSIS(moduleInstance)->rIE.r &= ~(mask);
+}
+
+void I2C_clearInterruptFlag(uint32_t moduleInstance, uint_fast16_t mask)
+{
+    ASSERT(
+            0x00
+            == (mask
+                    & ~(EUSCI_B_I2C_STOP_INTERRUPT
+                            + EUSCI_B_I2C_START_INTERRUPT
+                            + EUSCI_B_I2C_NAK_INTERRUPT
+                            + EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT
+                            + EUSCI_B_I2C_BIT9_POSITION_INTERRUPT
+                            + EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT
+                            + EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT
+                            + EUSCI_B_I2C_TRANSMIT_INTERRUPT0
+                            + EUSCI_B_I2C_TRANSMIT_INTERRUPT1
+                            + EUSCI_B_I2C_TRANSMIT_INTERRUPT2
+                            + EUSCI_B_I2C_TRANSMIT_INTERRUPT3
+                            + EUSCI_B_I2C_RECEIVE_INTERRUPT0
+                            + EUSCI_B_I2C_RECEIVE_INTERRUPT1
+                            + EUSCI_B_I2C_RECEIVE_INTERRUPT2
+                            + EUSCI_B_I2C_RECEIVE_INTERRUPT3)));
+    //Clear the I2C interrupt source.
+    EUSCI_B_CMSIS(moduleInstance)->rIFG.r &= ~(mask);
+}
+
+uint_fast16_t I2C_getInterruptStatus(uint32_t moduleInstance, uint16_t mask)
+{
+    ASSERT(
+            0x00
+            == (mask
+                    & ~(EUSCI_B_I2C_STOP_INTERRUPT
+                            + EUSCI_B_I2C_START_INTERRUPT
+                            + EUSCI_B_I2C_NAK_INTERRUPT
+                            + EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT
+                            + EUSCI_B_I2C_BIT9_POSITION_INTERRUPT
+                            + EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT
+                            + EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT
+                            + EUSCI_B_I2C_TRANSMIT_INTERRUPT0
+                            + EUSCI_B_I2C_TRANSMIT_INTERRUPT1
+                            + EUSCI_B_I2C_TRANSMIT_INTERRUPT2
+                            + EUSCI_B_I2C_TRANSMIT_INTERRUPT3
+                            + EUSCI_B_I2C_RECEIVE_INTERRUPT0
+                            + EUSCI_B_I2C_RECEIVE_INTERRUPT1
+                            + EUSCI_B_I2C_RECEIVE_INTERRUPT2
+                            + EUSCI_B_I2C_RECEIVE_INTERRUPT3)));
+    //Return the interrupt status of the request masked bit.
+    return EUSCI_B_CMSIS(moduleInstance)->rIFG.r & mask;
+}
+
+uint_fast16_t I2C_getEnabledInterruptStatus(uint32_t moduleInstance)
+{
+    return I2C_getInterruptStatus(moduleInstance,
+    EUSCI_B_CMSIS(moduleInstance)->rIE.r);
+}
+
+uint_fast16_t I2C_getMode(uint32_t moduleInstance)
+{
+    //Read the I2C mode.
+    return (EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r & UCTR);
+}
+
+void I2C_registerInterrupt(uint32_t moduleInstance, void (*intHandler)(void))
+{
+    switch (moduleInstance)
+    {
+    case EUSCI_B0_MODULE:
+        Interrupt_registerInterrupt(INT_EUSCIB0, intHandler);
+        Interrupt_enableInterrupt(INT_EUSCIB0);
+        break;
+    case EUSCI_B1_MODULE:
+        Interrupt_registerInterrupt(INT_EUSCIB1, intHandler);
+        Interrupt_enableInterrupt(INT_EUSCIB1);
+        break;
+#ifdef EUSCI_B2_MODULE
+    case EUSCI_B2_MODULE:
+        Interrupt_registerInterrupt(INT_EUSCIB2, intHandler);
+        Interrupt_enableInterrupt(INT_EUSCIB2);
+        break;
+#endif
+#ifdef EUSCI_B3_MODULE
+    case EUSCI_B3_MODULE:
+        Interrupt_registerInterrupt(INT_EUSCIB3, intHandler);
+        Interrupt_enableInterrupt(INT_EUSCIB3);
+        break;
+#endif
+    default:
+        ASSERT(false);
+    }
+}
+
+void I2C_unregisterInterrupt(uint32_t moduleInstance)
+{
+    switch (moduleInstance)
+    {
+    case EUSCI_B0_MODULE:
+        Interrupt_disableInterrupt(INT_EUSCIB0);
+        Interrupt_unregisterInterrupt(INT_EUSCIB0);
+        break;
+    case EUSCI_B1_MODULE:
+        Interrupt_disableInterrupt(INT_EUSCIB1);
+        Interrupt_unregisterInterrupt(INT_EUSCIB1);
+        break;
+#ifdef EUSCI_B2_MODULE
+    case EUSCI_B2_MODULE:
+        Interrupt_disableInterrupt(INT_EUSCIB2);
+        Interrupt_unregisterInterrupt(INT_EUSCIB2);
+        break;
+#endif
+#ifdef EUSCI_B3_MODULE
+    case EUSCI_B3_MODULE:
+        Interrupt_disableInterrupt(INT_EUSCIB3);
+        Interrupt_unregisterInterrupt(INT_EUSCIB3);
+        break;
+#endif
+    default:
+        ASSERT(false);
+    }
+}
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/i2c.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/i2c.h
new file mode 100644
index 000000000..95ca85dfb
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/i2c.h
@@ -0,0 +1,1407 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef I2C_H_
+#define I2C_H_
+
+//*****************************************************************************
+//
+//! \addtogroup i2c_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <msp.h>
+#include "eusci.h"
+
+#define EUSCI_B_I2C_NO_AUTO_STOP                                       UCASTP_0
+#define EUSCI_B_I2C_SET_BYTECOUNT_THRESHOLD_FLAG                       UCASTP_1
+#define EUSCI_B_I2C_SEND_STOP_AUTOMATICALLY_ON_BYTECOUNT_THRESHOLD     UCASTP_2
+
+#define EUSCI_B_I2C_SET_DATA_RATE_400KBPS                                400000
+#define EUSCI_B_I2C_SET_DATA_RATE_100KBPS                                100000
+
+#define EUSCI_B_I2C_CLOCKSOURCE_ACLK                               UCSSEL__ACLK
+#define EUSCI_B_I2C_CLOCKSOURCE_SMCLK                             UCSSEL__SMCLK
+
+#define EUSCI_B_I2C_OWN_ADDRESS_OFFSET0                                    0x00
+#define EUSCI_B_I2C_OWN_ADDRESS_OFFSET1                                    0x02
+#define EUSCI_B_I2C_OWN_ADDRESS_OFFSET2                                    0x04
+#define EUSCI_B_I2C_OWN_ADDRESS_OFFSET3                                    0x06
+
+#define EUSCI_B_I2C_OWN_ADDRESS_DISABLE                                    0x00
+#define EUSCI_B_I2C_OWN_ADDRESS_ENABLE                                   UCOAEN
+
+#define EUSCI_B_I2C_TRANSMIT_MODE                                          UCTR
+#define EUSCI_B_I2C_RECEIVE_MODE                                           0x00
+
+#define EUSCI_B_I2C_NAK_INTERRUPT                                      UCNACKIE
+#define EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT                            UCALIE
+#define EUSCI_B_I2C_STOP_INTERRUPT                                      UCSTPIE
+#define EUSCI_B_I2C_START_INTERRUPT                                     UCSTTIE
+#define EUSCI_B_I2C_TRANSMIT_INTERRUPT0                                 UCTXIE0
+#define EUSCI_B_I2C_TRANSMIT_INTERRUPT1                                 UCTXIE1
+#define EUSCI_B_I2C_TRANSMIT_INTERRUPT2                                 UCTXIE2
+#define EUSCI_B_I2C_TRANSMIT_INTERRUPT3                                 UCTXIE3
+#define EUSCI_B_I2C_RECEIVE_INTERRUPT0                                  UCRXIE0
+#define EUSCI_B_I2C_RECEIVE_INTERRUPT1                                  UCRXIE1
+#define EUSCI_B_I2C_RECEIVE_INTERRUPT2                                  UCRXIE2
+#define EUSCI_B_I2C_RECEIVE_INTERRUPT3                                  UCRXIE3
+#define EUSCI_B_I2C_BIT9_POSITION_INTERRUPT                            UCBIT9IE
+#define EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT                        UCCLTOIE
+#define EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT                             UCBCNTIE
+
+#define EUSCI_B_I2C_BUS_BUSY                                            UCBBUSY
+#define EUSCI_B_I2C_BUS_NOT_BUSY                                           0x00
+
+#define EUSCI_B_I2C_STOP_SEND_COMPLETE                                     0x00
+#define EUSCI_B_I2C_SENDING_STOP                                        UCTXSTP
+
+#define EUSCI_B_I2C_START_SEND_COMPLETE                                    0x00
+#define EUSCI_B_I2C_SENDING_START                                       UCTXSTT
+
+//*****************************************************************************
+//
+//! \typedef eUSCI_I2C_MasterConfig
+//! \brief Type definition for \link _eUSCI_I2C_MasterConfig \endlink structure
+//!
+//! \struct _eUSCI_I2C_MasterConfig
+//! \brief Configuration structure for master mode in the \b I2C module. See
+//!          \link I2C_initMaster \endlink for parameter documentation.
+//
+//*****************************************************************************
+typedef struct
+{
+    uint_fast8_t selectClockSource;
+    uint32_t i2cClk;
+    uint32_t dataRate;
+    uint_fast8_t byteCounterThreshold;
+    uint_fast8_t autoSTOPGeneration;
+} eUSCI_I2C_MasterConfig;
+
+
+//*****************************************************************************
+//
+//! Initializes the I2C Master block.
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//! \param config Configuration structure for I2C master mode
+//!
+//! <hr>
+//! <b>Configuration options for \link eUSCI_I2C_MasterConfig \endlink structure.</b>
+//! <hr>
+//!
+//! \param selectClockSource is the clock source.
+//!         Valid values are
+//!         - \b EUSCI_B_I2C_CLOCKSOURCE_ACLK
+//!         - \b EUSCI_B_I2C_CLOCKSOURCE_SMCLK
+//! \param i2cClk is the rate of the clock supplied to the I2C module
+//!                   (the frequency in Hz of the clock source specified in
+//!                     selectClockSource).
+//! \param dataRate set up for selecting data transfer rate.
+//!         Valid values are
+//!         - \b EUSCI_B_I2C_SET_DATA_RATE_400KBPS
+//!         - \b EUSCI_B_I2C_SET_DATA_RATE_100KBPS
+//! \param byteCounterThreshold sets threshold for automatic STOP or UCSTPIFG
+//! \param autoSTOPGeneration sets up the STOP condition generation.
+//!         Valid values are
+//!         - \b EUSCI_B_I2C_NO_AUTO_STOP
+//!         - \b EUSCI_B_I2C_SET_BYTECOUNT_THRESHOLD_FLAG
+//!         - \b EUSCI_B_I2C_SEND_STOP_AUTOMATICALLY_ON_BYTECOUNT_THRESHOLD
+//!
+//! This function initializes operation of the I2C Master block.  Upon
+//! successful initialization of the I2C block, this function will have set the
+//! bus speed for the master; however I2C module is still disabled till
+//! I2C_enableModule is invoked
+//!
+//! If the parameter \e dataRate is EUSCI_B_I2C_SET_DATA_RATE_400KBPS, then the
+//! master block will be set up to transfer data at 400 kbps; otherwise, it will
+//! be set up to transfer data at 100 kbps.
+//!
+//! Modified bits are \b UCMST,UCMODE_3,\b UCSYNC of \b UCBxCTL0 register
+//!                   \b UCSSELx, \b UCSWRST, of \b UCBxCTL1 register
+//!                   \b UCBxBR0 and \b UCBxBR1 registers
+//! \return None.
+//
+//*****************************************************************************
+extern void I2C_initMaster(uint32_t moduleInstance,
+        const eUSCI_I2C_MasterConfig *config);
+
+//*****************************************************************************
+//
+//! Initializes the I2C Slave block.
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//! \param slaveAddress 7-bit slave address
+//! \param slaveAddressOffset Own address Offset referred to- 'x' value of
+//!     UCBxI2COAx. Valid values are:
+//!                  - \b EUSCI_B_I2C_OWN_ADDRESS_OFFSET0,
+//!                  - \b EUSCI_B_I2C_OWN_ADDRESS_OFFSET1,
+//!                  - \b EUSCI_B_I2C_OWN_ADDRESS_OFFSET2,
+//!                  - \b EUSCI_B_I2C_OWN_ADDRESS_OFFSET3
+//! \param slaveOwnAddressEnable selects if the specified address is enabled
+//!     or disabled. Valid values are:
+//!                     - \b EUSCI_B_I2C_OWN_ADDRESS_DISABLE,
+//!                     - \b EUSCI_B_I2C_OWN_ADDRESS_ENABLE
+//!
+//! This function initializes operation of the I2C as a Slave mode.  Upon
+//! successful initialization of the I2C blocks, this function will have set
+//! the slave address but the I2C module is still disabled till
+//! I2C_enableModule is invoked.
+//!
+//! The parameter slaveAddress is the value that will be compared against the
+//! slave address sent by an I2C master.
+//!
+//! Modified bits are \b UCMODE_3, \b UCSYNC of \b UCBxCTL0 register
+//!                   \b UCSWRST of \b UCBxCTL1 register
+//!                   \b UCBxI2COA register
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void I2C_initSlave(uint32_t moduleInstance, uint_fast16_t slaveAddress,
+        uint_fast8_t slaveAddressOffset, uint32_t slaveOwnAddressEnable);
+
+//*****************************************************************************
+//
+//! Enables the I2C block.
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//! This will enable operation of the I2C block.
+//! Modified bits are \b UCSWRST of \b UCBxCTL1 register.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void I2C_enableModule(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Disables the I2C block.
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//! This will disable operation of the I2C block.
+//! Modified bits are \b UCSWRST of \b UCBxCTL1 register.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void I2C_disableModule(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Sets the address that the I2C Master will place on the bus.
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//! \param slaveAddress 7-bit slave address
+//!
+//! This function will set the address that the I2C Master will place on the
+//! bus when initiating a transaction.
+//! Modified register is  \b UCBxI2CSA register
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void I2C_setSlaveAddress(uint32_t moduleInstance,
+        uint_fast16_t slaveAddress);
+
+//*****************************************************************************
+//
+//! Sets the mode of the I2C device
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//! \param mode indicates whether module is in transmit/receive mode
+//!     - \b EUSCI_B_I2C_TRANSMIT_MODE
+//!     - \b EUSCI_B_I2C_RECEIVE_MODE [Default value]
+//!
+//! Modified bits are \b UCTR of \b UCBxCTL1 register
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void I2C_setMode(uint32_t moduleInstance, uint_fast8_t mode);
+
+//*****************************************************************************
+//
+//! \brief Gets the mode of the I2C device
+//!
+//! Current I2C transmit/receive mode.
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//! Modified bits are \b UCTR of \b UCBxCTL1 register.
+//!
+//! \return None
+//!         Return one of the following:
+//!         - \b EUSCI_B_I2C_TRANSMIT_MODE
+//!         - \b EUSCI_B_I2C_RECEIVE_MODE
+//!         \n indicating the current mode
+//
+//*****************************************************************************
+extern uint_fast8_t I2C_getMode(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Transmits a byte from the I2C Module.
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//! \param transmitData data to be transmitted from the I2C module
+//!
+//! This function will place the supplied data into I2C transmit data register
+//! to start transmission
+//! Modified register is \b UCBxTXBUF register
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void I2C_slavePutData(uint32_t moduleInstance, uint8_t transmitData);
+
+//*****************************************************************************
+//
+//! Receives a byte that has been sent to the I2C Module.
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//! This function reads a byte of data from the I2C receive data Register.
+//!
+//! \return Returns the byte received from by the I2C module, cast as an
+//! uint8_t.
+//! Modified bit is \b UCBxRXBUF register
+//
+//*****************************************************************************
+extern uint8_t I2C_slaveGetData(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Indicates whether or not the I2C bus is busy.
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//!
+//! This function returns an indication of whether or not the I2C bus is
+//! busy.This function checks the status of the bus via UCBBUSY bit in
+//! UCBxSTAT register.
+//!
+//! \return Returns EUSCI_B_I2C_BUS_BUSY if the I2C Master is busy; otherwise,
+//! returns EUSCI_B_I2C_BUS_NOT_BUSY.
+//
+//*****************************************************************************
+extern uint8_t I2C_isBusBusy(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Does single byte transmission from Master to Slave
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//! \param txData is the data byte to be transmitted
+//!
+//! This function is used by the Master module to send a single byte.
+//! This function
+//! - Sends START
+//! - Transmits the byte to the Slave
+//! - Sends STOP
+//!
+//! Modified registers are \b UCBxIE, \b UCBxCTL1, \b UCBxIFG, \b UCBxTXBUF,
+//! \b UCBxIE
+//!
+//! \return none
+//
+//*****************************************************************************
+extern void I2C_masterSendSingleByte(uint32_t moduleInstance, uint8_t txData);
+
+//*****************************************************************************
+//
+//! Does single byte transmission from Master to Slave with timeout
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//! \param txData is the data byte to be transmitted
+//! \param timeout is the amount of time to wait until giving up
+//!
+//! This function is used by the Master module to send a single byte.
+//! This function
+//! - Sends START
+//! - Transmits the byte to the Slave
+//! - Sends STOP
+//!
+//! Modified registers are \b UCBxIE, \b UCBxCTL1, \b UCBxIFG, \b UCBxTXBUF,
+//! \b UCBxIE
+//!
+//! \return 0x01 or 0x00URE of the transmission process.
+//
+//*****************************************************************************
+extern bool I2C_masterSendSingleByteWithTimeout(uint32_t moduleInstance,
+        uint8_t txData, uint32_t timeout);
+
+//*****************************************************************************
+//
+//! Starts multi-byte transmission from Master to Slave
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//! \param txData is the first data byte to be transmitted
+//!
+//! This function is used by the Master module to send a single byte.
+//! This function
+//! - Sends START
+//! - Transmits the first data byte of a multi-byte transmission to the Slave
+//!
+//! Modified registers are \b UCBxIE, \b UCBxCTL1, \b UCBxIFG, \b UCBxTXBUF,
+//! \b UCBxIE
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void I2C_masterSendMultiByteStart(uint32_t moduleInstance,
+        uint8_t txData);
+
+//*****************************************************************************
+//
+//! Starts multi-byte transmission from Master to Slave with timeout
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//! \param txData is the first data byte to be transmitted
+//! \param timeout is the amount of time to wait until giving up
+//!
+//! This function is used by the Master module to send a single byte.
+//! This function
+//! - Sends START
+//! - Transmits the first data byte of a multi-byte transmission to the Slave
+//!
+//! Modified registers are \b UCBxIE, \b UCBxCTL1, \b UCBxIFG, \b UCBxTXBUF,
+//! \b UCBxIE
+//!
+//! \return 0x01 or 0x00URE of the transmission process.
+//
+//*****************************************************************************
+extern bool I2C_masterSendMultiByteStartWithTimeout(uint32_t moduleInstance,
+        uint8_t txData, uint32_t timeout);
+
+//*****************************************************************************
+//
+//! Continues multi-byte transmission from Master to Slave
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//! \param txData is the next data byte to be transmitted
+//!
+//! This function is used by the Master module continue each byte of a
+//! multi-byte trasmission. This function
+//! - Transmits each data byte of a multi-byte transmission to the Slave
+//!
+//! Modified registers are \b UCBxTXBUF
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void I2C_masterSendMultiByteNext(uint32_t moduleInstance,
+        uint8_t txData);
+
+//*****************************************************************************
+//
+//! Continues multi-byte transmission from Master to Slave with timeout
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//! \param txData is the next data byte to be transmitted
+//!
+//! \param timeout is the amount of time to wait until giving up
+//!
+//! This function is used by the Master module continue each byte of a
+//! multi-byte transmission. This function
+//! - Transmits each data byte of a multi-byte transmission to the Slave
+//!
+//! Modified registers are \b UCBxTXBUF
+//!
+//! \return 0x01 or 0x00URE of the transmission process.
+//
+//*****************************************************************************
+extern bool I2C_masterSendMultiByteNextWithTimeout(uint32_t moduleInstance,
+        uint8_t txData, uint32_t timeout);
+
+//*****************************************************************************
+//
+//! Finishes multi-byte transmission from Master to Slave
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//! \param txData is the last data byte to be transmitted in a multi-byte
+//! transmsission
+//!
+//! This function is used by the Master module to send the last byte and STOP.
+//! This function
+//! - Transmits the last data byte of a multi-byte transmission to the Slave
+//! - Sends STOP
+//!
+//! Modified registers are \b UCBxTXBUF and \b UCBxCTL1.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void I2C_masterSendMultiByteFinish(uint32_t moduleInstance,
+        uint8_t txData);
+
+//*****************************************************************************
+//
+//! Finishes multi-byte transmission from Master to Slave with timeout
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//! \param txData is the last data byte to be transmitted in a multi-byte
+//! transmission
+//! \param timeout is the amount of time to wait until giving up
+//!
+//! This function is used by the Master module to send the last byte and STOP.
+//! This function
+//! - Transmits the last data byte of a multi-byte transmission to the Slave
+//! - Sends STOP
+//!
+//! Modified registers are \b UCBxTXBUF and \b UCBxCTL1.
+//!
+//! \return 0x01 or 0x00URE of the transmission process.
+//
+//*****************************************************************************
+extern bool I2C_masterSendMultiByteFinishWithTimeout(uint32_t moduleInstance,
+        uint8_t txData, uint32_t timeout);
+
+//*****************************************************************************
+//
+//! Send STOP byte at the end of a multi-byte transmission from Master to Slave
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//!
+//! This function is used by the Master module send STOP at the end of a
+//! multi-byte transmission
+//!
+//! This function
+//! - Send a STOP after current transmission is complete
+//!
+//! Modified bits are \b UCTXSTP bit of \b UCBxCTL1.
+//! \return None.
+//
+//*****************************************************************************
+extern void I2C_masterSendMultiByteStop(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Send STOP byte at the end of a multi-byte transmission from Master to Slave
+//! with timeout
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//! \param timeout is the amount of time to wait until giving up
+//!
+//! This function is used by the Master module send STOP at the end of a
+//! multi-byte transmission
+//!
+//! This function
+//! - Send a STOP after current transmission is complete
+//!
+//! Modified bits are \b UCTXSTP bit of \b UCBxCTL1.
+//! \return 0x01 or 0x00URE of the transmission process.
+//
+//*****************************************************************************
+extern bool I2C_masterSendMultiByteStopWithTimeout(uint32_t moduleInstance,
+        uint32_t timeout);
+
+//*****************************************************************************
+//
+//! Starts reception at the Master end
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//!
+//! This function is used by the Master module initiate reception of a single
+//! byte. This function
+//! - Sends START
+//!
+//! Modified bits are \b UCTXSTT bit of \b UCBxCTL1.
+//! \return None.
+//
+//*****************************************************************************
+extern void I2C_masterReceiveStart(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Starts multi-byte reception at the Master end one byte at a time
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//!
+//! This function is used by the Master module to receive each byte of a
+//! multi-byte reception
+//! This function reads currently received byte
+//!
+//! Modified register is \b UCBxRXBUF.
+//! \return Received byte at Master end.
+//
+//*****************************************************************************
+extern uint8_t I2C_masterReceiveMultiByteNext(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Finishes multi-byte reception at the Master end
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//!
+//! This function is used by the Master module to initiate completion of a
+//! multi-byte reception
+//! This function
+//! - Receives the current byte and initiates the STOP from Master to Slave
+//!
+//! Modified bits are \b UCTXSTP bit of \b UCBxCTL1.
+//!
+//! \return Received byte at Master end.
+//
+//*****************************************************************************
+extern uint8_t I2C_masterReceiveMultiByteFinish(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Finishes multi-byte reception at the Master end with timeout
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//! \param txData is a pointer to the location to store the received byte at
+//!     master end
+//! \param timeout is the amount of time to wait until giving up
+//!
+//! This function is used by the Master module to initiate completion of a
+//! multi-byte reception
+//! This function
+//! - Receives the current byte and initiates the STOP from Master to Slave
+//!
+//! Modified bits are \b UCTXSTP bit of \b UCBxCTL1.
+//!
+//! \return 0x01 or 0x00URE of the transmission process.
+//
+//*****************************************************************************
+extern bool I2C_masterReceiveMultiByteFinishWithTimeout(uint32_t moduleInstance,
+        uint8_t *txData, uint32_t timeout);
+
+//*****************************************************************************
+//
+//! Sends the STOP at the end of a multi-byte reception at the Master end
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//!
+//! This function is used by the Master module to initiate STOP
+//!
+//! Modified bits are UCTXSTP bit of UCBxCTL1.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void I2C_masterReceiveMultiByteStop(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Does single byte reception from the slave
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//! This function is used by the Master module to receive a single byte.
+//! This function:
+//! - Sends START and STOP
+//! - Waits for data reception
+//! - Receives one byte from the Slave
+//!
+//! Modified registers are \b UCBxIE, \b UCBxCTL1, \b UCBxIFG, \b UCBxTXBUF,
+//! \b UCBxIE
+//!
+//! \return The byte that has been received from the slave
+//
+//*****************************************************************************
+extern uint8_t I2C_masterReceiveSingleByte(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Receives a byte that has been sent to the I2C Master Module.
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//!
+//! This function reads a byte of data from the I2C receive data Register.
+//!
+//! \return Returns the byte received from by the I2C module, cast as an
+//! uint8_t.
+//
+//*****************************************************************************
+extern uint8_t I2C_masterReceiveSingle(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Returns the address of the RX Buffer of the I2C for the DMA module.
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//!
+//! Returns the address of the I2C RX Buffer. This can be used in conjunction
+//! with the DMA to store the received data directly to memory.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern uint32_t I2C_getReceiveBufferAddressForDMA(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Returns the address of the TX Buffer of the I2C for the DMA module.
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//!
+//! Returns the address of the I2C TX Buffer. This can be used in conjunction
+//! with the DMA to obtain transmitted data directly from memory.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern uint32_t I2C_getTransmitBufferAddressForDMA(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Indicates whether STOP got sent.
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//!
+//! This function returns an indication of whether or not STOP got sent
+//! This function checks the status of the bus via UCTXSTP bit in
+//! UCBxCTL1 register.
+//!
+//! \return Returns EUSCI_B_I2C_STOP_SEND_COMPLETE if the I2C Master
+//!         finished sending STOP; otherwise, returns EUSCI_B_I2C_SENDING_STOP.
+//
+//*****************************************************************************
+extern uint8_t I2C_masterIsStopSent(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Indicates whether Start got sent.
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//!
+//! This function returns an indication of whether or not Start got sent
+//! This function checks the status of the bus via UCTXSTT bit in
+//! UCBxCTL1 register.
+//!
+//! \return Returns true if the START has been sent, false if it is sending
+//
+//*****************************************************************************
+extern bool I2C_masterIsStartSent(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! This function is used by the Master module to initiate START
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//!
+//! This function is used by the Master module to initiate STOP
+//!
+//! Modified bits are UCTXSTT bit of UCBxCTLW0.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void I2C_masterSendStart(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Enables Multi Master Mode
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//!
+//! At the end of this function, the I2C module is still disabled till
+//! I2C_enableModule is invoked
+//!
+//! Modified bits are \b UCSWRST of \b OFS_UCBxCTLW0, \b UCMM bit of
+//! \b UCBxCTLW0
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void I2C_enableMultiMasterMode(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Disables Multi Master Mode
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//!
+//! At the end of this function, the I2C module is still disabled till
+//! I2C_enableModule is invoked
+//!
+//! Modified bits are \b UCSWRST of \b OFS_UCBxCTLW0, \b UCMM bit of
+//! \b UCBxCTLW0
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void I2C_disableMultiMasterMode(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Enables individual I2C interrupt sources.
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//! \param mask is the bit mask of the interrupt sources to
+//!                          be enabled.
+//!
+//! Enables the indicated I2C interrupt sources.  Only the sources that
+//! are enabled can be reflected to the processor interrupt; disabled sources
+//! have no effect on the processor.
+//!
+//! The mask parameter is the logical OR of any of the following:
+//!
+//! - \b EUSCI_B_I2C_STOP_INTERRUPT - STOP condition interrupt
+//! - \b EUSCI_B_I2C_START_INTERRUPT - START condition interrupt
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT0 - Transmit interrupt0
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT1 - Transmit interrupt1
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT2 - Transmit interrupt2
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT3 - Transmit interrupt3
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT0 - Receive interrupt0
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT1 - Receive interrupt1
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT2 - Receive interrupt2
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT3 - Receive interrupt3
+//! - \b EUSCI_B_I2C_NAK_INTERRUPT - Not-acknowledge interrupt
+//! - \b EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT - Arbitration lost interrupt
+//! - \b EUSCI_B_I2C_BIT9_POSITION_INTERRUPT - Bit position 9 interrupt enable
+//! - \b EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT - Clock low timeout interrupt
+//!                                                 enable
+//! - \b EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT - Byte counter interrupt enable
+//!
+//! Modified registers are UCBxIFG and OFS_UCBxIE.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void I2C_enableInterrupt(uint32_t moduleInstance, uint_fast16_t mask);
+
+//*****************************************************************************
+//
+//! Disables individual I2C interrupt sources.
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//! \param mask is the bit mask of the interrupt sources to be
+//! disabled.
+//!
+//! Disables the indicated I2C interrupt sources.  Only the sources that
+//! are enabled can be reflected to the processor interrupt; disabled sources
+//! have no effect on the processor.
+//!
+//! The mask parameter is the logical OR of any of the following:
+//!
+//! - \b EUSCI_B_I2C_STOP_INTERRUPT - STOP condition interrupt
+//! - \b EUSCI_B_I2C_START_INTERRUPT - START condition interrupt
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT0 - Transmit interrupt0
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT1 - Transmit interrupt1
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT2 - Transmit interrupt2
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT3 - Transmit interrupt3
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT0 - Receive interrupt0
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT1 - Receive interrupt1
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT2 - Receive interrupt2
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT3 - Receive interrupt3
+//! - \b EUSCI_B_I2C_NAK_INTERRUPT - Not-acknowledge interrupt
+//! - \b EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT - Arbitration lost interrupt
+//! - \b EUSCI_B_I2C_BIT9_POSITION_INTERRUPT - Bit position 9 interrupt enable
+//! - \b EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT - Clock low timeout interrupt
+//!                                                enable
+//! - \b EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT - Byte counter interrupt enable
+//!
+//! Modified register is \b UCBxIE.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void I2C_disableInterrupt(uint32_t moduleInstance, uint_fast16_t mask);
+
+//*****************************************************************************
+//
+//! Clears I2C interrupt sources.
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//! \param mask is a bit mask of the interrupt sources to be cleared.
+//!
+//! The I2C interrupt source is cleared, so that it no longer asserts.
+//! The highest interrupt flag is automatically cleared when an interrupt vector
+//! generator is used.
+//!
+//! The mask parameter has the same definition as the mask
+//! parameter to I2C_enableInterrupt().
+//!
+//! Modified register is \b UCBxIFG.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void I2C_clearInterruptFlag(uint32_t moduleInstance, uint_fast16_t mask);
+
+//*****************************************************************************
+//
+//! Gets the current I2C interrupt status.
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//! \param mask is the masked interrupt flag status to be returned.
+//!        Mask value is the logical OR of any of the following:
+//!        - \b EUSCI_B_I2C_NAK_INTERRUPT - Not-acknowledge interrupt
+//!        - \b EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT - Arbitration lost
+//!           interrupt
+//!        - \b EUSCI_B_I2C_STOP_INTERRUPT - STOP condition interrupt
+//!        - \b EUSCI_B_I2C_START_INTERRUPT - START condition interrupt
+//!        - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT0 - Transmit interrupt0
+//!        - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT1 - Transmit interrupt1
+//!        - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT2 - Transmit interrupt2
+//!        - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT3 - Transmit interrupt3
+//!        - \b EUSCI_B_I2C_RECEIVE_INTERRUPT0 - Receive interrupt0
+//!        - \b EUSCI_B_I2C_RECEIVE_INTERRUPT1 - Receive interrupt1
+//!        - \b EUSCI_B_I2C_RECEIVE_INTERRUPT2 - Receive interrupt2
+//!        - \b EUSCI_B_I2C_RECEIVE_INTERRUPT3 - Receive interrupt3
+//!        - \b EUSCI_B_I2C_BIT9_POSITION_INTERRUPT - Bit position 9 interrupt
+//!        - \b EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT - Clock low timeout
+//!           interrupt enable
+//!        - \b EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT - Byte counter interrupt
+//!           enable
+//!
+//! \return the masked status of the interrupt flag
+//! - \b EUSCI_B_I2C_STOP_INTERRUPT - STOP condition interrupt
+//! - \b EUSCI_B_I2C_START_INTERRUPT - START condition interrupt
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT0 - Transmit interrupt0
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT1 - Transmit interrupt1
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT2 - Transmit interrupt2
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT3 - Transmit interrupt3
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT0 - Receive interrupt0
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT1 - Receive interrupt1
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT2 - Receive interrupt2
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT3 - Receive interrupt3
+//! - \b EUSCI_B_I2C_NAK_INTERRUPT - Not-acknowledge interrupt
+//! - \b EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT - Arbitration lost interrupt
+//! - \b EUSCI_B_I2C_BIT9_POSITION_INTERRUPT - Bit position 9 interrupt enable
+//! - \b EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT - Clock low timeout interrupt
+//!                                                enable
+//! - \b EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT - Byte counter interrupt enable
+//
+//*****************************************************************************
+uint_fast16_t I2C_getInterruptStatus(uint32_t moduleInstance, uint16_t mask);
+
+//*****************************************************************************
+//
+//! Gets the current I2C interrupt status masked with the enabled interrupts.
+//! This function is useful to call in ISRs to get a list of pending interrupts
+//! that are actually enabled and could have caused the ISR.
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//! \return the masked status of the interrupt flag
+//! - \b EUSCI_B_I2C_STOP_INTERRUPT - STOP condition interrupt
+//! - \b EUSCI_B_I2C_START_INTERRUPT - START condition interrupt
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT0 - Transmit interrupt0
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT1 - Transmit interrupt1
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT2 - Transmit interrupt2
+//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT3 - Transmit interrupt3
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT0 - Receive interrupt0
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT1 - Receive interrupt1
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT2 - Receive interrupt2
+//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT3 - Receive interrupt3
+//! - \b EUSCI_B_I2C_NAK_INTERRUPT - Not-acknowledge interrupt
+//! - \b EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT - Arbitration lost interrupt
+//! - \b EUSCI_B_I2C_BIT9_POSITION_INTERRUPT - Bit position 9 interrupt enable
+//! - \b EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT - Clock low timeout interrupt
+//!                                                enable
+//! - \b EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT - Byte counter interrupt enable
+//
+//*****************************************************************************
+extern uint_fast16_t I2C_getEnabledInterruptStatus(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for I2C interrupts.
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//! \param intHandler is a pointer to the function to be called when the
+//! timer capture compare interrupt occurs.
+//!
+//! This function registers the handler to be called when an I2C
+//! interrupt occurs. This function enables the global interrupt in the
+//! interrupt controller; specific I2C interrupts must be enabled
+//! via I2C_enableInterrupt().  It is the interrupt handler's responsibility to
+//! clear the interrupt source via I2C_clearInterruptFlag().
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void I2C_registerInterrupt(uint32_t moduleInstance,
+        void (*intHandler)(void));
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the timer
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  <br>It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//! This function unregisters the handler to be called when timer
+//! interrupt occurs.  This function also masks off the interrupt in the
+//! interrupt controller so that the interrupt handler no longer is called.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void I2C_unregisterInterrupt(uint32_t moduleInstance);
+
+/* Backwards Compatibility Layer */
+#define EUSCI_B_I2C_slaveInit I2C_initSlave
+#define EUSCI_B_I2C_enable I2C_enableModule
+#define EUSCI_B_I2C_disable I2C_disableModule
+#define EUSCI_B_I2C_setSlaveAddress I2C_setSlaveAddress
+#define EUSCI_B_I2C_setMode I2C_setMode
+#define EUSCI_B_I2C_getMode I2C_getMode
+#define EUSCI_B_I2C_slaveDataPut I2C_slavePutData
+#define EUSCI_B_I2C_slaveDataGet I2C_slaveGetData
+#define EUSCI_B_I2C_isBusBusy I2C_isBusBusy
+#define EUSCI_B_I2C_masterIsStopSent I2C_masterIsStopSent
+#define EUSCI_B_I2C_masterIsStartSent I2C_masterIsStartSent
+#define EUSCI_B_I2C_enableInterrupt I2C_enableInterrupt
+#define EUSCI_B_I2C_disableInterrupt I2C_disableInterrupt
+#define EUSCI_B_I2C_clearInterruptFlag I2C_clearInterruptFlag
+#define EUSCI_B_I2C_getInterruptStatus  I2C_getEnabledInterruptStatus
+#define EUSCI_B_I2C_masterSendSingleByte I2C_masterSendSingleByte
+#define EUSCI_B_I2C_masterReceiveSingleByte I2C_masterReceiveSingleByte
+#define EUSCI_B_I2C_masterSendSingleByteWithTimeout I2C_masterSendSingleByteWithTimeout
+#define EUSCI_B_I2C_masterMultiByteSendStart I2C_masterSendMultiByteStart
+#define EUSCI_B_I2C_masterMultiByteSendStartWithTimeout I2C_masterSendMultiByteStartWithTimeout
+#define EUSCI_B_I2C_masterMultiByteSendNext I2C_masterSendMultiByteNext
+#define EUSCI_B_I2C_masterMultiByteSendNextWithTimeout I2C_masterSendMultiByteNextWithTimeout
+#define EUSCI_B_I2C_masterMultiByteSendFinish I2C_masterSendMultiByteFinish
+#define EUSCI_B_I2C_masterMultiByteSendFinishWithTimeout I2C_masterSendMultiByteFinishWithTimeout
+#define EUSCI_B_I2C_masterSendStart I2C_masterSendStart
+#define EUSCI_B_I2C_masterMultiByteSendStop I2C_masterSendMultiByteStop
+#define EUSCI_B_I2C_masterMultiByteSendStopWithTimeout I2C_masterSendMultiByteStopWithTimeout
+#define EUSCI_B_I2C_masterReceiveStart I2C_masterReceiveStart
+#define EUSCI_B_I2C_masterMultiByteReceiveNext I2C_masterReceiveMultiByteNext
+#define EUSCI_B_I2C_masterMultiByteReceiveFinish I2C_masterReceiveMultiByteFinish
+#define EUSCI_B_I2C_masterMultiByteReceiveFinishWithTimeout I2C_masterReceiveMultiByteFinishWithTimeout
+#define EUSCI_B_I2C_masterMultiByteReceiveStop I2C_masterReceiveMultiByteStop
+#define EUSCI_B_I2C_enableMultiMasterMode I2C_enableMultiMasterMode
+#define EUSCI_B_I2C_disableMultiMasterMode I2C_disableMultiMasterMode
+#define EUSCI_B_I2C_masterSingleReceive I2C_masterReceiveSingle
+#define EUSCI_B_I2C_getReceiveBufferAddressForDMA I2C_getReceiveBufferAddressForDMA
+#define EUSCI_B_I2C_getTransmitBufferAddressForDMA I2C_getTransmitBufferAddressForDMA
+
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif /* I2C_H_ */
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/cmsis_ccs.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/cmsis_ccs.h
new file mode 100644
index 000000000..84b3d2689
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/cmsis_ccs.h
@@ -0,0 +1,230 @@
+//*****************************************************************************
+//
+// Copyright (C) 2012 - 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+//  Redistributions of source code must retain the above copyright
+//  notice, this list of conditions and the following disclaimer.
+//
+//  Redistributions in binary form must reproduce the above copyright
+//  notice, this list of conditions and the following disclaimer in the
+//  documentation and/or other materials provided with the
+//  distribution.
+//
+//  Neither the name of Texas Instruments Incorporated nor the names of
+//  its contributors may be used to endorse or promote products derived
+//  from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// MSP432 Family CMSIS Definitions
+//
+//****************************************************************************
+
+#ifndef CMSIS_CCS_H_
+#define CMSIS_CCS_H_
+
+//*****************************************************************************
+// CMSIS-compatible instruction calls
+//*****************************************************************************
+
+// No Operation
+__attribute__( ( always_inline ) ) static inline void __nop(void)
+{
+	__asm("  nop");
+}
+
+// Wait For Interrupt
+__attribute__( ( always_inline ) ) static inline void __wfi(void)
+{
+	__asm("  wfi");
+}
+
+// Wait For Event
+__attribute__( ( always_inline ) ) static inline void __wfe(void)
+{
+	__asm("  wfe");
+}
+
+// Enable Interrupts
+__attribute__( ( always_inline ) ) static inline void __enable_irq(void)
+{
+	__asm("  cpsie i");
+}
+
+// Disable Interrupts
+__attribute__( ( always_inline ) ) static inline void __disable_irq(void)
+{
+	__asm("  cpsid i");
+}
+
+// Data Synchronization Barrier
+__attribute__( ( always_inline ) ) static inline void __DSB(void)
+{
+	__asm("  dsb");
+}
+
+#if (0)
+// Get Main Stack Pointer
+static inline uint32_t __get_MSP(void)
+{
+	register uint32_t result;
+	//__asm ("  mrs result, msp");
+	return(result);
+}
+
+// Set Main Stack Pointer
+static inline void __set_MSP(uint32_t topOfMainStack)
+{
+	asm(" .global topOfMainStack");
+	__asm ("  msr msp, topOfMainStack");
+}
+
+
+// Get Priority Mask
+static inline uint32_t __get_PRIMASK(void)
+{
+	uint32_t result;
+	__asm ("  mrs result, primask");
+	return(result);
+}
+
+
+// Set Priority Mask
+static inline void __set_PRIMASK(uint32_t priMask)
+{
+	__asm ("  msr primask, priMask");
+}
+#endif
+
+
+//
+// 	v5e, v6, Cortex-M3, Cortex-M4, Cortex-R4, and Cortex-A8 compiler intrinsics
+//
+#define __CLZ		_norm
+#define __SXTB		_sxtb
+#define __SXTH		_sxth
+#define __UXTB		_uxtb
+#define __UXTH		_uxth
+//  CCS supports intrinsics to take advantage of the shift operand left/right
+//	  before saturation extension of SSAT, but CMSIS does not take advantage
+//	  of those, so tell the compiler to use a sat & shift left with a shift
+//	  value of 0 whenever it encounters an SSAT
+#define __SSAT(VAL, BITPOS) \
+	_ssatl(VAL , 0, BITPOS)
+
+//
+//  Only define M4 based intrinsics if we're not using an M4
+//
+#if defined (__TI_TMS470_V7M4__)
+//		
+//	V5E, V6, Cortex-M4, Cortex-R4, and Cortex-A8 compiler intrinsics
+//
+#define __QADD		_sadd
+#define __QDADD		_sdadd
+#define __QDSUB		_sdsub
+#define	__SMLABB	_smlabb
+#define	__SMLABT	_smlabt
+#define __SMLALBB	_smlalbb
+#define __SMLALBT	_smlalbt
+#define __SMLALTB	_smlaltb
+#define __SMLALTT	_smlaltt
+#define __SMLATB	_smlatb
+#define __SMLATT	_smlatt
+#define __SMLAWB	_smlawb
+#define __SMLAWT	_smlawt
+
+#define __SMULBB	_smulbb
+#define __SMULBT	_smulbt
+#define __SMULTB	_smultb
+#define __SMULTT	_smultt
+#define __SMULWB	_smulwb
+#define __SMULWT	_smulwt
+#define __QSUB		_ssub
+#define __SUBC		_subc
+
+//
+//	v6, Cortex-M4, Cortex-R4, and Cortex-A8 compiler intrinsics
+//
+#define __SHASX		_shaddsubx
+#define __SHSAX		_shsubaddx
+#define __PKHBT		_pkhbt
+#define __PKHTB		_pkhtb
+#define __QADD16	_qadd16
+#define __QADD8		_qadd8
+#define __QSUB16	_qsub16
+#define __QSUB8		_qsub8
+#define __QASX		_saddsubx
+#define __QSAX		_qsubaddx
+#define __SADD16	_sadd16
+#define __SADD8		_sadd8
+#define __SASX		_saddsubx
+#define __SEL		_sel
+#define __SHADD16	_shadd16
+#define __SHADD8	_shadd8
+#define __SHSUB16	_shsub16
+#define __SHSUB8	_shsub8
+#define __SMLAD		_smlad
+#define __SMLADX	_smladx
+#define __SMLALD	_smlald
+#define __SMLALDX	_smlaldx
+#define __SMLSD		_smlsd
+#define __SMLSDX	_smlsdx
+#define __SMLSLD	_smlsld
+#define __SMLSLDX	_smlsldx
+#define __SMMLA		_smmla
+#define __SMMLAR	_smmlar
+#define __SMMLS		_smmls
+#define __SMMLSR	_smmlsr
+#define __SMMUL		_smmul
+#define __SMMULR	_smmulr
+#define __SMUAD		_smuad
+#define __SMUADX	_smuadx
+#define __SMUSD		_smusd
+#define __SMUSDX	_smusd
+#define __SSAT16	_ssat16
+#define __SSUB16	_ssub16
+#define __SSUB8		_ssub8
+#define __SSAX		_ssubaddx
+#define __SXTAB		_sxtab
+#define __SXTAB16	_sxtab16
+#define __SXTAH		_sxtah
+#define __UMAAL		_umaal
+#define __UADD16	_uadd16
+#define __UADD8		_uadd8
+#define __UHADD16	_uhadd16
+#define __UHADD8	_uhadd8
+#define __UASX		_uaddsubx
+#define __UHSUB16	_uhsub16
+#define __UHSUB8	_uhsub8
+#define __UQADD16	_uqadd16
+#define __UQADD8	_uqadd8
+#define __UQASX		_uqaddsubx
+#define __UQSUB16	_uqsub16
+#define __UQSUB8	_uqsub8
+#define __UQSAX		_uqsubaddx
+#define __USAD8		_usad8
+#define __USAT16	_usat16
+#define __USUB16	_usub16
+#define __USUB8		_usub8
+#define __USAX		_usubaddx
+#define __UXTAB		_uxtab
+#define __UXTAB16	_uxtab16
+#define __UXTAH		_uxtah
+#define __UXTB16	_uxtb16
+#endif /*__TI_TMS470_V7M4__*/
+
+#endif /*CMSIS_CCS_H_*/
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cm4.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cm4.h
new file mode 100644
index 000000000..2c8b0882c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cm4.h
@@ -0,0 +1,1772 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM4_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+#include <core_cm4_simd.h>               /* Compiler specific SIMD Intrinsics               */
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+    \brief      Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
+  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cm4_simd.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cm4_simd.h
new file mode 100644
index 000000000..af1831ee1
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cm4_simd.h
@@ -0,0 +1,673 @@
+/**************************************************************************//**
+ * @file     core_cm4_simd.h
+ * @brief    CMSIS Cortex-M4 SIMD Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_SIMD_H
+#define __CORE_CM4_SIMD_H
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_iar.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_ccs.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLALD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLALDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLSLD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLSLDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+/* not yet supported */
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CORE_CM4_SIMD_H */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cmFunc.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cmFunc.h
new file mode 100644
index 000000000..139bc3c5e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cmFunc.h
@@ -0,0 +1,636 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cmInstr.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cmInstr.h
new file mode 100644
index 000000000..8946c2c49
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cmInstr.h
@@ -0,0 +1,688 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V3.20
+ * @date     05. March 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2)); 
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+   uint32_t result;
+
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp.h
new file mode 100644
index 000000000..67ff5b0ef
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp.h
@@ -0,0 +1,55 @@
+//*****************************************************************************
+//
+// Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/ 
+//
+// Redistribution and use in source and binary forms, with or without 
+// modification, are permitted provided that the following conditions 
+// are met:
+//
+//  Redistributions of source code must retain the above copyright 
+//  notice, this list of conditions and the following disclaimer.
+//
+//  Redistributions in binary form must reproduce the above copyright
+//  notice, this list of conditions and the following disclaimer in the 
+//  documentation and/or other materials provided with the   
+//  distribution.
+//
+//  Neither the name of Texas Instruments Incorporated nor the names of
+//  its contributors may be used to endorse or promote products derived
+//  from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// MSP432 Family Generic Include File
+//
+// File creation date: 2015-01-02
+//
+//*****************************************************************************
+
+#ifndef __MSP432_H__
+#define __MSP432_H__
+
+//****************************************************************************
+// MSP432 devices
+//****************************************************************************
+#if defined (__MSP432P401R__)
+#include "msp432p401r.h"
+//****************************************************************************
+// Failed to match a default include file
+//****************************************************************************
+#else
+#error "Failed to match a default include file"
+#endif
+
+#endif // __MSP432_H__
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp432.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp432.h
new file mode 100644
index 000000000..9f6e1aae7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp432.h
@@ -0,0 +1,55 @@
+//*****************************************************************************
+//
+// Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/ 
+//
+// Redistribution and use in source and binary forms, with or without 
+// modification, are permitted provided that the following conditions 
+// are met:
+//
+//  Redistributions of source code must retain the above copyright 
+//  notice, this list of conditions and the following disclaimer.
+//
+//  Redistributions in binary form must reproduce the above copyright
+//  notice, this list of conditions and the following disclaimer in the 
+//  documentation and/or other materials provided with the   
+//  distribution.
+//
+//  Neither the name of Texas Instruments Incorporated nor the names of
+//  its contributors may be used to endorse or promote products derived
+//  from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// MSP432 Family Generic Include File
+//
+// File creation date: 2015-01-05
+//
+//*****************************************************************************
+
+#ifndef __MSP432_H__
+#define __MSP432_H__
+
+//****************************************************************************
+// MSP432 devices
+//****************************************************************************
+#if defined (__MSP432P401R__)
+#include "msp432p401r.h"
+//****************************************************************************
+// Failed to match a default include file
+//****************************************************************************
+#else
+#error "Failed to match a default include file"
+#endif
+
+#endif // __MSP432_H__
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp432p401r.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp432p401r.h
new file mode 100644
index 000000000..7bf3e6d63
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp432p401r.h
@@ -0,0 +1,18130 @@
+//*****************************************************************************
+//
+// Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+//  Redistributions of source code must retain the above copyright
+//  notice, this list of conditions and the following disclaimer.
+//
+//  Redistributions in binary form must reproduce the above copyright
+//  notice, this list of conditions and the following disclaimer in the
+//  documentation and/or other materials provided with the
+//  distribution.
+//
+//  Neither the name of Texas Instruments Incorporated nor the names of
+//  its contributors may be used to endorse or promote products derived
+//  from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// MSP432P401R Register Definitions
+//
+// This file includes definitions that are compatible with MSP430 code,
+// and additionally CMSIS compliant definitions
+//
+// When using MSP430 definitions the physical registers can be directly
+// accessed, e.g.
+//  - ADC14CTL0 |= ADC14SSEL__ACLK;
+//
+// When using CMSIS definitions, the register and bit defines have been
+// reformatted and shortened.
+//  - Registers:       ModuleName[ModuleInstance]->rRegisterName.r
+//  - Bits:            ModuleName[ModuleInstance]->rRegisterName.b.bBitName
+//  - Alternate Bits:  ModuleName[ModuleInstance]->rRegisterName.a.bBitName
+//
+// Writing to CMSIS bit fields can be done through both register level
+// access or bit level access, e.g.
+//  - ADC14->rCTL0.r       |= ADC14SSEL__ACLK;
+//  - ADC14->rCTL0.b.bSSEL  = ADC14SSEL__ACLK >> ADC14SSEL_OFS;
+//
+// File creation date: 2015-01-05
+//
+//****************************************************************************
+
+#ifndef __MSP432P401R_H__
+#define __MSP432P401R_H__
+
+// Use standard integer types with explicit width
+#include <stdint.h>
+
+// Remap MSP430 intrinsics to ARM equivalents
+#include "msp_compatibility.h"
+
+//*****************************************************************************
+// CMSIS-compatible Interrupt Number Definition
+//*****************************************************************************
+#ifndef __CMSIS_CONFIG__
+#define __CMSIS_CONFIG__
+
+typedef enum IRQn
+{
+  // Cortex-M4 Processor Exceptions Numbers
+  NonMaskableInt_IRQn         = -14,    /*  2 Non Maskable Interrupt */
+  HardFault_IRQn              = -13,    /*  3 Hard Fault Interrupt */
+  MemoryManagement_IRQn       = -12,    /*  4 Memory Management Interrupt */
+  BusFault_IRQn               = -11,    /*  5 Bus Fault Interrupt */
+  UsageFault_IRQn             = -10,    /*  6 Usage Fault Interrupt */
+  SVCall_IRQn                 = -5,     /* 11 SV Call Interrupt */
+  DebugMonitor_IRQn           = -4,     /* 12 Debug Monitor Interrupt */
+  PendSV_IRQn                 = -2,     /* 14 Pend SV Interrupt */
+  SysTick_IRQn                = -1,     /* 15 System Tick Interrupt */
+  //  Peripheral Exceptions Numbers
+  PSS_IRQn                    =  0,     /* 16 PSS Interrupt */
+  CS_IRQn                     =  1,     /* 17 CS Interrupt */
+  PCM_IRQn                    =  2,     /* 18 PCM Interrupt */
+  WDT_A_IRQn                  =  3,     /* 19 WDT_A Interrupt */
+  FPU_IRQn                    =  4,     /* 20 FPU Interrupt */
+  FLCTL_IRQn                  =  5,     /* 21 FLCTL Interrupt */
+  COMP_E0_IRQn                =  6,     /* 22 COMP_E0 Interrupt */
+  COMP_E1_IRQn                =  7,     /* 23 COMP_E1 Interrupt */
+  TA0_0_IRQn                  =  8,     /* 24 TA0_0 Interrupt */
+  TA0_N_IRQn                  =  9,     /* 25 TA0_N Interrupt */
+  TA1_0_IRQn                  = 10,     /* 26 TA1_0 Interrupt */
+  TA1_N_IRQn                  = 11,     /* 27 TA1_N Interrupt */
+  TA2_0_IRQn                  = 12,     /* 28 TA2_0 Interrupt */
+  TA2_N_IRQn                  = 13,     /* 29 TA2_N Interrupt */
+  TA3_0_IRQn                  = 14,     /* 30 TA3_0 Interrupt */
+  TA3_N_IRQn                  = 15,     /* 31 TA3_N Interrupt */
+  EUSCIA0_IRQn                = 16,     /* 32 EUSCIA0 Interrupt */
+  EUSCIA1_IRQn                = 17,     /* 33 EUSCIA1 Interrupt */
+  EUSCIA2_IRQn                = 18,     /* 34 EUSCIA2 Interrupt */
+  EUSCIA3_IRQn                = 19,     /* 35 EUSCIA3 Interrupt */
+  EUSCIB0_IRQn                = 20,     /* 36 EUSCIB0 Interrupt */
+  EUSCIB1_IRQn                = 21,     /* 37 EUSCIB1 Interrupt */
+  EUSCIB2_IRQn                = 22,     /* 38 EUSCIB2 Interrupt */
+  EUSCIB3_IRQn                = 23,     /* 39 EUSCIB3 Interrupt */
+  ADC14_IRQn                  = 24,     /* 40 ADC14 Interrupt */
+  T32_INT1_IRQn               = 25,     /* 41 T32_INT1 Interrupt */
+  T32_INT2_IRQn               = 26,     /* 42 T32_INT2 Interrupt */
+  T32_INTC_IRQn               = 27,     /* 43 T32_INTC Interrupt */
+  AES256_IRQn                 = 28,     /* 44 AES256 Interrupt */
+  RTC_C_IRQn                  = 29,     /* 45 RTC_C Interrupt */
+  DMA_ERR_IRQn                = 30,     /* 46 DMA_ERR Interrupt */
+  DMA_INT3_IRQn               = 31,     /* 47 DMA_INT3 Interrupt */
+  DMA_INT2_IRQn               = 32,     /* 48 DMA_INT2 Interrupt */
+  DMA_INT1_IRQn               = 33,     /* 49 DMA_INT1 Interrupt */
+  DMA_INT0_IRQn               = 34,     /* 50 DMA_INT0 Interrupt */
+  PORT1_IRQn                  = 35,     /* 51 PORT1 Interrupt */
+  PORT2_IRQn                  = 36,     /* 52 PORT2 Interrupt */
+  PORT3_IRQn                  = 37,     /* 53 PORT3 Interrupt */
+  PORT4_IRQn                  = 38,     /* 54 PORT4 Interrupt */
+  PORT5_IRQn                  = 39,     /* 55 PORT5 Interrupt */
+  PORT6_IRQn                  = 40      /* 56 PORT6 Interrupt */
+} IRQn_Type;
+
+//*****************************************************************************
+// CMSIS-compatible configuration of the Cortex-M4 Processor and Core Peripherals
+//*****************************************************************************
+#define __MPU_PRESENT           1     // MPU present or not
+#define __NVIC_PRIO_BITS        3     // Number of Bits used for Prio Levels
+#define __FPU_PRESENT           1     // FPU present or not
+
+#endif // __CMSIS_CONFIG__
+
+// Include CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+#ifdef __TMS470__
+#pragma diag_push
+#pragma CHECK_ULP("none")
+#include "core_cm4.h"
+#pragma diag_pop
+#else
+#include "core_cm4.h"
+#endif
+
+//*****************************************************************************
+// Definition of standard bits
+//*****************************************************************************
+#define BIT0                                               (0x0001u)
+#define BIT1                                               (0x0002u)
+#define BIT2                                               (0x0004u)
+#define BIT3                                               (0x0008u)
+#define BIT4                                               (0x0010u)
+#define BIT5                                               (0x0020u)
+#define BIT6                                               (0x0040u)
+#define BIT7                                               (0x0080u)
+#define BIT8                                               (0x0100u)
+#define BIT9                                               (0x0200u)
+#define BITA                                               (0x0400u)
+#define BITB                                               (0x0800u)
+#define BITC                                               (0x1000u)
+#define BITD                                               (0x2000u)
+#define BITE                                               (0x4000u)
+#define BITF                                               (0x8000u)
+#define BIT(x)                                             (1 << (x))
+
+//*****************************************************************************
+// Definitions for 8/16/32-bit wide memory access
+//*****************************************************************************
+#define HWREG8(x)                                          (*((volatile uint8_t *)(x)))
+#define HWREG16(x)                                         (*((volatile uint16_t *)(x)))
+#define HWREG32(x)                                         (*((volatile uint32_t *)(x)))
+#define HWREG(x)                                           (HWREG16(x))
+#define HWREG8_L(x)                                        (*((volatile uint8_t *)((uint8_t *)&x)))
+#define HWREG8_H(x)                                        (*((volatile uint8_t *)(((uint8_t *)&x)+1)))
+#define HWREG16_L(x)                                       (*((volatile uint16_t *)((uint16_t *)&x)))
+#define HWREG16_H(x)                                       (*((volatile uint16_t *)(((uint16_t *)&x)+1)))
+
+//*****************************************************************************
+// Definitions for 8/16/32-bit wide bit band access
+//*****************************************************************************
+#define HWREGBIT8(x, b)                                    (HWREG8(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
+#define HWREGBIT16(x, b)                                   (HWREG16(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
+#define HWREGBIT32(x, b)                                   (HWREG32(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
+#define BITBAND_SRAM(x, b)                                 (*((volatile uint8_t *) (0x22000000 +  (((uint32_t)(uint32_t *)&x) - 0x20000000)*32 + b*4)))
+#define BITBAND_PERI(x, b)                                 (*((volatile uint8_t *) (0x42000000 +  (((uint32_t)(uint32_t *)&x) - 0x40000000)*32 + b*4)))
+
+//*****************************************************************************
+// Device memory map
+//*****************************************************************************
+#define __MAIN_MEMORY_START__                              (0x00000000)          /* Main Flash memory start address */
+#define __MAIN_MEMORY_END__                                (0x0003FFFF)          /* Main Flash memory end address */
+#define __BSL_MEMORY_START__                               (0x00202000)          /* BSL memory start address */
+#define __BSL_MEMORY_END__                                 (0x00203FFF)          /* BSL memory end address */
+#define __SRAM_START__                                     (0x20000000)          /* SRAM memory start address */
+#define __SRAM_END__                                       (0x2000FFFF)          /* SRAM memory end address */
+
+//*****************************************************************************
+// Peripheral memory map
+//*****************************************************************************
+#define __MCU_HAS_ADC14__                                                        /* Module is available */
+#define __MCU_HAS_AES256__                                                       /* Module is available */
+#define __MCU_HAS_CAPTIO0__                                                      /* Module is available */
+#define __MCU_HAS_CAPTIO1__                                                      /* Module is available */
+#define __MCU_HAS_COMP_E0__                                                      /* Module is available */
+#define __MCU_HAS_COMP_E1__                                                      /* Module is available */
+#define __MCU_HAS_CRC32__                                                        /* Module is available */
+#define __MCU_HAS_CS__                                                           /* Module is available */
+#define __MCU_HAS_DIO__                                                          /* Module is available */
+#define __MCU_HAS_DMA__                                                          /* Module is available */
+#define __MCU_HAS_EUSCI_A0__                                                     /* Module is available */
+#define __MCU_HAS_EUSCI_A1__                                                     /* Module is available */
+#define __MCU_HAS_EUSCI_A2__                                                     /* Module is available */
+#define __MCU_HAS_EUSCI_A3__                                                     /* Module is available */
+#define __MCU_HAS_EUSCI_B0__                                                     /* Module is available */
+#define __MCU_HAS_EUSCI_B1__                                                     /* Module is available */
+#define __MCU_HAS_EUSCI_B2__                                                     /* Module is available */
+#define __MCU_HAS_EUSCI_B3__                                                     /* Module is available */
+#define __MCU_HAS_FLCTL__                                                        /* Module is available */
+#define __MCU_HAS_FPB__                                                          /* Module is available */
+#define __MCU_HAS_PCM__                                                          /* Module is available */
+#define __MCU_HAS_PMAP__                                                         /* Module is available */
+#define __MCU_HAS_PSS__                                                          /* Module is available */
+#define __MCU_HAS_REF_A__                                                        /* Module is available */
+#define __MCU_HAS_RSTCTL__                                                       /* Module is available */
+#define __MCU_HAS_RTC_C__                                                        /* Module is available */
+#define __MCU_HAS_SYSCTL__                                                       /* Module is available */
+#define __MCU_HAS_TIMER32__                                                      /* Module is available */
+#define __MCU_HAS_TIMER_A0__                                                     /* Module is available */
+#define __MCU_HAS_TIMER_A1__                                                     /* Module is available */
+#define __MCU_HAS_TIMER_A2__                                                     /* Module is available */
+#define __MCU_HAS_TIMER_A3__                                                     /* Module is available */
+#define __MCU_HAS_TLV__                                                          /* Module is available */
+#define __MCU_HAS_WDT_A__                                                        /* Module is available */
+
+#define ADC14_BASE                                         (0x40012000)          /* Base address of module registers */
+#define ADC14_MODULE                                       (0x40012000)          /* Base address of module registers */
+#define AES256_BASE                                        (0x40003C00)          /* Base address of module registers */
+#define AES256_MODULE                                      (0x40003C00)          /* Base address of module registers */
+#define CAPTIO0_BASE                                       (0x40005400)          /* Base address of module registers */
+#define CAPTIO0_MODULE                                     (0x40005400)          /* Base address of module registers */
+#define CAPTIO1_BASE                                       (0x40005800)          /* Base address of module registers */
+#define CAPTIO1_MODULE                                     (0x40005800)          /* Base address of module registers */
+#define COMP_E0_BASE                                       (0x40003400)          /* Base address of module registers */
+#define COMP_E0_MODULE                                     (0x40003400)          /* Base address of module registers */
+#define COMP_E1_BASE                                       (0x40003800)          /* Base address of module registers */
+#define COMP_E1_MODULE                                     (0x40003800)          /* Base address of module registers */
+#define CRC32_BASE                                         (0x40004000)          /* Base address of module registers */
+#define CRC32_MODULE                                       (0x40004000)          /* Base address of module registers */
+#define CS_BASE                                            (0x40010400)          /* Base address of module registers */
+#define CS_MODULE                                          (0x40010400)          /* Base address of module registers */
+#define DIO_BASE                                           (0x40004C00)          /* Base address of module registers */
+#define DIO_MODULE                                         (0x40004C00)          /* Base address of module registers */
+#define DMA_BASE                                           (0x4000E000)          /* Base address of module registers */
+#define DMA_MODULE                                         (0x4000E000)          /* Base address of module registers */
+#define EUSCI_A0_BASE                                      (0x40001000)          /* Base address of module registers */
+#define EUSCI_A0_MODULE                                    (0x40001000)          /* Base address of module registers */
+#define EUSCI_A1_BASE                                      (0x40001400)          /* Base address of module registers */
+#define EUSCI_A1_MODULE                                    (0x40001400)          /* Base address of module registers */
+#define EUSCI_A2_BASE                                      (0x40001800)          /* Base address of module registers */
+#define EUSCI_A2_MODULE                                    (0x40001800)          /* Base address of module registers */
+#define EUSCI_A3_BASE                                      (0x40001C00)          /* Base address of module registers */
+#define EUSCI_A3_MODULE                                    (0x40001C00)          /* Base address of module registers */
+#define EUSCI_B0_BASE                                      (0x40002000)          /* Base address of module registers */
+#define EUSCI_B0_MODULE                                    (0x40002000)          /* Base address of module registers */
+#define EUSCI_B1_BASE                                      (0x40002400)          /* Base address of module registers */
+#define EUSCI_B1_MODULE                                    (0x40002400)          /* Base address of module registers */
+#define EUSCI_B2_BASE                                      (0x40002800)          /* Base address of module registers */
+#define EUSCI_B2_MODULE                                    (0x40002800)          /* Base address of module registers */
+#define EUSCI_B3_BASE                                      (0x40002C00)          /* Base address of module registers */
+#define EUSCI_B3_MODULE                                    (0x40002C00)          /* Base address of module registers */
+#define FLCTL_BASE                                         (0x40011000)          /* Base address of module registers */
+#define FLCTL_MODULE                                       (0x40011000)          /* Base address of module registers */
+#define FPB_BASE                                           (0xE0002000)          /* Base address of module registers */
+#define FPB_MODULE                                         (0xE0002000)          /* Base address of module registers */
+#define PCM_BASE                                           (0x40010000)          /* Base address of module registers */
+#define PCM_MODULE                                         (0x40010000)          /* Base address of module registers */
+#define PMAP_BASE                                          (0x40005000)          /* Base address of module registers */
+#define PMAP_MODULE                                        (0x40005000)          /* Base address of module registers */
+#define PSS_BASE                                           (0x40010800)          /* Base address of module registers */
+#define PSS_MODULE                                         (0x40010800)          /* Base address of module registers */
+#define REF_A_BASE                                         (0x40003000)          /* Base address of module registers */
+#define REF_A_MODULE                                       (0x40003000)          /* Base address of module registers */
+#define RSTCTL_BASE                                        (0xE0042000)          /* Base address of module registers */
+#define RSTCTL_MODULE                                      (0xE0042000)          /* Base address of module registers */
+#define RTC_C_BASE                                         (0x40004400)          /* Base address of module registers */
+#define RTC_C_MODULE                                       (0x40004400)          /* Base address of module registers */
+#define SYSCTL_BASE                                        (0xE0043000)          /* Base address of module registers */
+#define SYSCTL_MODULE                                      (0xE0043000)          /* Base address of module registers */
+#define TIMER32_BASE                                       (0x4000C000)          /* Base address of module registers */
+#define TIMER32_MODULE                                     (0x4000C000)          /* Base address of module registers */
+#define TIMER_A0_BASE                                      (0x40000000)          /* Base address of module registers */
+#define TIMER_A0_MODULE                                    (0x40000000)          /* Base address of module registers */
+#define TIMER_A1_BASE                                      (0x40000400)          /* Base address of module registers */
+#define TIMER_A1_MODULE                                    (0x40000400)          /* Base address of module registers */
+#define TIMER_A2_BASE                                      (0x40000800)          /* Base address of module registers */
+#define TIMER_A2_MODULE                                    (0x40000800)          /* Base address of module registers */
+#define TIMER_A3_BASE                                      (0x40000C00)          /* Base address of module registers */
+#define TIMER_A3_MODULE                                    (0x40000C00)          /* Base address of module registers */
+#define TLV_BASE                                           (0x00201000)          /* Base address of module registers */
+#define TLV_MODULE                                         (0x00201000)          /* Base address of module registers */
+#define WDT_A_BASE                                         (0x40004800)          /* Base address of module registers */
+#define WDT_A_MODULE                                       (0x40004800)          /* Base address of module registers */
+
+#define ADC14                                              ((ADC14_Type *) ADC14_BASE)   
+#define AES256                                             ((AES256_Type *) AES256_BASE) 
+#define CAPTIO0                                            ((CAPTIO0_Type *) CAPTIO0_BASE)
+#define CAPTIO1                                            ((CAPTIO1_Type *) CAPTIO1_BASE)
+#define COMP_E0                                            ((COMP_E0_Type *) COMP_E0_BASE)
+#define COMP_E1                                            ((COMP_E1_Type *) COMP_E1_BASE)
+#define CRC32                                              ((CRC32_Type *) CRC32_BASE)   
+#define CS                                                 ((CS_Type *) CS_BASE)         
+#define DIO                                                ((DIO_Type *) DIO_BASE)       
+#define DMA                                                ((DMA_Type *) DMA_BASE)       
+#define EUSCI_A0                                           ((EUSCI_A0_Type *) EUSCI_A0_BASE)
+#define EUSCI_A1                                           ((EUSCI_A1_Type *) EUSCI_A1_BASE)
+#define EUSCI_A2                                           ((EUSCI_A2_Type *) EUSCI_A2_BASE)
+#define EUSCI_A3                                           ((EUSCI_A3_Type *) EUSCI_A3_BASE)
+#define EUSCI_B0                                           ((EUSCI_B0_Type *) EUSCI_B0_BASE)
+#define EUSCI_B1                                           ((EUSCI_B1_Type *) EUSCI_B1_BASE)
+#define EUSCI_B2                                           ((EUSCI_B2_Type *) EUSCI_B2_BASE)
+#define EUSCI_B3                                           ((EUSCI_B3_Type *) EUSCI_B3_BASE)
+#define FLCTL                                              ((FLCTL_Type *) FLCTL_BASE)   
+#define FPB                                                ((FPB_Type *) FPB_BASE)       
+#define PCM                                                ((PCM_Type *) PCM_BASE)       
+#define PMAP                                               ((PMAP_Type *) PMAP_BASE)     
+#define PSS                                                ((PSS_Type *) PSS_BASE)       
+#define REF_A                                              ((REF_A_Type *) REF_A_BASE)   
+#define RSTCTL                                             ((RSTCTL_Type *) RSTCTL_BASE) 
+#define RTC_C                                              ((RTC_C_Type *) RTC_C_BASE)   
+#define SYSCTL                                             ((SYSCTL_Type *) SYSCTL_BASE) 
+#define TIMER32                                            ((TIMER32_Type *) TIMER32_BASE)
+#define TIMER_A0                                           ((TIMER_A0_Type *) TIMER_A0_BASE)
+#define TIMER_A1                                           ((TIMER_A1_Type *) TIMER_A1_BASE)
+#define TIMER_A2                                           ((TIMER_A2_Type *) TIMER_A2_BASE)
+#define TIMER_A3                                           ((TIMER_A3_Type *) TIMER_A3_BASE)
+#define TLV                                                ((TLV_Type *) TLV_BASE)       
+#define WDT_A                                              ((WDT_A_Type *) WDT_A_BASE)   
+
+
+//*****************************************************************************
+// MSP-format peripheral registers
+//*****************************************************************************
+
+//*****************************************************************************
+// ADC14 Registers
+//*****************************************************************************
+#define ADC14CTL0                                          (HWREG32(0x40012000)) /* Control 0 Register  */
+#define ADC14CTL1                                          (HWREG32(0x40012004)) /* Control 1 Register */
+#define ADC14LO0                                           (HWREG32(0x40012008)) /* Window Comparator Low Threshold 0 Register  */
+#define ADC14HI0                                           (HWREG32(0x4001200C)) /* Window Comparator High Threshold 0 Register  */
+#define ADC14LO1                                           (HWREG32(0x40012010)) /* Window Comparator Low Threshold 1 Register  */
+#define ADC14HI1                                           (HWREG32(0x40012014)) /* Window Comparator High Threshold 1 Register  */
+#define ADC14MCTL0                                         (HWREG32(0x40012018)) /* Conversion Memory Control Register */
+#define ADC14MCTL1                                         (HWREG32(0x4001201C)) /* Conversion Memory Control Register */
+#define ADC14MCTL2                                         (HWREG32(0x40012020)) /* Conversion Memory Control Register */
+#define ADC14MCTL3                                         (HWREG32(0x40012024)) /* Conversion Memory Control Register */
+#define ADC14MCTL4                                         (HWREG32(0x40012028)) /* Conversion Memory Control Register */
+#define ADC14MCTL5                                         (HWREG32(0x4001202C)) /* Conversion Memory Control Register */
+#define ADC14MCTL6                                         (HWREG32(0x40012030)) /* Conversion Memory Control Register */
+#define ADC14MCTL7                                         (HWREG32(0x40012034)) /* Conversion Memory Control Register */
+#define ADC14MCTL8                                         (HWREG32(0x40012038)) /* Conversion Memory Control Register */
+#define ADC14MCTL9                                         (HWREG32(0x4001203C)) /* Conversion Memory Control Register */
+#define ADC14MCTL10                                        (HWREG32(0x40012040)) /* Conversion Memory Control Register */
+#define ADC14MCTL11                                        (HWREG32(0x40012044)) /* Conversion Memory Control Register */
+#define ADC14MCTL12                                        (HWREG32(0x40012048)) /* Conversion Memory Control Register */
+#define ADC14MCTL13                                        (HWREG32(0x4001204C)) /* Conversion Memory Control Register */
+#define ADC14MCTL14                                        (HWREG32(0x40012050)) /* Conversion Memory Control Register */
+#define ADC14MCTL15                                        (HWREG32(0x40012054)) /* Conversion Memory Control Register */
+#define ADC14MCTL16                                        (HWREG32(0x40012058)) /* Conversion Memory Control Register */
+#define ADC14MCTL17                                        (HWREG32(0x4001205C)) /* Conversion Memory Control Register */
+#define ADC14MCTL18                                        (HWREG32(0x40012060)) /* Conversion Memory Control Register */
+#define ADC14MCTL19                                        (HWREG32(0x40012064)) /* Conversion Memory Control Register */
+#define ADC14MCTL20                                        (HWREG32(0x40012068)) /* Conversion Memory Control Register */
+#define ADC14MCTL21                                        (HWREG32(0x4001206C)) /* Conversion Memory Control Register */
+#define ADC14MCTL22                                        (HWREG32(0x40012070)) /* Conversion Memory Control Register */
+#define ADC14MCTL23                                        (HWREG32(0x40012074)) /* Conversion Memory Control Register */
+#define ADC14MCTL24                                        (HWREG32(0x40012078)) /* Conversion Memory Control Register */
+#define ADC14MCTL25                                        (HWREG32(0x4001207C)) /* Conversion Memory Control Register */
+#define ADC14MCTL26                                        (HWREG32(0x40012080)) /* Conversion Memory Control Register */
+#define ADC14MCTL27                                        (HWREG32(0x40012084)) /* Conversion Memory Control Register */
+#define ADC14MCTL28                                        (HWREG32(0x40012088)) /* Conversion Memory Control Register */
+#define ADC14MCTL29                                        (HWREG32(0x4001208C)) /* Conversion Memory Control Register */
+#define ADC14MCTL30                                        (HWREG32(0x40012090)) /* Conversion Memory Control Register */
+#define ADC14MCTL31                                        (HWREG32(0x40012094)) /* Conversion Memory Control Register */
+#define ADC14MEM0                                          (HWREG32(0x40012098)) /* Conversion Memory Register */
+#define ADC14MEM1                                          (HWREG32(0x4001209C)) /* Conversion Memory Register */
+#define ADC14MEM2                                          (HWREG32(0x400120A0)) /* Conversion Memory Register */
+#define ADC14MEM3                                          (HWREG32(0x400120A4)) /* Conversion Memory Register */
+#define ADC14MEM4                                          (HWREG32(0x400120A8)) /* Conversion Memory Register */
+#define ADC14MEM5                                          (HWREG32(0x400120AC)) /* Conversion Memory Register */
+#define ADC14MEM6                                          (HWREG32(0x400120B0)) /* Conversion Memory Register */
+#define ADC14MEM7                                          (HWREG32(0x400120B4)) /* Conversion Memory Register */
+#define ADC14MEM8                                          (HWREG32(0x400120B8)) /* Conversion Memory Register */
+#define ADC14MEM9                                          (HWREG32(0x400120BC)) /* Conversion Memory Register */
+#define ADC14MEM10                                         (HWREG32(0x400120C0)) /* Conversion Memory Register */
+#define ADC14MEM11                                         (HWREG32(0x400120C4)) /* Conversion Memory Register */
+#define ADC14MEM12                                         (HWREG32(0x400120C8)) /* Conversion Memory Register */
+#define ADC14MEM13                                         (HWREG32(0x400120CC)) /* Conversion Memory Register */
+#define ADC14MEM14                                         (HWREG32(0x400120D0)) /* Conversion Memory Register */
+#define ADC14MEM15                                         (HWREG32(0x400120D4)) /* Conversion Memory Register */
+#define ADC14MEM16                                         (HWREG32(0x400120D8)) /* Conversion Memory Register */
+#define ADC14MEM17                                         (HWREG32(0x400120DC)) /* Conversion Memory Register */
+#define ADC14MEM18                                         (HWREG32(0x400120E0)) /* Conversion Memory Register */
+#define ADC14MEM19                                         (HWREG32(0x400120E4)) /* Conversion Memory Register */
+#define ADC14MEM20                                         (HWREG32(0x400120E8)) /* Conversion Memory Register */
+#define ADC14MEM21                                         (HWREG32(0x400120EC)) /* Conversion Memory Register */
+#define ADC14MEM22                                         (HWREG32(0x400120F0)) /* Conversion Memory Register */
+#define ADC14MEM23                                         (HWREG32(0x400120F4)) /* Conversion Memory Register */
+#define ADC14MEM24                                         (HWREG32(0x400120F8)) /* Conversion Memory Register */
+#define ADC14MEM25                                         (HWREG32(0x400120FC)) /* Conversion Memory Register */
+#define ADC14MEM26                                         (HWREG32(0x40012100)) /* Conversion Memory Register */
+#define ADC14MEM27                                         (HWREG32(0x40012104)) /* Conversion Memory Register */
+#define ADC14MEM28                                         (HWREG32(0x40012108)) /* Conversion Memory Register */
+#define ADC14MEM29                                         (HWREG32(0x4001210C)) /* Conversion Memory Register */
+#define ADC14MEM30                                         (HWREG32(0x40012110)) /* Conversion Memory Register */
+#define ADC14MEM31                                         (HWREG32(0x40012114)) /* Conversion Memory Register */
+#define ADC14IER0                                          (HWREG32(0x4001213C)) /* Interrupt Enable 0 Register  */
+#define ADC14IER1                                          (HWREG32(0x40012140)) /* Interrupt Enable 1 Register  */
+#define ADC14IFGR0                                         (HWREG32(0x40012144)) /* Interrupt Flag 0 Register  */
+#define ADC14IFGR1                                         (HWREG32(0x40012148)) /* Interrupt Flag 1 Register  */
+#define ADC14CLRIFGR0                                      (HWREG32(0x4001214C)) /* Clear Interrupt Flag 0 Register  */
+#define ADC14CLRIFGR1                                      (HWREG32(0x40012150)) /* Clear Interrupt Flag 1 Register  */
+#define ADC14IV                                            (HWREG32(0x40012154)) /* Interrupt Vector Register */
+
+/* Register offsets from ADC14_BASE address */
+#define OFS_ADC14CTL0                                      (0x00000000)          /* Control 0 Register  */
+#define OFS_ADC14CTL1                                      (0x00000004)          /* Control 1 Register */
+#define OFS_ADC14LO0                                       (0x00000008)          /* Window Comparator Low Threshold 0 Register  */
+#define OFS_ADC14HI0                                       (0x0000000c)          /* Window Comparator High Threshold 0 Register  */
+#define OFS_ADC14LO1                                       (0x00000010)          /* Window Comparator Low Threshold 1 Register  */
+#define OFS_ADC14HI1                                       (0x00000014)          /* Window Comparator High Threshold 1 Register  */
+#define OFS_ADC14MCTL0                                     (0x00000018)          /* Conversion Memory Control Register */
+#define OFS_ADC14MCTL1                                     (0x0000001C)          /* Conversion Memory Control Register */
+#define OFS_ADC14MCTL2                                     (0x00000020)          /* Conversion Memory Control Register */
+#define OFS_ADC14MCTL3                                     (0x00000024)          /* Conversion Memory Control Register */
+#define OFS_ADC14MCTL4                                     (0x00000028)          /* Conversion Memory Control Register */
+#define OFS_ADC14MCTL5                                     (0x0000002C)          /* Conversion Memory Control Register */
+#define OFS_ADC14MCTL6                                     (0x00000030)          /* Conversion Memory Control Register */
+#define OFS_ADC14MCTL7                                     (0x00000034)          /* Conversion Memory Control Register */
+#define OFS_ADC14MCTL8                                     (0x00000038)          /* Conversion Memory Control Register */
+#define OFS_ADC14MCTL9                                     (0x0000003C)          /* Conversion Memory Control Register */
+#define OFS_ADC14MCTL10                                    (0x00000040)          /* Conversion Memory Control Register */
+#define OFS_ADC14MCTL11                                    (0x00000044)          /* Conversion Memory Control Register */
+#define OFS_ADC14MCTL12                                    (0x00000048)          /* Conversion Memory Control Register */
+#define OFS_ADC14MCTL13                                    (0x0000004C)          /* Conversion Memory Control Register */
+#define OFS_ADC14MCTL14                                    (0x00000050)          /* Conversion Memory Control Register */
+#define OFS_ADC14MCTL15                                    (0x00000054)          /* Conversion Memory Control Register */
+#define OFS_ADC14MCTL16                                    (0x00000058)          /* Conversion Memory Control Register */
+#define OFS_ADC14MCTL17                                    (0x0000005C)          /* Conversion Memory Control Register */
+#define OFS_ADC14MCTL18                                    (0x00000060)          /* Conversion Memory Control Register */
+#define OFS_ADC14MCTL19                                    (0x00000064)          /* Conversion Memory Control Register */
+#define OFS_ADC14MCTL20                                    (0x00000068)          /* Conversion Memory Control Register */
+#define OFS_ADC14MCTL21                                    (0x0000006C)          /* Conversion Memory Control Register */
+#define OFS_ADC14MCTL22                                    (0x00000070)          /* Conversion Memory Control Register */
+#define OFS_ADC14MCTL23                                    (0x00000074)          /* Conversion Memory Control Register */
+#define OFS_ADC14MCTL24                                    (0x00000078)          /* Conversion Memory Control Register */
+#define OFS_ADC14MCTL25                                    (0x0000007C)          /* Conversion Memory Control Register */
+#define OFS_ADC14MCTL26                                    (0x00000080)          /* Conversion Memory Control Register */
+#define OFS_ADC14MCTL27                                    (0x00000084)          /* Conversion Memory Control Register */
+#define OFS_ADC14MCTL28                                    (0x00000088)          /* Conversion Memory Control Register */
+#define OFS_ADC14MCTL29                                    (0x0000008C)          /* Conversion Memory Control Register */
+#define OFS_ADC14MCTL30                                    (0x00000090)          /* Conversion Memory Control Register */
+#define OFS_ADC14MCTL31                                    (0x00000094)          /* Conversion Memory Control Register */
+#define OFS_ADC14MEM0                                      (0x00000098)          /* Conversion Memory Register */
+#define OFS_ADC14MEM1                                      (0x0000009C)          /* Conversion Memory Register */
+#define OFS_ADC14MEM2                                      (0x000000A0)          /* Conversion Memory Register */
+#define OFS_ADC14MEM3                                      (0x000000A4)          /* Conversion Memory Register */
+#define OFS_ADC14MEM4                                      (0x000000A8)          /* Conversion Memory Register */
+#define OFS_ADC14MEM5                                      (0x000000AC)          /* Conversion Memory Register */
+#define OFS_ADC14MEM6                                      (0x000000B0)          /* Conversion Memory Register */
+#define OFS_ADC14MEM7                                      (0x000000B4)          /* Conversion Memory Register */
+#define OFS_ADC14MEM8                                      (0x000000B8)          /* Conversion Memory Register */
+#define OFS_ADC14MEM9                                      (0x000000BC)          /* Conversion Memory Register */
+#define OFS_ADC14MEM10                                     (0x000000C0)          /* Conversion Memory Register */
+#define OFS_ADC14MEM11                                     (0x000000C4)          /* Conversion Memory Register */
+#define OFS_ADC14MEM12                                     (0x000000C8)          /* Conversion Memory Register */
+#define OFS_ADC14MEM13                                     (0x000000CC)          /* Conversion Memory Register */
+#define OFS_ADC14MEM14                                     (0x000000D0)          /* Conversion Memory Register */
+#define OFS_ADC14MEM15                                     (0x000000D4)          /* Conversion Memory Register */
+#define OFS_ADC14MEM16                                     (0x000000D8)          /* Conversion Memory Register */
+#define OFS_ADC14MEM17                                     (0x000000DC)          /* Conversion Memory Register */
+#define OFS_ADC14MEM18                                     (0x000000E0)          /* Conversion Memory Register */
+#define OFS_ADC14MEM19                                     (0x000000E4)          /* Conversion Memory Register */
+#define OFS_ADC14MEM20                                     (0x000000E8)          /* Conversion Memory Register */
+#define OFS_ADC14MEM21                                     (0x000000EC)          /* Conversion Memory Register */
+#define OFS_ADC14MEM22                                     (0x000000F0)          /* Conversion Memory Register */
+#define OFS_ADC14MEM23                                     (0x000000F4)          /* Conversion Memory Register */
+#define OFS_ADC14MEM24                                     (0x000000F8)          /* Conversion Memory Register */
+#define OFS_ADC14MEM25                                     (0x000000FC)          /* Conversion Memory Register */
+#define OFS_ADC14MEM26                                     (0x00000100)          /* Conversion Memory Register */
+#define OFS_ADC14MEM27                                     (0x00000104)          /* Conversion Memory Register */
+#define OFS_ADC14MEM28                                     (0x00000108)          /* Conversion Memory Register */
+#define OFS_ADC14MEM29                                     (0x0000010C)          /* Conversion Memory Register */
+#define OFS_ADC14MEM30                                     (0x00000110)          /* Conversion Memory Register */
+#define OFS_ADC14MEM31                                     (0x00000114)          /* Conversion Memory Register */
+#define OFS_ADC14IER0                                      (0x0000013c)          /* Interrupt Enable 0 Register  */
+#define OFS_ADC14IER1                                      (0x00000140)          /* Interrupt Enable 1 Register  */
+#define OFS_ADC14IFGR0                                     (0x00000144)          /* Interrupt Flag 0 Register  */
+#define OFS_ADC14IFGR1                                     (0x00000148)          /* Interrupt Flag 1 Register  */
+#define OFS_ADC14CLRIFGR0                                  (0x0000014c)          /* Clear Interrupt Flag 0 Register  */
+#define OFS_ADC14CLRIFGR1                                  (0x00000150)          /* Clear Interrupt Flag 1 Register  */
+#define OFS_ADC14IV                                        (0x00000154)          /* Interrupt Vector Register */
+
+
+//*****************************************************************************
+// AES256 Registers
+//*****************************************************************************
+#define AESACTL0                                           (HWREG16(0x40003C00)) /* AES Accelerator Control Register 0 */
+#define AESACTL1                                           (HWREG16(0x40003C02)) /* AES Accelerator Control Register 1 */
+#define AESASTAT                                           (HWREG16(0x40003C04)) /* AES Accelerator Status Register */
+#define AESAKEY                                            (HWREG16(0x40003C06)) /* AES Accelerator Key Register */
+#define AESADIN                                            (HWREG16(0x40003C08)) /* AES Accelerator Data In Register */
+#define AESADOUT                                           (HWREG16(0x40003C0A)) /* AES Accelerator Data Out Register */
+#define AESAXDIN                                           (HWREG16(0x40003C0C)) /* AES Accelerator XORed Data In Register */
+#define AESAXIN                                            (HWREG16(0x40003C0E)) /* AES Accelerator XORed Data In Register */
+
+/* Register offsets from AES256_BASE address */
+#define OFS_AESACTL0                                       (0x0000)              /* AES Accelerator Control Register 0 */
+#define OFS_AESACTL1                                       (0x0002)              /* AES Accelerator Control Register 1 */
+#define OFS_AESASTAT                                       (0x0004)              /* AES Accelerator Status Register */
+#define OFS_AESAKEY                                        (0x0006)              /* AES Accelerator Key Register */
+#define OFS_AESADIN                                        (0x0008)              /* AES Accelerator Data In Register */
+#define OFS_AESADOUT                                       (0x000a)              /* AES Accelerator Data Out Register */
+#define OFS_AESAXDIN                                       (0x000c)              /* AES Accelerator XORed Data In Register */
+#define OFS_AESAXIN                                        (0x000e)              /* AES Accelerator XORed Data In Register */
+
+
+//*****************************************************************************
+// CAPTIO0 Registers
+//*****************************************************************************
+#define CAPTIO0CTL                                         (HWREG16(0x4000540E)) /* Capacitive Touch IO x Control Register */
+
+/* Register offsets from CAPTIO0_BASE address */
+#define OFS_CAPTIO0CTL                                     (0x000e)              /* Capacitive Touch IO x Control Register */
+
+#define CAPTIO0CTL_L                                       (HWREG8_L(CAPTIO0CTL))/* Capacitive Touch IO x Control Register */
+#define CAPTIO0CTL_H                                       (HWREG8_H(CAPTIO0CTL))/* Capacitive Touch IO x Control Register */
+
+//*****************************************************************************
+// CAPTIO1 Registers
+//*****************************************************************************
+#define CAPTIO1CTL                                         (HWREG16(0x4000580E)) /* Capacitive Touch IO x Control Register */
+
+/* Register offsets from CAPTIO1_BASE address */
+#define OFS_CAPTIO1CTL                                     (0x000e)              /* Capacitive Touch IO x Control Register */
+
+#define CAPTIO1CTL_L                                       (HWREG8_L(CAPTIO1CTL))/* Capacitive Touch IO x Control Register */
+#define CAPTIO1CTL_H                                       (HWREG8_H(CAPTIO1CTL))/* Capacitive Touch IO x Control Register */
+
+//*****************************************************************************
+// COMP_E0 Registers
+//*****************************************************************************
+#define CE0CTL0                                            (HWREG16(0x40003400)) /* Comparator Control Register 0 */
+#define CE0CTL1                                            (HWREG16(0x40003402)) /* Comparator Control Register 1 */
+#define CE0CTL2                                            (HWREG16(0x40003404)) /* Comparator Control Register 2 */
+#define CE0CTL3                                            (HWREG16(0x40003406)) /* Comparator Control Register 3 */
+#define CE0INT                                             (HWREG16(0x4000340C)) /* Comparator Interrupt Control Register */
+#define CE0IV                                              (HWREG16(0x4000340E)) /* Comparator Interrupt Vector Word Register */
+
+/* Register offsets from COMP_E0_BASE address */
+#define OFS_CE0CTL0                                        (0x0000)              /* Comparator Control Register 0 */
+#define OFS_CE0CTL1                                        (0x0002)              /* Comparator Control Register 1 */
+#define OFS_CE0CTL2                                        (0x0004)              /* Comparator Control Register 2 */
+#define OFS_CE0CTL3                                        (0x0006)              /* Comparator Control Register 3 */
+#define OFS_CE0INT                                         (0x000c)              /* Comparator Interrupt Control Register */
+#define OFS_CE0IV                                          (0x000e)              /* Comparator Interrupt Vector Word Register */
+
+
+//*****************************************************************************
+// COMP_E1 Registers
+//*****************************************************************************
+#define CE1CTL0                                            (HWREG16(0x40003800)) /* Comparator Control Register 0 */
+#define CE1CTL1                                            (HWREG16(0x40003802)) /* Comparator Control Register 1 */
+#define CE1CTL2                                            (HWREG16(0x40003804)) /* Comparator Control Register 2 */
+#define CE1CTL3                                            (HWREG16(0x40003806)) /* Comparator Control Register 3 */
+#define CE1INT                                             (HWREG16(0x4000380C)) /* Comparator Interrupt Control Register */
+#define CE1IV                                              (HWREG16(0x4000380E)) /* Comparator Interrupt Vector Word Register */
+
+/* Register offsets from COMP_E1_BASE address */
+#define OFS_CE1CTL0                                        (0x0000)              /* Comparator Control Register 0 */
+#define OFS_CE1CTL1                                        (0x0002)              /* Comparator Control Register 1 */
+#define OFS_CE1CTL2                                        (0x0004)              /* Comparator Control Register 2 */
+#define OFS_CE1CTL3                                        (0x0006)              /* Comparator Control Register 3 */
+#define OFS_CE1INT                                         (0x000c)              /* Comparator Interrupt Control Register */
+#define OFS_CE1IV                                          (0x000e)              /* Comparator Interrupt Vector Word Register */
+
+
+//*****************************************************************************
+// COREDEBUG Registers
+//*****************************************************************************
+#define COREDEBUG_DHCSR                                    (HWREG32(0xE000EDF0)) /* Debug Halting Control and Status Register */
+#define COREDEBUG_DCRSR                                    (HWREG32(0xE000EDF4)) /* Deubg Core Register Selector Register */
+#define COREDEBUG_DCRDR                                    (HWREG32(0xE000EDF8)) /* Debug Core Register Data Register */
+#define COREDEBUG_DEMCR                                    (HWREG32(0xE000EDFC)) /* Debug Exception and Monitor Control Register */
+
+/* Register offsets from COREDEBUG_BASE address */
+#define OFS_COREDEBUG_DHCSR                                (0x00000DF0)          /* Debug Halting Control and Status Register */
+#define OFS_COREDEBUG_DCRSR                                (0x00000DF4)          /* Deubg Core Register Selector Register */
+#define OFS_COREDEBUG_DCRDR                                (0x00000DF8)          /* Debug Core Register Data Register */
+#define OFS_COREDEBUG_DEMCR                                (0x00000DFC)          /* Debug Exception and Monitor Control Register */
+
+
+//*****************************************************************************
+// CRC32 Registers
+//*****************************************************************************
+#define CRC32DI                                            (HWREG16(0x40004000)) /* Data Input for CRC32 Signature Computation */
+#define CRC32DIRB                                          (HWREG16(0x40004004)) /* Data In Reverse for CRC32 Computation */
+#define CRC32INIRES_LO                                     (HWREG16(0x40004008)) /* CRC32 Initialization and Result, lower 16 bits */
+#define CRC32INIRES_HI                                     (HWREG16(0x4000400A)) /* CRC32 Initialization and Result, upper 16 bits */
+#define CRC32RESR_LO                                       (HWREG16(0x4000400C)) /* CRC32 Result Reverse, lower 16 bits */
+#define CRC32RESR_HI                                       (HWREG16(0x4000400E)) /* CRC32 Result Reverse, Upper 16 bits */
+#define CRC16DI                                            (HWREG16(0x40004010)) /* Data Input for CRC16 computation */
+#define CRC16DIRB                                          (HWREG16(0x40004014)) /* CRC16 Data In Reverse */
+#define CRC16INIRES                                        (HWREG16(0x40004018)) /* CRC16 Initialization and Result register */
+#define CRC16RESR                                          (HWREG16(0x4000401E)) /* CRC16 Result Reverse */
+
+/* Register offsets from CRC32_BASE address */
+#define OFS_CRC32DI                                        (0x0000)              /* Data Input for CRC32 Signature Computation */
+#define OFS_CRC32DIRB                                      (0x0004)              /* Data In Reverse for CRC32 Computation */
+#define OFS_CRC32INIRES_LO                                 (0x0008)              /* CRC32 Initialization and Result, lower 16 bits */
+#define OFS_CRC32INIRES_HI                                 (0x000a)              /* CRC32 Initialization and Result, upper 16 bits */
+#define OFS_CRC32RESR_LO                                   (0x000c)              /* CRC32 Result Reverse, lower 16 bits */
+#define OFS_CRC32RESR_HI                                   (0x000e)              /* CRC32 Result Reverse, Upper 16 bits */
+#define OFS_CRC16DI                                        (0x0010)              /* Data Input for CRC16 computation */
+#define OFS_CRC16DIRB                                      (0x0014)              /* CRC16 Data In Reverse */
+#define OFS_CRC16INIRES                                    (0x0018)              /* CRC16 Initialization and Result register */
+#define OFS_CRC16RESR                                      (0x001e)              /* CRC16 Result Reverse */
+
+
+//*****************************************************************************
+// CS Registers
+//*****************************************************************************
+#define CSKEY                                              (HWREG32(0x40010400)) /* Key Register */
+#define CSCTL0                                             (HWREG32(0x40010404)) /* Control 0 Register */
+#define CSCTL1                                             (HWREG32(0x40010408)) /* Control 1 Register */
+#define CSCTL2                                             (HWREG32(0x4001040C)) /* Control 2 Register */
+#define CSCTL3                                             (HWREG32(0x40010410)) /* Control 3 Register */
+#define CSCTL4                                             (HWREG32(0x40010414)) /* Control 4 Register */
+#define CSCTL5                                             (HWREG32(0x40010418)) /* Control 5 Register */
+#define CSCTL6                                             (HWREG32(0x4001041C)) /* Control 6 Register */
+#define CSCTL7                                             (HWREG32(0x40010420)) /* Control 7 Register */
+#define CSCLKEN                                            (HWREG32(0x40010430)) /* Clock Enable Register */
+#define CSSTAT                                             (HWREG32(0x40010434)) /* Status Register */
+#define CSIE                                               (HWREG32(0x40010440)) /* Interrupt Enable Register */
+#define CSIFG                                              (HWREG32(0x40010448)) /* Interrupt Flag Register */
+#define CSCLRIFG                                           (HWREG32(0x40010450)) /* Clear Interrupt Flag Register */
+#define CSSETIFG                                           (HWREG32(0x40010458)) /* Set Interrupt Flag Register */
+#define CSDCOERCAL                                         (HWREG32(0x40010460)) /* DCO external resistor cailbration register */
+
+/* Register offsets from CS_BASE address */
+#define OFS_CSKEY                                          (0x00000000)          /* Key Register */
+#define OFS_CSCTL0                                         (0x00000004)          /* Control 0 Register */
+#define OFS_CSCTL1                                         (0x00000008)          /* Control 1 Register */
+#define OFS_CSCTL2                                         (0x0000000c)          /* Control 2 Register */
+#define OFS_CSCTL3                                         (0x00000010)          /* Control 3 Register */
+#define OFS_CSCTL4                                         (0x00000014)          /* Control 4 Register */
+#define OFS_CSCTL5                                         (0x00000018)          /* Control 5 Register */
+#define OFS_CSCTL6                                         (0x0000001c)          /* Control 6 Register */
+#define OFS_CSCTL7                                         (0x00000020)          /* Control 7 Register */
+#define OFS_CSCLKEN                                        (0x00000030)          /* Clock Enable Register */
+#define OFS_CSSTAT                                         (0x00000034)          /* Status Register */
+#define OFS_CSIE                                           (0x00000040)          /* Interrupt Enable Register */
+#define OFS_CSIFG                                          (0x00000048)          /* Interrupt Flag Register */
+#define OFS_CSCLRIFG                                       (0x00000050)          /* Clear Interrupt Flag Register */
+#define OFS_CSSETIFG                                       (0x00000058)          /* Set Interrupt Flag Register */
+#define OFS_CSDCOERCAL                                     (0x00000060)          /* DCO external resistor cailbration register */
+
+
+//*****************************************************************************
+// DIO Registers
+//*****************************************************************************
+#define PAIN                                               (HWREG16(0x40004C00)) /* Port A Input */
+#define PAOUT                                              (HWREG16(0x40004C02)) /* Port A Output */
+#define PADIR                                              (HWREG16(0x40004C04)) /* Port A Direction */
+#define PAREN                                              (HWREG16(0x40004C06)) /* Port A Resistor Enable */
+#define PADS                                               (HWREG16(0x40004C08)) /* Port A Drive Strength */
+#define PASEL0                                             (HWREG16(0x40004C0A)) /* Port A Select 0 */
+#define PASEL1                                             (HWREG16(0x40004C0C)) /* Port A Select 1 */
+#define P1IV                                               (HWREG16(0x40004C0E)) /* Port 1 Interrupt Vector Register */
+#define PASELC                                             (HWREG16(0x40004C16)) /* Port A Complement Select */
+#define PAIES                                              (HWREG16(0x40004C18)) /* Port A Interrupt Edge Select */
+#define PAIE                                               (HWREG16(0x40004C1A)) /* Port A Interrupt Enable */
+#define PAIFG                                              (HWREG16(0x40004C1C)) /* Port A Interrupt Flag */
+#define P2IV                                               (HWREG16(0x40004C1E)) /* Port 2 Interrupt Vector Register */
+#define PBIN                                               (HWREG16(0x40004C20)) /* Port B Input */
+#define PBOUT                                              (HWREG16(0x40004C22)) /* Port B Output */
+#define PBDIR                                              (HWREG16(0x40004C24)) /* Port B Direction */
+#define PBREN                                              (HWREG16(0x40004C26)) /* Port B Resistor Enable */
+#define PBDS                                               (HWREG16(0x40004C28)) /* Port B Drive Strength */
+#define PBSEL0                                             (HWREG16(0x40004C2A)) /* Port B Select 0 */
+#define PBSEL1                                             (HWREG16(0x40004C2C)) /* Port B Select 1 */
+#define P3IV                                               (HWREG16(0x40004C2E)) /* Port 3 Interrupt Vector Register */
+#define PBSELC                                             (HWREG16(0x40004C36)) /* Port B Complement Select */
+#define PBIES                                              (HWREG16(0x40004C38)) /* Port B Interrupt Edge Select */
+#define PBIE                                               (HWREG16(0x40004C3A)) /* Port B Interrupt Enable */
+#define PBIFG                                              (HWREG16(0x40004C3C)) /* Port B Interrupt Flag */
+#define P4IV                                               (HWREG16(0x40004C3E)) /* Port 4 Interrupt Vector Register */
+#define PCIN                                               (HWREG16(0x40004C40)) /* Port C Input */
+#define PCOUT                                              (HWREG16(0x40004C42)) /* Port C Output */
+#define PCDIR                                              (HWREG16(0x40004C44)) /* Port C Direction */
+#define PCREN                                              (HWREG16(0x40004C46)) /* Port C Resistor Enable */
+#define PCDS                                               (HWREG16(0x40004C48)) /* Port C Drive Strength */
+#define PCSEL0                                             (HWREG16(0x40004C4A)) /* Port C Select 0 */
+#define PCSEL1                                             (HWREG16(0x40004C4C)) /* Port C Select 1 */
+#define P5IV                                               (HWREG16(0x40004C4E)) /* Port 5 Interrupt Vector Register */
+#define PCSELC                                             (HWREG16(0x40004C56)) /* Port C Complement Select */
+#define PCIES                                              (HWREG16(0x40004C58)) /* Port C Interrupt Edge Select */
+#define PCIE                                               (HWREG16(0x40004C5A)) /* Port C Interrupt Enable */
+#define PCIFG                                              (HWREG16(0x40004C5C)) /* Port C Interrupt Flag */
+#define P6IV                                               (HWREG16(0x40004C5E)) /* Port 6 Interrupt Vector Register */
+#define PDIN                                               (HWREG16(0x40004C60)) /* Port D Input */
+#define PDOUT                                              (HWREG16(0x40004C62)) /* Port D Output */
+#define PDDIR                                              (HWREG16(0x40004C64)) /* Port D Direction */
+#define PDREN                                              (HWREG16(0x40004C66)) /* Port D Resistor Enable */
+#define PDDS                                               (HWREG16(0x40004C68)) /* Port D Drive Strength */
+#define PDSEL0                                             (HWREG16(0x40004C6A)) /* Port D Select 0 */
+#define PDSEL1                                             (HWREG16(0x40004C6C)) /* Port D Select 1 */
+#define P7IV                                               (HWREG16(0x40004C6E)) /* Port 7 Interrupt Vector Register */
+#define PDSELC                                             (HWREG16(0x40004C76)) /* Port D Complement Select */
+#define PDIES                                              (HWREG16(0x40004C78)) /* Port D Interrupt Edge Select */
+#define PDIE                                               (HWREG16(0x40004C7A)) /* Port D Interrupt Enable */
+#define PDIFG                                              (HWREG16(0x40004C7C)) /* Port D Interrupt Flag */
+#define P8IV                                               (HWREG16(0x40004C7E)) /* Port 8 Interrupt Vector Register */
+#define PEIN                                               (HWREG16(0x40004C80)) /* Port E Input */
+#define PEOUT                                              (HWREG16(0x40004C82)) /* Port E Output */
+#define PEDIR                                              (HWREG16(0x40004C84)) /* Port E Direction */
+#define PEREN                                              (HWREG16(0x40004C86)) /* Port E Resistor Enable */
+#define PEDS                                               (HWREG16(0x40004C88)) /* Port E Drive Strength */
+#define PESEL0                                             (HWREG16(0x40004C8A)) /* Port E Select 0 */
+#define PESEL1                                             (HWREG16(0x40004C8C)) /* Port E Select 1 */
+#define P9IV                                               (HWREG16(0x40004C8E)) /* Port 9 Interrupt Vector Register */
+#define PESELC                                             (HWREG16(0x40004C96)) /* Port E Complement Select */
+#define PEIES                                              (HWREG16(0x40004C98)) /* Port E Interrupt Edge Select */
+#define PEIE                                               (HWREG16(0x40004C9A)) /* Port E Interrupt Enable */
+#define PEIFG                                              (HWREG16(0x40004C9C)) /* Port E Interrupt Flag */
+#define P10IV                                              (HWREG16(0x40004C9E)) /* Port 10 Interrupt Vector Register */
+#define PJIN                                               (HWREG16(0x40004D20)) /* Port J Input */
+#define PJOUT                                              (HWREG16(0x40004D22)) /* Port J Output */
+#define PJDIR                                              (HWREG16(0x40004D24)) /* Port J Direction */
+#define PJREN                                              (HWREG16(0x40004D26)) /* Port J Resistor Enable */
+#define PJDS                                               (HWREG16(0x40004D28)) /* Port J Drive Strength */
+#define PJSEL0                                             (HWREG16(0x40004D2A)) /* Port J Select 0 */
+#define PJSEL1                                             (HWREG16(0x40004D2C)) /* Port J Select 1 */
+#define PJSELC                                             (HWREG16(0x40004D36)) /* Port J Complement Select */
+#define P1IN                                               (HWREG8(0x40004C00))  /* Port 1 Input */
+#define P2IN                                               (HWREG8(0x40004C01))  /* Port 2 Input */
+#define P2OUT                                              (HWREG8(0x40004C03))  /* Port 2 Output */
+#define P1OUT                                              (HWREG8(0x40004C02))  /* Port 1 Output */
+#define P1DIR                                              (HWREG8(0x40004C04))  /* Port 1 Direction */
+#define P2DIR                                              (HWREG8(0x40004C05))  /* Port 2 Direction */
+#define P1REN                                              (HWREG8(0x40004C06))  /* Port 1 Resistor Enable */
+#define P2REN                                              (HWREG8(0x40004C07))  /* Port 2 Resistor Enable */
+#define P1DS                                               (HWREG8(0x40004C08))  /* Port 1 Drive Strength */
+#define P2DS                                               (HWREG8(0x40004C09))  /* Port 2 Drive Strength */
+#define P1SEL0                                             (HWREG8(0x40004C0A))  /* Port 1 Select 0 */
+#define P2SEL0                                             (HWREG8(0x40004C0B))  /* Port 2 Select 0 */
+#define P1SEL1                                             (HWREG8(0x40004C0C))  /* Port 1 Select 1 */
+#define P2SEL1                                             (HWREG8(0x40004C0D))  /* Port 2 Select 1 */
+#define P1SELC                                             (HWREG8(0x40004C16))  /* Port 1 Complement Select */
+#define P2SELC                                             (HWREG8(0x40004C17))  /* Port 2 Complement Select */
+#define P1IES                                              (HWREG8(0x40004C18))  /* Port 1 Interrupt Edge Select */
+#define P2IES                                              (HWREG8(0x40004C19))  /* Port 2 Interrupt Edge Select */
+#define P1IE                                               (HWREG8(0x40004C1A))  /* Port 1 Interrupt Enable */
+#define P2IE                                               (HWREG8(0x40004C1B))  /* Port 2 Interrupt Enable */
+#define P1IFG                                              (HWREG8(0x40004C1C))  /* Port 1 Interrupt Flag */
+#define P2IFG                                              (HWREG8(0x40004C1D))  /* Port 2 Interrupt Flag */
+#define P3IN                                               (HWREG8(0x40004C20))  /* Port 3 Input */
+#define P4IN                                               (HWREG8(0x40004C21))  /* Port 4 Input */
+#define P3OUT                                              (HWREG8(0x40004C22))  /* Port 3 Output */
+#define P4OUT                                              (HWREG8(0x40004C23))  /* Port 4 Output */
+#define P3DIR                                              (HWREG8(0x40004C24))  /* Port 3 Direction */
+#define P4DIR                                              (HWREG8(0x40004C25))  /* Port 4 Direction */
+#define P3REN                                              (HWREG8(0x40004C26))  /* Port 3 Resistor Enable */
+#define P4REN                                              (HWREG8(0x40004C27))  /* Port 4 Resistor Enable */
+#define P3DS                                               (HWREG8(0x40004C28))  /* Port 3 Drive Strength */
+#define P4DS                                               (HWREG8(0x40004C29))  /* Port 4 Drive Strength */
+#define P4SEL0                                             (HWREG8(0x40004C2B))  /* Port 4 Select 0 */
+#define P3SEL0                                             (HWREG8(0x40004C2A))  /* Port 3 Select 0 */
+#define P3SEL1                                             (HWREG8(0x40004C2C))  /* Port 3 Select 1 */
+#define P4SEL1                                             (HWREG8(0x40004C2D))  /* Port 4 Select 1 */
+#define P3SELC                                             (HWREG8(0x40004C36))  /* Port 3 Complement Select */
+#define P4SELC                                             (HWREG8(0x40004C37))  /* Port 4 Complement Select */
+#define P3IES                                              (HWREG8(0x40004C38))  /* Port 3 Interrupt Edge Select */
+#define P4IES                                              (HWREG8(0x40004C39))  /* Port 4 Interrupt Edge Select */
+#define P3IE                                               (HWREG8(0x40004C3A))  /* Port 3 Interrupt Enable */
+#define P4IE                                               (HWREG8(0x40004C3B))  /* Port 4 Interrupt Enable */
+#define P3IFG                                              (HWREG8(0x40004C3C))  /* Port 3 Interrupt Flag */
+#define P4IFG                                              (HWREG8(0x40004C3D))  /* Port 4 Interrupt Flag */
+#define P5IN                                               (HWREG8(0x40004C40))  /* Port 5 Input */
+#define P6IN                                               (HWREG8(0x40004C41))  /* Port 6 Input */
+#define P5OUT                                              (HWREG8(0x40004C42))  /* Port 5 Output */
+#define P6OUT                                              (HWREG8(0x40004C43))  /* Port 6 Output */
+#define P5DIR                                              (HWREG8(0x40004C44))  /* Port 5 Direction */
+#define P6DIR                                              (HWREG8(0x40004C45))  /* Port 6 Direction */
+#define P5REN                                              (HWREG8(0x40004C46))  /* Port 5 Resistor Enable */
+#define P6REN                                              (HWREG8(0x40004C47))  /* Port 6 Resistor Enable */
+#define P5DS                                               (HWREG8(0x40004C48))  /* Port 5 Drive Strength */
+#define P6DS                                               (HWREG8(0x40004C49))  /* Port 6 Drive Strength */
+#define P5SEL0                                             (HWREG8(0x40004C4A))  /* Port 5 Select 0 */
+#define P6SEL0                                             (HWREG8(0x40004C4B))  /* Port 6 Select 0 */
+#define P5SEL1                                             (HWREG8(0x40004C4C))  /* Port 5 Select 1 */
+#define P6SEL1                                             (HWREG8(0x40004C4D))  /* Port 6 Select 1 */
+#define P5SELC                                             (HWREG8(0x40004C56))  /* Port 5 Complement Select */
+#define P6SELC                                             (HWREG8(0x40004C57))  /* Port 6 Complement Select */
+#define P5IES                                              (HWREG8(0x40004C58))  /* Port 5 Interrupt Edge Select */
+#define P6IES                                              (HWREG8(0x40004C59))  /* Port 6 Interrupt Edge Select */
+#define P5IE                                               (HWREG8(0x40004C5A))  /* Port 5 Interrupt Enable */
+#define P6IE                                               (HWREG8(0x40004C5B))  /* Port 6 Interrupt Enable */
+#define P5IFG                                              (HWREG8(0x40004C5C))  /* Port 5 Interrupt Flag */
+#define P6IFG                                              (HWREG8(0x40004C5D))  /* Port 6 Interrupt Flag */
+#define P7IN                                               (HWREG8(0x40004C60))  /* Port 7 Input */
+#define P8IN                                               (HWREG8(0x40004C61))  /* Port 8 Input */
+#define P7OUT                                              (HWREG8(0x40004C62))  /* Port 7 Output */
+#define P8OUT                                              (HWREG8(0x40004C63))  /* Port 8 Output */
+#define P7DIR                                              (HWREG8(0x40004C64))  /* Port 7 Direction */
+#define P8DIR                                              (HWREG8(0x40004C65))  /* Port 8 Direction */
+#define P7REN                                              (HWREG8(0x40004C66))  /* Port 7 Resistor Enable */
+#define P8REN                                              (HWREG8(0x40004C67))  /* Port 8 Resistor Enable */
+#define P7DS                                               (HWREG8(0x40004C68))  /* Port 7 Drive Strength */
+#define P8DS                                               (HWREG8(0x40004C69))  /* Port 8 Drive Strength */
+#define P7SEL0                                             (HWREG8(0x40004C6A))  /* Port 7 Select 0 */
+#define P8SEL0                                             (HWREG8(0x40004C6B))  /* Port 8 Select 0 */
+#define P7SEL1                                             (HWREG8(0x40004C6C))  /* Port 7 Select 1 */
+#define P8SEL1                                             (HWREG8(0x40004C6D))  /* Port 8 Select 1 */
+#define P7SELC                                             (HWREG8(0x40004C76))  /* Port 7 Complement Select */
+#define P8SELC                                             (HWREG8(0x40004C77))  /* Port 8 Complement Select */
+#define P7IES                                              (HWREG8(0x40004C78))  /* Port 7 Interrupt Edge Select */
+#define P8IES                                              (HWREG8(0x40004C79))  /* Port 8 Interrupt Edge Select */
+#define P7IE                                               (HWREG8(0x40004C7A))  /* Port 7 Interrupt Enable */
+#define P8IE                                               (HWREG8(0x40004C7B))  /* Port 8 Interrupt Enable */
+#define P7IFG                                              (HWREG8(0x40004C7C))  /* Port 7 Interrupt Flag */
+#define P8IFG                                              (HWREG8(0x40004C7D))  /* Port 8 Interrupt Flag */
+#define P9IN                                               (HWREG8(0x40004C80))  /* Port 9 Input */
+#define P10IN                                              (HWREG8(0x40004C81))  /* Port 10 Input */
+#define P9OUT                                              (HWREG8(0x40004C82))  /* Port 9 Output */
+#define P10OUT                                             (HWREG8(0x40004C83))  /* Port 10 Output */
+#define P9DIR                                              (HWREG8(0x40004C84))  /* Port 9 Direction */
+#define P10DIR                                             (HWREG8(0x40004C85))  /* Port 10 Direction */
+#define P9REN                                              (HWREG8(0x40004C86))  /* Port 9 Resistor Enable */
+#define P10REN                                             (HWREG8(0x40004C87))  /* Port 10 Resistor Enable */
+#define P9DS                                               (HWREG8(0x40004C88))  /* Port 9 Drive Strength */
+#define P10DS                                              (HWREG8(0x40004C89))  /* Port 10 Drive Strength */
+#define P9SEL0                                             (HWREG8(0x40004C8A))  /* Port 9 Select 0 */
+#define P10SEL0                                            (HWREG8(0x40004C8B))  /* Port 10 Select 0 */
+#define P9SEL1                                             (HWREG8(0x40004C8C))  /* Port 9 Select 1 */
+#define P10SEL1                                            (HWREG8(0x40004C8D))  /* Port 10 Select 1 */
+#define P9SELC                                             (HWREG8(0x40004C96))  /* Port 9 Complement Select */
+#define P10SELC                                            (HWREG8(0x40004C97))  /* Port 10 Complement Select */
+#define P9IES                                              (HWREG8(0x40004C98))  /* Port 9 Interrupt Edge Select */
+#define P10IES                                             (HWREG8(0x40004C99))  /* Port 10 Interrupt Edge Select */
+#define P9IE                                               (HWREG8(0x40004C9A))  /* Port 9 Interrupt Enable */
+#define P10IE                                              (HWREG8(0x40004C9B))  /* Port 10 Interrupt Enable */
+#define P9IFG                                              (HWREG8(0x40004C9C))  /* Port 9 Interrupt Flag */
+#define P10IFG                                             (HWREG8(0x40004C9D))  /* Port 10 Interrupt Flag */
+
+/* Register offsets from DIO_BASE address */
+#define OFS_PAIN                                           (0x0000)              /* Port A Input */
+#define OFS_PAOUT                                          (0x0002)              /* Port A Output */
+#define OFS_PADIR                                          (0x0004)              /* Port A Direction */
+#define OFS_PAREN                                          (0x0006)              /* Port A Resistor Enable */
+#define OFS_PADS                                           (0x0008)              /* Port A Drive Strength */
+#define OFS_PASEL0                                         (0x000a)              /* Port A Select 0 */
+#define OFS_PASEL1                                         (0x000c)              /* Port A Select 1 */
+#define OFS_P1IV                                           (0x000e)              /* Port 1 Interrupt Vector Register */
+#define OFS_PASELC                                         (0x0016)              /* Port A Complement Select */
+#define OFS_PAIES                                          (0x0018)              /* Port A Interrupt Edge Select */
+#define OFS_PAIE                                           (0x001a)              /* Port A Interrupt Enable */
+#define OFS_PAIFG                                          (0x001c)              /* Port A Interrupt Flag */
+#define OFS_P2IV                                           (0x001e)              /* Port 2 Interrupt Vector Register */
+#define OFS_PBIN                                           (0x0020)              /* Port B Input */
+#define OFS_PBOUT                                          (0x0022)              /* Port B Output */
+#define OFS_PBDIR                                          (0x0024)              /* Port B Direction */
+#define OFS_PBREN                                          (0x0026)              /* Port B Resistor Enable */
+#define OFS_PBDS                                           (0x0028)              /* Port B Drive Strength */
+#define OFS_PBSEL0                                         (0x002a)              /* Port B Select 0 */
+#define OFS_PBSEL1                                         (0x002c)              /* Port B Select 1 */
+#define OFS_P3IV                                           (0x002e)              /* Port 3 Interrupt Vector Register */
+#define OFS_PBSELC                                         (0x0036)              /* Port B Complement Select */
+#define OFS_PBIES                                          (0x0038)              /* Port B Interrupt Edge Select */
+#define OFS_PBIE                                           (0x003a)              /* Port B Interrupt Enable */
+#define OFS_PBIFG                                          (0x003c)              /* Port B Interrupt Flag */
+#define OFS_P4IV                                           (0x003e)              /* Port 4 Interrupt Vector Register */
+#define OFS_PCIN                                           (0x0040)              /* Port C Input */
+#define OFS_PCOUT                                          (0x0042)              /* Port C Output */
+#define OFS_PCDIR                                          (0x0044)              /* Port C Direction */
+#define OFS_PCREN                                          (0x0046)              /* Port C Resistor Enable */
+#define OFS_PCDS                                           (0x0048)              /* Port C Drive Strength */
+#define OFS_PCSEL0                                         (0x004a)              /* Port C Select 0 */
+#define OFS_PCSEL1                                         (0x004c)              /* Port C Select 1 */
+#define OFS_P5IV                                           (0x004e)              /* Port 5 Interrupt Vector Register */
+#define OFS_PCSELC                                         (0x0056)              /* Port C Complement Select */
+#define OFS_PCIES                                          (0x0058)              /* Port C Interrupt Edge Select */
+#define OFS_PCIE                                           (0x005a)              /* Port C Interrupt Enable */
+#define OFS_PCIFG                                          (0x005c)              /* Port C Interrupt Flag */
+#define OFS_P6IV                                           (0x005e)              /* Port 6 Interrupt Vector Register */
+#define OFS_PDIN                                           (0x0060)              /* Port D Input */
+#define OFS_PDOUT                                          (0x0062)              /* Port D Output */
+#define OFS_PDDIR                                          (0x0064)              /* Port D Direction */
+#define OFS_PDREN                                          (0x0066)              /* Port D Resistor Enable */
+#define OFS_PDDS                                           (0x0068)              /* Port D Drive Strength */
+#define OFS_PDSEL0                                         (0x006a)              /* Port D Select 0 */
+#define OFS_PDSEL1                                         (0x006c)              /* Port D Select 1 */
+#define OFS_P7IV                                           (0x006e)              /* Port 7 Interrupt Vector Register */
+#define OFS_PDSELC                                         (0x0076)              /* Port D Complement Select */
+#define OFS_PDIES                                          (0x0078)              /* Port D Interrupt Edge Select */
+#define OFS_PDIE                                           (0x007a)              /* Port D Interrupt Enable */
+#define OFS_PDIFG                                          (0x007c)              /* Port D Interrupt Flag */
+#define OFS_P8IV                                           (0x007e)              /* Port 8 Interrupt Vector Register */
+#define OFS_PEIN                                           (0x0080)              /* Port E Input */
+#define OFS_PEOUT                                          (0x0082)              /* Port E Output */
+#define OFS_PEDIR                                          (0x0084)              /* Port E Direction */
+#define OFS_PEREN                                          (0x0086)              /* Port E Resistor Enable */
+#define OFS_PEDS                                           (0x0088)              /* Port E Drive Strength */
+#define OFS_PESEL0                                         (0x008a)              /* Port E Select 0 */
+#define OFS_PESEL1                                         (0x008c)              /* Port E Select 1 */
+#define OFS_P9IV                                           (0x008e)              /* Port 9 Interrupt Vector Register */
+#define OFS_PESELC                                         (0x0096)              /* Port E Complement Select */
+#define OFS_PEIES                                          (0x0098)              /* Port E Interrupt Edge Select */
+#define OFS_PEIE                                           (0x009a)              /* Port E Interrupt Enable */
+#define OFS_PEIFG                                          (0x009c)              /* Port E Interrupt Flag */
+#define OFS_P10IV                                          (0x009e)              /* Port 10 Interrupt Vector Register */
+#define OFS_PJIN                                           (0x0120)              /* Port J Input */
+#define OFS_PJOUT                                          (0x0122)              /* Port J Output */
+#define OFS_PJDIR                                          (0x0124)              /* Port J Direction */
+#define OFS_PJREN                                          (0x0126)              /* Port J Resistor Enable */
+#define OFS_PJDS                                           (0x0128)              /* Port J Drive Strength */
+#define OFS_PJSEL0                                         (0x012a)              /* Port J Select 0 */
+#define OFS_PJSEL1                                         (0x012c)              /* Port J Select 1 */
+#define OFS_PJSELC                                         (0x0136)              /* Port J Complement Select */
+#define OFS_P1IN                                           (0x0000)              /* Port 1 Input */
+#define OFS_P2IN                                           (0x0000)              /* Port 2 Input */
+#define OFS_P2OUT                                          (0x0002)              /* Port 2 Output */
+#define OFS_P1OUT                                          (0x0002)              /* Port 1 Output */
+#define OFS_P1DIR                                          (0x0004)              /* Port 1 Direction */
+#define OFS_P2DIR                                          (0x0004)              /* Port 2 Direction */
+#define OFS_P1REN                                          (0x0006)              /* Port 1 Resistor Enable */
+#define OFS_P2REN                                          (0x0006)              /* Port 2 Resistor Enable */
+#define OFS_P1DS                                           (0x0008)              /* Port 1 Drive Strength */
+#define OFS_P2DS                                           (0x0008)              /* Port 2 Drive Strength */
+#define OFS_P1SEL0                                         (0x000a)              /* Port 1 Select 0 */
+#define OFS_P2SEL0                                         (0x000a)              /* Port 2 Select 0 */
+#define OFS_P1SEL1                                         (0x000c)              /* Port 1 Select 1 */
+#define OFS_P2SEL1                                         (0x000c)              /* Port 2 Select 1 */
+#define OFS_P1SELC                                         (0x0016)              /* Port 1 Complement Select */
+#define OFS_P2SELC                                         (0x0016)              /* Port 2 Complement Select */
+#define OFS_P1IES                                          (0x0018)              /* Port 1 Interrupt Edge Select */
+#define OFS_P2IES                                          (0x0018)              /* Port 2 Interrupt Edge Select */
+#define OFS_P1IE                                           (0x001a)              /* Port 1 Interrupt Enable */
+#define OFS_P2IE                                           (0x001a)              /* Port 2 Interrupt Enable */
+#define OFS_P1IFG                                          (0x001c)              /* Port 1 Interrupt Flag */
+#define OFS_P2IFG                                          (0x001c)              /* Port 2 Interrupt Flag */
+#define OFS_P3IN                                           (0x0020)              /* Port 3 Input */
+#define OFS_P4IN                                           (0x0020)              /* Port 4 Input */
+#define OFS_P3OUT                                          (0x0022)              /* Port 3 Output */
+#define OFS_P4OUT                                          (0x0022)              /* Port 4 Output */
+#define OFS_P3DIR                                          (0x0024)              /* Port 3 Direction */
+#define OFS_P4DIR                                          (0x0024)              /* Port 4 Direction */
+#define OFS_P3REN                                          (0x0026)              /* Port 3 Resistor Enable */
+#define OFS_P4REN                                          (0x0026)              /* Port 4 Resistor Enable */
+#define OFS_P3DS                                           (0x0028)              /* Port 3 Drive Strength */
+#define OFS_P4DS                                           (0x0028)              /* Port 4 Drive Strength */
+#define OFS_P4SEL0                                         (0x002a)              /* Port 4 Select 0 */
+#define OFS_P3SEL0                                         (0x002a)              /* Port 3 Select 0 */
+#define OFS_P3SEL1                                         (0x002c)              /* Port 3 Select 1 */
+#define OFS_P4SEL1                                         (0x002c)              /* Port 4 Select 1 */
+#define OFS_P3SELC                                         (0x0036)              /* Port 3 Complement Select */
+#define OFS_P4SELC                                         (0x0036)              /* Port 4 Complement Select */
+#define OFS_P3IES                                          (0x0038)              /* Port 3 Interrupt Edge Select */
+#define OFS_P4IES                                          (0x0038)              /* Port 4 Interrupt Edge Select */
+#define OFS_P3IE                                           (0x003a)              /* Port 3 Interrupt Enable */
+#define OFS_P4IE                                           (0x003a)              /* Port 4 Interrupt Enable */
+#define OFS_P3IFG                                          (0x003c)              /* Port 3 Interrupt Flag */
+#define OFS_P4IFG                                          (0x003c)              /* Port 4 Interrupt Flag */
+#define OFS_P5IN                                           (0x0040)              /* Port 5 Input */
+#define OFS_P6IN                                           (0x0040)              /* Port 6 Input */
+#define OFS_P5OUT                                          (0x0042)              /* Port 5 Output */
+#define OFS_P6OUT                                          (0x0042)              /* Port 6 Output */
+#define OFS_P5DIR                                          (0x0044)              /* Port 5 Direction */
+#define OFS_P6DIR                                          (0x0044)              /* Port 6 Direction */
+#define OFS_P5REN                                          (0x0046)              /* Port 5 Resistor Enable */
+#define OFS_P6REN                                          (0x0046)              /* Port 6 Resistor Enable */
+#define OFS_P5DS                                           (0x0048)              /* Port 5 Drive Strength */
+#define OFS_P6DS                                           (0x0048)              /* Port 6 Drive Strength */
+#define OFS_P5SEL0                                         (0x004a)              /* Port 5 Select 0 */
+#define OFS_P6SEL0                                         (0x004a)              /* Port 6 Select 0 */
+#define OFS_P5SEL1                                         (0x004c)              /* Port 5 Select 1 */
+#define OFS_P6SEL1                                         (0x004c)              /* Port 6 Select 1 */
+#define OFS_P5SELC                                         (0x0056)              /* Port 5 Complement Select */
+#define OFS_P6SELC                                         (0x0056)              /* Port 6 Complement Select */
+#define OFS_P5IES                                          (0x0058)              /* Port 5 Interrupt Edge Select */
+#define OFS_P6IES                                          (0x0058)              /* Port 6 Interrupt Edge Select */
+#define OFS_P5IE                                           (0x005a)              /* Port 5 Interrupt Enable */
+#define OFS_P6IE                                           (0x005a)              /* Port 6 Interrupt Enable */
+#define OFS_P5IFG                                          (0x005c)              /* Port 5 Interrupt Flag */
+#define OFS_P6IFG                                          (0x005c)              /* Port 6 Interrupt Flag */
+#define OFS_P7IN                                           (0x0060)              /* Port 7 Input */
+#define OFS_P8IN                                           (0x0060)              /* Port 8 Input */
+#define OFS_P7OUT                                          (0x0062)              /* Port 7 Output */
+#define OFS_P8OUT                                          (0x0062)              /* Port 8 Output */
+#define OFS_P7DIR                                          (0x0064)              /* Port 7 Direction */
+#define OFS_P8DIR                                          (0x0064)              /* Port 8 Direction */
+#define OFS_P7REN                                          (0x0066)              /* Port 7 Resistor Enable */
+#define OFS_P8REN                                          (0x0066)              /* Port 8 Resistor Enable */
+#define OFS_P7DS                                           (0x0068)              /* Port 7 Drive Strength */
+#define OFS_P8DS                                           (0x0068)              /* Port 8 Drive Strength */
+#define OFS_P7SEL0                                         (0x006a)              /* Port 7 Select 0 */
+#define OFS_P8SEL0                                         (0x006a)              /* Port 8 Select 0 */
+#define OFS_P7SEL1                                         (0x006c)              /* Port 7 Select 1 */
+#define OFS_P8SEL1                                         (0x006c)              /* Port 8 Select 1 */
+#define OFS_P7SELC                                         (0x0076)              /* Port 7 Complement Select */
+#define OFS_P8SELC                                         (0x0076)              /* Port 8 Complement Select */
+#define OFS_P7IES                                          (0x0078)              /* Port 7 Interrupt Edge Select */
+#define OFS_P8IES                                          (0x0078)              /* Port 8 Interrupt Edge Select */
+#define OFS_P7IE                                           (0x007a)              /* Port 7 Interrupt Enable */
+#define OFS_P8IE                                           (0x007a)              /* Port 8 Interrupt Enable */
+#define OFS_P7IFG                                          (0x007c)              /* Port 7 Interrupt Flag */
+#define OFS_P8IFG                                          (0x007c)              /* Port 8 Interrupt Flag */
+#define OFS_P9IN                                           (0x0080)              /* Port 9 Input */
+#define OFS_P10IN                                          (0x0080)              /* Port 10 Input */
+#define OFS_P9OUT                                          (0x0082)              /* Port 9 Output */
+#define OFS_P10OUT                                         (0x0082)              /* Port 10 Output */
+#define OFS_P9DIR                                          (0x0084)              /* Port 9 Direction */
+#define OFS_P10DIR                                         (0x0084)              /* Port 10 Direction */
+#define OFS_P9REN                                          (0x0086)              /* Port 9 Resistor Enable */
+#define OFS_P10REN                                         (0x0086)              /* Port 10 Resistor Enable */
+#define OFS_P9DS                                           (0x0088)              /* Port 9 Drive Strength */
+#define OFS_P10DS                                          (0x0088)              /* Port 10 Drive Strength */
+#define OFS_P9SEL0                                         (0x008a)              /* Port 9 Select 0 */
+#define OFS_P10SEL0                                        (0x008a)              /* Port 10 Select 0 */
+#define OFS_P9SEL1                                         (0x008c)              /* Port 9 Select 1 */
+#define OFS_P10SEL1                                        (0x008c)              /* Port 10 Select 1 */
+#define OFS_P9SELC                                         (0x0096)              /* Port 9 Complement Select */
+#define OFS_P10SELC                                        (0x0096)              /* Port 10 Complement Select */
+#define OFS_P9IES                                          (0x0098)              /* Port 9 Interrupt Edge Select */
+#define OFS_P10IES                                         (0x0098)              /* Port 10 Interrupt Edge Select */
+#define OFS_P9IE                                           (0x009a)              /* Port 9 Interrupt Enable */
+#define OFS_P10IE                                          (0x009a)              /* Port 10 Interrupt Enable */
+#define OFS_P9IFG                                          (0x009c)              /* Port 9 Interrupt Flag */
+#define OFS_P10IFG                                         (0x009c)              /* Port 10 Interrupt Flag */
+
+
+//*****************************************************************************
+// DMA Registers
+//*****************************************************************************
+#define DMA_DEVICE_CFG                                     (HWREG32(0x4000E000)) /* Device Configuration Status */
+#define DMA_SW_CHTRIG                                      (HWREG32(0x4000E004)) /* Software Channel Trigger Register */
+#define DMA_CH0_SRCCFG                                     (HWREG32(0x4000E010)) /* Channel n Source Configuration Register */
+#define DMA_CH1_SRCCFG                                     (HWREG32(0x4000E014)) /* Channel n Source Configuration Register */
+#define DMA_CH2_SRCCFG                                     (HWREG32(0x4000E018)) /* Channel n Source Configuration Register */
+#define DMA_CH3_SRCCFG                                     (HWREG32(0x4000E01C)) /* Channel n Source Configuration Register */
+#define DMA_CH4_SRCCFG                                     (HWREG32(0x4000E020)) /* Channel n Source Configuration Register */
+#define DMA_CH5_SRCCFG                                     (HWREG32(0x4000E024)) /* Channel n Source Configuration Register */
+#define DMA_CH6_SRCCFG                                     (HWREG32(0x4000E028)) /* Channel n Source Configuration Register */
+#define DMA_CH7_SRCCFG                                     (HWREG32(0x4000E02C)) /* Channel n Source Configuration Register */
+#define DMA_CH8_SRCCFG                                     (HWREG32(0x4000E030)) /* Channel n Source Configuration Register */
+#define DMA_CH9_SRCCFG                                     (HWREG32(0x4000E034)) /* Channel n Source Configuration Register */
+#define DMA_CH10_SRCCFG                                    (HWREG32(0x4000E038)) /* Channel n Source Configuration Register */
+#define DMA_CH11_SRCCFG                                    (HWREG32(0x4000E03C)) /* Channel n Source Configuration Register */
+#define DMA_CH12_SRCCFG                                    (HWREG32(0x4000E040)) /* Channel n Source Configuration Register */
+#define DMA_CH13_SRCCFG                                    (HWREG32(0x4000E044)) /* Channel n Source Configuration Register */
+#define DMA_CH14_SRCCFG                                    (HWREG32(0x4000E048)) /* Channel n Source Configuration Register */
+#define DMA_CH15_SRCCFG                                    (HWREG32(0x4000E04C)) /* Channel n Source Configuration Register */
+#define DMA_CH16_SRCCFG                                    (HWREG32(0x4000E050)) /* Channel n Source Configuration Register */
+#define DMA_CH17_SRCCFG                                    (HWREG32(0x4000E054)) /* Channel n Source Configuration Register */
+#define DMA_CH18_SRCCFG                                    (HWREG32(0x4000E058)) /* Channel n Source Configuration Register */
+#define DMA_CH19_SRCCFG                                    (HWREG32(0x4000E05C)) /* Channel n Source Configuration Register */
+#define DMA_CH20_SRCCFG                                    (HWREG32(0x4000E060)) /* Channel n Source Configuration Register */
+#define DMA_CH21_SRCCFG                                    (HWREG32(0x4000E064)) /* Channel n Source Configuration Register */
+#define DMA_CH22_SRCCFG                                    (HWREG32(0x4000E068)) /* Channel n Source Configuration Register */
+#define DMA_CH23_SRCCFG                                    (HWREG32(0x4000E06C)) /* Channel n Source Configuration Register */
+#define DMA_CH24_SRCCFG                                    (HWREG32(0x4000E070)) /* Channel n Source Configuration Register */
+#define DMA_CH25_SRCCFG                                    (HWREG32(0x4000E074)) /* Channel n Source Configuration Register */
+#define DMA_CH26_SRCCFG                                    (HWREG32(0x4000E078)) /* Channel n Source Configuration Register */
+#define DMA_CH27_SRCCFG                                    (HWREG32(0x4000E07C)) /* Channel n Source Configuration Register */
+#define DMA_CH28_SRCCFG                                    (HWREG32(0x4000E080)) /* Channel n Source Configuration Register */
+#define DMA_CH29_SRCCFG                                    (HWREG32(0x4000E084)) /* Channel n Source Configuration Register */
+#define DMA_CH30_SRCCFG                                    (HWREG32(0x4000E088)) /* Channel n Source Configuration Register */
+#define DMA_CH31_SRCCFG                                    (HWREG32(0x4000E08C)) /* Channel n Source Configuration Register */
+#define DMA_INT1_SRCCFG                                    (HWREG32(0x4000E100)) /* Interrupt 1 Source Channel Configuration */
+#define DMA_INT2_SRCCFG                                    (HWREG32(0x4000E104)) /* Interrupt 2 Source Channel Configuration Register */
+#define DMA_INT3_SRCCFG                                    (HWREG32(0x4000E108)) /* Interrupt 3 Source Channel Configuration Register */
+#define DMA_INT0_SRCFLG                                    (HWREG32(0x4000E110)) /* Interrupt 0 Source Channel Flag Register */
+#define DMA_INT0_CLRFLG                                    (HWREG32(0x4000E114)) /* Interrupt 0 Source Channel Clear Flag Register */
+#define DMA_STAT                                           (HWREG32(0x4000F000)) /* Status Register */
+#define DMA_CFG                                            (HWREG32(0x4000F004)) /* Configuration Register */
+#define DMA_CTLBASE                                        (HWREG32(0x4000F008)) /* Channel Control Data Base Pointer Register */
+#define DMA_ATLBASE                                        (HWREG32(0x4000F00C)) /* Channel Alternate Control Data Base Pointer Register */
+#define DMA_WAITSTAT                                       (HWREG32(0x4000F010)) /* Channel Wait on Request Status Register */
+#define DMA_SWREQ                                          (HWREG32(0x4000F014)) /* Channel Software Request Register */
+#define DMA_USEBURSTSET                                    (HWREG32(0x4000F018)) /* Channel Useburst Set Register */
+#define DMA_USEBURSTCLR                                    (HWREG32(0x4000F01C)) /* Channel Useburst Clear Register */
+#define DMA_REQMASKSET                                     (HWREG32(0x4000F020)) /* Channel Request Mask Set Register */
+#define DMA_REQMASKCLR                                     (HWREG32(0x4000F024)) /* Channel Request Mask Clear Register */
+#define DMA_ENASET                                         (HWREG32(0x4000F028)) /* Channel Enable Set Register */
+#define DMA_ENACLR                                         (HWREG32(0x4000F02C)) /* Channel Enable Clear Register */
+#define DMA_ALTSET                                         (HWREG32(0x4000F030)) /* Channel Primary-Alternate Set Register */
+#define DMA_ALTCLR                                         (HWREG32(0x4000F034)) /* Channel Primary-Alternate Clear Register */
+#define DMA_PRIOSET                                        (HWREG32(0x4000F038)) /* Channel Priority Set Register */
+#define DMA_PRIOCLR                                        (HWREG32(0x4000F03C)) /* Channel Priority Clear Register */
+#define DMA_ERRCLR                                         (HWREG32(0x4000F04C)) /* Bus Error Clear Register */
+
+/* Register offsets from DMA_BASE address */
+#define OFS_DMA_DEVICE_CFG                                 (0x00000000)          /* Device Configuration Status */
+#define OFS_DMA_SW_CHTRIG                                  (0x00000004)          /* Software Channel Trigger Register */
+#define OFS_DMA_CH0_SRCCFG                                 (0x00000010)          /* Channel n Source Configuration Register */
+#define OFS_DMA_CH1_SRCCFG                                 (0x00000014)          /* Channel n Source Configuration Register */
+#define OFS_DMA_CH2_SRCCFG                                 (0x00000018)          /* Channel n Source Configuration Register */
+#define OFS_DMA_CH3_SRCCFG                                 (0x0000001C)          /* Channel n Source Configuration Register */
+#define OFS_DMA_CH4_SRCCFG                                 (0x00000020)          /* Channel n Source Configuration Register */
+#define OFS_DMA_CH5_SRCCFG                                 (0x00000024)          /* Channel n Source Configuration Register */
+#define OFS_DMA_CH6_SRCCFG                                 (0x00000028)          /* Channel n Source Configuration Register */
+#define OFS_DMA_CH7_SRCCFG                                 (0x0000002C)          /* Channel n Source Configuration Register */
+#define OFS_DMA_CH8_SRCCFG                                 (0x00000030)          /* Channel n Source Configuration Register */
+#define OFS_DMA_CH9_SRCCFG                                 (0x00000034)          /* Channel n Source Configuration Register */
+#define OFS_DMA_CH10_SRCCFG                                (0x00000038)          /* Channel n Source Configuration Register */
+#define OFS_DMA_CH11_SRCCFG                                (0x0000003C)          /* Channel n Source Configuration Register */
+#define OFS_DMA_CH12_SRCCFG                                (0x00000040)          /* Channel n Source Configuration Register */
+#define OFS_DMA_CH13_SRCCFG                                (0x00000044)          /* Channel n Source Configuration Register */
+#define OFS_DMA_CH14_SRCCFG                                (0x00000048)          /* Channel n Source Configuration Register */
+#define OFS_DMA_CH15_SRCCFG                                (0x0000004C)          /* Channel n Source Configuration Register */
+#define OFS_DMA_CH16_SRCCFG                                (0x00000050)          /* Channel n Source Configuration Register */
+#define OFS_DMA_CH17_SRCCFG                                (0x00000054)          /* Channel n Source Configuration Register */
+#define OFS_DMA_CH18_SRCCFG                                (0x00000058)          /* Channel n Source Configuration Register */
+#define OFS_DMA_CH19_SRCCFG                                (0x0000005C)          /* Channel n Source Configuration Register */
+#define OFS_DMA_CH20_SRCCFG                                (0x00000060)          /* Channel n Source Configuration Register */
+#define OFS_DMA_CH21_SRCCFG                                (0x00000064)          /* Channel n Source Configuration Register */
+#define OFS_DMA_CH22_SRCCFG                                (0x00000068)          /* Channel n Source Configuration Register */
+#define OFS_DMA_CH23_SRCCFG                                (0x0000006C)          /* Channel n Source Configuration Register */
+#define OFS_DMA_CH24_SRCCFG                                (0x00000070)          /* Channel n Source Configuration Register */
+#define OFS_DMA_CH25_SRCCFG                                (0x00000074)          /* Channel n Source Configuration Register */
+#define OFS_DMA_CH26_SRCCFG                                (0x00000078)          /* Channel n Source Configuration Register */
+#define OFS_DMA_CH27_SRCCFG                                (0x0000007C)          /* Channel n Source Configuration Register */
+#define OFS_DMA_CH28_SRCCFG                                (0x00000080)          /* Channel n Source Configuration Register */
+#define OFS_DMA_CH29_SRCCFG                                (0x00000084)          /* Channel n Source Configuration Register */
+#define OFS_DMA_CH30_SRCCFG                                (0x00000088)          /* Channel n Source Configuration Register */
+#define OFS_DMA_CH31_SRCCFG                                (0x0000008C)          /* Channel n Source Configuration Register */
+#define OFS_DMA_INT1_SRCCFG                                (0x00000100)          /* Interrupt 1 Source Channel Configuration */
+#define OFS_DMA_INT2_SRCCFG                                (0x00000104)          /* Interrupt 2 Source Channel Configuration Register */
+#define OFS_DMA_INT3_SRCCFG                                (0x00000108)          /* Interrupt 3 Source Channel Configuration Register */
+#define OFS_DMA_INT0_SRCFLG                                (0x00000110)          /* Interrupt 0 Source Channel Flag Register */
+#define OFS_DMA_INT0_CLRFLG                                (0x00000114)          /* Interrupt 0 Source Channel Clear Flag Register */
+#define OFS_DMA_STAT                                       (0x00001000)          /* Status Register */
+#define OFS_DMA_CFG                                        (0x00001004)          /* Configuration Register */
+#define OFS_DMA_CTLBASE                                    (0x00001008)          /* Channel Control Data Base Pointer Register */
+#define OFS_DMA_ATLBASE                                    (0x0000100c)          /* Channel Alternate Control Data Base Pointer Register */
+#define OFS_DMA_WAITSTAT                                   (0x00001010)          /* Channel Wait on Request Status Register */
+#define OFS_DMA_SWREQ                                      (0x00001014)          /* Channel Software Request Register */
+#define OFS_DMA_USEBURSTSET                                (0x00001018)          /* Channel Useburst Set Register */
+#define OFS_DMA_USEBURSTCLR                                (0x0000101c)          /* Channel Useburst Clear Register */
+#define OFS_DMA_REQMASKSET                                 (0x00001020)          /* Channel Request Mask Set Register */
+#define OFS_DMA_REQMASKCLR                                 (0x00001024)          /* Channel Request Mask Clear Register */
+#define OFS_DMA_ENASET                                     (0x00001028)          /* Channel Enable Set Register */
+#define OFS_DMA_ENACLR                                     (0x0000102c)          /* Channel Enable Clear Register */
+#define OFS_DMA_ALTSET                                     (0x00001030)          /* Channel Primary-Alternate Set Register */
+#define OFS_DMA_ALTCLR                                     (0x00001034)          /* Channel Primary-Alternate Clear Register */
+#define OFS_DMA_PRIOSET                                    (0x00001038)          /* Channel Priority Set Register */
+#define OFS_DMA_PRIOCLR                                    (0x0000103c)          /* Channel Priority Clear Register */
+#define OFS_DMA_ERRCLR                                     (0x0000104c)          /* Bus Error Clear Register */
+
+
+//*****************************************************************************
+// DWT Registers
+//*****************************************************************************
+#define DWT_CTRL                                           (HWREG32(0xE0001000)) /* DWT Control Register */
+#define DWT_CYCCNT                                         (HWREG32(0xE0001004)) /* DWT Current PC Sampler Cycle Count Register */
+#define DWT_CPICNT                                         (HWREG32(0xE0001008)) /* DWT CPI Count Register */
+#define DWT_EXCCNT                                         (HWREG32(0xE000100C)) /* DWT Exception Overhead Count Register */
+#define DWT_SLEEPCNT                                       (HWREG32(0xE0001010)) /* DWT Sleep Count Register */
+#define DWT_LSUCNT                                         (HWREG32(0xE0001014)) /* DWT LSU Count Register */
+#define DWT_FOLDCNT                                        (HWREG32(0xE0001018)) /* DWT Fold Count Register */
+#define DWT_PCSR                                           (HWREG32(0xE000101C)) /* DWT Program Counter Sample Register */
+#define DWT_COMP0                                          (HWREG32(0xE0001020)) /* DWT Comparator Register 0 */
+#define DWT_MASK0                                          (HWREG32(0xE0001024)) /* DWT Mask Register 0 */
+#define DWT_FUNCTION0                                      (HWREG32(0xE0001028)) /* DWT Function Register 0 */
+#define DWT_COMP1                                          (HWREG32(0xE0001030)) /* DWT Comparator Register 1 */
+#define DWT_MASK1                                          (HWREG32(0xE0001034)) /* DWT Mask Register 1 */
+#define DWT_FUNCTION1                                      (HWREG32(0xE0001038)) /* DWT Function Register 1 */
+#define DWT_COMP2                                          (HWREG32(0xE0001040)) /* DWT Comparator Register 2 */
+#define DWT_MASK2                                          (HWREG32(0xE0001044)) /* DWT Mask Register 2 */
+#define DWT_FUNCTION2                                      (HWREG32(0xE0001048)) /* DWT Function Register 2 */
+#define DWT_COMP3                                          (HWREG32(0xE0001050)) /* DWT Comparator Register 3 */
+#define DWT_MASK3                                          (HWREG32(0xE0001054)) /* DWT Mask Register 3 */
+#define DWT_FUNCTION3                                      (HWREG32(0xE0001058)) /* DWT Function Register 3 */
+
+/* Register offsets from DWT_BASE address */
+#define OFS_DWT_CTRL                                       (0x00000000)          /* DWT Control Register */
+#define OFS_DWT_CYCCNT                                     (0x00000004)          /* DWT Current PC Sampler Cycle Count Register */
+#define OFS_DWT_CPICNT                                     (0x00000008)          /* DWT CPI Count Register */
+#define OFS_DWT_EXCCNT                                     (0x0000000C)          /* DWT Exception Overhead Count Register */
+#define OFS_DWT_SLEEPCNT                                   (0x00000010)          /* DWT Sleep Count Register */
+#define OFS_DWT_LSUCNT                                     (0x00000014)          /* DWT LSU Count Register */
+#define OFS_DWT_FOLDCNT                                    (0x00000018)          /* DWT Fold Count Register */
+#define OFS_DWT_PCSR                                       (0x0000001C)          /* DWT Program Counter Sample Register */
+#define OFS_DWT_COMP0                                      (0x00000020)          /* DWT Comparator Register 0 */
+#define OFS_DWT_MASK0                                      (0x00000024)          /* DWT Mask Register 0 */
+#define OFS_DWT_FUNCTION0                                  (0x00000028)          /* DWT Function Register 0 */
+#define OFS_DWT_COMP1                                      (0x00000030)          /* DWT Comparator Register 1 */
+#define OFS_DWT_MASK1                                      (0x00000034)          /* DWT Mask Register 1 */
+#define OFS_DWT_FUNCTION1                                  (0x00000038)          /* DWT Function Register 1 */
+#define OFS_DWT_COMP2                                      (0x00000040)          /* DWT Comparator Register 2 */
+#define OFS_DWT_MASK2                                      (0x00000044)          /* DWT Mask Register 2 */
+#define OFS_DWT_FUNCTION2                                  (0x00000048)          /* DWT Function Register 2 */
+#define OFS_DWT_COMP3                                      (0x00000050)          /* DWT Comparator Register 3 */
+#define OFS_DWT_MASK3                                      (0x00000054)          /* DWT Mask Register 3 */
+#define OFS_DWT_FUNCTION3                                  (0x00000058)          /* DWT Function Register 3 */
+
+
+//*****************************************************************************
+// EUSCI_A0 Registers
+//*****************************************************************************
+#define UCA0CTLW0                                          (HWREG16(0x40001000)) /* eUSCI_Ax Control Word Register 0 */
+#define UCA0CTLW0_SPI                                      (HWREG16(0x40001000)) /*  */
+#define UCA0CTLW1                                          (HWREG16(0x40001002)) /* eUSCI_Ax Control Word Register 1 */
+#define UCA0BRW                                            (HWREG16(0x40001006)) /* eUSCI_Ax Baud Rate Control Word Register */
+#define UCA0BRW_SPI                                        (HWREG16(0x40001006)) /*  */
+#define UCA0MCTLW                                          (HWREG16(0x40001008)) /* eUSCI_Ax Modulation Control Word Register */
+#define UCA0STATW                                          (HWREG16(0x4000100A)) /* eUSCI_Ax Status Register */
+#define UCA0STATW_SPI                                      (HWREG16(0x4000100A)) /*  */
+#define UCA0RXBUF                                          (HWREG16(0x4000100C)) /* eUSCI_Ax Receive Buffer Register */
+#define UCA0RXBUF_SPI                                      (HWREG16(0x4000100C)) /*  */
+#define UCA0TXBUF                                          (HWREG16(0x4000100E)) /* eUSCI_Ax Transmit Buffer Register */
+#define UCA0TXBUF_SPI                                      (HWREG16(0x4000100E)) /*  */
+#define UCA0ABCTL                                          (HWREG16(0x40001010)) /* eUSCI_Ax Auto Baud Rate Control Register */
+#define UCA0IRCTL                                          (HWREG16(0x40001012)) /* eUSCI_Ax IrDA Control Word Register */
+#define UCA0IE                                             (HWREG16(0x4000101A)) /* eUSCI_Ax Interrupt Enable Register */
+#define UCA0IE_SPI                                         (HWREG16(0x4000101A)) /*  */
+#define UCA0IFG                                            (HWREG16(0x4000101C)) /* eUSCI_Ax Interrupt Flag Register */
+#define UCA0IFG_SPI                                        (HWREG16(0x4000101C)) /*  */
+#define UCA0IV                                             (HWREG16(0x4000101E)) /* eUSCI_Ax Interrupt Vector Register */
+#define UCA0IV_SPI                                         (HWREG16(0x4000101E)) /*  */
+
+/* Register offsets from EUSCI_A0_BASE address */
+#define OFS_UCA0CTLW0                                      (0x0000)              /* eUSCI_Ax Control Word Register 0 */
+#define OFS_UCA0CTLW0_SPI                                  (0x0000)              /*  */
+#define OFS_UCA0CTLW1                                      (0x0002)              /* eUSCI_Ax Control Word Register 1 */
+#define OFS_UCA0BRW                                        (0x0006)              /* eUSCI_Ax Baud Rate Control Word Register */
+#define OFS_UCA0BRW_SPI                                    (0x0006)              /*  */
+#define OFS_UCA0MCTLW                                      (0x0008)              /* eUSCI_Ax Modulation Control Word Register */
+#define OFS_UCA0STATW                                      (0x000a)              /* eUSCI_Ax Status Register */
+#define OFS_UCA0STATW_SPI                                  (0x000a)              /*  */
+#define OFS_UCA0RXBUF                                      (0x000c)              /* eUSCI_Ax Receive Buffer Register */
+#define OFS_UCA0RXBUF_SPI                                  (0x000c)              /*  */
+#define OFS_UCA0TXBUF                                      (0x000e)              /* eUSCI_Ax Transmit Buffer Register */
+#define OFS_UCA0TXBUF_SPI                                  (0x000e)              /*  */
+#define OFS_UCA0ABCTL                                      (0x0010)              /* eUSCI_Ax Auto Baud Rate Control Register */
+#define OFS_UCA0IRCTL                                      (0x0012)              /* eUSCI_Ax IrDA Control Word Register */
+#define OFS_UCA0IE                                         (0x001a)              /* eUSCI_Ax Interrupt Enable Register */
+#define OFS_UCA0IE_SPI                                     (0x001a)              /*  */
+#define OFS_UCA0IFG                                        (0x001c)              /* eUSCI_Ax Interrupt Flag Register */
+#define OFS_UCA0IFG_SPI                                    (0x001c)              /*  */
+#define OFS_UCA0IV                                         (0x001e)              /* eUSCI_Ax Interrupt Vector Register */
+#define OFS_UCA0IV_SPI                                     (0x001e)              /*  */
+
+#define UCA0CTL0                                           (HWREG8_L(UCA0CTLW0)) /* eUSCI_Ax Control 0 */
+#define UCA0CTL1                                           (HWREG8_H(UCA0CTLW0)) /* eUSCI_Ax Control 1 */
+#define UCA0BR0                                            (HWREG8_L(UCA0BRW))   /* eUSCI_Ax Baud Rate Control 0 */
+#define UCA0BR1                                            (HWREG8_H(UCA0BRW))   /* eUSCI_Ax Baud Rate Control 1 */
+#define UCA0IRTCTL                                         (HWREG8_L(UCA0IRCTL)) /* eUSCI_Ax IrDA Transmit Control */
+#define UCA0IRRCTL                                         (HWREG8_H(UCA0IRCTL)) /* eUSCI_Ax IrDA Receive Control */
+
+//*****************************************************************************
+// EUSCI_A1 Registers
+//*****************************************************************************
+#define UCA1CTLW0                                          (HWREG16(0x40001400)) /* eUSCI_Ax Control Word Register 0 */
+#define UCA1CTLW0_SPI                                      (HWREG16(0x40001400)) /*  */
+#define UCA1CTLW1                                          (HWREG16(0x40001402)) /* eUSCI_Ax Control Word Register 1 */
+#define UCA1BRW                                            (HWREG16(0x40001406)) /* eUSCI_Ax Baud Rate Control Word Register */
+#define UCA1BRW_SPI                                        (HWREG16(0x40001406)) /*  */
+#define UCA1MCTLW                                          (HWREG16(0x40001408)) /* eUSCI_Ax Modulation Control Word Register */
+#define UCA1STATW                                          (HWREG16(0x4000140A)) /* eUSCI_Ax Status Register */
+#define UCA1STATW_SPI                                      (HWREG16(0x4000140A)) /*  */
+#define UCA1RXBUF                                          (HWREG16(0x4000140C)) /* eUSCI_Ax Receive Buffer Register */
+#define UCA1RXBUF_SPI                                      (HWREG16(0x4000140C)) /*  */
+#define UCA1TXBUF                                          (HWREG16(0x4000140E)) /* eUSCI_Ax Transmit Buffer Register */
+#define UCA1TXBUF_SPI                                      (HWREG16(0x4000140E)) /*  */
+#define UCA1ABCTL                                          (HWREG16(0x40001410)) /* eUSCI_Ax Auto Baud Rate Control Register */
+#define UCA1IRCTL                                          (HWREG16(0x40001412)) /* eUSCI_Ax IrDA Control Word Register */
+#define UCA1IE                                             (HWREG16(0x4000141A)) /* eUSCI_Ax Interrupt Enable Register */
+#define UCA1IE_SPI                                         (HWREG16(0x4000141A)) /*  */
+#define UCA1IFG                                            (HWREG16(0x4000141C)) /* eUSCI_Ax Interrupt Flag Register */
+#define UCA1IFG_SPI                                        (HWREG16(0x4000141C)) /*  */
+#define UCA1IV                                             (HWREG16(0x4000141E)) /* eUSCI_Ax Interrupt Vector Register */
+#define UCA1IV_SPI                                         (HWREG16(0x4000141E)) /*  */
+
+/* Register offsets from EUSCI_A1_BASE address */
+#define OFS_UCA1CTLW0                                      (0x0000)              /* eUSCI_Ax Control Word Register 0 */
+#define OFS_UCA1CTLW0_SPI                                  (0x0000)              /*  */
+#define OFS_UCA1CTLW1                                      (0x0002)              /* eUSCI_Ax Control Word Register 1 */
+#define OFS_UCA1BRW                                        (0x0006)              /* eUSCI_Ax Baud Rate Control Word Register */
+#define OFS_UCA1BRW_SPI                                    (0x0006)              /*  */
+#define OFS_UCA1MCTLW                                      (0x0008)              /* eUSCI_Ax Modulation Control Word Register */
+#define OFS_UCA1STATW                                      (0x000a)              /* eUSCI_Ax Status Register */
+#define OFS_UCA1STATW_SPI                                  (0x000a)              /*  */
+#define OFS_UCA1RXBUF                                      (0x000c)              /* eUSCI_Ax Receive Buffer Register */
+#define OFS_UCA1RXBUF_SPI                                  (0x000c)              /*  */
+#define OFS_UCA1TXBUF                                      (0x000e)              /* eUSCI_Ax Transmit Buffer Register */
+#define OFS_UCA1TXBUF_SPI                                  (0x000e)              /*  */
+#define OFS_UCA1ABCTL                                      (0x0010)              /* eUSCI_Ax Auto Baud Rate Control Register */
+#define OFS_UCA1IRCTL                                      (0x0012)              /* eUSCI_Ax IrDA Control Word Register */
+#define OFS_UCA1IE                                         (0x001a)              /* eUSCI_Ax Interrupt Enable Register */
+#define OFS_UCA1IE_SPI                                     (0x001a)              /*  */
+#define OFS_UCA1IFG                                        (0x001c)              /* eUSCI_Ax Interrupt Flag Register */
+#define OFS_UCA1IFG_SPI                                    (0x001c)              /*  */
+#define OFS_UCA1IV                                         (0x001e)              /* eUSCI_Ax Interrupt Vector Register */
+#define OFS_UCA1IV_SPI                                     (0x001e)              /*  */
+
+#define UCA1CTL0                                           (HWREG8_L(UCA1CTLW0)) /* eUSCI_Ax Control 0 */
+#define UCA1CTL1                                           (HWREG8_H(UCA1CTLW0)) /* eUSCI_Ax Control 1 */
+#define UCA1BR0                                            (HWREG8_L(UCA1BRW))   /* eUSCI_Ax Baud Rate Control 0 */
+#define UCA1BR1                                            (HWREG8_H(UCA1BRW))   /* eUSCI_Ax Baud Rate Control 1 */
+#define UCA1IRTCTL                                         (HWREG8_L(UCA1IRCTL)) /* eUSCI_Ax IrDA Transmit Control */
+#define UCA1IRRCTL                                         (HWREG8_H(UCA1IRCTL)) /* eUSCI_Ax IrDA Receive Control */
+
+//*****************************************************************************
+// EUSCI_A2 Registers
+//*****************************************************************************
+#define UCA2CTLW0                                          (HWREG16(0x40001800)) /* eUSCI_Ax Control Word Register 0 */
+#define UCA2CTLW0_SPI                                      (HWREG16(0x40001800)) /*  */
+#define UCA2CTLW1                                          (HWREG16(0x40001802)) /* eUSCI_Ax Control Word Register 1 */
+#define UCA2BRW                                            (HWREG16(0x40001806)) /* eUSCI_Ax Baud Rate Control Word Register */
+#define UCA2BRW_SPI                                        (HWREG16(0x40001806)) /*  */
+#define UCA2MCTLW                                          (HWREG16(0x40001808)) /* eUSCI_Ax Modulation Control Word Register */
+#define UCA2STATW                                          (HWREG16(0x4000180A)) /* eUSCI_Ax Status Register */
+#define UCA2STATW_SPI                                      (HWREG16(0x4000180A)) /*  */
+#define UCA2RXBUF                                          (HWREG16(0x4000180C)) /* eUSCI_Ax Receive Buffer Register */
+#define UCA2RXBUF_SPI                                      (HWREG16(0x4000180C)) /*  */
+#define UCA2TXBUF                                          (HWREG16(0x4000180E)) /* eUSCI_Ax Transmit Buffer Register */
+#define UCA2TXBUF_SPI                                      (HWREG16(0x4000180E)) /*  */
+#define UCA2ABCTL                                          (HWREG16(0x40001810)) /* eUSCI_Ax Auto Baud Rate Control Register */
+#define UCA2IRCTL                                          (HWREG16(0x40001812)) /* eUSCI_Ax IrDA Control Word Register */
+#define UCA2IE                                             (HWREG16(0x4000181A)) /* eUSCI_Ax Interrupt Enable Register */
+#define UCA2IE_SPI                                         (HWREG16(0x4000181A)) /*  */
+#define UCA2IFG                                            (HWREG16(0x4000181C)) /* eUSCI_Ax Interrupt Flag Register */
+#define UCA2IFG_SPI                                        (HWREG16(0x4000181C)) /*  */
+#define UCA2IV                                             (HWREG16(0x4000181E)) /* eUSCI_Ax Interrupt Vector Register */
+#define UCA2IV_SPI                                         (HWREG16(0x4000181E)) /*  */
+
+/* Register offsets from EUSCI_A2_BASE address */
+#define OFS_UCA2CTLW0                                      (0x0000)              /* eUSCI_Ax Control Word Register 0 */
+#define OFS_UCA2CTLW0_SPI                                  (0x0000)              /*  */
+#define OFS_UCA2CTLW1                                      (0x0002)              /* eUSCI_Ax Control Word Register 1 */
+#define OFS_UCA2BRW                                        (0x0006)              /* eUSCI_Ax Baud Rate Control Word Register */
+#define OFS_UCA2BRW_SPI                                    (0x0006)              /*  */
+#define OFS_UCA2MCTLW                                      (0x0008)              /* eUSCI_Ax Modulation Control Word Register */
+#define OFS_UCA2STATW                                      (0x000a)              /* eUSCI_Ax Status Register */
+#define OFS_UCA2STATW_SPI                                  (0x000a)              /*  */
+#define OFS_UCA2RXBUF                                      (0x000c)              /* eUSCI_Ax Receive Buffer Register */
+#define OFS_UCA2RXBUF_SPI                                  (0x000c)              /*  */
+#define OFS_UCA2TXBUF                                      (0x000e)              /* eUSCI_Ax Transmit Buffer Register */
+#define OFS_UCA2TXBUF_SPI                                  (0x000e)              /*  */
+#define OFS_UCA2ABCTL                                      (0x0010)              /* eUSCI_Ax Auto Baud Rate Control Register */
+#define OFS_UCA2IRCTL                                      (0x0012)              /* eUSCI_Ax IrDA Control Word Register */
+#define OFS_UCA2IE                                         (0x001a)              /* eUSCI_Ax Interrupt Enable Register */
+#define OFS_UCA2IE_SPI                                     (0x001a)              /*  */
+#define OFS_UCA2IFG                                        (0x001c)              /* eUSCI_Ax Interrupt Flag Register */
+#define OFS_UCA2IFG_SPI                                    (0x001c)              /*  */
+#define OFS_UCA2IV                                         (0x001e)              /* eUSCI_Ax Interrupt Vector Register */
+#define OFS_UCA2IV_SPI                                     (0x001e)              /*  */
+
+#define UCA2CTL0                                           (HWREG8_L(UCA2CTLW0)) /* eUSCI_Ax Control 0 */
+#define UCA2CTL1                                           (HWREG8_H(UCA2CTLW0)) /* eUSCI_Ax Control 1 */
+#define UCA2BR0                                            (HWREG8_L(UCA2BRW))   /* eUSCI_Ax Baud Rate Control 0 */
+#define UCA2BR1                                            (HWREG8_H(UCA2BRW))   /* eUSCI_Ax Baud Rate Control 1 */
+#define UCA2IRTCTL                                         (HWREG8_L(UCA2IRCTL)) /* eUSCI_Ax IrDA Transmit Control */
+#define UCA2IRRCTL                                         (HWREG8_H(UCA2IRCTL)) /* eUSCI_Ax IrDA Receive Control */
+
+//*****************************************************************************
+// EUSCI_A3 Registers
+//*****************************************************************************
+#define UCA3CTLW0                                          (HWREG16(0x40001C00)) /* eUSCI_Ax Control Word Register 0 */
+#define UCA3CTLW0_SPI                                      (HWREG16(0x40001C00)) /*  */
+#define UCA3CTLW1                                          (HWREG16(0x40001C02)) /* eUSCI_Ax Control Word Register 1 */
+#define UCA3BRW                                            (HWREG16(0x40001C06)) /* eUSCI_Ax Baud Rate Control Word Register */
+#define UCA3BRW_SPI                                        (HWREG16(0x40001C06)) /*  */
+#define UCA3MCTLW                                          (HWREG16(0x40001C08)) /* eUSCI_Ax Modulation Control Word Register */
+#define UCA3STATW                                          (HWREG16(0x40001C0A)) /* eUSCI_Ax Status Register */
+#define UCA3STATW_SPI                                      (HWREG16(0x40001C0A)) /*  */
+#define UCA3RXBUF                                          (HWREG16(0x40001C0C)) /* eUSCI_Ax Receive Buffer Register */
+#define UCA3RXBUF_SPI                                      (HWREG16(0x40001C0C)) /*  */
+#define UCA3TXBUF                                          (HWREG16(0x40001C0E)) /* eUSCI_Ax Transmit Buffer Register */
+#define UCA3TXBUF_SPI                                      (HWREG16(0x40001C0E)) /*  */
+#define UCA3ABCTL                                          (HWREG16(0x40001C10)) /* eUSCI_Ax Auto Baud Rate Control Register */
+#define UCA3IRCTL                                          (HWREG16(0x40001C12)) /* eUSCI_Ax IrDA Control Word Register */
+#define UCA3IE                                             (HWREG16(0x40001C1A)) /* eUSCI_Ax Interrupt Enable Register */
+#define UCA3IE_SPI                                         (HWREG16(0x40001C1A)) /*  */
+#define UCA3IFG                                            (HWREG16(0x40001C1C)) /* eUSCI_Ax Interrupt Flag Register */
+#define UCA3IFG_SPI                                        (HWREG16(0x40001C1C)) /*  */
+#define UCA3IV                                             (HWREG16(0x40001C1E)) /* eUSCI_Ax Interrupt Vector Register */
+#define UCA3IV_SPI                                         (HWREG16(0x40001C1E)) /*  */
+
+/* Register offsets from EUSCI_A3_BASE address */
+#define OFS_UCA3CTLW0                                      (0x0000)              /* eUSCI_Ax Control Word Register 0 */
+#define OFS_UCA3CTLW0_SPI                                  (0x0000)              /*  */
+#define OFS_UCA3CTLW1                                      (0x0002)              /* eUSCI_Ax Control Word Register 1 */
+#define OFS_UCA3BRW                                        (0x0006)              /* eUSCI_Ax Baud Rate Control Word Register */
+#define OFS_UCA3BRW_SPI                                    (0x0006)              /*  */
+#define OFS_UCA3MCTLW                                      (0x0008)              /* eUSCI_Ax Modulation Control Word Register */
+#define OFS_UCA3STATW                                      (0x000a)              /* eUSCI_Ax Status Register */
+#define OFS_UCA3STATW_SPI                                  (0x000a)              /*  */
+#define OFS_UCA3RXBUF                                      (0x000c)              /* eUSCI_Ax Receive Buffer Register */
+#define OFS_UCA3RXBUF_SPI                                  (0x000c)              /*  */
+#define OFS_UCA3TXBUF                                      (0x000e)              /* eUSCI_Ax Transmit Buffer Register */
+#define OFS_UCA3TXBUF_SPI                                  (0x000e)              /*  */
+#define OFS_UCA3ABCTL                                      (0x0010)              /* eUSCI_Ax Auto Baud Rate Control Register */
+#define OFS_UCA3IRCTL                                      (0x0012)              /* eUSCI_Ax IrDA Control Word Register */
+#define OFS_UCA3IE                                         (0x001a)              /* eUSCI_Ax Interrupt Enable Register */
+#define OFS_UCA3IE_SPI                                     (0x001a)              /*  */
+#define OFS_UCA3IFG                                        (0x001c)              /* eUSCI_Ax Interrupt Flag Register */
+#define OFS_UCA3IFG_SPI                                    (0x001c)              /*  */
+#define OFS_UCA3IV                                         (0x001e)              /* eUSCI_Ax Interrupt Vector Register */
+#define OFS_UCA3IV_SPI                                     (0x001e)              /*  */
+
+#define UCA3CTL0                                           (HWREG8_L(UCA3CTLW0)) /* eUSCI_Ax Control 0 */
+#define UCA3CTL1                                           (HWREG8_H(UCA3CTLW0)) /* eUSCI_Ax Control 1 */
+#define UCA3BR0                                            (HWREG8_L(UCA3BRW))   /* eUSCI_Ax Baud Rate Control 0 */
+#define UCA3BR1                                            (HWREG8_H(UCA3BRW))   /* eUSCI_Ax Baud Rate Control 1 */
+#define UCA3IRTCTL                                         (HWREG8_L(UCA3IRCTL)) /* eUSCI_Ax IrDA Transmit Control */
+#define UCA3IRRCTL                                         (HWREG8_H(UCA3IRCTL)) /* eUSCI_Ax IrDA Receive Control */
+
+//*****************************************************************************
+// EUSCI_B0 Registers
+//*****************************************************************************
+#define UCB0CTLW0                                          (HWREG16(0x40002000)) /* eUSCI_Bx Control Word Register 0 */
+#define UCB0CTLW0_SPI                                      (HWREG16(0x40002000)) /*  */
+#define UCB0CTLW1                                          (HWREG16(0x40002002)) /* eUSCI_Bx Control Word Register 1 */
+#define UCB0BRW                                            (HWREG16(0x40002006)) /* eUSCI_Bx Baud Rate Control Word Register */
+#define UCB0BRW_SPI                                        (HWREG16(0x40002006)) /*  */
+#define UCB0STATW                                          (HWREG16(0x40002008)) /* eUSCI_Bx Status Register */
+#define UCB0STATW_SPI                                      (HWREG16(0x40002008)) /*  */
+#define UCB0TBCNT                                          (HWREG16(0x4000200A)) /* eUSCI_Bx Byte Counter Threshold Register */
+#define UCB0RXBUF                                          (HWREG16(0x4000200C)) /* eUSCI_Bx Receive Buffer Register */
+#define UCB0RXBUF_SPI                                      (HWREG16(0x4000200C)) /*  */
+#define UCB0TXBUF                                          (HWREG16(0x4000200E)) /* eUSCI_Bx Transmit Buffer Register */
+#define UCB0TXBUF_SPI                                      (HWREG16(0x4000200E)) /*  */
+#define UCB0I2COA0                                         (HWREG16(0x40002014)) /* eUSCI_Bx I2C Own Address 0 Register */
+#define UCB0I2COA1                                         (HWREG16(0x40002016)) /* eUSCI_Bx I2C Own Address 1 Register */
+#define UCB0I2COA2                                         (HWREG16(0x40002018)) /* eUSCI_Bx I2C Own Address 2 Register */
+#define UCB0I2COA3                                         (HWREG16(0x4000201A)) /* eUSCI_Bx I2C Own Address 3 Register */
+#define UCB0ADDRX                                          (HWREG16(0x4000201C)) /* eUSCI_Bx I2C Received Address Register */
+#define UCB0ADDMASK                                        (HWREG16(0x4000201E)) /* eUSCI_Bx I2C Address Mask Register */
+#define UCB0I2CSA                                          (HWREG16(0x40002020)) /* eUSCI_Bx I2C Slave Address Register */
+#define UCB0IE                                             (HWREG16(0x4000202A)) /* eUSCI_Bx Interrupt Enable Register */
+#define UCB0IE_SPI                                         (HWREG16(0x4000202A)) /*  */
+#define UCB0IFG                                            (HWREG16(0x4000202C)) /* eUSCI_Bx Interrupt Flag Register */
+#define UCB0IFG_SPI                                        (HWREG16(0x4000202C)) /*  */
+#define UCB0IV                                             (HWREG16(0x4000202E)) /* eUSCI_Bx Interrupt Vector Register */
+#define UCB0IV_SPI                                         (HWREG16(0x4000202E)) /*  */
+
+/* Register offsets from EUSCI_B0_BASE address */
+#define OFS_UCB0CTLW0                                      (0x0000)              /* eUSCI_Bx Control Word Register 0 */
+#define OFS_UCB0CTLW0_SPI                                  (0x0000)              /*  */
+#define OFS_UCB0CTLW1                                      (0x0002)              /* eUSCI_Bx Control Word Register 1 */
+#define OFS_UCB0BRW                                        (0x0006)              /* eUSCI_Bx Baud Rate Control Word Register */
+#define OFS_UCB0BRW_SPI                                    (0x0006)              /*  */
+#define OFS_UCB0STATW                                      (0x0008)              /* eUSCI_Bx Status Register */
+#define OFS_UCB0STATW_SPI                                  (0x0008)              /*  */
+#define OFS_UCB0TBCNT                                      (0x000a)              /* eUSCI_Bx Byte Counter Threshold Register */
+#define OFS_UCB0RXBUF                                      (0x000c)              /* eUSCI_Bx Receive Buffer Register */
+#define OFS_UCB0RXBUF_SPI                                  (0x000c)              /*  */
+#define OFS_UCB0TXBUF                                      (0x000e)              /* eUSCI_Bx Transmit Buffer Register */
+#define OFS_UCB0TXBUF_SPI                                  (0x000e)              /*  */
+#define OFS_UCB0I2COA0                                     (0x0014)              /* eUSCI_Bx I2C Own Address 0 Register */
+#define OFS_UCB0I2COA1                                     (0x0016)              /* eUSCI_Bx I2C Own Address 1 Register */
+#define OFS_UCB0I2COA2                                     (0x0018)              /* eUSCI_Bx I2C Own Address 2 Register */
+#define OFS_UCB0I2COA3                                     (0x001a)              /* eUSCI_Bx I2C Own Address 3 Register */
+#define OFS_UCB0ADDRX                                      (0x001c)              /* eUSCI_Bx I2C Received Address Register */
+#define OFS_UCB0ADDMASK                                    (0x001e)              /* eUSCI_Bx I2C Address Mask Register */
+#define OFS_UCB0I2CSA                                      (0x0020)              /* eUSCI_Bx I2C Slave Address Register */
+#define OFS_UCB0IE                                         (0x002a)              /* eUSCI_Bx Interrupt Enable Register */
+#define OFS_UCB0IE_SPI                                     (0x002a)              /*  */
+#define OFS_UCB0IFG                                        (0x002c)              /* eUSCI_Bx Interrupt Flag Register */
+#define OFS_UCB0IFG_SPI                                    (0x002c)              /*  */
+#define OFS_UCB0IV                                         (0x002e)              /* eUSCI_Bx Interrupt Vector Register */
+#define OFS_UCB0IV_SPI                                     (0x002e)              /*  */
+
+#define UCB0CTL0                                           (HWREG8_L(UCB0CTLW0)) /* eUSCI_Bx Control 1 */
+#define UCB0CTL1                                           (HWREG8_H(UCB0CTLW0)) /* eUSCI_Bx Control 0 */
+#define UCB0BR0                                            (HWREG8_L(UCB0BRW))   /* eUSCI_Bx Bit Rate Control 0 */
+#define UCB0BR1                                            (HWREG8_H(UCB0BRW))   /* eUSCI_Bx Bit Rate Control 1 */
+#define UCB0STAT                                           (HWREG8_L(UCB0STATW)) /* eUSCI_Bx Status */
+#define UCB0BCNT                                           (HWREG8_H(UCB0STATW)) /* eUSCI_Bx Byte Counter Register */
+
+//*****************************************************************************
+// EUSCI_B1 Registers
+//*****************************************************************************
+#define UCB1CTLW0                                          (HWREG16(0x40002400)) /* eUSCI_Bx Control Word Register 0 */
+#define UCB1CTLW0_SPI                                      (HWREG16(0x40002400)) /*  */
+#define UCB1CTLW1                                          (HWREG16(0x40002402)) /* eUSCI_Bx Control Word Register 1 */
+#define UCB1BRW                                            (HWREG16(0x40002406)) /* eUSCI_Bx Baud Rate Control Word Register */
+#define UCB1BRW_SPI                                        (HWREG16(0x40002406)) /*  */
+#define UCB1STATW                                          (HWREG16(0x40002408)) /* eUSCI_Bx Status Register */
+#define UCB1STATW_SPI                                      (HWREG16(0x40002408)) /*  */
+#define UCB1TBCNT                                          (HWREG16(0x4000240A)) /* eUSCI_Bx Byte Counter Threshold Register */
+#define UCB1RXBUF                                          (HWREG16(0x4000240C)) /* eUSCI_Bx Receive Buffer Register */
+#define UCB1RXBUF_SPI                                      (HWREG16(0x4000240C)) /*  */
+#define UCB1TXBUF                                          (HWREG16(0x4000240E)) /* eUSCI_Bx Transmit Buffer Register */
+#define UCB1TXBUF_SPI                                      (HWREG16(0x4000240E)) /*  */
+#define UCB1I2COA0                                         (HWREG16(0x40002414)) /* eUSCI_Bx I2C Own Address 0 Register */
+#define UCB1I2COA1                                         (HWREG16(0x40002416)) /* eUSCI_Bx I2C Own Address 1 Register */
+#define UCB1I2COA2                                         (HWREG16(0x40002418)) /* eUSCI_Bx I2C Own Address 2 Register */
+#define UCB1I2COA3                                         (HWREG16(0x4000241A)) /* eUSCI_Bx I2C Own Address 3 Register */
+#define UCB1ADDRX                                          (HWREG16(0x4000241C)) /* eUSCI_Bx I2C Received Address Register */
+#define UCB1ADDMASK                                        (HWREG16(0x4000241E)) /* eUSCI_Bx I2C Address Mask Register */
+#define UCB1I2CSA                                          (HWREG16(0x40002420)) /* eUSCI_Bx I2C Slave Address Register */
+#define UCB1IE                                             (HWREG16(0x4000242A)) /* eUSCI_Bx Interrupt Enable Register */
+#define UCB1IE_SPI                                         (HWREG16(0x4000242A)) /*  */
+#define UCB1IFG                                            (HWREG16(0x4000242C)) /* eUSCI_Bx Interrupt Flag Register */
+#define UCB1IFG_SPI                                        (HWREG16(0x4000242C)) /*  */
+#define UCB1IV                                             (HWREG16(0x4000242E)) /* eUSCI_Bx Interrupt Vector Register */
+#define UCB1IV_SPI                                         (HWREG16(0x4000242E)) /*  */
+
+/* Register offsets from EUSCI_B1_BASE address */
+#define OFS_UCB1CTLW0                                      (0x0000)              /* eUSCI_Bx Control Word Register 0 */
+#define OFS_UCB1CTLW0_SPI                                  (0x0000)              /*  */
+#define OFS_UCB1CTLW1                                      (0x0002)              /* eUSCI_Bx Control Word Register 1 */
+#define OFS_UCB1BRW                                        (0x0006)              /* eUSCI_Bx Baud Rate Control Word Register */
+#define OFS_UCB1BRW_SPI                                    (0x0006)              /*  */
+#define OFS_UCB1STATW                                      (0x0008)              /* eUSCI_Bx Status Register */
+#define OFS_UCB1STATW_SPI                                  (0x0008)              /*  */
+#define OFS_UCB1TBCNT                                      (0x000a)              /* eUSCI_Bx Byte Counter Threshold Register */
+#define OFS_UCB1RXBUF                                      (0x000c)              /* eUSCI_Bx Receive Buffer Register */
+#define OFS_UCB1RXBUF_SPI                                  (0x000c)              /*  */
+#define OFS_UCB1TXBUF                                      (0x000e)              /* eUSCI_Bx Transmit Buffer Register */
+#define OFS_UCB1TXBUF_SPI                                  (0x000e)              /*  */
+#define OFS_UCB1I2COA0                                     (0x0014)              /* eUSCI_Bx I2C Own Address 0 Register */
+#define OFS_UCB1I2COA1                                     (0x0016)              /* eUSCI_Bx I2C Own Address 1 Register */
+#define OFS_UCB1I2COA2                                     (0x0018)              /* eUSCI_Bx I2C Own Address 2 Register */
+#define OFS_UCB1I2COA3                                     (0x001a)              /* eUSCI_Bx I2C Own Address 3 Register */
+#define OFS_UCB1ADDRX                                      (0x001c)              /* eUSCI_Bx I2C Received Address Register */
+#define OFS_UCB1ADDMASK                                    (0x001e)              /* eUSCI_Bx I2C Address Mask Register */
+#define OFS_UCB1I2CSA                                      (0x0020)              /* eUSCI_Bx I2C Slave Address Register */
+#define OFS_UCB1IE                                         (0x002a)              /* eUSCI_Bx Interrupt Enable Register */
+#define OFS_UCB1IE_SPI                                     (0x002a)              /*  */
+#define OFS_UCB1IFG                                        (0x002c)              /* eUSCI_Bx Interrupt Flag Register */
+#define OFS_UCB1IFG_SPI                                    (0x002c)              /*  */
+#define OFS_UCB1IV                                         (0x002e)              /* eUSCI_Bx Interrupt Vector Register */
+#define OFS_UCB1IV_SPI                                     (0x002e)              /*  */
+
+#define UCB1CTL0                                           (HWREG8_L(UCB1CTLW0)) /* eUSCI_Bx Control 1 */
+#define UCB1CTL1                                           (HWREG8_H(UCB1CTLW0)) /* eUSCI_Bx Control 0 */
+#define UCB1BR0                                            (HWREG8_L(UCB1BRW))   /* eUSCI_Bx Bit Rate Control 0 */
+#define UCB1BR1                                            (HWREG8_H(UCB1BRW))   /* eUSCI_Bx Bit Rate Control 1 */
+#define UCB1STAT                                           (HWREG8_L(UCB1STATW)) /* eUSCI_Bx Status */
+#define UCB1BCNT                                           (HWREG8_H(UCB1STATW)) /* eUSCI_Bx Byte Counter Register */
+
+//*****************************************************************************
+// EUSCI_B2 Registers
+//*****************************************************************************
+#define UCB2CTLW0                                          (HWREG16(0x40002800)) /* eUSCI_Bx Control Word Register 0 */
+#define UCB2CTLW0_SPI                                      (HWREG16(0x40002800)) /*  */
+#define UCB2CTLW1                                          (HWREG16(0x40002802)) /* eUSCI_Bx Control Word Register 1 */
+#define UCB2BRW                                            (HWREG16(0x40002806)) /* eUSCI_Bx Baud Rate Control Word Register */
+#define UCB2BRW_SPI                                        (HWREG16(0x40002806)) /*  */
+#define UCB2STATW                                          (HWREG16(0x40002808)) /* eUSCI_Bx Status Register */
+#define UCB2STATW_SPI                                      (HWREG16(0x40002808)) /*  */
+#define UCB2TBCNT                                          (HWREG16(0x4000280A)) /* eUSCI_Bx Byte Counter Threshold Register */
+#define UCB2RXBUF                                          (HWREG16(0x4000280C)) /* eUSCI_Bx Receive Buffer Register */
+#define UCB2RXBUF_SPI                                      (HWREG16(0x4000280C)) /*  */
+#define UCB2TXBUF                                          (HWREG16(0x4000280E)) /* eUSCI_Bx Transmit Buffer Register */
+#define UCB2TXBUF_SPI                                      (HWREG16(0x4000280E)) /*  */
+#define UCB2I2COA0                                         (HWREG16(0x40002814)) /* eUSCI_Bx I2C Own Address 0 Register */
+#define UCB2I2COA1                                         (HWREG16(0x40002816)) /* eUSCI_Bx I2C Own Address 1 Register */
+#define UCB2I2COA2                                         (HWREG16(0x40002818)) /* eUSCI_Bx I2C Own Address 2 Register */
+#define UCB2I2COA3                                         (HWREG16(0x4000281A)) /* eUSCI_Bx I2C Own Address 3 Register */
+#define UCB2ADDRX                                          (HWREG16(0x4000281C)) /* eUSCI_Bx I2C Received Address Register */
+#define UCB2ADDMASK                                        (HWREG16(0x4000281E)) /* eUSCI_Bx I2C Address Mask Register */
+#define UCB2I2CSA                                          (HWREG16(0x40002820)) /* eUSCI_Bx I2C Slave Address Register */
+#define UCB2IE                                             (HWREG16(0x4000282A)) /* eUSCI_Bx Interrupt Enable Register */
+#define UCB2IE_SPI                                         (HWREG16(0x4000282A)) /*  */
+#define UCB2IFG                                            (HWREG16(0x4000282C)) /* eUSCI_Bx Interrupt Flag Register */
+#define UCB2IFG_SPI                                        (HWREG16(0x4000282C)) /*  */
+#define UCB2IV                                             (HWREG16(0x4000282E)) /* eUSCI_Bx Interrupt Vector Register */
+#define UCB2IV_SPI                                         (HWREG16(0x4000282E)) /*  */
+
+/* Register offsets from EUSCI_B2_BASE address */
+#define OFS_UCB2CTLW0                                      (0x0000)              /* eUSCI_Bx Control Word Register 0 */
+#define OFS_UCB2CTLW0_SPI                                  (0x0000)              /*  */
+#define OFS_UCB2CTLW1                                      (0x0002)              /* eUSCI_Bx Control Word Register 1 */
+#define OFS_UCB2BRW                                        (0x0006)              /* eUSCI_Bx Baud Rate Control Word Register */
+#define OFS_UCB2BRW_SPI                                    (0x0006)              /*  */
+#define OFS_UCB2STATW                                      (0x0008)              /* eUSCI_Bx Status Register */
+#define OFS_UCB2STATW_SPI                                  (0x0008)              /*  */
+#define OFS_UCB2TBCNT                                      (0x000a)              /* eUSCI_Bx Byte Counter Threshold Register */
+#define OFS_UCB2RXBUF                                      (0x000c)              /* eUSCI_Bx Receive Buffer Register */
+#define OFS_UCB2RXBUF_SPI                                  (0x000c)              /*  */
+#define OFS_UCB2TXBUF                                      (0x000e)              /* eUSCI_Bx Transmit Buffer Register */
+#define OFS_UCB2TXBUF_SPI                                  (0x000e)              /*  */
+#define OFS_UCB2I2COA0                                     (0x0014)              /* eUSCI_Bx I2C Own Address 0 Register */
+#define OFS_UCB2I2COA1                                     (0x0016)              /* eUSCI_Bx I2C Own Address 1 Register */
+#define OFS_UCB2I2COA2                                     (0x0018)              /* eUSCI_Bx I2C Own Address 2 Register */
+#define OFS_UCB2I2COA3                                     (0x001a)              /* eUSCI_Bx I2C Own Address 3 Register */
+#define OFS_UCB2ADDRX                                      (0x001c)              /* eUSCI_Bx I2C Received Address Register */
+#define OFS_UCB2ADDMASK                                    (0x001e)              /* eUSCI_Bx I2C Address Mask Register */
+#define OFS_UCB2I2CSA                                      (0x0020)              /* eUSCI_Bx I2C Slave Address Register */
+#define OFS_UCB2IE                                         (0x002a)              /* eUSCI_Bx Interrupt Enable Register */
+#define OFS_UCB2IE_SPI                                     (0x002a)              /*  */
+#define OFS_UCB2IFG                                        (0x002c)              /* eUSCI_Bx Interrupt Flag Register */
+#define OFS_UCB2IFG_SPI                                    (0x002c)              /*  */
+#define OFS_UCB2IV                                         (0x002e)              /* eUSCI_Bx Interrupt Vector Register */
+#define OFS_UCB2IV_SPI                                     (0x002e)              /*  */
+
+#define UCB2CTL0                                           (HWREG8_L(UCB2CTLW0)) /* eUSCI_Bx Control 1 */
+#define UCB2CTL1                                           (HWREG8_H(UCB2CTLW0)) /* eUSCI_Bx Control 0 */
+#define UCB2BR0                                            (HWREG8_L(UCB2BRW))   /* eUSCI_Bx Bit Rate Control 0 */
+#define UCB2BR1                                            (HWREG8_H(UCB2BRW))   /* eUSCI_Bx Bit Rate Control 1 */
+#define UCB2STAT                                           (HWREG8_L(UCB2STATW)) /* eUSCI_Bx Status */
+#define UCB2BCNT                                           (HWREG8_H(UCB2STATW)) /* eUSCI_Bx Byte Counter Register */
+
+//*****************************************************************************
+// EUSCI_B3 Registers
+//*****************************************************************************
+#define UCB3CTLW0                                          (HWREG16(0x40002C00)) /* eUSCI_Bx Control Word Register 0 */
+#define UCB3CTLW0_SPI                                      (HWREG16(0x40002C00)) /*  */
+#define UCB3CTLW1                                          (HWREG16(0x40002C02)) /* eUSCI_Bx Control Word Register 1 */
+#define UCB3BRW                                            (HWREG16(0x40002C06)) /* eUSCI_Bx Baud Rate Control Word Register */
+#define UCB3BRW_SPI                                        (HWREG16(0x40002C06)) /*  */
+#define UCB3STATW                                          (HWREG16(0x40002C08)) /* eUSCI_Bx Status Register */
+#define UCB3STATW_SPI                                      (HWREG16(0x40002C08)) /*  */
+#define UCB3TBCNT                                          (HWREG16(0x40002C0A)) /* eUSCI_Bx Byte Counter Threshold Register */
+#define UCB3RXBUF                                          (HWREG16(0x40002C0C)) /* eUSCI_Bx Receive Buffer Register */
+#define UCB3RXBUF_SPI                                      (HWREG16(0x40002C0C)) /*  */
+#define UCB3TXBUF                                          (HWREG16(0x40002C0E)) /* eUSCI_Bx Transmit Buffer Register */
+#define UCB3TXBUF_SPI                                      (HWREG16(0x40002C0E)) /*  */
+#define UCB3I2COA0                                         (HWREG16(0x40002C14)) /* eUSCI_Bx I2C Own Address 0 Register */
+#define UCB3I2COA1                                         (HWREG16(0x40002C16)) /* eUSCI_Bx I2C Own Address 1 Register */
+#define UCB3I2COA2                                         (HWREG16(0x40002C18)) /* eUSCI_Bx I2C Own Address 2 Register */
+#define UCB3I2COA3                                         (HWREG16(0x40002C1A)) /* eUSCI_Bx I2C Own Address 3 Register */
+#define UCB3ADDRX                                          (HWREG16(0x40002C1C)) /* eUSCI_Bx I2C Received Address Register */
+#define UCB3ADDMASK                                        (HWREG16(0x40002C1E)) /* eUSCI_Bx I2C Address Mask Register */
+#define UCB3I2CSA                                          (HWREG16(0x40002C20)) /* eUSCI_Bx I2C Slave Address Register */
+#define UCB3IE                                             (HWREG16(0x40002C2A)) /* eUSCI_Bx Interrupt Enable Register */
+#define UCB3IE_SPI                                         (HWREG16(0x40002C2A)) /*  */
+#define UCB3IFG                                            (HWREG16(0x40002C2C)) /* eUSCI_Bx Interrupt Flag Register */
+#define UCB3IFG_SPI                                        (HWREG16(0x40002C2C)) /*  */
+#define UCB3IV                                             (HWREG16(0x40002C2E)) /* eUSCI_Bx Interrupt Vector Register */
+#define UCB3IV_SPI                                         (HWREG16(0x40002C2E)) /*  */
+
+/* Register offsets from EUSCI_B3_BASE address */
+#define OFS_UCB3CTLW0                                      (0x0000)              /* eUSCI_Bx Control Word Register 0 */
+#define OFS_UCB3CTLW0_SPI                                  (0x0000)              /*  */
+#define OFS_UCB3CTLW1                                      (0x0002)              /* eUSCI_Bx Control Word Register 1 */
+#define OFS_UCB3BRW                                        (0x0006)              /* eUSCI_Bx Baud Rate Control Word Register */
+#define OFS_UCB3BRW_SPI                                    (0x0006)              /*  */
+#define OFS_UCB3STATW                                      (0x0008)              /* eUSCI_Bx Status Register */
+#define OFS_UCB3STATW_SPI                                  (0x0008)              /*  */
+#define OFS_UCB3TBCNT                                      (0x000a)              /* eUSCI_Bx Byte Counter Threshold Register */
+#define OFS_UCB3RXBUF                                      (0x000c)              /* eUSCI_Bx Receive Buffer Register */
+#define OFS_UCB3RXBUF_SPI                                  (0x000c)              /*  */
+#define OFS_UCB3TXBUF                                      (0x000e)              /* eUSCI_Bx Transmit Buffer Register */
+#define OFS_UCB3TXBUF_SPI                                  (0x000e)              /*  */
+#define OFS_UCB3I2COA0                                     (0x0014)              /* eUSCI_Bx I2C Own Address 0 Register */
+#define OFS_UCB3I2COA1                                     (0x0016)              /* eUSCI_Bx I2C Own Address 1 Register */
+#define OFS_UCB3I2COA2                                     (0x0018)              /* eUSCI_Bx I2C Own Address 2 Register */
+#define OFS_UCB3I2COA3                                     (0x001a)              /* eUSCI_Bx I2C Own Address 3 Register */
+#define OFS_UCB3ADDRX                                      (0x001c)              /* eUSCI_Bx I2C Received Address Register */
+#define OFS_UCB3ADDMASK                                    (0x001e)              /* eUSCI_Bx I2C Address Mask Register */
+#define OFS_UCB3I2CSA                                      (0x0020)              /* eUSCI_Bx I2C Slave Address Register */
+#define OFS_UCB3IE                                         (0x002a)              /* eUSCI_Bx Interrupt Enable Register */
+#define OFS_UCB3IE_SPI                                     (0x002a)              /*  */
+#define OFS_UCB3IFG                                        (0x002c)              /* eUSCI_Bx Interrupt Flag Register */
+#define OFS_UCB3IFG_SPI                                    (0x002c)              /*  */
+#define OFS_UCB3IV                                         (0x002e)              /* eUSCI_Bx Interrupt Vector Register */
+#define OFS_UCB3IV_SPI                                     (0x002e)              /*  */
+
+#define UCB3CTL0                                           (HWREG8_L(UCB3CTLW0)) /* eUSCI_Bx Control 1 */
+#define UCB3CTL1                                           (HWREG8_H(UCB3CTLW0)) /* eUSCI_Bx Control 0 */
+#define UCB3BR0                                            (HWREG8_L(UCB3BRW))   /* eUSCI_Bx Bit Rate Control 0 */
+#define UCB3BR1                                            (HWREG8_H(UCB3BRW))   /* eUSCI_Bx Bit Rate Control 1 */
+#define UCB3STAT                                           (HWREG8_L(UCB3STATW)) /* eUSCI_Bx Status */
+#define UCB3BCNT                                           (HWREG8_H(UCB3STATW)) /* eUSCI_Bx Byte Counter Register */
+
+//*****************************************************************************
+// FLCTL Registers
+//*****************************************************************************
+#define FLCTL_POWER_STAT                                   (HWREG32(0x40011000)) /* Power Status Register */
+#define FLCTL_BANK0_RDCTL                                  (HWREG32(0x40011010)) /* Bank0 Read Control Register */
+#define FLCTL_BANK1_RDCTL                                  (HWREG32(0x40011014)) /* Bank1 Read Control Register */
+#define FLCTL_RDBRST_CTLSTAT                               (HWREG32(0x40011020)) /* Read Burst/Compare Control and Status Register */
+#define FLCTL_RDBRST_STARTADDR                             (HWREG32(0x40011024)) /* Read Burst/Compare Start Address Register */
+#define FLCTL_RDBRST_LEN                                   (HWREG32(0x40011028)) /* Read Burst/Compare Length Register */
+#define FLCTL_RDBRST_FAILADDR                              (HWREG32(0x4001103C)) /* Read Burst/Compare Fail Address Register */
+#define FLCTL_RDBRST_FAILCNT                               (HWREG32(0x40011040)) /* Read Burst/Compare Fail Count Register */
+#define FLCTL_PRG_CTLSTAT                                  (HWREG32(0x40011050)) /* Program Control and Status Register */
+#define FLCTL_PRGBRST_CTLSTAT                              (HWREG32(0x40011054)) /* Program Burst Control and Status Register */
+#define FLCTL_PRGBRST_STARTADDR                            (HWREG32(0x40011058)) /* Program Burst Start Address Register */
+#define FLCTL_PRGBRST_DATA0_0                              (HWREG32(0x40011060)) /* Program Burst Data0 Register0 */
+#define FLCTL_PRGBRST_DATA0_1                              (HWREG32(0x40011064)) /* Program Burst Data0 Register1 */
+#define FLCTL_PRGBRST_DATA0_2                              (HWREG32(0x40011068)) /* Program Burst Data0 Register2 */
+#define FLCTL_PRGBRST_DATA0_3                              (HWREG32(0x4001106C)) /* Program Burst Data0 Register3 */
+#define FLCTL_PRGBRST_DATA1_0                              (HWREG32(0x40011070)) /* Program Burst Data1 Register0 */
+#define FLCTL_PRGBRST_DATA1_1                              (HWREG32(0x40011074)) /* Program Burst Data1 Register1 */
+#define FLCTL_PRGBRST_DATA1_2                              (HWREG32(0x40011078)) /* Program Burst Data1 Register2 */
+#define FLCTL_PRGBRST_DATA1_3                              (HWREG32(0x4001107C)) /* Program Burst Data1 Register3 */
+#define FLCTL_PRGBRST_DATA2_0                              (HWREG32(0x40011080)) /* Program Burst Data2 Register0 */
+#define FLCTL_PRGBRST_DATA2_1                              (HWREG32(0x40011084)) /* Program Burst Data2 Register1 */
+#define FLCTL_PRGBRST_DATA2_2                              (HWREG32(0x40011088)) /* Program Burst Data2 Register2 */
+#define FLCTL_PRGBRST_DATA2_3                              (HWREG32(0x4001108C)) /* Program Burst Data2 Register3 */
+#define FLCTL_PRGBRST_DATA3_0                              (HWREG32(0x40011090)) /* Program Burst Data3 Register0 */
+#define FLCTL_PRGBRST_DATA3_1                              (HWREG32(0x40011094)) /* Program Burst Data3 Register1 */
+#define FLCTL_PRGBRST_DATA3_2                              (HWREG32(0x40011098)) /* Program Burst Data3 Register2 */
+#define FLCTL_PRGBRST_DATA3_3                              (HWREG32(0x4001109C)) /* Program Burst Data3 Register3 */
+#define FLCTL_ERASE_CTLSTAT                                (HWREG32(0x400110A0)) /* Erase Control and Status Register */
+#define FLCTL_ERASE_SECTADDR                               (HWREG32(0x400110A4)) /* Erase Sector Address Register */
+#define FLCTL_BANK0_INFO_WEPROT                            (HWREG32(0x400110B0)) /* Information Memory Bank0 Write/Erase Protection Register */
+#define FLCTL_BANK0_MAIN_WEPROT                            (HWREG32(0x400110B4)) /* Main Memory Bank0 Write/Erase Protection Register */
+#define FLCTL_BANK1_INFO_WEPROT                            (HWREG32(0x400110C0)) /* Information Memory Bank1 Write/Erase Protection Register */
+#define FLCTL_BANK1_MAIN_WEPROT                            (HWREG32(0x400110C4)) /* Main Memory Bank1 Write/Erase Protection Register */
+#define FLCTL_BMRK_CTLSTAT                                 (HWREG32(0x400110D0)) /* Benchmark Control and Status Register */
+#define FLCTL_BMRK_IFETCH                                  (HWREG32(0x400110D4)) /* Benchmark Instruction Fetch Count Register */
+#define FLCTL_BMRK_DREAD                                   (HWREG32(0x400110D8)) /* Benchmark Data Read Count Register */
+#define FLCTL_BMRK_CMP                                     (HWREG32(0x400110DC)) /* Benchmark Count Compare Register */
+#define FLCTL_IFG                                          (HWREG32(0x400110F0)) /* Interrupt Flag Register */
+#define FLCTL_IE                                           (HWREG32(0x400110F4)) /* Interrupt Enable Register */
+#define FLCTL_CLRIFG                                       (HWREG32(0x400110F8)) /* Clear Interrupt Flag Register */
+#define FLCTL_SETIFG                                       (HWREG32(0x400110FC)) /* Set Interrupt Flag Register */
+#define FLCTL_READ_TIMCTL                                  (HWREG32(0x40011100)) /* Read Timing Control Register */
+#define FLCTL_READMARGIN_TIMCTL                            (HWREG32(0x40011104)) /* Read Margin Timing Control Register */
+#define FLCTL_PRGVER_TIMCTL                                (HWREG32(0x40011108)) /* Program Verify Timing Control Register */
+#define FLCTL_ERSVER_TIMCTL                                (HWREG32(0x4001110C)) /* Erase Verify Timing Control Register */
+#define FLCTL_LKGVER_TIMCTL                                (HWREG32(0x40011110)) /* Leakage Verify Timing Control Register */
+#define FLCTL_PROGRAM_TIMCTL                               (HWREG32(0x40011114)) /* Program Timing Control Register */
+#define FLCTL_ERASE_TIMCTL                                 (HWREG32(0x40011118)) /* Erase Timing Control Register */
+#define FLCTL_MASSERASE_TIMCTL                             (HWREG32(0x4001111C)) /* Mass Erase Timing Control Register */
+#define FLCTL_BURSTPRG_TIMCTL                              (HWREG32(0x40011120)) /* Burst Program Timing Control Register */
+
+/* Register offsets from FLCTL_BASE address */
+#define OFS_FLCTL_POWER_STAT                               (0x00000000)          /* Power Status Register */
+#define OFS_FLCTL_BANK0_RDCTL                              (0x00000010)          /* Bank0 Read Control Register */
+#define OFS_FLCTL_BANK1_RDCTL                              (0x00000014)          /* Bank1 Read Control Register */
+#define OFS_FLCTL_RDBRST_CTLSTAT                           (0x00000020)          /* Read Burst/Compare Control and Status Register */
+#define OFS_FLCTL_RDBRST_STARTADDR                         (0x00000024)          /* Read Burst/Compare Start Address Register */
+#define OFS_FLCTL_RDBRST_LEN                               (0x00000028)          /* Read Burst/Compare Length Register */
+#define OFS_FLCTL_RDBRST_FAILADDR                          (0x0000003C)          /* Read Burst/Compare Fail Address Register */
+#define OFS_FLCTL_RDBRST_FAILCNT                           (0x00000040)          /* Read Burst/Compare Fail Count Register */
+#define OFS_FLCTL_PRG_CTLSTAT                              (0x00000050)          /* Program Control and Status Register */
+#define OFS_FLCTL_PRGBRST_CTLSTAT                          (0x00000054)          /* Program Burst Control and Status Register */
+#define OFS_FLCTL_PRGBRST_STARTADDR                        (0x00000058)          /* Program Burst Start Address Register */
+#define OFS_FLCTL_PRGBRST_DATA0_0                          (0x00000060)          /* Program Burst Data0 Register0 */
+#define OFS_FLCTL_PRGBRST_DATA0_1                          (0x00000064)          /* Program Burst Data0 Register1 */
+#define OFS_FLCTL_PRGBRST_DATA0_2                          (0x00000068)          /* Program Burst Data0 Register2 */
+#define OFS_FLCTL_PRGBRST_DATA0_3                          (0x0000006C)          /* Program Burst Data0 Register3 */
+#define OFS_FLCTL_PRGBRST_DATA1_0                          (0x00000070)          /* Program Burst Data1 Register0 */
+#define OFS_FLCTL_PRGBRST_DATA1_1                          (0x00000074)          /* Program Burst Data1 Register1 */
+#define OFS_FLCTL_PRGBRST_DATA1_2                          (0x00000078)          /* Program Burst Data1 Register2 */
+#define OFS_FLCTL_PRGBRST_DATA1_3                          (0x0000007C)          /* Program Burst Data1 Register3 */
+#define OFS_FLCTL_PRGBRST_DATA2_0                          (0x00000080)          /* Program Burst Data2 Register0 */
+#define OFS_FLCTL_PRGBRST_DATA2_1                          (0x00000084)          /* Program Burst Data2 Register1 */
+#define OFS_FLCTL_PRGBRST_DATA2_2                          (0x00000088)          /* Program Burst Data2 Register2 */
+#define OFS_FLCTL_PRGBRST_DATA2_3                          (0x0000008C)          /* Program Burst Data2 Register3 */
+#define OFS_FLCTL_PRGBRST_DATA3_0                          (0x00000090)          /* Program Burst Data3 Register0 */
+#define OFS_FLCTL_PRGBRST_DATA3_1                          (0x00000094)          /* Program Burst Data3 Register1 */
+#define OFS_FLCTL_PRGBRST_DATA3_2                          (0x00000098)          /* Program Burst Data3 Register2 */
+#define OFS_FLCTL_PRGBRST_DATA3_3                          (0x0000009C)          /* Program Burst Data3 Register3 */
+#define OFS_FLCTL_ERASE_CTLSTAT                            (0x000000A0)          /* Erase Control and Status Register */
+#define OFS_FLCTL_ERASE_SECTADDR                           (0x000000A4)          /* Erase Sector Address Register */
+#define OFS_FLCTL_BANK0_INFO_WEPROT                        (0x000000B0)          /* Information Memory Bank0 Write/Erase Protection Register */
+#define OFS_FLCTL_BANK0_MAIN_WEPROT                        (0x000000B4)          /* Main Memory Bank0 Write/Erase Protection Register */
+#define OFS_FLCTL_BANK1_INFO_WEPROT                        (0x000000C0)          /* Information Memory Bank1 Write/Erase Protection Register */
+#define OFS_FLCTL_BANK1_MAIN_WEPROT                        (0x000000C4)          /* Main Memory Bank1 Write/Erase Protection Register */
+#define OFS_FLCTL_BMRK_CTLSTAT                             (0x000000D0)          /* Benchmark Control and Status Register */
+#define OFS_FLCTL_BMRK_IFETCH                              (0x000000D4)          /* Benchmark Instruction Fetch Count Register */
+#define OFS_FLCTL_BMRK_DREAD                               (0x000000D8)          /* Benchmark Data Read Count Register */
+#define OFS_FLCTL_BMRK_CMP                                 (0x000000DC)          /* Benchmark Count Compare Register */
+#define OFS_FLCTL_IFG                                      (0x000000F0)          /* Interrupt Flag Register */
+#define OFS_FLCTL_IE                                       (0x000000F4)          /* Interrupt Enable Register */
+#define OFS_FLCTL_CLRIFG                                   (0x000000F8)          /* Clear Interrupt Flag Register */
+#define OFS_FLCTL_SETIFG                                   (0x000000FC)          /* Set Interrupt Flag Register */
+#define OFS_FLCTL_READ_TIMCTL                              (0x00000100)          /* Read Timing Control Register */
+#define OFS_FLCTL_READMARGIN_TIMCTL                        (0x00000104)          /* Read Margin Timing Control Register */
+#define OFS_FLCTL_PRGVER_TIMCTL                            (0x00000108)          /* Program Verify Timing Control Register */
+#define OFS_FLCTL_ERSVER_TIMCTL                            (0x0000010C)          /* Erase Verify Timing Control Register */
+#define OFS_FLCTL_LKGVER_TIMCTL                            (0x00000110)          /* Leakage Verify Timing Control Register */
+#define OFS_FLCTL_PROGRAM_TIMCTL                           (0x00000114)          /* Program Timing Control Register */
+#define OFS_FLCTL_ERASE_TIMCTL                             (0x00000118)          /* Erase Timing Control Register */
+#define OFS_FLCTL_MASSERASE_TIMCTL                         (0x0000011C)          /* Mass Erase Timing Control Register */
+#define OFS_FLCTL_BURSTPRG_TIMCTL                          (0x00000120)          /* Burst Program Timing Control Register */
+
+
+//*****************************************************************************
+// FPB Registers
+//*****************************************************************************
+#define FPB_FP_CTRL                                        (HWREG32(0xE0002000)) /* Flash Patch Control Register */
+#define FPB_FP_REMAP                                       (HWREG32(0xE0002004)) /* Flash Patch Remap Register */
+#define FPB_FP_COMP0                                       (HWREG32(0xE0002008)) /* Flash Patch Comparator Registers */
+#define FPB_FP_COMP1                                       (HWREG32(0xE000200C)) /* Flash Patch Comparator Registers */
+#define FPB_FP_COMP2                                       (HWREG32(0xE0002010)) /* Flash Patch Comparator Registers */
+#define FPB_FP_COMP3                                       (HWREG32(0xE0002014)) /* Flash Patch Comparator Registers */
+#define FPB_FP_COMP4                                       (HWREG32(0xE0002018)) /* Flash Patch Comparator Registers */
+#define FPB_FP_COMP5                                       (HWREG32(0xE000201C)) /* Flash Patch Comparator Registers */
+#define FPB_FP_COMP6                                       (HWREG32(0xE0002020)) /* Flash Patch Comparator Registers */
+#define FPB_FP_COMP7                                       (HWREG32(0xE0002024)) /* Flash Patch Comparator Registers */
+
+/* Register offsets from FPB_BASE address */
+#define OFS_FPB_FP_CTRL                                    (0x00000000)          /* Flash Patch Control Register */
+#define OFS_FPB_FP_REMAP                                   (0x00000004)          /* Flash Patch Remap Register */
+#define OFS_FPB_FP_COMP0                                   (0x00000008)          /* Flash Patch Comparator Registers */
+#define OFS_FPB_FP_COMP1                                   (0x0000000C)          /* Flash Patch Comparator Registers */
+#define OFS_FPB_FP_COMP2                                   (0x00000010)          /* Flash Patch Comparator Registers */
+#define OFS_FPB_FP_COMP3                                   (0x00000014)          /* Flash Patch Comparator Registers */
+#define OFS_FPB_FP_COMP4                                   (0x00000018)          /* Flash Patch Comparator Registers */
+#define OFS_FPB_FP_COMP5                                   (0x0000001C)          /* Flash Patch Comparator Registers */
+#define OFS_FPB_FP_COMP6                                   (0x00000020)          /* Flash Patch Comparator Registers */
+#define OFS_FPB_FP_COMP7                                   (0x00000024)          /* Flash Patch Comparator Registers */
+
+
+//*****************************************************************************
+// FPU Registers
+//*****************************************************************************
+#define FPU_FPCCR                                          (HWREG32(0xE000EF34)) /* Floating Point Context Control Register */
+#define FPU_FPCAR                                          (HWREG32(0xE000EF38)) /* Floating-Point Context Address Register */
+#define FPU_FPDSCR                                         (HWREG32(0xE000EF3C)) /* Floating Point Default Status Control Register */
+#define FPU_MVFR0                                          (HWREG32(0xE000EF40)) /* Media and FP Feature Register 0 (MVFR0) */
+#define FPU_MVFR1                                          (HWREG32(0xE000EF44)) /* Media and FP Feature Register 1 (MVFR1) */
+
+/* Register offsets from FPU_BASE address */
+#define OFS_FPU_FPCCR                                      (0x00000F34)          /* Floating Point Context Control Register */
+#define OFS_FPU_FPCAR                                      (0x00000F38)          /* Floating-Point Context Address Register */
+#define OFS_FPU_FPDSCR                                     (0x00000F3C)          /* Floating Point Default Status Control Register */
+#define OFS_FPU_MVFR0                                      (0x00000F40)          /* Media and FP Feature Register 0 (MVFR0) */
+#define OFS_FPU_MVFR1                                      (0x00000F44)          /* Media and FP Feature Register 1 (MVFR1) */
+
+
+//*****************************************************************************
+// ITM Registers
+//*****************************************************************************
+#define ITM_STIM0                                          (HWREG32(0xE0000000)) /* ITM Stimulus Port 0 */
+#define ITM_STIM1                                          (HWREG32(0xE0000004)) /* ITM Stimulus Port 1 */
+#define ITM_STIM2                                          (HWREG32(0xE0000008)) /* ITM Stimulus Port 2 */
+#define ITM_STIM3                                          (HWREG32(0xE000000C)) /* ITM Stimulus Port 3 */
+#define ITM_STIM4                                          (HWREG32(0xE0000010)) /* ITM Stimulus Port 4 */
+#define ITM_STIM5                                          (HWREG32(0xE0000014)) /* ITM Stimulus Port 5 */
+#define ITM_STIM6                                          (HWREG32(0xE0000018)) /* ITM Stimulus Port 6 */
+#define ITM_STIM7                                          (HWREG32(0xE000001C)) /* ITM Stimulus Port 7 */
+#define ITM_STIM8                                          (HWREG32(0xE0000020)) /* ITM Stimulus Port 8 */
+#define ITM_STIM9                                          (HWREG32(0xE0000024)) /* ITM Stimulus Port 9 */
+#define ITM_STIM10                                         (HWREG32(0xE0000028)) /* ITM Stimulus Port 10 */
+#define ITM_STIM11                                         (HWREG32(0xE000002C)) /* ITM Stimulus Port 11 */
+#define ITM_STIM12                                         (HWREG32(0xE0000030)) /* ITM Stimulus Port 12 */
+#define ITM_STIM13                                         (HWREG32(0xE0000034)) /* ITM Stimulus Port 13 */
+#define ITM_STIM14                                         (HWREG32(0xE0000038)) /* ITM Stimulus Port 14 */
+#define ITM_STIM15                                         (HWREG32(0xE000003C)) /* ITM Stimulus Port 15 */
+#define ITM_STIM16                                         (HWREG32(0xE0000040)) /* ITM Stimulus Port 16 */
+#define ITM_STIM17                                         (HWREG32(0xE0000044)) /* ITM Stimulus Port 17 */
+#define ITM_STIM18                                         (HWREG32(0xE0000048)) /* ITM Stimulus Port 18 */
+#define ITM_STIM19                                         (HWREG32(0xE000004C)) /* ITM Stimulus Port 19 */
+#define ITM_STIM20                                         (HWREG32(0xE0000050)) /* ITM Stimulus Port 20 */
+#define ITM_STIM21                                         (HWREG32(0xE0000054)) /* ITM Stimulus Port 21 */
+#define ITM_STIM22                                         (HWREG32(0xE0000058)) /* ITM Stimulus Port 22 */
+#define ITM_STIM23                                         (HWREG32(0xE000005C)) /* ITM Stimulus Port 23 */
+#define ITM_STIM24                                         (HWREG32(0xE0000060)) /* ITM Stimulus Port 24 */
+#define ITM_STIM25                                         (HWREG32(0xE0000064)) /* ITM Stimulus Port 25 */
+#define ITM_STIM26                                         (HWREG32(0xE0000068)) /* ITM Stimulus Port 26 */
+#define ITM_STIM27                                         (HWREG32(0xE000006C)) /* ITM Stimulus Port 27 */
+#define ITM_STIM28                                         (HWREG32(0xE0000070)) /* ITM Stimulus Port 28 */
+#define ITM_STIM29                                         (HWREG32(0xE0000074)) /* ITM Stimulus Port 29 */
+#define ITM_STIM30                                         (HWREG32(0xE0000078)) /* ITM Stimulus Port 30 */
+#define ITM_STIM31                                         (HWREG32(0xE000007C)) /* ITM Stimulus Port 31 */
+#define ITM_TER                                            (HWREG32(0xE0000E00)) /* ITM Trace Enable Register */
+#define ITM_TPR                                            (HWREG32(0xE0000E40)) /* ITM Trace Privilege Register */
+#define ITM_TCR                                            (HWREG32(0xE0000E80)) /* ITM Trace Control Register */
+#define ITM_IWR                                            (HWREG32(0xE0000EF8)) /* ITM Integration Write Register */
+#define ITM_IMCR                                           (HWREG32(0xE0000F00)) /* ITM Integration Mode Control Register */
+#define ITM_LAR                                            (HWREG32(0xE0000FB0)) /* ITM Lock Access Register */
+#define ITM_LSR                                            (HWREG32(0xE0000FB4)) /* ITM Lock Status Register */
+
+/* Register offsets from ITM_BASE address */
+#define OFS_ITM_STIM0                                      (0x00000000)          /* ITM Stimulus Port 0 */
+#define OFS_ITM_STIM1                                      (0x00000004)          /* ITM Stimulus Port 1 */
+#define OFS_ITM_STIM2                                      (0x00000008)          /* ITM Stimulus Port 2 */
+#define OFS_ITM_STIM3                                      (0x0000000C)          /* ITM Stimulus Port 3 */
+#define OFS_ITM_STIM4                                      (0x00000010)          /* ITM Stimulus Port 4 */
+#define OFS_ITM_STIM5                                      (0x00000014)          /* ITM Stimulus Port 5 */
+#define OFS_ITM_STIM6                                      (0x00000018)          /* ITM Stimulus Port 6 */
+#define OFS_ITM_STIM7                                      (0x0000001C)          /* ITM Stimulus Port 7 */
+#define OFS_ITM_STIM8                                      (0x00000020)          /* ITM Stimulus Port 8 */
+#define OFS_ITM_STIM9                                      (0x00000024)          /* ITM Stimulus Port 9 */
+#define OFS_ITM_STIM10                                     (0x00000028)          /* ITM Stimulus Port 10 */
+#define OFS_ITM_STIM11                                     (0x0000002C)          /* ITM Stimulus Port 11 */
+#define OFS_ITM_STIM12                                     (0x00000030)          /* ITM Stimulus Port 12 */
+#define OFS_ITM_STIM13                                     (0x00000034)          /* ITM Stimulus Port 13 */
+#define OFS_ITM_STIM14                                     (0x00000038)          /* ITM Stimulus Port 14 */
+#define OFS_ITM_STIM15                                     (0x0000003C)          /* ITM Stimulus Port 15 */
+#define OFS_ITM_STIM16                                     (0x00000040)          /* ITM Stimulus Port 16 */
+#define OFS_ITM_STIM17                                     (0x00000044)          /* ITM Stimulus Port 17 */
+#define OFS_ITM_STIM18                                     (0x00000048)          /* ITM Stimulus Port 18 */
+#define OFS_ITM_STIM19                                     (0x0000004C)          /* ITM Stimulus Port 19 */
+#define OFS_ITM_STIM20                                     (0x00000050)          /* ITM Stimulus Port 20 */
+#define OFS_ITM_STIM21                                     (0x00000054)          /* ITM Stimulus Port 21 */
+#define OFS_ITM_STIM22                                     (0x00000058)          /* ITM Stimulus Port 22 */
+#define OFS_ITM_STIM23                                     (0x0000005C)          /* ITM Stimulus Port 23 */
+#define OFS_ITM_STIM24                                     (0x00000060)          /* ITM Stimulus Port 24 */
+#define OFS_ITM_STIM25                                     (0x00000064)          /* ITM Stimulus Port 25 */
+#define OFS_ITM_STIM26                                     (0x00000068)          /* ITM Stimulus Port 26 */
+#define OFS_ITM_STIM27                                     (0x0000006C)          /* ITM Stimulus Port 27 */
+#define OFS_ITM_STIM28                                     (0x00000070)          /* ITM Stimulus Port 28 */
+#define OFS_ITM_STIM29                                     (0x00000074)          /* ITM Stimulus Port 29 */
+#define OFS_ITM_STIM30                                     (0x00000078)          /* ITM Stimulus Port 30 */
+#define OFS_ITM_STIM31                                     (0x0000007C)          /* ITM Stimulus Port 31 */
+#define OFS_ITM_TER                                        (0x00000E00)          /* ITM Trace Enable Register */
+#define OFS_ITM_TPR                                        (0x00000E40)          /* ITM Trace Privilege Register */
+#define OFS_ITM_TCR                                        (0x00000E80)          /* ITM Trace Control Register */
+#define OFS_ITM_IWR                                        (0x00000EF8)          /* ITM Integration Write Register */
+#define OFS_ITM_IMCR                                       (0x00000F00)          /* ITM Integration Mode Control Register */
+#define OFS_ITM_LAR                                        (0x00000FB0)          /* ITM Lock Access Register */
+#define OFS_ITM_LSR                                        (0x00000FB4)          /* ITM Lock Status Register */
+
+
+//*****************************************************************************
+// MPU Registers
+//*****************************************************************************
+#define MPU_TYPE                                           (HWREG32(0xE000ED90)) /* MPU Type Register */
+#define MPU_CTRL                                           (HWREG32(0xE000ED94)) /* MPU Control Register */
+#define MPU_RNR                                            (HWREG32(0xE000ED98)) /* MPU Region Number Register */
+#define MPU_RBAR                                           (HWREG32(0xE000ED9C)) /* MPU Region Base Address Register */
+#define MPU_RASR                                           (HWREG32(0xE000EDA0)) /* MPU Region Attribute and Size Register */
+#define MPU_RBAR_A1                                        (HWREG32(0xE000EDA4)) /* MPU Alias 1 Region Base Address register */
+#define MPU_RASR_A1                                        (HWREG32(0xE000EDA8)) /* MPU Alias 1 Region Attribute and Size register */
+#define MPU_RBAR_A2                                        (HWREG32(0xE000EDAC)) /* MPU Alias 2 Region Base Address register */
+#define MPU_RASR_A2                                        (HWREG32(0xE000EDB0)) /* MPU Alias 2 Region Attribute and Size register */
+#define MPU_RBAR_A3                                        (HWREG32(0xE000EDB4)) /* MPU Alias 3 Region Base Address register */
+#define MPU_RASR_A3                                        (HWREG32(0xE000EDB8)) /* MPU Alias 3 Region Attribute and Size register */
+
+/* Register offsets from MPU_BASE address */
+#define OFS_MPU_TYPE                                       (0x00000D90)          /* MPU Type Register */
+#define OFS_MPU_CTRL                                       (0x00000D94)          /* MPU Control Register */
+#define OFS_MPU_RNR                                        (0x00000D98)          /* MPU Region Number Register */
+#define OFS_MPU_RBAR                                       (0x00000D9C)          /* MPU Region Base Address Register */
+#define OFS_MPU_RASR                                       (0x00000DA0)          /* MPU Region Attribute and Size Register */
+#define OFS_MPU_RBAR_A1                                    (0x00000DA4)          /* MPU Alias 1 Region Base Address register */
+#define OFS_MPU_RASR_A1                                    (0x00000DA8)          /* MPU Alias 1 Region Attribute and Size register */
+#define OFS_MPU_RBAR_A2                                    (0x00000DAC)          /* MPU Alias 2 Region Base Address register */
+#define OFS_MPU_RASR_A2                                    (0x00000DB0)          /* MPU Alias 2 Region Attribute and Size register */
+#define OFS_MPU_RBAR_A3                                    (0x00000DB4)          /* MPU Alias 3 Region Base Address register */
+#define OFS_MPU_RASR_A3                                    (0x00000DB8)          /* MPU Alias 3 Region Attribute and Size register */
+
+
+//*****************************************************************************
+// NVIC Registers
+//*****************************************************************************
+#define NVIC_ISER0                                         (HWREG32(0xE000E100)) /* Irq 0 to 31 Set Enable Register */
+#define NVIC_ISER1                                         (HWREG32(0xE000E104)) /* Irq 32 to 63 Set Enable Register */
+#define NVIC_ICER0                                         (HWREG32(0xE000E180)) /* Irq 0 to 31 Clear Enable Register */
+#define NVIC_ICER1                                         (HWREG32(0xE000E184)) /* Irq 32 to 63 Clear Enable Register */
+#define NVIC_ISPR0                                         (HWREG32(0xE000E200)) /* Irq 0 to 31 Set Pending Register */
+#define NVIC_ISPR1                                         (HWREG32(0xE000E204)) /* Irq 32 to 63 Set Pending Register */
+#define NVIC_ICPR0                                         (HWREG32(0xE000E280)) /* Irq 0 to 31 Clear Pending Register */
+#define NVIC_ICPR1                                         (HWREG32(0xE000E284)) /* Irq 32 to 63 Clear Pending Register */
+#define NVIC_IABR0                                         (HWREG32(0xE000E300)) /* Irq 0 to 31 Active Bit Register */
+#define NVIC_IABR1                                         (HWREG32(0xE000E304)) /* Irq 32 to 63 Active Bit Register */
+#define NVIC_IPR0                                          (HWREG32(0xE000E400)) /* Irq 0 to 3 Priority Register */
+#define NVIC_IPR1                                          (HWREG32(0xE000E404)) /* Irq 4 to 7 Priority Register */
+#define NVIC_IPR2                                          (HWREG32(0xE000E408)) /* Irq 8 to 11 Priority Register */
+#define NVIC_IPR3                                          (HWREG32(0xE000E40C)) /* Irq 12 to 15 Priority Register */
+#define NVIC_IPR4                                          (HWREG32(0xE000E410)) /* Irq 16 to 19 Priority Register */
+#define NVIC_IPR5                                          (HWREG32(0xE000E414)) /* Irq 20 to 23 Priority Register */
+#define NVIC_IPR6                                          (HWREG32(0xE000E418)) /* Irq 24 to 27 Priority Register */
+#define NVIC_IPR7                                          (HWREG32(0xE000E41C)) /* Irq 28 to 31 Priority Register */
+#define NVIC_IPR8                                          (HWREG32(0xE000E420)) /* Irq 32 to 35 Priority Register */
+#define NVIC_IPR9                                          (HWREG32(0xE000E424)) /* Irq 36 to 39 Priority Register */
+#define NVIC_IPR10                                         (HWREG32(0xE000E428)) /* Irq 40 to 43 Priority Register */
+#define NVIC_IPR11                                         (HWREG32(0xE000E42C)) /* Irq 44 to 47 Priority Register */
+#define NVIC_IPR12                                         (HWREG32(0xE000E430)) /* Irq 48 to 51 Priority Register */
+#define NVIC_IPR13                                         (HWREG32(0xE000E434)) /* Irq 52 to 55 Priority Register */
+#define NVIC_IPR14                                         (HWREG32(0xE000E438)) /* Irq 56 to 59 Priority Register */
+#define NVIC_IPR15                                         (HWREG32(0xE000E43C)) /* Irq 60 to 63 Priority Register */
+#define NVIC_STIR                                          (HWREG32(0xE000EF00)) /* Software Trigger Interrupt Register */
+
+/* Register offsets from NVIC_BASE address */
+#define OFS_NVIC_ISER0                                     (0x00000100)          /* Irq 0 to 31 Set Enable Register */
+#define OFS_NVIC_ISER1                                     (0x00000104)          /* Irq 32 to 63 Set Enable Register */
+#define OFS_NVIC_ICER0                                     (0x00000180)          /* Irq 0 to 31 Clear Enable Register */
+#define OFS_NVIC_ICER1                                     (0x00000184)          /* Irq 32 to 63 Clear Enable Register */
+#define OFS_NVIC_ISPR0                                     (0x00000200)          /* Irq 0 to 31 Set Pending Register */
+#define OFS_NVIC_ISPR1                                     (0x00000204)          /* Irq 32 to 63 Set Pending Register */
+#define OFS_NVIC_ICPR0                                     (0x00000280)          /* Irq 0 to 31 Clear Pending Register */
+#define OFS_NVIC_ICPR1                                     (0x00000284)          /* Irq 32 to 63 Clear Pending Register */
+#define OFS_NVIC_IABR0                                     (0x00000300)          /* Irq 0 to 31 Active Bit Register */
+#define OFS_NVIC_IABR1                                     (0x00000304)          /* Irq 32 to 63 Active Bit Register */
+#define OFS_NVIC_IPR0                                      (0x00000400)          /* Irq 0 to 3 Priority Register */
+#define OFS_NVIC_IPR1                                      (0x00000404)          /* Irq 4 to 7 Priority Register */
+#define OFS_NVIC_IPR2                                      (0x00000408)          /* Irq 8 to 11 Priority Register */
+#define OFS_NVIC_IPR3                                      (0x0000040C)          /* Irq 12 to 15 Priority Register */
+#define OFS_NVIC_IPR4                                      (0x00000410)          /* Irq 16 to 19 Priority Register */
+#define OFS_NVIC_IPR5                                      (0x00000414)          /* Irq 20 to 23 Priority Register */
+#define OFS_NVIC_IPR6                                      (0x00000418)          /* Irq 24 to 27 Priority Register */
+#define OFS_NVIC_IPR7                                      (0x0000041C)          /* Irq 28 to 31 Priority Register */
+#define OFS_NVIC_IPR8                                      (0x00000420)          /* Irq 32 to 35 Priority Register */
+#define OFS_NVIC_IPR9                                      (0x00000424)          /* Irq 36 to 39 Priority Register */
+#define OFS_NVIC_IPR10                                     (0x00000428)          /* Irq 40 to 43 Priority Register */
+#define OFS_NVIC_IPR11                                     (0x0000042C)          /* Irq 44 to 47 Priority Register */
+#define OFS_NVIC_IPR12                                     (0x00000430)          /* Irq 48 to 51 Priority Register */
+#define OFS_NVIC_IPR13                                     (0x00000434)          /* Irq 52 to 55 Priority Register */
+#define OFS_NVIC_IPR14                                     (0x00000438)          /* Irq 56 to 59 Priority Register */
+#define OFS_NVIC_IPR15                                     (0x0000043C)          /* Irq 60 to 63 Priority Register */
+#define OFS_NVIC_STIR                                      (0x00000F00)          /* Software Trigger Interrupt Register */
+
+
+//*****************************************************************************
+// PCM Registers
+//*****************************************************************************
+#define PCMCTL0                                            (HWREG32(0x40010000)) /* Control 0 Register */
+#define PCMCTL1                                            (HWREG32(0x40010004)) /* Control 1 Register */
+#define PCMIE                                              (HWREG32(0x40010008)) /* Interrupt Enable Register */
+#define PCMIFG                                             (HWREG32(0x4001000C)) /* Interrupt Flag Register */
+#define PCMCLRIFG                                          (HWREG32(0x40010010)) /* Clear Interrupt Flag Register */
+
+/* Register offsets from PCM_BASE address */
+#define OFS_PCMCTL0                                        (0x00000000)          /* Control 0 Register */
+#define OFS_PCMCTL1                                        (0x00000004)          /* Control 1 Register */
+#define OFS_PCMIE                                          (0x00000008)          /* Interrupt Enable Register */
+#define OFS_PCMIFG                                         (0x0000000c)          /* Interrupt Flag Register */
+#define OFS_PCMCLRIFG                                      (0x00000010)          /* Clear Interrupt Flag Register */
+
+
+//*****************************************************************************
+// PMAP Registers
+//*****************************************************************************
+#define PMAPKEYID                                          (HWREG16(0x40005000)) /* Port Mapping Key Register */
+#define PMAPCTL                                            (HWREG16(0x40005002)) /* Port Mapping Control Register */
+#define P1MAP01                                            (HWREG16(0x40005008)) /* Port mapping register, P1.0 and P1.1 */
+#define P1MAP23                                            (HWREG16(0x4000500A)) /* Port mapping register, P1.2 and P1.3 */
+#define P1MAP45                                            (HWREG16(0x4000500C)) /* Port mapping register, P1.4 and P1.5 */
+#define P1MAP67                                            (HWREG16(0x4000500E)) /* Port mapping register, P1.6 and P1.7 */
+#define P2MAP01                                            (HWREG16(0x40005010)) /* Port mapping register, P2.0 and P2.1 */
+#define P2MAP23                                            (HWREG16(0x40005012)) /* Port mapping register, P2.2 and P2.3 */
+#define P2MAP45                                            (HWREG16(0x40005014)) /* Port mapping register, P2.4 and P2.5 */
+#define P2MAP67                                            (HWREG16(0x40005016)) /* Port mapping register, P2.6 and P2.7 */
+#define P3MAP01                                            (HWREG16(0x40005018)) /* Port mapping register, P3.0 and P3.1 */
+#define P3MAP23                                            (HWREG16(0x4000501A)) /* Port mapping register, P3.2 and P3.3 */
+#define P3MAP45                                            (HWREG16(0x4000501C)) /* Port mapping register, P3.4 and P3.5 */
+#define P3MAP67                                            (HWREG16(0x4000501E)) /* Port mapping register, P3.6 and P3.7 */
+#define P4MAP01                                            (HWREG16(0x40005020)) /* Port mapping register, P4.0 and P4.1 */
+#define P4MAP23                                            (HWREG16(0x40005022)) /* Port mapping register, P4.2 and P4.3 */
+#define P4MAP45                                            (HWREG16(0x40005024)) /* Port mapping register, P4.4 and P4.5 */
+#define P4MAP67                                            (HWREG16(0x40005026)) /* Port mapping register, P4.6 and P4.7 */
+#define P5MAP01                                            (HWREG16(0x40005028)) /* Port mapping register, P5.0 and P5.1 */
+#define P5MAP23                                            (HWREG16(0x4000502A)) /* Port mapping register, P5.2 and P5.3 */
+#define P5MAP45                                            (HWREG16(0x4000502C)) /* Port mapping register, P5.4 and P5.5 */
+#define P5MAP67                                            (HWREG16(0x4000502E)) /* Port mapping register, P5.6 and P5.7 */
+#define P6MAP01                                            (HWREG16(0x40005030)) /* Port mapping register, P6.0 and P6.1 */
+#define P6MAP23                                            (HWREG16(0x40005032)) /* Port mapping register, P6.2 and P6.3 */
+#define P6MAP45                                            (HWREG16(0x40005034)) /* Port mapping register, P6.4 and P6.5 */
+#define P6MAP67                                            (HWREG16(0x40005036)) /* Port mapping register, P6.6 and P6.7 */
+#define P7MAP01                                            (HWREG16(0x40005038)) /* Port mapping register, P7.0 and P7.1 */
+#define P7MAP23                                            (HWREG16(0x4000503A)) /* Port mapping register, P7.2 and P7.3 */
+#define P7MAP45                                            (HWREG16(0x4000503C)) /* Port mapping register, P7.4 and P7.5 */
+#define P7MAP67                                            (HWREG16(0x4000503E)) /* Port mapping register, P7.6 and P7.7 */
+
+/* Register offsets from PMAP_BASE address */
+#define OFS_PMAPKEYID                                      (0x0000)              /* Port Mapping Key Register */
+#define OFS_PMAPCTL                                        (0x0002)              /* Port Mapping Control Register */
+#define OFS_P1MAP01                                        (0x0008)              /* Port mapping register, P1.0 and P1.1 */
+#define OFS_P1MAP23                                        (0x000a)              /* Port mapping register, P1.2 and P1.3 */
+#define OFS_P1MAP45                                        (0x000c)              /* Port mapping register, P1.4 and P1.5 */
+#define OFS_P1MAP67                                        (0x000e)              /* Port mapping register, P1.6 and P1.7 */
+#define OFS_P2MAP01                                        (0x0010)              /* Port mapping register, P2.0 and P2.1 */
+#define OFS_P2MAP23                                        (0x0012)              /* Port mapping register, P2.2 and P2.3 */
+#define OFS_P2MAP45                                        (0x0014)              /* Port mapping register, P2.4 and P2.5 */
+#define OFS_P2MAP67                                        (0x0016)              /* Port mapping register, P2.6 and P2.7 */
+#define OFS_P3MAP01                                        (0x0018)              /* Port mapping register, P3.0 and P3.1 */
+#define OFS_P3MAP23                                        (0x001a)              /* Port mapping register, P3.2 and P3.3 */
+#define OFS_P3MAP45                                        (0x001c)              /* Port mapping register, P3.4 and P3.5 */
+#define OFS_P3MAP67                                        (0x001e)              /* Port mapping register, P3.6 and P3.7 */
+#define OFS_P4MAP01                                        (0x0020)              /* Port mapping register, P4.0 and P4.1 */
+#define OFS_P4MAP23                                        (0x0022)              /* Port mapping register, P4.2 and P4.3 */
+#define OFS_P4MAP45                                        (0x0024)              /* Port mapping register, P4.4 and P4.5 */
+#define OFS_P4MAP67                                        (0x0026)              /* Port mapping register, P4.6 and P4.7 */
+#define OFS_P5MAP01                                        (0x0028)              /* Port mapping register, P5.0 and P5.1 */
+#define OFS_P5MAP23                                        (0x002a)              /* Port mapping register, P5.2 and P5.3 */
+#define OFS_P5MAP45                                        (0x002c)              /* Port mapping register, P5.4 and P5.5 */
+#define OFS_P5MAP67                                        (0x002e)              /* Port mapping register, P5.6 and P5.7 */
+#define OFS_P6MAP01                                        (0x0030)              /* Port mapping register, P6.0 and P6.1 */
+#define OFS_P6MAP23                                        (0x0032)              /* Port mapping register, P6.2 and P6.3 */
+#define OFS_P6MAP45                                        (0x0034)              /* Port mapping register, P6.4 and P6.5 */
+#define OFS_P6MAP67                                        (0x0036)              /* Port mapping register, P6.6 and P6.7 */
+#define OFS_P7MAP01                                        (0x0038)              /* Port mapping register, P7.0 and P7.1 */
+#define OFS_P7MAP23                                        (0x003a)              /* Port mapping register, P7.2 and P7.3 */
+#define OFS_P7MAP45                                        (0x003c)              /* Port mapping register, P7.4 and P7.5 */
+#define OFS_P7MAP67                                        (0x003e)              /* Port mapping register, P7.6 and P7.7 */
+
+
+//*****************************************************************************
+// PSS Registers
+//*****************************************************************************
+#define PSSKEY                                             (HWREG32(0x40010800)) /* Key Register */
+#define PSSCTL0                                            (HWREG32(0x40010804)) /* Control 0 Register */
+#define PSSIE                                              (HWREG32(0x40010834)) /* Interrupt Enable Register */
+#define PSSIFG                                             (HWREG32(0x40010838)) /* Interrupt Flag Register */
+#define PSSCLRIFG                                          (HWREG32(0x4001083C)) /* Clear Interrupt Flag Register */
+
+/* Register offsets from PSS_BASE address */
+#define OFS_PSSKEY                                         (0x00000000)          /* Key Register */
+#define OFS_PSSCTL0                                        (0x00000004)          /* Control 0 Register */
+#define OFS_PSSIE                                          (0x00000034)          /* Interrupt Enable Register */
+#define OFS_PSSIFG                                         (0x00000038)          /* Interrupt Flag Register */
+#define OFS_PSSCLRIFG                                      (0x0000003c)          /* Clear Interrupt Flag Register */
+
+
+//*****************************************************************************
+// REF_A Registers
+//*****************************************************************************
+#define REFCTL0                                            (HWREG16(0x40003000)) /* REF Control Register 0 */
+
+/* Register offsets from REF_A_BASE address */
+#define OFS_REFCTL0                                        (0x0000)              /* REF Control Register 0 */
+
+#define REFCTL0_L                                          (HWREG8_L(REFCTL0))   /* REF Control Register 0 */
+#define REFCTL0_H                                          (HWREG8_H(REFCTL0))   /* REF Control Register 0 */
+
+//*****************************************************************************
+// RSTCTL Registers
+//*****************************************************************************
+#define RSTCTL_RESET_REQ                                   (HWREG32(0xE0042000)) /* Reset Request Register */
+#define RSTCTL_HARDRESET_CLR                               (HWREG32(0xE0042008)) /* Hard Reset Status Clear Register */
+#define RSTCTL_HARDRESET_SET                               (HWREG32(0xE004200C)) /* Hard Reset Status Set Register */
+#define RSTCTL_SOFTRESET_STAT                              (HWREG32(0xE0042010)) /* Soft Reset Status Register */
+#define RSTCTL_SOFTRESET_CLR                               (HWREG32(0xE0042014)) /* Soft Reset Status Clear Register */
+#define RSTCTL_SOFTRESET_SET                               (HWREG32(0xE0042018)) /* Soft Reset Status Set Register */
+#define RSTCTL_PSSRESET_STAT                               (HWREG32(0xE0042100)) /* PSS Reset Status Register */
+#define RSTCTL_PSSRESET_CLR                                (HWREG32(0xE0042104)) /* PSS Reset Status Clear Register */
+#define RSTCTL_PCMRESET_STAT                               (HWREG32(0xE0042108)) /* PCM Reset Status Register */
+#define RSTCTL_PCMRESET_CLR                                (HWREG32(0xE004210C)) /* PCM Reset Status Clear Register */
+#define RSTCTL_PINRESET_STAT                               (HWREG32(0xE0042110)) /* Pin Reset Status Register */
+#define RSTCTL_PINRESET_CLR                                (HWREG32(0xE0042114)) /* Pin Reset Status Clear Register */
+#define RSTCTL_REBOOTRESET_STAT                            (HWREG32(0xE0042118)) /* Reboot Reset Status Register */
+#define RSTCTL_REBOOTRESET_CLR                             (HWREG32(0xE004211C)) /* Reboot Reset Status Clear Register */
+
+/* Register offsets from RSTCTL_BASE address */
+#define OFS_RSTCTL_RESET_REQ                               (0x00000000)          /* Reset Request Register */
+#define OFS_RSTCTL_HARDRESET_CLR                           (0x00000008)          /* Hard Reset Status Clear Register */
+#define OFS_RSTCTL_HARDRESET_SET                           (0x0000000c)          /* Hard Reset Status Set Register */
+#define OFS_RSTCTL_SOFTRESET_STAT                          (0x00000010)          /* Soft Reset Status Register */
+#define OFS_RSTCTL_SOFTRESET_CLR                           (0x00000014)          /* Soft Reset Status Clear Register */
+#define OFS_RSTCTL_SOFTRESET_SET                           (0x00000018)          /* Soft Reset Status Set Register */
+#define OFS_RSTCTL_PSSRESET_STAT                           (0x00000100)          /* PSS Reset Status Register */
+#define OFS_RSTCTL_PSSRESET_CLR                            (0x00000104)          /* PSS Reset Status Clear Register */
+#define OFS_RSTCTL_PCMRESET_STAT                           (0x00000108)          /* PCM Reset Status Register */
+#define OFS_RSTCTL_PCMRESET_CLR                            (0x0000010c)          /* PCM Reset Status Clear Register */
+#define OFS_RSTCTL_PINRESET_STAT                           (0x00000110)          /* Pin Reset Status Register */
+#define OFS_RSTCTL_PINRESET_CLR                            (0x00000114)          /* Pin Reset Status Clear Register */
+#define OFS_RSTCTL_REBOOTRESET_STAT                        (0x00000118)          /* Reboot Reset Status Register */
+#define OFS_RSTCTL_REBOOTRESET_CLR                         (0x0000011c)          /* Reboot Reset Status Clear Register */
+
+
+//*****************************************************************************
+// RTC_C Registers
+//*****************************************************************************
+#define RTCCTL0                                            (HWREG16(0x40004400)) /* RTCCTL0 Register */
+#define RTCCTL13                                           (HWREG16(0x40004402)) /* RTCCTL13 Register */
+#define RTCOCAL                                            (HWREG16(0x40004404)) /* RTCOCAL Register */
+#define RTCTCMP                                            (HWREG16(0x40004406)) /* RTCTCMP Register */
+#define RTCPS0CTL                                          (HWREG16(0x40004408)) /* Real-Time Clock Prescale Timer 0 Control Register */
+#define RTCPS1CTL                                          (HWREG16(0x4000440A)) /* Real-Time Clock Prescale Timer 1 Control Register */
+#define RTCPS                                              (HWREG16(0x4000440C)) /* Real-Time Clock Prescale Timer Counter Register */
+#define RTCIV                                              (HWREG16(0x4000440E)) /* Real-Time Clock Interrupt Vector Register */
+#define RTCTIM0                                            (HWREG16(0x40004410)) /* RTCTIM0 Register ? Hexadecimal Format */
+#define RTCTIM0_BCD                                        (HWREG16(0x40004410)) /*  */
+#define RTCTIM1                                            (HWREG16(0x40004412)) /* Real-Time Clock Hour, Day of Week */
+#define RTCTIM1_BCD                                        (HWREG16(0x40004412)) /*  */
+#define RTCDATE                                            (HWREG16(0x40004414)) /* RTCDATE - Hexadecimal Format */
+#define RTCDATE_BCD                                        (HWREG16(0x40004414)) /*  */
+#define RTCYEAR                                            (HWREG16(0x40004416)) /* RTCYEAR Register ? Hexadecimal Format */
+#define RTCYEAR_BCD                                        (HWREG16(0x40004416)) /*  */
+#define RTCAMINHR                                          (HWREG16(0x40004418)) /* RTCMINHR - Hexadecimal Format */
+#define RTCAMINHR_BCD                                      (HWREG16(0x40004418)) /*  */
+#define RTCADOWDAY                                         (HWREG16(0x4000441A)) /* RTCADOWDAY - Hexadecimal Format */
+#define RTCADOWDAY_BCD                                     (HWREG16(0x4000441A)) /*  */
+#define RTCBIN2BCD                                         (HWREG16(0x4000441C)) /* Binary-to-BCD Conversion Register */
+#define RTCBCD2BIN                                         (HWREG16(0x4000441E)) /* BCD-to-Binary Conversion Register */
+
+/* Register offsets from RTC_C_BASE address */
+#define OFS_RTCCTL0                                        (0x0000)              /* RTCCTL0 Register */
+#define OFS_RTCCTL13                                       (0x0002)              /* RTCCTL13 Register */
+#define OFS_RTCOCAL                                        (0x0004)              /* RTCOCAL Register */
+#define OFS_RTCTCMP                                        (0x0006)              /* RTCTCMP Register */
+#define OFS_RTCPS0CTL                                      (0x0008)              /* Real-Time Clock Prescale Timer 0 Control Register */
+#define OFS_RTCPS1CTL                                      (0x000a)              /* Real-Time Clock Prescale Timer 1 Control Register */
+#define OFS_RTCPS                                          (0x000c)              /* Real-Time Clock Prescale Timer Counter Register */
+#define OFS_RTCIV                                          (0x000e)              /* Real-Time Clock Interrupt Vector Register */
+#define OFS_RTCTIM0                                        (0x0010)              /* RTCTIM0 Register ? Hexadecimal Format */
+#define OFS_RTCTIM0_BCD                                    (0x0010)              /*  */
+#define OFS_RTCTIM1                                        (0x0012)              /* Real-Time Clock Hour, Day of Week */
+#define OFS_RTCTIM1_BCD                                    (0x0012)              /*  */
+#define OFS_RTCDATE                                        (0x0014)              /* RTCDATE - Hexadecimal Format */
+#define OFS_RTCDATE_BCD                                    (0x0014)              /*  */
+#define OFS_RTCYEAR                                        (0x0016)              /* RTCYEAR Register ? Hexadecimal Format */
+#define OFS_RTCYEAR_BCD                                    (0x0016)              /*  */
+#define OFS_RTCAMINHR                                      (0x0018)              /* RTCMINHR - Hexadecimal Format */
+#define OFS_RTCAMINHR_BCD                                  (0x0018)              /*  */
+#define OFS_RTCADOWDAY                                     (0x001a)              /* RTCADOWDAY - Hexadecimal Format */
+#define OFS_RTCADOWDAY_BCD                                 (0x001a)              /*  */
+#define OFS_RTCBIN2BCD                                     (0x001c)              /* Binary-to-BCD Conversion Register */
+#define OFS_RTCBCD2BIN                                     (0x001e)              /* BCD-to-Binary Conversion Register */
+
+#define RTCCTL0_L                                          (HWREG8_L(RTCCTL0))   /* RTCCTL0 Register */
+#define RTCCTL0_H                                          (HWREG8_H(RTCCTL0))   /* RTCCTL0 Register */
+#define RTCCTL1                                            (HWREG8_L(RTCCTL13))  /* RTCCTL13 Register */
+#define RTCCTL13_L                                         (HWREG8_L(RTCCTL13))  /* RTCCTL13 Register */
+#define RTCCTL3                                            (HWREG8_H(RTCCTL13))  /* RTCCTL13 Register */
+#define RTCCTL13_H                                         (HWREG8_H(RTCCTL13))  /* RTCCTL13 Register */
+#define RTCOCAL_L                                          (HWREG8_L(RTCOCAL))   /* RTCOCAL Register */
+#define RTCOCAL_H                                          (HWREG8_H(RTCOCAL))   /* RTCOCAL Register */
+#define RTCTCMP_L                                          (HWREG8_L(RTCTCMP))   /* RTCTCMP Register */
+#define RTCTCMP_H                                          (HWREG8_H(RTCTCMP))   /* RTCTCMP Register */
+#define RTCPS0CTL_L                                        (HWREG8_L(RTCPS0CTL)) /* Real-Time Clock Prescale Timer 0 Control Register */
+#define RTCPS0CTL_H                                        (HWREG8_H(RTCPS0CTL)) /* Real-Time Clock Prescale Timer 0 Control Register */
+#define RTCPS1CTL_L                                        (HWREG8_L(RTCPS1CTL)) /* Real-Time Clock Prescale Timer 1 Control Register */
+#define RTCPS1CTL_H                                        (HWREG8_H(RTCPS1CTL)) /* Real-Time Clock Prescale Timer 1 Control Register */
+#define RTCPS0                                             (HWREG8_L(RTCPS))     /* Real-Time Clock Prescale Timer Counter Register */
+#define RTCPS_L                                            (HWREG8_L(RTCPS))     /* Real-Time Clock Prescale Timer Counter Register */
+#define RTCPS1                                             (HWREG8_H(RTCPS))     /* Real-Time Clock Prescale Timer Counter Register */
+#define RTCPS_H                                            (HWREG8_H(RTCPS))     /* Real-Time Clock Prescale Timer Counter Register */
+#define RTCSEC                                             (HWREG8_L(RTCTIM0))   /* Real-Time Clock Seconds */
+#define RTCTIM0_L                                          (HWREG8_L(RTCTIM0))   /* Real-Time Clock Seconds */
+#define RTCMIN                                             (HWREG8_H(RTCTIM0))   /* Real-Time Clock Minutes */
+#define RTCTIM0_H                                          (HWREG8_H(RTCTIM0))   /* Real-Time Clock Minutes */
+#define RTCHOUR                                            (HWREG8_L(RTCTIM1))   /* Real-Time Clock Hour */
+#define RTCTIM1_L                                          (HWREG8_L(RTCTIM1))   /* Real-Time Clock Hour */
+#define RTCDOW                                             (HWREG8_H(RTCTIM1))   /* Real-Time Clock Day of Week */
+#define RTCTIM1_H                                          (HWREG8_H(RTCTIM1))   /* Real-Time Clock Day of Week */
+#define RTCDAY                                             (HWREG8_L(RTCDATE))   /* Real-Time Clock Day of Month */
+#define RTCDATE_L                                          (HWREG8_L(RTCDATE))   /* Real-Time Clock Day of Month */
+#define RTCMON                                             (HWREG8_H(RTCDATE))   /* Real-Time Clock Month */
+#define RTCDATE_H                                          (HWREG8_H(RTCDATE))   /* Real-Time Clock Month */
+#define RTCAMIN                                            (HWREG8_L(RTCAMINHR)) /* Real-Time Clock Minutes Alarm */
+#define RTCAMINHR_L                                        (HWREG8_L(RTCAMINHR)) /* Real-Time Clock Minutes Alarm */
+#define RTCAHOUR                                           (HWREG8_H(RTCAMINHR)) /* Real-Time Clock Hours Alarm */
+#define RTCAMINHR_H                                        (HWREG8_H(RTCAMINHR)) /* Real-Time Clock Hours Alarm */
+#define RTCADOW                                            (HWREG8_L(RTCADOWDAY))/* Real-Time Clock Day of Week Alarm */
+#define RTCADOWDAY_L                                       (HWREG8_L(RTCADOWDAY))/* Real-Time Clock Day of Week Alarm */
+#define RTCADAY                                            (HWREG8_H(RTCADOWDAY))/* Real-Time Clock Day of Month Alarm */
+#define RTCADOWDAY_H                                       (HWREG8_H(RTCADOWDAY))/* Real-Time Clock Day of Month Alarm */
+
+//*****************************************************************************
+// SCB Registers
+//*****************************************************************************
+#define SCB_CPUID                                          (HWREG32(0xE000ED00)) /* CPUID Base Register */
+#define SCB_ICSR                                           (HWREG32(0xE000ED04)) /* Interrupt Control State Register */
+#define SCB_VTOR                                           (HWREG32(0xE000ED08)) /* Vector Table Offset Register */
+#define SCB_AIRCR                                          (HWREG32(0xE000ED0C)) /* Application Interrupt/Reset Control Register */
+#define SCB_SCR                                            (HWREG32(0xE000ED10)) /* System Control Register */
+#define SCB_CCR                                            (HWREG32(0xE000ED14)) /* Configuration Control Register */
+#define SCB_SHPR1                                          (HWREG32(0xE000ED18)) /* System Handlers 4-7 Priority Register */
+#define SCB_SHPR2                                          (HWREG32(0xE000ED1C)) /* System Handlers 8-11 Priority Register */
+#define SCB_SHPR3                                          (HWREG32(0xE000ED20)) /* System Handlers 12-15 Priority Register */
+#define SCB_SHCSR                                          (HWREG32(0xE000ED24)) /* System Handler Control and State Register */
+#define SCB_CFSR                                           (HWREG32(0xE000ED28)) /* Configurable Fault Status Registers */
+#define SCB_HFSR                                           (HWREG32(0xE000ED2C)) /* Hard Fault Status Register */
+#define SCB_DFSR                                           (HWREG32(0xE000ED30)) /* Debug Fault Status Register */
+#define SCB_MMFAR                                          (HWREG32(0xE000ED34)) /* Mem Manage Fault Address Register */
+#define SCB_BFAR                                           (HWREG32(0xE000ED38)) /* Bus Fault Address Register */
+#define SCB_AFSR                                           (HWREG32(0xE000ED3C)) /* Auxiliary Fault Status Register */
+#define SCB_PFR0                                           (HWREG32(0xE000ED40)) /* Processor Feature register0 */
+#define SCB_PFR1                                           (HWREG32(0xE000ED44)) /* Processor Feature register1 */
+#define SCB_DFR0                                           (HWREG32(0xE000ED48)) /* Debug Feature register0 */
+#define SCB_AFR0                                           (HWREG32(0xE000ED4C)) /* Auxiliary Feature register0 */
+#define SCB_MMFR0                                          (HWREG32(0xE000ED50)) /* Memory Model Feature register0 */
+#define SCB_MMFR1                                          (HWREG32(0xE000ED54)) /* Memory Model Feature register1 */
+#define SCB_MMFR2                                          (HWREG32(0xE000ED58)) /* Memory Model Feature register2 */
+#define SCB_MMFR3                                          (HWREG32(0xE000ED5C)) /* Memory Model Feature register3 */
+#define SCB_ISAR0                                          (HWREG32(0xE000ED60)) /* ISA Feature register0 */
+#define SCB_ISAR1                                          (HWREG32(0xE000ED64)) /* ISA Feature register1 */
+#define SCB_ISAR2                                          (HWREG32(0xE000ED68)) /* ISA Feature register2 */
+#define SCB_ISAR3                                          (HWREG32(0xE000ED6C)) /* ISA Feature register3 */
+#define SCB_ISAR4                                          (HWREG32(0xE000ED70)) /* ISA Feature register4 */
+#define SCB_CPACR                                          (HWREG32(0xE000ED88)) /* Coprocessor Access Control Register */
+
+/* Register offsets from SCB_BASE address */
+#define OFS_SCB_CPUID                                      (0x00000D00)          /* CPUID Base Register */
+#define OFS_SCB_ICSR                                       (0x00000D04)          /* Interrupt Control State Register */
+#define OFS_SCB_VTOR                                       (0x00000D08)          /* Vector Table Offset Register */
+#define OFS_SCB_AIRCR                                      (0x00000D0C)          /* Application Interrupt/Reset Control Register */
+#define OFS_SCB_SCR                                        (0x00000D10)          /* System Control Register */
+#define OFS_SCB_CCR                                        (0x00000D14)          /* Configuration Control Register */
+#define OFS_SCB_SHPR1                                      (0x00000D18)          /* System Handlers 4-7 Priority Register */
+#define OFS_SCB_SHPR2                                      (0x00000D1C)          /* System Handlers 8-11 Priority Register */
+#define OFS_SCB_SHPR3                                      (0x00000D20)          /* System Handlers 12-15 Priority Register */
+#define OFS_SCB_SHCSR                                      (0x00000D24)          /* System Handler Control and State Register */
+#define OFS_SCB_CFSR                                       (0x00000D28)          /* Configurable Fault Status Registers */
+#define OFS_SCB_HFSR                                       (0x00000D2C)          /* Hard Fault Status Register */
+#define OFS_SCB_DFSR                                       (0x00000D30)          /* Debug Fault Status Register */
+#define OFS_SCB_MMFAR                                      (0x00000D34)          /* Mem Manage Fault Address Register */
+#define OFS_SCB_BFAR                                       (0x00000D38)          /* Bus Fault Address Register */
+#define OFS_SCB_AFSR                                       (0x00000D3C)          /* Auxiliary Fault Status Register */
+#define OFS_SCB_PFR0                                       (0x00000D40)          /* Processor Feature register0 */
+#define OFS_SCB_PFR1                                       (0x00000D44)          /* Processor Feature register1 */
+#define OFS_SCB_DFR0                                       (0x00000D48)          /* Debug Feature register0 */
+#define OFS_SCB_AFR0                                       (0x00000D4C)          /* Auxiliary Feature register0 */
+#define OFS_SCB_MMFR0                                      (0x00000D50)          /* Memory Model Feature register0 */
+#define OFS_SCB_MMFR1                                      (0x00000D54)          /* Memory Model Feature register1 */
+#define OFS_SCB_MMFR2                                      (0x00000D58)          /* Memory Model Feature register2 */
+#define OFS_SCB_MMFR3                                      (0x00000D5C)          /* Memory Model Feature register3 */
+#define OFS_SCB_ISAR0                                      (0x00000D60)          /* ISA Feature register0 */
+#define OFS_SCB_ISAR1                                      (0x00000D64)          /* ISA Feature register1 */
+#define OFS_SCB_ISAR2                                      (0x00000D68)          /* ISA Feature register2 */
+#define OFS_SCB_ISAR3                                      (0x00000D6C)          /* ISA Feature register3 */
+#define OFS_SCB_ISAR4                                      (0x00000D70)          /* ISA Feature register4 */
+#define OFS_SCB_CPACR                                      (0x00000D88)          /* Coprocessor Access Control Register */
+
+
+//*****************************************************************************
+// SCnSCB Registers
+//*****************************************************************************
+#define SCnSCB_ICTR                                        (HWREG32(0xE000E004)) /* Interrupt Control Type Register */
+#define SCnSCB_ACTLR                                       (HWREG32(0xE000E008)) /* Auxiliary Control Register */
+
+/* Register offsets from SCnSCB_BASE address */
+#define OFS_SCnSCB_ICTR                                    (0x00000004)          /* Interrupt Control Type Register */
+#define OFS_SCnSCB_ACTLR                                   (0x00000008)          /* Auxiliary Control Register */
+
+
+//*****************************************************************************
+// SYSCTL Registers
+//*****************************************************************************
+#define SYSCTL_REBOOT_CTL                                  (HWREG32(0xE0043000)) /* Reboot Control Register */
+#define SYSCTL_NMI_CTLSTAT                                 (HWREG32(0xE0043004)) /* NMI Control and Status Register */
+#define SYSCTL_WDTRESET_CTL                                (HWREG32(0xE0043008)) /* Watchdog Reset Control Register */
+#define SYSCTL_PERIHALT_CTL                                (HWREG32(0xE004300C)) /* Peripheral Halt Control Register */
+#define SYSCTL_SRAM_SIZE                                   (HWREG32(0xE0043010)) /* SRAM Size Register */
+#define SYSCTL_SRAM_BANKEN                                 (HWREG32(0xE0043014)) /* SRAM Bank Enable Register */
+#define SYSCTL_SRAM_BANKRET                                (HWREG32(0xE0043018)) /* SRAM Bank Retention Control Register */
+#define SYSCTL_FLASH_SIZE                                  (HWREG32(0xE0043020)) /* Flash Size Register */
+#define SYSCTL_DIO_GLTFLT_CTL                              (HWREG32(0xE0043030)) /* Digital I/O Glitch Filter Control Register */
+#define SYSCTL_SECDATA_UNLOCK                              (HWREG32(0xE0043040)) /* IP Protected Secure Zone Data Access Unlock Register */
+#define SYSCTL_MASTER_UNLOCK                               (HWREG32(0xE0044000)) /* Master Unlock Register */
+#define SYSCTL_BOOTOVER_REQ0                               (HWREG32(0xE0044004)) /* Boot Override Request Register */
+#define SYSCTL_BOOTOVER_REQ1                               (HWREG32(0xE0044008)) /* Boot Override Request Register */
+#define SYSCTL_BOOTOVER_ACK                                (HWREG32(0xE004400C)) /* Boot Override Acknowledge Register */
+#define SYSCTL_RESET_REQ                                   (HWREG32(0xE0044010)) /* Reset Request Register */
+#define SYSCTL_RESET_STATOVER                              (HWREG32(0xE0044014)) /* Reset Status and Override Register */
+#define SYSCTL_SYSTEM_STAT                                 (HWREG32(0xE0044020)) /* System Status Register */
+
+/* Register offsets from SYSCTL_BASE address */
+#define OFS_SYSCTL_REBOOT_CTL                              (0x00000000)          /* Reboot Control Register */
+#define OFS_SYSCTL_NMI_CTLSTAT                             (0x00000004)          /* NMI Control and Status Register */
+#define OFS_SYSCTL_WDTRESET_CTL                            (0x00000008)          /* Watchdog Reset Control Register */
+#define OFS_SYSCTL_PERIHALT_CTL                            (0x0000000c)          /* Peripheral Halt Control Register */
+#define OFS_SYSCTL_SRAM_SIZE                               (0x00000010)          /* SRAM Size Register */
+#define OFS_SYSCTL_SRAM_BANKEN                             (0x00000014)          /* SRAM Bank Enable Register */
+#define OFS_SYSCTL_SRAM_BANKRET                            (0x00000018)          /* SRAM Bank Retention Control Register */
+#define OFS_SYSCTL_FLASH_SIZE                              (0x00000020)          /* Flash Size Register */
+#define OFS_SYSCTL_DIO_GLTFLT_CTL                          (0x00000030)          /* Digital I/O Glitch Filter Control Register */
+#define OFS_SYSCTL_SECDATA_UNLOCK                          (0x00000040)          /* IP Protected Secure Zone Data Access Unlock Register */
+#define OFS_SYSCTL_MASTER_UNLOCK                           (0x00001000)          /* Master Unlock Register */
+#define OFS_SYSCTL_BOOTOVER_REQ0                           (0x00001004)          /* Boot Override Request Register */
+#define OFS_SYSCTL_BOOTOVER_REQ1                           (0x00001008)          /* Boot Override Request Register */
+#define OFS_SYSCTL_BOOTOVER_ACK                            (0x0000100c)          /* Boot Override Acknowledge Register */
+#define OFS_SYSCTL_RESET_REQ                               (0x00001010)          /* Reset Request Register */
+#define OFS_SYSCTL_RESET_STATOVER                          (0x00001014)          /* Reset Status and Override Register */
+#define OFS_SYSCTL_SYSTEM_STAT                             (0x00001020)          /* System Status Register */
+
+
+//*****************************************************************************
+// SYSTICK Registers
+//*****************************************************************************
+#define SYSTICK_STCSR                                      (HWREG32(0xE000E010)) /* SysTick Control and Status Register */
+#define SYSTICK_STRVR                                      (HWREG32(0xE000E014)) /* SysTick Reload Value Register */
+#define SYSTICK_STCVR                                      (HWREG32(0xE000E018)) /* SysTick Current Value Register */
+#define SYSTICK_STCR                                       (HWREG32(0xE000E01C)) /* SysTick Calibration Value Register */
+
+/* Register offsets from SYSTICK_BASE address */
+#define OFS_SYSTICK_STCSR                                  (0x00000010)          /* SysTick Control and Status Register */
+#define OFS_SYSTICK_STRVR                                  (0x00000014)          /* SysTick Reload Value Register */
+#define OFS_SYSTICK_STCVR                                  (0x00000018)          /* SysTick Current Value Register */
+#define OFS_SYSTICK_STCR                                   (0x0000001C)          /* SysTick Calibration Value Register */
+
+
+//*****************************************************************************
+// TIMER32 Registers
+//*****************************************************************************
+#define TIMER32_LOAD1                                      (HWREG32(0x4000C000)) /* Timer 1 Load Register */
+#define TIMER32_VALUE1                                     (HWREG32(0x4000C004)) /* Timer 1 Current Value Register */
+#define TIMER32_CONTROL1                                   (HWREG32(0x4000C008)) /* Timer 1 Timer Control Register */
+#define TIMER32_INTCLR1                                    (HWREG32(0x4000C00C)) /* Timer 1 Interrupt Clear Register */
+#define TIMER32_RIS1                                       (HWREG32(0x4000C010)) /* Timer 1 Raw Interrupt Status Register */
+#define TIMER32_MIS1                                       (HWREG32(0x4000C014)) /* Timer 1 Interrupt Status Register */
+#define TIMER32_BGLOAD1                                    (HWREG32(0x4000C018)) /* Timer 1 Background Load Register */
+#define TIMER32_LOAD2                                      (HWREG32(0x4000C020)) /* Timer 2 Load Register */
+#define TIMER32_VALUE2                                     (HWREG32(0x4000C024)) /* Timer 2 Current Value Register */
+#define TIMER32_CONTROL2                                   (HWREG32(0x4000C028)) /* Timer 2 Timer Control Register */
+#define TIMER32_INTCLR2                                    (HWREG32(0x4000C02C)) /* Timer 2 Interrupt Clear Register */
+#define TIMER32_RIS2                                       (HWREG32(0x4000C030)) /* Timer 2 Raw Interrupt Status Register */
+#define TIMER32_MIS2                                       (HWREG32(0x4000C034)) /* Timer 2 Interrupt Status Register */
+#define TIMER32_BGLOAD2                                    (HWREG32(0x4000C038)) /* Timer 2 Background Load Register */
+
+/* Register offsets from TIMER32_BASE address */
+#define OFS_TIMER32_LOAD1                                  (0x00000000)          /* Timer 1 Load Register */
+#define OFS_TIMER32_VALUE1                                 (0x00000004)          /* Timer 1 Current Value Register */
+#define OFS_TIMER32_CONTROL1                               (0x00000008)          /* Timer 1 Timer Control Register */
+#define OFS_TIMER32_INTCLR1                                (0x0000000C)          /* Timer 1 Interrupt Clear Register */
+#define OFS_TIMER32_RIS1                                   (0x00000010)          /* Timer 1 Raw Interrupt Status Register */
+#define OFS_TIMER32_MIS1                                   (0x00000014)          /* Timer 1 Interrupt Status Register */
+#define OFS_TIMER32_BGLOAD1                                (0x00000018)          /* Timer 1 Background Load Register */
+#define OFS_TIMER32_LOAD2                                  (0x00000020)          /* Timer 2 Load Register */
+#define OFS_TIMER32_VALUE2                                 (0x00000024)          /* Timer 2 Current Value Register */
+#define OFS_TIMER32_CONTROL2                               (0x00000028)          /* Timer 2 Timer Control Register */
+#define OFS_TIMER32_INTCLR2                                (0x0000002C)          /* Timer 2 Interrupt Clear Register */
+#define OFS_TIMER32_RIS2                                   (0x00000030)          /* Timer 2 Raw Interrupt Status Register */
+#define OFS_TIMER32_MIS2                                   (0x00000034)          /* Timer 2 Interrupt Status Register */
+#define OFS_TIMER32_BGLOAD2                                (0x00000038)          /* Timer 2 Background Load Register */
+
+
+//*****************************************************************************
+// TIMER_A0 Registers
+//*****************************************************************************
+#define TA0CTL                                             (HWREG16(0x40000000)) /* TimerAx Control Register */
+#define TA0CCTL0                                           (HWREG16(0x40000002)) /* Timer_A Capture/Compare Control Register */
+#define TA0CCTL1                                           (HWREG16(0x40000004)) /* Timer_A Capture/Compare Control Register */
+#define TA0CCTL2                                           (HWREG16(0x40000006)) /* Timer_A Capture/Compare Control Register */
+#define TA0CCTL3                                           (HWREG16(0x40000008)) /* Timer_A Capture/Compare Control Register */
+#define TA0CCTL4                                           (HWREG16(0x4000000A)) /* Timer_A Capture/Compare Control Register */
+#define TA0CCTL5                                           (HWREG16(0x4000000C)) /* Timer_A Capture/Compare Control Register */
+#define TA0CCTL6                                           (HWREG16(0x4000000E)) /* Timer_A Capture/Compare Control Register */
+#define TA0R                                               (HWREG16(0x40000010)) /* TimerA register */
+#define TA0CCR0                                            (HWREG16(0x40000012)) /* Timer_A Capture/Compare  Register */
+#define TA0CCR1                                            (HWREG16(0x40000014)) /* Timer_A Capture/Compare  Register */
+#define TA0CCR2                                            (HWREG16(0x40000016)) /* Timer_A Capture/Compare  Register */
+#define TA0CCR3                                            (HWREG16(0x40000018)) /* Timer_A Capture/Compare  Register */
+#define TA0CCR4                                            (HWREG16(0x4000001A)) /* Timer_A Capture/Compare  Register */
+#define TA0CCR5                                            (HWREG16(0x4000001C)) /* Timer_A Capture/Compare  Register */
+#define TA0CCR6                                            (HWREG16(0x4000001E)) /* Timer_A Capture/Compare  Register */
+#define TA0EX0                                             (HWREG16(0x40000020)) /* TimerAx Expansion 0 Register */
+#define TA0IV                                              (HWREG16(0x4000002E)) /* TimerAx Interrupt Vector Register */
+
+/* Register offsets from TIMER_A0_BASE address */
+#define OFS_TA0CTL                                         (0x0000)              /* TimerAx Control Register */
+#define OFS_TA0CCTL0                                       (0x0002)              /* Timer_A Capture/Compare Control Register */
+#define OFS_TA0CCTL1                                       (0x0004)              /* Timer_A Capture/Compare Control Register */
+#define OFS_TA0CCTL2                                       (0x0006)              /* Timer_A Capture/Compare Control Register */
+#define OFS_TA0CCTL3                                       (0x0008)              /* Timer_A Capture/Compare Control Register */
+#define OFS_TA0CCTL4                                       (0x000A)              /* Timer_A Capture/Compare Control Register */
+#define OFS_TA0CCTL5                                       (0x000C)              /* Timer_A Capture/Compare Control Register */
+#define OFS_TA0CCTL6                                       (0x000E)              /* Timer_A Capture/Compare Control Register */
+#define OFS_TA0R                                           (0x0010)              /* TimerA register */
+#define OFS_TA0CCR0                                        (0x0012)              /* Timer_A Capture/Compare  Register */
+#define OFS_TA0CCR1                                        (0x0014)              /* Timer_A Capture/Compare  Register */
+#define OFS_TA0CCR2                                        (0x0016)              /* Timer_A Capture/Compare  Register */
+#define OFS_TA0CCR3                                        (0x0018)              /* Timer_A Capture/Compare  Register */
+#define OFS_TA0CCR4                                        (0x001A)              /* Timer_A Capture/Compare  Register */
+#define OFS_TA0CCR5                                        (0x001C)              /* Timer_A Capture/Compare  Register */
+#define OFS_TA0CCR6                                        (0x001E)              /* Timer_A Capture/Compare  Register */
+#define OFS_TA0EX0                                         (0x0020)              /* TimerAx Expansion 0 Register */
+#define OFS_TA0IV                                          (0x002e)              /* TimerAx Interrupt Vector Register */
+
+
+//*****************************************************************************
+// TIMER_A1 Registers
+//*****************************************************************************
+#define TA1CTL                                             (HWREG16(0x40000400)) /* TimerAx Control Register */
+#define TA1CCTL0                                           (HWREG16(0x40000402)) /* Timer_A Capture/Compare Control Register */
+#define TA1CCTL1                                           (HWREG16(0x40000404)) /* Timer_A Capture/Compare Control Register */
+#define TA1CCTL2                                           (HWREG16(0x40000406)) /* Timer_A Capture/Compare Control Register */
+#define TA1CCTL3                                           (HWREG16(0x40000408)) /* Timer_A Capture/Compare Control Register */
+#define TA1CCTL4                                           (HWREG16(0x4000040A)) /* Timer_A Capture/Compare Control Register */
+#define TA1CCTL5                                           (HWREG16(0x4000040C)) /* Timer_A Capture/Compare Control Register */
+#define TA1CCTL6                                           (HWREG16(0x4000040E)) /* Timer_A Capture/Compare Control Register */
+#define TA1R                                               (HWREG16(0x40000410)) /* TimerA register */
+#define TA1CCR0                                            (HWREG16(0x40000412)) /* Timer_A Capture/Compare  Register */
+#define TA1CCR1                                            (HWREG16(0x40000414)) /* Timer_A Capture/Compare  Register */
+#define TA1CCR2                                            (HWREG16(0x40000416)) /* Timer_A Capture/Compare  Register */
+#define TA1CCR3                                            (HWREG16(0x40000418)) /* Timer_A Capture/Compare  Register */
+#define TA1CCR4                                            (HWREG16(0x4000041A)) /* Timer_A Capture/Compare  Register */
+#define TA1CCR5                                            (HWREG16(0x4000041C)) /* Timer_A Capture/Compare  Register */
+#define TA1CCR6                                            (HWREG16(0x4000041E)) /* Timer_A Capture/Compare  Register */
+#define TA1EX0                                             (HWREG16(0x40000420)) /* TimerAx Expansion 0 Register */
+#define TA1IV                                              (HWREG16(0x4000042E)) /* TimerAx Interrupt Vector Register */
+
+/* Register offsets from TIMER_A1_BASE address */
+#define OFS_TA1CTL                                         (0x0000)              /* TimerAx Control Register */
+#define OFS_TA1CCTL0                                       (0x0002)              /* Timer_A Capture/Compare Control Register */
+#define OFS_TA1CCTL1                                       (0x0004)              /* Timer_A Capture/Compare Control Register */
+#define OFS_TA1CCTL2                                       (0x0006)              /* Timer_A Capture/Compare Control Register */
+#define OFS_TA1CCTL3                                       (0x0008)              /* Timer_A Capture/Compare Control Register */
+#define OFS_TA1CCTL4                                       (0x000A)              /* Timer_A Capture/Compare Control Register */
+#define OFS_TA1CCTL5                                       (0x000C)              /* Timer_A Capture/Compare Control Register */
+#define OFS_TA1CCTL6                                       (0x000E)              /* Timer_A Capture/Compare Control Register */
+#define OFS_TA1R                                           (0x0010)              /* TimerA register */
+#define OFS_TA1CCR0                                        (0x0012)              /* Timer_A Capture/Compare  Register */
+#define OFS_TA1CCR1                                        (0x0014)              /* Timer_A Capture/Compare  Register */
+#define OFS_TA1CCR2                                        (0x0016)              /* Timer_A Capture/Compare  Register */
+#define OFS_TA1CCR3                                        (0x0018)              /* Timer_A Capture/Compare  Register */
+#define OFS_TA1CCR4                                        (0x001A)              /* Timer_A Capture/Compare  Register */
+#define OFS_TA1CCR5                                        (0x001C)              /* Timer_A Capture/Compare  Register */
+#define OFS_TA1CCR6                                        (0x001E)              /* Timer_A Capture/Compare  Register */
+#define OFS_TA1EX0                                         (0x0020)              /* TimerAx Expansion 0 Register */
+#define OFS_TA1IV                                          (0x002e)              /* TimerAx Interrupt Vector Register */
+
+
+//*****************************************************************************
+// TIMER_A2 Registers
+//*****************************************************************************
+#define TA2CTL                                             (HWREG16(0x40000800)) /* TimerAx Control Register */
+#define TA2CCTL0                                           (HWREG16(0x40000802)) /* Timer_A Capture/Compare Control Register */
+#define TA2CCTL1                                           (HWREG16(0x40000804)) /* Timer_A Capture/Compare Control Register */
+#define TA2CCTL2                                           (HWREG16(0x40000806)) /* Timer_A Capture/Compare Control Register */
+#define TA2CCTL3                                           (HWREG16(0x40000808)) /* Timer_A Capture/Compare Control Register */
+#define TA2CCTL4                                           (HWREG16(0x4000080A)) /* Timer_A Capture/Compare Control Register */
+#define TA2CCTL5                                           (HWREG16(0x4000080C)) /* Timer_A Capture/Compare Control Register */
+#define TA2CCTL6                                           (HWREG16(0x4000080E)) /* Timer_A Capture/Compare Control Register */
+#define TA2R                                               (HWREG16(0x40000810)) /* TimerA register */
+#define TA2CCR0                                            (HWREG16(0x40000812)) /* Timer_A Capture/Compare  Register */
+#define TA2CCR1                                            (HWREG16(0x40000814)) /* Timer_A Capture/Compare  Register */
+#define TA2CCR2                                            (HWREG16(0x40000816)) /* Timer_A Capture/Compare  Register */
+#define TA2CCR3                                            (HWREG16(0x40000818)) /* Timer_A Capture/Compare  Register */
+#define TA2CCR4                                            (HWREG16(0x4000081A)) /* Timer_A Capture/Compare  Register */
+#define TA2CCR5                                            (HWREG16(0x4000081C)) /* Timer_A Capture/Compare  Register */
+#define TA2CCR6                                            (HWREG16(0x4000081E)) /* Timer_A Capture/Compare  Register */
+#define TA2EX0                                             (HWREG16(0x40000820)) /* TimerAx Expansion 0 Register */
+#define TA2IV                                              (HWREG16(0x4000082E)) /* TimerAx Interrupt Vector Register */
+
+/* Register offsets from TIMER_A2_BASE address */
+#define OFS_TA2CTL                                         (0x0000)              /* TimerAx Control Register */
+#define OFS_TA2CCTL0                                       (0x0002)              /* Timer_A Capture/Compare Control Register */
+#define OFS_TA2CCTL1                                       (0x0004)              /* Timer_A Capture/Compare Control Register */
+#define OFS_TA2CCTL2                                       (0x0006)              /* Timer_A Capture/Compare Control Register */
+#define OFS_TA2CCTL3                                       (0x0008)              /* Timer_A Capture/Compare Control Register */
+#define OFS_TA2CCTL4                                       (0x000A)              /* Timer_A Capture/Compare Control Register */
+#define OFS_TA2CCTL5                                       (0x000C)              /* Timer_A Capture/Compare Control Register */
+#define OFS_TA2CCTL6                                       (0x000E)              /* Timer_A Capture/Compare Control Register */
+#define OFS_TA2R                                           (0x0010)              /* TimerA register */
+#define OFS_TA2CCR0                                        (0x0012)              /* Timer_A Capture/Compare  Register */
+#define OFS_TA2CCR1                                        (0x0014)              /* Timer_A Capture/Compare  Register */
+#define OFS_TA2CCR2                                        (0x0016)              /* Timer_A Capture/Compare  Register */
+#define OFS_TA2CCR3                                        (0x0018)              /* Timer_A Capture/Compare  Register */
+#define OFS_TA2CCR4                                        (0x001A)              /* Timer_A Capture/Compare  Register */
+#define OFS_TA2CCR5                                        (0x001C)              /* Timer_A Capture/Compare  Register */
+#define OFS_TA2CCR6                                        (0x001E)              /* Timer_A Capture/Compare  Register */
+#define OFS_TA2EX0                                         (0x0020)              /* TimerAx Expansion 0 Register */
+#define OFS_TA2IV                                          (0x002e)              /* TimerAx Interrupt Vector Register */
+
+
+//*****************************************************************************
+// TIMER_A3 Registers
+//*****************************************************************************
+#define TA3CTL                                             (HWREG16(0x40000C00)) /* TimerAx Control Register */
+#define TA3CCTL0                                           (HWREG16(0x40000C02)) /* Timer_A Capture/Compare Control Register */
+#define TA3CCTL1                                           (HWREG16(0x40000C04)) /* Timer_A Capture/Compare Control Register */
+#define TA3CCTL2                                           (HWREG16(0x40000C06)) /* Timer_A Capture/Compare Control Register */
+#define TA3CCTL3                                           (HWREG16(0x40000C08)) /* Timer_A Capture/Compare Control Register */
+#define TA3CCTL4                                           (HWREG16(0x40000C0A)) /* Timer_A Capture/Compare Control Register */
+#define TA3CCTL5                                           (HWREG16(0x40000C0C)) /* Timer_A Capture/Compare Control Register */
+#define TA3CCTL6                                           (HWREG16(0x40000C0E)) /* Timer_A Capture/Compare Control Register */
+#define TA3R                                               (HWREG16(0x40000C10)) /* TimerA register */
+#define TA3CCR0                                            (HWREG16(0x40000C12)) /* Timer_A Capture/Compare  Register */
+#define TA3CCR1                                            (HWREG16(0x40000C14)) /* Timer_A Capture/Compare  Register */
+#define TA3CCR2                                            (HWREG16(0x40000C16)) /* Timer_A Capture/Compare  Register */
+#define TA3CCR3                                            (HWREG16(0x40000C18)) /* Timer_A Capture/Compare  Register */
+#define TA3CCR4                                            (HWREG16(0x40000C1A)) /* Timer_A Capture/Compare  Register */
+#define TA3CCR5                                            (HWREG16(0x40000C1C)) /* Timer_A Capture/Compare  Register */
+#define TA3CCR6                                            (HWREG16(0x40000C1E)) /* Timer_A Capture/Compare  Register */
+#define TA3EX0                                             (HWREG16(0x40000C20)) /* TimerAx Expansion 0 Register */
+#define TA3IV                                              (HWREG16(0x40000C2E)) /* TimerAx Interrupt Vector Register */
+
+/* Register offsets from TIMER_A3_BASE address */
+#define OFS_TA3CTL                                         (0x0000)              /* TimerAx Control Register */
+#define OFS_TA3CCTL0                                       (0x0002)              /* Timer_A Capture/Compare Control Register */
+#define OFS_TA3CCTL1                                       (0x0004)              /* Timer_A Capture/Compare Control Register */
+#define OFS_TA3CCTL2                                       (0x0006)              /* Timer_A Capture/Compare Control Register */
+#define OFS_TA3CCTL3                                       (0x0008)              /* Timer_A Capture/Compare Control Register */
+#define OFS_TA3CCTL4                                       (0x000A)              /* Timer_A Capture/Compare Control Register */
+#define OFS_TA3CCTL5                                       (0x000C)              /* Timer_A Capture/Compare Control Register */
+#define OFS_TA3CCTL6                                       (0x000E)              /* Timer_A Capture/Compare Control Register */
+#define OFS_TA3R                                           (0x0010)              /* TimerA register */
+#define OFS_TA3CCR0                                        (0x0012)              /* Timer_A Capture/Compare  Register */
+#define OFS_TA3CCR1                                        (0x0014)              /* Timer_A Capture/Compare  Register */
+#define OFS_TA3CCR2                                        (0x0016)              /* Timer_A Capture/Compare  Register */
+#define OFS_TA3CCR3                                        (0x0018)              /* Timer_A Capture/Compare  Register */
+#define OFS_TA3CCR4                                        (0x001A)              /* Timer_A Capture/Compare  Register */
+#define OFS_TA3CCR5                                        (0x001C)              /* Timer_A Capture/Compare  Register */
+#define OFS_TA3CCR6                                        (0x001E)              /* Timer_A Capture/Compare  Register */
+#define OFS_TA3EX0                                         (0x0020)              /* TimerAx Expansion 0 Register */
+#define OFS_TA3IV                                          (0x002e)              /* TimerAx Interrupt Vector Register */
+
+
+//*****************************************************************************
+// TLV Registers
+//*****************************************************************************
+#define TLV_TLV_CHECKSUM                                   (HWREG32(0x00201000)) /* TLV Checksum */
+#define TLV_DEVICE_INFO_TAG                                (HWREG32(0x00201004)) /* Device Info Tag */
+#define TLV_DEVICE_INFO_LEN                                (HWREG32(0x00201008)) /* Device Info Length */
+#define TLV_DEVICE_ID                                      (HWREG32(0x0020100C)) /* Device ID */
+#define TLV_HWREV                                          (HWREG32(0x00201010)) /* HW Revision */
+#define TLV_BCREV                                          (HWREG32(0x00201014)) /* Boot Code Revision */
+#define TLV_ROM_DRVLIB_REV                                 (HWREG32(0x00201018)) /* ROM Driver Library Revision */
+#define TLV_DIE_REC_TAG                                    (HWREG32(0x0020101C)) /* Die Record Tag */
+#define TLV_DIE_REC_LEN                                    (HWREG32(0x00201020)) /* Die Record Length */
+#define TLV_DIE_XPOS                                       (HWREG32(0x00201024)) /* Die X-Position */
+#define TLV_DIE_YPOS                                       (HWREG32(0x00201028)) /* Die Y-Position */
+#define TLV_WAFER_ID                                       (HWREG32(0x0020102C)) /* Wafer ID */
+#define TLV_LOT_ID                                         (HWREG32(0x00201030)) /* Lot ID */
+#define TLV_RESERVED0                                      (HWREG32(0x00201034)) /* Reserved */
+#define TLV_RESERVED1                                      (HWREG32(0x00201038)) /* Reserved */
+#define TLV_RESERVED2                                      (HWREG32(0x0020103C)) /* Reserved */
+#define TLV_TEST_RESULTS                                   (HWREG32(0x00201040)) /* Test Results */
+#define TLV_CS_CAL_TAG                                     (HWREG32(0x00201044)) /* Clock System Calibration Tag */
+#define TLV_CS_CAL_LEN                                     (HWREG32(0x00201048)) /* Clock System Calibration Length */
+#define TLV_DCOIR_FCAL_RSEL04                              (HWREG32(0x0020104C)) /* DCO IR mode: Frequency calibration for DCORSEL 0 to 4 */
+#define TLV_DCOIR_FCAL_RSEL5                               (HWREG32(0x00201050)) /* DCO IR mode: Frequency calibration for DCORSEL 5 */
+#define TLV_DCOIR_MAXPOSTUNE_RSEL04                        (HWREG32(0x00201054)) /* DCO IR mode: Max Positive Tune for DCORSEL 0 to 4 */
+#define TLV_DCOIR_MAXNEGTUNE_RSEL04                        (HWREG32(0x00201058)) /* DCO IR mode: Max Negative Tune for DCORSEL 0 to 4 */
+#define TLV_DCOIR_MAXPOSTUNE_RSEL5                         (HWREG32(0x0020105C)) /* DCO IR mode: Max Positive Tune for DCORSEL 5 */
+#define TLV_DCOIR_MAXNEGTUNE_RSEL5                         (HWREG32(0x00201060)) /* DCO IR mode: Max Negative Tune for DCORSEL 5 */
+#define TLV_DCOIR_CONSTK_RSEL04                            (HWREG32(0x00201064)) /* DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4 */
+#define TLV_DCOIR_CONSTK_RSEL5                             (HWREG32(0x00201068)) /* DCO IR mode: DCO Constant (K) for DCORSEL 5 */
+#define TLV_DCOER_FCAL_RSEL04                              (HWREG32(0x0020106C)) /* DCO ER mode: Frequency calibration for DCORSEL 0 to 4 */
+#define TLV_DCOER_FCAL_RSEL5                               (HWREG32(0x00201070)) /* DCO ER mode: Frequency calibration for DCORSEL 5 */
+#define TLV_DCOER_MAXPOSTUNE_RSEL04                        (HWREG32(0x00201074)) /* DCO ER mode: Max Positive Tune for DCORSEL 0 to 4 */
+#define TLV_DCOER_MAXNEGTUNE_RSEL04                        (HWREG32(0x00201078)) /* DCO ER mode: Max Negative Tune for DCORSEL 0 to 4 */
+#define TLV_DCOER_MAXPOSTUNE_RSEL5                         (HWREG32(0x0020107C)) /* DCO ER mode: Max Positive Tune for DCORSEL 5 */
+#define TLV_DCOER_MAXNEGTUNE_RSEL5                         (HWREG32(0x00201080)) /* DCO ER mode: Max Negative Tune for DCORSEL 5 */
+#define TLV_DCOER_CONSTK_RSEL04                            (HWREG32(0x00201084)) /* DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4 */
+#define TLV_DCOER_CONSTK_RSEL5                             (HWREG32(0x00201088)) /* DCO ER mode: DCO Constant (K) for DCORSEL 5 */
+#define TLV_ADC14_CAL_TAG                                  (HWREG32(0x0020108C)) /* ADC14 Calibration Tag */
+#define TLV_ADC14_CAL_LEN                                  (HWREG32(0x00201090)) /* ADC14 Calibration Length */
+#define TLV_ADC14_GF_EXTREF30C                             (HWREG32(0x00201094)) /* ADC14 Gain Factor for External Reference 30�C */
+#define TLV_ADC14_GF_EXTREF85C                             (HWREG32(0x00201098)) /* ADC14 Gain Factor for External Reference 85�C */
+#define TLV_ADC14_GF_BUF_EXTREF30C                         (HWREG32(0x0020109C)) /* ADC14 Gain Factor for Buffered External Reference 30�C */
+#define TLV_ADC14_GF_BUF_EXTREF85C                         (HWREG32(0x002010A0)) /* ADC14 Gain Factor for Buffered External Reference 85�C */
+#define TLV_ADC14_GF_BUF1P2V_INTREF30C_REFOUT0             (HWREG32(0x002010A4)) /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 30�C (REFOUT = 0) */
+#define TLV_ADC14_GF_BUF1P2V_INTREF85C_REFOUT0             (HWREG32(0x002010A8)) /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 85�C (REFOUT = 0) */
+#define TLV_ADC14_GF_BUF1P2V_INTREF30C_REFOUT1             (HWREG32(0x002010AC)) /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 30�C (REFOUT = 1) */
+#define TLV_ADC14_GF_BUF1P2V_INTREF85C_REFOUT1             (HWREG32(0x002010B0)) /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 85�C (REFOUT = 1) */
+#define TLV_ADC14_GF_BUF1P45V_INTREF30C_REFOUT0            (HWREG32(0x002010B4)) /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 30�C (REFOUT = 0) */
+#define TLV_ADC14_GF_BUF1P45V_INTREF85C_REFOUT0            (HWREG32(0x002010B8)) /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 85�C (REFOUT = 0) */
+#define TLV_ADC14_GF_BUF1P45V_INTREF30C_REFOUT1            (HWREG32(0x002010BC)) /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 30�C (REFOUT = 1) */
+#define TLV_ADC14_GF_BUF1P45V_INTREF85C_REFOUT1            (HWREG32(0x002010C0)) /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 85�C (REFOUT = 1) */
+#define TLV_ADC14_GF_BUF2P5V_INTREF30C_REFOUT0             (HWREG32(0x002010C4)) /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 30�C (REFOUT = 0) */
+#define TLV_ADC14_GF_BUF2P5V_INTREF85C_REFOUT0             (HWREG32(0x002010C8)) /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 85�C (REFOUT = 0) */
+#define TLV_ADC14_GF_BUF2P5V_INTREF30C_REFOUT1             (HWREG32(0x002010CC)) /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 30�C (REFOUT = 1) */
+#define TLV_ADC14_GF_BUF2P5V_INTREF85C_REFOUT1             (HWREG32(0x002010D0)) /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 85�C (REFOUT = 1) */
+#define TLV_ADC14_OFFSET_VRSEL_1                           (HWREG32(0x002010D4)) /* ADC14 Offset (ADC14VRSEL = 1h) */
+#define TLV_ADC14_OFFSET_VRSEL_E                           (HWREG32(0x002010D8)) /* ADC14 Offset (ADC14VRSEL = Eh) */
+#define TLV_ADC14_REF1P2V_TS30C                            (HWREG32(0x002010DC)) /* ADC14 1.2V Reference Temp. Sensor 30�C */
+#define TLV_ADC14_REF1P2V_TS85C                            (HWREG32(0x002010E0)) /* ADC14 1.2V Reference Temp. Sensor 85�C */
+#define TLV_ADC14_REF1P45V_TS30C                           (HWREG32(0x002010E4)) /* ADC14 1.45V Reference Temp. Sensor 30�C */
+#define TLV_ADC14_REF1P45V_TS85C                           (HWREG32(0x002010E8)) /* ADC14 1.45V Reference Temp. Sensor 85�C */
+#define TLV_ADC14_REF2P5V_TS30C                            (HWREG32(0x002010EC)) /* ADC14 2.5V Reference Temp. Sensor 30�C */
+#define TLV_ADC14_REF2P5V_TS85C                            (HWREG32(0x002010F0)) /* ADC14 2.5V Reference Temp. Sensor 85�C */
+#define TLV_REF_CAL_TAG                                    (HWREG32(0x002010F4)) /* REF Calibration Tag */
+#define TLV_REF_CAL_LEN                                    (HWREG32(0x002010F8)) /* REF Calibration Length */
+#define TLV_REF_1P2V                                       (HWREG32(0x002010FC)) /* REF 1.2V Reference */
+#define TLV_REF_1P45V                                      (HWREG32(0x00201100)) /* REF 1.45V Reference */
+#define TLV_REF_2P5V                                       (HWREG32(0x00201104)) /* REF 2.5V Reference */
+#define TLV_RANDOM_NUM_TAG                                 (HWREG32(0x00201108)) /* 128-bit Random Number Tag */
+#define TLV_RANDOM_NUM_LEN                                 (HWREG32(0x0020110C)) /* 128-bit Random Number Length */
+#define TLV_RANDOM_NUM_1                                   (HWREG32(0x00201110)) /* 32-bit Random Number 1 */
+#define TLV_RANDOM_NUM_2                                   (HWREG32(0x00201114)) /* 32-bit Random Number 2 */
+#define TLV_RANDOM_NUM_3                                   (HWREG32(0x00201118)) /* 32-bit Random Number 3 */
+#define TLV_RANDOM_NUM_4                                   (HWREG32(0x0020111C)) /* 32-bit Random Number 4 */
+#define TLV_BSL_CFG_TAG                                    (HWREG32(0x00201120)) /* BSL Configuration Tag */
+#define TLV_BSL_CFG_LEN                                    (HWREG32(0x00201124)) /* BSL Configuration Length */
+#define TLV_BSL_PERIPHIF_SEL                               (HWREG32(0x00201128)) /* BSL Peripheral Interface Selection */
+#define TLV_BSL_PORTIF_CFG_UART                            (HWREG32(0x0020112C)) /* BSL Port Interface Configuration for UART */
+#define TLV_BSL_PORTIF_CFG_SPI                             (HWREG32(0x00201130)) /* BSL Port Interface Configuration for SPI */
+#define TLV_BSL_PORTIF_CFG_I2C                             (HWREG32(0x00201134)) /* BSL Port Interface Configuration for I2C */
+#define TLV_TLV_END                                        (HWREG32(0x00201138)) /* TLV End Word */
+
+/* Register offsets from TLV_BASE address */
+#define OFS_TLV_TLV_CHECKSUM                               (0x00000000)          /* TLV Checksum */
+#define OFS_TLV_DEVICE_INFO_TAG                            (0x00000004)          /* Device Info Tag */
+#define OFS_TLV_DEVICE_INFO_LEN                            (0x00000008)          /* Device Info Length */
+#define OFS_TLV_DEVICE_ID                                  (0x0000000C)          /* Device ID */
+#define OFS_TLV_HWREV                                      (0x00000010)          /* HW Revision */
+#define OFS_TLV_BCREV                                      (0x00000014)          /* Boot Code Revision */
+#define OFS_TLV_ROM_DRVLIB_REV                             (0x00000018)          /* ROM Driver Library Revision */
+#define OFS_TLV_DIE_REC_TAG                                (0x0000001C)          /* Die Record Tag */
+#define OFS_TLV_DIE_REC_LEN                                (0x00000020)          /* Die Record Length */
+#define OFS_TLV_DIE_XPOS                                   (0x00000024)          /* Die X-Position */
+#define OFS_TLV_DIE_YPOS                                   (0x00000028)          /* Die Y-Position */
+#define OFS_TLV_WAFER_ID                                   (0x0000002C)          /* Wafer ID */
+#define OFS_TLV_LOT_ID                                     (0x00000030)          /* Lot ID */
+#define OFS_TLV_RESERVED0                                  (0x00000034)          /* Reserved */
+#define OFS_TLV_RESERVED1                                  (0x00000038)          /* Reserved */
+#define OFS_TLV_RESERVED2                                  (0x0000003c)          /* Reserved */
+#define OFS_TLV_TEST_RESULTS                               (0x00000040)          /* Test Results */
+#define OFS_TLV_CS_CAL_TAG                                 (0x00000044)          /* Clock System Calibration Tag */
+#define OFS_TLV_CS_CAL_LEN                                 (0x00000048)          /* Clock System Calibration Length */
+#define OFS_TLV_DCOIR_FCAL_RSEL04                          (0x0000004c)          /* DCO IR mode: Frequency calibration for DCORSEL 0 to 4 */
+#define OFS_TLV_DCOIR_FCAL_RSEL5                           (0x00000050)          /* DCO IR mode: Frequency calibration for DCORSEL 5 */
+#define OFS_TLV_DCOIR_MAXPOSTUNE_RSEL04                    (0x00000054)          /* DCO IR mode: Max Positive Tune for DCORSEL 0 to 4 */
+#define OFS_TLV_DCOIR_MAXNEGTUNE_RSEL04                    (0x00000058)          /* DCO IR mode: Max Negative Tune for DCORSEL 0 to 4 */
+#define OFS_TLV_DCOIR_MAXPOSTUNE_RSEL5                     (0x0000005c)          /* DCO IR mode: Max Positive Tune for DCORSEL 5 */
+#define OFS_TLV_DCOIR_MAXNEGTUNE_RSEL5                     (0x00000060)          /* DCO IR mode: Max Negative Tune for DCORSEL 5 */
+#define OFS_TLV_DCOIR_CONSTK_RSEL04                        (0x00000064)          /* DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4 */
+#define OFS_TLV_DCOIR_CONSTK_RSEL5                         (0x00000068)          /* DCO IR mode: DCO Constant (K) for DCORSEL 5 */
+#define OFS_TLV_DCOER_FCAL_RSEL04                          (0x0000006c)          /* DCO ER mode: Frequency calibration for DCORSEL 0 to 4 */
+#define OFS_TLV_DCOER_FCAL_RSEL5                           (0x00000070)          /* DCO ER mode: Frequency calibration for DCORSEL 5 */
+#define OFS_TLV_DCOER_MAXPOSTUNE_RSEL04                    (0x00000074)          /* DCO ER mode: Max Positive Tune for DCORSEL 0 to 4 */
+#define OFS_TLV_DCOER_MAXNEGTUNE_RSEL04                    (0x00000078)          /* DCO ER mode: Max Negative Tune for DCORSEL 0 to 4 */
+#define OFS_TLV_DCOER_MAXPOSTUNE_RSEL5                     (0x0000007c)          /* DCO ER mode: Max Positive Tune for DCORSEL 5 */
+#define OFS_TLV_DCOER_MAXNEGTUNE_RSEL5                     (0x00000080)          /* DCO ER mode: Max Negative Tune for DCORSEL 5 */
+#define OFS_TLV_DCOER_CONSTK_RSEL04                        (0x00000084)          /* DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4 */
+#define OFS_TLV_DCOER_CONSTK_RSEL5                         (0x00000088)          /* DCO ER mode: DCO Constant (K) for DCORSEL 5 */
+#define OFS_TLV_ADC14_CAL_TAG                              (0x0000008C)          /* ADC14 Calibration Tag */
+#define OFS_TLV_ADC14_CAL_LEN                              (0x00000090)          /* ADC14 Calibration Length */
+#define OFS_TLV_ADC14_GF_EXTREF30C                         (0x00000094)          /* ADC14 Gain Factor for External Reference 30�C */
+#define OFS_TLV_ADC14_GF_EXTREF85C                         (0x00000098)          /* ADC14 Gain Factor for External Reference 85�C */
+#define OFS_TLV_ADC14_GF_BUF_EXTREF30C                     (0x0000009C)          /* ADC14 Gain Factor for Buffered External Reference 30�C */
+#define OFS_TLV_ADC14_GF_BUF_EXTREF85C                     (0x000000A0)          /* ADC14 Gain Factor for Buffered External Reference 85�C */
+#define OFS_TLV_ADC14_GF_BUF1P2V_INTREF30C_REFOUT0         (0x000000A4)          /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 30�C (REFOUT = 0) */
+#define OFS_TLV_ADC14_GF_BUF1P2V_INTREF85C_REFOUT0         (0x000000A8)          /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 85�C (REFOUT = 0) */
+#define OFS_TLV_ADC14_GF_BUF1P2V_INTREF30C_REFOUT1         (0x000000AC)          /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 30�C (REFOUT = 1) */
+#define OFS_TLV_ADC14_GF_BUF1P2V_INTREF85C_REFOUT1         (0x000000B0)          /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 85�C (REFOUT = 1) */
+#define OFS_TLV_ADC14_GF_BUF1P45V_INTREF30C_REFOUT0        (0x000000B4)          /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 30�C (REFOUT = 0) */
+#define OFS_TLV_ADC14_GF_BUF1P45V_INTREF85C_REFOUT0        (0x000000B8)          /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 85�C (REFOUT = 0) */
+#define OFS_TLV_ADC14_GF_BUF1P45V_INTREF30C_REFOUT1        (0x000000BC)          /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 30�C (REFOUT = 1) */
+#define OFS_TLV_ADC14_GF_BUF1P45V_INTREF85C_REFOUT1        (0x000000C0)          /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 85�C (REFOUT = 1) */
+#define OFS_TLV_ADC14_GF_BUF2P5V_INTREF30C_REFOUT0         (0x000000C4)          /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 30�C (REFOUT = 0) */
+#define OFS_TLV_ADC14_GF_BUF2P5V_INTREF85C_REFOUT0         (0x000000C8)          /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 85�C (REFOUT = 0) */
+#define OFS_TLV_ADC14_GF_BUF2P5V_INTREF30C_REFOUT1         (0x000000CC)          /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 30�C (REFOUT = 1) */
+#define OFS_TLV_ADC14_GF_BUF2P5V_INTREF85C_REFOUT1         (0x000000D0)          /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 85�C (REFOUT = 1) */
+#define OFS_TLV_ADC14_OFFSET_VRSEL_1                       (0x000000D4)          /* ADC14 Offset (ADC14VRSEL = 1h) */
+#define OFS_TLV_ADC14_OFFSET_VRSEL_E                       (0x000000D8)          /* ADC14 Offset (ADC14VRSEL = Eh) */
+#define OFS_TLV_ADC14_REF1P2V_TS30C                        (0x000000DC)          /* ADC14 1.2V Reference Temp. Sensor 30�C */
+#define OFS_TLV_ADC14_REF1P2V_TS85C                        (0x000000E0)          /* ADC14 1.2V Reference Temp. Sensor 85�C */
+#define OFS_TLV_ADC14_REF1P45V_TS30C                       (0x000000E4)          /* ADC14 1.45V Reference Temp. Sensor 30�C */
+#define OFS_TLV_ADC14_REF1P45V_TS85C                       (0x000000E8)          /* ADC14 1.45V Reference Temp. Sensor 85�C */
+#define OFS_TLV_ADC14_REF2P5V_TS30C                        (0x000000EC)          /* ADC14 2.5V Reference Temp. Sensor 30�C */
+#define OFS_TLV_ADC14_REF2P5V_TS85C                        (0x000000F0)          /* ADC14 2.5V Reference Temp. Sensor 85�C */
+#define OFS_TLV_REF_CAL_TAG                                (0x000000F4)          /* REF Calibration Tag */
+#define OFS_TLV_REF_CAL_LEN                                (0x000000F8)          /* REF Calibration Length */
+#define OFS_TLV_REF_1P2V                                   (0x000000FC)          /* REF 1.2V Reference */
+#define OFS_TLV_REF_1P45V                                  (0x00000100)          /* REF 1.45V Reference */
+#define OFS_TLV_REF_2P5V                                   (0x00000104)          /* REF 2.5V Reference */
+#define OFS_TLV_RANDOM_NUM_TAG                             (0x00000108)          /* 128-bit Random Number Tag */
+#define OFS_TLV_RANDOM_NUM_LEN                             (0x0000010C)          /* 128-bit Random Number Length */
+#define OFS_TLV_RANDOM_NUM_1                               (0x00000110)          /* 32-bit Random Number 1 */
+#define OFS_TLV_RANDOM_NUM_2                               (0x00000114)          /* 32-bit Random Number 2 */
+#define OFS_TLV_RANDOM_NUM_3                               (0x00000118)          /* 32-bit Random Number 3 */
+#define OFS_TLV_RANDOM_NUM_4                               (0x0000011C)          /* 32-bit Random Number 4 */
+#define OFS_TLV_BSL_CFG_TAG                                (0x00000120)          /* BSL Configuration Tag */
+#define OFS_TLV_BSL_CFG_LEN                                (0x00000124)          /* BSL Configuration Length */
+#define OFS_TLV_BSL_PERIPHIF_SEL                           (0x00000128)          /* BSL Peripheral Interface Selection */
+#define OFS_TLV_BSL_PORTIF_CFG_UART                        (0x0000012C)          /* BSL Port Interface Configuration for UART */
+#define OFS_TLV_BSL_PORTIF_CFG_SPI                         (0x00000130)          /* BSL Port Interface Configuration for SPI */
+#define OFS_TLV_BSL_PORTIF_CFG_I2C                         (0x00000134)          /* BSL Port Interface Configuration for I2C */
+#define OFS_TLV_TLV_END                                    (0x00000138)          /* TLV End Word */
+
+
+//*****************************************************************************
+// WDT_A Registers
+//*****************************************************************************
+#define WDTCTL                                             (HWREG16(0x4000480C)) /* Watchdog Timer Control Register */
+
+/* Register offsets from WDT_A_BASE address */
+#define OFS_WDTCTL                                         (0x000c)              /* Watchdog Timer Control Register */
+
+
+//*****************************************************************************
+// CMSIS-format peripheral registers
+//*****************************************************************************
+
+//*****************************************************************************
+// ADC14 Registers
+//*****************************************************************************
+typedef struct {
+  union {    /* ADC14CTL0 Register */
+    __IO uint32_t r;
+    struct { /* ADC14CTL0 Bits */
+      __IO uint32_t bSC                 	:	1;  /* ADC14 start conversion */
+      __IO uint32_t bENC                	:	1;  /* ADC14 enable conversion */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bON                 	:	1;  /* ADC14 on */
+      __I  uint32_t bRESERVED1          	:	2;  /* Reserved */
+      __IO uint32_t bMSC                	:	1;  /* ADC14 multiple sample and conversion */
+      __IO uint32_t bSHT0               	:	4;  /* ADC14 sample-and-hold time */
+      __IO uint32_t bSHT1               	:	4;  /* ADC14 sample-and-hold time */
+      __I  uint32_t bBUSY               	:	1;  /* ADC14 busy */
+      __IO uint32_t bCONSEQ             	:	2;  /* ADC14 conversion sequence mode select */
+      __IO uint32_t bSSEL               	:	3;  /* ADC14 clock source select */
+      __IO uint32_t bDIV                	:	3;  /* ADC14 clock divider */
+      __IO uint32_t bISSH               	:	1;  /* ADC14 invert signal sample-and-hold */
+      __IO uint32_t bSHP                	:	1;  /* ADC14 sample-and-hold pulse-mode select */
+      __IO uint32_t bSHS                	:	3;  /* ADC14 sample-and-hold source select */
+      __IO uint32_t bPDIV               	:	2;  /* ADC14 predivider */
+    } b;
+  } rCTL0;
+  union {    /* ADC14CTL1 Register */
+    __IO uint32_t r;
+    struct { /* ADC14CTL1 Bits */
+      __IO uint32_t bPWRMD              	:	2;  /* ADC14 power modes */
+      __IO uint32_t bREFBURST           	:	1;  /* ADC14 reference buffer burst */
+      __IO uint32_t bDF                 	:	1;  /* ADC14 data read-back format */
+      __IO uint32_t bRES                	:	2;  /* ADC14 resolution */
+      __I  uint32_t bRESERVED0          	:	10;  /* Reserved */
+      __IO uint32_t bCSTARTADD          	:	5;  /* ADC14 conversion start address */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bBATMAP             	:	1;  /* Controls 1/2 AVCC ADC input channel selection */
+      __IO uint32_t bTCMAP              	:	1;  /* Controls temperature sensor ADC input channel selection */
+      __IO uint32_t bCH0MAP             	:	1;  /* Controls internal channel 0 selection to ADC input channel MAX-2 */
+      __IO uint32_t bCH1MAP             	:	1;  /* Controls internal channel 1 selection to ADC input channel MAX-3 */
+      __IO uint32_t bCH2MAP             	:	1;  /* Controls internal channel 2 selection to ADC input channel MAX-4 */
+      __IO uint32_t bCH3MAP             	:	1;  /* Controls internal channel 3 selection to ADC input channel MAX-5 */
+      __I  uint32_t bRESERVED2          	:	4;  /* Reserved */
+    } b;
+  } rCTL1;
+  union {    /* ADC14LO0 Register */
+    __IO uint32_t r;
+    struct { /* ADC14LO0 Bits */
+      __IO uint32_t bLO0                	:	16;  /* Low threshold 0 */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rLO0;
+  union {    /* ADC14HI0 Register */
+    __IO uint32_t r;
+    struct { /* ADC14HI0 Bits */
+      __IO uint32_t bHI0                	:	16;  /* High threshold 0 */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rHI0;
+  union {    /* ADC14LO1 Register */
+    __IO uint32_t r;
+    struct { /* ADC14LO1 Bits */
+      __IO uint32_t bLO1                	:	16;  /* Low threshold 1 */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rLO1;
+  union {    /* ADC14HI1 Register */
+    __IO uint32_t r;
+    struct { /* ADC14HI1 Bits */
+      __IO uint32_t bHI1                	:	16;  /* High threshold 1 */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rHI1;
+  union {    /* ADC14MCTL0 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MCTL0 Bits */
+      __IO uint32_t bINCH               	:	5;  /* Input channel select */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bEOS                	:	1;  /* End of sequence */
+      __IO uint32_t bVRSEL              	:	4;  /* Selects combinations of V(R+) and V(R-) sources */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bDIF                	:	1;  /* Differential mode */
+      __IO uint32_t bWINC               	:	1;  /* Comparator window enable */
+      __IO uint32_t bWINCTH             	:	1;  /* Window comparator threshold register selection */
+      __I  uint32_t bRESERVED2          	:	16;  /* Reserved */
+    } b;
+  } rMCTL0;
+  union {    /* ADC14MCTL1 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MCTL1 Bits */
+      __IO uint32_t bINCH               	:	5;  /* Input channel select */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bEOS                	:	1;  /* End of sequence */
+      __IO uint32_t bVRSEL              	:	4;  /* Selects combinations of V(R+) and V(R-) sources */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bDIF                	:	1;  /* Differential mode */
+      __IO uint32_t bWINC               	:	1;  /* Comparator window enable */
+      __IO uint32_t bWINCTH             	:	1;  /* Window comparator threshold register selection */
+      __I  uint32_t bRESERVED2          	:	16;  /* Reserved */
+    } b;
+  } rMCTL1;
+  union {    /* ADC14MCTL2 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MCTL2 Bits */
+      __IO uint32_t bINCH               	:	5;  /* Input channel select */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bEOS                	:	1;  /* End of sequence */
+      __IO uint32_t bVRSEL              	:	4;  /* Selects combinations of V(R+) and V(R-) sources */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bDIF                	:	1;  /* Differential mode */
+      __IO uint32_t bWINC               	:	1;  /* Comparator window enable */
+      __IO uint32_t bWINCTH             	:	1;  /* Window comparator threshold register selection */
+      __I  uint32_t bRESERVED2          	:	16;  /* Reserved */
+    } b;
+  } rMCTL2;
+  union {    /* ADC14MCTL3 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MCTL3 Bits */
+      __IO uint32_t bINCH               	:	5;  /* Input channel select */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bEOS                	:	1;  /* End of sequence */
+      __IO uint32_t bVRSEL              	:	4;  /* Selects combinations of V(R+) and V(R-) sources */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bDIF                	:	1;  /* Differential mode */
+      __IO uint32_t bWINC               	:	1;  /* Comparator window enable */
+      __IO uint32_t bWINCTH             	:	1;  /* Window comparator threshold register selection */
+      __I  uint32_t bRESERVED2          	:	16;  /* Reserved */
+    } b;
+  } rMCTL3;
+  union {    /* ADC14MCTL4 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MCTL4 Bits */
+      __IO uint32_t bINCH               	:	5;  /* Input channel select */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bEOS                	:	1;  /* End of sequence */
+      __IO uint32_t bVRSEL              	:	4;  /* Selects combinations of V(R+) and V(R-) sources */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bDIF                	:	1;  /* Differential mode */
+      __IO uint32_t bWINC               	:	1;  /* Comparator window enable */
+      __IO uint32_t bWINCTH             	:	1;  /* Window comparator threshold register selection */
+      __I  uint32_t bRESERVED2          	:	16;  /* Reserved */
+    } b;
+  } rMCTL4;
+  union {    /* ADC14MCTL5 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MCTL5 Bits */
+      __IO uint32_t bINCH               	:	5;  /* Input channel select */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bEOS                	:	1;  /* End of sequence */
+      __IO uint32_t bVRSEL              	:	4;  /* Selects combinations of V(R+) and V(R-) sources */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bDIF                	:	1;  /* Differential mode */
+      __IO uint32_t bWINC               	:	1;  /* Comparator window enable */
+      __IO uint32_t bWINCTH             	:	1;  /* Window comparator threshold register selection */
+      __I  uint32_t bRESERVED2          	:	16;  /* Reserved */
+    } b;
+  } rMCTL5;
+  union {    /* ADC14MCTL6 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MCTL6 Bits */
+      __IO uint32_t bINCH               	:	5;  /* Input channel select */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bEOS                	:	1;  /* End of sequence */
+      __IO uint32_t bVRSEL              	:	4;  /* Selects combinations of V(R+) and V(R-) sources */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bDIF                	:	1;  /* Differential mode */
+      __IO uint32_t bWINC               	:	1;  /* Comparator window enable */
+      __IO uint32_t bWINCTH             	:	1;  /* Window comparator threshold register selection */
+      __I  uint32_t bRESERVED2          	:	16;  /* Reserved */
+    } b;
+  } rMCTL6;
+  union {    /* ADC14MCTL7 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MCTL7 Bits */
+      __IO uint32_t bINCH               	:	5;  /* Input channel select */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bEOS                	:	1;  /* End of sequence */
+      __IO uint32_t bVRSEL              	:	4;  /* Selects combinations of V(R+) and V(R-) sources */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bDIF                	:	1;  /* Differential mode */
+      __IO uint32_t bWINC               	:	1;  /* Comparator window enable */
+      __IO uint32_t bWINCTH             	:	1;  /* Window comparator threshold register selection */
+      __I  uint32_t bRESERVED2          	:	16;  /* Reserved */
+    } b;
+  } rMCTL7;
+  union {    /* ADC14MCTL8 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MCTL8 Bits */
+      __IO uint32_t bINCH               	:	5;  /* Input channel select */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bEOS                	:	1;  /* End of sequence */
+      __IO uint32_t bVRSEL              	:	4;  /* Selects combinations of V(R+) and V(R-) sources */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bDIF                	:	1;  /* Differential mode */
+      __IO uint32_t bWINC               	:	1;  /* Comparator window enable */
+      __IO uint32_t bWINCTH             	:	1;  /* Window comparator threshold register selection */
+      __I  uint32_t bRESERVED2          	:	16;  /* Reserved */
+    } b;
+  } rMCTL8;
+  union {    /* ADC14MCTL9 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MCTL9 Bits */
+      __IO uint32_t bINCH               	:	5;  /* Input channel select */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bEOS                	:	1;  /* End of sequence */
+      __IO uint32_t bVRSEL              	:	4;  /* Selects combinations of V(R+) and V(R-) sources */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bDIF                	:	1;  /* Differential mode */
+      __IO uint32_t bWINC               	:	1;  /* Comparator window enable */
+      __IO uint32_t bWINCTH             	:	1;  /* Window comparator threshold register selection */
+      __I  uint32_t bRESERVED2          	:	16;  /* Reserved */
+    } b;
+  } rMCTL9;
+  union {    /* ADC14MCTL10 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MCTL10 Bits */
+      __IO uint32_t bINCH               	:	5;  /* Input channel select */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bEOS                	:	1;  /* End of sequence */
+      __IO uint32_t bVRSEL              	:	4;  /* Selects combinations of V(R+) and V(R-) sources */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bDIF                	:	1;  /* Differential mode */
+      __IO uint32_t bWINC               	:	1;  /* Comparator window enable */
+      __IO uint32_t bWINCTH             	:	1;  /* Window comparator threshold register selection */
+      __I  uint32_t bRESERVED2          	:	16;  /* Reserved */
+    } b;
+  } rMCTL10;
+  union {    /* ADC14MCTL11 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MCTL11 Bits */
+      __IO uint32_t bINCH               	:	5;  /* Input channel select */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bEOS                	:	1;  /* End of sequence */
+      __IO uint32_t bVRSEL              	:	4;  /* Selects combinations of V(R+) and V(R-) sources */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bDIF                	:	1;  /* Differential mode */
+      __IO uint32_t bWINC               	:	1;  /* Comparator window enable */
+      __IO uint32_t bWINCTH             	:	1;  /* Window comparator threshold register selection */
+      __I  uint32_t bRESERVED2          	:	16;  /* Reserved */
+    } b;
+  } rMCTL11;
+  union {    /* ADC14MCTL12 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MCTL12 Bits */
+      __IO uint32_t bINCH               	:	5;  /* Input channel select */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bEOS                	:	1;  /* End of sequence */
+      __IO uint32_t bVRSEL              	:	4;  /* Selects combinations of V(R+) and V(R-) sources */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bDIF                	:	1;  /* Differential mode */
+      __IO uint32_t bWINC               	:	1;  /* Comparator window enable */
+      __IO uint32_t bWINCTH             	:	1;  /* Window comparator threshold register selection */
+      __I  uint32_t bRESERVED2          	:	16;  /* Reserved */
+    } b;
+  } rMCTL12;
+  union {    /* ADC14MCTL13 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MCTL13 Bits */
+      __IO uint32_t bINCH               	:	5;  /* Input channel select */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bEOS                	:	1;  /* End of sequence */
+      __IO uint32_t bVRSEL              	:	4;  /* Selects combinations of V(R+) and V(R-) sources */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bDIF                	:	1;  /* Differential mode */
+      __IO uint32_t bWINC               	:	1;  /* Comparator window enable */
+      __IO uint32_t bWINCTH             	:	1;  /* Window comparator threshold register selection */
+      __I  uint32_t bRESERVED2          	:	16;  /* Reserved */
+    } b;
+  } rMCTL13;
+  union {    /* ADC14MCTL14 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MCTL14 Bits */
+      __IO uint32_t bINCH               	:	5;  /* Input channel select */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bEOS                	:	1;  /* End of sequence */
+      __IO uint32_t bVRSEL              	:	4;  /* Selects combinations of V(R+) and V(R-) sources */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bDIF                	:	1;  /* Differential mode */
+      __IO uint32_t bWINC               	:	1;  /* Comparator window enable */
+      __IO uint32_t bWINCTH             	:	1;  /* Window comparator threshold register selection */
+      __I  uint32_t bRESERVED2          	:	16;  /* Reserved */
+    } b;
+  } rMCTL14;
+  union {    /* ADC14MCTL15 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MCTL15 Bits */
+      __IO uint32_t bINCH               	:	5;  /* Input channel select */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bEOS                	:	1;  /* End of sequence */
+      __IO uint32_t bVRSEL              	:	4;  /* Selects combinations of V(R+) and V(R-) sources */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bDIF                	:	1;  /* Differential mode */
+      __IO uint32_t bWINC               	:	1;  /* Comparator window enable */
+      __IO uint32_t bWINCTH             	:	1;  /* Window comparator threshold register selection */
+      __I  uint32_t bRESERVED2          	:	16;  /* Reserved */
+    } b;
+  } rMCTL15;
+  union {    /* ADC14MCTL16 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MCTL16 Bits */
+      __IO uint32_t bINCH               	:	5;  /* Input channel select */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bEOS                	:	1;  /* End of sequence */
+      __IO uint32_t bVRSEL              	:	4;  /* Selects combinations of V(R+) and V(R-) sources */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bDIF                	:	1;  /* Differential mode */
+      __IO uint32_t bWINC               	:	1;  /* Comparator window enable */
+      __IO uint32_t bWINCTH             	:	1;  /* Window comparator threshold register selection */
+      __I  uint32_t bRESERVED2          	:	16;  /* Reserved */
+    } b;
+  } rMCTL16;
+  union {    /* ADC14MCTL17 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MCTL17 Bits */
+      __IO uint32_t bINCH               	:	5;  /* Input channel select */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bEOS                	:	1;  /* End of sequence */
+      __IO uint32_t bVRSEL              	:	4;  /* Selects combinations of V(R+) and V(R-) sources */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bDIF                	:	1;  /* Differential mode */
+      __IO uint32_t bWINC               	:	1;  /* Comparator window enable */
+      __IO uint32_t bWINCTH             	:	1;  /* Window comparator threshold register selection */
+      __I  uint32_t bRESERVED2          	:	16;  /* Reserved */
+    } b;
+  } rMCTL17;
+  union {    /* ADC14MCTL18 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MCTL18 Bits */
+      __IO uint32_t bINCH               	:	5;  /* Input channel select */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bEOS                	:	1;  /* End of sequence */
+      __IO uint32_t bVRSEL              	:	4;  /* Selects combinations of V(R+) and V(R-) sources */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bDIF                	:	1;  /* Differential mode */
+      __IO uint32_t bWINC               	:	1;  /* Comparator window enable */
+      __IO uint32_t bWINCTH             	:	1;  /* Window comparator threshold register selection */
+      __I  uint32_t bRESERVED2          	:	16;  /* Reserved */
+    } b;
+  } rMCTL18;
+  union {    /* ADC14MCTL19 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MCTL19 Bits */
+      __IO uint32_t bINCH               	:	5;  /* Input channel select */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bEOS                	:	1;  /* End of sequence */
+      __IO uint32_t bVRSEL              	:	4;  /* Selects combinations of V(R+) and V(R-) sources */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bDIF                	:	1;  /* Differential mode */
+      __IO uint32_t bWINC               	:	1;  /* Comparator window enable */
+      __IO uint32_t bWINCTH             	:	1;  /* Window comparator threshold register selection */
+      __I  uint32_t bRESERVED2          	:	16;  /* Reserved */
+    } b;
+  } rMCTL19;
+  union {    /* ADC14MCTL20 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MCTL20 Bits */
+      __IO uint32_t bINCH               	:	5;  /* Input channel select */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bEOS                	:	1;  /* End of sequence */
+      __IO uint32_t bVRSEL              	:	4;  /* Selects combinations of V(R+) and V(R-) sources */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bDIF                	:	1;  /* Differential mode */
+      __IO uint32_t bWINC               	:	1;  /* Comparator window enable */
+      __IO uint32_t bWINCTH             	:	1;  /* Window comparator threshold register selection */
+      __I  uint32_t bRESERVED2          	:	16;  /* Reserved */
+    } b;
+  } rMCTL20;
+  union {    /* ADC14MCTL21 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MCTL21 Bits */
+      __IO uint32_t bINCH               	:	5;  /* Input channel select */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bEOS                	:	1;  /* End of sequence */
+      __IO uint32_t bVRSEL              	:	4;  /* Selects combinations of V(R+) and V(R-) sources */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bDIF                	:	1;  /* Differential mode */
+      __IO uint32_t bWINC               	:	1;  /* Comparator window enable */
+      __IO uint32_t bWINCTH             	:	1;  /* Window comparator threshold register selection */
+      __I  uint32_t bRESERVED2          	:	16;  /* Reserved */
+    } b;
+  } rMCTL21;
+  union {    /* ADC14MCTL22 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MCTL22 Bits */
+      __IO uint32_t bINCH               	:	5;  /* Input channel select */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bEOS                	:	1;  /* End of sequence */
+      __IO uint32_t bVRSEL              	:	4;  /* Selects combinations of V(R+) and V(R-) sources */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bDIF                	:	1;  /* Differential mode */
+      __IO uint32_t bWINC               	:	1;  /* Comparator window enable */
+      __IO uint32_t bWINCTH             	:	1;  /* Window comparator threshold register selection */
+      __I  uint32_t bRESERVED2          	:	16;  /* Reserved */
+    } b;
+  } rMCTL22;
+  union {    /* ADC14MCTL23 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MCTL23 Bits */
+      __IO uint32_t bINCH               	:	5;  /* Input channel select */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bEOS                	:	1;  /* End of sequence */
+      __IO uint32_t bVRSEL              	:	4;  /* Selects combinations of V(R+) and V(R-) sources */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bDIF                	:	1;  /* Differential mode */
+      __IO uint32_t bWINC               	:	1;  /* Comparator window enable */
+      __IO uint32_t bWINCTH             	:	1;  /* Window comparator threshold register selection */
+      __I  uint32_t bRESERVED2          	:	16;  /* Reserved */
+    } b;
+  } rMCTL23;
+  union {    /* ADC14MCTL24 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MCTL24 Bits */
+      __IO uint32_t bINCH               	:	5;  /* Input channel select */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bEOS                	:	1;  /* End of sequence */
+      __IO uint32_t bVRSEL              	:	4;  /* Selects combinations of V(R+) and V(R-) sources */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bDIF                	:	1;  /* Differential mode */
+      __IO uint32_t bWINC               	:	1;  /* Comparator window enable */
+      __IO uint32_t bWINCTH             	:	1;  /* Window comparator threshold register selection */
+      __I  uint32_t bRESERVED2          	:	16;  /* Reserved */
+    } b;
+  } rMCTL24;
+  union {    /* ADC14MCTL25 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MCTL25 Bits */
+      __IO uint32_t bINCH               	:	5;  /* Input channel select */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bEOS                	:	1;  /* End of sequence */
+      __IO uint32_t bVRSEL              	:	4;  /* Selects combinations of V(R+) and V(R-) sources */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bDIF                	:	1;  /* Differential mode */
+      __IO uint32_t bWINC               	:	1;  /* Comparator window enable */
+      __IO uint32_t bWINCTH             	:	1;  /* Window comparator threshold register selection */
+      __I  uint32_t bRESERVED2          	:	16;  /* Reserved */
+    } b;
+  } rMCTL25;
+  union {    /* ADC14MCTL26 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MCTL26 Bits */
+      __IO uint32_t bINCH               	:	5;  /* Input channel select */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bEOS                	:	1;  /* End of sequence */
+      __IO uint32_t bVRSEL              	:	4;  /* Selects combinations of V(R+) and V(R-) sources */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bDIF                	:	1;  /* Differential mode */
+      __IO uint32_t bWINC               	:	1;  /* Comparator window enable */
+      __IO uint32_t bWINCTH             	:	1;  /* Window comparator threshold register selection */
+      __I  uint32_t bRESERVED2          	:	16;  /* Reserved */
+    } b;
+  } rMCTL26;
+  union {    /* ADC14MCTL27 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MCTL27 Bits */
+      __IO uint32_t bINCH               	:	5;  /* Input channel select */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bEOS                	:	1;  /* End of sequence */
+      __IO uint32_t bVRSEL              	:	4;  /* Selects combinations of V(R+) and V(R-) sources */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bDIF                	:	1;  /* Differential mode */
+      __IO uint32_t bWINC               	:	1;  /* Comparator window enable */
+      __IO uint32_t bWINCTH             	:	1;  /* Window comparator threshold register selection */
+      __I  uint32_t bRESERVED2          	:	16;  /* Reserved */
+    } b;
+  } rMCTL27;
+  union {    /* ADC14MCTL28 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MCTL28 Bits */
+      __IO uint32_t bINCH               	:	5;  /* Input channel select */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bEOS                	:	1;  /* End of sequence */
+      __IO uint32_t bVRSEL              	:	4;  /* Selects combinations of V(R+) and V(R-) sources */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bDIF                	:	1;  /* Differential mode */
+      __IO uint32_t bWINC               	:	1;  /* Comparator window enable */
+      __IO uint32_t bWINCTH             	:	1;  /* Window comparator threshold register selection */
+      __I  uint32_t bRESERVED2          	:	16;  /* Reserved */
+    } b;
+  } rMCTL28;
+  union {    /* ADC14MCTL29 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MCTL29 Bits */
+      __IO uint32_t bINCH               	:	5;  /* Input channel select */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bEOS                	:	1;  /* End of sequence */
+      __IO uint32_t bVRSEL              	:	4;  /* Selects combinations of V(R+) and V(R-) sources */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bDIF                	:	1;  /* Differential mode */
+      __IO uint32_t bWINC               	:	1;  /* Comparator window enable */
+      __IO uint32_t bWINCTH             	:	1;  /* Window comparator threshold register selection */
+      __I  uint32_t bRESERVED2          	:	16;  /* Reserved */
+    } b;
+  } rMCTL29;
+  union {    /* ADC14MCTL30 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MCTL30 Bits */
+      __IO uint32_t bINCH               	:	5;  /* Input channel select */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bEOS                	:	1;  /* End of sequence */
+      __IO uint32_t bVRSEL              	:	4;  /* Selects combinations of V(R+) and V(R-) sources */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bDIF                	:	1;  /* Differential mode */
+      __IO uint32_t bWINC               	:	1;  /* Comparator window enable */
+      __IO uint32_t bWINCTH             	:	1;  /* Window comparator threshold register selection */
+      __I  uint32_t bRESERVED2          	:	16;  /* Reserved */
+    } b;
+  } rMCTL30;
+  union {    /* ADC14MCTL31 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MCTL31 Bits */
+      __IO uint32_t bINCH               	:	5;  /* Input channel select */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bEOS                	:	1;  /* End of sequence */
+      __IO uint32_t bVRSEL              	:	4;  /* Selects combinations of V(R+) and V(R-) sources */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bDIF                	:	1;  /* Differential mode */
+      __IO uint32_t bWINC               	:	1;  /* Comparator window enable */
+      __IO uint32_t bWINCTH             	:	1;  /* Window comparator threshold register selection */
+      __I  uint32_t bRESERVED2          	:	16;  /* Reserved */
+    } b;
+  } rMCTL31;
+  union {    /* ADC14MEM0 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MEM0 Bits */
+      __IO uint32_t bCONVRES            	:	16;  /* Conversion Result */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rMEM0;
+  union {    /* ADC14MEM1 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MEM1 Bits */
+      __IO uint32_t bCONVRES            	:	16;  /* Conversion Result */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rMEM1;
+  union {    /* ADC14MEM2 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MEM2 Bits */
+      __IO uint32_t bCONVRES            	:	16;  /* Conversion Result */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rMEM2;
+  union {    /* ADC14MEM3 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MEM3 Bits */
+      __IO uint32_t bCONVRES            	:	16;  /* Conversion Result */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rMEM3;
+  union {    /* ADC14MEM4 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MEM4 Bits */
+      __IO uint32_t bCONVRES            	:	16;  /* Conversion Result */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rMEM4;
+  union {    /* ADC14MEM5 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MEM5 Bits */
+      __IO uint32_t bCONVRES            	:	16;  /* Conversion Result */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rMEM5;
+  union {    /* ADC14MEM6 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MEM6 Bits */
+      __IO uint32_t bCONVRES            	:	16;  /* Conversion Result */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rMEM6;
+  union {    /* ADC14MEM7 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MEM7 Bits */
+      __IO uint32_t bCONVRES            	:	16;  /* Conversion Result */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rMEM7;
+  union {    /* ADC14MEM8 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MEM8 Bits */
+      __IO uint32_t bCONVRES            	:	16;  /* Conversion Result */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rMEM8;
+  union {    /* ADC14MEM9 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MEM9 Bits */
+      __IO uint32_t bCONVRES            	:	16;  /* Conversion Result */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rMEM9;
+  union {    /* ADC14MEM10 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MEM10 Bits */
+      __IO uint32_t bCONVRES            	:	16;  /* Conversion Result */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rMEM10;
+  union {    /* ADC14MEM11 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MEM11 Bits */
+      __IO uint32_t bCONVRES            	:	16;  /* Conversion Result */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rMEM11;
+  union {    /* ADC14MEM12 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MEM12 Bits */
+      __IO uint32_t bCONVRES            	:	16;  /* Conversion Result */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rMEM12;
+  union {    /* ADC14MEM13 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MEM13 Bits */
+      __IO uint32_t bCONVRES            	:	16;  /* Conversion Result */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rMEM13;
+  union {    /* ADC14MEM14 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MEM14 Bits */
+      __IO uint32_t bCONVRES            	:	16;  /* Conversion Result */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rMEM14;
+  union {    /* ADC14MEM15 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MEM15 Bits */
+      __IO uint32_t bCONVRES            	:	16;  /* Conversion Result */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rMEM15;
+  union {    /* ADC14MEM16 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MEM16 Bits */
+      __IO uint32_t bCONVRES            	:	16;  /* Conversion Result */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rMEM16;
+  union {    /* ADC14MEM17 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MEM17 Bits */
+      __IO uint32_t bCONVRES            	:	16;  /* Conversion Result */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rMEM17;
+  union {    /* ADC14MEM18 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MEM18 Bits */
+      __IO uint32_t bCONVRES            	:	16;  /* Conversion Result */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rMEM18;
+  union {    /* ADC14MEM19 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MEM19 Bits */
+      __IO uint32_t bCONVRES            	:	16;  /* Conversion Result */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rMEM19;
+  union {    /* ADC14MEM20 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MEM20 Bits */
+      __IO uint32_t bCONVRES            	:	16;  /* Conversion Result */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rMEM20;
+  union {    /* ADC14MEM21 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MEM21 Bits */
+      __IO uint32_t bCONVRES            	:	16;  /* Conversion Result */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rMEM21;
+  union {    /* ADC14MEM22 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MEM22 Bits */
+      __IO uint32_t bCONVRES            	:	16;  /* Conversion Result */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rMEM22;
+  union {    /* ADC14MEM23 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MEM23 Bits */
+      __IO uint32_t bCONVRES            	:	16;  /* Conversion Result */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rMEM23;
+  union {    /* ADC14MEM24 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MEM24 Bits */
+      __IO uint32_t bCONVRES            	:	16;  /* Conversion Result */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rMEM24;
+  union {    /* ADC14MEM25 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MEM25 Bits */
+      __IO uint32_t bCONVRES            	:	16;  /* Conversion Result */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rMEM25;
+  union {    /* ADC14MEM26 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MEM26 Bits */
+      __IO uint32_t bCONVRES            	:	16;  /* Conversion Result */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rMEM26;
+  union {    /* ADC14MEM27 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MEM27 Bits */
+      __IO uint32_t bCONVRES            	:	16;  /* Conversion Result */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rMEM27;
+  union {    /* ADC14MEM28 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MEM28 Bits */
+      __IO uint32_t bCONVRES            	:	16;  /* Conversion Result */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rMEM28;
+  union {    /* ADC14MEM29 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MEM29 Bits */
+      __IO uint32_t bCONVRES            	:	16;  /* Conversion Result */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rMEM29;
+  union {    /* ADC14MEM30 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MEM30 Bits */
+      __IO uint32_t bCONVRES            	:	16;  /* Conversion Result */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rMEM30;
+  union {    /* ADC14MEM31 Register */
+    __IO uint32_t r;
+    struct { /* ADC14MEM31 Bits */
+      __IO uint32_t bCONVRES            	:	16;  /* Conversion Result */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rMEM31;
+  uint8_t  RESERVED0[36];
+  union {    /* ADC14IER0 Register */
+    __IO uint32_t r;
+    struct { /* ADC14IER0 Bits */
+      __IO uint32_t bIE0                	:	1;  /* Interrupt enable */
+      __IO uint32_t bIE1                	:	1;  /* Interrupt enable */
+      __IO uint32_t bIE2                	:	1;  /* Interrupt enable */
+      __IO uint32_t bIE3                	:	1;  /* Interrupt enable */
+      __IO uint32_t bIE4                	:	1;  /* Interrupt enable */
+      __IO uint32_t bIE5                	:	1;  /* Interrupt enable */
+      __IO uint32_t bIE6                	:	1;  /* Interrupt enable */
+      __IO uint32_t bIE7                	:	1;  /* Interrupt enable */
+      __IO uint32_t bIE8                	:	1;  /* Interrupt enable */
+      __IO uint32_t bIE9                	:	1;  /* Interrupt enable */
+      __IO uint32_t bIE10               	:	1;  /* Interrupt enable */
+      __IO uint32_t bIE11               	:	1;  /* Interrupt enable */
+      __IO uint32_t bIE12               	:	1;  /* Interrupt enable */
+      __IO uint32_t bIE13               	:	1;  /* Interrupt enable */
+      __IO uint32_t bIE14               	:	1;  /* Interrupt enable */
+      __IO uint32_t bIE15               	:	1;  /* Interrupt enable */
+      __IO uint32_t bIE16               	:	1;  /* Interrupt enable */
+      __IO uint32_t bIE17               	:	1;  /* Interrupt enable */
+      __IO uint32_t bIE18               	:	1;  /* Interrupt enable */
+      __IO uint32_t bIE19               	:	1;  /* Interrupt enable */
+      __IO uint32_t bIE20               	:	1;  /* Interrupt enable */
+      __IO uint32_t bIE21               	:	1;  /* Interrupt enable */
+      __IO uint32_t bIE22               	:	1;  /* Interrupt enable */
+      __IO uint32_t bIE23               	:	1;  /* Interrupt enable */
+      __IO uint32_t bIE24               	:	1;  /* Interrupt enable */
+      __IO uint32_t bIE25               	:	1;  /* Interrupt enable */
+      __IO uint32_t bIE26               	:	1;  /* Interrupt enable */
+      __IO uint32_t bIE27               	:	1;  /* Interrupt enable */
+      __IO uint32_t bIE28               	:	1;  /* Interrupt enable */
+      __IO uint32_t bIE29               	:	1;  /* Interrupt enable */
+      __IO uint32_t bIE30               	:	1;  /* Interrupt enable */
+      __IO uint32_t bIE31               	:	1;  /* Interrupt enable */
+    } b;
+  } rIER0;
+  union {    /* ADC14IER1 Register */
+    __IO uint32_t r;
+    struct { /* ADC14IER1 Bits */
+      __I  uint32_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint32_t bINIE               	:	1;  /* Interrupt enable for ADC14MEMx within comparator window */
+      __IO uint32_t bLOIE               	:	1;  /* Interrupt enable for ADC14MEMx below comparator window */
+      __IO uint32_t bHIIE               	:	1;  /* Interrupt enable for ADC14MEMx above comparator window */
+      __IO uint32_t bOVIE               	:	1;  /* ADC14MEMx overflow-interrupt enable */
+      __IO uint32_t bTOVIE              	:	1;  /* ADC14 conversion-time-overflow interrupt enable */
+      __IO uint32_t bRDYIE              	:	1;  /* ADC14 local buffered reference ready interrupt enable */
+      __I  uint32_t bRESERVED1          	:	25;  /* Reserved */
+    } b;
+  } rIER1;
+  union {    /* ADC14IFGR0 Register */
+    __I uint32_t r;
+    struct { /* ADC14IFGR0 Bits */
+      __I  uint32_t bIFG0               	:	1;  /* ADC14MEM0 interrupt flag */
+      __I  uint32_t bIFG1               	:	1;  /* ADC14MEM1 interrupt flag */
+      __I  uint32_t bIFG2               	:	1;  /* ADC14MEM2 interrupt flag */
+      __I  uint32_t bIFG3               	:	1;  /* ADC14MEM3 interrupt flag */
+      __I  uint32_t bIFG4               	:	1;  /* ADC14MEM4 interrupt flag */
+      __I  uint32_t bIFG5               	:	1;  /* ADC14MEM5 interrupt flag */
+      __I  uint32_t bIFG6               	:	1;  /* ADC14MEM6 interrupt flag */
+      __I  uint32_t bIFG7               	:	1;  /* ADC14MEM7 interrupt flag */
+      __I  uint32_t bIFG8               	:	1;  /* ADC14MEM8 interrupt flag */
+      __I  uint32_t bIFG9               	:	1;  /* ADC14MEM9 interrupt flag */
+      __I  uint32_t bIFG10              	:	1;  /* ADC14MEM10 interrupt flag */
+      __I  uint32_t bIFG11              	:	1;  /* ADC14MEM11 interrupt flag */
+      __I  uint32_t bIFG12              	:	1;  /* ADC14MEM12 interrupt flag */
+      __I  uint32_t bIFG13              	:	1;  /* ADC14MEM13 interrupt flag */
+      __I  uint32_t bIFG14              	:	1;  /* ADC14MEM14 interrupt flag */
+      __I  uint32_t bIFG15              	:	1;  /* ADC14MEM15 interrupt flag */
+      __I  uint32_t bIFG16              	:	1;  /* ADC14MEM16 interrupt flag */
+      __I  uint32_t bIFG17              	:	1;  /* ADC14MEM17 interrupt flag */
+      __I  uint32_t bIFG18              	:	1;  /* ADC14MEM18 interrupt flag */
+      __I  uint32_t bIFG19              	:	1;  /* ADC14MEM19 interrupt flag */
+      __I  uint32_t bIFG20              	:	1;  /* ADC14MEM20 interrupt flag */
+      __I  uint32_t bIFG21              	:	1;  /* ADC14MEM21 interrupt flag */
+      __I  uint32_t bIFG22              	:	1;  /* ADC14MEM22 interrupt flag */
+      __I  uint32_t bIFG23              	:	1;  /* ADC14MEM23 interrupt flag */
+      __I  uint32_t bIFG24              	:	1;  /* ADC14MEM24 interrupt flag */
+      __I  uint32_t bIFG25              	:	1;  /* ADC14MEM25 interrupt flag */
+      __I  uint32_t bIFG26              	:	1;  /* ADC14MEM26 interrupt flag */
+      __I  uint32_t bIFG27              	:	1;  /* ADC14MEM27 interrupt flag */
+      __I  uint32_t bIFG28              	:	1;  /* ADC14MEM28 interrupt flag */
+      __I  uint32_t bIFG29              	:	1;  /* ADC14MEM29 interrupt flag */
+      __I  uint32_t bIFG30              	:	1;  /* ADC14MEM30 interrupt flag */
+      __I  uint32_t bIFG31              	:	1;  /* ADC14MEM31 interrupt flag */
+    } b;
+  } rIFGR0;
+  union {    /* ADC14IFGR1 Register */
+    __I uint32_t r;
+    struct { /* ADC14IFGR1 Bits */
+      __I  uint32_t bRESERVED0          	:	1;  /* Reserved */
+      __I  uint32_t bINIFG              	:	1;  /* Interrupt flag for ADC14MEMx within comparator window */
+      __I  uint32_t bLOIFG              	:	1;  /* Interrupt flag for ADC14MEMx below comparator window */
+      __I  uint32_t bHIIFG              	:	1;  /* Interrupt flag for ADC14MEMx above comparator window */
+      __I  uint32_t bOVIFG              	:	1;  /* ADC14MEMx overflow interrupt flag */
+      __I  uint32_t bTOVIFG             	:	1;  /* ADC14 conversion time overflow interrupt flag */
+      __I  uint32_t bRDYIFG             	:	1;  /* ADC14 local buffered reference ready interrupt flag */
+      __I  uint32_t bRESERVED1          	:	25;  /* Reserved */
+    } b;
+  } rIFGR1;
+  union {    /* ADC14CLRIFGR0 Register */
+    __O uint32_t r;
+    struct { /* ADC14CLRIFGR0 Bits */
+      __O  uint32_t bCLRIFG0            	:	1;  /* clear ADC14IFG0 */
+      __O  uint32_t bCLRIFG1            	:	1;  /* clear ADC14IFG1 */
+      __O  uint32_t bCLRIFG2            	:	1;  /* clear ADC14IFG2 */
+      __O  uint32_t bCLRIFG3            	:	1;  /* clear ADC14IFG3 */
+      __O  uint32_t bCLRIFG4            	:	1;  /* clear ADC14IFG4 */
+      __O  uint32_t bCLRIFG5            	:	1;  /* clear ADC14IFG5 */
+      __O  uint32_t bCLRIFG6            	:	1;  /* clear ADC14IFG6 */
+      __O  uint32_t bCLRIFG7            	:	1;  /* clear ADC14IFG7 */
+      __O  uint32_t bCLRIFG8            	:	1;  /* clear ADC14IFG8 */
+      __O  uint32_t bCLRIFG9            	:	1;  /* clear ADC14IFG9 */
+      __O  uint32_t bCLRIFG10           	:	1;  /* clear ADC14IFG10 */
+      __O  uint32_t bCLRIFG11           	:	1;  /* clear ADC14IFG11 */
+      __O  uint32_t bCLRIFG12           	:	1;  /* clear ADC14IFG12 */
+      __O  uint32_t bCLRIFG13           	:	1;  /* clear ADC14IFG13 */
+      __O  uint32_t bCLRIFG14           	:	1;  /* clear ADC14IFG14 */
+      __O  uint32_t bCLRIFG15           	:	1;  /* clear ADC14IFG15 */
+      __O  uint32_t bCLRIFG16           	:	1;  /* clear ADC14IFG16 */
+      __O  uint32_t bCLRIFG17           	:	1;  /* clear ADC14IFG17 */
+      __O  uint32_t bCLRIFG18           	:	1;  /* clear ADC14IFG18 */
+      __O  uint32_t bCLRIFG19           	:	1;  /* clear ADC14IFG19 */
+      __O  uint32_t bCLRIFG20           	:	1;  /* clear ADC14IFG20 */
+      __O  uint32_t bCLRIFG21           	:	1;  /* clear ADC14IFG21 */
+      __O  uint32_t bCLRIFG22           	:	1;  /* clear ADC14IFG22 */
+      __O  uint32_t bCLRIFG23           	:	1;  /* clear ADC14IFG23 */
+      __O  uint32_t bCLRIFG24           	:	1;  /* clear ADC14IFG24 */
+      __O  uint32_t bCLRIFG25           	:	1;  /* clear ADC14IFG25 */
+      __O  uint32_t bCLRIFG26           	:	1;  /* clear ADC14IFG26 */
+      __O  uint32_t bCLRIFG27           	:	1;  /* clear ADC14IFG27 */
+      __O  uint32_t bCLRIFG28           	:	1;  /* clear ADC14IFG28 */
+      __O  uint32_t bCLRIFG29           	:	1;  /* clear ADC14IFG29 */
+      __O  uint32_t bCLRIFG30           	:	1;  /* clear ADC14IFG30 */
+      __O  uint32_t bCLRIFG31           	:	1;  /* clear ADC14IFG31 */
+    } b;
+  } rCLRIFGR0;
+  union {    /* ADC14CLRIFGR1 Register */
+    __IO uint32_t r;
+    struct { /* ADC14CLRIFGR1 Bits */
+      __I  uint32_t bRESERVED0          	:	1;  /* Reserved */
+      __O  uint32_t bCLRINIFG           	:	1;  /* clear ADC14INIFG */
+      __O  uint32_t bCLRLOIFG           	:	1;  /* clear ADC14LOIFG */
+      __O  uint32_t bCLRHIIFG           	:	1;  /* clear ADC14HIIFG */
+      __O  uint32_t bCLROVIFG           	:	1;  /* clear ADC14OVIFG */
+      __O  uint32_t bCLRTOVIFG          	:	1;  /* clear ADC14TOVIFG */
+      __O  uint32_t bCLRRDYIFG          	:	1;  /* clear ADC14RDYIFG */
+      __I  uint32_t bRESERVED1          	:	25;  /* Reserved */
+    } b;
+  } rCLRIFGR1;
+  __IO uint32_t rIV; /* Interrupt Vector Register */
+} ADC14_Type;
+
+
+//*****************************************************************************
+// AES256 Registers
+//*****************************************************************************
+typedef struct {
+  union {    /* AESACTL0 Register */
+    __IO uint16_t r;
+    struct { /* AESACTL0 Bits */
+      __IO uint16_t bOP                 	:	2;  /* AES operation */
+      __IO uint16_t bKL                 	:	2;  /* AES key length */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bCM                 	:	2;  /* AES cipher mode select */
+      __IO uint16_t bSWRST              	:	1;  /* AES software reset */
+      __IO uint16_t bRDYIFG             	:	1;  /* AES ready interrupt flag */
+      __I  uint16_t bRESERVED1          	:	2;  /* Reserved */
+      __IO uint16_t bERRFG              	:	1;  /* AES error flag */
+      __IO uint16_t bRDYIE              	:	1;  /* AES ready interrupt enable */
+      __I  uint16_t bRESERVED2          	:	2;  /* Reserved */
+      __IO uint16_t bCMEN               	:	1;  /* AES cipher mode enable */
+    } b;
+  } rCTL0;
+  union {    /* AESACTL1 Register */
+    __IO uint16_t r;
+    struct { /* AESACTL1 Bits */
+      __IO uint16_t bBLKCNT             	:	8;  /* Cipher Block Counter */
+      __I  uint16_t bRESERVED0          	:	8;  /* Reserved */
+    } b;
+  } rCTL1;
+  union {    /* AESASTAT Register */
+    __IO uint16_t r;
+    struct { /* AESASTAT Bits */
+      __IO uint16_t bBUSY               	:	1;  /* AES accelerator module busy */
+      __IO uint16_t bKEYWR              	:	1;  /* All 16 bytes written to AESAKEY */
+      __IO uint16_t bDINWR              	:	1;  /* All 16 bytes written to AESADIN, AESAXDIN or AESAXIN */
+      __I  uint16_t bDOUTRD             	:	1;  /* All 16 bytes read from AESADOUT */
+      __I  uint16_t bKEYCNT             	:	4;  /* Bytes written via AESAKEY for AESKLx=00, half-words written via AESAKEY */
+      __I  uint16_t bDINCNT             	:	4;  /* Bytes written via AESADIN, AESAXDIN or AESAXIN */
+      __I  uint16_t bDOUTCNT            	:	4;  /* Bytes read via AESADOUT */
+    } b;
+  } rSTAT;
+  union {    /* AESAKEY Register */
+    __O uint16_t r;
+    struct { /* AESAKEY Bits */
+      __O  uint16_t bKEY0               	:	8;  /* AES key byte n when AESAKEY is written as half-word */
+      __O  uint16_t bKEY1               	:	8;  /* AES key byte n+1 when AESAKEY is written as half-word */
+    } b;
+  } rKEY;
+  union {    /* AESADIN Register */
+    __O uint16_t r;
+    struct { /* AESADIN Bits */
+      __O  uint16_t bDIN0               	:	8;  /* AES data in byte n when AESADIN is written as half-word */
+      __O  uint16_t bDIN1               	:	8;  /* AES data in byte n+1 when AESADIN is written as half-word */
+    } b;
+  } rDIN;
+  union {    /* AESADOUT Register */
+    __O uint16_t r;
+    struct { /* AESADOUT Bits */
+      __O  uint16_t bDOUT0              	:	8;  /* AES data out byte n when AESADOUT is read as half-word */
+      __O  uint16_t bDOUT1              	:	8;  /* AES data out byte n+1 when AESADOUT is read as half-word */
+    } b;
+  } rDOUT;
+  union {    /* AESAXDIN Register */
+    __O uint16_t r;
+    struct { /* AESAXDIN Bits */
+      __O  uint16_t bXDIN0              	:	8;  /* AES data in byte n when AESAXDIN is written as half-word */
+      __O  uint16_t bXDIN1              	:	8;  /* AES data in byte n+1 when AESAXDIN is written as half-word */
+    } b;
+  } rXDIN;
+  union {    /* AESAXIN Register */
+    __O uint16_t r;
+    struct { /* AESAXIN Bits */
+      __O  uint16_t bXIN0               	:	8;  /* AES data in byte n when AESAXIN is written as half-word */
+      __O  uint16_t bXIN1               	:	8;  /* AES data in byte n+1 when AESAXIN is written as half-word */
+    } b;
+  } rXIN;
+} AES256_Type;
+
+
+//*****************************************************************************
+// CAPTIO0 Registers
+//*****************************************************************************
+typedef struct {
+  uint8_t  RESERVED0[14];
+  union {    /* CAPTIO0CTL Register */
+    __IO uint16_t r;
+    struct { /* CAPTIO0CTL Bits */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bPISEL              	:	3;  /* Capacitive Touch IO pin select */
+      __IO uint16_t bPOSEL              	:	4;  /* Capacitive Touch IO port select */
+      __IO uint16_t bEN                 	:	1;  /* Capacitive Touch IO enable */
+      __I  uint16_t bSTATE              	:	1;  /* Capacitive Touch IO state */
+      __I  uint16_t bRESERVED1          	:	6;  /* Reserved */
+    } b;
+  } rCTL;
+} CAPTIO0_Type;
+
+
+//*****************************************************************************
+// CAPTIO1 Registers
+//*****************************************************************************
+typedef struct {
+  uint8_t  RESERVED0[14];
+  union {    /* CAPTIO1CTL Register */
+    __IO uint16_t r;
+    struct { /* CAPTIO1CTL Bits */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bPISEL              	:	3;  /* Capacitive Touch IO pin select */
+      __IO uint16_t bPOSEL              	:	4;  /* Capacitive Touch IO port select */
+      __IO uint16_t bEN                 	:	1;  /* Capacitive Touch IO enable */
+      __I  uint16_t bSTATE              	:	1;  /* Capacitive Touch IO state */
+      __I  uint16_t bRESERVED1          	:	6;  /* Reserved */
+    } b;
+  } rCTL;
+} CAPTIO1_Type;
+
+
+//*****************************************************************************
+// COMP_E0 Registers
+//*****************************************************************************
+typedef struct {
+  union {    /* CE0CTL0 Register */
+    __IO uint16_t r;
+    struct { /* CE0CTL0 Bits */
+      __IO uint16_t bIPSEL              	:	4;  /* Channel input selected for the V+ terminal */
+      __I  uint16_t bRESERVED0          	:	3;  /* Reserved */
+      __IO uint16_t bIPEN               	:	1;  /* Channel input enable for the V+ terminal */
+      __IO uint16_t bIMSEL              	:	4;  /* Channel input selected for the - terminal */
+      __I  uint16_t bRESERVED1          	:	3;  /* Reserved */
+      __IO uint16_t bIMEN               	:	1;  /* Channel input enable for the - terminal */
+    } b;
+  } rCTL0;
+  union {    /* CE0CTL1 Register */
+    __IO uint16_t r;
+    struct { /* CE0CTL1 Bits */
+      __IO uint16_t bOUT                	:	1;  /* Comparator output value */
+      __IO uint16_t bOUTPOL             	:	1;  /* Comparator output polarity */
+      __IO uint16_t bF                  	:	1;  /* Comparator output filter */
+      __IO uint16_t bIES                	:	1;  /* Interrupt edge select for CEIIFG and CEIFG */
+      __IO uint16_t bSHORT              	:	1;  /* Input short */
+      __IO uint16_t bEX                 	:	1;  /* Exchange */
+      __IO uint16_t bFDLY               	:	2;  /* Filter delay */
+      __IO uint16_t bPWRMD              	:	2;  /* Power Mode */
+      __IO uint16_t bON                 	:	1;  /* Comparator On */
+      __IO uint16_t bMRVL               	:	1;  /* This bit is valid of CEMRVS is set to 1 */
+      __IO uint16_t bMRVS               	:	1;  /*  */
+      __I  uint16_t bRESERVED0          	:	3;  /* Reserved */
+    } b;
+  } rCTL1;
+  union {    /* CE0CTL2 Register */
+    __IO uint16_t r;
+    struct { /* CE0CTL2 Bits */
+      __IO uint16_t bREF0               	:	5;  /* Reference resistor tap 0 */
+      __IO uint16_t bRSEL               	:	1;  /* Reference select */
+      __IO uint16_t bRS                 	:	2;  /* Reference source */
+      __IO uint16_t bREF1               	:	5;  /* Reference resistor tap 1 */
+      __IO uint16_t bREFL               	:	2;  /* Reference voltage level */
+      __IO uint16_t bREFACC             	:	1;  /* Reference accuracy */
+    } b;
+  } rCTL2;
+  union {    /* CE0CTL3 Register */
+    __IO uint16_t r;
+    struct { /* CE0CTL3 Bits */
+      __IO uint16_t bPD0                	:	1;  /* Port disable */
+      __IO uint16_t bPD1                	:	1;  /* Port disable */
+      __IO uint16_t bPD2                	:	1;  /* Port disable */
+      __IO uint16_t bPD3                	:	1;  /* Port disable */
+      __IO uint16_t bPD4                	:	1;  /* Port disable */
+      __IO uint16_t bPD5                	:	1;  /* Port disable */
+      __IO uint16_t bPD6                	:	1;  /* Port disable */
+      __IO uint16_t bPD7                	:	1;  /* Port disable */
+      __IO uint16_t bPD8                	:	1;  /* Port disable */
+      __IO uint16_t bPD9                	:	1;  /* Port disable */
+      __IO uint16_t bPD10               	:	1;  /* Port disable */
+      __IO uint16_t bPD11               	:	1;  /* Port disable */
+      __IO uint16_t bPD12               	:	1;  /* Port disable */
+      __IO uint16_t bPD13               	:	1;  /* Port disable */
+      __IO uint16_t bPD14               	:	1;  /* Port disable */
+      __IO uint16_t bPD15               	:	1;  /* Port disable */
+    } b;
+  } rCTL3;
+  uint8_t  RESERVED0[4];
+  union {    /* CE0INT Register */
+    __IO uint16_t r;
+    struct { /* CE0INT Bits */
+      __IO uint16_t bIFG                	:	1;  /* Comparator output interrupt flag */
+      __IO uint16_t bIIFG               	:	1;  /* Comparator output inverted interrupt flag */
+      __I  uint16_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint16_t bRDYIFG             	:	1;  /* Comparator ready interrupt flag */
+      __I  uint16_t bRESERVED1          	:	3;  /* Reserved */
+      __IO uint16_t bIE                 	:	1;  /* Comparator output interrupt enable */
+      __IO uint16_t bIIE                	:	1;  /* Comparator output interrupt enable inverted polarity */
+      __I  uint16_t bRESERVED2          	:	2;  /* Reserved */
+      __IO uint16_t bRDYIE              	:	1;  /* Comparator ready interrupt enable */
+      __I  uint16_t bRESERVED3          	:	3;  /* Reserved */
+    } b;
+  } rINT;
+  __I uint16_t rIV; /* Comparator Interrupt Vector Word Register */
+} COMP_E0_Type;
+
+
+//*****************************************************************************
+// COMP_E1 Registers
+//*****************************************************************************
+typedef struct {
+  union {    /* CE1CTL0 Register */
+    __IO uint16_t r;
+    struct { /* CE1CTL0 Bits */
+      __IO uint16_t bIPSEL              	:	4;  /* Channel input selected for the V+ terminal */
+      __I  uint16_t bRESERVED0          	:	3;  /* Reserved */
+      __IO uint16_t bIPEN               	:	1;  /* Channel input enable for the V+ terminal */
+      __IO uint16_t bIMSEL              	:	4;  /* Channel input selected for the - terminal */
+      __I  uint16_t bRESERVED1          	:	3;  /* Reserved */
+      __IO uint16_t bIMEN               	:	1;  /* Channel input enable for the - terminal */
+    } b;
+  } rCTL0;
+  union {    /* CE1CTL1 Register */
+    __IO uint16_t r;
+    struct { /* CE1CTL1 Bits */
+      __IO uint16_t bOUT                	:	1;  /* Comparator output value */
+      __IO uint16_t bOUTPOL             	:	1;  /* Comparator output polarity */
+      __IO uint16_t bF                  	:	1;  /* Comparator output filter */
+      __IO uint16_t bIES                	:	1;  /* Interrupt edge select for CEIIFG and CEIFG */
+      __IO uint16_t bSHORT              	:	1;  /* Input short */
+      __IO uint16_t bEX                 	:	1;  /* Exchange */
+      __IO uint16_t bFDLY               	:	2;  /* Filter delay */
+      __IO uint16_t bPWRMD              	:	2;  /* Power Mode */
+      __IO uint16_t bON                 	:	1;  /* Comparator On */
+      __IO uint16_t bMRVL               	:	1;  /* This bit is valid of CEMRVS is set to 1 */
+      __IO uint16_t bMRVS               	:	1;  /*  */
+      __I  uint16_t bRESERVED0          	:	3;  /* Reserved */
+    } b;
+  } rCTL1;
+  union {    /* CE1CTL2 Register */
+    __IO uint16_t r;
+    struct { /* CE1CTL2 Bits */
+      __IO uint16_t bREF0               	:	5;  /* Reference resistor tap 0 */
+      __IO uint16_t bRSEL               	:	1;  /* Reference select */
+      __IO uint16_t bRS                 	:	2;  /* Reference source */
+      __IO uint16_t bREF1               	:	5;  /* Reference resistor tap 1 */
+      __IO uint16_t bREFL               	:	2;  /* Reference voltage level */
+      __IO uint16_t bREFACC             	:	1;  /* Reference accuracy */
+    } b;
+  } rCTL2;
+  union {    /* CE1CTL3 Register */
+    __IO uint16_t r;
+    struct { /* CE1CTL3 Bits */
+      __IO uint16_t bPD0                	:	1;  /* Port disable */
+      __IO uint16_t bPD1                	:	1;  /* Port disable */
+      __IO uint16_t bPD2                	:	1;  /* Port disable */
+      __IO uint16_t bPD3                	:	1;  /* Port disable */
+      __IO uint16_t bPD4                	:	1;  /* Port disable */
+      __IO uint16_t bPD5                	:	1;  /* Port disable */
+      __IO uint16_t bPD6                	:	1;  /* Port disable */
+      __IO uint16_t bPD7                	:	1;  /* Port disable */
+      __IO uint16_t bPD8                	:	1;  /* Port disable */
+      __IO uint16_t bPD9                	:	1;  /* Port disable */
+      __IO uint16_t bPD10               	:	1;  /* Port disable */
+      __IO uint16_t bPD11               	:	1;  /* Port disable */
+      __IO uint16_t bPD12               	:	1;  /* Port disable */
+      __IO uint16_t bPD13               	:	1;  /* Port disable */
+      __IO uint16_t bPD14               	:	1;  /* Port disable */
+      __IO uint16_t bPD15               	:	1;  /* Port disable */
+    } b;
+  } rCTL3;
+  uint8_t  RESERVED0[4];
+  union {    /* CE1INT Register */
+    __IO uint16_t r;
+    struct { /* CE1INT Bits */
+      __IO uint16_t bIFG                	:	1;  /* Comparator output interrupt flag */
+      __IO uint16_t bIIFG               	:	1;  /* Comparator output inverted interrupt flag */
+      __I  uint16_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint16_t bRDYIFG             	:	1;  /* Comparator ready interrupt flag */
+      __I  uint16_t bRESERVED1          	:	3;  /* Reserved */
+      __IO uint16_t bIE                 	:	1;  /* Comparator output interrupt enable */
+      __IO uint16_t bIIE                	:	1;  /* Comparator output interrupt enable inverted polarity */
+      __I  uint16_t bRESERVED2          	:	2;  /* Reserved */
+      __IO uint16_t bRDYIE              	:	1;  /* Comparator ready interrupt enable */
+      __I  uint16_t bRESERVED3          	:	3;  /* Reserved */
+    } b;
+  } rINT;
+  __I uint16_t rIV; /* Comparator Interrupt Vector Word Register */
+} COMP_E1_Type;
+
+
+//*****************************************************************************
+// CRC32 Registers
+//*****************************************************************************
+typedef struct {
+  __IO uint16_t rCRC32DI; /* Data Input for CRC32 Signature Computation */
+  uint8_t  RESERVED0[2];
+  __IO uint16_t rCRC32DIRB; /* Data In Reverse for CRC32 Computation */
+  uint8_t  RESERVED1[2];
+  __IO uint16_t rCRC32INIRES_LO; /* CRC32 Initialization and Result, lower 16 bits */
+  __IO uint16_t rCRC32INIRES_HI; /* CRC32 Initialization and Result, upper 16 bits */
+  __IO uint16_t rCRC32RESR_LO; /* CRC32 Result Reverse, lower 16 bits */
+  __IO uint16_t rCRC32RESR_HI; /* CRC32 Result Reverse, Upper 16 bits */
+  __IO uint16_t rCRC16DI; /* Data Input for CRC16 computation */
+  uint8_t  RESERVED2[2];
+  __IO uint16_t rCRC16DIRB; /* CRC16 Data In Reverse */
+  uint8_t  RESERVED3[2];
+  __IO uint16_t rCRC16INIRES; /* CRC16 Initialization and Result register */
+  uint8_t  RESERVED4[4];
+  __IO uint16_t rCRC16RESR; /* CRC16 Result Reverse */
+} CRC32_Type;
+
+
+//*****************************************************************************
+// CS Registers
+//*****************************************************************************
+typedef struct {
+  union {    /* CSKEY Register */
+    __IO uint32_t r;
+    struct { /* CSKEY Bits */
+      __IO uint32_t bKEY                	:	16;  /* Write xxxx_695Ah to unlock */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rKEY;
+  union {    /* CSCTL0 Register */
+    __IO uint32_t r;
+    struct { /* CSCTL0 Bits */
+      __IO uint32_t bDCOTUNE            	:	13;  /* DCO frequency tuning select */
+      __I  uint32_t bRESERVED0          	:	3;  /* Reserved */
+      __IO uint32_t bDCORSEL            	:	3;  /* DCO frequency range select */
+      __I  uint32_t bRESERVED1          	:	3;  /* Reserved */
+      __IO uint32_t bDCORES             	:	1;  /* Enables the DCO external resistor mode */
+      __IO uint32_t bDCOEN              	:	1;  /* Enables the DCO oscillator */
+      __IO uint32_t bDIS_DCO_DELAY_CNT  	:	1;  /*  */
+      __I  uint32_t bRESERVED2          	:	7;  /* Reserved */
+    } b;
+  } rCTL0;
+  union {    /* CSCTL1 Register */
+    __IO uint32_t r;
+    struct { /* CSCTL1 Bits */
+      __IO uint32_t bSELM               	:	3;  /* Selects the MCLK source */
+      __I  uint32_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint32_t bSELS               	:	3;  /* Selects the SMCLK and HSMCLK source */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bSELA               	:	3;  /* Selects the ACLK source */
+      __I  uint32_t bRESERVED2          	:	1;  /* Reserved */
+      __IO uint32_t bSELB               	:	1;  /* Selects the BCLK source */
+      __I  uint32_t bRESERVED3          	:	3;  /* Reserved */
+      __IO uint32_t bDIVM               	:	3;  /* MCLK source divider */
+      __I  uint32_t bRESERVED4          	:	1;  /* Reserved */
+      __IO uint32_t bDIVHS              	:	3;  /* HSMCLK source divider */
+      __I  uint32_t bRESERVED5          	:	1;  /* Reserved */
+      __IO uint32_t bDIVA               	:	3;  /* ACLK source divider */
+      __I  uint32_t bRESERVED6          	:	1;  /* Reserved */
+      __IO uint32_t bDIVS               	:	3;  /* SMCLK source divider */
+      __I  uint32_t bRESERVED7          	:	1;  /* Reserved */
+    } b;
+  } rCTL1;
+  union {    /* CSCTL2 Register */
+    __IO uint32_t r;
+    struct { /* CSCTL2 Bits */
+      __IO uint32_t bLFXTDRIVE          	:	3;  /* LFXT oscillator current can be adjusted to its drive needs */
+      __IO uint32_t bRESERVED0          	:	4;  /* Reserved */
+      __IO uint32_t bLFXTAGCOFF         	:	1;  /* Disables the automatic gain control of the LFXT crystal */
+      __IO uint32_t bLFXT_EN            	:	1;  /* Turns on the LFXT oscillator regardless if used as a clock resource */
+      __IO uint32_t bLFXTBYPASS         	:	1;  /* LFXT bypass select */
+      __I  uint32_t bRESERVED1          	:	6;  /* Reserved */
+      __IO uint32_t bHFXTDRIVE          	:	1;  /* HFXT oscillator drive selection */
+      __IO uint32_t bRESERVED5          	:	2;  /* Reserved */
+      __I  uint32_t bRESERVED2          	:	1;  /* Reserved */
+      __IO uint32_t bHFXTFREQ           	:	3;  /* HFXT frequency selection */
+      __I  uint32_t bRESERVED3          	:	1;  /* Reserved */
+      __IO uint32_t bHFXT_EN            	:	1;  /* Turns on the HFXT oscillator regardless if used as a clock resource */
+      __IO uint32_t bHFXTBYPASS         	:	1;  /* HFXT bypass select */
+      __I  uint32_t bRESERVED4          	:	6;  /* Reserved */
+    } b;
+  } rCTL2;
+  union {    /* CSCTL3 Register */
+    __IO uint32_t r;
+    struct { /* CSCTL3 Bits */
+      __IO uint32_t bFCNTLF             	:	2;  /* Start flag counter for LFXT */
+      __O  uint32_t bRFCNTLF            	:	1;  /* Reset start fault counter for LFXT */
+      __IO uint32_t bFCNTLF_EN          	:	1;  /* Enable start fault counter for LFXT */
+      __IO uint32_t bFCNTHF             	:	2;  /* Start flag counter for HFXT */
+      __O  uint32_t bRFCNTHF            	:	1;  /* Reset start fault counter for HFXT */
+      __IO uint32_t bFCNTHF_EN          	:	1;  /* Enable start fault counter for HFXT */
+      __IO uint32_t bFCNTHF2            	:	2;  /* Start flag counter for HFXT2 */
+      __O  uint32_t bRFCNTHF2           	:	1;  /* Reset start fault counter for HFXT2 */
+      __IO uint32_t bFCNTHF2_EN         	:	1;  /* Enable start fault counter for HFXT2 */
+      __I  uint32_t bRESERVED0          	:	20;  /* Reserved */
+    } b;
+  } rCTL3;
+  union {    /* CSCTL4 Register */
+    __IO uint32_t r;
+    struct { /* CSCTL4 Bits */
+      __IO uint32_t bHFXT2DRIVE         	:	3;  /* HFXT2 oscillator current can be adjusted to its drive needs */
+      __I  uint32_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint32_t bHFXT2FREQ          	:	3;  /* HFXT2 frequency selection */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bHFXT2_EN           	:	1;  /* Turns on the HFXT2 oscillator */
+      __IO uint32_t bHFXT2BYPASS        	:	1;  /* HFXT2 bypass select */
+      __I  uint32_t bRESERVED2          	:	22;  /* Reserved */
+    } b;
+  } rCTL4;
+  union {    /* CSCTL5 Register */
+    __IO uint32_t r;
+    struct { /* CSCTL5 Bits */
+      __IO uint32_t bREFCNTSEL          	:	3;  /* Reference counter source select */
+      __IO uint32_t bREFCNTPS           	:	3;  /* Reference clock prescaler */
+      __I  uint32_t bRESERVED0          	:	1;  /* Reserved */
+      __O  uint32_t bCALSTART           	:	1;  /* Start clock calibration counters */
+      __IO uint32_t bPERCNTSEL          	:	3;  /* Period counter source select */
+      __I  uint32_t bRESERVED1          	:	21;  /* Reserved */
+    } b;
+  } rCTL5;
+  union {    /* CSCTL6 Register */
+    __IO uint32_t r;
+    struct { /* CSCTL6 Bits */
+      __I  uint32_t bPERCNT             	:	16;  /* Calibration period counter */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rCTL6;
+  union {    /* CSCTL7 Register */
+    __IO uint32_t r;
+    struct { /* CSCTL7 Bits */
+      __IO uint32_t bREFCNT             	:	16;  /* Calibration reference period counter */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rCTL7;
+  uint8_t  RESERVED0[12];
+  union {    /* CSCLKEN Register */
+    __IO uint32_t r;
+    struct { /* CSCLKEN Bits */
+      __IO uint32_t bACLK_EN            	:	1;  /* ACLK system clock conditional request enable */
+      __IO uint32_t bMCLK_EN            	:	1;  /* MCLK system clock conditional request enable */
+      __IO uint32_t bHSMCLK_EN          	:	1;  /* HSMCLK system clock conditional request enable */
+      __IO uint32_t bSMCLK_EN           	:	1;  /* SMCLK system clock conditional request enable */
+      __I  uint32_t bRESERVED0          	:	4;  /* Reserved */
+      __IO uint32_t bVLO_EN             	:	1;  /* Turns on the VLO oscillator */
+      __IO uint32_t bREFO_EN            	:	1;  /* Turns on the REFO oscillator */
+      __IO uint32_t bMODOSC_EN          	:	1;  /* Turns on the MODOSC oscillator */
+      __I  uint32_t bRESERVED1          	:	4;  /* Reserved */
+      __IO uint32_t bREFOFSEL           	:	1;  /* Selects REFO nominal frequency */
+      __I  uint32_t bRESERVED2          	:	16;  /* Reserved */
+    } b;
+  } rCLKEN;
+  union {    /* CSSTAT Register */
+    __I uint32_t r;
+    struct { /* CSSTAT Bits */
+      __I  uint32_t bDCO_ON             	:	1;  /* DCO status */
+      __I  uint32_t bDCOBIAS_ON         	:	1;  /* DCO bias status */
+      __I  uint32_t bHFXT_ON            	:	1;  /* HFXT status */
+      __I  uint32_t bHFXT2_ON           	:	1;  /* HFXT2 status */
+      __I  uint32_t bMODOSC_ON          	:	1;  /* MODOSC status */
+      __I  uint32_t bVLO_ON             	:	1;  /* VLO status */
+      __I  uint32_t bLFXT_ON            	:	1;  /* LFXT status */
+      __I  uint32_t bREFO_ON            	:	1;  /* REFO status */
+      __I  uint32_t bRESERVED0          	:	8;  /* Reserved */
+      __I  uint32_t bACLK_ON            	:	1;  /* ACLK system clock status */
+      __I  uint32_t bMCLK_ON            	:	1;  /* MCLK system clock status */
+      __I  uint32_t bHSMCLK_ON          	:	1;  /* HSMCLK system clock status */
+      __I  uint32_t bSMCLK_ON           	:	1;  /* SMCLK system clock status */
+      __I  uint32_t bMODCLK_ON          	:	1;  /* MODCLK system clock status */
+      __I  uint32_t bVLOCLK_ON          	:	1;  /* VLOCLK system clock status */
+      __I  uint32_t bLFXTCLK_ON         	:	1;  /* LFXTCLK system clock status */
+      __I  uint32_t bREFOCLK_ON         	:	1;  /* REFOCLK system clock status */
+      __I  uint32_t bACLK_READY         	:	1;  /* ACLK Ready status */
+      __I  uint32_t bMCLK_READY         	:	1;  /* MCLK Ready status */
+      __I  uint32_t bHSMCLK_READY       	:	1;  /* HSMCLK Ready status */
+      __I  uint32_t bSMCLK_READY        	:	1;  /* SMCLK Ready status */
+      __I  uint32_t bBCLK_READY         	:	1;  /* BCLK Ready status */
+      __I  uint32_t bRESERVED1          	:	3;  /* Reserved */
+    } b;
+  } rSTAT;
+  uint8_t  RESERVED1[8];
+  union {    /* CSIE Register */
+    __IO uint32_t r;
+    struct { /* CSIE Bits */
+      __IO uint32_t bLFXTIE             	:	1;  /* LFXT oscillator fault flag interrupt enable */
+      __IO uint32_t bHFXTIE             	:	1;  /* HFXT oscillator fault flag interrupt enable */
+      __IO uint32_t bHFXT2IE            	:	1;  /* HFXT2 oscillator fault flag interrupt enable */
+      __I  uint32_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint32_t bDCOMINIE           	:	1;  /* DCO minimum fault flag interrupt enable */
+      __IO uint32_t bDCOMAXIE           	:	1;  /* DCO maximum fault flag interrupt enable */
+      __IO uint32_t bDCORIE             	:	1;  /* DCO external resistor fault flag interrupt enable */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bFCNTLFIE           	:	1;  /* Start fault counter interrupt enable LFXT */
+      __IO uint32_t bFCNTHFIE           	:	1;  /* Start fault counter interrupt enable HFXT */
+      __IO uint32_t bFCNTHF2IE          	:	1;  /* Start fault counter interrupt enable HFXT2 */
+      __I  uint32_t bRESERVED2          	:	1;  /* Reserved */
+      __IO uint32_t bPLLOOLIE           	:	1;  /* PLL out-of-lock interrupt enable */
+      __IO uint32_t bPLLLOSIE           	:	1;  /* PLL loss-of-signal interrupt enable */
+      __IO uint32_t bPLLOORIE           	:	1;  /* PLL out-of-range interrupt enable */
+      __IO uint32_t bCALIE              	:	1;  /* REFCNT period counter interrupt enable */
+      __I  uint32_t bRESERVED3          	:	16;  /* Reserved */
+    } b;
+  } rIE;
+  uint8_t  RESERVED2[4];
+  union {    /* CSIFG Register */
+    __I uint32_t r;
+    struct { /* CSIFG Bits */
+      __I  uint32_t bLFXTIFG            	:	1;  /* LFXT oscillator fault flag */
+      __I  uint32_t bHFXTIFG            	:	1;  /* HFXT oscillator fault flag */
+      __I  uint32_t bHFXT2IFG           	:	1;  /* HFXT2 oscillator fault flag */
+      __I  uint32_t bRESERVED0          	:	1;  /* Reserved */
+      __I  uint32_t bDCOMINIFG          	:	1;  /* DCO minimum fault flag */
+      __I  uint32_t bDCOMAXIFG          	:	1;  /* DCO maximum fault flag */
+      __I  uint32_t bDCORIFG            	:	1;  /* DCO external resistor fault flag */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __I  uint32_t bFCNTLFIFG          	:	1;  /* Start fault counter interrupt flag LFXT */
+      __I  uint32_t bFCNTHFIFG          	:	1;  /* Start fault counter interrupt flag HFXT */
+      __I  uint32_t bRESERVED2          	:	1;  /* Reserved */
+      __I  uint32_t bFCNTHF2IFG         	:	1;  /* Start fault counter interrupt flag HFXT2 */
+      __I  uint32_t bPLLOOLIFG          	:	1;  /* PLL out-of-lock interrupt flag */
+      __I  uint32_t bPLLLOSIFG          	:	1;  /* PLL loss-of-signal interrupt flag */
+      __I  uint32_t bPLLOORIFG          	:	1;  /* PLL out-of-range interrupt flag */
+      __I  uint32_t bCALIFG             	:	1;  /* REFCNT period counter expired */
+      __I  uint32_t bRESERVED3          	:	16;  /* Reserved */
+    } b;
+  } rIFG;
+  uint8_t  RESERVED3[4];
+  union {    /* CSCLRIFG Register */
+    __IO uint32_t r;
+    struct { /* CSCLRIFG Bits */
+      __O  uint32_t bCLR_LFXTIFG        	:	1;  /* Clear LFXT oscillator fault interrupt flag */
+      __O  uint32_t bCLR_HFXTIFG        	:	1;  /* Clear HFXT oscillator fault interrupt flag */
+      __O  uint32_t bCLR_HFXT2IFG       	:	1;  /* Clear HFXT2 oscillator fault interrupt flag */
+      __I  uint32_t bRESERVED0          	:	1;  /* Reserved */
+      __O  uint32_t bCLR_DCOMINIFG      	:	1;  /* Clear DCO minimum fault interrupt flag */
+      __O  uint32_t bCLR_DCOMAXIFG      	:	1;  /* Clear DCO maximum fault interrupt flag */
+      __O  uint32_t bCLR_DCORIFG        	:	1;  /* Clear DCO external resistor fault interrupt flag */
+      __O  uint32_t bCLR_CALIFG         	:	1;  /* REFCNT period counter clear interrupt flag */
+      __O  uint32_t bCLR_FCNTLFIFG      	:	1;  /* Start fault counter clear interrupt flag LFXT */
+      __O  uint32_t bCLR_FCNTHFIFG      	:	1;  /* Start fault counter clear interrupt flag HFXT */
+      __O  uint32_t bCLR_FCNTHF2IFG     	:	1;  /* Start fault counter clear interrupt flag HFXT2 */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __O  uint32_t bCLR_PLLOOLIFG      	:	1;  /* PLL out-of-lock clear interrupt flag */
+      __O  uint32_t bCLR_PLLLOSIFG      	:	1;  /* PLL loss-of-signal clear interrupt flag */
+      __O  uint32_t bCLR_PLLOORIFG      	:	1;  /* PLL out-of-range clear interrupt flag */
+      __I  uint32_t bRESERVED2          	:	17;  /* Reserved */
+    } b;
+  } rCLRIFG;
+  uint8_t  RESERVED4[4];
+  union {    /* CSSETIFG Register */
+    __IO uint32_t r;
+    struct { /* CSSETIFG Bits */
+      __O  uint32_t bSET_LFXTIFG        	:	1;  /* Set LFXT oscillator fault interrupt flag */
+      __O  uint32_t bSET_HFXTIFG        	:	1;  /* Set HFXT oscillator fault interrupt flag */
+      __O  uint32_t bSET_HFXT2IFG       	:	1;  /* Set HFXT2 oscillator fault interrupt flag */
+      __I  uint32_t bRESERVED0          	:	1;  /* Reserved */
+      __O  uint32_t bSET_DCOMINIFG      	:	1;  /* Set DCO minimum fault interrupt flag */
+      __O  uint32_t bSET_DCOMAXIFG      	:	1;  /* Set DCO maximum fault interrupt flag */
+      __O  uint32_t bSET_DCORIFG        	:	1;  /* Set DCO external resistor fault interrupt flag */
+      __O  uint32_t bSET_CALIFG         	:	1;  /* REFCNT period counter set interrupt flag */
+      __O  uint32_t bSET_FCNTLFIFG      	:	1;  /* Start fault counter set interrupt flag LFXT */
+      __O  uint32_t bSET_FCNTHFIFG      	:	1;  /* Start fault counter set interrupt flag HFXT */
+      __O  uint32_t bSET_FCNTHF2IFG     	:	1;  /* Start fault counter set interrupt flag HFXT2 */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __O  uint32_t bSET_PLLOOLIFG      	:	1;  /* PLL out-of-lock set interrupt flag */
+      __O  uint32_t bSET_PLLLOSIFG      	:	1;  /* PLL loss-of-signal set interrupt flag */
+      __O  uint32_t bSET_PLLOORIFG      	:	1;  /* PLL out-of-range set interrupt flag */
+      __I  uint32_t bRESERVED2          	:	17;  /* Reserved */
+    } b;
+  } rSETIFG;
+  uint8_t  RESERVED5[4];
+  union {    /* CSDCOERCAL Register */
+    __IO uint32_t r;
+    struct { /* CSDCOERCAL Bits */
+      __IO uint32_t bDCO_TCTRIM         	:	2;  /* DCO Temperature compensation Trim */
+      __I  uint32_t bRESERVED0          	:	14;  /* Reserved */
+      __IO uint32_t bDCO_FTRIM          	:	11;  /* DCO frequency trim */
+      __I  uint32_t bRESERVED1          	:	5;  /* Reserved */
+    } b;
+  } rDCOERCAL;
+} CS_Type;
+
+
+//*****************************************************************************
+// DIO Registers
+//*****************************************************************************
+typedef struct {
+  union {    /* PAIN Register */
+    __I uint16_t r;
+    struct { /* PAIN Bits */
+      __I  uint16_t bP1IN               	:	8;  /* Port 1 Input */
+      __I  uint16_t bP2IN               	:	8;  /* Port 2 Input */
+    } b;
+  } rPAIN;
+  union {    /* PAOUT Register */
+    __IO uint16_t r;
+    struct { /* PAOUT Bits */
+      __IO uint16_t bP1OUT              	:	8;  /* Port 1 Output */
+      __IO uint16_t bP2OUT              	:	8;  /* Port 2 Output */
+    } b;
+  } rPAOUT;
+  union {    /* PADIR Register */
+    __IO uint16_t r;
+    struct { /* PADIR Bits */
+      __IO uint16_t bP1DIR              	:	8;  /* Port 1 Direction */
+      __IO uint16_t bP2DIR              	:	8;  /* Port 2 Direction */
+    } b;
+  } rPADIR;
+  union {    /* PAREN Register */
+    __IO uint16_t r;
+    struct { /* PAREN Bits */
+      __IO uint16_t bP1REN              	:	8;  /* Port 1 Resistor Enable */
+      __IO uint16_t bP2REN              	:	8;  /* Port 2 Resistor Enable */
+    } b;
+  } rPAREN;
+  union {    /* PADS Register */
+    __IO uint16_t r;
+    struct { /* PADS Bits */
+      __IO uint16_t bP1DS               	:	8;  /* Port 1 Drive Strength */
+      __IO uint16_t bP2DS               	:	8;  /* Port 2 Drive Strength */
+    } b;
+  } rPADS;
+  union {    /* PASEL0 Register */
+    __IO uint16_t r;
+    struct { /* PASEL0 Bits */
+      __IO uint16_t bP1SEL0             	:	8;  /* Port 1 Select 0 */
+      __IO uint16_t bP2SEL0             	:	8;  /* Port 2 Select 0 */
+    } b;
+  } rPASEL0;
+  union {    /* PASEL1 Register */
+    __IO uint16_t r;
+    struct { /* PASEL1 Bits */
+      __IO uint16_t bP1SEL1             	:	8;  /* Port 1 Select 1 */
+      __IO uint16_t bP2SEL1             	:	8;  /* Port 2 Select 1 */
+    } b;
+  } rPASEL1;
+  union {    /* P1IV Register */
+    __I uint16_t r;
+    struct { /* P1IV Bits */
+      __I  uint16_t bP1IV               	:	5;  /* Port 1 interrupt vector value */
+      __I  uint16_t bRESERVED0          	:	11;  /* Reserved */
+    } b;
+  } rP1IV;
+  uint8_t  RESERVED0[6];
+  union {    /* PASELC Register */
+    __IO uint16_t r;
+    struct { /* PASELC Bits */
+      __IO uint16_t bP1SELC             	:	8;  /* Port 1 Complement Select */
+      __IO uint16_t bP2SELC             	:	8;  /* Port 2 Complement Select */
+    } b;
+  } rPASELC;
+  union {    /* PAIES Register */
+    __IO uint16_t r;
+    struct { /* PAIES Bits */
+      __IO uint16_t bP1IES              	:	8;  /* Port 1 Interrupt Edge Select */
+      __IO uint16_t bP2IES              	:	8;  /* Port 2 Interrupt Edge Select */
+    } b;
+  } rPAIES;
+  union {    /* PAIE Register */
+    __IO uint16_t r;
+    struct { /* PAIE Bits */
+      __IO uint16_t bP1IE               	:	8;  /* Port 1 Interrupt Enable */
+      __IO uint16_t bP2IE               	:	8;  /* Port 2 Interrupt Enable */
+    } b;
+  } rPAIE;
+  union {    /* PAIFG Register */
+    __IO uint16_t r;
+    struct { /* PAIFG Bits */
+      __IO uint16_t bP1IFG              	:	8;  /* Port 1 Interrupt Flag */
+      __IO uint16_t bP2IFG              	:	8;  /* Port 2 Interrupt Flag */
+    } b;
+  } rPAIFG;
+  union {    /* P2IV Register */
+    __I uint16_t r;
+    struct { /* P2IV Bits */
+      __I  uint16_t bP2IV               	:	5;  /* Port 2 interrupt vector value */
+      __I  uint16_t bRESERVED0          	:	11;  /* Reserved */
+    } b;
+  } rP2IV;
+  union {    /* PBIN Register */
+    __I uint16_t r;
+    struct { /* PBIN Bits */
+      __I  uint16_t bP3IN               	:	8;  /* Port 3 Input */
+      __I  uint16_t bP4IN               	:	8;  /* Port 4 Input */
+    } b;
+  } rPBIN;
+  union {    /* PBOUT Register */
+    __IO uint16_t r;
+    struct { /* PBOUT Bits */
+      __IO uint16_t bP3OUT              	:	8;  /* Port 3 Output */
+      __IO uint16_t bP4OUT              	:	8;  /* Port 4 Output */
+    } b;
+  } rPBOUT;
+  union {    /* PBDIR Register */
+    __IO uint16_t r;
+    struct { /* PBDIR Bits */
+      __IO uint16_t bP3DIR              	:	8;  /* Port 3 Direction */
+      __IO uint16_t bP4DIR              	:	8;  /* Port 4 Direction */
+    } b;
+  } rPBDIR;
+  union {    /* PBREN Register */
+    __IO uint16_t r;
+    struct { /* PBREN Bits */
+      __IO uint16_t bP3REN              	:	8;  /* Port 3 Resistor Enable */
+      __IO uint16_t bP4REN              	:	8;  /* Port 4 Resistor Enable */
+    } b;
+  } rPBREN;
+  union {    /* PBDS Register */
+    __IO uint16_t r;
+    struct { /* PBDS Bits */
+      __IO uint16_t bP3DS               	:	8;  /* Port 3 Drive Strength */
+      __IO uint16_t bP4DS               	:	8;  /* Port 4 Drive Strength */
+    } b;
+  } rPBDS;
+  union {    /* PBSEL0 Register */
+    __IO uint16_t r;
+    struct { /* PBSEL0 Bits */
+      __IO uint16_t bP3SEL0             	:	8;  /* Port 3 Select 0 */
+      __IO uint16_t bP4SEL0             	:	8;  /* Port 4 Select 0 */
+    } b;
+  } rPBSEL0;
+  union {    /* PBSEL1 Register */
+    __IO uint16_t r;
+    struct { /* PBSEL1 Bits */
+      __IO uint16_t bP3SEL1             	:	8;  /* Port 3 Select 1 */
+      __IO uint16_t bP4SEL1             	:	8;  /* Port 4 Select 1 */
+    } b;
+  } rPBSEL1;
+  union {    /* P3IV Register */
+    __I uint16_t r;
+    struct { /* P3IV Bits */
+      __I  uint16_t bP3IV               	:	5;  /* Port 3 interrupt vector value */
+      __I  uint16_t bRESERVED0          	:	11;  /* Reserved */
+    } b;
+  } rP3IV;
+  uint8_t  RESERVED1[6];
+  union {    /* PBSELC Register */
+    __IO uint16_t r;
+    struct { /* PBSELC Bits */
+      __IO uint16_t bP3SELC             	:	8;  /* Port 3 Complement Select */
+      __IO uint16_t bP4SELC             	:	8;  /* Port 4 Complement Select */
+    } b;
+  } rPBSELC;
+  union {    /* PBIES Register */
+    __IO uint16_t r;
+    struct { /* PBIES Bits */
+      __IO uint16_t bP3IES              	:	8;  /* Port 3 Interrupt Edge Select */
+      __IO uint16_t bP4IES              	:	8;  /* Port 4 Interrupt Edge Select */
+    } b;
+  } rPBIES;
+  union {    /* PBIE Register */
+    __IO uint16_t r;
+    struct { /* PBIE Bits */
+      __IO uint16_t bP3IE               	:	8;  /* Port 3 Interrupt Enable */
+      __IO uint16_t bP4IE               	:	8;  /* Port 4 Interrupt Enable */
+    } b;
+  } rPBIE;
+  union {    /* PBIFG Register */
+    __IO uint16_t r;
+    struct { /* PBIFG Bits */
+      __IO uint16_t bP3IFG              	:	8;  /* Port 3 Interrupt Flag */
+      __IO uint16_t bP4IFG              	:	8;  /* Port 4 Interrupt Flag */
+    } b;
+  } rPBIFG;
+  union {    /* P4IV Register */
+    __I uint16_t r;
+    struct { /* P4IV Bits */
+      __I  uint16_t bP4IV               	:	5;  /* Port 4 interrupt vector value */
+      __I  uint16_t bRESERVED0          	:	11;  /* Reserved */
+    } b;
+  } rP4IV;
+  union {    /* PCIN Register */
+    __I uint16_t r;
+    struct { /* PCIN Bits */
+      __I  uint16_t bP5IN               	:	8;  /* Port 5 Input */
+      __I  uint16_t bP6IN               	:	8;  /* Port 6 Input */
+    } b;
+  } rPCIN;
+  union {    /* PCOUT Register */
+    __IO uint16_t r;
+    struct { /* PCOUT Bits */
+      __IO uint16_t bP5OUT              	:	8;  /* Port 5 Output */
+      __IO uint16_t bP6OUT              	:	8;  /* Port 6 Output */
+    } b;
+  } rPCOUT;
+  union {    /* PCDIR Register */
+    __IO uint16_t r;
+    struct { /* PCDIR Bits */
+      __IO uint16_t bP5DIR              	:	8;  /* Port 5 Direction */
+      __IO uint16_t bP6DIR              	:	8;  /* Port 6 Direction */
+    } b;
+  } rPCDIR;
+  union {    /* PCREN Register */
+    __IO uint16_t r;
+    struct { /* PCREN Bits */
+      __IO uint16_t bP5REN              	:	8;  /* Port 5 Resistor Enable */
+      __IO uint16_t bP6REN              	:	8;  /* Port 6 Resistor Enable */
+    } b;
+  } rPCREN;
+  union {    /* PCDS Register */
+    __IO uint16_t r;
+    struct { /* PCDS Bits */
+      __IO uint16_t bP5DS               	:	8;  /* Port 5 Drive Strength */
+      __IO uint16_t bP6DS               	:	8;  /* Port 6 Drive Strength */
+    } b;
+  } rPCDS;
+  union {    /* PCSEL0 Register */
+    __IO uint16_t r;
+    struct { /* PCSEL0 Bits */
+      __IO uint16_t bP5SEL0             	:	8;  /* Port 5 Select 0 */
+      __IO uint16_t bP6SEL0             	:	8;  /* Port 6 Select 0 */
+    } b;
+  } rPCSEL0;
+  union {    /* PCSEL1 Register */
+    __IO uint16_t r;
+    struct { /* PCSEL1 Bits */
+      __IO uint16_t bP5SEL1             	:	8;  /* Port 5 Select 1 */
+      __IO uint16_t bP6SEL1             	:	8;  /* Port 6 Select 1 */
+    } b;
+  } rPCSEL1;
+  union {    /* P5IV Register */
+    __I uint16_t r;
+    struct { /* P5IV Bits */
+      __I  uint16_t bP5IV               	:	5;  /* Port 5 interrupt vector value */
+      __I  uint16_t bRESERVED0          	:	11;  /* Reserved */
+    } b;
+  } rP5IV;
+  uint8_t  RESERVED2[6];
+  union {    /* PCSELC Register */
+    __IO uint16_t r;
+    struct { /* PCSELC Bits */
+      __IO uint16_t bP5SELC             	:	8;  /* Port 5 Complement Select */
+      __IO uint16_t bP6SELC             	:	8;  /* Port 6 Complement Select */
+    } b;
+  } rPCSELC;
+  union {    /* PCIES Register */
+    __IO uint16_t r;
+    struct { /* PCIES Bits */
+      __IO uint16_t bP5IES              	:	8;  /* Port 5 Interrupt Edge Select */
+      __IO uint16_t bP6IES              	:	8;  /* Port 6 Interrupt Edge Select */
+    } b;
+  } rPCIES;
+  union {    /* PCIE Register */
+    __IO uint16_t r;
+    struct { /* PCIE Bits */
+      __IO uint16_t bP5IE               	:	8;  /* Port 5 Interrupt Enable */
+      __IO uint16_t bP6IE               	:	8;  /* Port 6 Interrupt Enable */
+    } b;
+  } rPCIE;
+  union {    /* PCIFG Register */
+    __IO uint16_t r;
+    struct { /* PCIFG Bits */
+      __IO uint16_t bP5IFG              	:	8;  /* Port 5 Interrupt Flag */
+      __IO uint16_t bP6IFG              	:	8;  /* Port 6 Interrupt Flag */
+    } b;
+  } rPCIFG;
+  union {    /* P6IV Register */
+    __I uint16_t r;
+    struct { /* P6IV Bits */
+      __I  uint16_t bP6IV               	:	5;  /* Port 6 interrupt vector value */
+      __I  uint16_t bRESERVED0          	:	11;  /* Reserved */
+    } b;
+  } rP6IV;
+  union {    /* PDIN Register */
+    __I uint16_t r;
+    struct { /* PDIN Bits */
+      __I  uint16_t bP7IN               	:	8;  /* Port 7 Input */
+      __I  uint16_t bP8IN               	:	8;  /* Port 8 Input */
+    } b;
+  } rPDIN;
+  union {    /* PDOUT Register */
+    __IO uint16_t r;
+    struct { /* PDOUT Bits */
+      __IO uint16_t bP7OUT              	:	8;  /* Port 7 Output */
+      __IO uint16_t bP8OUT              	:	8;  /* Port 8 Output */
+    } b;
+  } rPDOUT;
+  union {    /* PDDIR Register */
+    __IO uint16_t r;
+    struct { /* PDDIR Bits */
+      __IO uint16_t bP7DIR              	:	8;  /* Port 7 Direction */
+      __IO uint16_t bP8DIR              	:	8;  /* Port 8 Direction */
+    } b;
+  } rPDDIR;
+  union {    /* PDREN Register */
+    __IO uint16_t r;
+    struct { /* PDREN Bits */
+      __IO uint16_t bP7REN              	:	8;  /* Port 7 Resistor Enable */
+      __IO uint16_t bP8REN              	:	8;  /* Port 8 Resistor Enable */
+    } b;
+  } rPDREN;
+  union {    /* PDDS Register */
+    __IO uint16_t r;
+    struct { /* PDDS Bits */
+      __IO uint16_t bP7DS               	:	8;  /* Port 7 Drive Strength */
+      __IO uint16_t bP8DS               	:	8;  /* Port 8 Drive Strength */
+    } b;
+  } rPDDS;
+  union {    /* PDSEL0 Register */
+    __IO uint16_t r;
+    struct { /* PDSEL0 Bits */
+      __IO uint16_t bP7SEL0             	:	8;  /* Port 7 Select 0 */
+      __IO uint16_t bP8SEL0             	:	8;  /* Port 8 Select 0 */
+    } b;
+  } rPDSEL0;
+  union {    /* PDSEL1 Register */
+    __IO uint16_t r;
+    struct { /* PDSEL1 Bits */
+      __IO uint16_t bP7SEL1             	:	8;  /* Port 7 Select 1 */
+      __IO uint16_t bP8SEL1             	:	8;  /* Port 8 Select 1 */
+    } b;
+  } rPDSEL1;
+  union {    /* P7IV Register */
+    __I uint16_t r;
+    struct { /* P7IV Bits */
+      __I  uint16_t bP7IV               	:	5;  /* Port 7 interrupt vector value */
+      __I  uint16_t bRESERVED0          	:	11;  /* Reserved */
+    } b;
+  } rP7IV;
+  uint8_t  RESERVED3[6];
+  union {    /* PDSELC Register */
+    __IO uint16_t r;
+    struct { /* PDSELC Bits */
+      __IO uint16_t bP7SELC             	:	8;  /* Port 7 Complement Select */
+      __IO uint16_t bP8SELC             	:	8;  /* Port 8 Complement Select */
+    } b;
+  } rPDSELC;
+  union {    /* PDIES Register */
+    __IO uint16_t r;
+    struct { /* PDIES Bits */
+      __IO uint16_t bP7IES              	:	8;  /* Port 7 Interrupt Edge Select */
+      __IO uint16_t bP8IES              	:	8;  /* Port 8 Interrupt Edge Select */
+    } b;
+  } rPDIES;
+  union {    /* PDIE Register */
+    __IO uint16_t r;
+    struct { /* PDIE Bits */
+      __IO uint16_t bP7IE               	:	8;  /* Port 7 Interrupt Enable */
+      __IO uint16_t bP8IE               	:	8;  /* Port 8 Interrupt Enable */
+    } b;
+  } rPDIE;
+  union {    /* PDIFG Register */
+    __IO uint16_t r;
+    struct { /* PDIFG Bits */
+      __IO uint16_t bP7IFG              	:	8;  /* Port 7 Interrupt Flag */
+      __IO uint16_t bP8IFG              	:	8;  /* Port 8 Interrupt Flag */
+    } b;
+  } rPDIFG;
+  union {    /* P8IV Register */
+    __I uint16_t r;
+    struct { /* P8IV Bits */
+      __I  uint16_t bP8IV               	:	5;  /* Port 8 interrupt vector value */
+      __I  uint16_t bRESERVED0          	:	11;  /* Reserved */
+    } b;
+  } rP8IV;
+  union {    /* PEIN Register */
+    __I uint16_t r;
+    struct { /* PEIN Bits */
+      __I  uint16_t bP9IN               	:	8;  /* Port 9 Input */
+      __I  uint16_t bP10IN              	:	8;  /* Port 10 Input */
+    } b;
+  } rPEIN;
+  union {    /* PEOUT Register */
+    __IO uint16_t r;
+    struct { /* PEOUT Bits */
+      __IO uint16_t bP9OUT              	:	8;  /* Port 9 Output */
+      __IO uint16_t bP10OUT             	:	8;  /* Port 10 Output */
+    } b;
+  } rPEOUT;
+  union {    /* PEDIR Register */
+    __IO uint16_t r;
+    struct { /* PEDIR Bits */
+      __IO uint16_t bP9DIR              	:	8;  /* Port 9 Direction */
+      __IO uint16_t bP10DIR             	:	8;  /* Port 10 Direction */
+    } b;
+  } rPEDIR;
+  union {    /* PEREN Register */
+    __IO uint16_t r;
+    struct { /* PEREN Bits */
+      __IO uint16_t bP9REN              	:	8;  /* Port 9 Resistor Enable */
+      __IO uint16_t bP10REN             	:	8;  /* Port 10 Resistor Enable */
+    } b;
+  } rPEREN;
+  union {    /* PEDS Register */
+    __IO uint16_t r;
+    struct { /* PEDS Bits */
+      __IO uint16_t bP9DS               	:	8;  /* Port 9 Drive Strength */
+      __IO uint16_t bP10DS              	:	8;  /* Port 10 Drive Strength */
+    } b;
+  } rPEDS;
+  union {    /* PESEL0 Register */
+    __IO uint16_t r;
+    struct { /* PESEL0 Bits */
+      __IO uint16_t bP9SEL0             	:	8;  /* Port 9 Select 0 */
+      __IO uint16_t bP10SEL0            	:	8;  /* Port 10 Select 0 */
+    } b;
+  } rPESEL0;
+  union {    /* PESEL1 Register */
+    __IO uint16_t r;
+    struct { /* PESEL1 Bits */
+      __IO uint16_t bP9SEL1             	:	8;  /* Port 9 Select 1 */
+      __IO uint16_t bP10SEL1            	:	8;  /* Port 10 Select 1 */
+    } b;
+  } rPESEL1;
+  union {    /* P9IV Register */
+    __I uint16_t r;
+    struct { /* P9IV Bits */
+      __I  uint16_t bP9IV               	:	5;  /* Port 9 interrupt vector value */
+      __I  uint16_t bRESERVED0          	:	11;  /* Reserved */
+    } b;
+  } rP9IV;
+  uint8_t  RESERVED4[6];
+  union {    /* PESELC Register */
+    __IO uint16_t r;
+    struct { /* PESELC Bits */
+      __IO uint16_t bP9SELC             	:	8;  /* Port 9 Complement Select */
+      __IO uint16_t bP10SELC            	:	8;  /* Port 10 Complement Select */
+    } b;
+  } rPESELC;
+  union {    /* PEIES Register */
+    __IO uint16_t r;
+    struct { /* PEIES Bits */
+      __IO uint16_t bP9IES              	:	8;  /* Port 9 Interrupt Edge Select */
+      __IO uint16_t bP10IES             	:	8;  /* Port 10 Interrupt Edge Select */
+    } b;
+  } rPEIES;
+  union {    /* PEIE Register */
+    __IO uint16_t r;
+    struct { /* PEIE Bits */
+      __IO uint16_t bP9IE               	:	8;  /* Port 9 Interrupt Enable */
+      __IO uint16_t bP10IE              	:	8;  /* Port 10 Interrupt Enable */
+    } b;
+  } rPEIE;
+  union {    /* PEIFG Register */
+    __IO uint16_t r;
+    struct { /* PEIFG Bits */
+      __IO uint16_t bP9IFG              	:	8;  /* Port 9 Interrupt Flag */
+      __IO uint16_t bP10IFG             	:	8;  /* Port 10 Interrupt Flag */
+    } b;
+  } rPEIFG;
+  union {    /* P10IV Register */
+    __I uint16_t r;
+    struct { /* P10IV Bits */
+      __I  uint16_t bP10IV              	:	5;  /* Port 10 interrupt vector value */
+      __I  uint16_t bRESERVED0          	:	11;  /* Reserved */
+    } b;
+  } rP10IV;
+  uint8_t  RESERVED5[128];
+  __I uint16_t rPJIN; /* Port J Input */
+  __IO uint16_t rPJOUT; /* Port J Output */
+  __IO uint16_t rPJDIR; /* Port J Direction */
+  __IO uint16_t rPJREN; /* Port J Resistor Enable */
+  __IO uint16_t rPJDS; /* Port J Drive Strength */
+  __IO uint16_t rPJSEL0; /* Port J Select 0 */
+  __IO uint16_t rPJSEL1; /* Port J Select 1 */
+  uint8_t  RESERVED6[8];
+  __IO uint16_t rPJSELC; /* Port J Complement Select */
+} DIO_Type;
+
+
+//*****************************************************************************
+// DMA Registers
+//*****************************************************************************
+typedef struct {
+  union {    /* DMA_DEVICE_CFG Register */
+    __I uint32_t r;
+    struct { /* DMA_DEVICE_CFG Bits */
+      __I  uint32_t bNUM_DMA_CHANNELS   	:	8;  /* Number of DMA channels available */
+      __I  uint32_t bNUM_SRC_PER_CHANNEL	:	8;  /* Number of DMA sources per channel */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rDEVICE_CFG;
+  union {    /* DMA_SW_CHTRIG Register */
+    __IO uint32_t r;
+    struct { /* DMA_SW_CHTRIG Bits */
+      __IO uint32_t bCH0                	:	1;  /* Write 1, triggers DMA_CHANNEL0 */
+      __IO uint32_t bCH1                	:	1;  /* Write 1, triggers DMA_CHANNEL1 */
+      __IO uint32_t bCH2                	:	1;  /* Write 1, triggers DMA_CHANNEL2 */
+      __IO uint32_t bCH3                	:	1;  /* Write 1, triggers DMA_CHANNEL3 */
+      __IO uint32_t bCH4                	:	1;  /* Write 1, triggers DMA_CHANNEL4 */
+      __IO uint32_t bCH5                	:	1;  /* Write 1, triggers DMA_CHANNEL5 */
+      __IO uint32_t bCH6                	:	1;  /* Write 1, triggers DMA_CHANNEL6 */
+      __IO uint32_t bCH7                	:	1;  /* Write 1, triggers DMA_CHANNEL7 */
+      __IO uint32_t bCH8                	:	1;  /* Write 1, triggers DMA_CHANNEL8 */
+      __IO uint32_t bCH9                	:	1;  /* Write 1, triggers DMA_CHANNEL9 */
+      __IO uint32_t bCH10               	:	1;  /* Write 1, triggers DMA_CHANNEL10 */
+      __IO uint32_t bCH11               	:	1;  /* Write 1, triggers DMA_CHANNEL11 */
+      __IO uint32_t bCH12               	:	1;  /* Write 1, triggers DMA_CHANNEL12 */
+      __IO uint32_t bCH13               	:	1;  /* Write 1, triggers DMA_CHANNEL13 */
+      __IO uint32_t bCH14               	:	1;  /* Write 1, triggers DMA_CHANNEL14 */
+      __IO uint32_t bCH15               	:	1;  /* Write 1, triggers DMA_CHANNEL15 */
+      __IO uint32_t bCH16               	:	1;  /* Write 1, triggers DMA_CHANNEL16 */
+      __IO uint32_t bCH17               	:	1;  /* Write 1, triggers DMA_CHANNEL17 */
+      __IO uint32_t bCH18               	:	1;  /* Write 1, triggers DMA_CHANNEL18 */
+      __IO uint32_t bCH19               	:	1;  /* Write 1, triggers DMA_CHANNEL19 */
+      __IO uint32_t bCH20               	:	1;  /* Write 1, triggers DMA_CHANNEL20 */
+      __IO uint32_t bCH21               	:	1;  /* Write 1, triggers DMA_CHANNEL21 */
+      __IO uint32_t bCH22               	:	1;  /* Write 1, triggers DMA_CHANNEL22 */
+      __IO uint32_t bCH23               	:	1;  /* Write 1, triggers DMA_CHANNEL23 */
+      __IO uint32_t bCH24               	:	1;  /* Write 1, triggers DMA_CHANNEL24 */
+      __IO uint32_t bCH25               	:	1;  /* Write 1, triggers DMA_CHANNEL25 */
+      __IO uint32_t bCH26               	:	1;  /* Write 1, triggers DMA_CHANNEL26 */
+      __IO uint32_t bCH27               	:	1;  /* Write 1, triggers DMA_CHANNEL27 */
+      __IO uint32_t bCH28               	:	1;  /* Write 1, triggers DMA_CHANNEL28 */
+      __IO uint32_t bCH29               	:	1;  /* Write 1, triggers DMA_CHANNEL29 */
+      __IO uint32_t bCH30               	:	1;  /* Write 1, triggers DMA_CHANNEL30 */
+      __IO uint32_t bCH31               	:	1;  /* Write 1, triggers DMA_CHANNEL31 */
+    } b;
+  } rSW_CHTRIG;
+  uint8_t  RESERVED0[8];
+  union {    /* DMA_CH0_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_CH0_SRCCFG Bits */
+      __IO uint32_t bDMA_SRC            	:	8;  /* Device level DMA source mapping to channel input */
+      __I  uint32_t bRESERVED0          	:	24;  /* Reserved */
+    } b;
+  } rCH0_SRCCFG;
+  union {    /* DMA_CH1_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_CH1_SRCCFG Bits */
+      __IO uint32_t bDMA_SRC            	:	8;  /* Device level DMA source mapping to channel input */
+      __I  uint32_t bRESERVED0          	:	24;  /* Reserved */
+    } b;
+  } rCH1_SRCCFG;
+  union {    /* DMA_CH2_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_CH2_SRCCFG Bits */
+      __IO uint32_t bDMA_SRC            	:	8;  /* Device level DMA source mapping to channel input */
+      __I  uint32_t bRESERVED0          	:	24;  /* Reserved */
+    } b;
+  } rCH2_SRCCFG;
+  union {    /* DMA_CH3_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_CH3_SRCCFG Bits */
+      __IO uint32_t bDMA_SRC            	:	8;  /* Device level DMA source mapping to channel input */
+      __I  uint32_t bRESERVED0          	:	24;  /* Reserved */
+    } b;
+  } rCH3_SRCCFG;
+  union {    /* DMA_CH4_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_CH4_SRCCFG Bits */
+      __IO uint32_t bDMA_SRC            	:	8;  /* Device level DMA source mapping to channel input */
+      __I  uint32_t bRESERVED0          	:	24;  /* Reserved */
+    } b;
+  } rCH4_SRCCFG;
+  union {    /* DMA_CH5_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_CH5_SRCCFG Bits */
+      __IO uint32_t bDMA_SRC            	:	8;  /* Device level DMA source mapping to channel input */
+      __I  uint32_t bRESERVED0          	:	24;  /* Reserved */
+    } b;
+  } rCH5_SRCCFG;
+  union {    /* DMA_CH6_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_CH6_SRCCFG Bits */
+      __IO uint32_t bDMA_SRC            	:	8;  /* Device level DMA source mapping to channel input */
+      __I  uint32_t bRESERVED0          	:	24;  /* Reserved */
+    } b;
+  } rCH6_SRCCFG;
+  union {    /* DMA_CH7_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_CH7_SRCCFG Bits */
+      __IO uint32_t bDMA_SRC            	:	8;  /* Device level DMA source mapping to channel input */
+      __I  uint32_t bRESERVED0          	:	24;  /* Reserved */
+    } b;
+  } rCH7_SRCCFG;
+  union {    /* DMA_CH8_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_CH8_SRCCFG Bits */
+      __IO uint32_t bDMA_SRC            	:	8;  /* Device level DMA source mapping to channel input */
+      __I  uint32_t bRESERVED0          	:	24;  /* Reserved */
+    } b;
+  } rCH8_SRCCFG;
+  union {    /* DMA_CH9_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_CH9_SRCCFG Bits */
+      __IO uint32_t bDMA_SRC            	:	8;  /* Device level DMA source mapping to channel input */
+      __I  uint32_t bRESERVED0          	:	24;  /* Reserved */
+    } b;
+  } rCH9_SRCCFG;
+  union {    /* DMA_CH10_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_CH10_SRCCFG Bits */
+      __IO uint32_t bDMA_SRC            	:	8;  /* Device level DMA source mapping to channel input */
+      __I  uint32_t bRESERVED0          	:	24;  /* Reserved */
+    } b;
+  } rCH10_SRCCFG;
+  union {    /* DMA_CH11_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_CH11_SRCCFG Bits */
+      __IO uint32_t bDMA_SRC            	:	8;  /* Device level DMA source mapping to channel input */
+      __I  uint32_t bRESERVED0          	:	24;  /* Reserved */
+    } b;
+  } rCH11_SRCCFG;
+  union {    /* DMA_CH12_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_CH12_SRCCFG Bits */
+      __IO uint32_t bDMA_SRC            	:	8;  /* Device level DMA source mapping to channel input */
+      __I  uint32_t bRESERVED0          	:	24;  /* Reserved */
+    } b;
+  } rCH12_SRCCFG;
+  union {    /* DMA_CH13_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_CH13_SRCCFG Bits */
+      __IO uint32_t bDMA_SRC            	:	8;  /* Device level DMA source mapping to channel input */
+      __I  uint32_t bRESERVED0          	:	24;  /* Reserved */
+    } b;
+  } rCH13_SRCCFG;
+  union {    /* DMA_CH14_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_CH14_SRCCFG Bits */
+      __IO uint32_t bDMA_SRC            	:	8;  /* Device level DMA source mapping to channel input */
+      __I  uint32_t bRESERVED0          	:	24;  /* Reserved */
+    } b;
+  } rCH14_SRCCFG;
+  union {    /* DMA_CH15_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_CH15_SRCCFG Bits */
+      __IO uint32_t bDMA_SRC            	:	8;  /* Device level DMA source mapping to channel input */
+      __I  uint32_t bRESERVED0          	:	24;  /* Reserved */
+    } b;
+  } rCH15_SRCCFG;
+  union {    /* DMA_CH16_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_CH16_SRCCFG Bits */
+      __IO uint32_t bDMA_SRC            	:	8;  /* Device level DMA source mapping to channel input */
+      __I  uint32_t bRESERVED0          	:	24;  /* Reserved */
+    } b;
+  } rCH16_SRCCFG;
+  union {    /* DMA_CH17_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_CH17_SRCCFG Bits */
+      __IO uint32_t bDMA_SRC            	:	8;  /* Device level DMA source mapping to channel input */
+      __I  uint32_t bRESERVED0          	:	24;  /* Reserved */
+    } b;
+  } rCH17_SRCCFG;
+  union {    /* DMA_CH18_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_CH18_SRCCFG Bits */
+      __IO uint32_t bDMA_SRC            	:	8;  /* Device level DMA source mapping to channel input */
+      __I  uint32_t bRESERVED0          	:	24;  /* Reserved */
+    } b;
+  } rCH18_SRCCFG;
+  union {    /* DMA_CH19_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_CH19_SRCCFG Bits */
+      __IO uint32_t bDMA_SRC            	:	8;  /* Device level DMA source mapping to channel input */
+      __I  uint32_t bRESERVED0          	:	24;  /* Reserved */
+    } b;
+  } rCH19_SRCCFG;
+  union {    /* DMA_CH20_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_CH20_SRCCFG Bits */
+      __IO uint32_t bDMA_SRC            	:	8;  /* Device level DMA source mapping to channel input */
+      __I  uint32_t bRESERVED0          	:	24;  /* Reserved */
+    } b;
+  } rCH20_SRCCFG;
+  union {    /* DMA_CH21_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_CH21_SRCCFG Bits */
+      __IO uint32_t bDMA_SRC            	:	8;  /* Device level DMA source mapping to channel input */
+      __I  uint32_t bRESERVED0          	:	24;  /* Reserved */
+    } b;
+  } rCH21_SRCCFG;
+  union {    /* DMA_CH22_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_CH22_SRCCFG Bits */
+      __IO uint32_t bDMA_SRC            	:	8;  /* Device level DMA source mapping to channel input */
+      __I  uint32_t bRESERVED0          	:	24;  /* Reserved */
+    } b;
+  } rCH22_SRCCFG;
+  union {    /* DMA_CH23_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_CH23_SRCCFG Bits */
+      __IO uint32_t bDMA_SRC            	:	8;  /* Device level DMA source mapping to channel input */
+      __I  uint32_t bRESERVED0          	:	24;  /* Reserved */
+    } b;
+  } rCH23_SRCCFG;
+  union {    /* DMA_CH24_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_CH24_SRCCFG Bits */
+      __IO uint32_t bDMA_SRC            	:	8;  /* Device level DMA source mapping to channel input */
+      __I  uint32_t bRESERVED0          	:	24;  /* Reserved */
+    } b;
+  } rCH24_SRCCFG;
+  union {    /* DMA_CH25_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_CH25_SRCCFG Bits */
+      __IO uint32_t bDMA_SRC            	:	8;  /* Device level DMA source mapping to channel input */
+      __I  uint32_t bRESERVED0          	:	24;  /* Reserved */
+    } b;
+  } rCH25_SRCCFG;
+  union {    /* DMA_CH26_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_CH26_SRCCFG Bits */
+      __IO uint32_t bDMA_SRC            	:	8;  /* Device level DMA source mapping to channel input */
+      __I  uint32_t bRESERVED0          	:	24;  /* Reserved */
+    } b;
+  } rCH26_SRCCFG;
+  union {    /* DMA_CH27_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_CH27_SRCCFG Bits */
+      __IO uint32_t bDMA_SRC            	:	8;  /* Device level DMA source mapping to channel input */
+      __I  uint32_t bRESERVED0          	:	24;  /* Reserved */
+    } b;
+  } rCH27_SRCCFG;
+  union {    /* DMA_CH28_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_CH28_SRCCFG Bits */
+      __IO uint32_t bDMA_SRC            	:	8;  /* Device level DMA source mapping to channel input */
+      __I  uint32_t bRESERVED0          	:	24;  /* Reserved */
+    } b;
+  } rCH28_SRCCFG;
+  union {    /* DMA_CH29_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_CH29_SRCCFG Bits */
+      __IO uint32_t bDMA_SRC            	:	8;  /* Device level DMA source mapping to channel input */
+      __I  uint32_t bRESERVED0          	:	24;  /* Reserved */
+    } b;
+  } rCH29_SRCCFG;
+  union {    /* DMA_CH30_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_CH30_SRCCFG Bits */
+      __IO uint32_t bDMA_SRC            	:	8;  /* Device level DMA source mapping to channel input */
+      __I  uint32_t bRESERVED0          	:	24;  /* Reserved */
+    } b;
+  } rCH30_SRCCFG;
+  union {    /* DMA_CH31_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_CH31_SRCCFG Bits */
+      __IO uint32_t bDMA_SRC            	:	8;  /* Device level DMA source mapping to channel input */
+      __I  uint32_t bRESERVED0          	:	24;  /* Reserved */
+    } b;
+  } rCH31_SRCCFG;
+  uint8_t  RESERVED1[112];
+  union {    /* DMA_INT1_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_INT1_SRCCFG Bits */
+      __IO uint32_t bINT_SRC            	:	5;  /* Controls which channel's completion event is mapped as a source of this Interrupt */
+      __IO uint32_t bEN                 	:	1;  /* Enables DMA_INT1 mapping */
+      __I  uint32_t bRESERVED0          	:	26;  /* Reserved */
+    } b;
+  } rINT1_SRCCFG;
+  union {    /* DMA_INT2_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_INT2_SRCCFG Bits */
+      __IO uint32_t bINT_SRC            	:	5;  /* Controls which channel's completion event is mapped as a source of this Interrupt */
+      __IO uint32_t bEN                 	:	1;  /* Enables DMA_INT2 mapping */
+      __I  uint32_t bRESERVED0          	:	26;  /* Reserved */
+    } b;
+  } rINT2_SRCCFG;
+  union {    /* DMA_INT3_SRCCFG Register */
+    __IO uint32_t r;
+    struct { /* DMA_INT3_SRCCFG Bits */
+      __IO uint32_t bINT_SRC            	:	5;  /* Controls which channel's completion event is mapped as a source of this Interrupt */
+      __IO uint32_t bEN                 	:	1;  /* Enables DMA_INT3 mapping */
+      __I  uint32_t bRESERVED0          	:	26;  /* Reserved */
+    } b;
+  } rINT3_SRCCFG;
+  uint8_t  RESERVED2[4];
+  union {    /* DMA_INT0_SRCFLG Register */
+    __I uint32_t r;
+    struct { /* DMA_INT0_SRCFLG Bits */
+      __I  uint32_t bCH0                	:	1;  /* Channel 0 was the source of DMA_INT0 */
+      __I  uint32_t bCH1                	:	1;  /* Channel 1 was the source of DMA_INT0 */
+      __I  uint32_t bCH2                	:	1;  /* Channel 2 was the source of DMA_INT0 */
+      __I  uint32_t bCH3                	:	1;  /* Channel 3 was the source of DMA_INT0 */
+      __I  uint32_t bCH4                	:	1;  /* Channel 4 was the source of DMA_INT0 */
+      __I  uint32_t bCH5                	:	1;  /* Channel 5 was the source of DMA_INT0 */
+      __I  uint32_t bCH6                	:	1;  /* Channel 6 was the source of DMA_INT0 */
+      __I  uint32_t bCH7                	:	1;  /* Channel 7 was the source of DMA_INT0 */
+      __I  uint32_t bCH8                	:	1;  /* Channel 8 was the source of DMA_INT0 */
+      __I  uint32_t bCH9                	:	1;  /* Channel 9 was the source of DMA_INT0 */
+      __I  uint32_t bCH10               	:	1;  /* Channel 10 was the source of DMA_INT0 */
+      __I  uint32_t bCH11               	:	1;  /* Channel 11 was the source of DMA_INT0 */
+      __I  uint32_t bCH12               	:	1;  /* Channel 12 was the source of DMA_INT0 */
+      __I  uint32_t bCH13               	:	1;  /* Channel 13 was the source of DMA_INT0 */
+      __I  uint32_t bCH14               	:	1;  /* Channel 14 was the source of DMA_INT0 */
+      __I  uint32_t bCH15               	:	1;  /* Channel 15 was the source of DMA_INT0 */
+      __I  uint32_t bCH16               	:	1;  /* Channel 16 was the source of DMA_INT0 */
+      __I  uint32_t bCH17               	:	1;  /* Channel 17 was the source of DMA_INT0 */
+      __I  uint32_t bCH18               	:	1;  /* Channel 18 was the source of DMA_INT0 */
+      __I  uint32_t bCH19               	:	1;  /* Channel 19 was the source of DMA_INT0 */
+      __I  uint32_t bCH20               	:	1;  /* Channel 20 was the source of DMA_INT0 */
+      __I  uint32_t bCH21               	:	1;  /* Channel 21 was the source of DMA_INT0 */
+      __I  uint32_t bCH22               	:	1;  /* Channel 22 was the source of DMA_INT0 */
+      __I  uint32_t bCH23               	:	1;  /* Channel 23 was the source of DMA_INT0 */
+      __I  uint32_t bCH24               	:	1;  /* Channel 24 was the source of DMA_INT0 */
+      __I  uint32_t bCH25               	:	1;  /* Channel 25 was the source of DMA_INT0 */
+      __I  uint32_t bCH26               	:	1;  /* Channel 26 was the source of DMA_INT0 */
+      __I  uint32_t bCH27               	:	1;  /* Channel 27 was the source of DMA_INT0 */
+      __I  uint32_t bCH28               	:	1;  /* Channel 28 was the source of DMA_INT0 */
+      __I  uint32_t bCH29               	:	1;  /* Channel 29 was the source of DMA_INT0 */
+      __I  uint32_t bCH30               	:	1;  /* Channel 30 was the source of DMA_INT0 */
+      __I  uint32_t bCH31               	:	1;  /* Channel 31 was the source of DMA_INT0 */
+    } b;
+  } rINT0_SRCFLG;
+  union {    /* DMA_INT0_CLRFLG Register */
+    __O uint32_t r;
+    struct { /* DMA_INT0_CLRFLG Bits */
+      __O  uint32_t bCH0                	:	1;  /* Clear corresponding DMA_INT0_SRCFLG_REG */
+      __O  uint32_t bCH1                	:	1;  /* Clear corresponding DMA_INT0_SRCFLG_REG */
+      __O  uint32_t bCH2                	:	1;  /* Clear corresponding DMA_INT0_SRCFLG_REG */
+      __O  uint32_t bCH3                	:	1;  /* Clear corresponding DMA_INT0_SRCFLG_REG */
+      __O  uint32_t bCH4                	:	1;  /* Clear corresponding DMA_INT0_SRCFLG_REG */
+      __O  uint32_t bCH5                	:	1;  /* Clear corresponding DMA_INT0_SRCFLG_REG */
+      __O  uint32_t bCH6                	:	1;  /* Clear corresponding DMA_INT0_SRCFLG_REG */
+      __O  uint32_t bCH7                	:	1;  /* Clear corresponding DMA_INT0_SRCFLG_REG */
+      __O  uint32_t bCH8                	:	1;  /* Clear corresponding DMA_INT0_SRCFLG_REG */
+      __O  uint32_t bCH9                	:	1;  /* Clear corresponding DMA_INT0_SRCFLG_REG */
+      __O  uint32_t bCH10               	:	1;  /* Clear corresponding DMA_INT0_SRCFLG_REG */
+      __O  uint32_t bCH11               	:	1;  /* Clear corresponding DMA_INT0_SRCFLG_REG */
+      __O  uint32_t bCH12               	:	1;  /* Clear corresponding DMA_INT0_SRCFLG_REG */
+      __O  uint32_t bCH13               	:	1;  /* Clear corresponding DMA_INT0_SRCFLG_REG */
+      __O  uint32_t bCH14               	:	1;  /* Clear corresponding DMA_INT0_SRCFLG_REG */
+      __O  uint32_t bCH15               	:	1;  /* Clear corresponding DMA_INT0_SRCFLG_REG */
+      __O  uint32_t bCH16               	:	1;  /* Clear corresponding DMA_INT0_SRCFLG_REG */
+      __O  uint32_t bCH17               	:	1;  /* Clear corresponding DMA_INT0_SRCFLG_REG */
+      __O  uint32_t bCH18               	:	1;  /* Clear corresponding DMA_INT0_SRCFLG_REG */
+      __O  uint32_t bCH19               	:	1;  /* Clear corresponding DMA_INT0_SRCFLG_REG */
+      __O  uint32_t bCH20               	:	1;  /* Clear corresponding DMA_INT0_SRCFLG_REG */
+      __O  uint32_t bCH21               	:	1;  /* Clear corresponding DMA_INT0_SRCFLG_REG */
+      __O  uint32_t bCH22               	:	1;  /* Clear corresponding DMA_INT0_SRCFLG_REG */
+      __O  uint32_t bCH23               	:	1;  /* Clear corresponding DMA_INT0_SRCFLG_REG */
+      __O  uint32_t bCH24               	:	1;  /* Clear corresponding DMA_INT0_SRCFLG_REG */
+      __O  uint32_t bCH25               	:	1;  /* Clear corresponding DMA_INT0_SRCFLG_REG */
+      __O  uint32_t bCH26               	:	1;  /* Clear corresponding DMA_INT0_SRCFLG_REG */
+      __O  uint32_t bCH27               	:	1;  /* Clear corresponding DMA_INT0_SRCFLG_REG */
+      __O  uint32_t bCH28               	:	1;  /* Clear corresponding DMA_INT0_SRCFLG_REG */
+      __O  uint32_t bCH29               	:	1;  /* Clear corresponding DMA_INT0_SRCFLG_REG */
+      __O  uint32_t bCH30               	:	1;  /* Clear corresponding DMA_INT0_SRCFLG_REG */
+      __O  uint32_t bCH31               	:	1;  /* Clear corresponding DMA_INT0_SRCFLG_REG */
+    } b;
+  } rINT0_CLRFLG;
+  uint8_t  RESERVED3[3816];
+  union {    /* DMA_STAT Register */
+    __I uint32_t r;
+    struct { /* DMA_STAT Bits */
+      __I  uint32_t bMASTEN             	:	1;  /*  */
+      __I  uint32_t bRESERVED0          	:	3;  /* Reserved */
+      __I  uint32_t b                   	:	4;  /*  */
+      __I  uint32_t bRESERVED1          	:	8;  /* Reserved */
+      __I  uint32_t bRESERVED2          	:	7;  /* Reserved */
+    } b;
+  } rSTAT;
+  union {    /* DMA_CFG Register */
+    __O uint32_t r;
+    struct { /* DMA_CFG Bits */
+      __O  uint32_t b                   	:	1;  /*  */
+      __O  uint32_t bRESERVED0          	:	4;  /* Reserved */
+      __O  uint32_t bRESERVED1          	:	24;  /* Reserved */
+    } b;
+  } rCFG;
+  union {    /* DMA_CTLBASE Register */
+    __IO uint32_t r;
+    struct { /* DMA_CTLBASE Bits */
+      __I  uint32_t bRESERVED0          	:	5;  /* Reserved */
+      __IO uint32_t b                   	:	27;  /*  */
+    } b;
+  } rCTLBASE;
+  __I uint32_t rATLBASE; /* Channel Alternate Control Data Base Pointer Register */
+  __I uint32_t rWAITSTAT; /* Channel Wait on Request Status Register */
+  __O uint32_t rSWREQ; /* Channel Software Request Register */
+  __IO uint32_t rUSEBURSTSET; /* Channel Useburst Set Register */
+  __O uint32_t rUSEBURSTCLR; /* Channel Useburst Clear Register */
+  __IO uint32_t rREQMASKSET; /* Channel Request Mask Set Register */
+  __O uint32_t rREQMASKCLR; /* Channel Request Mask Clear Register */
+  __IO uint32_t rENASET; /* Channel Enable Set Register */
+  __O uint32_t rENACLR; /* Channel Enable Clear Register */
+  __IO uint32_t rALTSET; /* Channel Primary-Alternate Set Register */
+  __O uint32_t rALTCLR; /* Channel Primary-Alternate Clear Register */
+  __IO uint32_t rPRIOSET; /* Channel Priority Set Register */
+  __O uint32_t rPRIOCLR; /* Channel Priority Clear Register */
+  uint8_t  RESERVED4[12];
+  union {    /* DMA_ERRCLR Register */
+    __IO uint32_t r;
+    struct { /* DMA_ERRCLR Bits */
+      __IO uint32_t b                   	:	1;  /*  */
+      __I  uint32_t bRESERVED0          	:	31;  /* Reserved */
+    } b;
+  } rERRCLR;
+} DMA_Type;
+
+
+//*****************************************************************************
+// EUSCI_A0 Registers
+//*****************************************************************************
+typedef struct {
+  union {    /* UCA0CTLW0 Register */
+    __IO uint16_t r;
+    struct { /* UCA0CTLW0 Bits */
+      __IO uint16_t bSWRST              	:	1;  /* Software reset enable */
+      __IO uint16_t bTXBRK              	:	1;  /* Transmit break */
+      __IO uint16_t bTXADDR             	:	1;  /* Transmit address */
+      __IO uint16_t bDORM               	:	1;  /* Dormant */
+      __IO uint16_t bBRKIE              	:	1;  /* Receive break character interrupt enable */
+      __IO uint16_t bRXEIE              	:	1;  /* Receive erroneous-character interrupt enable */
+      __IO uint16_t bSSEL               	:	2;  /* eUSCI_A clock source select */
+      __IO uint16_t bSYNC               	:	1;  /* Synchronous mode enable */
+      __IO uint16_t bMODE               	:	2;  /* eUSCI_A mode */
+      __IO uint16_t bSPB                	:	1;  /* Stop bit select */
+      __IO uint16_t b7BIT               	:	1;  /* Character length */
+      __IO uint16_t bMSB                	:	1;  /* MSB first select */
+      __IO uint16_t bPAR                	:	1;  /* Parity select */
+      __IO uint16_t bPEN                	:	1;  /* Parity enable */
+    } b;
+    struct { /* UCA0CTLW0_SPI Bits */
+      __IO uint16_t bSWRST              	:	1;  /* Software reset enable */
+      __IO uint16_t bSTEM               	:	1;  /* STE mode select in master mode. */
+      __I  uint16_t bRESERVED           	:	4;  /* Reserved */
+      __IO uint16_t bSSEL               	:	2;  /* eUSCI_A clock source select */
+      __IO uint16_t bSYNC               	:	1;  /* Synchronous mode enable */
+      __IO uint16_t bMODE               	:	2;  /* eUSCI mode */
+      __IO uint16_t bMST                	:	1;  /* Master mode select */
+      __IO uint16_t b7BIT               	:	1;  /* Character length */
+      __IO uint16_t bMSB                	:	1;  /* MSB first select */
+      __IO uint16_t bCKPL               	:	1;  /* Clock polarity select */
+      __IO uint16_t bCKPH               	:	1;  /* Clock phase select */
+    } a;
+  } rCTLW0;
+  union {    /* UCA0CTLW1 Register */
+    __IO uint16_t r;
+    struct { /* UCA0CTLW1 Bits */
+      __IO uint16_t bGLIT               	:	2;  /* Deglitch time */
+      __I  uint16_t bRESERVED0          	:	14;  /* Reserved */
+    } b;
+  } rCTLW1;
+  uint8_t  RESERVED0[2];
+  __IO uint16_t rBRW; /* eUSCI_Ax Baud Rate Control Word Register */
+  union {    /* UCA0MCTLW Register */
+    __IO uint16_t r;
+    struct { /* UCA0MCTLW Bits */
+      __IO uint16_t bOS16               	:	1;  /* Oversampling mode enabled */
+      __I  uint16_t bRESERVED0          	:	3;  /* Reserved */
+      __IO uint16_t bBRF                	:	4;  /* First modulation stage select */
+      __IO uint16_t bBRS                	:	8;  /* Second modulation stage select */
+    } b;
+  } rMCTLW;
+  union {    /* UCA0STATW Register */
+    __IO uint16_t r;
+    struct { /* UCA0STATW Bits */
+      __I  uint16_t bBUSY               	:	1;  /* eUSCI_A busy */
+      __IO uint16_t bADDR_IDLE          	:	1;  /* Address received / Idle line detected */
+      __IO uint16_t bRXERR              	:	1;  /* Receive error flag */
+      __IO uint16_t bBRK                	:	1;  /* Break detect flag */
+      __IO uint16_t bPE                 	:	1;  /*  */
+      __IO uint16_t bOE                 	:	1;  /* Overrun error flag */
+      __IO uint16_t bFE                 	:	1;  /* Framing error flag */
+      __IO uint16_t bLISTEN             	:	1;  /* Listen enable */
+      __I  uint16_t bRESERVED0          	:	8;  /* Reserved */
+    } b;
+    struct { /* UCA0STATW_SPI Bits */
+      __I  uint16_t bBUSY               	:	1;  /* eUSCI_A busy */
+      __IO uint16_t bRESERVED           	:	4;  /* Reserved */
+      __IO uint16_t bOE                 	:	1;  /* Overrun error flag */
+      __IO uint16_t bFE                 	:	1;  /* Framing error flag */
+      __IO uint16_t bLISTEN             	:	1;  /* Listen enable */
+    } a;
+  } rSTATW;
+  union {    /* UCA0RXBUF Register */
+    __I uint16_t r;
+    struct { /* UCA0RXBUF Bits */
+      __I  uint16_t bRXBUF              	:	8;  /* Receive data buffer */
+      __I  uint16_t bRESERVED0          	:	8;  /* Reserved */
+    } b;
+    struct { /* UCA0RXBUF_SPI Bits */
+      __I  uint16_t bRXBUF              	:	8;  /* Receive data buffer */
+      __I  uint16_t bRESERVED           	:	8;  /* Reserved */
+    } a;
+  } rRXBUF;
+  union {    /* UCA0TXBUF Register */
+    __IO uint16_t r;
+    struct { /* UCA0TXBUF Bits */
+      __IO uint16_t bTXBUF              	:	8;  /* Transmit data buffer */
+      __I  uint16_t bRESERVED0          	:	8;  /* Reserved */
+    } b;
+    struct { /* UCA0TXBUF_SPI Bits */
+      __IO uint16_t bTXBUF              	:	8;  /* Transmit data buffer */
+      __I  uint16_t bRESERVED           	:	8;  /* Reserved */
+    } a;
+  } rTXBUF;
+  union {    /* UCA0ABCTL Register */
+    __IO uint16_t r;
+    struct { /* UCA0ABCTL Bits */
+      __IO uint16_t bABDEN              	:	1;  /* Automatic baud-rate detect enable */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bBTOE               	:	1;  /* Break time out error */
+      __IO uint16_t bSTOE               	:	1;  /* Synch field time out error */
+      __IO uint16_t bDELIM              	:	2;  /* Break/synch delimiter length */
+      __I  uint16_t bRESERVED1          	:	10;  /* Reserved */
+    } b;
+  } rABCTL;
+  union {    /* UCA0IRCTL Register */
+    __IO uint16_t r;
+    struct { /* UCA0IRCTL Bits */
+      __IO uint16_t bIREN               	:	1;  /* IrDA encoder/decoder enable */
+      __IO uint16_t bIRTXCLK            	:	1;  /* IrDA transmit pulse clock select */
+      __IO uint16_t bIRTXPL             	:	6;  /* Transmit pulse length */
+      __IO uint16_t bIRRXFE             	:	1;  /* IrDA receive filter enabled */
+      __IO uint16_t bIRRXPL             	:	1;  /* IrDA receive input UCAxRXD polarity */
+      __IO uint16_t bIRRXFL             	:	4;  /* Receive filter length */
+    } b;
+  } rIRCTL;
+  uint8_t  RESERVED1[6];
+  union {    /* UCA0IE Register */
+    __IO uint16_t r;
+    struct { /* UCA0IE Bits */
+      __IO uint16_t bRXIE               	:	1;  /* Receive interrupt enable */
+      __IO uint16_t bTXIE               	:	1;  /* Transmit interrupt enable */
+      __IO uint16_t bSTTIE              	:	1;  /* Start bit interrupt enable */
+      __IO uint16_t bTXCPTIE            	:	1;  /* Transmit complete interrupt enable */
+      __I  uint16_t bRESERVED0          	:	12;  /* Reserved */
+    } b;
+    struct { /* UCA0IE_SPI Bits */
+      __IO uint16_t bRXIE               	:	1;  /* Receive interrupt enable */
+      __IO uint16_t bTXIE               	:	1;  /* Transmit interrupt enable */
+      __I  uint16_t bRESERVED           	:	14;  /* Reserved */
+    } a;
+  } rIE;
+  union {    /* UCA0IFG Register */
+    __IO uint16_t r;
+    struct { /* UCA0IFG Bits */
+      __IO uint16_t bRXIFG              	:	1;  /* Receive interrupt flag */
+      __IO uint16_t bTXIFG              	:	1;  /* Transmit interrupt flag */
+      __IO uint16_t bSTTIFG             	:	1;  /* Start bit interrupt flag */
+      __IO uint16_t bTXCPTIFG           	:	1;  /* Transmit ready interrupt enable */
+      __I  uint16_t bRESERVED0          	:	12;  /* Reserved */
+    } b;
+    struct { /* UCA0IFG_SPI Bits */
+      __IO uint16_t bRXIFG              	:	1;  /* Receive interrupt flag */
+      __IO uint16_t bTXIFG              	:	1;  /* Transmit interrupt flag */
+      __I  uint16_t bRESERVED           	:	14;  /* Reserved */
+    } a;
+  } rIFG;
+  __I uint16_t rIV; /* eUSCI_Ax Interrupt Vector Register */
+} EUSCI_A0_Type;
+
+
+//*****************************************************************************
+// EUSCI_A1 Registers
+//*****************************************************************************
+typedef struct {
+  union {    /* UCA1CTLW0 Register */
+    __IO uint16_t r;
+    struct { /* UCA1CTLW0 Bits */
+      __IO uint16_t bSWRST              	:	1;  /* Software reset enable */
+      __IO uint16_t bTXBRK              	:	1;  /* Transmit break */
+      __IO uint16_t bTXADDR             	:	1;  /* Transmit address */
+      __IO uint16_t bDORM               	:	1;  /* Dormant */
+      __IO uint16_t bBRKIE              	:	1;  /* Receive break character interrupt enable */
+      __IO uint16_t bRXEIE              	:	1;  /* Receive erroneous-character interrupt enable */
+      __IO uint16_t bSSEL               	:	2;  /* eUSCI_A clock source select */
+      __IO uint16_t bSYNC               	:	1;  /* Synchronous mode enable */
+      __IO uint16_t bMODE               	:	2;  /* eUSCI_A mode */
+      __IO uint16_t bSPB                	:	1;  /* Stop bit select */
+      __IO uint16_t b7BIT               	:	1;  /* Character length */
+      __IO uint16_t bMSB                	:	1;  /* MSB first select */
+      __IO uint16_t bPAR                	:	1;  /* Parity select */
+      __IO uint16_t bPEN                	:	1;  /* Parity enable */
+    } b;
+    struct { /* UCA1CTLW0_SPI Bits */
+      __IO uint16_t bSWRST              	:	1;  /* Software reset enable */
+      __IO uint16_t bSTEM               	:	1;  /* STE mode select in master mode. */
+      __I  uint16_t bRESERVED           	:	4;  /* Reserved */
+      __IO uint16_t bSSEL               	:	2;  /* eUSCI_A clock source select */
+      __IO uint16_t bSYNC               	:	1;  /* Synchronous mode enable */
+      __IO uint16_t bMODE               	:	2;  /* eUSCI mode */
+      __IO uint16_t bMST                	:	1;  /* Master mode select */
+      __IO uint16_t b7BIT               	:	1;  /* Character length */
+      __IO uint16_t bMSB                	:	1;  /* MSB first select */
+      __IO uint16_t bCKPL               	:	1;  /* Clock polarity select */
+      __IO uint16_t bCKPH               	:	1;  /* Clock phase select */
+    } a;
+  } rCTLW0;
+  union {    /* UCA1CTLW1 Register */
+    __IO uint16_t r;
+    struct { /* UCA1CTLW1 Bits */
+      __IO uint16_t bGLIT               	:	2;  /* Deglitch time */
+      __I  uint16_t bRESERVED0          	:	14;  /* Reserved */
+    } b;
+  } rCTLW1;
+  uint8_t  RESERVED0[2];
+  __IO uint16_t rBRW; /* eUSCI_Ax Baud Rate Control Word Register */
+  union {    /* UCA1MCTLW Register */
+    __IO uint16_t r;
+    struct { /* UCA1MCTLW Bits */
+      __IO uint16_t bOS16               	:	1;  /* Oversampling mode enabled */
+      __I  uint16_t bRESERVED0          	:	3;  /* Reserved */
+      __IO uint16_t bBRF                	:	4;  /* First modulation stage select */
+      __IO uint16_t bBRS                	:	8;  /* Second modulation stage select */
+    } b;
+  } rMCTLW;
+  union {    /* UCA1STATW Register */
+    __IO uint16_t r;
+    struct { /* UCA1STATW Bits */
+      __I  uint16_t bBUSY               	:	1;  /* eUSCI_A busy */
+      __IO uint16_t bADDR_IDLE          	:	1;  /* Address received / Idle line detected */
+      __IO uint16_t bRXERR              	:	1;  /* Receive error flag */
+      __IO uint16_t bBRK                	:	1;  /* Break detect flag */
+      __IO uint16_t bPE                 	:	1;  /*  */
+      __IO uint16_t bOE                 	:	1;  /* Overrun error flag */
+      __IO uint16_t bFE                 	:	1;  /* Framing error flag */
+      __IO uint16_t bLISTEN             	:	1;  /* Listen enable */
+      __I  uint16_t bRESERVED0          	:	8;  /* Reserved */
+    } b;
+    struct { /* UCA1STATW_SPI Bits */
+      __I  uint16_t bBUSY               	:	1;  /* eUSCI_A busy */
+      __IO uint16_t bRESERVED           	:	4;  /* Reserved */
+      __IO uint16_t bOE                 	:	1;  /* Overrun error flag */
+      __IO uint16_t bFE                 	:	1;  /* Framing error flag */
+      __IO uint16_t bLISTEN             	:	1;  /* Listen enable */
+    } a;
+  } rSTATW;
+  union {    /* UCA1RXBUF Register */
+    __I uint16_t r;
+    struct { /* UCA1RXBUF Bits */
+      __I  uint16_t bRXBUF              	:	8;  /* Receive data buffer */
+      __I  uint16_t bRESERVED0          	:	8;  /* Reserved */
+    } b;
+    struct { /* UCA1RXBUF_SPI Bits */
+      __I  uint16_t bRXBUF              	:	8;  /* Receive data buffer */
+      __I  uint16_t bRESERVED           	:	8;  /* Reserved */
+    } a;
+  } rRXBUF;
+  union {    /* UCA1TXBUF Register */
+    __IO uint16_t r;
+    struct { /* UCA1TXBUF Bits */
+      __IO uint16_t bTXBUF              	:	8;  /* Transmit data buffer */
+      __I  uint16_t bRESERVED0          	:	8;  /* Reserved */
+    } b;
+    struct { /* UCA1TXBUF_SPI Bits */
+      __IO uint16_t bTXBUF              	:	8;  /* Transmit data buffer */
+      __I  uint16_t bRESERVED           	:	8;  /* Reserved */
+    } a;
+  } rTXBUF;
+  union {    /* UCA1ABCTL Register */
+    __IO uint16_t r;
+    struct { /* UCA1ABCTL Bits */
+      __IO uint16_t bABDEN              	:	1;  /* Automatic baud-rate detect enable */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bBTOE               	:	1;  /* Break time out error */
+      __IO uint16_t bSTOE               	:	1;  /* Synch field time out error */
+      __IO uint16_t bDELIM              	:	2;  /* Break/synch delimiter length */
+      __I  uint16_t bRESERVED1          	:	10;  /* Reserved */
+    } b;
+  } rABCTL;
+  union {    /* UCA1IRCTL Register */
+    __IO uint16_t r;
+    struct { /* UCA1IRCTL Bits */
+      __IO uint16_t bIREN               	:	1;  /* IrDA encoder/decoder enable */
+      __IO uint16_t bIRTXCLK            	:	1;  /* IrDA transmit pulse clock select */
+      __IO uint16_t bIRTXPL             	:	6;  /* Transmit pulse length */
+      __IO uint16_t bIRRXFE             	:	1;  /* IrDA receive filter enabled */
+      __IO uint16_t bIRRXPL             	:	1;  /* IrDA receive input UCAxRXD polarity */
+      __IO uint16_t bIRRXFL             	:	4;  /* Receive filter length */
+    } b;
+  } rIRCTL;
+  uint8_t  RESERVED1[6];
+  union {    /* UCA1IE Register */
+    __IO uint16_t r;
+    struct { /* UCA1IE Bits */
+      __IO uint16_t bRXIE               	:	1;  /* Receive interrupt enable */
+      __IO uint16_t bTXIE               	:	1;  /* Transmit interrupt enable */
+      __IO uint16_t bSTTIE              	:	1;  /* Start bit interrupt enable */
+      __IO uint16_t bTXCPTIE            	:	1;  /* Transmit complete interrupt enable */
+      __I  uint16_t bRESERVED0          	:	12;  /* Reserved */
+    } b;
+    struct { /* UCA1IE_SPI Bits */
+      __IO uint16_t bRXIE               	:	1;  /* Receive interrupt enable */
+      __IO uint16_t bTXIE               	:	1;  /* Transmit interrupt enable */
+      __I  uint16_t bRESERVED           	:	14;  /* Reserved */
+    } a;
+  } rIE;
+  union {    /* UCA1IFG Register */
+    __IO uint16_t r;
+    struct { /* UCA1IFG Bits */
+      __IO uint16_t bRXIFG              	:	1;  /* Receive interrupt flag */
+      __IO uint16_t bTXIFG              	:	1;  /* Transmit interrupt flag */
+      __IO uint16_t bSTTIFG             	:	1;  /* Start bit interrupt flag */
+      __IO uint16_t bTXCPTIFG           	:	1;  /* Transmit ready interrupt enable */
+      __I  uint16_t bRESERVED0          	:	12;  /* Reserved */
+    } b;
+    struct { /* UCA1IFG_SPI Bits */
+      __IO uint16_t bRXIFG              	:	1;  /* Receive interrupt flag */
+      __IO uint16_t bTXIFG              	:	1;  /* Transmit interrupt flag */
+      __I  uint16_t bRESERVED           	:	14;  /* Reserved */
+    } a;
+  } rIFG;
+  __I uint16_t rIV; /* eUSCI_Ax Interrupt Vector Register */
+} EUSCI_A1_Type;
+
+
+//*****************************************************************************
+// EUSCI_A2 Registers
+//*****************************************************************************
+typedef struct {
+  union {    /* UCA2CTLW0 Register */
+    __IO uint16_t r;
+    struct { /* UCA2CTLW0 Bits */
+      __IO uint16_t bSWRST              	:	1;  /* Software reset enable */
+      __IO uint16_t bTXBRK              	:	1;  /* Transmit break */
+      __IO uint16_t bTXADDR             	:	1;  /* Transmit address */
+      __IO uint16_t bDORM               	:	1;  /* Dormant */
+      __IO uint16_t bBRKIE              	:	1;  /* Receive break character interrupt enable */
+      __IO uint16_t bRXEIE              	:	1;  /* Receive erroneous-character interrupt enable */
+      __IO uint16_t bSSEL               	:	2;  /* eUSCI_A clock source select */
+      __IO uint16_t bSYNC               	:	1;  /* Synchronous mode enable */
+      __IO uint16_t bMODE               	:	2;  /* eUSCI_A mode */
+      __IO uint16_t bSPB                	:	1;  /* Stop bit select */
+      __IO uint16_t b7BIT               	:	1;  /* Character length */
+      __IO uint16_t bMSB                	:	1;  /* MSB first select */
+      __IO uint16_t bPAR                	:	1;  /* Parity select */
+      __IO uint16_t bPEN                	:	1;  /* Parity enable */
+    } b;
+    struct { /* UCA2CTLW0_SPI Bits */
+      __IO uint16_t bSWRST              	:	1;  /* Software reset enable */
+      __IO uint16_t bSTEM               	:	1;  /* STE mode select in master mode. */
+      __I  uint16_t bRESERVED           	:	4;  /* Reserved */
+      __IO uint16_t bSSEL               	:	2;  /* eUSCI_A clock source select */
+      __IO uint16_t bSYNC               	:	1;  /* Synchronous mode enable */
+      __IO uint16_t bMODE               	:	2;  /* eUSCI mode */
+      __IO uint16_t bMST                	:	1;  /* Master mode select */
+      __IO uint16_t b7BIT               	:	1;  /* Character length */
+      __IO uint16_t bMSB                	:	1;  /* MSB first select */
+      __IO uint16_t bCKPL               	:	1;  /* Clock polarity select */
+      __IO uint16_t bCKPH               	:	1;  /* Clock phase select */
+    } a;
+  } rCTLW0;
+  union {    /* UCA2CTLW1 Register */
+    __IO uint16_t r;
+    struct { /* UCA2CTLW1 Bits */
+      __IO uint16_t bGLIT               	:	2;  /* Deglitch time */
+      __I  uint16_t bRESERVED0          	:	14;  /* Reserved */
+    } b;
+  } rCTLW1;
+  uint8_t  RESERVED0[2];
+  __IO uint16_t rBRW; /* eUSCI_Ax Baud Rate Control Word Register */
+  union {    /* UCA2MCTLW Register */
+    __IO uint16_t r;
+    struct { /* UCA2MCTLW Bits */
+      __IO uint16_t bOS16               	:	1;  /* Oversampling mode enabled */
+      __I  uint16_t bRESERVED0          	:	3;  /* Reserved */
+      __IO uint16_t bBRF                	:	4;  /* First modulation stage select */
+      __IO uint16_t bBRS                	:	8;  /* Second modulation stage select */
+    } b;
+  } rMCTLW;
+  union {    /* UCA2STATW Register */
+    __IO uint16_t r;
+    struct { /* UCA2STATW Bits */
+      __I  uint16_t bBUSY               	:	1;  /* eUSCI_A busy */
+      __IO uint16_t bADDR_IDLE          	:	1;  /* Address received / Idle line detected */
+      __IO uint16_t bRXERR              	:	1;  /* Receive error flag */
+      __IO uint16_t bBRK                	:	1;  /* Break detect flag */
+      __IO uint16_t bPE                 	:	1;  /*  */
+      __IO uint16_t bOE                 	:	1;  /* Overrun error flag */
+      __IO uint16_t bFE                 	:	1;  /* Framing error flag */
+      __IO uint16_t bLISTEN             	:	1;  /* Listen enable */
+      __I  uint16_t bRESERVED0          	:	8;  /* Reserved */
+    } b;
+    struct { /* UCA2STATW_SPI Bits */
+      __I  uint16_t bBUSY               	:	1;  /* eUSCI_A busy */
+      __IO uint16_t bRESERVED           	:	4;  /* Reserved */
+      __IO uint16_t bOE                 	:	1;  /* Overrun error flag */
+      __IO uint16_t bFE                 	:	1;  /* Framing error flag */
+      __IO uint16_t bLISTEN             	:	1;  /* Listen enable */
+    } a;
+  } rSTATW;
+  union {    /* UCA2RXBUF Register */
+    __I uint16_t r;
+    struct { /* UCA2RXBUF Bits */
+      __I  uint16_t bRXBUF              	:	8;  /* Receive data buffer */
+      __I  uint16_t bRESERVED0          	:	8;  /* Reserved */
+    } b;
+    struct { /* UCA2RXBUF_SPI Bits */
+      __I  uint16_t bRXBUF              	:	8;  /* Receive data buffer */
+      __I  uint16_t bRESERVED           	:	8;  /* Reserved */
+    } a;
+  } rRXBUF;
+  union {    /* UCA2TXBUF Register */
+    __IO uint16_t r;
+    struct { /* UCA2TXBUF Bits */
+      __IO uint16_t bTXBUF              	:	8;  /* Transmit data buffer */
+      __I  uint16_t bRESERVED0          	:	8;  /* Reserved */
+    } b;
+    struct { /* UCA2TXBUF_SPI Bits */
+      __IO uint16_t bTXBUF              	:	8;  /* Transmit data buffer */
+      __I  uint16_t bRESERVED           	:	8;  /* Reserved */
+    } a;
+  } rTXBUF;
+  union {    /* UCA2ABCTL Register */
+    __IO uint16_t r;
+    struct { /* UCA2ABCTL Bits */
+      __IO uint16_t bABDEN              	:	1;  /* Automatic baud-rate detect enable */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bBTOE               	:	1;  /* Break time out error */
+      __IO uint16_t bSTOE               	:	1;  /* Synch field time out error */
+      __IO uint16_t bDELIM              	:	2;  /* Break/synch delimiter length */
+      __I  uint16_t bRESERVED1          	:	10;  /* Reserved */
+    } b;
+  } rABCTL;
+  union {    /* UCA2IRCTL Register */
+    __IO uint16_t r;
+    struct { /* UCA2IRCTL Bits */
+      __IO uint16_t bIREN               	:	1;  /* IrDA encoder/decoder enable */
+      __IO uint16_t bIRTXCLK            	:	1;  /* IrDA transmit pulse clock select */
+      __IO uint16_t bIRTXPL             	:	6;  /* Transmit pulse length */
+      __IO uint16_t bIRRXFE             	:	1;  /* IrDA receive filter enabled */
+      __IO uint16_t bIRRXPL             	:	1;  /* IrDA receive input UCAxRXD polarity */
+      __IO uint16_t bIRRXFL             	:	4;  /* Receive filter length */
+    } b;
+  } rIRCTL;
+  uint8_t  RESERVED1[6];
+  union {    /* UCA2IE Register */
+    __IO uint16_t r;
+    struct { /* UCA2IE Bits */
+      __IO uint16_t bRXIE               	:	1;  /* Receive interrupt enable */
+      __IO uint16_t bTXIE               	:	1;  /* Transmit interrupt enable */
+      __IO uint16_t bSTTIE              	:	1;  /* Start bit interrupt enable */
+      __IO uint16_t bTXCPTIE            	:	1;  /* Transmit complete interrupt enable */
+      __I  uint16_t bRESERVED0          	:	12;  /* Reserved */
+    } b;
+    struct { /* UCA2IE_SPI Bits */
+      __IO uint16_t bRXIE               	:	1;  /* Receive interrupt enable */
+      __IO uint16_t bTXIE               	:	1;  /* Transmit interrupt enable */
+      __I  uint16_t bRESERVED           	:	14;  /* Reserved */
+    } a;
+  } rIE;
+  union {    /* UCA2IFG Register */
+    __IO uint16_t r;
+    struct { /* UCA2IFG Bits */
+      __IO uint16_t bRXIFG              	:	1;  /* Receive interrupt flag */
+      __IO uint16_t bTXIFG              	:	1;  /* Transmit interrupt flag */
+      __IO uint16_t bSTTIFG             	:	1;  /* Start bit interrupt flag */
+      __IO uint16_t bTXCPTIFG           	:	1;  /* Transmit ready interrupt enable */
+      __I  uint16_t bRESERVED0          	:	12;  /* Reserved */
+    } b;
+    struct { /* UCA2IFG_SPI Bits */
+      __IO uint16_t bRXIFG              	:	1;  /* Receive interrupt flag */
+      __IO uint16_t bTXIFG              	:	1;  /* Transmit interrupt flag */
+      __I  uint16_t bRESERVED           	:	14;  /* Reserved */
+    } a;
+  } rIFG;
+  __I uint16_t rIV; /* eUSCI_Ax Interrupt Vector Register */
+} EUSCI_A2_Type;
+
+
+//*****************************************************************************
+// EUSCI_A3 Registers
+//*****************************************************************************
+typedef struct {
+  union {    /* UCA3CTLW0 Register */
+    __IO uint16_t r;
+    struct { /* UCA3CTLW0 Bits */
+      __IO uint16_t bSWRST              	:	1;  /* Software reset enable */
+      __IO uint16_t bTXBRK              	:	1;  /* Transmit break */
+      __IO uint16_t bTXADDR             	:	1;  /* Transmit address */
+      __IO uint16_t bDORM               	:	1;  /* Dormant */
+      __IO uint16_t bBRKIE              	:	1;  /* Receive break character interrupt enable */
+      __IO uint16_t bRXEIE              	:	1;  /* Receive erroneous-character interrupt enable */
+      __IO uint16_t bSSEL               	:	2;  /* eUSCI_A clock source select */
+      __IO uint16_t bSYNC               	:	1;  /* Synchronous mode enable */
+      __IO uint16_t bMODE               	:	2;  /* eUSCI_A mode */
+      __IO uint16_t bSPB                	:	1;  /* Stop bit select */
+      __IO uint16_t b7BIT               	:	1;  /* Character length */
+      __IO uint16_t bMSB                	:	1;  /* MSB first select */
+      __IO uint16_t bPAR                	:	1;  /* Parity select */
+      __IO uint16_t bPEN                	:	1;  /* Parity enable */
+    } b;
+    struct { /* UCA3CTLW0_SPI Bits */
+      __IO uint16_t bSWRST              	:	1;  /* Software reset enable */
+      __IO uint16_t bSTEM               	:	1;  /* STE mode select in master mode. */
+      __I  uint16_t bRESERVED           	:	4;  /* Reserved */
+      __IO uint16_t bSSEL               	:	2;  /* eUSCI_A clock source select */
+      __IO uint16_t bSYNC               	:	1;  /* Synchronous mode enable */
+      __IO uint16_t bMODE               	:	2;  /* eUSCI mode */
+      __IO uint16_t bMST                	:	1;  /* Master mode select */
+      __IO uint16_t b7BIT               	:	1;  /* Character length */
+      __IO uint16_t bMSB                	:	1;  /* MSB first select */
+      __IO uint16_t bCKPL               	:	1;  /* Clock polarity select */
+      __IO uint16_t bCKPH               	:	1;  /* Clock phase select */
+    } a;
+  } rCTLW0;
+  union {    /* UCA3CTLW1 Register */
+    __IO uint16_t r;
+    struct { /* UCA3CTLW1 Bits */
+      __IO uint16_t bGLIT               	:	2;  /* Deglitch time */
+      __I  uint16_t bRESERVED0          	:	14;  /* Reserved */
+    } b;
+  } rCTLW1;
+  uint8_t  RESERVED0[2];
+  __IO uint16_t rBRW; /* eUSCI_Ax Baud Rate Control Word Register */
+  union {    /* UCA3MCTLW Register */
+    __IO uint16_t r;
+    struct { /* UCA3MCTLW Bits */
+      __IO uint16_t bOS16               	:	1;  /* Oversampling mode enabled */
+      __I  uint16_t bRESERVED0          	:	3;  /* Reserved */
+      __IO uint16_t bBRF                	:	4;  /* First modulation stage select */
+      __IO uint16_t bBRS                	:	8;  /* Second modulation stage select */
+    } b;
+  } rMCTLW;
+  union {    /* UCA3STATW Register */
+    __IO uint16_t r;
+    struct { /* UCA3STATW Bits */
+      __I  uint16_t bBUSY               	:	1;  /* eUSCI_A busy */
+      __IO uint16_t bADDR_IDLE          	:	1;  /* Address received / Idle line detected */
+      __IO uint16_t bRXERR              	:	1;  /* Receive error flag */
+      __IO uint16_t bBRK                	:	1;  /* Break detect flag */
+      __IO uint16_t bPE                 	:	1;  /*  */
+      __IO uint16_t bOE                 	:	1;  /* Overrun error flag */
+      __IO uint16_t bFE                 	:	1;  /* Framing error flag */
+      __IO uint16_t bLISTEN             	:	1;  /* Listen enable */
+      __I  uint16_t bRESERVED0          	:	8;  /* Reserved */
+    } b;
+    struct { /* UCA3STATW_SPI Bits */
+      __I  uint16_t bBUSY               	:	1;  /* eUSCI_A busy */
+      __IO uint16_t bRESERVED           	:	4;  /* Reserved */
+      __IO uint16_t bOE                 	:	1;  /* Overrun error flag */
+      __IO uint16_t bFE                 	:	1;  /* Framing error flag */
+      __IO uint16_t bLISTEN             	:	1;  /* Listen enable */
+    } a;
+  } rSTATW;
+  union {    /* UCA3RXBUF Register */
+    __I uint16_t r;
+    struct { /* UCA3RXBUF Bits */
+      __I  uint16_t bRXBUF              	:	8;  /* Receive data buffer */
+      __I  uint16_t bRESERVED0          	:	8;  /* Reserved */
+    } b;
+    struct { /* UCA3RXBUF_SPI Bits */
+      __I  uint16_t bRXBUF              	:	8;  /* Receive data buffer */
+      __I  uint16_t bRESERVED           	:	8;  /* Reserved */
+    } a;
+  } rRXBUF;
+  union {    /* UCA3TXBUF Register */
+    __IO uint16_t r;
+    struct { /* UCA3TXBUF Bits */
+      __IO uint16_t bTXBUF              	:	8;  /* Transmit data buffer */
+      __I  uint16_t bRESERVED0          	:	8;  /* Reserved */
+    } b;
+    struct { /* UCA3TXBUF_SPI Bits */
+      __IO uint16_t bTXBUF              	:	8;  /* Transmit data buffer */
+      __I  uint16_t bRESERVED           	:	8;  /* Reserved */
+    } a;
+  } rTXBUF;
+  union {    /* UCA3ABCTL Register */
+    __IO uint16_t r;
+    struct { /* UCA3ABCTL Bits */
+      __IO uint16_t bABDEN              	:	1;  /* Automatic baud-rate detect enable */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bBTOE               	:	1;  /* Break time out error */
+      __IO uint16_t bSTOE               	:	1;  /* Synch field time out error */
+      __IO uint16_t bDELIM              	:	2;  /* Break/synch delimiter length */
+      __I  uint16_t bRESERVED1          	:	10;  /* Reserved */
+    } b;
+  } rABCTL;
+  union {    /* UCA3IRCTL Register */
+    __IO uint16_t r;
+    struct { /* UCA3IRCTL Bits */
+      __IO uint16_t bIREN               	:	1;  /* IrDA encoder/decoder enable */
+      __IO uint16_t bIRTXCLK            	:	1;  /* IrDA transmit pulse clock select */
+      __IO uint16_t bIRTXPL             	:	6;  /* Transmit pulse length */
+      __IO uint16_t bIRRXFE             	:	1;  /* IrDA receive filter enabled */
+      __IO uint16_t bIRRXPL             	:	1;  /* IrDA receive input UCAxRXD polarity */
+      __IO uint16_t bIRRXFL             	:	4;  /* Receive filter length */
+    } b;
+  } rIRCTL;
+  uint8_t  RESERVED1[6];
+  union {    /* UCA3IE Register */
+    __IO uint16_t r;
+    struct { /* UCA3IE Bits */
+      __IO uint16_t bRXIE               	:	1;  /* Receive interrupt enable */
+      __IO uint16_t bTXIE               	:	1;  /* Transmit interrupt enable */
+      __IO uint16_t bSTTIE              	:	1;  /* Start bit interrupt enable */
+      __IO uint16_t bTXCPTIE            	:	1;  /* Transmit complete interrupt enable */
+      __I  uint16_t bRESERVED0          	:	12;  /* Reserved */
+    } b;
+    struct { /* UCA3IE_SPI Bits */
+      __IO uint16_t bRXIE               	:	1;  /* Receive interrupt enable */
+      __IO uint16_t bTXIE               	:	1;  /* Transmit interrupt enable */
+      __I  uint16_t bRESERVED           	:	14;  /* Reserved */
+    } a;
+  } rIE;
+  union {    /* UCA3IFG Register */
+    __IO uint16_t r;
+    struct { /* UCA3IFG Bits */
+      __IO uint16_t bRXIFG              	:	1;  /* Receive interrupt flag */
+      __IO uint16_t bTXIFG              	:	1;  /* Transmit interrupt flag */
+      __IO uint16_t bSTTIFG             	:	1;  /* Start bit interrupt flag */
+      __IO uint16_t bTXCPTIFG           	:	1;  /* Transmit ready interrupt enable */
+      __I  uint16_t bRESERVED0          	:	12;  /* Reserved */
+    } b;
+    struct { /* UCA3IFG_SPI Bits */
+      __IO uint16_t bRXIFG              	:	1;  /* Receive interrupt flag */
+      __IO uint16_t bTXIFG              	:	1;  /* Transmit interrupt flag */
+      __I  uint16_t bRESERVED           	:	14;  /* Reserved */
+    } a;
+  } rIFG;
+  __I uint16_t rIV; /* eUSCI_Ax Interrupt Vector Register */
+} EUSCI_A3_Type;
+
+
+//*****************************************************************************
+// EUSCI_B0 Registers
+//*****************************************************************************
+typedef struct {
+  union {    /* UCB0CTLW0 Register */
+    __IO uint16_t r;
+    struct { /* UCB0CTLW0 Bits */
+      __IO uint16_t bSWRST              	:	1;  /* Software reset enable */
+      __IO uint16_t bTXSTT              	:	1;  /* Transmit START condition in master mode */
+      __IO uint16_t bTXSTP              	:	1;  /* Transmit STOP condition in master mode */
+      __IO uint16_t bTXNACK             	:	1;  /* Transmit a NACK */
+      __IO uint16_t bTR                 	:	1;  /* Transmitter/receiver */
+      __IO uint16_t bTXACK              	:	1;  /* Transmit ACK condition in slave mode */
+      __IO uint16_t bSSEL               	:	2;  /* eUSCI_B clock source select */
+      __IO uint16_t bSYNC               	:	1;  /* Synchronous mode enable */
+      __IO uint16_t bMODE               	:	2;  /* eUSCI_B mode */
+      __IO uint16_t bMST                	:	1;  /* Master mode select */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bMM                 	:	1;  /* Multi-master environment select */
+      __IO uint16_t bSLA10              	:	1;  /* Slave addressing mode select */
+      __IO uint16_t bA10                	:	1;  /* Own addressing mode select */
+    } b;
+    struct { /* UCB0CTLW0_SPI Bits */
+      __IO uint16_t bSWRST              	:	1;  /* Software reset enable */
+      __IO uint16_t bSTEM               	:	1;  /* STE mode select in master mode. */
+      __I  uint16_t bRESERVED           	:	4;  /* Reserved */
+      __IO uint16_t bSSEL               	:	2;  /* eUSCI_B clock source select */
+      __IO uint16_t bSYNC               	:	1;  /* Synchronous mode enable */
+      __IO uint16_t bMODE               	:	2;  /* eUSCI mode */
+      __IO uint16_t bMST                	:	1;  /* Master mode select */
+      __IO uint16_t b7BIT               	:	1;  /* Character length */
+      __IO uint16_t bMSB                	:	1;  /* MSB first select */
+      __IO uint16_t bCKPL               	:	1;  /* Clock polarity select */
+      __IO uint16_t bCKPH               	:	1;  /* Clock phase select */
+    } a;
+  } rCTLW0;
+  union {    /* UCB0CTLW1 Register */
+    __IO uint16_t r;
+    struct { /* UCB0CTLW1 Bits */
+      __IO uint16_t bGLIT               	:	2;  /* Deglitch time */
+      __IO uint16_t bASTP               	:	2;  /* Automatic STOP condition generation */
+      __IO uint16_t bSWACK              	:	1;  /* SW or HW ACK control */
+      __IO uint16_t bSTPNACK            	:	1;  /* ACK all master bytes */
+      __IO uint16_t bCLTO               	:	2;  /* Clock low timeout select */
+      __IO uint16_t bETXINT             	:	1;  /* Early UCTXIFG0 */
+      __I  uint16_t bRESERVED0          	:	7;  /* Reserved */
+    } b;
+  } rCTLW1;
+  uint8_t  RESERVED0[2];
+  __IO uint16_t rBRW; /* eUSCI_Bx Baud Rate Control Word Register */
+  union {    /* UCB0STATW Register */
+    __IO uint16_t r;
+    struct { /* UCB0STATW Bits */
+      __I  uint16_t bRESERVED1          	:	4;  /* Reserved */
+      __I  uint16_t bBBUSY              	:	1;  /* Bus busy */
+      __I  uint16_t bGC                 	:	1;  /* General call address received */
+      __I  uint16_t bSCLLOW             	:	1;  /* SCL low */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __I  uint16_t bBCNT               	:	8;  /* Hardware byte counter value */
+    } b;
+    struct { /* UCB0STATW_SPI Bits */
+      __I  uint16_t bBUSY               	:	1;  /* eUSCI_B busy */
+      __IO uint16_t bRESERVED           	:	4;  /* Reserved */
+      __IO uint16_t bOE                 	:	1;  /* Overrun error flag */
+      __IO uint16_t bFE                 	:	1;  /* Framing error flag */
+      __IO uint16_t bLISTEN             	:	1;  /* Listen enable */
+    } a;
+  } rSTATW;
+  union {    /* UCB0TBCNT Register */
+    __IO uint16_t r;
+    struct { /* UCB0TBCNT Bits */
+      __IO uint16_t bTBCNT              	:	8;  /* Byte counter threshold value */
+      __I  uint16_t bRESERVED0          	:	8;  /* Reserved */
+    } b;
+  } rTBCNT;
+  union {    /* UCB0RXBUF Register */
+    __I uint16_t r;
+    struct { /* UCB0RXBUF Bits */
+      __I  uint16_t bRXBUF              	:	8;  /* Receive data buffer */
+      __I  uint16_t bRESERVED0          	:	8;  /* Reserved */
+    } b;
+    struct { /* UCB0RXBUF_SPI Bits */
+      __I  uint16_t bRXBUF              	:	8;  /* Receive data buffer */
+      __I  uint16_t bRESERVED           	:	8;  /* Reserved */
+    } a;
+  } rRXBUF;
+  union {    /* UCB0TXBUF Register */
+    __IO uint16_t r;
+    struct { /* UCB0TXBUF Bits */
+      __IO uint16_t bTXBUF              	:	8;  /* Transmit data buffer */
+      __I  uint16_t bRESERVED0          	:	8;  /* Reserved */
+    } b;
+    struct { /* UCB0TXBUF_SPI Bits */
+      __IO uint16_t bTXBUF              	:	8;  /* Transmit data buffer */
+      __I  uint16_t bRESERVED           	:	8;  /* Reserved */
+    } a;
+  } rTXBUF;
+  uint8_t  RESERVED1[4];
+  union {    /* UCB0I2COA0 Register */
+    __IO uint16_t r;
+    struct { /* UCB0I2COA0 Bits */
+      __IO uint16_t bI2COA0             	:	10;  /* I2C own address */
+      __IO uint16_t bOAEN               	:	1;  /* Own Address enable register */
+      __I  uint16_t bRESERVED0          	:	4;  /* Reserved */
+      __IO uint16_t bGCEN               	:	1;  /* General call response enable */
+    } b;
+  } rI2COA0;
+  union {    /* UCB0I2COA1 Register */
+    __IO uint16_t r;
+    struct { /* UCB0I2COA1 Bits */
+      __IO uint16_t bI2COA1             	:	10;  /* I2C own address */
+      __IO uint16_t bOAEN               	:	1;  /* Own Address enable register */
+      __I  uint16_t bRESERVED0          	:	5;  /* Reserved */
+    } b;
+  } rI2COA1;
+  union {    /* UCB0I2COA2 Register */
+    __IO uint16_t r;
+    struct { /* UCB0I2COA2 Bits */
+      __IO uint16_t bI2COA2             	:	10;  /* I2C own address */
+      __IO uint16_t bOAEN               	:	1;  /* Own Address enable register */
+      __I  uint16_t bRESERVED0          	:	5;  /* Reserved */
+    } b;
+  } rI2COA2;
+  union {    /* UCB0I2COA3 Register */
+    __IO uint16_t r;
+    struct { /* UCB0I2COA3 Bits */
+      __IO uint16_t bI2COA3             	:	10;  /* I2C own address */
+      __IO uint16_t bOAEN               	:	1;  /* Own Address enable register */
+      __I  uint16_t bRESERVED0          	:	5;  /* Reserved */
+    } b;
+  } rI2COA3;
+  union {    /* UCB0ADDRX Register */
+    __I uint16_t r;
+    struct { /* UCB0ADDRX Bits */
+      __I  uint16_t bADDRX              	:	10;  /* Received Address Register */
+      __I  uint16_t bRESERVED0          	:	6;  /* Reserved */
+    } b;
+  } rADDRX;
+  union {    /* UCB0ADDMASK Register */
+    __IO uint16_t r;
+    struct { /* UCB0ADDMASK Bits */
+      __IO uint16_t bADDMASK            	:	10;  /*  */
+      __I  uint16_t bRESERVED0          	:	6;  /* Reserved */
+    } b;
+  } rADDMASK;
+  union {    /* UCB0I2CSA Register */
+    __IO uint16_t r;
+    struct { /* UCB0I2CSA Bits */
+      __IO uint16_t bI2CSA              	:	10;  /* I2C slave address */
+      __I  uint16_t bRESERVED0          	:	6;  /* Reserved */
+    } b;
+  } rI2CSA;
+  uint8_t  RESERVED2[8];
+  union {    /* UCB0IE Register */
+    __IO uint16_t r;
+    struct { /* UCB0IE Bits */
+      __IO uint16_t bRXIE0              	:	1;  /* Receive interrupt enable 0 */
+      __IO uint16_t bTXIE0              	:	1;  /* Transmit interrupt enable 0 */
+      __IO uint16_t bSTTIE              	:	1;  /* START condition interrupt enable */
+      __IO uint16_t bSTPIE              	:	1;  /* STOP condition interrupt enable */
+      __IO uint16_t bALIE               	:	1;  /* Arbitration lost interrupt enable */
+      __IO uint16_t bNACKIE             	:	1;  /* Not-acknowledge interrupt enable */
+      __IO uint16_t bBCNTIE             	:	1;  /* Byte counter interrupt enable */
+      __IO uint16_t bCLTOIE             	:	1;  /* Clock low timeout interrupt enable */
+      __IO uint16_t bRXIE1              	:	1;  /* Receive interrupt enable 1 */
+      __IO uint16_t bTXIE1              	:	1;  /* Transmit interrupt enable 1 */
+      __IO uint16_t bRXIE2              	:	1;  /* Receive interrupt enable 2 */
+      __IO uint16_t bTXIE2              	:	1;  /* Transmit interrupt enable 2 */
+      __IO uint16_t bRXIE3              	:	1;  /* Receive interrupt enable 3 */
+      __IO uint16_t bTXIE3              	:	1;  /* Transmit interrupt enable 3 */
+      __IO uint16_t bBIT9IE             	:	1;  /* Bit position 9 interrupt enable */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+    } b;
+    struct { /* UCB0IE_SPI Bits */
+      __IO uint16_t bRXIE               	:	1;  /* Receive interrupt enable */
+      __IO uint16_t bTXIE               	:	1;  /* Transmit interrupt enable */
+      __I  uint16_t bRESERVED           	:	14;  /* Reserved */
+    } a;
+  } rIE;
+  union {    /* UCB0IFG Register */
+    __IO uint16_t r;
+    struct { /* UCB0IFG Bits */
+      __IO uint16_t bRXIFG0             	:	1;  /* eUSCI_B receive interrupt flag 0 */
+      __IO uint16_t bTXIFG0             	:	1;  /* eUSCI_B transmit interrupt flag 0 */
+      __IO uint16_t bSTTIFG             	:	1;  /* START condition interrupt flag */
+      __IO uint16_t bSTPIFG             	:	1;  /* STOP condition interrupt flag */
+      __IO uint16_t bALIFG              	:	1;  /* Arbitration lost interrupt flag */
+      __IO uint16_t bNACKIFG            	:	1;  /* Not-acknowledge received interrupt flag */
+      __IO uint16_t bBCNTIFG            	:	1;  /* Byte counter interrupt flag */
+      __IO uint16_t bCLTOIFG            	:	1;  /* Clock low timeout interrupt flag */
+      __IO uint16_t bRXIFG1             	:	1;  /* eUSCI_B receive interrupt flag 1 */
+      __IO uint16_t bTXIFG1             	:	1;  /* eUSCI_B transmit interrupt flag 1 */
+      __IO uint16_t bRXIFG2             	:	1;  /* eUSCI_B receive interrupt flag 2 */
+      __IO uint16_t bTXIFG2             	:	1;  /* eUSCI_B transmit interrupt flag 2 */
+      __IO uint16_t bRXIFG3             	:	1;  /* eUSCI_B receive interrupt flag 3 */
+      __IO uint16_t bTXIFG3             	:	1;  /* eUSCI_B transmit interrupt flag 3 */
+      __IO uint16_t bBIT9IFG            	:	1;  /* Bit position 9 interrupt flag */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+    } b;
+    struct { /* UCB0IFG_SPI Bits */
+      __IO uint16_t bRXIFG              	:	1;  /* Receive interrupt flag */
+      __IO uint16_t bTXIFG              	:	1;  /* Transmit interrupt flag */
+      __I  uint16_t bRESERVED           	:	14;  /* Reserved */
+    } a;
+  } rIFG;
+  __I uint16_t rIV; /* eUSCI_Bx Interrupt Vector Register */
+} EUSCI_B0_Type;
+
+
+//*****************************************************************************
+// EUSCI_B1 Registers
+//*****************************************************************************
+typedef struct {
+  union {    /* UCB1CTLW0 Register */
+    __IO uint16_t r;
+    struct { /* UCB1CTLW0 Bits */
+      __IO uint16_t bSWRST              	:	1;  /* Software reset enable */
+      __IO uint16_t bTXSTT              	:	1;  /* Transmit START condition in master mode */
+      __IO uint16_t bTXSTP              	:	1;  /* Transmit STOP condition in master mode */
+      __IO uint16_t bTXNACK             	:	1;  /* Transmit a NACK */
+      __IO uint16_t bTR                 	:	1;  /* Transmitter/receiver */
+      __IO uint16_t bTXACK              	:	1;  /* Transmit ACK condition in slave mode */
+      __IO uint16_t bSSEL               	:	2;  /* eUSCI_B clock source select */
+      __IO uint16_t bSYNC               	:	1;  /* Synchronous mode enable */
+      __IO uint16_t bMODE               	:	2;  /* eUSCI_B mode */
+      __IO uint16_t bMST                	:	1;  /* Master mode select */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bMM                 	:	1;  /* Multi-master environment select */
+      __IO uint16_t bSLA10              	:	1;  /* Slave addressing mode select */
+      __IO uint16_t bA10                	:	1;  /* Own addressing mode select */
+    } b;
+    struct { /* UCB1CTLW0_SPI Bits */
+      __IO uint16_t bSWRST              	:	1;  /* Software reset enable */
+      __IO uint16_t bSTEM               	:	1;  /* STE mode select in master mode. */
+      __I  uint16_t bRESERVED           	:	4;  /* Reserved */
+      __IO uint16_t bSSEL               	:	2;  /* eUSCI_B clock source select */
+      __IO uint16_t bSYNC               	:	1;  /* Synchronous mode enable */
+      __IO uint16_t bMODE               	:	2;  /* eUSCI mode */
+      __IO uint16_t bMST                	:	1;  /* Master mode select */
+      __IO uint16_t b7BIT               	:	1;  /* Character length */
+      __IO uint16_t bMSB                	:	1;  /* MSB first select */
+      __IO uint16_t bCKPL               	:	1;  /* Clock polarity select */
+      __IO uint16_t bCKPH               	:	1;  /* Clock phase select */
+    } a;
+  } rCTLW0;
+  union {    /* UCB1CTLW1 Register */
+    __IO uint16_t r;
+    struct { /* UCB1CTLW1 Bits */
+      __IO uint16_t bGLIT               	:	2;  /* Deglitch time */
+      __IO uint16_t bASTP               	:	2;  /* Automatic STOP condition generation */
+      __IO uint16_t bSWACK              	:	1;  /* SW or HW ACK control */
+      __IO uint16_t bSTPNACK            	:	1;  /* ACK all master bytes */
+      __IO uint16_t bCLTO               	:	2;  /* Clock low timeout select */
+      __IO uint16_t bETXINT             	:	1;  /* Early UCTXIFG0 */
+      __I  uint16_t bRESERVED0          	:	7;  /* Reserved */
+    } b;
+  } rCTLW1;
+  uint8_t  RESERVED0[2];
+  __IO uint16_t rBRW; /* eUSCI_Bx Baud Rate Control Word Register */
+  union {    /* UCB1STATW Register */
+    __IO uint16_t r;
+    struct { /* UCB1STATW Bits */
+      __I  uint16_t bRESERVED1          	:	4;  /* Reserved */
+      __I  uint16_t bBBUSY              	:	1;  /* Bus busy */
+      __I  uint16_t bGC                 	:	1;  /* General call address received */
+      __I  uint16_t bSCLLOW             	:	1;  /* SCL low */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __I  uint16_t bBCNT               	:	8;  /* Hardware byte counter value */
+    } b;
+    struct { /* UCB1STATW_SPI Bits */
+      __I  uint16_t bBUSY               	:	1;  /* eUSCI_B busy */
+      __IO uint16_t bRESERVED           	:	4;  /* Reserved */
+      __IO uint16_t bOE                 	:	1;  /* Overrun error flag */
+      __IO uint16_t bFE                 	:	1;  /* Framing error flag */
+      __IO uint16_t bLISTEN             	:	1;  /* Listen enable */
+    } a;
+  } rSTATW;
+  union {    /* UCB1TBCNT Register */
+    __IO uint16_t r;
+    struct { /* UCB1TBCNT Bits */
+      __IO uint16_t bTBCNT              	:	8;  /* Byte counter threshold value */
+      __I  uint16_t bRESERVED0          	:	8;  /* Reserved */
+    } b;
+  } rTBCNT;
+  union {    /* UCB1RXBUF Register */
+    __I uint16_t r;
+    struct { /* UCB1RXBUF Bits */
+      __I  uint16_t bRXBUF              	:	8;  /* Receive data buffer */
+      __I  uint16_t bRESERVED0          	:	8;  /* Reserved */
+    } b;
+    struct { /* UCB1RXBUF_SPI Bits */
+      __I  uint16_t bRXBUF              	:	8;  /* Receive data buffer */
+      __I  uint16_t bRESERVED           	:	8;  /* Reserved */
+    } a;
+  } rRXBUF;
+  union {    /* UCB1TXBUF Register */
+    __IO uint16_t r;
+    struct { /* UCB1TXBUF Bits */
+      __IO uint16_t bTXBUF              	:	8;  /* Transmit data buffer */
+      __I  uint16_t bRESERVED0          	:	8;  /* Reserved */
+    } b;
+    struct { /* UCB1TXBUF_SPI Bits */
+      __IO uint16_t bTXBUF              	:	8;  /* Transmit data buffer */
+      __I  uint16_t bRESERVED           	:	8;  /* Reserved */
+    } a;
+  } rTXBUF;
+  uint8_t  RESERVED1[4];
+  union {    /* UCB1I2COA0 Register */
+    __IO uint16_t r;
+    struct { /* UCB1I2COA0 Bits */
+      __IO uint16_t bI2COA0             	:	10;  /* I2C own address */
+      __IO uint16_t bOAEN               	:	1;  /* Own Address enable register */
+      __I  uint16_t bRESERVED0          	:	4;  /* Reserved */
+      __IO uint16_t bGCEN               	:	1;  /* General call response enable */
+    } b;
+  } rI2COA0;
+  union {    /* UCB1I2COA1 Register */
+    __IO uint16_t r;
+    struct { /* UCB1I2COA1 Bits */
+      __IO uint16_t bI2COA1             	:	10;  /* I2C own address */
+      __IO uint16_t bOAEN               	:	1;  /* Own Address enable register */
+      __I  uint16_t bRESERVED0          	:	5;  /* Reserved */
+    } b;
+  } rI2COA1;
+  union {    /* UCB1I2COA2 Register */
+    __IO uint16_t r;
+    struct { /* UCB1I2COA2 Bits */
+      __IO uint16_t bI2COA2             	:	10;  /* I2C own address */
+      __IO uint16_t bOAEN               	:	1;  /* Own Address enable register */
+      __I  uint16_t bRESERVED0          	:	5;  /* Reserved */
+    } b;
+  } rI2COA2;
+  union {    /* UCB1I2COA3 Register */
+    __IO uint16_t r;
+    struct { /* UCB1I2COA3 Bits */
+      __IO uint16_t bI2COA3             	:	10;  /* I2C own address */
+      __IO uint16_t bOAEN               	:	1;  /* Own Address enable register */
+      __I  uint16_t bRESERVED0          	:	5;  /* Reserved */
+    } b;
+  } rI2COA3;
+  union {    /* UCB1ADDRX Register */
+    __I uint16_t r;
+    struct { /* UCB1ADDRX Bits */
+      __I  uint16_t bADDRX              	:	10;  /* Received Address Register */
+      __I  uint16_t bRESERVED0          	:	6;  /* Reserved */
+    } b;
+  } rADDRX;
+  union {    /* UCB1ADDMASK Register */
+    __IO uint16_t r;
+    struct { /* UCB1ADDMASK Bits */
+      __IO uint16_t bADDMASK            	:	10;  /*  */
+      __I  uint16_t bRESERVED0          	:	6;  /* Reserved */
+    } b;
+  } rADDMASK;
+  union {    /* UCB1I2CSA Register */
+    __IO uint16_t r;
+    struct { /* UCB1I2CSA Bits */
+      __IO uint16_t bI2CSA              	:	10;  /* I2C slave address */
+      __I  uint16_t bRESERVED0          	:	6;  /* Reserved */
+    } b;
+  } rI2CSA;
+  uint8_t  RESERVED2[8];
+  union {    /* UCB1IE Register */
+    __IO uint16_t r;
+    struct { /* UCB1IE Bits */
+      __IO uint16_t bRXIE0              	:	1;  /* Receive interrupt enable 0 */
+      __IO uint16_t bTXIE0              	:	1;  /* Transmit interrupt enable 0 */
+      __IO uint16_t bSTTIE              	:	1;  /* START condition interrupt enable */
+      __IO uint16_t bSTPIE              	:	1;  /* STOP condition interrupt enable */
+      __IO uint16_t bALIE               	:	1;  /* Arbitration lost interrupt enable */
+      __IO uint16_t bNACKIE             	:	1;  /* Not-acknowledge interrupt enable */
+      __IO uint16_t bBCNTIE             	:	1;  /* Byte counter interrupt enable */
+      __IO uint16_t bCLTOIE             	:	1;  /* Clock low timeout interrupt enable */
+      __IO uint16_t bRXIE1              	:	1;  /* Receive interrupt enable 1 */
+      __IO uint16_t bTXIE1              	:	1;  /* Transmit interrupt enable 1 */
+      __IO uint16_t bRXIE2              	:	1;  /* Receive interrupt enable 2 */
+      __IO uint16_t bTXIE2              	:	1;  /* Transmit interrupt enable 2 */
+      __IO uint16_t bRXIE3              	:	1;  /* Receive interrupt enable 3 */
+      __IO uint16_t bTXIE3              	:	1;  /* Transmit interrupt enable 3 */
+      __IO uint16_t bBIT9IE             	:	1;  /* Bit position 9 interrupt enable */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+    } b;
+    struct { /* UCB1IE_SPI Bits */
+      __IO uint16_t bRXIE               	:	1;  /* Receive interrupt enable */
+      __IO uint16_t bTXIE               	:	1;  /* Transmit interrupt enable */
+      __I  uint16_t bRESERVED           	:	14;  /* Reserved */
+    } a;
+  } rIE;
+  union {    /* UCB1IFG Register */
+    __IO uint16_t r;
+    struct { /* UCB1IFG Bits */
+      __IO uint16_t bRXIFG0             	:	1;  /* eUSCI_B receive interrupt flag 0 */
+      __IO uint16_t bTXIFG0             	:	1;  /* eUSCI_B transmit interrupt flag 0 */
+      __IO uint16_t bSTTIFG             	:	1;  /* START condition interrupt flag */
+      __IO uint16_t bSTPIFG             	:	1;  /* STOP condition interrupt flag */
+      __IO uint16_t bALIFG              	:	1;  /* Arbitration lost interrupt flag */
+      __IO uint16_t bNACKIFG            	:	1;  /* Not-acknowledge received interrupt flag */
+      __IO uint16_t bBCNTIFG            	:	1;  /* Byte counter interrupt flag */
+      __IO uint16_t bCLTOIFG            	:	1;  /* Clock low timeout interrupt flag */
+      __IO uint16_t bRXIFG1             	:	1;  /* eUSCI_B receive interrupt flag 1 */
+      __IO uint16_t bTXIFG1             	:	1;  /* eUSCI_B transmit interrupt flag 1 */
+      __IO uint16_t bRXIFG2             	:	1;  /* eUSCI_B receive interrupt flag 2 */
+      __IO uint16_t bTXIFG2             	:	1;  /* eUSCI_B transmit interrupt flag 2 */
+      __IO uint16_t bRXIFG3             	:	1;  /* eUSCI_B receive interrupt flag 3 */
+      __IO uint16_t bTXIFG3             	:	1;  /* eUSCI_B transmit interrupt flag 3 */
+      __IO uint16_t bBIT9IFG            	:	1;  /* Bit position 9 interrupt flag */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+    } b;
+    struct { /* UCB1IFG_SPI Bits */
+      __IO uint16_t bRXIFG              	:	1;  /* Receive interrupt flag */
+      __IO uint16_t bTXIFG              	:	1;  /* Transmit interrupt flag */
+      __I  uint16_t bRESERVED           	:	14;  /* Reserved */
+    } a;
+  } rIFG;
+  __I uint16_t rIV; /* eUSCI_Bx Interrupt Vector Register */
+} EUSCI_B1_Type;
+
+
+//*****************************************************************************
+// EUSCI_B2 Registers
+//*****************************************************************************
+typedef struct {
+  union {    /* UCB2CTLW0 Register */
+    __IO uint16_t r;
+    struct { /* UCB2CTLW0 Bits */
+      __IO uint16_t bSWRST              	:	1;  /* Software reset enable */
+      __IO uint16_t bTXSTT              	:	1;  /* Transmit START condition in master mode */
+      __IO uint16_t bTXSTP              	:	1;  /* Transmit STOP condition in master mode */
+      __IO uint16_t bTXNACK             	:	1;  /* Transmit a NACK */
+      __IO uint16_t bTR                 	:	1;  /* Transmitter/receiver */
+      __IO uint16_t bTXACK              	:	1;  /* Transmit ACK condition in slave mode */
+      __IO uint16_t bSSEL               	:	2;  /* eUSCI_B clock source select */
+      __IO uint16_t bSYNC               	:	1;  /* Synchronous mode enable */
+      __IO uint16_t bMODE               	:	2;  /* eUSCI_B mode */
+      __IO uint16_t bMST                	:	1;  /* Master mode select */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bMM                 	:	1;  /* Multi-master environment select */
+      __IO uint16_t bSLA10              	:	1;  /* Slave addressing mode select */
+      __IO uint16_t bA10                	:	1;  /* Own addressing mode select */
+    } b;
+    struct { /* UCB2CTLW0_SPI Bits */
+      __IO uint16_t bSWRST              	:	1;  /* Software reset enable */
+      __IO uint16_t bSTEM               	:	1;  /* STE mode select in master mode. */
+      __I  uint16_t bRESERVED           	:	4;  /* Reserved */
+      __IO uint16_t bSSEL               	:	2;  /* eUSCI_B clock source select */
+      __IO uint16_t bSYNC               	:	1;  /* Synchronous mode enable */
+      __IO uint16_t bMODE               	:	2;  /* eUSCI mode */
+      __IO uint16_t bMST                	:	1;  /* Master mode select */
+      __IO uint16_t b7BIT               	:	1;  /* Character length */
+      __IO uint16_t bMSB                	:	1;  /* MSB first select */
+      __IO uint16_t bCKPL               	:	1;  /* Clock polarity select */
+      __IO uint16_t bCKPH               	:	1;  /* Clock phase select */
+    } a;
+  } rCTLW0;
+  union {    /* UCB2CTLW1 Register */
+    __IO uint16_t r;
+    struct { /* UCB2CTLW1 Bits */
+      __IO uint16_t bGLIT               	:	2;  /* Deglitch time */
+      __IO uint16_t bASTP               	:	2;  /* Automatic STOP condition generation */
+      __IO uint16_t bSWACK              	:	1;  /* SW or HW ACK control */
+      __IO uint16_t bSTPNACK            	:	1;  /* ACK all master bytes */
+      __IO uint16_t bCLTO               	:	2;  /* Clock low timeout select */
+      __IO uint16_t bETXINT             	:	1;  /* Early UCTXIFG0 */
+      __I  uint16_t bRESERVED0          	:	7;  /* Reserved */
+    } b;
+  } rCTLW1;
+  uint8_t  RESERVED0[2];
+  __IO uint16_t rBRW; /* eUSCI_Bx Baud Rate Control Word Register */
+  union {    /* UCB2STATW Register */
+    __IO uint16_t r;
+    struct { /* UCB2STATW Bits */
+      __I  uint16_t bRESERVED1          	:	4;  /* Reserved */
+      __I  uint16_t bBBUSY              	:	1;  /* Bus busy */
+      __I  uint16_t bGC                 	:	1;  /* General call address received */
+      __I  uint16_t bSCLLOW             	:	1;  /* SCL low */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __I  uint16_t bBCNT               	:	8;  /* Hardware byte counter value */
+    } b;
+    struct { /* UCB2STATW_SPI Bits */
+      __I  uint16_t bBUSY               	:	1;  /* eUSCI_B busy */
+      __IO uint16_t bRESERVED           	:	4;  /* Reserved */
+      __IO uint16_t bOE                 	:	1;  /* Overrun error flag */
+      __IO uint16_t bFE                 	:	1;  /* Framing error flag */
+      __IO uint16_t bLISTEN             	:	1;  /* Listen enable */
+    } a;
+  } rSTATW;
+  union {    /* UCB2TBCNT Register */
+    __IO uint16_t r;
+    struct { /* UCB2TBCNT Bits */
+      __IO uint16_t bTBCNT              	:	8;  /* Byte counter threshold value */
+      __I  uint16_t bRESERVED0          	:	8;  /* Reserved */
+    } b;
+  } rTBCNT;
+  union {    /* UCB2RXBUF Register */
+    __I uint16_t r;
+    struct { /* UCB2RXBUF Bits */
+      __I  uint16_t bRXBUF              	:	8;  /* Receive data buffer */
+      __I  uint16_t bRESERVED0          	:	8;  /* Reserved */
+    } b;
+    struct { /* UCB2RXBUF_SPI Bits */
+      __I  uint16_t bRXBUF              	:	8;  /* Receive data buffer */
+      __I  uint16_t bRESERVED           	:	8;  /* Reserved */
+    } a;
+  } rRXBUF;
+  union {    /* UCB2TXBUF Register */
+    __IO uint16_t r;
+    struct { /* UCB2TXBUF Bits */
+      __IO uint16_t bTXBUF              	:	8;  /* Transmit data buffer */
+      __I  uint16_t bRESERVED0          	:	8;  /* Reserved */
+    } b;
+    struct { /* UCB2TXBUF_SPI Bits */
+      __IO uint16_t bTXBUF              	:	8;  /* Transmit data buffer */
+      __I  uint16_t bRESERVED           	:	8;  /* Reserved */
+    } a;
+  } rTXBUF;
+  uint8_t  RESERVED1[4];
+  union {    /* UCB2I2COA0 Register */
+    __IO uint16_t r;
+    struct { /* UCB2I2COA0 Bits */
+      __IO uint16_t bI2COA0             	:	10;  /* I2C own address */
+      __IO uint16_t bOAEN               	:	1;  /* Own Address enable register */
+      __I  uint16_t bRESERVED0          	:	4;  /* Reserved */
+      __IO uint16_t bGCEN               	:	1;  /* General call response enable */
+    } b;
+  } rI2COA0;
+  union {    /* UCB2I2COA1 Register */
+    __IO uint16_t r;
+    struct { /* UCB2I2COA1 Bits */
+      __IO uint16_t bI2COA1             	:	10;  /* I2C own address */
+      __IO uint16_t bOAEN               	:	1;  /* Own Address enable register */
+      __I  uint16_t bRESERVED0          	:	5;  /* Reserved */
+    } b;
+  } rI2COA1;
+  union {    /* UCB2I2COA2 Register */
+    __IO uint16_t r;
+    struct { /* UCB2I2COA2 Bits */
+      __IO uint16_t bI2COA2             	:	10;  /* I2C own address */
+      __IO uint16_t bOAEN               	:	1;  /* Own Address enable register */
+      __I  uint16_t bRESERVED0          	:	5;  /* Reserved */
+    } b;
+  } rI2COA2;
+  union {    /* UCB2I2COA3 Register */
+    __IO uint16_t r;
+    struct { /* UCB2I2COA3 Bits */
+      __IO uint16_t bI2COA3             	:	10;  /* I2C own address */
+      __IO uint16_t bOAEN               	:	1;  /* Own Address enable register */
+      __I  uint16_t bRESERVED0          	:	5;  /* Reserved */
+    } b;
+  } rI2COA3;
+  union {    /* UCB2ADDRX Register */
+    __I uint16_t r;
+    struct { /* UCB2ADDRX Bits */
+      __I  uint16_t bADDRX              	:	10;  /* Received Address Register */
+      __I  uint16_t bRESERVED0          	:	6;  /* Reserved */
+    } b;
+  } rADDRX;
+  union {    /* UCB2ADDMASK Register */
+    __IO uint16_t r;
+    struct { /* UCB2ADDMASK Bits */
+      __IO uint16_t bADDMASK            	:	10;  /*  */
+      __I  uint16_t bRESERVED0          	:	6;  /* Reserved */
+    } b;
+  } rADDMASK;
+  union {    /* UCB2I2CSA Register */
+    __IO uint16_t r;
+    struct { /* UCB2I2CSA Bits */
+      __IO uint16_t bI2CSA              	:	10;  /* I2C slave address */
+      __I  uint16_t bRESERVED0          	:	6;  /* Reserved */
+    } b;
+  } rI2CSA;
+  uint8_t  RESERVED2[8];
+  union {    /* UCB2IE Register */
+    __IO uint16_t r;
+    struct { /* UCB2IE Bits */
+      __IO uint16_t bRXIE0              	:	1;  /* Receive interrupt enable 0 */
+      __IO uint16_t bTXIE0              	:	1;  /* Transmit interrupt enable 0 */
+      __IO uint16_t bSTTIE              	:	1;  /* START condition interrupt enable */
+      __IO uint16_t bSTPIE              	:	1;  /* STOP condition interrupt enable */
+      __IO uint16_t bALIE               	:	1;  /* Arbitration lost interrupt enable */
+      __IO uint16_t bNACKIE             	:	1;  /* Not-acknowledge interrupt enable */
+      __IO uint16_t bBCNTIE             	:	1;  /* Byte counter interrupt enable */
+      __IO uint16_t bCLTOIE             	:	1;  /* Clock low timeout interrupt enable */
+      __IO uint16_t bRXIE1              	:	1;  /* Receive interrupt enable 1 */
+      __IO uint16_t bTXIE1              	:	1;  /* Transmit interrupt enable 1 */
+      __IO uint16_t bRXIE2              	:	1;  /* Receive interrupt enable 2 */
+      __IO uint16_t bTXIE2              	:	1;  /* Transmit interrupt enable 2 */
+      __IO uint16_t bRXIE3              	:	1;  /* Receive interrupt enable 3 */
+      __IO uint16_t bTXIE3              	:	1;  /* Transmit interrupt enable 3 */
+      __IO uint16_t bBIT9IE             	:	1;  /* Bit position 9 interrupt enable */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+    } b;
+    struct { /* UCB2IE_SPI Bits */
+      __IO uint16_t bRXIE               	:	1;  /* Receive interrupt enable */
+      __IO uint16_t bTXIE               	:	1;  /* Transmit interrupt enable */
+      __I  uint16_t bRESERVED           	:	14;  /* Reserved */
+    } a;
+  } rIE;
+  union {    /* UCB2IFG Register */
+    __IO uint16_t r;
+    struct { /* UCB2IFG Bits */
+      __IO uint16_t bRXIFG0             	:	1;  /* eUSCI_B receive interrupt flag 0 */
+      __IO uint16_t bTXIFG0             	:	1;  /* eUSCI_B transmit interrupt flag 0 */
+      __IO uint16_t bSTTIFG             	:	1;  /* START condition interrupt flag */
+      __IO uint16_t bSTPIFG             	:	1;  /* STOP condition interrupt flag */
+      __IO uint16_t bALIFG              	:	1;  /* Arbitration lost interrupt flag */
+      __IO uint16_t bNACKIFG            	:	1;  /* Not-acknowledge received interrupt flag */
+      __IO uint16_t bBCNTIFG            	:	1;  /* Byte counter interrupt flag */
+      __IO uint16_t bCLTOIFG            	:	1;  /* Clock low timeout interrupt flag */
+      __IO uint16_t bRXIFG1             	:	1;  /* eUSCI_B receive interrupt flag 1 */
+      __IO uint16_t bTXIFG1             	:	1;  /* eUSCI_B transmit interrupt flag 1 */
+      __IO uint16_t bRXIFG2             	:	1;  /* eUSCI_B receive interrupt flag 2 */
+      __IO uint16_t bTXIFG2             	:	1;  /* eUSCI_B transmit interrupt flag 2 */
+      __IO uint16_t bRXIFG3             	:	1;  /* eUSCI_B receive interrupt flag 3 */
+      __IO uint16_t bTXIFG3             	:	1;  /* eUSCI_B transmit interrupt flag 3 */
+      __IO uint16_t bBIT9IFG            	:	1;  /* Bit position 9 interrupt flag */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+    } b;
+    struct { /* UCB2IFG_SPI Bits */
+      __IO uint16_t bRXIFG              	:	1;  /* Receive interrupt flag */
+      __IO uint16_t bTXIFG              	:	1;  /* Transmit interrupt flag */
+      __I  uint16_t bRESERVED           	:	14;  /* Reserved */
+    } a;
+  } rIFG;
+  __I uint16_t rIV; /* eUSCI_Bx Interrupt Vector Register */
+} EUSCI_B2_Type;
+
+
+//*****************************************************************************
+// EUSCI_B3 Registers
+//*****************************************************************************
+typedef struct {
+  union {    /* UCB3CTLW0 Register */
+    __IO uint16_t r;
+    struct { /* UCB3CTLW0 Bits */
+      __IO uint16_t bSWRST              	:	1;  /* Software reset enable */
+      __IO uint16_t bTXSTT              	:	1;  /* Transmit START condition in master mode */
+      __IO uint16_t bTXSTP              	:	1;  /* Transmit STOP condition in master mode */
+      __IO uint16_t bTXNACK             	:	1;  /* Transmit a NACK */
+      __IO uint16_t bTR                 	:	1;  /* Transmitter/receiver */
+      __IO uint16_t bTXACK              	:	1;  /* Transmit ACK condition in slave mode */
+      __IO uint16_t bSSEL               	:	2;  /* eUSCI_B clock source select */
+      __IO uint16_t bSYNC               	:	1;  /* Synchronous mode enable */
+      __IO uint16_t bMODE               	:	2;  /* eUSCI_B mode */
+      __IO uint16_t bMST                	:	1;  /* Master mode select */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bMM                 	:	1;  /* Multi-master environment select */
+      __IO uint16_t bSLA10              	:	1;  /* Slave addressing mode select */
+      __IO uint16_t bA10                	:	1;  /* Own addressing mode select */
+    } b;
+    struct { /* UCB3CTLW0_SPI Bits */
+      __IO uint16_t bSWRST              	:	1;  /* Software reset enable */
+      __IO uint16_t bSTEM               	:	1;  /* STE mode select in master mode. */
+      __I  uint16_t bRESERVED           	:	4;  /* Reserved */
+      __IO uint16_t bSSEL               	:	2;  /* eUSCI_B clock source select */
+      __IO uint16_t bSYNC               	:	1;  /* Synchronous mode enable */
+      __IO uint16_t bMODE               	:	2;  /* eUSCI mode */
+      __IO uint16_t bMST                	:	1;  /* Master mode select */
+      __IO uint16_t b7BIT               	:	1;  /* Character length */
+      __IO uint16_t bMSB                	:	1;  /* MSB first select */
+      __IO uint16_t bCKPL               	:	1;  /* Clock polarity select */
+      __IO uint16_t bCKPH               	:	1;  /* Clock phase select */
+    } a;
+  } rCTLW0;
+  union {    /* UCB3CTLW1 Register */
+    __IO uint16_t r;
+    struct { /* UCB3CTLW1 Bits */
+      __IO uint16_t bGLIT               	:	2;  /* Deglitch time */
+      __IO uint16_t bASTP               	:	2;  /* Automatic STOP condition generation */
+      __IO uint16_t bSWACK              	:	1;  /* SW or HW ACK control */
+      __IO uint16_t bSTPNACK            	:	1;  /* ACK all master bytes */
+      __IO uint16_t bCLTO               	:	2;  /* Clock low timeout select */
+      __IO uint16_t bETXINT             	:	1;  /* Early UCTXIFG0 */
+      __I  uint16_t bRESERVED0          	:	7;  /* Reserved */
+    } b;
+  } rCTLW1;
+  uint8_t  RESERVED0[2];
+  __IO uint16_t rBRW; /* eUSCI_Bx Baud Rate Control Word Register */
+  union {    /* UCB3STATW Register */
+    __IO uint16_t r;
+    struct { /* UCB3STATW Bits */
+      __I  uint16_t bRESERVED1          	:	4;  /* Reserved */
+      __I  uint16_t bBBUSY              	:	1;  /* Bus busy */
+      __I  uint16_t bGC                 	:	1;  /* General call address received */
+      __I  uint16_t bSCLLOW             	:	1;  /* SCL low */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __I  uint16_t bBCNT               	:	8;  /* Hardware byte counter value */
+    } b;
+    struct { /* UCB3STATW_SPI Bits */
+      __I  uint16_t bBUSY               	:	1;  /* eUSCI_B busy */
+      __IO uint16_t bRESERVED           	:	4;  /* Reserved */
+      __IO uint16_t bOE                 	:	1;  /* Overrun error flag */
+      __IO uint16_t bFE                 	:	1;  /* Framing error flag */
+      __IO uint16_t bLISTEN             	:	1;  /* Listen enable */
+    } a;
+  } rSTATW;
+  union {    /* UCB3TBCNT Register */
+    __IO uint16_t r;
+    struct { /* UCB3TBCNT Bits */
+      __IO uint16_t bTBCNT              	:	8;  /* Byte counter threshold value */
+      __I  uint16_t bRESERVED0          	:	8;  /* Reserved */
+    } b;
+  } rTBCNT;
+  union {    /* UCB3RXBUF Register */
+    __I uint16_t r;
+    struct { /* UCB3RXBUF Bits */
+      __I  uint16_t bRXBUF              	:	8;  /* Receive data buffer */
+      __I  uint16_t bRESERVED0          	:	8;  /* Reserved */
+    } b;
+    struct { /* UCB3RXBUF_SPI Bits */
+      __I  uint16_t bRXBUF              	:	8;  /* Receive data buffer */
+      __I  uint16_t bRESERVED           	:	8;  /* Reserved */
+    } a;
+  } rRXBUF;
+  union {    /* UCB3TXBUF Register */
+    __IO uint16_t r;
+    struct { /* UCB3TXBUF Bits */
+      __IO uint16_t bTXBUF              	:	8;  /* Transmit data buffer */
+      __I  uint16_t bRESERVED0          	:	8;  /* Reserved */
+    } b;
+    struct { /* UCB3TXBUF_SPI Bits */
+      __IO uint16_t bTXBUF              	:	8;  /* Transmit data buffer */
+      __I  uint16_t bRESERVED           	:	8;  /* Reserved */
+    } a;
+  } rTXBUF;
+  uint8_t  RESERVED1[4];
+  union {    /* UCB3I2COA0 Register */
+    __IO uint16_t r;
+    struct { /* UCB3I2COA0 Bits */
+      __IO uint16_t bI2COA0             	:	10;  /* I2C own address */
+      __IO uint16_t bOAEN               	:	1;  /* Own Address enable register */
+      __I  uint16_t bRESERVED0          	:	4;  /* Reserved */
+      __IO uint16_t bGCEN               	:	1;  /* General call response enable */
+    } b;
+  } rI2COA0;
+  union {    /* UCB3I2COA1 Register */
+    __IO uint16_t r;
+    struct { /* UCB3I2COA1 Bits */
+      __IO uint16_t bI2COA1             	:	10;  /* I2C own address */
+      __IO uint16_t bOAEN               	:	1;  /* Own Address enable register */
+      __I  uint16_t bRESERVED0          	:	5;  /* Reserved */
+    } b;
+  } rI2COA1;
+  union {    /* UCB3I2COA2 Register */
+    __IO uint16_t r;
+    struct { /* UCB3I2COA2 Bits */
+      __IO uint16_t bI2COA2             	:	10;  /* I2C own address */
+      __IO uint16_t bOAEN               	:	1;  /* Own Address enable register */
+      __I  uint16_t bRESERVED0          	:	5;  /* Reserved */
+    } b;
+  } rI2COA2;
+  union {    /* UCB3I2COA3 Register */
+    __IO uint16_t r;
+    struct { /* UCB3I2COA3 Bits */
+      __IO uint16_t bI2COA3             	:	10;  /* I2C own address */
+      __IO uint16_t bOAEN               	:	1;  /* Own Address enable register */
+      __I  uint16_t bRESERVED0          	:	5;  /* Reserved */
+    } b;
+  } rI2COA3;
+  union {    /* UCB3ADDRX Register */
+    __I uint16_t r;
+    struct { /* UCB3ADDRX Bits */
+      __I  uint16_t bADDRX              	:	10;  /* Received Address Register */
+      __I  uint16_t bRESERVED0          	:	6;  /* Reserved */
+    } b;
+  } rADDRX;
+  union {    /* UCB3ADDMASK Register */
+    __IO uint16_t r;
+    struct { /* UCB3ADDMASK Bits */
+      __IO uint16_t bADDMASK            	:	10;  /*  */
+      __I  uint16_t bRESERVED0          	:	6;  /* Reserved */
+    } b;
+  } rADDMASK;
+  union {    /* UCB3I2CSA Register */
+    __IO uint16_t r;
+    struct { /* UCB3I2CSA Bits */
+      __IO uint16_t bI2CSA              	:	10;  /* I2C slave address */
+      __I  uint16_t bRESERVED0          	:	6;  /* Reserved */
+    } b;
+  } rI2CSA;
+  uint8_t  RESERVED2[8];
+  union {    /* UCB3IE Register */
+    __IO uint16_t r;
+    struct { /* UCB3IE Bits */
+      __IO uint16_t bRXIE0              	:	1;  /* Receive interrupt enable 0 */
+      __IO uint16_t bTXIE0              	:	1;  /* Transmit interrupt enable 0 */
+      __IO uint16_t bSTTIE              	:	1;  /* START condition interrupt enable */
+      __IO uint16_t bSTPIE              	:	1;  /* STOP condition interrupt enable */
+      __IO uint16_t bALIE               	:	1;  /* Arbitration lost interrupt enable */
+      __IO uint16_t bNACKIE             	:	1;  /* Not-acknowledge interrupt enable */
+      __IO uint16_t bBCNTIE             	:	1;  /* Byte counter interrupt enable */
+      __IO uint16_t bCLTOIE             	:	1;  /* Clock low timeout interrupt enable */
+      __IO uint16_t bRXIE1              	:	1;  /* Receive interrupt enable 1 */
+      __IO uint16_t bTXIE1              	:	1;  /* Transmit interrupt enable 1 */
+      __IO uint16_t bRXIE2              	:	1;  /* Receive interrupt enable 2 */
+      __IO uint16_t bTXIE2              	:	1;  /* Transmit interrupt enable 2 */
+      __IO uint16_t bRXIE3              	:	1;  /* Receive interrupt enable 3 */
+      __IO uint16_t bTXIE3              	:	1;  /* Transmit interrupt enable 3 */
+      __IO uint16_t bBIT9IE             	:	1;  /* Bit position 9 interrupt enable */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+    } b;
+    struct { /* UCB3IE_SPI Bits */
+      __IO uint16_t bRXIE               	:	1;  /* Receive interrupt enable */
+      __IO uint16_t bTXIE               	:	1;  /* Transmit interrupt enable */
+      __I  uint16_t bRESERVED           	:	14;  /* Reserved */
+    } a;
+  } rIE;
+  union {    /* UCB3IFG Register */
+    __IO uint16_t r;
+    struct { /* UCB3IFG Bits */
+      __IO uint16_t bRXIFG0             	:	1;  /* eUSCI_B receive interrupt flag 0 */
+      __IO uint16_t bTXIFG0             	:	1;  /* eUSCI_B transmit interrupt flag 0 */
+      __IO uint16_t bSTTIFG             	:	1;  /* START condition interrupt flag */
+      __IO uint16_t bSTPIFG             	:	1;  /* STOP condition interrupt flag */
+      __IO uint16_t bALIFG              	:	1;  /* Arbitration lost interrupt flag */
+      __IO uint16_t bNACKIFG            	:	1;  /* Not-acknowledge received interrupt flag */
+      __IO uint16_t bBCNTIFG            	:	1;  /* Byte counter interrupt flag */
+      __IO uint16_t bCLTOIFG            	:	1;  /* Clock low timeout interrupt flag */
+      __IO uint16_t bRXIFG1             	:	1;  /* eUSCI_B receive interrupt flag 1 */
+      __IO uint16_t bTXIFG1             	:	1;  /* eUSCI_B transmit interrupt flag 1 */
+      __IO uint16_t bRXIFG2             	:	1;  /* eUSCI_B receive interrupt flag 2 */
+      __IO uint16_t bTXIFG2             	:	1;  /* eUSCI_B transmit interrupt flag 2 */
+      __IO uint16_t bRXIFG3             	:	1;  /* eUSCI_B receive interrupt flag 3 */
+      __IO uint16_t bTXIFG3             	:	1;  /* eUSCI_B transmit interrupt flag 3 */
+      __IO uint16_t bBIT9IFG            	:	1;  /* Bit position 9 interrupt flag */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+    } b;
+    struct { /* UCB3IFG_SPI Bits */
+      __IO uint16_t bRXIFG              	:	1;  /* Receive interrupt flag */
+      __IO uint16_t bTXIFG              	:	1;  /* Transmit interrupt flag */
+      __I  uint16_t bRESERVED           	:	14;  /* Reserved */
+    } a;
+  } rIFG;
+  __I uint16_t rIV; /* eUSCI_Bx Interrupt Vector Register */
+} EUSCI_B3_Type;
+
+
+//*****************************************************************************
+// FLCTL Registers
+//*****************************************************************************
+typedef struct {
+  union {    /* FLCTL_POWER_STAT Register */
+    __I uint32_t r;
+    struct { /* FLCTL_POWER_STAT Bits */
+      __I  uint32_t bPSTAT              	:	3;  /*  */
+      __I  uint32_t bLDOSTAT            	:	1;  /* PSS FLDO GOOD status */
+      __I  uint32_t bVREFSTAT           	:	1;  /* PSS VREF stable status */
+      __I  uint32_t bIREFSTAT           	:	1;  /* PSS IREF stable status */
+      __I  uint32_t bTRIMSTAT           	:	1;  /* PSS trim done status */
+      __I  uint32_t bRD_2T              	:	1;  /* Indicates if Flash is being accessed in 2T mode */
+      __I  uint32_t bRESERVED0          	:	24;  /* Reserved */
+    } b;
+  } rPOWER_STAT;
+  uint8_t  RESERVED0[12];
+  union {    /* FLCTL_BANK0_RDCTL Register */
+    __IO uint32_t r;
+    struct { /* FLCTL_BANK0_RDCTL Bits */
+      __IO uint32_t bRD_MODE            	:	4;  /* Flash read mode control setting for Bank 0 */
+      __IO uint32_t bBUFI               	:	1;  /* Enables read buffering feature for instruction fetches to this Bank */
+      __IO uint32_t bBUFD               	:	1;  /* Enables read buffering feature for data reads to this Bank */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bRESERVED2          	:	1;  /* Reserved */
+      __IO uint32_t bRESERVED3          	:	1;  /* Reserved */
+      __IO uint32_t bRESERVED4          	:	1;  /* Reserved */
+      __IO uint32_t bWAIT               	:	4;  /* Number of wait states for read */
+      __I  uint32_t bRD_MODE_STATUS     	:	4;  /* Read mode */
+      __I  uint32_t bRESERVED5          	:	12;  /* Reserved */
+    } b;
+  } rBANK0_RDCTL;
+  union {    /* FLCTL_BANK1_RDCTL Register */
+    __IO uint32_t r;
+    struct { /* FLCTL_BANK1_RDCTL Bits */
+      __IO uint32_t bRD_MODE            	:	4;  /* Flash read mode control setting for Bank 0 */
+      __IO uint32_t bBUFI               	:	1;  /* Enables read buffering feature for instruction fetches to this Bank */
+      __IO uint32_t bBUFD               	:	1;  /* Enables read buffering feature for data reads to this Bank */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bRESERVED2          	:	1;  /* Reserved */
+      __IO uint32_t bRESERVED3          	:	1;  /* Reserved */
+      __IO uint32_t bRESERVED4          	:	1;  /* Reserved */
+      __IO uint32_t bWAIT               	:	4;  /* Number of wait states for read */
+      __I  uint32_t bRD_MODE_STATUS     	:	4;  /* Read mode */
+      __I  uint32_t bRESERVED5          	:	12;  /* Reserved */
+    } b;
+  } rBANK1_RDCTL;
+  uint8_t  RESERVED1[8];
+  union {    /* FLCTL_RDBRST_CTLSTAT Register */
+    __IO uint32_t r;
+    struct { /* FLCTL_RDBRST_CTLSTAT Bits */
+      __O  uint32_t bSTART              	:	1;  /* Start of burst/compare operation */
+      __IO uint32_t bMEM_TYPE           	:	2;  /* Type of memory that burst is carried out on */
+      __IO uint32_t bSTOP_FAIL          	:	1;  /* Terminate burst/compare operation */
+      __IO uint32_t bDATA_CMP           	:	1;  /* Data pattern used for comparison against memory read data */
+      __IO uint32_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint32_t bTEST_EN            	:	1;  /* Enable comparison against test data compare registers */
+      __I  uint32_t bRESERVED1          	:	9;  /* Reserved */
+      __I  uint32_t bBRST_STAT          	:	2;  /* Status of Burst/Compare operation */
+      __I  uint32_t bCMP_ERR            	:	1;  /* Burst/Compare Operation encountered atleast one data */
+      __I  uint32_t bADDR_ERR           	:	1;  /* Burst/Compare Operation was terminated due to access to */
+      __I  uint32_t bRESERVED2          	:	3;  /* Reserved */
+      __O  uint32_t bCLR_STAT           	:	1;  /* Clear status bits 19-16 of this register */
+      __I  uint32_t bRESERVED3          	:	8;  /* Reserved */
+    } b;
+  } rRDBRST_CTLSTAT;
+  union {    /* FLCTL_RDBRST_STARTADDR Register */
+    __IO uint32_t r;
+    struct { /* FLCTL_RDBRST_STARTADDR Bits */
+      __IO uint32_t bSTART_ADDRESS      	:	21;  /* Start Address of Burst Operation */
+      __I  uint32_t bRESERVED0          	:	11;  /* Reserved */
+    } b;
+  } rRDBRST_STARTADDR;
+  union {    /* FLCTL_RDBRST_LEN Register */
+    __IO uint32_t r;
+    struct { /* FLCTL_RDBRST_LEN Bits */
+      __IO uint32_t bBURST_LENGTH       	:	21;  /* Length of Burst Operation */
+      __I  uint32_t bRESERVED0          	:	11;  /* Reserved */
+    } b;
+  } rRDBRST_LEN;
+  uint8_t  RESERVED2[16];
+  union {    /* FLCTL_RDBRST_FAILADDR Register */
+    __IO uint32_t r;
+    struct { /* FLCTL_RDBRST_FAILADDR Bits */
+      __IO uint32_t bFAIL_ADDRESS       	:	21;  /* Reflects address of last failed compare */
+      __I  uint32_t bRESERVED0          	:	11;  /* Reserved */
+    } b;
+  } rRDBRST_FAILADDR;
+  union {    /* FLCTL_RDBRST_FAILCNT Register */
+    __IO uint32_t r;
+    struct { /* FLCTL_RDBRST_FAILCNT Bits */
+      __IO uint32_t bFAIL_COUNT         	:	17;  /* Number of failures encountered in burst operation */
+      __I  uint32_t bRESERVED0          	:	15;  /* Reserved */
+    } b;
+  } rRDBRST_FAILCNT;
+  uint8_t  RESERVED3[12];
+  union {    /* FLCTL_PRG_CTLSTAT Register */
+    __IO uint32_t r;
+    struct { /* FLCTL_PRG_CTLSTAT Bits */
+      __IO uint32_t bENABLE             	:	1;  /* Master control for all word program operations */
+      __IO uint32_t bMODE               	:	1;  /* Write mode */
+      __IO uint32_t bVER_PRE            	:	1;  /* Controls automatic pre program verify operations */
+      __IO uint32_t bVER_PST            	:	1;  /* Controls automatic post program verify operations */
+      __I  uint32_t bRESERVED0          	:	12;  /* Reserved */
+      __I  uint32_t bSTATUS             	:	2;  /* Status of program operations in the Flash memory */
+      __I  uint32_t bBNK_ACT            	:	1;  /* Bank active */
+      __I  uint32_t bRESERVED1          	:	13;  /* Reserved */
+    } b;
+  } rPRG_CTLSTAT;
+  union {    /* FLCTL_PRGBRST_CTLSTAT Register */
+    __IO uint32_t r;
+    struct { /* FLCTL_PRGBRST_CTLSTAT Bits */
+      __O  uint32_t bSTART              	:	1;  /* Trigger start of burst program operation */
+      __IO uint32_t bTYPE               	:	2;  /* Type of memory that burst program is carried out on */
+      __IO uint32_t bLEN                	:	3;  /* Length of burst */
+      __IO uint32_t bAUTO_PRE           	:	1;  /* Auto-Verify operation before the Burst Program */
+      __IO uint32_t bAUTO_PST           	:	1;  /* Auto-Verify operation after the Burst Program */
+      __I  uint32_t bRESERVED0          	:	8;  /* Reserved */
+      __I  uint32_t bBURST_STATUS       	:	3;  /* Status of a Burst Operation */
+      __I  uint32_t bPRE_ERR            	:	1;  /* Burst Operation encountered preprogram auto-verify errors */
+      __I  uint32_t bPST_ERR            	:	1;  /* Burst Operation encountered postprogram auto-verify errors */
+      __I  uint32_t bADDR_ERR           	:	1;  /* Burst Operation was terminated due to attempted program of reserved memory */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __O  uint32_t bCLR_STAT           	:	1;  /* Clear status bits 21-16 of this register */
+      __I  uint32_t bRESERVED2          	:	8;  /* Reserved */
+    } b;
+  } rPRGBRST_CTLSTAT;
+  union {    /* FLCTL_PRGBRST_STARTADDR Register */
+    __IO uint32_t r;
+    struct { /* FLCTL_PRGBRST_STARTADDR Bits */
+      __IO uint32_t bSTART_ADDRESS      	:	22;  /* Start Address of Program Burst Operation */
+      __I  uint32_t bRESERVED0          	:	10;  /* Reserved */
+    } b;
+  } rPRGBRST_STARTADDR;
+  uint8_t  RESERVED4[4];
+  __IO uint32_t rPRGBRST_DATA0_0; /* Program Burst Data0 Register0 */
+  __IO uint32_t rPRGBRST_DATA0_1; /* Program Burst Data0 Register1 */
+  __IO uint32_t rPRGBRST_DATA0_2; /* Program Burst Data0 Register2 */
+  __IO uint32_t rPRGBRST_DATA0_3; /* Program Burst Data0 Register3 */
+  __IO uint32_t rPRGBRST_DATA1_0; /* Program Burst Data1 Register0 */
+  __IO uint32_t rPRGBRST_DATA1_1; /* Program Burst Data1 Register1 */
+  __IO uint32_t rPRGBRST_DATA1_2; /* Program Burst Data1 Register2 */
+  __IO uint32_t rPRGBRST_DATA1_3; /* Program Burst Data1 Register3 */
+  __IO uint32_t rPRGBRST_DATA2_0; /* Program Burst Data2 Register0 */
+  __IO uint32_t rPRGBRST_DATA2_1; /* Program Burst Data2 Register1 */
+  __IO uint32_t rPRGBRST_DATA2_2; /* Program Burst Data2 Register2 */
+  __IO uint32_t rPRGBRST_DATA2_3; /* Program Burst Data2 Register3 */
+  __IO uint32_t rPRGBRST_DATA3_0; /* Program Burst Data3 Register0 */
+  __IO uint32_t rPRGBRST_DATA3_1; /* Program Burst Data3 Register1 */
+  __IO uint32_t rPRGBRST_DATA3_2; /* Program Burst Data3 Register2 */
+  __IO uint32_t rPRGBRST_DATA3_3; /* Program Burst Data3 Register3 */
+  union {    /* FLCTL_ERASE_CTLSTAT Register */
+    __IO uint32_t r;
+    struct { /* FLCTL_ERASE_CTLSTAT Bits */
+      __O  uint32_t bSTART              	:	1;  /* Start of Erase operation */
+      __IO uint32_t bMODE               	:	1;  /* Erase mode selected by application */
+      __IO uint32_t bTYPE               	:	2;  /* Type of memory that erase operation is carried out on */
+      __I  uint32_t bRESERVED0          	:	12;  /* Reserved */
+      __I  uint32_t bSTATUS             	:	2;  /* Status of erase operations in the Flash memory */
+      __I  uint32_t bADDR_ERR           	:	1;  /* Erase Operation was terminated due to attempted erase of reserved memory address */
+      __O  uint32_t bCLR_STAT           	:	1;  /* Clear status bits 18-16 of this register */
+      __I  uint32_t bRESERVED1          	:	12;  /* Reserved */
+    } b;
+  } rERASE_CTLSTAT;
+  union {    /* FLCTL_ERASE_SECTADDR Register */
+    __IO uint32_t r;
+    struct { /* FLCTL_ERASE_SECTADDR Bits */
+      __IO uint32_t bSECT_ADDRESS       	:	22;  /* Address of Sector being Erased */
+      __I  uint32_t bRESERVED0          	:	10;  /* Reserved */
+    } b;
+  } rERASE_SECTADDR;
+  uint8_t  RESERVED5[8];
+  union {    /* FLCTL_BANK0_INFO_WEPROT Register */
+    __IO uint32_t r;
+    struct { /* FLCTL_BANK0_INFO_WEPROT Bits */
+      __IO uint32_t bPROT0              	:	1;  /* Protects Sector 0 from program or erase */
+      __IO uint32_t bPROT1              	:	1;  /* Protects Sector 1 from program or erase */
+      __I  uint32_t bRESERVED0          	:	30;  /* Reserved */
+    } b;
+  } rBANK0_INFO_WEPROT;
+  union {    /* FLCTL_BANK0_MAIN_WEPROT Register */
+    __IO uint32_t r;
+    struct { /* FLCTL_BANK0_MAIN_WEPROT Bits */
+      __IO uint32_t bPROT0              	:	1;  /* Protects Sector 0 from program or erase */
+      __IO uint32_t bPROT1              	:	1;  /* Protects Sector 1 from program or erase */
+      __IO uint32_t bPROT2              	:	1;  /* Protects Sector 2 from program or erase */
+      __IO uint32_t bPROT3              	:	1;  /* Protects Sector 3 from program or erase */
+      __IO uint32_t bPROT4              	:	1;  /* Protects Sector 4 from program or erase */
+      __IO uint32_t bPROT5              	:	1;  /* Protects Sector 5 from program or erase */
+      __IO uint32_t bPROT6              	:	1;  /* Protects Sector 6 from program or erase */
+      __IO uint32_t bPROT7              	:	1;  /* Protects Sector 7 from program or erase */
+      __IO uint32_t bPROT8              	:	1;  /* Protects Sector 8 from program or erase */
+      __IO uint32_t bPROT9              	:	1;  /* Protects Sector 9 from program or erase */
+      __IO uint32_t bPROT10             	:	1;  /* Protects Sector 10 from program or erase */
+      __IO uint32_t bPROT11             	:	1;  /* Protects Sector 11 from program or erase */
+      __IO uint32_t bPROT12             	:	1;  /* Protects Sector 12 from program or erase */
+      __IO uint32_t bPROT13             	:	1;  /* Protects Sector 13 from program or erase */
+      __IO uint32_t bPROT14             	:	1;  /* Protects Sector 14 from program or erase */
+      __IO uint32_t bPROT15             	:	1;  /* Protects Sector 15 from program or erase */
+      __IO uint32_t bPROT16             	:	1;  /* Protects Sector 16 from program or erase */
+      __IO uint32_t bPROT17             	:	1;  /* Protects Sector 17 from program or erase */
+      __IO uint32_t bPROT18             	:	1;  /* Protects Sector 18 from program or erase */
+      __IO uint32_t bPROT19             	:	1;  /* Protects Sector 19 from program or erase */
+      __IO uint32_t bPROT20             	:	1;  /* Protects Sector 20 from program or erase */
+      __IO uint32_t bPROT21             	:	1;  /* Protects Sector 21 from program or erase */
+      __IO uint32_t bPROT22             	:	1;  /* Protects Sector 22 from program or erase */
+      __IO uint32_t bPROT23             	:	1;  /* Protects Sector 23 from program or erase */
+      __IO uint32_t bPROT24             	:	1;  /* Protects Sector 24 from program or erase */
+      __IO uint32_t bPROT25             	:	1;  /* Protects Sector 25 from program or erase */
+      __IO uint32_t bPROT26             	:	1;  /* Protects Sector 26 from program or erase */
+      __IO uint32_t bPROT27             	:	1;  /* Protects Sector 27 from program or erase */
+      __IO uint32_t bPROT28             	:	1;  /* Protects Sector 28 from program or erase */
+      __IO uint32_t bPROT29             	:	1;  /* Protects Sector 29 from program or erase */
+      __IO uint32_t bPROT30             	:	1;  /* Protects Sector 30 from program or erase */
+      __IO uint32_t bPROT31             	:	1;  /* Protects Sector 31 from program or erase */
+    } b;
+  } rBANK0_MAIN_WEPROT;
+  uint8_t  RESERVED6[8];
+  union {    /* FLCTL_BANK1_INFO_WEPROT Register */
+    __IO uint32_t r;
+    struct { /* FLCTL_BANK1_INFO_WEPROT Bits */
+      __IO uint32_t bPROT0              	:	1;  /* Protects Sector 0 from program or erase operations */
+      __IO uint32_t bPROT1              	:	1;  /* Protects Sector 1 from program or erase operations */
+      __I  uint32_t bRESERVED0          	:	30;  /* Reserved */
+    } b;
+  } rBANK1_INFO_WEPROT;
+  union {    /* FLCTL_BANK1_MAIN_WEPROT Register */
+    __IO uint32_t r;
+    struct { /* FLCTL_BANK1_MAIN_WEPROT Bits */
+      __IO uint32_t bPROT0              	:	1;  /* Protects Sector 0 from program or erase operations */
+      __IO uint32_t bPROT1              	:	1;  /* Protects Sector 1 from program or erase operations */
+      __IO uint32_t bPROT2              	:	1;  /* Protects Sector 2 from program or erase operations */
+      __IO uint32_t bPROT3              	:	1;  /* Protects Sector 3 from program or erase operations */
+      __IO uint32_t bPROT4              	:	1;  /* Protects Sector 4 from program or erase operations */
+      __IO uint32_t bPROT5              	:	1;  /* Protects Sector 5 from program or erase operations */
+      __IO uint32_t bPROT6              	:	1;  /* Protects Sector 6 from program or erase operations */
+      __IO uint32_t bPROT7              	:	1;  /* Protects Sector 7 from program or erase operations */
+      __IO uint32_t bPROT8              	:	1;  /* Protects Sector 8 from program or erase operations */
+      __IO uint32_t bPROT9              	:	1;  /* Protects Sector 9 from program or erase operations */
+      __IO uint32_t bPROT10             	:	1;  /* Protects Sector 10 from program or erase operations */
+      __IO uint32_t bPROT11             	:	1;  /* Protects Sector 11 from program or erase operations */
+      __IO uint32_t bPROT12             	:	1;  /* Protects Sector 12 from program or erase operations */
+      __IO uint32_t bPROT13             	:	1;  /* Protects Sector 13 from program or erase operations */
+      __IO uint32_t bPROT14             	:	1;  /* Protects Sector 14 from program or erase operations */
+      __IO uint32_t bPROT15             	:	1;  /* Protects Sector 15 from program or erase operations */
+      __IO uint32_t bPROT16             	:	1;  /* Protects Sector 16 from program or erase operations */
+      __IO uint32_t bPROT17             	:	1;  /* Protects Sector 17 from program or erase operations */
+      __IO uint32_t bPROT18             	:	1;  /* Protects Sector 18 from program or erase operations */
+      __IO uint32_t bPROT19             	:	1;  /* Protects Sector 19 from program or erase operations */
+      __IO uint32_t bPROT20             	:	1;  /* Protects Sector 20 from program or erase operations */
+      __IO uint32_t bPROT21             	:	1;  /* Protects Sector 21 from program or erase operations */
+      __IO uint32_t bPROT22             	:	1;  /* Protects Sector 22 from program or erase operations */
+      __IO uint32_t bPROT23             	:	1;  /* Protects Sector 23 from program or erase operations */
+      __IO uint32_t bPROT24             	:	1;  /* Protects Sector 24 from program or erase operations */
+      __IO uint32_t bPROT25             	:	1;  /* Protects Sector 25 from program or erase operations */
+      __IO uint32_t bPROT26             	:	1;  /* Protects Sector 26 from program or erase operations */
+      __IO uint32_t bPROT27             	:	1;  /* Protects Sector 27 from program or erase operations */
+      __IO uint32_t bPROT28             	:	1;  /* Protects Sector 28 from program or erase operations */
+      __IO uint32_t bPROT29             	:	1;  /* Protects Sector 29 from program or erase operations */
+      __IO uint32_t bPROT30             	:	1;  /* Protects Sector 30 from program or erase operations */
+      __IO uint32_t bPROT31             	:	1;  /* Protects Sector 31 from program or erase operations */
+    } b;
+  } rBANK1_MAIN_WEPROT;
+  uint8_t  RESERVED7[8];
+  union {    /* FLCTL_BMRK_CTLSTAT Register */
+    __IO uint32_t r;
+    struct { /* FLCTL_BMRK_CTLSTAT Bits */
+      __IO uint32_t bI_BMRK             	:	1;  /*  */
+      __IO uint32_t bD_BMRK             	:	1;  /*  */
+      __IO uint32_t bCMP_EN             	:	1;  /*  */
+      __IO uint32_t bCMP_SEL            	:	1;  /*  */
+      __I  uint32_t bRESERVED0          	:	28;  /* Reserved */
+    } b;
+  } rBMRK_CTLSTAT;
+  __IO uint32_t rBMRK_IFETCH; /* Benchmark Instruction Fetch Count Register */
+  __IO uint32_t rBMRK_DREAD; /* Benchmark Data Read Count Register */
+  __IO uint32_t rBMRK_CMP; /* Benchmark Count Compare Register */
+  uint8_t  RESERVED8[16];
+  union {    /* FLCTL_IFG Register */
+    __IO uint32_t r;
+    struct { /* FLCTL_IFG Bits */
+      __I  uint32_t bRDBRST             	:	1;  /*  */
+      __I  uint32_t bAVPRE              	:	1;  /*  */
+      __I  uint32_t bAVPST              	:	1;  /*  */
+      __I  uint32_t bPRG                	:	1;  /*  */
+      __I  uint32_t bPRGB               	:	1;  /*  */
+      __I  uint32_t bERASE              	:	1;  /*  */
+      __I  uint32_t bRESERVED0          	:	1;  /* Reserved */
+      __I  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __I  uint32_t bBMRK               	:	1;  /*  */
+      __I  uint32_t bPRG_ERR            	:	1;  /*  */
+      __I  uint32_t bRESERVED2          	:	22;  /* Reserved */
+    } b;
+  } rIFG;
+  union {    /* FLCTL_IE Register */
+    __IO uint32_t r;
+    struct { /* FLCTL_IE Bits */
+      __IO uint32_t bRDBRST             	:	1;  /*  */
+      __IO uint32_t bAVPRE              	:	1;  /*  */
+      __IO uint32_t bAVPST              	:	1;  /*  */
+      __IO uint32_t bPRG                	:	1;  /*  */
+      __IO uint32_t bPRGB               	:	1;  /*  */
+      __IO uint32_t bERASE              	:	1;  /*  */
+      __IO uint32_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __IO uint32_t bBMRK               	:	1;  /*  */
+      __IO uint32_t bPRG_ERR            	:	1;  /*  */
+      __I  uint32_t bRESERVED2          	:	22;  /* Reserved */
+    } b;
+  } rIE;
+  union {    /* FLCTL_CLRIFG Register */
+    __IO uint32_t r;
+    struct { /* FLCTL_CLRIFG Bits */
+      __O  uint32_t bRDBRST             	:	1;  /*  */
+      __O  uint32_t bAVPRE              	:	1;  /*  */
+      __O  uint32_t bAVPST              	:	1;  /*  */
+      __O  uint32_t bPRG                	:	1;  /*  */
+      __O  uint32_t bPRGB               	:	1;  /*  */
+      __O  uint32_t bERASE              	:	1;  /*  */
+      __O  uint32_t bRESERVED0          	:	1;  /* Reserved */
+      __O  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __O  uint32_t bBMRK               	:	1;  /*  */
+      __O  uint32_t bPRG_ERR            	:	1;  /*  */
+      __I  uint32_t bRESERVED2          	:	22;  /* Reserved */
+    } b;
+  } rCLRIFG;
+  union {    /* FLCTL_SETIFG Register */
+    __IO uint32_t r;
+    struct { /* FLCTL_SETIFG Bits */
+      __O  uint32_t bRDBRST             	:	1;  /*  */
+      __O  uint32_t bAVPRE              	:	1;  /*  */
+      __O  uint32_t bAVPST              	:	1;  /*  */
+      __O  uint32_t bPRG                	:	1;  /*  */
+      __O  uint32_t bPRGB               	:	1;  /*  */
+      __O  uint32_t bERASE              	:	1;  /*  */
+      __O  uint32_t bRESERVED0          	:	1;  /* Reserved */
+      __O  uint32_t bRESERVED1          	:	1;  /* Reserved */
+      __O  uint32_t bBMRK               	:	1;  /*  */
+      __O  uint32_t bPRG_ERR            	:	1;  /*  */
+      __I  uint32_t bRESERVED2          	:	22;  /* Reserved */
+    } b;
+  } rSETIFG;
+  union {    /* FLCTL_READ_TIMCTL Register */
+    __IO uint32_t r;
+    struct { /* FLCTL_READ_TIMCTL Bits */
+      __IO uint32_t bSETUP              	:	8;  /*  */
+      __IO uint32_t bHOLD               	:	4;  /*  */
+      __IO uint32_t bIREF_BOOST1        	:	4;  /*  */
+      __IO uint32_t bSETUP_LONG         	:	8;  /*  */
+      __I  uint32_t bRESERVED0          	:	8;  /* Reserved */
+    } b;
+  } rREAD_TIMCTL;
+  union {    /* FLCTL_READMARGIN_TIMCTL Register */
+    __IO uint32_t r;
+    struct { /* FLCTL_READMARGIN_TIMCTL Bits */
+      __IO uint32_t bSETUP              	:	8;  /*  */
+      __IO uint32_t bHOLD               	:	4;  /*  */
+      __I  uint32_t bRESERVED0          	:	4;  /* Reserved */
+      __I  uint32_t bRESERVED1          	:	16;  /* Reserved */
+    } b;
+  } rREADMARGIN_TIMCTL;
+  union {    /* FLCTL_PRGVER_TIMCTL Register */
+    __IO uint32_t r;
+    struct { /* FLCTL_PRGVER_TIMCTL Bits */
+      __IO uint32_t bSETUP              	:	8;  /*  */
+      __IO uint32_t bACTIVE             	:	4;  /*  */
+      __IO uint32_t bHOLD               	:	4;  /*  */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rPRGVER_TIMCTL;
+  union {    /* FLCTL_ERSVER_TIMCTL Register */
+    __IO uint32_t r;
+    struct { /* FLCTL_ERSVER_TIMCTL Bits */
+      __IO uint32_t bSETUP              	:	8;  /*  */
+      __IO uint32_t bHOLD               	:	4;  /*  */
+      __I  uint32_t bRESERVED0          	:	4;  /* Reserved */
+      __I  uint32_t bRESERVED1          	:	16;  /* Reserved */
+    } b;
+  } rERSVER_TIMCTL;
+  union {    /* FLCTL_LKGVER_TIMCTL Register */
+    __IO uint32_t r;
+    struct { /* FLCTL_LKGVER_TIMCTL Bits */
+      __IO uint32_t bSETUP              	:	8;  /*  */
+      __IO uint32_t bHOLD               	:	4;  /*  */
+      __I  uint32_t bRESERVED0          	:	4;  /* Reserved */
+      __I  uint32_t bRESERVED1          	:	16;  /* Reserved */
+    } b;
+  } rLKGVER_TIMCTL;
+  union {    /* FLCTL_PROGRAM_TIMCTL Register */
+    __IO uint32_t r;
+    struct { /* FLCTL_PROGRAM_TIMCTL Bits */
+      __IO uint32_t bSETUP              	:	8;  /*  */
+      __IO uint32_t bACTIVE             	:	20;  /*  */
+      __IO uint32_t bHOLD               	:	4;  /*  */
+    } b;
+  } rPROGRAM_TIMCTL;
+  union {    /* FLCTL_ERASE_TIMCTL Register */
+    __IO uint32_t r;
+    struct { /* FLCTL_ERASE_TIMCTL Bits */
+      __IO uint32_t bSETUP              	:	8;  /*  */
+      __IO uint32_t bACTIVE             	:	20;  /*  */
+      __IO uint32_t bHOLD               	:	4;  /*  */
+    } b;
+  } rERASE_TIMCTL;
+  union {    /* FLCTL_MASSERASE_TIMCTL Register */
+    __IO uint32_t r;
+    struct { /* FLCTL_MASSERASE_TIMCTL Bits */
+      __IO uint32_t bBOOST_ACTIVE       	:	8;  /*  */
+      __IO uint32_t bBOOST_HOLD         	:	8;  /*  */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rMASSERASE_TIMCTL;
+  union {    /* FLCTL_BURSTPRG_TIMCTL Register */
+    __IO uint32_t r;
+    struct { /* FLCTL_BURSTPRG_TIMCTL Bits */
+      __I  uint32_t bRESERVED0          	:	8;  /* Reserved */
+      __IO uint32_t bACTIVE             	:	20;  /*  */
+      __I  uint32_t bRESERVED1          	:	4;  /* Reserved */
+    } b;
+  } rBURSTPRG_TIMCTL;
+} FLCTL_Type;
+
+
+//*****************************************************************************
+// PCM Registers
+//*****************************************************************************
+typedef struct {
+  union {    /* PCMCTL0 Register */
+    __IO uint32_t r;
+    struct { /* PCMCTL0 Bits */
+      __IO uint32_t bAMR                	:	4;  /* Active Mode Request */
+      __IO uint32_t bLPMR               	:	4;  /* Low Power Mode Request */
+      __I  uint32_t bCPM                	:	6;  /* Current Power Mode */
+      __I  uint32_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint32_t bKEY                	:	16;  /* PCM key */
+    } b;
+  } rCTL0;
+  union {    /* PCMCTL1 Register */
+    __IO uint32_t r;
+    struct { /* PCMCTL1 Bits */
+      __IO uint32_t bLOCKLPM5           	:	1;  /* Lock LPM5 */
+      __IO uint32_t bLOCKBKUP           	:	1;  /* Lock Backup */
+      __IO uint32_t bFORCE_LPM_ENTRY    	:	1;  /* Force LPM entry */
+      __I  uint32_t bRESERVED0          	:	5;  /* Reserved */
+      __IO uint32_t bPMR_BUSY           	:	1;  /* Power mode request busy flag */
+      __I  uint32_t bRESERVED1          	:	7;  /* Reserved */
+      __IO uint32_t bKEY                	:	16;  /* PCM key */
+    } b;
+  } rCTL1;
+  union {    /* PCMIE Register */
+    __IO uint32_t r;
+    struct { /* PCMIE Bits */
+      __IO uint32_t bLPM_INVALID_TR_IE  	:	1;  /* LPM invalid transition interrupt enable */
+      __IO uint32_t bLPM_INVALID_CLK_IE 	:	1;  /* LPM invalid clock interrupt enable */
+      __IO uint32_t bAM_INVALID_TR_IE   	:	1;  /* Active mode invalid transition interrupt enable */
+      __I  uint32_t bRESERVED0          	:	3;  /* Reserved */
+      __IO uint32_t bDCDC_ERROR_IE      	:	1;  /* DC-DC error interrupt enable */
+      __I  uint32_t bRESERVED1          	:	25;  /* Reserved */
+    } b;
+  } rIE;
+  union {    /* PCMIFG Register */
+    __I uint32_t r;
+    struct { /* PCMIFG Bits */
+      __I  uint32_t bLPM_INVALID_TR_IFG 	:	1;  /* LPM invalid transition flag */
+      __I  uint32_t bLPM_INVALID_CLK_IFG	:	1;  /* LPM invalid clock flag */
+      __I  uint32_t bAM_INVALID_TR_IFG  	:	1;  /* Active mode invalid transition flag */
+      __I  uint32_t bRESERVED0          	:	3;  /* Reserved */
+      __I  uint32_t bDCDC_ERROR_IFG     	:	1;  /* DC-DC error flag */
+      __I  uint32_t bRESERVED1          	:	25;  /* Reserved */
+    } b;
+  } rIFG;
+  union {    /* PCMCLRIFG Register */
+    __O uint32_t r;
+    struct { /* PCMCLRIFG Bits */
+      __O  uint32_t bCLR_LPM_INVALID_TR_IFG	:	1;  /* Clear LPM invalid transition flag */
+      __O  uint32_t bCLR_LPM_INVALID_CLK_IFG	:	1;  /* Clear LPM invalid clock flag */
+      __O  uint32_t bCLR_AM_INVALID_TR_IFG	:	1;  /* Clear active mode invalid transition flag */
+      __O  uint32_t bRESERVED0          	:	3;  /* Reserved */
+      __O  uint32_t bCLR_DCDC_ERROR_IFG 	:	1;  /* Clear DC-DC error flag */
+      __O  uint32_t bRESERVED1          	:	25;  /* Reserved */
+    } b;
+  } rCLRIFG;
+} PCM_Type;
+
+
+//*****************************************************************************
+// PMAP Registers
+//*****************************************************************************
+typedef struct {
+  __IO uint16_t rKEYID; /* Port Mapping Key Register */
+  union {    /* PMAPCTL Register */
+    __IO uint16_t r;
+    struct { /* PMAPCTL Bits */
+      __I  uint16_t bLOCKED             	:	1;  /* Port mapping lock bit */
+      __IO uint16_t bPRECFG             	:	1;  /* Port mapping reconfiguration control bit */
+      __I  uint16_t bRESERVED0          	:	14;  /* Reserved */
+    } b;
+  } rCTL;
+  uint8_t  RESERVED0[4];
+  __IO uint16_t rP1MAP01; /* Port mapping register, P1.0 and P1.1 */
+  __IO uint16_t rP1MAP23; /* Port mapping register, P1.2 and P1.3 */
+  __IO uint16_t rP1MAP45; /* Port mapping register, P1.4 and P1.5 */
+  __IO uint16_t rP1MAP67; /* Port mapping register, P1.6 and P1.7 */
+  __IO uint16_t rP2MAP01; /* Port mapping register, P2.0 and P2.1 */
+  __IO uint16_t rP2MAP23; /* Port mapping register, P2.2 and P2.3 */
+  __IO uint16_t rP2MAP45; /* Port mapping register, P2.4 and P2.5 */
+  __IO uint16_t rP2MAP67; /* Port mapping register, P2.6 and P2.7 */
+  __IO uint16_t rP3MAP01; /* Port mapping register, P3.0 and P3.1 */
+  __IO uint16_t rP3MAP23; /* Port mapping register, P3.2 and P3.3 */
+  __IO uint16_t rP3MAP45; /* Port mapping register, P3.4 and P3.5 */
+  __IO uint16_t rP3MAP67; /* Port mapping register, P3.6 and P3.7 */
+  __IO uint16_t rP4MAP01; /* Port mapping register, P4.0 and P4.1 */
+  __IO uint16_t rP4MAP23; /* Port mapping register, P4.2 and P4.3 */
+  __IO uint16_t rP4MAP45; /* Port mapping register, P4.4 and P4.5 */
+  __IO uint16_t rP4MAP67; /* Port mapping register, P4.6 and P4.7 */
+  __IO uint16_t rP5MAP01; /* Port mapping register, P5.0 and P5.1 */
+  __IO uint16_t rP5MAP23; /* Port mapping register, P5.2 and P5.3 */
+  __IO uint16_t rP5MAP45; /* Port mapping register, P5.4 and P5.5 */
+  __IO uint16_t rP5MAP67; /* Port mapping register, P5.6 and P5.7 */
+  __IO uint16_t rP6MAP01; /* Port mapping register, P6.0 and P6.1 */
+  __IO uint16_t rP6MAP23; /* Port mapping register, P6.2 and P6.3 */
+  __IO uint16_t rP6MAP45; /* Port mapping register, P6.4 and P6.5 */
+  __IO uint16_t rP6MAP67; /* Port mapping register, P6.6 and P6.7 */
+  __IO uint16_t rP7MAP01; /* Port mapping register, P7.0 and P7.1 */
+  __IO uint16_t rP7MAP23; /* Port mapping register, P7.2 and P7.3 */
+  __IO uint16_t rP7MAP45; /* Port mapping register, P7.4 and P7.5 */
+  __IO uint16_t rP7MAP67; /* Port mapping register, P7.6 and P7.7 */
+} PMAP_Type;
+
+
+//*****************************************************************************
+// PSS Registers
+//*****************************************************************************
+typedef struct {
+  union {    /* PSSKEY Register */
+    __IO uint32_t r;
+    struct { /* PSSKEY Bits */
+      __IO uint32_t bKEY                	:	16;  /* PSS control key */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rKEY;
+  union {    /* PSSCTL0 Register */
+    __IO uint32_t r;
+    struct { /* PSSCTL0 Bits */
+      __IO uint32_t bSVSMHOFF           	:	1;  /* SVSM high-side off */
+      __IO uint32_t bSVSMHLP            	:	1;  /* SVSM high-side low power normal performance mode */
+      __IO uint32_t bSVSMHS             	:	1;  /* Supply supervisor or monitor selection for the high-side */
+      __IO uint32_t bSVSMHTH            	:	3;  /* SVSM high-side reset voltage level */
+      __IO uint32_t bSVMHOE             	:	1;  /* SVSM high-side output enable */
+      __IO uint32_t bSVMHOUTPOLAL       	:	1;  /* SVMHOUT pin polarity active low */
+      __IO uint32_t bSVSLOFF            	:	1;  /* SVS low-side off */
+      __IO uint32_t bSVSLLP             	:	1;  /* SVS low-side low power normal performance mode */
+      __IO uint32_t bDCDC_FORCE         	:	1;  /* Disables automatic supply voltage detection */
+      __I  uint32_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint32_t bVCORETRAN          	:	2;  /* Controls VCORE Level Transition time */
+      __I  uint32_t bRESERVED1          	:	18;  /* Reserved */
+    } b;
+  } rCTL0;
+  union {    /* PSSCTL1 Register */
+    __IO uint32_t r;
+    struct { /* PSSCTL1 Bits */
+      __IO uint32_t bDOCMON             	:	1;  /* Turns the DOCM module on or off */
+      __IO uint32_t bDOCMSAMP           	:	1;  /* DOCM sample current */
+      __I  uint32_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint32_t bDOCMCM             	:	6;  /* Controls current mirrors in DOCM for conversion */
+      __I  uint32_t bRESERVED1          	:	23;  /* Reserved */
+    } b;
+  } rCTL1;
+  union {    /* PSSCTL2 Register */
+    __I uint32_t r;
+    struct { /* PSSCTL2 Bits */
+      __I  uint32_t bDOCMOUT            	:	6;  /* DOCM comparator output */
+      __I  uint32_t bRESERVED0          	:	26;  /* Reserved */
+    } b;
+  } rCTL2;
+  uint8_t  RESERVED0[36];
+  union {    /* PSSIE Register */
+    __IO uint32_t r;
+    struct { /* PSSIE Bits */
+      __I  uint32_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint32_t bSVSMHIE            	:	1;  /* High-side SVSM interrupt enable */
+      __I  uint32_t bRESERVED1          	:	30;  /* Reserved */
+    } b;
+  } rIE;
+  union {    /* PSSIFG Register */
+    __I uint32_t r;
+    struct { /* PSSIFG Bits */
+      __I  uint32_t bRESERVED0          	:	1;  /* Reserved */
+      __I  uint32_t bSVSMHIFG           	:	1;  /* High-side SVSM interrupt flag */
+      __I  uint32_t bRESERVED1          	:	30;  /* Reserved */
+    } b;
+  } rIFG;
+  union {    /* PSSCLRIFG Register */
+    __IO uint32_t r;
+    struct { /* PSSCLRIFG Bits */
+      __I  uint32_t bRESERVED0          	:	1;  /* Reserved */
+      __O  uint32_t bCLRSVSMHIFG        	:	1;  /* SVSMH clear interrupt flag */
+      __I  uint32_t bRESERVED1          	:	30;  /* Reserved */
+    } b;
+  } rCLRIFG;
+} PSS_Type;
+
+
+//*****************************************************************************
+// REF_A Registers
+//*****************************************************************************
+typedef struct {
+  union {    /* REFCTL0 Register */
+    __IO uint16_t r;
+    struct { /* REFCTL0 Bits */
+      __IO uint16_t bON                 	:	1;  /* Reference enable */
+      __IO uint16_t bOUT                	:	1;  /* Reference output buffer */
+      __IO uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bTCOFF              	:	1;  /* Temperature sensor disabled */
+      __IO uint16_t bVSEL               	:	2;  /* Reference voltage level select */
+      __IO uint16_t bGENOT              	:	1;  /* Reference generator one-time trigger */
+      __IO uint16_t bBGOT               	:	1;  /* Bandgap and bandgap buffer one-time trigger */
+      __I  uint16_t bGENACT             	:	1;  /* Reference generator active */
+      __I  uint16_t bBGACT              	:	1;  /* Reference bandgap active */
+      __I  uint16_t bGENBUSY            	:	1;  /* Reference generator busy */
+      __I  uint16_t bBGMODE             	:	1;  /* Bandgap mode */
+      __I  uint16_t bGENRDY             	:	1;  /* Variable reference voltage ready status */
+      __I  uint16_t bBGRDY              	:	1;  /* Buffered bandgap voltage ready status */
+      __I  uint16_t bRESERVED1          	:	2;  /* Reserved */
+    } b;
+  } rCTL0;
+} REF_A_Type;
+
+
+//*****************************************************************************
+// RSTCTL Registers
+//*****************************************************************************
+typedef struct {
+  union {    /* RSTCTL_RESET_REQ Register */
+    __IO uint32_t r;
+    struct { /* RSTCTL_RESET_REQ Bits */
+      __O  uint32_t bSOFT_REQ           	:	1;  /* Soft Reset request */
+      __O  uint32_t bHARD_REQ           	:	1;  /* Hard Reset request */
+      __I  uint32_t bRESERVED0          	:	6;  /* Reserved */
+      __O  uint32_t bRSTKEY             	:	8;  /* Write key to unlock reset request bits */
+      __I  uint32_t bRESERVED1          	:	16;  /* Reserved */
+    } b;
+  } rRESET_REQ;
+  union {    /* RSTCTL_HARDRESET_STAT Register */
+    __I uint32_t r;
+    struct { /* RSTCTL_HARDRESET_STAT Bits */
+      __I  uint32_t bSRC0               	:	1;  /* Indicates that SRC0 was the source of the Hard Reset */
+      __I  uint32_t bSRC1               	:	1;  /* Indicates that SRC1 was the source of the Hard Reset */
+      __I  uint32_t bSRC2               	:	1;  /* Indicates that SRC2 was the source of the Hard Reset */
+      __I  uint32_t bSRC3               	:	1;  /* Indicates that SRC3 was the source of the Hard Reset */
+      __I  uint32_t bSRC4               	:	1;  /* Indicates that SRC4 was the source of the Hard Reset */
+      __I  uint32_t bSRC5               	:	1;  /* Indicates that SRC5 was the source of the Hard Reset */
+      __I  uint32_t bSRC6               	:	1;  /* Indicates that SRC6 was the source of the Hard Reset */
+      __I  uint32_t bSRC7               	:	1;  /* Indicates that SRC7 was the source of the Hard Reset */
+      __I  uint32_t bSRC8               	:	1;  /* Indicates that SRC8 was the source of the Hard Reset */
+      __I  uint32_t bSRC9               	:	1;  /* Indicates that SRC9 was the source of the Hard Reset */
+      __I  uint32_t bSRC10              	:	1;  /* Indicates that SRC10 was the source of the Hard Reset */
+      __I  uint32_t bSRC11              	:	1;  /* Indicates that SRC11 was the source of the Hard Reset */
+      __I  uint32_t bSRC12              	:	1;  /* Indicates that SRC12 was the source of the Hard Reset */
+      __I  uint32_t bSRC13              	:	1;  /* Indicates that SRC13 was the source of the Hard Reset */
+      __I  uint32_t bSRC14              	:	1;  /* Indicates that SRC14 was the source of the Hard Reset */
+      __I  uint32_t bSRC15              	:	1;  /* Indicates that SRC15 was the source of the Hard Reset */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rHARDRESET_STAT;
+  union {    /* RSTCTL_HARDRESET_CLR Register */
+    __IO uint32_t r;
+    struct { /* RSTCTL_HARDRESET_CLR Bits */
+      __O  uint32_t bSRC0               	:	1;  /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+      __O  uint32_t bSRC1               	:	1;  /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+      __O  uint32_t bSRC2               	:	1;  /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+      __O  uint32_t bSRC3               	:	1;  /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+      __O  uint32_t bSRC4               	:	1;  /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+      __O  uint32_t bSRC5               	:	1;  /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+      __O  uint32_t bSRC6               	:	1;  /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+      __O  uint32_t bSRC7               	:	1;  /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+      __O  uint32_t bSRC8               	:	1;  /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT  */
+      __O  uint32_t bSRC9               	:	1;  /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+      __O  uint32_t bSRC10              	:	1;  /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+      __O  uint32_t bSRC11              	:	1;  /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+      __O  uint32_t bSRC12              	:	1;  /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+      __O  uint32_t bSRC13              	:	1;  /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+      __O  uint32_t bSRC14              	:	1;  /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+      __O  uint32_t bSRC15              	:	1;  /* Write 1 clears the corresponding bit in the RSTCTL_HRDRESETSTAT_REG */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rHARDRESET_CLR;
+  union {    /* RSTCTL_HARDRESET_SET Register */
+    __IO uint32_t r;
+    struct { /* RSTCTL_HARDRESET_SET Bits */
+      __O  uint32_t bSRC0               	:	1;  /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
+      __O  uint32_t bSRC1               	:	1;  /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
+      __O  uint32_t bSRC2               	:	1;  /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
+      __O  uint32_t bSRC3               	:	1;  /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
+      __O  uint32_t bSRC4               	:	1;  /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
+      __O  uint32_t bSRC5               	:	1;  /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
+      __O  uint32_t bSRC6               	:	1;  /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
+      __O  uint32_t bSRC7               	:	1;  /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
+      __O  uint32_t bSRC8               	:	1;  /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
+      __O  uint32_t bSRC9               	:	1;  /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
+      __O  uint32_t bSRC10              	:	1;  /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
+      __O  uint32_t bSRC11              	:	1;  /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
+      __O  uint32_t bSRC12              	:	1;  /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
+      __O  uint32_t bSRC13              	:	1;  /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
+      __O  uint32_t bSRC14              	:	1;  /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
+      __O  uint32_t bSRC15              	:	1;  /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rHARDRESET_SET;
+  union {    /* RSTCTL_SOFTRESET_STAT Register */
+    __I uint32_t r;
+    struct { /* RSTCTL_SOFTRESET_STAT Bits */
+      __I  uint32_t bSRC0               	:	1;  /* If 1, indicates that SRC0 was the source of the Soft Reset */
+      __I  uint32_t bSRC1               	:	1;  /* If 1, indicates that SRC1 was the source of the Soft Reset */
+      __I  uint32_t bSRC2               	:	1;  /* If 1, indicates that SRC2 was the source of the Soft Reset */
+      __I  uint32_t bSRC3               	:	1;  /* If 1, indicates that SRC3 was the source of the Soft Reset */
+      __I  uint32_t bSRC4               	:	1;  /* If 1, indicates that SRC4 was the source of the Soft Reset */
+      __I  uint32_t bSRC5               	:	1;  /* If 1, indicates that SRC5 was the source of the Soft Reset */
+      __I  uint32_t bSRC6               	:	1;  /* If 1, indicates that SRC6 was the source of the Soft Reset */
+      __I  uint32_t bSRC7               	:	1;  /* If 1, indicates that SRC7 was the source of the Soft Reset */
+      __I  uint32_t bSRC8               	:	1;  /* If 1, indicates that SRC8 was the source of the Soft Reset */
+      __I  uint32_t bSRC9               	:	1;  /* If 1, indicates that SRC9 was the source of the Soft Reset */
+      __I  uint32_t bSRC10              	:	1;  /* If 1, indicates that SRC10 was the source of the Soft Reset */
+      __I  uint32_t bSRC11              	:	1;  /* If 1, indicates that SRC11 was the source of the Soft Reset */
+      __I  uint32_t bSRC12              	:	1;  /* If 1, indicates that SRC12 was the source of the Soft Reset */
+      __I  uint32_t bSRC13              	:	1;  /* If 1, indicates that SRC13 was the source of the Soft Reset */
+      __I  uint32_t bSRC14              	:	1;  /* If 1, indicates that SRC14 was the source of the Soft Reset */
+      __I  uint32_t bSRC15              	:	1;  /* If 1, indicates that SRC15 was the source of the Soft Reset */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rSOFTRESET_STAT;
+  union {    /* RSTCTL_SOFTRESET_CLR Register */
+    __IO uint32_t r;
+    struct { /* RSTCTL_SOFTRESET_CLR Bits */
+      __O  uint32_t bSRC0               	:	1;  /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+      __O  uint32_t bSRC1               	:	1;  /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+      __O  uint32_t bSRC2               	:	1;  /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+      __O  uint32_t bSRC3               	:	1;  /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+      __O  uint32_t bSRC4               	:	1;  /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+      __O  uint32_t bSRC5               	:	1;  /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+      __O  uint32_t bSRC6               	:	1;  /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+      __O  uint32_t bSRC7               	:	1;  /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+      __O  uint32_t bSRC8               	:	1;  /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+      __O  uint32_t bSRC9               	:	1;  /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+      __O  uint32_t bSRC10              	:	1;  /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+      __O  uint32_t bSRC11              	:	1;  /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+      __O  uint32_t bSRC12              	:	1;  /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+      __O  uint32_t bSRC13              	:	1;  /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+      __O  uint32_t bSRC14              	:	1;  /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+      __O  uint32_t bSRC15              	:	1;  /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rSOFTRESET_CLR;
+  union {    /* RSTCTL_SOFTRESET_SET Register */
+    __IO uint32_t r;
+    struct { /* RSTCTL_SOFTRESET_SET Bits */
+      __O  uint32_t bSRC0               	:	1;  /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
+      __O  uint32_t bSRC1               	:	1;  /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
+      __O  uint32_t bSRC2               	:	1;  /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
+      __O  uint32_t bSRC3               	:	1;  /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
+      __O  uint32_t bSRC4               	:	1;  /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
+      __O  uint32_t bSRC5               	:	1;  /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
+      __O  uint32_t bSRC6               	:	1;  /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
+      __O  uint32_t bSRC7               	:	1;  /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
+      __O  uint32_t bSRC8               	:	1;  /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
+      __O  uint32_t bSRC9               	:	1;  /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
+      __O  uint32_t bSRC10              	:	1;  /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
+      __O  uint32_t bSRC11              	:	1;  /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
+      __O  uint32_t bSRC12              	:	1;  /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
+      __O  uint32_t bSRC13              	:	1;  /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
+      __O  uint32_t bSRC14              	:	1;  /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
+      __O  uint32_t bSRC15              	:	1;  /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rSOFTRESET_SET;
+  uint8_t  RESERVED0[228];
+  union {    /* RSTCTL_PSSRESET_STAT Register */
+    __I uint32_t r;
+    struct { /* RSTCTL_PSSRESET_STAT Bits */
+      __I  uint32_t bSVSL               	:	1;  /* Indicates if POR was caused by an SVSL trip condition in the PSS */
+      __I  uint32_t bSVSMH              	:	1;  /* Indicates if POR was caused by an SVSMH trip condition int the PSS */
+      __I  uint32_t bBGREF              	:	1;  /* Indicates if POR was caused by a BGREF not okay condition in the PSS */
+      __I  uint32_t bVCCDET             	:	1;  /* Indicates if POR was caused by a VCCDET trip condition in the PSS */
+      __I  uint32_t bRESERVED0          	:	28;  /* Reserved */
+    } b;
+  } rPSSRESET_STAT;
+  union {    /* RSTCTL_PSSRESET_CLR Register */
+    __IO uint32_t r;
+    struct { /* RSTCTL_PSSRESET_CLR Bits */
+      __O  uint32_t bCLR                	:	1;  /* Write 1 clears all PSS Reset Flags in the RSTCTL_PSSRESET_STAT */
+      __I  uint32_t bRESERVED0          	:	31;  /* Reserved */
+    } b;
+  } rPSSRESET_CLR;
+  union {    /* RSTCTL_PCMRESET_STAT Register */
+    __I uint32_t r;
+    struct { /* RSTCTL_PCMRESET_STAT Bits */
+      __I  uint32_t bLPM35              	:	1;  /* Indicates if POR was caused by PCM due to an exit from LPM3.5 */
+      __I  uint32_t bLPM45              	:	1;  /* Indicates if POR was caused by PCM due to an exit from LPM4.5 */
+      __I  uint32_t bRESERVED0          	:	30;  /* Reserved */
+    } b;
+  } rPCMRESET_STAT;
+  union {    /* RSTCTL_PCMRESET_CLR Register */
+    __IO uint32_t r;
+    struct { /* RSTCTL_PCMRESET_CLR Bits */
+      __O  uint32_t bCLR                	:	1;  /* Write 1 clears all PCM Reset Flags in the RSTCTL_PCMRESET_STAT */
+      __I  uint32_t bRESERVED0          	:	31;  /* Reserved */
+    } b;
+  } rPCMRESET_CLR;
+  union {    /* RSTCTL_PINRESET_STAT Register */
+    __I uint32_t r;
+    struct { /* RSTCTL_PINRESET_STAT Bits */
+      __I  uint32_t bRSTNMI             	:	1;  /* POR was caused by RSTn/NMI pin based reset event */
+      __I  uint32_t bRESERVED0          	:	31;  /* Reserved */
+    } b;
+  } rPINRESET_STAT;
+  union {    /* RSTCTL_PINRESET_CLR Register */
+    __IO uint32_t r;
+    struct { /* RSTCTL_PINRESET_CLR Bits */
+      __O  uint32_t bCLR                	:	1;  /* Write 1 clears the RSTn/NMI Pin Reset Flag in RSTCTL_PINRESET_STAT */
+      __I  uint32_t bRESERVED0          	:	31;  /* Reserved */
+    } b;
+  } rPINRESET_CLR;
+  union {    /* RSTCTL_REBOOTRESET_STAT Register */
+    __I uint32_t r;
+    struct { /* RSTCTL_REBOOTRESET_STAT Bits */
+      __I  uint32_t bREBOOT             	:	1;  /* Indicates if Reboot reset was caused by the SYSCTL module. */
+      __I  uint32_t bRESERVED0          	:	31;  /* Reserved */
+    } b;
+  } rREBOOTRESET_STAT;
+  union {    /* RSTCTL_REBOOTRESET_CLR Register */
+    __IO uint32_t r;
+    struct { /* RSTCTL_REBOOTRESET_CLR Bits */
+      __O  uint32_t bCLR                	:	1;  /* Write 1 clears the Reboot Reset Flag in RSTCTL_REBOOTRESET_STAT */
+      __I  uint32_t bRESERVED0          	:	31;  /* Reserved */
+    } b;
+  } rREBOOTRESET_CLR;
+} RSTCTL_Type;
+
+
+//*****************************************************************************
+// RTC_C Registers
+//*****************************************************************************
+typedef struct {
+  union {    /* RTCCTL0 Register */
+    __IO uint16_t r;
+    struct { /* RTCCTL0 Bits */
+      __IO uint16_t bRDYIFG             	:	1;  /* Real-time clock ready interrupt flag */
+      __IO uint16_t bAIFG               	:	1;  /* Real-time clock alarm interrupt flag */
+      __IO uint16_t bTEVIFG             	:	1;  /* Real-time clock time event interrupt flag */
+      __IO uint16_t bOFIFG              	:	1;  /* 32-kHz crystal oscillator fault interrupt flag */
+      __IO uint16_t bRDYIE              	:	1;  /* Real-time clock ready interrupt enable */
+      __IO uint16_t bAIE                	:	1;  /* Real-time clock alarm interrupt enable */
+      __IO uint16_t bTEVIE              	:	1;  /* Real-time clock time event interrupt enable */
+      __IO uint16_t bOFIE               	:	1;  /* 32-kHz crystal oscillator fault interrupt enable */
+      __IO uint16_t bKEY                	:	8;  /* Real-time clock key */
+    } b;
+  } rCTL0;
+  union {    /* RTCCTL13 Register */
+    __IO uint16_t r;
+    struct { /* RTCCTL13 Bits */
+      __IO uint16_t bTEV                	:	2;  /* Real-time clock time event */
+      __IO uint16_t bSSEL               	:	2;  /* Real-time clock source select */
+      __I  uint16_t bRDY                	:	1;  /* Real-time clock ready */
+      __I  uint16_t bMODE               	:	1;  /*  */
+      __IO uint16_t bHOLD               	:	1;  /* Real-time clock hold */
+      __IO uint16_t bBCD                	:	1;  /* Real-time clock BCD select */
+      __IO uint16_t bCALF               	:	2;  /* Real-time clock calibration frequency */
+      __I  uint16_t bRESERVED0          	:	6;  /* Reserved */
+    } b;
+  } rCTL13;
+  union {    /* RTCOCAL Register */
+    __IO uint16_t r;
+    struct { /* RTCOCAL Bits */
+      __IO uint16_t bOCAL               	:	8;  /* Real-time clock offset error calibration */
+      __I  uint16_t bRESERVED0          	:	7;  /* Reserved */
+      __IO uint16_t bOCALS              	:	1;  /* Real-time clock offset error calibration sign */
+    } b;
+  } rOCAL;
+  union {    /* RTCTCMP Register */
+    __IO uint16_t r;
+    struct { /* RTCTCMP Bits */
+      __IO uint16_t bTCMP               	:	8;  /* Real-time clock temperature compensation */
+      __I  uint16_t bRESERVED0          	:	5;  /* Reserved */
+      __I  uint16_t bTCOK               	:	1;  /* Real-time clock temperature compensation write OK */
+      __I  uint16_t bTCRDY              	:	1;  /* Real-time clock temperature compensation ready */
+      __IO uint16_t bTCMPS              	:	1;  /* Real-time clock temperature compensation sign */
+    } b;
+  } rTCMP;
+  union {    /* RTCPS0CTL Register */
+    __IO uint16_t r;
+    struct { /* RTCPS0CTL Bits */
+      __IO uint16_t bRT0PSIFG           	:	1;  /* Prescale timer 0 interrupt flag */
+      __IO uint16_t bRT0PSIE            	:	1;  /* Prescale timer 0 interrupt enable */
+      __IO uint16_t bRT0IP              	:	3;  /* Prescale timer 0 interrupt interval */
+      __I  uint16_t bRESERVED0          	:	11;  /* Reserved */
+    } b;
+  } rPS0CTL;
+  union {    /* RTCPS1CTL Register */
+    __IO uint16_t r;
+    struct { /* RTCPS1CTL Bits */
+      __IO uint16_t bRT1PSIFG           	:	1;  /* Prescale timer 1 interrupt flag */
+      __IO uint16_t bRT1PSIE            	:	1;  /* Prescale timer 1 interrupt enable */
+      __IO uint16_t bRT1IP              	:	3;  /* Prescale timer 1 interrupt interval */
+      __I  uint16_t bRESERVED0          	:	11;  /* Reserved */
+    } b;
+  } rPS1CTL;
+  union {    /* RTCPS Register */
+    __IO uint16_t r;
+    struct { /* RTCPS Bits */
+      __IO uint16_t bRT0PS              	:	8;  /* Prescale timer 0 counter value */
+      __IO uint16_t bRT1PS              	:	8;  /* Prescale timer 1 counter value */
+    } b;
+  } rPS;
+  __I uint16_t rIV; /* Real-Time Clock Interrupt Vector Register */
+  union {    /* RTCTIM0 Register */
+    __IO uint16_t r;
+    struct { /* RTCTIM0 Bits */
+      __IO uint16_t bSEC                	:	6;  /* Seconds (0 to 59) */
+      __I  uint16_t bRESERVED0          	:	2;  /* Reserved */
+      __IO uint16_t bMIN                	:	6;  /* Minutes (0 to 59) */
+      __I  uint16_t bRESERVED1          	:	2;  /* Reserved */
+    } b;
+    struct { /* RTCTIM0_BCD Bits */
+      __IO uint16_t bSEC_LD             	:	4;  /* Seconds ? low digit (0 to 9) */
+      __IO uint16_t bSEC_HD             	:	3;  /* Seconds ? high digit (0 to 5) */
+      __I  uint16_t bRESERVED           	:	1;  /* Reserved */
+      __IO uint16_t bMIN_LD             	:	4;  /* Minutes ? low digit (0 to 9) */
+      __IO uint16_t bMIN_HD             	:	3;  /* Minutes ? high digit (0 to 5) */
+    } a;
+  } rTIM0;
+  union {    /* RTCTIM1 Register */
+    __IO uint16_t r;
+    struct { /* RTCTIM1 Bits */
+      __IO uint16_t bHOUR               	:	5;  /* Hours (0 to 23) */
+      __I  uint16_t bRESERVED0          	:	3;  /* Reserved */
+      __IO uint16_t bDOW                	:	3;  /* Day of week (0 to 6) */
+      __I  uint16_t bRESERVED1          	:	5;  /* Reserved */
+    } b;
+    struct { /* RTCTIM1_BCD Bits */
+      __IO uint16_t bHOUR_LD            	:	4;  /* Hours ? low digit (0 to 9) */
+      __IO uint16_t bHOUR_HD            	:	2;  /* Hours ? high digit (0 to 2) */
+      __I  uint16_t bRESERVED           	:	2;  /* Reserved */
+      __IO uint16_t bDOW                	:	3;  /* Day of week (0 to 6) */
+    } a;
+  } rTIM1;
+  union {    /* RTCDATE Register */
+    __IO uint16_t r;
+    struct { /* RTCDATE Bits */
+      __IO uint16_t bDAY                	:	5;  /* Day of month (1 to 28, 29, 30, 31) */
+      __I  uint16_t bRESERVED0          	:	3;  /* Reserved */
+      __IO uint16_t bMON                	:	4;  /* Month (1 to 12) */
+      __I  uint16_t bRESERVED1          	:	4;  /* Reserved */
+    } b;
+    struct { /* RTCDATE_BCD Bits */
+      __IO uint16_t bDAY_LD             	:	4;  /* Day of month ? low digit (0 to 9) */
+      __IO uint16_t bDAY_HD             	:	2;  /* Day of month ? high digit (0 to 3) */
+      __I  uint16_t bRESERVED           	:	2;  /* Reserved */
+      __IO uint16_t bMON_LD             	:	4;  /* Month ? low digit (0 to 9) */
+      __IO uint16_t bMON_HD             	:	1;  /* Month ? high digit (0 or 1) */
+    } a;
+  } rDATE;
+  union {    /* RTCYEAR Register */
+    __IO uint16_t r;
+    struct { /* RTCYEAR Bits */
+      __IO uint16_t bYEAR_LB            	:	8;  /* Year ? low byte. Valid values for Year are 0 to 4095. */
+      __IO uint16_t bYEAR_HB            	:	4;  /* Year ? high byte. Valid values for Year are 0 to 4095. */
+      __I  uint16_t bRESERVED0          	:	4;  /* Reserved */
+    } b;
+    struct { /* RTCYEAR_BCD Bits */
+      __IO uint16_t bYEAR               	:	4;  /* Year ? lowest digit (0 to 9) */
+      __IO uint16_t bDEC                	:	4;  /* Decade (0 to 9) */
+      __IO uint16_t bCENT_LD            	:	4;  /* Century ? low digit (0 to 9) */
+      __IO uint16_t bCENT_HD            	:	3;  /* Century ? high digit (0 to 4) */
+      __I  uint16_t bRESERVED           	:	1;  /* Reserved */
+    } a;
+  } rYEAR;
+  union {    /* RTCAMINHR Register */
+    __IO uint16_t r;
+    struct { /* RTCAMINHR Bits */
+      __IO uint16_t bMIN                	:	6;  /* Minutes (0 to 59) */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bMINAE              	:	1;  /* Alarm enable */
+      __IO uint16_t bHOUR               	:	5;  /* Hours (0 to 23) */
+      __I  uint16_t bRESERVED1          	:	2;  /* Reserved */
+      __IO uint16_t bHOURAE             	:	1;  /* Alarm enable */
+    } b;
+    struct { /* RTCAMINHR_BCD Bits */
+      __IO uint16_t bMIN_LD             	:	4;  /* Minutes ? low digit (0 to 9) */
+      __IO uint16_t bMIN_HD             	:	3;  /* Minutes ? high digit (0 to 5) */
+      __IO uint16_t b                   	:	1;  /* Alarm enable */
+      __IO uint16_t bHOUR_LD            	:	4;  /* Hours ? low digit (0 to 9) */
+      __IO uint16_t bHOUR_HD            	:	2;  /* Hours ? high digit (0 to 2) */
+      __I  uint16_t bRESERVED           	:	1;  /* Reserved */
+      __IO uint16_t bHOURAE             	:	1;  /* Alarm enable */
+    } a;
+  } rAMINHR;
+  union {    /* RTCADOWDAY Register */
+    __IO uint16_t r;
+    struct { /* RTCADOWDAY Bits */
+      __IO uint16_t bDOW                	:	3;  /* Day of week (0 to 6) */
+      __I  uint16_t bRESERVED0          	:	4;  /* Reserved */
+      __IO uint16_t bDOWAE              	:	1;  /* Alarm enable */
+      __IO uint16_t bDAY                	:	5;  /* Day of month (1 to 28, 29, 30, 31) */
+      __I  uint16_t bRESERVED1          	:	2;  /* Reserved */
+      __IO uint16_t bDAYAE              	:	1;  /* Alarm enable */
+    } b;
+    struct { /* RTCADOWDAY_BCD Bits */
+      __IO uint16_t bDOW                	:	3;  /* Day of week (0 to 6) */
+      __I  uint16_t bRESERVED           	:	4;  /* Reserved */
+      __IO uint16_t bDOWAE              	:	1;  /* Alarm enable */
+      __IO uint16_t bDAY_LD             	:	4;  /* Day of month ? low digit (0 to 9) */
+      __IO uint16_t bDAY_HD             	:	2;  /* Day of month ? high digit (0 to 3) */
+      __IO uint16_t bDAYAE              	:	1;  /* Alarm enable */
+    } a;
+  } rADOWDAY;
+  __IO uint16_t rBIN2BCD; /* Binary-to-BCD Conversion Register */
+  __IO uint16_t rBCD2BIN; /* BCD-to-Binary Conversion Register */
+} RTC_C_Type;
+
+
+//*****************************************************************************
+// SYSCTL Registers
+//*****************************************************************************
+typedef struct {
+  union {    /* SYS_REBOOT_CTL Register */
+    __IO uint32_t r;
+    struct { /* SYS_REBOOT_CTL Bits */
+      __IO uint32_t bREBOOT             	:	1;  /* Write 1 initiates a Reboot of the device */
+      __I  uint32_t bRESERVED0          	:	7;  /* Reserved */
+      __O  uint32_t bWKEY               	:	8;  /* Key to enable writes to bit 0 */
+      __I  uint32_t bRESERVED1          	:	16;  /* Reserved */
+    } b;
+  } rREBOOT_CTL;
+  union {    /* SYS_NMI_CTLSTAT Register */
+    __IO uint32_t r;
+    struct { /* SYS_NMI_CTLSTAT Bits */
+      __IO uint32_t bCS_SRC             	:	1;  /* CS interrupt as a source of NMI */
+      __IO uint32_t bPSS_SRC            	:	1;  /* PSS interrupt as a source of NMI */
+      __IO uint32_t bPCM_SRC            	:	1;  /* PCM interrupt as a source of NMI */
+      __IO uint32_t bPIN_SRC            	:	1;  /*  */
+      __I  uint32_t bRESERVED0          	:	12;  /* Reserved */
+      __I  uint32_t bCS_FLG             	:	1;  /* CS interrupt was the source of NMI */
+      __I  uint32_t bPSS_FLG            	:	1;  /* PSS interrupt was the source of NMI */
+      __I  uint32_t bPCM_FLG            	:	1;  /* PCM interrupt was the source of NMI */
+      __IO uint32_t bPIN_FLG            	:	1;  /* RSTn/NMI pin was the source of NMI */
+      __I  uint32_t bRESERVED1          	:	12;  /* Reserved */
+    } b;
+  } rNMI_CTLSTAT;
+  union {    /* SYS_WDTRESET_CTL Register */
+    __IO uint32_t r;
+    struct { /* SYS_WDTRESET_CTL Bits */
+      __IO uint32_t bTIMEOUT            	:	1;  /* WDT timeout reset type */
+      __IO uint32_t bVIOLATION          	:	1;  /* WDT password violation reset type */
+      __I  uint32_t bRESERVED0          	:	30;  /* Reserved */
+    } b;
+  } rWDTRESET_CTL;
+  union {    /* SYS_PERIHALT_CTL Register */
+    __IO uint32_t r;
+    struct { /* SYS_PERIHALT_CTL Bits */
+      __IO uint32_t bT16_0              	:	1;  /* Freezes IP operation when CPU is halted */
+      __IO uint32_t bT16_1              	:	1;  /* Freezes IP operation when CPU is halted */
+      __IO uint32_t bT16_2              	:	1;  /* Freezes IP operation when CPU is halted */
+      __IO uint32_t bT16_3              	:	1;  /* Freezes IP operation when CPU is halted */
+      __IO uint32_t bT32_0              	:	1;  /* Freezes IP operation when CPU is halted */
+      __IO uint32_t bEUA0               	:	1;  /* Freezes IP operation when CPU is halted */
+      __IO uint32_t bEUA1               	:	1;  /* Freezes IP operation when CPU is halted */
+      __IO uint32_t bEUA2               	:	1;  /* Freezes IP operation when CPU is halted */
+      __IO uint32_t bEUA3               	:	1;  /* Freezes IP operation when CPU is halted */
+      __IO uint32_t bEUB0               	:	1;  /* Freezes IP operation when CPU is halted */
+      __IO uint32_t bEUB1               	:	1;  /* Freezes IP operation when CPU is halted */
+      __IO uint32_t bEUB2               	:	1;  /* Freezes IP operation when CPU is halted */
+      __IO uint32_t bEUB3               	:	1;  /* Freezes IP operation when CPU is halted */
+      __IO uint32_t bADC                	:	1;  /* Freezes IP operation when CPU is halted */
+      __IO uint32_t bWDT                	:	1;  /* Freezes IP operation when CPU is halted */
+      __IO uint32_t bDMA                	:	1;  /* Freezes IP operation when CPU is halted */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rPERIHALT_CTL;
+  __I uint32_t rSRAM_SIZE; /* SRAM Size Register */
+  union {    /* SYS_SRAM_BANKEN Register */
+    __IO uint32_t r;
+    struct { /* SYS_SRAM_BANKEN Bits */
+      __I  uint32_t bBNK0_EN            	:	1;  /* SRAM Bank0 enable */
+      __IO uint32_t bBNK1_EN            	:	1;  /* SRAM Bank1 enable */
+      __IO uint32_t bBNK2_EN            	:	1;  /* SRAM Bank1 enable */
+      __IO uint32_t bBNK3_EN            	:	1;  /* SRAM Bank1 enable */
+      __IO uint32_t bBNK4_EN            	:	1;  /* SRAM Bank1 enable */
+      __IO uint32_t bBNK5_EN            	:	1;  /* SRAM Bank1 enable */
+      __IO uint32_t bBNK6_EN            	:	1;  /* SRAM Bank1 enable */
+      __IO uint32_t bBNK7_EN            	:	1;  /* SRAM Bank1 enable */
+      __I  uint32_t bRESERVED0          	:	8;  /* Reserved */
+      __I  uint32_t bSRAM_RDY           	:	1;  /* SRAM ready */
+      __I  uint32_t bRESERVED1          	:	15;  /* Reserved */
+    } b;
+  } rSRAM_BANKEN;
+  union {    /* SYS_SRAM_BANKRET Register */
+    __IO uint32_t r;
+    struct { /* SYS_SRAM_BANKRET Bits */
+      __I  uint32_t bBNK0_RET           	:	1;  /* Bank0 retention */
+      __IO uint32_t bBNK1_RET           	:	1;  /* Bank1 retention */
+      __IO uint32_t bBNK2_RET           	:	1;  /* Bank2 retention */
+      __IO uint32_t bBNK3_RET           	:	1;  /* Bank3 retention */
+      __IO uint32_t bBNK4_RET           	:	1;  /* Bank4 retention */
+      __IO uint32_t bBNK5_RET           	:	1;  /* Bank5 retention */
+      __IO uint32_t bBNK6_RET           	:	1;  /* Bank6 retention */
+      __IO uint32_t bBNK7_RET           	:	1;  /* Bank7 retention */
+      __I  uint32_t bRESERVED0          	:	8;  /* Reserved */
+      __I  uint32_t bSRAM_RDY           	:	1;  /* SRAM ready */
+      __I  uint32_t bRESERVED1          	:	15;  /* Reserved */
+    } b;
+  } rSRAM_BANKRET;
+  uint8_t  RESERVED0[4];
+  __I uint32_t rFLASH_SIZE; /* Flash Size Register */
+  uint8_t  RESERVED1[12];
+  union {    /* SYS_DIO_GLTFLT_CTL Register */
+    __IO uint32_t r;
+    struct { /* SYS_DIO_GLTFLT_CTL Bits */
+      __IO uint32_t bGLTCH_EN           	:	1;  /* Glitch filter enable */
+      __I  uint32_t bRESERVED0          	:	31;  /* Reserved */
+    } b;
+  } rDIO_GLTFLT_CTL;
+  uint8_t  RESERVED2[12];
+  union {    /* SYS_SECDATA_UNLOCK Register */
+    __IO uint32_t r;
+    struct { /* SYS_SECDATA_UNLOCK Bits */
+      __IO uint32_t bUNLKEY             	:	16;  /* Unlock key */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rSECDATA_UNLOCK;
+  uint8_t  RESERVED3[4028];
+  union {    /* SYS_MASTER_UNLOCK Register */
+    __IO uint32_t r;
+    struct { /* SYS_MASTER_UNLOCK Bits */
+      __IO uint32_t bUNLKEY             	:	16;  /* Unlock Key */
+      __I  uint32_t bRESERVED0          	:	16;  /* Reserved */
+    } b;
+  } rMASTER_UNLOCK;
+  __IO uint32_t rBOOTOVER_REQ0; /* Boot Override Request Register */
+  __IO uint32_t rBOOTOVER_REQ1; /* Boot Override Request Register */
+  __IO uint32_t rBOOTOVER_ACK; /* Boot Override Acknowledge Register */
+  union {    /* SYS_RESET_REQ Register */
+    __IO uint32_t r;
+    struct { /* SYS_RESET_REQ Bits */
+      __O  uint32_t bPOR                	:	1;  /* Generate POR */
+      __O  uint32_t bREBOOT             	:	1;  /* Generate Reboot_Reset */
+      __I  uint32_t bRESERVED0          	:	6;  /* Reserved */
+      __O  uint32_t bWKEY               	:	8;  /* Write key */
+      __I  uint32_t bRESERVED1          	:	16;  /* Reserved */
+    } b;
+  } rRESET_REQ;
+  union {    /* SYS_RESET_STATOVER Register */
+    __IO uint32_t r;
+    struct { /* SYS_RESET_STATOVER Bits */
+      __I  uint32_t bSOFT               	:	1;  /* Indicates if SOFT Reset is active */
+      __I  uint32_t bHARD               	:	1;  /* Indicates if HARD Reset is active */
+      __I  uint32_t bREBOOT             	:	1;  /* Indicates if Reboot Reset is active */
+      __I  uint32_t bRESERVED0          	:	5;  /* Reserved */
+      __IO uint32_t bSOFT_OVER          	:	1;  /* SOFT_Reset overwrite request */
+      __IO uint32_t bHARD_OVER          	:	1;  /* HARD_Reset overwrite request */
+      __IO uint32_t bRBT_OVER           	:	1;  /* Reboot Reset overwrite request */
+      __I  uint32_t bRESERVED1          	:	21;  /* Reserved */
+    } b;
+  } rRESET_STATOVER;
+  uint8_t  RESERVED4[8];
+  union {    /* SYS_SYSTEM_STAT Register */
+    __I uint32_t r;
+    struct { /* SYS_SYSTEM_STAT Bits */
+      __I  uint32_t bRESERVED0          	:	3;  /* Reserved */
+      __I  uint32_t bDBG_SEC_ACT        	:	1;  /* Debug Security active */
+      __I  uint32_t bJTAG_SWD_LOCK_ACT  	:	1;  /* Indicates if JTAG and SWD Lock is active */
+      __I  uint32_t bIP_PROT_ACT        	:	1;  /* Indicates if IP protection is active */
+      __I  uint32_t bRESERVED1          	:	26;  /* Reserved */
+    } b;
+  } rSYSTEM_STAT;
+} SYSCTL_Type;
+
+
+//*****************************************************************************
+// TIMER32 Registers
+//*****************************************************************************
+typedef struct {
+  __IO uint32_t rLOAD1; /* Timer 1 Load Register */
+  __I uint32_t rVALUE1; /* Timer 1 Current Value Register */
+  union {    /* T32CONTROL1 Register */
+    __IO uint32_t r;
+    struct { /* T32CONTROL1 Bits */
+      __IO uint32_t bONESHOT            	:	1;  /* Selects one-shot or wrapping counter mode */
+      __IO uint32_t bSIZE               	:	1;  /* Selects 16 or 32 bit counter operation */
+      __IO uint32_t bPRESCALE           	:	2;  /* Prescale bits */
+      __I  uint32_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint32_t bIE                 	:	1;  /* Interrupt enable bit */
+      __IO uint32_t bMODE               	:	1;  /* Mode bit */
+      __IO uint32_t bENABLE             	:	1;  /*  */
+      __I  uint32_t bRESERVED1          	:	24;  /* Reserved */
+    } b;
+  } rCONTROL1;
+  __O uint32_t rINTCLR1; /* Timer 1 Interrupt Clear Register */
+  union {    /* T32RIS1 Register */
+    __I uint32_t r;
+    struct { /* T32RIS1 Bits */
+      __I  uint32_t bRAW_IFG            	:	1;  /* Raw interrupt status */
+      __I  uint32_t b                   	:	31;  /*  */
+    } b;
+  } rRIS1;
+  union {    /* T32MIS1 Register */
+    __I uint32_t r;
+    struct { /* T32MIS1 Bits */
+      __I  uint32_t b                   	:	1;  /* Enabled interrupt status */
+      __I  uint32_t bRESERVED0          	:	31;  /* Reserved */
+    } b;
+  } rMIS1;
+  __IO uint32_t rBGLOAD1; /* Timer 1 Background Load Register */
+  uint8_t  RESERVED0[4];
+  __IO uint32_t rLOAD2; /* Timer 2 Load Register */
+  __I uint32_t rVALUE2; /* Timer 2 Current Value Register */
+  union {    /* T32CONTROL2 Register */
+    __IO uint32_t r;
+    struct { /* T32CONTROL2 Bits */
+      __IO uint32_t bONESHOT            	:	1;  /* Selects one-shot or wrapping counter mode */
+      __IO uint32_t bSIZE               	:	1;  /* Selects 16 or 32 bit counter operation */
+      __IO uint32_t bPRESCALE           	:	2;  /* Prescale bits */
+      __I  uint32_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint32_t bIE                 	:	1;  /* Interrupt enable bit */
+      __IO uint32_t bMODE               	:	1;  /* Mode bit */
+      __IO uint32_t bENABLE             	:	1;  /*  */
+      __I  uint32_t bRESERVED1          	:	24;  /* Reserved */
+    } b;
+  } rCONTROL2;
+  __O uint32_t rINTCLR2; /* Timer 2 Interrupt Clear Register */
+  union {    /* T32RIS2 Register */
+    __I uint32_t r;
+    struct { /* T32RIS2 Bits */
+      __I  uint32_t bRAW_IFG            	:	1;  /* Raw interrupt status */
+      __I  uint32_t bRESERVED0          	:	31;  /* Reserved */
+    } b;
+  } rRIS2;
+  union {    /* T32MIS2 Register */
+    __I uint32_t r;
+    struct { /* T32MIS2 Bits */
+      __I  uint32_t bIFG                	:	1;  /* Enabled interrupt status */
+      __I  uint32_t bRESERVED0          	:	31;  /* Reserved */
+    } b;
+  } rMIS2;
+  __IO uint32_t rBGLOAD2; /* Timer 2 Background Load Register */
+  uint8_t  RESERVED1[3780];
+  union {    /* T32ITCR Register */
+    __IO uint32_t r;
+    struct { /* T32ITCR Bits */
+      __IO uint32_t bTEST_EN            	:	1;  /* Test mode */
+      __I  uint32_t b                   	:	31;  /*  */
+    } b;
+  } rITCR;
+  union {    /* T32ITOP Register */
+    __IO uint32_t r;
+    struct { /* T32ITOP Bits */
+      __O  uint32_t bTIMINT1_VAL        	:	1;  /* Value output on TIMINT1 */
+      __O  uint32_t bTIMINT2_VAL        	:	1;  /* Value output on TIMINT2 */
+      __I  uint32_t bRESERVED0          	:	30;  /* Reserved */
+    } b;
+  } rITOP;
+} TIMER32_Type;
+
+
+//*****************************************************************************
+// TIMER_A0 Registers
+//*****************************************************************************
+typedef struct {
+  union {    /* TA0CTL Register */
+    __IO uint16_t r;
+    struct { /* TA0CTL Bits */
+      __IO uint16_t bIFG                	:	1;  /* TimerA interrupt flag */
+      __IO uint16_t bIE                 	:	1;  /* TimerA interrupt enable */
+      __IO uint16_t bCLR                	:	1;  /* TimerA clear */
+      __IO uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bMC                 	:	2;  /* Mode control */
+      __IO uint16_t bID                 	:	2;  /* Input divider */
+      __IO uint16_t bSSEL               	:	2;  /* TimerA clock source select */
+      __IO uint16_t bRESERVED1          	:	6;  /* Reserved */
+    } b;
+  } rCTL;
+  union {    /* TA0CCTL0 Register */
+    __IO uint16_t r;
+    struct { /* TA0CCTL0 Bits */
+      __IO uint16_t bCCIFG              	:	1;  /* Capture/compare interrupt flag */
+      __IO uint16_t bCOV                	:	1;  /* Capture overflow */
+      __IO uint16_t bOUT                	:	1;  /* Output */
+      __I  uint16_t bCCI                	:	1;  /* Capture/compare input */
+      __IO uint16_t bCCIE               	:	1;  /* Capture/compare interrupt enable */
+      __IO uint16_t bOUTMOD             	:	3;  /* Output mode */
+      __IO uint16_t bCAP                	:	1;  /* Capture mode */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bSCCI               	:	1;  /* Synchronized capture/compare input */
+      __IO uint16_t bSCS                	:	1;  /* Synchronize capture source */
+      __IO uint16_t bCCIS               	:	2;  /* Capture/compare input select */
+      __IO uint16_t bCM                 	:	2;  /* Capture mode */
+    } b;
+  } rCCTL0;
+  union {    /* TA0CCTL1 Register */
+    __IO uint16_t r;
+    struct { /* TA0CCTL1 Bits */
+      __IO uint16_t bCCIFG              	:	1;  /* Capture/compare interrupt flag */
+      __IO uint16_t bCOV                	:	1;  /* Capture overflow */
+      __IO uint16_t bOUT                	:	1;  /* Output */
+      __I  uint16_t bCCI                	:	1;  /* Capture/compare input */
+      __IO uint16_t bCCIE               	:	1;  /* Capture/compare interrupt enable */
+      __IO uint16_t bOUTMOD             	:	3;  /* Output mode */
+      __IO uint16_t bCAP                	:	1;  /* Capture mode */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bSCCI               	:	1;  /* Synchronized capture/compare input */
+      __IO uint16_t bSCS                	:	1;  /* Synchronize capture source */
+      __IO uint16_t bCCIS               	:	2;  /* Capture/compare input select */
+      __IO uint16_t bCM                 	:	2;  /* Capture mode */
+    } b;
+  } rCCTL1;
+  union {    /* TA0CCTL2 Register */
+    __IO uint16_t r;
+    struct { /* TA0CCTL2 Bits */
+      __IO uint16_t bCCIFG              	:	1;  /* Capture/compare interrupt flag */
+      __IO uint16_t bCOV                	:	1;  /* Capture overflow */
+      __IO uint16_t bOUT                	:	1;  /* Output */
+      __I  uint16_t bCCI                	:	1;  /* Capture/compare input */
+      __IO uint16_t bCCIE               	:	1;  /* Capture/compare interrupt enable */
+      __IO uint16_t bOUTMOD             	:	3;  /* Output mode */
+      __IO uint16_t bCAP                	:	1;  /* Capture mode */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bSCCI               	:	1;  /* Synchronized capture/compare input */
+      __IO uint16_t bSCS                	:	1;  /* Synchronize capture source */
+      __IO uint16_t bCCIS               	:	2;  /* Capture/compare input select */
+      __IO uint16_t bCM                 	:	2;  /* Capture mode */
+    } b;
+  } rCCTL2;
+  union {    /* TA0CCTL3 Register */
+    __IO uint16_t r;
+    struct { /* TA0CCTL3 Bits */
+      __IO uint16_t bCCIFG              	:	1;  /* Capture/compare interrupt flag */
+      __IO uint16_t bCOV                	:	1;  /* Capture overflow */
+      __IO uint16_t bOUT                	:	1;  /* Output */
+      __I  uint16_t bCCI                	:	1;  /* Capture/compare input */
+      __IO uint16_t bCCIE               	:	1;  /* Capture/compare interrupt enable */
+      __IO uint16_t bOUTMOD             	:	3;  /* Output mode */
+      __IO uint16_t bCAP                	:	1;  /* Capture mode */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bSCCI               	:	1;  /* Synchronized capture/compare input */
+      __IO uint16_t bSCS                	:	1;  /* Synchronize capture source */
+      __IO uint16_t bCCIS               	:	2;  /* Capture/compare input select */
+      __IO uint16_t bCM                 	:	2;  /* Capture mode */
+    } b;
+  } rCCTL3;
+  union {    /* TA0CCTL4 Register */
+    __IO uint16_t r;
+    struct { /* TA0CCTL4 Bits */
+      __IO uint16_t bCCIFG              	:	1;  /* Capture/compare interrupt flag */
+      __IO uint16_t bCOV                	:	1;  /* Capture overflow */
+      __IO uint16_t bOUT                	:	1;  /* Output */
+      __I  uint16_t bCCI                	:	1;  /* Capture/compare input */
+      __IO uint16_t bCCIE               	:	1;  /* Capture/compare interrupt enable */
+      __IO uint16_t bOUTMOD             	:	3;  /* Output mode */
+      __IO uint16_t bCAP                	:	1;  /* Capture mode */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bSCCI               	:	1;  /* Synchronized capture/compare input */
+      __IO uint16_t bSCS                	:	1;  /* Synchronize capture source */
+      __IO uint16_t bCCIS               	:	2;  /* Capture/compare input select */
+      __IO uint16_t bCM                 	:	2;  /* Capture mode */
+    } b;
+  } rCCTL4;
+  union {    /* TA0CCTL5 Register */
+    __IO uint16_t r;
+    struct { /* TA0CCTL5 Bits */
+      __IO uint16_t bCCIFG              	:	1;  /* Capture/compare interrupt flag */
+      __IO uint16_t bCOV                	:	1;  /* Capture overflow */
+      __IO uint16_t bOUT                	:	1;  /* Output */
+      __I  uint16_t bCCI                	:	1;  /* Capture/compare input */
+      __IO uint16_t bCCIE               	:	1;  /* Capture/compare interrupt enable */
+      __IO uint16_t bOUTMOD             	:	3;  /* Output mode */
+      __IO uint16_t bCAP                	:	1;  /* Capture mode */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bSCCI               	:	1;  /* Synchronized capture/compare input */
+      __IO uint16_t bSCS                	:	1;  /* Synchronize capture source */
+      __IO uint16_t bCCIS               	:	2;  /* Capture/compare input select */
+      __IO uint16_t bCM                 	:	2;  /* Capture mode */
+    } b;
+  } rCCTL5;
+  union {    /* TA0CCTL6 Register */
+    __IO uint16_t r;
+    struct { /* TA0CCTL6 Bits */
+      __IO uint16_t bCCIFG              	:	1;  /* Capture/compare interrupt flag */
+      __IO uint16_t bCOV                	:	1;  /* Capture overflow */
+      __IO uint16_t bOUT                	:	1;  /* Output */
+      __I  uint16_t bCCI                	:	1;  /* Capture/compare input */
+      __IO uint16_t bCCIE               	:	1;  /* Capture/compare interrupt enable */
+      __IO uint16_t bOUTMOD             	:	3;  /* Output mode */
+      __IO uint16_t bCAP                	:	1;  /* Capture mode */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bSCCI               	:	1;  /* Synchronized capture/compare input */
+      __IO uint16_t bSCS                	:	1;  /* Synchronize capture source */
+      __IO uint16_t bCCIS               	:	2;  /* Capture/compare input select */
+      __IO uint16_t bCM                 	:	2;  /* Capture mode */
+    } b;
+  } rCCTL6;
+  __IO uint16_t rR; /* TimerA register */
+  __IO uint16_t rCCR0; /* Timer_A Capture/Compare  Register */
+  __IO uint16_t rCCR1; /* Timer_A Capture/Compare  Register */
+  __IO uint16_t rCCR2; /* Timer_A Capture/Compare  Register */
+  __IO uint16_t rCCR3; /* Timer_A Capture/Compare  Register */
+  __IO uint16_t rCCR4; /* Timer_A Capture/Compare  Register */
+  __IO uint16_t rCCR5; /* Timer_A Capture/Compare  Register */
+  __IO uint16_t rCCR6; /* Timer_A Capture/Compare  Register */
+  union {    /* TA0EX0 Register */
+    __IO uint16_t r;
+    struct { /* TA0EX0 Bits */
+      __IO uint16_t bIDEX               	:	3;  /* Input divider expansion */
+      __I  uint16_t bRESERVED0          	:	13;  /* Reserved */
+    } b;
+  } rEX0;
+  uint8_t  RESERVED0[12];
+  __I uint16_t rIV; /* TimerAx Interrupt Vector Register */
+} TIMER_A0_Type;
+
+
+//*****************************************************************************
+// TIMER_A1 Registers
+//*****************************************************************************
+typedef struct {
+  union {    /* TA1CTL Register */
+    __IO uint16_t r;
+    struct { /* TA1CTL Bits */
+      __IO uint16_t bIFG                	:	1;  /* TimerA interrupt flag */
+      __IO uint16_t bIE                 	:	1;  /* TimerA interrupt enable */
+      __IO uint16_t bCLR                	:	1;  /* TimerA clear */
+      __IO uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bMC                 	:	2;  /* Mode control */
+      __IO uint16_t bID                 	:	2;  /* Input divider */
+      __IO uint16_t bSSEL               	:	2;  /* TimerA clock source select */
+      __IO uint16_t bRESERVED1          	:	6;  /* Reserved */
+    } b;
+  } rCTL;
+  union {    /* TA1CCTL0 Register */
+    __IO uint16_t r;
+    struct { /* TA1CCTL0 Bits */
+      __IO uint16_t bCCIFG              	:	1;  /* Capture/compare interrupt flag */
+      __IO uint16_t bCOV                	:	1;  /* Capture overflow */
+      __IO uint16_t bOUT                	:	1;  /* Output */
+      __I  uint16_t bCCI                	:	1;  /* Capture/compare input */
+      __IO uint16_t bCCIE               	:	1;  /* Capture/compare interrupt enable */
+      __IO uint16_t bOUTMOD             	:	3;  /* Output mode */
+      __IO uint16_t bCAP                	:	1;  /* Capture mode */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bSCCI               	:	1;  /* Synchronized capture/compare input */
+      __IO uint16_t bSCS                	:	1;  /* Synchronize capture source */
+      __IO uint16_t bCCIS               	:	2;  /* Capture/compare input select */
+      __IO uint16_t bCM                 	:	2;  /* Capture mode */
+    } b;
+  } rCCTL0;
+  union {    /* TA1CCTL1 Register */
+    __IO uint16_t r;
+    struct { /* TA1CCTL1 Bits */
+      __IO uint16_t bCCIFG              	:	1;  /* Capture/compare interrupt flag */
+      __IO uint16_t bCOV                	:	1;  /* Capture overflow */
+      __IO uint16_t bOUT                	:	1;  /* Output */
+      __I  uint16_t bCCI                	:	1;  /* Capture/compare input */
+      __IO uint16_t bCCIE               	:	1;  /* Capture/compare interrupt enable */
+      __IO uint16_t bOUTMOD             	:	3;  /* Output mode */
+      __IO uint16_t bCAP                	:	1;  /* Capture mode */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bSCCI               	:	1;  /* Synchronized capture/compare input */
+      __IO uint16_t bSCS                	:	1;  /* Synchronize capture source */
+      __IO uint16_t bCCIS               	:	2;  /* Capture/compare input select */
+      __IO uint16_t bCM                 	:	2;  /* Capture mode */
+    } b;
+  } rCCTL1;
+  union {    /* TA1CCTL2 Register */
+    __IO uint16_t r;
+    struct { /* TA1CCTL2 Bits */
+      __IO uint16_t bCCIFG              	:	1;  /* Capture/compare interrupt flag */
+      __IO uint16_t bCOV                	:	1;  /* Capture overflow */
+      __IO uint16_t bOUT                	:	1;  /* Output */
+      __I  uint16_t bCCI                	:	1;  /* Capture/compare input */
+      __IO uint16_t bCCIE               	:	1;  /* Capture/compare interrupt enable */
+      __IO uint16_t bOUTMOD             	:	3;  /* Output mode */
+      __IO uint16_t bCAP                	:	1;  /* Capture mode */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bSCCI               	:	1;  /* Synchronized capture/compare input */
+      __IO uint16_t bSCS                	:	1;  /* Synchronize capture source */
+      __IO uint16_t bCCIS               	:	2;  /* Capture/compare input select */
+      __IO uint16_t bCM                 	:	2;  /* Capture mode */
+    } b;
+  } rCCTL2;
+  union {    /* TA1CCTL3 Register */
+    __IO uint16_t r;
+    struct { /* TA1CCTL3 Bits */
+      __IO uint16_t bCCIFG              	:	1;  /* Capture/compare interrupt flag */
+      __IO uint16_t bCOV                	:	1;  /* Capture overflow */
+      __IO uint16_t bOUT                	:	1;  /* Output */
+      __I  uint16_t bCCI                	:	1;  /* Capture/compare input */
+      __IO uint16_t bCCIE               	:	1;  /* Capture/compare interrupt enable */
+      __IO uint16_t bOUTMOD             	:	3;  /* Output mode */
+      __IO uint16_t bCAP                	:	1;  /* Capture mode */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bSCCI               	:	1;  /* Synchronized capture/compare input */
+      __IO uint16_t bSCS                	:	1;  /* Synchronize capture source */
+      __IO uint16_t bCCIS               	:	2;  /* Capture/compare input select */
+      __IO uint16_t bCM                 	:	2;  /* Capture mode */
+    } b;
+  } rCCTL3;
+  union {    /* TA1CCTL4 Register */
+    __IO uint16_t r;
+    struct { /* TA1CCTL4 Bits */
+      __IO uint16_t bCCIFG              	:	1;  /* Capture/compare interrupt flag */
+      __IO uint16_t bCOV                	:	1;  /* Capture overflow */
+      __IO uint16_t bOUT                	:	1;  /* Output */
+      __I  uint16_t bCCI                	:	1;  /* Capture/compare input */
+      __IO uint16_t bCCIE               	:	1;  /* Capture/compare interrupt enable */
+      __IO uint16_t bOUTMOD             	:	3;  /* Output mode */
+      __IO uint16_t bCAP                	:	1;  /* Capture mode */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bSCCI               	:	1;  /* Synchronized capture/compare input */
+      __IO uint16_t bSCS                	:	1;  /* Synchronize capture source */
+      __IO uint16_t bCCIS               	:	2;  /* Capture/compare input select */
+      __IO uint16_t bCM                 	:	2;  /* Capture mode */
+    } b;
+  } rCCTL4;
+  union {    /* TA1CCTL5 Register */
+    __IO uint16_t r;
+    struct { /* TA1CCTL5 Bits */
+      __IO uint16_t bCCIFG              	:	1;  /* Capture/compare interrupt flag */
+      __IO uint16_t bCOV                	:	1;  /* Capture overflow */
+      __IO uint16_t bOUT                	:	1;  /* Output */
+      __I  uint16_t bCCI                	:	1;  /* Capture/compare input */
+      __IO uint16_t bCCIE               	:	1;  /* Capture/compare interrupt enable */
+      __IO uint16_t bOUTMOD             	:	3;  /* Output mode */
+      __IO uint16_t bCAP                	:	1;  /* Capture mode */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bSCCI               	:	1;  /* Synchronized capture/compare input */
+      __IO uint16_t bSCS                	:	1;  /* Synchronize capture source */
+      __IO uint16_t bCCIS               	:	2;  /* Capture/compare input select */
+      __IO uint16_t bCM                 	:	2;  /* Capture mode */
+    } b;
+  } rCCTL5;
+  union {    /* TA1CCTL6 Register */
+    __IO uint16_t r;
+    struct { /* TA1CCTL6 Bits */
+      __IO uint16_t bCCIFG              	:	1;  /* Capture/compare interrupt flag */
+      __IO uint16_t bCOV                	:	1;  /* Capture overflow */
+      __IO uint16_t bOUT                	:	1;  /* Output */
+      __I  uint16_t bCCI                	:	1;  /* Capture/compare input */
+      __IO uint16_t bCCIE               	:	1;  /* Capture/compare interrupt enable */
+      __IO uint16_t bOUTMOD             	:	3;  /* Output mode */
+      __IO uint16_t bCAP                	:	1;  /* Capture mode */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bSCCI               	:	1;  /* Synchronized capture/compare input */
+      __IO uint16_t bSCS                	:	1;  /* Synchronize capture source */
+      __IO uint16_t bCCIS               	:	2;  /* Capture/compare input select */
+      __IO uint16_t bCM                 	:	2;  /* Capture mode */
+    } b;
+  } rCCTL6;
+  __IO uint16_t rR; /* TimerA register */
+  __IO uint16_t rCCR0; /* Timer_A Capture/Compare  Register */
+  __IO uint16_t rCCR1; /* Timer_A Capture/Compare  Register */
+  __IO uint16_t rCCR2; /* Timer_A Capture/Compare  Register */
+  __IO uint16_t rCCR3; /* Timer_A Capture/Compare  Register */
+  __IO uint16_t rCCR4; /* Timer_A Capture/Compare  Register */
+  __IO uint16_t rCCR5; /* Timer_A Capture/Compare  Register */
+  __IO uint16_t rCCR6; /* Timer_A Capture/Compare  Register */
+  union {    /* TA1EX0 Register */
+    __IO uint16_t r;
+    struct { /* TA1EX0 Bits */
+      __IO uint16_t bIDEX               	:	3;  /* Input divider expansion */
+      __I  uint16_t bRESERVED0          	:	13;  /* Reserved */
+    } b;
+  } rEX0;
+  uint8_t  RESERVED0[12];
+  __I uint16_t rIV; /* TimerAx Interrupt Vector Register */
+} TIMER_A1_Type;
+
+
+//*****************************************************************************
+// TIMER_A2 Registers
+//*****************************************************************************
+typedef struct {
+  union {    /* TA2CTL Register */
+    __IO uint16_t r;
+    struct { /* TA2CTL Bits */
+      __IO uint16_t bIFG                	:	1;  /* TimerA interrupt flag */
+      __IO uint16_t bIE                 	:	1;  /* TimerA interrupt enable */
+      __IO uint16_t bCLR                	:	1;  /* TimerA clear */
+      __IO uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bMC                 	:	2;  /* Mode control */
+      __IO uint16_t bID                 	:	2;  /* Input divider */
+      __IO uint16_t bSSEL               	:	2;  /* TimerA clock source select */
+      __IO uint16_t bRESERVED1          	:	6;  /* Reserved */
+    } b;
+  } rCTL;
+  union {    /* TA2CCTL0 Register */
+    __IO uint16_t r;
+    struct { /* TA2CCTL0 Bits */
+      __IO uint16_t bCCIFG              	:	1;  /* Capture/compare interrupt flag */
+      __IO uint16_t bCOV                	:	1;  /* Capture overflow */
+      __IO uint16_t bOUT                	:	1;  /* Output */
+      __I  uint16_t bCCI                	:	1;  /* Capture/compare input */
+      __IO uint16_t bCCIE               	:	1;  /* Capture/compare interrupt enable */
+      __IO uint16_t bOUTMOD             	:	3;  /* Output mode */
+      __IO uint16_t bCAP                	:	1;  /* Capture mode */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bSCCI               	:	1;  /* Synchronized capture/compare input */
+      __IO uint16_t bSCS                	:	1;  /* Synchronize capture source */
+      __IO uint16_t bCCIS               	:	2;  /* Capture/compare input select */
+      __IO uint16_t bCM                 	:	2;  /* Capture mode */
+    } b;
+  } rCCTL0;
+  union {    /* TA2CCTL1 Register */
+    __IO uint16_t r;
+    struct { /* TA2CCTL1 Bits */
+      __IO uint16_t bCCIFG              	:	1;  /* Capture/compare interrupt flag */
+      __IO uint16_t bCOV                	:	1;  /* Capture overflow */
+      __IO uint16_t bOUT                	:	1;  /* Output */
+      __I  uint16_t bCCI                	:	1;  /* Capture/compare input */
+      __IO uint16_t bCCIE               	:	1;  /* Capture/compare interrupt enable */
+      __IO uint16_t bOUTMOD             	:	3;  /* Output mode */
+      __IO uint16_t bCAP                	:	1;  /* Capture mode */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bSCCI               	:	1;  /* Synchronized capture/compare input */
+      __IO uint16_t bSCS                	:	1;  /* Synchronize capture source */
+      __IO uint16_t bCCIS               	:	2;  /* Capture/compare input select */
+      __IO uint16_t bCM                 	:	2;  /* Capture mode */
+    } b;
+  } rCCTL1;
+  union {    /* TA2CCTL2 Register */
+    __IO uint16_t r;
+    struct { /* TA2CCTL2 Bits */
+      __IO uint16_t bCCIFG              	:	1;  /* Capture/compare interrupt flag */
+      __IO uint16_t bCOV                	:	1;  /* Capture overflow */
+      __IO uint16_t bOUT                	:	1;  /* Output */
+      __I  uint16_t bCCI                	:	1;  /* Capture/compare input */
+      __IO uint16_t bCCIE               	:	1;  /* Capture/compare interrupt enable */
+      __IO uint16_t bOUTMOD             	:	3;  /* Output mode */
+      __IO uint16_t bCAP                	:	1;  /* Capture mode */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bSCCI               	:	1;  /* Synchronized capture/compare input */
+      __IO uint16_t bSCS                	:	1;  /* Synchronize capture source */
+      __IO uint16_t bCCIS               	:	2;  /* Capture/compare input select */
+      __IO uint16_t bCM                 	:	2;  /* Capture mode */
+    } b;
+  } rCCTL2;
+  union {    /* TA2CCTL3 Register */
+    __IO uint16_t r;
+    struct { /* TA2CCTL3 Bits */
+      __IO uint16_t bCCIFG              	:	1;  /* Capture/compare interrupt flag */
+      __IO uint16_t bCOV                	:	1;  /* Capture overflow */
+      __IO uint16_t bOUT                	:	1;  /* Output */
+      __I  uint16_t bCCI                	:	1;  /* Capture/compare input */
+      __IO uint16_t bCCIE               	:	1;  /* Capture/compare interrupt enable */
+      __IO uint16_t bOUTMOD             	:	3;  /* Output mode */
+      __IO uint16_t bCAP                	:	1;  /* Capture mode */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bSCCI               	:	1;  /* Synchronized capture/compare input */
+      __IO uint16_t bSCS                	:	1;  /* Synchronize capture source */
+      __IO uint16_t bCCIS               	:	2;  /* Capture/compare input select */
+      __IO uint16_t bCM                 	:	2;  /* Capture mode */
+    } b;
+  } rCCTL3;
+  union {    /* TA2CCTL4 Register */
+    __IO uint16_t r;
+    struct { /* TA2CCTL4 Bits */
+      __IO uint16_t bCCIFG              	:	1;  /* Capture/compare interrupt flag */
+      __IO uint16_t bCOV                	:	1;  /* Capture overflow */
+      __IO uint16_t bOUT                	:	1;  /* Output */
+      __I  uint16_t bCCI                	:	1;  /* Capture/compare input */
+      __IO uint16_t bCCIE               	:	1;  /* Capture/compare interrupt enable */
+      __IO uint16_t bOUTMOD             	:	3;  /* Output mode */
+      __IO uint16_t bCAP                	:	1;  /* Capture mode */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bSCCI               	:	1;  /* Synchronized capture/compare input */
+      __IO uint16_t bSCS                	:	1;  /* Synchronize capture source */
+      __IO uint16_t bCCIS               	:	2;  /* Capture/compare input select */
+      __IO uint16_t bCM                 	:	2;  /* Capture mode */
+    } b;
+  } rCCTL4;
+  union {    /* TA2CCTL5 Register */
+    __IO uint16_t r;
+    struct { /* TA2CCTL5 Bits */
+      __IO uint16_t bCCIFG              	:	1;  /* Capture/compare interrupt flag */
+      __IO uint16_t bCOV                	:	1;  /* Capture overflow */
+      __IO uint16_t bOUT                	:	1;  /* Output */
+      __I  uint16_t bCCI                	:	1;  /* Capture/compare input */
+      __IO uint16_t bCCIE               	:	1;  /* Capture/compare interrupt enable */
+      __IO uint16_t bOUTMOD             	:	3;  /* Output mode */
+      __IO uint16_t bCAP                	:	1;  /* Capture mode */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bSCCI               	:	1;  /* Synchronized capture/compare input */
+      __IO uint16_t bSCS                	:	1;  /* Synchronize capture source */
+      __IO uint16_t bCCIS               	:	2;  /* Capture/compare input select */
+      __IO uint16_t bCM                 	:	2;  /* Capture mode */
+    } b;
+  } rCCTL5;
+  union {    /* TA2CCTL6 Register */
+    __IO uint16_t r;
+    struct { /* TA2CCTL6 Bits */
+      __IO uint16_t bCCIFG              	:	1;  /* Capture/compare interrupt flag */
+      __IO uint16_t bCOV                	:	1;  /* Capture overflow */
+      __IO uint16_t bOUT                	:	1;  /* Output */
+      __I  uint16_t bCCI                	:	1;  /* Capture/compare input */
+      __IO uint16_t bCCIE               	:	1;  /* Capture/compare interrupt enable */
+      __IO uint16_t bOUTMOD             	:	3;  /* Output mode */
+      __IO uint16_t bCAP                	:	1;  /* Capture mode */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bSCCI               	:	1;  /* Synchronized capture/compare input */
+      __IO uint16_t bSCS                	:	1;  /* Synchronize capture source */
+      __IO uint16_t bCCIS               	:	2;  /* Capture/compare input select */
+      __IO uint16_t bCM                 	:	2;  /* Capture mode */
+    } b;
+  } rCCTL6;
+  __IO uint16_t rR; /* TimerA register */
+  __IO uint16_t rCCR0; /* Timer_A Capture/Compare  Register */
+  __IO uint16_t rCCR1; /* Timer_A Capture/Compare  Register */
+  __IO uint16_t rCCR2; /* Timer_A Capture/Compare  Register */
+  __IO uint16_t rCCR3; /* Timer_A Capture/Compare  Register */
+  __IO uint16_t rCCR4; /* Timer_A Capture/Compare  Register */
+  __IO uint16_t rCCR5; /* Timer_A Capture/Compare  Register */
+  __IO uint16_t rCCR6; /* Timer_A Capture/Compare  Register */
+  union {    /* TA2EX0 Register */
+    __IO uint16_t r;
+    struct { /* TA2EX0 Bits */
+      __IO uint16_t bIDEX               	:	3;  /* Input divider expansion */
+      __I  uint16_t bRESERVED0          	:	13;  /* Reserved */
+    } b;
+  } rEX0;
+  uint8_t  RESERVED0[12];
+  __I uint16_t rIV; /* TimerAx Interrupt Vector Register */
+} TIMER_A2_Type;
+
+
+//*****************************************************************************
+// TIMER_A3 Registers
+//*****************************************************************************
+typedef struct {
+  union {    /* TA3CTL Register */
+    __IO uint16_t r;
+    struct { /* TA3CTL Bits */
+      __IO uint16_t bIFG                	:	1;  /* TimerA interrupt flag */
+      __IO uint16_t bIE                 	:	1;  /* TimerA interrupt enable */
+      __IO uint16_t bCLR                	:	1;  /* TimerA clear */
+      __IO uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bMC                 	:	2;  /* Mode control */
+      __IO uint16_t bID                 	:	2;  /* Input divider */
+      __IO uint16_t bSSEL               	:	2;  /* TimerA clock source select */
+      __IO uint16_t bRESERVED1          	:	6;  /* Reserved */
+    } b;
+  } rCTL;
+  union {    /* TA3CCTL0 Register */
+    __IO uint16_t r;
+    struct { /* TA3CCTL0 Bits */
+      __IO uint16_t bCCIFG              	:	1;  /* Capture/compare interrupt flag */
+      __IO uint16_t bCOV                	:	1;  /* Capture overflow */
+      __IO uint16_t bOUT                	:	1;  /* Output */
+      __I  uint16_t bCCI                	:	1;  /* Capture/compare input */
+      __IO uint16_t bCCIE               	:	1;  /* Capture/compare interrupt enable */
+      __IO uint16_t bOUTMOD             	:	3;  /* Output mode */
+      __IO uint16_t bCAP                	:	1;  /* Capture mode */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bSCCI               	:	1;  /* Synchronized capture/compare input */
+      __IO uint16_t bSCS                	:	1;  /* Synchronize capture source */
+      __IO uint16_t bCCIS               	:	2;  /* Capture/compare input select */
+      __IO uint16_t bCM                 	:	2;  /* Capture mode */
+    } b;
+  } rCCTL0;
+  union {    /* TA3CCTL1 Register */
+    __IO uint16_t r;
+    struct { /* TA3CCTL1 Bits */
+      __IO uint16_t bCCIFG              	:	1;  /* Capture/compare interrupt flag */
+      __IO uint16_t bCOV                	:	1;  /* Capture overflow */
+      __IO uint16_t bOUT                	:	1;  /* Output */
+      __I  uint16_t bCCI                	:	1;  /* Capture/compare input */
+      __IO uint16_t bCCIE               	:	1;  /* Capture/compare interrupt enable */
+      __IO uint16_t bOUTMOD             	:	3;  /* Output mode */
+      __IO uint16_t bCAP                	:	1;  /* Capture mode */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bSCCI               	:	1;  /* Synchronized capture/compare input */
+      __IO uint16_t bSCS                	:	1;  /* Synchronize capture source */
+      __IO uint16_t bCCIS               	:	2;  /* Capture/compare input select */
+      __IO uint16_t bCM                 	:	2;  /* Capture mode */
+    } b;
+  } rCCTL1;
+  union {    /* TA3CCTL2 Register */
+    __IO uint16_t r;
+    struct { /* TA3CCTL2 Bits */
+      __IO uint16_t bCCIFG              	:	1;  /* Capture/compare interrupt flag */
+      __IO uint16_t bCOV                	:	1;  /* Capture overflow */
+      __IO uint16_t bOUT                	:	1;  /* Output */
+      __I  uint16_t bCCI                	:	1;  /* Capture/compare input */
+      __IO uint16_t bCCIE               	:	1;  /* Capture/compare interrupt enable */
+      __IO uint16_t bOUTMOD             	:	3;  /* Output mode */
+      __IO uint16_t bCAP                	:	1;  /* Capture mode */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bSCCI               	:	1;  /* Synchronized capture/compare input */
+      __IO uint16_t bSCS                	:	1;  /* Synchronize capture source */
+      __IO uint16_t bCCIS               	:	2;  /* Capture/compare input select */
+      __IO uint16_t bCM                 	:	2;  /* Capture mode */
+    } b;
+  } rCCTL2;
+  union {    /* TA3CCTL3 Register */
+    __IO uint16_t r;
+    struct { /* TA3CCTL3 Bits */
+      __IO uint16_t bCCIFG              	:	1;  /* Capture/compare interrupt flag */
+      __IO uint16_t bCOV                	:	1;  /* Capture overflow */
+      __IO uint16_t bOUT                	:	1;  /* Output */
+      __I  uint16_t bCCI                	:	1;  /* Capture/compare input */
+      __IO uint16_t bCCIE               	:	1;  /* Capture/compare interrupt enable */
+      __IO uint16_t bOUTMOD             	:	3;  /* Output mode */
+      __IO uint16_t bCAP                	:	1;  /* Capture mode */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bSCCI               	:	1;  /* Synchronized capture/compare input */
+      __IO uint16_t bSCS                	:	1;  /* Synchronize capture source */
+      __IO uint16_t bCCIS               	:	2;  /* Capture/compare input select */
+      __IO uint16_t bCM                 	:	2;  /* Capture mode */
+    } b;
+  } rCCTL3;
+  union {    /* TA3CCTL4 Register */
+    __IO uint16_t r;
+    struct { /* TA3CCTL4 Bits */
+      __IO uint16_t bCCIFG              	:	1;  /* Capture/compare interrupt flag */
+      __IO uint16_t bCOV                	:	1;  /* Capture overflow */
+      __IO uint16_t bOUT                	:	1;  /* Output */
+      __I  uint16_t bCCI                	:	1;  /* Capture/compare input */
+      __IO uint16_t bCCIE               	:	1;  /* Capture/compare interrupt enable */
+      __IO uint16_t bOUTMOD             	:	3;  /* Output mode */
+      __IO uint16_t bCAP                	:	1;  /* Capture mode */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bSCCI               	:	1;  /* Synchronized capture/compare input */
+      __IO uint16_t bSCS                	:	1;  /* Synchronize capture source */
+      __IO uint16_t bCCIS               	:	2;  /* Capture/compare input select */
+      __IO uint16_t bCM                 	:	2;  /* Capture mode */
+    } b;
+  } rCCTL4;
+  union {    /* TA3CCTL5 Register */
+    __IO uint16_t r;
+    struct { /* TA3CCTL5 Bits */
+      __IO uint16_t bCCIFG              	:	1;  /* Capture/compare interrupt flag */
+      __IO uint16_t bCOV                	:	1;  /* Capture overflow */
+      __IO uint16_t bOUT                	:	1;  /* Output */
+      __I  uint16_t bCCI                	:	1;  /* Capture/compare input */
+      __IO uint16_t bCCIE               	:	1;  /* Capture/compare interrupt enable */
+      __IO uint16_t bOUTMOD             	:	3;  /* Output mode */
+      __IO uint16_t bCAP                	:	1;  /* Capture mode */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bSCCI               	:	1;  /* Synchronized capture/compare input */
+      __IO uint16_t bSCS                	:	1;  /* Synchronize capture source */
+      __IO uint16_t bCCIS               	:	2;  /* Capture/compare input select */
+      __IO uint16_t bCM                 	:	2;  /* Capture mode */
+    } b;
+  } rCCTL5;
+  union {    /* TA3CCTL6 Register */
+    __IO uint16_t r;
+    struct { /* TA3CCTL6 Bits */
+      __IO uint16_t bCCIFG              	:	1;  /* Capture/compare interrupt flag */
+      __IO uint16_t bCOV                	:	1;  /* Capture overflow */
+      __IO uint16_t bOUT                	:	1;  /* Output */
+      __I  uint16_t bCCI                	:	1;  /* Capture/compare input */
+      __IO uint16_t bCCIE               	:	1;  /* Capture/compare interrupt enable */
+      __IO uint16_t bOUTMOD             	:	3;  /* Output mode */
+      __IO uint16_t bCAP                	:	1;  /* Capture mode */
+      __I  uint16_t bRESERVED0          	:	1;  /* Reserved */
+      __IO uint16_t bSCCI               	:	1;  /* Synchronized capture/compare input */
+      __IO uint16_t bSCS                	:	1;  /* Synchronize capture source */
+      __IO uint16_t bCCIS               	:	2;  /* Capture/compare input select */
+      __IO uint16_t bCM                 	:	2;  /* Capture mode */
+    } b;
+  } rCCTL6;
+  __IO uint16_t rR; /* TimerA register */
+  __IO uint16_t rCCR0; /* Timer_A Capture/Compare  Register */
+  __IO uint16_t rCCR1; /* Timer_A Capture/Compare  Register */
+  __IO uint16_t rCCR2; /* Timer_A Capture/Compare  Register */
+  __IO uint16_t rCCR3; /* Timer_A Capture/Compare  Register */
+  __IO uint16_t rCCR4; /* Timer_A Capture/Compare  Register */
+  __IO uint16_t rCCR5; /* Timer_A Capture/Compare  Register */
+  __IO uint16_t rCCR6; /* Timer_A Capture/Compare  Register */
+  union {    /* TA3EX0 Register */
+    __IO uint16_t r;
+    struct { /* TA3EX0 Bits */
+      __IO uint16_t bIDEX               	:	3;  /* Input divider expansion */
+      __I  uint16_t bRESERVED0          	:	13;  /* Reserved */
+    } b;
+  } rEX0;
+  uint8_t  RESERVED0[12];
+  __I uint16_t rIV; /* TimerAx Interrupt Vector Register */
+} TIMER_A3_Type;
+
+
+//*****************************************************************************
+// TLV Registers
+//*****************************************************************************
+typedef struct {
+  __IO uint32_t rTLV_CHECKSUM; /* TLV Checksum */
+  __IO uint32_t rDEVICE_INFO_TAG; /* Device Info Tag */
+  __IO uint32_t rDEVICE_INFO_LEN; /* Device Info Length */
+  __IO uint32_t rDEVICE_ID; /* Device ID */
+  __IO uint32_t rHWREV; /* HW Revision */
+  __IO uint32_t rBCREV; /* Boot Code Revision */
+  __IO uint32_t rROM_DRVLIB_REV; /* ROM Driver Library Revision */
+  __IO uint32_t rDIE_REC_TAG; /* Die Record Tag */
+  __IO uint32_t rDIE_REC_LEN; /* Die Record Length */
+  __IO uint32_t rDIE_XPOS; /* Die X-Position */
+  __IO uint32_t rDIE_YPOS; /* Die Y-Position */
+  __IO uint32_t rWAFER_ID; /* Wafer ID */
+  __IO uint32_t rLOT_ID; /* Lot ID */
+  __IO uint32_t rRESERVED0; /* Reserved */
+  __IO uint32_t rRESERVED1; /* Reserved */
+  __IO uint32_t rRESERVED2; /* Reserved */
+  __IO uint32_t rTEST_RESULTS; /* Test Results */
+  __IO uint32_t rCS_CAL_TAG; /* Clock System Calibration Tag */
+  __IO uint32_t rCS_CAL_LEN; /* Clock System Calibration Length */
+  __IO uint32_t rDCOIR_FCAL_RSEL04; /* DCO IR mode: Frequency calibration for DCORSEL 0 to 4 */
+  __IO uint32_t rDCOIR_FCAL_RSEL5; /* DCO IR mode: Frequency calibration for DCORSEL 5 */
+  __IO uint32_t rDCOIR_MAXPOSTUNE_RSEL04; /* DCO IR mode: Max Positive Tune for DCORSEL 0 to 4 */
+  __IO uint32_t rDCOIR_MAXNEGTUNE_RSEL04; /* DCO IR mode: Max Negative Tune for DCORSEL 0 to 4 */
+  __IO uint32_t rDCOIR_MAXPOSTUNE_RSEL5; /* DCO IR mode: Max Positive Tune for DCORSEL 5 */
+  __IO uint32_t rDCOIR_MAXNEGTUNE_RSEL5; /* DCO IR mode: Max Negative Tune for DCORSEL 5 */
+  __IO uint32_t rDCOIR_CONSTK_RSEL04; /* DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4 */
+  __IO uint32_t rDCOIR_CONSTK_RSEL5; /* DCO IR mode: DCO Constant (K) for DCORSEL 5 */
+  __IO uint32_t rDCOER_FCAL_RSEL04; /* DCO ER mode: Frequency calibration for DCORSEL 0 to 4 */
+  __IO uint32_t rDCOER_FCAL_RSEL5; /* DCO ER mode: Frequency calibration for DCORSEL 5 */
+  __IO uint32_t rDCOER_MAXPOSTUNE_RSEL04; /* DCO ER mode: Max Positive Tune for DCORSEL 0 to 4 */
+  __IO uint32_t rDCOER_MAXNEGTUNE_RSEL04; /* DCO ER mode: Max Negative Tune for DCORSEL 0 to 4 */
+  __IO uint32_t rDCOER_MAXPOSTUNE_RSEL5; /* DCO ER mode: Max Positive Tune for DCORSEL 5 */
+  __IO uint32_t rDCOER_MAXNEGTUNE_RSEL5; /* DCO ER mode: Max Negative Tune for DCORSEL 5 */
+  __IO uint32_t rDCOER_CONSTK_RSEL04; /* DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4 */
+  __IO uint32_t rDCOER_CONSTK_RSEL5; /* DCO ER mode: DCO Constant (K) for DCORSEL 5 */
+  __IO uint32_t rADC14_CAL_TAG; /* ADC14 Calibration Tag */
+  __IO uint32_t rADC14_CAL_LEN; /* ADC14 Calibration Length */
+  __IO uint32_t rADC14_GF_EXTREF30C; /* ADC14 Gain Factor for External Reference 30�C */
+  __IO uint32_t rADC14_GF_EXTREF85C; /* ADC14 Gain Factor for External Reference 85�C */
+  __IO uint32_t rADC14_GF_BUF_EXTREF30C; /* ADC14 Gain Factor for Buffered External Reference 30�C */
+  __IO uint32_t rADC14_GF_BUF_EXTREF85C; /* ADC14 Gain Factor for Buffered External Reference 85�C */
+  __IO uint32_t rADC14_GF_BUF1P2V_INTREF30C_REFOUT0; /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 30�C (REFOUT = 0) */
+  __IO uint32_t rADC14_GF_BUF1P2V_INTREF85C_REFOUT0; /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 85�C (REFOUT = 0) */
+  __IO uint32_t rADC14_GF_BUF1P2V_INTREF30C_REFOUT1; /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 30�C (REFOUT = 1) */
+  __IO uint32_t rADC14_GF_BUF1P2V_INTREF85C_REFOUT1; /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 85�C (REFOUT = 1) */
+  __IO uint32_t rADC14_GF_BUF1P45V_INTREF30C_REFOUT0; /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 30�C (REFOUT = 0) */
+  __IO uint32_t rADC14_GF_BUF1P45V_INTREF85C_REFOUT0; /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 85�C (REFOUT = 0) */
+  __IO uint32_t rADC14_GF_BUF1P45V_INTREF30C_REFOUT1; /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 30�C (REFOUT = 1) */
+  __IO uint32_t rADC14_GF_BUF1P45V_INTREF85C_REFOUT1; /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 85�C (REFOUT = 1) */
+  __IO uint32_t rADC14_GF_BUF2P5V_INTREF30C_REFOUT0; /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 30�C (REFOUT = 0) */
+  __IO uint32_t rADC14_GF_BUF2P5V_INTREF85C_REFOUT0; /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 85�C (REFOUT = 0) */
+  __IO uint32_t rADC14_GF_BUF2P5V_INTREF30C_REFOUT1; /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 30�C (REFOUT = 1) */
+  __IO uint32_t rADC14_GF_BUF2P5V_INTREF85C_REFOUT1; /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 85�C (REFOUT = 1) */
+  __IO uint32_t rADC14_OFFSET_VRSEL_1; /* ADC14 Offset (ADC14VRSEL = 1h) */
+  __IO uint32_t rADC14_OFFSET_VRSEL_E; /* ADC14 Offset (ADC14VRSEL = Eh) */
+  __IO uint32_t rADC14_REF1P2V_TS30C; /* ADC14 1.2V Reference Temp. Sensor 30�C */
+  __IO uint32_t rADC14_REF1P2V_TS85C; /* ADC14 1.2V Reference Temp. Sensor 85�C */
+  __IO uint32_t rADC14_REF1P45V_TS30C; /* ADC14 1.45V Reference Temp. Sensor 30�C */
+  __IO uint32_t rADC14_REF1P45V_TS85C; /* ADC14 1.45V Reference Temp. Sensor 85�C */
+  __IO uint32_t rADC14_REF2P5V_TS30C; /* ADC14 2.5V Reference Temp. Sensor 30�C */
+  __IO uint32_t rADC14_REF2P5V_TS85C; /* ADC14 2.5V Reference Temp. Sensor 85�C */
+  __IO uint32_t rREF_CAL_TAG; /* REF Calibration Tag */
+  __IO uint32_t rREF_CAL_LEN; /* REF Calibration Length */
+  __IO uint32_t rREF_1P2V; /* REF 1.2V Reference */
+  __IO uint32_t rREF_1P45V; /* REF 1.45V Reference */
+  __IO uint32_t rREF_2P5V; /* REF 2.5V Reference */
+  __IO uint32_t rRANDOM_NUM_TAG; /* 128-bit Random Number Tag */
+  __IO uint32_t rRANDOM_NUM_LEN; /* 128-bit Random Number Length */
+  __IO uint32_t rRANDOM_NUM_1; /* 32-bit Random Number 1 */
+  __IO uint32_t rRANDOM_NUM_2; /* 32-bit Random Number 2 */
+  __IO uint32_t rRANDOM_NUM_3; /* 32-bit Random Number 3 */
+  __IO uint32_t rRANDOM_NUM_4; /* 32-bit Random Number 4 */
+  __IO uint32_t rBSL_CFG_TAG; /* BSL Configuration Tag */
+  __IO uint32_t rBSL_CFG_LEN; /* BSL Configuration Length */
+  __IO uint32_t rBSL_PERIPHIF_SEL; /* BSL Peripheral Interface Selection */
+  __IO uint32_t rBSL_PORTIF_CFG_UART; /* BSL Port Interface Configuration for UART */
+  __IO uint32_t rBSL_PORTIF_CFG_SPI; /* BSL Port Interface Configuration for SPI */
+  __IO uint32_t rBSL_PORTIF_CFG_I2C; /* BSL Port Interface Configuration for I2C */
+  __IO uint32_t rTLV_END; /* TLV End Word */
+} TLV_Type;
+
+
+//*****************************************************************************
+// WDT_A Registers
+//*****************************************************************************
+typedef struct {
+  uint8_t  RESERVED0[12];
+  union {    /* WDTCTL Register */
+    __IO uint16_t r;
+    struct { /* WDTCTL Bits */
+      __IO uint16_t bIS                 	:	3;  /* Watchdog timer interval select */
+      __O  uint16_t bCNTCL              	:	1;  /* Watchdog timer counter clear */
+      __IO uint16_t bTMSEL              	:	1;  /* Watchdog timer mode select */
+      __IO uint16_t bSSEL               	:	2;  /* Watchdog timer clock source select */
+      __IO uint16_t bHOLD               	:	1;  /* Watchdog timer hold */
+      __IO uint16_t bPW                 	:	8;  /* Watchdog timer password */
+    } b;
+  } rCTL;
+} WDT_A_Type;
+
+
+//*****************************************************************************
+// Peripheral register control bits
+//*****************************************************************************
+
+//*****************************************************************************
+// ADC14 Bits
+//*****************************************************************************
+/* ADC14CTL0[ADC14SC] Bits */
+#define ADC14SC_OFS                                        ( 0)                  /* ADC14SC Offset */
+#define ADC14SC                                            (0x00000001)          /* ADC14 start conversion */
+/* ADC14CTL0[ADC14ENC] Bits */
+#define ADC14ENC_OFS                                       ( 1)                  /* ADC14ENC Offset */
+#define ADC14ENC                                           (0x00000002)          /* ADC14 enable conversion */
+/* ADC14CTL0[ADC14ON] Bits */
+#define ADC14ON_OFS                                        ( 4)                  /* ADC14ON Offset */
+#define ADC14ON                                            (0x00000010)          /* ADC14 on */
+/* ADC14CTL0[ADC14MSC] Bits */
+#define ADC14MSC_OFS                                       ( 7)                  /* ADC14MSC Offset */
+#define ADC14MSC                                           (0x00000080)          /* ADC14 multiple sample and conversion */
+/* ADC14CTL0[ADC14SHT0] Bits */
+#define ADC14SHT0_OFS                                      ( 8)                  /* ADC14SHT0 Offset */
+#define ADC14SHT0_M                                        (0x00000f00)          /* ADC14 sample-and-hold time */
+#define ADC14SHT00                                         (0x00000100)          /* ADC14 sample-and-hold time */
+#define ADC14SHT01                                         (0x00000200)          /* ADC14 sample-and-hold time */
+#define ADC14SHT02                                         (0x00000400)          /* ADC14 sample-and-hold time */
+#define ADC14SHT03                                         (0x00000800)          /* ADC14 sample-and-hold time */
+#define ADC14SHT0_0                                        (0x00000000)          /* 4 */
+#define ADC14SHT0_1                                        (0x00000100)          /* 8 */
+#define ADC14SHT0_2                                        (0x00000200)          /* 16 */
+#define ADC14SHT0_3                                        (0x00000300)          /* 32 */
+#define ADC14SHT0_4                                        (0x00000400)          /* 64 */
+#define ADC14SHT0_5                                        (0x00000500)          /* 96 */
+#define ADC14SHT0_6                                        (0x00000600)          /* 128 */
+#define ADC14SHT0_7                                        (0x00000700)          /* 192 */
+#define ADC14SHT0__4                                       (0x00000000)          /* 4 */
+#define ADC14SHT0__8                                       (0x00000100)          /* 8 */
+#define ADC14SHT0__16                                      (0x00000200)          /* 16 */
+#define ADC14SHT0__32                                      (0x00000300)          /* 32 */
+#define ADC14SHT0__64                                      (0x00000400)          /* 64 */
+#define ADC14SHT0__96                                      (0x00000500)          /* 96 */
+#define ADC14SHT0__128                                     (0x00000600)          /* 128 */
+#define ADC14SHT0__192                                     (0x00000700)          /* 192 */
+/* ADC14CTL0[ADC14SHT1] Bits */
+#define ADC14SHT1_OFS                                      (12)                  /* ADC14SHT1 Offset */
+#define ADC14SHT1_M                                        (0x0000f000)          /* ADC14 sample-and-hold time */
+#define ADC14SHT10                                         (0x00001000)          /* ADC14 sample-and-hold time */
+#define ADC14SHT11                                         (0x00002000)          /* ADC14 sample-and-hold time */
+#define ADC14SHT12                                         (0x00004000)          /* ADC14 sample-and-hold time */
+#define ADC14SHT13                                         (0x00008000)          /* ADC14 sample-and-hold time */
+#define ADC14SHT1_0                                        (0x00000000)          /* 4 */
+#define ADC14SHT1_1                                        (0x00001000)          /* 8 */
+#define ADC14SHT1_2                                        (0x00002000)          /* 16 */
+#define ADC14SHT1_3                                        (0x00003000)          /* 32 */
+#define ADC14SHT1_4                                        (0x00004000)          /* 64 */
+#define ADC14SHT1_5                                        (0x00005000)          /* 96 */
+#define ADC14SHT1_6                                        (0x00006000)          /* 128 */
+#define ADC14SHT1_7                                        (0x00007000)          /* 192 */
+#define ADC14SHT1__4                                       (0x00000000)          /* 4 */
+#define ADC14SHT1__8                                       (0x00001000)          /* 8 */
+#define ADC14SHT1__16                                      (0x00002000)          /* 16 */
+#define ADC14SHT1__32                                      (0x00003000)          /* 32 */
+#define ADC14SHT1__64                                      (0x00004000)          /* 64 */
+#define ADC14SHT1__96                                      (0x00005000)          /* 96 */
+#define ADC14SHT1__128                                     (0x00006000)          /* 128 */
+#define ADC14SHT1__192                                     (0x00007000)          /* 192 */
+/* ADC14CTL0[ADC14BUSY] Bits */
+#define ADC14BUSY_OFS                                      (16)                  /* ADC14BUSY Offset */
+#define ADC14BUSY                                          (0x00010000)          /* ADC14 busy */
+/* ADC14CTL0[ADC14CONSEQ] Bits */
+#define ADC14CONSEQ_OFS                                    (17)                  /* ADC14CONSEQ Offset */
+#define ADC14CONSEQ_M                                      (0x00060000)          /* ADC14 conversion sequence mode select */
+#define ADC14CONSEQ0                                       (0x00020000)          /* ADC14 conversion sequence mode select */
+#define ADC14CONSEQ1                                       (0x00040000)          /* ADC14 conversion sequence mode select */
+#define ADC14CONSEQ_0                                      (0x00000000)          /* Single-channel, single-conversion */
+#define ADC14CONSEQ_1                                      (0x00020000)          /* Sequence-of-channels */
+#define ADC14CONSEQ_2                                      (0x00040000)          /* Repeat-single-channel */
+#define ADC14CONSEQ_3                                      (0x00060000)          /* Repeat-sequence-of-channels */
+/* ADC14CTL0[ADC14SSEL] Bits */
+#define ADC14SSEL_OFS                                      (19)                  /* ADC14SSEL Offset */
+#define ADC14SSEL_M                                        (0x00380000)          /* ADC14 clock source select */
+#define ADC14SSEL0                                         (0x00080000)          /* ADC14 clock source select */
+#define ADC14SSEL1                                         (0x00100000)          /* ADC14 clock source select */
+#define ADC14SSEL2                                         (0x00200000)          /* ADC14 clock source select */
+#define ADC14SSEL_0                                        (0x00000000)          /* MODCLK */
+#define ADC14SSEL_1                                        (0x00080000)          /* SYSCLK */
+#define ADC14SSEL_2                                        (0x00100000)          /* ACLK */
+#define ADC14SSEL_3                                        (0x00180000)          /* MCLK */
+#define ADC14SSEL_4                                        (0x00200000)          /* SMCLK */
+#define ADC14SSEL_5                                        (0x00280000)          /* HSMCLK */
+#define ADC14SSEL__MODCLK                                  (0x00000000)          /* MODCLK */
+#define ADC14SSEL__SYSCLK                                  (0x00080000)          /* SYSCLK */
+#define ADC14SSEL__ACLK                                    (0x00100000)          /* ACLK */
+#define ADC14SSEL__MCLK                                    (0x00180000)          /* MCLK */
+#define ADC14SSEL__SMCLK                                   (0x00200000)          /* SMCLK */
+#define ADC14SSEL__HSMCLK                                  (0x00280000)          /* HSMCLK */
+/* ADC14CTL0[ADC14DIV] Bits */
+#define ADC14DIV_OFS                                       (22)                  /* ADC14DIV Offset */
+#define ADC14DIV_M                                         (0x01c00000)          /* ADC14 clock divider */
+#define ADC14DIV0                                          (0x00400000)          /* ADC14 clock divider */
+#define ADC14DIV1                                          (0x00800000)          /* ADC14 clock divider */
+#define ADC14DIV2                                          (0x01000000)          /* ADC14 clock divider */
+#define ADC14DIV_0                                         (0x00000000)          /* /1 */
+#define ADC14DIV_1                                         (0x00400000)          /* /2 */
+#define ADC14DIV_2                                         (0x00800000)          /* /3 */
+#define ADC14DIV_3                                         (0x00c00000)          /* /4 */
+#define ADC14DIV_4                                         (0x01000000)          /* /5 */
+#define ADC14DIV_5                                         (0x01400000)          /* /6 */
+#define ADC14DIV_6                                         (0x01800000)          /* /7 */
+#define ADC14DIV_7                                         (0x01c00000)          /* /8 */
+#define ADC14DIV__1                                        (0x00000000)          /* /1 */
+#define ADC14DIV__2                                        (0x00400000)          /* /2 */
+#define ADC14DIV__3                                        (0x00800000)          /* /3 */
+#define ADC14DIV__4                                        (0x00c00000)          /* /4 */
+#define ADC14DIV__5                                        (0x01000000)          /* /5 */
+#define ADC14DIV__6                                        (0x01400000)          /* /6 */
+#define ADC14DIV__7                                        (0x01800000)          /* /7 */
+#define ADC14DIV__8                                        (0x01c00000)          /* /8 */
+/* ADC14CTL0[ADC14ISSH] Bits */
+#define ADC14ISSH_OFS                                      (25)                  /* ADC14ISSH Offset */
+#define ADC14ISSH                                          (0x02000000)          /* ADC14 invert signal sample-and-hold */
+/* ADC14CTL0[ADC14SHP] Bits */
+#define ADC14SHP_OFS                                       (26)                  /* ADC14SHP Offset */
+#define ADC14SHP                                           (0x04000000)          /* ADC14 sample-and-hold pulse-mode select */
+/* ADC14CTL0[ADC14SHS] Bits */
+#define ADC14SHS_OFS                                       (27)                  /* ADC14SHS Offset */
+#define ADC14SHS_M                                         (0x38000000)          /* ADC14 sample-and-hold source select */
+#define ADC14SHS0                                          (0x08000000)          /* ADC14 sample-and-hold source select */
+#define ADC14SHS1                                          (0x10000000)          /* ADC14 sample-and-hold source select */
+#define ADC14SHS2                                          (0x20000000)          /* ADC14 sample-and-hold source select */
+#define ADC14SHS_0                                         (0x00000000)          /* ADC14SC bit */
+#define ADC14SHS_1                                         (0x08000000)          /* See device-specific data sheet for source */
+#define ADC14SHS_2                                         (0x10000000)          /* See device-specific data sheet for source */
+#define ADC14SHS_3                                         (0x18000000)          /* See device-specific data sheet for source */
+#define ADC14SHS_4                                         (0x20000000)          /* See device-specific data sheet for source */
+#define ADC14SHS_5                                         (0x28000000)          /* See device-specific data sheet for source */
+#define ADC14SHS_6                                         (0x30000000)          /* See device-specific data sheet for source */
+#define ADC14SHS_7                                         (0x38000000)          /* See device-specific data sheet for source */
+/* ADC14CTL0[ADC14PDIV] Bits */
+#define ADC14PDIV_OFS                                      (30)                  /* ADC14PDIV Offset */
+#define ADC14PDIV_M                                        (0xc0000000)          /* ADC14 predivider */
+#define ADC14PDIV0                                         (0x40000000)          /* ADC14 predivider */
+#define ADC14PDIV1                                         (0x80000000)          /* ADC14 predivider */
+#define ADC14PDIV_0                                        (0x00000000)          /* Predivide by 1 */
+#define ADC14PDIV_1                                        (0x40000000)          /* Predivide by 4 */
+#define ADC14PDIV_2                                        (0x80000000)          /* Predivide by 32 */
+#define ADC14PDIV_3                                        (0xc0000000)          /* Predivide by 64 */
+#define ADC14PDIV__1                                       (0x00000000)          /* Predivide by 1 */
+#define ADC14PDIV__4                                       (0x40000000)          /* Predivide by 4 */
+#define ADC14PDIV__32                                      (0x80000000)          /* Predivide by 32 */
+#define ADC14PDIV__64                                      (0xc0000000)          /* Predivide by 64 */
+/* ADC14CTL1[ADC14PWRMD] Bits */
+#define ADC14PWRMD_OFS                                     ( 0)                  /* ADC14PWRMD Offset */
+#define ADC14PWRMD_M                                       (0x00000003)          /* ADC14 power modes */
+#define ADC14PWRMD0                                        (0x00000001)          /* ADC14 power modes */
+#define ADC14PWRMD1                                        (0x00000002)          /* ADC14 power modes */
+#define ADC14PWRMD_0                                       (0x00000000)          /* Regular power mode for use with any resolution setting. Sample rate can be up to 1 Msps. */
+#define ADC14PWRMD_2                                       (0x00000002)          /* Low-power mode for 12-bit, 10-bit, and 8-bit resolution settings. Sample rate must not exceed 200 ksps. */
+/* ADC14CTL1[ADC14REFBURST] Bits */
+#define ADC14REFBURST_OFS                                  ( 2)                  /* ADC14REFBURST Offset */
+#define ADC14REFBURST                                      (0x00000004)          /* ADC14 reference buffer burst */
+/* ADC14CTL1[ADC14DF] Bits */
+#define ADC14DF_OFS                                        ( 3)                  /* ADC14DF Offset */
+#define ADC14DF                                            (0x00000008)          /* ADC14 data read-back format */
+/* ADC14CTL1[ADC14RES] Bits */
+#define ADC14RES_OFS                                       ( 4)                  /* ADC14RES Offset */
+#define ADC14RES_M                                         (0x00000030)          /* ADC14 resolution */
+#define ADC14RES0                                          (0x00000010)          /* ADC14 resolution */
+#define ADC14RES1                                          (0x00000020)          /* ADC14 resolution */
+#define ADC14RES_0                                         (0x00000000)          /* 8 bit (9 clock cycle conversion time) */
+#define ADC14RES_1                                         (0x00000010)          /* 10 bit (11 clock cycle conversion time) */
+#define ADC14RES_2                                         (0x00000020)          /* 12 bit (14 clock cycle conversion time) */
+#define ADC14RES_3                                         (0x00000030)          /* 14 bit (16 clock cycle conversion time) */
+#define ADC14RES__8BIT                                     (0x00000000)          /* 8 bit (9 clock cycle conversion time) */
+#define ADC14RES__10BIT                                    (0x00000010)          /* 10 bit (11 clock cycle conversion time) */
+#define ADC14RES__12BIT                                    (0x00000020)          /* 12 bit (14 clock cycle conversion time) */
+#define ADC14RES__14BIT                                    (0x00000030)          /* 14 bit (16 clock cycle conversion time) */
+/* ADC14CTL1[ADC14CSTARTADD] Bits */
+#define ADC14CSTARTADD_OFS                                 (16)                  /* ADC14CSTARTADD Offset */
+#define ADC14CSTARTADD_M                                   (0x001f0000)          /* ADC14 conversion start address */
+/* ADC14CTL1[ADC14BATMAP] Bits */
+#define ADC14BATMAP_OFS                                    (22)                  /* ADC14BATMAP Offset */
+#define ADC14BATMAP                                        (0x00400000)          /* Controls 1/2 AVCC ADC input channel selection */
+/* ADC14CTL1[ADC14TCMAP] Bits */
+#define ADC14TCMAP_OFS                                     (23)                  /* ADC14TCMAP Offset */
+#define ADC14TCMAP                                         (0x00800000)          /* Controls temperature sensor ADC input channel selection */
+/* ADC14CTL1[ADC14CH0MAP] Bits */
+#define ADC14CH0MAP_OFS                                    (24)                  /* ADC14CH0MAP Offset */
+#define ADC14CH0MAP                                        (0x01000000)          /* Controls internal channel 0 selection to ADC input channel MAX-2 */
+/* ADC14CTL1[ADC14CH1MAP] Bits */
+#define ADC14CH1MAP_OFS                                    (25)                  /* ADC14CH1MAP Offset */
+#define ADC14CH1MAP                                        (0x02000000)          /* Controls internal channel 1 selection to ADC input channel MAX-3 */
+/* ADC14CTL1[ADC14CH2MAP] Bits */
+#define ADC14CH2MAP_OFS                                    (26)                  /* ADC14CH2MAP Offset */
+#define ADC14CH2MAP                                        (0x04000000)          /* Controls internal channel 2 selection to ADC input channel MAX-4 */
+/* ADC14CTL1[ADC14CH3MAP] Bits */
+#define ADC14CH3MAP_OFS                                    (27)                  /* ADC14CH3MAP Offset */
+#define ADC14CH3MAP                                        (0x08000000)          /* Controls internal channel 3 selection to ADC input channel MAX-5 */
+/* ADC14LO0[ADC14LO0] Bits */
+#define ADC14LO0_OFS                                       ( 0)                  /* ADC14LO0 Offset */
+#define ADC14LO0_M                                         (0x0000ffff)          /* Low threshold 0 */
+/* ADC14HI0[ADC14HI0] Bits */
+#define ADC14HI0_OFS                                       ( 0)                  /* ADC14HI0 Offset */
+#define ADC14HI0_M                                         (0x0000ffff)          /* High threshold 0 */
+/* ADC14LO1[ADC14LO1] Bits */
+#define ADC14LO1_OFS                                       ( 0)                  /* ADC14LO1 Offset */
+#define ADC14LO1_M                                         (0x0000ffff)          /* Low threshold 1 */
+/* ADC14HI1[ADC14HI1] Bits */
+#define ADC14HI1_OFS                                       ( 0)                  /* ADC14HI1 Offset */
+#define ADC14HI1_M                                         (0x0000ffff)          /* High threshold 1 */
+/* ADC14MCTL[ADC14INCH] Bits */
+#define ADC14INCH_OFS                                      ( 0)                  /* ADC14INCH Offset */
+#define ADC14INCH_M                                        (0x0000001f)          /* Input channel select */
+#define ADC14INCH0                                         (0x00000001)          /* Input channel select */
+#define ADC14INCH1                                         (0x00000002)          /* Input channel select */
+#define ADC14INCH2                                         (0x00000004)          /* Input channel select */
+#define ADC14INCH3                                         (0x00000008)          /* Input channel select */
+#define ADC14INCH4                                         (0x00000010)          /* Input channel select */
+#define ADC14INCH_0                                        (0x00000000)          /* If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */
+#define ADC14INCH_1                                        (0x00000001)          /* If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */
+#define ADC14INCH_2                                        (0x00000002)          /* If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */
+#define ADC14INCH_3                                        (0x00000003)          /* If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */
+#define ADC14INCH_4                                        (0x00000004)          /* If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */
+#define ADC14INCH_5                                        (0x00000005)          /* If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */
+#define ADC14INCH_6                                        (0x00000006)          /* If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */
+#define ADC14INCH_7                                        (0x00000007)          /* If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */
+#define ADC14INCH_8                                        (0x00000008)          /* If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */
+#define ADC14INCH_9                                        (0x00000009)          /* If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */
+#define ADC14INCH_10                                       (0x0000000a)          /* If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */
+#define ADC14INCH_11                                       (0x0000000b)          /* If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */
+#define ADC14INCH_12                                       (0x0000000c)          /* If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */
+#define ADC14INCH_13                                       (0x0000000d)          /* If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */
+#define ADC14INCH_14                                       (0x0000000e)          /* If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */
+#define ADC14INCH_15                                       (0x0000000f)          /* If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */
+#define ADC14INCH_16                                       (0x00000010)          /* If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */
+#define ADC14INCH_17                                       (0x00000011)          /* If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */
+#define ADC14INCH_18                                       (0x00000012)          /* If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */
+#define ADC14INCH_19                                       (0x00000013)          /* If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */
+#define ADC14INCH_20                                       (0x00000014)          /* If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */
+#define ADC14INCH_21                                       (0x00000015)          /* If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */
+#define ADC14INCH_22                                       (0x00000016)          /* If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */
+#define ADC14INCH_23                                       (0x00000017)          /* If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */
+#define ADC14INCH_24                                       (0x00000018)          /* If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */
+#define ADC14INCH_25                                       (0x00000019)          /* If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */
+#define ADC14INCH_26                                       (0x0000001a)          /* If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */
+#define ADC14INCH_27                                       (0x0000001b)          /* If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */
+#define ADC14INCH_28                                       (0x0000001c)          /* If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */
+#define ADC14INCH_29                                       (0x0000001d)          /* If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */
+#define ADC14INCH_30                                       (0x0000001e)          /* If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */
+#define ADC14INCH_31                                       (0x0000001f)          /* If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */
+/* ADC14MCTL[ADC14EOS] Bits */
+#define ADC14EOS_OFS                                       ( 7)                  /* ADC14EOS Offset */
+#define ADC14EOS                                           (0x00000080)          /* End of sequence */
+/* ADC14MCTL[ADC14VRSEL] Bits */
+#define ADC14VRSEL_OFS                                     ( 8)                  /* ADC14VRSEL Offset */
+#define ADC14VRSEL_M                                       (0x00000f00)          /* Selects combinations of V(R+) and V(R-) sources */
+#define ADC14VRSEL0                                        (0x00000100)          /* Selects combinations of V(R+) and V(R-) sources */
+#define ADC14VRSEL1                                        (0x00000200)          /* Selects combinations of V(R+) and V(R-) sources */
+#define ADC14VRSEL2                                        (0x00000400)          /* Selects combinations of V(R+) and V(R-) sources */
+#define ADC14VRSEL3                                        (0x00000800)          /* Selects combinations of V(R+) and V(R-) sources */
+#define ADC14VRSEL_0                                       (0x00000000)          /* V(R+) = AVCC, V(R-) = AVSS */
+#define ADC14VRSEL_1                                       (0x00000100)          /* V(R+) = VREF buffered, V(R-) = AVSS */
+#define ADC14VRSEL_14                                      (0x00000e00)          /* V(R+) = VeREF+, V(R-) = VeREF- */
+#define ADC14VRSEL_15                                      (0x00000f00)          /* V(R+) = VeREF+ buffered, V(R-) = VeREF */
+/* ADC14MCTL[ADC14DIF] Bits */
+#define ADC14DIF_OFS                                       (13)                  /* ADC14DIF Offset */
+#define ADC14DIF                                           (0x00002000)          /* Differential mode */
+/* ADC14MCTL[ADC14WINC] Bits */
+#define ADC14WINC_OFS                                      (14)                  /* ADC14WINC Offset */
+#define ADC14WINC                                          (0x00004000)          /* Comparator window enable */
+/* ADC14MCTL[ADC14WINCTH] Bits */
+#define ADC14WINCTH_OFS                                    (15)                  /* ADC14WINCTH Offset */
+#define ADC14WINCTH                                        (0x00008000)          /* Window comparator threshold register selection */
+/* ADC14MEM[CONVERSION_RESULTS] Bits */
+#define CONVERSION_RESULTS_OFS                             ( 0)                  /* Conversion_Results Offset */
+#define CONVERSION_RESULTS_M                               (0x0000ffff)          /* Conversion Result */
+/* ADC14IER0[ADC14IE0] Bits */
+#define ADC14IE0_OFS                                       ( 0)                  /* ADC14IE0 Offset */
+#define ADC14IE0                                           (0x00000001)          /* Interrupt enable */
+/* ADC14IER0[ADC14IE1] Bits */
+#define ADC14IE1_OFS                                       ( 1)                  /* ADC14IE1 Offset */
+#define ADC14IE1                                           (0x00000002)          /* Interrupt enable */
+/* ADC14IER0[ADC14IE2] Bits */
+#define ADC14IE2_OFS                                       ( 2)                  /* ADC14IE2 Offset */
+#define ADC14IE2                                           (0x00000004)          /* Interrupt enable */
+/* ADC14IER0[ADC14IE3] Bits */
+#define ADC14IE3_OFS                                       ( 3)                  /* ADC14IE3 Offset */
+#define ADC14IE3                                           (0x00000008)          /* Interrupt enable */
+/* ADC14IER0[ADC14IE4] Bits */
+#define ADC14IE4_OFS                                       ( 4)                  /* ADC14IE4 Offset */
+#define ADC14IE4                                           (0x00000010)          /* Interrupt enable */
+/* ADC14IER0[ADC14IE5] Bits */
+#define ADC14IE5_OFS                                       ( 5)                  /* ADC14IE5 Offset */
+#define ADC14IE5                                           (0x00000020)          /* Interrupt enable */
+/* ADC14IER0[ADC14IE6] Bits */
+#define ADC14IE6_OFS                                       ( 6)                  /* ADC14IE6 Offset */
+#define ADC14IE6                                           (0x00000040)          /* Interrupt enable */
+/* ADC14IER0[ADC14IE7] Bits */
+#define ADC14IE7_OFS                                       ( 7)                  /* ADC14IE7 Offset */
+#define ADC14IE7                                           (0x00000080)          /* Interrupt enable */
+/* ADC14IER0[ADC14IE8] Bits */
+#define ADC14IE8_OFS                                       ( 8)                  /* ADC14IE8 Offset */
+#define ADC14IE8                                           (0x00000100)          /* Interrupt enable */
+/* ADC14IER0[ADC14IE9] Bits */
+#define ADC14IE9_OFS                                       ( 9)                  /* ADC14IE9 Offset */
+#define ADC14IE9                                           (0x00000200)          /* Interrupt enable */
+/* ADC14IER0[ADC14IE10] Bits */
+#define ADC14IE10_OFS                                      (10)                  /* ADC14IE10 Offset */
+#define ADC14IE10                                          (0x00000400)          /* Interrupt enable */
+/* ADC14IER0[ADC14IE11] Bits */
+#define ADC14IE11_OFS                                      (11)                  /* ADC14IE11 Offset */
+#define ADC14IE11                                          (0x00000800)          /* Interrupt enable */
+/* ADC14IER0[ADC14IE12] Bits */
+#define ADC14IE12_OFS                                      (12)                  /* ADC14IE12 Offset */
+#define ADC14IE12                                          (0x00001000)          /* Interrupt enable */
+/* ADC14IER0[ADC14IE13] Bits */
+#define ADC14IE13_OFS                                      (13)                  /* ADC14IE13 Offset */
+#define ADC14IE13                                          (0x00002000)          /* Interrupt enable */
+/* ADC14IER0[ADC14IE14] Bits */
+#define ADC14IE14_OFS                                      (14)                  /* ADC14IE14 Offset */
+#define ADC14IE14                                          (0x00004000)          /* Interrupt enable */
+/* ADC14IER0[ADC14IE15] Bits */
+#define ADC14IE15_OFS                                      (15)                  /* ADC14IE15 Offset */
+#define ADC14IE15                                          (0x00008000)          /* Interrupt enable */
+/* ADC14IER0[ADC14IE16] Bits */
+#define ADC14IE16_OFS                                      (16)                  /* ADC14IE16 Offset */
+#define ADC14IE16                                          (0x00010000)          /* Interrupt enable */
+/* ADC14IER0[ADC14IE17] Bits */
+#define ADC14IE17_OFS                                      (17)                  /* ADC14IE17 Offset */
+#define ADC14IE17                                          (0x00020000)          /* Interrupt enable */
+/* ADC14IER0[ADC14IE19] Bits */
+#define ADC14IE19_OFS                                      (19)                  /* ADC14IE19 Offset */
+#define ADC14IE19                                          (0x00080000)          /* Interrupt enable */
+/* ADC14IER0[ADC14IE18] Bits */
+#define ADC14IE18_OFS                                      (18)                  /* ADC14IE18 Offset */
+#define ADC14IE18                                          (0x00040000)          /* Interrupt enable */
+/* ADC14IER0[ADC14IE20] Bits */
+#define ADC14IE20_OFS                                      (20)                  /* ADC14IE20 Offset */
+#define ADC14IE20                                          (0x00100000)          /* Interrupt enable */
+/* ADC14IER0[ADC14IE21] Bits */
+#define ADC14IE21_OFS                                      (21)                  /* ADC14IE21 Offset */
+#define ADC14IE21                                          (0x00200000)          /* Interrupt enable */
+/* ADC14IER0[ADC14IE22] Bits */
+#define ADC14IE22_OFS                                      (22)                  /* ADC14IE22 Offset */
+#define ADC14IE22                                          (0x00400000)          /* Interrupt enable */
+/* ADC14IER0[ADC14IE23] Bits */
+#define ADC14IE23_OFS                                      (23)                  /* ADC14IE23 Offset */
+#define ADC14IE23                                          (0x00800000)          /* Interrupt enable */
+/* ADC14IER0[ADC14IE24] Bits */
+#define ADC14IE24_OFS                                      (24)                  /* ADC14IE24 Offset */
+#define ADC14IE24                                          (0x01000000)          /* Interrupt enable */
+/* ADC14IER0[ADC14IE25] Bits */
+#define ADC14IE25_OFS                                      (25)                  /* ADC14IE25 Offset */
+#define ADC14IE25                                          (0x02000000)          /* Interrupt enable */
+/* ADC14IER0[ADC14IE26] Bits */
+#define ADC14IE26_OFS                                      (26)                  /* ADC14IE26 Offset */
+#define ADC14IE26                                          (0x04000000)          /* Interrupt enable */
+/* ADC14IER0[ADC14IE27] Bits */
+#define ADC14IE27_OFS                                      (27)                  /* ADC14IE27 Offset */
+#define ADC14IE27                                          (0x08000000)          /* Interrupt enable */
+/* ADC14IER0[ADC14IE28] Bits */
+#define ADC14IE28_OFS                                      (28)                  /* ADC14IE28 Offset */
+#define ADC14IE28                                          (0x10000000)          /* Interrupt enable */
+/* ADC14IER0[ADC14IE29] Bits */
+#define ADC14IE29_OFS                                      (29)                  /* ADC14IE29 Offset */
+#define ADC14IE29                                          (0x20000000)          /* Interrupt enable */
+/* ADC14IER0[ADC14IE30] Bits */
+#define ADC14IE30_OFS                                      (30)                  /* ADC14IE30 Offset */
+#define ADC14IE30                                          (0x40000000)          /* Interrupt enable */
+/* ADC14IER0[ADC14IE31] Bits */
+#define ADC14IE31_OFS                                      (31)                  /* ADC14IE31 Offset */
+#define ADC14IE31                                          (0x80000000)          /* Interrupt enable */
+/* ADC14IER1[ADC14INIE] Bits */
+#define ADC14INIE_OFS                                      ( 1)                  /* ADC14INIE Offset */
+#define ADC14INIE                                          (0x00000002)          /* Interrupt enable for ADC14MEMx within comparator window */
+/* ADC14IER1[ADC14LOIE] Bits */
+#define ADC14LOIE_OFS                                      ( 2)                  /* ADC14LOIE Offset */
+#define ADC14LOIE                                          (0x00000004)          /* Interrupt enable for ADC14MEMx below comparator window */
+/* ADC14IER1[ADC14HIIE] Bits */
+#define ADC14HIIE_OFS                                      ( 3)                  /* ADC14HIIE Offset */
+#define ADC14HIIE                                          (0x00000008)          /* Interrupt enable for ADC14MEMx above comparator window */
+/* ADC14IER1[ADC14OVIE] Bits */
+#define ADC14OVIE_OFS                                      ( 4)                  /* ADC14OVIE Offset */
+#define ADC14OVIE                                          (0x00000010)          /* ADC14MEMx overflow-interrupt enable */
+/* ADC14IER1[ADC14TOVIE] Bits */
+#define ADC14TOVIE_OFS                                     ( 5)                  /* ADC14TOVIE Offset */
+#define ADC14TOVIE                                         (0x00000020)          /* ADC14 conversion-time-overflow interrupt enable */
+/* ADC14IER1[ADC14RDYIE] Bits */
+#define ADC14RDYIE_OFS                                     ( 6)                  /* ADC14RDYIE Offset */
+#define ADC14RDYIE                                         (0x00000040)          /* ADC14 local buffered reference ready interrupt enable */
+/* ADC14IFGR0[ADC14IFG0] Bits */
+#define ADC14IFG0_OFS                                      ( 0)                  /* ADC14IFG0 Offset */
+#define ADC14IFG0                                          (0x00000001)          /* ADC14MEM0 interrupt flag */
+/* ADC14IFGR0[ADC14IFG1] Bits */
+#define ADC14IFG1_OFS                                      ( 1)                  /* ADC14IFG1 Offset */
+#define ADC14IFG1                                          (0x00000002)          /* ADC14MEM1 interrupt flag */
+/* ADC14IFGR0[ADC14IFG2] Bits */
+#define ADC14IFG2_OFS                                      ( 2)                  /* ADC14IFG2 Offset */
+#define ADC14IFG2                                          (0x00000004)          /* ADC14MEM2 interrupt flag */
+/* ADC14IFGR0[ADC14IFG3] Bits */
+#define ADC14IFG3_OFS                                      ( 3)                  /* ADC14IFG3 Offset */
+#define ADC14IFG3                                          (0x00000008)          /* ADC14MEM3 interrupt flag */
+/* ADC14IFGR0[ADC14IFG4] Bits */
+#define ADC14IFG4_OFS                                      ( 4)                  /* ADC14IFG4 Offset */
+#define ADC14IFG4                                          (0x00000010)          /* ADC14MEM4 interrupt flag */
+/* ADC14IFGR0[ADC14IFG5] Bits */
+#define ADC14IFG5_OFS                                      ( 5)                  /* ADC14IFG5 Offset */
+#define ADC14IFG5                                          (0x00000020)          /* ADC14MEM5 interrupt flag */
+/* ADC14IFGR0[ADC14IFG6] Bits */
+#define ADC14IFG6_OFS                                      ( 6)                  /* ADC14IFG6 Offset */
+#define ADC14IFG6                                          (0x00000040)          /* ADC14MEM6 interrupt flag */
+/* ADC14IFGR0[ADC14IFG7] Bits */
+#define ADC14IFG7_OFS                                      ( 7)                  /* ADC14IFG7 Offset */
+#define ADC14IFG7                                          (0x00000080)          /* ADC14MEM7 interrupt flag */
+/* ADC14IFGR0[ADC14IFG8] Bits */
+#define ADC14IFG8_OFS                                      ( 8)                  /* ADC14IFG8 Offset */
+#define ADC14IFG8                                          (0x00000100)          /* ADC14MEM8 interrupt flag */
+/* ADC14IFGR0[ADC14IFG9] Bits */
+#define ADC14IFG9_OFS                                      ( 9)                  /* ADC14IFG9 Offset */
+#define ADC14IFG9                                          (0x00000200)          /* ADC14MEM9 interrupt flag */
+/* ADC14IFGR0[ADC14IFG10] Bits */
+#define ADC14IFG10_OFS                                     (10)                  /* ADC14IFG10 Offset */
+#define ADC14IFG10                                         (0x00000400)          /* ADC14MEM10 interrupt flag */
+/* ADC14IFGR0[ADC14IFG11] Bits */
+#define ADC14IFG11_OFS                                     (11)                  /* ADC14IFG11 Offset */
+#define ADC14IFG11                                         (0x00000800)          /* ADC14MEM11 interrupt flag */
+/* ADC14IFGR0[ADC14IFG12] Bits */
+#define ADC14IFG12_OFS                                     (12)                  /* ADC14IFG12 Offset */
+#define ADC14IFG12                                         (0x00001000)          /* ADC14MEM12 interrupt flag */
+/* ADC14IFGR0[ADC14IFG13] Bits */
+#define ADC14IFG13_OFS                                     (13)                  /* ADC14IFG13 Offset */
+#define ADC14IFG13                                         (0x00002000)          /* ADC14MEM13 interrupt flag */
+/* ADC14IFGR0[ADC14IFG14] Bits */
+#define ADC14IFG14_OFS                                     (14)                  /* ADC14IFG14 Offset */
+#define ADC14IFG14                                         (0x00004000)          /* ADC14MEM14 interrupt flag */
+/* ADC14IFGR0[ADC14IFG15] Bits */
+#define ADC14IFG15_OFS                                     (15)                  /* ADC14IFG15 Offset */
+#define ADC14IFG15                                         (0x00008000)          /* ADC14MEM15 interrupt flag */
+/* ADC14IFGR0[ADC14IFG16] Bits */
+#define ADC14IFG16_OFS                                     (16)                  /* ADC14IFG16 Offset */
+#define ADC14IFG16                                         (0x00010000)          /* ADC14MEM16 interrupt flag */
+/* ADC14IFGR0[ADC14IFG17] Bits */
+#define ADC14IFG17_OFS                                     (17)                  /* ADC14IFG17 Offset */
+#define ADC14IFG17                                         (0x00020000)          /* ADC14MEM17 interrupt flag */
+/* ADC14IFGR0[ADC14IFG18] Bits */
+#define ADC14IFG18_OFS                                     (18)                  /* ADC14IFG18 Offset */
+#define ADC14IFG18                                         (0x00040000)          /* ADC14MEM18 interrupt flag */
+/* ADC14IFGR0[ADC14IFG19] Bits */
+#define ADC14IFG19_OFS                                     (19)                  /* ADC14IFG19 Offset */
+#define ADC14IFG19                                         (0x00080000)          /* ADC14MEM19 interrupt flag */
+/* ADC14IFGR0[ADC14IFG20] Bits */
+#define ADC14IFG20_OFS                                     (20)                  /* ADC14IFG20 Offset */
+#define ADC14IFG20                                         (0x00100000)          /* ADC14MEM20 interrupt flag */
+/* ADC14IFGR0[ADC14IFG21] Bits */
+#define ADC14IFG21_OFS                                     (21)                  /* ADC14IFG21 Offset */
+#define ADC14IFG21                                         (0x00200000)          /* ADC14MEM21 interrupt flag */
+/* ADC14IFGR0[ADC14IFG22] Bits */
+#define ADC14IFG22_OFS                                     (22)                  /* ADC14IFG22 Offset */
+#define ADC14IFG22                                         (0x00400000)          /* ADC14MEM22 interrupt flag */
+/* ADC14IFGR0[ADC14IFG23] Bits */
+#define ADC14IFG23_OFS                                     (23)                  /* ADC14IFG23 Offset */
+#define ADC14IFG23                                         (0x00800000)          /* ADC14MEM23 interrupt flag */
+/* ADC14IFGR0[ADC14IFG24] Bits */
+#define ADC14IFG24_OFS                                     (24)                  /* ADC14IFG24 Offset */
+#define ADC14IFG24                                         (0x01000000)          /* ADC14MEM24 interrupt flag */
+/* ADC14IFGR0[ADC14IFG25] Bits */
+#define ADC14IFG25_OFS                                     (25)                  /* ADC14IFG25 Offset */
+#define ADC14IFG25                                         (0x02000000)          /* ADC14MEM25 interrupt flag */
+/* ADC14IFGR0[ADC14IFG26] Bits */
+#define ADC14IFG26_OFS                                     (26)                  /* ADC14IFG26 Offset */
+#define ADC14IFG26                                         (0x04000000)          /* ADC14MEM26 interrupt flag */
+/* ADC14IFGR0[ADC14IFG27] Bits */
+#define ADC14IFG27_OFS                                     (27)                  /* ADC14IFG27 Offset */
+#define ADC14IFG27                                         (0x08000000)          /* ADC14MEM27 interrupt flag */
+/* ADC14IFGR0[ADC14IFG28] Bits */
+#define ADC14IFG28_OFS                                     (28)                  /* ADC14IFG28 Offset */
+#define ADC14IFG28                                         (0x10000000)          /* ADC14MEM28 interrupt flag */
+/* ADC14IFGR0[ADC14IFG29] Bits */
+#define ADC14IFG29_OFS                                     (29)                  /* ADC14IFG29 Offset */
+#define ADC14IFG29                                         (0x20000000)          /* ADC14MEM29 interrupt flag */
+/* ADC14IFGR0[ADC14IFG30] Bits */
+#define ADC14IFG30_OFS                                     (30)                  /* ADC14IFG30 Offset */
+#define ADC14IFG30                                         (0x40000000)          /* ADC14MEM30 interrupt flag */
+/* ADC14IFGR0[ADC14IFG31] Bits */
+#define ADC14IFG31_OFS                                     (31)                  /* ADC14IFG31 Offset */
+#define ADC14IFG31                                         (0x80000000)          /* ADC14MEM31 interrupt flag */
+/* ADC14IFGR1[ADC14INIFG] Bits */
+#define ADC14INIFG_OFS                                     ( 1)                  /* ADC14INIFG Offset */
+#define ADC14INIFG                                         (0x00000002)          /* Interrupt flag for ADC14MEMx within comparator window */
+/* ADC14IFGR1[ADC14LOIFG] Bits */
+#define ADC14LOIFG_OFS                                     ( 2)                  /* ADC14LOIFG Offset */
+#define ADC14LOIFG                                         (0x00000004)          /* Interrupt flag for ADC14MEMx below comparator window */
+/* ADC14IFGR1[ADC14HIIFG] Bits */
+#define ADC14HIIFG_OFS                                     ( 3)                  /* ADC14HIIFG Offset */
+#define ADC14HIIFG                                         (0x00000008)          /* Interrupt flag for ADC14MEMx above comparator window */
+/* ADC14IFGR1[ADC14OVIFG] Bits */
+#define ADC14OVIFG_OFS                                     ( 4)                  /* ADC14OVIFG Offset */
+#define ADC14OVIFG                                         (0x00000010)          /* ADC14MEMx overflow interrupt flag */
+/* ADC14IFGR1[ADC14TOVIFG] Bits */
+#define ADC14TOVIFG_OFS                                    ( 5)                  /* ADC14TOVIFG Offset */
+#define ADC14TOVIFG                                        (0x00000020)          /* ADC14 conversion time overflow interrupt flag */
+/* ADC14IFGR1[ADC14RDYIFG] Bits */
+#define ADC14RDYIFG_OFS                                    ( 6)                  /* ADC14RDYIFG Offset */
+#define ADC14RDYIFG                                        (0x00000040)          /* ADC14 local buffered reference ready interrupt flag */
+/* ADC14CLRIFGR0[CLRADC14IFG0] Bits */
+#define CLRADC14IFG0_OFS                                   ( 0)                  /* CLRADC14IFG0 Offset */
+#define CLRADC14IFG0                                       (0x00000001)          /* clear ADC14IFG0 */
+/* ADC14CLRIFGR0[CLRADC14IFG1] Bits */
+#define CLRADC14IFG1_OFS                                   ( 1)                  /* CLRADC14IFG1 Offset */
+#define CLRADC14IFG1                                       (0x00000002)          /* clear ADC14IFG1 */
+/* ADC14CLRIFGR0[CLRADC14IFG2] Bits */
+#define CLRADC14IFG2_OFS                                   ( 2)                  /* CLRADC14IFG2 Offset */
+#define CLRADC14IFG2                                       (0x00000004)          /* clear ADC14IFG2 */
+/* ADC14CLRIFGR0[CLRADC14IFG3] Bits */
+#define CLRADC14IFG3_OFS                                   ( 3)                  /* CLRADC14IFG3 Offset */
+#define CLRADC14IFG3                                       (0x00000008)          /* clear ADC14IFG3 */
+/* ADC14CLRIFGR0[CLRADC14IFG4] Bits */
+#define CLRADC14IFG4_OFS                                   ( 4)                  /* CLRADC14IFG4 Offset */
+#define CLRADC14IFG4                                       (0x00000010)          /* clear ADC14IFG4 */
+/* ADC14CLRIFGR0[CLRADC14IFG5] Bits */
+#define CLRADC14IFG5_OFS                                   ( 5)                  /* CLRADC14IFG5 Offset */
+#define CLRADC14IFG5                                       (0x00000020)          /* clear ADC14IFG5 */
+/* ADC14CLRIFGR0[CLRADC14IFG6] Bits */
+#define CLRADC14IFG6_OFS                                   ( 6)                  /* CLRADC14IFG6 Offset */
+#define CLRADC14IFG6                                       (0x00000040)          /* clear ADC14IFG6 */
+/* ADC14CLRIFGR0[CLRADC14IFG7] Bits */
+#define CLRADC14IFG7_OFS                                   ( 7)                  /* CLRADC14IFG7 Offset */
+#define CLRADC14IFG7                                       (0x00000080)          /* clear ADC14IFG7 */
+/* ADC14CLRIFGR0[CLRADC14IFG8] Bits */
+#define CLRADC14IFG8_OFS                                   ( 8)                  /* CLRADC14IFG8 Offset */
+#define CLRADC14IFG8                                       (0x00000100)          /* clear ADC14IFG8 */
+/* ADC14CLRIFGR0[CLRADC14IFG9] Bits */
+#define CLRADC14IFG9_OFS                                   ( 9)                  /* CLRADC14IFG9 Offset */
+#define CLRADC14IFG9                                       (0x00000200)          /* clear ADC14IFG9 */
+/* ADC14CLRIFGR0[CLRADC14IFG10] Bits */
+#define CLRADC14IFG10_OFS                                  (10)                  /* CLRADC14IFG10 Offset */
+#define CLRADC14IFG10                                      (0x00000400)          /* clear ADC14IFG10 */
+/* ADC14CLRIFGR0[CLRADC14IFG11] Bits */
+#define CLRADC14IFG11_OFS                                  (11)                  /* CLRADC14IFG11 Offset */
+#define CLRADC14IFG11                                      (0x00000800)          /* clear ADC14IFG11 */
+/* ADC14CLRIFGR0[CLRADC14IFG12] Bits */
+#define CLRADC14IFG12_OFS                                  (12)                  /* CLRADC14IFG12 Offset */
+#define CLRADC14IFG12                                      (0x00001000)          /* clear ADC14IFG12 */
+/* ADC14CLRIFGR0[CLRADC14IFG13] Bits */
+#define CLRADC14IFG13_OFS                                  (13)                  /* CLRADC14IFG13 Offset */
+#define CLRADC14IFG13                                      (0x00002000)          /* clear ADC14IFG13 */
+/* ADC14CLRIFGR0[CLRADC14IFG14] Bits */
+#define CLRADC14IFG14_OFS                                  (14)                  /* CLRADC14IFG14 Offset */
+#define CLRADC14IFG14                                      (0x00004000)          /* clear ADC14IFG14 */
+/* ADC14CLRIFGR0[CLRADC14IFG15] Bits */
+#define CLRADC14IFG15_OFS                                  (15)                  /* CLRADC14IFG15 Offset */
+#define CLRADC14IFG15                                      (0x00008000)          /* clear ADC14IFG15 */
+/* ADC14CLRIFGR0[CLRADC14IFG16] Bits */
+#define CLRADC14IFG16_OFS                                  (16)                  /* CLRADC14IFG16 Offset */
+#define CLRADC14IFG16                                      (0x00010000)          /* clear ADC14IFG16 */
+/* ADC14CLRIFGR0[CLRADC14IFG17] Bits */
+#define CLRADC14IFG17_OFS                                  (17)                  /* CLRADC14IFG17 Offset */
+#define CLRADC14IFG17                                      (0x00020000)          /* clear ADC14IFG17 */
+/* ADC14CLRIFGR0[CLRADC14IFG18] Bits */
+#define CLRADC14IFG18_OFS                                  (18)                  /* CLRADC14IFG18 Offset */
+#define CLRADC14IFG18                                      (0x00040000)          /* clear ADC14IFG18 */
+/* ADC14CLRIFGR0[CLRADC14IFG19] Bits */
+#define CLRADC14IFG19_OFS                                  (19)                  /* CLRADC14IFG19 Offset */
+#define CLRADC14IFG19                                      (0x00080000)          /* clear ADC14IFG19 */
+/* ADC14CLRIFGR0[CLRADC14IFG20] Bits */
+#define CLRADC14IFG20_OFS                                  (20)                  /* CLRADC14IFG20 Offset */
+#define CLRADC14IFG20                                      (0x00100000)          /* clear ADC14IFG20 */
+/* ADC14CLRIFGR0[CLRADC14IFG21] Bits */
+#define CLRADC14IFG21_OFS                                  (21)                  /* CLRADC14IFG21 Offset */
+#define CLRADC14IFG21                                      (0x00200000)          /* clear ADC14IFG21 */
+/* ADC14CLRIFGR0[CLRADC14IFG22] Bits */
+#define CLRADC14IFG22_OFS                                  (22)                  /* CLRADC14IFG22 Offset */
+#define CLRADC14IFG22                                      (0x00400000)          /* clear ADC14IFG22 */
+/* ADC14CLRIFGR0[CLRADC14IFG23] Bits */
+#define CLRADC14IFG23_OFS                                  (23)                  /* CLRADC14IFG23 Offset */
+#define CLRADC14IFG23                                      (0x00800000)          /* clear ADC14IFG23 */
+/* ADC14CLRIFGR0[CLRADC14IFG24] Bits */
+#define CLRADC14IFG24_OFS                                  (24)                  /* CLRADC14IFG24 Offset */
+#define CLRADC14IFG24                                      (0x01000000)          /* clear ADC14IFG24 */
+/* ADC14CLRIFGR0[CLRADC14IFG25] Bits */
+#define CLRADC14IFG25_OFS                                  (25)                  /* CLRADC14IFG25 Offset */
+#define CLRADC14IFG25                                      (0x02000000)          /* clear ADC14IFG25 */
+/* ADC14CLRIFGR0[CLRADC14IFG26] Bits */
+#define CLRADC14IFG26_OFS                                  (26)                  /* CLRADC14IFG26 Offset */
+#define CLRADC14IFG26                                      (0x04000000)          /* clear ADC14IFG26 */
+/* ADC14CLRIFGR0[CLRADC14IFG27] Bits */
+#define CLRADC14IFG27_OFS                                  (27)                  /* CLRADC14IFG27 Offset */
+#define CLRADC14IFG27                                      (0x08000000)          /* clear ADC14IFG27 */
+/* ADC14CLRIFGR0[CLRADC14IFG28] Bits */
+#define CLRADC14IFG28_OFS                                  (28)                  /* CLRADC14IFG28 Offset */
+#define CLRADC14IFG28                                      (0x10000000)          /* clear ADC14IFG28 */
+/* ADC14CLRIFGR0[CLRADC14IFG29] Bits */
+#define CLRADC14IFG29_OFS                                  (29)                  /* CLRADC14IFG29 Offset */
+#define CLRADC14IFG29                                      (0x20000000)          /* clear ADC14IFG29 */
+/* ADC14CLRIFGR0[CLRADC14IFG30] Bits */
+#define CLRADC14IFG30_OFS                                  (30)                  /* CLRADC14IFG30 Offset */
+#define CLRADC14IFG30                                      (0x40000000)          /* clear ADC14IFG30 */
+/* ADC14CLRIFGR0[CLRADC14IFG31] Bits */
+#define CLRADC14IFG31_OFS                                  (31)                  /* CLRADC14IFG31 Offset */
+#define CLRADC14IFG31                                      (0x80000000)          /* clear ADC14IFG31 */
+/* ADC14CLRIFGR1[CLRADC14INIFG] Bits */
+#define CLRADC14INIFG_OFS                                  ( 1)                  /* CLRADC14INIFG Offset */
+#define CLRADC14INIFG                                      (0x00000002)          /* clear ADC14INIFG */
+/* ADC14CLRIFGR1[CLRADC14LOIFG] Bits */
+#define CLRADC14LOIFG_OFS                                  ( 2)                  /* CLRADC14LOIFG Offset */
+#define CLRADC14LOIFG                                      (0x00000004)          /* clear ADC14LOIFG */
+/* ADC14CLRIFGR1[CLRADC14HIIFG] Bits */
+#define CLRADC14HIIFG_OFS                                  ( 3)                  /* CLRADC14HIIFG Offset */
+#define CLRADC14HIIFG                                      (0x00000008)          /* clear ADC14HIIFG */
+/* ADC14CLRIFGR1[CLRADC14OVIFG] Bits */
+#define CLRADC14OVIFG_OFS                                  ( 4)                  /* CLRADC14OVIFG Offset */
+#define CLRADC14OVIFG                                      (0x00000010)          /* clear ADC14OVIFG */
+/* ADC14CLRIFGR1[CLRADC14TOVIFG] Bits */
+#define CLRADC14TOVIFG_OFS                                 ( 5)                  /* CLRADC14TOVIFG Offset */
+#define CLRADC14TOVIFG                                     (0x00000020)          /* clear ADC14TOVIFG */
+/* ADC14CLRIFGR1[CLRADC14RDYIFG] Bits */
+#define CLRADC14RDYIFG_OFS                                 ( 6)                  /* CLRADC14RDYIFG Offset */
+#define CLRADC14RDYIFG                                     (0x00000040)          /* clear ADC14RDYIFG */
+
+
+//*****************************************************************************
+// AES256 Bits
+//*****************************************************************************
+/* AESACTL0[AESOP] Bits */
+#define AESOP0                                             (0x0001)              /* AESOP Bit 0 */
+#define AESOP1                                             (0x0002)              /* AESOP Bit 1 */
+/* AESACTL0[AESOP] Bits */
+#define AESOP_OFS                                          ( 0)                  /* AESOPx Offset */
+#define AESOP_M                                            (0x0003)              /* AES operation */
+//#define AESOP0                                             (0x0001)              /* AES operation */
+//#define AESOP1                                             (0x0002)              /* AES operation */
+#define AESOP_0                                            (0x0000)              /* Encryption */
+#define AESOP_1                                            (0x0001)              /* Decryption. The provided key is the same key used for encryption */
+#define AESOP_2                                            (0x0002)              /* Generate first round key required for decryption */
+#define AESOP_3                                            (0x0003)              /* Decryption. The provided key is the first round key required for decryption */
+/* AESACTL0[AESKL] Bits */
+#define AESKL0                                             (0x0004)              /* AESKL Bit 0 */
+#define AESKL1                                             (0x0008)              /* AESKL Bit 1 */
+/* AESACTL0[AESKL] Bits */
+#define AESKL_OFS                                          ( 2)                  /* AESKLx Offset */
+#define AESKL_M                                            (0x000c)              /* AES key length */
+//#define AESKL0                                             (0x0004)              /* AES key length */
+//#define AESKL1                                             (0x0008)              /* AES key length */
+#define AESKL_0                                            (0x0000)              /* AES128. The key size is 128 bit */
+#define AESKL_1                                            (0x0004)              /* AES192. The key size is 192 bit. */
+#define AESKL_2                                            (0x0008)              /* AES256. The key size is 256 bit */
+#define AESKL__128BIT                                      (0x0000)              /* AES128. The key size is 128 bit */
+#define AESKL__192BIT                                      (0x0004)              /* AES192. The key size is 192 bit. */
+#define AESKL__256BIT                                      (0x0008)              /* AES256. The key size is 256 bit */
+/* AESACTL0[AESCM] Bits */
+#define AESCM0                                             (0x0020)              /* AESCM Bit 0 */
+#define AESCM1                                             (0x0040)              /* AESCM Bit 1 */
+/* AESACTL0[AESCM] Bits */
+#define AESCM_OFS                                          ( 5)                  /* AESCMx Offset */
+#define AESCM_M                                            (0x0060)              /* AES cipher mode select */
+//#define AESCM0                                             (0x0020)              /* AES cipher mode select */
+//#define AESCM1                                             (0x0040)              /* AES cipher mode select */
+#define AESCM_0                                            (0x0000)              /* ECB */
+#define AESCM_1                                            (0x0020)              /* CBC */
+#define AESCM_2                                            (0x0040)              /* OFB */
+#define AESCM_3                                            (0x0060)              /* CFB */
+#define AESCM__ECB                                         (0x0000)              /* ECB */
+#define AESCM__CBC                                         (0x0020)              /* CBC */
+#define AESCM__OFB                                         (0x0040)              /* OFB */
+#define AESCM__CFB                                         (0x0060)              /* CFB */
+/* AESACTL0[AESSWRST] Bits */
+#define AESSWRST_OFS                                       ( 7)                  /* AESSWRST Offset */
+#define AESSWRST                                           (0x0080)              /* AES software reset */
+/* AESACTL0[AESRDYIFG] Bits */
+#define AESRDYIFG_OFS                                      ( 8)                  /* AESRDYIFG Offset */
+#define AESRDYIFG                                          (0x0100)              /* AES ready interrupt flag */
+/* AESACTL0[AESERRFG] Bits */
+#define AESERRFG_OFS                                       (11)                  /* AESERRFG Offset */
+#define AESERRFG                                           (0x0800)              /* AES error flag */
+/* AESACTL0[AESRDYIE] Bits */
+#define AESRDYIE_OFS                                       (12)                  /* AESRDYIE Offset */
+#define AESRDYIE                                           (0x1000)              /* AES ready interrupt enable */
+/* AESACTL0[AESCMEN] Bits */
+#define AESCMEN_OFS                                        (15)                  /* AESCMEN Offset */
+#define AESCMEN                                            (0x8000)              /* AES cipher mode enable */
+/* AESACTL1[AESBLKCNT] Bits */
+#define AESBLKCNT0                                         (0x0001)              /* AESBLKCNT Bit 0 */
+#define AESBLKCNT1                                         (0x0002)              /* AESBLKCNT Bit 1 */
+#define AESBLKCNT2                                         (0x0004)              /* AESBLKCNT Bit 2 */
+#define AESBLKCNT3                                         (0x0008)              /* AESBLKCNT Bit 3 */
+#define AESBLKCNT4                                         (0x0010)              /* AESBLKCNT Bit 4 */
+#define AESBLKCNT5                                         (0x0020)              /* AESBLKCNT Bit 5 */
+#define AESBLKCNT6                                         (0x0040)              /* AESBLKCNT Bit 6 */
+#define AESBLKCNT7                                         (0x0080)              /* AESBLKCNT Bit 7 */
+/* AESACTL1[AESBLKCNT] Bits */
+#define AESBLKCNT_OFS                                      ( 0)                  /* AESBLKCNTx Offset */
+#define AESBLKCNT_M                                        (0x00ff)              /* Cipher Block Counter */
+/* AESASTAT[AESBUSY] Bits */
+#define AESBUSY_OFS                                        ( 0)                  /* AESBUSY Offset */
+#define AESBUSY                                            (0x0001)              /* AES accelerator module busy */
+/* AESASTAT[AESKEYWR] Bits */
+#define AESKEYWR_OFS                                       ( 1)                  /* AESKEYWR Offset */
+#define AESKEYWR                                           (0x0002)              /* All 16 bytes written to AESAKEY */
+/* AESASTAT[AESDINWR] Bits */
+#define AESDINWR_OFS                                       ( 2)                  /* AESDINWR Offset */
+#define AESDINWR                                           (0x0004)              /* All 16 bytes written to AESADIN, AESAXDIN or AESAXIN */
+/* AESASTAT[AESDOUTRD] Bits */
+#define AESDOUTRD_OFS                                      ( 3)                  /* AESDOUTRD Offset */
+#define AESDOUTRD                                          (0x0008)              /* All 16 bytes read from AESADOUT */
+/* AESASTAT[AESKEYCNT] Bits */
+#define AESKEYCNT0                                         (0x0010)              /* AESKEYCNT Bit 0 */
+#define AESKEYCNT1                                         (0x0020)              /* AESKEYCNT Bit 1 */
+#define AESKEYCNT2                                         (0x0040)              /* AESKEYCNT Bit 2 */
+#define AESKEYCNT3                                         (0x0080)              /* AESKEYCNT Bit 3 */
+/* AESASTAT[AESKEYCNT] Bits */
+#define AESKEYCNT_OFS                                      ( 4)                  /* AESKEYCNTx Offset */
+#define AESKEYCNT_M                                        (0x00f0)              /* Bytes written via AESAKEY for AESKLx=00, half-words written via AESAKEY */
+/* AESASTAT[AESDINCNT] Bits */
+#define AESDINCNT0                                         (0x0100)              /* AESDINCNT Bit 0 */
+#define AESDINCNT1                                         (0x0200)              /* AESDINCNT Bit 1 */
+#define AESDINCNT2                                         (0x0400)              /* AESDINCNT Bit 2 */
+#define AESDINCNT3                                         (0x0800)              /* AESDINCNT Bit 3 */
+/* AESASTAT[AESDINCNT] Bits */
+#define AESDINCNT_OFS                                      ( 8)                  /* AESDINCNTx Offset */
+#define AESDINCNT_M                                        (0x0f00)              /* Bytes written via AESADIN, AESAXDIN or AESAXIN */
+/* AESASTAT[AESDOUTCNT] Bits */
+#define AESDOUTCNT0                                        (0x1000)              /* AESDOUTCNT Bit 0 */
+#define AESDOUTCNT1                                        (0x2000)              /* AESDOUTCNT Bit 1 */
+#define AESDOUTCNT2                                        (0x4000)              /* AESDOUTCNT Bit 2 */
+#define AESDOUTCNT3                                        (0x8000)              /* AESDOUTCNT Bit 3 */
+/* AESASTAT[AESDOUTCNT] Bits */
+#define AESDOUTCNT_OFS                                     (12)                  /* AESDOUTCNTx Offset */
+#define AESDOUTCNT_M                                       (0xf000)              /* Bytes read via AESADOUT */
+/* AESAKEY[AESKEY0] Bits */
+#define AESKEY00                                           (0x0001)              /* AESKEY0 Bit 0 */
+#define AESKEY01                                           (0x0002)              /* AESKEY0 Bit 1 */
+#define AESKEY02                                           (0x0004)              /* AESKEY0 Bit 2 */
+#define AESKEY03                                           (0x0008)              /* AESKEY0 Bit 3 */
+#define AESKEY04                                           (0x0010)              /* AESKEY0 Bit 4 */
+#define AESKEY05                                           (0x0020)              /* AESKEY0 Bit 5 */
+#define AESKEY06                                           (0x0040)              /* AESKEY0 Bit 6 */
+#define AESKEY07                                           (0x0080)              /* AESKEY0 Bit 7 */
+/* AESAKEY[AESKEY0] Bits */
+#define AESKEY0_OFS                                        ( 0)                  /* AESKEY0x Offset */
+#define AESKEY0_M                                          (0x00ff)              /* AES key byte n when AESAKEY is written as half-word */
+/* AESAKEY[AESKEY1] Bits */
+#define AESKEY10                                           (0x0100)              /* AESKEY1 Bit 0 */
+#define AESKEY11                                           (0x0200)              /* AESKEY1 Bit 1 */
+#define AESKEY12                                           (0x0400)              /* AESKEY1 Bit 2 */
+#define AESKEY13                                           (0x0800)              /* AESKEY1 Bit 3 */
+#define AESKEY14                                           (0x1000)              /* AESKEY1 Bit 4 */
+#define AESKEY15                                           (0x2000)              /* AESKEY1 Bit 5 */
+#define AESKEY16                                           (0x4000)              /* AESKEY1 Bit 6 */
+#define AESKEY17                                           (0x8000)              /* AESKEY1 Bit 7 */
+/* AESAKEY[AESKEY1] Bits */
+#define AESKEY1_OFS                                        ( 8)                  /* AESKEY1x Offset */
+#define AESKEY1_M                                          (0xff00)              /* AES key byte n+1 when AESAKEY is written as half-word */
+/* AESADIN[AESDIN0] Bits */
+#define AESDIN00                                           (0x0001)              /* AESDIN0 Bit 0 */
+#define AESDIN01                                           (0x0002)              /* AESDIN0 Bit 1 */
+#define AESDIN02                                           (0x0004)              /* AESDIN0 Bit 2 */
+#define AESDIN03                                           (0x0008)              /* AESDIN0 Bit 3 */
+#define AESDIN04                                           (0x0010)              /* AESDIN0 Bit 4 */
+#define AESDIN05                                           (0x0020)              /* AESDIN0 Bit 5 */
+#define AESDIN06                                           (0x0040)              /* AESDIN0 Bit 6 */
+#define AESDIN07                                           (0x0080)              /* AESDIN0 Bit 7 */
+/* AESADIN[AESDIN0] Bits */
+#define AESDIN0_OFS                                        ( 0)                  /* AESDIN0x Offset */
+#define AESDIN0_M                                          (0x00ff)              /* AES data in byte n when AESADIN is written as half-word */
+/* AESADIN[AESDIN1] Bits */
+#define AESDIN10                                           (0x0100)              /* AESDIN1 Bit 0 */
+#define AESDIN11                                           (0x0200)              /* AESDIN1 Bit 1 */
+#define AESDIN12                                           (0x0400)              /* AESDIN1 Bit 2 */
+#define AESDIN13                                           (0x0800)              /* AESDIN1 Bit 3 */
+#define AESDIN14                                           (0x1000)              /* AESDIN1 Bit 4 */
+#define AESDIN15                                           (0x2000)              /* AESDIN1 Bit 5 */
+#define AESDIN16                                           (0x4000)              /* AESDIN1 Bit 6 */
+#define AESDIN17                                           (0x8000)              /* AESDIN1 Bit 7 */
+/* AESADIN[AESDIN1] Bits */
+#define AESDIN1_OFS                                        ( 8)                  /* AESDIN1x Offset */
+#define AESDIN1_M                                          (0xff00)              /* AES data in byte n+1 when AESADIN is written as half-word */
+/* AESADOUT[AESDOUT0] Bits */
+#define AESDOUT00                                          (0x0001)              /* AESDOUT0 Bit 0 */
+#define AESDOUT01                                          (0x0002)              /* AESDOUT0 Bit 1 */
+#define AESDOUT02                                          (0x0004)              /* AESDOUT0 Bit 2 */
+#define AESDOUT03                                          (0x0008)              /* AESDOUT0 Bit 3 */
+#define AESDOUT04                                          (0x0010)              /* AESDOUT0 Bit 4 */
+#define AESDOUT05                                          (0x0020)              /* AESDOUT0 Bit 5 */
+#define AESDOUT06                                          (0x0040)              /* AESDOUT0 Bit 6 */
+#define AESDOUT07                                          (0x0080)              /* AESDOUT0 Bit 7 */
+/* AESADOUT[AESDOUT0] Bits */
+#define AESDOUT0_OFS                                       ( 0)                  /* AESDOUT0x Offset */
+#define AESDOUT0_M                                         (0x00ff)              /* AES data out byte n when AESADOUT is read as half-word */
+/* AESADOUT[AESDOUT1] Bits */
+#define AESDOUT10                                          (0x0100)              /* AESDOUT1 Bit 0 */
+#define AESDOUT11                                          (0x0200)              /* AESDOUT1 Bit 1 */
+#define AESDOUT12                                          (0x0400)              /* AESDOUT1 Bit 2 */
+#define AESDOUT13                                          (0x0800)              /* AESDOUT1 Bit 3 */
+#define AESDOUT14                                          (0x1000)              /* AESDOUT1 Bit 4 */
+#define AESDOUT15                                          (0x2000)              /* AESDOUT1 Bit 5 */
+#define AESDOUT16                                          (0x4000)              /* AESDOUT1 Bit 6 */
+#define AESDOUT17                                          (0x8000)              /* AESDOUT1 Bit 7 */
+/* AESADOUT[AESDOUT1] Bits */
+#define AESDOUT1_OFS                                       ( 8)                  /* AESDOUT1x Offset */
+#define AESDOUT1_M                                         (0xff00)              /* AES data out byte n+1 when AESADOUT is read as half-word */
+/* AESAXDIN[AESXDIN0] Bits */
+#define AESXDIN00                                          (0x0001)              /* AESXDIN0 Bit 0 */
+#define AESXDIN01                                          (0x0002)              /* AESXDIN0 Bit 1 */
+#define AESXDIN02                                          (0x0004)              /* AESXDIN0 Bit 2 */
+#define AESXDIN03                                          (0x0008)              /* AESXDIN0 Bit 3 */
+#define AESXDIN04                                          (0x0010)              /* AESXDIN0 Bit 4 */
+#define AESXDIN05                                          (0x0020)              /* AESXDIN0 Bit 5 */
+#define AESXDIN06                                          (0x0040)              /* AESXDIN0 Bit 6 */
+#define AESXDIN07                                          (0x0080)              /* AESXDIN0 Bit 7 */
+/* AESAXDIN[AESXDIN0] Bits */
+#define AESXDIN0_OFS                                       ( 0)                  /* AESXDIN0x Offset */
+#define AESXDIN0_M                                         (0x00ff)              /* AES data in byte n when AESAXDIN is written as half-word */
+/* AESAXDIN[AESXDIN1] Bits */
+#define AESXDIN10                                          (0x0100)              /* AESXDIN1 Bit 0 */
+#define AESXDIN11                                          (0x0200)              /* AESXDIN1 Bit 1 */
+#define AESXDIN12                                          (0x0400)              /* AESXDIN1 Bit 2 */
+#define AESXDIN13                                          (0x0800)              /* AESXDIN1 Bit 3 */
+#define AESXDIN14                                          (0x1000)              /* AESXDIN1 Bit 4 */
+#define AESXDIN15                                          (0x2000)              /* AESXDIN1 Bit 5 */
+#define AESXDIN16                                          (0x4000)              /* AESXDIN1 Bit 6 */
+#define AESXDIN17                                          (0x8000)              /* AESXDIN1 Bit 7 */
+/* AESAXDIN[AESXDIN1] Bits */
+#define AESXDIN1_OFS                                       ( 8)                  /* AESXDIN1x Offset */
+#define AESXDIN1_M                                         (0xff00)              /* AES data in byte n+1 when AESAXDIN is written as half-word */
+/* AESAXIN[AESXIN0] Bits */
+#define AESXIN00                                           (0x0001)              /* AESXIN0 Bit 0 */
+#define AESXIN01                                           (0x0002)              /* AESXIN0 Bit 1 */
+#define AESXIN02                                           (0x0004)              /* AESXIN0 Bit 2 */
+#define AESXIN03                                           (0x0008)              /* AESXIN0 Bit 3 */
+#define AESXIN04                                           (0x0010)              /* AESXIN0 Bit 4 */
+#define AESXIN05                                           (0x0020)              /* AESXIN0 Bit 5 */
+#define AESXIN06                                           (0x0040)              /* AESXIN0 Bit 6 */
+#define AESXIN07                                           (0x0080)              /* AESXIN0 Bit 7 */
+/* AESAXIN[AESXIN0] Bits */
+#define AESXIN0_OFS                                        ( 0)                  /* AESXIN0x Offset */
+#define AESXIN0_M                                          (0x00ff)              /* AES data in byte n when AESAXIN is written as half-word */
+/* AESAXIN[AESXIN1] Bits */
+#define AESXIN10                                           (0x0100)              /* AESXIN1 Bit 0 */
+#define AESXIN11                                           (0x0200)              /* AESXIN1 Bit 1 */
+#define AESXIN12                                           (0x0400)              /* AESXIN1 Bit 2 */
+#define AESXIN13                                           (0x0800)              /* AESXIN1 Bit 3 */
+#define AESXIN14                                           (0x1000)              /* AESXIN1 Bit 4 */
+#define AESXIN15                                           (0x2000)              /* AESXIN1 Bit 5 */
+#define AESXIN16                                           (0x4000)              /* AESXIN1 Bit 6 */
+#define AESXIN17                                           (0x8000)              /* AESXIN1 Bit 7 */
+/* AESAXIN[AESXIN1] Bits */
+#define AESXIN1_OFS                                        ( 8)                  /* AESXIN1x Offset */
+#define AESXIN1_M                                          (0xff00)              /* AES data in byte n+1 when AESAXIN is written as half-word */
+
+
+//*****************************************************************************
+// CAPTIO0 Bits
+//*****************************************************************************
+/* CAPTIO0CTL[CAPTIOPISEL] Bits */
+#define CAPTIOPISEL0                                       (0x0002)              /* CAPTIOPISEL Bit 0 */
+#define CAPTIOPISEL1                                       (0x0004)              /* CAPTIOPISEL Bit 1 */
+#define CAPTIOPISEL2                                       (0x0008)              /* CAPTIOPISEL Bit 2 */
+/* CAPTIO0CTL[CAPTIOPISEL] Bits */
+#define CAPTIOPISEL_OFS                                    ( 1)                  /* CAPTIOPISELx Offset */
+#define CAPTIOPISEL_M                                      (0x000e)              /* Capacitive Touch IO pin select */
+//#define CAPTIOPISEL0                                       (0x0002)              /* Capacitive Touch IO pin select */
+//#define CAPTIOPISEL1                                       (0x0004)              /* Capacitive Touch IO pin select */
+//#define CAPTIOPISEL2                                       (0x0008)              /* Capacitive Touch IO pin select */
+#define CAPTIOPISEL_0                                      (0x0000)              /* Px.0 */
+#define CAPTIOPISEL_1                                      (0x0002)              /* Px.1 */
+#define CAPTIOPISEL_2                                      (0x0004)              /* Px.2 */
+#define CAPTIOPISEL_3                                      (0x0006)              /* Px.3 */
+#define CAPTIOPISEL_4                                      (0x0008)              /* Px.4 */
+#define CAPTIOPISEL_5                                      (0x000a)              /* Px.5 */
+#define CAPTIOPISEL_6                                      (0x000c)              /* Px.6 */
+#define CAPTIOPISEL_7                                      (0x000e)              /* Px.7 */
+/* CAPTIO0CTL[CAPTIOPOSEL] Bits */
+#define CAPTIOPOSEL0                                       (0x0010)              /* CAPTIOPOSEL Bit 0 */
+#define CAPTIOPOSEL1                                       (0x0020)              /* CAPTIOPOSEL Bit 1 */
+#define CAPTIOPOSEL2                                       (0x0040)              /* CAPTIOPOSEL Bit 2 */
+#define CAPTIOPOSEL3                                       (0x0080)              /* CAPTIOPOSEL Bit 3 */
+/* CAPTIO0CTL[CAPTIOPOSEL] Bits */
+#define CAPTIOPOSEL_OFS                                    ( 4)                  /* CAPTIOPOSELx Offset */
+#define CAPTIOPOSEL_M                                      (0x00f0)              /* Capacitive Touch IO port select */
+//#define CAPTIOPOSEL0                                       (0x0010)              /* Capacitive Touch IO port select */
+//#define CAPTIOPOSEL1                                       (0x0020)              /* Capacitive Touch IO port select */
+//#define CAPTIOPOSEL2                                       (0x0040)              /* Capacitive Touch IO port select */
+//#define CAPTIOPOSEL3                                       (0x0080)              /* Capacitive Touch IO port select */
+#define CAPTIOPOSEL_0                                      (0x0000)              /* Px = PJ */
+#define CAPTIOPOSEL_1                                      (0x0010)              /* Px = P1 */
+#define CAPTIOPOSEL_2                                      (0x0020)              /* Px = P2 */
+#define CAPTIOPOSEL_3                                      (0x0030)              /* Px = P3 */
+#define CAPTIOPOSEL_4                                      (0x0040)              /* Px = P4 */
+#define CAPTIOPOSEL_5                                      (0x0050)              /* Px = P5 */
+#define CAPTIOPOSEL_6                                      (0x0060)              /* Px = P6 */
+#define CAPTIOPOSEL_7                                      (0x0070)              /* Px = P7 */
+#define CAPTIOPOSEL_8                                      (0x0080)              /* Px = P8 */
+#define CAPTIOPOSEL_9                                      (0x0090)              /* Px = P9 */
+#define CAPTIOPOSEL_10                                     (0x00a0)              /* Px = P10 */
+#define CAPTIOPOSEL_11                                     (0x00b0)              /* Px = P11 */
+#define CAPTIOPOSEL_12                                     (0x00c0)              /* Px = P12 */
+#define CAPTIOPOSEL_13                                     (0x00d0)              /* Px = P13 */
+#define CAPTIOPOSEL_14                                     (0x00e0)              /* Px = P14 */
+#define CAPTIOPOSEL_15                                     (0x00f0)              /* Px = P15 */
+#define CAPTIOPOSEL__PJ                                    (0x0000)              /* Px = PJ */
+#define CAPTIOPOSEL__P1                                    (0x0010)              /* Px = P1 */
+#define CAPTIOPOSEL__P2                                    (0x0020)              /* Px = P2 */
+#define CAPTIOPOSEL__P3                                    (0x0030)              /* Px = P3 */
+#define CAPTIOPOSEL__P4                                    (0x0040)              /* Px = P4 */
+#define CAPTIOPOSEL__P5                                    (0x0050)              /* Px = P5 */
+#define CAPTIOPOSEL__P6                                    (0x0060)              /* Px = P6 */
+#define CAPTIOPOSEL__P7                                    (0x0070)              /* Px = P7 */
+#define CAPTIOPOSEL__P8                                    (0x0080)              /* Px = P8 */
+#define CAPTIOPOSEL__P9                                    (0x0090)              /* Px = P9 */
+#define CAPTIOPOSEL__P10                                   (0x00a0)              /* Px = P10 */
+#define CAPTIOPOSEL__P11                                   (0x00b0)              /* Px = P11 */
+#define CAPTIOPOSEL__P12                                   (0x00c0)              /* Px = P12 */
+#define CAPTIOPOSEL__P13                                   (0x00d0)              /* Px = P13 */
+#define CAPTIOPOSEL__P14                                   (0x00e0)              /* Px = P14 */
+#define CAPTIOPOSEL__P15                                   (0x00f0)              /* Px = P15 */
+/* CAPTIO0CTL[CAPTIOEN] Bits */
+#define CAPTIOEN_OFS                                       ( 8)                  /* CAPTIOEN Offset */
+#define CAPTIOEN                                           (0x0100)              /* Capacitive Touch IO enable */
+/* CAPTIO0CTL[CAPTIOSTATE] Bits */
+#define CAPTIOSTATE_OFS                                    ( 9)                  /* CAPTIOSTATE Offset */
+#define CAPTIOSTATE                                        (0x0200)              /* Capacitive Touch IO state */
+
+
+//*****************************************************************************
+// CAPTIO1 Bits
+//*****************************************************************************
+/* CAPTIO1CTL[CAPTIOPISEL] Bits */
+//#define CAPTIOPISEL0                                       (0x0002)              /* CAPTIOPISEL Bit 0 */
+//#define CAPTIOPISEL1                                       (0x0004)              /* CAPTIOPISEL Bit 1 */
+//#define CAPTIOPISEL2                                       (0x0008)              /* CAPTIOPISEL Bit 2 */
+/* CAPTIO1CTL[CAPTIOPISEL] Bits */
+//#define CAPTIOPISEL_OFS                                    ( 1)                  /* CAPTIOPISELx Offset */
+//#define CAPTIOPISEL_M                                      (0x000e)              /* Capacitive Touch IO pin select */
+//#define CAPTIOPISEL0                                       (0x0002)              /* Capacitive Touch IO pin select */
+//#define CAPTIOPISEL1                                       (0x0004)              /* Capacitive Touch IO pin select */
+//#define CAPTIOPISEL2                                       (0x0008)              /* Capacitive Touch IO pin select */
+//#define CAPTIOPISEL_0                                      (0x0000)              /* Px.0 */
+//#define CAPTIOPISEL_1                                      (0x0002)              /* Px.1 */
+//#define CAPTIOPISEL_2                                      (0x0004)              /* Px.2 */
+//#define CAPTIOPISEL_3                                      (0x0006)              /* Px.3 */
+//#define CAPTIOPISEL_4                                      (0x0008)              /* Px.4 */
+//#define CAPTIOPISEL_5                                      (0x000a)              /* Px.5 */
+//#define CAPTIOPISEL_6                                      (0x000c)              /* Px.6 */
+//#define CAPTIOPISEL_7                                      (0x000e)              /* Px.7 */
+/* CAPTIO1CTL[CAPTIOPOSEL] Bits */
+//#define CAPTIOPOSEL0                                       (0x0010)              /* CAPTIOPOSEL Bit 0 */
+//#define CAPTIOPOSEL1                                       (0x0020)              /* CAPTIOPOSEL Bit 1 */
+//#define CAPTIOPOSEL2                                       (0x0040)              /* CAPTIOPOSEL Bit 2 */
+//#define CAPTIOPOSEL3                                       (0x0080)              /* CAPTIOPOSEL Bit 3 */
+/* CAPTIO1CTL[CAPTIOPOSEL] Bits */
+//#define CAPTIOPOSEL_OFS                                    ( 4)                  /* CAPTIOPOSELx Offset */
+//#define CAPTIOPOSEL_M                                      (0x00f0)              /* Capacitive Touch IO port select */
+//#define CAPTIOPOSEL0                                       (0x0010)              /* Capacitive Touch IO port select */
+//#define CAPTIOPOSEL1                                       (0x0020)              /* Capacitive Touch IO port select */
+//#define CAPTIOPOSEL2                                       (0x0040)              /* Capacitive Touch IO port select */
+//#define CAPTIOPOSEL3                                       (0x0080)              /* Capacitive Touch IO port select */
+//#define CAPTIOPOSEL_0                                      (0x0000)              /* Px = PJ */
+//#define CAPTIOPOSEL_1                                      (0x0010)              /* Px = P1 */
+//#define CAPTIOPOSEL_2                                      (0x0020)              /* Px = P2 */
+//#define CAPTIOPOSEL_3                                      (0x0030)              /* Px = P3 */
+//#define CAPTIOPOSEL_4                                      (0x0040)              /* Px = P4 */
+//#define CAPTIOPOSEL_5                                      (0x0050)              /* Px = P5 */
+//#define CAPTIOPOSEL_6                                      (0x0060)              /* Px = P6 */
+//#define CAPTIOPOSEL_7                                      (0x0070)              /* Px = P7 */
+//#define CAPTIOPOSEL_8                                      (0x0080)              /* Px = P8 */
+//#define CAPTIOPOSEL_9                                      (0x0090)              /* Px = P9 */
+//#define CAPTIOPOSEL_10                                     (0x00a0)              /* Px = P10 */
+//#define CAPTIOPOSEL_11                                     (0x00b0)              /* Px = P11 */
+//#define CAPTIOPOSEL_12                                     (0x00c0)              /* Px = P12 */
+//#define CAPTIOPOSEL_13                                     (0x00d0)              /* Px = P13 */
+//#define CAPTIOPOSEL_14                                     (0x00e0)              /* Px = P14 */
+//#define CAPTIOPOSEL_15                                     (0x00f0)              /* Px = P15 */
+//#define CAPTIOPOSEL__PJ                                    (0x0000)              /* Px = PJ */
+//#define CAPTIOPOSEL__P1                                    (0x0010)              /* Px = P1 */
+//#define CAPTIOPOSEL__P2                                    (0x0020)              /* Px = P2 */
+//#define CAPTIOPOSEL__P3                                    (0x0030)              /* Px = P3 */
+//#define CAPTIOPOSEL__P4                                    (0x0040)              /* Px = P4 */
+//#define CAPTIOPOSEL__P5                                    (0x0050)              /* Px = P5 */
+//#define CAPTIOPOSEL__P6                                    (0x0060)              /* Px = P6 */
+//#define CAPTIOPOSEL__P7                                    (0x0070)              /* Px = P7 */
+//#define CAPTIOPOSEL__P8                                    (0x0080)              /* Px = P8 */
+//#define CAPTIOPOSEL__P9                                    (0x0090)              /* Px = P9 */
+//#define CAPTIOPOSEL__P10                                   (0x00a0)              /* Px = P10 */
+//#define CAPTIOPOSEL__P11                                   (0x00b0)              /* Px = P11 */
+//#define CAPTIOPOSEL__P12                                   (0x00c0)              /* Px = P12 */
+//#define CAPTIOPOSEL__P13                                   (0x00d0)              /* Px = P13 */
+//#define CAPTIOPOSEL__P14                                   (0x00e0)              /* Px = P14 */
+//#define CAPTIOPOSEL__P15                                   (0x00f0)              /* Px = P15 */
+/* CAPTIO1CTL[CAPTIOEN] Bits */
+//#define CAPTIOEN_OFS                                       ( 8)                  /* CAPTIOEN Offset */
+//#define CAPTIOEN                                           (0x0100)              /* Capacitive Touch IO enable */
+/* CAPTIO1CTL[CAPTIOSTATE] Bits */
+//#define CAPTIOSTATE_OFS                                    ( 9)                  /* CAPTIOSTATE Offset */
+//#define CAPTIOSTATE                                        (0x0200)              /* Capacitive Touch IO state */
+
+
+//*****************************************************************************
+// COMP_E0 Bits
+//*****************************************************************************
+/* CE0CTL0[CEIPSEL] Bits */
+#define CEIPSEL_OFS                                        ( 0)                  /* CEIPSEL Offset */
+#define CEIPSEL_M                                          (0x000f)              /* Channel input selected for the V+ terminal */
+#define CEIPSEL0                                           (0x0001)              /* Channel input selected for the V+ terminal */
+#define CEIPSEL1                                           (0x0002)              /* Channel input selected for the V+ terminal */
+#define CEIPSEL2                                           (0x0004)              /* Channel input selected for the V+ terminal */
+#define CEIPSEL3                                           (0x0008)              /* Channel input selected for the V+ terminal */
+#define CEIPSEL_0                                          (0x0000)              /* Channel 0 selected */
+#define CEIPSEL_1                                          (0x0001)              /* Channel 1 selected */
+#define CEIPSEL_2                                          (0x0002)              /* Channel 2 selected */
+#define CEIPSEL_3                                          (0x0003)              /* Channel 3 selected */
+#define CEIPSEL_4                                          (0x0004)              /* Channel 4 selected */
+#define CEIPSEL_5                                          (0x0005)              /* Channel 5 selected */
+#define CEIPSEL_6                                          (0x0006)              /* Channel 6 selected */
+#define CEIPSEL_7                                          (0x0007)              /* Channel 7 selected */
+#define CEIPSEL_8                                          (0x0008)              /* Channel 8 selected */
+#define CEIPSEL_9                                          (0x0009)              /* Channel 9 selected */
+#define CEIPSEL_10                                         (0x000a)              /* Channel 10 selected */
+#define CEIPSEL_11                                         (0x000b)              /* Channel 11 selected */
+#define CEIPSEL_12                                         (0x000c)              /* Channel 12 selected */
+#define CEIPSEL_13                                         (0x000d)              /* Channel 13 selected */
+#define CEIPSEL_14                                         (0x000e)              /* Channel 14 selected */
+#define CEIPSEL_15                                         (0x000f)              /* Channel 15 selected */
+/* CE0CTL0[CEIPEN] Bits */
+#define CEIPEN_OFS                                         ( 7)                  /* CEIPEN Offset */
+#define CEIPEN                                             (0x0080)              /* Channel input enable for the V+ terminal */
+/* CE0CTL0[CEIMSEL] Bits */
+#define CEIMSEL_OFS                                        ( 8)                  /* CEIMSEL Offset */
+#define CEIMSEL_M                                          (0x0f00)              /* Channel input selected for the - terminal */
+#define CEIMSEL0                                           (0x0100)              /* Channel input selected for the - terminal */
+#define CEIMSEL1                                           (0x0200)              /* Channel input selected for the - terminal */
+#define CEIMSEL2                                           (0x0400)              /* Channel input selected for the - terminal */
+#define CEIMSEL3                                           (0x0800)              /* Channel input selected for the - terminal */
+#define CEIMSEL_0                                          (0x0000)              /* Channel 0 selected */
+#define CEIMSEL_1                                          (0x0100)              /* Channel 1 selected */
+#define CEIMSEL_2                                          (0x0200)              /* Channel 2 selected */
+#define CEIMSEL_3                                          (0x0300)              /* Channel 3 selected */
+#define CEIMSEL_4                                          (0x0400)              /* Channel 4 selected */
+#define CEIMSEL_5                                          (0x0500)              /* Channel 5 selected */
+#define CEIMSEL_6                                          (0x0600)              /* Channel 6 selected */
+#define CEIMSEL_7                                          (0x0700)              /* Channel 7 selected */
+#define CEIMSEL_8                                          (0x0800)              /* Channel 8 selected */
+#define CEIMSEL_9                                          (0x0900)              /* Channel 9 selected */
+#define CEIMSEL_10                                         (0x0a00)              /* Channel 10 selected */
+#define CEIMSEL_11                                         (0x0b00)              /* Channel 11 selected */
+#define CEIMSEL_12                                         (0x0c00)              /* Channel 12 selected */
+#define CEIMSEL_13                                         (0x0d00)              /* Channel 13 selected */
+#define CEIMSEL_14                                         (0x0e00)              /* Channel 14 selected */
+#define CEIMSEL_15                                         (0x0f00)              /* Channel 15 selected */
+/* CE0CTL0[CEIMEN] Bits */
+#define CEIMEN_OFS                                         (15)                  /* CEIMEN Offset */
+#define CEIMEN                                             (0x8000)              /* Channel input enable for the - terminal */
+/* CE0CTL1[CEOUT] Bits */
+#define CEOUT_OFS                                          ( 0)                  /* CEOUT Offset */
+#define CEOUT                                              (0x0001)              /* Comparator output value */
+/* CE0CTL1[CEOUTPOL] Bits */
+#define CEOUTPOL_OFS                                       ( 1)                  /* CEOUTPOL Offset */
+#define CEOUTPOL                                           (0x0002)              /* Comparator output polarity */
+/* CE0CTL1[CEF] Bits */
+#define CEF_OFS                                            ( 2)                  /* CEF Offset */
+#define CEF                                                (0x0004)              /* Comparator output filter */
+/* CE0CTL1[CEIES] Bits */
+#define CEIES_OFS                                          ( 3)                  /* CEIES Offset */
+#define CEIES                                              (0x0008)              /* Interrupt edge select for CEIIFG and CEIFG */
+/* CE0CTL1[CESHORT] Bits */
+#define CESHORT_OFS                                        ( 4)                  /* CESHORT Offset */
+#define CESHORT                                            (0x0010)              /* Input short */
+/* CE0CTL1[CEEX] Bits */
+#define CEEX_OFS                                           ( 5)                  /* CEEX Offset */
+#define CEEX                                               (0x0020)              /* Exchange */
+/* CE0CTL1[CEFDLY] Bits */
+#define CEFDLY_OFS                                         ( 6)                  /* CEFDLY Offset */
+#define CEFDLY_M                                           (0x00c0)              /* Filter delay */
+#define CEFDLY0                                            (0x0040)              /* Filter delay */
+#define CEFDLY1                                            (0x0080)              /* Filter delay */
+#define CEFDLY_0                                           (0x0000)              /* Typical filter delay of TBD (450) ns */
+#define CEFDLY_1                                           (0x0040)              /* Typical filter delay of TBD (900) ns */
+#define CEFDLY_2                                           (0x0080)              /* Typical filter delay of TBD (1800) ns */
+#define CEFDLY_3                                           (0x00c0)              /* Typical filter delay of TBD (3600) ns */
+/* CE0CTL1[CEPWRMD] Bits */
+#define CEPWRMD_OFS                                        ( 8)                  /* CEPWRMD Offset */
+#define CEPWRMD_M                                          (0x0300)              /* Power Mode */
+#define CEPWRMD0                                           (0x0100)              /* Power Mode */
+#define CEPWRMD1                                           (0x0200)              /* Power Mode */
+#define CEPWRMD_0                                          (0x0000)              /* High-speed mode */
+#define CEPWRMD_1                                          (0x0100)              /* Normal mode */
+#define CEPWRMD_2                                          (0x0200)              /* Ultra-low power mode */
+/* CE0CTL1[CEON] Bits */
+#define CEON_OFS                                           (10)                  /* CEON Offset */
+#define CEON                                               (0x0400)              /* Comparator On */
+/* CE0CTL1[CEMRVL] Bits */
+#define CEMRVL_OFS                                         (11)                  /* CEMRVL Offset */
+#define CEMRVL                                             (0x0800)              /* This bit is valid of CEMRVS is set to 1 */
+/* CE0CTL1[CEMRVS] Bits */
+#define CEMRVS_OFS                                         (12)                  /* CEMRVS Offset */
+#define CEMRVS                                             (0x1000)              /*  */
+/* CE0CTL2[CEREF0] Bits */
+#define CEREF0_OFS                                         ( 0)                  /* CEREF0 Offset */
+#define CEREF0_M                                           (0x001f)              /* Reference resistor tap 0 */
+/* CE0CTL2[CERSEL] Bits */
+#define CERSEL_OFS                                         ( 5)                  /* CERSEL Offset */
+#define CERSEL                                             (0x0020)              /* Reference select */
+/* CE0CTL2[CERS] Bits */
+#define CERS_OFS                                           ( 6)                  /* CERS Offset */
+#define CERS_M                                             (0x00c0)              /* Reference source */
+#define CERS0                                              (0x0040)              /* Reference source */
+#define CERS1                                              (0x0080)              /* Reference source */
+#define CERS_0                                             (0x0000)              /* No current is drawn by the reference circuitry */
+#define CERS_1                                             (0x0040)              /* VCC applied to the resistor ladder */
+#define CERS_2                                             (0x0080)              /* Shared reference voltage applied to the resistor ladder */
+#define CERS_3                                             (0x00c0)              /* Shared reference voltage supplied to V(CREF). Resistor ladder is off */
+/* CE0CTL2[CEREF1] Bits */
+#define CEREF1_OFS                                         ( 8)                  /* CEREF1 Offset */
+#define CEREF1_M                                           (0x1f00)              /* Reference resistor tap 1 */
+/* CE0CTL2[CEREFL] Bits */
+#define CEREFL_OFS                                         (13)                  /* CEREFL Offset */
+#define CEREFL_M                                           (0x6000)              /* Reference voltage level */
+#define CEREFL0                                            (0x2000)              /* Reference voltage level */
+#define CEREFL1                                            (0x4000)              /* Reference voltage level */
+#define CEREFL_0                                           (0x0000)              /* Reference amplifier is disabled. No reference voltage is requested */
+#define CEREFL_1                                           (0x2000)              /* 1.2 V is selected as shared reference voltage input */
+#define CEREFL_2                                           (0x4000)              /* 2.0 V is selected as shared reference voltage input */
+#define CEREFL_3                                           (0x6000)              /* 2.5 V is selected as shared reference voltage input */
+#define CEREFL__OFF                                        (0x0000)              /* Reference amplifier is disabled. No reference voltage is requested */
+#define CEREFL__1P2V                                       (0x2000)              /* 1.2 V is selected as shared reference voltage input */
+#define CEREFL__2P0V                                       (0x4000)              /* 2.0 V is selected as shared reference voltage input */
+#define CEREFL__2P5V                                       (0x6000)              /* 2.5 V is selected as shared reference voltage input */
+/* CE0CTL2[CEREFACC] Bits */
+#define CEREFACC_OFS                                       (15)                  /* CEREFACC Offset */
+#define CEREFACC                                           (0x8000)              /* Reference accuracy */
+/* CE0CTL3[CEPD0] Bits */
+#define CEPD0_OFS                                          ( 0)                  /* CEPD0 Offset */
+#define CEPD0                                              (0x0001)              /* Port disable */
+/* CE0CTL3[CEPD1] Bits */
+#define CEPD1_OFS                                          ( 1)                  /* CEPD1 Offset */
+#define CEPD1                                              (0x0002)              /* Port disable */
+/* CE0CTL3[CEPD2] Bits */
+#define CEPD2_OFS                                          ( 2)                  /* CEPD2 Offset */
+#define CEPD2                                              (0x0004)              /* Port disable */
+/* CE0CTL3[CEPD3] Bits */
+#define CEPD3_OFS                                          ( 3)                  /* CEPD3 Offset */
+#define CEPD3                                              (0x0008)              /* Port disable */
+/* CE0CTL3[CEPD4] Bits */
+#define CEPD4_OFS                                          ( 4)                  /* CEPD4 Offset */
+#define CEPD4                                              (0x0010)              /* Port disable */
+/* CE0CTL3[CEPD5] Bits */
+#define CEPD5_OFS                                          ( 5)                  /* CEPD5 Offset */
+#define CEPD5                                              (0x0020)              /* Port disable */
+/* CE0CTL3[CEPD6] Bits */
+#define CEPD6_OFS                                          ( 6)                  /* CEPD6 Offset */
+#define CEPD6                                              (0x0040)              /* Port disable */
+/* CE0CTL3[CEPD7] Bits */
+#define CEPD7_OFS                                          ( 7)                  /* CEPD7 Offset */
+#define CEPD7                                              (0x0080)              /* Port disable */
+/* CE0CTL3[CEPD8] Bits */
+#define CEPD8_OFS                                          ( 8)                  /* CEPD8 Offset */
+#define CEPD8                                              (0x0100)              /* Port disable */
+/* CE0CTL3[CEPD9] Bits */
+#define CEPD9_OFS                                          ( 9)                  /* CEPD9 Offset */
+#define CEPD9                                              (0x0200)              /* Port disable */
+/* CE0CTL3[CEPD10] Bits */
+#define CEPD10_OFS                                         (10)                  /* CEPD10 Offset */
+#define CEPD10                                             (0x0400)              /* Port disable */
+/* CE0CTL3[CEPD11] Bits */
+#define CEPD11_OFS                                         (11)                  /* CEPD11 Offset */
+#define CEPD11                                             (0x0800)              /* Port disable */
+/* CE0CTL3[CEPD12] Bits */
+#define CEPD12_OFS                                         (12)                  /* CEPD12 Offset */
+#define CEPD12                                             (0x1000)              /* Port disable */
+/* CE0CTL3[CEPD13] Bits */
+#define CEPD13_OFS                                         (13)                  /* CEPD13 Offset */
+#define CEPD13                                             (0x2000)              /* Port disable */
+/* CE0CTL3[CEPD14] Bits */
+#define CEPD14_OFS                                         (14)                  /* CEPD14 Offset */
+#define CEPD14                                             (0x4000)              /* Port disable */
+/* CE0CTL3[CEPD15] Bits */
+#define CEPD15_OFS                                         (15)                  /* CEPD15 Offset */
+#define CEPD15                                             (0x8000)              /* Port disable */
+/* CE0INT[CEIFG] Bits */
+#define CEIFG_OFS                                          ( 0)                  /* CEIFG Offset */
+#define CEIFG                                              (0x0001)              /* Comparator output interrupt flag */
+/* CE0INT[CEIIFG] Bits */
+#define CEIIFG_OFS                                         ( 1)                  /* CEIIFG Offset */
+#define CEIIFG                                             (0x0002)              /* Comparator output inverted interrupt flag */
+/* CE0INT[CERDYIFG] Bits */
+#define CERDYIFG_OFS                                       ( 4)                  /* CERDYIFG Offset */
+#define CERDYIFG                                           (0x0010)              /* Comparator ready interrupt flag */
+/* CE0INT[CEIE] Bits */
+#define CEIE_OFS                                           ( 8)                  /* CEIE Offset */
+#define CEIE                                               (0x0100)              /* Comparator output interrupt enable */
+/* CE0INT[CEIIE] Bits */
+#define CEIIE_OFS                                          ( 9)                  /* CEIIE Offset */
+#define CEIIE                                              (0x0200)              /* Comparator output interrupt enable inverted polarity */
+/* CE0INT[CERDYIE] Bits */
+#define CERDYIE_OFS                                        (12)                  /* CERDYIE Offset */
+#define CERDYIE                                            (0x1000)              /* Comparator ready interrupt enable */
+
+
+//*****************************************************************************
+// COMP_E1 Bits
+//*****************************************************************************
+/* CE1CTL0[CEIPSEL] Bits */
+//#define CEIPSEL_OFS                                        ( 0)                  /* CEIPSEL Offset */
+//#define CEIPSEL_M                                          (0x000f)              /* Channel input selected for the V+ terminal */
+//#define CEIPSEL0                                           (0x0001)              /* Channel input selected for the V+ terminal */
+//#define CEIPSEL1                                           (0x0002)              /* Channel input selected for the V+ terminal */
+//#define CEIPSEL2                                           (0x0004)              /* Channel input selected for the V+ terminal */
+//#define CEIPSEL3                                           (0x0008)              /* Channel input selected for the V+ terminal */
+//#define CEIPSEL_0                                          (0x0000)              /* Channel 0 selected */
+//#define CEIPSEL_1                                          (0x0001)              /* Channel 1 selected */
+//#define CEIPSEL_2                                          (0x0002)              /* Channel 2 selected */
+//#define CEIPSEL_3                                          (0x0003)              /* Channel 3 selected */
+//#define CEIPSEL_4                                          (0x0004)              /* Channel 4 selected */
+//#define CEIPSEL_5                                          (0x0005)              /* Channel 5 selected */
+//#define CEIPSEL_6                                          (0x0006)              /* Channel 6 selected */
+//#define CEIPSEL_7                                          (0x0007)              /* Channel 7 selected */
+//#define CEIPSEL_8                                          (0x0008)              /* Channel 8 selected */
+//#define CEIPSEL_9                                          (0x0009)              /* Channel 9 selected */
+//#define CEIPSEL_10                                         (0x000a)              /* Channel 10 selected */
+//#define CEIPSEL_11                                         (0x000b)              /* Channel 11 selected */
+//#define CEIPSEL_12                                         (0x000c)              /* Channel 12 selected */
+//#define CEIPSEL_13                                         (0x000d)              /* Channel 13 selected */
+//#define CEIPSEL_14                                         (0x000e)              /* Channel 14 selected */
+//#define CEIPSEL_15                                         (0x000f)              /* Channel 15 selected */
+/* CE1CTL0[CEIPEN] Bits */
+//#define CEIPEN_OFS                                         ( 7)                  /* CEIPEN Offset */
+//#define CEIPEN                                             (0x0080)              /* Channel input enable for the V+ terminal */
+/* CE1CTL0[CEIMSEL] Bits */
+//#define CEIMSEL_OFS                                        ( 8)                  /* CEIMSEL Offset */
+//#define CEIMSEL_M                                          (0x0f00)              /* Channel input selected for the - terminal */
+//#define CEIMSEL0                                           (0x0100)              /* Channel input selected for the - terminal */
+//#define CEIMSEL1                                           (0x0200)              /* Channel input selected for the - terminal */
+//#define CEIMSEL2                                           (0x0400)              /* Channel input selected for the - terminal */
+//#define CEIMSEL3                                           (0x0800)              /* Channel input selected for the - terminal */
+//#define CEIMSEL_0                                          (0x0000)              /* Channel 0 selected */
+//#define CEIMSEL_1                                          (0x0100)              /* Channel 1 selected */
+//#define CEIMSEL_2                                          (0x0200)              /* Channel 2 selected */
+//#define CEIMSEL_3                                          (0x0300)              /* Channel 3 selected */
+//#define CEIMSEL_4                                          (0x0400)              /* Channel 4 selected */
+//#define CEIMSEL_5                                          (0x0500)              /* Channel 5 selected */
+//#define CEIMSEL_6                                          (0x0600)              /* Channel 6 selected */
+//#define CEIMSEL_7                                          (0x0700)              /* Channel 7 selected */
+//#define CEIMSEL_8                                          (0x0800)              /* Channel 8 selected */
+//#define CEIMSEL_9                                          (0x0900)              /* Channel 9 selected */
+//#define CEIMSEL_10                                         (0x0a00)              /* Channel 10 selected */
+//#define CEIMSEL_11                                         (0x0b00)              /* Channel 11 selected */
+//#define CEIMSEL_12                                         (0x0c00)              /* Channel 12 selected */
+//#define CEIMSEL_13                                         (0x0d00)              /* Channel 13 selected */
+//#define CEIMSEL_14                                         (0x0e00)              /* Channel 14 selected */
+//#define CEIMSEL_15                                         (0x0f00)              /* Channel 15 selected */
+/* CE1CTL0[CEIMEN] Bits */
+//#define CEIMEN_OFS                                         (15)                  /* CEIMEN Offset */
+//#define CEIMEN                                             (0x8000)              /* Channel input enable for the - terminal */
+/* CE1CTL1[CEOUT] Bits */
+//#define CEOUT_OFS                                          ( 0)                  /* CEOUT Offset */
+//#define CEOUT                                              (0x0001)              /* Comparator output value */
+/* CE1CTL1[CEOUTPOL] Bits */
+//#define CEOUTPOL_OFS                                       ( 1)                  /* CEOUTPOL Offset */
+//#define CEOUTPOL                                           (0x0002)              /* Comparator output polarity */
+/* CE1CTL1[CEF] Bits */
+//#define CEF_OFS                                            ( 2)                  /* CEF Offset */
+//#define CEF                                                (0x0004)              /* Comparator output filter */
+/* CE1CTL1[CEIES] Bits */
+//#define CEIES_OFS                                          ( 3)                  /* CEIES Offset */
+//#define CEIES                                              (0x0008)              /* Interrupt edge select for CEIIFG and CEIFG */
+/* CE1CTL1[CESHORT] Bits */
+//#define CESHORT_OFS                                        ( 4)                  /* CESHORT Offset */
+//#define CESHORT                                            (0x0010)              /* Input short */
+/* CE1CTL1[CEEX] Bits */
+//#define CEEX_OFS                                           ( 5)                  /* CEEX Offset */
+//#define CEEX                                               (0x0020)              /* Exchange */
+/* CE1CTL1[CEFDLY] Bits */
+//#define CEFDLY_OFS                                         ( 6)                  /* CEFDLY Offset */
+//#define CEFDLY_M                                           (0x00c0)              /* Filter delay */
+//#define CEFDLY0                                            (0x0040)              /* Filter delay */
+//#define CEFDLY1                                            (0x0080)              /* Filter delay */
+//#define CEFDLY_0                                           (0x0000)              /* Typical filter delay of TBD (450) ns */
+//#define CEFDLY_1                                           (0x0040)              /* Typical filter delay of TBD (900) ns */
+//#define CEFDLY_2                                           (0x0080)              /* Typical filter delay of TBD (1800) ns */
+//#define CEFDLY_3                                           (0x00c0)              /* Typical filter delay of TBD (3600) ns */
+/* CE1CTL1[CEPWRMD] Bits */
+//#define CEPWRMD_OFS                                        ( 8)                  /* CEPWRMD Offset */
+//#define CEPWRMD_M                                          (0x0300)              /* Power Mode */
+//#define CEPWRMD0                                           (0x0100)              /* Power Mode */
+//#define CEPWRMD1                                           (0x0200)              /* Power Mode */
+//#define CEPWRMD_0                                          (0x0000)              /* High-speed mode */
+//#define CEPWRMD_1                                          (0x0100)              /* Normal mode */
+//#define CEPWRMD_2                                          (0x0200)              /* Ultra-low power mode */
+/* CE1CTL1[CEON] Bits */
+//#define CEON_OFS                                           (10)                  /* CEON Offset */
+//#define CEON                                               (0x0400)              /* Comparator On */
+/* CE1CTL1[CEMRVL] Bits */
+//#define CEMRVL_OFS                                         (11)                  /* CEMRVL Offset */
+//#define CEMRVL                                             (0x0800)              /* This bit is valid of CEMRVS is set to 1 */
+/* CE1CTL1[CEMRVS] Bits */
+//#define CEMRVS_OFS                                         (12)                  /* CEMRVS Offset */
+//#define CEMRVS                                             (0x1000)              /*  */
+/* CE1CTL2[CEREF0] Bits */
+//#define CEREF0_OFS                                         ( 0)                  /* CEREF0 Offset */
+//#define CEREF0_M                                           (0x001f)              /* Reference resistor tap 0 */
+/* CE1CTL2[CERSEL] Bits */
+//#define CERSEL_OFS                                         ( 5)                  /* CERSEL Offset */
+//#define CERSEL                                             (0x0020)              /* Reference select */
+/* CE1CTL2[CERS] Bits */
+//#define CERS_OFS                                           ( 6)                  /* CERS Offset */
+//#define CERS_M                                             (0x00c0)              /* Reference source */
+//#define CERS0                                              (0x0040)              /* Reference source */
+//#define CERS1                                              (0x0080)              /* Reference source */
+//#define CERS_0                                             (0x0000)              /* No current is drawn by the reference circuitry */
+//#define CERS_1                                             (0x0040)              /* VCC applied to the resistor ladder */
+//#define CERS_2                                             (0x0080)              /* Shared reference voltage applied to the resistor ladder */
+//#define CERS_3                                             (0x00c0)              /* Shared reference voltage supplied to V(CREF). Resistor ladder is off */
+/* CE1CTL2[CEREF1] Bits */
+//#define CEREF1_OFS                                         ( 8)                  /* CEREF1 Offset */
+//#define CEREF1_M                                           (0x1f00)              /* Reference resistor tap 1 */
+/* CE1CTL2[CEREFL] Bits */
+//#define CEREFL_OFS                                         (13)                  /* CEREFL Offset */
+//#define CEREFL_M                                           (0x6000)              /* Reference voltage level */
+//#define CEREFL0                                            (0x2000)              /* Reference voltage level */
+//#define CEREFL1                                            (0x4000)              /* Reference voltage level */
+//#define CEREFL_0                                           (0x0000)              /* Reference amplifier is disabled. No reference voltage is requested */
+//#define CEREFL_1                                           (0x2000)              /* 1.2 V is selected as shared reference voltage input */
+//#define CEREFL_2                                           (0x4000)              /* 2.0 V is selected as shared reference voltage input */
+//#define CEREFL_3                                           (0x6000)              /* 2.5 V is selected as shared reference voltage input */
+//#define CEREFL__OFF                                        (0x0000)              /* Reference amplifier is disabled. No reference voltage is requested */
+//#define CEREFL__1P2V                                       (0x2000)              /* 1.2 V is selected as shared reference voltage input */
+//#define CEREFL__2P0V                                       (0x4000)              /* 2.0 V is selected as shared reference voltage input */
+//#define CEREFL__2P5V                                       (0x6000)              /* 2.5 V is selected as shared reference voltage input */
+/* CE1CTL2[CEREFACC] Bits */
+//#define CEREFACC_OFS                                       (15)                  /* CEREFACC Offset */
+//#define CEREFACC                                           (0x8000)              /* Reference accuracy */
+/* CE1CTL3[CEPD0] Bits */
+//#define CEPD0_OFS                                          ( 0)                  /* CEPD0 Offset */
+//#define CEPD0                                              (0x0001)              /* Port disable */
+/* CE1CTL3[CEPD1] Bits */
+//#define CEPD1_OFS                                          ( 1)                  /* CEPD1 Offset */
+//#define CEPD1                                              (0x0002)              /* Port disable */
+/* CE1CTL3[CEPD2] Bits */
+//#define CEPD2_OFS                                          ( 2)                  /* CEPD2 Offset */
+//#define CEPD2                                              (0x0004)              /* Port disable */
+/* CE1CTL3[CEPD3] Bits */
+//#define CEPD3_OFS                                          ( 3)                  /* CEPD3 Offset */
+//#define CEPD3                                              (0x0008)              /* Port disable */
+/* CE1CTL3[CEPD4] Bits */
+//#define CEPD4_OFS                                          ( 4)                  /* CEPD4 Offset */
+//#define CEPD4                                              (0x0010)              /* Port disable */
+/* CE1CTL3[CEPD5] Bits */
+//#define CEPD5_OFS                                          ( 5)                  /* CEPD5 Offset */
+//#define CEPD5                                              (0x0020)              /* Port disable */
+/* CE1CTL3[CEPD6] Bits */
+//#define CEPD6_OFS                                          ( 6)                  /* CEPD6 Offset */
+//#define CEPD6                                              (0x0040)              /* Port disable */
+/* CE1CTL3[CEPD7] Bits */
+//#define CEPD7_OFS                                          ( 7)                  /* CEPD7 Offset */
+//#define CEPD7                                              (0x0080)              /* Port disable */
+/* CE1CTL3[CEPD8] Bits */
+//#define CEPD8_OFS                                          ( 8)                  /* CEPD8 Offset */
+//#define CEPD8                                              (0x0100)              /* Port disable */
+/* CE1CTL3[CEPD9] Bits */
+//#define CEPD9_OFS                                          ( 9)                  /* CEPD9 Offset */
+//#define CEPD9                                              (0x0200)              /* Port disable */
+/* CE1CTL3[CEPD10] Bits */
+//#define CEPD10_OFS                                         (10)                  /* CEPD10 Offset */
+//#define CEPD10                                             (0x0400)              /* Port disable */
+/* CE1CTL3[CEPD11] Bits */
+//#define CEPD11_OFS                                         (11)                  /* CEPD11 Offset */
+//#define CEPD11                                             (0x0800)              /* Port disable */
+/* CE1CTL3[CEPD12] Bits */
+//#define CEPD12_OFS                                         (12)                  /* CEPD12 Offset */
+//#define CEPD12                                             (0x1000)              /* Port disable */
+/* CE1CTL3[CEPD13] Bits */
+//#define CEPD13_OFS                                         (13)                  /* CEPD13 Offset */
+//#define CEPD13                                             (0x2000)              /* Port disable */
+/* CE1CTL3[CEPD14] Bits */
+//#define CEPD14_OFS                                         (14)                  /* CEPD14 Offset */
+//#define CEPD14                                             (0x4000)              /* Port disable */
+/* CE1CTL3[CEPD15] Bits */
+//#define CEPD15_OFS                                         (15)                  /* CEPD15 Offset */
+//#define CEPD15                                             (0x8000)              /* Port disable */
+/* CE1INT[CEIFG] Bits */
+//#define CEIFG_OFS                                          ( 0)                  /* CEIFG Offset */
+//#define CEIFG                                              (0x0001)              /* Comparator output interrupt flag */
+/* CE1INT[CEIIFG] Bits */
+//#define CEIIFG_OFS                                         ( 1)                  /* CEIIFG Offset */
+//#define CEIIFG                                             (0x0002)              /* Comparator output inverted interrupt flag */
+/* CE1INT[CERDYIFG] Bits */
+//#define CERDYIFG_OFS                                       ( 4)                  /* CERDYIFG Offset */
+//#define CERDYIFG                                           (0x0010)              /* Comparator ready interrupt flag */
+/* CE1INT[CEIE] Bits */
+//#define CEIE_OFS                                           ( 8)                  /* CEIE Offset */
+//#define CEIE                                               (0x0100)              /* Comparator output interrupt enable */
+/* CE1INT[CEIIE] Bits */
+//#define CEIIE_OFS                                          ( 9)                  /* CEIIE Offset */
+//#define CEIIE                                              (0x0200)              /* Comparator output interrupt enable inverted polarity */
+/* CE1INT[CERDYIE] Bits */
+//#define CERDYIE_OFS                                        (12)                  /* CERDYIE Offset */
+//#define CERDYIE                                            (0x1000)              /* Comparator ready interrupt enable */
+
+
+//*****************************************************************************
+// COREDEBUG Bits
+//*****************************************************************************
+/* COREDEBUG_DHCSR[COREDEBUG_DHCSR_C_DEBUGEN] Bits */
+#define COREDEBUG_DHCSR_C_DEBUGEN_OFS                      ( 0)                  /* C_DEBUGEN Offset */
+#define COREDEBUG_DHCSR_C_DEBUGEN                          (0x00000001)          /*  */
+/* COREDEBUG_DHCSR[COREDEBUG_DHCSR_C_HALT] Bits */
+#define COREDEBUG_DHCSR_C_HALT_OFS                         ( 1)                  /* C_HALT Offset */
+#define COREDEBUG_DHCSR_C_HALT                             (0x00000002)          /*  */
+/* COREDEBUG_DHCSR[COREDEBUG_DHCSR_C_STEP] Bits */
+#define COREDEBUG_DHCSR_C_STEP_OFS                         ( 2)                  /* C_STEP Offset */
+#define COREDEBUG_DHCSR_C_STEP                             (0x00000004)          /*  */
+/* COREDEBUG_DHCSR[COREDEBUG_DHCSR_C_MASKINTS] Bits */
+#define COREDEBUG_DHCSR_C_MASKINTS_OFS                     ( 3)                  /* C_MASKINTS Offset */
+#define COREDEBUG_DHCSR_C_MASKINTS                         (0x00000008)          /*  */
+/* COREDEBUG_DHCSR[COREDEBUG_DHCSR_C_SNAPSTALL] Bits */
+#define COREDEBUG_DHCSR_C_SNAPSTALL_OFS                    ( 5)                  /* C_SNAPSTALL Offset */
+#define COREDEBUG_DHCSR_C_SNAPSTALL                        (0x00000020)          /*  */
+/* COREDEBUG_DHCSR[COREDEBUG_DHCSR_S_REGRDY] Bits */
+#define COREDEBUG_DHCSR_S_REGRDY_OFS                       (16)                  /* S_REGRDY Offset */
+#define COREDEBUG_DHCSR_S_REGRDY                           (0x00010000)          /*  */
+/* COREDEBUG_DHCSR[COREDEBUG_DHCSR_S_HALT] Bits */
+#define COREDEBUG_DHCSR_S_HALT_OFS                         (17)                  /* S_HALT Offset */
+#define COREDEBUG_DHCSR_S_HALT                             (0x00020000)          /*  */
+/* COREDEBUG_DHCSR[COREDEBUG_DHCSR_S_SLEEP] Bits */
+#define COREDEBUG_DHCSR_S_SLEEP_OFS                        (18)                  /* S_SLEEP Offset */
+#define COREDEBUG_DHCSR_S_SLEEP                            (0x00040000)          /*  */
+/* COREDEBUG_DHCSR[COREDEBUG_DHCSR_S_LOCKUP] Bits */
+#define COREDEBUG_DHCSR_S_LOCKUP_OFS                       (19)                  /* S_LOCKUP Offset */
+#define COREDEBUG_DHCSR_S_LOCKUP                           (0x00080000)          /*  */
+/* COREDEBUG_DHCSR[COREDEBUG_DHCSR_S_RETIRE_ST] Bits */
+#define COREDEBUG_DHCSR_S_RETIRE_ST_OFS                    (24)                  /* S_RETIRE_ST Offset */
+#define COREDEBUG_DHCSR_S_RETIRE_ST                        (0x01000000)          /*  */
+/* COREDEBUG_DHCSR[COREDEBUG_DHCSR_S_RESET_ST] Bits */
+#define COREDEBUG_DHCSR_S_RESET_ST_OFS                     (25)                  /* S_RESET_ST Offset */
+#define COREDEBUG_DHCSR_S_RESET_ST                         (0x02000000)          /*  */
+/* COREDEBUG_DCRSR[COREDEBUG_DCRSR_REGSEL] Bits */
+#define COREDEBUG_DCRSR_REGSEL_OFS                         ( 0)                  /* REGSEL Offset */
+#define COREDEBUG_DCRSR_REGSEL_M                           (0x0000001f)          /*  */
+#define COREDEBUG_DCRSR_REGSEL0                            (0x00000001)          /*  */
+#define COREDEBUG_DCRSR_REGSEL1                            (0x00000002)          /*  */
+#define COREDEBUG_DCRSR_REGSEL2                            (0x00000004)          /*  */
+#define COREDEBUG_DCRSR_REGSEL3                            (0x00000008)          /*  */
+#define COREDEBUG_DCRSR_REGSEL4                            (0x00000010)          /*  */
+#define COREDEBUG_DCRSR_REGSEL_0                           (0x00000000)          /* R11 */
+//#define COREDEBUG_DCRSR_REGSEL_0                           (0x00000000)          /* R0 */
+#define COREDEBUG_DCRSR_REGSEL_1                           (0x00000001)          /* R1 */
+#define COREDEBUG_DCRSR_REGSEL_2                           (0x00000002)          /* R2 */
+#define COREDEBUG_DCRSR_REGSEL_3                           (0x00000003)          /* R3 */
+#define COREDEBUG_DCRSR_REGSEL_4                           (0x00000004)          /* R4 */
+#define COREDEBUG_DCRSR_REGSEL_5                           (0x00000005)          /* R5 */
+#define COREDEBUG_DCRSR_REGSEL_6                           (0x00000006)          /* R6 */
+#define COREDEBUG_DCRSR_REGSEL_7                           (0x00000007)          /* R7 */
+#define COREDEBUG_DCRSR_REGSEL_8                           (0x00000008)          /* R8 */
+#define COREDEBUG_DCRSR_REGSEL_9                           (0x00000009)          /* R9 */
+#define COREDEBUG_DCRSR_REGSEL_10                          (0x0000000a)          /* R10 */
+#define COREDEBUG_DCRSR_REGSEL_12                          (0x0000000c)          /* R12 */
+#define COREDEBUG_DCRSR_REGSEL_13                          (0x0000000d)          /* Current SP */
+#define COREDEBUG_DCRSR_REGSEL_14                          (0x0000000e)          /* LR */
+#define COREDEBUG_DCRSR_REGSEL_15                          (0x0000000f)          /* DebugReturnAddress */
+#define COREDEBUG_DCRSR_REGSEL_16                          (0x00000010)          /* xPSR/flags, execution state information, and exception number */
+#define COREDEBUG_DCRSR_REGSEL_17                          (0x00000011)          /* MSP (Main SP) */
+#define COREDEBUG_DCRSR_REGSEL_18                          (0x00000012)          /* PSP (Process SP) */
+#define COREDEBUG_DCRSR_REGSEL_20                          (0x00000014)          /* CONTROL bits [31:24], FAULTMASK bits [23:16], BASEPRI bits [15:8], PRIMASK bits [7:0] */
+/* COREDEBUG_DCRSR[COREDEBUG_DCRSR_REGWNR] Bits */
+#define COREDEBUG_DCRSR_REGWNR_OFS                         (16)                  /* REGWNR Offset */
+#define COREDEBUG_DCRSR_REGWNR                             (0x00010000)          /*  */
+/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_VC_CORERESET] Bits */
+#define COREDEBUG_DEMCR_VC_CORERESET_OFS                   ( 0)                  /* VC_CORERESET Offset */
+#define COREDEBUG_DEMCR_VC_CORERESET                       (0x00000001)          /*  */
+/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_VC_MMERR] Bits */
+#define COREDEBUG_DEMCR_VC_MMERR_OFS                       ( 4)                  /* VC_MMERR Offset */
+#define COREDEBUG_DEMCR_VC_MMERR                           (0x00000010)          /*  */
+/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_VC_NOCPERR] Bits */
+#define COREDEBUG_DEMCR_VC_NOCPERR_OFS                     ( 5)                  /* VC_NOCPERR Offset */
+#define COREDEBUG_DEMCR_VC_NOCPERR                         (0x00000020)          /*  */
+/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_VC_CHKERR] Bits */
+#define COREDEBUG_DEMCR_VC_CHKERR_OFS                      ( 6)                  /* VC_CHKERR Offset */
+#define COREDEBUG_DEMCR_VC_CHKERR                          (0x00000040)          /*  */
+/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_VC_STATERR] Bits */
+#define COREDEBUG_DEMCR_VC_STATERR_OFS                     ( 7)                  /* VC_STATERR Offset */
+#define COREDEBUG_DEMCR_VC_STATERR                         (0x00000080)          /*  */
+/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_VC_BUSERR] Bits */
+#define COREDEBUG_DEMCR_VC_BUSERR_OFS                      ( 8)                  /* VC_BUSERR Offset */
+#define COREDEBUG_DEMCR_VC_BUSERR                          (0x00000100)          /*  */
+/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_VC_INTERR] Bits */
+#define COREDEBUG_DEMCR_VC_INTERR_OFS                      ( 9)                  /* VC_INTERR Offset */
+#define COREDEBUG_DEMCR_VC_INTERR                          (0x00000200)          /*  */
+/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_VC_HARDERR] Bits */
+#define COREDEBUG_DEMCR_VC_HARDERR_OFS                     (10)                  /* VC_HARDERR Offset */
+#define COREDEBUG_DEMCR_VC_HARDERR                         (0x00000400)          /*  */
+/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_MON_EN] Bits */
+#define COREDEBUG_DEMCR_MON_EN_OFS                         (16)                  /* MON_EN Offset */
+#define COREDEBUG_DEMCR_MON_EN                             (0x00010000)          /*  */
+/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_MON_PEND] Bits */
+#define COREDEBUG_DEMCR_MON_PEND_OFS                       (17)                  /* MON_PEND Offset */
+#define COREDEBUG_DEMCR_MON_PEND                           (0x00020000)          /*  */
+/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_MON_STEP] Bits */
+#define COREDEBUG_DEMCR_MON_STEP_OFS                       (18)                  /* MON_STEP Offset */
+#define COREDEBUG_DEMCR_MON_STEP                           (0x00040000)          /*  */
+/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_MON_REQ] Bits */
+#define COREDEBUG_DEMCR_MON_REQ_OFS                        (19)                  /* MON_REQ Offset */
+#define COREDEBUG_DEMCR_MON_REQ                            (0x00080000)          /*  */
+/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_TRCENA] Bits */
+#define COREDEBUG_DEMCR_TRCENA_OFS                         (24)                  /* TRCENA Offset */
+#define COREDEBUG_DEMCR_TRCENA                             (0x01000000)          /*  */
+
+
+//*****************************************************************************
+// CRC32 Bits
+//*****************************************************************************
+
+
+//*****************************************************************************
+// CS Bits
+//*****************************************************************************
+/* CSKEY[CSKEY] Bits */
+#define CSKEY_OFS                                          ( 0)                  /* CSKEY Offset */
+#define CSKEY_M                                            (0x0000ffff)          /* Write xxxx_695Ah to unlock */
+/* CSCTL0[DCOTUNE] Bits */
+#define DCOTUNE_OFS                                        ( 0)                  /* DCOTUNE Offset */
+#define DCOTUNE_M                                          (0x00001fff)          /* DCO frequency tuning select */
+/* CSCTL0[DCORSEL] Bits */
+#define DCORSEL_OFS                                        (16)                  /* DCORSEL Offset */
+#define DCORSEL_M                                          (0x00070000)          /* DCO frequency range select */
+#define DCORSEL0                                           (0x00010000)          /* DCO frequency range select */
+#define DCORSEL1                                           (0x00020000)          /* DCO frequency range select */
+#define DCORSEL2                                           (0x00040000)          /* DCO frequency range select */
+#define DCORSEL_0                                          (0x00000000)          /* Nominal DCO Frequency Range (MHz): 1 to 2 */
+#define DCORSEL_1                                          (0x00010000)          /* Nominal DCO Frequency Range (MHz): 2 to 4 */
+#define DCORSEL_2                                          (0x00020000)          /* Nominal DCO Frequency Range (MHz): 4 to 8 */
+#define DCORSEL_3                                          (0x00030000)          /* Nominal DCO Frequency Range (MHz): 8 to 16 */
+#define DCORSEL_4                                          (0x00040000)          /* Nominal DCO Frequency Range (MHz): 16 to 32 */
+#define DCORSEL_5                                          (0x00050000)          /* Nominal DCO Frequency Range (MHz): 32 to 64 */
+/* CSCTL0[DCORES] Bits */
+#define DCORES_OFS                                         (22)                  /* DCORES Offset */
+#define DCORES                                             (0x00400000)          /* Enables the DCO external resistor mode */
+/* CSCTL0[DCOEN] Bits */
+#define DCOEN_OFS                                          (23)                  /* DCOEN Offset */
+#define DCOEN                                              (0x00800000)          /* Enables the DCO oscillator */
+/* CSCTL0[DIS_DCO_DELAY_CNT] Bits */
+#define DIS_DCO_DELAY_CNT_OFS                              (24)                  /* DIS_DCO_DELAY_CNT Offset */
+#define DIS_DCO_DELAY_CNT                                  (0x01000000)          /*  */
+/* CSCTL1[SELM] Bits */
+#define SELM_OFS                                           ( 0)                  /* SELM Offset */
+#define SELM_M                                             (0x00000007)          /* Selects the MCLK source */
+#define SELM0                                              (0x00000001)          /* Selects the MCLK source */
+#define SELM1                                              (0x00000002)          /* Selects the MCLK source */
+#define SELM2                                              (0x00000004)          /* Selects the MCLK source */
+#define SELM_0                                             (0x00000000)          /* when LFXT available, otherwise REFOCLK */
+#define SELM_1                                             (0x00000001)          /*  */
+#define SELM_2                                             (0x00000002)          /*  */
+#define SELM_3                                             (0x00000003)          /*  */
+#define SELM_4                                             (0x00000004)          /*  */
+#define SELM_5                                             (0x00000005)          /* when HFXT available, otherwise DCOCLK */
+#define SELM_6                                             (0x00000006)          /* when HFXT2 available, otherwise DCOCLK */
+#define SELM__LFXTCLK                                      (0x00000000)          /* when LFXT available, otherwise REFOCLK */
+#define SELM__VLOCLK                                       (0x00000001)          /*  */
+#define SELM__REFOCLK                                      (0x00000002)          /*  */
+#define SELM__DCOCLK                                       (0x00000003)          /*  */
+#define SELM__MODOSC                                       (0x00000004)          /*  */
+#define SELM__HFXTCLK                                      (0x00000005)          /* when HFXT available, otherwise DCOCLK */
+#define SELM__HFXT2CLK                                     (0x00000006)          /* when HFXT2 available, otherwise DCOCLK */
+#define SELM_7                                             (0x00000007)          /* for future use. Defaults to DCOCLK. Not recommended for use  to ensure future compatibilities. */
+/* CSCTL1[SELS] Bits */
+#define SELS_OFS                                           ( 4)                  /* SELS Offset */
+#define SELS_M                                             (0x00000070)          /* Selects the SMCLK and HSMCLK source */
+#define SELS0                                              (0x00000010)          /* Selects the SMCLK and HSMCLK source */
+#define SELS1                                              (0x00000020)          /* Selects the SMCLK and HSMCLK source */
+#define SELS2                                              (0x00000040)          /* Selects the SMCLK and HSMCLK source */
+#define SELS_0                                             (0x00000000)          /* when LFXT available, otherwise REFOCLK */
+#define SELS_1                                             (0x00000010)          /*  */
+#define SELS_2                                             (0x00000020)          /*  */
+#define SELS_3                                             (0x00000030)          /*  */
+#define SELS_4                                             (0x00000040)          /*  */
+#define SELS_5                                             (0x00000050)          /* when HFXT available, otherwise DCOCLK */
+#define SELS_6                                             (0x00000060)          /* when HFXT2 available, otherwise DCOCLK */
+#define SELS__LFXTCLK                                      (0x00000000)          /* when LFXT available, otherwise REFOCLK */
+#define SELS__VLOCLK                                       (0x00000010)          /*  */
+#define SELS__REFOCLK                                      (0x00000020)          /*  */
+#define SELS__DCOCLK                                       (0x00000030)          /*  */
+#define SELS__MODOSC                                       (0x00000040)          /*  */
+#define SELS__HFXTCLK                                      (0x00000050)          /* when HFXT available, otherwise DCOCLK */
+#define SELS__HFXT2CLK                                     (0x00000060)          /* when HFXT2 available, otherwise DCOCLK */
+#define SELS_7                                             (0x00000070)          /* for furture use. Defaults to DCOCLK. Do not use to ensure future compatibilities. */
+/* CSCTL1[SELA] Bits */
+#define SELA_OFS                                           ( 8)                  /* SELA Offset */
+#define SELA_M                                             (0x00000700)          /* Selects the ACLK source */
+#define SELA0                                              (0x00000100)          /* Selects the ACLK source */
+#define SELA1                                              (0x00000200)          /* Selects the ACLK source */
+#define SELA2                                              (0x00000400)          /* Selects the ACLK source */
+#define SELA_0                                             (0x00000000)          /* when LFXT available, otherwise REFOCLK */
+#define SELA_1                                             (0x00000100)          /*  */
+#define SELA_2                                             (0x00000200)          /*  */
+#define SELA__LFXTCLK                                      (0x00000000)          /* when LFXT available, otherwise REFOCLK */
+#define SELA__VLOCLK                                       (0x00000100)          /*  */
+#define SELA__REFOCLK                                      (0x00000200)          /*  */
+#define SELA_3                                             (0x00000300)          /* for future use. Defaults to REFOCLK. Not recommended  for use to ensure future compatibilities. */
+#define SELA_4                                             (0x00000400)          /* for future use. Defaults to REFOCLK. Not recommended  for use to ensure future compatibilities. */
+#define SELA_5                                             (0x00000500)          /* for future use. Defaults to REFOCLK. Not recommended  for use to ensure future compatibilities. */
+#define SELA_6                                             (0x00000600)          /* for future use. Defaults to REFOCLK. Not recommended  for use to ensure future compatibilities. */
+#define SELA_7                                             (0x00000700)          /* for future use. Defaults to REFOCLK. Not recommended  for use to ensure future compatibilities. */
+/* CSCTL1[SELB] Bits */
+#define SELB_OFS                                           (12)                  /* SELB Offset */
+#define SELB                                               (0x00001000)          /* Selects the BCLK source */
+/* CSCTL1[DIVM] Bits */
+#define DIVM_OFS                                           (16)                  /* DIVM Offset */
+#define DIVM_M                                             (0x00070000)          /* MCLK source divider */
+#define DIVM0                                              (0x00010000)          /* MCLK source divider */
+#define DIVM1                                              (0x00020000)          /* MCLK source divider */
+#define DIVM2                                              (0x00040000)          /* MCLK source divider */
+#define DIVM_0                                             (0x00000000)          /* f(MCLK)/1 */
+#define DIVM_1                                             (0x00010000)          /* f(MCLK)/2 */
+#define DIVM_2                                             (0x00020000)          /* f(MCLK)/4 */
+#define DIVM_3                                             (0x00030000)          /* f(MCLK)/8 */
+#define DIVM_4                                             (0x00040000)          /* f(MCLK)/16 */
+#define DIVM_5                                             (0x00050000)          /* f(MCLK)/32 */
+#define DIVM_6                                             (0x00060000)          /* f(MCLK)/64 */
+#define DIVM_7                                             (0x00070000)          /* f(MCLK)/128 */
+#define DIVM__1                                            (0x00000000)          /* f(MCLK)/1 */
+#define DIVM__2                                            (0x00010000)          /* f(MCLK)/2 */
+#define DIVM__4                                            (0x00020000)          /* f(MCLK)/4 */
+#define DIVM__8                                            (0x00030000)          /* f(MCLK)/8 */
+#define DIVM__16                                           (0x00040000)          /* f(MCLK)/16 */
+#define DIVM__32                                           (0x00050000)          /* f(MCLK)/32 */
+#define DIVM__64                                           (0x00060000)          /* f(MCLK)/64 */
+#define DIVM__128                                          (0x00070000)          /* f(MCLK)/128 */
+/* CSCTL1[DIVHS] Bits */
+#define DIVHS_OFS                                          (20)                  /* DIVHS Offset */
+#define DIVHS_M                                            (0x00700000)          /* HSMCLK source divider */
+#define DIVHS0                                             (0x00100000)          /* HSMCLK source divider */
+#define DIVHS1                                             (0x00200000)          /* HSMCLK source divider */
+#define DIVHS2                                             (0x00400000)          /* HSMCLK source divider */
+#define DIVHS_0                                            (0x00000000)          /* f(HSMCLK)/1 */
+#define DIVHS_1                                            (0x00100000)          /* f(HSMCLK)/2 */
+#define DIVHS_2                                            (0x00200000)          /* f(HSMCLK)/4 */
+#define DIVHS_3                                            (0x00300000)          /* f(HSMCLK)/8 */
+#define DIVHS_4                                            (0x00400000)          /* f(HSMCLK)/16 */
+#define DIVHS_5                                            (0x00500000)          /* f(HSMCLK)/32 */
+#define DIVHS_6                                            (0x00600000)          /* f(HSMCLK)/64 */
+#define DIVHS_7                                            (0x00700000)          /* f(HSMCLK)/128 */
+#define DIVHS__1                                           (0x00000000)          /* f(HSMCLK)/1 */
+#define DIVHS__2                                           (0x00100000)          /* f(HSMCLK)/2 */
+#define DIVHS__4                                           (0x00200000)          /* f(HSMCLK)/4 */
+#define DIVHS__8                                           (0x00300000)          /* f(HSMCLK)/8 */
+#define DIVHS__16                                          (0x00400000)          /* f(HSMCLK)/16 */
+#define DIVHS__32                                          (0x00500000)          /* f(HSMCLK)/32 */
+#define DIVHS__64                                          (0x00600000)          /* f(HSMCLK)/64 */
+#define DIVHS__128                                         (0x00700000)          /* f(HSMCLK)/128 */
+/* CSCTL1[DIVA] Bits */
+#define DIVA_OFS                                           (24)                  /* DIVA Offset */
+#define DIVA_M                                             (0x07000000)          /* ACLK source divider */
+#define DIVA0                                              (0x01000000)          /* ACLK source divider */
+#define DIVA1                                              (0x02000000)          /* ACLK source divider */
+#define DIVA2                                              (0x04000000)          /* ACLK source divider */
+#define DIVA_0                                             (0x00000000)          /* f(ACLK)/1 */
+#define DIVA_1                                             (0x01000000)          /* f(ACLK)/2 */
+#define DIVA_2                                             (0x02000000)          /* f(ACLK)/4 */
+#define DIVA_3                                             (0x03000000)          /* f(ACLK)/8 */
+#define DIVA_4                                             (0x04000000)          /* f(ACLK)/16 */
+#define DIVA_5                                             (0x05000000)          /* f(ACLK)/32 */
+#define DIVA_6                                             (0x06000000)          /* f(ACLK)/64 */
+#define DIVA_7                                             (0x07000000)          /* f(ACLK)/128 */
+#define DIVA__1                                            (0x00000000)          /* f(ACLK)/1 */
+#define DIVA__2                                            (0x01000000)          /* f(ACLK)/2 */
+#define DIVA__4                                            (0x02000000)          /* f(ACLK)/4 */
+#define DIVA__8                                            (0x03000000)          /* f(ACLK)/8 */
+#define DIVA__16                                           (0x04000000)          /* f(ACLK)/16 */
+#define DIVA__32                                           (0x05000000)          /* f(ACLK)/32 */
+#define DIVA__64                                           (0x06000000)          /* f(ACLK)/64 */
+#define DIVA__128                                          (0x07000000)          /* f(ACLK)/128 */
+/* CSCTL1[DIVS] Bits */
+#define DIVS_OFS                                           (28)                  /* DIVS Offset */
+#define DIVS_M                                             (0x70000000)          /* SMCLK source divider */
+#define DIVS0                                              (0x10000000)          /* SMCLK source divider */
+#define DIVS1                                              (0x20000000)          /* SMCLK source divider */
+#define DIVS2                                              (0x40000000)          /* SMCLK source divider */
+#define DIVS_0                                             (0x00000000)          /* f(SMCLK)/1 */
+#define DIVS_1                                             (0x10000000)          /* f(SMCLK)/2 */
+#define DIVS_2                                             (0x20000000)          /* f(SMCLK)/4 */
+#define DIVS_3                                             (0x30000000)          /* f(SMCLK)/8 */
+#define DIVS_4                                             (0x40000000)          /* f(SMCLK)/16 */
+#define DIVS_5                                             (0x50000000)          /* f(SMCLK)/32 */
+#define DIVS_6                                             (0x60000000)          /* f(SMCLK)/64 */
+#define DIVS_7                                             (0x70000000)          /* f(SMCLK)/128 */
+#define DIVS__1                                            (0x00000000)          /* f(SMCLK)/1 */
+#define DIVS__2                                            (0x10000000)          /* f(SMCLK)/2 */
+#define DIVS__4                                            (0x20000000)          /* f(SMCLK)/4 */
+#define DIVS__8                                            (0x30000000)          /* f(SMCLK)/8 */
+#define DIVS__16                                           (0x40000000)          /* f(SMCLK)/16 */
+#define DIVS__32                                           (0x50000000)          /* f(SMCLK)/32 */
+#define DIVS__64                                           (0x60000000)          /* f(SMCLK)/64 */
+#define DIVS__128                                          (0x70000000)          /* f(SMCLK)/128 */
+/* CSCTL2[LFXTDRIVE] Bits */
+#define LFXTDRIVE_OFS                                      ( 0)                  /* LFXTDRIVE Offset */
+#define LFXTDRIVE_M                                        (0x00000007)          /* LFXT oscillator current can be adjusted to its drive needs */
+#define LFXTDRIVE0                                         (0x00000001)          /* LFXT oscillator current can be adjusted to its drive needs */
+#define LFXTDRIVE1                                         (0x00000002)          /* LFXT oscillator current can be adjusted to its drive needs */
+#define LFXTDRIVE2                                         (0x00000004)          /* LFXT oscillator current can be adjusted to its drive needs */
+#define LFXTDRIVE_0                                        (0x00000000)          /* Lowest current consumption. */
+#define LFXTDRIVE_1                                        (0x00000001)          /* Increased drive strength LFXT oscillator. */
+#define LFXTDRIVE_2                                        (0x00000002)          /* Increased drive strength LFXT oscillator. */
+#define LFXTDRIVE_3                                        (0x00000003)          /* Increased drive strength LFXT oscillator. */
+#define LFXTDRIVE_4                                        (0x00000004)          /* Increased drive strength LFXT oscillator. */
+#define LFXTDRIVE_5                                        (0x00000005)          /* Increased drive strength LFXT oscillator. */
+#define LFXTDRIVE_6                                        (0x00000006)          /* Increased drive strength LFXT oscillator. */
+#define LFXTDRIVE_7                                        (0x00000007)          /* Maximum drive strength LFXT oscillator. */
+/* CSCTL2[LFXTAGCOFF] Bits */
+#define LFXTAGCOFF_OFS                                     ( 7)                  /* LFXTAGCOFF Offset */
+#define LFXTAGCOFF                                         (0x00000080)          /* Disables the automatic gain control of the LFXT crystal */
+/* CSCTL2[LFXT_EN] Bits */
+#define LFXT_EN_OFS                                        ( 8)                  /* LFXT_EN Offset */
+#define LFXT_EN                                            (0x00000100)          /* Turns on the LFXT oscillator regardless if used as a clock resource */
+/* CSCTL2[LFXTBYPASS] Bits */
+#define LFXTBYPASS_OFS                                     ( 9)                  /* LFXTBYPASS Offset */
+#define LFXTBYPASS                                         (0x00000200)          /* LFXT bypass select */
+/* CSCTL2[HFXTDRIVE] Bits */
+#define HFXTDRIVE_OFS                                      (16)                  /* HFXTDRIVE Offset */
+#define HFXTDRIVE                                          (0x00010000)          /* HFXT oscillator drive selection */
+/* CSCTL2[HFXTFREQ] Bits */
+#define HFXTFREQ_OFS                                       (20)                  /* HFXTFREQ Offset */
+#define HFXTFREQ_M                                         (0x00700000)          /* HFXT frequency selection */
+#define HFXTFREQ0                                          (0x00100000)          /* HFXT frequency selection */
+#define HFXTFREQ1                                          (0x00200000)          /* HFXT frequency selection */
+#define HFXTFREQ2                                          (0x00400000)          /* HFXT frequency selection */
+#define HFXTFREQ_0                                         (0x00000000)          /* 1 MHz to 4 MHz */
+#define HFXTFREQ_1                                         (0x00100000)          /* >4 MHz to 8 MHz */
+#define HFXTFREQ_2                                         (0x00200000)          /* >8 MHz to 16 MHz */
+#define HFXTFREQ_3                                         (0x00300000)          /* >16 MHz to 24 MHz */
+#define HFXTFREQ_4                                         (0x00400000)          /* >24 MHz to 32 MHz */
+#define HFXTFREQ_5                                         (0x00500000)          /* >32 MHz to 40 MHz */
+#define HFXTFREQ_6                                         (0x00600000)          /* >40 MHz to 48 MHz */
+/* CSCTL2[HFXT_EN] Bits */
+#define HFXT_EN_OFS                                        (24)                  /* HFXT_EN Offset */
+#define HFXT_EN                                            (0x01000000)          /* Turns on the HFXT oscillator regardless if used as a clock resource */
+/* CSCTL2[HFXTBYPASS] Bits */
+#define HFXTBYPASS_OFS                                     (25)                  /* HFXTBYPASS Offset */
+#define HFXTBYPASS                                         (0x02000000)          /* HFXT bypass select */
+/* CSCTL3[FCNTLF] Bits */
+#define FCNTLF_OFS                                         ( 0)                  /* FCNTLF Offset */
+#define FCNTLF_M                                           (0x00000003)          /* Start flag counter for LFXT */
+#define FCNTLF0                                            (0x00000001)          /* Start flag counter for LFXT */
+#define FCNTLF1                                            (0x00000002)          /* Start flag counter for LFXT */
+#define FCNTLF_0                                           (0x00000000)          /* 4096 cycles */
+#define FCNTLF_1                                           (0x00000001)          /* 8192 cycles */
+#define FCNTLF_2                                           (0x00000002)          /* 16384 cycles */
+#define FCNTLF_3                                           (0x00000003)          /* 32768 cycles */
+#define FCNTLF__4096                                       (0x00000000)          /* 4096 cycles */
+#define FCNTLF__8192                                       (0x00000001)          /* 8192 cycles */
+#define FCNTLF__16384                                      (0x00000002)          /* 16384 cycles */
+#define FCNTLF__32768                                      (0x00000003)          /* 32768 cycles */
+/* CSCTL3[RFCNTLF] Bits */
+#define RFCNTLF_OFS                                        ( 2)                  /* RFCNTLF Offset */
+#define RFCNTLF                                            (0x00000004)          /* Reset start fault counter for LFXT */
+/* CSCTL3[FCNTLF_EN] Bits */
+#define FCNTLF_EN_OFS                                      ( 3)                  /* FCNTLF_EN Offset */
+#define FCNTLF_EN                                          (0x00000008)          /* Enable start fault counter for LFXT */
+/* CSCTL3[FCNTHF] Bits */
+#define FCNTHF_OFS                                         ( 4)                  /* FCNTHF Offset */
+#define FCNTHF_M                                           (0x00000030)          /* Start flag counter for HFXT */
+#define FCNTHF0                                            (0x00000010)          /* Start flag counter for HFXT */
+#define FCNTHF1                                            (0x00000020)          /* Start flag counter for HFXT */
+#define FCNTHF_0                                           (0x00000000)          /* 2048 cycles */
+#define FCNTHF_1                                           (0x00000010)          /* 4096 cycles */
+#define FCNTHF_2                                           (0x00000020)          /* 8192 cycles */
+#define FCNTHF_3                                           (0x00000030)          /* 16384 cycles */
+#define FCNTHF__2048                                       (0x00000000)          /* 2048 cycles */
+#define FCNTHF__4096                                       (0x00000010)          /* 4096 cycles */
+#define FCNTHF__8192                                       (0x00000020)          /* 8192 cycles */
+#define FCNTHF__16384                                      (0x00000030)          /* 16384 cycles */
+/* CSCTL3[RFCNTHF] Bits */
+#define RFCNTHF_OFS                                        ( 6)                  /* RFCNTHF Offset */
+#define RFCNTHF                                            (0x00000040)          /* Reset start fault counter for HFXT */
+/* CSCTL3[FCNTHF_EN] Bits */
+#define FCNTHF_EN_OFS                                      ( 7)                  /* FCNTHF_EN Offset */
+#define FCNTHF_EN                                          (0x00000080)          /* Enable start fault counter for HFXT */
+/* CSCTL3[FCNTHF2] Bits */
+#define FCNTHF2_OFS                                        ( 8)                  /* FCNTHF2 Offset */
+#define FCNTHF2_M                                          (0x00000300)          /* Start flag counter for HFXT2 */
+#define FCNTHF20                                           (0x00000100)          /* Start flag counter for HFXT2 */
+#define FCNTHF21                                           (0x00000200)          /* Start flag counter for HFXT2 */
+#define FCNTHF2_0                                          (0x00000000)          /* 2048 cycles */
+#define FCNTHF2_1                                          (0x00000100)          /* 4096 cycles */
+#define FCNTHF2_2                                          (0x00000200)          /* 8192 cycles */
+#define FCNTHF2_3                                          (0x00000300)          /* 16384 cycles */
+#define FCNTHF2__2048                                      (0x00000000)          /* 2048 cycles */
+#define FCNTHF2__4096                                      (0x00000100)          /* 4096 cycles */
+#define FCNTHF2__8192                                      (0x00000200)          /* 8192 cycles */
+#define FCNTHF2__16384                                     (0x00000300)          /* 16384 cycles */
+/* CSCTL3[RFCNTHF2] Bits */
+#define RFCNTHF2_OFS                                       (10)                  /* RFCNTHF2 Offset */
+#define RFCNTHF2                                           (0x00000400)          /* Reset start fault counter for HFXT2 */
+/* CSCTL3[FCNTHF2_EN] Bits */
+#define FCNTHF2_EN_OFS                                     (11)                  /* FCNTHF2_EN Offset */
+#define FCNTHF2_EN                                         (0x00000800)          /* Enable start fault counter for HFXT2 */
+/* CSCTL4[HFXT2DRIVE] Bits */
+#define HFXT2DRIVE_OFS                                     ( 0)                  /* HFXT2DRIVE Offset */
+#define HFXT2DRIVE_M                                       (0x00000007)          /* HFXT2 oscillator current can be adjusted to its drive needs */
+#define HFXT2DRIVE0                                        (0x00000001)          /* HFXT2 oscillator current can be adjusted to its drive needs */
+#define HFXT2DRIVE1                                        (0x00000002)          /* HFXT2 oscillator current can be adjusted to its drive needs */
+#define HFXT2DRIVE2                                        (0x00000004)          /* HFXT2 oscillator current can be adjusted to its drive needs */
+#define HFXT2DRIVE_0                                       (0x00000000)          /* Lowest current consumption */
+#define HFXT2DRIVE_1                                       (0x00000001)          /* Increased drive strength HFXT2 oscillator */
+#define HFXT2DRIVE_2                                       (0x00000002)          /* Increased drive strength HFXT2 oscillator */
+#define HFXT2DRIVE_3                                       (0x00000003)          /* Increased drive strength HFXT2 oscillator */
+#define HFXT2DRIVE_4                                       (0x00000004)          /* Increased drive strength HFXT2 oscillator */
+#define HFXT2DRIVE_5                                       (0x00000005)          /* Increased drive strength HFXT2 oscillator */
+#define HFXT2DRIVE_6                                       (0x00000006)          /* Increased drive strength HFXT2 oscillator */
+#define HFXT2DRIVE_7                                       (0x00000007)          /* Maximum drive strength HFXT2 oscillator */
+/* CSCTL4[HFXT2FREQ] Bits */
+#define HFXT2FREQ_OFS                                      ( 4)                  /* HFXT2FREQ Offset */
+#define HFXT2FREQ_M                                        (0x00000070)          /* HFXT2 frequency selection */
+/* CSCTL4[HFXT2_EN] Bits */
+#define HFXT2_EN_OFS                                       ( 8)                  /* HFXT2_EN Offset */
+#define HFXT2_EN                                           (0x00000100)          /* Turns on the HFXT2 oscillator */
+/* CSCTL4[HFXT2BYPASS] Bits */
+#define HFXT2BYPASS_OFS                                    ( 9)                  /* HFXT2BYPASS Offset */
+#define HFXT2BYPASS                                        (0x00000200)          /* HFXT2 bypass select */
+/* CSCTL5[REFCNTSEL] Bits */
+#define REFCNTSEL_OFS                                      ( 0)                  /* REFCNTSEL Offset */
+#define REFCNTSEL_M                                        (0x00000007)          /* Reference counter source select */
+/* CSCTL5[REFCNTPS] Bits */
+#define REFCNTPS_OFS                                       ( 3)                  /* REFCNTPS Offset */
+#define REFCNTPS_M                                         (0x00000038)          /* Reference clock prescaler */
+/* CSCTL5[CALSTART] Bits */
+#define CALSTART_OFS                                       ( 7)                  /* CALSTART Offset */
+#define CALSTART                                           (0x00000080)          /* Start clock calibration counters */
+/* CSCTL5[PERCNTSEL] Bits */
+#define PERCNTSEL_OFS                                      ( 8)                  /* PERCNTSEL Offset */
+#define PERCNTSEL_M                                        (0x00000700)          /* Period counter source select */
+/* CSCTL6[PERCNT] Bits */
+#define PERCNT_OFS                                         ( 0)                  /* PERCNT Offset */
+#define PERCNT_M                                           (0x0000ffff)          /* Calibration period counter */
+/* CSCTL7[REFCNT] Bits */
+#define REFCNT_OFS                                         ( 0)                  /* REFCNT Offset */
+#define REFCNT_M                                           (0x0000ffff)          /* Calibration reference period counter */
+/* CSCLKEN[ACLK_EN] Bits */
+#define ACLK_EN_OFS                                        ( 0)                  /* ACLK_EN Offset */
+#define ACLK_EN                                            (0x00000001)          /* ACLK system clock conditional request enable */
+/* CSCLKEN[MCLK_EN] Bits */
+#define MCLK_EN_OFS                                        ( 1)                  /* MCLK_EN Offset */
+#define MCLK_EN                                            (0x00000002)          /* MCLK system clock conditional request enable */
+/* CSCLKEN[HSMCLK_EN] Bits */
+#define HSMCLK_EN_OFS                                      ( 2)                  /* HSMCLK_EN Offset */
+#define HSMCLK_EN                                          (0x00000004)          /* HSMCLK system clock conditional request enable */
+/* CSCLKEN[SMCLK_EN] Bits */
+#define SMCLK_EN_OFS                                       ( 3)                  /* SMCLK_EN Offset */
+#define SMCLK_EN                                           (0x00000008)          /* SMCLK system clock conditional request enable */
+/* CSCLKEN[VLO_EN] Bits */
+#define VLO_EN_OFS                                         ( 8)                  /* VLO_EN Offset */
+#define VLO_EN                                             (0x00000100)          /* Turns on the VLO oscillator */
+/* CSCLKEN[REFO_EN] Bits */
+#define REFO_EN_OFS                                        ( 9)                  /* REFO_EN Offset */
+#define REFO_EN                                            (0x00000200)          /* Turns on the REFO oscillator */
+/* CSCLKEN[MODOSC_EN] Bits */
+#define MODOSC_EN_OFS                                      (10)                  /* MODOSC_EN Offset */
+#define MODOSC_EN                                          (0x00000400)          /* Turns on the MODOSC oscillator */
+/* CSCLKEN[REFOFSEL] Bits */
+#define REFOFSEL_OFS                                       (15)                  /* REFOFSEL Offset */
+#define REFOFSEL                                           (0x00008000)          /* Selects REFO nominal frequency */
+/* CSSTAT[DCO_ON] Bits */
+#define DCO_ON_OFS                                         ( 0)                  /* DCO_ON Offset */
+#define DCO_ON                                             (0x00000001)          /* DCO status */
+/* CSSTAT[DCOBIAS_ON] Bits */
+#define DCOBIAS_ON_OFS                                     ( 1)                  /* DCOBIAS_ON Offset */
+#define DCOBIAS_ON                                         (0x00000002)          /* DCO bias status */
+/* CSSTAT[HFXT_ON] Bits */
+#define HFXT_ON_OFS                                        ( 2)                  /* HFXT_ON Offset */
+#define HFXT_ON                                            (0x00000004)          /* HFXT status */
+/* CSSTAT[HFXT2_ON] Bits */
+#define HFXT2_ON_OFS                                       ( 3)                  /* HFXT2_ON Offset */
+#define HFXT2_ON                                           (0x00000008)          /* HFXT2 status */
+/* CSSTAT[MODOSC_ON] Bits */
+#define MODOSC_ON_OFS                                      ( 4)                  /* MODOSC_ON Offset */
+#define MODOSC_ON                                          (0x00000010)          /* MODOSC status */
+/* CSSTAT[VLO_ON] Bits */
+#define VLO_ON_OFS                                         ( 5)                  /* VLO_ON Offset */
+#define VLO_ON                                             (0x00000020)          /* VLO status */
+/* CSSTAT[LFXT_ON] Bits */
+#define LFXT_ON_OFS                                        ( 6)                  /* LFXT_ON Offset */
+#define LFXT_ON                                            (0x00000040)          /* LFXT status */
+/* CSSTAT[REFO_ON] Bits */
+#define REFO_ON_OFS                                        ( 7)                  /* REFO_ON Offset */
+#define REFO_ON                                            (0x00000080)          /* REFO status */
+/* CSSTAT[ACLK_ON] Bits */
+#define ACLK_ON_OFS                                        (16)                  /* ACLK_ON Offset */
+#define ACLK_ON                                            (0x00010000)          /* ACLK system clock status */
+/* CSSTAT[MCLK_ON] Bits */
+#define MCLK_ON_OFS                                        (17)                  /* MCLK_ON Offset */
+#define MCLK_ON                                            (0x00020000)          /* MCLK system clock status */
+/* CSSTAT[HSMCLK_ON] Bits */
+#define HSMCLK_ON_OFS                                      (18)                  /* HSMCLK_ON Offset */
+#define HSMCLK_ON                                          (0x00040000)          /* HSMCLK system clock status */
+/* CSSTAT[SMCLK_ON] Bits */
+#define SMCLK_ON_OFS                                       (19)                  /* SMCLK_ON Offset */
+#define SMCLK_ON                                           (0x00080000)          /* SMCLK system clock status */
+/* CSSTAT[MODCLK_ON] Bits */
+#define MODCLK_ON_OFS                                      (20)                  /* MODCLK_ON Offset */
+#define MODCLK_ON                                          (0x00100000)          /* MODCLK system clock status */
+/* CSSTAT[VLOCLK_ON] Bits */
+#define VLOCLK_ON_OFS                                      (21)                  /* VLOCLK_ON Offset */
+#define VLOCLK_ON                                          (0x00200000)          /* VLOCLK system clock status */
+/* CSSTAT[LFXTCLK_ON] Bits */
+#define LFXTCLK_ON_OFS                                     (22)                  /* LFXTCLK_ON Offset */
+#define LFXTCLK_ON                                         (0x00400000)          /* LFXTCLK system clock status */
+/* CSSTAT[REFOCLK_ON] Bits */
+#define REFOCLK_ON_OFS                                     (23)                  /* REFOCLK_ON Offset */
+#define REFOCLK_ON                                         (0x00800000)          /* REFOCLK system clock status */
+/* CSSTAT[ACLK_READY] Bits */
+#define ACLK_READY_OFS                                     (24)                  /* ACLK_READY Offset */
+#define ACLK_READY                                         (0x01000000)          /* ACLK Ready status */
+/* CSSTAT[MCLK_READY] Bits */
+#define MCLK_READY_OFS                                     (25)                  /* MCLK_READY Offset */
+#define MCLK_READY                                         (0x02000000)          /* MCLK Ready status */
+/* CSSTAT[HSMCLK_READY] Bits */
+#define HSMCLK_READY_OFS                                   (26)                  /* HSMCLK_READY Offset */
+#define HSMCLK_READY                                       (0x04000000)          /* HSMCLK Ready status */
+/* CSSTAT[SMCLK_READY] Bits */
+#define SMCLK_READY_OFS                                    (27)                  /* SMCLK_READY Offset */
+#define SMCLK_READY                                        (0x08000000)          /* SMCLK Ready status */
+/* CSSTAT[BCLK_READY] Bits */
+#define BCLK_READY_OFS                                     (28)                  /* BCLK_READY Offset */
+#define BCLK_READY                                         (0x10000000)          /* BCLK Ready status */
+/* CSIE[LFXTIE] Bits */
+#define LFXTIE_OFS                                         ( 0)                  /* LFXTIE Offset */
+#define LFXTIE                                             (0x00000001)          /* LFXT oscillator fault flag interrupt enable */
+/* CSIE[HFXTIE] Bits */
+#define HFXTIE_OFS                                         ( 1)                  /* HFXTIE Offset */
+#define HFXTIE                                             (0x00000002)          /* HFXT oscillator fault flag interrupt enable */
+/* CSIE[HFXT2IE] Bits */
+#define HFXT2IE_OFS                                        ( 2)                  /* HFXT2IE Offset */
+#define HFXT2IE                                            (0x00000004)          /* HFXT2 oscillator fault flag interrupt enable */
+/* CSIE[DCOMINIE] Bits */
+#define DCOMINIE_OFS                                       ( 4)                  /* DCOMINIE Offset */
+#define DCOMINIE                                           (0x00000010)          /* DCO minimum fault flag interrupt enable */
+/* CSIE[DCOMAXIE] Bits */
+#define DCOMAXIE_OFS                                       ( 5)                  /* DCOMAXIE Offset */
+#define DCOMAXIE                                           (0x00000020)          /* DCO maximum fault flag interrupt enable */
+/* CSIE[DCORIE] Bits */
+#define DCORIE_OFS                                         ( 6)                  /* DCORIE Offset */
+#define DCORIE                                             (0x00000040)          /* DCO external resistor fault flag interrupt enable */
+/* CSIE[FCNTLFIE] Bits */
+#define FCNTLFIE_OFS                                       ( 8)                  /* FCNTLFIE Offset */
+#define FCNTLFIE                                           (0x00000100)          /* Start fault counter interrupt enable LFXT */
+/* CSIE[FCNTHFIE] Bits */
+#define FCNTHFIE_OFS                                       ( 9)                  /* FCNTHFIE Offset */
+#define FCNTHFIE                                           (0x00000200)          /* Start fault counter interrupt enable HFXT */
+/* CSIE[FCNTHF2IE] Bits */
+#define FCNTHF2IE_OFS                                      (10)                  /* FCNTHF2IE Offset */
+#define FCNTHF2IE                                          (0x00000400)          /* Start fault counter interrupt enable HFXT2 */
+/* CSIE[PLLOOLIE] Bits */
+#define PLLOOLIE_OFS                                       (12)                  /* PLLOOLIE Offset */
+#define PLLOOLIE                                           (0x00001000)          /* PLL out-of-lock interrupt enable */
+/* CSIE[PLLLOSIE] Bits */
+#define PLLLOSIE_OFS                                       (13)                  /* PLLLOSIE Offset */
+#define PLLLOSIE                                           (0x00002000)          /* PLL loss-of-signal interrupt enable */
+/* CSIE[PLLOORIE] Bits */
+#define PLLOORIE_OFS                                       (14)                  /* PLLOORIE Offset */
+#define PLLOORIE                                           (0x00004000)          /* PLL out-of-range interrupt enable */
+/* CSIE[CALIE] Bits */
+#define CALIE_OFS                                          (15)                  /* CALIE Offset */
+#define CALIE                                              (0x00008000)          /* REFCNT period counter interrupt enable */
+/* CSIFG[LFXTIFG] Bits */
+#define LFXTIFG_OFS                                        ( 0)                  /* LFXTIFG Offset */
+#define LFXTIFG                                            (0x00000001)          /* LFXT oscillator fault flag */
+/* CSIFG[HFXTIFG] Bits */
+#define HFXTIFG_OFS                                        ( 1)                  /* HFXTIFG Offset */
+#define HFXTIFG                                            (0x00000002)          /* HFXT oscillator fault flag */
+/* CSIFG[HFXT2IFG] Bits */
+#define HFXT2IFG_OFS                                       ( 2)                  /* HFXT2IFG Offset */
+#define HFXT2IFG                                           (0x00000004)          /* HFXT2 oscillator fault flag */
+/* CSIFG[DCOMINIFG] Bits */
+#define DCOMINIFG_OFS                                      ( 4)                  /* DCOMINIFG Offset */
+#define DCOMINIFG                                          (0x00000010)          /* DCO minimum fault flag */
+/* CSIFG[DCOMAXIFG] Bits */
+#define DCOMAXIFG_OFS                                      ( 5)                  /* DCOMAXIFG Offset */
+#define DCOMAXIFG                                          (0x00000020)          /* DCO maximum fault flag */
+/* CSIFG[DCORIFG] Bits */
+#define DCORIFG_OFS                                        ( 6)                  /* DCORIFG Offset */
+#define DCORIFG                                            (0x00000040)          /* DCO external resistor fault flag */
+/* CSIFG[FCNTLFIFG] Bits */
+#define FCNTLFIFG_OFS                                      ( 8)                  /* FCNTLFIFG Offset */
+#define FCNTLFIFG                                          (0x00000100)          /* Start fault counter interrupt flag LFXT */
+/* CSIFG[FCNTHFIFG] Bits */
+#define FCNTHFIFG_OFS                                      ( 9)                  /* FCNTHFIFG Offset */
+#define FCNTHFIFG                                          (0x00000200)          /* Start fault counter interrupt flag HFXT */
+/* CSIFG[FCNTHF2IFG] Bits */
+#define FCNTHF2IFG_OFS                                     (11)                  /* FCNTHF2IFG Offset */
+#define FCNTHF2IFG                                         (0x00000800)          /* Start fault counter interrupt flag HFXT2 */
+/* CSIFG[PLLOOLIFG] Bits */
+#define PLLOOLIFG_OFS                                      (12)                  /* PLLOOLIFG Offset */
+#define PLLOOLIFG                                          (0x00001000)          /* PLL out-of-lock interrupt flag */
+/* CSIFG[PLLLOSIFG] Bits */
+#define PLLLOSIFG_OFS                                      (13)                  /* PLLLOSIFG Offset */
+#define PLLLOSIFG                                          (0x00002000)          /* PLL loss-of-signal interrupt flag */
+/* CSIFG[PLLOORIFG] Bits */
+#define PLLOORIFG_OFS                                      (14)                  /* PLLOORIFG Offset */
+#define PLLOORIFG                                          (0x00004000)          /* PLL out-of-range interrupt flag */
+/* CSIFG[CALIFG] Bits */
+#define CALIFG_OFS                                         (15)                  /* CALIFG Offset */
+#define CALIFG                                             (0x00008000)          /* REFCNT period counter expired */
+/* CSCLRIFG[CLR_LFXTIFG] Bits */
+#define CLR_LFXTIFG_OFS                                    ( 0)                  /* CLR_LFXTIFG Offset */
+#define CLR_LFXTIFG                                        (0x00000001)          /* Clear LFXT oscillator fault interrupt flag */
+/* CSCLRIFG[CLR_HFXTIFG] Bits */
+#define CLR_HFXTIFG_OFS                                    ( 1)                  /* CLR_HFXTIFG Offset */
+#define CLR_HFXTIFG                                        (0x00000002)          /* Clear HFXT oscillator fault interrupt flag */
+/* CSCLRIFG[CLR_HFXT2IFG] Bits */
+#define CLR_HFXT2IFG_OFS                                   ( 2)                  /* CLR_HFXT2IFG Offset */
+#define CLR_HFXT2IFG                                       (0x00000004)          /* Clear HFXT2 oscillator fault interrupt flag */
+/* CSCLRIFG[CLR_DCOMAXIFG] Bits */
+#define CLR_DCOMAXIFG_OFS                                  ( 5)                  /* CLR_DCOMAXIFG Offset */
+#define CLR_DCOMAXIFG                                      (0x00000020)          /* Clear DCO maximum fault interrupt flag */
+/* CSCLRIFG[CLR_DCORIFG] Bits */
+#define CLR_DCORIFG_OFS                                    ( 6)                  /* CLR_DCORIFG Offset */
+#define CLR_DCORIFG                                        (0x00000040)          /* Clear DCO external resistor fault interrupt flag */
+/* CSCLRIFG[CLR_CALIFG] Bits */
+#define CLR_CALIFG_OFS                                     ( 7)                  /* CLR_CALIFG Offset */
+#define CLR_CALIFG                                         (0x00000080)          /* REFCNT period counter clear interrupt flag */
+/* CSCLRIFG[CLR_DCOMINIFG] Bits */
+#define CLR_DCOMINIFG_OFS                                  ( 4)                  /* CLR_DCOMINIFG Offset */
+#define CLR_DCOMINIFG                                      (0x00000010)          /* Clear DCO minimum fault interrupt flag */
+/* CSCLRIFG[CLR_FCNTLFIFG] Bits */
+#define CLR_FCNTLFIFG_OFS                                  ( 8)                  /* CLR_FCNTLFIFG Offset */
+#define CLR_FCNTLFIFG                                      (0x00000100)          /* Start fault counter clear interrupt flag LFXT */
+/* CSCLRIFG[CLR_FCNTHFIFG] Bits */
+#define CLR_FCNTHFIFG_OFS                                  ( 9)                  /* CLR_FCNTHFIFG Offset */
+#define CLR_FCNTHFIFG                                      (0x00000200)          /* Start fault counter clear interrupt flag HFXT */
+/* CSCLRIFG[CLR_FCNTHF2IFG] Bits */
+#define CLR_FCNTHF2IFG_OFS                                 (10)                  /* CLR_FCNTHF2IFG Offset */
+#define CLR_FCNTHF2IFG                                     (0x00000400)          /* Start fault counter clear interrupt flag HFXT2 */
+/* CSCLRIFG[CLR_PLLOOLIFG] Bits */
+#define CLR_PLLOOLIFG_OFS                                  (12)                  /* CLR_PLLOOLIFG Offset */
+#define CLR_PLLOOLIFG                                      (0x00001000)          /* PLL out-of-lock clear interrupt flag */
+/* CSCLRIFG[CLR_PLLLOSIFG] Bits */
+#define CLR_PLLLOSIFG_OFS                                  (13)                  /* CLR_PLLLOSIFG Offset */
+#define CLR_PLLLOSIFG                                      (0x00002000)          /* PLL loss-of-signal clear interrupt flag */
+/* CSCLRIFG[CLR_PLLOORIFG] Bits */
+#define CLR_PLLOORIFG_OFS                                  (14)                  /* CLR_PLLOORIFG Offset */
+#define CLR_PLLOORIFG                                      (0x00004000)          /* PLL out-of-range clear interrupt flag */
+/* CSSETIFG[SET_LFXTIFG] Bits */
+#define SET_LFXTIFG_OFS                                    ( 0)                  /* SET_LFXTIFG Offset */
+#define SET_LFXTIFG                                        (0x00000001)          /* Set LFXT oscillator fault interrupt flag */
+/* CSSETIFG[SET_HFXTIFG] Bits */
+#define SET_HFXTIFG_OFS                                    ( 1)                  /* SET_HFXTIFG Offset */
+#define SET_HFXTIFG                                        (0x00000002)          /* Set HFXT oscillator fault interrupt flag */
+/* CSSETIFG[SET_HFXT2IFG] Bits */
+#define SET_HFXT2IFG_OFS                                   ( 2)                  /* SET_HFXT2IFG Offset */
+#define SET_HFXT2IFG                                       (0x00000004)          /* Set HFXT2 oscillator fault interrupt flag */
+/* CSSETIFG[SET_DCOMINIFG] Bits */
+#define SET_DCOMINIFG_OFS                                  ( 4)                  /* SET_DCOMINIFG Offset */
+#define SET_DCOMINIFG                                      (0x00000010)          /* Set DCO minimum fault interrupt flag */
+/* CSSETIFG[SET_DCOMAXIFG] Bits */
+#define SET_DCOMAXIFG_OFS                                  ( 5)                  /* SET_DCOMAXIFG Offset */
+#define SET_DCOMAXIFG                                      (0x00000020)          /* Set DCO maximum fault interrupt flag */
+/* CSSETIFG[SET_DCORIFG] Bits */
+#define SET_DCORIFG_OFS                                    ( 6)                  /* SET_DCORIFG Offset */
+#define SET_DCORIFG                                        (0x00000040)          /* Set DCO external resistor fault interrupt flag */
+/* CSSETIFG[SET_CALIFG] Bits */
+#define SET_CALIFG_OFS                                     ( 7)                  /* SET_CALIFG Offset */
+#define SET_CALIFG                                         (0x00000080)          /* REFCNT period counter set interrupt flag */
+/* CSSETIFG[SET_FCNTHFIFG] Bits */
+#define SET_FCNTHFIFG_OFS                                  ( 9)                  /* SET_FCNTHFIFG Offset */
+#define SET_FCNTHFIFG                                      (0x00000200)          /* Start fault counter set interrupt flag HFXT */
+/* CSSETIFG[SET_FCNTHF2IFG] Bits */
+#define SET_FCNTHF2IFG_OFS                                 (10)                  /* SET_FCNTHF2IFG Offset */
+#define SET_FCNTHF2IFG                                     (0x00000400)          /* Start fault counter set interrupt flag HFXT2 */
+/* CSSETIFG[SET_FCNTLFIFG] Bits */
+#define SET_FCNTLFIFG_OFS                                  ( 8)                  /* SET_FCNTLFIFG Offset */
+#define SET_FCNTLFIFG                                      (0x00000100)          /* Start fault counter set interrupt flag LFXT */
+/* CSSETIFG[SET_PLLOOLIFG] Bits */
+#define SET_PLLOOLIFG_OFS                                  (12)                  /* SET_PLLOOLIFG Offset */
+#define SET_PLLOOLIFG                                      (0x00001000)          /* PLL out-of-lock set interrupt flag */
+/* CSSETIFG[SET_PLLLOSIFG] Bits */
+#define SET_PLLLOSIFG_OFS                                  (13)                  /* SET_PLLLOSIFG Offset */
+#define SET_PLLLOSIFG                                      (0x00002000)          /* PLL loss-of-signal set interrupt flag */
+/* CSSETIFG[SET_PLLOORIFG] Bits */
+#define SET_PLLOORIFG_OFS                                  (14)                  /* SET_PLLOORIFG Offset */
+#define SET_PLLOORIFG                                      (0x00004000)          /* PLL out-of-range set interrupt flag */
+/* CSDCOERCAL[DCO_TCTRIM] Bits */
+#define DCO_TCTRIM_OFS                                     ( 0)                  /* DCO_TCTRIM Offset */
+#define DCO_TCTRIM_M                                       (0x00000003)          /* DCO Temperature compensation Trim */
+/* CSDCOERCAL[DCO_FTRIM] Bits */
+#define DCO_FTRIM_OFS                                      (16)                  /* DCO_FTRIM Offset */
+#define DCO_FTRIM_M                                        (0x07ff0000)          /* DCO frequency trim */
+
+/* Pre-defined bitfield values */
+#define CSKEY_VAL                                             (0x0000695A)          /* CS control key value */
+
+
+//*****************************************************************************
+// DIO Bits
+//*****************************************************************************
+/* PAIN[P1IN] Bits */
+#define P1IN_OFS                                           ( 0)                  /* P1IN Offset */
+#define P1IN_M                                             (0x00ff)              /* Port 1 Input */
+/* PAIN[P2IN] Bits */
+#define P2IN_OFS                                           ( 8)                  /* P2IN Offset */
+#define P2IN_M                                             (0xff00)              /* Port 2 Input */
+/* PAOUT[P2OUT] Bits */
+#define P2OUT_OFS                                          ( 8)                  /* P2OUT Offset */
+#define P2OUT_M                                            (0xff00)              /* Port 2 Output */
+/* PAOUT[P1OUT] Bits */
+#define P1OUT_OFS                                          ( 0)                  /* P1OUT Offset */
+#define P1OUT_M                                            (0x00ff)              /* Port 1 Output */
+/* PADIR[P1DIR] Bits */
+#define P1DIR_OFS                                          ( 0)                  /* P1DIR Offset */
+#define P1DIR_M                                            (0x00ff)              /* Port 1 Direction */
+/* PADIR[P2DIR] Bits */
+#define P2DIR_OFS                                          ( 8)                  /* P2DIR Offset */
+#define P2DIR_M                                            (0xff00)              /* Port 2 Direction */
+/* PAREN[P1REN] Bits */
+#define P1REN_OFS                                          ( 0)                  /* P1REN Offset */
+#define P1REN_M                                            (0x00ff)              /* Port 1 Resistor Enable */
+/* PAREN[P2REN] Bits */
+#define P2REN_OFS                                          ( 8)                  /* P2REN Offset */
+#define P2REN_M                                            (0xff00)              /* Port 2 Resistor Enable */
+/* PADS[P1DS] Bits */
+#define P1DS_OFS                                           ( 0)                  /* P1DS Offset */
+#define P1DS_M                                             (0x00ff)              /* Port 1 Drive Strength */
+/* PADS[P2DS] Bits */
+#define P2DS_OFS                                           ( 8)                  /* P2DS Offset */
+#define P2DS_M                                             (0xff00)              /* Port 2 Drive Strength */
+/* PASEL0[P1SEL0] Bits */
+#define P1SEL0_OFS                                         ( 0)                  /* P1SEL0 Offset */
+#define P1SEL0_M                                           (0x00ff)              /* Port 1 Select 0 */
+/* PASEL0[P2SEL0] Bits */
+#define P2SEL0_OFS                                         ( 8)                  /* P2SEL0 Offset */
+#define P2SEL0_M                                           (0xff00)              /* Port 2 Select 0 */
+/* PASEL1[P1SEL1] Bits */
+#define P1SEL1_OFS                                         ( 0)                  /* P1SEL1 Offset */
+#define P1SEL1_M                                           (0x00ff)              /* Port 1 Select 1 */
+/* PASEL1[P2SEL1] Bits */
+#define P2SEL1_OFS                                         ( 8)                  /* P2SEL1 Offset */
+#define P2SEL1_M                                           (0xff00)              /* Port 2 Select 1 */
+/* P1IV[P1IV] Bits */
+#define P1IV_OFS                                           ( 0)                  /* P1IV Offset */
+#define P1IV_M                                             (0x001f)              /* Port 1 interrupt vector value */
+#define P1IV0                                              (0x0001)              /* Port 1 interrupt vector value */
+#define P1IV1                                              (0x0002)              /* Port 1 interrupt vector value */
+#define P1IV2                                              (0x0004)              /* Port 1 interrupt vector value */
+#define P1IV3                                              (0x0008)              /* Port 1 interrupt vector value */
+#define P1IV4                                              (0x0010)              /* Port 1 interrupt vector value */
+#define P1IV_0                                             (0x0000)              /* No interrupt pending */
+#define P1IV_2                                             (0x0002)              /* Interrupt Source: Port 1.0 interrupt; Interrupt Flag: P1IFG0; Interrupt Priority: Highest */
+#define P1IV_4                                             (0x0004)              /* Interrupt Source: Port 1.1 interrupt; Interrupt Flag: P1IFG1 */
+#define P1IV_6                                             (0x0006)              /* Interrupt Source: Port 1.2 interrupt; Interrupt Flag: P1IFG2 */
+#define P1IV_8                                             (0x0008)              /* Interrupt Source: Port 1.3 interrupt; Interrupt Flag: P1IFG3 */
+#define P1IV_10                                            (0x000a)              /* Interrupt Source: Port 1.4 interrupt; Interrupt Flag: P1IFG4 */
+#define P1IV_12                                            (0x000c)              /* Interrupt Source: Port 1.5 interrupt; Interrupt Flag: P1IFG5 */
+#define P1IV_14                                            (0x000e)              /* Interrupt Source: Port 1.6 interrupt; Interrupt Flag: P1IFG6 */
+#define P1IV_16                                            (0x0010)              /* Interrupt Source: Port 1.7 interrupt; Interrupt Flag: P1IFG7; Interrupt Priority: Lowest */
+#define P1IV__NONE                                         (0x0000)              /* No interrupt pending */
+#define P1IV__P1IFG0                                       (0x0002)              /* Interrupt Source: Port 1.0 interrupt; Interrupt Flag: P1IFG0; Interrupt Priority: Highest */
+#define P1IV__P1IFG1                                       (0x0004)              /* Interrupt Source: Port 1.1 interrupt; Interrupt Flag: P1IFG1 */
+#define P1IV__P1IFG2                                       (0x0006)              /* Interrupt Source: Port 1.2 interrupt; Interrupt Flag: P1IFG2 */
+#define P1IV__P1IFG3                                       (0x0008)              /* Interrupt Source: Port 1.3 interrupt; Interrupt Flag: P1IFG3 */
+#define P1IV__P1IFG4                                       (0x000a)              /* Interrupt Source: Port 1.4 interrupt; Interrupt Flag: P1IFG4 */
+#define P1IV__P1IFG5                                       (0x000c)              /* Interrupt Source: Port 1.5 interrupt; Interrupt Flag: P1IFG5 */
+#define P1IV__P1IFG6                                       (0x000e)              /* Interrupt Source: Port 1.6 interrupt; Interrupt Flag: P1IFG6 */
+#define P1IV__P1IFG7                                       (0x0010)              /* Interrupt Source: Port 1.7 interrupt; Interrupt Flag: P1IFG7; Interrupt Priority: Lowest */
+/* PASELC[P1SELC] Bits */
+#define P1SELC_OFS                                         ( 0)                  /* P1SELC Offset */
+#define P1SELC_M                                           (0x00ff)              /* Port 1 Complement Select */
+/* PASELC[P2SELC] Bits */
+#define P2SELC_OFS                                         ( 8)                  /* P2SELC Offset */
+#define P2SELC_M                                           (0xff00)              /* Port 2 Complement Select */
+/* PAIES[P1IES] Bits */
+#define P1IES_OFS                                          ( 0)                  /* P1IES Offset */
+#define P1IES_M                                            (0x00ff)              /* Port 1 Interrupt Edge Select */
+/* PAIES[P2IES] Bits */
+#define P2IES_OFS                                          ( 8)                  /* P2IES Offset */
+#define P2IES_M                                            (0xff00)              /* Port 2 Interrupt Edge Select */
+/* PAIE[P1IE] Bits */
+#define P1IE_OFS                                           ( 0)                  /* P1IE Offset */
+#define P1IE_M                                             (0x00ff)              /* Port 1 Interrupt Enable */
+/* PAIE[P2IE] Bits */
+#define P2IE_OFS                                           ( 8)                  /* P2IE Offset */
+#define P2IE_M                                             (0xff00)              /* Port 2 Interrupt Enable */
+/* PAIFG[P1IFG] Bits */
+#define P1IFG_OFS                                          ( 0)                  /* P1IFG Offset */
+#define P1IFG_M                                            (0x00ff)              /* Port 1 Interrupt Flag */
+/* PAIFG[P2IFG] Bits */
+#define P2IFG_OFS                                          ( 8)                  /* P2IFG Offset */
+#define P2IFG_M                                            (0xff00)              /* Port 2 Interrupt Flag */
+/* P2IV[P2IV] Bits */
+#define P2IV_OFS                                           ( 0)                  /* P2IV Offset */
+#define P2IV_M                                             (0x001f)              /* Port 2 interrupt vector value */
+#define P2IV0                                              (0x0001)              /* Port 2 interrupt vector value */
+#define P2IV1                                              (0x0002)              /* Port 2 interrupt vector value */
+#define P2IV2                                              (0x0004)              /* Port 2 interrupt vector value */
+#define P2IV3                                              (0x0008)              /* Port 2 interrupt vector value */
+#define P2IV4                                              (0x0010)              /* Port 2 interrupt vector value */
+#define P2IV_0                                             (0x0000)              /* No interrupt pending */
+#define P2IV_2                                             (0x0002)              /* Interrupt Source: Port 2.0 interrupt; Interrupt Flag: P2IFG0; Interrupt Priority: Highest */
+#define P2IV_4                                             (0x0004)              /* Interrupt Source: Port 2.1 interrupt; Interrupt Flag: P2IFG1 */
+#define P2IV_6                                             (0x0006)              /* Interrupt Source: Port 2.2 interrupt; Interrupt Flag: P2IFG2 */
+#define P2IV_8                                             (0x0008)              /* Interrupt Source: Port 2.3 interrupt; Interrupt Flag: P2IFG3 */
+#define P2IV_10                                            (0x000a)              /* Interrupt Source: Port 2.4 interrupt; Interrupt Flag: P2IFG4 */
+#define P2IV_12                                            (0x000c)              /* Interrupt Source: Port 2.5 interrupt; Interrupt Flag: P2IFG5 */
+#define P2IV_14                                            (0x000e)              /* Interrupt Source: Port 2.6 interrupt; Interrupt Flag: P2IFG6 */
+#define P2IV_16                                            (0x0010)              /* Interrupt Source: Port 2.7 interrupt; Interrupt Flag: P2IFG7; Interrupt Priority: Lowest */
+#define P2IV__NONE                                         (0x0000)              /* No interrupt pending */
+#define P2IV__P2IFG0                                       (0x0002)              /* Interrupt Source: Port 2.0 interrupt; Interrupt Flag: P2IFG0; Interrupt Priority: Highest */
+#define P2IV__P2IFG1                                       (0x0004)              /* Interrupt Source: Port 2.1 interrupt; Interrupt Flag: P2IFG1 */
+#define P2IV__P2IFG2                                       (0x0006)              /* Interrupt Source: Port 2.2 interrupt; Interrupt Flag: P2IFG2 */
+#define P2IV__P2IFG3                                       (0x0008)              /* Interrupt Source: Port 2.3 interrupt; Interrupt Flag: P2IFG3 */
+#define P2IV__P2IFG4                                       (0x000a)              /* Interrupt Source: Port 2.4 interrupt; Interrupt Flag: P2IFG4 */
+#define P2IV__P2IFG5                                       (0x000c)              /* Interrupt Source: Port 2.5 interrupt; Interrupt Flag: P2IFG5 */
+#define P2IV__P2IFG6                                       (0x000e)              /* Interrupt Source: Port 2.6 interrupt; Interrupt Flag: P2IFG6 */
+#define P2IV__P2IFG7                                       (0x0010)              /* Interrupt Source: Port 2.7 interrupt; Interrupt Flag: P2IFG7; Interrupt Priority: Lowest */
+/* PBIN[P3IN] Bits */
+#define P3IN_OFS                                           ( 0)                  /* P3IN Offset */
+#define P3IN_M                                             (0x00ff)              /* Port 3 Input */
+/* PBIN[P4IN] Bits */
+#define P4IN_OFS                                           ( 8)                  /* P4IN Offset */
+#define P4IN_M                                             (0xff00)              /* Port 4 Input */
+/* PBOUT[P3OUT] Bits */
+#define P3OUT_OFS                                          ( 0)                  /* P3OUT Offset */
+#define P3OUT_M                                            (0x00ff)              /* Port 3 Output */
+/* PBOUT[P4OUT] Bits */
+#define P4OUT_OFS                                          ( 8)                  /* P4OUT Offset */
+#define P4OUT_M                                            (0xff00)              /* Port 4 Output */
+/* PBDIR[P3DIR] Bits */
+#define P3DIR_OFS                                          ( 0)                  /* P3DIR Offset */
+#define P3DIR_M                                            (0x00ff)              /* Port 3 Direction */
+/* PBDIR[P4DIR] Bits */
+#define P4DIR_OFS                                          ( 8)                  /* P4DIR Offset */
+#define P4DIR_M                                            (0xff00)              /* Port 4 Direction */
+/* PBREN[P3REN] Bits */
+#define P3REN_OFS                                          ( 0)                  /* P3REN Offset */
+#define P3REN_M                                            (0x00ff)              /* Port 3 Resistor Enable */
+/* PBREN[P4REN] Bits */
+#define P4REN_OFS                                          ( 8)                  /* P4REN Offset */
+#define P4REN_M                                            (0xff00)              /* Port 4 Resistor Enable */
+/* PBDS[P3DS] Bits */
+#define P3DS_OFS                                           ( 0)                  /* P3DS Offset */
+#define P3DS_M                                             (0x00ff)              /* Port 3 Drive Strength */
+/* PBDS[P4DS] Bits */
+#define P4DS_OFS                                           ( 8)                  /* P4DS Offset */
+#define P4DS_M                                             (0xff00)              /* Port 4 Drive Strength */
+/* PBSEL0[P4SEL0] Bits */
+#define P4SEL0_OFS                                         ( 8)                  /* P4SEL0 Offset */
+#define P4SEL0_M                                           (0xff00)              /* Port 4 Select 0 */
+/* PBSEL0[P3SEL0] Bits */
+#define P3SEL0_OFS                                         ( 0)                  /* P3SEL0 Offset */
+#define P3SEL0_M                                           (0x00ff)              /* Port 3 Select 0 */
+/* PBSEL1[P3SEL1] Bits */
+#define P3SEL1_OFS                                         ( 0)                  /* P3SEL1 Offset */
+#define P3SEL1_M                                           (0x00ff)              /* Port 3 Select 1 */
+/* PBSEL1[P4SEL1] Bits */
+#define P4SEL1_OFS                                         ( 8)                  /* P4SEL1 Offset */
+#define P4SEL1_M                                           (0xff00)              /* Port 4 Select 1 */
+/* P3IV[P3IV] Bits */
+#define P3IV_OFS                                           ( 0)                  /* P3IV Offset */
+#define P3IV_M                                             (0x001f)              /* Port 3 interrupt vector value */
+#define P3IV0                                              (0x0001)              /* Port 3 interrupt vector value */
+#define P3IV1                                              (0x0002)              /* Port 3 interrupt vector value */
+#define P3IV2                                              (0x0004)              /* Port 3 interrupt vector value */
+#define P3IV3                                              (0x0008)              /* Port 3 interrupt vector value */
+#define P3IV4                                              (0x0010)              /* Port 3 interrupt vector value */
+#define P3IV_0                                             (0x0000)              /* No interrupt pending */
+#define P3IV_2                                             (0x0002)              /* Interrupt Source: Port 3.0 interrupt; Interrupt Flag: P3IFG0; Interrupt Priority: Highest */
+#define P3IV_4                                             (0x0004)              /* Interrupt Source: Port 3.1 interrupt; Interrupt Flag: P3IFG1 */
+#define P3IV_6                                             (0x0006)              /* Interrupt Source: Port 3.2 interrupt; Interrupt Flag: P3IFG2 */
+#define P3IV_8                                             (0x0008)              /* Interrupt Source: Port 3.3 interrupt; Interrupt Flag: P3IFG3 */
+#define P3IV_10                                            (0x000a)              /* Interrupt Source: Port 3.4 interrupt; Interrupt Flag: P3IFG4 */
+#define P3IV_12                                            (0x000c)              /* Interrupt Source: Port 3.5 interrupt; Interrupt Flag: P3IFG5 */
+#define P3IV_14                                            (0x000e)              /* Interrupt Source: Port 3.6 interrupt; Interrupt Flag: P3IFG6 */
+#define P3IV_16                                            (0x0010)              /* Interrupt Source: Port 3.7 interrupt; Interrupt Flag: P3IFG7; Interrupt Priority: Lowest */
+#define P3IV__NONE                                         (0x0000)              /* No interrupt pending */
+#define P3IV__P3IFG0                                       (0x0002)              /* Interrupt Source: Port 3.0 interrupt; Interrupt Flag: P3IFG0; Interrupt Priority: Highest */
+#define P3IV__P3IFG1                                       (0x0004)              /* Interrupt Source: Port 3.1 interrupt; Interrupt Flag: P3IFG1 */
+#define P3IV__P3IFG2                                       (0x0006)              /* Interrupt Source: Port 3.2 interrupt; Interrupt Flag: P3IFG2 */
+#define P3IV__P3IFG3                                       (0x0008)              /* Interrupt Source: Port 3.3 interrupt; Interrupt Flag: P3IFG3 */
+#define P3IV__P3IFG4                                       (0x000a)              /* Interrupt Source: Port 3.4 interrupt; Interrupt Flag: P3IFG4 */
+#define P3IV__P3IFG5                                       (0x000c)              /* Interrupt Source: Port 3.5 interrupt; Interrupt Flag: P3IFG5 */
+#define P3IV__P3IFG6                                       (0x000e)              /* Interrupt Source: Port 3.6 interrupt; Interrupt Flag: P3IFG6 */
+#define P3IV__P3IFG7                                       (0x0010)              /* Interrupt Source: Port 3.7 interrupt; Interrupt Flag: P3IFG7; Interrupt Priority: Lowest */
+/* PBSELC[P3SELC] Bits */
+#define P3SELC_OFS                                         ( 0)                  /* P3SELC Offset */
+#define P3SELC_M                                           (0x00ff)              /* Port 3 Complement Select */
+/* PBSELC[P4SELC] Bits */
+#define P4SELC_OFS                                         ( 8)                  /* P4SELC Offset */
+#define P4SELC_M                                           (0xff00)              /* Port 4 Complement Select */
+/* PBIES[P3IES] Bits */
+#define P3IES_OFS                                          ( 0)                  /* P3IES Offset */
+#define P3IES_M                                            (0x00ff)              /* Port 3 Interrupt Edge Select */
+/* PBIES[P4IES] Bits */
+#define P4IES_OFS                                          ( 8)                  /* P4IES Offset */
+#define P4IES_M                                            (0xff00)              /* Port 4 Interrupt Edge Select */
+/* PBIE[P3IE] Bits */
+#define P3IE_OFS                                           ( 0)                  /* P3IE Offset */
+#define P3IE_M                                             (0x00ff)              /* Port 3 Interrupt Enable */
+/* PBIE[P4IE] Bits */
+#define P4IE_OFS                                           ( 8)                  /* P4IE Offset */
+#define P4IE_M                                             (0xff00)              /* Port 4 Interrupt Enable */
+/* PBIFG[P3IFG] Bits */
+#define P3IFG_OFS                                          ( 0)                  /* P3IFG Offset */
+#define P3IFG_M                                            (0x00ff)              /* Port 3 Interrupt Flag */
+/* PBIFG[P4IFG] Bits */
+#define P4IFG_OFS                                          ( 8)                  /* P4IFG Offset */
+#define P4IFG_M                                            (0xff00)              /* Port 4 Interrupt Flag */
+/* P4IV[P4IV] Bits */
+#define P4IV_OFS                                           ( 0)                  /* P4IV Offset */
+#define P4IV_M                                             (0x001f)              /* Port 4 interrupt vector value */
+#define P4IV0                                              (0x0001)              /* Port 4 interrupt vector value */
+#define P4IV1                                              (0x0002)              /* Port 4 interrupt vector value */
+#define P4IV2                                              (0x0004)              /* Port 4 interrupt vector value */
+#define P4IV3                                              (0x0008)              /* Port 4 interrupt vector value */
+#define P4IV4                                              (0x0010)              /* Port 4 interrupt vector value */
+#define P4IV_0                                             (0x0000)              /* No interrupt pending */
+#define P4IV_2                                             (0x0002)              /* Interrupt Source: Port 4.0 interrupt; Interrupt Flag: P4IFG0; Interrupt Priority: Highest */
+#define P4IV_4                                             (0x0004)              /* Interrupt Source: Port 4.1 interrupt; Interrupt Flag: P4IFG1 */
+#define P4IV_6                                             (0x0006)              /* Interrupt Source: Port 4.2 interrupt; Interrupt Flag: P4IFG2 */
+#define P4IV_8                                             (0x0008)              /* Interrupt Source: Port 4.3 interrupt; Interrupt Flag: P4IFG3 */
+#define P4IV_10                                            (0x000a)              /* Interrupt Source: Port 4.4 interrupt; Interrupt Flag: P4IFG4 */
+#define P4IV_12                                            (0x000c)              /* Interrupt Source: Port 4.5 interrupt; Interrupt Flag: P4IFG5 */
+#define P4IV_14                                            (0x000e)              /* Interrupt Source: Port 4.6 interrupt; Interrupt Flag: P4IFG6 */
+#define P4IV_16                                            (0x0010)              /* Interrupt Source: Port 4.7 interrupt; Interrupt Flag: P4IFG7; Interrupt Priority: Lowest */
+#define P4IV__NONE                                         (0x0000)              /* No interrupt pending */
+#define P4IV__P4IFG0                                       (0x0002)              /* Interrupt Source: Port 4.0 interrupt; Interrupt Flag: P4IFG0; Interrupt Priority: Highest */
+#define P4IV__P4IFG1                                       (0x0004)              /* Interrupt Source: Port 4.1 interrupt; Interrupt Flag: P4IFG1 */
+#define P4IV__P4IFG2                                       (0x0006)              /* Interrupt Source: Port 4.2 interrupt; Interrupt Flag: P4IFG2 */
+#define P4IV__P4IFG3                                       (0x0008)              /* Interrupt Source: Port 4.3 interrupt; Interrupt Flag: P4IFG3 */
+#define P4IV__P4IFG4                                       (0x000a)              /* Interrupt Source: Port 4.4 interrupt; Interrupt Flag: P4IFG4 */
+#define P4IV__P4IFG5                                       (0x000c)              /* Interrupt Source: Port 4.5 interrupt; Interrupt Flag: P4IFG5 */
+#define P4IV__P4IFG6                                       (0x000e)              /* Interrupt Source: Port 4.6 interrupt; Interrupt Flag: P4IFG6 */
+#define P4IV__P4IFG7                                       (0x0010)              /* Interrupt Source: Port 4.7 interrupt; Interrupt Flag: P4IFG7; Interrupt Priority: Lowest */
+/* PCIN[P5IN] Bits */
+#define P5IN_OFS                                           ( 0)                  /* P5IN Offset */
+#define P5IN_M                                             (0x00ff)              /* Port 5 Input */
+/* PCIN[P6IN] Bits */
+#define P6IN_OFS                                           ( 8)                  /* P6IN Offset */
+#define P6IN_M                                             (0xff00)              /* Port 6 Input */
+/* PCOUT[P5OUT] Bits */
+#define P5OUT_OFS                                          ( 0)                  /* P5OUT Offset */
+#define P5OUT_M                                            (0x00ff)              /* Port 5 Output */
+/* PCOUT[P6OUT] Bits */
+#define P6OUT_OFS                                          ( 8)                  /* P6OUT Offset */
+#define P6OUT_M                                            (0xff00)              /* Port 6 Output */
+/* PCDIR[P5DIR] Bits */
+#define P5DIR_OFS                                          ( 0)                  /* P5DIR Offset */
+#define P5DIR_M                                            (0x00ff)              /* Port 5 Direction */
+/* PCDIR[P6DIR] Bits */
+#define P6DIR_OFS                                          ( 8)                  /* P6DIR Offset */
+#define P6DIR_M                                            (0xff00)              /* Port 6 Direction */
+/* PCREN[P5REN] Bits */
+#define P5REN_OFS                                          ( 0)                  /* P5REN Offset */
+#define P5REN_M                                            (0x00ff)              /* Port 5 Resistor Enable */
+/* PCREN[P6REN] Bits */
+#define P6REN_OFS                                          ( 8)                  /* P6REN Offset */
+#define P6REN_M                                            (0xff00)              /* Port 6 Resistor Enable */
+/* PCDS[P5DS] Bits */
+#define P5DS_OFS                                           ( 0)                  /* P5DS Offset */
+#define P5DS_M                                             (0x00ff)              /* Port 5 Drive Strength */
+/* PCDS[P6DS] Bits */
+#define P6DS_OFS                                           ( 8)                  /* P6DS Offset */
+#define P6DS_M                                             (0xff00)              /* Port 6 Drive Strength */
+/* PCSEL0[P5SEL0] Bits */
+#define P5SEL0_OFS                                         ( 0)                  /* P5SEL0 Offset */
+#define P5SEL0_M                                           (0x00ff)              /* Port 5 Select 0 */
+/* PCSEL0[P6SEL0] Bits */
+#define P6SEL0_OFS                                         ( 8)                  /* P6SEL0 Offset */
+#define P6SEL0_M                                           (0xff00)              /* Port 6 Select 0 */
+/* PCSEL1[P5SEL1] Bits */
+#define P5SEL1_OFS                                         ( 0)                  /* P5SEL1 Offset */
+#define P5SEL1_M                                           (0x00ff)              /* Port 5 Select 1 */
+/* PCSEL1[P6SEL1] Bits */
+#define P6SEL1_OFS                                         ( 8)                  /* P6SEL1 Offset */
+#define P6SEL1_M                                           (0xff00)              /* Port 6 Select 1 */
+/* P5IV[P5IV] Bits */
+#define P5IV_OFS                                           ( 0)                  /* P5IV Offset */
+#define P5IV_M                                             (0x001f)              /* Port 5 interrupt vector value */
+#define P5IV0                                              (0x0001)              /* Port 5 interrupt vector value */
+#define P5IV1                                              (0x0002)              /* Port 5 interrupt vector value */
+#define P5IV2                                              (0x0004)              /* Port 5 interrupt vector value */
+#define P5IV3                                              (0x0008)              /* Port 5 interrupt vector value */
+#define P5IV4                                              (0x0010)              /* Port 5 interrupt vector value */
+#define P5IV_0                                             (0x0000)              /* No interrupt pending */
+#define P5IV_2                                             (0x0002)              /* Interrupt Source: Port 5.0 interrupt; Interrupt Flag: P5IFG0; Interrupt Priority: Highest */
+#define P5IV_4                                             (0x0004)              /* Interrupt Source: Port 5.1 interrupt; Interrupt Flag: P5IFG1 */
+#define P5IV_6                                             (0x0006)              /* Interrupt Source: Port 5.2 interrupt; Interrupt Flag: P5IFG2 */
+#define P5IV_8                                             (0x0008)              /* Interrupt Source: Port 5.3 interrupt; Interrupt Flag: P5IFG3 */
+#define P5IV_10                                            (0x000a)              /* Interrupt Source: Port 5.4 interrupt; Interrupt Flag: P5IFG4 */
+#define P5IV_12                                            (0x000c)              /* Interrupt Source: Port 5.5 interrupt; Interrupt Flag: P5IFG5 */
+#define P5IV_14                                            (0x000e)              /* Interrupt Source: Port 5.6 interrupt; Interrupt Flag: P5IFG6 */
+#define P5IV_16                                            (0x0010)              /* Interrupt Source: Port 5.7 interrupt; Interrupt Flag: P5IFG7; Interrupt Priority: Lowest */
+#define P5IV__NONE                                         (0x0000)              /* No interrupt pending */
+#define P5IV__P5IFG0                                       (0x0002)              /* Interrupt Source: Port 5.0 interrupt; Interrupt Flag: P5IFG0; Interrupt Priority: Highest */
+#define P5IV__P5IFG1                                       (0x0004)              /* Interrupt Source: Port 5.1 interrupt; Interrupt Flag: P5IFG1 */
+#define P5IV__P5IFG2                                       (0x0006)              /* Interrupt Source: Port 5.2 interrupt; Interrupt Flag: P5IFG2 */
+#define P5IV__P5IFG3                                       (0x0008)              /* Interrupt Source: Port 5.3 interrupt; Interrupt Flag: P5IFG3 */
+#define P5IV__P5IFG4                                       (0x000a)              /* Interrupt Source: Port 5.4 interrupt; Interrupt Flag: P5IFG4 */
+#define P5IV__P5IFG5                                       (0x000c)              /* Interrupt Source: Port 5.5 interrupt; Interrupt Flag: P5IFG5 */
+#define P5IV__P5IFG6                                       (0x000e)              /* Interrupt Source: Port 5.6 interrupt; Interrupt Flag: P5IFG6 */
+#define P5IV__P5IFG7                                       (0x0010)              /* Interrupt Source: Port 5.7 interrupt; Interrupt Flag: P5IFG7; Interrupt Priority: Lowest */
+/* PCSELC[P5SELC] Bits */
+#define P5SELC_OFS                                         ( 0)                  /* P5SELC Offset */
+#define P5SELC_M                                           (0x00ff)              /* Port 5 Complement Select */
+/* PCSELC[P6SELC] Bits */
+#define P6SELC_OFS                                         ( 8)                  /* P6SELC Offset */
+#define P6SELC_M                                           (0xff00)              /* Port 6 Complement Select */
+/* PCIES[P5IES] Bits */
+#define P5IES_OFS                                          ( 0)                  /* P5IES Offset */
+#define P5IES_M                                            (0x00ff)              /* Port 5 Interrupt Edge Select */
+/* PCIES[P6IES] Bits */
+#define P6IES_OFS                                          ( 8)                  /* P6IES Offset */
+#define P6IES_M                                            (0xff00)              /* Port 6 Interrupt Edge Select */
+/* PCIE[P5IE] Bits */
+#define P5IE_OFS                                           ( 0)                  /* P5IE Offset */
+#define P5IE_M                                             (0x00ff)              /* Port 5 Interrupt Enable */
+/* PCIE[P6IE] Bits */
+#define P6IE_OFS                                           ( 8)                  /* P6IE Offset */
+#define P6IE_M                                             (0xff00)              /* Port 6 Interrupt Enable */
+/* PCIFG[P5IFG] Bits */
+#define P5IFG_OFS                                          ( 0)                  /* P5IFG Offset */
+#define P5IFG_M                                            (0x00ff)              /* Port 5 Interrupt Flag */
+/* PCIFG[P6IFG] Bits */
+#define P6IFG_OFS                                          ( 8)                  /* P6IFG Offset */
+#define P6IFG_M                                            (0xff00)              /* Port 6 Interrupt Flag */
+/* P6IV[P6IV] Bits */
+#define P6IV_OFS                                           ( 0)                  /* P6IV Offset */
+#define P6IV_M                                             (0x001f)              /* Port 6 interrupt vector value */
+#define P6IV0                                              (0x0001)              /* Port 6 interrupt vector value */
+#define P6IV1                                              (0x0002)              /* Port 6 interrupt vector value */
+#define P6IV2                                              (0x0004)              /* Port 6 interrupt vector value */
+#define P6IV3                                              (0x0008)              /* Port 6 interrupt vector value */
+#define P6IV4                                              (0x0010)              /* Port 6 interrupt vector value */
+#define P6IV_0                                             (0x0000)              /* No interrupt pending */
+#define P6IV_2                                             (0x0002)              /* Interrupt Source: Port 6.0 interrupt; Interrupt Flag: P6IFG0; Interrupt Priority: Highest */
+#define P6IV_4                                             (0x0004)              /* Interrupt Source: Port 6.1 interrupt; Interrupt Flag: P6IFG1 */
+#define P6IV_6                                             (0x0006)              /* Interrupt Source: Port 6.2 interrupt; Interrupt Flag: P6IFG2 */
+#define P6IV_8                                             (0x0008)              /* Interrupt Source: Port 6.3 interrupt; Interrupt Flag: P6IFG3 */
+#define P6IV_10                                            (0x000a)              /* Interrupt Source: Port 6.4 interrupt; Interrupt Flag: P6IFG4 */
+#define P6IV_12                                            (0x000c)              /* Interrupt Source: Port 6.5 interrupt; Interrupt Flag: P6IFG5 */
+#define P6IV_14                                            (0x000e)              /* Interrupt Source: Port 6.6 interrupt; Interrupt Flag: P6IFG6 */
+#define P6IV_16                                            (0x0010)              /* Interrupt Source: Port 6.7 interrupt; Interrupt Flag: P6IFG7; Interrupt Priority: Lowest */
+#define P6IV__NONE                                         (0x0000)              /* No interrupt pending */
+#define P6IV__P6IFG0                                       (0x0002)              /* Interrupt Source: Port 6.0 interrupt; Interrupt Flag: P6IFG0; Interrupt Priority: Highest */
+#define P6IV__P6IFG1                                       (0x0004)              /* Interrupt Source: Port 6.1 interrupt; Interrupt Flag: P6IFG1 */
+#define P6IV__P6IFG2                                       (0x0006)              /* Interrupt Source: Port 6.2 interrupt; Interrupt Flag: P6IFG2 */
+#define P6IV__P6IFG3                                       (0x0008)              /* Interrupt Source: Port 6.3 interrupt; Interrupt Flag: P6IFG3 */
+#define P6IV__P6IFG4                                       (0x000a)              /* Interrupt Source: Port 6.4 interrupt; Interrupt Flag: P6IFG4 */
+#define P6IV__P6IFG5                                       (0x000c)              /* Interrupt Source: Port 6.5 interrupt; Interrupt Flag: P6IFG5 */
+#define P6IV__P6IFG6                                       (0x000e)              /* Interrupt Source: Port 6.6 interrupt; Interrupt Flag: P6IFG6 */
+#define P6IV__P6IFG7                                       (0x0010)              /* Interrupt Source: Port 6.7 interrupt; Interrupt Flag: P6IFG7; Interrupt Priority: Lowest */
+/* PDIN[P7IN] Bits */
+#define P7IN_OFS                                           ( 0)                  /* P7IN Offset */
+#define P7IN_M                                             (0x00ff)              /* Port 7 Input */
+/* PDIN[P8IN] Bits */
+#define P8IN_OFS                                           ( 8)                  /* P8IN Offset */
+#define P8IN_M                                             (0xff00)              /* Port 8 Input */
+/* PDOUT[P7OUT] Bits */
+#define P7OUT_OFS                                          ( 0)                  /* P7OUT Offset */
+#define P7OUT_M                                            (0x00ff)              /* Port 7 Output */
+/* PDOUT[P8OUT] Bits */
+#define P8OUT_OFS                                          ( 8)                  /* P8OUT Offset */
+#define P8OUT_M                                            (0xff00)              /* Port 8 Output */
+/* PDDIR[P7DIR] Bits */
+#define P7DIR_OFS                                          ( 0)                  /* P7DIR Offset */
+#define P7DIR_M                                            (0x00ff)              /* Port 7 Direction */
+/* PDDIR[P8DIR] Bits */
+#define P8DIR_OFS                                          ( 8)                  /* P8DIR Offset */
+#define P8DIR_M                                            (0xff00)              /* Port 8 Direction */
+/* PDREN[P7REN] Bits */
+#define P7REN_OFS                                          ( 0)                  /* P7REN Offset */
+#define P7REN_M                                            (0x00ff)              /* Port 7 Resistor Enable */
+/* PDREN[P8REN] Bits */
+#define P8REN_OFS                                          ( 8)                  /* P8REN Offset */
+#define P8REN_M                                            (0xff00)              /* Port 8 Resistor Enable */
+/* PDDS[P7DS] Bits */
+#define P7DS_OFS                                           ( 0)                  /* P7DS Offset */
+#define P7DS_M                                             (0x00ff)              /* Port 7 Drive Strength */
+/* PDDS[P8DS] Bits */
+#define P8DS_OFS                                           ( 8)                  /* P8DS Offset */
+#define P8DS_M                                             (0xff00)              /* Port 8 Drive Strength */
+/* PDSEL0[P7SEL0] Bits */
+#define P7SEL0_OFS                                         ( 0)                  /* P7SEL0 Offset */
+#define P7SEL0_M                                           (0x00ff)              /* Port 7 Select 0 */
+/* PDSEL0[P8SEL0] Bits */
+#define P8SEL0_OFS                                         ( 8)                  /* P8SEL0 Offset */
+#define P8SEL0_M                                           (0xff00)              /* Port 8 Select 0 */
+/* PDSEL1[P7SEL1] Bits */
+#define P7SEL1_OFS                                         ( 0)                  /* P7SEL1 Offset */
+#define P7SEL1_M                                           (0x00ff)              /* Port 7 Select 1 */
+/* PDSEL1[P8SEL1] Bits */
+#define P8SEL1_OFS                                         ( 8)                  /* P8SEL1 Offset */
+#define P8SEL1_M                                           (0xff00)              /* Port 8 Select 1 */
+/* P7IV[P7IV] Bits */
+#define P7IV_OFS                                           ( 0)                  /* P7IV Offset */
+#define P7IV_M                                             (0x001f)              /* Port 7 interrupt vector value */
+#define P7IV0                                              (0x0001)              /* Port 7 interrupt vector value */
+#define P7IV1                                              (0x0002)              /* Port 7 interrupt vector value */
+#define P7IV2                                              (0x0004)              /* Port 7 interrupt vector value */
+#define P7IV3                                              (0x0008)              /* Port 7 interrupt vector value */
+#define P7IV4                                              (0x0010)              /* Port 7 interrupt vector value */
+#define P7IV_0                                             (0x0000)              /* No interrupt pending */
+#define P7IV_2                                             (0x0002)              /* Interrupt Source: Port 7.0 interrupt; Interrupt Flag: P7IFG0; Interrupt Priority: Highest */
+#define P7IV_4                                             (0x0004)              /* Interrupt Source: Port 7.1 interrupt; Interrupt Flag: P7IFG1 */
+#define P7IV_6                                             (0x0006)              /* Interrupt Source: Port 7.2 interrupt; Interrupt Flag: P7IFG2 */
+#define P7IV_8                                             (0x0008)              /* Interrupt Source: Port 7.3 interrupt; Interrupt Flag: P7IFG3 */
+#define P7IV_10                                            (0x000a)              /* Interrupt Source: Port 7.4 interrupt; Interrupt Flag: P7IFG4 */
+#define P7IV_12                                            (0x000c)              /* Interrupt Source: Port 7.5 interrupt; Interrupt Flag: P7IFG5 */
+#define P7IV_14                                            (0x000e)              /* Interrupt Source: Port 7.6 interrupt; Interrupt Flag: P7IFG6 */
+#define P7IV_16                                            (0x0010)              /* Interrupt Source: Port 7.7 interrupt; Interrupt Flag: P7IFG7; Interrupt Priority: Lowest */
+#define P7IV__NONE                                         (0x0000)              /* No interrupt pending */
+#define P7IV__P7IFG0                                       (0x0002)              /* Interrupt Source: Port 7.0 interrupt; Interrupt Flag: P7IFG0; Interrupt Priority: Highest */
+#define P7IV__P7IFG1                                       (0x0004)              /* Interrupt Source: Port 7.1 interrupt; Interrupt Flag: P7IFG1 */
+#define P7IV__P7IFG2                                       (0x0006)              /* Interrupt Source: Port 7.2 interrupt; Interrupt Flag: P7IFG2 */
+#define P7IV__P7IFG3                                       (0x0008)              /* Interrupt Source: Port 7.3 interrupt; Interrupt Flag: P7IFG3 */
+#define P7IV__P7IFG4                                       (0x000a)              /* Interrupt Source: Port 7.4 interrupt; Interrupt Flag: P7IFG4 */
+#define P7IV__P7IFG5                                       (0x000c)              /* Interrupt Source: Port 7.5 interrupt; Interrupt Flag: P7IFG5 */
+#define P7IV__P7IFG6                                       (0x000e)              /* Interrupt Source: Port 7.6 interrupt; Interrupt Flag: P7IFG6 */
+#define P7IV__P7IFG7                                       (0x0010)              /* Interrupt Source: Port 7.7 interrupt; Interrupt Flag: P7IFG7; Interrupt Priority: Lowest */
+/* PDSELC[P7SELC] Bits */
+#define P7SELC_OFS                                         ( 0)                  /* P7SELC Offset */
+#define P7SELC_M                                           (0x00ff)              /* Port 7 Complement Select */
+/* PDSELC[P8SELC] Bits */
+#define P8SELC_OFS                                         ( 8)                  /* P8SELC Offset */
+#define P8SELC_M                                           (0xff00)              /* Port 8 Complement Select */
+/* PDIES[P7IES] Bits */
+#define P7IES_OFS                                          ( 0)                  /* P7IES Offset */
+#define P7IES_M                                            (0x00ff)              /* Port 7 Interrupt Edge Select */
+/* PDIES[P8IES] Bits */
+#define P8IES_OFS                                          ( 8)                  /* P8IES Offset */
+#define P8IES_M                                            (0xff00)              /* Port 8 Interrupt Edge Select */
+/* PDIE[P7IE] Bits */
+#define P7IE_OFS                                           ( 0)                  /* P7IE Offset */
+#define P7IE_M                                             (0x00ff)              /* Port 7 Interrupt Enable */
+/* PDIE[P8IE] Bits */
+#define P8IE_OFS                                           ( 8)                  /* P8IE Offset */
+#define P8IE_M                                             (0xff00)              /* Port 8 Interrupt Enable */
+/* PDIFG[P7IFG] Bits */
+#define P7IFG_OFS                                          ( 0)                  /* P7IFG Offset */
+#define P7IFG_M                                            (0x00ff)              /* Port 7 Interrupt Flag */
+/* PDIFG[P8IFG] Bits */
+#define P8IFG_OFS                                          ( 8)                  /* P8IFG Offset */
+#define P8IFG_M                                            (0xff00)              /* Port 8 Interrupt Flag */
+/* P8IV[P8IV] Bits */
+#define P8IV_OFS                                           ( 0)                  /* P8IV Offset */
+#define P8IV_M                                             (0x001f)              /* Port 8 interrupt vector value */
+#define P8IV0                                              (0x0001)              /* Port 8 interrupt vector value */
+#define P8IV1                                              (0x0002)              /* Port 8 interrupt vector value */
+#define P8IV2                                              (0x0004)              /* Port 8 interrupt vector value */
+#define P8IV3                                              (0x0008)              /* Port 8 interrupt vector value */
+#define P8IV4                                              (0x0010)              /* Port 8 interrupt vector value */
+#define P8IV_0                                             (0x0000)              /* No interrupt pending */
+#define P8IV_2                                             (0x0002)              /* Interrupt Source: Port 8.0 interrupt; Interrupt Flag: P8IFG0; Interrupt Priority: Highest */
+#define P8IV_4                                             (0x0004)              /* Interrupt Source: Port 8.1 interrupt; Interrupt Flag: P8IFG1 */
+#define P8IV_6                                             (0x0006)              /* Interrupt Source: Port 8.2 interrupt; Interrupt Flag: P8IFG2 */
+#define P8IV_8                                             (0x0008)              /* Interrupt Source: Port 8.3 interrupt; Interrupt Flag: P8IFG3 */
+#define P8IV_10                                            (0x000a)              /* Interrupt Source: Port 8.4 interrupt; Interrupt Flag: P8IFG4 */
+#define P8IV_12                                            (0x000c)              /* Interrupt Source: Port 8.5 interrupt; Interrupt Flag: P8IFG5 */
+#define P8IV_14                                            (0x000e)              /* Interrupt Source: Port 8.6 interrupt; Interrupt Flag: P8IFG6 */
+#define P8IV_16                                            (0x0010)              /* Interrupt Source: Port 8.7 interrupt; Interrupt Flag: P8IFG7; Interrupt Priority: Lowest */
+#define P8IV__NONE                                         (0x0000)              /* No interrupt pending */
+#define P8IV__P8IFG0                                       (0x0002)              /* Interrupt Source: Port 8.0 interrupt; Interrupt Flag: P8IFG0; Interrupt Priority: Highest */
+#define P8IV__P8IFG1                                       (0x0004)              /* Interrupt Source: Port 8.1 interrupt; Interrupt Flag: P8IFG1 */
+#define P8IV__P8IFG2                                       (0x0006)              /* Interrupt Source: Port 8.2 interrupt; Interrupt Flag: P8IFG2 */
+#define P8IV__P8IFG3                                       (0x0008)              /* Interrupt Source: Port 8.3 interrupt; Interrupt Flag: P8IFG3 */
+#define P8IV__P8IFG4                                       (0x000a)              /* Interrupt Source: Port 8.4 interrupt; Interrupt Flag: P8IFG4 */
+#define P8IV__P8IFG5                                       (0x000c)              /* Interrupt Source: Port 8.5 interrupt; Interrupt Flag: P8IFG5 */
+#define P8IV__P8IFG6                                       (0x000e)              /* Interrupt Source: Port 8.6 interrupt; Interrupt Flag: P8IFG6 */
+#define P8IV__P8IFG7                                       (0x0010)              /* Interrupt Source: Port 8.7 interrupt; Interrupt Flag: P8IFG7; Interrupt Priority: Lowest */
+/* PEIN[P9IN] Bits */
+#define P9IN_OFS                                           ( 0)                  /* P9IN Offset */
+#define P9IN_M                                             (0x00ff)              /* Port 9 Input */
+/* PEIN[P10IN] Bits */
+#define P10IN_OFS                                          ( 8)                  /* P10IN Offset */
+#define P10IN_M                                            (0xff00)              /* Port 10 Input */
+/* PEOUT[P9OUT] Bits */
+#define P9OUT_OFS                                          ( 0)                  /* P9OUT Offset */
+#define P9OUT_M                                            (0x00ff)              /* Port 9 Output */
+/* PEOUT[P10OUT] Bits */
+#define P10OUT_OFS                                         ( 8)                  /* P10OUT Offset */
+#define P10OUT_M                                           (0xff00)              /* Port 10 Output */
+/* PEDIR[P9DIR] Bits */
+#define P9DIR_OFS                                          ( 0)                  /* P9DIR Offset */
+#define P9DIR_M                                            (0x00ff)              /* Port 9 Direction */
+/* PEDIR[P10DIR] Bits */
+#define P10DIR_OFS                                         ( 8)                  /* P10DIR Offset */
+#define P10DIR_M                                           (0xff00)              /* Port 10 Direction */
+/* PEREN[P9REN] Bits */
+#define P9REN_OFS                                          ( 0)                  /* P9REN Offset */
+#define P9REN_M                                            (0x00ff)              /* Port 9 Resistor Enable */
+/* PEREN[P10REN] Bits */
+#define P10REN_OFS                                         ( 8)                  /* P10REN Offset */
+#define P10REN_M                                           (0xff00)              /* Port 10 Resistor Enable */
+/* PEDS[P9DS] Bits */
+#define P9DS_OFS                                           ( 0)                  /* P9DS Offset */
+#define P9DS_M                                             (0x00ff)              /* Port 9 Drive Strength */
+/* PEDS[P10DS] Bits */
+#define P10DS_OFS                                          ( 8)                  /* P10DS Offset */
+#define P10DS_M                                            (0xff00)              /* Port 10 Drive Strength */
+/* PESEL0[P9SEL0] Bits */
+#define P9SEL0_OFS                                         ( 0)                  /* P9SEL0 Offset */
+#define P9SEL0_M                                           (0x00ff)              /* Port 9 Select 0 */
+/* PESEL0[P10SEL0] Bits */
+#define P10SEL0_OFS                                        ( 8)                  /* P10SEL0 Offset */
+#define P10SEL0_M                                          (0xff00)              /* Port 10 Select 0 */
+/* PESEL1[P9SEL1] Bits */
+#define P9SEL1_OFS                                         ( 0)                  /* P9SEL1 Offset */
+#define P9SEL1_M                                           (0x00ff)              /* Port 9 Select 1 */
+/* PESEL1[P10SEL1] Bits */
+#define P10SEL1_OFS                                        ( 8)                  /* P10SEL1 Offset */
+#define P10SEL1_M                                          (0xff00)              /* Port 10 Select 1 */
+/* P9IV[P9IV] Bits */
+#define P9IV_OFS                                           ( 0)                  /* P9IV Offset */
+#define P9IV_M                                             (0x001f)              /* Port 9 interrupt vector value */
+#define P9IV0                                              (0x0001)              /* Port 9 interrupt vector value */
+#define P9IV1                                              (0x0002)              /* Port 9 interrupt vector value */
+#define P9IV2                                              (0x0004)              /* Port 9 interrupt vector value */
+#define P9IV3                                              (0x0008)              /* Port 9 interrupt vector value */
+#define P9IV4                                              (0x0010)              /* Port 9 interrupt vector value */
+#define P9IV_0                                             (0x0000)              /* No interrupt pending */
+#define P9IV_2                                             (0x0002)              /* Interrupt Source: Port 9.0 interrupt; Interrupt Flag: P9IFG0; Interrupt Priority: Highest */
+#define P9IV_4                                             (0x0004)              /* Interrupt Source: Port 9.1 interrupt; Interrupt Flag: P9IFG1 */
+#define P9IV_6                                             (0x0006)              /* Interrupt Source: Port 9.2 interrupt; Interrupt Flag: P9IFG2 */
+#define P9IV_8                                             (0x0008)              /* Interrupt Source: Port 9.3 interrupt; Interrupt Flag: P9IFG3 */
+#define P9IV_10                                            (0x000a)              /* Interrupt Source: Port 9.4 interrupt; Interrupt Flag: P9IFG4 */
+#define P9IV_12                                            (0x000c)              /* Interrupt Source: Port 9.5 interrupt; Interrupt Flag: P9IFG5 */
+#define P9IV_14                                            (0x000e)              /* Interrupt Source: Port 9.6 interrupt; Interrupt Flag: P9IFG6 */
+#define P9IV_16                                            (0x0010)              /* Interrupt Source: Port 9.7 interrupt; Interrupt Flag: P9IFG7; Interrupt Priority: Lowest */
+#define P9IV__NONE                                         (0x0000)              /* No interrupt pending */
+#define P9IV__P9IFG0                                       (0x0002)              /* Interrupt Source: Port 9.0 interrupt; Interrupt Flag: P9IFG0; Interrupt Priority: Highest */
+#define P9IV__P9IFG1                                       (0x0004)              /* Interrupt Source: Port 9.1 interrupt; Interrupt Flag: P9IFG1 */
+#define P9IV__P9IFG2                                       (0x0006)              /* Interrupt Source: Port 9.2 interrupt; Interrupt Flag: P9IFG2 */
+#define P9IV__P9IFG3                                       (0x0008)              /* Interrupt Source: Port 9.3 interrupt; Interrupt Flag: P9IFG3 */
+#define P9IV__P9IFG4                                       (0x000a)              /* Interrupt Source: Port 9.4 interrupt; Interrupt Flag: P9IFG4 */
+#define P9IV__P9IFG5                                       (0x000c)              /* Interrupt Source: Port 9.5 interrupt; Interrupt Flag: P9IFG5 */
+#define P9IV__P9IFG6                                       (0x000e)              /* Interrupt Source: Port 9.6 interrupt; Interrupt Flag: P9IFG6 */
+#define P9IV__P9IFG7                                       (0x0010)              /* Interrupt Source: Port 9.7 interrupt; Interrupt Flag: P9IFG7; Interrupt Priority: Lowest */
+/* PESELC[P9SELC] Bits */
+#define P9SELC_OFS                                         ( 0)                  /* P9SELC Offset */
+#define P9SELC_M                                           (0x00ff)              /* Port 9 Complement Select */
+/* PESELC[P10SELC] Bits */
+#define P10SELC_OFS                                        ( 8)                  /* P10SELC Offset */
+#define P10SELC_M                                          (0xff00)              /* Port 10 Complement Select */
+/* PEIES[P9IES] Bits */
+#define P9IES_OFS                                          ( 0)                  /* P9IES Offset */
+#define P9IES_M                                            (0x00ff)              /* Port 9 Interrupt Edge Select */
+/* PEIES[P10IES] Bits */
+#define P10IES_OFS                                         ( 8)                  /* P10IES Offset */
+#define P10IES_M                                           (0xff00)              /* Port 10 Interrupt Edge Select */
+/* PEIE[P9IE] Bits */
+#define P9IE_OFS                                           ( 0)                  /* P9IE Offset */
+#define P9IE_M                                             (0x00ff)              /* Port 9 Interrupt Enable */
+/* PEIE[P10IE] Bits */
+#define P10IE_OFS                                          ( 8)                  /* P10IE Offset */
+#define P10IE_M                                            (0xff00)              /* Port 10 Interrupt Enable */
+/* PEIFG[P9IFG] Bits */
+#define P9IFG_OFS                                          ( 0)                  /* P9IFG Offset */
+#define P9IFG_M                                            (0x00ff)              /* Port 9 Interrupt Flag */
+/* PEIFG[P10IFG] Bits */
+#define P10IFG_OFS                                         ( 8)                  /* P10IFG Offset */
+#define P10IFG_M                                           (0xff00)              /* Port 10 Interrupt Flag */
+/* P10IV[P10IV] Bits */
+#define P10IV_OFS                                          ( 0)                  /* P10IV Offset */
+#define P10IV_M                                            (0x001f)              /* Port 10 interrupt vector value */
+#define P10IV0                                             (0x0001)              /* Port 10 interrupt vector value */
+#define P10IV1                                             (0x0002)              /* Port 10 interrupt vector value */
+#define P10IV2                                             (0x0004)              /* Port 10 interrupt vector value */
+#define P10IV3                                             (0x0008)              /* Port 10 interrupt vector value */
+#define P10IV4                                             (0x0010)              /* Port 10 interrupt vector value */
+#define P10IV_0                                            (0x0000)              /* No interrupt pending */
+#define P10IV_2                                            (0x0002)              /* Interrupt Source: Port 10.0 interrupt; Interrupt Flag: P10IFG0; Interrupt Priority: Highest */
+#define P10IV_4                                            (0x0004)              /* Interrupt Source: Port 10.1 interrupt; Interrupt Flag: P10IFG1 */
+#define P10IV_6                                            (0x0006)              /* Interrupt Source: Port 10.2 interrupt; Interrupt Flag: P10IFG2 */
+#define P10IV_8                                            (0x0008)              /* Interrupt Source: Port 10.3 interrupt; Interrupt Flag: P10IFG3 */
+#define P10IV_10                                           (0x000a)              /* Interrupt Source: Port 10.4 interrupt; Interrupt Flag: P10IFG4 */
+#define P10IV_12                                           (0x000c)              /* Interrupt Source: Port 10.5 interrupt; Interrupt Flag: P10IFG5 */
+#define P10IV_14                                           (0x000e)              /* Interrupt Source: Port 10.6 interrupt; Interrupt Flag: P10IFG6 */
+#define P10IV_16                                           (0x0010)              /* Interrupt Source: Port 10.7 interrupt; Interrupt Flag: P10IFG7; Interrupt Priority: Lowest */
+#define P10IV__NONE                                        (0x0000)              /* No interrupt pending */
+#define P10IV__P10IFG0                                     (0x0002)              /* Interrupt Source: Port 10.0 interrupt; Interrupt Flag: P10IFG0; Interrupt Priority: Highest */
+#define P10IV__P10IFG1                                     (0x0004)              /* Interrupt Source: Port 10.1 interrupt; Interrupt Flag: P10IFG1 */
+#define P10IV__P10IFG2                                     (0x0006)              /* Interrupt Source: Port 10.2 interrupt; Interrupt Flag: P10IFG2 */
+#define P10IV__P10IFG3                                     (0x0008)              /* Interrupt Source: Port 10.3 interrupt; Interrupt Flag: P10IFG3 */
+#define P10IV__P10IFG4                                     (0x000a)              /* Interrupt Source: Port 10.4 interrupt; Interrupt Flag: P10IFG4 */
+#define P10IV__P10IFG5                                     (0x000c)              /* Interrupt Source: Port 10.5 interrupt; Interrupt Flag: P10IFG5 */
+#define P10IV__P10IFG6                                     (0x000e)              /* Interrupt Source: Port 10.6 interrupt; Interrupt Flag: P10IFG6 */
+#define P10IV__P10IFG7                                     (0x0010)              /* Interrupt Source: Port 10.7 interrupt; Interrupt Flag: P10IFG7; Interrupt Priority: Lowest */
+
+
+//*****************************************************************************
+// DMA Bits
+//*****************************************************************************
+/* DMA_DEVICE_CFG[DMA_DEVICE_CFG_NUM_DMA_CHANNELS] Bits */
+#define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_OFS                ( 0)                  /* NUM_DMA_CHANNELS Offset */
+#define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_M                  (0x000000ff)          /* Number of DMA channels available */
+/* DMA_DEVICE_CFG[DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL] Bits */
+#define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_OFS             ( 8)                  /* NUM_SRC_PER_CHANNEL Offset */
+#define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_M               (0x0000ff00)          /* Number of DMA sources per channel */
+/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH0] Bits */
+#define DMA_SW_CHTRIG_CH0_OFS                              ( 0)                  /* CH0 Offset */
+#define DMA_SW_CHTRIG_CH0                                  (0x00000001)          /* Write 1, triggers DMA_CHANNEL0 */
+/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH1] Bits */
+#define DMA_SW_CHTRIG_CH1_OFS                              ( 1)                  /* CH1 Offset */
+#define DMA_SW_CHTRIG_CH1                                  (0x00000002)          /* Write 1, triggers DMA_CHANNEL1 */
+/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH2] Bits */
+#define DMA_SW_CHTRIG_CH2_OFS                              ( 2)                  /* CH2 Offset */
+#define DMA_SW_CHTRIG_CH2                                  (0x00000004)          /* Write 1, triggers DMA_CHANNEL2 */
+/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH3] Bits */
+#define DMA_SW_CHTRIG_CH3_OFS                              ( 3)                  /* CH3 Offset */
+#define DMA_SW_CHTRIG_CH3                                  (0x00000008)          /* Write 1, triggers DMA_CHANNEL3 */
+/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH4] Bits */
+#define DMA_SW_CHTRIG_CH4_OFS                              ( 4)                  /* CH4 Offset */
+#define DMA_SW_CHTRIG_CH4                                  (0x00000010)          /* Write 1, triggers DMA_CHANNEL4 */
+/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH5] Bits */
+#define DMA_SW_CHTRIG_CH5_OFS                              ( 5)                  /* CH5 Offset */
+#define DMA_SW_CHTRIG_CH5                                  (0x00000020)          /* Write 1, triggers DMA_CHANNEL5 */
+/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH6] Bits */
+#define DMA_SW_CHTRIG_CH6_OFS                              ( 6)                  /* CH6 Offset */
+#define DMA_SW_CHTRIG_CH6                                  (0x00000040)          /* Write 1, triggers DMA_CHANNEL6 */
+/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH7] Bits */
+#define DMA_SW_CHTRIG_CH7_OFS                              ( 7)                  /* CH7 Offset */
+#define DMA_SW_CHTRIG_CH7                                  (0x00000080)          /* Write 1, triggers DMA_CHANNEL7 */
+/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH8] Bits */
+#define DMA_SW_CHTRIG_CH8_OFS                              ( 8)                  /* CH8 Offset */
+#define DMA_SW_CHTRIG_CH8                                  (0x00000100)          /* Write 1, triggers DMA_CHANNEL8 */
+/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH9] Bits */
+#define DMA_SW_CHTRIG_CH9_OFS                              ( 9)                  /* CH9 Offset */
+#define DMA_SW_CHTRIG_CH9                                  (0x00000200)          /* Write 1, triggers DMA_CHANNEL9 */
+/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH10] Bits */
+#define DMA_SW_CHTRIG_CH10_OFS                             (10)                  /* CH10 Offset */
+#define DMA_SW_CHTRIG_CH10                                 (0x00000400)          /* Write 1, triggers DMA_CHANNEL10 */
+/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH11] Bits */
+#define DMA_SW_CHTRIG_CH11_OFS                             (11)                  /* CH11 Offset */
+#define DMA_SW_CHTRIG_CH11                                 (0x00000800)          /* Write 1, triggers DMA_CHANNEL11 */
+/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH12] Bits */
+#define DMA_SW_CHTRIG_CH12_OFS                             (12)                  /* CH12 Offset */
+#define DMA_SW_CHTRIG_CH12                                 (0x00001000)          /* Write 1, triggers DMA_CHANNEL12 */
+/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH13] Bits */
+#define DMA_SW_CHTRIG_CH13_OFS                             (13)                  /* CH13 Offset */
+#define DMA_SW_CHTRIG_CH13                                 (0x00002000)          /* Write 1, triggers DMA_CHANNEL13 */
+/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH14] Bits */
+#define DMA_SW_CHTRIG_CH14_OFS                             (14)                  /* CH14 Offset */
+#define DMA_SW_CHTRIG_CH14                                 (0x00004000)          /* Write 1, triggers DMA_CHANNEL14 */
+/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH15] Bits */
+#define DMA_SW_CHTRIG_CH15_OFS                             (15)                  /* CH15 Offset */
+#define DMA_SW_CHTRIG_CH15                                 (0x00008000)          /* Write 1, triggers DMA_CHANNEL15 */
+/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH16] Bits */
+#define DMA_SW_CHTRIG_CH16_OFS                             (16)                  /* CH16 Offset */
+#define DMA_SW_CHTRIG_CH16                                 (0x00010000)          /* Write 1, triggers DMA_CHANNEL16 */
+/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH17] Bits */
+#define DMA_SW_CHTRIG_CH17_OFS                             (17)                  /* CH17 Offset */
+#define DMA_SW_CHTRIG_CH17                                 (0x00020000)          /* Write 1, triggers DMA_CHANNEL17 */
+/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH18] Bits */
+#define DMA_SW_CHTRIG_CH18_OFS                             (18)                  /* CH18 Offset */
+#define DMA_SW_CHTRIG_CH18                                 (0x00040000)          /* Write 1, triggers DMA_CHANNEL18 */
+/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH19] Bits */
+#define DMA_SW_CHTRIG_CH19_OFS                             (19)                  /* CH19 Offset */
+#define DMA_SW_CHTRIG_CH19                                 (0x00080000)          /* Write 1, triggers DMA_CHANNEL19 */
+/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH20] Bits */
+#define DMA_SW_CHTRIG_CH20_OFS                             (20)                  /* CH20 Offset */
+#define DMA_SW_CHTRIG_CH20                                 (0x00100000)          /* Write 1, triggers DMA_CHANNEL20 */
+/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH21] Bits */
+#define DMA_SW_CHTRIG_CH21_OFS                             (21)                  /* CH21 Offset */
+#define DMA_SW_CHTRIG_CH21                                 (0x00200000)          /* Write 1, triggers DMA_CHANNEL21 */
+/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH22] Bits */
+#define DMA_SW_CHTRIG_CH22_OFS                             (22)                  /* CH22 Offset */
+#define DMA_SW_CHTRIG_CH22                                 (0x00400000)          /* Write 1, triggers DMA_CHANNEL22 */
+/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH23] Bits */
+#define DMA_SW_CHTRIG_CH23_OFS                             (23)                  /* CH23 Offset */
+#define DMA_SW_CHTRIG_CH23                                 (0x00800000)          /* Write 1, triggers DMA_CHANNEL23 */
+/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH24] Bits */
+#define DMA_SW_CHTRIG_CH24_OFS                             (24)                  /* CH24 Offset */
+#define DMA_SW_CHTRIG_CH24                                 (0x01000000)          /* Write 1, triggers DMA_CHANNEL24 */
+/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH25] Bits */
+#define DMA_SW_CHTRIG_CH25_OFS                             (25)                  /* CH25 Offset */
+#define DMA_SW_CHTRIG_CH25                                 (0x02000000)          /* Write 1, triggers DMA_CHANNEL25 */
+/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH26] Bits */
+#define DMA_SW_CHTRIG_CH26_OFS                             (26)                  /* CH26 Offset */
+#define DMA_SW_CHTRIG_CH26                                 (0x04000000)          /* Write 1, triggers DMA_CHANNEL26 */
+/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH27] Bits */
+#define DMA_SW_CHTRIG_CH27_OFS                             (27)                  /* CH27 Offset */
+#define DMA_SW_CHTRIG_CH27                                 (0x08000000)          /* Write 1, triggers DMA_CHANNEL27 */
+/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH28] Bits */
+#define DMA_SW_CHTRIG_CH28_OFS                             (28)                  /* CH28 Offset */
+#define DMA_SW_CHTRIG_CH28                                 (0x10000000)          /* Write 1, triggers DMA_CHANNEL28 */
+/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH29] Bits */
+#define DMA_SW_CHTRIG_CH29_OFS                             (29)                  /* CH29 Offset */
+#define DMA_SW_CHTRIG_CH29                                 (0x20000000)          /* Write 1, triggers DMA_CHANNEL29 */
+/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH30] Bits */
+#define DMA_SW_CHTRIG_CH30_OFS                             (30)                  /* CH30 Offset */
+#define DMA_SW_CHTRIG_CH30                                 (0x40000000)          /* Write 1, triggers DMA_CHANNEL30 */
+/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH31] Bits */
+#define DMA_SW_CHTRIG_CH31_OFS                             (31)                  /* CH31 Offset */
+#define DMA_SW_CHTRIG_CH31                                 (0x80000000)          /* Write 1, triggers DMA_CHANNEL31 */
+/* DMA_CH_SRCCFG[DMA_CHN_SRCCFG_DMA_SRC] Bits */
+#define DMA_CHN_SRCCFG_DMA_SRC_OFS                         ( 0)                  /* DMA_SRC Offset */
+#define DMA_CHN_SRCCFG_DMA_SRC_M                           (0x000000ff)          /* Device level DMA source mapping to channel input */
+/* DMA_INT1_SRCCFG[DMA_INT1_SRCCFG_INT_SRC] Bits */
+#define DMA_INT1_SRCCFG_INT_SRC_OFS                        ( 0)                  /* INT_SRC Offset */
+#define DMA_INT1_SRCCFG_INT_SRC_M                          (0x0000001f)          /* Controls which channel's completion event is mapped as a source of this Interrupt */
+/* DMA_INT1_SRCCFG[DMA_INT1_SRCCFG_EN] Bits */
+#define DMA_INT1_SRCCFG_EN_OFS                             ( 5)                  /* EN Offset */
+#define DMA_INT1_SRCCFG_EN                                 (0x00000020)          /* Enables DMA_INT1 mapping */
+/* DMA_INT2_SRCCFG[DMA_INT2_SRCCFG_INT_SRC] Bits */
+#define DMA_INT2_SRCCFG_INT_SRC_OFS                        ( 0)                  /* INT_SRC Offset */
+#define DMA_INT2_SRCCFG_INT_SRC_M                          (0x0000001f)          /* Controls which channel's completion event is mapped as a source of this Interrupt */
+/* DMA_INT2_SRCCFG[DMA_INT2_SRCCFG_EN] Bits */
+#define DMA_INT2_SRCCFG_EN_OFS                             ( 5)                  /* EN Offset */
+#define DMA_INT2_SRCCFG_EN                                 (0x00000020)          /* Enables DMA_INT2 mapping */
+/* DMA_INT3_SRCCFG[DMA_INT3_SRCCFG_INT_SRC] Bits */
+#define DMA_INT3_SRCCFG_INT_SRC_OFS                        ( 0)                  /* INT_SRC Offset */
+#define DMA_INT3_SRCCFG_INT_SRC_M                          (0x0000001f)          /* Controls which channel's completion event is mapped as a source of this Interrupt */
+/* DMA_INT3_SRCCFG[DMA_INT3_SRCCFG_EN] Bits */
+#define DMA_INT3_SRCCFG_EN_OFS                             ( 5)                  /* EN Offset */
+#define DMA_INT3_SRCCFG_EN                                 (0x00000020)          /* Enables DMA_INT3 mapping */
+/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH0] Bits */
+#define DMA_INT0_SRCFLG_CH0_OFS                            ( 0)                  /* CH0 Offset */
+#define DMA_INT0_SRCFLG_CH0                                (0x00000001)          /* Channel 0 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH1] Bits */
+#define DMA_INT0_SRCFLG_CH1_OFS                            ( 1)                  /* CH1 Offset */
+#define DMA_INT0_SRCFLG_CH1                                (0x00000002)          /* Channel 1 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH2] Bits */
+#define DMA_INT0_SRCFLG_CH2_OFS                            ( 2)                  /* CH2 Offset */
+#define DMA_INT0_SRCFLG_CH2                                (0x00000004)          /* Channel 2 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH3] Bits */
+#define DMA_INT0_SRCFLG_CH3_OFS                            ( 3)                  /* CH3 Offset */
+#define DMA_INT0_SRCFLG_CH3                                (0x00000008)          /* Channel 3 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH4] Bits */
+#define DMA_INT0_SRCFLG_CH4_OFS                            ( 4)                  /* CH4 Offset */
+#define DMA_INT0_SRCFLG_CH4                                (0x00000010)          /* Channel 4 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH5] Bits */
+#define DMA_INT0_SRCFLG_CH5_OFS                            ( 5)                  /* CH5 Offset */
+#define DMA_INT0_SRCFLG_CH5                                (0x00000020)          /* Channel 5 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH6] Bits */
+#define DMA_INT0_SRCFLG_CH6_OFS                            ( 6)                  /* CH6 Offset */
+#define DMA_INT0_SRCFLG_CH6                                (0x00000040)          /* Channel 6 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH7] Bits */
+#define DMA_INT0_SRCFLG_CH7_OFS                            ( 7)                  /* CH7 Offset */
+#define DMA_INT0_SRCFLG_CH7                                (0x00000080)          /* Channel 7 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH8] Bits */
+#define DMA_INT0_SRCFLG_CH8_OFS                            ( 8)                  /* CH8 Offset */
+#define DMA_INT0_SRCFLG_CH8                                (0x00000100)          /* Channel 8 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH9] Bits */
+#define DMA_INT0_SRCFLG_CH9_OFS                            ( 9)                  /* CH9 Offset */
+#define DMA_INT0_SRCFLG_CH9                                (0x00000200)          /* Channel 9 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH10] Bits */
+#define DMA_INT0_SRCFLG_CH10_OFS                           (10)                  /* CH10 Offset */
+#define DMA_INT0_SRCFLG_CH10                               (0x00000400)          /* Channel 10 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH11] Bits */
+#define DMA_INT0_SRCFLG_CH11_OFS                           (11)                  /* CH11 Offset */
+#define DMA_INT0_SRCFLG_CH11                               (0x00000800)          /* Channel 11 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH12] Bits */
+#define DMA_INT0_SRCFLG_CH12_OFS                           (12)                  /* CH12 Offset */
+#define DMA_INT0_SRCFLG_CH12                               (0x00001000)          /* Channel 12 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH13] Bits */
+#define DMA_INT0_SRCFLG_CH13_OFS                           (13)                  /* CH13 Offset */
+#define DMA_INT0_SRCFLG_CH13                               (0x00002000)          /* Channel 13 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH14] Bits */
+#define DMA_INT0_SRCFLG_CH14_OFS                           (14)                  /* CH14 Offset */
+#define DMA_INT0_SRCFLG_CH14                               (0x00004000)          /* Channel 14 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH15] Bits */
+#define DMA_INT0_SRCFLG_CH15_OFS                           (15)                  /* CH15 Offset */
+#define DMA_INT0_SRCFLG_CH15                               (0x00008000)          /* Channel 15 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH16] Bits */
+#define DMA_INT0_SRCFLG_CH16_OFS                           (16)                  /* CH16 Offset */
+#define DMA_INT0_SRCFLG_CH16                               (0x00010000)          /* Channel 16 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH17] Bits */
+#define DMA_INT0_SRCFLG_CH17_OFS                           (17)                  /* CH17 Offset */
+#define DMA_INT0_SRCFLG_CH17                               (0x00020000)          /* Channel 17 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH18] Bits */
+#define DMA_INT0_SRCFLG_CH18_OFS                           (18)                  /* CH18 Offset */
+#define DMA_INT0_SRCFLG_CH18                               (0x00040000)          /* Channel 18 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH19] Bits */
+#define DMA_INT0_SRCFLG_CH19_OFS                           (19)                  /* CH19 Offset */
+#define DMA_INT0_SRCFLG_CH19                               (0x00080000)          /* Channel 19 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH20] Bits */
+#define DMA_INT0_SRCFLG_CH20_OFS                           (20)                  /* CH20 Offset */
+#define DMA_INT0_SRCFLG_CH20                               (0x00100000)          /* Channel 20 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH21] Bits */
+#define DMA_INT0_SRCFLG_CH21_OFS                           (21)                  /* CH21 Offset */
+#define DMA_INT0_SRCFLG_CH21                               (0x00200000)          /* Channel 21 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH22] Bits */
+#define DMA_INT0_SRCFLG_CH22_OFS                           (22)                  /* CH22 Offset */
+#define DMA_INT0_SRCFLG_CH22                               (0x00400000)          /* Channel 22 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH23] Bits */
+#define DMA_INT0_SRCFLG_CH23_OFS                           (23)                  /* CH23 Offset */
+#define DMA_INT0_SRCFLG_CH23                               (0x00800000)          /* Channel 23 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH24] Bits */
+#define DMA_INT0_SRCFLG_CH24_OFS                           (24)                  /* CH24 Offset */
+#define DMA_INT0_SRCFLG_CH24                               (0x01000000)          /* Channel 24 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH25] Bits */
+#define DMA_INT0_SRCFLG_CH25_OFS                           (25)                  /* CH25 Offset */
+#define DMA_INT0_SRCFLG_CH25                               (0x02000000)          /* Channel 25 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH26] Bits */
+#define DMA_INT0_SRCFLG_CH26_OFS                           (26)                  /* CH26 Offset */
+#define DMA_INT0_SRCFLG_CH26                               (0x04000000)          /* Channel 26 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH27] Bits */
+#define DMA_INT0_SRCFLG_CH27_OFS                           (27)                  /* CH27 Offset */
+#define DMA_INT0_SRCFLG_CH27                               (0x08000000)          /* Channel 27 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH28] Bits */
+#define DMA_INT0_SRCFLG_CH28_OFS                           (28)                  /* CH28 Offset */
+#define DMA_INT0_SRCFLG_CH28                               (0x10000000)          /* Channel 28 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH29] Bits */
+#define DMA_INT0_SRCFLG_CH29_OFS                           (29)                  /* CH29 Offset */
+#define DMA_INT0_SRCFLG_CH29                               (0x20000000)          /* Channel 29 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH30] Bits */
+#define DMA_INT0_SRCFLG_CH30_OFS                           (30)                  /* CH30 Offset */
+#define DMA_INT0_SRCFLG_CH30                               (0x40000000)          /* Channel 30 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH31] Bits */
+#define DMA_INT0_SRCFLG_CH31_OFS                           (31)                  /* CH31 Offset */
+#define DMA_INT0_SRCFLG_CH31                               (0x80000000)          /* Channel 31 was the source of DMA_INT0 */
+/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH0] Bits */
+#define DMA_INT0_CLRFLG_CH0_OFS                            ( 0)                  /* CH0 Offset */
+#define DMA_INT0_CLRFLG_CH0                                (0x00000001)          /* Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH1] Bits */
+#define DMA_INT0_CLRFLG_CH1_OFS                            ( 1)                  /* CH1 Offset */
+#define DMA_INT0_CLRFLG_CH1                                (0x00000002)          /* Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH2] Bits */
+#define DMA_INT0_CLRFLG_CH2_OFS                            ( 2)                  /* CH2 Offset */
+#define DMA_INT0_CLRFLG_CH2                                (0x00000004)          /* Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH3] Bits */
+#define DMA_INT0_CLRFLG_CH3_OFS                            ( 3)                  /* CH3 Offset */
+#define DMA_INT0_CLRFLG_CH3                                (0x00000008)          /* Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH4] Bits */
+#define DMA_INT0_CLRFLG_CH4_OFS                            ( 4)                  /* CH4 Offset */
+#define DMA_INT0_CLRFLG_CH4                                (0x00000010)          /* Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH5] Bits */
+#define DMA_INT0_CLRFLG_CH5_OFS                            ( 5)                  /* CH5 Offset */
+#define DMA_INT0_CLRFLG_CH5                                (0x00000020)          /* Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH6] Bits */
+#define DMA_INT0_CLRFLG_CH6_OFS                            ( 6)                  /* CH6 Offset */
+#define DMA_INT0_CLRFLG_CH6                                (0x00000040)          /* Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH7] Bits */
+#define DMA_INT0_CLRFLG_CH7_OFS                            ( 7)                  /* CH7 Offset */
+#define DMA_INT0_CLRFLG_CH7                                (0x00000080)          /* Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH8] Bits */
+#define DMA_INT0_CLRFLG_CH8_OFS                            ( 8)                  /* CH8 Offset */
+#define DMA_INT0_CLRFLG_CH8                                (0x00000100)          /* Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH9] Bits */
+#define DMA_INT0_CLRFLG_CH9_OFS                            ( 9)                  /* CH9 Offset */
+#define DMA_INT0_CLRFLG_CH9                                (0x00000200)          /* Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH10] Bits */
+#define DMA_INT0_CLRFLG_CH10_OFS                           (10)                  /* CH10 Offset */
+#define DMA_INT0_CLRFLG_CH10                               (0x00000400)          /* Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH11] Bits */
+#define DMA_INT0_CLRFLG_CH11_OFS                           (11)                  /* CH11 Offset */
+#define DMA_INT0_CLRFLG_CH11                               (0x00000800)          /* Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH12] Bits */
+#define DMA_INT0_CLRFLG_CH12_OFS                           (12)                  /* CH12 Offset */
+#define DMA_INT0_CLRFLG_CH12                               (0x00001000)          /* Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH13] Bits */
+#define DMA_INT0_CLRFLG_CH13_OFS                           (13)                  /* CH13 Offset */
+#define DMA_INT0_CLRFLG_CH13                               (0x00002000)          /* Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH14] Bits */
+#define DMA_INT0_CLRFLG_CH14_OFS                           (14)                  /* CH14 Offset */
+#define DMA_INT0_CLRFLG_CH14                               (0x00004000)          /* Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH15] Bits */
+#define DMA_INT0_CLRFLG_CH15_OFS                           (15)                  /* CH15 Offset */
+#define DMA_INT0_CLRFLG_CH15                               (0x00008000)          /* Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH16] Bits */
+#define DMA_INT0_CLRFLG_CH16_OFS                           (16)                  /* CH16 Offset */
+#define DMA_INT0_CLRFLG_CH16                               (0x00010000)          /* Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH17] Bits */
+#define DMA_INT0_CLRFLG_CH17_OFS                           (17)                  /* CH17 Offset */
+#define DMA_INT0_CLRFLG_CH17                               (0x00020000)          /* Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH18] Bits */
+#define DMA_INT0_CLRFLG_CH18_OFS                           (18)                  /* CH18 Offset */
+#define DMA_INT0_CLRFLG_CH18                               (0x00040000)          /* Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH19] Bits */
+#define DMA_INT0_CLRFLG_CH19_OFS                           (19)                  /* CH19 Offset */
+#define DMA_INT0_CLRFLG_CH19                               (0x00080000)          /* Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH20] Bits */
+#define DMA_INT0_CLRFLG_CH20_OFS                           (20)                  /* CH20 Offset */
+#define DMA_INT0_CLRFLG_CH20                               (0x00100000)          /* Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH21] Bits */
+#define DMA_INT0_CLRFLG_CH21_OFS                           (21)                  /* CH21 Offset */
+#define DMA_INT0_CLRFLG_CH21                               (0x00200000)          /* Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH22] Bits */
+#define DMA_INT0_CLRFLG_CH22_OFS                           (22)                  /* CH22 Offset */
+#define DMA_INT0_CLRFLG_CH22                               (0x00400000)          /* Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH23] Bits */
+#define DMA_INT0_CLRFLG_CH23_OFS                           (23)                  /* CH23 Offset */
+#define DMA_INT0_CLRFLG_CH23                               (0x00800000)          /* Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH24] Bits */
+#define DMA_INT0_CLRFLG_CH24_OFS                           (24)                  /* CH24 Offset */
+#define DMA_INT0_CLRFLG_CH24                               (0x01000000)          /* Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH25] Bits */
+#define DMA_INT0_CLRFLG_CH25_OFS                           (25)                  /* CH25 Offset */
+#define DMA_INT0_CLRFLG_CH25                               (0x02000000)          /* Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH26] Bits */
+#define DMA_INT0_CLRFLG_CH26_OFS                           (26)                  /* CH26 Offset */
+#define DMA_INT0_CLRFLG_CH26                               (0x04000000)          /* Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH27] Bits */
+#define DMA_INT0_CLRFLG_CH27_OFS                           (27)                  /* CH27 Offset */
+#define DMA_INT0_CLRFLG_CH27                               (0x08000000)          /* Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH28] Bits */
+#define DMA_INT0_CLRFLG_CH28_OFS                           (28)                  /* CH28 Offset */
+#define DMA_INT0_CLRFLG_CH28                               (0x10000000)          /* Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH29] Bits */
+#define DMA_INT0_CLRFLG_CH29_OFS                           (29)                  /* CH29 Offset */
+#define DMA_INT0_CLRFLG_CH29                               (0x20000000)          /* Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH30] Bits */
+#define DMA_INT0_CLRFLG_CH30_OFS                           (30)                  /* CH30 Offset */
+#define DMA_INT0_CLRFLG_CH30                               (0x40000000)          /* Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH31] Bits */
+#define DMA_INT0_CLRFLG_CH31_OFS                           (31)                  /* CH31 Offset */
+#define DMA_INT0_CLRFLG_CH31                               (0x80000000)          /* Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_STAT[DMA_STAT_MASTEN] Bits */
+#define DMA_STAT_MASTEN_OFS                                ( 0)                  /* MASTEN Offset */
+#define DMA_STAT_MASTEN                                    (0x00000001)          /*  */
+/* DMA_STAT[DMA_STAT_] Bits */
+#define DMA_STAT__OFS                                      ( 4)                  /* STATE Offset */
+#define DMA_STAT__M                                        (0x000000f0)          /*  */
+#define DMA_STAT_0                                         (0x00000010)          /*  */
+#define DMA_STAT_1                                         (0x00000020)          /*  */
+#define DMA_STAT_2                                         (0x00000040)          /*  */
+#define DMA_STAT_3                                         (0x00000080)          /*  */
+#define DMA_STAT__0                                        (0x00000000)          /* idle */
+#define DMA_STAT__1                                        (0x00000010)          /* reading channel controller data */
+#define DMA_STAT__2                                        (0x00000020)          /* reading source data end pointer */
+#define DMA_STAT__3                                        (0x00000030)          /* reading destination data end pointer */
+#define DMA_STAT__4                                        (0x00000040)          /* reading source data */
+#define DMA_STAT__5                                        (0x00000050)          /* writing destination data */
+#define DMA_STAT__6                                        (0x00000060)          /* waiting for DMA request to clear */
+#define DMA_STAT__7                                        (0x00000070)          /* writing channel controller data */
+#define DMA_STAT__8                                        (0x00000080)          /* stalled */
+#define DMA_STAT__9                                        (0x00000090)          /* done */
+#define DMA_STAT__10                                       (0x000000a0)          /* peripheral scatter-gather transition */
+#define DMA_STAT__11                                       (0x000000b0)          /* Reserved */
+#define DMA_STAT__12                                       (0x000000c0)          /* Reserved */
+#define DMA_STAT__13                                       (0x000000d0)          /* Reserved */
+#define DMA_STAT__14                                       (0x000000e0)          /* Reserved */
+#define DMA_STAT__15                                       (0x000000f0)          /* Reserved */
+/* DMA_STAT[DMA_STAT_] Bits */
+//#define DMA_STAT__OFS                                      (16)                  /* DMACHANS Offset */
+//#define DMA_STAT__M                                        (0x001f0000)          /*  */
+//#define DMA_STAT_0                                         (0x00010000)          /*  */
+//#define DMA_STAT_1                                         (0x00020000)          /*  */
+//#define DMA_STAT_2                                         (0x00040000)          /*  */
+//#define DMA_STAT_3                                         (0x00080000)          /*  */
+#define DMA_STAT_4                                         (0x00100000)          /*  */
+//#define DMA_STAT__0                                        (0x00000000)          /* Controller configured to use 1 DMA channel */
+//#define DMA_STAT__1                                        (0x00010000)          /* Controller configured to use 2 DMA channels */
+#define DMA_STAT__30                                       (0x001e0000)          /* Controller configured to use 31 DMA channels */
+#define DMA_STAT__31                                       (0x001f0000)          /* Controller configured to use 32 DMA channels */
+/* DMA_STAT[DMA_STAT_] Bits */
+//#define DMA_STAT__OFS                                      (28)                  /* TESTSTAT Offset */
+//#define DMA_STAT__M                                        (0xf0000000)          /*  */
+//#define DMA_STAT_0                                         (0x10000000)          /*  */
+//#define DMA_STAT_1                                         (0x20000000)          /*  */
+//#define DMA_STAT_2                                         (0x40000000)          /*  */
+//#define DMA_STAT_3                                         (0x80000000)          /*  */
+//#define DMA_STAT__0                                        (0x00000000)          /* Controller does not include the integration test logic */
+//#define DMA_STAT__1                                        (0x10000000)          /* Controller includes the integration test logic */
+/* DMA_CFG[DMA_CFG_] Bits */
+#define DMA_CFG__OFS                                       ( 0)                  /* MASTEN Offset */
+#define DMA_CFG_                                           (0x00000001)          /*  */
+/* DMA_CFG[DMA_CFG_] Bits */
+//#define DMA_CFG__OFS                                       ( 5)                  /* CHPROTCTRL Offset */
+#define DMA_CFG__M                                         (0x000000e0)          /*  */
+/* DMA_CTLBASE[DMA_CTLBASE_] Bits */
+#define DMA_CTLBASE__OFS                                   ( 5)                  /* ADDR Offset */
+#define DMA_CTLBASE__M                                     (0xffffffe0)          /*  */
+/* DMA_ERRCLR[DMA_ERRCLR_] Bits */
+#define DMA_ERRCLR__OFS                                    ( 0)                  /* ERRCLR Offset */
+#define DMA_ERRCLR_                                        (0x00000001)          /*  */
+
+/* UDMA_STAT Control Bits */
+#define UDMA_STAT_DMACHANS_M                               0x001F0000            /* Available uDMA Channels Minus 1 */
+#define UDMA_STAT_STATE_M                                  0x000000F0            /* Control State Machine Status */
+#define UDMA_STAT_STATE_IDLE                               0x00000000            /* Idle */
+#define UDMA_STAT_STATE_RD_CTRL                            0x00000010            /* Reading channel controller data */
+#define UDMA_STAT_STATE_RD_SRCENDP                         0x00000020            /* Reading source end pointer */
+#define UDMA_STAT_STATE_RD_DSTENDP                         0x00000030            /* Reading destination end pointer */
+#define UDMA_STAT_STATE_RD_SRCDAT                          0x00000040            /* Reading source data */
+#define UDMA_STAT_STATE_WR_DSTDAT                          0x00000050            /* Writing destination data */
+#define UDMA_STAT_STATE_WAIT                               0x00000060            /* Waiting for uDMA request to */
+                                                                                 /* clear */
+#define UDMA_STAT_STATE_WR_CTRL                            0x00000070            /* Writing channel controller data */
+#define UDMA_STAT_STATE_STALL                              0x00000080            /* Stalled */
+#define UDMA_STAT_STATE_DONE                               0x00000090            /* Done */
+#define UDMA_STAT_STATE_UNDEF                              0x000000A0            /* Undefined */
+#define UDMA_STAT_MASTEN                                   0x00000001            /* Master Enable Status */
+#define UDMA_STAT_DMACHANS_S                               16
+
+/* UDMA_CFG Control Bits */
+#define UDMA_CFG_MASTEN                                    0x00000001            /* Controller Master Enable */
+
+/* UDMA_CTLBASE Control Bits */
+#define UDMA_CTLBASE_ADDR_M                                0xFFFFFC00            /* Channel Control Base Address */
+#define UDMA_CTLBASE_ADDR_S                                10
+
+/* UDMA_ALTBASE Control Bits */
+#define UDMA_ALTBASE_ADDR_M                                0xFFFFFFFF            /* Alternate Channel Address Pointer */
+#define UDMA_ALTBASE_ADDR_S                                0
+
+/* UDMA_WAITSTAT Control Bits */
+#define UDMA_WAITSTAT_WAITREQ_M                            0xFFFFFFFF            /* Channel [n] Wait Status */
+
+/* UDMA_SWREQ Control Bits */
+#define UDMA_SWREQ_M                                       0xFFFFFFFF            /* Channel [n] Software Request */
+
+/* UDMA_USEBURSTSET Control Bits */
+#define UDMA_USEBURSTSET_SET_M                             0xFFFFFFFF            /* Channel [n] Useburst Set */
+
+/* UDMA_USEBURSTCLR Control Bits */
+#define UDMA_USEBURSTCLR_CLR_M                             0xFFFFFFFF            /* Channel [n] Useburst Clear */
+
+/* UDMA_REQMASKSET Control Bits */
+#define UDMA_REQMASKSET_SET_M                              0xFFFFFFFF            /* Channel [n] Request Mask Set */
+
+/* UDMA_REQMASKCLR Control Bits */
+#define UDMA_REQMASKCLR_CLR_M                              0xFFFFFFFF            /* Channel [n] Request Mask Clear */
+
+/* UDMA_ENASET Control Bits */
+#define UDMA_ENASET_SET_M                                  0xFFFFFFFF            /* Channel [n] Enable Set */
+
+/* UDMA_ENACLR Control Bits */
+#define UDMA_ENACLR_CLR_M                                  0xFFFFFFFF            /* Clear Channel [n] Enable Clear */
+
+/* UDMA_ALTSET Control Bits */
+#define UDMA_ALTSET_SET_M                                  0xFFFFFFFF            /* Channel [n] Alternate Set */
+
+/* UDMA_ALTCLR Control Bits */
+#define UDMA_ALTCLR_CLR_M                                  0xFFFFFFFF            /* Channel [n] Alternate Clear */
+
+/* UDMA_PRIOSET Control Bits */
+#define UDMA_PRIOSET_SET_M                                 0xFFFFFFFF            /* Channel [n] Priority Set */
+
+/* UDMA_PRIOCLR Control Bits */
+#define UDMA_PRIOCLR_CLR_M                                 0xFFFFFFFF            /* Channel [n] Priority Clear */
+
+/* UDMA_ERRCLR Control Bits */
+#define UDMA_ERRCLR_ERRCLR                                 0x00000001            /* uDMA Bus Error Status */
+
+/* UDMA_CHASGN Control Bits */
+#define UDMA_CHASGN_M                                      0xFFFFFFFF            /* Channel [n] Assignment Select */
+#define UDMA_CHASGN_PRIMARY                                0x00000000            /* Use the primary channel */
+                                                                                 /* assignment */
+#define UDMA_CHASGN_SECONDARY                              0x00000001            /* Use the secondary channel */
+                                                                                 /* assignment */
+
+/* Micro Direct Memory Access (uDMA) offsets */
+#define UDMA_O_SRCENDP                                     0x00000000            /* DMA Channel Source Address End */
+                                                                                 /* Pointer */
+#define UDMA_O_DSTENDP                                     0x00000004            /* DMA Channel Destination Address */
+                                                                                 /* End Pointer */
+#define UDMA_O_CHCTL                                       0x00000008            /* DMA Channel Control Word */
+
+/* UDMA_O_SRCENDP Control Bits */
+#define UDMA_SRCENDP_ADDR_M                                0xFFFFFFFF            /* Source Address End Pointer */
+#define UDMA_SRCENDP_ADDR_S                                0
+
+/* UDMA_O_DSTENDP Control Bits */
+#define UDMA_DSTENDP_ADDR_M                                0xFFFFFFFF            /* Destination Address End Pointer */
+#define UDMA_DSTENDP_ADDR_S                                0
+
+/* UDMA_O_CHCTL Control Bits */
+#define UDMA_CHCTL_DSTINC_M                                0xC0000000            /* Destination Address Increment */
+#define UDMA_CHCTL_DSTINC_8                                0x00000000            /* Byte */
+#define UDMA_CHCTL_DSTINC_16                               0x40000000            /* Half-word */
+#define UDMA_CHCTL_DSTINC_32                               0x80000000            /* Word */
+#define UDMA_CHCTL_DSTINC_NONE                             0xC0000000            /* No increment */
+#define UDMA_CHCTL_DSTSIZE_M                               0x30000000            /* Destination Data Size */
+#define UDMA_CHCTL_DSTSIZE_8                               0x00000000            /* Byte */
+#define UDMA_CHCTL_DSTSIZE_16                              0x10000000            /* Half-word */
+#define UDMA_CHCTL_DSTSIZE_32                              0x20000000            /* Word */
+#define UDMA_CHCTL_SRCINC_M                                0x0C000000            /* Source Address Increment */
+#define UDMA_CHCTL_SRCINC_8                                0x00000000            /* Byte */
+#define UDMA_CHCTL_SRCINC_16                               0x04000000            /* Half-word */
+#define UDMA_CHCTL_SRCINC_32                               0x08000000            /* Word */
+#define UDMA_CHCTL_SRCINC_NONE                             0x0C000000            /* No increment */
+#define UDMA_CHCTL_SRCSIZE_M                               0x03000000            /* Source Data Size */
+#define UDMA_CHCTL_SRCSIZE_8                               0x00000000            /* Byte */
+#define UDMA_CHCTL_SRCSIZE_16                              0x01000000            /* Half-word */
+#define UDMA_CHCTL_SRCSIZE_32                              0x02000000            /* Word */
+#define UDMA_CHCTL_ARBSIZE_M                               0x0003C000            /* Arbitration Size */
+#define UDMA_CHCTL_ARBSIZE_1                               0x00000000            /* 1 Transfer */
+#define UDMA_CHCTL_ARBSIZE_2                               0x00004000            /* 2 Transfers */
+#define UDMA_CHCTL_ARBSIZE_4                               0x00008000            /* 4 Transfers */
+#define UDMA_CHCTL_ARBSIZE_8                               0x0000C000            /* 8 Transfers */
+#define UDMA_CHCTL_ARBSIZE_16                              0x00010000            /* 16 Transfers */
+#define UDMA_CHCTL_ARBSIZE_32                              0x00014000            /* 32 Transfers */
+#define UDMA_CHCTL_ARBSIZE_64                              0x00018000            /* 64 Transfers */
+#define UDMA_CHCTL_ARBSIZE_128                             0x0001C000            /* 128 Transfers */
+#define UDMA_CHCTL_ARBSIZE_256                             0x00020000            /* 256 Transfers */
+#define UDMA_CHCTL_ARBSIZE_512                             0x00024000            /* 512 Transfers */
+#define UDMA_CHCTL_ARBSIZE_1024                            0x00028000            /* 1024 Transfers */
+#define UDMA_CHCTL_XFERSIZE_M                              0x00003FF0            /* Transfer Size (minus 1) */
+#define UDMA_CHCTL_NXTUSEBURST                             0x00000008            /* Next Useburst */
+#define UDMA_CHCTL_XFERMODE_M                              0x00000007            /* uDMA Transfer Mode */
+#define UDMA_CHCTL_XFERMODE_STOP                           0x00000000            /* Stop */
+#define UDMA_CHCTL_XFERMODE_BASIC                          0x00000001            /* Basic */
+#define UDMA_CHCTL_XFERMODE_AUTO                           0x00000002            /* Auto-Request */
+#define UDMA_CHCTL_XFERMODE_PINGPONG                       0x00000003            /* Ping-Pong */
+#define UDMA_CHCTL_XFERMODE_MEM_SG                         0x00000004            /* Memory Scatter-Gather */
+#define UDMA_CHCTL_XFERMODE_MEM_SGA                        0x00000005            /* Alternate Memory Scatter-Gather */
+#define UDMA_CHCTL_XFERMODE_PER_SG                         0x00000006            /* Peripheral Scatter-Gather */
+#define UDMA_CHCTL_XFERMODE_PER_SGA                        0x00000007            /* Alternate Peripheral */
+                                                                                 /* Scatter-Gather */
+#define UDMA_CHCTL_XFERSIZE_S                              4
+
+
+//*****************************************************************************
+// DWT Bits
+//*****************************************************************************
+/* DWT_CTRL[DWT_CTRL_CYCCNTENA] Bits */
+#define DWT_CTRL_CYCCNTENA_OFS                             ( 0)                  /* CYCCNTENA Offset */
+#define DWT_CTRL_CYCCNTENA                                 (0x00000001)          /*  */
+/* DWT_CTRL[DWT_CTRL_POSTPRESET] Bits */
+#define DWT_CTRL_POSTPRESET_OFS                            ( 1)                  /* POSTPRESET Offset */
+#define DWT_CTRL_POSTPRESET_M                              (0x0000001e)          /*  */
+/* DWT_CTRL[DWT_CTRL_POSTCNT] Bits */
+#define DWT_CTRL_POSTCNT_OFS                               ( 5)                  /* POSTCNT Offset */
+#define DWT_CTRL_POSTCNT_M                                 (0x000001e0)          /*  */
+/* DWT_CTRL[DWT_CTRL_CYCTAP] Bits */
+#define DWT_CTRL_CYCTAP_OFS                                ( 9)                  /* CYCTAP Offset */
+#define DWT_CTRL_CYCTAP                                    (0x00000200)          /*  */
+/* DWT_CTRL[DWT_CTRL_SYNCTAP] Bits */
+#define DWT_CTRL_SYNCTAP_OFS                               (10)                  /* SYNCTAP Offset */
+#define DWT_CTRL_SYNCTAP_M                                 (0x00000c00)          /*  */
+#define DWT_CTRL_SYNCTAP0                                  (0x00000400)          /*  */
+#define DWT_CTRL_SYNCTAP1                                  (0x00000800)          /*  */
+#define DWT_CTRL_SYNCTAP_0                                 (0x00000000)          /* Disabled. No synch counting. */
+#define DWT_CTRL_SYNCTAP_1                                 (0x00000400)          /* Tap at CYCCNT bit 24. */
+#define DWT_CTRL_SYNCTAP_2                                 (0x00000800)          /* Tap at CYCCNT bit 26. */
+#define DWT_CTRL_SYNCTAP_3                                 (0x00000c00)          /* Tap at CYCCNT bit 28. */
+/* DWT_CTRL[DWT_CTRL_PCSAMPLEENA] Bits */
+#define DWT_CTRL_PCSAMPLEENA_OFS                           (12)                  /* PCSAMPLEENA Offset */
+#define DWT_CTRL_PCSAMPLEENA                               (0x00001000)          /*  */
+/* DWT_CTRL[DWT_CTRL_EXCTRCENA] Bits */
+#define DWT_CTRL_EXCTRCENA_OFS                             (16)                  /* EXCTRCENA Offset */
+#define DWT_CTRL_EXCTRCENA                                 (0x00010000)          /*  */
+/* DWT_CTRL[DWT_CTRL_CPIEVTENA] Bits */
+#define DWT_CTRL_CPIEVTENA_OFS                             (17)                  /* CPIEVTENA Offset */
+#define DWT_CTRL_CPIEVTENA                                 (0x00020000)          /*  */
+/* DWT_CTRL[DWT_CTRL_EXCEVTENA] Bits */
+#define DWT_CTRL_EXCEVTENA_OFS                             (18)                  /* EXCEVTENA Offset */
+#define DWT_CTRL_EXCEVTENA                                 (0x00040000)          /*  */
+/* DWT_CTRL[DWT_CTRL_SLEEPEVTENA] Bits */
+#define DWT_CTRL_SLEEPEVTENA_OFS                           (19)                  /* SLEEPEVTENA Offset */
+#define DWT_CTRL_SLEEPEVTENA                               (0x00080000)          /*  */
+/* DWT_CTRL[DWT_CTRL_LSUEVTENA] Bits */
+#define DWT_CTRL_LSUEVTENA_OFS                             (20)                  /* LSUEVTENA Offset */
+#define DWT_CTRL_LSUEVTENA                                 (0x00100000)          /*  */
+/* DWT_CTRL[DWT_CTRL_FOLDEVTENA] Bits */
+#define DWT_CTRL_FOLDEVTENA_OFS                            (21)                  /* FOLDEVTENA Offset */
+#define DWT_CTRL_FOLDEVTENA                                (0x00200000)          /*  */
+/* DWT_CTRL[DWT_CTRL_CYCEVTENA] Bits */
+#define DWT_CTRL_CYCEVTENA_OFS                             (22)                  /* CYCEVTENA Offset */
+#define DWT_CTRL_CYCEVTENA                                 (0x00400000)          /*  */
+/* DWT_CTRL[DWT_CTRL_NOPRFCNT] Bits */
+#define DWT_CTRL_NOPRFCNT_OFS                              (24)                  /* NOPRFCNT Offset */
+#define DWT_CTRL_NOPRFCNT                                  (0x01000000)          /*  */
+/* DWT_CTRL[DWT_CTRL_NOCYCCNT] Bits */
+#define DWT_CTRL_NOCYCCNT_OFS                              (25)                  /* NOCYCCNT Offset */
+#define DWT_CTRL_NOCYCCNT                                  (0x02000000)          /*  */
+/* DWT_CPICNT[DWT_CPICNT_CPICNT] Bits */
+#define DWT_CPICNT_CPICNT_OFS                              ( 0)                  /* CPICNT Offset */
+#define DWT_CPICNT_CPICNT_M                                (0x000000ff)          /*  */
+/* DWT_EXCCNT[DWT_EXCCNT_EXCCNT] Bits */
+#define DWT_EXCCNT_EXCCNT_OFS                              ( 0)                  /* EXCCNT Offset */
+#define DWT_EXCCNT_EXCCNT_M                                (0x000000ff)          /*  */
+/* DWT_SLEEPCNT[DWT_SLEEPCNT_SLEEPCNT] Bits */
+#define DWT_SLEEPCNT_SLEEPCNT_OFS                          ( 0)                  /* SLEEPCNT Offset */
+#define DWT_SLEEPCNT_SLEEPCNT_M                            (0x000000ff)          /*  */
+/* DWT_LSUCNT[DWT_LSUCNT_LSUCNT] Bits */
+#define DWT_LSUCNT_LSUCNT_OFS                              ( 0)                  /* LSUCNT Offset */
+#define DWT_LSUCNT_LSUCNT_M                                (0x000000ff)          /*  */
+/* DWT_FOLDCNT[DWT_FOLDCNT_FOLDCNT] Bits */
+#define DWT_FOLDCNT_FOLDCNT_OFS                            ( 0)                  /* FOLDCNT Offset */
+#define DWT_FOLDCNT_FOLDCNT_M                              (0x000000ff)          /*  */
+/* DWT_MASK0[DWT_MASK0_MASK] Bits */
+#define DWT_MASK0_MASK_OFS                                 ( 0)                  /* MASK Offset */
+#define DWT_MASK0_MASK_M                                   (0x0000000f)          /*  */
+/* DWT_FUNCTION0[DWT_FUNCTION0_FUNCTION] Bits */
+#define DWT_FUNCTION0_FUNCTION_OFS                         ( 0)                  /* FUNCTION Offset */
+#define DWT_FUNCTION0_FUNCTION_M                           (0x0000000f)          /*  */
+#define DWT_FUNCTION0_FUNCTION0                            (0x00000001)          /*  */
+#define DWT_FUNCTION0_FUNCTION1                            (0x00000002)          /*  */
+#define DWT_FUNCTION0_FUNCTION2                            (0x00000004)          /*  */
+#define DWT_FUNCTION0_FUNCTION3                            (0x00000008)          /*  */
+#define DWT_FUNCTION0_FUNCTION_0                           (0x00000000)          /* Disabled */
+#define DWT_FUNCTION0_FUNCTION_1                           (0x00000001)          /* EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM */
+#define DWT_FUNCTION0_FUNCTION_2                           (0x00000002)          /* EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. */
+#define DWT_FUNCTION0_FUNCTION_3                           (0x00000003)          /* EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. */
+#define DWT_FUNCTION0_FUNCTION_4                           (0x00000004)          /* Watchpoint on PC match. */
+#define DWT_FUNCTION0_FUNCTION_5                           (0x00000005)          /* Watchpoint on read. */
+#define DWT_FUNCTION0_FUNCTION_6                           (0x00000006)          /* Watchpoint on write. */
+#define DWT_FUNCTION0_FUNCTION_7                           (0x00000007)          /* Watchpoint on read or write. */
+#define DWT_FUNCTION0_FUNCTION_8                           (0x00000008)          /* ETM trigger on PC match */
+#define DWT_FUNCTION0_FUNCTION_9                           (0x00000009)          /* ETM trigger on read */
+#define DWT_FUNCTION0_FUNCTION_10                          (0x0000000a)          /* ETM trigger on write */
+#define DWT_FUNCTION0_FUNCTION_11                          (0x0000000b)          /* ETM trigger on read or write */
+#define DWT_FUNCTION0_FUNCTION_12                          (0x0000000c)          /* EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers */
+#define DWT_FUNCTION0_FUNCTION_13                          (0x0000000d)          /* EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers */
+#define DWT_FUNCTION0_FUNCTION_14                          (0x0000000e)          /* EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers */
+#define DWT_FUNCTION0_FUNCTION_15                          (0x0000000f)          /* EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers */
+/* DWT_FUNCTION0[DWT_FUNCTION0_EMITRANGE] Bits */
+#define DWT_FUNCTION0_EMITRANGE_OFS                        ( 5)                  /* EMITRANGE Offset */
+#define DWT_FUNCTION0_EMITRANGE                            (0x00000020)          /*  */
+/* DWT_FUNCTION0[DWT_FUNCTION0_DATAVMATCH] Bits */
+#define DWT_FUNCTION0_DATAVMATCH_OFS                       ( 8)                  /* DATAVMATCH Offset */
+#define DWT_FUNCTION0_DATAVMATCH                           (0x00000100)          /*  */
+/* DWT_FUNCTION0[DWT_FUNCTION0_LNK1ENA] Bits */
+#define DWT_FUNCTION0_LNK1ENA_OFS                          ( 9)                  /* LNK1ENA Offset */
+#define DWT_FUNCTION0_LNK1ENA                              (0x00000200)          /*  */
+/* DWT_FUNCTION0[DWT_FUNCTION0_DATAVSIZE] Bits */
+#define DWT_FUNCTION0_DATAVSIZE_OFS                        (10)                  /* DATAVSIZE Offset */
+#define DWT_FUNCTION0_DATAVSIZE_M                          (0x00000c00)          /*  */
+#define DWT_FUNCTION0_DATAVSIZE0                           (0x00000400)          /*  */
+#define DWT_FUNCTION0_DATAVSIZE1                           (0x00000800)          /*  */
+#define DWT_FUNCTION0_DATAVSIZE_0                          (0x00000000)          /* byte */
+#define DWT_FUNCTION0_DATAVSIZE_1                          (0x00000400)          /* halfword */
+#define DWT_FUNCTION0_DATAVSIZE_2                          (0x00000800)          /* word */
+#define DWT_FUNCTION0_DATAVSIZE_3                          (0x00000c00)          /* Unpredictable. */
+/* DWT_FUNCTION0[DWT_FUNCTION0_DATAVADDR0] Bits */
+#define DWT_FUNCTION0_DATAVADDR0_OFS                       (12)                  /* DATAVADDR0 Offset */
+#define DWT_FUNCTION0_DATAVADDR0_M                         (0x0000f000)          /*  */
+/* DWT_FUNCTION0[DWT_FUNCTION0_DATAVADDR1] Bits */
+#define DWT_FUNCTION0_DATAVADDR1_OFS                       (16)                  /* DATAVADDR1 Offset */
+#define DWT_FUNCTION0_DATAVADDR1_M                         (0x000f0000)          /*  */
+/* DWT_FUNCTION0[DWT_FUNCTION0_MATCHED] Bits */
+#define DWT_FUNCTION0_MATCHED_OFS                          (24)                  /* MATCHED Offset */
+#define DWT_FUNCTION0_MATCHED                              (0x01000000)          /*  */
+/* DWT_MASK1[DWT_MASK1_MASK] Bits */
+#define DWT_MASK1_MASK_OFS                                 ( 0)                  /* MASK Offset */
+#define DWT_MASK1_MASK_M                                   (0x0000000f)          /*  */
+/* DWT_FUNCTION1[DWT_FUNCTION1_FUNCTION] Bits */
+#define DWT_FUNCTION1_FUNCTION_OFS                         ( 0)                  /* FUNCTION Offset */
+#define DWT_FUNCTION1_FUNCTION_M                           (0x0000000f)          /*  */
+#define DWT_FUNCTION1_FUNCTION0                            (0x00000001)          /*  */
+#define DWT_FUNCTION1_FUNCTION1                            (0x00000002)          /*  */
+#define DWT_FUNCTION1_FUNCTION2                            (0x00000004)          /*  */
+#define DWT_FUNCTION1_FUNCTION3                            (0x00000008)          /*  */
+#define DWT_FUNCTION1_FUNCTION_0                           (0x00000000)          /* Disabled */
+#define DWT_FUNCTION1_FUNCTION_1                           (0x00000001)          /* EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM */
+#define DWT_FUNCTION1_FUNCTION_2                           (0x00000002)          /* EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. */
+#define DWT_FUNCTION1_FUNCTION_3                           (0x00000003)          /* EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. */
+#define DWT_FUNCTION1_FUNCTION_4                           (0x00000004)          /* Watchpoint on PC match. */
+#define DWT_FUNCTION1_FUNCTION_5                           (0x00000005)          /* Watchpoint on read. */
+#define DWT_FUNCTION1_FUNCTION_6                           (0x00000006)          /* Watchpoint on write. */
+#define DWT_FUNCTION1_FUNCTION_7                           (0x00000007)          /* Watchpoint on read or write. */
+#define DWT_FUNCTION1_FUNCTION_8                           (0x00000008)          /* ETM trigger on PC match */
+#define DWT_FUNCTION1_FUNCTION_9                           (0x00000009)          /* ETM trigger on read */
+#define DWT_FUNCTION1_FUNCTION_10                          (0x0000000a)          /* ETM trigger on write */
+#define DWT_FUNCTION1_FUNCTION_11                          (0x0000000b)          /* ETM trigger on read or write */
+#define DWT_FUNCTION1_FUNCTION_12                          (0x0000000c)          /* EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers */
+#define DWT_FUNCTION1_FUNCTION_13                          (0x0000000d)          /* EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers */
+#define DWT_FUNCTION1_FUNCTION_14                          (0x0000000e)          /* EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers */
+#define DWT_FUNCTION1_FUNCTION_15                          (0x0000000f)          /* EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers */
+/* DWT_FUNCTION1[DWT_FUNCTION1_EMITRANGE] Bits */
+#define DWT_FUNCTION1_EMITRANGE_OFS                        ( 5)                  /* EMITRANGE Offset */
+#define DWT_FUNCTION1_EMITRANGE                            (0x00000020)          /*  */
+/* DWT_FUNCTION1[DWT_FUNCTION1_CYCMATCH] Bits */
+#define DWT_FUNCTION1_CYCMATCH_OFS                         ( 7)                  /* CYCMATCH Offset */
+#define DWT_FUNCTION1_CYCMATCH                             (0x00000080)          /*  */
+/* DWT_FUNCTION1[DWT_FUNCTION1_DATAVMATCH] Bits */
+#define DWT_FUNCTION1_DATAVMATCH_OFS                       ( 8)                  /* DATAVMATCH Offset */
+#define DWT_FUNCTION1_DATAVMATCH                           (0x00000100)          /*  */
+/* DWT_FUNCTION1[DWT_FUNCTION1_LNK1ENA] Bits */
+#define DWT_FUNCTION1_LNK1ENA_OFS                          ( 9)                  /* LNK1ENA Offset */
+#define DWT_FUNCTION1_LNK1ENA                              (0x00000200)          /*  */
+/* DWT_FUNCTION1[DWT_FUNCTION1_DATAVSIZE] Bits */
+#define DWT_FUNCTION1_DATAVSIZE_OFS                        (10)                  /* DATAVSIZE Offset */
+#define DWT_FUNCTION1_DATAVSIZE_M                          (0x00000c00)          /*  */
+#define DWT_FUNCTION1_DATAVSIZE0                           (0x00000400)          /*  */
+#define DWT_FUNCTION1_DATAVSIZE1                           (0x00000800)          /*  */
+#define DWT_FUNCTION1_DATAVSIZE_0                          (0x00000000)          /* byte */
+#define DWT_FUNCTION1_DATAVSIZE_1                          (0x00000400)          /* halfword */
+#define DWT_FUNCTION1_DATAVSIZE_2                          (0x00000800)          /* word */
+#define DWT_FUNCTION1_DATAVSIZE_3                          (0x00000c00)          /* Unpredictable. */
+/* DWT_FUNCTION1[DWT_FUNCTION1_DATAVADDR0] Bits */
+#define DWT_FUNCTION1_DATAVADDR0_OFS                       (12)                  /* DATAVADDR0 Offset */
+#define DWT_FUNCTION1_DATAVADDR0_M                         (0x0000f000)          /*  */
+/* DWT_FUNCTION1[DWT_FUNCTION1_DATAVADDR1] Bits */
+#define DWT_FUNCTION1_DATAVADDR1_OFS                       (16)                  /* DATAVADDR1 Offset */
+#define DWT_FUNCTION1_DATAVADDR1_M                         (0x000f0000)          /*  */
+/* DWT_FUNCTION1[DWT_FUNCTION1_MATCHED] Bits */
+#define DWT_FUNCTION1_MATCHED_OFS                          (24)                  /* MATCHED Offset */
+#define DWT_FUNCTION1_MATCHED                              (0x01000000)          /*  */
+/* DWT_MASK2[DWT_MASK2_MASK] Bits */
+#define DWT_MASK2_MASK_OFS                                 ( 0)                  /* MASK Offset */
+#define DWT_MASK2_MASK_M                                   (0x0000000f)          /*  */
+/* DWT_FUNCTION2[DWT_FUNCTION2_FUNCTION] Bits */
+#define DWT_FUNCTION2_FUNCTION_OFS                         ( 0)                  /* FUNCTION Offset */
+#define DWT_FUNCTION2_FUNCTION_M                           (0x0000000f)          /*  */
+#define DWT_FUNCTION2_FUNCTION0                            (0x00000001)          /*  */
+#define DWT_FUNCTION2_FUNCTION1                            (0x00000002)          /*  */
+#define DWT_FUNCTION2_FUNCTION2                            (0x00000004)          /*  */
+#define DWT_FUNCTION2_FUNCTION3                            (0x00000008)          /*  */
+#define DWT_FUNCTION2_FUNCTION_0                           (0x00000000)          /* Disabled */
+#define DWT_FUNCTION2_FUNCTION_1                           (0x00000001)          /* EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM */
+#define DWT_FUNCTION2_FUNCTION_2                           (0x00000002)          /* EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. */
+#define DWT_FUNCTION2_FUNCTION_3                           (0x00000003)          /* EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. */
+#define DWT_FUNCTION2_FUNCTION_4                           (0x00000004)          /* Watchpoint on PC match. */
+#define DWT_FUNCTION2_FUNCTION_5                           (0x00000005)          /* Watchpoint on read. */
+#define DWT_FUNCTION2_FUNCTION_6                           (0x00000006)          /* Watchpoint on write. */
+#define DWT_FUNCTION2_FUNCTION_7                           (0x00000007)          /* Watchpoint on read or write. */
+#define DWT_FUNCTION2_FUNCTION_8                           (0x00000008)          /* ETM trigger on PC match */
+#define DWT_FUNCTION2_FUNCTION_9                           (0x00000009)          /* ETM trigger on read */
+#define DWT_FUNCTION2_FUNCTION_10                          (0x0000000a)          /* ETM trigger on write */
+#define DWT_FUNCTION2_FUNCTION_11                          (0x0000000b)          /* ETM trigger on read or write */
+#define DWT_FUNCTION2_FUNCTION_12                          (0x0000000c)          /* EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers */
+#define DWT_FUNCTION2_FUNCTION_13                          (0x0000000d)          /* EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers */
+#define DWT_FUNCTION2_FUNCTION_14                          (0x0000000e)          /* EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers */
+#define DWT_FUNCTION2_FUNCTION_15                          (0x0000000f)          /* EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers */
+/* DWT_FUNCTION2[DWT_FUNCTION2_EMITRANGE] Bits */
+#define DWT_FUNCTION2_EMITRANGE_OFS                        ( 5)                  /* EMITRANGE Offset */
+#define DWT_FUNCTION2_EMITRANGE                            (0x00000020)          /*  */
+/* DWT_FUNCTION2[DWT_FUNCTION2_DATAVMATCH] Bits */
+#define DWT_FUNCTION2_DATAVMATCH_OFS                       ( 8)                  /* DATAVMATCH Offset */
+#define DWT_FUNCTION2_DATAVMATCH                           (0x00000100)          /*  */
+/* DWT_FUNCTION2[DWT_FUNCTION2_LNK1ENA] Bits */
+#define DWT_FUNCTION2_LNK1ENA_OFS                          ( 9)                  /* LNK1ENA Offset */
+#define DWT_FUNCTION2_LNK1ENA                              (0x00000200)          /*  */
+/* DWT_FUNCTION2[DWT_FUNCTION2_DATAVSIZE] Bits */
+#define DWT_FUNCTION2_DATAVSIZE_OFS                        (10)                  /* DATAVSIZE Offset */
+#define DWT_FUNCTION2_DATAVSIZE_M                          (0x00000c00)          /*  */
+#define DWT_FUNCTION2_DATAVSIZE0                           (0x00000400)          /*  */
+#define DWT_FUNCTION2_DATAVSIZE1                           (0x00000800)          /*  */
+#define DWT_FUNCTION2_DATAVSIZE_0                          (0x00000000)          /* byte */
+#define DWT_FUNCTION2_DATAVSIZE_1                          (0x00000400)          /* halfword */
+#define DWT_FUNCTION2_DATAVSIZE_2                          (0x00000800)          /* word */
+#define DWT_FUNCTION2_DATAVSIZE_3                          (0x00000c00)          /* Unpredictable. */
+/* DWT_FUNCTION2[DWT_FUNCTION2_DATAVADDR0] Bits */
+#define DWT_FUNCTION2_DATAVADDR0_OFS                       (12)                  /* DATAVADDR0 Offset */
+#define DWT_FUNCTION2_DATAVADDR0_M                         (0x0000f000)          /*  */
+/* DWT_FUNCTION2[DWT_FUNCTION2_DATAVADDR1] Bits */
+#define DWT_FUNCTION2_DATAVADDR1_OFS                       (16)                  /* DATAVADDR1 Offset */
+#define DWT_FUNCTION2_DATAVADDR1_M                         (0x000f0000)          /*  */
+/* DWT_FUNCTION2[DWT_FUNCTION2_MATCHED] Bits */
+#define DWT_FUNCTION2_MATCHED_OFS                          (24)                  /* MATCHED Offset */
+#define DWT_FUNCTION2_MATCHED                              (0x01000000)          /*  */
+/* DWT_MASK3[DWT_MASK3_MASK] Bits */
+#define DWT_MASK3_MASK_OFS                                 ( 0)                  /* MASK Offset */
+#define DWT_MASK3_MASK_M                                   (0x0000000f)          /*  */
+/* DWT_FUNCTION3[DWT_FUNCTION3_FUNCTION] Bits */
+#define DWT_FUNCTION3_FUNCTION_OFS                         ( 0)                  /* FUNCTION Offset */
+#define DWT_FUNCTION3_FUNCTION_M                           (0x0000000f)          /*  */
+#define DWT_FUNCTION3_FUNCTION0                            (0x00000001)          /*  */
+#define DWT_FUNCTION3_FUNCTION1                            (0x00000002)          /*  */
+#define DWT_FUNCTION3_FUNCTION2                            (0x00000004)          /*  */
+#define DWT_FUNCTION3_FUNCTION3                            (0x00000008)          /*  */
+#define DWT_FUNCTION3_FUNCTION_0                           (0x00000000)          /* Disabled */
+#define DWT_FUNCTION3_FUNCTION_1                           (0x00000001)          /* EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM */
+#define DWT_FUNCTION3_FUNCTION_2                           (0x00000002)          /* EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. */
+#define DWT_FUNCTION3_FUNCTION_3                           (0x00000003)          /* EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. */
+#define DWT_FUNCTION3_FUNCTION_4                           (0x00000004)          /* Watchpoint on PC match. */
+#define DWT_FUNCTION3_FUNCTION_5                           (0x00000005)          /* Watchpoint on read. */
+#define DWT_FUNCTION3_FUNCTION_6                           (0x00000006)          /* Watchpoint on write. */
+#define DWT_FUNCTION3_FUNCTION_7                           (0x00000007)          /* Watchpoint on read or write. */
+#define DWT_FUNCTION3_FUNCTION_8                           (0x00000008)          /* ETM trigger on PC match */
+#define DWT_FUNCTION3_FUNCTION_9                           (0x00000009)          /* ETM trigger on read */
+#define DWT_FUNCTION3_FUNCTION_10                          (0x0000000a)          /* ETM trigger on write */
+#define DWT_FUNCTION3_FUNCTION_11                          (0x0000000b)          /* ETM trigger on read or write */
+#define DWT_FUNCTION3_FUNCTION_12                          (0x0000000c)          /* EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers */
+#define DWT_FUNCTION3_FUNCTION_13                          (0x0000000d)          /* EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers */
+#define DWT_FUNCTION3_FUNCTION_14                          (0x0000000e)          /* EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers */
+#define DWT_FUNCTION3_FUNCTION_15                          (0x0000000f)          /* EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers */
+/* DWT_FUNCTION3[DWT_FUNCTION3_EMITRANGE] Bits */
+#define DWT_FUNCTION3_EMITRANGE_OFS                        ( 5)                  /* EMITRANGE Offset */
+#define DWT_FUNCTION3_EMITRANGE                            (0x00000020)          /*  */
+/* DWT_FUNCTION3[DWT_FUNCTION3_DATAVMATCH] Bits */
+#define DWT_FUNCTION3_DATAVMATCH_OFS                       ( 8)                  /* DATAVMATCH Offset */
+#define DWT_FUNCTION3_DATAVMATCH                           (0x00000100)          /*  */
+/* DWT_FUNCTION3[DWT_FUNCTION3_LNK1ENA] Bits */
+#define DWT_FUNCTION3_LNK1ENA_OFS                          ( 9)                  /* LNK1ENA Offset */
+#define DWT_FUNCTION3_LNK1ENA                              (0x00000200)          /*  */
+/* DWT_FUNCTION3[DWT_FUNCTION3_DATAVSIZE] Bits */
+#define DWT_FUNCTION3_DATAVSIZE_OFS                        (10)                  /* DATAVSIZE Offset */
+#define DWT_FUNCTION3_DATAVSIZE_M                          (0x00000c00)          /*  */
+#define DWT_FUNCTION3_DATAVSIZE0                           (0x00000400)          /*  */
+#define DWT_FUNCTION3_DATAVSIZE1                           (0x00000800)          /*  */
+#define DWT_FUNCTION3_DATAVSIZE_0                          (0x00000000)          /* byte */
+#define DWT_FUNCTION3_DATAVSIZE_1                          (0x00000400)          /* halfword */
+#define DWT_FUNCTION3_DATAVSIZE_2                          (0x00000800)          /* word */
+#define DWT_FUNCTION3_DATAVSIZE_3                          (0x00000c00)          /* Unpredictable. */
+/* DWT_FUNCTION3[DWT_FUNCTION3_DATAVADDR0] Bits */
+#define DWT_FUNCTION3_DATAVADDR0_OFS                       (12)                  /* DATAVADDR0 Offset */
+#define DWT_FUNCTION3_DATAVADDR0_M                         (0x0000f000)          /*  */
+/* DWT_FUNCTION3[DWT_FUNCTION3_DATAVADDR1] Bits */
+#define DWT_FUNCTION3_DATAVADDR1_OFS                       (16)                  /* DATAVADDR1 Offset */
+#define DWT_FUNCTION3_DATAVADDR1_M                         (0x000f0000)          /*  */
+/* DWT_FUNCTION3[DWT_FUNCTION3_MATCHED] Bits */
+#define DWT_FUNCTION3_MATCHED_OFS                          (24)                  /* MATCHED Offset */
+#define DWT_FUNCTION3_MATCHED                              (0x01000000)          /*  */
+
+
+//*****************************************************************************
+// EUSCI_A0 Bits
+//*****************************************************************************
+/* UCA0CTLW0[UCSWRST] Bits */
+#define UCSWRST_OFS                                        ( 0)                  /* UCSWRST Offset */
+#define UCSWRST                                            (0x0001)              /* Software reset enable */
+/* UCA0CTLW0[UCTXBRK] Bits */
+#define UCTXBRK_OFS                                        ( 1)                  /* UCTXBRK Offset */
+#define UCTXBRK                                            (0x0002)              /* Transmit break */
+/* UCA0CTLW0[UCTXADDR] Bits */
+#define UCTXADDR_OFS                                       ( 2)                  /* UCTXADDR Offset */
+#define UCTXADDR                                           (0x0004)              /* Transmit address */
+/* UCA0CTLW0[UCDORM] Bits */
+#define UCDORM_OFS                                         ( 3)                  /* UCDORM Offset */
+#define UCDORM                                             (0x0008)              /* Dormant */
+/* UCA0CTLW0[UCBRKIE] Bits */
+#define UCBRKIE_OFS                                        ( 4)                  /* UCBRKIE Offset */
+#define UCBRKIE                                            (0x0010)              /* Receive break character interrupt enable */
+/* UCA0CTLW0[UCRXEIE] Bits */
+#define UCRXEIE_OFS                                        ( 5)                  /* UCRXEIE Offset */
+#define UCRXEIE                                            (0x0020)              /* Receive erroneous-character interrupt enable */
+/* UCA0CTLW0[UCSSEL] Bits */
+#define UCSSEL_OFS                                         ( 6)                  /* UCSSEL Offset */
+#define UCSSEL_M                                           (0x00c0)              /* eUSCI_A clock source select */
+#define UCSSEL0                                            (0x0040)              /* eUSCI_A clock source select */
+#define UCSSEL1                                            (0x0080)              /* eUSCI_A clock source select */
+#define UCSSEL_0                                           (0x0000)              /* UCLK */
+#define UCSSEL_1                                           (0x0040)              /* ACLK */
+#define UCSSEL_2                                           (0x0080)              /* SMCLK */
+#define UCSSEL__UCLK                                       (0x0000)              /* UCLK */
+#define UCSSEL__ACLK                                       (0x0040)              /* ACLK */
+#define UCSSEL__SMCLK                                      (0x0080)              /* SMCLK */
+/* UCA0CTLW0[UCSYNC] Bits */
+#define UCSYNC_OFS                                         ( 8)                  /* UCSYNC Offset */
+#define UCSYNC                                             (0x0100)              /* Synchronous mode enable */
+/* UCA0CTLW0[UCMODE] Bits */
+#define UCMODE_OFS                                         ( 9)                  /* UCMODE Offset */
+#define UCMODE_M                                           (0x0600)              /* eUSCI_A mode */
+#define UCMODE0                                            (0x0200)              /* eUSCI_A mode */
+#define UCMODE1                                            (0x0400)              /* eUSCI_A mode */
+#define UCMODE_0                                           (0x0000)              /* UART mode */
+#define UCMODE_1                                           (0x0200)              /* Idle-line multiprocessor mode */
+#define UCMODE_2                                           (0x0400)              /* Address-bit multiprocessor mode */
+#define UCMODE_3                                           (0x0600)              /* UART mode with automatic baud-rate detection */
+/* UCA0CTLW0[UCSPB] Bits */
+#define UCSPB_OFS                                          (11)                  /* UCSPB Offset */
+#define UCSPB                                              (0x0800)              /* Stop bit select */
+/* UCA0CTLW0[UC7BIT] Bits */
+#define UC7BIT_OFS                                         (12)                  /* UC7BIT Offset */
+#define UC7BIT                                             (0x1000)              /* Character length */
+/* UCA0CTLW0[UCMSB] Bits */
+#define UCMSB_OFS                                          (13)                  /* UCMSB Offset */
+#define UCMSB                                              (0x2000)              /* MSB first select */
+/* UCA0CTLW0[UCPAR] Bits */
+#define UCPAR_OFS                                          (14)                  /* UCPAR Offset */
+#define UCPAR                                              (0x4000)              /* Parity select */
+/* UCA0CTLW0[UCPEN] Bits */
+#define UCPEN_OFS                                          (15)                  /* UCPEN Offset */
+#define UCPEN                                              (0x8000)              /* Parity enable */
+/* UCA0CTLW0_SPI[UCSWRST] Bits */
+//#define UCSWRST_OFS                                        ( 0)                  /* UCSWRST Offset */
+//#define UCSWRST                                            (0x0001)              /* Software reset enable */
+/* UCA0CTLW0_SPI[UCSTEM] Bits */
+#define UCSTEM_OFS                                         ( 1)                  /* UCSTEM Offset */
+#define UCSTEM                                             (0x0002)              /* STE mode select in master mode. */
+/* UCA0CTLW0_SPI[UCSSEL] Bits */
+//#define UCSSEL_OFS                                         ( 6)                  /* UCSSEL Offset */
+//#define UCSSEL_M                                           (0x00c0)              /* eUSCI_A clock source select */
+//#define UCSSEL0                                            (0x0040)              /* eUSCI_A clock source select */
+//#define UCSSEL1                                            (0x0080)              /* eUSCI_A clock source select */
+//#define UCSSEL_1                                           (0x0040)              /* ACLK */
+//#define UCSSEL_2                                           (0x0080)              /* SMCLK */
+//#define UCSSEL_0                                           (0x0000)              /* Reserved */
+//#define UCSSEL__ACLK                                       (0x0040)              /* ACLK */
+//#define UCSSEL__SMCLK                                      (0x0080)              /* SMCLK */
+/* UCA0CTLW0_SPI[UCSYNC] Bits */
+//#define UCSYNC_OFS                                         ( 8)                  /* UCSYNC Offset */
+//#define UCSYNC                                             (0x0100)              /* Synchronous mode enable */
+/* UCA0CTLW0_SPI[UCMODE] Bits */
+//#define UCMODE_OFS                                         ( 9)                  /* UCMODE Offset */
+//#define UCMODE_M                                           (0x0600)              /* eUSCI mode */
+//#define UCMODE0                                            (0x0200)              /* eUSCI mode */
+//#define UCMODE1                                            (0x0400)              /* eUSCI mode */
+//#define UCMODE_0                                           (0x0000)              /* 3-pin SPI */
+//#define UCMODE_1                                           (0x0200)              /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */
+//#define UCMODE_2                                           (0x0400)              /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */
+/* UCA0CTLW0_SPI[UCMST] Bits */
+#define UCMST_OFS                                          (11)                  /* UCMST Offset */
+#define UCMST                                              (0x0800)              /* Master mode select */
+/* UCA0CTLW0_SPI[UC7BIT] Bits */
+//#define UC7BIT_OFS                                         (12)                  /* UC7BIT Offset */
+//#define UC7BIT                                             (0x1000)              /* Character length */
+/* UCA0CTLW0_SPI[UCMSB] Bits */
+//#define UCMSB_OFS                                          (13)                  /* UCMSB Offset */
+//#define UCMSB                                              (0x2000)              /* MSB first select */
+/* UCA0CTLW0_SPI[UCCKPL] Bits */
+#define UCCKPL_OFS                                         (14)                  /* UCCKPL Offset */
+#define UCCKPL                                             (0x4000)              /* Clock polarity select */
+/* UCA0CTLW0_SPI[UCCKPH] Bits */
+#define UCCKPH_OFS                                         (15)                  /* UCCKPH Offset */
+#define UCCKPH                                             (0x8000)              /* Clock phase select */
+/* UCA0CTLW1[UCGLIT] Bits */
+#define UCGLIT_OFS                                         ( 0)                  /* UCGLIT Offset */
+#define UCGLIT_M                                           (0x0003)              /* Deglitch time */
+#define UCGLIT0                                            (0x0001)              /* Deglitch time */
+#define UCGLIT1                                            (0x0002)              /* Deglitch time */
+#define UCGLIT_0                                           (0x0000)              /* Approximately 2 ns (equivalent of 1 delay element) */
+#define UCGLIT_1                                           (0x0001)              /* Approximately 50 ns */
+#define UCGLIT_2                                           (0x0002)              /* Approximately 100 ns */
+#define UCGLIT_3                                           (0x0003)              /* Approximately 200 ns */
+/* UCA0MCTLW[UCOS16] Bits */
+#define UCOS16_OFS                                         ( 0)                  /* UCOS16 Offset */
+#define UCOS16                                             (0x0001)              /* Oversampling mode enabled */
+/* UCA0MCTLW[UCBRF] Bits */
+#define UCBRF_OFS                                          ( 4)                  /* UCBRF Offset */
+#define UCBRF_M                                            (0x00f0)              /* First modulation stage select */
+/* UCA0MCTLW[UCBRS] Bits */
+#define UCBRS_OFS                                          ( 8)                  /* UCBRS Offset */
+#define UCBRS_M                                            (0xff00)              /* Second modulation stage select */
+/* UCA0STATW[UCBUSY] Bits */
+#define UCBUSY_OFS                                         ( 0)                  /* UCBUSY Offset */
+#define UCBUSY                                             (0x0001)              /* eUSCI_A busy */
+/* UCA0STATW[UCADDR_UCIDLE] Bits */
+#define UCADDR_UCIDLE_OFS                                  ( 1)                  /* UCADDR_UCIDLE Offset */
+#define UCADDR_UCIDLE                                      (0x0002)              /* Address received / Idle line detected */
+/* UCA0STATW[UCRXERR] Bits */
+#define UCRXERR_OFS                                        ( 2)                  /* UCRXERR Offset */
+#define UCRXERR                                            (0x0004)              /* Receive error flag */
+/* UCA0STATW[UCBRK] Bits */
+#define UCBRK_OFS                                          ( 3)                  /* UCBRK Offset */
+#define UCBRK                                              (0x0008)              /* Break detect flag */
+/* UCA0STATW[UCPE] Bits */
+#define UCPE_OFS                                           ( 4)                  /* UCPE Offset */
+#define UCPE                                               (0x0010)              /*  */
+/* UCA0STATW[UCOE] Bits */
+#define UCOE_OFS                                           ( 5)                  /* UCOE Offset */
+#define UCOE                                               (0x0020)              /* Overrun error flag */
+/* UCA0STATW[UCFE] Bits */
+#define UCFE_OFS                                           ( 6)                  /* UCFE Offset */
+#define UCFE                                               (0x0040)              /* Framing error flag */
+/* UCA0STATW[UCLISTEN] Bits */
+#define UCLISTEN_OFS                                       ( 7)                  /* UCLISTEN Offset */
+#define UCLISTEN                                           (0x0080)              /* Listen enable */
+/* UCA0STATW_SPI[UCBUSY] Bits */
+//#define UCBUSY_OFS                                         ( 0)                  /* UCBUSY Offset */
+//#define UCBUSY                                             (0x0001)              /* eUSCI_A busy */
+/* UCA0STATW_SPI[UCOE] Bits */
+//#define UCOE_OFS                                           ( 5)                  /* UCOE Offset */
+//#define UCOE                                               (0x0020)              /* Overrun error flag */
+/* UCA0STATW_SPI[UCFE] Bits */
+//#define UCFE_OFS                                           ( 6)                  /* UCFE Offset */
+//#define UCFE                                               (0x0040)              /* Framing error flag */
+/* UCA0STATW_SPI[UCLISTEN] Bits */
+//#define UCLISTEN_OFS                                       ( 7)                  /* UCLISTEN Offset */
+//#define UCLISTEN                                           (0x0080)              /* Listen enable */
+/* UCA0RXBUF[UCRXBUF] Bits */
+#define UCRXBUF_OFS                                        ( 0)                  /* UCRXBUF Offset */
+#define UCRXBUF_M                                          (0x00ff)              /* Receive data buffer */
+/* UCA0RXBUF_SPI[UCRXBUF] Bits */
+//#define UCRXBUF_OFS                                        ( 0)                  /* UCRXBUF Offset */
+//#define UCRXBUF_M                                          (0x00ff)              /* Receive data buffer */
+/* UCA0TXBUF[UCTXBUF] Bits */
+#define UCTXBUF_OFS                                        ( 0)                  /* UCTXBUF Offset */
+#define UCTXBUF_M                                          (0x00ff)              /* Transmit data buffer */
+/* UCA0TXBUF_SPI[UCTXBUF] Bits */
+//#define UCTXBUF_OFS                                        ( 0)                  /* UCTXBUF Offset */
+//#define UCTXBUF_M                                          (0x00ff)              /* Transmit data buffer */
+/* UCA0ABCTL[UCABDEN] Bits */
+#define UCABDEN_OFS                                        ( 0)                  /* UCABDEN Offset */
+#define UCABDEN                                            (0x0001)              /* Automatic baud-rate detect enable */
+/* UCA0ABCTL[UCBTOE] Bits */
+#define UCBTOE_OFS                                         ( 2)                  /* UCBTOE Offset */
+#define UCBTOE                                             (0x0004)              /* Break time out error */
+/* UCA0ABCTL[UCSTOE] Bits */
+#define UCSTOE_OFS                                         ( 3)                  /* UCSTOE Offset */
+#define UCSTOE                                             (0x0008)              /* Synch field time out error */
+/* UCA0ABCTL[UCDELIM] Bits */
+#define UCDELIM_OFS                                        ( 4)                  /* UCDELIM Offset */
+#define UCDELIM_M                                          (0x0030)              /* Break/synch delimiter length */
+#define UCDELIM0                                           (0x0010)              /* Break/synch delimiter length */
+#define UCDELIM1                                           (0x0020)              /* Break/synch delimiter length */
+#define UCDELIM_0                                          (0x0000)              /* 1 bit time */
+#define UCDELIM_1                                          (0x0010)              /* 2 bit times */
+#define UCDELIM_2                                          (0x0020)              /* 3 bit times */
+#define UCDELIM_3                                          (0x0030)              /* 4 bit times */
+/* UCA0IRCTL[UCIREN] Bits */
+#define UCIREN_OFS                                         ( 0)                  /* UCIREN Offset */
+#define UCIREN                                             (0x0001)              /* IrDA encoder/decoder enable */
+/* UCA0IRCTL[UCIRTXCLK] Bits */
+#define UCIRTXCLK_OFS                                      ( 1)                  /* UCIRTXCLK Offset */
+#define UCIRTXCLK                                          (0x0002)              /* IrDA transmit pulse clock select */
+/* UCA0IRCTL[UCIRTXPL] Bits */
+#define UCIRTXPL_OFS                                       ( 2)                  /* UCIRTXPL Offset */
+#define UCIRTXPL_M                                         (0x00fc)              /* Transmit pulse length */
+/* UCA0IRCTL[UCIRRXFE] Bits */
+#define UCIRRXFE_OFS                                       ( 8)                  /* UCIRRXFE Offset */
+#define UCIRRXFE                                           (0x0100)              /* IrDA receive filter enabled */
+/* UCA0IRCTL[UCIRRXPL] Bits */
+#define UCIRRXPL_OFS                                       ( 9)                  /* UCIRRXPL Offset */
+#define UCIRRXPL                                           (0x0200)              /* IrDA receive input UCAxRXD polarity */
+/* UCA0IRCTL[UCIRRXFL] Bits */
+#define UCIRRXFL_OFS                                       (10)                  /* UCIRRXFL Offset */
+#define UCIRRXFL_M                                         (0x3c00)              /* Receive filter length */
+/* UCA0IE[UCRXIE] Bits */
+#define UCRXIE_OFS                                         ( 0)                  /* UCRXIE Offset */
+#define UCRXIE                                             (0x0001)              /* Receive interrupt enable */
+/* UCA0IE[UCTXIE] Bits */
+#define UCTXIE_OFS                                         ( 1)                  /* UCTXIE Offset */
+#define UCTXIE                                             (0x0002)              /* Transmit interrupt enable */
+/* UCA0IE[UCSTTIE] Bits */
+#define UCSTTIE_OFS                                        ( 2)                  /* UCSTTIE Offset */
+#define UCSTTIE                                            (0x0004)              /* Start bit interrupt enable */
+/* UCA0IE[UCTXCPTIE] Bits */
+#define UCTXCPTIE_OFS                                      ( 3)                  /* UCTXCPTIE Offset */
+#define UCTXCPTIE                                          (0x0008)              /* Transmit complete interrupt enable */
+/* UCA0IE_SPI[UCRXIE] Bits */
+//#define UCRXIE_OFS                                         ( 0)                  /* UCRXIE Offset */
+//#define UCRXIE                                             (0x0001)              /* Receive interrupt enable */
+/* UCA0IE_SPI[UCTXIE] Bits */
+//#define UCTXIE_OFS                                         ( 1)                  /* UCTXIE Offset */
+//#define UCTXIE                                             (0x0002)              /* Transmit interrupt enable */
+/* UCA0IFG[UCRXIFG] Bits */
+#define UCRXIFG_OFS                                        ( 0)                  /* UCRXIFG Offset */
+#define UCRXIFG                                            (0x0001)              /* Receive interrupt flag */
+/* UCA0IFG[UCTXIFG] Bits */
+#define UCTXIFG_OFS                                        ( 1)                  /* UCTXIFG Offset */
+#define UCTXIFG                                            (0x0002)              /* Transmit interrupt flag */
+/* UCA0IFG[UCSTTIFG] Bits */
+#define UCSTTIFG_OFS                                       ( 2)                  /* UCSTTIFG Offset */
+#define UCSTTIFG                                           (0x0004)              /* Start bit interrupt flag */
+/* UCA0IFG[UCTXCPTIFG] Bits */
+#define UCTXCPTIFG_OFS                                     ( 3)                  /* UCTXCPTIFG Offset */
+#define UCTXCPTIFG                                         (0x0008)              /* Transmit ready interrupt enable */
+/* UCA0IFG_SPI[UCRXIFG] Bits */
+//#define UCRXIFG_OFS                                        ( 0)                  /* UCRXIFG Offset */
+//#define UCRXIFG                                            (0x0001)              /* Receive interrupt flag */
+/* UCA0IFG_SPI[UCTXIFG] Bits */
+//#define UCTXIFG_OFS                                        ( 1)                  /* UCTXIFG Offset */
+//#define UCTXIFG                                            (0x0002)              /* Transmit interrupt flag */
+
+
+//*****************************************************************************
+// EUSCI_A1 Bits
+//*****************************************************************************
+/* UCA1CTLW0[UCSWRST] Bits */
+//#define UCSWRST_OFS                                        ( 0)                  /* UCSWRST Offset */
+//#define UCSWRST                                            (0x0001)              /* Software reset enable */
+/* UCA1CTLW0[UCTXBRK] Bits */
+//#define UCTXBRK_OFS                                        ( 1)                  /* UCTXBRK Offset */
+//#define UCTXBRK                                            (0x0002)              /* Transmit break */
+/* UCA1CTLW0[UCTXADDR] Bits */
+//#define UCTXADDR_OFS                                       ( 2)                  /* UCTXADDR Offset */
+//#define UCTXADDR                                           (0x0004)              /* Transmit address */
+/* UCA1CTLW0[UCDORM] Bits */
+//#define UCDORM_OFS                                         ( 3)                  /* UCDORM Offset */
+//#define UCDORM                                             (0x0008)              /* Dormant */
+/* UCA1CTLW0[UCBRKIE] Bits */
+//#define UCBRKIE_OFS                                        ( 4)                  /* UCBRKIE Offset */
+//#define UCBRKIE                                            (0x0010)              /* Receive break character interrupt enable */
+/* UCA1CTLW0[UCRXEIE] Bits */
+//#define UCRXEIE_OFS                                        ( 5)                  /* UCRXEIE Offset */
+//#define UCRXEIE                                            (0x0020)              /* Receive erroneous-character interrupt enable */
+/* UCA1CTLW0[UCSSEL] Bits */
+//#define UCSSEL_OFS                                         ( 6)                  /* UCSSEL Offset */
+//#define UCSSEL_M                                           (0x00c0)              /* eUSCI_A clock source select */
+//#define UCSSEL0                                            (0x0040)              /* eUSCI_A clock source select */
+//#define UCSSEL1                                            (0x0080)              /* eUSCI_A clock source select */
+//#define UCSSEL_0                                           (0x0000)              /* UCLK */
+//#define UCSSEL_1                                           (0x0040)              /* ACLK */
+//#define UCSSEL_2                                           (0x0080)              /* SMCLK */
+//#define UCSSEL__UCLK                                       (0x0000)              /* UCLK */
+//#define UCSSEL__ACLK                                       (0x0040)              /* ACLK */
+//#define UCSSEL__SMCLK                                      (0x0080)              /* SMCLK */
+/* UCA1CTLW0[UCSYNC] Bits */
+//#define UCSYNC_OFS                                         ( 8)                  /* UCSYNC Offset */
+//#define UCSYNC                                             (0x0100)              /* Synchronous mode enable */
+/* UCA1CTLW0[UCMODE] Bits */
+//#define UCMODE_OFS                                         ( 9)                  /* UCMODE Offset */
+//#define UCMODE_M                                           (0x0600)              /* eUSCI_A mode */
+//#define UCMODE0                                            (0x0200)              /* eUSCI_A mode */
+//#define UCMODE1                                            (0x0400)              /* eUSCI_A mode */
+//#define UCMODE_0                                           (0x0000)              /* UART mode */
+//#define UCMODE_1                                           (0x0200)              /* Idle-line multiprocessor mode */
+//#define UCMODE_2                                           (0x0400)              /* Address-bit multiprocessor mode */
+//#define UCMODE_3                                           (0x0600)              /* UART mode with automatic baud-rate detection */
+/* UCA1CTLW0[UCSPB] Bits */
+//#define UCSPB_OFS                                          (11)                  /* UCSPB Offset */
+//#define UCSPB                                              (0x0800)              /* Stop bit select */
+/* UCA1CTLW0[UC7BIT] Bits */
+//#define UC7BIT_OFS                                         (12)                  /* UC7BIT Offset */
+//#define UC7BIT                                             (0x1000)              /* Character length */
+/* UCA1CTLW0[UCMSB] Bits */
+//#define UCMSB_OFS                                          (13)                  /* UCMSB Offset */
+//#define UCMSB                                              (0x2000)              /* MSB first select */
+/* UCA1CTLW0[UCPAR] Bits */
+//#define UCPAR_OFS                                          (14)                  /* UCPAR Offset */
+//#define UCPAR                                              (0x4000)              /* Parity select */
+/* UCA1CTLW0[UCPEN] Bits */
+//#define UCPEN_OFS                                          (15)                  /* UCPEN Offset */
+//#define UCPEN                                              (0x8000)              /* Parity enable */
+/* UCA1CTLW0_SPI[UCSWRST] Bits */
+//#define UCSWRST_OFS                                        ( 0)                  /* UCSWRST Offset */
+//#define UCSWRST                                            (0x0001)              /* Software reset enable */
+/* UCA1CTLW0_SPI[UCSTEM] Bits */
+//#define UCSTEM_OFS                                         ( 1)                  /* UCSTEM Offset */
+//#define UCSTEM                                             (0x0002)              /* STE mode select in master mode. */
+/* UCA1CTLW0_SPI[UCSSEL] Bits */
+//#define UCSSEL_OFS                                         ( 6)                  /* UCSSEL Offset */
+//#define UCSSEL_M                                           (0x00c0)              /* eUSCI_A clock source select */
+//#define UCSSEL0                                            (0x0040)              /* eUSCI_A clock source select */
+//#define UCSSEL1                                            (0x0080)              /* eUSCI_A clock source select */
+//#define UCSSEL_1                                           (0x0040)              /* ACLK */
+//#define UCSSEL_2                                           (0x0080)              /* SMCLK */
+//#define UCSSEL_0                                           (0x0000)              /* Reserved */
+//#define UCSSEL__ACLK                                       (0x0040)              /* ACLK */
+//#define UCSSEL__SMCLK                                      (0x0080)              /* SMCLK */
+/* UCA1CTLW0_SPI[UCSYNC] Bits */
+//#define UCSYNC_OFS                                         ( 8)                  /* UCSYNC Offset */
+//#define UCSYNC                                             (0x0100)              /* Synchronous mode enable */
+/* UCA1CTLW0_SPI[UCMODE] Bits */
+//#define UCMODE_OFS                                         ( 9)                  /* UCMODE Offset */
+//#define UCMODE_M                                           (0x0600)              /* eUSCI mode */
+//#define UCMODE0                                            (0x0200)              /* eUSCI mode */
+//#define UCMODE1                                            (0x0400)              /* eUSCI mode */
+//#define UCMODE_0                                           (0x0000)              /* 3-pin SPI */
+//#define UCMODE_1                                           (0x0200)              /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */
+//#define UCMODE_2                                           (0x0400)              /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */
+/* UCA1CTLW0_SPI[UCMST] Bits */
+//#define UCMST_OFS                                          (11)                  /* UCMST Offset */
+//#define UCMST                                              (0x0800)              /* Master mode select */
+/* UCA1CTLW0_SPI[UC7BIT] Bits */
+//#define UC7BIT_OFS                                         (12)                  /* UC7BIT Offset */
+//#define UC7BIT                                             (0x1000)              /* Character length */
+/* UCA1CTLW0_SPI[UCMSB] Bits */
+//#define UCMSB_OFS                                          (13)                  /* UCMSB Offset */
+//#define UCMSB                                              (0x2000)              /* MSB first select */
+/* UCA1CTLW0_SPI[UCCKPL] Bits */
+//#define UCCKPL_OFS                                         (14)                  /* UCCKPL Offset */
+//#define UCCKPL                                             (0x4000)              /* Clock polarity select */
+/* UCA1CTLW0_SPI[UCCKPH] Bits */
+//#define UCCKPH_OFS                                         (15)                  /* UCCKPH Offset */
+//#define UCCKPH                                             (0x8000)              /* Clock phase select */
+/* UCA1CTLW1[UCGLIT] Bits */
+//#define UCGLIT_OFS                                         ( 0)                  /* UCGLIT Offset */
+//#define UCGLIT_M                                           (0x0003)              /* Deglitch time */
+//#define UCGLIT0                                            (0x0001)              /* Deglitch time */
+//#define UCGLIT1                                            (0x0002)              /* Deglitch time */
+//#define UCGLIT_0                                           (0x0000)              /* Approximately 2 ns (equivalent of 1 delay element) */
+//#define UCGLIT_1                                           (0x0001)              /* Approximately 50 ns */
+//#define UCGLIT_2                                           (0x0002)              /* Approximately 100 ns */
+//#define UCGLIT_3                                           (0x0003)              /* Approximately 200 ns */
+/* UCA1MCTLW[UCOS16] Bits */
+//#define UCOS16_OFS                                         ( 0)                  /* UCOS16 Offset */
+//#define UCOS16                                             (0x0001)              /* Oversampling mode enabled */
+/* UCA1MCTLW[UCBRF] Bits */
+//#define UCBRF_OFS                                          ( 4)                  /* UCBRF Offset */
+//#define UCBRF_M                                            (0x00f0)              /* First modulation stage select */
+/* UCA1MCTLW[UCBRS] Bits */
+//#define UCBRS_OFS                                          ( 8)                  /* UCBRS Offset */
+//#define UCBRS_M                                            (0xff00)              /* Second modulation stage select */
+/* UCA1STATW[UCBUSY] Bits */
+//#define UCBUSY_OFS                                         ( 0)                  /* UCBUSY Offset */
+//#define UCBUSY                                             (0x0001)              /* eUSCI_A busy */
+/* UCA1STATW[UCADDR_UCIDLE] Bits */
+//#define UCADDR_UCIDLE_OFS                                  ( 1)                  /* UCADDR_UCIDLE Offset */
+//#define UCADDR_UCIDLE                                      (0x0002)              /* Address received / Idle line detected */
+/* UCA1STATW[UCRXERR] Bits */
+//#define UCRXERR_OFS                                        ( 2)                  /* UCRXERR Offset */
+//#define UCRXERR                                            (0x0004)              /* Receive error flag */
+/* UCA1STATW[UCBRK] Bits */
+//#define UCBRK_OFS                                          ( 3)                  /* UCBRK Offset */
+//#define UCBRK                                              (0x0008)              /* Break detect flag */
+/* UCA1STATW[UCPE] Bits */
+//#define UCPE_OFS                                           ( 4)                  /* UCPE Offset */
+//#define UCPE                                               (0x0010)              /*  */
+/* UCA1STATW[UCOE] Bits */
+//#define UCOE_OFS                                           ( 5)                  /* UCOE Offset */
+//#define UCOE                                               (0x0020)              /* Overrun error flag */
+/* UCA1STATW[UCFE] Bits */
+//#define UCFE_OFS                                           ( 6)                  /* UCFE Offset */
+//#define UCFE                                               (0x0040)              /* Framing error flag */
+/* UCA1STATW[UCLISTEN] Bits */
+//#define UCLISTEN_OFS                                       ( 7)                  /* UCLISTEN Offset */
+//#define UCLISTEN                                           (0x0080)              /* Listen enable */
+/* UCA1STATW_SPI[UCBUSY] Bits */
+//#define UCBUSY_OFS                                         ( 0)                  /* UCBUSY Offset */
+//#define UCBUSY                                             (0x0001)              /* eUSCI_A busy */
+/* UCA1STATW_SPI[UCOE] Bits */
+//#define UCOE_OFS                                           ( 5)                  /* UCOE Offset */
+//#define UCOE                                               (0x0020)              /* Overrun error flag */
+/* UCA1STATW_SPI[UCFE] Bits */
+//#define UCFE_OFS                                           ( 6)                  /* UCFE Offset */
+//#define UCFE                                               (0x0040)              /* Framing error flag */
+/* UCA1STATW_SPI[UCLISTEN] Bits */
+//#define UCLISTEN_OFS                                       ( 7)                  /* UCLISTEN Offset */
+//#define UCLISTEN                                           (0x0080)              /* Listen enable */
+/* UCA1RXBUF[UCRXBUF] Bits */
+//#define UCRXBUF_OFS                                        ( 0)                  /* UCRXBUF Offset */
+//#define UCRXBUF_M                                          (0x00ff)              /* Receive data buffer */
+/* UCA1RXBUF_SPI[UCRXBUF] Bits */
+//#define UCRXBUF_OFS                                        ( 0)                  /* UCRXBUF Offset */
+//#define UCRXBUF_M                                          (0x00ff)              /* Receive data buffer */
+/* UCA1TXBUF[UCTXBUF] Bits */
+//#define UCTXBUF_OFS                                        ( 0)                  /* UCTXBUF Offset */
+//#define UCTXBUF_M                                          (0x00ff)              /* Transmit data buffer */
+/* UCA1TXBUF_SPI[UCTXBUF] Bits */
+//#define UCTXBUF_OFS                                        ( 0)                  /* UCTXBUF Offset */
+//#define UCTXBUF_M                                          (0x00ff)              /* Transmit data buffer */
+/* UCA1ABCTL[UCABDEN] Bits */
+//#define UCABDEN_OFS                                        ( 0)                  /* UCABDEN Offset */
+//#define UCABDEN                                            (0x0001)              /* Automatic baud-rate detect enable */
+/* UCA1ABCTL[UCBTOE] Bits */
+//#define UCBTOE_OFS                                         ( 2)                  /* UCBTOE Offset */
+//#define UCBTOE                                             (0x0004)              /* Break time out error */
+/* UCA1ABCTL[UCSTOE] Bits */
+//#define UCSTOE_OFS                                         ( 3)                  /* UCSTOE Offset */
+//#define UCSTOE                                             (0x0008)              /* Synch field time out error */
+/* UCA1ABCTL[UCDELIM] Bits */
+//#define UCDELIM_OFS                                        ( 4)                  /* UCDELIM Offset */
+//#define UCDELIM_M                                          (0x0030)              /* Break/synch delimiter length */
+//#define UCDELIM0                                           (0x0010)              /* Break/synch delimiter length */
+//#define UCDELIM1                                           (0x0020)              /* Break/synch delimiter length */
+//#define UCDELIM_0                                          (0x0000)              /* 1 bit time */
+//#define UCDELIM_1                                          (0x0010)              /* 2 bit times */
+//#define UCDELIM_2                                          (0x0020)              /* 3 bit times */
+//#define UCDELIM_3                                          (0x0030)              /* 4 bit times */
+/* UCA1IRCTL[UCIREN] Bits */
+//#define UCIREN_OFS                                         ( 0)                  /* UCIREN Offset */
+//#define UCIREN                                             (0x0001)              /* IrDA encoder/decoder enable */
+/* UCA1IRCTL[UCIRTXCLK] Bits */
+//#define UCIRTXCLK_OFS                                      ( 1)                  /* UCIRTXCLK Offset */
+//#define UCIRTXCLK                                          (0x0002)              /* IrDA transmit pulse clock select */
+/* UCA1IRCTL[UCIRTXPL] Bits */
+//#define UCIRTXPL_OFS                                       ( 2)                  /* UCIRTXPL Offset */
+//#define UCIRTXPL_M                                         (0x00fc)              /* Transmit pulse length */
+/* UCA1IRCTL[UCIRRXFE] Bits */
+//#define UCIRRXFE_OFS                                       ( 8)                  /* UCIRRXFE Offset */
+//#define UCIRRXFE                                           (0x0100)              /* IrDA receive filter enabled */
+/* UCA1IRCTL[UCIRRXPL] Bits */
+//#define UCIRRXPL_OFS                                       ( 9)                  /* UCIRRXPL Offset */
+//#define UCIRRXPL                                           (0x0200)              /* IrDA receive input UCAxRXD polarity */
+/* UCA1IRCTL[UCIRRXFL] Bits */
+//#define UCIRRXFL_OFS                                       (10)                  /* UCIRRXFL Offset */
+//#define UCIRRXFL_M                                         (0x3c00)              /* Receive filter length */
+/* UCA1IE[UCRXIE] Bits */
+//#define UCRXIE_OFS                                         ( 0)                  /* UCRXIE Offset */
+//#define UCRXIE                                             (0x0001)              /* Receive interrupt enable */
+/* UCA1IE[UCTXIE] Bits */
+//#define UCTXIE_OFS                                         ( 1)                  /* UCTXIE Offset */
+//#define UCTXIE                                             (0x0002)              /* Transmit interrupt enable */
+/* UCA1IE[UCSTTIE] Bits */
+//#define UCSTTIE_OFS                                        ( 2)                  /* UCSTTIE Offset */
+//#define UCSTTIE                                            (0x0004)              /* Start bit interrupt enable */
+/* UCA1IE[UCTXCPTIE] Bits */
+//#define UCTXCPTIE_OFS                                      ( 3)                  /* UCTXCPTIE Offset */
+//#define UCTXCPTIE                                          (0x0008)              /* Transmit complete interrupt enable */
+/* UCA1IE_SPI[UCRXIE] Bits */
+//#define UCRXIE_OFS                                         ( 0)                  /* UCRXIE Offset */
+//#define UCRXIE                                             (0x0001)              /* Receive interrupt enable */
+/* UCA1IE_SPI[UCTXIE] Bits */
+//#define UCTXIE_OFS                                         ( 1)                  /* UCTXIE Offset */
+//#define UCTXIE                                             (0x0002)              /* Transmit interrupt enable */
+/* UCA1IFG[UCRXIFG] Bits */
+//#define UCRXIFG_OFS                                        ( 0)                  /* UCRXIFG Offset */
+//#define UCRXIFG                                            (0x0001)              /* Receive interrupt flag */
+/* UCA1IFG[UCTXIFG] Bits */
+//#define UCTXIFG_OFS                                        ( 1)                  /* UCTXIFG Offset */
+//#define UCTXIFG                                            (0x0002)              /* Transmit interrupt flag */
+/* UCA1IFG[UCSTTIFG] Bits */
+//#define UCSTTIFG_OFS                                       ( 2)                  /* UCSTTIFG Offset */
+//#define UCSTTIFG                                           (0x0004)              /* Start bit interrupt flag */
+/* UCA1IFG[UCTXCPTIFG] Bits */
+//#define UCTXCPTIFG_OFS                                     ( 3)                  /* UCTXCPTIFG Offset */
+//#define UCTXCPTIFG                                         (0x0008)              /* Transmit ready interrupt enable */
+/* UCA1IFG_SPI[UCRXIFG] Bits */
+//#define UCRXIFG_OFS                                        ( 0)                  /* UCRXIFG Offset */
+//#define UCRXIFG                                            (0x0001)              /* Receive interrupt flag */
+/* UCA1IFG_SPI[UCTXIFG] Bits */
+//#define UCTXIFG_OFS                                        ( 1)                  /* UCTXIFG Offset */
+//#define UCTXIFG                                            (0x0002)              /* Transmit interrupt flag */
+
+
+//*****************************************************************************
+// EUSCI_A2 Bits
+//*****************************************************************************
+/* UCA2CTLW0[UCSWRST] Bits */
+//#define UCSWRST_OFS                                        ( 0)                  /* UCSWRST Offset */
+//#define UCSWRST                                            (0x0001)              /* Software reset enable */
+/* UCA2CTLW0[UCTXBRK] Bits */
+//#define UCTXBRK_OFS                                        ( 1)                  /* UCTXBRK Offset */
+//#define UCTXBRK                                            (0x0002)              /* Transmit break */
+/* UCA2CTLW0[UCTXADDR] Bits */
+//#define UCTXADDR_OFS                                       ( 2)                  /* UCTXADDR Offset */
+//#define UCTXADDR                                           (0x0004)              /* Transmit address */
+/* UCA2CTLW0[UCDORM] Bits */
+//#define UCDORM_OFS                                         ( 3)                  /* UCDORM Offset */
+//#define UCDORM                                             (0x0008)              /* Dormant */
+/* UCA2CTLW0[UCBRKIE] Bits */
+//#define UCBRKIE_OFS                                        ( 4)                  /* UCBRKIE Offset */
+//#define UCBRKIE                                            (0x0010)              /* Receive break character interrupt enable */
+/* UCA2CTLW0[UCRXEIE] Bits */
+//#define UCRXEIE_OFS                                        ( 5)                  /* UCRXEIE Offset */
+//#define UCRXEIE                                            (0x0020)              /* Receive erroneous-character interrupt enable */
+/* UCA2CTLW0[UCSSEL] Bits */
+//#define UCSSEL_OFS                                         ( 6)                  /* UCSSEL Offset */
+//#define UCSSEL_M                                           (0x00c0)              /* eUSCI_A clock source select */
+//#define UCSSEL0                                            (0x0040)              /* eUSCI_A clock source select */
+//#define UCSSEL1                                            (0x0080)              /* eUSCI_A clock source select */
+//#define UCSSEL_0                                           (0x0000)              /* UCLK */
+//#define UCSSEL_1                                           (0x0040)              /* ACLK */
+//#define UCSSEL_2                                           (0x0080)              /* SMCLK */
+//#define UCSSEL__UCLK                                       (0x0000)              /* UCLK */
+//#define UCSSEL__ACLK                                       (0x0040)              /* ACLK */
+//#define UCSSEL__SMCLK                                      (0x0080)              /* SMCLK */
+/* UCA2CTLW0[UCSYNC] Bits */
+//#define UCSYNC_OFS                                         ( 8)                  /* UCSYNC Offset */
+//#define UCSYNC                                             (0x0100)              /* Synchronous mode enable */
+/* UCA2CTLW0[UCMODE] Bits */
+//#define UCMODE_OFS                                         ( 9)                  /* UCMODE Offset */
+//#define UCMODE_M                                           (0x0600)              /* eUSCI_A mode */
+//#define UCMODE0                                            (0x0200)              /* eUSCI_A mode */
+//#define UCMODE1                                            (0x0400)              /* eUSCI_A mode */
+//#define UCMODE_0                                           (0x0000)              /* UART mode */
+//#define UCMODE_1                                           (0x0200)              /* Idle-line multiprocessor mode */
+//#define UCMODE_2                                           (0x0400)              /* Address-bit multiprocessor mode */
+//#define UCMODE_3                                           (0x0600)              /* UART mode with automatic baud-rate detection */
+/* UCA2CTLW0[UCSPB] Bits */
+//#define UCSPB_OFS                                          (11)                  /* UCSPB Offset */
+//#define UCSPB                                              (0x0800)              /* Stop bit select */
+/* UCA2CTLW0[UC7BIT] Bits */
+//#define UC7BIT_OFS                                         (12)                  /* UC7BIT Offset */
+//#define UC7BIT                                             (0x1000)              /* Character length */
+/* UCA2CTLW0[UCMSB] Bits */
+//#define UCMSB_OFS                                          (13)                  /* UCMSB Offset */
+//#define UCMSB                                              (0x2000)              /* MSB first select */
+/* UCA2CTLW0[UCPAR] Bits */
+//#define UCPAR_OFS                                          (14)                  /* UCPAR Offset */
+//#define UCPAR                                              (0x4000)              /* Parity select */
+/* UCA2CTLW0[UCPEN] Bits */
+//#define UCPEN_OFS                                          (15)                  /* UCPEN Offset */
+//#define UCPEN                                              (0x8000)              /* Parity enable */
+/* UCA2CTLW0_SPI[UCSWRST] Bits */
+//#define UCSWRST_OFS                                        ( 0)                  /* UCSWRST Offset */
+//#define UCSWRST                                            (0x0001)              /* Software reset enable */
+/* UCA2CTLW0_SPI[UCSTEM] Bits */
+//#define UCSTEM_OFS                                         ( 1)                  /* UCSTEM Offset */
+//#define UCSTEM                                             (0x0002)              /* STE mode select in master mode. */
+/* UCA2CTLW0_SPI[UCSSEL] Bits */
+//#define UCSSEL_OFS                                         ( 6)                  /* UCSSEL Offset */
+//#define UCSSEL_M                                           (0x00c0)              /* eUSCI_A clock source select */
+//#define UCSSEL0                                            (0x0040)              /* eUSCI_A clock source select */
+//#define UCSSEL1                                            (0x0080)              /* eUSCI_A clock source select */
+//#define UCSSEL_1                                           (0x0040)              /* ACLK */
+//#define UCSSEL_2                                           (0x0080)              /* SMCLK */
+//#define UCSSEL_0                                           (0x0000)              /* Reserved */
+//#define UCSSEL__ACLK                                       (0x0040)              /* ACLK */
+//#define UCSSEL__SMCLK                                      (0x0080)              /* SMCLK */
+/* UCA2CTLW0_SPI[UCSYNC] Bits */
+//#define UCSYNC_OFS                                         ( 8)                  /* UCSYNC Offset */
+//#define UCSYNC                                             (0x0100)              /* Synchronous mode enable */
+/* UCA2CTLW0_SPI[UCMODE] Bits */
+//#define UCMODE_OFS                                         ( 9)                  /* UCMODE Offset */
+//#define UCMODE_M                                           (0x0600)              /* eUSCI mode */
+//#define UCMODE0                                            (0x0200)              /* eUSCI mode */
+//#define UCMODE1                                            (0x0400)              /* eUSCI mode */
+//#define UCMODE_0                                           (0x0000)              /* 3-pin SPI */
+//#define UCMODE_1                                           (0x0200)              /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */
+//#define UCMODE_2                                           (0x0400)              /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */
+/* UCA2CTLW0_SPI[UCMST] Bits */
+//#define UCMST_OFS                                          (11)                  /* UCMST Offset */
+//#define UCMST                                              (0x0800)              /* Master mode select */
+/* UCA2CTLW0_SPI[UC7BIT] Bits */
+//#define UC7BIT_OFS                                         (12)                  /* UC7BIT Offset */
+//#define UC7BIT                                             (0x1000)              /* Character length */
+/* UCA2CTLW0_SPI[UCMSB] Bits */
+//#define UCMSB_OFS                                          (13)                  /* UCMSB Offset */
+//#define UCMSB                                              (0x2000)              /* MSB first select */
+/* UCA2CTLW0_SPI[UCCKPL] Bits */
+//#define UCCKPL_OFS                                         (14)                  /* UCCKPL Offset */
+//#define UCCKPL                                             (0x4000)              /* Clock polarity select */
+/* UCA2CTLW0_SPI[UCCKPH] Bits */
+//#define UCCKPH_OFS                                         (15)                  /* UCCKPH Offset */
+//#define UCCKPH                                             (0x8000)              /* Clock phase select */
+/* UCA2CTLW1[UCGLIT] Bits */
+//#define UCGLIT_OFS                                         ( 0)                  /* UCGLIT Offset */
+//#define UCGLIT_M                                           (0x0003)              /* Deglitch time */
+//#define UCGLIT0                                            (0x0001)              /* Deglitch time */
+//#define UCGLIT1                                            (0x0002)              /* Deglitch time */
+//#define UCGLIT_0                                           (0x0000)              /* Approximately 2 ns (equivalent of 1 delay element) */
+//#define UCGLIT_1                                           (0x0001)              /* Approximately 50 ns */
+//#define UCGLIT_2                                           (0x0002)              /* Approximately 100 ns */
+//#define UCGLIT_3                                           (0x0003)              /* Approximately 200 ns */
+/* UCA2MCTLW[UCOS16] Bits */
+//#define UCOS16_OFS                                         ( 0)                  /* UCOS16 Offset */
+//#define UCOS16                                             (0x0001)              /* Oversampling mode enabled */
+/* UCA2MCTLW[UCBRF] Bits */
+//#define UCBRF_OFS                                          ( 4)                  /* UCBRF Offset */
+//#define UCBRF_M                                            (0x00f0)              /* First modulation stage select */
+/* UCA2MCTLW[UCBRS] Bits */
+//#define UCBRS_OFS                                          ( 8)                  /* UCBRS Offset */
+//#define UCBRS_M                                            (0xff00)              /* Second modulation stage select */
+/* UCA2STATW[UCBUSY] Bits */
+//#define UCBUSY_OFS                                         ( 0)                  /* UCBUSY Offset */
+//#define UCBUSY                                             (0x0001)              /* eUSCI_A busy */
+/* UCA2STATW[UCADDR_UCIDLE] Bits */
+//#define UCADDR_UCIDLE_OFS                                  ( 1)                  /* UCADDR_UCIDLE Offset */
+//#define UCADDR_UCIDLE                                      (0x0002)              /* Address received / Idle line detected */
+/* UCA2STATW[UCRXERR] Bits */
+//#define UCRXERR_OFS                                        ( 2)                  /* UCRXERR Offset */
+//#define UCRXERR                                            (0x0004)              /* Receive error flag */
+/* UCA2STATW[UCBRK] Bits */
+//#define UCBRK_OFS                                          ( 3)                  /* UCBRK Offset */
+//#define UCBRK                                              (0x0008)              /* Break detect flag */
+/* UCA2STATW[UCPE] Bits */
+//#define UCPE_OFS                                           ( 4)                  /* UCPE Offset */
+//#define UCPE                                               (0x0010)              /*  */
+/* UCA2STATW[UCOE] Bits */
+//#define UCOE_OFS                                           ( 5)                  /* UCOE Offset */
+//#define UCOE                                               (0x0020)              /* Overrun error flag */
+/* UCA2STATW[UCFE] Bits */
+//#define UCFE_OFS                                           ( 6)                  /* UCFE Offset */
+//#define UCFE                                               (0x0040)              /* Framing error flag */
+/* UCA2STATW[UCLISTEN] Bits */
+//#define UCLISTEN_OFS                                       ( 7)                  /* UCLISTEN Offset */
+//#define UCLISTEN                                           (0x0080)              /* Listen enable */
+/* UCA2STATW_SPI[UCBUSY] Bits */
+//#define UCBUSY_OFS                                         ( 0)                  /* UCBUSY Offset */
+//#define UCBUSY                                             (0x0001)              /* eUSCI_A busy */
+/* UCA2STATW_SPI[UCOE] Bits */
+//#define UCOE_OFS                                           ( 5)                  /* UCOE Offset */
+//#define UCOE                                               (0x0020)              /* Overrun error flag */
+/* UCA2STATW_SPI[UCFE] Bits */
+//#define UCFE_OFS                                           ( 6)                  /* UCFE Offset */
+//#define UCFE                                               (0x0040)              /* Framing error flag */
+/* UCA2STATW_SPI[UCLISTEN] Bits */
+//#define UCLISTEN_OFS                                       ( 7)                  /* UCLISTEN Offset */
+//#define UCLISTEN                                           (0x0080)              /* Listen enable */
+/* UCA2RXBUF[UCRXBUF] Bits */
+//#define UCRXBUF_OFS                                        ( 0)                  /* UCRXBUF Offset */
+//#define UCRXBUF_M                                          (0x00ff)              /* Receive data buffer */
+/* UCA2RXBUF_SPI[UCRXBUF] Bits */
+//#define UCRXBUF_OFS                                        ( 0)                  /* UCRXBUF Offset */
+//#define UCRXBUF_M                                          (0x00ff)              /* Receive data buffer */
+/* UCA2TXBUF[UCTXBUF] Bits */
+//#define UCTXBUF_OFS                                        ( 0)                  /* UCTXBUF Offset */
+//#define UCTXBUF_M                                          (0x00ff)              /* Transmit data buffer */
+/* UCA2TXBUF_SPI[UCTXBUF] Bits */
+//#define UCTXBUF_OFS                                        ( 0)                  /* UCTXBUF Offset */
+//#define UCTXBUF_M                                          (0x00ff)              /* Transmit data buffer */
+/* UCA2ABCTL[UCABDEN] Bits */
+//#define UCABDEN_OFS                                        ( 0)                  /* UCABDEN Offset */
+//#define UCABDEN                                            (0x0001)              /* Automatic baud-rate detect enable */
+/* UCA2ABCTL[UCBTOE] Bits */
+//#define UCBTOE_OFS                                         ( 2)                  /* UCBTOE Offset */
+//#define UCBTOE                                             (0x0004)              /* Break time out error */
+/* UCA2ABCTL[UCSTOE] Bits */
+//#define UCSTOE_OFS                                         ( 3)                  /* UCSTOE Offset */
+//#define UCSTOE                                             (0x0008)              /* Synch field time out error */
+/* UCA2ABCTL[UCDELIM] Bits */
+//#define UCDELIM_OFS                                        ( 4)                  /* UCDELIM Offset */
+//#define UCDELIM_M                                          (0x0030)              /* Break/synch delimiter length */
+//#define UCDELIM0                                           (0x0010)              /* Break/synch delimiter length */
+//#define UCDELIM1                                           (0x0020)              /* Break/synch delimiter length */
+//#define UCDELIM_0                                          (0x0000)              /* 1 bit time */
+//#define UCDELIM_1                                          (0x0010)              /* 2 bit times */
+//#define UCDELIM_2                                          (0x0020)              /* 3 bit times */
+//#define UCDELIM_3                                          (0x0030)              /* 4 bit times */
+/* UCA2IRCTL[UCIREN] Bits */
+//#define UCIREN_OFS                                         ( 0)                  /* UCIREN Offset */
+//#define UCIREN                                             (0x0001)              /* IrDA encoder/decoder enable */
+/* UCA2IRCTL[UCIRTXCLK] Bits */
+//#define UCIRTXCLK_OFS                                      ( 1)                  /* UCIRTXCLK Offset */
+//#define UCIRTXCLK                                          (0x0002)              /* IrDA transmit pulse clock select */
+/* UCA2IRCTL[UCIRTXPL] Bits */
+//#define UCIRTXPL_OFS                                       ( 2)                  /* UCIRTXPL Offset */
+//#define UCIRTXPL_M                                         (0x00fc)              /* Transmit pulse length */
+/* UCA2IRCTL[UCIRRXFE] Bits */
+//#define UCIRRXFE_OFS                                       ( 8)                  /* UCIRRXFE Offset */
+//#define UCIRRXFE                                           (0x0100)              /* IrDA receive filter enabled */
+/* UCA2IRCTL[UCIRRXPL] Bits */
+//#define UCIRRXPL_OFS                                       ( 9)                  /* UCIRRXPL Offset */
+//#define UCIRRXPL                                           (0x0200)              /* IrDA receive input UCAxRXD polarity */
+/* UCA2IRCTL[UCIRRXFL] Bits */
+//#define UCIRRXFL_OFS                                       (10)                  /* UCIRRXFL Offset */
+//#define UCIRRXFL_M                                         (0x3c00)              /* Receive filter length */
+/* UCA2IE[UCRXIE] Bits */
+//#define UCRXIE_OFS                                         ( 0)                  /* UCRXIE Offset */
+//#define UCRXIE                                             (0x0001)              /* Receive interrupt enable */
+/* UCA2IE[UCTXIE] Bits */
+//#define UCTXIE_OFS                                         ( 1)                  /* UCTXIE Offset */
+//#define UCTXIE                                             (0x0002)              /* Transmit interrupt enable */
+/* UCA2IE[UCSTTIE] Bits */
+//#define UCSTTIE_OFS                                        ( 2)                  /* UCSTTIE Offset */
+//#define UCSTTIE                                            (0x0004)              /* Start bit interrupt enable */
+/* UCA2IE[UCTXCPTIE] Bits */
+//#define UCTXCPTIE_OFS                                      ( 3)                  /* UCTXCPTIE Offset */
+//#define UCTXCPTIE                                          (0x0008)              /* Transmit complete interrupt enable */
+/* UCA2IE_SPI[UCRXIE] Bits */
+//#define UCRXIE_OFS                                         ( 0)                  /* UCRXIE Offset */
+//#define UCRXIE                                             (0x0001)              /* Receive interrupt enable */
+/* UCA2IE_SPI[UCTXIE] Bits */
+//#define UCTXIE_OFS                                         ( 1)                  /* UCTXIE Offset */
+//#define UCTXIE                                             (0x0002)              /* Transmit interrupt enable */
+/* UCA2IFG[UCRXIFG] Bits */
+//#define UCRXIFG_OFS                                        ( 0)                  /* UCRXIFG Offset */
+//#define UCRXIFG                                            (0x0001)              /* Receive interrupt flag */
+/* UCA2IFG[UCTXIFG] Bits */
+//#define UCTXIFG_OFS                                        ( 1)                  /* UCTXIFG Offset */
+//#define UCTXIFG                                            (0x0002)              /* Transmit interrupt flag */
+/* UCA2IFG[UCSTTIFG] Bits */
+//#define UCSTTIFG_OFS                                       ( 2)                  /* UCSTTIFG Offset */
+//#define UCSTTIFG                                           (0x0004)              /* Start bit interrupt flag */
+/* UCA2IFG[UCTXCPTIFG] Bits */
+//#define UCTXCPTIFG_OFS                                     ( 3)                  /* UCTXCPTIFG Offset */
+//#define UCTXCPTIFG                                         (0x0008)              /* Transmit ready interrupt enable */
+/* UCA2IFG_SPI[UCRXIFG] Bits */
+//#define UCRXIFG_OFS                                        ( 0)                  /* UCRXIFG Offset */
+//#define UCRXIFG                                            (0x0001)              /* Receive interrupt flag */
+/* UCA2IFG_SPI[UCTXIFG] Bits */
+//#define UCTXIFG_OFS                                        ( 1)                  /* UCTXIFG Offset */
+//#define UCTXIFG                                            (0x0002)              /* Transmit interrupt flag */
+
+
+//*****************************************************************************
+// EUSCI_A3 Bits
+//*****************************************************************************
+/* UCA3CTLW0[UCSWRST] Bits */
+//#define UCSWRST_OFS                                        ( 0)                  /* UCSWRST Offset */
+//#define UCSWRST                                            (0x0001)              /* Software reset enable */
+/* UCA3CTLW0[UCTXBRK] Bits */
+//#define UCTXBRK_OFS                                        ( 1)                  /* UCTXBRK Offset */
+//#define UCTXBRK                                            (0x0002)              /* Transmit break */
+/* UCA3CTLW0[UCTXADDR] Bits */
+//#define UCTXADDR_OFS                                       ( 2)                  /* UCTXADDR Offset */
+//#define UCTXADDR                                           (0x0004)              /* Transmit address */
+/* UCA3CTLW0[UCDORM] Bits */
+//#define UCDORM_OFS                                         ( 3)                  /* UCDORM Offset */
+//#define UCDORM                                             (0x0008)              /* Dormant */
+/* UCA3CTLW0[UCBRKIE] Bits */
+//#define UCBRKIE_OFS                                        ( 4)                  /* UCBRKIE Offset */
+//#define UCBRKIE                                            (0x0010)              /* Receive break character interrupt enable */
+/* UCA3CTLW0[UCRXEIE] Bits */
+//#define UCRXEIE_OFS                                        ( 5)                  /* UCRXEIE Offset */
+//#define UCRXEIE                                            (0x0020)              /* Receive erroneous-character interrupt enable */
+/* UCA3CTLW0[UCSSEL] Bits */
+//#define UCSSEL_OFS                                         ( 6)                  /* UCSSEL Offset */
+//#define UCSSEL_M                                           (0x00c0)              /* eUSCI_A clock source select */
+//#define UCSSEL0                                            (0x0040)              /* eUSCI_A clock source select */
+//#define UCSSEL1                                            (0x0080)              /* eUSCI_A clock source select */
+//#define UCSSEL_0                                           (0x0000)              /* UCLK */
+//#define UCSSEL_1                                           (0x0040)              /* ACLK */
+//#define UCSSEL_2                                           (0x0080)              /* SMCLK */
+//#define UCSSEL__UCLK                                       (0x0000)              /* UCLK */
+//#define UCSSEL__ACLK                                       (0x0040)              /* ACLK */
+//#define UCSSEL__SMCLK                                      (0x0080)              /* SMCLK */
+/* UCA3CTLW0[UCSYNC] Bits */
+//#define UCSYNC_OFS                                         ( 8)                  /* UCSYNC Offset */
+//#define UCSYNC                                             (0x0100)              /* Synchronous mode enable */
+/* UCA3CTLW0[UCMODE] Bits */
+//#define UCMODE_OFS                                         ( 9)                  /* UCMODE Offset */
+//#define UCMODE_M                                           (0x0600)              /* eUSCI_A mode */
+//#define UCMODE0                                            (0x0200)              /* eUSCI_A mode */
+//#define UCMODE1                                            (0x0400)              /* eUSCI_A mode */
+//#define UCMODE_0                                           (0x0000)              /* UART mode */
+//#define UCMODE_1                                           (0x0200)              /* Idle-line multiprocessor mode */
+//#define UCMODE_2                                           (0x0400)              /* Address-bit multiprocessor mode */
+//#define UCMODE_3                                           (0x0600)              /* UART mode with automatic baud-rate detection */
+/* UCA3CTLW0[UCSPB] Bits */
+//#define UCSPB_OFS                                          (11)                  /* UCSPB Offset */
+//#define UCSPB                                              (0x0800)              /* Stop bit select */
+/* UCA3CTLW0[UC7BIT] Bits */
+//#define UC7BIT_OFS                                         (12)                  /* UC7BIT Offset */
+//#define UC7BIT                                             (0x1000)              /* Character length */
+/* UCA3CTLW0[UCMSB] Bits */
+//#define UCMSB_OFS                                          (13)                  /* UCMSB Offset */
+//#define UCMSB                                              (0x2000)              /* MSB first select */
+/* UCA3CTLW0[UCPAR] Bits */
+//#define UCPAR_OFS                                          (14)                  /* UCPAR Offset */
+//#define UCPAR                                              (0x4000)              /* Parity select */
+/* UCA3CTLW0[UCPEN] Bits */
+//#define UCPEN_OFS                                          (15)                  /* UCPEN Offset */
+//#define UCPEN                                              (0x8000)              /* Parity enable */
+/* UCA3CTLW0_SPI[UCSWRST] Bits */
+//#define UCSWRST_OFS                                        ( 0)                  /* UCSWRST Offset */
+//#define UCSWRST                                            (0x0001)              /* Software reset enable */
+/* UCA3CTLW0_SPI[UCSTEM] Bits */
+//#define UCSTEM_OFS                                         ( 1)                  /* UCSTEM Offset */
+//#define UCSTEM                                             (0x0002)              /* STE mode select in master mode. */
+/* UCA3CTLW0_SPI[UCSSEL] Bits */
+//#define UCSSEL_OFS                                         ( 6)                  /* UCSSEL Offset */
+//#define UCSSEL_M                                           (0x00c0)              /* eUSCI_A clock source select */
+//#define UCSSEL0                                            (0x0040)              /* eUSCI_A clock source select */
+//#define UCSSEL1                                            (0x0080)              /* eUSCI_A clock source select */
+//#define UCSSEL_1                                           (0x0040)              /* ACLK */
+//#define UCSSEL_2                                           (0x0080)              /* SMCLK */
+//#define UCSSEL_0                                           (0x0000)              /* Reserved */
+//#define UCSSEL__ACLK                                       (0x0040)              /* ACLK */
+//#define UCSSEL__SMCLK                                      (0x0080)              /* SMCLK */
+/* UCA3CTLW0_SPI[UCSYNC] Bits */
+//#define UCSYNC_OFS                                         ( 8)                  /* UCSYNC Offset */
+//#define UCSYNC                                             (0x0100)              /* Synchronous mode enable */
+/* UCA3CTLW0_SPI[UCMODE] Bits */
+//#define UCMODE_OFS                                         ( 9)                  /* UCMODE Offset */
+//#define UCMODE_M                                           (0x0600)              /* eUSCI mode */
+//#define UCMODE0                                            (0x0200)              /* eUSCI mode */
+//#define UCMODE1                                            (0x0400)              /* eUSCI mode */
+//#define UCMODE_0                                           (0x0000)              /* 3-pin SPI */
+//#define UCMODE_1                                           (0x0200)              /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */
+//#define UCMODE_2                                           (0x0400)              /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */
+/* UCA3CTLW0_SPI[UCMST] Bits */
+//#define UCMST_OFS                                          (11)                  /* UCMST Offset */
+//#define UCMST                                              (0x0800)              /* Master mode select */
+/* UCA3CTLW0_SPI[UC7BIT] Bits */
+//#define UC7BIT_OFS                                         (12)                  /* UC7BIT Offset */
+//#define UC7BIT                                             (0x1000)              /* Character length */
+/* UCA3CTLW0_SPI[UCMSB] Bits */
+//#define UCMSB_OFS                                          (13)                  /* UCMSB Offset */
+//#define UCMSB                                              (0x2000)              /* MSB first select */
+/* UCA3CTLW0_SPI[UCCKPL] Bits */
+//#define UCCKPL_OFS                                         (14)                  /* UCCKPL Offset */
+//#define UCCKPL                                             (0x4000)              /* Clock polarity select */
+/* UCA3CTLW0_SPI[UCCKPH] Bits */
+//#define UCCKPH_OFS                                         (15)                  /* UCCKPH Offset */
+//#define UCCKPH                                             (0x8000)              /* Clock phase select */
+/* UCA3CTLW1[UCGLIT] Bits */
+//#define UCGLIT_OFS                                         ( 0)                  /* UCGLIT Offset */
+//#define UCGLIT_M                                           (0x0003)              /* Deglitch time */
+//#define UCGLIT0                                            (0x0001)              /* Deglitch time */
+//#define UCGLIT1                                            (0x0002)              /* Deglitch time */
+//#define UCGLIT_0                                           (0x0000)              /* Approximately 2 ns (equivalent of 1 delay element) */
+//#define UCGLIT_1                                           (0x0001)              /* Approximately 50 ns */
+//#define UCGLIT_2                                           (0x0002)              /* Approximately 100 ns */
+//#define UCGLIT_3                                           (0x0003)              /* Approximately 200 ns */
+/* UCA3MCTLW[UCOS16] Bits */
+//#define UCOS16_OFS                                         ( 0)                  /* UCOS16 Offset */
+//#define UCOS16                                             (0x0001)              /* Oversampling mode enabled */
+/* UCA3MCTLW[UCBRF] Bits */
+//#define UCBRF_OFS                                          ( 4)                  /* UCBRF Offset */
+//#define UCBRF_M                                            (0x00f0)              /* First modulation stage select */
+/* UCA3MCTLW[UCBRS] Bits */
+//#define UCBRS_OFS                                          ( 8)                  /* UCBRS Offset */
+//#define UCBRS_M                                            (0xff00)              /* Second modulation stage select */
+/* UCA3STATW[UCBUSY] Bits */
+//#define UCBUSY_OFS                                         ( 0)                  /* UCBUSY Offset */
+//#define UCBUSY                                             (0x0001)              /* eUSCI_A busy */
+/* UCA3STATW[UCADDR_UCIDLE] Bits */
+//#define UCADDR_UCIDLE_OFS                                  ( 1)                  /* UCADDR_UCIDLE Offset */
+//#define UCADDR_UCIDLE                                      (0x0002)              /* Address received / Idle line detected */
+/* UCA3STATW[UCRXERR] Bits */
+//#define UCRXERR_OFS                                        ( 2)                  /* UCRXERR Offset */
+//#define UCRXERR                                            (0x0004)              /* Receive error flag */
+/* UCA3STATW[UCBRK] Bits */
+//#define UCBRK_OFS                                          ( 3)                  /* UCBRK Offset */
+//#define UCBRK                                              (0x0008)              /* Break detect flag */
+/* UCA3STATW[UCPE] Bits */
+//#define UCPE_OFS                                           ( 4)                  /* UCPE Offset */
+//#define UCPE                                               (0x0010)              /*  */
+/* UCA3STATW[UCOE] Bits */
+//#define UCOE_OFS                                           ( 5)                  /* UCOE Offset */
+//#define UCOE                                               (0x0020)              /* Overrun error flag */
+/* UCA3STATW[UCFE] Bits */
+//#define UCFE_OFS                                           ( 6)                  /* UCFE Offset */
+//#define UCFE                                               (0x0040)              /* Framing error flag */
+/* UCA3STATW[UCLISTEN] Bits */
+//#define UCLISTEN_OFS                                       ( 7)                  /* UCLISTEN Offset */
+//#define UCLISTEN                                           (0x0080)              /* Listen enable */
+/* UCA3STATW_SPI[UCBUSY] Bits */
+//#define UCBUSY_OFS                                         ( 0)                  /* UCBUSY Offset */
+//#define UCBUSY                                             (0x0001)              /* eUSCI_A busy */
+/* UCA3STATW_SPI[UCOE] Bits */
+//#define UCOE_OFS                                           ( 5)                  /* UCOE Offset */
+//#define UCOE                                               (0x0020)              /* Overrun error flag */
+/* UCA3STATW_SPI[UCFE] Bits */
+//#define UCFE_OFS                                           ( 6)                  /* UCFE Offset */
+//#define UCFE                                               (0x0040)              /* Framing error flag */
+/* UCA3STATW_SPI[UCLISTEN] Bits */
+//#define UCLISTEN_OFS                                       ( 7)                  /* UCLISTEN Offset */
+//#define UCLISTEN                                           (0x0080)              /* Listen enable */
+/* UCA3RXBUF[UCRXBUF] Bits */
+//#define UCRXBUF_OFS                                        ( 0)                  /* UCRXBUF Offset */
+//#define UCRXBUF_M                                          (0x00ff)              /* Receive data buffer */
+/* UCA3RXBUF_SPI[UCRXBUF] Bits */
+//#define UCRXBUF_OFS                                        ( 0)                  /* UCRXBUF Offset */
+//#define UCRXBUF_M                                          (0x00ff)              /* Receive data buffer */
+/* UCA3TXBUF[UCTXBUF] Bits */
+//#define UCTXBUF_OFS                                        ( 0)                  /* UCTXBUF Offset */
+//#define UCTXBUF_M                                          (0x00ff)              /* Transmit data buffer */
+/* UCA3TXBUF_SPI[UCTXBUF] Bits */
+//#define UCTXBUF_OFS                                        ( 0)                  /* UCTXBUF Offset */
+//#define UCTXBUF_M                                          (0x00ff)              /* Transmit data buffer */
+/* UCA3ABCTL[UCABDEN] Bits */
+//#define UCABDEN_OFS                                        ( 0)                  /* UCABDEN Offset */
+//#define UCABDEN                                            (0x0001)              /* Automatic baud-rate detect enable */
+/* UCA3ABCTL[UCBTOE] Bits */
+//#define UCBTOE_OFS                                         ( 2)                  /* UCBTOE Offset */
+//#define UCBTOE                                             (0x0004)              /* Break time out error */
+/* UCA3ABCTL[UCSTOE] Bits */
+//#define UCSTOE_OFS                                         ( 3)                  /* UCSTOE Offset */
+//#define UCSTOE                                             (0x0008)              /* Synch field time out error */
+/* UCA3ABCTL[UCDELIM] Bits */
+//#define UCDELIM_OFS                                        ( 4)                  /* UCDELIM Offset */
+//#define UCDELIM_M                                          (0x0030)              /* Break/synch delimiter length */
+//#define UCDELIM0                                           (0x0010)              /* Break/synch delimiter length */
+//#define UCDELIM1                                           (0x0020)              /* Break/synch delimiter length */
+//#define UCDELIM_0                                          (0x0000)              /* 1 bit time */
+//#define UCDELIM_1                                          (0x0010)              /* 2 bit times */
+//#define UCDELIM_2                                          (0x0020)              /* 3 bit times */
+//#define UCDELIM_3                                          (0x0030)              /* 4 bit times */
+/* UCA3IRCTL[UCIREN] Bits */
+//#define UCIREN_OFS                                         ( 0)                  /* UCIREN Offset */
+//#define UCIREN                                             (0x0001)              /* IrDA encoder/decoder enable */
+/* UCA3IRCTL[UCIRTXCLK] Bits */
+//#define UCIRTXCLK_OFS                                      ( 1)                  /* UCIRTXCLK Offset */
+//#define UCIRTXCLK                                          (0x0002)              /* IrDA transmit pulse clock select */
+/* UCA3IRCTL[UCIRTXPL] Bits */
+//#define UCIRTXPL_OFS                                       ( 2)                  /* UCIRTXPL Offset */
+//#define UCIRTXPL_M                                         (0x00fc)              /* Transmit pulse length */
+/* UCA3IRCTL[UCIRRXFE] Bits */
+//#define UCIRRXFE_OFS                                       ( 8)                  /* UCIRRXFE Offset */
+//#define UCIRRXFE                                           (0x0100)              /* IrDA receive filter enabled */
+/* UCA3IRCTL[UCIRRXPL] Bits */
+//#define UCIRRXPL_OFS                                       ( 9)                  /* UCIRRXPL Offset */
+//#define UCIRRXPL                                           (0x0200)              /* IrDA receive input UCAxRXD polarity */
+/* UCA3IRCTL[UCIRRXFL] Bits */
+//#define UCIRRXFL_OFS                                       (10)                  /* UCIRRXFL Offset */
+//#define UCIRRXFL_M                                         (0x3c00)              /* Receive filter length */
+/* UCA3IE[UCRXIE] Bits */
+//#define UCRXIE_OFS                                         ( 0)                  /* UCRXIE Offset */
+//#define UCRXIE                                             (0x0001)              /* Receive interrupt enable */
+/* UCA3IE[UCTXIE] Bits */
+//#define UCTXIE_OFS                                         ( 1)                  /* UCTXIE Offset */
+//#define UCTXIE                                             (0x0002)              /* Transmit interrupt enable */
+/* UCA3IE[UCSTTIE] Bits */
+//#define UCSTTIE_OFS                                        ( 2)                  /* UCSTTIE Offset */
+//#define UCSTTIE                                            (0x0004)              /* Start bit interrupt enable */
+/* UCA3IE[UCTXCPTIE] Bits */
+//#define UCTXCPTIE_OFS                                      ( 3)                  /* UCTXCPTIE Offset */
+//#define UCTXCPTIE                                          (0x0008)              /* Transmit complete interrupt enable */
+/* UCA3IE_SPI[UCRXIE] Bits */
+//#define UCRXIE_OFS                                         ( 0)                  /* UCRXIE Offset */
+//#define UCRXIE                                             (0x0001)              /* Receive interrupt enable */
+/* UCA3IE_SPI[UCTXIE] Bits */
+//#define UCTXIE_OFS                                         ( 1)                  /* UCTXIE Offset */
+//#define UCTXIE                                             (0x0002)              /* Transmit interrupt enable */
+/* UCA3IFG[UCRXIFG] Bits */
+//#define UCRXIFG_OFS                                        ( 0)                  /* UCRXIFG Offset */
+//#define UCRXIFG                                            (0x0001)              /* Receive interrupt flag */
+/* UCA3IFG[UCTXIFG] Bits */
+//#define UCTXIFG_OFS                                        ( 1)                  /* UCTXIFG Offset */
+//#define UCTXIFG                                            (0x0002)              /* Transmit interrupt flag */
+/* UCA3IFG[UCSTTIFG] Bits */
+//#define UCSTTIFG_OFS                                       ( 2)                  /* UCSTTIFG Offset */
+//#define UCSTTIFG                                           (0x0004)              /* Start bit interrupt flag */
+/* UCA3IFG[UCTXCPTIFG] Bits */
+//#define UCTXCPTIFG_OFS                                     ( 3)                  /* UCTXCPTIFG Offset */
+//#define UCTXCPTIFG                                         (0x0008)              /* Transmit ready interrupt enable */
+/* UCA3IFG_SPI[UCRXIFG] Bits */
+//#define UCRXIFG_OFS                                        ( 0)                  /* UCRXIFG Offset */
+//#define UCRXIFG                                            (0x0001)              /* Receive interrupt flag */
+/* UCA3IFG_SPI[UCTXIFG] Bits */
+//#define UCTXIFG_OFS                                        ( 1)                  /* UCTXIFG Offset */
+//#define UCTXIFG                                            (0x0002)              /* Transmit interrupt flag */
+
+
+//*****************************************************************************
+// EUSCI_B0 Bits
+//*****************************************************************************
+/* UCB0CTLW0[UCSWRST] Bits */
+//#define UCSWRST_OFS                                        ( 0)                  /* UCSWRST Offset */
+//#define UCSWRST                                            (0x0001)              /* Software reset enable */
+/* UCB0CTLW0[UCTXSTT] Bits */
+#define UCTXSTT_OFS                                        ( 1)                  /* UCTXSTT Offset */
+#define UCTXSTT                                            (0x0002)              /* Transmit START condition in master mode */
+/* UCB0CTLW0[UCTXSTP] Bits */
+#define UCTXSTP_OFS                                        ( 2)                  /* UCTXSTP Offset */
+#define UCTXSTP                                            (0x0004)              /* Transmit STOP condition in master mode */
+/* UCB0CTLW0[UCTXNACK] Bits */
+#define UCTXNACK_OFS                                       ( 3)                  /* UCTXNACK Offset */
+#define UCTXNACK                                           (0x0008)              /* Transmit a NACK */
+/* UCB0CTLW0[UCTR] Bits */
+#define UCTR_OFS                                           ( 4)                  /* UCTR Offset */
+#define UCTR                                               (0x0010)              /* Transmitter/receiver */
+/* UCB0CTLW0[UCTXACK] Bits */
+#define UCTXACK_OFS                                        ( 5)                  /* UCTXACK Offset */
+#define UCTXACK                                            (0x0020)              /* Transmit ACK condition in slave mode */
+/* UCB0CTLW0[UCSSEL] Bits */
+//#define UCSSEL_OFS                                         ( 6)                  /* UCSSEL Offset */
+//#define UCSSEL_M                                           (0x00c0)              /* eUSCI_B clock source select */
+//#define UCSSEL0                                            (0x0040)              /* eUSCI_B clock source select */
+//#define UCSSEL1                                            (0x0080)              /* eUSCI_B clock source select */
+//#define UCSSEL_0                                           (0x0000)              /* UCLKI */
+//#define UCSSEL_1                                           (0x0040)              /* ACLK */
+//#define UCSSEL_2                                           (0x0080)              /* SMCLK */
+#define UCSSEL__UCLKI                                      (0x0000)              /* UCLKI */
+//#define UCSSEL__ACLK                                       (0x0040)              /* ACLK */
+//#define UCSSEL__SMCLK                                      (0x0080)              /* SMCLK */
+#define UCSSEL_3                                           (0x00c0)              /* SMCLK */
+/* UCB0CTLW0[UCSYNC] Bits */
+//#define UCSYNC_OFS                                         ( 8)                  /* UCSYNC Offset */
+//#define UCSYNC                                             (0x0100)              /* Synchronous mode enable */
+/* UCB0CTLW0[UCMODE] Bits */
+//#define UCMODE_OFS                                         ( 9)                  /* UCMODE Offset */
+//#define UCMODE_M                                           (0x0600)              /* eUSCI_B mode */
+//#define UCMODE0                                            (0x0200)              /* eUSCI_B mode */
+//#define UCMODE1                                            (0x0400)              /* eUSCI_B mode */
+//#define UCMODE_0                                           (0x0000)              /* 3-pin SPI */
+//#define UCMODE_1                                           (0x0200)              /* 4-pin SPI (master or slave enabled if STE = 1) */
+//#define UCMODE_2                                           (0x0400)              /* 4-pin SPI (master or slave enabled if STE = 0) */
+//#define UCMODE_3                                           (0x0600)              /* I2C mode */
+/* UCB0CTLW0[UCMST] Bits */
+//#define UCMST_OFS                                          (11)                  /* UCMST Offset */
+//#define UCMST                                              (0x0800)              /* Master mode select */
+/* UCB0CTLW0[UCMM] Bits */
+#define UCMM_OFS                                           (13)                  /* UCMM Offset */
+#define UCMM                                               (0x2000)              /* Multi-master environment select */
+/* UCB0CTLW0[UCSLA10] Bits */
+#define UCSLA10_OFS                                        (14)                  /* UCSLA10 Offset */
+#define UCSLA10                                            (0x4000)              /* Slave addressing mode select */
+/* UCB0CTLW0[UCA10] Bits */
+#define UCA10_OFS                                          (15)                  /* UCA10 Offset */
+#define UCA10                                              (0x8000)              /* Own addressing mode select */
+/* UCB0CTLW0_SPI[UCSWRST] Bits */
+//#define UCSWRST_OFS                                        ( 0)                  /* UCSWRST Offset */
+//#define UCSWRST                                            (0x0001)              /* Software reset enable */
+/* UCB0CTLW0_SPI[UCSTEM] Bits */
+//#define UCSTEM_OFS                                         ( 1)                  /* UCSTEM Offset */
+//#define UCSTEM                                             (0x0002)              /* STE mode select in master mode. */
+/* UCB0CTLW0_SPI[UCSSEL] Bits */
+//#define UCSSEL_OFS                                         ( 6)                  /* UCSSEL Offset */
+//#define UCSSEL_M                                           (0x00c0)              /* eUSCI_B clock source select */
+//#define UCSSEL0                                            (0x0040)              /* eUSCI_B clock source select */
+//#define UCSSEL1                                            (0x0080)              /* eUSCI_B clock source select */
+//#define UCSSEL_1                                           (0x0040)              /* ACLK */
+//#define UCSSEL_2                                           (0x0080)              /* SMCLK */
+//#define UCSSEL_0                                           (0x0000)              /* Reserved */
+//#define UCSSEL__ACLK                                       (0x0040)              /* ACLK */
+//#define UCSSEL__SMCLK                                      (0x0080)              /* SMCLK */
+//#define UCSSEL_3                                           (0x00c0)              /* SMCLK */
+/* UCB0CTLW0_SPI[UCSYNC] Bits */
+//#define UCSYNC_OFS                                         ( 8)                  /* UCSYNC Offset */
+//#define UCSYNC                                             (0x0100)              /* Synchronous mode enable */
+/* UCB0CTLW0_SPI[UCMODE] Bits */
+//#define UCMODE_OFS                                         ( 9)                  /* UCMODE Offset */
+//#define UCMODE_M                                           (0x0600)              /* eUSCI mode */
+//#define UCMODE0                                            (0x0200)              /* eUSCI mode */
+//#define UCMODE1                                            (0x0400)              /* eUSCI mode */
+//#define UCMODE_0                                           (0x0000)              /* 3-pin SPI */
+//#define UCMODE_1                                           (0x0200)              /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */
+//#define UCMODE_2                                           (0x0400)              /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */
+//#define UCMODE_3                                           (0x0600)              /* I2C mode */
+/* UCB0CTLW0_SPI[UCMST] Bits */
+//#define UCMST_OFS                                          (11)                  /* UCMST Offset */
+//#define UCMST                                              (0x0800)              /* Master mode select */
+/* UCB0CTLW0_SPI[UC7BIT] Bits */
+//#define UC7BIT_OFS                                         (12)                  /* UC7BIT Offset */
+//#define UC7BIT                                             (0x1000)              /* Character length */
+/* UCB0CTLW0_SPI[UCMSB] Bits */
+//#define UCMSB_OFS                                          (13)                  /* UCMSB Offset */
+//#define UCMSB                                              (0x2000)              /* MSB first select */
+/* UCB0CTLW0_SPI[UCCKPL] Bits */
+//#define UCCKPL_OFS                                         (14)                  /* UCCKPL Offset */
+//#define UCCKPL                                             (0x4000)              /* Clock polarity select */
+/* UCB0CTLW0_SPI[UCCKPH] Bits */
+//#define UCCKPH_OFS                                         (15)                  /* UCCKPH Offset */
+//#define UCCKPH                                             (0x8000)              /* Clock phase select */
+/* UCB0CTLW1[UCGLIT] Bits */
+//#define UCGLIT_OFS                                         ( 0)                  /* UCGLIT Offset */
+//#define UCGLIT_M                                           (0x0003)              /* Deglitch time */
+//#define UCGLIT0                                            (0x0001)              /* Deglitch time */
+//#define UCGLIT1                                            (0x0002)              /* Deglitch time */
+//#define UCGLIT_0                                           (0x0000)              /* 50 ns */
+//#define UCGLIT_1                                           (0x0001)              /* 25 ns */
+//#define UCGLIT_2                                           (0x0002)              /* 12.5 ns */
+//#define UCGLIT_3                                           (0x0003)              /* 6.25 ns */
+/* UCB0CTLW1[UCASTP] Bits */
+#define UCASTP_OFS                                         ( 2)                  /* UCASTP Offset */
+#define UCASTP_M                                           (0x000c)              /* Automatic STOP condition generation */
+#define UCASTP0                                            (0x0004)              /* Automatic STOP condition generation */
+#define UCASTP1                                            (0x0008)              /* Automatic STOP condition generation */
+#define UCASTP_0                                           (0x0000)              /* No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */
+#define UCASTP_1                                           (0x0004)              /* UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT */
+#define UCASTP_2                                           (0x0008)              /* A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold */
+/* UCB0CTLW1[UCSWACK] Bits */
+#define UCSWACK_OFS                                        ( 4)                  /* UCSWACK Offset */
+#define UCSWACK                                            (0x0010)              /* SW or HW ACK control */
+/* UCB0CTLW1[UCSTPNACK] Bits */
+#define UCSTPNACK_OFS                                      ( 5)                  /* UCSTPNACK Offset */
+#define UCSTPNACK                                          (0x0020)              /* ACK all master bytes */
+/* UCB0CTLW1[UCCLTO] Bits */
+#define UCCLTO_OFS                                         ( 6)                  /* UCCLTO Offset */
+#define UCCLTO_M                                           (0x00c0)              /* Clock low timeout select */
+#define UCCLTO0                                            (0x0040)              /* Clock low timeout select */
+#define UCCLTO1                                            (0x0080)              /* Clock low timeout select */
+#define UCCLTO_0                                           (0x0000)              /* Disable clock low timeout counter */
+#define UCCLTO_1                                           (0x0040)              /* 135 000 SYSCLK cycles (approximately 28 ms) */
+#define UCCLTO_2                                           (0x0080)              /* 150 000 SYSCLK cycles (approximately 31 ms) */
+#define UCCLTO_3                                           (0x00c0)              /* 165 000 SYSCLK cycles (approximately 34 ms) */
+/* UCB0CTLW1[UCETXINT] Bits */
+#define UCETXINT_OFS                                       ( 8)                  /* UCETXINT Offset */
+#define UCETXINT                                           (0x0100)              /* Early UCTXIFG0 */
+/* UCB0STATW[UCBBUSY] Bits */
+#define UCBBUSY_OFS                                        ( 4)                  /* UCBBUSY Offset */
+#define UCBBUSY                                            (0x0010)              /* Bus busy */
+/* UCB0STATW[UCGC] Bits */
+#define UCGC_OFS                                           ( 5)                  /* UCGC Offset */
+#define UCGC                                               (0x0020)              /* General call address received */
+/* UCB0STATW[UCSCLLOW] Bits */
+#define UCSCLLOW_OFS                                       ( 6)                  /* UCSCLLOW Offset */
+#define UCSCLLOW                                           (0x0040)              /* SCL low */
+/* UCB0STATW[UCBCNT] Bits */
+#define UCBCNT_OFS                                         ( 8)                  /* UCBCNT Offset */
+#define UCBCNT_M                                           (0xff00)              /* Hardware byte counter value */
+/* UCB0STATW_SPI[UCBUSY] Bits */
+//#define UCBUSY_OFS                                         ( 0)                  /* UCBUSY Offset */
+//#define UCBUSY                                             (0x0001)              /* eUSCI_B busy */
+/* UCB0STATW_SPI[UCOE] Bits */
+//#define UCOE_OFS                                           ( 5)                  /* UCOE Offset */
+//#define UCOE                                               (0x0020)              /* Overrun error flag */
+/* UCB0STATW_SPI[UCFE] Bits */
+//#define UCFE_OFS                                           ( 6)                  /* UCFE Offset */
+//#define UCFE                                               (0x0040)              /* Framing error flag */
+/* UCB0STATW_SPI[UCLISTEN] Bits */
+//#define UCLISTEN_OFS                                       ( 7)                  /* UCLISTEN Offset */
+//#define UCLISTEN                                           (0x0080)              /* Listen enable */
+/* UCB0TBCNT[UCTBCNT] Bits */
+#define UCTBCNT_OFS                                        ( 0)                  /* UCTBCNT Offset */
+#define UCTBCNT_M                                          (0x00ff)              /* Byte counter threshold value */
+/* UCB0RXBUF[UCRXBUF] Bits */
+//#define UCRXBUF_OFS                                        ( 0)                  /* UCRXBUF Offset */
+//#define UCRXBUF_M                                          (0x00ff)              /* Receive data buffer */
+/* UCB0RXBUF_SPI[UCRXBUF] Bits */
+//#define UCRXBUF_OFS                                        ( 0)                  /* UCRXBUF Offset */
+//#define UCRXBUF_M                                          (0x00ff)              /* Receive data buffer */
+/* UCB0TXBUF[UCTXBUF] Bits */
+//#define UCTXBUF_OFS                                        ( 0)                  /* UCTXBUF Offset */
+//#define UCTXBUF_M                                          (0x00ff)              /* Transmit data buffer */
+/* UCB0TXBUF_SPI[UCTXBUF] Bits */
+//#define UCTXBUF_OFS                                        ( 0)                  /* UCTXBUF Offset */
+//#define UCTXBUF_M                                          (0x00ff)              /* Transmit data buffer */
+/* UCB0I2COA0[I2COA0] Bits */
+#define I2COA0_OFS                                         ( 0)                  /* I2COA0 Offset */
+#define I2COA0_M                                           (0x03ff)              /* I2C own address */
+/* UCB0I2COA0[UCOAEN] Bits */
+#define UCOAEN_OFS                                         (10)                  /* UCOAEN Offset */
+#define UCOAEN                                             (0x0400)              /* Own Address enable register */
+/* UCB0I2COA0[UCGCEN] Bits */
+#define UCGCEN_OFS                                         (15)                  /* UCGCEN Offset */
+#define UCGCEN                                             (0x8000)              /* General call response enable */
+/* UCB0I2COA1[I2COA1] Bits */
+#define I2COA1_OFS                                         ( 0)                  /* I2COA1 Offset */
+#define I2COA1_M                                           (0x03ff)              /* I2C own address */
+/* UCB0I2COA1[UCOAEN] Bits */
+//#define UCOAEN_OFS                                         (10)                  /* UCOAEN Offset */
+//#define UCOAEN                                             (0x0400)              /* Own Address enable register */
+/* UCB0I2COA2[I2COA2] Bits */
+#define I2COA2_OFS                                         ( 0)                  /* I2COA2 Offset */
+#define I2COA2_M                                           (0x03ff)              /* I2C own address */
+/* UCB0I2COA2[UCOAEN] Bits */
+//#define UCOAEN_OFS                                         (10)                  /* UCOAEN Offset */
+//#define UCOAEN                                             (0x0400)              /* Own Address enable register */
+/* UCB0I2COA3[I2COA3] Bits */
+#define I2COA3_OFS                                         ( 0)                  /* I2COA3 Offset */
+#define I2COA3_M                                           (0x03ff)              /* I2C own address */
+/* UCB0I2COA3[UCOAEN] Bits */
+//#define UCOAEN_OFS                                         (10)                  /* UCOAEN Offset */
+//#define UCOAEN                                             (0x0400)              /* Own Address enable register */
+/* UCB0ADDRX[ADDRX] Bits */
+#define ADDRX_OFS                                          ( 0)                  /* ADDRX Offset */
+#define ADDRX_M                                            (0x03ff)              /* Received Address Register */
+/* UCB0ADDMASK[ADDMASK] Bits */
+#define ADDMASK_OFS                                        ( 0)                  /* ADDMASK Offset */
+#define ADDMASK_M                                          (0x03ff)              /*  */
+/* UCB0I2CSA[I2CSA] Bits */
+#define I2CSA_OFS                                          ( 0)                  /* I2CSA Offset */
+#define I2CSA_M                                            (0x03ff)              /* I2C slave address */
+/* UCB0IE[UCRXIE0] Bits */
+#define UCRXIE0_OFS                                        ( 0)                  /* UCRXIE0 Offset */
+#define UCRXIE0                                            (0x0001)              /* Receive interrupt enable 0 */
+/* UCB0IE[UCTXIE0] Bits */
+#define UCTXIE0_OFS                                        ( 1)                  /* UCTXIE0 Offset */
+#define UCTXIE0                                            (0x0002)              /* Transmit interrupt enable 0 */
+/* UCB0IE[UCSTTIE] Bits */
+//#define UCSTTIE_OFS                                        ( 2)                  /* UCSTTIE Offset */
+//#define UCSTTIE                                            (0x0004)              /* START condition interrupt enable */
+/* UCB0IE[UCSTPIE] Bits */
+#define UCSTPIE_OFS                                        ( 3)                  /* UCSTPIE Offset */
+#define UCSTPIE                                            (0x0008)              /* STOP condition interrupt enable */
+/* UCB0IE[UCALIE] Bits */
+#define UCALIE_OFS                                         ( 4)                  /* UCALIE Offset */
+#define UCALIE                                             (0x0010)              /* Arbitration lost interrupt enable */
+/* UCB0IE[UCNACKIE] Bits */
+#define UCNACKIE_OFS                                       ( 5)                  /* UCNACKIE Offset */
+#define UCNACKIE                                           (0x0020)              /* Not-acknowledge interrupt enable */
+/* UCB0IE[UCBCNTIE] Bits */
+#define UCBCNTIE_OFS                                       ( 6)                  /* UCBCNTIE Offset */
+#define UCBCNTIE                                           (0x0040)              /* Byte counter interrupt enable */
+/* UCB0IE[UCCLTOIE] Bits */
+#define UCCLTOIE_OFS                                       ( 7)                  /* UCCLTOIE Offset */
+#define UCCLTOIE                                           (0x0080)              /* Clock low timeout interrupt enable */
+/* UCB0IE[UCRXIE1] Bits */
+#define UCRXIE1_OFS                                        ( 8)                  /* UCRXIE1 Offset */
+#define UCRXIE1                                            (0x0100)              /* Receive interrupt enable 1 */
+/* UCB0IE[UCTXIE1] Bits */
+#define UCTXIE1_OFS                                        ( 9)                  /* UCTXIE1 Offset */
+#define UCTXIE1                                            (0x0200)              /* Transmit interrupt enable 1 */
+/* UCB0IE[UCRXIE2] Bits */
+#define UCRXIE2_OFS                                        (10)                  /* UCRXIE2 Offset */
+#define UCRXIE2                                            (0x0400)              /* Receive interrupt enable 2 */
+/* UCB0IE[UCTXIE2] Bits */
+#define UCTXIE2_OFS                                        (11)                  /* UCTXIE2 Offset */
+#define UCTXIE2                                            (0x0800)              /* Transmit interrupt enable 2 */
+/* UCB0IE[UCRXIE3] Bits */
+#define UCRXIE3_OFS                                        (12)                  /* UCRXIE3 Offset */
+#define UCRXIE3                                            (0x1000)              /* Receive interrupt enable 3 */
+/* UCB0IE[UCTXIE3] Bits */
+#define UCTXIE3_OFS                                        (13)                  /* UCTXIE3 Offset */
+#define UCTXIE3                                            (0x2000)              /* Transmit interrupt enable 3 */
+/* UCB0IE[UCBIT9IE] Bits */
+#define UCBIT9IE_OFS                                       (14)                  /* UCBIT9IE Offset */
+#define UCBIT9IE                                           (0x4000)              /* Bit position 9 interrupt enable */
+/* UCB0IE_SPI[UCRXIE] Bits */
+//#define UCRXIE_OFS                                         ( 0)                  /* UCRXIE Offset */
+//#define UCRXIE                                             (0x0001)              /* Receive interrupt enable */
+/* UCB0IE_SPI[UCTXIE] Bits */
+//#define UCTXIE_OFS                                         ( 1)                  /* UCTXIE Offset */
+//#define UCTXIE                                             (0x0002)              /* Transmit interrupt enable */
+/* UCB0IFG[UCRXIFG0] Bits */
+#define UCRXIFG0_OFS                                       ( 0)                  /* UCRXIFG0 Offset */
+#define UCRXIFG0                                           (0x0001)              /* eUSCI_B receive interrupt flag 0 */
+/* UCB0IFG[UCTXIFG0] Bits */
+#define UCTXIFG0_OFS                                       ( 1)                  /* UCTXIFG0 Offset */
+#define UCTXIFG0                                           (0x0002)              /* eUSCI_B transmit interrupt flag 0 */
+/* UCB0IFG[UCSTTIFG] Bits */
+//#define UCSTTIFG_OFS                                       ( 2)                  /* UCSTTIFG Offset */
+//#define UCSTTIFG                                           (0x0004)              /* START condition interrupt flag */
+/* UCB0IFG[UCSTPIFG] Bits */
+#define UCSTPIFG_OFS                                       ( 3)                  /* UCSTPIFG Offset */
+#define UCSTPIFG                                           (0x0008)              /* STOP condition interrupt flag */
+/* UCB0IFG[UCALIFG] Bits */
+#define UCALIFG_OFS                                        ( 4)                  /* UCALIFG Offset */
+#define UCALIFG                                            (0x0010)              /* Arbitration lost interrupt flag */
+/* UCB0IFG[UCNACKIFG] Bits */
+#define UCNACKIFG_OFS                                      ( 5)                  /* UCNACKIFG Offset */
+#define UCNACKIFG                                          (0x0020)              /* Not-acknowledge received interrupt flag */
+/* UCB0IFG[UCBCNTIFG] Bits */
+#define UCBCNTIFG_OFS                                      ( 6)                  /* UCBCNTIFG Offset */
+#define UCBCNTIFG                                          (0x0040)              /* Byte counter interrupt flag */
+/* UCB0IFG[UCCLTOIFG] Bits */
+#define UCCLTOIFG_OFS                                      ( 7)                  /* UCCLTOIFG Offset */
+#define UCCLTOIFG                                          (0x0080)              /* Clock low timeout interrupt flag */
+/* UCB0IFG[UCRXIFG1] Bits */
+#define UCRXIFG1_OFS                                       ( 8)                  /* UCRXIFG1 Offset */
+#define UCRXIFG1                                           (0x0100)              /* eUSCI_B receive interrupt flag 1 */
+/* UCB0IFG[UCTXIFG1] Bits */
+#define UCTXIFG1_OFS                                       ( 9)                  /* UCTXIFG1 Offset */
+#define UCTXIFG1                                           (0x0200)              /* eUSCI_B transmit interrupt flag 1 */
+/* UCB0IFG[UCRXIFG2] Bits */
+#define UCRXIFG2_OFS                                       (10)                  /* UCRXIFG2 Offset */
+#define UCRXIFG2                                           (0x0400)              /* eUSCI_B receive interrupt flag 2 */
+/* UCB0IFG[UCTXIFG2] Bits */
+#define UCTXIFG2_OFS                                       (11)                  /* UCTXIFG2 Offset */
+#define UCTXIFG2                                           (0x0800)              /* eUSCI_B transmit interrupt flag 2 */
+/* UCB0IFG[UCRXIFG3] Bits */
+#define UCRXIFG3_OFS                                       (12)                  /* UCRXIFG3 Offset */
+#define UCRXIFG3                                           (0x1000)              /* eUSCI_B receive interrupt flag 3 */
+/* UCB0IFG[UCTXIFG3] Bits */
+#define UCTXIFG3_OFS                                       (13)                  /* UCTXIFG3 Offset */
+#define UCTXIFG3                                           (0x2000)              /* eUSCI_B transmit interrupt flag 3 */
+/* UCB0IFG[UCBIT9IFG] Bits */
+#define UCBIT9IFG_OFS                                      (14)                  /* UCBIT9IFG Offset */
+#define UCBIT9IFG                                          (0x4000)              /* Bit position 9 interrupt flag */
+/* UCB0IFG_SPI[UCRXIFG] Bits */
+//#define UCRXIFG_OFS                                        ( 0)                  /* UCRXIFG Offset */
+//#define UCRXIFG                                            (0x0001)              /* Receive interrupt flag */
+/* UCB0IFG_SPI[UCTXIFG] Bits */
+//#define UCTXIFG_OFS                                        ( 1)                  /* UCTXIFG Offset */
+//#define UCTXIFG                                            (0x0002)              /* Transmit interrupt flag */
+
+
+//*****************************************************************************
+// EUSCI_B1 Bits
+//*****************************************************************************
+/* UCB1CTLW0[UCSWRST] Bits */
+//#define UCSWRST_OFS                                        ( 0)                  /* UCSWRST Offset */
+//#define UCSWRST                                            (0x0001)              /* Software reset enable */
+/* UCB1CTLW0[UCTXSTT] Bits */
+//#define UCTXSTT_OFS                                        ( 1)                  /* UCTXSTT Offset */
+//#define UCTXSTT                                            (0x0002)              /* Transmit START condition in master mode */
+/* UCB1CTLW0[UCTXSTP] Bits */
+//#define UCTXSTP_OFS                                        ( 2)                  /* UCTXSTP Offset */
+//#define UCTXSTP                                            (0x0004)              /* Transmit STOP condition in master mode */
+/* UCB1CTLW0[UCTXNACK] Bits */
+//#define UCTXNACK_OFS                                       ( 3)                  /* UCTXNACK Offset */
+//#define UCTXNACK                                           (0x0008)              /* Transmit a NACK */
+/* UCB1CTLW0[UCTR] Bits */
+//#define UCTR_OFS                                           ( 4)                  /* UCTR Offset */
+//#define UCTR                                               (0x0010)              /* Transmitter/receiver */
+/* UCB1CTLW0[UCTXACK] Bits */
+//#define UCTXACK_OFS                                        ( 5)                  /* UCTXACK Offset */
+//#define UCTXACK                                            (0x0020)              /* Transmit ACK condition in slave mode */
+/* UCB1CTLW0[UCSSEL] Bits */
+//#define UCSSEL_OFS                                         ( 6)                  /* UCSSEL Offset */
+//#define UCSSEL_M                                           (0x00c0)              /* eUSCI_B clock source select */
+//#define UCSSEL0                                            (0x0040)              /* eUSCI_B clock source select */
+//#define UCSSEL1                                            (0x0080)              /* eUSCI_B clock source select */
+//#define UCSSEL_0                                           (0x0000)              /* UCLKI */
+//#define UCSSEL_1                                           (0x0040)              /* ACLK */
+//#define UCSSEL_2                                           (0x0080)              /* SMCLK */
+//#define UCSSEL__UCLKI                                      (0x0000)              /* UCLKI */
+//#define UCSSEL__ACLK                                       (0x0040)              /* ACLK */
+//#define UCSSEL__SMCLK                                      (0x0080)              /* SMCLK */
+//#define UCSSEL_3                                           (0x00c0)              /* SMCLK */
+/* UCB1CTLW0[UCSYNC] Bits */
+//#define UCSYNC_OFS                                         ( 8)                  /* UCSYNC Offset */
+//#define UCSYNC                                             (0x0100)              /* Synchronous mode enable */
+/* UCB1CTLW0[UCMODE] Bits */
+//#define UCMODE_OFS                                         ( 9)                  /* UCMODE Offset */
+//#define UCMODE_M                                           (0x0600)              /* eUSCI_B mode */
+//#define UCMODE0                                            (0x0200)              /* eUSCI_B mode */
+//#define UCMODE1                                            (0x0400)              /* eUSCI_B mode */
+//#define UCMODE_0                                           (0x0000)              /* 3-pin SPI */
+//#define UCMODE_1                                           (0x0200)              /* 4-pin SPI (master or slave enabled if STE = 1) */
+//#define UCMODE_2                                           (0x0400)              /* 4-pin SPI (master or slave enabled if STE = 0) */
+//#define UCMODE_3                                           (0x0600)              /* I2C mode */
+/* UCB1CTLW0[UCMST] Bits */
+//#define UCMST_OFS                                          (11)                  /* UCMST Offset */
+//#define UCMST                                              (0x0800)              /* Master mode select */
+/* UCB1CTLW0[UCMM] Bits */
+//#define UCMM_OFS                                           (13)                  /* UCMM Offset */
+//#define UCMM                                               (0x2000)              /* Multi-master environment select */
+/* UCB1CTLW0[UCSLA10] Bits */
+//#define UCSLA10_OFS                                        (14)                  /* UCSLA10 Offset */
+//#define UCSLA10                                            (0x4000)              /* Slave addressing mode select */
+/* UCB1CTLW0[UCA10] Bits */
+//#define UCA10_OFS                                          (15)                  /* UCA10 Offset */
+//#define UCA10                                              (0x8000)              /* Own addressing mode select */
+/* UCB1CTLW0_SPI[UCSWRST] Bits */
+//#define UCSWRST_OFS                                        ( 0)                  /* UCSWRST Offset */
+//#define UCSWRST                                            (0x0001)              /* Software reset enable */
+/* UCB1CTLW0_SPI[UCSTEM] Bits */
+//#define UCSTEM_OFS                                         ( 1)                  /* UCSTEM Offset */
+//#define UCSTEM                                             (0x0002)              /* STE mode select in master mode. */
+/* UCB1CTLW0_SPI[UCSSEL] Bits */
+//#define UCSSEL_OFS                                         ( 6)                  /* UCSSEL Offset */
+//#define UCSSEL_M                                           (0x00c0)              /* eUSCI_B clock source select */
+//#define UCSSEL0                                            (0x0040)              /* eUSCI_B clock source select */
+//#define UCSSEL1                                            (0x0080)              /* eUSCI_B clock source select */
+//#define UCSSEL_1                                           (0x0040)              /* ACLK */
+//#define UCSSEL_2                                           (0x0080)              /* SMCLK */
+//#define UCSSEL_0                                           (0x0000)              /* Reserved */
+//#define UCSSEL__ACLK                                       (0x0040)              /* ACLK */
+//#define UCSSEL__SMCLK                                      (0x0080)              /* SMCLK */
+//#define UCSSEL_3                                           (0x00c0)              /* SMCLK */
+/* UCB1CTLW0_SPI[UCSYNC] Bits */
+//#define UCSYNC_OFS                                         ( 8)                  /* UCSYNC Offset */
+//#define UCSYNC                                             (0x0100)              /* Synchronous mode enable */
+/* UCB1CTLW0_SPI[UCMODE] Bits */
+//#define UCMODE_OFS                                         ( 9)                  /* UCMODE Offset */
+//#define UCMODE_M                                           (0x0600)              /* eUSCI mode */
+//#define UCMODE0                                            (0x0200)              /* eUSCI mode */
+//#define UCMODE1                                            (0x0400)              /* eUSCI mode */
+//#define UCMODE_0                                           (0x0000)              /* 3-pin SPI */
+//#define UCMODE_1                                           (0x0200)              /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */
+//#define UCMODE_2                                           (0x0400)              /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */
+//#define UCMODE_3                                           (0x0600)              /* I2C mode */
+/* UCB1CTLW0_SPI[UCMST] Bits */
+//#define UCMST_OFS                                          (11)                  /* UCMST Offset */
+//#define UCMST                                              (0x0800)              /* Master mode select */
+/* UCB1CTLW0_SPI[UC7BIT] Bits */
+//#define UC7BIT_OFS                                         (12)                  /* UC7BIT Offset */
+//#define UC7BIT                                             (0x1000)              /* Character length */
+/* UCB1CTLW0_SPI[UCMSB] Bits */
+//#define UCMSB_OFS                                          (13)                  /* UCMSB Offset */
+//#define UCMSB                                              (0x2000)              /* MSB first select */
+/* UCB1CTLW0_SPI[UCCKPL] Bits */
+//#define UCCKPL_OFS                                         (14)                  /* UCCKPL Offset */
+//#define UCCKPL                                             (0x4000)              /* Clock polarity select */
+/* UCB1CTLW0_SPI[UCCKPH] Bits */
+//#define UCCKPH_OFS                                         (15)                  /* UCCKPH Offset */
+//#define UCCKPH                                             (0x8000)              /* Clock phase select */
+/* UCB1CTLW1[UCGLIT] Bits */
+//#define UCGLIT_OFS                                         ( 0)                  /* UCGLIT Offset */
+//#define UCGLIT_M                                           (0x0003)              /* Deglitch time */
+//#define UCGLIT0                                            (0x0001)              /* Deglitch time */
+//#define UCGLIT1                                            (0x0002)              /* Deglitch time */
+//#define UCGLIT_0                                           (0x0000)              /* 50 ns */
+//#define UCGLIT_1                                           (0x0001)              /* 25 ns */
+//#define UCGLIT_2                                           (0x0002)              /* 12.5 ns */
+//#define UCGLIT_3                                           (0x0003)              /* 6.25 ns */
+/* UCB1CTLW1[UCASTP] Bits */
+//#define UCASTP_OFS                                         ( 2)                  /* UCASTP Offset */
+//#define UCASTP_M                                           (0x000c)              /* Automatic STOP condition generation */
+//#define UCASTP0                                            (0x0004)              /* Automatic STOP condition generation */
+//#define UCASTP1                                            (0x0008)              /* Automatic STOP condition generation */
+//#define UCASTP_0                                           (0x0000)              /* No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */
+//#define UCASTP_1                                           (0x0004)              /* UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT */
+//#define UCASTP_2                                           (0x0008)              /* A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold */
+/* UCB1CTLW1[UCSWACK] Bits */
+//#define UCSWACK_OFS                                        ( 4)                  /* UCSWACK Offset */
+//#define UCSWACK                                            (0x0010)              /* SW or HW ACK control */
+/* UCB1CTLW1[UCSTPNACK] Bits */
+//#define UCSTPNACK_OFS                                      ( 5)                  /* UCSTPNACK Offset */
+//#define UCSTPNACK                                          (0x0020)              /* ACK all master bytes */
+/* UCB1CTLW1[UCCLTO] Bits */
+//#define UCCLTO_OFS                                         ( 6)                  /* UCCLTO Offset */
+//#define UCCLTO_M                                           (0x00c0)              /* Clock low timeout select */
+//#define UCCLTO0                                            (0x0040)              /* Clock low timeout select */
+//#define UCCLTO1                                            (0x0080)              /* Clock low timeout select */
+//#define UCCLTO_0                                           (0x0000)              /* Disable clock low timeout counter */
+//#define UCCLTO_1                                           (0x0040)              /* 135 000 SYSCLK cycles (approximately 28 ms) */
+//#define UCCLTO_2                                           (0x0080)              /* 150 000 SYSCLK cycles (approximately 31 ms) */
+//#define UCCLTO_3                                           (0x00c0)              /* 165 000 SYSCLK cycles (approximately 34 ms) */
+/* UCB1CTLW1[UCETXINT] Bits */
+//#define UCETXINT_OFS                                       ( 8)                  /* UCETXINT Offset */
+//#define UCETXINT                                           (0x0100)              /* Early UCTXIFG0 */
+/* UCB1STATW[UCBBUSY] Bits */
+//#define UCBBUSY_OFS                                        ( 4)                  /* UCBBUSY Offset */
+//#define UCBBUSY                                            (0x0010)              /* Bus busy */
+/* UCB1STATW[UCGC] Bits */
+//#define UCGC_OFS                                           ( 5)                  /* UCGC Offset */
+//#define UCGC                                               (0x0020)              /* General call address received */
+/* UCB1STATW[UCSCLLOW] Bits */
+//#define UCSCLLOW_OFS                                       ( 6)                  /* UCSCLLOW Offset */
+//#define UCSCLLOW                                           (0x0040)              /* SCL low */
+/* UCB1STATW[UCBCNT] Bits */
+//#define UCBCNT_OFS                                         ( 8)                  /* UCBCNT Offset */
+//#define UCBCNT_M                                           (0xff00)              /* Hardware byte counter value */
+/* UCB1STATW_SPI[UCBUSY] Bits */
+//#define UCBUSY_OFS                                         ( 0)                  /* UCBUSY Offset */
+//#define UCBUSY                                             (0x0001)              /* eUSCI_B busy */
+/* UCB1STATW_SPI[UCOE] Bits */
+//#define UCOE_OFS                                           ( 5)                  /* UCOE Offset */
+//#define UCOE                                               (0x0020)              /* Overrun error flag */
+/* UCB1STATW_SPI[UCFE] Bits */
+//#define UCFE_OFS                                           ( 6)                  /* UCFE Offset */
+//#define UCFE                                               (0x0040)              /* Framing error flag */
+/* UCB1STATW_SPI[UCLISTEN] Bits */
+//#define UCLISTEN_OFS                                       ( 7)                  /* UCLISTEN Offset */
+//#define UCLISTEN                                           (0x0080)              /* Listen enable */
+/* UCB1TBCNT[UCTBCNT] Bits */
+//#define UCTBCNT_OFS                                        ( 0)                  /* UCTBCNT Offset */
+//#define UCTBCNT_M                                          (0x00ff)              /* Byte counter threshold value */
+/* UCB1RXBUF[UCRXBUF] Bits */
+//#define UCRXBUF_OFS                                        ( 0)                  /* UCRXBUF Offset */
+//#define UCRXBUF_M                                          (0x00ff)              /* Receive data buffer */
+/* UCB1RXBUF_SPI[UCRXBUF] Bits */
+//#define UCRXBUF_OFS                                        ( 0)                  /* UCRXBUF Offset */
+//#define UCRXBUF_M                                          (0x00ff)              /* Receive data buffer */
+/* UCB1TXBUF[UCTXBUF] Bits */
+//#define UCTXBUF_OFS                                        ( 0)                  /* UCTXBUF Offset */
+//#define UCTXBUF_M                                          (0x00ff)              /* Transmit data buffer */
+/* UCB1TXBUF_SPI[UCTXBUF] Bits */
+//#define UCTXBUF_OFS                                        ( 0)                  /* UCTXBUF Offset */
+//#define UCTXBUF_M                                          (0x00ff)              /* Transmit data buffer */
+/* UCB1I2COA0[I2COA0] Bits */
+//#define I2COA0_OFS                                         ( 0)                  /* I2COA0 Offset */
+//#define I2COA0_M                                           (0x03ff)              /* I2C own address */
+/* UCB1I2COA0[UCOAEN] Bits */
+//#define UCOAEN_OFS                                         (10)                  /* UCOAEN Offset */
+//#define UCOAEN                                             (0x0400)              /* Own Address enable register */
+/* UCB1I2COA0[UCGCEN] Bits */
+//#define UCGCEN_OFS                                         (15)                  /* UCGCEN Offset */
+//#define UCGCEN                                             (0x8000)              /* General call response enable */
+/* UCB1I2COA1[I2COA1] Bits */
+//#define I2COA1_OFS                                         ( 0)                  /* I2COA1 Offset */
+//#define I2COA1_M                                           (0x03ff)              /* I2C own address */
+/* UCB1I2COA1[UCOAEN] Bits */
+//#define UCOAEN_OFS                                         (10)                  /* UCOAEN Offset */
+//#define UCOAEN                                             (0x0400)              /* Own Address enable register */
+/* UCB1I2COA2[I2COA2] Bits */
+//#define I2COA2_OFS                                         ( 0)                  /* I2COA2 Offset */
+//#define I2COA2_M                                           (0x03ff)              /* I2C own address */
+/* UCB1I2COA2[UCOAEN] Bits */
+//#define UCOAEN_OFS                                         (10)                  /* UCOAEN Offset */
+//#define UCOAEN                                             (0x0400)              /* Own Address enable register */
+/* UCB1I2COA3[I2COA3] Bits */
+//#define I2COA3_OFS                                         ( 0)                  /* I2COA3 Offset */
+//#define I2COA3_M                                           (0x03ff)              /* I2C own address */
+/* UCB1I2COA3[UCOAEN] Bits */
+//#define UCOAEN_OFS                                         (10)                  /* UCOAEN Offset */
+//#define UCOAEN                                             (0x0400)              /* Own Address enable register */
+/* UCB1ADDRX[ADDRX] Bits */
+//#define ADDRX_OFS                                          ( 0)                  /* ADDRX Offset */
+//#define ADDRX_M                                            (0x03ff)              /* Received Address Register */
+/* UCB1ADDMASK[ADDMASK] Bits */
+//#define ADDMASK_OFS                                        ( 0)                  /* ADDMASK Offset */
+//#define ADDMASK_M                                          (0x03ff)              /*  */
+/* UCB1I2CSA[I2CSA] Bits */
+//#define I2CSA_OFS                                          ( 0)                  /* I2CSA Offset */
+//#define I2CSA_M                                            (0x03ff)              /* I2C slave address */
+/* UCB1IE[UCRXIE0] Bits */
+//#define UCRXIE0_OFS                                        ( 0)                  /* UCRXIE0 Offset */
+//#define UCRXIE0                                            (0x0001)              /* Receive interrupt enable 0 */
+/* UCB1IE[UCTXIE0] Bits */
+//#define UCTXIE0_OFS                                        ( 1)                  /* UCTXIE0 Offset */
+//#define UCTXIE0                                            (0x0002)              /* Transmit interrupt enable 0 */
+/* UCB1IE[UCSTTIE] Bits */
+//#define UCSTTIE_OFS                                        ( 2)                  /* UCSTTIE Offset */
+//#define UCSTTIE                                            (0x0004)              /* START condition interrupt enable */
+/* UCB1IE[UCSTPIE] Bits */
+//#define UCSTPIE_OFS                                        ( 3)                  /* UCSTPIE Offset */
+//#define UCSTPIE                                            (0x0008)              /* STOP condition interrupt enable */
+/* UCB1IE[UCALIE] Bits */
+//#define UCALIE_OFS                                         ( 4)                  /* UCALIE Offset */
+//#define UCALIE                                             (0x0010)              /* Arbitration lost interrupt enable */
+/* UCB1IE[UCNACKIE] Bits */
+//#define UCNACKIE_OFS                                       ( 5)                  /* UCNACKIE Offset */
+//#define UCNACKIE                                           (0x0020)              /* Not-acknowledge interrupt enable */
+/* UCB1IE[UCBCNTIE] Bits */
+//#define UCBCNTIE_OFS                                       ( 6)                  /* UCBCNTIE Offset */
+//#define UCBCNTIE                                           (0x0040)              /* Byte counter interrupt enable */
+/* UCB1IE[UCCLTOIE] Bits */
+//#define UCCLTOIE_OFS                                       ( 7)                  /* UCCLTOIE Offset */
+//#define UCCLTOIE                                           (0x0080)              /* Clock low timeout interrupt enable */
+/* UCB1IE[UCRXIE1] Bits */
+//#define UCRXIE1_OFS                                        ( 8)                  /* UCRXIE1 Offset */
+//#define UCRXIE1                                            (0x0100)              /* Receive interrupt enable 1 */
+/* UCB1IE[UCTXIE1] Bits */
+//#define UCTXIE1_OFS                                        ( 9)                  /* UCTXIE1 Offset */
+//#define UCTXIE1                                            (0x0200)              /* Transmit interrupt enable 1 */
+/* UCB1IE[UCRXIE2] Bits */
+//#define UCRXIE2_OFS                                        (10)                  /* UCRXIE2 Offset */
+//#define UCRXIE2                                            (0x0400)              /* Receive interrupt enable 2 */
+/* UCB1IE[UCTXIE2] Bits */
+//#define UCTXIE2_OFS                                        (11)                  /* UCTXIE2 Offset */
+//#define UCTXIE2                                            (0x0800)              /* Transmit interrupt enable 2 */
+/* UCB1IE[UCRXIE3] Bits */
+//#define UCRXIE3_OFS                                        (12)                  /* UCRXIE3 Offset */
+//#define UCRXIE3                                            (0x1000)              /* Receive interrupt enable 3 */
+/* UCB1IE[UCTXIE3] Bits */
+//#define UCTXIE3_OFS                                        (13)                  /* UCTXIE3 Offset */
+//#define UCTXIE3                                            (0x2000)              /* Transmit interrupt enable 3 */
+/* UCB1IE[UCBIT9IE] Bits */
+//#define UCBIT9IE_OFS                                       (14)                  /* UCBIT9IE Offset */
+//#define UCBIT9IE                                           (0x4000)              /* Bit position 9 interrupt enable */
+/* UCB1IE_SPI[UCRXIE] Bits */
+//#define UCRXIE_OFS                                         ( 0)                  /* UCRXIE Offset */
+//#define UCRXIE                                             (0x0001)              /* Receive interrupt enable */
+/* UCB1IE_SPI[UCTXIE] Bits */
+//#define UCTXIE_OFS                                         ( 1)                  /* UCTXIE Offset */
+//#define UCTXIE                                             (0x0002)              /* Transmit interrupt enable */
+/* UCB1IFG[UCRXIFG0] Bits */
+//#define UCRXIFG0_OFS                                       ( 0)                  /* UCRXIFG0 Offset */
+//#define UCRXIFG0                                           (0x0001)              /* eUSCI_B receive interrupt flag 0 */
+/* UCB1IFG[UCTXIFG0] Bits */
+//#define UCTXIFG0_OFS                                       ( 1)                  /* UCTXIFG0 Offset */
+//#define UCTXIFG0                                           (0x0002)              /* eUSCI_B transmit interrupt flag 0 */
+/* UCB1IFG[UCSTTIFG] Bits */
+//#define UCSTTIFG_OFS                                       ( 2)                  /* UCSTTIFG Offset */
+//#define UCSTTIFG                                           (0x0004)              /* START condition interrupt flag */
+/* UCB1IFG[UCSTPIFG] Bits */
+//#define UCSTPIFG_OFS                                       ( 3)                  /* UCSTPIFG Offset */
+//#define UCSTPIFG                                           (0x0008)              /* STOP condition interrupt flag */
+/* UCB1IFG[UCALIFG] Bits */
+//#define UCALIFG_OFS                                        ( 4)                  /* UCALIFG Offset */
+//#define UCALIFG                                            (0x0010)              /* Arbitration lost interrupt flag */
+/* UCB1IFG[UCNACKIFG] Bits */
+//#define UCNACKIFG_OFS                                      ( 5)                  /* UCNACKIFG Offset */
+//#define UCNACKIFG                                          (0x0020)              /* Not-acknowledge received interrupt flag */
+/* UCB1IFG[UCBCNTIFG] Bits */
+//#define UCBCNTIFG_OFS                                      ( 6)                  /* UCBCNTIFG Offset */
+//#define UCBCNTIFG                                          (0x0040)              /* Byte counter interrupt flag */
+/* UCB1IFG[UCCLTOIFG] Bits */
+//#define UCCLTOIFG_OFS                                      ( 7)                  /* UCCLTOIFG Offset */
+//#define UCCLTOIFG                                          (0x0080)              /* Clock low timeout interrupt flag */
+/* UCB1IFG[UCRXIFG1] Bits */
+//#define UCRXIFG1_OFS                                       ( 8)                  /* UCRXIFG1 Offset */
+//#define UCRXIFG1                                           (0x0100)              /* eUSCI_B receive interrupt flag 1 */
+/* UCB1IFG[UCTXIFG1] Bits */
+//#define UCTXIFG1_OFS                                       ( 9)                  /* UCTXIFG1 Offset */
+//#define UCTXIFG1                                           (0x0200)              /* eUSCI_B transmit interrupt flag 1 */
+/* UCB1IFG[UCRXIFG2] Bits */
+//#define UCRXIFG2_OFS                                       (10)                  /* UCRXIFG2 Offset */
+//#define UCRXIFG2                                           (0x0400)              /* eUSCI_B receive interrupt flag 2 */
+/* UCB1IFG[UCTXIFG2] Bits */
+//#define UCTXIFG2_OFS                                       (11)                  /* UCTXIFG2 Offset */
+//#define UCTXIFG2                                           (0x0800)              /* eUSCI_B transmit interrupt flag 2 */
+/* UCB1IFG[UCRXIFG3] Bits */
+//#define UCRXIFG3_OFS                                       (12)                  /* UCRXIFG3 Offset */
+//#define UCRXIFG3                                           (0x1000)              /* eUSCI_B receive interrupt flag 3 */
+/* UCB1IFG[UCTXIFG3] Bits */
+//#define UCTXIFG3_OFS                                       (13)                  /* UCTXIFG3 Offset */
+//#define UCTXIFG3                                           (0x2000)              /* eUSCI_B transmit interrupt flag 3 */
+/* UCB1IFG[UCBIT9IFG] Bits */
+//#define UCBIT9IFG_OFS                                      (14)                  /* UCBIT9IFG Offset */
+//#define UCBIT9IFG                                          (0x4000)              /* Bit position 9 interrupt flag */
+/* UCB1IFG_SPI[UCRXIFG] Bits */
+//#define UCRXIFG_OFS                                        ( 0)                  /* UCRXIFG Offset */
+//#define UCRXIFG                                            (0x0001)              /* Receive interrupt flag */
+/* UCB1IFG_SPI[UCTXIFG] Bits */
+//#define UCTXIFG_OFS                                        ( 1)                  /* UCTXIFG Offset */
+//#define UCTXIFG                                            (0x0002)              /* Transmit interrupt flag */
+
+
+//*****************************************************************************
+// EUSCI_B2 Bits
+//*****************************************************************************
+/* UCB2CTLW0[UCSWRST] Bits */
+//#define UCSWRST_OFS                                        ( 0)                  /* UCSWRST Offset */
+//#define UCSWRST                                            (0x0001)              /* Software reset enable */
+/* UCB2CTLW0[UCTXSTT] Bits */
+//#define UCTXSTT_OFS                                        ( 1)                  /* UCTXSTT Offset */
+//#define UCTXSTT                                            (0x0002)              /* Transmit START condition in master mode */
+/* UCB2CTLW0[UCTXSTP] Bits */
+//#define UCTXSTP_OFS                                        ( 2)                  /* UCTXSTP Offset */
+//#define UCTXSTP                                            (0x0004)              /* Transmit STOP condition in master mode */
+/* UCB2CTLW0[UCTXNACK] Bits */
+//#define UCTXNACK_OFS                                       ( 3)                  /* UCTXNACK Offset */
+//#define UCTXNACK                                           (0x0008)              /* Transmit a NACK */
+/* UCB2CTLW0[UCTR] Bits */
+//#define UCTR_OFS                                           ( 4)                  /* UCTR Offset */
+//#define UCTR                                               (0x0010)              /* Transmitter/receiver */
+/* UCB2CTLW0[UCTXACK] Bits */
+//#define UCTXACK_OFS                                        ( 5)                  /* UCTXACK Offset */
+//#define UCTXACK                                            (0x0020)              /* Transmit ACK condition in slave mode */
+/* UCB2CTLW0[UCSSEL] Bits */
+//#define UCSSEL_OFS                                         ( 6)                  /* UCSSEL Offset */
+//#define UCSSEL_M                                           (0x00c0)              /* eUSCI_B clock source select */
+//#define UCSSEL0                                            (0x0040)              /* eUSCI_B clock source select */
+//#define UCSSEL1                                            (0x0080)              /* eUSCI_B clock source select */
+//#define UCSSEL_0                                           (0x0000)              /* UCLKI */
+//#define UCSSEL_1                                           (0x0040)              /* ACLK */
+//#define UCSSEL_2                                           (0x0080)              /* SMCLK */
+//#define UCSSEL__UCLKI                                      (0x0000)              /* UCLKI */
+//#define UCSSEL__ACLK                                       (0x0040)              /* ACLK */
+//#define UCSSEL__SMCLK                                      (0x0080)              /* SMCLK */
+//#define UCSSEL_3                                           (0x00c0)              /* SMCLK */
+/* UCB2CTLW0[UCSYNC] Bits */
+//#define UCSYNC_OFS                                         ( 8)                  /* UCSYNC Offset */
+//#define UCSYNC                                             (0x0100)              /* Synchronous mode enable */
+/* UCB2CTLW0[UCMODE] Bits */
+//#define UCMODE_OFS                                         ( 9)                  /* UCMODE Offset */
+//#define UCMODE_M                                           (0x0600)              /* eUSCI_B mode */
+//#define UCMODE0                                            (0x0200)              /* eUSCI_B mode */
+//#define UCMODE1                                            (0x0400)              /* eUSCI_B mode */
+//#define UCMODE_0                                           (0x0000)              /* 3-pin SPI */
+//#define UCMODE_1                                           (0x0200)              /* 4-pin SPI (master or slave enabled if STE = 1) */
+//#define UCMODE_2                                           (0x0400)              /* 4-pin SPI (master or slave enabled if STE = 0) */
+//#define UCMODE_3                                           (0x0600)              /* I2C mode */
+/* UCB2CTLW0[UCMST] Bits */
+//#define UCMST_OFS                                          (11)                  /* UCMST Offset */
+//#define UCMST                                              (0x0800)              /* Master mode select */
+/* UCB2CTLW0[UCMM] Bits */
+//#define UCMM_OFS                                           (13)                  /* UCMM Offset */
+//#define UCMM                                               (0x2000)              /* Multi-master environment select */
+/* UCB2CTLW0[UCSLA10] Bits */
+//#define UCSLA10_OFS                                        (14)                  /* UCSLA10 Offset */
+//#define UCSLA10                                            (0x4000)              /* Slave addressing mode select */
+/* UCB2CTLW0[UCA10] Bits */
+//#define UCA10_OFS                                          (15)                  /* UCA10 Offset */
+//#define UCA10                                              (0x8000)              /* Own addressing mode select */
+/* UCB2CTLW0_SPI[UCSWRST] Bits */
+//#define UCSWRST_OFS                                        ( 0)                  /* UCSWRST Offset */
+//#define UCSWRST                                            (0x0001)              /* Software reset enable */
+/* UCB2CTLW0_SPI[UCSTEM] Bits */
+//#define UCSTEM_OFS                                         ( 1)                  /* UCSTEM Offset */
+//#define UCSTEM                                             (0x0002)              /* STE mode select in master mode. */
+/* UCB2CTLW0_SPI[UCSSEL] Bits */
+//#define UCSSEL_OFS                                         ( 6)                  /* UCSSEL Offset */
+//#define UCSSEL_M                                           (0x00c0)              /* eUSCI_B clock source select */
+//#define UCSSEL0                                            (0x0040)              /* eUSCI_B clock source select */
+//#define UCSSEL1                                            (0x0080)              /* eUSCI_B clock source select */
+//#define UCSSEL_1                                           (0x0040)              /* ACLK */
+//#define UCSSEL_2                                           (0x0080)              /* SMCLK */
+//#define UCSSEL_0                                           (0x0000)              /* Reserved */
+//#define UCSSEL__ACLK                                       (0x0040)              /* ACLK */
+//#define UCSSEL__SMCLK                                      (0x0080)              /* SMCLK */
+//#define UCSSEL_3                                           (0x00c0)              /* SMCLK */
+/* UCB2CTLW0_SPI[UCSYNC] Bits */
+//#define UCSYNC_OFS                                         ( 8)                  /* UCSYNC Offset */
+//#define UCSYNC                                             (0x0100)              /* Synchronous mode enable */
+/* UCB2CTLW0_SPI[UCMODE] Bits */
+//#define UCMODE_OFS                                         ( 9)                  /* UCMODE Offset */
+//#define UCMODE_M                                           (0x0600)              /* eUSCI mode */
+//#define UCMODE0                                            (0x0200)              /* eUSCI mode */
+//#define UCMODE1                                            (0x0400)              /* eUSCI mode */
+//#define UCMODE_0                                           (0x0000)              /* 3-pin SPI */
+//#define UCMODE_1                                           (0x0200)              /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */
+//#define UCMODE_2                                           (0x0400)              /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */
+//#define UCMODE_3                                           (0x0600)              /* I2C mode */
+/* UCB2CTLW0_SPI[UCMST] Bits */
+//#define UCMST_OFS                                          (11)                  /* UCMST Offset */
+//#define UCMST                                              (0x0800)              /* Master mode select */
+/* UCB2CTLW0_SPI[UC7BIT] Bits */
+//#define UC7BIT_OFS                                         (12)                  /* UC7BIT Offset */
+//#define UC7BIT                                             (0x1000)              /* Character length */
+/* UCB2CTLW0_SPI[UCMSB] Bits */
+//#define UCMSB_OFS                                          (13)                  /* UCMSB Offset */
+//#define UCMSB                                              (0x2000)              /* MSB first select */
+/* UCB2CTLW0_SPI[UCCKPL] Bits */
+//#define UCCKPL_OFS                                         (14)                  /* UCCKPL Offset */
+//#define UCCKPL                                             (0x4000)              /* Clock polarity select */
+/* UCB2CTLW0_SPI[UCCKPH] Bits */
+//#define UCCKPH_OFS                                         (15)                  /* UCCKPH Offset */
+//#define UCCKPH                                             (0x8000)              /* Clock phase select */
+/* UCB2CTLW1[UCGLIT] Bits */
+//#define UCGLIT_OFS                                         ( 0)                  /* UCGLIT Offset */
+//#define UCGLIT_M                                           (0x0003)              /* Deglitch time */
+//#define UCGLIT0                                            (0x0001)              /* Deglitch time */
+//#define UCGLIT1                                            (0x0002)              /* Deglitch time */
+//#define UCGLIT_0                                           (0x0000)              /* 50 ns */
+//#define UCGLIT_1                                           (0x0001)              /* 25 ns */
+//#define UCGLIT_2                                           (0x0002)              /* 12.5 ns */
+//#define UCGLIT_3                                           (0x0003)              /* 6.25 ns */
+/* UCB2CTLW1[UCASTP] Bits */
+//#define UCASTP_OFS                                         ( 2)                  /* UCASTP Offset */
+//#define UCASTP_M                                           (0x000c)              /* Automatic STOP condition generation */
+//#define UCASTP0                                            (0x0004)              /* Automatic STOP condition generation */
+//#define UCASTP1                                            (0x0008)              /* Automatic STOP condition generation */
+//#define UCASTP_0                                           (0x0000)              /* No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */
+//#define UCASTP_1                                           (0x0004)              /* UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT */
+//#define UCASTP_2                                           (0x0008)              /* A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold */
+/* UCB2CTLW1[UCSWACK] Bits */
+//#define UCSWACK_OFS                                        ( 4)                  /* UCSWACK Offset */
+//#define UCSWACK                                            (0x0010)              /* SW or HW ACK control */
+/* UCB2CTLW1[UCSTPNACK] Bits */
+//#define UCSTPNACK_OFS                                      ( 5)                  /* UCSTPNACK Offset */
+//#define UCSTPNACK                                          (0x0020)              /* ACK all master bytes */
+/* UCB2CTLW1[UCCLTO] Bits */
+//#define UCCLTO_OFS                                         ( 6)                  /* UCCLTO Offset */
+//#define UCCLTO_M                                           (0x00c0)              /* Clock low timeout select */
+//#define UCCLTO0                                            (0x0040)              /* Clock low timeout select */
+//#define UCCLTO1                                            (0x0080)              /* Clock low timeout select */
+//#define UCCLTO_0                                           (0x0000)              /* Disable clock low timeout counter */
+//#define UCCLTO_1                                           (0x0040)              /* 135 000 SYSCLK cycles (approximately 28 ms) */
+//#define UCCLTO_2                                           (0x0080)              /* 150 000 SYSCLK cycles (approximately 31 ms) */
+//#define UCCLTO_3                                           (0x00c0)              /* 165 000 SYSCLK cycles (approximately 34 ms) */
+/* UCB2CTLW1[UCETXINT] Bits */
+//#define UCETXINT_OFS                                       ( 8)                  /* UCETXINT Offset */
+//#define UCETXINT                                           (0x0100)              /* Early UCTXIFG0 */
+/* UCB2STATW[UCBBUSY] Bits */
+//#define UCBBUSY_OFS                                        ( 4)                  /* UCBBUSY Offset */
+//#define UCBBUSY                                            (0x0010)              /* Bus busy */
+/* UCB2STATW[UCGC] Bits */
+//#define UCGC_OFS                                           ( 5)                  /* UCGC Offset */
+//#define UCGC                                               (0x0020)              /* General call address received */
+/* UCB2STATW[UCSCLLOW] Bits */
+//#define UCSCLLOW_OFS                                       ( 6)                  /* UCSCLLOW Offset */
+//#define UCSCLLOW                                           (0x0040)              /* SCL low */
+/* UCB2STATW[UCBCNT] Bits */
+//#define UCBCNT_OFS                                         ( 8)                  /* UCBCNT Offset */
+//#define UCBCNT_M                                           (0xff00)              /* Hardware byte counter value */
+/* UCB2STATW_SPI[UCBUSY] Bits */
+//#define UCBUSY_OFS                                         ( 0)                  /* UCBUSY Offset */
+//#define UCBUSY                                             (0x0001)              /* eUSCI_B busy */
+/* UCB2STATW_SPI[UCOE] Bits */
+//#define UCOE_OFS                                           ( 5)                  /* UCOE Offset */
+//#define UCOE                                               (0x0020)              /* Overrun error flag */
+/* UCB2STATW_SPI[UCFE] Bits */
+//#define UCFE_OFS                                           ( 6)                  /* UCFE Offset */
+//#define UCFE                                               (0x0040)              /* Framing error flag */
+/* UCB2STATW_SPI[UCLISTEN] Bits */
+//#define UCLISTEN_OFS                                       ( 7)                  /* UCLISTEN Offset */
+//#define UCLISTEN                                           (0x0080)              /* Listen enable */
+/* UCB2TBCNT[UCTBCNT] Bits */
+//#define UCTBCNT_OFS                                        ( 0)                  /* UCTBCNT Offset */
+//#define UCTBCNT_M                                          (0x00ff)              /* Byte counter threshold value */
+/* UCB2RXBUF[UCRXBUF] Bits */
+//#define UCRXBUF_OFS                                        ( 0)                  /* UCRXBUF Offset */
+//#define UCRXBUF_M                                          (0x00ff)              /* Receive data buffer */
+/* UCB2RXBUF_SPI[UCRXBUF] Bits */
+//#define UCRXBUF_OFS                                        ( 0)                  /* UCRXBUF Offset */
+//#define UCRXBUF_M                                          (0x00ff)              /* Receive data buffer */
+/* UCB2TXBUF[UCTXBUF] Bits */
+//#define UCTXBUF_OFS                                        ( 0)                  /* UCTXBUF Offset */
+//#define UCTXBUF_M                                          (0x00ff)              /* Transmit data buffer */
+/* UCB2TXBUF_SPI[UCTXBUF] Bits */
+//#define UCTXBUF_OFS                                        ( 0)                  /* UCTXBUF Offset */
+//#define UCTXBUF_M                                          (0x00ff)              /* Transmit data buffer */
+/* UCB2I2COA0[I2COA0] Bits */
+//#define I2COA0_OFS                                         ( 0)                  /* I2COA0 Offset */
+//#define I2COA0_M                                           (0x03ff)              /* I2C own address */
+/* UCB2I2COA0[UCOAEN] Bits */
+//#define UCOAEN_OFS                                         (10)                  /* UCOAEN Offset */
+//#define UCOAEN                                             (0x0400)              /* Own Address enable register */
+/* UCB2I2COA0[UCGCEN] Bits */
+//#define UCGCEN_OFS                                         (15)                  /* UCGCEN Offset */
+//#define UCGCEN                                             (0x8000)              /* General call response enable */
+/* UCB2I2COA1[I2COA1] Bits */
+//#define I2COA1_OFS                                         ( 0)                  /* I2COA1 Offset */
+//#define I2COA1_M                                           (0x03ff)              /* I2C own address */
+/* UCB2I2COA1[UCOAEN] Bits */
+//#define UCOAEN_OFS                                         (10)                  /* UCOAEN Offset */
+//#define UCOAEN                                             (0x0400)              /* Own Address enable register */
+/* UCB2I2COA2[I2COA2] Bits */
+//#define I2COA2_OFS                                         ( 0)                  /* I2COA2 Offset */
+//#define I2COA2_M                                           (0x03ff)              /* I2C own address */
+/* UCB2I2COA2[UCOAEN] Bits */
+//#define UCOAEN_OFS                                         (10)                  /* UCOAEN Offset */
+//#define UCOAEN                                             (0x0400)              /* Own Address enable register */
+/* UCB2I2COA3[I2COA3] Bits */
+//#define I2COA3_OFS                                         ( 0)                  /* I2COA3 Offset */
+//#define I2COA3_M                                           (0x03ff)              /* I2C own address */
+/* UCB2I2COA3[UCOAEN] Bits */
+//#define UCOAEN_OFS                                         (10)                  /* UCOAEN Offset */
+//#define UCOAEN                                             (0x0400)              /* Own Address enable register */
+/* UCB2ADDRX[ADDRX] Bits */
+//#define ADDRX_OFS                                          ( 0)                  /* ADDRX Offset */
+//#define ADDRX_M                                            (0x03ff)              /* Received Address Register */
+/* UCB2ADDMASK[ADDMASK] Bits */
+//#define ADDMASK_OFS                                        ( 0)                  /* ADDMASK Offset */
+//#define ADDMASK_M                                          (0x03ff)              /*  */
+/* UCB2I2CSA[I2CSA] Bits */
+//#define I2CSA_OFS                                          ( 0)                  /* I2CSA Offset */
+//#define I2CSA_M                                            (0x03ff)              /* I2C slave address */
+/* UCB2IE[UCRXIE0] Bits */
+//#define UCRXIE0_OFS                                        ( 0)                  /* UCRXIE0 Offset */
+//#define UCRXIE0                                            (0x0001)              /* Receive interrupt enable 0 */
+/* UCB2IE[UCTXIE0] Bits */
+//#define UCTXIE0_OFS                                        ( 1)                  /* UCTXIE0 Offset */
+//#define UCTXIE0                                            (0x0002)              /* Transmit interrupt enable 0 */
+/* UCB2IE[UCSTTIE] Bits */
+//#define UCSTTIE_OFS                                        ( 2)                  /* UCSTTIE Offset */
+//#define UCSTTIE                                            (0x0004)              /* START condition interrupt enable */
+/* UCB2IE[UCSTPIE] Bits */
+//#define UCSTPIE_OFS                                        ( 3)                  /* UCSTPIE Offset */
+//#define UCSTPIE                                            (0x0008)              /* STOP condition interrupt enable */
+/* UCB2IE[UCALIE] Bits */
+//#define UCALIE_OFS                                         ( 4)                  /* UCALIE Offset */
+//#define UCALIE                                             (0x0010)              /* Arbitration lost interrupt enable */
+/* UCB2IE[UCNACKIE] Bits */
+//#define UCNACKIE_OFS                                       ( 5)                  /* UCNACKIE Offset */
+//#define UCNACKIE                                           (0x0020)              /* Not-acknowledge interrupt enable */
+/* UCB2IE[UCBCNTIE] Bits */
+//#define UCBCNTIE_OFS                                       ( 6)                  /* UCBCNTIE Offset */
+//#define UCBCNTIE                                           (0x0040)              /* Byte counter interrupt enable */
+/* UCB2IE[UCCLTOIE] Bits */
+//#define UCCLTOIE_OFS                                       ( 7)                  /* UCCLTOIE Offset */
+//#define UCCLTOIE                                           (0x0080)              /* Clock low timeout interrupt enable */
+/* UCB2IE[UCRXIE1] Bits */
+//#define UCRXIE1_OFS                                        ( 8)                  /* UCRXIE1 Offset */
+//#define UCRXIE1                                            (0x0100)              /* Receive interrupt enable 1 */
+/* UCB2IE[UCTXIE1] Bits */
+//#define UCTXIE1_OFS                                        ( 9)                  /* UCTXIE1 Offset */
+//#define UCTXIE1                                            (0x0200)              /* Transmit interrupt enable 1 */
+/* UCB2IE[UCRXIE2] Bits */
+//#define UCRXIE2_OFS                                        (10)                  /* UCRXIE2 Offset */
+//#define UCRXIE2                                            (0x0400)              /* Receive interrupt enable 2 */
+/* UCB2IE[UCTXIE2] Bits */
+//#define UCTXIE2_OFS                                        (11)                  /* UCTXIE2 Offset */
+//#define UCTXIE2                                            (0x0800)              /* Transmit interrupt enable 2 */
+/* UCB2IE[UCRXIE3] Bits */
+//#define UCRXIE3_OFS                                        (12)                  /* UCRXIE3 Offset */
+//#define UCRXIE3                                            (0x1000)              /* Receive interrupt enable 3 */
+/* UCB2IE[UCTXIE3] Bits */
+//#define UCTXIE3_OFS                                        (13)                  /* UCTXIE3 Offset */
+//#define UCTXIE3                                            (0x2000)              /* Transmit interrupt enable 3 */
+/* UCB2IE[UCBIT9IE] Bits */
+//#define UCBIT9IE_OFS                                       (14)                  /* UCBIT9IE Offset */
+//#define UCBIT9IE                                           (0x4000)              /* Bit position 9 interrupt enable */
+/* UCB2IE_SPI[UCRXIE] Bits */
+//#define UCRXIE_OFS                                         ( 0)                  /* UCRXIE Offset */
+//#define UCRXIE                                             (0x0001)              /* Receive interrupt enable */
+/* UCB2IE_SPI[UCTXIE] Bits */
+//#define UCTXIE_OFS                                         ( 1)                  /* UCTXIE Offset */
+//#define UCTXIE                                             (0x0002)              /* Transmit interrupt enable */
+/* UCB2IFG[UCRXIFG0] Bits */
+//#define UCRXIFG0_OFS                                       ( 0)                  /* UCRXIFG0 Offset */
+//#define UCRXIFG0                                           (0x0001)              /* eUSCI_B receive interrupt flag 0 */
+/* UCB2IFG[UCTXIFG0] Bits */
+//#define UCTXIFG0_OFS                                       ( 1)                  /* UCTXIFG0 Offset */
+//#define UCTXIFG0                                           (0x0002)              /* eUSCI_B transmit interrupt flag 0 */
+/* UCB2IFG[UCSTTIFG] Bits */
+//#define UCSTTIFG_OFS                                       ( 2)                  /* UCSTTIFG Offset */
+//#define UCSTTIFG                                           (0x0004)              /* START condition interrupt flag */
+/* UCB2IFG[UCSTPIFG] Bits */
+//#define UCSTPIFG_OFS                                       ( 3)                  /* UCSTPIFG Offset */
+//#define UCSTPIFG                                           (0x0008)              /* STOP condition interrupt flag */
+/* UCB2IFG[UCALIFG] Bits */
+//#define UCALIFG_OFS                                        ( 4)                  /* UCALIFG Offset */
+//#define UCALIFG                                            (0x0010)              /* Arbitration lost interrupt flag */
+/* UCB2IFG[UCNACKIFG] Bits */
+//#define UCNACKIFG_OFS                                      ( 5)                  /* UCNACKIFG Offset */
+//#define UCNACKIFG                                          (0x0020)              /* Not-acknowledge received interrupt flag */
+/* UCB2IFG[UCBCNTIFG] Bits */
+//#define UCBCNTIFG_OFS                                      ( 6)                  /* UCBCNTIFG Offset */
+//#define UCBCNTIFG                                          (0x0040)              /* Byte counter interrupt flag */
+/* UCB2IFG[UCCLTOIFG] Bits */
+//#define UCCLTOIFG_OFS                                      ( 7)                  /* UCCLTOIFG Offset */
+//#define UCCLTOIFG                                          (0x0080)              /* Clock low timeout interrupt flag */
+/* UCB2IFG[UCRXIFG1] Bits */
+//#define UCRXIFG1_OFS                                       ( 8)                  /* UCRXIFG1 Offset */
+//#define UCRXIFG1                                           (0x0100)              /* eUSCI_B receive interrupt flag 1 */
+/* UCB2IFG[UCTXIFG1] Bits */
+//#define UCTXIFG1_OFS                                       ( 9)                  /* UCTXIFG1 Offset */
+//#define UCTXIFG1                                           (0x0200)              /* eUSCI_B transmit interrupt flag 1 */
+/* UCB2IFG[UCRXIFG2] Bits */
+//#define UCRXIFG2_OFS                                       (10)                  /* UCRXIFG2 Offset */
+//#define UCRXIFG2                                           (0x0400)              /* eUSCI_B receive interrupt flag 2 */
+/* UCB2IFG[UCTXIFG2] Bits */
+//#define UCTXIFG2_OFS                                       (11)                  /* UCTXIFG2 Offset */
+//#define UCTXIFG2                                           (0x0800)              /* eUSCI_B transmit interrupt flag 2 */
+/* UCB2IFG[UCRXIFG3] Bits */
+//#define UCRXIFG3_OFS                                       (12)                  /* UCRXIFG3 Offset */
+//#define UCRXIFG3                                           (0x1000)              /* eUSCI_B receive interrupt flag 3 */
+/* UCB2IFG[UCTXIFG3] Bits */
+//#define UCTXIFG3_OFS                                       (13)                  /* UCTXIFG3 Offset */
+//#define UCTXIFG3                                           (0x2000)              /* eUSCI_B transmit interrupt flag 3 */
+/* UCB2IFG[UCBIT9IFG] Bits */
+//#define UCBIT9IFG_OFS                                      (14)                  /* UCBIT9IFG Offset */
+//#define UCBIT9IFG                                          (0x4000)              /* Bit position 9 interrupt flag */
+/* UCB2IFG_SPI[UCRXIFG] Bits */
+//#define UCRXIFG_OFS                                        ( 0)                  /* UCRXIFG Offset */
+//#define UCRXIFG                                            (0x0001)              /* Receive interrupt flag */
+/* UCB2IFG_SPI[UCTXIFG] Bits */
+//#define UCTXIFG_OFS                                        ( 1)                  /* UCTXIFG Offset */
+//#define UCTXIFG                                            (0x0002)              /* Transmit interrupt flag */
+
+
+//*****************************************************************************
+// EUSCI_B3 Bits
+//*****************************************************************************
+/* UCB3CTLW0[UCSWRST] Bits */
+//#define UCSWRST_OFS                                        ( 0)                  /* UCSWRST Offset */
+//#define UCSWRST                                            (0x0001)              /* Software reset enable */
+/* UCB3CTLW0[UCTXSTT] Bits */
+//#define UCTXSTT_OFS                                        ( 1)                  /* UCTXSTT Offset */
+//#define UCTXSTT                                            (0x0002)              /* Transmit START condition in master mode */
+/* UCB3CTLW0[UCTXSTP] Bits */
+//#define UCTXSTP_OFS                                        ( 2)                  /* UCTXSTP Offset */
+//#define UCTXSTP                                            (0x0004)              /* Transmit STOP condition in master mode */
+/* UCB3CTLW0[UCTXNACK] Bits */
+//#define UCTXNACK_OFS                                       ( 3)                  /* UCTXNACK Offset */
+//#define UCTXNACK                                           (0x0008)              /* Transmit a NACK */
+/* UCB3CTLW0[UCTR] Bits */
+//#define UCTR_OFS                                           ( 4)                  /* UCTR Offset */
+//#define UCTR                                               (0x0010)              /* Transmitter/receiver */
+/* UCB3CTLW0[UCTXACK] Bits */
+//#define UCTXACK_OFS                                        ( 5)                  /* UCTXACK Offset */
+//#define UCTXACK                                            (0x0020)              /* Transmit ACK condition in slave mode */
+/* UCB3CTLW0[UCSSEL] Bits */
+//#define UCSSEL_OFS                                         ( 6)                  /* UCSSEL Offset */
+//#define UCSSEL_M                                           (0x00c0)              /* eUSCI_B clock source select */
+//#define UCSSEL0                                            (0x0040)              /* eUSCI_B clock source select */
+//#define UCSSEL1                                            (0x0080)              /* eUSCI_B clock source select */
+//#define UCSSEL_0                                           (0x0000)              /* UCLKI */
+//#define UCSSEL_1                                           (0x0040)              /* ACLK */
+//#define UCSSEL_2                                           (0x0080)              /* SMCLK */
+//#define UCSSEL__UCLKI                                      (0x0000)              /* UCLKI */
+//#define UCSSEL__ACLK                                       (0x0040)              /* ACLK */
+//#define UCSSEL__SMCLK                                      (0x0080)              /* SMCLK */
+//#define UCSSEL_3                                           (0x00c0)              /* SMCLK */
+/* UCB3CTLW0[UCSYNC] Bits */
+//#define UCSYNC_OFS                                         ( 8)                  /* UCSYNC Offset */
+//#define UCSYNC                                             (0x0100)              /* Synchronous mode enable */
+/* UCB3CTLW0[UCMODE] Bits */
+//#define UCMODE_OFS                                         ( 9)                  /* UCMODE Offset */
+//#define UCMODE_M                                           (0x0600)              /* eUSCI_B mode */
+//#define UCMODE0                                            (0x0200)              /* eUSCI_B mode */
+//#define UCMODE1                                            (0x0400)              /* eUSCI_B mode */
+//#define UCMODE_0                                           (0x0000)              /* 3-pin SPI */
+//#define UCMODE_1                                           (0x0200)              /* 4-pin SPI (master or slave enabled if STE = 1) */
+//#define UCMODE_2                                           (0x0400)              /* 4-pin SPI (master or slave enabled if STE = 0) */
+//#define UCMODE_3                                           (0x0600)              /* I2C mode */
+/* UCB3CTLW0[UCMST] Bits */
+//#define UCMST_OFS                                          (11)                  /* UCMST Offset */
+//#define UCMST                                              (0x0800)              /* Master mode select */
+/* UCB3CTLW0[UCMM] Bits */
+//#define UCMM_OFS                                           (13)                  /* UCMM Offset */
+//#define UCMM                                               (0x2000)              /* Multi-master environment select */
+/* UCB3CTLW0[UCSLA10] Bits */
+//#define UCSLA10_OFS                                        (14)                  /* UCSLA10 Offset */
+//#define UCSLA10                                            (0x4000)              /* Slave addressing mode select */
+/* UCB3CTLW0[UCA10] Bits */
+//#define UCA10_OFS                                          (15)                  /* UCA10 Offset */
+//#define UCA10                                              (0x8000)              /* Own addressing mode select */
+/* UCB3CTLW0_SPI[UCSWRST] Bits */
+//#define UCSWRST_OFS                                        ( 0)                  /* UCSWRST Offset */
+//#define UCSWRST                                            (0x0001)              /* Software reset enable */
+/* UCB3CTLW0_SPI[UCSTEM] Bits */
+//#define UCSTEM_OFS                                         ( 1)                  /* UCSTEM Offset */
+//#define UCSTEM                                             (0x0002)              /* STE mode select in master mode. */
+/* UCB3CTLW0_SPI[UCSSEL] Bits */
+//#define UCSSEL_OFS                                         ( 6)                  /* UCSSEL Offset */
+//#define UCSSEL_M                                           (0x00c0)              /* eUSCI_B clock source select */
+//#define UCSSEL0                                            (0x0040)              /* eUSCI_B clock source select */
+//#define UCSSEL1                                            (0x0080)              /* eUSCI_B clock source select */
+//#define UCSSEL_1                                           (0x0040)              /* ACLK */
+//#define UCSSEL_2                                           (0x0080)              /* SMCLK */
+//#define UCSSEL_0                                           (0x0000)              /* Reserved */
+//#define UCSSEL__ACLK                                       (0x0040)              /* ACLK */
+//#define UCSSEL__SMCLK                                      (0x0080)              /* SMCLK */
+//#define UCSSEL_3                                           (0x00c0)              /* SMCLK */
+/* UCB3CTLW0_SPI[UCSYNC] Bits */
+//#define UCSYNC_OFS                                         ( 8)                  /* UCSYNC Offset */
+//#define UCSYNC                                             (0x0100)              /* Synchronous mode enable */
+/* UCB3CTLW0_SPI[UCMODE] Bits */
+//#define UCMODE_OFS                                         ( 9)                  /* UCMODE Offset */
+//#define UCMODE_M                                           (0x0600)              /* eUSCI mode */
+//#define UCMODE0                                            (0x0200)              /* eUSCI mode */
+//#define UCMODE1                                            (0x0400)              /* eUSCI mode */
+//#define UCMODE_0                                           (0x0000)              /* 3-pin SPI */
+//#define UCMODE_1                                           (0x0200)              /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */
+//#define UCMODE_2                                           (0x0400)              /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */
+//#define UCMODE_3                                           (0x0600)              /* I2C mode */
+/* UCB3CTLW0_SPI[UCMST] Bits */
+//#define UCMST_OFS                                          (11)                  /* UCMST Offset */
+//#define UCMST                                              (0x0800)              /* Master mode select */
+/* UCB3CTLW0_SPI[UC7BIT] Bits */
+//#define UC7BIT_OFS                                         (12)                  /* UC7BIT Offset */
+//#define UC7BIT                                             (0x1000)              /* Character length */
+/* UCB3CTLW0_SPI[UCMSB] Bits */
+//#define UCMSB_OFS                                          (13)                  /* UCMSB Offset */
+//#define UCMSB                                              (0x2000)              /* MSB first select */
+/* UCB3CTLW0_SPI[UCCKPL] Bits */
+//#define UCCKPL_OFS                                         (14)                  /* UCCKPL Offset */
+//#define UCCKPL                                             (0x4000)              /* Clock polarity select */
+/* UCB3CTLW0_SPI[UCCKPH] Bits */
+//#define UCCKPH_OFS                                         (15)                  /* UCCKPH Offset */
+//#define UCCKPH                                             (0x8000)              /* Clock phase select */
+/* UCB3CTLW1[UCGLIT] Bits */
+//#define UCGLIT_OFS                                         ( 0)                  /* UCGLIT Offset */
+//#define UCGLIT_M                                           (0x0003)              /* Deglitch time */
+//#define UCGLIT0                                            (0x0001)              /* Deglitch time */
+//#define UCGLIT1                                            (0x0002)              /* Deglitch time */
+//#define UCGLIT_0                                           (0x0000)              /* 50 ns */
+//#define UCGLIT_1                                           (0x0001)              /* 25 ns */
+//#define UCGLIT_2                                           (0x0002)              /* 12.5 ns */
+//#define UCGLIT_3                                           (0x0003)              /* 6.25 ns */
+/* UCB3CTLW1[UCASTP] Bits */
+//#define UCASTP_OFS                                         ( 2)                  /* UCASTP Offset */
+//#define UCASTP_M                                           (0x000c)              /* Automatic STOP condition generation */
+//#define UCASTP0                                            (0x0004)              /* Automatic STOP condition generation */
+//#define UCASTP1                                            (0x0008)              /* Automatic STOP condition generation */
+//#define UCASTP_0                                           (0x0000)              /* No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */
+//#define UCASTP_1                                           (0x0004)              /* UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT */
+//#define UCASTP_2                                           (0x0008)              /* A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold */
+/* UCB3CTLW1[UCSWACK] Bits */
+//#define UCSWACK_OFS                                        ( 4)                  /* UCSWACK Offset */
+//#define UCSWACK                                            (0x0010)              /* SW or HW ACK control */
+/* UCB3CTLW1[UCSTPNACK] Bits */
+//#define UCSTPNACK_OFS                                      ( 5)                  /* UCSTPNACK Offset */
+//#define UCSTPNACK                                          (0x0020)              /* ACK all master bytes */
+/* UCB3CTLW1[UCCLTO] Bits */
+//#define UCCLTO_OFS                                         ( 6)                  /* UCCLTO Offset */
+//#define UCCLTO_M                                           (0x00c0)              /* Clock low timeout select */
+//#define UCCLTO0                                            (0x0040)              /* Clock low timeout select */
+//#define UCCLTO1                                            (0x0080)              /* Clock low timeout select */
+//#define UCCLTO_0                                           (0x0000)              /* Disable clock low timeout counter */
+//#define UCCLTO_1                                           (0x0040)              /* 135 000 SYSCLK cycles (approximately 28 ms) */
+//#define UCCLTO_2                                           (0x0080)              /* 150 000 SYSCLK cycles (approximately 31 ms) */
+//#define UCCLTO_3                                           (0x00c0)              /* 165 000 SYSCLK cycles (approximately 34 ms) */
+/* UCB3CTLW1[UCETXINT] Bits */
+//#define UCETXINT_OFS                                       ( 8)                  /* UCETXINT Offset */
+//#define UCETXINT                                           (0x0100)              /* Early UCTXIFG0 */
+/* UCB3STATW[UCBBUSY] Bits */
+//#define UCBBUSY_OFS                                        ( 4)                  /* UCBBUSY Offset */
+//#define UCBBUSY                                            (0x0010)              /* Bus busy */
+/* UCB3STATW[UCGC] Bits */
+//#define UCGC_OFS                                           ( 5)                  /* UCGC Offset */
+//#define UCGC                                               (0x0020)              /* General call address received */
+/* UCB3STATW[UCSCLLOW] Bits */
+//#define UCSCLLOW_OFS                                       ( 6)                  /* UCSCLLOW Offset */
+//#define UCSCLLOW                                           (0x0040)              /* SCL low */
+/* UCB3STATW[UCBCNT] Bits */
+//#define UCBCNT_OFS                                         ( 8)                  /* UCBCNT Offset */
+//#define UCBCNT_M                                           (0xff00)              /* Hardware byte counter value */
+/* UCB3STATW_SPI[UCBUSY] Bits */
+//#define UCBUSY_OFS                                         ( 0)                  /* UCBUSY Offset */
+//#define UCBUSY                                             (0x0001)              /* eUSCI_B busy */
+/* UCB3STATW_SPI[UCOE] Bits */
+//#define UCOE_OFS                                           ( 5)                  /* UCOE Offset */
+//#define UCOE                                               (0x0020)              /* Overrun error flag */
+/* UCB3STATW_SPI[UCFE] Bits */
+//#define UCFE_OFS                                           ( 6)                  /* UCFE Offset */
+//#define UCFE                                               (0x0040)              /* Framing error flag */
+/* UCB3STATW_SPI[UCLISTEN] Bits */
+//#define UCLISTEN_OFS                                       ( 7)                  /* UCLISTEN Offset */
+//#define UCLISTEN                                           (0x0080)              /* Listen enable */
+/* UCB3TBCNT[UCTBCNT] Bits */
+//#define UCTBCNT_OFS                                        ( 0)                  /* UCTBCNT Offset */
+//#define UCTBCNT_M                                          (0x00ff)              /* Byte counter threshold value */
+/* UCB3RXBUF[UCRXBUF] Bits */
+//#define UCRXBUF_OFS                                        ( 0)                  /* UCRXBUF Offset */
+//#define UCRXBUF_M                                          (0x00ff)              /* Receive data buffer */
+/* UCB3RXBUF_SPI[UCRXBUF] Bits */
+//#define UCRXBUF_OFS                                        ( 0)                  /* UCRXBUF Offset */
+//#define UCRXBUF_M                                          (0x00ff)              /* Receive data buffer */
+/* UCB3TXBUF[UCTXBUF] Bits */
+//#define UCTXBUF_OFS                                        ( 0)                  /* UCTXBUF Offset */
+//#define UCTXBUF_M                                          (0x00ff)              /* Transmit data buffer */
+/* UCB3TXBUF_SPI[UCTXBUF] Bits */
+//#define UCTXBUF_OFS                                        ( 0)                  /* UCTXBUF Offset */
+//#define UCTXBUF_M                                          (0x00ff)              /* Transmit data buffer */
+/* UCB3I2COA0[I2COA0] Bits */
+//#define I2COA0_OFS                                         ( 0)                  /* I2COA0 Offset */
+//#define I2COA0_M                                           (0x03ff)              /* I2C own address */
+/* UCB3I2COA0[UCOAEN] Bits */
+//#define UCOAEN_OFS                                         (10)                  /* UCOAEN Offset */
+//#define UCOAEN                                             (0x0400)              /* Own Address enable register */
+/* UCB3I2COA0[UCGCEN] Bits */
+//#define UCGCEN_OFS                                         (15)                  /* UCGCEN Offset */
+//#define UCGCEN                                             (0x8000)              /* General call response enable */
+/* UCB3I2COA1[I2COA1] Bits */
+//#define I2COA1_OFS                                         ( 0)                  /* I2COA1 Offset */
+//#define I2COA1_M                                           (0x03ff)              /* I2C own address */
+/* UCB3I2COA1[UCOAEN] Bits */
+//#define UCOAEN_OFS                                         (10)                  /* UCOAEN Offset */
+//#define UCOAEN                                             (0x0400)              /* Own Address enable register */
+/* UCB3I2COA2[I2COA2] Bits */
+//#define I2COA2_OFS                                         ( 0)                  /* I2COA2 Offset */
+//#define I2COA2_M                                           (0x03ff)              /* I2C own address */
+/* UCB3I2COA2[UCOAEN] Bits */
+//#define UCOAEN_OFS                                         (10)                  /* UCOAEN Offset */
+//#define UCOAEN                                             (0x0400)              /* Own Address enable register */
+/* UCB3I2COA3[I2COA3] Bits */
+//#define I2COA3_OFS                                         ( 0)                  /* I2COA3 Offset */
+//#define I2COA3_M                                           (0x03ff)              /* I2C own address */
+/* UCB3I2COA3[UCOAEN] Bits */
+//#define UCOAEN_OFS                                         (10)                  /* UCOAEN Offset */
+//#define UCOAEN                                             (0x0400)              /* Own Address enable register */
+/* UCB3ADDRX[ADDRX] Bits */
+//#define ADDRX_OFS                                          ( 0)                  /* ADDRX Offset */
+//#define ADDRX_M                                            (0x03ff)              /* Received Address Register */
+/* UCB3ADDMASK[ADDMASK] Bits */
+//#define ADDMASK_OFS                                        ( 0)                  /* ADDMASK Offset */
+//#define ADDMASK_M                                          (0x03ff)              /*  */
+/* UCB3I2CSA[I2CSA] Bits */
+//#define I2CSA_OFS                                          ( 0)                  /* I2CSA Offset */
+//#define I2CSA_M                                            (0x03ff)              /* I2C slave address */
+/* UCB3IE[UCRXIE0] Bits */
+//#define UCRXIE0_OFS                                        ( 0)                  /* UCRXIE0 Offset */
+//#define UCRXIE0                                            (0x0001)              /* Receive interrupt enable 0 */
+/* UCB3IE[UCTXIE0] Bits */
+//#define UCTXIE0_OFS                                        ( 1)                  /* UCTXIE0 Offset */
+//#define UCTXIE0                                            (0x0002)              /* Transmit interrupt enable 0 */
+/* UCB3IE[UCSTTIE] Bits */
+//#define UCSTTIE_OFS                                        ( 2)                  /* UCSTTIE Offset */
+//#define UCSTTIE                                            (0x0004)              /* START condition interrupt enable */
+/* UCB3IE[UCSTPIE] Bits */
+//#define UCSTPIE_OFS                                        ( 3)                  /* UCSTPIE Offset */
+//#define UCSTPIE                                            (0x0008)              /* STOP condition interrupt enable */
+/* UCB3IE[UCALIE] Bits */
+//#define UCALIE_OFS                                         ( 4)                  /* UCALIE Offset */
+//#define UCALIE                                             (0x0010)              /* Arbitration lost interrupt enable */
+/* UCB3IE[UCNACKIE] Bits */
+//#define UCNACKIE_OFS                                       ( 5)                  /* UCNACKIE Offset */
+//#define UCNACKIE                                           (0x0020)              /* Not-acknowledge interrupt enable */
+/* UCB3IE[UCBCNTIE] Bits */
+//#define UCBCNTIE_OFS                                       ( 6)                  /* UCBCNTIE Offset */
+//#define UCBCNTIE                                           (0x0040)              /* Byte counter interrupt enable */
+/* UCB3IE[UCCLTOIE] Bits */
+//#define UCCLTOIE_OFS                                       ( 7)                  /* UCCLTOIE Offset */
+//#define UCCLTOIE                                           (0x0080)              /* Clock low timeout interrupt enable */
+/* UCB3IE[UCRXIE1] Bits */
+//#define UCRXIE1_OFS                                        ( 8)                  /* UCRXIE1 Offset */
+//#define UCRXIE1                                            (0x0100)              /* Receive interrupt enable 1 */
+/* UCB3IE[UCTXIE1] Bits */
+//#define UCTXIE1_OFS                                        ( 9)                  /* UCTXIE1 Offset */
+//#define UCTXIE1                                            (0x0200)              /* Transmit interrupt enable 1 */
+/* UCB3IE[UCRXIE2] Bits */
+//#define UCRXIE2_OFS                                        (10)                  /* UCRXIE2 Offset */
+//#define UCRXIE2                                            (0x0400)              /* Receive interrupt enable 2 */
+/* UCB3IE[UCTXIE2] Bits */
+//#define UCTXIE2_OFS                                        (11)                  /* UCTXIE2 Offset */
+//#define UCTXIE2                                            (0x0800)              /* Transmit interrupt enable 2 */
+/* UCB3IE[UCRXIE3] Bits */
+//#define UCRXIE3_OFS                                        (12)                  /* UCRXIE3 Offset */
+//#define UCRXIE3                                            (0x1000)              /* Receive interrupt enable 3 */
+/* UCB3IE[UCTXIE3] Bits */
+//#define UCTXIE3_OFS                                        (13)                  /* UCTXIE3 Offset */
+//#define UCTXIE3                                            (0x2000)              /* Transmit interrupt enable 3 */
+/* UCB3IE[UCBIT9IE] Bits */
+//#define UCBIT9IE_OFS                                       (14)                  /* UCBIT9IE Offset */
+//#define UCBIT9IE                                           (0x4000)              /* Bit position 9 interrupt enable */
+/* UCB3IE_SPI[UCRXIE] Bits */
+//#define UCRXIE_OFS                                         ( 0)                  /* UCRXIE Offset */
+//#define UCRXIE                                             (0x0001)              /* Receive interrupt enable */
+/* UCB3IE_SPI[UCTXIE] Bits */
+//#define UCTXIE_OFS                                         ( 1)                  /* UCTXIE Offset */
+//#define UCTXIE                                             (0x0002)              /* Transmit interrupt enable */
+/* UCB3IFG[UCRXIFG0] Bits */
+//#define UCRXIFG0_OFS                                       ( 0)                  /* UCRXIFG0 Offset */
+//#define UCRXIFG0                                           (0x0001)              /* eUSCI_B receive interrupt flag 0 */
+/* UCB3IFG[UCTXIFG0] Bits */
+//#define UCTXIFG0_OFS                                       ( 1)                  /* UCTXIFG0 Offset */
+//#define UCTXIFG0                                           (0x0002)              /* eUSCI_B transmit interrupt flag 0 */
+/* UCB3IFG[UCSTTIFG] Bits */
+//#define UCSTTIFG_OFS                                       ( 2)                  /* UCSTTIFG Offset */
+//#define UCSTTIFG                                           (0x0004)              /* START condition interrupt flag */
+/* UCB3IFG[UCSTPIFG] Bits */
+//#define UCSTPIFG_OFS                                       ( 3)                  /* UCSTPIFG Offset */
+//#define UCSTPIFG                                           (0x0008)              /* STOP condition interrupt flag */
+/* UCB3IFG[UCALIFG] Bits */
+//#define UCALIFG_OFS                                        ( 4)                  /* UCALIFG Offset */
+//#define UCALIFG                                            (0x0010)              /* Arbitration lost interrupt flag */
+/* UCB3IFG[UCNACKIFG] Bits */
+//#define UCNACKIFG_OFS                                      ( 5)                  /* UCNACKIFG Offset */
+//#define UCNACKIFG                                          (0x0020)              /* Not-acknowledge received interrupt flag */
+/* UCB3IFG[UCBCNTIFG] Bits */
+//#define UCBCNTIFG_OFS                                      ( 6)                  /* UCBCNTIFG Offset */
+//#define UCBCNTIFG                                          (0x0040)              /* Byte counter interrupt flag */
+/* UCB3IFG[UCCLTOIFG] Bits */
+//#define UCCLTOIFG_OFS                                      ( 7)                  /* UCCLTOIFG Offset */
+//#define UCCLTOIFG                                          (0x0080)              /* Clock low timeout interrupt flag */
+/* UCB3IFG[UCRXIFG1] Bits */
+//#define UCRXIFG1_OFS                                       ( 8)                  /* UCRXIFG1 Offset */
+//#define UCRXIFG1                                           (0x0100)              /* eUSCI_B receive interrupt flag 1 */
+/* UCB3IFG[UCTXIFG1] Bits */
+//#define UCTXIFG1_OFS                                       ( 9)                  /* UCTXIFG1 Offset */
+//#define UCTXIFG1                                           (0x0200)              /* eUSCI_B transmit interrupt flag 1 */
+/* UCB3IFG[UCRXIFG2] Bits */
+//#define UCRXIFG2_OFS                                       (10)                  /* UCRXIFG2 Offset */
+//#define UCRXIFG2                                           (0x0400)              /* eUSCI_B receive interrupt flag 2 */
+/* UCB3IFG[UCTXIFG2] Bits */
+//#define UCTXIFG2_OFS                                       (11)                  /* UCTXIFG2 Offset */
+//#define UCTXIFG2                                           (0x0800)              /* eUSCI_B transmit interrupt flag 2 */
+/* UCB3IFG[UCRXIFG3] Bits */
+//#define UCRXIFG3_OFS                                       (12)                  /* UCRXIFG3 Offset */
+//#define UCRXIFG3                                           (0x1000)              /* eUSCI_B receive interrupt flag 3 */
+/* UCB3IFG[UCTXIFG3] Bits */
+//#define UCTXIFG3_OFS                                       (13)                  /* UCTXIFG3 Offset */
+//#define UCTXIFG3                                           (0x2000)              /* eUSCI_B transmit interrupt flag 3 */
+/* UCB3IFG[UCBIT9IFG] Bits */
+//#define UCBIT9IFG_OFS                                      (14)                  /* UCBIT9IFG Offset */
+//#define UCBIT9IFG                                          (0x4000)              /* Bit position 9 interrupt flag */
+/* UCB3IFG_SPI[UCRXIFG] Bits */
+//#define UCRXIFG_OFS                                        ( 0)                  /* UCRXIFG Offset */
+//#define UCRXIFG                                            (0x0001)              /* Receive interrupt flag */
+/* UCB3IFG_SPI[UCTXIFG] Bits */
+//#define UCTXIFG_OFS                                        ( 1)                  /* UCTXIFG Offset */
+//#define UCTXIFG                                            (0x0002)              /* Transmit interrupt flag */
+
+
+//*****************************************************************************
+// FLCTL Bits
+//*****************************************************************************
+/* FLCTL_POWER_STAT[FLCTL_POWER_STAT_PSTAT] Bits */
+#define FLCTL_POWER_STAT_PSTAT_OFS                         ( 0)                  /* PSTAT Offset */
+#define FLCTL_POWER_STAT_PSTAT_M                           (0x00000007)          /*  */
+#define FLCTL_POWER_STAT_PSTAT0                            (0x00000001)          /*  */
+#define FLCTL_POWER_STAT_PSTAT1                            (0x00000002)          /*  */
+#define FLCTL_POWER_STAT_PSTAT2                            (0x00000004)          /*  */
+#define FLCTL_POWER_STAT_PSTAT_0                           (0x00000000)          /* Flash IP in power-down mode */
+#define FLCTL_POWER_STAT_PSTAT_1                           (0x00000001)          /* Flash IP Vdd domain power-up in progress */
+#define FLCTL_POWER_STAT_PSTAT_2                           (0x00000002)          /* PSS LDO_GOOD, IREF_OK and VREF_OK check in progress */
+#define FLCTL_POWER_STAT_PSTAT_3                           (0x00000003)          /* Flash IP SAFE_LV check in progress */
+#define FLCTL_POWER_STAT_PSTAT_4                           (0x00000004)          /* Flash IP Active */
+#define FLCTL_POWER_STAT_PSTAT_5                           (0x00000005)          /* Flash IP Active in Low-Frequency Active and Low-Frequency LPM0 modes. */
+#define FLCTL_POWER_STAT_PSTAT_6                           (0x00000006)          /* Flash IP in Standby mode */
+#define FLCTL_POWER_STAT_PSTAT_7                           (0x00000007)          /* Flash IP in Current mirror boost state */
+/* FLCTL_POWER_STAT[FLCTL_POWER_STAT_LDOSTAT] Bits */
+#define FLCTL_POWER_STAT_LDOSTAT_OFS                       ( 3)                  /* LDOSTAT Offset */
+#define FLCTL_POWER_STAT_LDOSTAT                           (0x00000008)          /* PSS FLDO GOOD status */
+/* FLCTL_POWER_STAT[FLCTL_POWER_STAT_VREFSTAT] Bits */
+#define FLCTL_POWER_STAT_VREFSTAT_OFS                      ( 4)                  /* VREFSTAT Offset */
+#define FLCTL_POWER_STAT_VREFSTAT                          (0x00000010)          /* PSS VREF stable status */
+/* FLCTL_POWER_STAT[FLCTL_POWER_STAT_IREFSTAT] Bits */
+#define FLCTL_POWER_STAT_IREFSTAT_OFS                      ( 5)                  /* IREFSTAT Offset */
+#define FLCTL_POWER_STAT_IREFSTAT                          (0x00000020)          /* PSS IREF stable status */
+/* FLCTL_POWER_STAT[FLCTL_POWER_STAT_TRIMSTAT] Bits */
+#define FLCTL_POWER_STAT_TRIMSTAT_OFS                      ( 6)                  /* TRIMSTAT Offset */
+#define FLCTL_POWER_STAT_TRIMSTAT                          (0x00000040)          /* PSS trim done status */
+/* FLCTL_POWER_STAT[FLCTL_POWER_STAT_RD_2T] Bits */
+#define FLCTL_POWER_STAT_RD_2T_OFS                         ( 7)                  /* RD_2T Offset */
+#define FLCTL_POWER_STAT_RD_2T                             (0x00000080)          /* Indicates if Flash is being accessed in 2T mode */
+/* FLCTL_BANK0_RDCTL[FLCTL_BANK0_RDCTL_RD_MODE] Bits */
+#define FLCTL_BANK0_RDCTL_RD_MODE_OFS                      ( 0)                  /* RD_MODE Offset */
+#define FLCTL_BANK0_RDCTL_RD_MODE_M                        (0x0000000f)          /* Flash read mode control setting for Bank 0 */
+#define FLCTL_BANK0_RDCTL_RD_MODE0                         (0x00000001)          /* Flash read mode control setting for Bank 0 */
+#define FLCTL_BANK0_RDCTL_RD_MODE1                         (0x00000002)          /* Flash read mode control setting for Bank 0 */
+#define FLCTL_BANK0_RDCTL_RD_MODE2                         (0x00000004)          /* Flash read mode control setting for Bank 0 */
+#define FLCTL_BANK0_RDCTL_RD_MODE3                         (0x00000008)          /* Flash read mode control setting for Bank 0 */
+#define FLCTL_BANK0_RDCTL_RD_MODE_0                        (0x00000000)          /* Normal read mode */
+#define FLCTL_BANK0_RDCTL_RD_MODE_1                        (0x00000001)          /* Read Margin 0 */
+#define FLCTL_BANK0_RDCTL_RD_MODE_2                        (0x00000002)          /* Read Margin 1 */
+#define FLCTL_BANK0_RDCTL_RD_MODE_3                        (0x00000003)          /* Program Verify */
+#define FLCTL_BANK0_RDCTL_RD_MODE_4                        (0x00000004)          /* Erase Verify */
+#define FLCTL_BANK0_RDCTL_RD_MODE_5                        (0x00000005)          /* Leakage Verify */
+#define FLCTL_BANK0_RDCTL_RD_MODE_9                        (0x00000009)          /* Read Margin 0B */
+#define FLCTL_BANK0_RDCTL_RD_MODE_10                       (0x0000000a)          /* Read Margin 1B */
+/* FLCTL_BANK0_RDCTL[FLCTL_BANK0_RDCTL_BUFI] Bits */
+#define FLCTL_BANK0_RDCTL_BUFI_OFS                         ( 4)                  /* BUFI Offset */
+#define FLCTL_BANK0_RDCTL_BUFI                             (0x00000010)          /* Enables read buffering feature for instruction fetches to this Bank */
+/* FLCTL_BANK0_RDCTL[FLCTL_BANK0_RDCTL_BUFD] Bits */
+#define FLCTL_BANK0_RDCTL_BUFD_OFS                         ( 5)                  /* BUFD Offset */
+#define FLCTL_BANK0_RDCTL_BUFD                             (0x00000020)          /* Enables read buffering feature for data reads to this Bank */
+/* FLCTL_BANK0_RDCTL[FLCTL_BANK0_RDCTL_WAIT] Bits */
+#define FLCTL_BANK0_RDCTL_WAIT_OFS                         (12)                  /* WAIT Offset */
+#define FLCTL_BANK0_RDCTL_WAIT_M                           (0x0000f000)          /* Number of wait states for read */
+#define FLCTL_BANK0_RDCTL_WAIT0                            (0x00001000)          /* Number of wait states for read */
+#define FLCTL_BANK0_RDCTL_WAIT1                            (0x00002000)          /* Number of wait states for read */
+#define FLCTL_BANK0_RDCTL_WAIT2                            (0x00004000)          /* Number of wait states for read */
+#define FLCTL_BANK0_RDCTL_WAIT3                            (0x00008000)          /* Number of wait states for read */
+#define FLCTL_BANK0_RDCTL_WAIT_0                           (0x00000000)          /* 0 wait states */
+#define FLCTL_BANK0_RDCTL_WAIT_1                           (0x00001000)          /* 1 wait states */
+#define FLCTL_BANK0_RDCTL_WAIT_2                           (0x00002000)          /* 2 wait states */
+#define FLCTL_BANK0_RDCTL_WAIT_3                           (0x00003000)          /* 3 wait states */
+#define FLCTL_BANK0_RDCTL_WAIT_4                           (0x00004000)          /* 4 wait states */
+#define FLCTL_BANK0_RDCTL_WAIT_5                           (0x00005000)          /* 5 wait states */
+#define FLCTL_BANK0_RDCTL_WAIT_6                           (0x00006000)          /* 6 wait states */
+#define FLCTL_BANK0_RDCTL_WAIT_7                           (0x00007000)          /* 7 wait states */
+#define FLCTL_BANK0_RDCTL_WAIT_8                           (0x00008000)          /* 8 wait states */
+#define FLCTL_BANK0_RDCTL_WAIT_9                           (0x00009000)          /* 9 wait states */
+#define FLCTL_BANK0_RDCTL_WAIT_10                          (0x0000a000)          /* 10 wait states */
+#define FLCTL_BANK0_RDCTL_WAIT_11                          (0x0000b000)          /* 11 wait states */
+#define FLCTL_BANK0_RDCTL_WAIT_12                          (0x0000c000)          /* 12 wait states */
+#define FLCTL_BANK0_RDCTL_WAIT_13                          (0x0000d000)          /* 13 wait states */
+#define FLCTL_BANK0_RDCTL_WAIT_14                          (0x0000e000)          /* 14 wait states */
+#define FLCTL_BANK0_RDCTL_WAIT_15                          (0x0000f000)          /* 15 wait states */
+/* FLCTL_BANK0_RDCTL[FLCTL_BANK0_RDCTL_RD_MODE_STATUS] Bits */
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_OFS               (16)                  /* RD_MODE_STATUS Offset */
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_M                 (0x000f0000)          /* Read mode */
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS0                  (0x00010000)          /* Read mode */
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS1                  (0x00020000)          /* Read mode */
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS2                  (0x00040000)          /* Read mode */
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS3                  (0x00080000)          /* Read mode */
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_0                 (0x00000000)          /* Normal read mode */
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_1                 (0x00010000)          /* Read Margin 0 */
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_2                 (0x00020000)          /* Read Margin 1 */
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_3                 (0x00030000)          /* Program Verify */
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_4                 (0x00040000)          /* Erase Verify */
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_5                 (0x00050000)          /* Leakage Verify */
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_9                 (0x00090000)          /* Read Margin 0B */
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_10                (0x000a0000)          /* Read Margin 1B */
+/* FLCTL_BANK1_RDCTL[FLCTL_BANK1_RDCTL_RD_MODE] Bits */
+#define FLCTL_BANK1_RDCTL_RD_MODE_OFS                      ( 0)                  /* RD_MODE Offset */
+#define FLCTL_BANK1_RDCTL_RD_MODE_M                        (0x0000000f)          /* Flash read mode control setting for Bank 0 */
+#define FLCTL_BANK1_RDCTL_RD_MODE0                         (0x00000001)          /* Flash read mode control setting for Bank 0 */
+#define FLCTL_BANK1_RDCTL_RD_MODE1                         (0x00000002)          /* Flash read mode control setting for Bank 0 */
+#define FLCTL_BANK1_RDCTL_RD_MODE2                         (0x00000004)          /* Flash read mode control setting for Bank 0 */
+#define FLCTL_BANK1_RDCTL_RD_MODE3                         (0x00000008)          /* Flash read mode control setting for Bank 0 */
+#define FLCTL_BANK1_RDCTL_RD_MODE_0                        (0x00000000)          /* Normal read mode */
+#define FLCTL_BANK1_RDCTL_RD_MODE_1                        (0x00000001)          /* Read Margin 0 */
+#define FLCTL_BANK1_RDCTL_RD_MODE_2                        (0x00000002)          /* Read Margin 1 */
+#define FLCTL_BANK1_RDCTL_RD_MODE_3                        (0x00000003)          /* Program Verify */
+#define FLCTL_BANK1_RDCTL_RD_MODE_4                        (0x00000004)          /* Erase Verify */
+#define FLCTL_BANK1_RDCTL_RD_MODE_5                        (0x00000005)          /* Leakage Verify */
+#define FLCTL_BANK1_RDCTL_RD_MODE_9                        (0x00000009)          /* Read Margin 0B */
+#define FLCTL_BANK1_RDCTL_RD_MODE_10                       (0x0000000a)          /* Read Margin 1B */
+/* FLCTL_BANK1_RDCTL[FLCTL_BANK1_RDCTL_BUFI] Bits */
+#define FLCTL_BANK1_RDCTL_BUFI_OFS                         ( 4)                  /* BUFI Offset */
+#define FLCTL_BANK1_RDCTL_BUFI                             (0x00000010)          /* Enables read buffering feature for instruction fetches to this Bank */
+/* FLCTL_BANK1_RDCTL[FLCTL_BANK1_RDCTL_BUFD] Bits */
+#define FLCTL_BANK1_RDCTL_BUFD_OFS                         ( 5)                  /* BUFD Offset */
+#define FLCTL_BANK1_RDCTL_BUFD                             (0x00000020)          /* Enables read buffering feature for data reads to this Bank */
+/* FLCTL_BANK1_RDCTL[FLCTL_BANK1_RDCTL_RD_MODE_STATUS] Bits */
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_OFS               (16)                  /* RD_MODE_STATUS Offset */
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_M                 (0x000f0000)          /* Read mode */
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS0                  (0x00010000)          /* Read mode */
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS1                  (0x00020000)          /* Read mode */
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS2                  (0x00040000)          /* Read mode */
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS3                  (0x00080000)          /* Read mode */
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_0                 (0x00000000)          /* Normal read mode */
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_1                 (0x00010000)          /* Read Margin 0 */
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_2                 (0x00020000)          /* Read Margin 1 */
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_3                 (0x00030000)          /* Program Verify */
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_4                 (0x00040000)          /* Erase Verify */
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_5                 (0x00050000)          /* Leakage Verify */
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_9                 (0x00090000)          /* Read Margin 0B */
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_10                (0x000a0000)          /* Read Margin 1B */
+/* FLCTL_BANK1_RDCTL[FLCTL_BANK1_RDCTL_WAIT] Bits */
+#define FLCTL_BANK1_RDCTL_WAIT_OFS                         (12)                  /* WAIT Offset */
+#define FLCTL_BANK1_RDCTL_WAIT_M                           (0x0000f000)          /* Number of wait states for read */
+#define FLCTL_BANK1_RDCTL_WAIT0                            (0x00001000)          /* Number of wait states for read */
+#define FLCTL_BANK1_RDCTL_WAIT1                            (0x00002000)          /* Number of wait states for read */
+#define FLCTL_BANK1_RDCTL_WAIT2                            (0x00004000)          /* Number of wait states for read */
+#define FLCTL_BANK1_RDCTL_WAIT3                            (0x00008000)          /* Number of wait states for read */
+#define FLCTL_BANK1_RDCTL_WAIT_0                           (0x00000000)          /* 0 wait states */
+#define FLCTL_BANK1_RDCTL_WAIT_1                           (0x00001000)          /* 1 wait states */
+#define FLCTL_BANK1_RDCTL_WAIT_2                           (0x00002000)          /* 2 wait states */
+#define FLCTL_BANK1_RDCTL_WAIT_3                           (0x00003000)          /* 3 wait states */
+#define FLCTL_BANK1_RDCTL_WAIT_4                           (0x00004000)          /* 4 wait states */
+#define FLCTL_BANK1_RDCTL_WAIT_5                           (0x00005000)          /* 5 wait states */
+#define FLCTL_BANK1_RDCTL_WAIT_6                           (0x00006000)          /* 6 wait states */
+#define FLCTL_BANK1_RDCTL_WAIT_7                           (0x00007000)          /* 7 wait states */
+#define FLCTL_BANK1_RDCTL_WAIT_8                           (0x00008000)          /* 8 wait states */
+#define FLCTL_BANK1_RDCTL_WAIT_9                           (0x00009000)          /* 9 wait states */
+#define FLCTL_BANK1_RDCTL_WAIT_10                          (0x0000a000)          /* 10 wait states */
+#define FLCTL_BANK1_RDCTL_WAIT_11                          (0x0000b000)          /* 11 wait states */
+#define FLCTL_BANK1_RDCTL_WAIT_12                          (0x0000c000)          /* 12 wait states */
+#define FLCTL_BANK1_RDCTL_WAIT_13                          (0x0000d000)          /* 13 wait states */
+#define FLCTL_BANK1_RDCTL_WAIT_14                          (0x0000e000)          /* 14 wait states */
+#define FLCTL_BANK1_RDCTL_WAIT_15                          (0x0000f000)          /* 15 wait states */
+/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_START] Bits */
+#define FLCTL_RDBRST_CTLSTAT_START_OFS                     ( 0)                  /* START Offset */
+#define FLCTL_RDBRST_CTLSTAT_START                         (0x00000001)          /* Start of burst/compare operation */
+/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_MEM_TYPE] Bits */
+#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_OFS                  ( 1)                  /* MEM_TYPE Offset */
+#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_M                    (0x00000006)          /* Type of memory that burst is carried out on */
+#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE0                     (0x00000002)          /* Type of memory that burst is carried out on */
+#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE1                     (0x00000004)          /* Type of memory that burst is carried out on */
+#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_0                    (0x00000000)          /* Main Memory */
+#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_1                    (0x00000002)          /* Information Memory */
+#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_2                    (0x00000004)          /* Reserved */
+#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_3                    (0x00000006)          /* Engineering Memory */
+/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_STOP_FAIL] Bits */
+#define FLCTL_RDBRST_CTLSTAT_STOP_FAIL_OFS                 ( 3)                  /* STOP_FAIL Offset */
+#define FLCTL_RDBRST_CTLSTAT_STOP_FAIL                     (0x00000008)          /* Terminate burst/compare operation */
+/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_DATA_CMP] Bits */
+#define FLCTL_RDBRST_CTLSTAT_DATA_CMP_OFS                  ( 4)                  /* DATA_CMP Offset */
+#define FLCTL_RDBRST_CTLSTAT_DATA_CMP                      (0x00000010)          /* Data pattern used for comparison against memory read data */
+/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_TEST_EN] Bits */
+#define FLCTL_RDBRST_CTLSTAT_TEST_EN_OFS                   ( 6)                  /* TEST_EN Offset */
+#define FLCTL_RDBRST_CTLSTAT_TEST_EN                       (0x00000040)          /* Enable comparison against test data compare registers */
+/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_BRST_STAT] Bits */
+#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_OFS                 (16)                  /* BRST_STAT Offset */
+#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_M                   (0x00030000)          /* Status of Burst/Compare operation */
+#define FLCTL_RDBRST_CTLSTAT_BRST_STAT0                    (0x00010000)          /* Status of Burst/Compare operation */
+#define FLCTL_RDBRST_CTLSTAT_BRST_STAT1                    (0x00020000)          /* Status of Burst/Compare operation */
+#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_0                   (0x00000000)          /* Idle */
+#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_1                   (0x00010000)          /* Burst/Compare START bit written, but operation pending */
+#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_2                   (0x00020000)          /* Burst/Compare in progress */
+#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_3                   (0x00030000)          /* Burst complete (status of completed burst remains in this state unless explicitly cleared by SW) */
+/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_CMP_ERR] Bits */
+#define FLCTL_RDBRST_CTLSTAT_CMP_ERR_OFS                   (18)                  /* CMP_ERR Offset */
+#define FLCTL_RDBRST_CTLSTAT_CMP_ERR                       (0x00040000)          /* Burst/Compare Operation encountered atleast one data */
+/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_ADDR_ERR] Bits */
+#define FLCTL_RDBRST_CTLSTAT_ADDR_ERR_OFS                  (19)                  /* ADDR_ERR Offset */
+#define FLCTL_RDBRST_CTLSTAT_ADDR_ERR                      (0x00080000)          /* Burst/Compare Operation was terminated due to access to */
+/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_CLR_STAT] Bits */
+#define FLCTL_RDBRST_CTLSTAT_CLR_STAT_OFS                  (23)                  /* CLR_STAT Offset */
+#define FLCTL_RDBRST_CTLSTAT_CLR_STAT                      (0x00800000)          /* Clear status bits 19-16 of this register */
+/* FLCTL_RDBRST_STARTADDR[FLCTL_RDBRST_STARTADDR_START_ADDRESS] Bits */
+#define FLCTL_RDBRST_STARTADDR_START_ADDRESS_OFS           ( 0)                  /* START_ADDRESS Offset */
+#define FLCTL_RDBRST_STARTADDR_START_ADDRESS_M             (0x001fffff)          /* Start Address of Burst Operation */
+/* FLCTL_RDBRST_LEN[FLCTL_RDBRST_LEN_BURST_LENGTH] Bits */
+#define FLCTL_RDBRST_LEN_BURST_LENGTH_OFS                  ( 0)                  /* BURST_LENGTH Offset */
+#define FLCTL_RDBRST_LEN_BURST_LENGTH_M                    (0x001fffff)          /* Length of Burst Operation */
+/* FLCTL_RDBRST_FAILADDR[FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS] Bits */
+#define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_OFS             ( 0)                  /* FAIL_ADDRESS Offset */
+#define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_M               (0x001fffff)          /* Reflects address of last failed compare */
+/* FLCTL_RDBRST_FAILCNT[FLCTL_RDBRST_FAILCNT_FAIL_COUNT] Bits */
+#define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_OFS                ( 0)                  /* FAIL_COUNT Offset */
+#define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_M                  (0x0001ffff)          /* Number of failures encountered in burst operation */
+/* FLCTL_PRG_CTLSTAT[FLCTL_PRG_CTLSTAT_ENABLE] Bits */
+#define FLCTL_PRG_CTLSTAT_ENABLE_OFS                       ( 0)                  /* ENABLE Offset */
+#define FLCTL_PRG_CTLSTAT_ENABLE                           (0x00000001)          /* Master control for all word program operations */
+/* FLCTL_PRG_CTLSTAT[FLCTL_PRG_CTLSTAT_MODE] Bits */
+#define FLCTL_PRG_CTLSTAT_MODE_OFS                         ( 1)                  /* MODE Offset */
+#define FLCTL_PRG_CTLSTAT_MODE                             (0x00000002)          /* Write mode */
+/* FLCTL_PRG_CTLSTAT[FLCTL_PRG_CTLSTAT_VER_PRE] Bits */
+#define FLCTL_PRG_CTLSTAT_VER_PRE_OFS                      ( 2)                  /* VER_PRE Offset */
+#define FLCTL_PRG_CTLSTAT_VER_PRE                          (0x00000004)          /* Controls automatic pre program verify operations */
+/* FLCTL_PRG_CTLSTAT[FLCTL_PRG_CTLSTAT_VER_PST] Bits */
+#define FLCTL_PRG_CTLSTAT_VER_PST_OFS                      ( 3)                  /* VER_PST Offset */
+#define FLCTL_PRG_CTLSTAT_VER_PST                          (0x00000008)          /* Controls automatic post program verify operations */
+/* FLCTL_PRG_CTLSTAT[FLCTL_PRG_CTLSTAT_STATUS] Bits */
+#define FLCTL_PRG_CTLSTAT_STATUS_OFS                       (16)                  /* STATUS Offset */
+#define FLCTL_PRG_CTLSTAT_STATUS_M                         (0x00030000)          /* Status of program operations in the Flash memory */
+#define FLCTL_PRG_CTLSTAT_STATUS0                          (0x00010000)          /* Status of program operations in the Flash memory */
+#define FLCTL_PRG_CTLSTAT_STATUS1                          (0x00020000)          /* Status of program operations in the Flash memory */
+#define FLCTL_PRG_CTLSTAT_STATUS_0                         (0x00000000)          /* Idle (no program operation currently active) */
+#define FLCTL_PRG_CTLSTAT_STATUS_1                         (0x00010000)          /* Single word program operation triggered, but pending */
+#define FLCTL_PRG_CTLSTAT_STATUS_2                         (0x00020000)          /* Single word program in progress */
+#define FLCTL_PRG_CTLSTAT_STATUS_3                         (0x00030000)          /* Reserved (Idle) */
+/* FLCTL_PRG_CTLSTAT[FLCTL_PRG_CTLSTAT_BNK_ACT] Bits */
+#define FLCTL_PRG_CTLSTAT_BNK_ACT_OFS                      (18)                  /* BNK_ACT Offset */
+#define FLCTL_PRG_CTLSTAT_BNK_ACT                          (0x00040000)          /* Bank active */
+/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_START] Bits */
+#define FLCTL_PRGBRST_CTLSTAT_START_OFS                    ( 0)                  /* START Offset */
+#define FLCTL_PRGBRST_CTLSTAT_START                        (0x00000001)          /* Trigger start of burst program operation */
+/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_TYPE] Bits */
+#define FLCTL_PRGBRST_CTLSTAT_TYPE_OFS                     ( 1)                  /* TYPE Offset */
+#define FLCTL_PRGBRST_CTLSTAT_TYPE_M                       (0x00000006)          /* Type of memory that burst program is carried out on */
+#define FLCTL_PRGBRST_CTLSTAT_TYPE0                        (0x00000002)          /* Type of memory that burst program is carried out on */
+#define FLCTL_PRGBRST_CTLSTAT_TYPE1                        (0x00000004)          /* Type of memory that burst program is carried out on */
+#define FLCTL_PRGBRST_CTLSTAT_TYPE_0                       (0x00000000)          /* Main Memory */
+#define FLCTL_PRGBRST_CTLSTAT_TYPE_1                       (0x00000002)          /* Information Memory */
+#define FLCTL_PRGBRST_CTLSTAT_TYPE_2                       (0x00000004)          /* Reserved */
+#define FLCTL_PRGBRST_CTLSTAT_TYPE_3                       (0x00000006)          /* Engineering Memory */
+/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_LEN] Bits */
+#define FLCTL_PRGBRST_CTLSTAT_LEN_OFS                      ( 3)                  /* LEN Offset */
+#define FLCTL_PRGBRST_CTLSTAT_LEN_M                        (0x00000038)          /* Length of burst */
+#define FLCTL_PRGBRST_CTLSTAT_LEN0                         (0x00000008)          /* Length of burst */
+#define FLCTL_PRGBRST_CTLSTAT_LEN1                         (0x00000010)          /* Length of burst */
+#define FLCTL_PRGBRST_CTLSTAT_LEN2                         (0x00000020)          /* Length of burst */
+#define FLCTL_PRGBRST_CTLSTAT_LEN_0                        (0x00000000)          /* No burst operation */
+#define FLCTL_PRGBRST_CTLSTAT_LEN_1                        (0x00000008)          /* 1 word burst of 128 bits, starting with address in the FLCTL_PRGBRST_STARTADDR Register */
+#define FLCTL_PRGBRST_CTLSTAT_LEN_2                        (0x00000010)          /* 2*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register */
+#define FLCTL_PRGBRST_CTLSTAT_LEN_3                        (0x00000018)          /* 3*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register */
+#define FLCTL_PRGBRST_CTLSTAT_LEN_4                        (0x00000020)          /* 4*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register */
+/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_AUTO_PRE] Bits */
+#define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE_OFS                 ( 6)                  /* AUTO_PRE Offset */
+#define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE                     (0x00000040)          /* Auto-Verify operation before the Burst Program */
+/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_AUTO_PST] Bits */
+#define FLCTL_PRGBRST_CTLSTAT_AUTO_PST_OFS                 ( 7)                  /* AUTO_PST Offset */
+#define FLCTL_PRGBRST_CTLSTAT_AUTO_PST                     (0x00000080)          /* Auto-Verify operation after the Burst Program */
+/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_BURST_STATUS] Bits */
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_OFS             (16)                  /* BURST_STATUS Offset */
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_M               (0x00070000)          /* Status of a Burst Operation */
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS0                (0x00010000)          /* Status of a Burst Operation */
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS1                (0x00020000)          /* Status of a Burst Operation */
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS2                (0x00040000)          /* Status of a Burst Operation */
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_0               (0x00000000)          /* Idle (Burst not active) */
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_1               (0x00010000)          /* Burst program started but pending */
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_2               (0x00020000)          /* Burst active, with 1st 128 bit word being written into Flash */
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_3               (0x00030000)          /* Burst active, with 2nd 128 bit word being written into Flash */
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_4               (0x00040000)          /* Burst active, with 3rd 128 bit word being written into Flash */
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_5               (0x00050000)          /* Burst active, with 4th 128 bit word being written into Flash */
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_6               (0x00060000)          /* Reserved (Idle) */
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_7               (0x00070000)          /* Burst Complete (status of completed burst remains in this state unless explicitly cleared by SW) */
+/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_PRE_ERR] Bits */
+#define FLCTL_PRGBRST_CTLSTAT_PRE_ERR_OFS                  (19)                  /* PRE_ERR Offset */
+#define FLCTL_PRGBRST_CTLSTAT_PRE_ERR                      (0x00080000)          /* Burst Operation encountered preprogram auto-verify errors */
+/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_PST_ERR] Bits */
+#define FLCTL_PRGBRST_CTLSTAT_PST_ERR_OFS                  (20)                  /* PST_ERR Offset */
+#define FLCTL_PRGBRST_CTLSTAT_PST_ERR                      (0x00100000)          /* Burst Operation encountered postprogram auto-verify errors */
+/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_ADDR_ERR] Bits */
+#define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR_OFS                 (21)                  /* ADDR_ERR Offset */
+#define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR                     (0x00200000)          /* Burst Operation was terminated due to attempted program of reserved memory */
+/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_CLR_STAT] Bits */
+#define FLCTL_PRGBRST_CTLSTAT_CLR_STAT_OFS                 (23)                  /* CLR_STAT Offset */
+#define FLCTL_PRGBRST_CTLSTAT_CLR_STAT                     (0x00800000)          /* Clear status bits 21-16 of this register */
+/* FLCTL_PRGBRST_STARTADDR[FLCTL_PRGBRST_STARTADDR_START_ADDRESS] Bits */
+#define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_OFS          ( 0)                  /* START_ADDRESS Offset */
+#define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_M            (0x003fffff)          /* Start Address of Program Burst Operation */
+/* FLCTL_ERASE_CTLSTAT[FLCTL_ERASE_CTLSTAT_START] Bits */
+#define FLCTL_ERASE_CTLSTAT_START_OFS                      ( 0)                  /* START Offset */
+#define FLCTL_ERASE_CTLSTAT_START                          (0x00000001)          /* Start of Erase operation */
+/* FLCTL_ERASE_CTLSTAT[FLCTL_ERASE_CTLSTAT_MODE] Bits */
+#define FLCTL_ERASE_CTLSTAT_MODE_OFS                       ( 1)                  /* MODE Offset */
+#define FLCTL_ERASE_CTLSTAT_MODE                           (0x00000002)          /* Erase mode selected by application */
+/* FLCTL_ERASE_CTLSTAT[FLCTL_ERASE_CTLSTAT_TYPE] Bits */
+#define FLCTL_ERASE_CTLSTAT_TYPE_OFS                       ( 2)                  /* TYPE Offset */
+#define FLCTL_ERASE_CTLSTAT_TYPE_M                         (0x0000000c)          /* Type of memory that erase operation is carried out on */
+#define FLCTL_ERASE_CTLSTAT_TYPE0                          (0x00000004)          /* Type of memory that erase operation is carried out on */
+#define FLCTL_ERASE_CTLSTAT_TYPE1                          (0x00000008)          /* Type of memory that erase operation is carried out on */
+#define FLCTL_ERASE_CTLSTAT_TYPE_0                         (0x00000000)          /* Main Memory */
+#define FLCTL_ERASE_CTLSTAT_TYPE_1                         (0x00000004)          /* Information Memory */
+#define FLCTL_ERASE_CTLSTAT_TYPE_2                         (0x00000008)          /* Reserved */
+#define FLCTL_ERASE_CTLSTAT_TYPE_3                         (0x0000000c)          /* Engineering Memory */
+/* FLCTL_ERASE_CTLSTAT[FLCTL_ERASE_CTLSTAT_STATUS] Bits */
+#define FLCTL_ERASE_CTLSTAT_STATUS_OFS                     (16)                  /* STATUS Offset */
+#define FLCTL_ERASE_CTLSTAT_STATUS_M                       (0x00030000)          /* Status of erase operations in the Flash memory */
+#define FLCTL_ERASE_CTLSTAT_STATUS0                        (0x00010000)          /* Status of erase operations in the Flash memory */
+#define FLCTL_ERASE_CTLSTAT_STATUS1                        (0x00020000)          /* Status of erase operations in the Flash memory */
+#define FLCTL_ERASE_CTLSTAT_STATUS_0                       (0x00000000)          /* Idle (no program operation currently active) */
+#define FLCTL_ERASE_CTLSTAT_STATUS_1                       (0x00010000)          /* Erase operation triggered to START but pending */
+#define FLCTL_ERASE_CTLSTAT_STATUS_2                       (0x00020000)          /* Erase operation in progress */
+#define FLCTL_ERASE_CTLSTAT_STATUS_3                       (0x00030000)          /* Erase operation completed (status of completed erase remains in this state unless explicitly cleared by SW) */
+/* FLCTL_ERASE_CTLSTAT[FLCTL_ERASE_CTLSTAT_ADDR_ERR] Bits */
+#define FLCTL_ERASE_CTLSTAT_ADDR_ERR_OFS                   (18)                  /* ADDR_ERR Offset */
+#define FLCTL_ERASE_CTLSTAT_ADDR_ERR                       (0x00040000)          /* Erase Operation was terminated due to attempted erase of reserved memory address */
+/* FLCTL_ERASE_CTLSTAT[FLCTL_ERASE_CTLSTAT_CLR_STAT] Bits */
+#define FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS                   (19)                  /* CLR_STAT Offset */
+#define FLCTL_ERASE_CTLSTAT_CLR_STAT                       (0x00080000)          /* Clear status bits 18-16 of this register */
+/* FLCTL_ERASE_SECTADDR[FLCTL_ERASE_SECTADDR_SECT_ADDRESS] Bits */
+#define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_OFS              ( 0)                  /* SECT_ADDRESS Offset */
+#define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_M                (0x003fffff)          /* Address of Sector being Erased */
+/* FLCTL_BANK0_INFO_WEPROT[FLCTL_BANK0_INFO_WEPROT_PROT0] Bits */
+#define FLCTL_BANK0_INFO_WEPROT_PROT0_OFS                  ( 0)                  /* PROT0 Offset */
+#define FLCTL_BANK0_INFO_WEPROT_PROT0                      (0x00000001)          /* Protects Sector 0 from program or erase */
+/* FLCTL_BANK0_INFO_WEPROT[FLCTL_BANK0_INFO_WEPROT_PROT1] Bits */
+#define FLCTL_BANK0_INFO_WEPROT_PROT1_OFS                  ( 1)                  /* PROT1 Offset */
+#define FLCTL_BANK0_INFO_WEPROT_PROT1                      (0x00000002)          /* Protects Sector 1 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT0] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT0_OFS                  ( 0)                  /* PROT0 Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT0                      (0x00000001)          /* Protects Sector 0 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT1] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT1_OFS                  ( 1)                  /* PROT1 Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT1                      (0x00000002)          /* Protects Sector 1 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT2] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT2_OFS                  ( 2)                  /* PROT2 Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT2                      (0x00000004)          /* Protects Sector 2 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT3] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT3_OFS                  ( 3)                  /* PROT3 Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT3                      (0x00000008)          /* Protects Sector 3 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT4] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT4_OFS                  ( 4)                  /* PROT4 Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT4                      (0x00000010)          /* Protects Sector 4 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT5] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT5_OFS                  ( 5)                  /* PROT5 Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT5                      (0x00000020)          /* Protects Sector 5 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT6] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT6_OFS                  ( 6)                  /* PROT6 Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT6                      (0x00000040)          /* Protects Sector 6 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT7] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT7_OFS                  ( 7)                  /* PROT7 Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT7                      (0x00000080)          /* Protects Sector 7 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT8] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT8_OFS                  ( 8)                  /* PROT8 Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT8                      (0x00000100)          /* Protects Sector 8 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT9] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT9_OFS                  ( 9)                  /* PROT9 Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT9                      (0x00000200)          /* Protects Sector 9 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT10] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT10_OFS                 (10)                  /* PROT10 Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT10                     (0x00000400)          /* Protects Sector 10 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT11] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT11_OFS                 (11)                  /* PROT11 Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT11                     (0x00000800)          /* Protects Sector 11 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT12] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT12_OFS                 (12)                  /* PROT12 Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT12                     (0x00001000)          /* Protects Sector 12 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT13] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT13_OFS                 (13)                  /* PROT13 Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT13                     (0x00002000)          /* Protects Sector 13 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT14] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT14_OFS                 (14)                  /* PROT14 Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT14                     (0x00004000)          /* Protects Sector 14 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT15] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT15_OFS                 (15)                  /* PROT15 Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT15                     (0x00008000)          /* Protects Sector 15 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT16] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT16_OFS                 (16)                  /* PROT16 Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT16                     (0x00010000)          /* Protects Sector 16 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT17] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT17_OFS                 (17)                  /* PROT17 Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT17                     (0x00020000)          /* Protects Sector 17 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT18] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT18_OFS                 (18)                  /* PROT18 Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT18                     (0x00040000)          /* Protects Sector 18 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT19] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT19_OFS                 (19)                  /* PROT19 Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT19                     (0x00080000)          /* Protects Sector 19 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT20] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT20_OFS                 (20)                  /* PROT20 Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT20                     (0x00100000)          /* Protects Sector 20 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT21] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT21_OFS                 (21)                  /* PROT21 Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT21                     (0x00200000)          /* Protects Sector 21 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT22] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT22_OFS                 (22)                  /* PROT22 Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT22                     (0x00400000)          /* Protects Sector 22 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT23] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT23_OFS                 (23)                  /* PROT23 Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT23                     (0x00800000)          /* Protects Sector 23 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT24] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT24_OFS                 (24)                  /* PROT24 Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT24                     (0x01000000)          /* Protects Sector 24 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT25] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT25_OFS                 (25)                  /* PROT25 Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT25                     (0x02000000)          /* Protects Sector 25 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT26] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT26_OFS                 (26)                  /* PROT26 Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT26                     (0x04000000)          /* Protects Sector 26 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT27] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT27_OFS                 (27)                  /* PROT27 Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT27                     (0x08000000)          /* Protects Sector 27 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT28] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT28_OFS                 (28)                  /* PROT28 Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT28                     (0x10000000)          /* Protects Sector 28 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT29] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT29_OFS                 (29)                  /* PROT29 Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT29                     (0x20000000)          /* Protects Sector 29 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT30] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT30_OFS                 (30)                  /* PROT30 Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT30                     (0x40000000)          /* Protects Sector 30 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT31] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT31_OFS                 (31)                  /* PROT31 Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT31                     (0x80000000)          /* Protects Sector 31 from program or erase */
+/* FLCTL_BANK1_INFO_WEPROT[FLCTL_BANK1_INFO_WEPROT_PROT0] Bits */
+#define FLCTL_BANK1_INFO_WEPROT_PROT0_OFS                  ( 0)                  /* PROT0 Offset */
+#define FLCTL_BANK1_INFO_WEPROT_PROT0                      (0x00000001)          /* Protects Sector 0 from program or erase operations */
+/* FLCTL_BANK1_INFO_WEPROT[FLCTL_BANK1_INFO_WEPROT_PROT1] Bits */
+#define FLCTL_BANK1_INFO_WEPROT_PROT1_OFS                  ( 1)                  /* PROT1 Offset */
+#define FLCTL_BANK1_INFO_WEPROT_PROT1                      (0x00000002)          /* Protects Sector 1 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT0] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT0_OFS                  ( 0)                  /* PROT0 Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT0                      (0x00000001)          /* Protects Sector 0 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT1] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT1_OFS                  ( 1)                  /* PROT1 Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT1                      (0x00000002)          /* Protects Sector 1 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT2] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT2_OFS                  ( 2)                  /* PROT2 Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT2                      (0x00000004)          /* Protects Sector 2 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT3] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT3_OFS                  ( 3)                  /* PROT3 Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT3                      (0x00000008)          /* Protects Sector 3 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT4] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT4_OFS                  ( 4)                  /* PROT4 Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT4                      (0x00000010)          /* Protects Sector 4 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT5] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT5_OFS                  ( 5)                  /* PROT5 Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT5                      (0x00000020)          /* Protects Sector 5 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT6] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT6_OFS                  ( 6)                  /* PROT6 Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT6                      (0x00000040)          /* Protects Sector 6 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT7] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT7_OFS                  ( 7)                  /* PROT7 Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT7                      (0x00000080)          /* Protects Sector 7 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT8] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT8_OFS                  ( 8)                  /* PROT8 Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT8                      (0x00000100)          /* Protects Sector 8 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT9] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT9_OFS                  ( 9)                  /* PROT9 Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT9                      (0x00000200)          /* Protects Sector 9 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT10] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT10_OFS                 (10)                  /* PROT10 Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT10                     (0x00000400)          /* Protects Sector 10 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT11] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT11_OFS                 (11)                  /* PROT11 Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT11                     (0x00000800)          /* Protects Sector 11 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT12] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT12_OFS                 (12)                  /* PROT12 Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT12                     (0x00001000)          /* Protects Sector 12 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT13] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT13_OFS                 (13)                  /* PROT13 Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT13                     (0x00002000)          /* Protects Sector 13 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT14] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT14_OFS                 (14)                  /* PROT14 Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT14                     (0x00004000)          /* Protects Sector 14 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT15] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT15_OFS                 (15)                  /* PROT15 Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT15                     (0x00008000)          /* Protects Sector 15 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT16] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT16_OFS                 (16)                  /* PROT16 Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT16                     (0x00010000)          /* Protects Sector 16 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT17] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT17_OFS                 (17)                  /* PROT17 Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT17                     (0x00020000)          /* Protects Sector 17 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT18] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT18_OFS                 (18)                  /* PROT18 Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT18                     (0x00040000)          /* Protects Sector 18 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT19] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT19_OFS                 (19)                  /* PROT19 Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT19                     (0x00080000)          /* Protects Sector 19 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT20] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT20_OFS                 (20)                  /* PROT20 Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT20                     (0x00100000)          /* Protects Sector 20 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT21] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT21_OFS                 (21)                  /* PROT21 Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT21                     (0x00200000)          /* Protects Sector 21 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT22] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT22_OFS                 (22)                  /* PROT22 Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT22                     (0x00400000)          /* Protects Sector 22 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT23] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT23_OFS                 (23)                  /* PROT23 Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT23                     (0x00800000)          /* Protects Sector 23 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT24] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT24_OFS                 (24)                  /* PROT24 Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT24                     (0x01000000)          /* Protects Sector 24 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT25] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT25_OFS                 (25)                  /* PROT25 Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT25                     (0x02000000)          /* Protects Sector 25 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT26] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT26_OFS                 (26)                  /* PROT26 Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT26                     (0x04000000)          /* Protects Sector 26 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT27] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT27_OFS                 (27)                  /* PROT27 Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT27                     (0x08000000)          /* Protects Sector 27 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT28] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT28_OFS                 (28)                  /* PROT28 Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT28                     (0x10000000)          /* Protects Sector 28 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT29] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT29_OFS                 (29)                  /* PROT29 Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT29                     (0x20000000)          /* Protects Sector 29 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT30] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT30_OFS                 (30)                  /* PROT30 Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT30                     (0x40000000)          /* Protects Sector 30 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT31] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT31_OFS                 (31)                  /* PROT31 Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT31                     (0x80000000)          /* Protects Sector 31 from program or erase operations */
+/* FLCTL_BMRK_CTLSTAT[FLCTL_BMRK_CTLSTAT_I_BMRK] Bits */
+#define FLCTL_BMRK_CTLSTAT_I_BMRK_OFS                      ( 0)                  /* I_BMRK Offset */
+#define FLCTL_BMRK_CTLSTAT_I_BMRK                          (0x00000001)          /*  */
+/* FLCTL_BMRK_CTLSTAT[FLCTL_BMRK_CTLSTAT_D_BMRK] Bits */
+#define FLCTL_BMRK_CTLSTAT_D_BMRK_OFS                      ( 1)                  /* D_BMRK Offset */
+#define FLCTL_BMRK_CTLSTAT_D_BMRK                          (0x00000002)          /*  */
+/* FLCTL_BMRK_CTLSTAT[FLCTL_BMRK_CTLSTAT_CMP_EN] Bits */
+#define FLCTL_BMRK_CTLSTAT_CMP_EN_OFS                      ( 2)                  /* CMP_EN Offset */
+#define FLCTL_BMRK_CTLSTAT_CMP_EN                          (0x00000004)          /*  */
+/* FLCTL_BMRK_CTLSTAT[FLCTL_BMRK_CTLSTAT_CMP_SEL] Bits */
+#define FLCTL_BMRK_CTLSTAT_CMP_SEL_OFS                     ( 3)                  /* CMP_SEL Offset */
+#define FLCTL_BMRK_CTLSTAT_CMP_SEL                         (0x00000008)          /*  */
+/* FLCTL_IFG[FLCTL_IFG_RDBRST] Bits */
+#define FLCTL_IFG_RDBRST_OFS                               ( 0)                  /* RDBRST Offset */
+#define FLCTL_IFG_RDBRST                                   (0x00000001)          /*  */
+/* FLCTL_IFG[FLCTL_IFG_AVPRE] Bits */
+#define FLCTL_IFG_AVPRE_OFS                                ( 1)                  /* AVPRE Offset */
+#define FLCTL_IFG_AVPRE                                    (0x00000002)          /*  */
+/* FLCTL_IFG[FLCTL_IFG_AVPST] Bits */
+#define FLCTL_IFG_AVPST_OFS                                ( 2)                  /* AVPST Offset */
+#define FLCTL_IFG_AVPST                                    (0x00000004)          /*  */
+/* FLCTL_IFG[FLCTL_IFG_PRG] Bits */
+#define FLCTL_IFG_PRG_OFS                                  ( 3)                  /* PRG Offset */
+#define FLCTL_IFG_PRG                                      (0x00000008)          /*  */
+/* FLCTL_IFG[FLCTL_IFG_PRGB] Bits */
+#define FLCTL_IFG_PRGB_OFS                                 ( 4)                  /* PRGB Offset */
+#define FLCTL_IFG_PRGB                                     (0x00000010)          /*  */
+/* FLCTL_IFG[FLCTL_IFG_ERASE] Bits */
+#define FLCTL_IFG_ERASE_OFS                                ( 5)                  /* ERASE Offset */
+#define FLCTL_IFG_ERASE                                    (0x00000020)          /*  */
+/* FLCTL_IFG[FLCTL_IFG_BMRK] Bits */
+#define FLCTL_IFG_BMRK_OFS                                 ( 8)                  /* BMRK Offset */
+#define FLCTL_IFG_BMRK                                     (0x00000100)          /*  */
+/* FLCTL_IFG[FLCTL_IFG_PRG_ERR] Bits */
+#define FLCTL_IFG_PRG_ERR_OFS                              ( 9)                  /* PRG_ERR Offset */
+#define FLCTL_IFG_PRG_ERR                                  (0x00000200)          /*  */
+/* FLCTL_IE[FLCTL_IE_RDBRST] Bits */
+#define FLCTL_IE_RDBRST_OFS                                ( 0)                  /* RDBRST Offset */
+#define FLCTL_IE_RDBRST                                    (0x00000001)          /*  */
+/* FLCTL_IE[FLCTL_IE_AVPRE] Bits */
+#define FLCTL_IE_AVPRE_OFS                                 ( 1)                  /* AVPRE Offset */
+#define FLCTL_IE_AVPRE                                     (0x00000002)          /*  */
+/* FLCTL_IE[FLCTL_IE_AVPST] Bits */
+#define FLCTL_IE_AVPST_OFS                                 ( 2)                  /* AVPST Offset */
+#define FLCTL_IE_AVPST                                     (0x00000004)          /*  */
+/* FLCTL_IE[FLCTL_IE_PRG] Bits */
+#define FLCTL_IE_PRG_OFS                                   ( 3)                  /* PRG Offset */
+#define FLCTL_IE_PRG                                       (0x00000008)          /*  */
+/* FLCTL_IE[FLCTL_IE_PRGB] Bits */
+#define FLCTL_IE_PRGB_OFS                                  ( 4)                  /* PRGB Offset */
+#define FLCTL_IE_PRGB                                      (0x00000010)          /*  */
+/* FLCTL_IE[FLCTL_IE_ERASE] Bits */
+#define FLCTL_IE_ERASE_OFS                                 ( 5)                  /* ERASE Offset */
+#define FLCTL_IE_ERASE                                     (0x00000020)          /*  */
+/* FLCTL_IE[FLCTL_IE_BMRK] Bits */
+#define FLCTL_IE_BMRK_OFS                                  ( 8)                  /* BMRK Offset */
+#define FLCTL_IE_BMRK                                      (0x00000100)          /*  */
+/* FLCTL_IE[FLCTL_IE_PRG_ERR] Bits */
+#define FLCTL_IE_PRG_ERR_OFS                               ( 9)                  /* PRG_ERR Offset */
+#define FLCTL_IE_PRG_ERR                                   (0x00000200)          /*  */
+/* FLCTL_CLRIFG[FLCTL_CLRIFG_RDBRST] Bits */
+#define FLCTL_CLRIFG_RDBRST_OFS                            ( 0)                  /* RDBRST Offset */
+#define FLCTL_CLRIFG_RDBRST                                (0x00000001)          /*  */
+/* FLCTL_CLRIFG[FLCTL_CLRIFG_AVPRE] Bits */
+#define FLCTL_CLRIFG_AVPRE_OFS                             ( 1)                  /* AVPRE Offset */
+#define FLCTL_CLRIFG_AVPRE                                 (0x00000002)          /*  */
+/* FLCTL_CLRIFG[FLCTL_CLRIFG_AVPST] Bits */
+#define FLCTL_CLRIFG_AVPST_OFS                             ( 2)                  /* AVPST Offset */
+#define FLCTL_CLRIFG_AVPST                                 (0x00000004)          /*  */
+/* FLCTL_CLRIFG[FLCTL_CLRIFG_PRG] Bits */
+#define FLCTL_CLRIFG_PRG_OFS                               ( 3)                  /* PRG Offset */
+#define FLCTL_CLRIFG_PRG                                   (0x00000008)          /*  */
+/* FLCTL_CLRIFG[FLCTL_CLRIFG_PRGB] Bits */
+#define FLCTL_CLRIFG_PRGB_OFS                              ( 4)                  /* PRGB Offset */
+#define FLCTL_CLRIFG_PRGB                                  (0x00000010)          /*  */
+/* FLCTL_CLRIFG[FLCTL_CLRIFG_ERASE] Bits */
+#define FLCTL_CLRIFG_ERASE_OFS                             ( 5)                  /* ERASE Offset */
+#define FLCTL_CLRIFG_ERASE                                 (0x00000020)          /*  */
+/* FLCTL_CLRIFG[FLCTL_CLRIFG_BMRK] Bits */
+#define FLCTL_CLRIFG_BMRK_OFS                              ( 8)                  /* BMRK Offset */
+#define FLCTL_CLRIFG_BMRK                                  (0x00000100)          /*  */
+/* FLCTL_CLRIFG[FLCTL_CLRIFG_PRG_ERR] Bits */
+#define FLCTL_CLRIFG_PRG_ERR_OFS                           ( 9)                  /* PRG_ERR Offset */
+#define FLCTL_CLRIFG_PRG_ERR                               (0x00000200)          /*  */
+/* FLCTL_SETIFG[FLCTL_SETIFG_RDBRST] Bits */
+#define FLCTL_SETIFG_RDBRST_OFS                            ( 0)                  /* RDBRST Offset */
+#define FLCTL_SETIFG_RDBRST                                (0x00000001)          /*  */
+/* FLCTL_SETIFG[FLCTL_SETIFG_AVPRE] Bits */
+#define FLCTL_SETIFG_AVPRE_OFS                             ( 1)                  /* AVPRE Offset */
+#define FLCTL_SETIFG_AVPRE                                 (0x00000002)          /*  */
+/* FLCTL_SETIFG[FLCTL_SETIFG_AVPST] Bits */
+#define FLCTL_SETIFG_AVPST_OFS                             ( 2)                  /* AVPST Offset */
+#define FLCTL_SETIFG_AVPST                                 (0x00000004)          /*  */
+/* FLCTL_SETIFG[FLCTL_SETIFG_PRG] Bits */
+#define FLCTL_SETIFG_PRG_OFS                               ( 3)                  /* PRG Offset */
+#define FLCTL_SETIFG_PRG                                   (0x00000008)          /*  */
+/* FLCTL_SETIFG[FLCTL_SETIFG_PRGB] Bits */
+#define FLCTL_SETIFG_PRGB_OFS                              ( 4)                  /* PRGB Offset */
+#define FLCTL_SETIFG_PRGB                                  (0x00000010)          /*  */
+/* FLCTL_SETIFG[FLCTL_SETIFG_ERASE] Bits */
+#define FLCTL_SETIFG_ERASE_OFS                             ( 5)                  /* ERASE Offset */
+#define FLCTL_SETIFG_ERASE                                 (0x00000020)          /*  */
+/* FLCTL_SETIFG[FLCTL_SETIFG_BMRK] Bits */
+#define FLCTL_SETIFG_BMRK_OFS                              ( 8)                  /* BMRK Offset */
+#define FLCTL_SETIFG_BMRK                                  (0x00000100)          /*  */
+/* FLCTL_SETIFG[FLCTL_SETIFG_PRG_ERR] Bits */
+#define FLCTL_SETIFG_PRG_ERR_OFS                           ( 9)                  /* PRG_ERR Offset */
+#define FLCTL_SETIFG_PRG_ERR                               (0x00000200)          /*  */
+/* FLCTL_READ_TIMCTL[FLCTL_READ_TIMCTL_SETUP] Bits */
+#define FLCTL_READ_TIMCTL_SETUP_OFS                        ( 0)                  /* SETUP Offset */
+#define FLCTL_READ_TIMCTL_SETUP_M                          (0x000000ff)          /*  */
+/* FLCTL_READ_TIMCTL[FLCTL_READ_TIMCTL_HOLD] Bits */
+#define FLCTL_READ_TIMCTL_HOLD_OFS                         ( 8)                  /* HOLD Offset */
+#define FLCTL_READ_TIMCTL_HOLD_M                           (0x00000f00)          /*  */
+/* FLCTL_READ_TIMCTL[FLCTL_READ_TIMCTL_IREF_BOOST1] Bits */
+#define FLCTL_READ_TIMCTL_IREF_BOOST1_OFS                  (12)                  /* IREF_BOOST1 Offset */
+#define FLCTL_READ_TIMCTL_IREF_BOOST1_M                    (0x0000f000)          /*  */
+/* FLCTL_READ_TIMCTL[FLCTL_READ_TIMCTL_SETUP_LONG] Bits */
+#define FLCTL_READ_TIMCTL_SETUP_LONG_OFS                   (16)                  /* SETUP_LONG Offset */
+#define FLCTL_READ_TIMCTL_SETUP_LONG_M                     (0x00ff0000)          /*  */
+/* FLCTL_READMARGIN_TIMCTL[FLCTL_READMARGIN_TIMCTL_SETUP] Bits */
+#define FLCTL_READMARGIN_TIMCTL_SETUP_OFS                  ( 0)                  /* SETUP Offset */
+#define FLCTL_READMARGIN_TIMCTL_SETUP_M                    (0x000000ff)          /*  */
+/* FLCTL_READMARGIN_TIMCTL[FLCTL_READMARGIN_TIMCTL_HOLD] Bits */
+#define FLCTL_READMARGIN_TIMCTL_HOLD_OFS                   ( 8)                  /* HOLD Offset */
+#define FLCTL_READMARGIN_TIMCTL_HOLD_M                     (0x00000f00)          /*  */
+/* FLCTL_PRGVER_TIMCTL[FLCTL_PRGVER_TIMCTL_SETUP] Bits */
+#define FLCTL_PRGVER_TIMCTL_SETUP_OFS                      ( 0)                  /* SETUP Offset */
+#define FLCTL_PRGVER_TIMCTL_SETUP_M                        (0x000000ff)          /*  */
+/* FLCTL_PRGVER_TIMCTL[FLCTL_PRGVER_TIMCTL_ACTIVE] Bits */
+#define FLCTL_PRGVER_TIMCTL_ACTIVE_OFS                     ( 8)                  /* ACTIVE Offset */
+#define FLCTL_PRGVER_TIMCTL_ACTIVE_M                       (0x00000f00)          /*  */
+/* FLCTL_PRGVER_TIMCTL[FLCTL_PRGVER_TIMCTL_HOLD] Bits */
+#define FLCTL_PRGVER_TIMCTL_HOLD_OFS                       (12)                  /* HOLD Offset */
+#define FLCTL_PRGVER_TIMCTL_HOLD_M                         (0x0000f000)          /*  */
+/* FLCTL_ERSVER_TIMCTL[FLCTL_ERSVER_TIMCTL_SETUP] Bits */
+#define FLCTL_ERSVER_TIMCTL_SETUP_OFS                      ( 0)                  /* SETUP Offset */
+#define FLCTL_ERSVER_TIMCTL_SETUP_M                        (0x000000ff)          /*  */
+/* FLCTL_ERSVER_TIMCTL[FLCTL_ERSVER_TIMCTL_HOLD] Bits */
+#define FLCTL_ERSVER_TIMCTL_HOLD_OFS                       ( 8)                  /* HOLD Offset */
+#define FLCTL_ERSVER_TIMCTL_HOLD_M                         (0x00000f00)          /*  */
+/* FLCTL_LKGVER_TIMCTL[FLCTL_LKGVER_TIMCTL_SETUP] Bits */
+#define FLCTL_LKGVER_TIMCTL_SETUP_OFS                      ( 0)                  /* SETUP Offset */
+#define FLCTL_LKGVER_TIMCTL_SETUP_M                        (0x000000ff)          /*  */
+/* FLCTL_LKGVER_TIMCTL[FLCTL_LKGVER_TIMCTL_HOLD] Bits */
+#define FLCTL_LKGVER_TIMCTL_HOLD_OFS                       ( 8)                  /* HOLD Offset */
+#define FLCTL_LKGVER_TIMCTL_HOLD_M                         (0x00000f00)          /*  */
+/* FLCTL_PROGRAM_TIMCTL[FLCTL_PROGRAM_TIMCTL_SETUP] Bits */
+#define FLCTL_PROGRAM_TIMCTL_SETUP_OFS                     ( 0)                  /* SETUP Offset */
+#define FLCTL_PROGRAM_TIMCTL_SETUP_M                       (0x000000ff)          /*  */
+/* FLCTL_PROGRAM_TIMCTL[FLCTL_PROGRAM_TIMCTL_ACTIVE] Bits */
+#define FLCTL_PROGRAM_TIMCTL_ACTIVE_OFS                    ( 8)                  /* ACTIVE Offset */
+#define FLCTL_PROGRAM_TIMCTL_ACTIVE_M                      (0x0fffff00)          /*  */
+/* FLCTL_PROGRAM_TIMCTL[FLCTL_PROGRAM_TIMCTL_HOLD] Bits */
+#define FLCTL_PROGRAM_TIMCTL_HOLD_OFS                      (28)                  /* HOLD Offset */
+#define FLCTL_PROGRAM_TIMCTL_HOLD_M                        (0xf0000000)          /*  */
+/* FLCTL_ERASE_TIMCTL[FLCTL_ERASE_TIMCTL_SETUP] Bits */
+#define FLCTL_ERASE_TIMCTL_SETUP_OFS                       ( 0)                  /* SETUP Offset */
+#define FLCTL_ERASE_TIMCTL_SETUP_M                         (0x000000ff)          /*  */
+/* FLCTL_ERASE_TIMCTL[FLCTL_ERASE_TIMCTL_ACTIVE] Bits */
+#define FLCTL_ERASE_TIMCTL_ACTIVE_OFS                      ( 8)                  /* ACTIVE Offset */
+#define FLCTL_ERASE_TIMCTL_ACTIVE_M                        (0x0fffff00)          /*  */
+/* FLCTL_ERASE_TIMCTL[FLCTL_ERASE_TIMCTL_HOLD] Bits */
+#define FLCTL_ERASE_TIMCTL_HOLD_OFS                        (28)                  /* HOLD Offset */
+#define FLCTL_ERASE_TIMCTL_HOLD_M                          (0xf0000000)          /*  */
+/* FLCTL_MASSERASE_TIMCTL[FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE] Bits */
+#define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_OFS            ( 0)                  /* BOOST_ACTIVE Offset */
+#define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_M              (0x000000ff)          /*  */
+/* FLCTL_MASSERASE_TIMCTL[FLCTL_MASSERASE_TIMCTL_BOOST_HOLD] Bits */
+#define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_OFS              ( 8)                  /* BOOST_HOLD Offset */
+#define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_M                (0x0000ff00)          /*  */
+/* FLCTL_BURSTPRG_TIMCTL[FLCTL_BURSTPRG_TIMCTL_ACTIVE] Bits */
+#define FLCTL_BURSTPRG_TIMCTL_ACTIVE_OFS                   ( 8)                  /* ACTIVE Offset */
+#define FLCTL_BURSTPRG_TIMCTL_ACTIVE_M                     (0x0fffff00)          /*  */
+
+
+//*****************************************************************************
+// FPB Bits
+//*****************************************************************************
+/* FPB_FP_CTRL[FPB_FP_CTRL_ENABLE] Bits */
+#define FPB_FP_CTRL_ENABLE_OFS                             ( 0)                  /* ENABLE Offset */
+#define FPB_FP_CTRL_ENABLE                                 (0x00000001)          /*  */
+/* FPB_FP_CTRL[FPB_FP_CTRL_KEY] Bits */
+#define FPB_FP_CTRL_KEY_OFS                                ( 1)                  /* KEY Offset */
+#define FPB_FP_CTRL_KEY                                    (0x00000002)          /*  */
+/* FPB_FP_CTRL[FPB_FP_CTRL_NUM_CODE1] Bits */
+#define FPB_FP_CTRL_NUM_CODE1_OFS                          ( 4)                  /* NUM_CODE1 Offset */
+#define FPB_FP_CTRL_NUM_CODE1_M                            (0x000000f0)          /*  */
+#define FPB_FP_CTRL_NUM_CODE10                             (0x00000010)          /*  */
+#define FPB_FP_CTRL_NUM_CODE11                             (0x00000020)          /*  */
+#define FPB_FP_CTRL_NUM_CODE12                             (0x00000040)          /*  */
+#define FPB_FP_CTRL_NUM_CODE13                             (0x00000080)          /*  */
+#define FPB_FP_CTRL_NUM_CODE1_0                            (0x00000000)          /* no code slots */
+#define FPB_FP_CTRL_NUM_CODE1_2                            (0x00000020)          /* two code slots */
+#define FPB_FP_CTRL_NUM_CODE1_6                            (0x00000060)          /* six code slots */
+/* FPB_FP_CTRL[FPB_FP_CTRL_NUM_LIT] Bits */
+#define FPB_FP_CTRL_NUM_LIT_OFS                            ( 8)                  /* NUM_LIT Offset */
+#define FPB_FP_CTRL_NUM_LIT_M                              (0x00000f00)          /*  */
+#define FPB_FP_CTRL_NUM_LIT0                               (0x00000100)          /*  */
+#define FPB_FP_CTRL_NUM_LIT1                               (0x00000200)          /*  */
+#define FPB_FP_CTRL_NUM_LIT2                               (0x00000400)          /*  */
+#define FPB_FP_CTRL_NUM_LIT3                               (0x00000800)          /*  */
+#define FPB_FP_CTRL_NUM_LIT_0                              (0x00000000)          /* no literal slots */
+#define FPB_FP_CTRL_NUM_LIT_2                              (0x00000200)          /* two literal slots */
+/* FPB_FP_CTRL[FPB_FP_CTRL_NUM_CODE2] Bits */
+#define FPB_FP_CTRL_NUM_CODE2_OFS                          (12)                  /* NUM_CODE2 Offset */
+#define FPB_FP_CTRL_NUM_CODE2_M                            (0x00003000)          /*  */
+/* FPB_FP_REMAP[FPB_FP_REMAP_REMAP] Bits */
+#define FPB_FP_REMAP_REMAP_OFS                             ( 5)                  /* REMAP Offset */
+#define FPB_FP_REMAP_REMAP_M                               (0x1fffffe0)          /*  */
+/* FPB_FP_COMP0[FPB_FP_COMP0_ENABLE] Bits */
+#define FPB_FP_COMP0_ENABLE_OFS                            ( 0)                  /* ENABLE Offset */
+#define FPB_FP_COMP0_ENABLE                                (0x00000001)          /*  */
+/* FPB_FP_COMP0[FPB_FP_COMP0_COMP] Bits */
+#define FPB_FP_COMP0_COMP_OFS                              ( 2)                  /* COMP Offset */
+#define FPB_FP_COMP0_COMP_M                                (0x1ffffffc)          /*  */
+/* FPB_FP_COMP0[FPB_FP_COMP0_REPLACE] Bits */
+#define FPB_FP_COMP0_REPLACE_OFS                           (30)                  /* REPLACE Offset */
+#define FPB_FP_COMP0_REPLACE_M                             (0xc0000000)          /*  */
+#define FPB_FP_COMP0_REPLACE0                              (0x40000000)          /*  */
+#define FPB_FP_COMP0_REPLACE1                              (0x80000000)          /*  */
+#define FPB_FP_COMP0_REPLACE_0                             (0x00000000)          /* remap to remap address. See FP_REMAP */
+#define FPB_FP_COMP0_REPLACE_1                             (0x40000000)          /* set BKPT on lower halfword, upper is unaffected */
+#define FPB_FP_COMP0_REPLACE_2                             (0x80000000)          /* set BKPT on upper halfword, lower is unaffected */
+#define FPB_FP_COMP0_REPLACE_3                             (0xc0000000)          /* set BKPT on both lower and upper halfwords. */
+/* FPB_FP_COMP1[FPB_FP_COMP1_ENABLE] Bits */
+#define FPB_FP_COMP1_ENABLE_OFS                            ( 0)                  /* ENABLE Offset */
+#define FPB_FP_COMP1_ENABLE                                (0x00000001)          /*  */
+/* FPB_FP_COMP1[FPB_FP_COMP1_COMP] Bits */
+#define FPB_FP_COMP1_COMP_OFS                              ( 2)                  /* COMP Offset */
+#define FPB_FP_COMP1_COMP_M                                (0x1ffffffc)          /*  */
+/* FPB_FP_COMP1[FPB_FP_COMP1_REPLACE] Bits */
+#define FPB_FP_COMP1_REPLACE_OFS                           (30)                  /* REPLACE Offset */
+#define FPB_FP_COMP1_REPLACE_M                             (0xc0000000)          /*  */
+#define FPB_FP_COMP1_REPLACE0                              (0x40000000)          /*  */
+#define FPB_FP_COMP1_REPLACE1                              (0x80000000)          /*  */
+#define FPB_FP_COMP1_REPLACE_0                             (0x00000000)          /* remap to remap address. See FP_REMAP */
+#define FPB_FP_COMP1_REPLACE_1                             (0x40000000)          /* set BKPT on lower halfword, upper is unaffected */
+#define FPB_FP_COMP1_REPLACE_2                             (0x80000000)          /* set BKPT on upper halfword, lower is unaffected */
+#define FPB_FP_COMP1_REPLACE_3                             (0xc0000000)          /* set BKPT on both lower and upper halfwords. */
+/* FPB_FP_COMP2[FPB_FP_COMP2_ENABLE] Bits */
+#define FPB_FP_COMP2_ENABLE_OFS                            ( 0)                  /* ENABLE Offset */
+#define FPB_FP_COMP2_ENABLE                                (0x00000001)          /*  */
+/* FPB_FP_COMP2[FPB_FP_COMP2_COMP] Bits */
+#define FPB_FP_COMP2_COMP_OFS                              ( 2)                  /* COMP Offset */
+#define FPB_FP_COMP2_COMP_M                                (0x1ffffffc)          /*  */
+/* FPB_FP_COMP2[FPB_FP_COMP2_REPLACE] Bits */
+#define FPB_FP_COMP2_REPLACE_OFS                           (30)                  /* REPLACE Offset */
+#define FPB_FP_COMP2_REPLACE_M                             (0xc0000000)          /*  */
+#define FPB_FP_COMP2_REPLACE0                              (0x40000000)          /*  */
+#define FPB_FP_COMP2_REPLACE1                              (0x80000000)          /*  */
+#define FPB_FP_COMP2_REPLACE_0                             (0x00000000)          /* remap to remap address. See FP_REMAP */
+#define FPB_FP_COMP2_REPLACE_1                             (0x40000000)          /* set BKPT on lower halfword, upper is unaffected */
+#define FPB_FP_COMP2_REPLACE_2                             (0x80000000)          /* set BKPT on upper halfword, lower is unaffected */
+#define FPB_FP_COMP2_REPLACE_3                             (0xc0000000)          /* set BKPT on both lower and upper halfwords. */
+/* FPB_FP_COMP3[FPB_FP_COMP3_ENABLE] Bits */
+#define FPB_FP_COMP3_ENABLE_OFS                            ( 0)                  /* ENABLE Offset */
+#define FPB_FP_COMP3_ENABLE                                (0x00000001)          /*  */
+/* FPB_FP_COMP3[FPB_FP_COMP3_COMP] Bits */
+#define FPB_FP_COMP3_COMP_OFS                              ( 2)                  /* COMP Offset */
+#define FPB_FP_COMP3_COMP_M                                (0x1ffffffc)          /*  */
+/* FPB_FP_COMP3[FPB_FP_COMP3_REPLACE] Bits */
+#define FPB_FP_COMP3_REPLACE_OFS                           (30)                  /* REPLACE Offset */
+#define FPB_FP_COMP3_REPLACE_M                             (0xc0000000)          /*  */
+#define FPB_FP_COMP3_REPLACE0                              (0x40000000)          /*  */
+#define FPB_FP_COMP3_REPLACE1                              (0x80000000)          /*  */
+#define FPB_FP_COMP3_REPLACE_0                             (0x00000000)          /* remap to remap address. See FP_REMAP */
+#define FPB_FP_COMP3_REPLACE_1                             (0x40000000)          /* set BKPT on lower halfword, upper is unaffected */
+#define FPB_FP_COMP3_REPLACE_2                             (0x80000000)          /* set BKPT on upper halfword, lower is unaffected */
+#define FPB_FP_COMP3_REPLACE_3                             (0xc0000000)          /* set BKPT on both lower and upper halfwords. */
+/* FPB_FP_COMP4[FPB_FP_COMP4_ENABLE] Bits */
+#define FPB_FP_COMP4_ENABLE_OFS                            ( 0)                  /* ENABLE Offset */
+#define FPB_FP_COMP4_ENABLE                                (0x00000001)          /*  */
+/* FPB_FP_COMP4[FPB_FP_COMP4_COMP] Bits */
+#define FPB_FP_COMP4_COMP_OFS                              ( 2)                  /* COMP Offset */
+#define FPB_FP_COMP4_COMP_M                                (0x1ffffffc)          /*  */
+/* FPB_FP_COMP4[FPB_FP_COMP4_REPLACE] Bits */
+#define FPB_FP_COMP4_REPLACE_OFS                           (30)                  /* REPLACE Offset */
+#define FPB_FP_COMP4_REPLACE_M                             (0xc0000000)          /*  */
+#define FPB_FP_COMP4_REPLACE0                              (0x40000000)          /*  */
+#define FPB_FP_COMP4_REPLACE1                              (0x80000000)          /*  */
+#define FPB_FP_COMP4_REPLACE_0                             (0x00000000)          /* remap to remap address. See FP_REMAP */
+#define FPB_FP_COMP4_REPLACE_1                             (0x40000000)          /* set BKPT on lower halfword, upper is unaffected */
+#define FPB_FP_COMP4_REPLACE_2                             (0x80000000)          /* set BKPT on upper halfword, lower is unaffected */
+#define FPB_FP_COMP4_REPLACE_3                             (0xc0000000)          /* set BKPT on both lower and upper halfwords. */
+/* FPB_FP_COMP5[FPB_FP_COMP5_ENABLE] Bits */
+#define FPB_FP_COMP5_ENABLE_OFS                            ( 0)                  /* ENABLE Offset */
+#define FPB_FP_COMP5_ENABLE                                (0x00000001)          /*  */
+/* FPB_FP_COMP5[FPB_FP_COMP5_COMP] Bits */
+#define FPB_FP_COMP5_COMP_OFS                              ( 2)                  /* COMP Offset */
+#define FPB_FP_COMP5_COMP_M                                (0x1ffffffc)          /*  */
+/* FPB_FP_COMP5[FPB_FP_COMP5_REPLACE] Bits */
+#define FPB_FP_COMP5_REPLACE_OFS                           (30)                  /* REPLACE Offset */
+#define FPB_FP_COMP5_REPLACE_M                             (0xc0000000)          /*  */
+#define FPB_FP_COMP5_REPLACE0                              (0x40000000)          /*  */
+#define FPB_FP_COMP5_REPLACE1                              (0x80000000)          /*  */
+#define FPB_FP_COMP5_REPLACE_0                             (0x00000000)          /* remap to remap address. See FP_REMAP */
+#define FPB_FP_COMP5_REPLACE_1                             (0x40000000)          /* set BKPT on lower halfword, upper is unaffected */
+#define FPB_FP_COMP5_REPLACE_2                             (0x80000000)          /* set BKPT on upper halfword, lower is unaffected */
+#define FPB_FP_COMP5_REPLACE_3                             (0xc0000000)          /* set BKPT on both lower and upper halfwords. */
+/* FPB_FP_COMP6[FPB_FP_COMP6_ENABLE] Bits */
+#define FPB_FP_COMP6_ENABLE_OFS                            ( 0)                  /* ENABLE Offset */
+#define FPB_FP_COMP6_ENABLE                                (0x00000001)          /*  */
+/* FPB_FP_COMP6[FPB_FP_COMP6_COMP] Bits */
+#define FPB_FP_COMP6_COMP_OFS                              ( 2)                  /* COMP Offset */
+#define FPB_FP_COMP6_COMP_M                                (0x1ffffffc)          /*  */
+/* FPB_FP_COMP6[FPB_FP_COMP6_REPLACE] Bits */
+#define FPB_FP_COMP6_REPLACE_OFS                           (30)                  /* REPLACE Offset */
+#define FPB_FP_COMP6_REPLACE_M                             (0xc0000000)          /*  */
+#define FPB_FP_COMP6_REPLACE0                              (0x40000000)          /*  */
+#define FPB_FP_COMP6_REPLACE1                              (0x80000000)          /*  */
+#define FPB_FP_COMP6_REPLACE_0                             (0x00000000)          /* remap to remap address. See FP_REMAP */
+#define FPB_FP_COMP6_REPLACE_1                             (0x40000000)          /* set BKPT on lower halfword, upper is unaffected */
+#define FPB_FP_COMP6_REPLACE_2                             (0x80000000)          /* set BKPT on upper halfword, lower is unaffected */
+#define FPB_FP_COMP6_REPLACE_3                             (0xc0000000)          /* set BKPT on both lower and upper halfwords. */
+/* FPB_FP_COMP7[FPB_FP_COMP7_ENABLE] Bits */
+#define FPB_FP_COMP7_ENABLE_OFS                            ( 0)                  /* ENABLE Offset */
+#define FPB_FP_COMP7_ENABLE                                (0x00000001)          /*  */
+/* FPB_FP_COMP7[FPB_FP_COMP7_COMP] Bits */
+#define FPB_FP_COMP7_COMP_OFS                              ( 2)                  /* COMP Offset */
+#define FPB_FP_COMP7_COMP_M                                (0x1ffffffc)          /*  */
+/* FPB_FP_COMP7[FPB_FP_COMP7_REPLACE] Bits */
+#define FPB_FP_COMP7_REPLACE_OFS                           (30)                  /* REPLACE Offset */
+#define FPB_FP_COMP7_REPLACE_M                             (0xc0000000)          /*  */
+#define FPB_FP_COMP7_REPLACE0                              (0x40000000)          /*  */
+#define FPB_FP_COMP7_REPLACE1                              (0x80000000)          /*  */
+#define FPB_FP_COMP7_REPLACE_0                             (0x00000000)          /* remap to remap address. See FP_REMAP */
+#define FPB_FP_COMP7_REPLACE_1                             (0x40000000)          /* set BKPT on lower halfword, upper is unaffected */
+#define FPB_FP_COMP7_REPLACE_2                             (0x80000000)          /* set BKPT on upper halfword, lower is unaffected */
+#define FPB_FP_COMP7_REPLACE_3                             (0xc0000000)          /* set BKPT on both lower and upper halfwords. */
+
+
+//*****************************************************************************
+// FPU Bits
+//*****************************************************************************
+/* FPU_FPCCR[FPU_FPCCR_ASPEN] Bits */
+#define FPU_FPCCR_ASPEN_OFS                                (31)                  /* ASPEN Offset */
+#define FPU_FPCCR_ASPEN                                    (0x80000000)          /*  */
+/* FPU_FPCCR[FPU_FPCCR_LSPEN] Bits */
+#define FPU_FPCCR_LSPEN_OFS                                (30)                  /* LSPEN Offset */
+#define FPU_FPCCR_LSPEN                                    (0x40000000)          /*  */
+/* FPU_FPCCR[FPU_FPCCR_MONRDY] Bits */
+#define FPU_FPCCR_MONRDY_OFS                               ( 8)                  /* MONRDY Offset */
+#define FPU_FPCCR_MONRDY                                   (0x00000100)          /*  */
+/* FPU_FPCCR[FPU_FPCCR_BFRDY] Bits */
+#define FPU_FPCCR_BFRDY_OFS                                ( 6)                  /* BFRDY Offset */
+#define FPU_FPCCR_BFRDY                                    (0x00000040)          /*  */
+/* FPU_FPCCR[FPU_FPCCR_MMRDY] Bits */
+#define FPU_FPCCR_MMRDY_OFS                                ( 5)                  /* MMRDY Offset */
+#define FPU_FPCCR_MMRDY                                    (0x00000020)          /*  */
+/* FPU_FPCCR[FPU_FPCCR_HFRDY] Bits */
+#define FPU_FPCCR_HFRDY_OFS                                ( 4)                  /* HFRDY Offset */
+#define FPU_FPCCR_HFRDY                                    (0x00000010)          /*  */
+/* FPU_FPCCR[FPU_FPCCR_THREAD] Bits */
+#define FPU_FPCCR_THREAD_OFS                               ( 3)                  /* THREAD Offset */
+#define FPU_FPCCR_THREAD                                   (0x00000008)          /*  */
+/* FPU_FPCCR[FPU_FPCCR_USER] Bits */
+#define FPU_FPCCR_USER_OFS                                 ( 1)                  /* USER Offset */
+#define FPU_FPCCR_USER                                     (0x00000002)          /*  */
+/* FPU_FPCCR[FPU_FPCCR_LSPACT] Bits */
+#define FPU_FPCCR_LSPACT_OFS                               ( 0)                  /* LSPACT Offset */
+#define FPU_FPCCR_LSPACT                                   (0x00000001)          /*  */
+/* FPU_FPCAR[FPU_FPCAR_ADDRESS] Bits */
+#define FPU_FPCAR_ADDRESS_OFS                              ( 2)                  /* ADDRESS Offset */
+#define FPU_FPCAR_ADDRESS_M                                (0x7ffffffc)          /*  */
+/* FPU_FPDSCR[FPU_FPDSCR_AHP] Bits */
+#define FPU_FPDSCR_AHP_OFS                                 (26)                  /* AHP Offset */
+#define FPU_FPDSCR_AHP                                     (0x04000000)          /*  */
+/* FPU_FPDSCR[FPU_FPDSCR_DN] Bits */
+#define FPU_FPDSCR_DN_OFS                                  (25)                  /* DN Offset */
+#define FPU_FPDSCR_DN                                      (0x02000000)          /*  */
+/* FPU_FPDSCR[FPU_FPDSCR_FZ] Bits */
+#define FPU_FPDSCR_FZ_OFS                                  (24)                  /* FZ Offset */
+#define FPU_FPDSCR_FZ                                      (0x01000000)          /*  */
+/* FPU_FPDSCR[FPU_FPDSCR_RMODE] Bits */
+#define FPU_FPDSCR_RMODE_OFS                               (22)                  /* RMODE Offset */
+#define FPU_FPDSCR_RMODE_M                                 (0x00c00000)          /*  */
+/* FPU_MVFR0[FPU_MVFR0_FP_ROUNDING_MODES] Bits */
+#define FPU_MVFR0_FP_ROUNDING_MODES_OFS                    (28)                  /* FP_ROUNDING_MODES Offset */
+#define FPU_MVFR0_FP_ROUNDING_MODES_M                      (0xf0000000)          /*  */
+/* FPU_MVFR0[FPU_MVFR0_SHORT_VECTORS] Bits */
+#define FPU_MVFR0_SHORT_VECTORS_OFS                        (24)                  /* SHORT_VECTORS Offset */
+#define FPU_MVFR0_SHORT_VECTORS_M                          (0x0f000000)          /*  */
+/* FPU_MVFR0[FPU_MVFR0_SQUARE_ROOT] Bits */
+#define FPU_MVFR0_SQUARE_ROOT_OFS                          (20)                  /* SQUARE_ROOT Offset */
+#define FPU_MVFR0_SQUARE_ROOT_M                            (0x00f00000)          /*  */
+/* FPU_MVFR0[FPU_MVFR0_DIVIDE] Bits */
+#define FPU_MVFR0_DIVIDE_OFS                               (16)                  /* DIVIDE Offset */
+#define FPU_MVFR0_DIVIDE_M                                 (0x000f0000)          /*  */
+/* FPU_MVFR0[FPU_MVFR0_FP_ECEPTION_TRAPPING] Bits */
+#define FPU_MVFR0_FP_ECEPTION_TRAPPING_OFS                 (12)                  /* FP_EXCEPTION_TRAPPING Offset */
+#define FPU_MVFR0_FP_ECEPTION_TRAPPING_M                   (0x0000f000)          /*  */
+/* FPU_MVFR0[FPU_MVFR0_DOUBLE_PRECISION] Bits */
+#define FPU_MVFR0_DOUBLE_PRECISION_OFS                     ( 8)                  /* DOUBLE_PRECISION Offset */
+#define FPU_MVFR0_DOUBLE_PRECISION_M                       (0x00000f00)          /*  */
+/* FPU_MVFR0[FPU_MVFR0_SINGLE_PRECISION] Bits */
+#define FPU_MVFR0_SINGLE_PRECISION_OFS                     ( 4)                  /* SINGLE_PRECISION Offset */
+#define FPU_MVFR0_SINGLE_PRECISION_M                       (0x000000f0)          /*  */
+/* FPU_MVFR0[FPU_MVFR0_A_SIMD_REGISTERS] Bits */
+#define FPU_MVFR0_A_SIMD_REGISTERS_OFS                     ( 0)                  /* A_SIMD_REGISTERS Offset */
+#define FPU_MVFR0_A_SIMD_REGISTERS_M                       (0x0000000f)          /*  */
+/* FPU_MVFR1[FPU_MVFR1_FP_FUSED_MAC] Bits */
+#define FPU_MVFR1_FP_FUSED_MAC_OFS                         (28)                  /* FP_FUSED_MAC Offset */
+#define FPU_MVFR1_FP_FUSED_MAC_M                           (0xf0000000)          /*  */
+/* FPU_MVFR1[FPU_MVFR1_FP_HPFP] Bits */
+#define FPU_MVFR1_FP_HPFP_OFS                              (24)                  /* FP_HPFP Offset */
+#define FPU_MVFR1_FP_HPFP_M                                (0x0f000000)          /*  */
+/* FPU_MVFR1[FPU_MVFR1_D_NAN_MODE] Bits */
+#define FPU_MVFR1_D_NAN_MODE_OFS                           ( 4)                  /* D_NAN_MODE Offset */
+#define FPU_MVFR1_D_NAN_MODE_M                             (0x000000f0)          /*  */
+/* FPU_MVFR1[FPU_MVFR1_FTZ_MODE] Bits */
+#define FPU_MVFR1_FTZ_MODE_OFS                             ( 0)                  /* FTZ_MODE Offset */
+#define FPU_MVFR1_FTZ_MODE_M                               (0x0000000f)          /*  */
+
+
+//*****************************************************************************
+// ITM Bits
+//*****************************************************************************
+/* ITM_TPR[ITM_TPR_PRIVMASK] Bits */
+#define ITM_TPR_PRIVMASK_OFS                               ( 0)                  /* PRIVMASK Offset */
+#define ITM_TPR_PRIVMASK_M                                 (0x0000000f)          /*  */
+/* ITM_TCR[ITM_TCR_ITMENA] Bits */
+#define ITM_TCR_ITMENA_OFS                                 ( 0)                  /* ITMENA Offset */
+#define ITM_TCR_ITMENA                                     (0x00000001)          /*  */
+/* ITM_TCR[ITM_TCR_TSENA] Bits */
+#define ITM_TCR_TSENA_OFS                                  ( 1)                  /* TSENA Offset */
+#define ITM_TCR_TSENA                                      (0x00000002)          /*  */
+/* ITM_TCR[ITM_TCR_SYNCENA] Bits */
+#define ITM_TCR_SYNCENA_OFS                                ( 2)                  /* SYNCENA Offset */
+#define ITM_TCR_SYNCENA                                    (0x00000004)          /*  */
+/* ITM_TCR[ITM_TCR_DWTENA] Bits */
+#define ITM_TCR_DWTENA_OFS                                 ( 3)                  /* DWTENA Offset */
+#define ITM_TCR_DWTENA                                     (0x00000008)          /*  */
+/* ITM_TCR[ITM_TCR_SWOENA] Bits */
+#define ITM_TCR_SWOENA_OFS                                 ( 4)                  /* SWOENA Offset */
+#define ITM_TCR_SWOENA                                     (0x00000010)          /*  */
+/* ITM_TCR[ITM_TCR_TSPRESCALE] Bits */
+#define ITM_TCR_TSPRESCALE_OFS                             ( 8)                  /* TSPRESCALE Offset */
+#define ITM_TCR_TSPRESCALE_M                               (0x00000300)          /*  */
+#define ITM_TCR_TSPRESCALE0                                (0x00000100)          /*  */
+#define ITM_TCR_TSPRESCALE1                                (0x00000200)          /*  */
+#define ITM_TCR_TSPRESCALE_0                               (0x00000000)          /* no prescaling */
+#define ITM_TCR_TSPRESCALE_1                               (0x00000100)          /* divide by 4 */
+#define ITM_TCR_TSPRESCALE_2                               (0x00000200)          /* divide by 16 */
+#define ITM_TCR_TSPRESCALE_3                               (0x00000300)          /* divide by 64 */
+/* ITM_TCR[ITM_TCR_ATBID] Bits */
+#define ITM_TCR_ATBID_OFS                                  (16)                  /* ATBID Offset */
+#define ITM_TCR_ATBID_M                                    (0x007f0000)          /*  */
+/* ITM_TCR[ITM_TCR_BUSY] Bits */
+#define ITM_TCR_BUSY_OFS                                   (23)                  /* BUSY Offset */
+#define ITM_TCR_BUSY                                       (0x00800000)          /*  */
+/* ITM_IWR[ITM_IWR_ATVALIDM] Bits */
+#define ITM_IWR_ATVALIDM_OFS                               ( 0)                  /* ATVALIDM Offset */
+#define ITM_IWR_ATVALIDM                                   (0x00000001)          /*  */
+/* ITM_IMCR[ITM_IMCR_INTEGRATION] Bits */
+#define ITM_IMCR_INTEGRATION_OFS                           ( 0)                  /* INTEGRATION Offset */
+#define ITM_IMCR_INTEGRATION                               (0x00000001)          /*  */
+/* ITM_LSR[ITM_LSR_PRESENT] Bits */
+#define ITM_LSR_PRESENT_OFS                                ( 0)                  /* PRESENT Offset */
+#define ITM_LSR_PRESENT                                    (0x00000001)          /*  */
+/* ITM_LSR[ITM_LSR_ACCESS] Bits */
+#define ITM_LSR_ACCESS_OFS                                 ( 1)                  /* ACCESS Offset */
+#define ITM_LSR_ACCESS                                     (0x00000002)          /*  */
+/* ITM_LSR[ITM_LSR_BYTEACC] Bits */
+#define ITM_LSR_BYTEACC_OFS                                ( 2)                  /* BYTEACC Offset */
+#define ITM_LSR_BYTEACC                                    (0x00000004)          /*  */
+
+
+//*****************************************************************************
+// MPU Bits
+//*****************************************************************************
+/* MPU_TYPE[MPU_TYPE_SEPARATE] Bits */
+#define MPU_TYPE_SEPARATE_OFS                              ( 0)                  /* SEPARATE Offset */
+#define MPU_TYPE_SEPARATE                                  (0x00000001)          /*  */
+/* MPU_TYPE[MPU_TYPE_DREGION] Bits */
+#define MPU_TYPE_DREGION_OFS                               ( 8)                  /* DREGION Offset */
+#define MPU_TYPE_DREGION_M                                 (0x0000ff00)          /*  */
+/* MPU_TYPE[MPU_TYPE_IREGION] Bits */
+#define MPU_TYPE_IREGION_OFS                               (16)                  /* IREGION Offset */
+#define MPU_TYPE_IREGION_M                                 (0x00ff0000)          /*  */
+/* MPU_CTRL[MPU_CTRL_ENABLE] Bits */
+#define MPU_CTRL_ENABLE_OFS                                ( 0)                  /* ENABLE Offset */
+#define MPU_CTRL_ENABLE                                    (0x00000001)          /*  */
+/* MPU_CTRL[MPU_CTRL_HFNMIENA] Bits */
+#define MPU_CTRL_HFNMIENA_OFS                              ( 1)                  /* HFNMIENA Offset */
+#define MPU_CTRL_HFNMIENA                                  (0x00000002)          /*  */
+/* MPU_CTRL[MPU_CTRL_PRIVDEFENA] Bits */
+#define MPU_CTRL_PRIVDEFENA_OFS                            ( 2)                  /* PRIVDEFENA Offset */
+#define MPU_CTRL_PRIVDEFENA                                (0x00000004)          /*  */
+/* MPU_RNR[MPU_RNR_REGION] Bits */
+#define MPU_RNR_REGION_OFS                                 ( 0)                  /* REGION Offset */
+#define MPU_RNR_REGION_M                                   (0x000000ff)          /*  */
+/* MPU_RBAR[MPU_RBAR_REGION] Bits */
+#define MPU_RBAR_REGION_OFS                                ( 0)                  /* REGION Offset */
+#define MPU_RBAR_REGION_M                                  (0x0000000f)          /*  */
+/* MPU_RBAR[MPU_RBAR_VALID] Bits */
+#define MPU_RBAR_VALID_OFS                                 ( 4)                  /* VALID Offset */
+#define MPU_RBAR_VALID                                     (0x00000010)          /*  */
+/* MPU_RBAR[MPU_RBAR_ADDR] Bits */
+#define MPU_RBAR_ADDR_OFS                                  ( 5)                  /* ADDR Offset */
+#define MPU_RBAR_ADDR_M                                    (0xffffffe0)          /*  */
+/* MPU_RASR[MPU_RASR_ENABLE] Bits */
+#define MPU_RASR_ENABLE_OFS                                ( 0)                  /* ENABLE Offset */
+#define MPU_RASR_ENABLE                                    (0x00000001)          /*  */
+/* MPU_RASR[MPU_RASR_SIZE] Bits */
+#define MPU_RASR_SIZE_OFS                                  ( 1)                  /* SIZE Offset */
+#define MPU_RASR_SIZE_M                                    (0x0000003e)          /*  */
+#define MPU_RASR_SIZE0                                     (0x00000002)          /*  */
+#define MPU_RASR_SIZE1                                     (0x00000004)          /*  */
+#define MPU_RASR_SIZE2                                     (0x00000008)          /*  */
+#define MPU_RASR_SIZE3                                     (0x00000010)          /*  */
+#define MPU_RASR_SIZE4                                     (0x00000020)          /*  */
+#define MPU_RASR_SIZE_0                                    (0x00000000)          /* 4KB */
+#define MPU_RASR_SIZE_1                                    (0x00000002)          /* 256MB */
+#define MPU_RASR_SIZE_4                                    (0x00000008)          /* 32B */
+#define MPU_RASR_SIZE_5                                    (0x0000000a)          /* 64B */
+#define MPU_RASR_SIZE_6                                    (0x0000000c)          /* 128B */
+#define MPU_RASR_SIZE_7                                    (0x0000000e)          /* 256B */
+#define MPU_RASR_SIZE_8                                    (0x00000010)          /* 512B */
+#define MPU_RASR_SIZE_9                                    (0x00000012)          /* 1KB */
+#define MPU_RASR_SIZE_10                                   (0x00000014)          /* 2KB */
+#define MPU_RASR_SIZE_12                                   (0x00000018)          /* 8KB */
+#define MPU_RASR_SIZE_13                                   (0x0000001a)          /* 16KB */
+#define MPU_RASR_SIZE_14                                   (0x0000001c)          /* 32KB */
+#define MPU_RASR_SIZE_15                                   (0x0000001e)          /* 64KB */
+#define MPU_RASR_SIZE_16                                   (0x00000020)          /* 128KB */
+#define MPU_RASR_SIZE_17                                   (0x00000022)          /* 256KB */
+#define MPU_RASR_SIZE_18                                   (0x00000024)          /* 512KB */
+#define MPU_RASR_SIZE_19                                   (0x00000026)          /* 1MB */
+#define MPU_RASR_SIZE_20                                   (0x00000028)          /* 2MB */
+#define MPU_RASR_SIZE_21                                   (0x0000002a)          /* 4MB */
+#define MPU_RASR_SIZE_22                                   (0x0000002c)          /* 8MB */
+#define MPU_RASR_SIZE_23                                   (0x0000002e)          /* 16MB */
+#define MPU_RASR_SIZE_24                                   (0x00000030)          /* 32MB */
+#define MPU_RASR_SIZE_25                                   (0x00000032)          /* 64MB */
+#define MPU_RASR_SIZE_26                                   (0x00000034)          /* 128MB */
+#define MPU_RASR_SIZE_28                                   (0x00000038)          /* 512MB */
+#define MPU_RASR_SIZE_29                                   (0x0000003a)          /* 1GB */
+#define MPU_RASR_SIZE_30                                   (0x0000003c)          /* 2GB */
+#define MPU_RASR_SIZE_31                                   (0x0000003e)          /* 4GB */
+/* MPU_RASR[MPU_RASR_SRD] Bits */
+#define MPU_RASR_SRD_OFS                                   ( 8)                  /* SRD Offset */
+#define MPU_RASR_SRD_M                                     (0x0000ff00)          /*  */
+/* MPU_RASR[MPU_RASR_B] Bits */
+#define MPU_RASR_B_OFS                                     (16)                  /* B Offset */
+#define MPU_RASR_B                                         (0x00010000)          /*  */
+/* MPU_RASR[MPU_RASR_C] Bits */
+#define MPU_RASR_C_OFS                                     (17)                  /* C Offset */
+#define MPU_RASR_C                                         (0x00020000)          /*  */
+/* MPU_RASR[MPU_RASR_S] Bits */
+#define MPU_RASR_S_OFS                                     (18)                  /* S Offset */
+#define MPU_RASR_S                                         (0x00040000)          /*  */
+/* MPU_RASR[MPU_RASR_TEX] Bits */
+#define MPU_RASR_TEX_OFS                                   (19)                  /* TEX Offset */
+#define MPU_RASR_TEX_M                                     (0x00380000)          /*  */
+/* MPU_RASR[MPU_RASR_AP] Bits */
+#define MPU_RASR_AP_OFS                                    (24)                  /* AP Offset */
+#define MPU_RASR_AP_M                                      (0x07000000)          /*  */
+#define MPU_RASR_AP0                                       (0x01000000)          /*  */
+#define MPU_RASR_AP1                                       (0x02000000)          /*  */
+#define MPU_RASR_AP2                                       (0x04000000)          /*  */
+#define MPU_RASR_AP_0                                      (0x00000000)          /* Priviliged permissions: No access. User permissions: No access. */
+#define MPU_RASR_AP_1                                      (0x01000000)          /* Priviliged permissions: Read-write. User permissions: No access. */
+#define MPU_RASR_AP_2                                      (0x02000000)          /* Priviliged permissions: Read-write. User permissions: Read-only. */
+#define MPU_RASR_AP_3                                      (0x03000000)          /* Priviliged permissions: Read-write. User permissions: Read-write. */
+#define MPU_RASR_AP_5                                      (0x05000000)          /* Priviliged permissions: Read-only. User permissions: No access. */
+#define MPU_RASR_AP_6                                      (0x06000000)          /* Priviliged permissions: Read-only. User permissions: Read-only. */
+#define MPU_RASR_AP_7                                      (0x07000000)          /* Priviliged permissions: Read-only. User permissions: Read-only. */
+/* MPU_RASR[MPU_RASR_XN] Bits */
+#define MPU_RASR_XN_OFS                                    (28)                  /* XN Offset */
+#define MPU_RASR_XN                                        (0x10000000)          /*  */
+
+/* Pre-defined bitfield values */
+
+/*  MPU_RASR_SIZE Bitfield Bits */
+#define MPU_RASR_SIZE__4                                   (0x00000008)          /* 64B */
+#define MPU_RASR_SIZE__32B                                 (0x00000008)          /* 32B */
+#define MPU_RASR_SIZE__64B                                 (0x0000000c)          /* 128B */
+#define MPU_RASR_SIZE__256B                                (0x0000000e)          /* 256B */
+#define MPU_RASR_SIZE__512B                                (0x00000010)          /* 512B */
+#define MPU_RASR_SIZE__1K                                  (0x00000012)          /* 1KB */
+#define MPU_RASR_SIZE__2K                                  (0x00000014)          /* 2KB */
+#define MPU_RASR_SIZE__4K                                  (0x00000016)          /* 4KB */
+#define MPU_RASR_SIZE__8K                                  (0x00000018)          /* 8KB */
+#define MPU_RASR_SIZE__16K                                 (0x0000001a)          /* 16KB */
+#define MPU_RASR_SIZE__32K                                 (0x0000001c)          /* 32KB */
+#define MPU_RASR_SIZE__64K                                 (0x0000001e)          /* 64KB */
+#define MPU_RASR_SIZE__128K                                (0x00000020)          /* 128KB */
+#define MPU_RASR_SIZE__256K                                (0x00000022)          /* 256KB */
+#define MPU_RASR_SIZE__512K                                (0x00000024)          /* 512KB */
+#define MPU_RASR_SIZE__1M                                  (0x00000026)          /* 1MB */
+#define MPU_RASR_SIZE__2M                                  (0x00000028)          /* 2MB */
+#define MPU_RASR_SIZE__4M                                  (0x0000002a)          /* 4MB */
+#define MPU_RASR_SIZE__8M                                  (0x0000002c)          /* 8MB */
+#define MPU_RASR_SIZE__16M                                 (0x0000002e)          /* 16MB */
+#define MPU_RASR_SIZE__32M                                 (0x00000030)          /* 32MB */
+#define MPU_RASR_SIZE__64M                                 (0x00000032)          /* 64MB */
+#define MPU_RASR_SIZE__128M                                (0x00000034)          /* 128MB */
+#define MPU_RASR_SIZE__256M                                (0x00000036)          /* 256MB */
+#define MPU_RASR_SIZE__512M                                (0x00000038)          /* 512MB */
+#define MPU_RASR_SIZE__1G                                  (0x0000003a)          /* 1GB */
+#define MPU_RASR_SIZE__2G                                  (0x0000003c)          /* 2GB */
+#define MPU_RASR_SIZE__4G                                  (0x0000003e)          /* 4GB */
+
+/*  MPU_RASR_AP Bitfield Bits */
+#define MPU_RASR_AP_PRV_NO_USR_NO                          (0x00000000)          /* Priviliged permissions: No access. User permissions: No access. */
+#define MPU_RASR_AP_PRV_RW_USR_NO                          (0x01000000)          /* Priviliged permissions: Read-write. User permissions: No access. */
+#define MPU_RASR_AP_PRV_RW_USR_RO                          (0x02000000)          /* Priviliged permissions: Read-write. User permissions: Read-only. */ 
+#define MPU_RASR_AP_PRV_RW_USR_RW                          (0x03000000)          /* Priviliged permissions: Read-write. User permissions: Read-write. */
+#define MPU_RASR_AP_PRV_RO_USR_NO                          (0x05000000)          /* Priviliged permissions: Read-only. User permissions: No access. */
+#define MPU_RASR_AP_PRV_RO_USR_RO                          (0x06000000)          /* Priviliged permissions: Read-only. User permissions: Read-only. */
+
+/* MPU_RASR_XN Bitfield Bits */
+#define MPU_RASR_AP_EXEC                                   (0x00000000)          /* Instruction access enabled */     
+#define MPU_RASR_AP_NOEXEC                                 (0x10000000)          /* Instruction access disabled */
+
+
+//*****************************************************************************
+// NVIC Bits
+//*****************************************************************************
+/* NVIC_IPR0[NVIC_IPR0_PRI_0] Bits */
+#define NVIC_IPR0_PRI_0_OFS                                ( 0)                  /* PRI_0 Offset */
+#define NVIC_IPR0_PRI_0_M                                  (0x000000ff)          /*  */
+/* NVIC_IPR0[NVIC_IPR0_PRI_1] Bits */
+#define NVIC_IPR0_PRI_1_OFS                                ( 8)                  /* PRI_1 Offset */
+#define NVIC_IPR0_PRI_1_M                                  (0x0000ff00)          /*  */
+/* NVIC_IPR0[NVIC_IPR0_PRI_2] Bits */
+#define NVIC_IPR0_PRI_2_OFS                                (16)                  /* PRI_2 Offset */
+#define NVIC_IPR0_PRI_2_M                                  (0x00ff0000)          /*  */
+/* NVIC_IPR0[NVIC_IPR0_PRI_3] Bits */
+#define NVIC_IPR0_PRI_3_OFS                                (24)                  /* PRI_3 Offset */
+#define NVIC_IPR0_PRI_3_M                                  (0xff000000)          /*  */
+/* NVIC_IPR1[NVIC_IPR1_PRI_4] Bits */
+#define NVIC_IPR1_PRI_4_OFS                                ( 0)                  /* PRI_4 Offset */
+#define NVIC_IPR1_PRI_4_M                                  (0x000000ff)          /*  */
+/* NVIC_IPR1[NVIC_IPR1_PRI_5] Bits */
+#define NVIC_IPR1_PRI_5_OFS                                ( 8)                  /* PRI_5 Offset */
+#define NVIC_IPR1_PRI_5_M                                  (0x0000ff00)          /*  */
+/* NVIC_IPR1[NVIC_IPR1_PRI_6] Bits */
+#define NVIC_IPR1_PRI_6_OFS                                (16)                  /* PRI_6 Offset */
+#define NVIC_IPR1_PRI_6_M                                  (0x00ff0000)          /*  */
+/* NVIC_IPR1[NVIC_IPR1_PRI_7] Bits */
+#define NVIC_IPR1_PRI_7_OFS                                (24)                  /* PRI_7 Offset */
+#define NVIC_IPR1_PRI_7_M                                  (0xff000000)          /*  */
+/* NVIC_IPR2[NVIC_IPR2_PRI_8] Bits */
+#define NVIC_IPR2_PRI_8_OFS                                ( 0)                  /* PRI_8 Offset */
+#define NVIC_IPR2_PRI_8_M                                  (0x000000ff)          /*  */
+/* NVIC_IPR2[NVIC_IPR2_PRI_9] Bits */
+#define NVIC_IPR2_PRI_9_OFS                                ( 8)                  /* PRI_9 Offset */
+#define NVIC_IPR2_PRI_9_M                                  (0x0000ff00)          /*  */
+/* NVIC_IPR2[NVIC_IPR2_PRI_10] Bits */
+#define NVIC_IPR2_PRI_10_OFS                               (16)                  /* PRI_10 Offset */
+#define NVIC_IPR2_PRI_10_M                                 (0x00ff0000)          /*  */
+/* NVIC_IPR2[NVIC_IPR2_PRI_11] Bits */
+#define NVIC_IPR2_PRI_11_OFS                               (24)                  /* PRI_11 Offset */
+#define NVIC_IPR2_PRI_11_M                                 (0xff000000)          /*  */
+/* NVIC_IPR3[NVIC_IPR3_PRI_12] Bits */
+#define NVIC_IPR3_PRI_12_OFS                               ( 0)                  /* PRI_12 Offset */
+#define NVIC_IPR3_PRI_12_M                                 (0x000000ff)          /*  */
+/* NVIC_IPR3[NVIC_IPR3_PRI_13] Bits */
+#define NVIC_IPR3_PRI_13_OFS                               ( 8)                  /* PRI_13 Offset */
+#define NVIC_IPR3_PRI_13_M                                 (0x0000ff00)          /*  */
+/* NVIC_IPR3[NVIC_IPR3_PRI_14] Bits */
+#define NVIC_IPR3_PRI_14_OFS                               (16)                  /* PRI_14 Offset */
+#define NVIC_IPR3_PRI_14_M                                 (0x00ff0000)          /*  */
+/* NVIC_IPR3[NVIC_IPR3_PRI_15] Bits */
+#define NVIC_IPR3_PRI_15_OFS                               (24)                  /* PRI_15 Offset */
+#define NVIC_IPR3_PRI_15_M                                 (0xff000000)          /*  */
+/* NVIC_IPR4[NVIC_IPR4_PRI_16] Bits */
+#define NVIC_IPR4_PRI_16_OFS                               ( 0)                  /* PRI_16 Offset */
+#define NVIC_IPR4_PRI_16_M                                 (0x000000ff)          /*  */
+/* NVIC_IPR4[NVIC_IPR4_PRI_17] Bits */
+#define NVIC_IPR4_PRI_17_OFS                               ( 8)                  /* PRI_17 Offset */
+#define NVIC_IPR4_PRI_17_M                                 (0x0000ff00)          /*  */
+/* NVIC_IPR4[NVIC_IPR4_PRI_18] Bits */
+#define NVIC_IPR4_PRI_18_OFS                               (16)                  /* PRI_18 Offset */
+#define NVIC_IPR4_PRI_18_M                                 (0x00ff0000)          /*  */
+/* NVIC_IPR4[NVIC_IPR4_PRI_19] Bits */
+#define NVIC_IPR4_PRI_19_OFS                               (24)                  /* PRI_19 Offset */
+#define NVIC_IPR4_PRI_19_M                                 (0xff000000)          /*  */
+/* NVIC_IPR5[NVIC_IPR5_PRI_20] Bits */
+#define NVIC_IPR5_PRI_20_OFS                               ( 0)                  /* PRI_20 Offset */
+#define NVIC_IPR5_PRI_20_M                                 (0x000000ff)          /*  */
+/* NVIC_IPR5[NVIC_IPR5_PRI_21] Bits */
+#define NVIC_IPR5_PRI_21_OFS                               ( 8)                  /* PRI_21 Offset */
+#define NVIC_IPR5_PRI_21_M                                 (0x0000ff00)          /*  */
+/* NVIC_IPR5[NVIC_IPR5_PRI_22] Bits */
+#define NVIC_IPR5_PRI_22_OFS                               (16)                  /* PRI_22 Offset */
+#define NVIC_IPR5_PRI_22_M                                 (0x00ff0000)          /*  */
+/* NVIC_IPR5[NVIC_IPR5_PRI_23] Bits */
+#define NVIC_IPR5_PRI_23_OFS                               (24)                  /* PRI_23 Offset */
+#define NVIC_IPR5_PRI_23_M                                 (0xff000000)          /*  */
+/* NVIC_IPR6[NVIC_IPR6_PRI_24] Bits */
+#define NVIC_IPR6_PRI_24_OFS                               ( 0)                  /* PRI_24 Offset */
+#define NVIC_IPR6_PRI_24_M                                 (0x000000ff)          /*  */
+/* NVIC_IPR6[NVIC_IPR6_PRI_25] Bits */
+#define NVIC_IPR6_PRI_25_OFS                               ( 8)                  /* PRI_25 Offset */
+#define NVIC_IPR6_PRI_25_M                                 (0x0000ff00)          /*  */
+/* NVIC_IPR6[NVIC_IPR6_PRI_26] Bits */
+#define NVIC_IPR6_PRI_26_OFS                               (16)                  /* PRI_26 Offset */
+#define NVIC_IPR6_PRI_26_M                                 (0x00ff0000)          /*  */
+/* NVIC_IPR6[NVIC_IPR6_PRI_27] Bits */
+#define NVIC_IPR6_PRI_27_OFS                               (24)                  /* PRI_27 Offset */
+#define NVIC_IPR6_PRI_27_M                                 (0xff000000)          /*  */
+/* NVIC_IPR7[NVIC_IPR7_PRI_28] Bits */
+#define NVIC_IPR7_PRI_28_OFS                               ( 0)                  /* PRI_28 Offset */
+#define NVIC_IPR7_PRI_28_M                                 (0x000000ff)          /*  */
+/* NVIC_IPR7[NVIC_IPR7_PRI_29] Bits */
+#define NVIC_IPR7_PRI_29_OFS                               ( 8)                  /* PRI_29 Offset */
+#define NVIC_IPR7_PRI_29_M                                 (0x0000ff00)          /*  */
+/* NVIC_IPR7[NVIC_IPR7_PRI_30] Bits */
+#define NVIC_IPR7_PRI_30_OFS                               (16)                  /* PRI_30 Offset */
+#define NVIC_IPR7_PRI_30_M                                 (0x00ff0000)          /*  */
+/* NVIC_IPR7[NVIC_IPR7_PRI_31] Bits */
+#define NVIC_IPR7_PRI_31_OFS                               (24)                  /* PRI_31 Offset */
+#define NVIC_IPR7_PRI_31_M                                 (0xff000000)          /*  */
+/* NVIC_IPR8[NVIC_IPR8_PRI_32] Bits */
+#define NVIC_IPR8_PRI_32_OFS                               ( 0)                  /* PRI_32 Offset */
+#define NVIC_IPR8_PRI_32_M                                 (0x000000ff)          /*  */
+/* NVIC_IPR8[NVIC_IPR8_PRI_33] Bits */
+#define NVIC_IPR8_PRI_33_OFS                               ( 8)                  /* PRI_33 Offset */
+#define NVIC_IPR8_PRI_33_M                                 (0x0000ff00)          /*  */
+/* NVIC_IPR8[NVIC_IPR8_PRI_34] Bits */
+#define NVIC_IPR8_PRI_34_OFS                               (16)                  /* PRI_34 Offset */
+#define NVIC_IPR8_PRI_34_M                                 (0x00ff0000)          /*  */
+/* NVIC_IPR8[NVIC_IPR8_PRI_35] Bits */
+#define NVIC_IPR8_PRI_35_OFS                               (24)                  /* PRI_35 Offset */
+#define NVIC_IPR8_PRI_35_M                                 (0xff000000)          /*  */
+/* NVIC_IPR9[NVIC_IPR9_PRI_36] Bits */
+#define NVIC_IPR9_PRI_36_OFS                               ( 0)                  /* PRI_36 Offset */
+#define NVIC_IPR9_PRI_36_M                                 (0x000000ff)          /*  */
+/* NVIC_IPR9[NVIC_IPR9_PRI_37] Bits */
+#define NVIC_IPR9_PRI_37_OFS                               ( 8)                  /* PRI_37 Offset */
+#define NVIC_IPR9_PRI_37_M                                 (0x0000ff00)          /*  */
+/* NVIC_IPR9[NVIC_IPR9_PRI_38] Bits */
+#define NVIC_IPR9_PRI_38_OFS                               (16)                  /* PRI_38 Offset */
+#define NVIC_IPR9_PRI_38_M                                 (0x00ff0000)          /*  */
+/* NVIC_IPR9[NVIC_IPR9_PRI_39] Bits */
+#define NVIC_IPR9_PRI_39_OFS                               (24)                  /* PRI_39 Offset */
+#define NVIC_IPR9_PRI_39_M                                 (0xff000000)          /*  */
+/* NVIC_IPR10[NVIC_IPR10_PRI_40] Bits */
+#define NVIC_IPR10_PRI_40_OFS                              ( 0)                  /* PRI_40 Offset */
+#define NVIC_IPR10_PRI_40_M                                (0x000000ff)          /*  */
+/* NVIC_IPR10[NVIC_IPR10_PRI_41] Bits */
+#define NVIC_IPR10_PRI_41_OFS                              ( 8)                  /* PRI_41 Offset */
+#define NVIC_IPR10_PRI_41_M                                (0x0000ff00)          /*  */
+/* NVIC_IPR10[NVIC_IPR10_PRI_42] Bits */
+#define NVIC_IPR10_PRI_42_OFS                              (16)                  /* PRI_42 Offset */
+#define NVIC_IPR10_PRI_42_M                                (0x00ff0000)          /*  */
+/* NVIC_IPR10[NVIC_IPR10_PRI_43] Bits */
+#define NVIC_IPR10_PRI_43_OFS                              (24)                  /* PRI_43 Offset */
+#define NVIC_IPR10_PRI_43_M                                (0xff000000)          /*  */
+/* NVIC_IPR11[NVIC_IPR11_PRI_44] Bits */
+#define NVIC_IPR11_PRI_44_OFS                              ( 0)                  /* PRI_44 Offset */
+#define NVIC_IPR11_PRI_44_M                                (0x000000ff)          /*  */
+/* NVIC_IPR11[NVIC_IPR11_PRI_45] Bits */
+#define NVIC_IPR11_PRI_45_OFS                              ( 8)                  /* PRI_45 Offset */
+#define NVIC_IPR11_PRI_45_M                                (0x0000ff00)          /*  */
+/* NVIC_IPR11[NVIC_IPR11_PRI_46] Bits */
+#define NVIC_IPR11_PRI_46_OFS                              (16)                  /* PRI_46 Offset */
+#define NVIC_IPR11_PRI_46_M                                (0x00ff0000)          /*  */
+/* NVIC_IPR11[NVIC_IPR11_PRI_47] Bits */
+#define NVIC_IPR11_PRI_47_OFS                              (24)                  /* PRI_47 Offset */
+#define NVIC_IPR11_PRI_47_M                                (0xff000000)          /*  */
+/* NVIC_IPR12[NVIC_IPR12_PRI_48] Bits */
+#define NVIC_IPR12_PRI_48_OFS                              ( 0)                  /* PRI_48 Offset */
+#define NVIC_IPR12_PRI_48_M                                (0x000000ff)          /*  */
+/* NVIC_IPR12[NVIC_IPR12_PRI_49] Bits */
+#define NVIC_IPR12_PRI_49_OFS                              ( 8)                  /* PRI_49 Offset */
+#define NVIC_IPR12_PRI_49_M                                (0x0000ff00)          /*  */
+/* NVIC_IPR12[NVIC_IPR12_PRI_50] Bits */
+#define NVIC_IPR12_PRI_50_OFS                              (16)                  /* PRI_50 Offset */
+#define NVIC_IPR12_PRI_50_M                                (0x00ff0000)          /*  */
+/* NVIC_IPR12[NVIC_IPR12_PRI_51] Bits */
+#define NVIC_IPR12_PRI_51_OFS                              (24)                  /* PRI_51 Offset */
+#define NVIC_IPR12_PRI_51_M                                (0xff000000)          /*  */
+/* NVIC_IPR13[NVIC_IPR13_PRI_52] Bits */
+#define NVIC_IPR13_PRI_52_OFS                              ( 0)                  /* PRI_52 Offset */
+#define NVIC_IPR13_PRI_52_M                                (0x000000ff)          /*  */
+/* NVIC_IPR13[NVIC_IPR13_PRI_53] Bits */
+#define NVIC_IPR13_PRI_53_OFS                              ( 8)                  /* PRI_53 Offset */
+#define NVIC_IPR13_PRI_53_M                                (0x0000ff00)          /*  */
+/* NVIC_IPR13[NVIC_IPR13_PRI_54] Bits */
+#define NVIC_IPR13_PRI_54_OFS                              (16)                  /* PRI_54 Offset */
+#define NVIC_IPR13_PRI_54_M                                (0x00ff0000)          /*  */
+/* NVIC_IPR13[NVIC_IPR13_PRI_55] Bits */
+#define NVIC_IPR13_PRI_55_OFS                              (24)                  /* PRI_55 Offset */
+#define NVIC_IPR13_PRI_55_M                                (0xff000000)          /*  */
+/* NVIC_IPR14[NVIC_IPR14_PRI_56] Bits */
+#define NVIC_IPR14_PRI_56_OFS                              ( 0)                  /* PRI_56 Offset */
+#define NVIC_IPR14_PRI_56_M                                (0x000000ff)          /*  */
+/* NVIC_IPR14[NVIC_IPR14_PRI_57] Bits */
+#define NVIC_IPR14_PRI_57_OFS                              ( 8)                  /* PRI_57 Offset */
+#define NVIC_IPR14_PRI_57_M                                (0x0000ff00)          /*  */
+/* NVIC_IPR14[NVIC_IPR14_PRI_58] Bits */
+#define NVIC_IPR14_PRI_58_OFS                              (16)                  /* PRI_58 Offset */
+#define NVIC_IPR14_PRI_58_M                                (0x00ff0000)          /*  */
+/* NVIC_IPR14[NVIC_IPR14_PRI_59] Bits */
+#define NVIC_IPR14_PRI_59_OFS                              (24)                  /* PRI_59 Offset */
+#define NVIC_IPR14_PRI_59_M                                (0xff000000)          /*  */
+/* NVIC_IPR15[NVIC_IPR15_PRI_60] Bits */
+#define NVIC_IPR15_PRI_60_OFS                              ( 0)                  /* PRI_60 Offset */
+#define NVIC_IPR15_PRI_60_M                                (0x000000ff)          /*  */
+/* NVIC_IPR15[NVIC_IPR15_PRI_61] Bits */
+#define NVIC_IPR15_PRI_61_OFS                              ( 8)                  /* PRI_61 Offset */
+#define NVIC_IPR15_PRI_61_M                                (0x0000ff00)          /*  */
+/* NVIC_IPR15[NVIC_IPR15_PRI_62] Bits */
+#define NVIC_IPR15_PRI_62_OFS                              (16)                  /* PRI_62 Offset */
+#define NVIC_IPR15_PRI_62_M                                (0x00ff0000)          /*  */
+/* NVIC_IPR15[NVIC_IPR15_PRI_63] Bits */
+#define NVIC_IPR15_PRI_63_OFS                              (24)                  /* PRI_63 Offset */
+#define NVIC_IPR15_PRI_63_M                                (0xff000000)          /*  */
+/* NVIC_STIR[NVIC_STIR_INTID] Bits */
+#define NVIC_STIR_INTID_OFS                                ( 0)                  /* INTID Offset */
+#define NVIC_STIR_INTID_M                                  (0x000001ff)          /*  */
+
+
+//*****************************************************************************
+// PCM Bits
+//*****************************************************************************
+/* PCMCTL0[AMR] Bits */
+#define AMR_OFS                                            ( 0)                  /* AMR Offset */
+#define AMR_M                                              (0x0000000f)          /* Active Mode Request */
+#define AMR0                                               (0x00000001)          /* Active Mode Request */
+#define AMR1                                               (0x00000002)          /* Active Mode Request */
+#define AMR2                                               (0x00000004)          /* Active Mode Request */
+#define AMR3                                               (0x00000008)          /* Active Mode Request */
+#define AMR_0                                              (0x00000000)          /* LDO based Active Mode at Core voltage setting 0. */
+#define AMR_1                                              (0x00000001)          /* LDO based Active Mode at Core voltage setting 1. */
+#define AMR_4                                              (0x00000004)          /* DC-DC based Active Mode at Core voltage setting 0. */
+#define AMR_5                                              (0x00000005)          /* DC-DC based Active Mode at Core voltage setting 1. */
+#define AMR_8                                              (0x00000008)          /* Low-Frequency Active Mode at Core voltage setting 0. */
+#define AMR_9                                              (0x00000009)          /* Low-Frequency Active Mode at Core voltage setting 1. */
+#define AMR__AM_LDO_VCORE0                                 (0x00000000)          /* LDO based Active Mode at Core voltage setting 0. */
+#define AMR__AM_LDO_VCORE1                                 (0x00000001)          /* LDO based Active Mode at Core voltage setting 1. */
+#define AMR__AM_DCDC_VCORE0                                (0x00000004)          /* DC-DC based Active Mode at Core voltage setting 0. */
+#define AMR__AM_DCDC_VCORE1                                (0x00000005)          /* DC-DC based Active Mode at Core voltage setting 1. */
+#define AMR__AM_LF_VCORE0                                  (0x00000008)          /* Low-Frequency Active Mode at Core voltage setting 0. */
+#define AMR__AM_LF_VCORE1                                  (0x00000009)          /* Low-Frequency Active Mode at Core voltage setting 1. */
+/* PCMCTL0[LPMR] Bits */
+#define LPMR_OFS                                           ( 4)                  /* LPMR Offset */
+#define LPMR_M                                             (0x000000f0)          /* Low Power Mode Request */
+#define LPMR0                                              (0x00000010)          /* Low Power Mode Request */
+#define LPMR1                                              (0x00000020)          /* Low Power Mode Request */
+#define LPMR2                                              (0x00000040)          /* Low Power Mode Request */
+#define LPMR3                                              (0x00000080)          /* Low Power Mode Request */
+#define LPMR_0                                             (0x00000000)          /* LPM3. Core voltage setting is similar to the mode from which LPM3 is entered. */
+#define LPMR_10                                            (0x000000a0)          /* LPM3.5. Core voltage setting 0. */
+#define LPMR_12                                            (0x000000c0)          /* LPM4.5 */
+#define LPMR__LPM3                                         (0x00000000)          /* LPM3. Core voltage setting is similar to the mode from which LPM3 is entered. */
+#define LPMR__LPM35                                        (0x000000a0)          /* LPM3.5. Core voltage setting 0. */
+#define LPMR__LPM45                                        (0x000000c0)          /* LPM4.5 */
+/* PCMCTL0[CPM] Bits */
+#define CPM_OFS                                            ( 8)                  /* CPM Offset */
+#define CPM_M                                              (0x00003f00)          /* Current Power Mode */
+#define CPM0                                               (0x00000100)          /* Current Power Mode */
+#define CPM1                                               (0x00000200)          /* Current Power Mode */
+#define CPM2                                               (0x00000400)          /* Current Power Mode */
+#define CPM3                                               (0x00000800)          /* Current Power Mode */
+#define CPM4                                               (0x00001000)          /* Current Power Mode */
+#define CPM5                                               (0x00002000)          /* Current Power Mode */
+#define CPM_0                                              (0x00000000)          /* LDO based Active Mode at Core voltage setting 0. */
+#define CPM_1                                              (0x00000100)          /* LDO based Active Mode at Core voltage setting 1. */
+#define CPM_4                                              (0x00000400)          /* DC-DC based Active Mode at Core voltage setting 0. */
+#define CPM_5                                              (0x00000500)          /* DC-DC based Active Mode at Core voltage setting 1. */
+#define CPM_8                                              (0x00000800)          /* Low-Frequency Active Mode at Core voltage setting 0. */
+#define CPM_9                                              (0x00000900)          /* Low-Frequency Active Mode at Core voltage setting 1. */
+#define CPM_16                                             (0x00001000)          /* LDO based LPM0 at Core voltage setting 0. */
+#define CPM_17                                             (0x00001100)          /* LDO based LPM0 at Core voltage setting 1. */
+#define CPM_20                                             (0x00001400)          /* DC-DC based LPM0 at Core voltage setting 0. */
+#define CPM_21                                             (0x00001500)          /* DC-DC based LPM0 at Core voltage setting 1. */
+#define CPM_24                                             (0x00001800)          /* Low-Frequency LPM0 at Core voltage setting 0. */
+#define CPM_25                                             (0x00001900)          /* Low-Frequency LPM0 at Core voltage setting 1. */
+#define CPM_32                                             (0x00002000)          /* LPM3 */
+#define CPM__AM_LDO_VCORE0                                 (0x00000000)          /* LDO based Active Mode at Core voltage setting 0. */
+#define CPM__AM_LDO_VCORE1                                 (0x00000100)          /* LDO based Active Mode at Core voltage setting 1. */
+#define CPM__AM_DCDC_VCORE0                                (0x00000400)          /* DC-DC based Active Mode at Core voltage setting 0. */
+#define CPM__AM_DCDC_VCORE1                                (0x00000500)          /* DC-DC based Active Mode at Core voltage setting 1. */
+#define CPM__AM_LF_VCORE0                                  (0x00000800)          /* Low-Frequency Active Mode at Core voltage setting 0. */
+#define CPM__AM_LF_VCORE1                                  (0x00000900)          /* Low-Frequency Active Mode at Core voltage setting 1. */
+#define CPM__LPM0_LDO_VCORE0                               (0x00001000)          /* LDO based LPM0 at Core voltage setting 0. */
+#define CPM__LPM0_LDO_VCORE1                               (0x00001100)          /* LDO based LPM0 at Core voltage setting 1. */
+#define CPM__LPM0_DCDC_VCORE0                              (0x00001400)          /* DC-DC based LPM0 at Core voltage setting 0. */
+#define CPM__LPM0_DCDC_VCORE1                              (0x00001500)          /* DC-DC based LPM0 at Core voltage setting 1. */
+#define CPM__LPM0_LF_VCORE0                                (0x00001800)          /* Low-Frequency LPM0 at Core voltage setting 0. */
+#define CPM__LPM0_LF_VCORE1                                (0x00001900)          /* Low-Frequency LPM0 at Core voltage setting 1. */
+#define CPM__LPM3                                          (0x00002000)          /* LPM3 */
+/* PCMCTL0[PCMKEY] Bits */
+#define PCMKEY_OFS                                         (16)                  /* PCMKEY Offset */
+#define PCMKEY_M                                           (0xffff0000)          /* PCM key */
+/* PCMCTL1[LOCKLPM5] Bits */
+#define LOCKLPM5_OFS                                       ( 0)                  /* LOCKLPM5 Offset */
+#define LOCKLPM5                                           (0x00000001)          /* Lock LPM5 */
+/* PCMCTL1[LOCKBKUP] Bits */
+#define LOCKBKUP_OFS                                       ( 1)                  /* LOCKBKUP Offset */
+#define LOCKBKUP                                           (0x00000002)          /* Lock Backup */
+/* PCMCTL1[FORCE_LPM_ENTRY] Bits */
+#define FORCE_LPM_ENTRY_OFS                                ( 2)                  /* FORCE_LPM_ENTRY Offset */
+#define FORCE_LPM_ENTRY                                    (0x00000004)          /* Force LPM entry */
+/* PCMCTL1[PMR_BUSY] Bits */
+#define PMR_BUSY_OFS                                       ( 8)                  /* PMR_BUSY Offset */
+#define PMR_BUSY                                           (0x00000100)          /* Power mode request busy flag */
+/* PCMCTL1[PCMKEY] Bits */
+//#define PCMKEY_OFS                                         (16)                  /* PCMKEY Offset */
+//#define PCMKEY_M                                           (0xffff0000)          /* PCM key */
+/* PCMIE[LPM_INVALID_TR_IE] Bits */
+#define LPM_INVALID_TR_IE_OFS                              ( 0)                  /* LPM_INVALID_TR_IE Offset */
+#define LPM_INVALID_TR_IE                                  (0x00000001)          /* LPM invalid transition interrupt enable */
+/* PCMIE[LPM_INVALID_CLK_IE] Bits */
+#define LPM_INVALID_CLK_IE_OFS                             ( 1)                  /* LPM_INVALID_CLK_IE Offset */
+#define LPM_INVALID_CLK_IE                                 (0x00000002)          /* LPM invalid clock interrupt enable */
+/* PCMIE[AM_INVALID_TR_IE] Bits */
+#define AM_INVALID_TR_IE_OFS                               ( 2)                  /* AM_INVALID_TR_IE Offset */
+#define AM_INVALID_TR_IE                                   (0x00000004)          /* Active mode invalid transition interrupt enable */
+/* PCMIE[DCDC_ERROR_IE] Bits */
+#define DCDC_ERROR_IE_OFS                                  ( 6)                  /* DCDC_ERROR_IE Offset */
+#define DCDC_ERROR_IE                                      (0x00000040)          /* DC-DC error interrupt enable */
+/* PCMIFG[LPM_INVALID_TR_IFG] Bits */
+#define LPM_INVALID_TR_IFG_OFS                             ( 0)                  /* LPM_INVALID_TR_IFG Offset */
+#define LPM_INVALID_TR_IFG                                 (0x00000001)          /* LPM invalid transition flag */
+/* PCMIFG[LPM_INVALID_CLK_IFG] Bits */
+#define LPM_INVALID_CLK_IFG_OFS                            ( 1)                  /* LPM_INVALID_CLK_IFG Offset */
+#define LPM_INVALID_CLK_IFG                                (0x00000002)          /* LPM invalid clock flag */
+/* PCMIFG[AM_INVALID_TR_IFG] Bits */
+#define AM_INVALID_TR_IFG_OFS                              ( 2)                  /* AM_INVALID_TR_IFG Offset */
+#define AM_INVALID_TR_IFG                                  (0x00000004)          /* Active mode invalid transition flag */
+/* PCMIFG[DCDC_ERROR_IFG] Bits */
+#define DCDC_ERROR_IFG_OFS                                 ( 6)                  /* DCDC_ERROR_IFG Offset */
+#define DCDC_ERROR_IFG                                     (0x00000040)          /* DC-DC error flag */
+/* PCMCLRIFG[CLR_LPM_INVALID_TR_IFG] Bits */
+#define CLR_LPM_INVALID_TR_IFG_OFS                         ( 0)                  /* CLR_LPM_INVALID_TR_IFG Offset */
+#define CLR_LPM_INVALID_TR_IFG                             (0x00000001)          /* Clear LPM invalid transition flag */
+/* PCMCLRIFG[CLR_LPM_INVALID_CLK_IFG] Bits */
+#define CLR_LPM_INVALID_CLK_IFG_OFS                        ( 1)                  /* CLR_LPM_INVALID_CLK_IFG Offset */
+#define CLR_LPM_INVALID_CLK_IFG                            (0x00000002)          /* Clear LPM invalid clock flag */
+/* PCMCLRIFG[CLR_AM_INVALID_TR_IFG] Bits */
+#define CLR_AM_INVALID_TR_IFG_OFS                          ( 2)                  /* CLR_AM_INVALID_TR_IFG Offset */
+#define CLR_AM_INVALID_TR_IFG                              (0x00000004)          /* Clear active mode invalid transition flag */
+/* PCMCLRIFG[CLR_DCDC_ERROR_IFG] Bits */
+#define CLR_DCDC_ERROR_IFG_OFS                             ( 6)                  /* CLR_DCDC_ERROR_IFG Offset */
+#define CLR_DCDC_ERROR_IFG                                 (0x00000040)          /* Clear DC-DC error flag */
+
+/* Pre-defined bitfield values */
+#define PCM_PMR_KEY_VAL                                    (0x695A0000)          /* PCM key value */
+#define PCM_CTL_KEY_VAL                                    (0x695A0000)          /* PCM key value */
+
+
+//*****************************************************************************
+// PMAP Bits
+//*****************************************************************************
+/* PMAPCTL[PMAPLOCKED] Bits */
+#define PMAPLOCKED_OFS                                     ( 0)                  /* PMAPLOCKED Offset */
+#define PMAPLOCKED                                         (0x0001)              /* Port mapping lock bit */
+/* PMAPCTL[PMAPRECFG] Bits */
+#define PMAPRECFG_OFS                                      ( 1)                  /* PMAPRECFG Offset */
+#define PMAPRECFG                                          (0x0002)              /* Port mapping reconfiguration control bit */
+
+/* Pre-defined bitfield values */
+#define PM_NONE                                            0
+#define PM_UCA0CLK                                         1
+#define PM_UCA0RXD                                         2
+#define PM_UCA0SOMI                                        2
+#define PM_UCA0TXD                                         3
+#define PM_UCA0SIMO                                        3
+#define PM_UCB0CLK                                         4
+#define PM_UCB0SDA                                         5
+#define PM_UCB0SIMO                                        5
+#define PM_UCB0SCL                                         6
+#define PM_UCB0SOMI                                        6
+#define PM_UCA1STE                                         7 
+#define PM_UCA1CLK                                         8
+#define PM_UCA1RXD                                         9
+#define PM_UCA1SOMI                                        9
+#define PM_UCA1TXD                                         10
+#define PM_UCA1SIMO                                        10
+#define PM_UCA2STE                                         11
+#define PM_UCA2CLK                                         12
+#define PM_UCA2RXD                                         13
+#define PM_UCA2SOMI                                        13
+#define PM_UCA2TXD                                         14
+#define PM_UCA2SIMO                                        14
+#define PM_UCB2STE                                         15
+#define PM_UCB2CLK                                         16
+#define PM_UCB2SDA                                         17
+#define PM_UCB2SIMO                                        17
+#define PM_UCB2SCL                                         18
+#define PM_UCB2SOMI                                        18
+#define PM_TA0CCR0A                                        19
+#define PM_TA0CCR1A                                        20
+#define PM_TA0CCR2A                                        21
+#define PM_TA0CCR3A                                        22
+#define PM_TA0CCR4A                                        23
+#define PM_TA1CCR1A                                        24
+#define PM_TA1CCR2A                                        25
+#define PM_TA1CCR3A                                        26
+#define PM_TA1CCR4A                                        27
+#define PM_TA0CLK                                          28
+#define PM_CE0OUT                                          28
+#define PM_TA1CLK                                          29
+#define PM_CE1OUT                                          29
+#define PM_DMAE0                                           30
+#define PM_SMCLK                                           30
+#define PM_ANALOG                                          31
+
+#define PMAP_KEYID_VAL                                     (0x2D52)              /* Port mapping controller write access key */
+ 
+
+//*****************************************************************************
+// PSS Bits
+//*****************************************************************************
+/* PSSKEY[PSSKEY] Bits */
+#define PSSKEY_OFS                                         ( 0)                  /* PSSKEY Offset */
+#define PSSKEY_M                                           (0x0000ffff)          /* PSS control key */
+/* PSSCTL0[SVSMHOFF] Bits */
+#define SVSMHOFF_OFS                                       ( 0)                  /* SVSMHOFF Offset */
+#define SVSMHOFF                                           (0x00000001)          /* SVSM high-side off */
+/* PSSCTL0[SVSMHLP] Bits */
+#define SVSMHLP_OFS                                        ( 1)                  /* SVSMHLP Offset */
+#define SVSMHLP                                            (0x00000002)          /* SVSM high-side low power normal performance mode */
+/* PSSCTL0[SVSMHS] Bits */
+#define SVSMHS_OFS                                         ( 2)                  /* SVSMHS Offset */
+#define SVSMHS                                             (0x00000004)          /* Supply supervisor or monitor selection for the high-side */
+/* PSSCTL0[SVSMHTH] Bits */
+#define SVSMHTH_OFS                                        ( 3)                  /* SVSMHTH Offset */
+#define SVSMHTH_M                                          (0x00000038)          /* SVSM high-side reset voltage level */
+/* PSSCTL0[SVMHOE] Bits */
+#define SVMHOE_OFS                                         ( 6)                  /* SVMHOE Offset */
+#define SVMHOE                                             (0x00000040)          /* SVSM high-side output enable */
+/* PSSCTL0[SVMHOUTPOLAL] Bits */
+#define SVMHOUTPOLAL_OFS                                   ( 7)                  /* SVMHOUTPOLAL Offset */
+#define SVMHOUTPOLAL                                       (0x00000080)          /* SVMHOUT pin polarity active low */
+/* PSSCTL0[SVSLOFF] Bits */
+#define SVSLOFF_OFS                                        ( 8)                  /* SVSLOFF Offset */
+#define SVSLOFF                                            (0x00000100)          /* SVS low-side off */
+/* PSSCTL0[SVSLLP] Bits */
+#define SVSLLP_OFS                                         ( 9)                  /* SVSLLP Offset */
+#define SVSLLP                                             (0x00000200)          /* SVS low-side low power normal performance mode */
+/* PSSCTL0[DCDC_FORCE] Bits */
+#define DCDC_FORCE_OFS                                     (10)                  /* DCDC_FORCE Offset */
+#define DCDC_FORCE                                         (0x00000400)          /* Disables automatic supply voltage detection */
+/* PSSCTL0[VCORETRAN] Bits */
+#define VCORETRAN_OFS                                      (12)                  /* VCORETRAN Offset */
+#define VCORETRAN_M                                        (0x00003000)          /* Controls VCORE Level Transition time */
+#define VCORETRAN0                                         (0x00001000)          /* Controls VCORE Level Transition time */
+#define VCORETRAN1                                         (0x00002000)          /* Controls VCORE Level Transition time */
+#define VCORETRAN_0                                        (0x00000000)          /* 32 ?s / 100 mV */
+#define VCORETRAN_1                                        (0x00001000)          /* 64 ?s / 100 mV */
+#define VCORETRAN_2                                        (0x00002000)          /* 128 ?s / 100 mV (default) */
+#define VCORETRAN_3                                        (0x00003000)          /* 256 ?s / 100 mV */
+#define VCORETRAN__32                                      (0x00000000)          /* 32 ?s / 100 mV */
+#define VCORETRAN__64                                      (0x00001000)          /* 64 ?s / 100 mV */
+#define VCORETRAN__128                                     (0x00002000)          /* 128 ?s / 100 mV (default) */
+#define VCORETRAN__256                                     (0x00003000)          /* 256 ?s / 100 mV */
+/* PSSIE[SVSMHIE] Bits */
+#define SVSMHIE_OFS                                        ( 1)                  /* SVSMHIE Offset */
+#define SVSMHIE                                            (0x00000002)          /* High-side SVSM interrupt enable */
+/* PSSIFG[SVSMHIFG] Bits */
+#define SVSMHIFG_OFS                                       ( 1)                  /* SVSMHIFG Offset */
+#define SVSMHIFG                                           (0x00000002)          /* High-side SVSM interrupt flag */
+/* PSSCLRIFG[CLRSVSMHIFG] Bits */
+#define CLRSVSMHIFG_OFS                                    ( 1)                  /* CLRSVSMHIFG Offset */
+#define CLRSVSMHIFG                                        (0x00000002)          /* SVSMH clear interrupt flag */
+
+/* Pre-defined bitfield values */
+#define PSS_KEY_KEY_VAL                                    (0x0000695A)          /* PSS control key value */
+
+
+//*****************************************************************************
+// REF_A Bits
+//*****************************************************************************
+/* REFCTL0[REFON] Bits */
+#define REFON_OFS                                          ( 0)                  /* REFON Offset */
+#define REFON                                              (0x0001)              /* Reference enable */
+/* REFCTL0[REFOUT] Bits */
+#define REFOUT_OFS                                         ( 1)                  /* REFOUT Offset */
+#define REFOUT                                             (0x0002)              /* Reference output buffer */
+/* REFCTL0[REFTCOFF] Bits */
+#define REFTCOFF_OFS                                       ( 3)                  /* REFTCOFF Offset */
+#define REFTCOFF                                           (0x0008)              /* Temperature sensor disabled */
+/* REFCTL0[REFVSEL] Bits */
+#define REFVSEL_OFS                                        ( 4)                  /* REFVSEL Offset */
+#define REFVSEL_M                                          (0x0030)              /* Reference voltage level select */
+#define REFVSEL0                                           (0x0010)              /* Reference voltage level select */
+#define REFVSEL1                                           (0x0020)              /* Reference voltage level select */
+#define REFVSEL_0                                          (0x0000)              /* 1.2 V available when reference requested or REFON = 1 */
+#define REFVSEL_1                                          (0x0010)              /* 1.45 V available when reference requested or REFON = 1 */
+#define REFVSEL_3                                          (0x0030)              /* 2.5 V available when reference requested or REFON = 1 */
+/* REFCTL0[REFGENOT] Bits */
+#define REFGENOT_OFS                                       ( 6)                  /* REFGENOT Offset */
+#define REFGENOT                                           (0x0040)              /* Reference generator one-time trigger */
+/* REFCTL0[REFBGOT] Bits */
+#define REFBGOT_OFS                                        ( 7)                  /* REFBGOT Offset */
+#define REFBGOT                                            (0x0080)              /* Bandgap and bandgap buffer one-time trigger */
+/* REFCTL0[REFGENACT] Bits */
+#define REFGENACT_OFS                                      ( 8)                  /* REFGENACT Offset */
+#define REFGENACT                                          (0x0100)              /* Reference generator active */
+/* REFCTL0[REFBGACT] Bits */
+#define REFBGACT_OFS                                       ( 9)                  /* REFBGACT Offset */
+#define REFBGACT                                           (0x0200)              /* Reference bandgap active */
+/* REFCTL0[REFGENBUSY] Bits */
+#define REFGENBUSY_OFS                                     (10)                  /* REFGENBUSY Offset */
+#define REFGENBUSY                                         (0x0400)              /* Reference generator busy */
+/* REFCTL0[BGMODE] Bits */
+#define BGMODE_OFS                                         (11)                  /* BGMODE Offset */
+#define BGMODE                                             (0x0800)              /* Bandgap mode */
+/* REFCTL0[REFGENRDY] Bits */
+#define REFGENRDY_OFS                                      (12)                  /* REFGENRDY Offset */
+#define REFGENRDY                                          (0x1000)              /* Variable reference voltage ready status */
+/* REFCTL0[REFBGRDY] Bits */
+#define REFBGRDY_OFS                                       (13)                  /* REFBGRDY Offset */
+#define REFBGRDY                                           (0x2000)              /* Buffered bandgap voltage ready status */
+
+
+//*****************************************************************************
+// RSTCTL Bits
+//*****************************************************************************
+/* RSTCTL_RESET_REQ[RSTCTL_RESET_REQ_SOFT_REQ] Bits */
+#define RSTCTL_RESET_REQ_SOFT_REQ_OFS                      ( 0)                  /* SOFT_REQ Offset */
+#define RSTCTL_RESET_REQ_SOFT_REQ                          (0x00000001)          /* Soft Reset request */
+/* RSTCTL_RESET_REQ[RSTCTL_RESET_REQ_HARD_REQ] Bits */
+#define RSTCTL_RESET_REQ_HARD_REQ_OFS                      ( 1)                  /* HARD_REQ Offset */
+#define RSTCTL_RESET_REQ_HARD_REQ                          (0x00000002)          /* Hard Reset request */
+/* RSTCTL_RESET_REQ[RSTCTL_RESET_REQ_RSTKEY] Bits */
+#define RSTCTL_RESET_REQ_RSTKEY_OFS                        ( 8)                  /* RSTKEY Offset */
+#define RSTCTL_RESET_REQ_RSTKEY_M                          (0x0000ff00)          /* Write key to unlock reset request bits */
+/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC0] Bits */
+#define RSTCTL_HARDRESET_CLR_SRC0_OFS                      ( 0)                  /* SRC0 Offset */
+#define RSTCTL_HARDRESET_CLR_SRC0                          (0x00000001)          /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC1] Bits */
+#define RSTCTL_HARDRESET_CLR_SRC1_OFS                      ( 1)                  /* SRC1 Offset */
+#define RSTCTL_HARDRESET_CLR_SRC1                          (0x00000002)          /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC2] Bits */
+#define RSTCTL_HARDRESET_CLR_SRC2_OFS                      ( 2)                  /* SRC2 Offset */
+#define RSTCTL_HARDRESET_CLR_SRC2                          (0x00000004)          /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC3] Bits */
+#define RSTCTL_HARDRESET_CLR_SRC3_OFS                      ( 3)                  /* SRC3 Offset */
+#define RSTCTL_HARDRESET_CLR_SRC3                          (0x00000008)          /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC4] Bits */
+#define RSTCTL_HARDRESET_CLR_SRC4_OFS                      ( 4)                  /* SRC4 Offset */
+#define RSTCTL_HARDRESET_CLR_SRC4                          (0x00000010)          /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC5] Bits */
+#define RSTCTL_HARDRESET_CLR_SRC5_OFS                      ( 5)                  /* SRC5 Offset */
+#define RSTCTL_HARDRESET_CLR_SRC5                          (0x00000020)          /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC6] Bits */
+#define RSTCTL_HARDRESET_CLR_SRC6_OFS                      ( 6)                  /* SRC6 Offset */
+#define RSTCTL_HARDRESET_CLR_SRC6                          (0x00000040)          /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC7] Bits */
+#define RSTCTL_HARDRESET_CLR_SRC7_OFS                      ( 7)                  /* SRC7 Offset */
+#define RSTCTL_HARDRESET_CLR_SRC7                          (0x00000080)          /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC8] Bits */
+#define RSTCTL_HARDRESET_CLR_SRC8_OFS                      ( 8)                  /* SRC8 Offset */
+#define RSTCTL_HARDRESET_CLR_SRC8                          (0x00000100)          /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT  */
+/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC9] Bits */
+#define RSTCTL_HARDRESET_CLR_SRC9_OFS                      ( 9)                  /* SRC9 Offset */
+#define RSTCTL_HARDRESET_CLR_SRC9                          (0x00000200)          /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC10] Bits */
+#define RSTCTL_HARDRESET_CLR_SRC10_OFS                     (10)                  /* SRC10 Offset */
+#define RSTCTL_HARDRESET_CLR_SRC10                         (0x00000400)          /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC11] Bits */
+#define RSTCTL_HARDRESET_CLR_SRC11_OFS                     (11)                  /* SRC11 Offset */
+#define RSTCTL_HARDRESET_CLR_SRC11                         (0x00000800)          /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC12] Bits */
+#define RSTCTL_HARDRESET_CLR_SRC12_OFS                     (12)                  /* SRC12 Offset */
+#define RSTCTL_HARDRESET_CLR_SRC12                         (0x00001000)          /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC13] Bits */
+#define RSTCTL_HARDRESET_CLR_SRC13_OFS                     (13)                  /* SRC13 Offset */
+#define RSTCTL_HARDRESET_CLR_SRC13                         (0x00002000)          /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC14] Bits */
+#define RSTCTL_HARDRESET_CLR_SRC14_OFS                     (14)                  /* SRC14 Offset */
+#define RSTCTL_HARDRESET_CLR_SRC14                         (0x00004000)          /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC15] Bits */
+#define RSTCTL_HARDRESET_CLR_SRC15_OFS                     (15)                  /* SRC15 Offset */
+#define RSTCTL_HARDRESET_CLR_SRC15                         (0x00008000)          /* Write 1 clears the corresponding bit in the RSTCTL_HRDRESETSTAT_REG */
+/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC0] Bits */
+#define RSTCTL_HARDRESET_SET_SRC0_OFS                      ( 0)                  /* SRC0 Offset */
+#define RSTCTL_HARDRESET_SET_SRC0                          (0x00000001)          /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
+/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC1] Bits */
+#define RSTCTL_HARDRESET_SET_SRC1_OFS                      ( 1)                  /* SRC1 Offset */
+#define RSTCTL_HARDRESET_SET_SRC1                          (0x00000002)          /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
+/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC2] Bits */
+#define RSTCTL_HARDRESET_SET_SRC2_OFS                      ( 2)                  /* SRC2 Offset */
+#define RSTCTL_HARDRESET_SET_SRC2                          (0x00000004)          /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
+/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC3] Bits */
+#define RSTCTL_HARDRESET_SET_SRC3_OFS                      ( 3)                  /* SRC3 Offset */
+#define RSTCTL_HARDRESET_SET_SRC3                          (0x00000008)          /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
+/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC4] Bits */
+#define RSTCTL_HARDRESET_SET_SRC4_OFS                      ( 4)                  /* SRC4 Offset */
+#define RSTCTL_HARDRESET_SET_SRC4                          (0x00000010)          /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
+/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC5] Bits */
+#define RSTCTL_HARDRESET_SET_SRC5_OFS                      ( 5)                  /* SRC5 Offset */
+#define RSTCTL_HARDRESET_SET_SRC5                          (0x00000020)          /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
+/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC6] Bits */
+#define RSTCTL_HARDRESET_SET_SRC6_OFS                      ( 6)                  /* SRC6 Offset */
+#define RSTCTL_HARDRESET_SET_SRC6                          (0x00000040)          /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
+/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC7] Bits */
+#define RSTCTL_HARDRESET_SET_SRC7_OFS                      ( 7)                  /* SRC7 Offset */
+#define RSTCTL_HARDRESET_SET_SRC7                          (0x00000080)          /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
+/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC8] Bits */
+#define RSTCTL_HARDRESET_SET_SRC8_OFS                      ( 8)                  /* SRC8 Offset */
+#define RSTCTL_HARDRESET_SET_SRC8                          (0x00000100)          /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
+/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC9] Bits */
+#define RSTCTL_HARDRESET_SET_SRC9_OFS                      ( 9)                  /* SRC9 Offset */
+#define RSTCTL_HARDRESET_SET_SRC9                          (0x00000200)          /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
+/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC10] Bits */
+#define RSTCTL_HARDRESET_SET_SRC10_OFS                     (10)                  /* SRC10 Offset */
+#define RSTCTL_HARDRESET_SET_SRC10                         (0x00000400)          /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
+/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC11] Bits */
+#define RSTCTL_HARDRESET_SET_SRC11_OFS                     (11)                  /* SRC11 Offset */
+#define RSTCTL_HARDRESET_SET_SRC11                         (0x00000800)          /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
+/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC12] Bits */
+#define RSTCTL_HARDRESET_SET_SRC12_OFS                     (12)                  /* SRC12 Offset */
+#define RSTCTL_HARDRESET_SET_SRC12                         (0x00001000)          /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
+/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC13] Bits */
+#define RSTCTL_HARDRESET_SET_SRC13_OFS                     (13)                  /* SRC13 Offset */
+#define RSTCTL_HARDRESET_SET_SRC13                         (0x00002000)          /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
+/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC14] Bits */
+#define RSTCTL_HARDRESET_SET_SRC14_OFS                     (14)                  /* SRC14 Offset */
+#define RSTCTL_HARDRESET_SET_SRC14                         (0x00004000)          /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
+/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC15] Bits */
+#define RSTCTL_HARDRESET_SET_SRC15_OFS                     (15)                  /* SRC15 Offset */
+#define RSTCTL_HARDRESET_SET_SRC15                         (0x00008000)          /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
+/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC0] Bits */
+#define RSTCTL_SOFTRESET_STAT_SRC0_OFS                     ( 0)                  /* SRC0 Offset */
+#define RSTCTL_SOFTRESET_STAT_SRC0                         (0x00000001)          /* If 1, indicates that SRC0 was the source of the Soft Reset */
+/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC1] Bits */
+#define RSTCTL_SOFTRESET_STAT_SRC1_OFS                     ( 1)                  /* SRC1 Offset */
+#define RSTCTL_SOFTRESET_STAT_SRC1                         (0x00000002)          /* If 1, indicates that SRC1 was the source of the Soft Reset */
+/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC2] Bits */
+#define RSTCTL_SOFTRESET_STAT_SRC2_OFS                     ( 2)                  /* SRC2 Offset */
+#define RSTCTL_SOFTRESET_STAT_SRC2                         (0x00000004)          /* If 1, indicates that SRC2 was the source of the Soft Reset */
+/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC3] Bits */
+#define RSTCTL_SOFTRESET_STAT_SRC3_OFS                     ( 3)                  /* SRC3 Offset */
+#define RSTCTL_SOFTRESET_STAT_SRC3                         (0x00000008)          /* If 1, indicates that SRC3 was the source of the Soft Reset */
+/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC4] Bits */
+#define RSTCTL_SOFTRESET_STAT_SRC4_OFS                     ( 4)                  /* SRC4 Offset */
+#define RSTCTL_SOFTRESET_STAT_SRC4                         (0x00000010)          /* If 1, indicates that SRC4 was the source of the Soft Reset */
+/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC5] Bits */
+#define RSTCTL_SOFTRESET_STAT_SRC5_OFS                     ( 5)                  /* SRC5 Offset */
+#define RSTCTL_SOFTRESET_STAT_SRC5                         (0x00000020)          /* If 1, indicates that SRC5 was the source of the Soft Reset */
+/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC6] Bits */
+#define RSTCTL_SOFTRESET_STAT_SRC6_OFS                     ( 6)                  /* SRC6 Offset */
+#define RSTCTL_SOFTRESET_STAT_SRC6                         (0x00000040)          /* If 1, indicates that SRC6 was the source of the Soft Reset */
+/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC7] Bits */
+#define RSTCTL_SOFTRESET_STAT_SRC7_OFS                     ( 7)                  /* SRC7 Offset */
+#define RSTCTL_SOFTRESET_STAT_SRC7                         (0x00000080)          /* If 1, indicates that SRC7 was the source of the Soft Reset */
+/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC8] Bits */
+#define RSTCTL_SOFTRESET_STAT_SRC8_OFS                     ( 8)                  /* SRC8 Offset */
+#define RSTCTL_SOFTRESET_STAT_SRC8                         (0x00000100)          /* If 1, indicates that SRC8 was the source of the Soft Reset */
+/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC9] Bits */
+#define RSTCTL_SOFTRESET_STAT_SRC9_OFS                     ( 9)                  /* SRC9 Offset */
+#define RSTCTL_SOFTRESET_STAT_SRC9                         (0x00000200)          /* If 1, indicates that SRC9 was the source of the Soft Reset */
+/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC10] Bits */
+#define RSTCTL_SOFTRESET_STAT_SRC10_OFS                    (10)                  /* SRC10 Offset */
+#define RSTCTL_SOFTRESET_STAT_SRC10                        (0x00000400)          /* If 1, indicates that SRC10 was the source of the Soft Reset */
+/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC11] Bits */
+#define RSTCTL_SOFTRESET_STAT_SRC11_OFS                    (11)                  /* SRC11 Offset */
+#define RSTCTL_SOFTRESET_STAT_SRC11                        (0x00000800)          /* If 1, indicates that SRC11 was the source of the Soft Reset */
+/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC12] Bits */
+#define RSTCTL_SOFTRESET_STAT_SRC12_OFS                    (12)                  /* SRC12 Offset */
+#define RSTCTL_SOFTRESET_STAT_SRC12                        (0x00001000)          /* If 1, indicates that SRC12 was the source of the Soft Reset */
+/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC13] Bits */
+#define RSTCTL_SOFTRESET_STAT_SRC13_OFS                    (13)                  /* SRC13 Offset */
+#define RSTCTL_SOFTRESET_STAT_SRC13                        (0x00002000)          /* If 1, indicates that SRC13 was the source of the Soft Reset */
+/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC14] Bits */
+#define RSTCTL_SOFTRESET_STAT_SRC14_OFS                    (14)                  /* SRC14 Offset */
+#define RSTCTL_SOFTRESET_STAT_SRC14                        (0x00004000)          /* If 1, indicates that SRC14 was the source of the Soft Reset */
+/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC15] Bits */
+#define RSTCTL_SOFTRESET_STAT_SRC15_OFS                    (15)                  /* SRC15 Offset */
+#define RSTCTL_SOFTRESET_STAT_SRC15                        (0x00008000)          /* If 1, indicates that SRC15 was the source of the Soft Reset */
+/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC0] Bits */
+#define RSTCTL_SOFTRESET_CLR_SRC0_OFS                      ( 0)                  /* SRC0 Offset */
+#define RSTCTL_SOFTRESET_CLR_SRC0                          (0x00000001)          /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC1] Bits */
+#define RSTCTL_SOFTRESET_CLR_SRC1_OFS                      ( 1)                  /* SRC1 Offset */
+#define RSTCTL_SOFTRESET_CLR_SRC1                          (0x00000002)          /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC2] Bits */
+#define RSTCTL_SOFTRESET_CLR_SRC2_OFS                      ( 2)                  /* SRC2 Offset */
+#define RSTCTL_SOFTRESET_CLR_SRC2                          (0x00000004)          /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC3] Bits */
+#define RSTCTL_SOFTRESET_CLR_SRC3_OFS                      ( 3)                  /* SRC3 Offset */
+#define RSTCTL_SOFTRESET_CLR_SRC3                          (0x00000008)          /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC4] Bits */
+#define RSTCTL_SOFTRESET_CLR_SRC4_OFS                      ( 4)                  /* SRC4 Offset */
+#define RSTCTL_SOFTRESET_CLR_SRC4                          (0x00000010)          /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC5] Bits */
+#define RSTCTL_SOFTRESET_CLR_SRC5_OFS                      ( 5)                  /* SRC5 Offset */
+#define RSTCTL_SOFTRESET_CLR_SRC5                          (0x00000020)          /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC6] Bits */
+#define RSTCTL_SOFTRESET_CLR_SRC6_OFS                      ( 6)                  /* SRC6 Offset */
+#define RSTCTL_SOFTRESET_CLR_SRC6                          (0x00000040)          /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC7] Bits */
+#define RSTCTL_SOFTRESET_CLR_SRC7_OFS                      ( 7)                  /* SRC7 Offset */
+#define RSTCTL_SOFTRESET_CLR_SRC7                          (0x00000080)          /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC8] Bits */
+#define RSTCTL_SOFTRESET_CLR_SRC8_OFS                      ( 8)                  /* SRC8 Offset */
+#define RSTCTL_SOFTRESET_CLR_SRC8                          (0x00000100)          /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC9] Bits */
+#define RSTCTL_SOFTRESET_CLR_SRC9_OFS                      ( 9)                  /* SRC9 Offset */
+#define RSTCTL_SOFTRESET_CLR_SRC9                          (0x00000200)          /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC10] Bits */
+#define RSTCTL_SOFTRESET_CLR_SRC10_OFS                     (10)                  /* SRC10 Offset */
+#define RSTCTL_SOFTRESET_CLR_SRC10                         (0x00000400)          /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC11] Bits */
+#define RSTCTL_SOFTRESET_CLR_SRC11_OFS                     (11)                  /* SRC11 Offset */
+#define RSTCTL_SOFTRESET_CLR_SRC11                         (0x00000800)          /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC12] Bits */
+#define RSTCTL_SOFTRESET_CLR_SRC12_OFS                     (12)                  /* SRC12 Offset */
+#define RSTCTL_SOFTRESET_CLR_SRC12                         (0x00001000)          /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC13] Bits */
+#define RSTCTL_SOFTRESET_CLR_SRC13_OFS                     (13)                  /* SRC13 Offset */
+#define RSTCTL_SOFTRESET_CLR_SRC13                         (0x00002000)          /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC14] Bits */
+#define RSTCTL_SOFTRESET_CLR_SRC14_OFS                     (14)                  /* SRC14 Offset */
+#define RSTCTL_SOFTRESET_CLR_SRC14                         (0x00004000)          /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC15] Bits */
+#define RSTCTL_SOFTRESET_CLR_SRC15_OFS                     (15)                  /* SRC15 Offset */
+#define RSTCTL_SOFTRESET_CLR_SRC15                         (0x00008000)          /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC0] Bits */
+#define RSTCTL_SOFTRESET_SET_SRC0_OFS                      ( 0)                  /* SRC0 Offset */
+#define RSTCTL_SOFTRESET_SET_SRC0                          (0x00000001)          /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
+/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC1] Bits */
+#define RSTCTL_SOFTRESET_SET_SRC1_OFS                      ( 1)                  /* SRC1 Offset */
+#define RSTCTL_SOFTRESET_SET_SRC1                          (0x00000002)          /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
+/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC2] Bits */
+#define RSTCTL_SOFTRESET_SET_SRC2_OFS                      ( 2)                  /* SRC2 Offset */
+#define RSTCTL_SOFTRESET_SET_SRC2                          (0x00000004)          /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
+/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC3] Bits */
+#define RSTCTL_SOFTRESET_SET_SRC3_OFS                      ( 3)                  /* SRC3 Offset */
+#define RSTCTL_SOFTRESET_SET_SRC3                          (0x00000008)          /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
+/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC4] Bits */
+#define RSTCTL_SOFTRESET_SET_SRC4_OFS                      ( 4)                  /* SRC4 Offset */
+#define RSTCTL_SOFTRESET_SET_SRC4                          (0x00000010)          /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
+/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC5] Bits */
+#define RSTCTL_SOFTRESET_SET_SRC5_OFS                      ( 5)                  /* SRC5 Offset */
+#define RSTCTL_SOFTRESET_SET_SRC5                          (0x00000020)          /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
+/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC6] Bits */
+#define RSTCTL_SOFTRESET_SET_SRC6_OFS                      ( 6)                  /* SRC6 Offset */
+#define RSTCTL_SOFTRESET_SET_SRC6                          (0x00000040)          /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
+/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC7] Bits */
+#define RSTCTL_SOFTRESET_SET_SRC7_OFS                      ( 7)                  /* SRC7 Offset */
+#define RSTCTL_SOFTRESET_SET_SRC7                          (0x00000080)          /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
+/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC8] Bits */
+#define RSTCTL_SOFTRESET_SET_SRC8_OFS                      ( 8)                  /* SRC8 Offset */
+#define RSTCTL_SOFTRESET_SET_SRC8                          (0x00000100)          /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
+/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC9] Bits */
+#define RSTCTL_SOFTRESET_SET_SRC9_OFS                      ( 9)                  /* SRC9 Offset */
+#define RSTCTL_SOFTRESET_SET_SRC9                          (0x00000200)          /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
+/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC10] Bits */
+#define RSTCTL_SOFTRESET_SET_SRC10_OFS                     (10)                  /* SRC10 Offset */
+#define RSTCTL_SOFTRESET_SET_SRC10                         (0x00000400)          /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
+/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC11] Bits */
+#define RSTCTL_SOFTRESET_SET_SRC11_OFS                     (11)                  /* SRC11 Offset */
+#define RSTCTL_SOFTRESET_SET_SRC11                         (0x00000800)          /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
+/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC12] Bits */
+#define RSTCTL_SOFTRESET_SET_SRC12_OFS                     (12)                  /* SRC12 Offset */
+#define RSTCTL_SOFTRESET_SET_SRC12                         (0x00001000)          /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
+/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC13] Bits */
+#define RSTCTL_SOFTRESET_SET_SRC13_OFS                     (13)                  /* SRC13 Offset */
+#define RSTCTL_SOFTRESET_SET_SRC13                         (0x00002000)          /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
+/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC14] Bits */
+#define RSTCTL_SOFTRESET_SET_SRC14_OFS                     (14)                  /* SRC14 Offset */
+#define RSTCTL_SOFTRESET_SET_SRC14                         (0x00004000)          /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
+/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC15] Bits */
+#define RSTCTL_SOFTRESET_SET_SRC15_OFS                     (15)                  /* SRC15 Offset */
+#define RSTCTL_SOFTRESET_SET_SRC15                         (0x00008000)          /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
+/* RSTCTL_PSSRESET_STAT[RSTCTL_PSSRESET_STAT_SVSL] Bits */
+#define RSTCTL_PSSRESET_STAT_SVSL_OFS                      ( 0)                  /* SVSL Offset */
+#define RSTCTL_PSSRESET_STAT_SVSL                          (0x00000001)          /* Indicates if POR was caused by an SVSL trip condition in the PSS */
+/* RSTCTL_PSSRESET_STAT[RSTCTL_PSSRESET_STAT_SVSMH] Bits */
+#define RSTCTL_PSSRESET_STAT_SVSMH_OFS                     ( 1)                  /* SVSMH Offset */
+#define RSTCTL_PSSRESET_STAT_SVSMH                         (0x00000002)          /* Indicates if POR was caused by an SVSMH trip condition int the PSS */
+/* RSTCTL_PSSRESET_STAT[RSTCTL_PSSRESET_STAT_BGREF] Bits */
+#define RSTCTL_PSSRESET_STAT_BGREF_OFS                     ( 2)                  /* BGREF Offset */
+#define RSTCTL_PSSRESET_STAT_BGREF                         (0x00000004)          /* Indicates if POR was caused by a BGREF not okay condition in the PSS */
+/* RSTCTL_PSSRESET_STAT[RSTCTL_PSSRESET_STAT_VCCDET] Bits */
+#define RSTCTL_PSSRESET_STAT_VCCDET_OFS                    ( 3)                  /* VCCDET Offset */
+#define RSTCTL_PSSRESET_STAT_VCCDET                        (0x00000008)          /* Indicates if POR was caused by a VCCDET trip condition in the PSS */
+/* RSTCTL_PSSRESET_CLR[RSTCTL_PSSRESET_CLR_CLR] Bits */
+#define RSTCTL_PSSRESET_CLR_CLR_OFS                        ( 0)                  /* CLR Offset */
+#define RSTCTL_PSSRESET_CLR_CLR                            (0x00000001)          /* Write 1 clears all PSS Reset Flags in the RSTCTL_PSSRESET_STAT */
+/* RSTCTL_PCMRESET_STAT[RSTCTL_PCMRESET_STAT_LPM35] Bits */
+#define RSTCTL_PCMRESET_STAT_LPM35_OFS                     ( 0)                  /* LPM35 Offset */
+#define RSTCTL_PCMRESET_STAT_LPM35                         (0x00000001)          /* Indicates if POR was caused by PCM due to an exit from LPM3.5 */
+/* RSTCTL_PCMRESET_STAT[RSTCTL_PCMRESET_STAT_LPM45] Bits */
+#define RSTCTL_PCMRESET_STAT_LPM45_OFS                     ( 1)                  /* LPM45 Offset */
+#define RSTCTL_PCMRESET_STAT_LPM45                         (0x00000002)          /* Indicates if POR was caused by PCM due to an exit from LPM4.5 */
+/* RSTCTL_PCMRESET_CLR[RSTCTL_PCMRESET_CLR_CLR] Bits */
+#define RSTCTL_PCMRESET_CLR_CLR_OFS                        ( 0)                  /* CLR Offset */
+#define RSTCTL_PCMRESET_CLR_CLR                            (0x00000001)          /* Write 1 clears all PCM Reset Flags in the RSTCTL_PCMRESET_STAT */
+/* RSTCTL_PINRESET_STAT[RSTCTL_PINRESET_STAT_RSTNMI] Bits */
+#define RSTCTL_PINRESET_STAT_RSTNMI_OFS                    ( 0)                  /* RSTNMI Offset */
+#define RSTCTL_PINRESET_STAT_RSTNMI                        (0x00000001)          /* POR was caused by RSTn/NMI pin based reset event */
+/* RSTCTL_PINRESET_CLR[RSTCTL_PINRESET_CLR_CLR] Bits */
+#define RSTCTL_PINRESET_CLR_CLR_OFS                        ( 0)                  /* CLR Offset */
+#define RSTCTL_PINRESET_CLR_CLR                            (0x00000001)          /* Write 1 clears the RSTn/NMI Pin Reset Flag in RSTCTL_PINRESET_STAT */
+/* RSTCTL_REBOOTRESET_STAT[RSTCTL_REBOOTRESET_STAT_REBOOT] Bits */
+#define RSTCTL_REBOOTRESET_STAT_REBOOT_OFS                 ( 0)                  /* REBOOT Offset */
+#define RSTCTL_REBOOTRESET_STAT_REBOOT                     (0x00000001)          /* Indicates if Reboot reset was caused by the SYSCTL module. */
+/* RSTCTL_REBOOTRESET_CLR[RSTCTL_REBOOTRESET_CLR_CLR] Bits */
+#define RSTCTL_REBOOTRESET_CLR_CLR_OFS                     ( 0)                  /* CLR Offset */
+#define RSTCTL_REBOOTRESET_CLR_CLR                         (0x00000001)          /* Write 1 clears the Reboot Reset Flag in RSTCTL_REBOOTRESET_STAT */
+
+/* Pre-defined bitfield values */
+#define RSTCTL_RESETREQ_RSTKEY_VAL                         (0x00006900)          /* Key value to enable writes to bits 1-0 */
+
+
+//*****************************************************************************
+// RTC_C Bits
+//*****************************************************************************
+/* RTCCTL0[RTCRDYIFG] Bits */
+#define RTCRDYIFG_OFS                                      ( 0)                  /* RTCRDYIFG Offset */
+#define RTCRDYIFG                                          (0x0001)              /* Real-time clock ready interrupt flag */
+/* RTCCTL0[RTCAIFG] Bits */
+#define RTCAIFG_OFS                                        ( 1)                  /* RTCAIFG Offset */
+#define RTCAIFG                                            (0x0002)              /* Real-time clock alarm interrupt flag */
+/* RTCCTL0[RTCTEVIFG] Bits */
+#define RTCTEVIFG_OFS                                      ( 2)                  /* RTCTEVIFG Offset */
+#define RTCTEVIFG                                          (0x0004)              /* Real-time clock time event interrupt flag */
+/* RTCCTL0[RTCOFIFG] Bits */
+#define RTCOFIFG_OFS                                       ( 3)                  /* RTCOFIFG Offset */
+#define RTCOFIFG                                           (0x0008)              /* 32-kHz crystal oscillator fault interrupt flag */
+/* RTCCTL0[RTCRDYIE] Bits */
+#define RTCRDYIE_OFS                                       ( 4)                  /* RTCRDYIE Offset */
+#define RTCRDYIE                                           (0x0010)              /* Real-time clock ready interrupt enable */
+/* RTCCTL0[RTCAIE] Bits */
+#define RTCAIE_OFS                                         ( 5)                  /* RTCAIE Offset */
+#define RTCAIE                                             (0x0020)              /* Real-time clock alarm interrupt enable */
+/* RTCCTL0[RTCTEVIE] Bits */
+#define RTCTEVIE_OFS                                       ( 6)                  /* RTCTEVIE Offset */
+#define RTCTEVIE                                           (0x0040)              /* Real-time clock time event interrupt enable */
+/* RTCCTL0[RTCOFIE] Bits */
+#define RTCOFIE_OFS                                        ( 7)                  /* RTCOFIE Offset */
+#define RTCOFIE                                            (0x0080)              /* 32-kHz crystal oscillator fault interrupt enable */
+/* RTCCTL0[RTCKEY] Bits */
+#define RTCKEY_OFS                                         ( 8)                  /* RTCKEY Offset */
+#define RTCKEY_M                                           (0xff00)              /* Real-time clock key */
+/* RTCCTL13[RTCTEV] Bits */
+#define RTCTEV_OFS                                         ( 0)                  /* RTCTEV Offset */
+#define RTCTEV_M                                           (0x0003)              /* Real-time clock time event */
+#define RTCTEV0                                            (0x0001)              /* Real-time clock time event */
+#define RTCTEV1                                            (0x0002)              /* Real-time clock time event */
+#define RTCTEV_0                                           (0x0000)              /* Minute changed */
+#define RTCTEV_1                                           (0x0001)              /* Hour changed */
+#define RTCTEV_2                                           (0x0002)              /* Every day at midnight (00:00) */
+#define RTCTEV_3                                           (0x0003)              /* Every day at noon (12:00) */
+/* RTCCTL13[RTCSSEL] Bits */
+#define RTCSSEL_OFS                                        ( 2)                  /* RTCSSEL Offset */
+#define RTCSSEL_M                                          (0x000c)              /* Real-time clock source select */
+#define RTCSSEL0                                           (0x0004)              /* Real-time clock source select */
+#define RTCSSEL1                                           (0x0008)              /* Real-time clock source select */
+#define RTCSSEL_0                                          (0x0000)              /* BCLK */
+#define RTCSSEL__BCLK                                      (0x0000)              /* BCLK */
+/* RTCCTL13[RTCRDY] Bits */
+#define RTCRDY_OFS                                         ( 4)                  /* RTCRDY Offset */
+#define RTCRDY                                             (0x0010)              /* Real-time clock ready */
+/* RTCCTL13[RTCMODE] Bits */
+#define RTCMODE_OFS                                        ( 5)                  /* RTCMODE Offset */
+#define RTCMODE                                            (0x0020)              /*  */
+/* RTCCTL13[RTCHOLD] Bits */
+#define RTCHOLD_OFS                                        ( 6)                  /* RTCHOLD Offset */
+#define RTCHOLD                                            (0x0040)              /* Real-time clock hold */
+/* RTCCTL13[RTCBCD] Bits */
+#define RTCBCD_OFS                                         ( 7)                  /* RTCBCD Offset */
+#define RTCBCD                                             (0x0080)              /* Real-time clock BCD select */
+/* RTCCTL13[RTCCALF] Bits */
+#define RTCCALF_OFS                                        ( 8)                  /* RTCCALF Offset */
+#define RTCCALF_M                                          (0x0300)              /* Real-time clock calibration frequency */
+#define RTCCALF0                                           (0x0100)              /* Real-time clock calibration frequency */
+#define RTCCALF1                                           (0x0200)              /* Real-time clock calibration frequency */
+#define RTCCALF_0                                          (0x0000)              /* No frequency output to RTCCLK pin */
+#define RTCCALF_1                                          (0x0100)              /* 512 Hz */
+#define RTCCALF_2                                          (0x0200)              /* 256 Hz */
+#define RTCCALF_3                                          (0x0300)              /* 1 Hz */
+#define RTCCALF__NONE                                      (0x0000)              /* No frequency output to RTCCLK pin */
+#define RTCCALF__512                                       (0x0100)              /* 512 Hz */
+#define RTCCALF__256                                       (0x0200)              /* 256 Hz */
+#define RTCCALF__1                                         (0x0300)              /* 1 Hz */
+/* RTCOCAL[RTCOCAL] Bits */
+#define RTCOCAL_OFS                                        ( 0)                  /* RTCOCAL Offset */
+#define RTCOCAL_M                                          (0x00ff)              /* Real-time clock offset error calibration */
+/* RTCOCAL[RTCOCALS] Bits */
+#define RTCOCALS_OFS                                       (15)                  /* RTCOCALS Offset */
+#define RTCOCALS                                           (0x8000)              /* Real-time clock offset error calibration sign */
+/* RTCTCMP[RTCTCMP] Bits */
+#define RTCTCMP_OFS                                        ( 0)                  /* RTCTCMP Offset */
+#define RTCTCMP_M                                          (0x00ff)              /* Real-time clock temperature compensation */
+/* RTCTCMP[RTCTCOK] Bits */
+#define RTCTCOK_OFS                                        (13)                  /* RTCTCOK Offset */
+#define RTCTCOK                                            (0x2000)              /* Real-time clock temperature compensation write OK */
+/* RTCTCMP[RTCTCRDY] Bits */
+#define RTCTCRDY_OFS                                       (14)                  /* RTCTCRDY Offset */
+#define RTCTCRDY                                           (0x4000)              /* Real-time clock temperature compensation ready */
+/* RTCTCMP[RTCTCMPS] Bits */
+#define RTCTCMPS_OFS                                       (15)                  /* RTCTCMPS Offset */
+#define RTCTCMPS                                           (0x8000)              /* Real-time clock temperature compensation sign */
+/* RTCPS0CTL[RT0PSIFG] Bits */
+#define RT0PSIFG_OFS                                       ( 0)                  /* RT0PSIFG Offset */
+#define RT0PSIFG                                           (0x0001)              /* Prescale timer 0 interrupt flag */
+/* RTCPS0CTL[RT0PSIE] Bits */
+#define RT0PSIE_OFS                                        ( 1)                  /* RT0PSIE Offset */
+#define RT0PSIE                                            (0x0002)              /* Prescale timer 0 interrupt enable */
+/* RTCPS0CTL[RT0IP] Bits */
+#define RT0IP_OFS                                          ( 2)                  /* RT0IP Offset */
+#define RT0IP_M                                            (0x001c)              /* Prescale timer 0 interrupt interval */
+#define RT0IP0                                             (0x0004)              /* Prescale timer 0 interrupt interval */
+#define RT0IP1                                             (0x0008)              /* Prescale timer 0 interrupt interval */
+#define RT0IP2                                             (0x0010)              /* Prescale timer 0 interrupt interval */
+#define RT0IP_0                                            (0x0000)              /* Divide by 2 */
+#define RT0IP_1                                            (0x0004)              /* Divide by 4 */
+#define RT0IP_2                                            (0x0008)              /* Divide by 8 */
+#define RT0IP_3                                            (0x000c)              /* Divide by 16 */
+#define RT0IP_4                                            (0x0010)              /* Divide by 32 */
+#define RT0IP_5                                            (0x0014)              /* Divide by 64 */
+#define RT0IP_6                                            (0x0018)              /* Divide by 128 */
+#define RT0IP_7                                            (0x001c)              /* Divide by 256 */
+#define RT0IP__2                                           (0x0000)              /* Divide by 2 */
+#define RT0IP__4                                           (0x0004)              /* Divide by 4 */
+#define RT0IP__8                                           (0x0008)              /* Divide by 8 */
+#define RT0IP__16                                          (0x000c)              /* Divide by 16 */
+#define RT0IP__32                                          (0x0010)              /* Divide by 32 */
+#define RT0IP__64                                          (0x0014)              /* Divide by 64 */
+#define RT0IP__128                                         (0x0018)              /* Divide by 128 */
+#define RT0IP__256                                         (0x001c)              /* Divide by 256 */
+/* RTCPS1CTL[RT1PSIFG] Bits */
+#define RT1PSIFG_OFS                                       ( 0)                  /* RT1PSIFG Offset */
+#define RT1PSIFG                                           (0x0001)              /* Prescale timer 1 interrupt flag */
+/* RTCPS1CTL[RT1PSIE] Bits */
+#define RT1PSIE_OFS                                        ( 1)                  /* RT1PSIE Offset */
+#define RT1PSIE                                            (0x0002)              /* Prescale timer 1 interrupt enable */
+/* RTCPS1CTL[RT1IP] Bits */
+#define RT1IP_OFS                                          ( 2)                  /* RT1IP Offset */
+#define RT1IP_M                                            (0x001c)              /* Prescale timer 1 interrupt interval */
+#define RT1IP0                                             (0x0004)              /* Prescale timer 1 interrupt interval */
+#define RT1IP1                                             (0x0008)              /* Prescale timer 1 interrupt interval */
+#define RT1IP2                                             (0x0010)              /* Prescale timer 1 interrupt interval */
+#define RT1IP_0                                            (0x0000)              /* Divide by 2 */
+#define RT1IP_1                                            (0x0004)              /* Divide by 4 */
+#define RT1IP_2                                            (0x0008)              /* Divide by 8 */
+#define RT1IP_3                                            (0x000c)              /* Divide by 16 */
+#define RT1IP_4                                            (0x0010)              /* Divide by 32 */
+#define RT1IP_5                                            (0x0014)              /* Divide by 64 */
+#define RT1IP_6                                            (0x0018)              /* Divide by 128 */
+#define RT1IP_7                                            (0x001c)              /* Divide by 256 */
+#define RT1IP__2                                           (0x0000)              /* Divide by 2 */
+#define RT1IP__4                                           (0x0004)              /* Divide by 4 */
+#define RT1IP__8                                           (0x0008)              /* Divide by 8 */
+#define RT1IP__16                                          (0x000c)              /* Divide by 16 */
+#define RT1IP__32                                          (0x0010)              /* Divide by 32 */
+#define RT1IP__64                                          (0x0014)              /* Divide by 64 */
+#define RT1IP__128                                         (0x0018)              /* Divide by 128 */
+#define RT1IP__256                                         (0x001c)              /* Divide by 256 */
+/* RTCPS[RT0PS] Bits */
+#define RT0PS_OFS                                          ( 0)                  /* RT0PS Offset */
+#define RT0PS_M                                            (0x00ff)              /* Prescale timer 0 counter value */
+/* RTCPS[RT1PS] Bits */
+#define RT1PS_OFS                                          ( 8)                  /* RT1PS Offset */
+#define RT1PS_M                                            (0xff00)              /* Prescale timer 1 counter value */
+/* RTCTIM0[SECONDS] Bits */
+#define SECONDS_OFS                                        ( 0)                  /* Seconds Offset */
+#define SECONDS_M                                          (0x003f)              /* Seconds (0 to 59) */
+/* RTCTIM0[MINUTES] Bits */
+#define MINUTES_OFS                                        ( 8)                  /* Minutes Offset */
+#define MINUTES_M                                          (0x3f00)              /* Minutes (0 to 59) */
+/* RTCTIM0_BCD[SECONDSLOWDIGIT] Bits */
+#define SECONDSLOWDIGIT_OFS                                ( 0)                  /* SecondsLowDigit Offset */
+#define SECONDSLOWDIGIT_M                                  (0x000f)              /* Seconds ? low digit (0 to 9) */
+/* RTCTIM0_BCD[SECONDSHIGHDIGIT] Bits */
+#define SECONDSHIGHDIGIT_OFS                               ( 4)                  /* SecondsHighDigit Offset */
+#define SECONDSHIGHDIGIT_M                                 (0x0070)              /* Seconds ? high digit (0 to 5) */
+/* RTCTIM0_BCD[MINUTESLOWDIGIT] Bits */
+#define MINUTESLOWDIGIT_OFS                                ( 8)                  /* MinutesLowDigit Offset */
+#define MINUTESLOWDIGIT_M                                  (0x0f00)              /* Minutes ? low digit (0 to 9) */
+/* RTCTIM0_BCD[MINUTESHIGHDIGIT] Bits */
+#define MINUTESHIGHDIGIT_OFS                               (12)                  /* MinutesHighDigit Offset */
+#define MINUTESHIGHDIGIT_M                                 (0x7000)              /* Minutes ? high digit (0 to 5) */
+/* RTCTIM1[HOURS] Bits */
+#define HOURS_OFS                                          ( 0)                  /* Hours Offset */
+#define HOURS_M                                            (0x001f)              /* Hours (0 to 23) */
+/* RTCTIM1[DAYOFWEEK] Bits */
+#define DAYOFWEEK_OFS                                      ( 8)                  /* DayofWeek Offset */
+#define DAYOFWEEK_M                                        (0x0700)              /* Day of week (0 to 6) */
+/* RTCTIM1_BCD[HOURSLOWDIGIT] Bits */
+#define HOURSLOWDIGIT_OFS                                  ( 0)                  /* HoursLowDigit Offset */
+#define HOURSLOWDIGIT_M                                    (0x000f)              /* Hours ? low digit (0 to 9) */
+/* RTCTIM1_BCD[HOURSHIGHDIGIT] Bits */
+#define HOURSHIGHDIGIT_OFS                                 ( 4)                  /* HoursHighDigit Offset */
+#define HOURSHIGHDIGIT_M                                   (0x0030)              /* Hours ? high digit (0 to 2) */
+/* RTCTIM1_BCD[DAYOFWEEK] Bits */
+//#define DAYOFWEEK_OFS                                      ( 8)                  /* DayofWeek Offset */
+//#define DAYOFWEEK_M                                        (0x0700)              /* Day of week (0 to 6) */
+/* RTCDATE[DAY] Bits */
+#define DAY_OFS                                            ( 0)                  /* Day Offset */
+#define DAY_M                                              (0x001f)              /* Day of month (1 to 28, 29, 30, 31) */
+/* RTCDATE[MONTH] Bits */
+#define MONTH_OFS                                          ( 8)                  /* Month Offset */
+#define MONTH_M                                            (0x0f00)              /* Month (1 to 12) */
+/* RTCDATE_BCD[DAYLOWDIGIT] Bits */
+#define DAYLOWDIGIT_OFS                                    ( 0)                  /* DayLowDigit Offset */
+#define DAYLOWDIGIT_M                                      (0x000f)              /* Day of month ? low digit (0 to 9) */
+/* RTCDATE_BCD[DAYHIGHDIGIT] Bits */
+#define DAYHIGHDIGIT_OFS                                   ( 4)                  /* DayHighDigit Offset */
+#define DAYHIGHDIGIT_M                                     (0x0030)              /* Day of month ? high digit (0 to 3) */
+/* RTCDATE_BCD[MONTHLOWDIGIT] Bits */
+#define MONTHLOWDIGIT_OFS                                  ( 8)                  /* MonthLowDigit Offset */
+#define MONTHLOWDIGIT_M                                    (0x0f00)              /* Month ? low digit (0 to 9) */
+/* RTCDATE_BCD[MONTHHIGHDIGIT] Bits */
+#define MONTHHIGHDIGIT_OFS                                 (12)                  /* MonthHighDigit Offset */
+#define MONTHHIGHDIGIT                                     (0x1000)              /* Month ? high digit (0 or 1) */
+/* RTCYEAR[YEARLOWBYTE] Bits */
+#define YEARLOWBYTE_OFS                                    ( 0)                  /* YearLowByte Offset */
+#define YEARLOWBYTE_M                                      (0x00ff)              /* Year ? low byte. Valid values for Year are 0 to 4095. */
+/* RTCYEAR[YEARHIGHBYTE] Bits */
+#define YEARHIGHBYTE_OFS                                   ( 8)                  /* YearHighByte Offset */
+#define YEARHIGHBYTE_M                                     (0x0f00)              /* Year ? high byte. Valid values for Year are 0 to 4095. */
+/* RTCYEAR_BCD[YEAR] Bits */
+#define YEAR_OFS                                           ( 0)                  /* Year Offset */
+#define YEAR_M                                             (0x000f)              /* Year ? lowest digit (0 to 9) */
+/* RTCYEAR_BCD[DECADE] Bits */
+#define DECADE_OFS                                         ( 4)                  /* Decade Offset */
+#define DECADE_M                                           (0x00f0)              /* Decade (0 to 9) */
+/* RTCYEAR_BCD[CENTURYLOWDIGIT] Bits */
+#define CENTURYLOWDIGIT_OFS                                ( 8)                  /* CenturyLowDigit Offset */
+#define CENTURYLOWDIGIT_M                                  (0x0f00)              /* Century ? low digit (0 to 9) */
+/* RTCYEAR_BCD[CENTURYHIGHDIGIT] Bits */
+#define CENTURYHIGHDIGIT_OFS                               (12)                  /* CenturyHighDigit Offset */
+#define CENTURYHIGHDIGIT_M                                 (0x7000)              /* Century ? high digit (0 to 4) */
+/* RTCAMINHR[MINUTES] Bits */
+//#define MINUTES_OFS                                        ( 0)                  /* Minutes Offset */
+//#define MINUTES_M                                          (0x003f)              /* Minutes (0 to 59) */
+/* RTCAMINHR[MINAE] Bits */
+#define MINAE_OFS                                          ( 7)                  /* MINAE Offset */
+#define MINAE                                              (0x0080)              /* Alarm enable */
+/* RTCAMINHR[HOURS] Bits */
+//#define HOURS_OFS                                          ( 8)                  /* Hours Offset */
+//#define HOURS_M                                            (0x1f00)              /* Hours (0 to 23) */
+/* RTCAMINHR[HOURAE] Bits */
+#define HOURAE_OFS                                         (15)                  /* HOURAE Offset */
+#define HOURAE                                             (0x8000)              /* Alarm enable */
+/* RTCAMINHR_BCD[MINUTESLOWDIGIT] Bits */
+//#define MINUTESLOWDIGIT_OFS                                ( 0)                  /* MinutesLowDigit Offset */
+//#define MINUTESLOWDIGIT_M                                  (0x000f)              /* Minutes ? low digit (0 to 9) */
+/* RTCAMINHR_BCD[MINUTESHIGHDIGIT] Bits */
+//#define MINUTESHIGHDIGIT_OFS                               ( 4)                  /* MinutesHighDigit Offset */
+//#define MINUTESHIGHDIGIT_M                                 (0x0070)              /* Minutes ? high digit (0 to 5) */
+/* RTCAMINHR_BCD[MINAE] Bits */
+//#define MINAE_OFS                                          ( 7)                  /* MINAE Offset */
+//#define MINAE                                              (0x0080)              /* Alarm enable */
+/* RTCAMINHR_BCD[HOURSLOWDIGIT] Bits */
+//#define HOURSLOWDIGIT_OFS                                  ( 8)                  /* HoursLowDigit Offset */
+//#define HOURSLOWDIGIT_M                                    (0x0f00)              /* Hours ? low digit (0 to 9) */
+/* RTCAMINHR_BCD[HOURSHIGHDIGIT] Bits */
+//#define HOURSHIGHDIGIT_OFS                                 (12)                  /* HoursHighDigit Offset */
+//#define HOURSHIGHDIGIT_M                                   (0x3000)              /* Hours ? high digit (0 to 2) */
+/* RTCAMINHR_BCD[HOURAE] Bits */
+//#define HOURAE_OFS                                         (15)                  /* HOURAE Offset */
+//#define HOURAE                                             (0x8000)              /* Alarm enable */
+/* RTCADOWDAY[DAYOFWEEK] Bits */
+//#define DAYOFWEEK_OFS                                      ( 0)                  /* DayofWeek Offset */
+//#define DAYOFWEEK_M                                        (0x0007)              /* Day of week (0 to 6) */
+/* RTCADOWDAY[DOWAE] Bits */
+#define DOWAE_OFS                                          ( 7)                  /* DOWAE Offset */
+#define DOWAE                                              (0x0080)              /* Alarm enable */
+/* RTCADOWDAY[DAYOFMONTH] Bits */
+#define DAYOFMONTH_OFS                                     ( 8)                  /* DayofMonth Offset */
+#define DAYOFMONTH_M                                       (0x1f00)              /* Day of month (1 to 28, 29, 30, 31) */
+/* RTCADOWDAY[DAYAE] Bits */
+#define DAYAE_OFS                                          (15)                  /* DAYAE Offset */
+#define DAYAE                                              (0x8000)              /* Alarm enable */
+/* RTCADOWDAY_BCD[DAYOFWEEK] Bits */
+//#define DAYOFWEEK_OFS                                      ( 0)                  /* DayofWeek Offset */
+//#define DAYOFWEEK_M                                        (0x0007)              /* Day of week (0 to 6) */
+/* RTCADOWDAY_BCD[DOWAE] Bits */
+//#define DOWAE_OFS                                          ( 7)                  /* DOWAE Offset */
+//#define DOWAE                                              (0x0080)              /* Alarm enable */
+/* RTCADOWDAY_BCD[DAYLOWDIGIT] Bits */
+//#define DAYLOWDIGIT_OFS                                    ( 8)                  /* DayLowDigit Offset */
+//#define DAYLOWDIGIT_M                                      (0x0f00)              /* Day of month ? low digit (0 to 9) */
+/* RTCADOWDAY_BCD[DAYHIGHDIGIT] Bits */
+//#define DAYHIGHDIGIT_OFS                                   (12)                  /* DayHighDigit Offset */
+//#define DAYHIGHDIGIT_M                                     (0x3000)              /* Day of month ? high digit (0 to 3) */
+/* RTCADOWDAY_BCD[DAYAE] Bits */
+//#define DAYAE_OFS                                          (15)                  /* DAYAE Offset */
+//#define DAYAE                                              (0x8000)              /* Alarm enable */
+
+/* Pre-defined bitfield values */
+#define RTCKEY                                              (0xA500)              /* RTC_C Key Value for RTC_C write access */
+#define RTCKEY_H                                            (0x00A5)              /* RTC_C Key Value for RTC_C write access */
+#define RTCKEY_VAL                                          (0xA500)              /* RTC_C Key Value for RTC_C write access */
+
+
+//*****************************************************************************
+// SCB Bits
+//*****************************************************************************
+/* SCB_CPUID[SCB_CPUID_REVISION] Bits */
+#define SCB_CPUID_REVISION_OFS                             ( 0)                  /* REVISION Offset */
+#define SCB_CPUID_REVISION_M                               (0x0000000f)          /*  */
+/* SCB_CPUID[SCB_CPUID_PARTNO] Bits */
+#define SCB_CPUID_PARTNO_OFS                               ( 4)                  /* PARTNO Offset */
+#define SCB_CPUID_PARTNO_M                                 (0x0000fff0)          /*  */
+/* SCB_CPUID[SCB_CPUID_CONSTANT] Bits */
+#define SCB_CPUID_CONSTANT_OFS                             (16)                  /* CONSTANT Offset */
+#define SCB_CPUID_CONSTANT_M                               (0x000f0000)          /*  */
+/* SCB_CPUID[SCB_CPUID_VARIANT] Bits */
+#define SCB_CPUID_VARIANT_OFS                              (20)                  /* VARIANT Offset */
+#define SCB_CPUID_VARIANT_M                                (0x00f00000)          /*  */
+/* SCB_CPUID[SCB_CPUID_IMPLEMENTER] Bits */
+#define SCB_CPUID_IMPLEMENTER_OFS                          (24)                  /* IMPLEMENTER Offset */
+#define SCB_CPUID_IMPLEMENTER_M                            (0xff000000)          /*  */
+/* SCB_ICSR[SCB_ICSR_VECTACTIVE] Bits */
+#define SCB_ICSR_VECTACTIVE_OFS                            ( 0)                  /* VECTACTIVE Offset */
+#define SCB_ICSR_VECTACTIVE_M                              (0x000001ff)          /*  */
+/* SCB_ICSR[SCB_ICSR_RETTOBASE] Bits */
+#define SCB_ICSR_RETTOBASE_OFS                             (11)                  /* RETTOBASE Offset */
+#define SCB_ICSR_RETTOBASE                                 (0x00000800)          /*  */
+/* SCB_ICSR[SCB_ICSR_VECTPENDING] Bits */
+#define SCB_ICSR_VECTPENDING_OFS                           (12)                  /* VECTPENDING Offset */
+#define SCB_ICSR_VECTPENDING_M                             (0x0003f000)          /*  */
+/* SCB_ICSR[SCB_ICSR_ISRPENDING] Bits */
+#define SCB_ICSR_ISRPENDING_OFS                            (22)                  /* ISRPENDING Offset */
+#define SCB_ICSR_ISRPENDING                                (0x00400000)          /*  */
+/* SCB_ICSR[SCB_ICSR_ISRPREEMPT] Bits */
+#define SCB_ICSR_ISRPREEMPT_OFS                            (23)                  /* ISRPREEMPT Offset */
+#define SCB_ICSR_ISRPREEMPT                                (0x00800000)          /*  */
+/* SCB_ICSR[SCB_ICSR_PENDSTCLR] Bits */
+#define SCB_ICSR_PENDSTCLR_OFS                             (25)                  /* PENDSTCLR Offset */
+#define SCB_ICSR_PENDSTCLR                                 (0x02000000)          /*  */
+/* SCB_ICSR[SCB_ICSR_PENDSTSET] Bits */
+#define SCB_ICSR_PENDSTSET_OFS                             (26)                  /* PENDSTSET Offset */
+#define SCB_ICSR_PENDSTSET                                 (0x04000000)          /*  */
+/* SCB_ICSR[SCB_ICSR_PENDSVCLR] Bits */
+#define SCB_ICSR_PENDSVCLR_OFS                             (27)                  /* PENDSVCLR Offset */
+#define SCB_ICSR_PENDSVCLR                                 (0x08000000)          /*  */
+/* SCB_ICSR[SCB_ICSR_PENDSVSET] Bits */
+#define SCB_ICSR_PENDSVSET_OFS                             (28)                  /* PENDSVSET Offset */
+#define SCB_ICSR_PENDSVSET                                 (0x10000000)          /*  */
+/* SCB_ICSR[SCB_ICSR_NMIPENDSET] Bits */
+#define SCB_ICSR_NMIPENDSET_OFS                            (31)                  /* NMIPENDSET Offset */
+#define SCB_ICSR_NMIPENDSET                                (0x80000000)          /*  */
+/* SCB_VTOR[SCB_VTOR_TBLOFF] Bits */
+#define SCB_VTOR_TBLOFF_OFS                                ( 7)                  /* TBLOFF Offset */
+#define SCB_VTOR_TBLOFF_M                                  (0x1fffff80)          /*  */
+/* SCB_VTOR[SCB_VTOR_TBLBASE] Bits */
+#define SCB_VTOR_TBLBASE_OFS                               (29)                  /* TBLBASE Offset */
+#define SCB_VTOR_TBLBASE                                   (0x20000000)          /*  */
+/* SCB_AIRCR[SCB_AIRCR_VECTRESET] Bits */
+#define SCB_AIRCR_VECTRESET_OFS                            ( 0)                  /* VECTRESET Offset */
+#define SCB_AIRCR_VECTRESET                                (0x00000001)          /*  */
+/* SCB_AIRCR[SCB_AIRCR_VECTCLRACTIVE] Bits */
+#define SCB_AIRCR_VECTCLRACTIVE_OFS                        ( 1)                  /* VECTCLRACTIVE Offset */
+#define SCB_AIRCR_VECTCLRACTIVE                            (0x00000002)          /*  */
+/* SCB_AIRCR[SCB_AIRCR_SYSRESETREQ] Bits */
+#define SCB_AIRCR_SYSRESETREQ_OFS                          ( 2)                  /* SYSRESETREQ Offset */
+#define SCB_AIRCR_SYSRESETREQ                              (0x00000004)          /*  */
+/* SCB_AIRCR[SCB_AIRCR_PRIGROUP] Bits */
+#define SCB_AIRCR_PRIGROUP_OFS                             ( 8)                  /* PRIGROUP Offset */
+#define SCB_AIRCR_PRIGROUP_M                               (0x00000700)          /*  */
+/* SCB_AIRCR[SCB_AIRCR_ENDIANESS] Bits */
+#define SCB_AIRCR_ENDIANESS_OFS                            (15)                  /* ENDIANESS Offset */
+#define SCB_AIRCR_ENDIANESS                                (0x00008000)          /*  */
+/* SCB_AIRCR[SCB_AIRCR_VECTKEY] Bits */
+#define SCB_AIRCR_VECTKEY_OFS                              (16)                  /* VECTKEY Offset */
+#define SCB_AIRCR_VECTKEY_M                                (0xffff0000)          /*  */
+/* SCB_SCR[SCB_SCR_SLEEPONEXIT] Bits */
+#define SCB_SCR_SLEEPONEXIT_OFS                            ( 1)                  /* SLEEPONEXIT Offset */
+#define SCB_SCR_SLEEPONEXIT                                (0x00000002)          /*  */
+/* SCB_SCR[SCB_SCR_SLEEPDEEP] Bits */
+#define SCB_SCR_SLEEPDEEP_OFS                              ( 2)                  /* SLEEPDEEP Offset */
+#define SCB_SCR_SLEEPDEEP                                  (0x00000004)          /*  */
+/* SCB_SCR[SCB_SCR_SEVONPEND] Bits */
+#define SCB_SCR_SEVONPEND_OFS                              ( 4)                  /* SEVONPEND Offset */
+#define SCB_SCR_SEVONPEND                                  (0x00000010)          /*  */
+/* SCB_CCR[SCB_CCR_NONBASETHREDENA] Bits */
+#define SCB_CCR_NONBASETHREDENA_OFS                        ( 0)                  /* NONBASETHREDENA Offset */
+#define SCB_CCR_NONBASETHREDENA                            (0x00000001)          /*  */
+/* SCB_CCR[SCB_CCR_USERSETMPEND] Bits */
+#define SCB_CCR_USERSETMPEND_OFS                           ( 1)                  /* USERSETMPEND Offset */
+#define SCB_CCR_USERSETMPEND                               (0x00000002)          /*  */
+/* SCB_CCR[SCB_CCR_UNALIGN_TRP] Bits */
+#define SCB_CCR_UNALIGN_TRP_OFS                            ( 3)                  /* UNALIGN_TRP Offset */
+#define SCB_CCR_UNALIGN_TRP                                (0x00000008)          /*  */
+/* SCB_CCR[SCB_CCR_DIV_0_TRP] Bits */
+#define SCB_CCR_DIV_0_TRP_OFS                              ( 4)                  /* DIV_0_TRP Offset */
+#define SCB_CCR_DIV_0_TRP                                  (0x00000010)          /*  */
+/* SCB_CCR[SCB_CCR_BFHFNMIGN] Bits */
+#define SCB_CCR_BFHFNMIGN_OFS                              ( 8)                  /* BFHFNMIGN Offset */
+#define SCB_CCR_BFHFNMIGN                                  (0x00000100)          /*  */
+/* SCB_CCR[SCB_CCR_STKALIGN] Bits */
+#define SCB_CCR_STKALIGN_OFS                               ( 9)                  /* STKALIGN Offset */
+#define SCB_CCR_STKALIGN                                   (0x00000200)          /*  */
+/* SCB_SHPR1[SCB_SHPR1_PRI_4] Bits */
+#define SCB_SHPR1_PRI_4_OFS                                ( 0)                  /* PRI_4 Offset */
+#define SCB_SHPR1_PRI_4_M                                  (0x000000ff)          /*  */
+/* SCB_SHPR1[SCB_SHPR1_PRI_5] Bits */
+#define SCB_SHPR1_PRI_5_OFS                                ( 8)                  /* PRI_5 Offset */
+#define SCB_SHPR1_PRI_5_M                                  (0x0000ff00)          /*  */
+/* SCB_SHPR1[SCB_SHPR1_PRI_6] Bits */
+#define SCB_SHPR1_PRI_6_OFS                                (16)                  /* PRI_6 Offset */
+#define SCB_SHPR1_PRI_6_M                                  (0x00ff0000)          /*  */
+/* SCB_SHPR1[SCB_SHPR1_PRI_7] Bits */
+#define SCB_SHPR1_PRI_7_OFS                                (24)                  /* PRI_7 Offset */
+#define SCB_SHPR1_PRI_7_M                                  (0xff000000)          /*  */
+/* SCB_SHPR2[SCB_SHPR2_PRI_8] Bits */
+#define SCB_SHPR2_PRI_8_OFS                                ( 0)                  /* PRI_8 Offset */
+#define SCB_SHPR2_PRI_8_M                                  (0x000000ff)          /*  */
+/* SCB_SHPR2[SCB_SHPR2_PRI_9] Bits */
+#define SCB_SHPR2_PRI_9_OFS                                ( 8)                  /* PRI_9 Offset */
+#define SCB_SHPR2_PRI_9_M                                  (0x0000ff00)          /*  */
+/* SCB_SHPR2[SCB_SHPR2_PRI_10] Bits */
+#define SCB_SHPR2_PRI_10_OFS                               (16)                  /* PRI_10 Offset */
+#define SCB_SHPR2_PRI_10_M                                 (0x00ff0000)          /*  */
+/* SCB_SHPR2[SCB_SHPR2_PRI_11] Bits */
+#define SCB_SHPR2_PRI_11_OFS                               (24)                  /* PRI_11 Offset */
+#define SCB_SHPR2_PRI_11_M                                 (0xff000000)          /*  */
+/* SCB_SHPR3[SCB_SHPR3_PRI_12] Bits */
+#define SCB_SHPR3_PRI_12_OFS                               ( 0)                  /* PRI_12 Offset */
+#define SCB_SHPR3_PRI_12_M                                 (0x000000ff)          /*  */
+/* SCB_SHPR3[SCB_SHPR3_PRI_13] Bits */
+#define SCB_SHPR3_PRI_13_OFS                               ( 8)                  /* PRI_13 Offset */
+#define SCB_SHPR3_PRI_13_M                                 (0x0000ff00)          /*  */
+/* SCB_SHPR3[SCB_SHPR3_PRI_14] Bits */
+#define SCB_SHPR3_PRI_14_OFS                               (16)                  /* PRI_14 Offset */
+#define SCB_SHPR3_PRI_14_M                                 (0x00ff0000)          /*  */
+/* SCB_SHPR3[SCB_SHPR3_PRI_15] Bits */
+#define SCB_SHPR3_PRI_15_OFS                               (24)                  /* PRI_15 Offset */
+#define SCB_SHPR3_PRI_15_M                                 (0xff000000)          /*  */
+/* SCB_SHCSR[SCB_SHCSR_MEMFAULTACT] Bits */
+#define SCB_SHCSR_MEMFAULTACT_OFS                          ( 0)                  /* MEMFAULTACT Offset */
+#define SCB_SHCSR_MEMFAULTACT                              (0x00000001)          /*  */
+/* SCB_SHCSR[SCB_SHCSR_BUSFAULTACT] Bits */
+#define SCB_SHCSR_BUSFAULTACT_OFS                          ( 1)                  /* BUSFAULTACT Offset */
+#define SCB_SHCSR_BUSFAULTACT                              (0x00000002)          /*  */
+/* SCB_SHCSR[SCB_SHCSR_USGFAULTACT] Bits */
+#define SCB_SHCSR_USGFAULTACT_OFS                          ( 3)                  /* USGFAULTACT Offset */
+#define SCB_SHCSR_USGFAULTACT                              (0x00000008)          /*  */
+/* SCB_SHCSR[SCB_SHCSR_SVCALLACT] Bits */
+#define SCB_SHCSR_SVCALLACT_OFS                            ( 7)                  /* SVCALLACT Offset */
+#define SCB_SHCSR_SVCALLACT                                (0x00000080)          /*  */
+/* SCB_SHCSR[SCB_SHCSR_MONITORACT] Bits */
+#define SCB_SHCSR_MONITORACT_OFS                           ( 8)                  /* MONITORACT Offset */
+#define SCB_SHCSR_MONITORACT                               (0x00000100)          /*  */
+/* SCB_SHCSR[SCB_SHCSR_PENDSVACT] Bits */
+#define SCB_SHCSR_PENDSVACT_OFS                            (10)                  /* PENDSVACT Offset */
+#define SCB_SHCSR_PENDSVACT                                (0x00000400)          /*  */
+/* SCB_SHCSR[SCB_SHCSR_SYSTICKACT] Bits */
+#define SCB_SHCSR_SYSTICKACT_OFS                           (11)                  /* SYSTICKACT Offset */
+#define SCB_SHCSR_SYSTICKACT                               (0x00000800)          /*  */
+/* SCB_SHCSR[SCB_SHCSR_USGFAULTPENDED] Bits */
+#define SCB_SHCSR_USGFAULTPENDED_OFS                       (12)                  /* USGFAULTPENDED Offset */
+#define SCB_SHCSR_USGFAULTPENDED                           (0x00001000)          /*  */
+/* SCB_SHCSR[SCB_SHCSR_MEMFAULTPENDED] Bits */
+#define SCB_SHCSR_MEMFAULTPENDED_OFS                       (13)                  /* MEMFAULTPENDED Offset */
+#define SCB_SHCSR_MEMFAULTPENDED                           (0x00002000)          /*  */
+/* SCB_SHCSR[SCB_SHCSR_BUSFAULTPENDED] Bits */
+#define SCB_SHCSR_BUSFAULTPENDED_OFS                       (14)                  /* BUSFAULTPENDED Offset */
+#define SCB_SHCSR_BUSFAULTPENDED                           (0x00004000)          /*  */
+/* SCB_SHCSR[SCB_SHCSR_SVCALLPENDED] Bits */
+#define SCB_SHCSR_SVCALLPENDED_OFS                         (15)                  /* SVCALLPENDED Offset */
+#define SCB_SHCSR_SVCALLPENDED                             (0x00008000)          /*  */
+/* SCB_SHCSR[SCB_SHCSR_MEMFAULTENA] Bits */
+#define SCB_SHCSR_MEMFAULTENA_OFS                          (16)                  /* MEMFAULTENA Offset */
+#define SCB_SHCSR_MEMFAULTENA                              (0x00010000)          /*  */
+/* SCB_SHCSR[SCB_SHCSR_BUSFAULTENA] Bits */
+#define SCB_SHCSR_BUSFAULTENA_OFS                          (17)                  /* BUSFAULTENA Offset */
+#define SCB_SHCSR_BUSFAULTENA                              (0x00020000)          /*  */
+/* SCB_SHCSR[SCB_SHCSR_USGFAULTENA] Bits */
+#define SCB_SHCSR_USGFAULTENA_OFS                          (18)                  /* USGFAULTENA Offset */
+#define SCB_SHCSR_USGFAULTENA                              (0x00040000)          /*  */
+/* SCB_CFSR[SCB_CFSR_IACCVIOL] Bits */
+#define SCB_CFSR_IACCVIOL_OFS                              ( 0)                  /* IACCVIOL Offset */
+#define SCB_CFSR_IACCVIOL                                  (0x00000001)          /*  */
+/* SCB_CFSR[SCB_CFSR_DACCVIOL] Bits */
+#define SCB_CFSR_DACCVIOL_OFS                              ( 1)                  /* DACCVIOL Offset */
+#define SCB_CFSR_DACCVIOL                                  (0x00000002)          /*  */
+/* SCB_CFSR[SCB_CFSR_MUNSTKERR] Bits */
+#define SCB_CFSR_MUNSTKERR_OFS                             ( 3)                  /* MUNSTKERR Offset */
+#define SCB_CFSR_MUNSTKERR                                 (0x00000008)          /*  */
+/* SCB_CFSR[SCB_CFSR_MSTKERR] Bits */
+#define SCB_CFSR_MSTKERR_OFS                               ( 4)                  /* MSTKERR Offset */
+#define SCB_CFSR_MSTKERR                                   (0x00000010)          /*  */
+/* SCB_CFSR[SCB_CFSR_MMARVALID] Bits */
+#define SCB_CFSR_MMARVALID_OFS                             ( 7)                  /* MMARVALID Offset */
+#define SCB_CFSR_MMARVALID                                 (0x00000080)          /*  */
+/* SCB_CFSR[SCB_CFSR_IBUSERR] Bits */
+#define SCB_CFSR_IBUSERR_OFS                               ( 8)                  /* IBUSERR Offset */
+#define SCB_CFSR_IBUSERR                                   (0x00000100)          /*  */
+/* SCB_CFSR[SCB_CFSR_PRECISERR] Bits */
+#define SCB_CFSR_PRECISERR_OFS                             ( 9)                  /* PRECISERR Offset */
+#define SCB_CFSR_PRECISERR                                 (0x00000200)          /*  */
+/* SCB_CFSR[SCB_CFSR_IMPRECISERR] Bits */
+#define SCB_CFSR_IMPRECISERR_OFS                           (10)                  /* IMPRECISERR Offset */
+#define SCB_CFSR_IMPRECISERR                               (0x00000400)          /*  */
+/* SCB_CFSR[SCB_CFSR_UNSTKERR] Bits */
+#define SCB_CFSR_UNSTKERR_OFS                              (11)                  /* UNSTKERR Offset */
+#define SCB_CFSR_UNSTKERR                                  (0x00000800)          /*  */
+/* SCB_CFSR[SCB_CFSR_STKERR] Bits */
+#define SCB_CFSR_STKERR_OFS                                (12)                  /* STKERR Offset */
+#define SCB_CFSR_STKERR                                    (0x00001000)          /*  */
+/* SCB_CFSR[SCB_CFSR_BFARVALID] Bits */
+#define SCB_CFSR_BFARVALID_OFS                             (15)                  /* BFARVALID Offset */
+#define SCB_CFSR_BFARVALID                                 (0x00008000)          /*  */
+/* SCB_CFSR[SCB_CFSR_UNDEFINSTR] Bits */
+#define SCB_CFSR_UNDEFINSTR_OFS                            (16)                  /* UNDEFINSTR Offset */
+#define SCB_CFSR_UNDEFINSTR                                (0x00010000)          /*  */
+/* SCB_CFSR[SCB_CFSR_INVSTATE] Bits */
+#define SCB_CFSR_INVSTATE_OFS                              (17)                  /* INVSTATE Offset */
+#define SCB_CFSR_INVSTATE                                  (0x00020000)          /*  */
+/* SCB_CFSR[SCB_CFSR_INVPC] Bits */
+#define SCB_CFSR_INVPC_OFS                                 (18)                  /* INVPC Offset */
+#define SCB_CFSR_INVPC                                     (0x00040000)          /*  */
+/* SCB_CFSR[SCB_CFSR_NOCP] Bits */
+#define SCB_CFSR_NOCP_OFS                                  (19)                  /* NOCP Offset */
+#define SCB_CFSR_NOCP                                      (0x00080000)          /*  */
+/* SCB_CFSR[SCB_CFSR_UNALIGNED] Bits */
+#define SCB_CFSR_UNALIGNED_OFS                             (24)                  /* UNALIGNED Offset */
+#define SCB_CFSR_UNALIGNED                                 (0x01000000)          /*  */
+/* SCB_CFSR[SCB_CFSR_DIVBYZERO] Bits */
+#define SCB_CFSR_DIVBYZERO_OFS                             (25)                  /* DIVBYZERO Offset */
+#define SCB_CFSR_DIVBYZERO                                 (0x02000000)          /*  */
+/* SCB_CFSR[SCB_CFSR_MLSPERR] Bits */
+#define SCB_CFSR_MLSPERR_OFS                               ( 5)                  /* MLSPERR Offset */
+#define SCB_CFSR_MLSPERR                                   (0x00000020)          /*  */
+/* SCB_CFSR[SCB_CFSR_LSPERR] Bits */
+#define SCB_CFSR_LSPERR_OFS                                (13)                  /* LSPERR Offset */
+#define SCB_CFSR_LSPERR                                    (0x00002000)          /*  */
+/* SCB_HFSR[SCB_HFSR_VECTTBL] Bits */
+#define SCB_HFSR_VECTTBL_OFS                               ( 1)                  /* VECTTBL Offset */
+#define SCB_HFSR_VECTTBL                                   (0x00000002)          /*  */
+/* SCB_HFSR[SCB_HFSR_FORCED] Bits */
+#define SCB_HFSR_FORCED_OFS                                (30)                  /* FORCED Offset */
+#define SCB_HFSR_FORCED                                    (0x40000000)          /*  */
+/* SCB_HFSR[SCB_HFSR_DEBUGEVT] Bits */
+#define SCB_HFSR_DEBUGEVT_OFS                              (31)                  /* DEBUGEVT Offset */
+#define SCB_HFSR_DEBUGEVT                                  (0x80000000)          /*  */
+/* SCB_DFSR[SCB_DFSR_HALTED] Bits */
+#define SCB_DFSR_HALTED_OFS                                ( 0)                  /* HALTED Offset */
+#define SCB_DFSR_HALTED                                    (0x00000001)          /*  */
+/* SCB_DFSR[SCB_DFSR_BKPT] Bits */
+#define SCB_DFSR_BKPT_OFS                                  ( 1)                  /* BKPT Offset */
+#define SCB_DFSR_BKPT                                      (0x00000002)          /*  */
+/* SCB_DFSR[SCB_DFSR_DWTTRAP] Bits */
+#define SCB_DFSR_DWTTRAP_OFS                               ( 2)                  /* DWTTRAP Offset */
+#define SCB_DFSR_DWTTRAP                                   (0x00000004)          /*  */
+/* SCB_DFSR[SCB_DFSR_VCATCH] Bits */
+#define SCB_DFSR_VCATCH_OFS                                ( 3)                  /* VCATCH Offset */
+#define SCB_DFSR_VCATCH                                    (0x00000008)          /*  */
+/* SCB_DFSR[SCB_DFSR_EXTERNAL] Bits */
+#define SCB_DFSR_EXTERNAL_OFS                              ( 4)                  /* EXTERNAL Offset */
+#define SCB_DFSR_EXTERNAL                                  (0x00000010)          /*  */
+/* SCB_PFR0[SCB_PFR0_STATE0] Bits */
+#define SCB_PFR0_STATE0_OFS                                ( 0)                  /* STATE0 Offset */
+#define SCB_PFR0_STATE0_M                                  (0x0000000f)          /*  */
+#define SCB_PFR0_STATE00                                   (0x00000001)          /*  */
+#define SCB_PFR0_STATE01                                   (0x00000002)          /*  */
+#define SCB_PFR0_STATE02                                   (0x00000004)          /*  */
+#define SCB_PFR0_STATE03                                   (0x00000008)          /*  */
+#define SCB_PFR0_STATE0_0                                  (0x00000000)          /* no ARM encoding */
+#define SCB_PFR0_STATE0_1                                  (0x00000001)          /* N/A */
+/* SCB_PFR0[SCB_PFR0_STATE1] Bits */
+#define SCB_PFR0_STATE1_OFS                                ( 4)                  /* STATE1 Offset */
+#define SCB_PFR0_STATE1_M                                  (0x000000f0)          /*  */
+#define SCB_PFR0_STATE10                                   (0x00000010)          /*  */
+#define SCB_PFR0_STATE11                                   (0x00000020)          /*  */
+#define SCB_PFR0_STATE12                                   (0x00000040)          /*  */
+#define SCB_PFR0_STATE13                                   (0x00000080)          /*  */
+#define SCB_PFR0_STATE1_0                                  (0x00000000)          /* N/A */
+#define SCB_PFR0_STATE1_1                                  (0x00000010)          /* N/A */
+#define SCB_PFR0_STATE1_2                                  (0x00000020)          /* Thumb-2 encoding with the 16-bit basic instructions plus 32-bit Buncond/BL but no other 32-bit basic instructions (Note non-basic 32-bit instructions can be added using the appropriate instruction attribute, but other 32-bit basic instructions cannot.) */
+#define SCB_PFR0_STATE1_3                                  (0x00000030)          /* Thumb-2 encoding with all Thumb-2 basic instructions */
+/* SCB_PFR1[SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL] Bits */
+#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_OFS     ( 8)                  /* MICROCONTROLLER_PROGRAMMERS_MODEL Offset */
+#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_M       (0x00000f00)          /*  */
+#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL0        (0x00000100)          /*  */
+#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL1        (0x00000200)          /*  */
+#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL2        (0x00000400)          /*  */
+#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL3        (0x00000800)          /*  */
+#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_0       (0x00000000)          /* not supported */
+#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_2       (0x00000200)          /* two-stack support */
+/* SCB_DFR0[SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL] Bits */
+#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_OFS           (20)                  /* MICROCONTROLLER_DEBUG_MODEL Offset */
+#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_M             (0x00f00000)          /*  */
+#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL0              (0x00100000)          /*  */
+#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL1              (0x00200000)          /*  */
+#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL2              (0x00400000)          /*  */
+#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL3              (0x00800000)          /*  */
+#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_0             (0x00000000)          /* not supported */
+#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_1             (0x00100000)          /* Microcontroller debug v1 (ITMv1, DWTv1, optional ETM) */
+/* SCB_MMFR0[SCB_MMFR0_PMSA_SUPPORT] Bits */
+#define SCB_MMFR0_PMSA_SUPPORT_OFS                         ( 4)                  /* PMSA_SUPPORT Offset */
+#define SCB_MMFR0_PMSA_SUPPORT_M                           (0x000000f0)          /*  */
+#define SCB_MMFR0_PMSA_SUPPORT0                            (0x00000010)          /*  */
+#define SCB_MMFR0_PMSA_SUPPORT1                            (0x00000020)          /*  */
+#define SCB_MMFR0_PMSA_SUPPORT2                            (0x00000040)          /*  */
+#define SCB_MMFR0_PMSA_SUPPORT3                            (0x00000080)          /*  */
+#define SCB_MMFR0_PMSA_SUPPORT_0                           (0x00000000)          /* not supported */
+#define SCB_MMFR0_PMSA_SUPPORT_1                           (0x00000010)          /* IMPLEMENTATION DEFINED (N/A) */
+#define SCB_MMFR0_PMSA_SUPPORT_2                           (0x00000020)          /* PMSA base (features as defined for ARMv6) (N/A) */
+#define SCB_MMFR0_PMSA_SUPPORT_3                           (0x00000030)          /* PMSAv7 (base plus subregion support) */
+/* SCB_MMFR0[SCB_MMFR0_CACHE_COHERENCE_SUPPORT] Bits */
+#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_OFS              ( 8)                  /* CACHE_COHERENCE_SUPPORT Offset */
+#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_M                (0x00000f00)          /*  */
+#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT0                 (0x00000100)          /*  */
+#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT1                 (0x00000200)          /*  */
+#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT2                 (0x00000400)          /*  */
+#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT3                 (0x00000800)          /*  */
+#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_0                (0x00000000)          /* no shared support */
+#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_1                (0x00000100)          /* partial-inner-shared coherency (coherency amongst some - but not all - of the entities within an inner-coherent domain) */
+#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_2                (0x00000200)          /* full-inner-shared coherency (coherency amongst all of the entities within an inner-coherent domain) */
+#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_3                (0x00000300)          /* full coherency (coherency amongst all of the entities) */
+/* SCB_MMFR0[SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT] Bits */
+#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_OFS           (12)                  /* OUTER_NON_SHARABLE_SUPPORT Offset */
+#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_M             (0x0000f000)          /*  */
+#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT0              (0x00001000)          /*  */
+#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT1              (0x00002000)          /*  */
+#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT2              (0x00004000)          /*  */
+#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT3              (0x00008000)          /*  */
+#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_0             (0x00000000)          /* Outer non-sharable not supported */
+#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_1             (0x00001000)          /* Outer sharable supported */
+/* SCB_MMFR0[SCB_MMFR0_AUILIARY_REGISTER_SUPPORT] Bits */
+#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_OFS            (20)                  /* AUXILIARY_REGISTER_SUPPORT Offset */
+#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_M              (0x00f00000)          /*  */
+#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT0               (0x00100000)          /*  */
+#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT1               (0x00200000)          /*  */
+#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT2               (0x00400000)          /*  */
+#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT3               (0x00800000)          /*  */
+#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_0              (0x00000000)          /* not supported */
+#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_1              (0x00100000)          /* Auxiliary control register */
+/* SCB_MMFR2[SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING] Bits */
+#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_OFS          (24)                  /* WAIT_FOR_INTERRUPT_STALLING Offset */
+#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_M            (0x0f000000)          /*  */
+#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING0             (0x01000000)          /*  */
+#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING1             (0x02000000)          /*  */
+#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING2             (0x04000000)          /*  */
+#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING3             (0x08000000)          /*  */
+#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_0            (0x00000000)          /* not supported */
+#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_1            (0x01000000)          /* wait for interrupt supported */
+/* SCB_ISAR0[SCB_ISAR0_BITCOUNT_INSTRS] Bits */
+#define SCB_ISAR0_BITCOUNT_INSTRS_OFS                      ( 4)                  /* BITCOUNT_INSTRS Offset */
+#define SCB_ISAR0_BITCOUNT_INSTRS_M                        (0x000000f0)          /*  */
+#define SCB_ISAR0_BITCOUNT_INSTRS0                         (0x00000010)          /*  */
+#define SCB_ISAR0_BITCOUNT_INSTRS1                         (0x00000020)          /*  */
+#define SCB_ISAR0_BITCOUNT_INSTRS2                         (0x00000040)          /*  */
+#define SCB_ISAR0_BITCOUNT_INSTRS3                         (0x00000080)          /*  */
+#define SCB_ISAR0_BITCOUNT_INSTRS_0                        (0x00000000)          /* no bit-counting instructions present */
+#define SCB_ISAR0_BITCOUNT_INSTRS_1                        (0x00000010)          /* adds CLZ */
+/* SCB_ISAR0[SCB_ISAR0_BITFIELD_INSTRS] Bits */
+#define SCB_ISAR0_BITFIELD_INSTRS_OFS                      ( 8)                  /* BITFIELD_INSTRS Offset */
+#define SCB_ISAR0_BITFIELD_INSTRS_M                        (0x00000f00)          /*  */
+#define SCB_ISAR0_BITFIELD_INSTRS0                         (0x00000100)          /*  */
+#define SCB_ISAR0_BITFIELD_INSTRS1                         (0x00000200)          /*  */
+#define SCB_ISAR0_BITFIELD_INSTRS2                         (0x00000400)          /*  */
+#define SCB_ISAR0_BITFIELD_INSTRS3                         (0x00000800)          /*  */
+#define SCB_ISAR0_BITFIELD_INSTRS_0                        (0x00000000)          /* no bitfield instructions present */
+#define SCB_ISAR0_BITFIELD_INSTRS_1                        (0x00000100)          /* adds BFC, BFI, SBFX, UBFX */
+/* SCB_ISAR0[SCB_ISAR0_CMPBRANCH_INSTRS] Bits */
+#define SCB_ISAR0_CMPBRANCH_INSTRS_OFS                     (12)                  /* CMPBRANCH_INSTRS Offset */
+#define SCB_ISAR0_CMPBRANCH_INSTRS_M                       (0x0000f000)          /*  */
+#define SCB_ISAR0_CMPBRANCH_INSTRS0                        (0x00001000)          /*  */
+#define SCB_ISAR0_CMPBRANCH_INSTRS1                        (0x00002000)          /*  */
+#define SCB_ISAR0_CMPBRANCH_INSTRS2                        (0x00004000)          /*  */
+#define SCB_ISAR0_CMPBRANCH_INSTRS3                        (0x00008000)          /*  */
+#define SCB_ISAR0_CMPBRANCH_INSTRS_0                       (0x00000000)          /* no combined compare-and-branch instructions present */
+#define SCB_ISAR0_CMPBRANCH_INSTRS_1                       (0x00001000)          /* adds CB{N}Z */
+/* SCB_ISAR0[SCB_ISAR0_COPROC_INSTRS] Bits */
+#define SCB_ISAR0_COPROC_INSTRS_OFS                        (16)                  /* COPROC_INSTRS Offset */
+#define SCB_ISAR0_COPROC_INSTRS_M                          (0x000f0000)          /*  */
+#define SCB_ISAR0_COPROC_INSTRS0                           (0x00010000)          /*  */
+#define SCB_ISAR0_COPROC_INSTRS1                           (0x00020000)          /*  */
+#define SCB_ISAR0_COPROC_INSTRS2                           (0x00040000)          /*  */
+#define SCB_ISAR0_COPROC_INSTRS3                           (0x00080000)          /*  */
+#define SCB_ISAR0_COPROC_INSTRS_0                          (0x00000000)          /* no coprocessor support, other than for separately attributed architectures such as CP15 or VFP */
+#define SCB_ISAR0_COPROC_INSTRS_1                          (0x00010000)          /* adds generic CDP, LDC, MCR, MRC, STC */
+#define SCB_ISAR0_COPROC_INSTRS_2                          (0x00020000)          /* adds generic CDP2, LDC2, MCR2, MRC2, STC2 */
+#define SCB_ISAR0_COPROC_INSTRS_3                          (0x00030000)          /* adds generic MCRR, MRRC */
+#define SCB_ISAR0_COPROC_INSTRS_4                          (0x00040000)          /* adds generic MCRR2, MRRC2 */
+/* SCB_ISAR0[SCB_ISAR0_DEBUG_INSTRS] Bits */
+#define SCB_ISAR0_DEBUG_INSTRS_OFS                         (20)                  /* DEBUG_INSTRS Offset */
+#define SCB_ISAR0_DEBUG_INSTRS_M                           (0x00f00000)          /*  */
+#define SCB_ISAR0_DEBUG_INSTRS0                            (0x00100000)          /*  */
+#define SCB_ISAR0_DEBUG_INSTRS1                            (0x00200000)          /*  */
+#define SCB_ISAR0_DEBUG_INSTRS2                            (0x00400000)          /*  */
+#define SCB_ISAR0_DEBUG_INSTRS3                            (0x00800000)          /*  */
+#define SCB_ISAR0_DEBUG_INSTRS_0                           (0x00000000)          /* no debug instructions present */
+#define SCB_ISAR0_DEBUG_INSTRS_1                           (0x00100000)          /* adds BKPT */
+/* SCB_ISAR0[SCB_ISAR0_DIVIDE_INSTRS] Bits */
+#define SCB_ISAR0_DIVIDE_INSTRS_OFS                        (24)                  /* DIVIDE_INSTRS Offset */
+#define SCB_ISAR0_DIVIDE_INSTRS_M                          (0x0f000000)          /*  */
+#define SCB_ISAR0_DIVIDE_INSTRS0                           (0x01000000)          /*  */
+#define SCB_ISAR0_DIVIDE_INSTRS1                           (0x02000000)          /*  */
+#define SCB_ISAR0_DIVIDE_INSTRS2                           (0x04000000)          /*  */
+#define SCB_ISAR0_DIVIDE_INSTRS3                           (0x08000000)          /*  */
+#define SCB_ISAR0_DIVIDE_INSTRS_0                          (0x00000000)          /* no divide instructions present */
+#define SCB_ISAR0_DIVIDE_INSTRS_1                          (0x01000000)          /* adds SDIV, UDIV (v1 quotient only result) */
+/* SCB_ISAR1[SCB_ISAR1_ETEND_INSRS] Bits */
+#define SCB_ISAR1_ETEND_INSRS_OFS                          (12)                  /* EXTEND_INSRS Offset */
+#define SCB_ISAR1_ETEND_INSRS_M                            (0x0000f000)          /*  */
+#define SCB_ISAR1_ETEND_INSRS0                             (0x00001000)          /*  */
+#define SCB_ISAR1_ETEND_INSRS1                             (0x00002000)          /*  */
+#define SCB_ISAR1_ETEND_INSRS2                             (0x00004000)          /*  */
+#define SCB_ISAR1_ETEND_INSRS3                             (0x00008000)          /*  */
+#define SCB_ISAR1_ETEND_INSRS_0                            (0x00000000)          /* no scalar (i.e. non-SIMD) sign/zero-extend instructions present */
+#define SCB_ISAR1_ETEND_INSRS_1                            (0x00001000)          /* adds SXTB, SXTH, UXTB, UXTH */
+#define SCB_ISAR1_ETEND_INSRS_2                            (0x00002000)          /* N/A */
+/* SCB_ISAR1[SCB_ISAR1_IFTHEN_INSTRS] Bits */
+#define SCB_ISAR1_IFTHEN_INSTRS_OFS                        (16)                  /* IFTHEN_INSTRS Offset */
+#define SCB_ISAR1_IFTHEN_INSTRS_M                          (0x000f0000)          /*  */
+#define SCB_ISAR1_IFTHEN_INSTRS0                           (0x00010000)          /*  */
+#define SCB_ISAR1_IFTHEN_INSTRS1                           (0x00020000)          /*  */
+#define SCB_ISAR1_IFTHEN_INSTRS2                           (0x00040000)          /*  */
+#define SCB_ISAR1_IFTHEN_INSTRS3                           (0x00080000)          /*  */
+#define SCB_ISAR1_IFTHEN_INSTRS_0                          (0x00000000)          /* IT instructions not present */
+#define SCB_ISAR1_IFTHEN_INSTRS_1                          (0x00010000)          /* adds IT instructions (and IT bits in PSRs) */
+/* SCB_ISAR1[SCB_ISAR1_IMMEDIATE_INSTRS] Bits */
+#define SCB_ISAR1_IMMEDIATE_INSTRS_OFS                     (20)                  /* IMMEDIATE_INSTRS Offset */
+#define SCB_ISAR1_IMMEDIATE_INSTRS_M                       (0x00f00000)          /*  */
+#define SCB_ISAR1_IMMEDIATE_INSTRS0                        (0x00100000)          /*  */
+#define SCB_ISAR1_IMMEDIATE_INSTRS1                        (0x00200000)          /*  */
+#define SCB_ISAR1_IMMEDIATE_INSTRS2                        (0x00400000)          /*  */
+#define SCB_ISAR1_IMMEDIATE_INSTRS3                        (0x00800000)          /*  */
+#define SCB_ISAR1_IMMEDIATE_INSTRS_0                       (0x00000000)          /* no special immediate-generating instructions present */
+#define SCB_ISAR1_IMMEDIATE_INSTRS_1                       (0x00100000)          /* adds ADDW, MOVW, MOVT, SUBW */
+/* SCB_ISAR1[SCB_ISAR1_INTERWORK_INSTRS] Bits */
+#define SCB_ISAR1_INTERWORK_INSTRS_OFS                     (24)                  /* INTERWORK_INSTRS Offset */
+#define SCB_ISAR1_INTERWORK_INSTRS_M                       (0x0f000000)          /*  */
+#define SCB_ISAR1_INTERWORK_INSTRS0                        (0x01000000)          /*  */
+#define SCB_ISAR1_INTERWORK_INSTRS1                        (0x02000000)          /*  */
+#define SCB_ISAR1_INTERWORK_INSTRS2                        (0x04000000)          /*  */
+#define SCB_ISAR1_INTERWORK_INSTRS3                        (0x08000000)          /*  */
+#define SCB_ISAR1_INTERWORK_INSTRS_0                       (0x00000000)          /* no interworking instructions supported */
+#define SCB_ISAR1_INTERWORK_INSTRS_1                       (0x01000000)          /* adds BX (and T bit in PSRs) */
+#define SCB_ISAR1_INTERWORK_INSTRS_2                       (0x02000000)          /* adds BLX, and PC loads have BX-like behavior */
+#define SCB_ISAR1_INTERWORK_INSTRS_3                       (0x03000000)          /* N/A */
+/* SCB_ISAR2[SCB_ISAR2_LOADSTORE_INSTRS] Bits */
+#define SCB_ISAR2_LOADSTORE_INSTRS_OFS                     ( 0)                  /* LOADSTORE_INSTRS Offset */
+#define SCB_ISAR2_LOADSTORE_INSTRS_M                       (0x0000000f)          /*  */
+#define SCB_ISAR2_LOADSTORE_INSTRS0                        (0x00000001)          /*  */
+#define SCB_ISAR2_LOADSTORE_INSTRS1                        (0x00000002)          /*  */
+#define SCB_ISAR2_LOADSTORE_INSTRS2                        (0x00000004)          /*  */
+#define SCB_ISAR2_LOADSTORE_INSTRS3                        (0x00000008)          /*  */
+#define SCB_ISAR2_LOADSTORE_INSTRS_0                       (0x00000000)          /* no additional normal load/store instructions present */
+#define SCB_ISAR2_LOADSTORE_INSTRS_1                       (0x00000001)          /* adds LDRD/STRD */
+/* SCB_ISAR2[SCB_ISAR2_MEMHINT_INSTRS] Bits */
+#define SCB_ISAR2_MEMHINT_INSTRS_OFS                       ( 4)                  /* MEMHINT_INSTRS Offset */
+#define SCB_ISAR2_MEMHINT_INSTRS_M                         (0x000000f0)          /*  */
+#define SCB_ISAR2_MEMHINT_INSTRS0                          (0x00000010)          /*  */
+#define SCB_ISAR2_MEMHINT_INSTRS1                          (0x00000020)          /*  */
+#define SCB_ISAR2_MEMHINT_INSTRS2                          (0x00000040)          /*  */
+#define SCB_ISAR2_MEMHINT_INSTRS3                          (0x00000080)          /*  */
+#define SCB_ISAR2_MEMHINT_INSTRS_0                         (0x00000000)          /* no memory hint instructions presen */
+#define SCB_ISAR2_MEMHINT_INSTRS_1                         (0x00000010)          /* adds PLD */
+#define SCB_ISAR2_MEMHINT_INSTRS_2                         (0x00000020)          /* adds PLD (ie a repeat on value 1) */
+#define SCB_ISAR2_MEMHINT_INSTRS_3                         (0x00000030)          /* adds PLI */
+/* SCB_ISAR2[SCB_ISAR2_MULTIACCESSINT_INSTRS] Bits */
+#define SCB_ISAR2_MULTIACCESSINT_INSTRS_OFS                ( 8)                  /* MULTIACCESSINT_INSTRS Offset */
+#define SCB_ISAR2_MULTIACCESSINT_INSTRS_M                  (0x00000f00)          /*  */
+#define SCB_ISAR2_MULTIACCESSINT_INSTRS0                   (0x00000100)          /*  */
+#define SCB_ISAR2_MULTIACCESSINT_INSTRS1                   (0x00000200)          /*  */
+#define SCB_ISAR2_MULTIACCESSINT_INSTRS2                   (0x00000400)          /*  */
+#define SCB_ISAR2_MULTIACCESSINT_INSTRS3                   (0x00000800)          /*  */
+#define SCB_ISAR2_MULTIACCESSINT_INSTRS_0                  (0x00000000)          /* the (LDM/STM) instructions are non-interruptible */
+#define SCB_ISAR2_MULTIACCESSINT_INSTRS_1                  (0x00000100)          /* the (LDM/STM) instructions are restartable */
+#define SCB_ISAR2_MULTIACCESSINT_INSTRS_2                  (0x00000200)          /* the (LDM/STM) instructions are continuable */
+/* SCB_ISAR2[SCB_ISAR2_MULT_INSTRS] Bits */
+#define SCB_ISAR2_MULT_INSTRS_OFS                          (12)                  /* MULT_INSTRS Offset */
+#define SCB_ISAR2_MULT_INSTRS_M                            (0x0000f000)          /*  */
+#define SCB_ISAR2_MULT_INSTRS0                             (0x00001000)          /*  */
+#define SCB_ISAR2_MULT_INSTRS1                             (0x00002000)          /*  */
+#define SCB_ISAR2_MULT_INSTRS2                             (0x00004000)          /*  */
+#define SCB_ISAR2_MULT_INSTRS3                             (0x00008000)          /*  */
+#define SCB_ISAR2_MULT_INSTRS_0                            (0x00000000)          /* only MUL present */
+#define SCB_ISAR2_MULT_INSTRS_1                            (0x00001000)          /* adds MLA */
+#define SCB_ISAR2_MULT_INSTRS_2                            (0x00002000)          /* adds MLS */
+/* SCB_ISAR2[SCB_ISAR2_MULTS_INSTRS] Bits */
+#define SCB_ISAR2_MULTS_INSTRS_OFS                         (16)                  /* MULTS_INSTRS Offset */
+#define SCB_ISAR2_MULTS_INSTRS_M                           (0x000f0000)          /*  */
+#define SCB_ISAR2_MULTS_INSTRS0                            (0x00010000)          /*  */
+#define SCB_ISAR2_MULTS_INSTRS1                            (0x00020000)          /*  */
+#define SCB_ISAR2_MULTS_INSTRS2                            (0x00040000)          /*  */
+#define SCB_ISAR2_MULTS_INSTRS3                            (0x00080000)          /*  */
+#define SCB_ISAR2_MULTS_INSTRS_0                           (0x00000000)          /* no signed multiply instructions present */
+#define SCB_ISAR2_MULTS_INSTRS_1                           (0x00010000)          /* adds SMULL, SMLAL */
+#define SCB_ISAR2_MULTS_INSTRS_2                           (0x00020000)          /* N/A */
+#define SCB_ISAR2_MULTS_INSTRS_3                           (0x00030000)          /* N/A */
+/* SCB_ISAR2[SCB_ISAR2_MULTU_INSTRS] Bits */
+#define SCB_ISAR2_MULTU_INSTRS_OFS                         (20)                  /* MULTU_INSTRS Offset */
+#define SCB_ISAR2_MULTU_INSTRS_M                           (0x00f00000)          /*  */
+#define SCB_ISAR2_MULTU_INSTRS0                            (0x00100000)          /*  */
+#define SCB_ISAR2_MULTU_INSTRS1                            (0x00200000)          /*  */
+#define SCB_ISAR2_MULTU_INSTRS2                            (0x00400000)          /*  */
+#define SCB_ISAR2_MULTU_INSTRS3                            (0x00800000)          /*  */
+#define SCB_ISAR2_MULTU_INSTRS_0                           (0x00000000)          /* no unsigned multiply instructions present */
+#define SCB_ISAR2_MULTU_INSTRS_1                           (0x00100000)          /* adds UMULL, UMLAL */
+#define SCB_ISAR2_MULTU_INSTRS_2                           (0x00200000)          /* N/A */
+/* SCB_ISAR2[SCB_ISAR2_REVERSAL_INSTRS] Bits */
+#define SCB_ISAR2_REVERSAL_INSTRS_OFS                      (28)                  /* REVERSAL_INSTRS Offset */
+#define SCB_ISAR2_REVERSAL_INSTRS_M                        (0xf0000000)          /*  */
+#define SCB_ISAR2_REVERSAL_INSTRS0                         (0x10000000)          /*  */
+#define SCB_ISAR2_REVERSAL_INSTRS1                         (0x20000000)          /*  */
+#define SCB_ISAR2_REVERSAL_INSTRS2                         (0x40000000)          /*  */
+#define SCB_ISAR2_REVERSAL_INSTRS3                         (0x80000000)          /*  */
+#define SCB_ISAR2_REVERSAL_INSTRS_0                        (0x00000000)          /* no reversal instructions present */
+#define SCB_ISAR2_REVERSAL_INSTRS_1                        (0x10000000)          /* adds REV, REV16, REVSH */
+#define SCB_ISAR2_REVERSAL_INSTRS_2                        (0x20000000)          /* adds RBIT */
+/* SCB_ISAR3[SCB_ISAR3_SATRUATE_INSTRS] Bits */
+#define SCB_ISAR3_SATRUATE_INSTRS_OFS                      ( 0)                  /* SATRUATE_INSTRS Offset */
+#define SCB_ISAR3_SATRUATE_INSTRS_M                        (0x0000000f)          /*  */
+#define SCB_ISAR3_SATRUATE_INSTRS0                         (0x00000001)          /*  */
+#define SCB_ISAR3_SATRUATE_INSTRS1                         (0x00000002)          /*  */
+#define SCB_ISAR3_SATRUATE_INSTRS2                         (0x00000004)          /*  */
+#define SCB_ISAR3_SATRUATE_INSTRS3                         (0x00000008)          /*  */
+#define SCB_ISAR3_SATRUATE_INSTRS_0                        (0x00000000)          /* no non-SIMD saturate instructions present */
+#define SCB_ISAR3_SATRUATE_INSTRS_1                        (0x00000001)          /* N/A */
+/* SCB_ISAR3[SCB_ISAR3_SIMD_INSTRS] Bits */
+#define SCB_ISAR3_SIMD_INSTRS_OFS                          ( 4)                  /* SIMD_INSTRS Offset */
+#define SCB_ISAR3_SIMD_INSTRS_M                            (0x000000f0)          /*  */
+#define SCB_ISAR3_SIMD_INSTRS0                             (0x00000010)          /*  */
+#define SCB_ISAR3_SIMD_INSTRS1                             (0x00000020)          /*  */
+#define SCB_ISAR3_SIMD_INSTRS2                             (0x00000040)          /*  */
+#define SCB_ISAR3_SIMD_INSTRS3                             (0x00000080)          /*  */
+#define SCB_ISAR3_SIMD_INSTRS_0                            (0x00000000)          /* no SIMD instructions present */
+#define SCB_ISAR3_SIMD_INSTRS_1                            (0x00000010)          /* adds SSAT, USAT (and the Q flag in the PSRs) */
+#define SCB_ISAR3_SIMD_INSTRS_3                            (0x00000030)          /* N/A */
+/* SCB_ISAR3[SCB_ISAR3_SVC_INSTRS] Bits */
+#define SCB_ISAR3_SVC_INSTRS_OFS                           ( 8)                  /* SVC_INSTRS Offset */
+#define SCB_ISAR3_SVC_INSTRS_M                             (0x00000f00)          /*  */
+#define SCB_ISAR3_SVC_INSTRS0                              (0x00000100)          /*  */
+#define SCB_ISAR3_SVC_INSTRS1                              (0x00000200)          /*  */
+#define SCB_ISAR3_SVC_INSTRS2                              (0x00000400)          /*  */
+#define SCB_ISAR3_SVC_INSTRS3                              (0x00000800)          /*  */
+#define SCB_ISAR3_SVC_INSTRS_0                             (0x00000000)          /* no SVC (SWI) instructions present */
+#define SCB_ISAR3_SVC_INSTRS_1                             (0x00000100)          /* adds SVC (SWI) */
+/* SCB_ISAR3[SCB_ISAR3_SYNCPRIM_INSTRS] Bits */
+#define SCB_ISAR3_SYNCPRIM_INSTRS_OFS                      (12)                  /* SYNCPRIM_INSTRS Offset */
+#define SCB_ISAR3_SYNCPRIM_INSTRS_M                        (0x0000f000)          /*  */
+#define SCB_ISAR3_SYNCPRIM_INSTRS0                         (0x00001000)          /*  */
+#define SCB_ISAR3_SYNCPRIM_INSTRS1                         (0x00002000)          /*  */
+#define SCB_ISAR3_SYNCPRIM_INSTRS2                         (0x00004000)          /*  */
+#define SCB_ISAR3_SYNCPRIM_INSTRS3                         (0x00008000)          /*  */
+#define SCB_ISAR3_SYNCPRIM_INSTRS_0                        (0x00000000)          /* no synchronization primitives present */
+#define SCB_ISAR3_SYNCPRIM_INSTRS_1                        (0x00001000)          /* adds LDREX, STREX */
+#define SCB_ISAR3_SYNCPRIM_INSTRS_2                        (0x00002000)          /* adds LDREXB, LDREXH, LDREXD, STREXB, STREXH, STREXD, CLREX(N/A) */
+/* SCB_ISAR3[SCB_ISAR3_TABBRANCH_INSTRS] Bits */
+#define SCB_ISAR3_TABBRANCH_INSTRS_OFS                     (16)                  /* TABBRANCH_INSTRS Offset */
+#define SCB_ISAR3_TABBRANCH_INSTRS_M                       (0x000f0000)          /*  */
+#define SCB_ISAR3_TABBRANCH_INSTRS0                        (0x00010000)          /*  */
+#define SCB_ISAR3_TABBRANCH_INSTRS1                        (0x00020000)          /*  */
+#define SCB_ISAR3_TABBRANCH_INSTRS2                        (0x00040000)          /*  */
+#define SCB_ISAR3_TABBRANCH_INSTRS3                        (0x00080000)          /*  */
+#define SCB_ISAR3_TABBRANCH_INSTRS_0                       (0x00000000)          /* no table-branch instructions present */
+#define SCB_ISAR3_TABBRANCH_INSTRS_1                       (0x00010000)          /* adds TBB, TBH */
+/* SCB_ISAR3[SCB_ISAR3_THUMBCOPY_INSTRS] Bits */
+#define SCB_ISAR3_THUMBCOPY_INSTRS_OFS                     (20)                  /* THUMBCOPY_INSTRS Offset */
+#define SCB_ISAR3_THUMBCOPY_INSTRS_M                       (0x00f00000)          /*  */
+#define SCB_ISAR3_THUMBCOPY_INSTRS0                        (0x00100000)          /*  */
+#define SCB_ISAR3_THUMBCOPY_INSTRS1                        (0x00200000)          /*  */
+#define SCB_ISAR3_THUMBCOPY_INSTRS2                        (0x00400000)          /*  */
+#define SCB_ISAR3_THUMBCOPY_INSTRS3                        (0x00800000)          /*  */
+#define SCB_ISAR3_THUMBCOPY_INSTRS_0                       (0x00000000)          /* Thumb MOV(register) instruction does not allow low reg -> low reg */
+#define SCB_ISAR3_THUMBCOPY_INSTRS_1                       (0x00100000)          /* adds Thumb MOV(register) low reg -> low reg and the CPY alias */
+/* SCB_ISAR3[SCB_ISAR3_TRUENOP_INSTRS] Bits */
+#define SCB_ISAR3_TRUENOP_INSTRS_OFS                       (24)                  /* TRUENOP_INSTRS Offset */
+#define SCB_ISAR3_TRUENOP_INSTRS_M                         (0x0f000000)          /*  */
+#define SCB_ISAR3_TRUENOP_INSTRS0                          (0x01000000)          /*  */
+#define SCB_ISAR3_TRUENOP_INSTRS1                          (0x02000000)          /*  */
+#define SCB_ISAR3_TRUENOP_INSTRS2                          (0x04000000)          /*  */
+#define SCB_ISAR3_TRUENOP_INSTRS3                          (0x08000000)          /*  */
+#define SCB_ISAR3_TRUENOP_INSTRS_0                         (0x00000000)          /* true NOP instructions not present - that is, NOP instructions with no register dependencies */
+#define SCB_ISAR3_TRUENOP_INSTRS_1                         (0x01000000)          /* adds "true NOP", and the capability of additional "NOP compatible hints" */
+/* SCB_ISAR4[SCB_ISAR4_UNPRIV_INSTRS] Bits */
+#define SCB_ISAR4_UNPRIV_INSTRS_OFS                        ( 0)                  /* UNPRIV_INSTRS Offset */
+#define SCB_ISAR4_UNPRIV_INSTRS_M                          (0x0000000f)          /*  */
+#define SCB_ISAR4_UNPRIV_INSTRS0                           (0x00000001)          /*  */
+#define SCB_ISAR4_UNPRIV_INSTRS1                           (0x00000002)          /*  */
+#define SCB_ISAR4_UNPRIV_INSTRS2                           (0x00000004)          /*  */
+#define SCB_ISAR4_UNPRIV_INSTRS3                           (0x00000008)          /*  */
+#define SCB_ISAR4_UNPRIV_INSTRS_0                          (0x00000000)          /* no "T variant" instructions exist */
+#define SCB_ISAR4_UNPRIV_INSTRS_1                          (0x00000001)          /* adds LDRBT, LDRT, STRBT, STRT */
+#define SCB_ISAR4_UNPRIV_INSTRS_2                          (0x00000002)          /* adds LDRHT, LDRSBT, LDRSHT, STRHT */
+/* SCB_ISAR4[SCB_ISAR4_WITHSHIFTS_INSTRS] Bits */
+#define SCB_ISAR4_WITHSHIFTS_INSTRS_OFS                    ( 4)                  /* WITHSHIFTS_INSTRS Offset */
+#define SCB_ISAR4_WITHSHIFTS_INSTRS_M                      (0x000000f0)          /*  */
+#define SCB_ISAR4_WITHSHIFTS_INSTRS0                       (0x00000010)          /*  */
+#define SCB_ISAR4_WITHSHIFTS_INSTRS1                       (0x00000020)          /*  */
+#define SCB_ISAR4_WITHSHIFTS_INSTRS2                       (0x00000040)          /*  */
+#define SCB_ISAR4_WITHSHIFTS_INSTRS3                       (0x00000080)          /*  */
+#define SCB_ISAR4_WITHSHIFTS_INSTRS_0                      (0x00000000)          /* non-zero shifts only support MOV and shift instructions (see notes) */
+#define SCB_ISAR4_WITHSHIFTS_INSTRS_1                      (0x00000010)          /* shifts of loads/stores over the range LSL 0-3 */
+#define SCB_ISAR4_WITHSHIFTS_INSTRS_3                      (0x00000030)          /* adds other constant shift options. */
+#define SCB_ISAR4_WITHSHIFTS_INSTRS_4                      (0x00000040)          /* adds register-controlled shift options. */
+/* SCB_ISAR4[SCB_ISAR4_WRITEBACK_INSTRS] Bits */
+#define SCB_ISAR4_WRITEBACK_INSTRS_OFS                     ( 8)                  /* WRITEBACK_INSTRS Offset */
+#define SCB_ISAR4_WRITEBACK_INSTRS_M                       (0x00000f00)          /*  */
+#define SCB_ISAR4_WRITEBACK_INSTRS0                        (0x00000100)          /*  */
+#define SCB_ISAR4_WRITEBACK_INSTRS1                        (0x00000200)          /*  */
+#define SCB_ISAR4_WRITEBACK_INSTRS2                        (0x00000400)          /*  */
+#define SCB_ISAR4_WRITEBACK_INSTRS3                        (0x00000800)          /*  */
+#define SCB_ISAR4_WRITEBACK_INSTRS_0                       (0x00000000)          /* only non-writeback addressing modes present, except that LDMIA/STMDB/PUSH/POP instructions support writeback addressing. */
+#define SCB_ISAR4_WRITEBACK_INSTRS_1                       (0x00000100)          /* adds all currently-defined writeback addressing modes (ARMv7, Thumb-2) */
+/* SCB_ISAR4[SCB_ISAR4_BARRIER_INSTRS] Bits */
+#define SCB_ISAR4_BARRIER_INSTRS_OFS                       (16)                  /* BARRIER_INSTRS Offset */
+#define SCB_ISAR4_BARRIER_INSTRS_M                         (0x000f0000)          /*  */
+#define SCB_ISAR4_BARRIER_INSTRS0                          (0x00010000)          /*  */
+#define SCB_ISAR4_BARRIER_INSTRS1                          (0x00020000)          /*  */
+#define SCB_ISAR4_BARRIER_INSTRS2                          (0x00040000)          /*  */
+#define SCB_ISAR4_BARRIER_INSTRS3                          (0x00080000)          /*  */
+#define SCB_ISAR4_BARRIER_INSTRS_0                         (0x00000000)          /* no barrier instructions supported */
+#define SCB_ISAR4_BARRIER_INSTRS_1                         (0x00010000)          /* adds DMB, DSB, ISB barrier instructions */
+/* SCB_ISAR4[SCB_ISAR4_SYNCPRIM_INSTRS_FRAC] Bits */
+#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_OFS                 (20)                  /* SYNCPRIM_INSTRS_FRAC Offset */
+#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_M                   (0x00f00000)          /*  */
+#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC0                    (0x00100000)          /*  */
+#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC1                    (0x00200000)          /*  */
+#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC2                    (0x00400000)          /*  */
+#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC3                    (0x00800000)          /*  */
+#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_0                   (0x00000000)          /* no additional support */
+#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_3                   (0x00300000)          /* adds CLREX, LDREXB, STREXB, LDREXH, STREXH */
+/* SCB_ISAR4[SCB_ISAR4_PSR_M_INSTRS] Bits */
+#define SCB_ISAR4_PSR_M_INSTRS_OFS                         (24)                  /* PSR_M_INSTRS Offset */
+#define SCB_ISAR4_PSR_M_INSTRS_M                           (0x0f000000)          /*  */
+#define SCB_ISAR4_PSR_M_INSTRS0                            (0x01000000)          /*  */
+#define SCB_ISAR4_PSR_M_INSTRS1                            (0x02000000)          /*  */
+#define SCB_ISAR4_PSR_M_INSTRS2                            (0x04000000)          /*  */
+#define SCB_ISAR4_PSR_M_INSTRS3                            (0x08000000)          /*  */
+#define SCB_ISAR4_PSR_M_INSTRS_0                           (0x00000000)          /* instructions not present */
+#define SCB_ISAR4_PSR_M_INSTRS_1                           (0x01000000)          /* adds CPS, MRS, and MSR instructions (M-profile forms) */
+/* SCB_CPACR[SCB_CPACR_CP11] Bits */
+#define SCB_CPACR_CP11_OFS                                 (22)                  /* CP11 Offset */
+#define SCB_CPACR_CP11_M                                   (0x00c00000)          /*  */
+/* SCB_CPACR[SCB_CPACR_CP10] Bits */
+#define SCB_CPACR_CP10_OFS                                 (20)                  /* CP10 Offset */
+#define SCB_CPACR_CP10_M                                   (0x00300000)          /*  */
+
+
+//*****************************************************************************
+// SCnSCB Bits
+//*****************************************************************************
+/* SCSCB_ICTR[SCNSCB_ICTR_INTLINESNUM] Bits */
+#define SCNSCB_ICTR_INTLINESNUM_OFS                        ( 0)                  /* INTLINESNUM Offset */
+#define SCNSCB_ICTR_INTLINESNUM_M                          (0x0000001f)          /*  */
+/* SCSCB_ACTLR[SCNSCB_ACTLR_DISMCYCINT] Bits */
+#define SCNSCB_ACTLR_DISMCYCINT_OFS                        ( 0)                  /* DISMCYCINT Offset */
+#define SCNSCB_ACTLR_DISMCYCINT                            (0x00000001)          /*  */
+/* SCSCB_ACTLR[SCNSCB_ACTLR_DISDEFWBUF] Bits */
+#define SCNSCB_ACTLR_DISDEFWBUF_OFS                        ( 1)                  /* DISDEFWBUF Offset */
+#define SCNSCB_ACTLR_DISDEFWBUF                            (0x00000002)          /*  */
+/* SCSCB_ACTLR[SCNSCB_ACTLR_DISFOLD] Bits */
+#define SCNSCB_ACTLR_DISFOLD_OFS                           ( 2)                  /* DISFOLD Offset */
+#define SCNSCB_ACTLR_DISFOLD                               (0x00000004)          /*  */
+
+
+//*****************************************************************************
+// SYSCTL Bits
+//*****************************************************************************
+/* SYSCTL_REBOOT_CTL[SYSCTL_REBOOT_CTL_REBOOT] Bits */
+#define SYSCTL_REBOOT_CTL_REBOOT_OFS                       ( 0)                  /* REBOOT Offset */
+#define SYSCTL_REBOOT_CTL_REBOOT                           (0x00000001)          /* Write 1 initiates a Reboot of the device */
+/* SYSCTL_REBOOT_CTL[SYSCTL_REBOOT_CTL_WKEY] Bits */
+#define SYSCTL_REBOOT_CTL_WKEY_OFS                         ( 8)                  /* WKEY Offset */
+#define SYSCTL_REBOOT_CTL_WKEY_M                           (0x0000ff00)          /* Key to enable writes to bit 0 */
+/* SYSCTL_NMI_CTLSTAT[SYSCTL_NMI_CTLSTAT_CS_SRC] Bits */
+#define SYSCTL_NMI_CTLSTAT_CS_SRC_OFS                      ( 0)                  /* CS_SRC Offset */
+#define SYSCTL_NMI_CTLSTAT_CS_SRC                          (0x00000001)          /* CS interrupt as a source of NMI */
+/* SYSCTL_NMI_CTLSTAT[SYSCTL_NMI_CTLSTAT_PSS_SRC] Bits */
+#define SYSCTL_NMI_CTLSTAT_PSS_SRC_OFS                     ( 1)                  /* PSS_SRC Offset */
+#define SYSCTL_NMI_CTLSTAT_PSS_SRC                         (0x00000002)          /* PSS interrupt as a source of NMI */
+/* SYSCTL_NMI_CTLSTAT[SYSCTL_NMI_CTLSTAT_PCM_SRC] Bits */
+#define SYSCTL_NMI_CTLSTAT_PCM_SRC_OFS                     ( 2)                  /* PCM_SRC Offset */
+#define SYSCTL_NMI_CTLSTAT_PCM_SRC                         (0x00000004)          /* PCM interrupt as a source of NMI */
+/* SYSCTL_NMI_CTLSTAT[SYSCTL_NMI_CTLSTAT_PIN_SRC] Bits */
+#define SYSCTL_NMI_CTLSTAT_PIN_SRC_OFS                     ( 3)                  /* PIN_SRC Offset */
+#define SYSCTL_NMI_CTLSTAT_PIN_SRC                         (0x00000008)          /*  */
+/* SYSCTL_NMI_CTLSTAT[SYSCTL_NMI_CTLSTAT_CS_FLG] Bits */
+#define SYSCTL_NMI_CTLSTAT_CS_FLG_OFS                      (16)                  /* CS_FLG Offset */
+#define SYSCTL_NMI_CTLSTAT_CS_FLG                          (0x00010000)          /* CS interrupt was the source of NMI */
+/* SYSCTL_NMI_CTLSTAT[SYSCTL_NMI_CTLSTAT_PSS_FLG] Bits */
+#define SYSCTL_NMI_CTLSTAT_PSS_FLG_OFS                     (17)                  /* PSS_FLG Offset */
+#define SYSCTL_NMI_CTLSTAT_PSS_FLG                         (0x00020000)          /* PSS interrupt was the source of NMI */
+/* SYSCTL_NMI_CTLSTAT[SYSCTL_NMI_CTLSTAT_PCM_FLG] Bits */
+#define SYSCTL_NMI_CTLSTAT_PCM_FLG_OFS                     (18)                  /* PCM_FLG Offset */
+#define SYSCTL_NMI_CTLSTAT_PCM_FLG                         (0x00040000)          /* PCM interrupt was the source of NMI */
+/* SYSCTL_NMI_CTLSTAT[SYSCTL_NMI_CTLSTAT_PIN_FLG] Bits */
+#define SYSCTL_NMI_CTLSTAT_PIN_FLG_OFS                     (19)                  /* PIN_FLG Offset */
+#define SYSCTL_NMI_CTLSTAT_PIN_FLG                         (0x00080000)          /* RSTn/NMI pin was the source of NMI */
+/* SYSCTL_WDTRESET_CTL[SYSCTL_WDTRESET_CTL_TIMEOUT] Bits */
+#define SYSCTL_WDTRESET_CTL_TIMEOUT_OFS                    ( 0)                  /* TIMEOUT Offset */
+#define SYSCTL_WDTRESET_CTL_TIMEOUT                        (0x00000001)          /* WDT timeout reset type */
+/* SYSCTL_WDTRESET_CTL[SYSCTL_WDTRESET_CTL_VIOLATION] Bits */
+#define SYSCTL_WDTRESET_CTL_VIOLATION_OFS                  ( 1)                  /* VIOLATION Offset */
+#define SYSCTL_WDTRESET_CTL_VIOLATION                      (0x00000002)          /* WDT password violation reset type */
+/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_T16_0] Bits */
+#define SYSCTL_PERIHALT_CTL_T16_0_OFS                      ( 0)                  /* T16_0 Offset */
+#define SYSCTL_PERIHALT_CTL_T16_0                          (0x00000001)          /* Freezes IP operation when CPU is halted */
+/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_T16_1] Bits */
+#define SYSCTL_PERIHALT_CTL_T16_1_OFS                      ( 1)                  /* T16_1 Offset */
+#define SYSCTL_PERIHALT_CTL_T16_1                          (0x00000002)          /* Freezes IP operation when CPU is halted */
+/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_T16_2] Bits */
+#define SYSCTL_PERIHALT_CTL_T16_2_OFS                      ( 2)                  /* T16_2 Offset */
+#define SYSCTL_PERIHALT_CTL_T16_2                          (0x00000004)          /* Freezes IP operation when CPU is halted */
+/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_T16_3] Bits */
+#define SYSCTL_PERIHALT_CTL_T16_3_OFS                      ( 3)                  /* T16_3 Offset */
+#define SYSCTL_PERIHALT_CTL_T16_3                          (0x00000008)          /* Freezes IP operation when CPU is halted */
+/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_T32_0] Bits */
+#define SYSCTL_PERIHALT_CTL_T32_0_OFS                      ( 4)                  /* T32_0 Offset */
+#define SYSCTL_PERIHALT_CTL_T32_0                          (0x00000010)          /* Freezes IP operation when CPU is halted */
+/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_EUA0] Bits */
+#define SYSCTL_PERIHALT_CTL_EUA0_OFS                       ( 5)                  /* eUA0 Offset */
+#define SYSCTL_PERIHALT_CTL_EUA0                           (0x00000020)          /* Freezes IP operation when CPU is halted */
+/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_EUA1] Bits */
+#define SYSCTL_PERIHALT_CTL_EUA1_OFS                       ( 6)                  /* eUA1 Offset */
+#define SYSCTL_PERIHALT_CTL_EUA1                           (0x00000040)          /* Freezes IP operation when CPU is halted */
+/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_EUA2] Bits */
+#define SYSCTL_PERIHALT_CTL_EUA2_OFS                       ( 7)                  /* eUA2 Offset */
+#define SYSCTL_PERIHALT_CTL_EUA2                           (0x00000080)          /* Freezes IP operation when CPU is halted */
+/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_EUA3] Bits */
+#define SYSCTL_PERIHALT_CTL_EUA3_OFS                       ( 8)                  /* eUA3 Offset */
+#define SYSCTL_PERIHALT_CTL_EUA3                           (0x00000100)          /* Freezes IP operation when CPU is halted */
+/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_EUB0] Bits */
+#define SYSCTL_PERIHALT_CTL_EUB0_OFS                       ( 9)                  /* eUB0 Offset */
+#define SYSCTL_PERIHALT_CTL_EUB0                           (0x00000200)          /* Freezes IP operation when CPU is halted */
+/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_EUB1] Bits */
+#define SYSCTL_PERIHALT_CTL_EUB1_OFS                       (10)                  /* eUB1 Offset */
+#define SYSCTL_PERIHALT_CTL_EUB1                           (0x00000400)          /* Freezes IP operation when CPU is halted */
+/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_EUB2] Bits */
+#define SYSCTL_PERIHALT_CTL_EUB2_OFS                       (11)                  /* eUB2 Offset */
+#define SYSCTL_PERIHALT_CTL_EUB2                           (0x00000800)          /* Freezes IP operation when CPU is halted */
+/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_EUB3] Bits */
+#define SYSCTL_PERIHALT_CTL_EUB3_OFS                       (12)                  /* eUB3 Offset */
+#define SYSCTL_PERIHALT_CTL_EUB3                           (0x00001000)          /* Freezes IP operation when CPU is halted */
+/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_ADC] Bits */
+#define SYSCTL_PERIHALT_CTL_ADC_OFS                        (13)                  /* ADC Offset */
+#define SYSCTL_PERIHALT_CTL_ADC                            (0x00002000)          /* Freezes IP operation when CPU is halted */
+/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_WDT] Bits */
+#define SYSCTL_PERIHALT_CTL_WDT_OFS                        (14)                  /* WDT Offset */
+#define SYSCTL_PERIHALT_CTL_WDT                            (0x00004000)          /* Freezes IP operation when CPU is halted */
+/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_DMA] Bits */
+#define SYSCTL_PERIHALT_CTL_DMA_OFS                        (15)                  /* DMA Offset */
+#define SYSCTL_PERIHALT_CTL_DMA                            (0x00008000)          /* Freezes IP operation when CPU is halted */
+/* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_BNK0_EN] Bits */
+#define SYSCTL_SRAM_BANKEN_BNK0_EN_OFS                     ( 0)                  /* BNK0_EN Offset */
+#define SYSCTL_SRAM_BANKEN_BNK0_EN                         (0x00000001)          /* SRAM Bank0 enable */
+/* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_BNK1_EN] Bits */
+#define SYSCTL_SRAM_BANKEN_BNK1_EN_OFS                     ( 1)                  /* BNK1_EN Offset */
+#define SYSCTL_SRAM_BANKEN_BNK1_EN                         (0x00000002)          /* SRAM Bank1 enable */
+/* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_BNK2_EN] Bits */
+#define SYSCTL_SRAM_BANKEN_BNK2_EN_OFS                     ( 2)                  /* BNK2_EN Offset */
+#define SYSCTL_SRAM_BANKEN_BNK2_EN                         (0x00000004)          /* SRAM Bank1 enable */
+/* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_BNK3_EN] Bits */
+#define SYSCTL_SRAM_BANKEN_BNK3_EN_OFS                     ( 3)                  /* BNK3_EN Offset */
+#define SYSCTL_SRAM_BANKEN_BNK3_EN                         (0x00000008)          /* SRAM Bank1 enable */
+/* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_BNK4_EN] Bits */
+#define SYSCTL_SRAM_BANKEN_BNK4_EN_OFS                     ( 4)                  /* BNK4_EN Offset */
+#define SYSCTL_SRAM_BANKEN_BNK4_EN                         (0x00000010)          /* SRAM Bank1 enable */
+/* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_BNK5_EN] Bits */
+#define SYSCTL_SRAM_BANKEN_BNK5_EN_OFS                     ( 5)                  /* BNK5_EN Offset */
+#define SYSCTL_SRAM_BANKEN_BNK5_EN                         (0x00000020)          /* SRAM Bank1 enable */
+/* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_BNK6_EN] Bits */
+#define SYSCTL_SRAM_BANKEN_BNK6_EN_OFS                     ( 6)                  /* BNK6_EN Offset */
+#define SYSCTL_SRAM_BANKEN_BNK6_EN                         (0x00000040)          /* SRAM Bank1 enable */
+/* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_BNK7_EN] Bits */
+#define SYSCTL_SRAM_BANKEN_BNK7_EN_OFS                     ( 7)                  /* BNK7_EN Offset */
+#define SYSCTL_SRAM_BANKEN_BNK7_EN                         (0x00000080)          /* SRAM Bank1 enable */
+/* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_SRAM_RDY] Bits */
+#define SYSCTL_SRAM_BANKEN_SRAM_RDY_OFS                    (16)                  /* SRAM_RDY Offset */
+#define SYSCTL_SRAM_BANKEN_SRAM_RDY                        (0x00010000)          /* SRAM ready */
+/* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_BNK0_RET] Bits */
+#define SYSCTL_SRAM_BANKRET_BNK0_RET_OFS                   ( 0)                  /* BNK0_RET Offset */
+#define SYSCTL_SRAM_BANKRET_BNK0_RET                       (0x00000001)          /* Bank0 retention */
+/* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_BNK1_RET] Bits */
+#define SYSCTL_SRAM_BANKRET_BNK1_RET_OFS                   ( 1)                  /* BNK1_RET Offset */
+#define SYSCTL_SRAM_BANKRET_BNK1_RET                       (0x00000002)          /* Bank1 retention */
+/* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_BNK2_RET] Bits */
+#define SYSCTL_SRAM_BANKRET_BNK2_RET_OFS                   ( 2)                  /* BNK2_RET Offset */
+#define SYSCTL_SRAM_BANKRET_BNK2_RET                       (0x00000004)          /* Bank2 retention */
+/* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_BNK3_RET] Bits */
+#define SYSCTL_SRAM_BANKRET_BNK3_RET_OFS                   ( 3)                  /* BNK3_RET Offset */
+#define SYSCTL_SRAM_BANKRET_BNK3_RET                       (0x00000008)          /* Bank3 retention */
+/* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_BNK4_RET] Bits */
+#define SYSCTL_SRAM_BANKRET_BNK4_RET_OFS                   ( 4)                  /* BNK4_RET Offset */
+#define SYSCTL_SRAM_BANKRET_BNK4_RET                       (0x00000010)          /* Bank4 retention */
+/* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_BNK5_RET] Bits */
+#define SYSCTL_SRAM_BANKRET_BNK5_RET_OFS                   ( 5)                  /* BNK5_RET Offset */
+#define SYSCTL_SRAM_BANKRET_BNK5_RET                       (0x00000020)          /* Bank5 retention */
+/* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_BNK6_RET] Bits */
+#define SYSCTL_SRAM_BANKRET_BNK6_RET_OFS                   ( 6)                  /* BNK6_RET Offset */
+#define SYSCTL_SRAM_BANKRET_BNK6_RET                       (0x00000040)          /* Bank6 retention */
+/* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_BNK7_RET] Bits */
+#define SYSCTL_SRAM_BANKRET_BNK7_RET_OFS                   ( 7)                  /* BNK7_RET Offset */
+#define SYSCTL_SRAM_BANKRET_BNK7_RET                       (0x00000080)          /* Bank7 retention */
+/* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_SRAM_RDY] Bits */
+#define SYSCTL_SRAM_BANKRET_SRAM_RDY_OFS                   (16)                  /* SRAM_RDY Offset */
+#define SYSCTL_SRAM_BANKRET_SRAM_RDY                       (0x00010000)          /* SRAM ready */
+/* SYSCTL_DIO_GLTFLT_CTL[SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN] Bits */
+#define SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN_OFS                 ( 0)                  /* GLTCH_EN Offset */
+#define SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN                     (0x00000001)          /* Glitch filter enable */
+/* SYSCTL_SECDATA_UNLOCK[SYSCTL_SECDATA_UNLOCK_UNLKEY] Bits */
+#define SYSCTL_SECDATA_UNLOCK_UNLKEY_OFS                   ( 0)                  /* UNLKEY Offset */
+#define SYSCTL_SECDATA_UNLOCK_UNLKEY_M                     (0x0000ffff)          /* Unlock key */
+/* SYSCTL_MASTER_UNLOCK[SYSCTL_MASTER_UNLOCK_UNLKEY] Bits */
+#define SYSCTL_MASTER_UNLOCK_UNLKEY_OFS                    ( 0)                  /* UNLKEY Offset */
+#define SYSCTL_MASTER_UNLOCK_UNLKEY_M                      (0x0000ffff)          /* Unlock Key */
+/* SYSCTL_RESET_REQ[SYSCTL_RESET_REQ_POR] Bits */
+#define SYSCTL_RESET_REQ_POR_OFS                           ( 0)                  /* POR Offset */
+#define SYSCTL_RESET_REQ_POR                               (0x00000001)          /* Generate POR */
+/* SYSCTL_RESET_REQ[SYSCTL_RESET_REQ_REBOOT] Bits */
+#define SYSCTL_RESET_REQ_REBOOT_OFS                        ( 1)                  /* REBOOT Offset */
+#define SYSCTL_RESET_REQ_REBOOT                            (0x00000002)          /* Generate Reboot_Reset */
+/* SYSCTL_RESET_REQ[SYSCTL_RESET_REQ_WKEY] Bits */
+#define SYSCTL_RESET_REQ_WKEY_OFS                          ( 8)                  /* WKEY Offset */
+#define SYSCTL_RESET_REQ_WKEY_M                            (0x0000ff00)          /* Write key */
+/* SYSCTL_RESET_STATOVER[SYSCTL_RESET_STATOVER_SOFT] Bits */
+#define SYSCTL_RESET_STATOVER_SOFT_OFS                     ( 0)                  /* SOFT Offset */
+#define SYSCTL_RESET_STATOVER_SOFT                         (0x00000001)          /* Indicates if SOFT Reset is active */
+/* SYSCTL_RESET_STATOVER[SYSCTL_RESET_STATOVER_HARD] Bits */
+#define SYSCTL_RESET_STATOVER_HARD_OFS                     ( 1)                  /* HARD Offset */
+#define SYSCTL_RESET_STATOVER_HARD                         (0x00000002)          /* Indicates if HARD Reset is active */
+/* SYSCTL_RESET_STATOVER[SYSCTL_RESET_STATOVER_REBOOT] Bits */
+#define SYSCTL_RESET_STATOVER_REBOOT_OFS                   ( 2)                  /* REBOOT Offset */
+#define SYSCTL_RESET_STATOVER_REBOOT                       (0x00000004)          /* Indicates if Reboot Reset is active */
+/* SYSCTL_RESET_STATOVER[SYSCTL_RESET_STATOVER_SOFT_OVER] Bits */
+#define SYSCTL_RESET_STATOVER_SOFT_OVER_OFS                ( 8)                  /* SOFT_OVER Offset */
+#define SYSCTL_RESET_STATOVER_SOFT_OVER                    (0x00000100)          /* SOFT_Reset overwrite request */
+/* SYSCTL_RESET_STATOVER[SYSCTL_RESET_STATOVER_HARD_OVER] Bits */
+#define SYSCTL_RESET_STATOVER_HARD_OVER_OFS                ( 9)                  /* HARD_OVER Offset */
+#define SYSCTL_RESET_STATOVER_HARD_OVER                    (0x00000200)          /* HARD_Reset overwrite request */
+/* SYSCTL_RESET_STATOVER[SYSCTL_RESET_STATOVER_RBT_OVER] Bits */
+#define SYSCTL_RESET_STATOVER_RBT_OVER_OFS                 (10)                  /* RBT_OVER Offset */
+#define SYSCTL_RESET_STATOVER_RBT_OVER                     (0x00000400)          /* Reboot Reset overwrite request */
+/* SYSCTL_SYSTEM_STAT[SYSCTL_SYSTEM_STAT_DBG_SEC_ACT] Bits */
+#define SYSCTL_SYSTEM_STAT_DBG_SEC_ACT_OFS                 ( 3)                  /* DBG_SEC_ACT Offset */
+#define SYSCTL_SYSTEM_STAT_DBG_SEC_ACT                     (0x00000008)          /* Debug Security active */
+/* SYSCTL_SYSTEM_STAT[SYSCTL_SYSTEM_STAT_JTAG_SWD_LOCK_ACT] Bits */
+#define SYSCTL_SYSTEM_STAT_JTAG_SWD_LOCK_ACT_OFS           ( 4)                  /* JTAG_SWD_LOCK_ACT Offset */
+#define SYSCTL_SYSTEM_STAT_JTAG_SWD_LOCK_ACT               (0x00000010)          /* Indicates if JTAG and SWD Lock is active */
+/* SYSCTL_SYSTEM_STAT[SYSCTL_SYSTEM_STAT_IP_PROT_ACT] Bits */
+#define SYSCTL_SYSTEM_STAT_IP_PROT_ACT_OFS                 ( 5)                  /* IP_PROT_ACT Offset */
+#define SYSCTL_SYSTEM_STAT_IP_PROT_ACT                     (0x00000020)          /* Indicates if IP protection is active */
+
+/* Pre-defined bitfield values */
+#define SYSCTL_REBOOT_CTL_WKEY_VAL                         (0x00006900)          /* Key value to enable writes to bit 0 */
+                                                                                /* cleared */
+
+//*****************************************************************************
+// SYSTICK Bits
+//*****************************************************************************
+/* SYSTICK_STCSR[SYSTICK_STCSR_ENABLE] Bits */
+#define SYSTICK_STCSR_ENABLE_OFS                           ( 0)                  /* ENABLE Offset */
+#define SYSTICK_STCSR_ENABLE                               (0x00000001)          /*  */
+/* SYSTICK_STCSR[SYSTICK_STCSR_TICKINT] Bits */
+#define SYSTICK_STCSR_TICKINT_OFS                          ( 1)                  /* TICKINT Offset */
+#define SYSTICK_STCSR_TICKINT                              (0x00000002)          /*  */
+/* SYSTICK_STCSR[SYSTICK_STCSR_CLKSOURCE] Bits */
+#define SYSTICK_STCSR_CLKSOURCE_OFS                        ( 2)                  /* CLKSOURCE Offset */
+#define SYSTICK_STCSR_CLKSOURCE                            (0x00000004)          /*  */
+/* SYSTICK_STCSR[SYSTICK_STCSR_COUNTFLAG] Bits */
+#define SYSTICK_STCSR_COUNTFLAG_OFS                        (16)                  /* COUNTFLAG Offset */
+#define SYSTICK_STCSR_COUNTFLAG                            (0x00010000)          /*  */
+/* SYSTICK_STRVR[SYSTICK_STRVR_RELOAD] Bits */
+#define SYSTICK_STRVR_RELOAD_OFS                           ( 0)                  /* RELOAD Offset */
+#define SYSTICK_STRVR_RELOAD_M                             (0x00ffffff)          /*  */
+/* SYSTICK_STCVR[SYSTICK_STCVR_CURRENT] Bits */
+#define SYSTICK_STCVR_CURRENT_OFS                          ( 0)                  /* CURRENT Offset */
+#define SYSTICK_STCVR_CURRENT_M                            (0x00ffffff)          /*  */
+/* SYSTICK_STCR[SYSTICK_STCR_TENMS] Bits */
+#define SYSTICK_STCR_TENMS_OFS                             ( 0)                  /* TENMS Offset */
+#define SYSTICK_STCR_TENMS_M                               (0x00ffffff)          /*  */
+/* SYSTICK_STCR[SYSTICK_STCR_SKEW] Bits */
+#define SYSTICK_STCR_SKEW_OFS                              (30)                  /* SKEW Offset */
+#define SYSTICK_STCR_SKEW                                  (0x40000000)          /*  */
+/* SYSTICK_STCR[SYSTICK_STCR_NOREF] Bits */
+#define SYSTICK_STCR_NOREF_OFS                             (31)                  /* NOREF Offset */
+#define SYSTICK_STCR_NOREF                                 (0x80000000)          /*  */
+
+
+//*****************************************************************************
+// TIMER32 Bits
+//*****************************************************************************
+/* TIMER32_CONTROL1[TIMER32_CONTROL1_ONESHOT] Bits */
+#define TIMER32_CONTROL1_ONESHOT_OFS                       ( 0)                  /* ONESHOT Offset */
+#define TIMER32_CONTROL1_ONESHOT                           (0x00000001)          /* Selects one-shot or wrapping counter mode */
+/* TIMER32_CONTROL1[TIMER32_CONTROL1_SIZE] Bits */
+#define TIMER32_CONTROL1_SIZE_OFS                          ( 1)                  /* SIZE Offset */
+#define TIMER32_CONTROL1_SIZE                              (0x00000002)          /* Selects 16 or 32 bit counter operation */
+/* TIMER32_CONTROL1[TIMER32_CONTROL1_PRESCALE] Bits */
+#define TIMER32_CONTROL1_PRESCALE_OFS                      ( 2)                  /* PRESCALE Offset */
+#define TIMER32_CONTROL1_PRESCALE_M                        (0x0000000c)          /* Prescale bits */
+#define TIMER32_CONTROL1_PRESCALE0                         (0x00000004)          /* Prescale bits */
+#define TIMER32_CONTROL1_PRESCALE1                         (0x00000008)          /* Prescale bits */
+#define TIMER32_CONTROL1_PRESCALE_0                        (0x00000000)          /* 0 stages of prescale, clock is divided by 1 */
+#define TIMER32_CONTROL1_PRESCALE_1                        (0x00000004)          /* 4 stages of prescale, clock is divided by 16 */
+#define TIMER32_CONTROL1_PRESCALE_2                        (0x00000008)          /* 8 stages of prescale, clock is divided by 256 */
+/* TIMER32_CONTROL1[TIMER32_CONTROL1_IE] Bits */
+#define TIMER32_CONTROL1_IE_OFS                            ( 5)                  /* IE Offset */
+#define TIMER32_CONTROL1_IE                                (0x00000020)          /* Interrupt enable bit */
+/* TIMER32_CONTROL1[TIMER32_CONTROL1_MODE] Bits */
+#define TIMER32_CONTROL1_MODE_OFS                          ( 6)                  /* MODE Offset */
+#define TIMER32_CONTROL1_MODE                              (0x00000040)          /* Mode bit */
+/* TIMER32_CONTROL1[TIMER32_CONTROL1_ENABLE] Bits */
+#define TIMER32_CONTROL1_ENABLE_OFS                        ( 7)                  /* ENABLE Offset */
+#define TIMER32_CONTROL1_ENABLE                            (0x00000080)          /*  */
+/* TIMER32_RIS1[TIMER32_RIS1_RAW_IFG] Bits */
+#define TIMER32_RIS1_RAW_IFG_OFS                           ( 0)                  /* RAW_IFG Offset */
+#define TIMER32_RIS1_RAW_IFG                               (0x00000001)          /* Raw interrupt status */
+/* TIMER32_MIS1[TIMER32_MIS1_] Bits */
+#define TIMER32_MIS1__OFS                                  ( 0)                  /* IFG Offset */
+#define TIMER32_MIS1_                                      (0x00000001)          /* Enabled interrupt status */
+/* TIMER32_CONTROL2[TIMER32_CONTROL2_ONESHOT] Bits */
+#define TIMER32_CONTROL2_ONESHOT_OFS                       ( 0)                  /* ONESHOT Offset */
+#define TIMER32_CONTROL2_ONESHOT                           (0x00000001)          /* Selects one-shot or wrapping counter mode */
+/* TIMER32_CONTROL2[TIMER32_CONTROL2_SIZE] Bits */
+#define TIMER32_CONTROL2_SIZE_OFS                          ( 1)                  /* SIZE Offset */
+#define TIMER32_CONTROL2_SIZE                              (0x00000002)          /* Selects 16 or 32 bit counter operation */
+/* TIMER32_CONTROL2[TIMER32_CONTROL2_PRESCALE] Bits */
+#define TIMER32_CONTROL2_PRESCALE_OFS                      ( 2)                  /* PRESCALE Offset */
+#define TIMER32_CONTROL2_PRESCALE_M                        (0x0000000c)          /* Prescale bits */
+#define TIMER32_CONTROL2_PRESCALE0                         (0x00000004)          /* Prescale bits */
+#define TIMER32_CONTROL2_PRESCALE1                         (0x00000008)          /* Prescale bits */
+#define TIMER32_CONTROL2_PRESCALE_0                        (0x00000000)          /* 0 stages of prescale, clock is divided by 1 */
+#define TIMER32_CONTROL2_PRESCALE_1                        (0x00000004)          /* 4 stages of prescale, clock is divided by 16 */
+#define TIMER32_CONTROL2_PRESCALE_2                        (0x00000008)          /* 8 stages of prescale, clock is divided by 256 */
+/* TIMER32_CONTROL2[TIMER32_CONTROL2_IE] Bits */
+#define TIMER32_CONTROL2_IE_OFS                            ( 5)                  /* IE Offset */
+#define TIMER32_CONTROL2_IE                                (0x00000020)          /* Interrupt enable bit */
+/* TIMER32_CONTROL2[TIMER32_CONTROL2_MODE] Bits */
+#define TIMER32_CONTROL2_MODE_OFS                          ( 6)                  /* MODE Offset */
+#define TIMER32_CONTROL2_MODE                              (0x00000040)          /* Mode bit */
+/* TIMER32_CONTROL2[TIMER32_CONTROL2_ENABLE] Bits */
+#define TIMER32_CONTROL2_ENABLE_OFS                        ( 7)                  /* ENABLE Offset */
+#define TIMER32_CONTROL2_ENABLE                            (0x00000080)          /*  */
+/* TIMER32_RIS2[TIMER32_RIS2_RAW_IFG] Bits */
+#define TIMER32_RIS2_RAW_IFG_OFS                           ( 0)                  /* RAW_IFG Offset */
+#define TIMER32_RIS2_RAW_IFG                               (0x00000001)          /* Raw interrupt status */
+/* TIMER32_MIS2[TIMER32_MIS2_IFG] Bits */
+#define TIMER32_MIS2_IFG_OFS                               ( 0)                  /* IFG Offset */
+#define TIMER32_MIS2_IFG                                   (0x00000001)          /* Enabled interrupt status */
+
+
+//*****************************************************************************
+// TIMER_A0 Bits
+//*****************************************************************************
+/* TA0CTL[TAIFG] Bits */
+#define TAIFG_OFS                                          ( 0)                  /* TAIFG Offset */
+#define TAIFG                                              (0x0001)              /* TimerA interrupt flag */
+/* TA0CTL[TAIE] Bits */
+#define TAIE_OFS                                           ( 1)                  /* TAIE Offset */
+#define TAIE                                               (0x0002)              /* TimerA interrupt enable */
+/* TA0CTL[TACLR] Bits */
+#define TACLR_OFS                                          ( 2)                  /* TACLR Offset */
+#define TACLR                                              (0x0004)              /* TimerA clear */
+/* TA0CTL[MC] Bits */
+#define MC_OFS                                             ( 4)                  /* MC Offset */
+#define MC_M                                               (0x0030)              /* Mode control */
+#define MC0                                                (0x0010)              /* Mode control */
+#define MC1                                                (0x0020)              /* Mode control */
+#define MC_0                                               (0x0000)              /* Stop mode: Timer is halted */
+#define MC_1                                               (0x0010)              /* Up mode: Timer counts up to TAxCCR0 */
+#define MC_2                                               (0x0020)              /* Continuous mode: Timer counts up to 0FFFFh */
+#define MC_3                                               (0x0030)              /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
+#define MC__STOP                                           (0x0000)              /* Stop mode: Timer is halted */
+#define MC__UP                                             (0x0010)              /* Up mode: Timer counts up to TAxCCR0 */
+#define MC__CONTINUOUS                                     (0x0020)              /* Continuous mode: Timer counts up to 0FFFFh */
+#define MC__UPDOWN                                         (0x0030)              /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
+/* TA0CTL[ID] Bits */
+#define ID_OFS                                             ( 6)                  /* ID Offset */
+#define ID_M                                               (0x00c0)              /* Input divider */
+#define ID0                                                (0x0040)              /* Input divider */
+#define ID1                                                (0x0080)              /* Input divider */
+#define ID_0                                               (0x0000)              /* /1 */
+#define ID_1                                               (0x0040)              /* /2 */
+#define ID_2                                               (0x0080)              /* /4 */
+#define ID_3                                               (0x00c0)              /* /8 */
+#define ID__1                                              (0x0000)              /* /1 */
+#define ID__2                                              (0x0040)              /* /2 */
+#define ID__4                                              (0x0080)              /* /4 */
+#define ID__8                                              (0x00c0)              /* /8 */
+/* TA0CTL[TASSEL] Bits */
+#define TASSEL_OFS                                         ( 8)                  /* TASSEL Offset */
+#define TASSEL_M                                           (0x0300)              /* TimerA clock source select */
+#define TASSEL0                                            (0x0100)              /* TimerA clock source select */
+#define TASSEL1                                            (0x0200)              /* TimerA clock source select */
+#define TASSEL_0                                           (0x0000)              /* TAxCLK */
+#define TASSEL_1                                           (0x0100)              /* ACLK */
+#define TASSEL_2                                           (0x0200)              /* SMCLK */
+#define TASSEL_3                                           (0x0300)              /* INCLK */
+#define TASSEL__TACLK                                      (0x0000)              /* TAxCLK */
+#define TASSEL__ACLK                                       (0x0100)              /* ACLK */
+#define TASSEL__SMCLK                                      (0x0200)              /* SMCLK */
+#define TASSEL__INCLK                                      (0x0300)              /* INCLK */
+/* TA0CCTL[CCIFG] Bits */
+#define CCIFG_OFS                                          ( 0)                  /* CCIFG Offset */
+#define CCIFG                                              (0x0001)              /* Capture/compare interrupt flag */
+/* TA0CCTL[COV] Bits */
+#define COV_OFS                                            ( 1)                  /* COV Offset */
+#define COV                                                (0x0002)              /* Capture overflow */
+/* TA0CCTL[OUT] Bits */
+#define OUT_OFS                                            ( 2)                  /* OUT Offset */
+#define OUT                                                (0x0004)              /* Output */
+/* TA0CCTL[CCI] Bits */
+#define CCI_OFS                                            ( 3)                  /* CCI Offset */
+#define CCI                                                (0x0008)              /* Capture/compare input */
+/* TA0CCTL[CCIE] Bits */
+#define CCIE_OFS                                           ( 4)                  /* CCIE Offset */
+#define CCIE                                               (0x0010)              /* Capture/compare interrupt enable */
+/* TA0CCTL[OUTMOD] Bits */
+#define OUTMOD_OFS                                         ( 5)                  /* OUTMOD Offset */
+#define OUTMOD_M                                           (0x00e0)              /* Output mode */
+#define OUTMOD0                                            (0x0020)              /* Output mode */
+#define OUTMOD1                                            (0x0040)              /* Output mode */
+#define OUTMOD2                                            (0x0080)              /* Output mode */
+#define OUTMOD_0                                           (0x0000)              /* OUT bit value */
+#define OUTMOD_1                                           (0x0020)              /* Set */
+#define OUTMOD_2                                           (0x0040)              /* Toggle/reset */
+#define OUTMOD_3                                           (0x0060)              /* Set/reset */
+#define OUTMOD_4                                           (0x0080)              /* Toggle */
+#define OUTMOD_5                                           (0x00a0)              /* Reset */
+#define OUTMOD_6                                           (0x00c0)              /* Toggle/set */
+#define OUTMOD_7                                           (0x00e0)              /* Reset/set */
+/* TA0CCTL[CAP] Bits */
+#define CAP_OFS                                            ( 8)                  /* CAP Offset */
+#define CAP                                                (0x0100)              /* Capture mode */
+/* TA0CCTL[SCCI] Bits */
+#define SCCI_OFS                                           (10)                  /* SCCI Offset */
+#define SCCI                                               (0x0400)              /* Synchronized capture/compare input */
+/* TA0CCTL[SCS] Bits */
+#define SCS_OFS                                            (11)                  /* SCS Offset */
+#define SCS                                                (0x0800)              /* Synchronize capture source */
+/* TA0CCTL[CCIS] Bits */
+#define CCIS_OFS                                           (12)                  /* CCIS Offset */
+#define CCIS_M                                             (0x3000)              /* Capture/compare input select */
+#define CCIS0                                              (0x1000)              /* Capture/compare input select */
+#define CCIS1                                              (0x2000)              /* Capture/compare input select */
+#define CCIS_0                                             (0x0000)              /* CCIxA */
+#define CCIS_1                                             (0x1000)              /* CCIxB */
+#define CCIS_2                                             (0x2000)              /* GND */
+#define CCIS_3                                             (0x3000)              /* VCC */
+#define CCIS__CCIA                                         (0x0000)              /* CCIxA */
+#define CCIS__CCIB                                         (0x1000)              /* CCIxB */
+#define CCIS__GND                                          (0x2000)              /* GND */
+#define CCIS__VCC                                          (0x3000)              /* VCC */
+/* TA0CCTL[CM] Bits */
+#define CM_OFS                                             (14)                  /* CM Offset */
+#define CM_M                                               (0xc000)              /* Capture mode */
+#define CM0                                                (0x4000)              /* Capture mode */
+#define CM1                                                (0x8000)              /* Capture mode */
+#define CM_0                                               (0x0000)              /* No capture */
+#define CM_1                                               (0x4000)              /* Capture on rising edge */
+#define CM_2                                               (0x8000)              /* Capture on falling edge */
+#define CM_3                                               (0xc000)              /* Capture on both rising and falling edges */
+#define CM__NONE                                           (0x0000)              /* No capture */
+#define CM__RISING                                         (0x4000)              /* Capture on rising edge */
+#define CM__FALLING                                        (0x8000)              /* Capture on falling edge */
+#define CM__BOTH                                           (0xc000)              /* Capture on both rising and falling edges */
+/* TA0EX0[TAIDEX] Bits */
+#define TAIDEX_OFS                                         ( 0)                  /* TAIDEX Offset */
+#define TAIDEX_M                                           (0x0007)              /* Input divider expansion */
+#define TAIDEX0                                            (0x0001)              /* Input divider expansion */
+#define TAIDEX1                                            (0x0002)              /* Input divider expansion */
+#define TAIDEX2                                            (0x0004)              /* Input divider expansion */
+#define TAIDEX_0                                           (0x0000)              /* Divide by 1 */
+#define TAIDEX_1                                           (0x0001)              /* Divide by 2 */
+#define TAIDEX_2                                           (0x0002)              /* Divide by 3 */
+#define TAIDEX_3                                           (0x0003)              /* Divide by 4 */
+#define TAIDEX_4                                           (0x0004)              /* Divide by 5 */
+#define TAIDEX_5                                           (0x0005)              /* Divide by 6 */
+#define TAIDEX_6                                           (0x0006)              /* Divide by 7 */
+#define TAIDEX_7                                           (0x0007)              /* Divide by 8 */
+#define TAIDEX__1                                          (0x0000)              /* Divide by 1 */
+#define TAIDEX__2                                          (0x0001)              /* Divide by 2 */
+#define TAIDEX__3                                          (0x0002)              /* Divide by 3 */
+#define TAIDEX__4                                          (0x0003)              /* Divide by 4 */
+#define TAIDEX__5                                          (0x0004)              /* Divide by 5 */
+#define TAIDEX__6                                          (0x0005)              /* Divide by 6 */
+#define TAIDEX__7                                          (0x0006)              /* Divide by 7 */
+#define TAIDEX__8                                          (0x0007)              /* Divide by 8 */
+
+
+//*****************************************************************************
+// TIMER_A1 Bits
+//*****************************************************************************
+/* TA1CTL[TAIFG] Bits */
+//#define TAIFG_OFS                                          ( 0)                  /* TAIFG Offset */
+//#define TAIFG                                              (0x0001)              /* TimerA interrupt flag */
+/* TA1CTL[TAIE] Bits */
+//#define TAIE_OFS                                           ( 1)                  /* TAIE Offset */
+//#define TAIE                                               (0x0002)              /* TimerA interrupt enable */
+/* TA1CTL[TACLR] Bits */
+//#define TACLR_OFS                                          ( 2)                  /* TACLR Offset */
+//#define TACLR                                              (0x0004)              /* TimerA clear */
+/* TA1CTL[MC] Bits */
+//#define MC_OFS                                             ( 4)                  /* MC Offset */
+//#define MC_M                                               (0x0030)              /* Mode control */
+//#define MC0                                                (0x0010)              /* Mode control */
+//#define MC1                                                (0x0020)              /* Mode control */
+//#define MC_0                                               (0x0000)              /* Stop mode: Timer is halted */
+//#define MC_1                                               (0x0010)              /* Up mode: Timer counts up to TAxCCR0 */
+//#define MC_2                                               (0x0020)              /* Continuous mode: Timer counts up to 0FFFFh */
+//#define MC_3                                               (0x0030)              /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
+//#define MC__STOP                                           (0x0000)              /* Stop mode: Timer is halted */
+//#define MC__UP                                             (0x0010)              /* Up mode: Timer counts up to TAxCCR0 */
+//#define MC__CONTINUOUS                                     (0x0020)              /* Continuous mode: Timer counts up to 0FFFFh */
+//#define MC__UPDOWN                                         (0x0030)              /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
+/* TA1CTL[ID] Bits */
+//#define ID_OFS                                             ( 6)                  /* ID Offset */
+//#define ID_M                                               (0x00c0)              /* Input divider */
+//#define ID0                                                (0x0040)              /* Input divider */
+//#define ID1                                                (0x0080)              /* Input divider */
+//#define ID_0                                               (0x0000)              /* /1 */
+//#define ID_1                                               (0x0040)              /* /2 */
+//#define ID_2                                               (0x0080)              /* /4 */
+//#define ID_3                                               (0x00c0)              /* /8 */
+//#define ID__1                                              (0x0000)              /* /1 */
+//#define ID__2                                              (0x0040)              /* /2 */
+//#define ID__4                                              (0x0080)              /* /4 */
+//#define ID__8                                              (0x00c0)              /* /8 */
+/* TA1CTL[TASSEL] Bits */
+//#define TASSEL_OFS                                         ( 8)                  /* TASSEL Offset */
+//#define TASSEL_M                                           (0x0300)              /* TimerA clock source select */
+//#define TASSEL0                                            (0x0100)              /* TimerA clock source select */
+//#define TASSEL1                                            (0x0200)              /* TimerA clock source select */
+//#define TASSEL_0                                           (0x0000)              /* TAxCLK */
+//#define TASSEL_1                                           (0x0100)              /* ACLK */
+//#define TASSEL_2                                           (0x0200)              /* SMCLK */
+//#define TASSEL_3                                           (0x0300)              /* INCLK */
+//#define TASSEL__TACLK                                      (0x0000)              /* TAxCLK */
+//#define TASSEL__ACLK                                       (0x0100)              /* ACLK */
+//#define TASSEL__SMCLK                                      (0x0200)              /* SMCLK */
+//#define TASSEL__INCLK                                      (0x0300)              /* INCLK */
+/* TA1CCTL[CCIFG] Bits */
+//#define CCIFG_OFS                                          ( 0)                  /* CCIFG Offset */
+//#define CCIFG                                              (0x0001)              /* Capture/compare interrupt flag */
+/* TA1CCTL[COV] Bits */
+//#define COV_OFS                                            ( 1)                  /* COV Offset */
+//#define COV                                                (0x0002)              /* Capture overflow */
+/* TA1CCTL[OUT] Bits */
+//#define OUT_OFS                                            ( 2)                  /* OUT Offset */
+//#define OUT                                                (0x0004)              /* Output */
+/* TA1CCTL[CCI] Bits */
+//#define CCI_OFS                                            ( 3)                  /* CCI Offset */
+//#define CCI                                                (0x0008)              /* Capture/compare input */
+/* TA1CCTL[CCIE] Bits */
+//#define CCIE_OFS                                           ( 4)                  /* CCIE Offset */
+//#define CCIE                                               (0x0010)              /* Capture/compare interrupt enable */
+/* TA1CCTL[OUTMOD] Bits */
+//#define OUTMOD_OFS                                         ( 5)                  /* OUTMOD Offset */
+//#define OUTMOD_M                                           (0x00e0)              /* Output mode */
+//#define OUTMOD0                                            (0x0020)              /* Output mode */
+//#define OUTMOD1                                            (0x0040)              /* Output mode */
+//#define OUTMOD2                                            (0x0080)              /* Output mode */
+//#define OUTMOD_0                                           (0x0000)              /* OUT bit value */
+//#define OUTMOD_1                                           (0x0020)              /* Set */
+//#define OUTMOD_2                                           (0x0040)              /* Toggle/reset */
+//#define OUTMOD_3                                           (0x0060)              /* Set/reset */
+//#define OUTMOD_4                                           (0x0080)              /* Toggle */
+//#define OUTMOD_5                                           (0x00a0)              /* Reset */
+//#define OUTMOD_6                                           (0x00c0)              /* Toggle/set */
+//#define OUTMOD_7                                           (0x00e0)              /* Reset/set */
+/* TA1CCTL[CAP] Bits */
+//#define CAP_OFS                                            ( 8)                  /* CAP Offset */
+//#define CAP                                                (0x0100)              /* Capture mode */
+/* TA1CCTL[SCCI] Bits */
+//#define SCCI_OFS                                           (10)                  /* SCCI Offset */
+//#define SCCI                                               (0x0400)              /* Synchronized capture/compare input */
+/* TA1CCTL[SCS] Bits */
+//#define SCS_OFS                                            (11)                  /* SCS Offset */
+//#define SCS                                                (0x0800)              /* Synchronize capture source */
+/* TA1CCTL[CCIS] Bits */
+//#define CCIS_OFS                                           (12)                  /* CCIS Offset */
+//#define CCIS_M                                             (0x3000)              /* Capture/compare input select */
+//#define CCIS0                                              (0x1000)              /* Capture/compare input select */
+//#define CCIS1                                              (0x2000)              /* Capture/compare input select */
+//#define CCIS_0                                             (0x0000)              /* CCIxA */
+//#define CCIS_1                                             (0x1000)              /* CCIxB */
+//#define CCIS_2                                             (0x2000)              /* GND */
+//#define CCIS_3                                             (0x3000)              /* VCC */
+//#define CCIS__CCIA                                         (0x0000)              /* CCIxA */
+//#define CCIS__CCIB                                         (0x1000)              /* CCIxB */
+//#define CCIS__GND                                          (0x2000)              /* GND */
+//#define CCIS__VCC                                          (0x3000)              /* VCC */
+/* TA1CCTL[CM] Bits */
+//#define CM_OFS                                             (14)                  /* CM Offset */
+//#define CM_M                                               (0xc000)              /* Capture mode */
+//#define CM0                                                (0x4000)              /* Capture mode */
+//#define CM1                                                (0x8000)              /* Capture mode */
+//#define CM_0                                               (0x0000)              /* No capture */
+//#define CM_1                                               (0x4000)              /* Capture on rising edge */
+//#define CM_2                                               (0x8000)              /* Capture on falling edge */
+//#define CM_3                                               (0xc000)              /* Capture on both rising and falling edges */
+//#define CM__NONE                                           (0x0000)              /* No capture */
+//#define CM__RISING                                         (0x4000)              /* Capture on rising edge */
+//#define CM__FALLING                                        (0x8000)              /* Capture on falling edge */
+//#define CM__BOTH                                           (0xc000)              /* Capture on both rising and falling edges */
+/* TA1EX0[TAIDEX] Bits */
+//#define TAIDEX_OFS                                         ( 0)                  /* TAIDEX Offset */
+//#define TAIDEX_M                                           (0x0007)              /* Input divider expansion */
+//#define TAIDEX0                                            (0x0001)              /* Input divider expansion */
+//#define TAIDEX1                                            (0x0002)              /* Input divider expansion */
+//#define TAIDEX2                                            (0x0004)              /* Input divider expansion */
+//#define TAIDEX_0                                           (0x0000)              /* Divide by 1 */
+//#define TAIDEX_1                                           (0x0001)              /* Divide by 2 */
+//#define TAIDEX_2                                           (0x0002)              /* Divide by 3 */
+//#define TAIDEX_3                                           (0x0003)              /* Divide by 4 */
+//#define TAIDEX_4                                           (0x0004)              /* Divide by 5 */
+//#define TAIDEX_5                                           (0x0005)              /* Divide by 6 */
+//#define TAIDEX_6                                           (0x0006)              /* Divide by 7 */
+//#define TAIDEX_7                                           (0x0007)              /* Divide by 8 */
+//#define TAIDEX__1                                          (0x0000)              /* Divide by 1 */
+//#define TAIDEX__2                                          (0x0001)              /* Divide by 2 */
+//#define TAIDEX__3                                          (0x0002)              /* Divide by 3 */
+//#define TAIDEX__4                                          (0x0003)              /* Divide by 4 */
+//#define TAIDEX__5                                          (0x0004)              /* Divide by 5 */
+//#define TAIDEX__6                                          (0x0005)              /* Divide by 6 */
+//#define TAIDEX__7                                          (0x0006)              /* Divide by 7 */
+//#define TAIDEX__8                                          (0x0007)              /* Divide by 8 */
+
+
+//*****************************************************************************
+// TIMER_A2 Bits
+//*****************************************************************************
+/* TA2CTL[TAIFG] Bits */
+//#define TAIFG_OFS                                          ( 0)                  /* TAIFG Offset */
+//#define TAIFG                                              (0x0001)              /* TimerA interrupt flag */
+/* TA2CTL[TAIE] Bits */
+//#define TAIE_OFS                                           ( 1)                  /* TAIE Offset */
+//#define TAIE                                               (0x0002)              /* TimerA interrupt enable */
+/* TA2CTL[TACLR] Bits */
+//#define TACLR_OFS                                          ( 2)                  /* TACLR Offset */
+//#define TACLR                                              (0x0004)              /* TimerA clear */
+/* TA2CTL[MC] Bits */
+//#define MC_OFS                                             ( 4)                  /* MC Offset */
+//#define MC_M                                               (0x0030)              /* Mode control */
+//#define MC0                                                (0x0010)              /* Mode control */
+//#define MC1                                                (0x0020)              /* Mode control */
+//#define MC_0                                               (0x0000)              /* Stop mode: Timer is halted */
+//#define MC_1                                               (0x0010)              /* Up mode: Timer counts up to TAxCCR0 */
+//#define MC_2                                               (0x0020)              /* Continuous mode: Timer counts up to 0FFFFh */
+//#define MC_3                                               (0x0030)              /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
+//#define MC__STOP                                           (0x0000)              /* Stop mode: Timer is halted */
+//#define MC__UP                                             (0x0010)              /* Up mode: Timer counts up to TAxCCR0 */
+//#define MC__CONTINUOUS                                     (0x0020)              /* Continuous mode: Timer counts up to 0FFFFh */
+//#define MC__UPDOWN                                         (0x0030)              /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
+/* TA2CTL[ID] Bits */
+//#define ID_OFS                                             ( 6)                  /* ID Offset */
+//#define ID_M                                               (0x00c0)              /* Input divider */
+//#define ID0                                                (0x0040)              /* Input divider */
+//#define ID1                                                (0x0080)              /* Input divider */
+//#define ID_0                                               (0x0000)              /* /1 */
+//#define ID_1                                               (0x0040)              /* /2 */
+//#define ID_2                                               (0x0080)              /* /4 */
+//#define ID_3                                               (0x00c0)              /* /8 */
+//#define ID__1                                              (0x0000)              /* /1 */
+//#define ID__2                                              (0x0040)              /* /2 */
+//#define ID__4                                              (0x0080)              /* /4 */
+//#define ID__8                                              (0x00c0)              /* /8 */
+/* TA2CTL[TASSEL] Bits */
+//#define TASSEL_OFS                                         ( 8)                  /* TASSEL Offset */
+//#define TASSEL_M                                           (0x0300)              /* TimerA clock source select */
+//#define TASSEL0                                            (0x0100)              /* TimerA clock source select */
+//#define TASSEL1                                            (0x0200)              /* TimerA clock source select */
+//#define TASSEL_0                                           (0x0000)              /* TAxCLK */
+//#define TASSEL_1                                           (0x0100)              /* ACLK */
+//#define TASSEL_2                                           (0x0200)              /* SMCLK */
+//#define TASSEL_3                                           (0x0300)              /* INCLK */
+//#define TASSEL__TACLK                                      (0x0000)              /* TAxCLK */
+//#define TASSEL__ACLK                                       (0x0100)              /* ACLK */
+//#define TASSEL__SMCLK                                      (0x0200)              /* SMCLK */
+//#define TASSEL__INCLK                                      (0x0300)              /* INCLK */
+/* TA2CCTL[CCIFG] Bits */
+//#define CCIFG_OFS                                          ( 0)                  /* CCIFG Offset */
+//#define CCIFG                                              (0x0001)              /* Capture/compare interrupt flag */
+/* TA2CCTL[COV] Bits */
+//#define COV_OFS                                            ( 1)                  /* COV Offset */
+//#define COV                                                (0x0002)              /* Capture overflow */
+/* TA2CCTL[OUT] Bits */
+//#define OUT_OFS                                            ( 2)                  /* OUT Offset */
+//#define OUT                                                (0x0004)              /* Output */
+/* TA2CCTL[CCI] Bits */
+//#define CCI_OFS                                            ( 3)                  /* CCI Offset */
+//#define CCI                                                (0x0008)              /* Capture/compare input */
+/* TA2CCTL[CCIE] Bits */
+//#define CCIE_OFS                                           ( 4)                  /* CCIE Offset */
+//#define CCIE                                               (0x0010)              /* Capture/compare interrupt enable */
+/* TA2CCTL[OUTMOD] Bits */
+//#define OUTMOD_OFS                                         ( 5)                  /* OUTMOD Offset */
+//#define OUTMOD_M                                           (0x00e0)              /* Output mode */
+//#define OUTMOD0                                            (0x0020)              /* Output mode */
+//#define OUTMOD1                                            (0x0040)              /* Output mode */
+//#define OUTMOD2                                            (0x0080)              /* Output mode */
+//#define OUTMOD_0                                           (0x0000)              /* OUT bit value */
+//#define OUTMOD_1                                           (0x0020)              /* Set */
+//#define OUTMOD_2                                           (0x0040)              /* Toggle/reset */
+//#define OUTMOD_3                                           (0x0060)              /* Set/reset */
+//#define OUTMOD_4                                           (0x0080)              /* Toggle */
+//#define OUTMOD_5                                           (0x00a0)              /* Reset */
+//#define OUTMOD_6                                           (0x00c0)              /* Toggle/set */
+//#define OUTMOD_7                                           (0x00e0)              /* Reset/set */
+/* TA2CCTL[CAP] Bits */
+//#define CAP_OFS                                            ( 8)                  /* CAP Offset */
+//#define CAP                                                (0x0100)              /* Capture mode */
+/* TA2CCTL[SCCI] Bits */
+//#define SCCI_OFS                                           (10)                  /* SCCI Offset */
+//#define SCCI                                               (0x0400)              /* Synchronized capture/compare input */
+/* TA2CCTL[SCS] Bits */
+//#define SCS_OFS                                            (11)                  /* SCS Offset */
+//#define SCS                                                (0x0800)              /* Synchronize capture source */
+/* TA2CCTL[CCIS] Bits */
+//#define CCIS_OFS                                           (12)                  /* CCIS Offset */
+//#define CCIS_M                                             (0x3000)              /* Capture/compare input select */
+//#define CCIS0                                              (0x1000)              /* Capture/compare input select */
+//#define CCIS1                                              (0x2000)              /* Capture/compare input select */
+//#define CCIS_0                                             (0x0000)              /* CCIxA */
+//#define CCIS_1                                             (0x1000)              /* CCIxB */
+//#define CCIS_2                                             (0x2000)              /* GND */
+//#define CCIS_3                                             (0x3000)              /* VCC */
+//#define CCIS__CCIA                                         (0x0000)              /* CCIxA */
+//#define CCIS__CCIB                                         (0x1000)              /* CCIxB */
+//#define CCIS__GND                                          (0x2000)              /* GND */
+//#define CCIS__VCC                                          (0x3000)              /* VCC */
+/* TA2CCTL[CM] Bits */
+//#define CM_OFS                                             (14)                  /* CM Offset */
+//#define CM_M                                               (0xc000)              /* Capture mode */
+//#define CM0                                                (0x4000)              /* Capture mode */
+//#define CM1                                                (0x8000)              /* Capture mode */
+//#define CM_0                                               (0x0000)              /* No capture */
+//#define CM_1                                               (0x4000)              /* Capture on rising edge */
+//#define CM_2                                               (0x8000)              /* Capture on falling edge */
+//#define CM_3                                               (0xc000)              /* Capture on both rising and falling edges */
+//#define CM__NONE                                           (0x0000)              /* No capture */
+//#define CM__RISING                                         (0x4000)              /* Capture on rising edge */
+//#define CM__FALLING                                        (0x8000)              /* Capture on falling edge */
+//#define CM__BOTH                                           (0xc000)              /* Capture on both rising and falling edges */
+/* TA2EX0[TAIDEX] Bits */
+//#define TAIDEX_OFS                                         ( 0)                  /* TAIDEX Offset */
+//#define TAIDEX_M                                           (0x0007)              /* Input divider expansion */
+//#define TAIDEX0                                            (0x0001)              /* Input divider expansion */
+//#define TAIDEX1                                            (0x0002)              /* Input divider expansion */
+//#define TAIDEX2                                            (0x0004)              /* Input divider expansion */
+//#define TAIDEX_0                                           (0x0000)              /* Divide by 1 */
+//#define TAIDEX_1                                           (0x0001)              /* Divide by 2 */
+//#define TAIDEX_2                                           (0x0002)              /* Divide by 3 */
+//#define TAIDEX_3                                           (0x0003)              /* Divide by 4 */
+//#define TAIDEX_4                                           (0x0004)              /* Divide by 5 */
+//#define TAIDEX_5                                           (0x0005)              /* Divide by 6 */
+//#define TAIDEX_6                                           (0x0006)              /* Divide by 7 */
+//#define TAIDEX_7                                           (0x0007)              /* Divide by 8 */
+//#define TAIDEX__1                                          (0x0000)              /* Divide by 1 */
+//#define TAIDEX__2                                          (0x0001)              /* Divide by 2 */
+//#define TAIDEX__3                                          (0x0002)              /* Divide by 3 */
+//#define TAIDEX__4                                          (0x0003)              /* Divide by 4 */
+//#define TAIDEX__5                                          (0x0004)              /* Divide by 5 */
+//#define TAIDEX__6                                          (0x0005)              /* Divide by 6 */
+//#define TAIDEX__7                                          (0x0006)              /* Divide by 7 */
+//#define TAIDEX__8                                          (0x0007)              /* Divide by 8 */
+
+
+//*****************************************************************************
+// TIMER_A3 Bits
+//*****************************************************************************
+/* TA3CTL[TAIFG] Bits */
+//#define TAIFG_OFS                                          ( 0)                  /* TAIFG Offset */
+//#define TAIFG                                              (0x0001)              /* TimerA interrupt flag */
+/* TA3CTL[TAIE] Bits */
+//#define TAIE_OFS                                           ( 1)                  /* TAIE Offset */
+//#define TAIE                                               (0x0002)              /* TimerA interrupt enable */
+/* TA3CTL[TACLR] Bits */
+//#define TACLR_OFS                                          ( 2)                  /* TACLR Offset */
+//#define TACLR                                              (0x0004)              /* TimerA clear */
+/* TA3CTL[MC] Bits */
+//#define MC_OFS                                             ( 4)                  /* MC Offset */
+//#define MC_M                                               (0x0030)              /* Mode control */
+//#define MC0                                                (0x0010)              /* Mode control */
+//#define MC1                                                (0x0020)              /* Mode control */
+//#define MC_0                                               (0x0000)              /* Stop mode: Timer is halted */
+//#define MC_1                                               (0x0010)              /* Up mode: Timer counts up to TAxCCR0 */
+//#define MC_2                                               (0x0020)              /* Continuous mode: Timer counts up to 0FFFFh */
+//#define MC_3                                               (0x0030)              /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
+//#define MC__STOP                                           (0x0000)              /* Stop mode: Timer is halted */
+//#define MC__UP                                             (0x0010)              /* Up mode: Timer counts up to TAxCCR0 */
+//#define MC__CONTINUOUS                                     (0x0020)              /* Continuous mode: Timer counts up to 0FFFFh */
+//#define MC__UPDOWN                                         (0x0030)              /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
+/* TA3CTL[ID] Bits */
+//#define ID_OFS                                             ( 6)                  /* ID Offset */
+//#define ID_M                                               (0x00c0)              /* Input divider */
+//#define ID0                                                (0x0040)              /* Input divider */
+//#define ID1                                                (0x0080)              /* Input divider */
+//#define ID_0                                               (0x0000)              /* /1 */
+//#define ID_1                                               (0x0040)              /* /2 */
+//#define ID_2                                               (0x0080)              /* /4 */
+//#define ID_3                                               (0x00c0)              /* /8 */
+//#define ID__1                                              (0x0000)              /* /1 */
+//#define ID__2                                              (0x0040)              /* /2 */
+//#define ID__4                                              (0x0080)              /* /4 */
+//#define ID__8                                              (0x00c0)              /* /8 */
+/* TA3CTL[TASSEL] Bits */
+//#define TASSEL_OFS                                         ( 8)                  /* TASSEL Offset */
+//#define TASSEL_M                                           (0x0300)              /* TimerA clock source select */
+//#define TASSEL0                                            (0x0100)              /* TimerA clock source select */
+//#define TASSEL1                                            (0x0200)              /* TimerA clock source select */
+//#define TASSEL_0                                           (0x0000)              /* TAxCLK */
+//#define TASSEL_1                                           (0x0100)              /* ACLK */
+//#define TASSEL_2                                           (0x0200)              /* SMCLK */
+//#define TASSEL_3                                           (0x0300)              /* INCLK */
+//#define TASSEL__TACLK                                      (0x0000)              /* TAxCLK */
+//#define TASSEL__ACLK                                       (0x0100)              /* ACLK */
+//#define TASSEL__SMCLK                                      (0x0200)              /* SMCLK */
+//#define TASSEL__INCLK                                      (0x0300)              /* INCLK */
+/* TA3CCTL[CCIFG] Bits */
+//#define CCIFG_OFS                                          ( 0)                  /* CCIFG Offset */
+//#define CCIFG                                              (0x0001)              /* Capture/compare interrupt flag */
+/* TA3CCTL[COV] Bits */
+//#define COV_OFS                                            ( 1)                  /* COV Offset */
+//#define COV                                                (0x0002)              /* Capture overflow */
+/* TA3CCTL[OUT] Bits */
+//#define OUT_OFS                                            ( 2)                  /* OUT Offset */
+//#define OUT                                                (0x0004)              /* Output */
+/* TA3CCTL[CCI] Bits */
+//#define CCI_OFS                                            ( 3)                  /* CCI Offset */
+//#define CCI                                                (0x0008)              /* Capture/compare input */
+/* TA3CCTL[CCIE] Bits */
+//#define CCIE_OFS                                           ( 4)                  /* CCIE Offset */
+//#define CCIE                                               (0x0010)              /* Capture/compare interrupt enable */
+/* TA3CCTL[OUTMOD] Bits */
+//#define OUTMOD_OFS                                         ( 5)                  /* OUTMOD Offset */
+//#define OUTMOD_M                                           (0x00e0)              /* Output mode */
+//#define OUTMOD0                                            (0x0020)              /* Output mode */
+//#define OUTMOD1                                            (0x0040)              /* Output mode */
+//#define OUTMOD2                                            (0x0080)              /* Output mode */
+//#define OUTMOD_0                                           (0x0000)              /* OUT bit value */
+//#define OUTMOD_1                                           (0x0020)              /* Set */
+//#define OUTMOD_2                                           (0x0040)              /* Toggle/reset */
+//#define OUTMOD_3                                           (0x0060)              /* Set/reset */
+//#define OUTMOD_4                                           (0x0080)              /* Toggle */
+//#define OUTMOD_5                                           (0x00a0)              /* Reset */
+//#define OUTMOD_6                                           (0x00c0)              /* Toggle/set */
+//#define OUTMOD_7                                           (0x00e0)              /* Reset/set */
+/* TA3CCTL[CAP] Bits */
+//#define CAP_OFS                                            ( 8)                  /* CAP Offset */
+//#define CAP                                                (0x0100)              /* Capture mode */
+/* TA3CCTL[SCCI] Bits */
+//#define SCCI_OFS                                           (10)                  /* SCCI Offset */
+//#define SCCI                                               (0x0400)              /* Synchronized capture/compare input */
+/* TA3CCTL[SCS] Bits */
+//#define SCS_OFS                                            (11)                  /* SCS Offset */
+//#define SCS                                                (0x0800)              /* Synchronize capture source */
+/* TA3CCTL[CCIS] Bits */
+//#define CCIS_OFS                                           (12)                  /* CCIS Offset */
+//#define CCIS_M                                             (0x3000)              /* Capture/compare input select */
+//#define CCIS0                                              (0x1000)              /* Capture/compare input select */
+//#define CCIS1                                              (0x2000)              /* Capture/compare input select */
+//#define CCIS_0                                             (0x0000)              /* CCIxA */
+//#define CCIS_1                                             (0x1000)              /* CCIxB */
+//#define CCIS_2                                             (0x2000)              /* GND */
+//#define CCIS_3                                             (0x3000)              /* VCC */
+//#define CCIS__CCIA                                         (0x0000)              /* CCIxA */
+//#define CCIS__CCIB                                         (0x1000)              /* CCIxB */
+//#define CCIS__GND                                          (0x2000)              /* GND */
+//#define CCIS__VCC                                          (0x3000)              /* VCC */
+/* TA3CCTL[CM] Bits */
+//#define CM_OFS                                             (14)                  /* CM Offset */
+//#define CM_M                                               (0xc000)              /* Capture mode */
+//#define CM0                                                (0x4000)              /* Capture mode */
+//#define CM1                                                (0x8000)              /* Capture mode */
+//#define CM_0                                               (0x0000)              /* No capture */
+//#define CM_1                                               (0x4000)              /* Capture on rising edge */
+//#define CM_2                                               (0x8000)              /* Capture on falling edge */
+//#define CM_3                                               (0xc000)              /* Capture on both rising and falling edges */
+//#define CM__NONE                                           (0x0000)              /* No capture */
+//#define CM__RISING                                         (0x4000)              /* Capture on rising edge */
+//#define CM__FALLING                                        (0x8000)              /* Capture on falling edge */
+//#define CM__BOTH                                           (0xc000)              /* Capture on both rising and falling edges */
+/* TA3EX0[TAIDEX] Bits */
+//#define TAIDEX_OFS                                         ( 0)                  /* TAIDEX Offset */
+//#define TAIDEX_M                                           (0x0007)              /* Input divider expansion */
+//#define TAIDEX0                                            (0x0001)              /* Input divider expansion */
+//#define TAIDEX1                                            (0x0002)              /* Input divider expansion */
+//#define TAIDEX2                                            (0x0004)              /* Input divider expansion */
+//#define TAIDEX_0                                           (0x0000)              /* Divide by 1 */
+//#define TAIDEX_1                                           (0x0001)              /* Divide by 2 */
+//#define TAIDEX_2                                           (0x0002)              /* Divide by 3 */
+//#define TAIDEX_3                                           (0x0003)              /* Divide by 4 */
+//#define TAIDEX_4                                           (0x0004)              /* Divide by 5 */
+//#define TAIDEX_5                                           (0x0005)              /* Divide by 6 */
+//#define TAIDEX_6                                           (0x0006)              /* Divide by 7 */
+//#define TAIDEX_7                                           (0x0007)              /* Divide by 8 */
+//#define TAIDEX__1                                          (0x0000)              /* Divide by 1 */
+//#define TAIDEX__2                                          (0x0001)              /* Divide by 2 */
+//#define TAIDEX__3                                          (0x0002)              /* Divide by 3 */
+//#define TAIDEX__4                                          (0x0003)              /* Divide by 4 */
+//#define TAIDEX__5                                          (0x0004)              /* Divide by 5 */
+//#define TAIDEX__6                                          (0x0005)              /* Divide by 6 */
+//#define TAIDEX__7                                          (0x0006)              /* Divide by 7 */
+//#define TAIDEX__8                                          (0x0007)              /* Divide by 8 */
+
+
+//*****************************************************************************
+// TLV Bits
+//*****************************************************************************
+
+
+//*****************************************************************************
+// WDT_A Bits
+//*****************************************************************************
+/* WDTCTL[WDTIS] Bits */
+#define WDTIS_OFS                                          ( 0)                  /* WDTIS Offset */
+#define WDTIS_M                                            (0x0007)              /* Watchdog timer interval select */
+#define WDTIS0                                             (0x0001)              /* Watchdog timer interval select */
+#define WDTIS1                                             (0x0002)              /* Watchdog timer interval select */
+#define WDTIS2                                             (0x0004)              /* Watchdog timer interval select */
+#define WDTIS_0                                            (0x0000)              /* Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) */
+#define WDTIS_1                                            (0x0001)              /* Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) */
+#define WDTIS_2                                            (0x0002)              /* Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) */
+#define WDTIS_3                                            (0x0003)              /* Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) */
+#define WDTIS_4                                            (0x0004)              /* Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) */
+#define WDTIS_5                                            (0x0005)              /* Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) */
+#define WDTIS_6                                            (0x0006)              /* Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) */
+#define WDTIS_7                                            (0x0007)              /* Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) */
+/* WDTCTL[WDTCNTCL] Bits */
+#define WDTCNTCL_OFS                                       ( 3)                  /* WDTCNTCL Offset */
+#define WDTCNTCL                                           (0x0008)              /* Watchdog timer counter clear */
+/* WDTCTL[WDTTMSEL] Bits */
+#define WDTTMSEL_OFS                                       ( 4)                  /* WDTTMSEL Offset */
+#define WDTTMSEL                                           (0x0010)              /* Watchdog timer mode select */
+/* WDTCTL[WDTSSEL] Bits */
+#define WDTSSEL_OFS                                        ( 5)                  /* WDTSSEL Offset */
+#define WDTSSEL_M                                          (0x0060)              /* Watchdog timer clock source select */
+#define WDTSSEL0                                           (0x0020)              /* Watchdog timer clock source select */
+#define WDTSSEL1                                           (0x0040)              /* Watchdog timer clock source select */
+#define WDTSSEL_0                                          (0x0000)              /* SMCLK */
+#define WDTSSEL_1                                          (0x0020)              /* ACLK */
+#define WDTSSEL_2                                          (0x0040)              /* VLOCLK */
+#define WDTSSEL_3                                          (0x0060)              /* BCLK */
+#define WDTSSEL__SMCLK                                     (0x0000)              /* SMCLK */
+#define WDTSSEL__ACLK                                      (0x0020)              /* ACLK */
+#define WDTSSEL__VLOCLK                                    (0x0040)              /* VLOCLK */
+#define WDTSSEL__BCLK                                      (0x0060)              /* BCLK */
+/* WDTCTL[WDTHOLD] Bits */
+#define WDTHOLD_OFS                                        ( 7)                  /* WDTHOLD Offset */
+#define WDTHOLD                                            (0x0080)              /* Watchdog timer hold */
+/* WDTCTL[WDTPW] Bits */
+#define WDTPW_OFS                                          ( 8)                  /* WDTPW Offset */
+#define WDTPW_M                                            (0xff00)              /* Watchdog timer password */
+
+/* Pre-defined bitfield values */
+#define WDTPW                                              (0x5A00)              /* WDT Key Value for WDT write access */
+
+//*****************************************************************************
+// BSL
+//*****************************************************************************
+#define BSL_DEFAULT_PARAM                                  (0xFC48FFFF)          /* I2C slave address = 0x48, Interface selection = Auto */
+#define BSL_API_TABLE_ADDR                                 (0x00202000)          /* Address of BSL API table */
+#define BSL_ENTRY_FUNCTION                                 (*((uint32_t *)BSL_API_TABLE_ADDR))
+
+#define BSL_AUTO_INTERFACE                                 (0x0000E0000)         /* Auto detect interface */
+#define BSL_UART_INTERFACE                                 (0x0000C0000)         /* UART interface */
+#define BSL_SPI_INTERFACE                                  (0x0000A0000)         /* SPI interface */
+#define BSL_I2C_INTERFACE                                  (0x000080000)         /* I2C interface */
+
+#define BSL_INVOKE(x)                                      ((void (*)())BSL_ENTRY_FUNCTION)((uint32_t) x) /* Invoke the BSL with paramters */
+
+//*****************************************************************************
+// ULP Advisor
+//*****************************************************************************
+#ifdef __TMS470__
+#pragma ULP_PORT_CONFIG(1,DIR={0x40004C04,8},OUT={0x40004C02,8},SEL1={0x40004C0A,8},SEL2={0x40004C0C,8})
+#pragma ULP_PORT_CONFIG(2,DIR={0x40004C05,8},OUT={0x40004C03,8},SEL1={0x40004C0B,8},SEL2={0x40004C0D,8})
+#pragma ULP_PORT_CONFIG(3,DIR={0x40004C24,8},OUT={0x40004C22,8},SEL1={0x40004C2A,8},SEL2={0x40004C2C,8})
+#pragma ULP_PORT_CONFIG(4,DIR={0x40004C25,8},OUT={0x40004C23,8},SEL1={0x40004C2B,8},SEL2={0x40004C2D,8})
+#pragma ULP_PORT_CONFIG(5,DIR={0x40004C44,8},OUT={0x40004C42,8},SEL1={0x40004C4A,8},SEL2={0x40004C4C,8})
+#pragma ULP_PORT_CONFIG(6,DIR={0x40004C45,8},OUT={0x40004C43,8},SEL1={0x40004C4B,8},SEL2={0x40004C4D,8})
+#pragma ULP_PORT_CONFIG(7,DIR={0x40004C64,8},OUT={0x40004C62,8},SEL1={0x40004C6A,8},SEL2={0x40004C6C,8})
+#pragma ULP_PORT_CONFIG(8,DIR={0x40004C65,8},OUT={0x40004C63,8},SEL1={0x40004C6B,8},SEL2={0x40004C6D,8})
+#pragma ULP_PORT_CONFIG(9,DIR={0x40004C84,8},OUT={0x40004C82,8},SEL1={0x40004C8A,8},SEL2={0x40004C8C,8})
+#pragma ULP_PORT_CONFIG(10,DIR={0x40004C85,8},OUT={0x40004C83,8},SEL1={0x40004C8B,8},SEL2={0x40004C8D,8})
+#endif
+
+//*****************************************************************************
+// NVIC interrupts
+//*****************************************************************************
+
+// System exceptions
+#define FAULT_NMI                                          ( 2)                  /* NMI fault */
+#define FAULT_HARD                                         ( 3)                  /* Hard fault */
+#define FAULT_MPU                                          ( 4)                  /* MPU fault */
+#define FAULT_BUS                                          ( 5)                  /* Bus fault */
+#define FAULT_USAGE                                        ( 6)                  /* Usage fault */
+#define FAULT_SVCALL                                       (11)                  /* SVCall */
+#define FAULT_DEBUG                                        (12)                  /* Debug monitor */
+#define FAULT_PENDSV                                       (14)                  /* PendSV */
+#define FAULT_SYSTICK                                      (15)                  /* System Tick */
+
+// External interrupts
+#define INT_PSS                                            (16)                  /* PSS IRQ */
+#define INT_CS                                             (17)                  /* CS IRQ */
+#define INT_PCM                                            (18)                  /* PCM IRQ */
+#define INT_WDT_A                                          (19)                  /* WDT_A IRQ */
+#define INT_FPU                                            (20)                  /* FPU IRQ */
+#define INT_FLCTL                                          (21)                  /* FLCTL IRQ */
+#define INT_COMP_E0                                        (22)                  /* COMP_E0 IRQ */
+#define INT_COMP_E1                                        (23)                  /* COMP_E1 IRQ */
+#define INT_TA0_0                                          (24)                  /* TA0_0 IRQ */
+#define INT_TA0_N                                          (25)                  /* TA0_N IRQ */
+#define INT_TA1_0                                          (26)                  /* TA1_0 IRQ */
+#define INT_TA1_N                                          (27)                  /* TA1_N IRQ */
+#define INT_TA2_0                                          (28)                  /* TA2_0 IRQ */
+#define INT_TA2_N                                          (29)                  /* TA2_N IRQ */
+#define INT_TA3_0                                          (30)                  /* TA3_0 IRQ */
+#define INT_TA3_N                                          (31)                  /* TA3_N IRQ */
+#define INT_EUSCIA0                                        (32)                  /* EUSCIA0 IRQ */
+#define INT_EUSCIA1                                        (33)                  /* EUSCIA1 IRQ */
+#define INT_EUSCIA2                                        (34)                  /* EUSCIA2 IRQ */
+#define INT_EUSCIA3                                        (35)                  /* EUSCIA3 IRQ */
+#define INT_EUSCIB0                                        (36)                  /* EUSCIB0 IRQ */
+#define INT_EUSCIB1                                        (37)                  /* EUSCIB1 IRQ */
+#define INT_EUSCIB2                                        (38)                  /* EUSCIB2 IRQ */
+#define INT_EUSCIB3                                        (39)                  /* EUSCIB3 IRQ */
+#define INT_ADC14                                          (40)                  /* ADC14 IRQ */
+#define INT_T32_INT1                                       (41)                  /* T32_INT1 IRQ */
+#define INT_T32_INT2                                       (42)                  /* T32_INT2 IRQ */
+#define INT_T32_INTC                                       (43)                  /* T32_INTC IRQ */
+#define INT_AES256                                         (44)                  /* AES256 IRQ */
+#define INT_RTC_C                                          (45)                  /* RTC_C IRQ */
+#define INT_DMA_ERR                                        (46)                  /* DMA_ERR IRQ */
+#define INT_DMA_INT3                                       (47)                  /* DMA_INT3 IRQ */
+#define INT_DMA_INT2                                       (48)                  /* DMA_INT2 IRQ */
+#define INT_DMA_INT1                                       (49)                  /* DMA_INT1 IRQ */
+#define INT_DMA_INT0                                       (50)                  /* DMA_INT0 IRQ */
+#define INT_PORT1                                          (51)                  /* PORT1 IRQ */
+#define INT_PORT2                                          (52)                  /* PORT2 IRQ */
+#define INT_PORT3                                          (53)                  /* PORT3 IRQ */
+#define INT_PORT4                                          (54)                  /* PORT4 IRQ */
+#define INT_PORT5                                          (55)                  /* PORT5 IRQ */
+#define INT_PORT6                                          (56)                  /* PORT6 IRQ */
+
+// Highest interrupt available
+#define NUM_INTERRUPTS                                     (56)
+
+#endif // __MSP432P401R_H__
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp_compatibility.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp_compatibility.h
new file mode 100644
index 000000000..15dec1f51
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp_compatibility.h
@@ -0,0 +1,167 @@
+//*****************************************************************************
+//
+// Copyright (C) 2013 - 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+//  Redistributions of source code must retain the above copyright
+//  notice, this list of conditions and the following disclaimer.
+//
+//  Redistributions in binary form must reproduce the above copyright
+//  notice, this list of conditions and the following disclaimer in the
+//  documentation and/or other materials provided with the
+//  distribution.
+//
+//  Neither the name of Texas Instruments Incorporated nor the names of
+//  its contributors may be used to endorse or promote products derived
+//  from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// MSP430 intrinsic redefinitions for use with MSP432 Family Devices
+//
+//****************************************************************************
+
+// Intrinsics with ARM equivalents
+#if defined ( __TMS470__ ) /* TI CGT Compiler */
+
+#include <cmsis_ccs.h>
+
+#define __sleep()                       __wfi()
+#define __deep_sleep()                  { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __wfi(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; }
+#define __low_power_mode_off_on_exit()  { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; }
+#define __get_SP_register()             __get_MSP()
+#define __set_SP_register(x)            __set_MSP(x)
+#define __get_interrupt_state()         __get_PRIMASK()
+#define __set_interrupt_state(x)        __set_PRIMASK(x)
+#define __enable_interrupt()            _enable_interrupts()
+#define __enable_interrupts()           _enable_interrupts()
+#define __disable_interrupt()           _disable_interrupts()
+#define __disable_interrupts()          _disable_interrupts()
+#define __no_operation()                __asm("  nop")
+
+#elif defined ( __ICCARM__ )  /* IAR Compiler */
+
+#include <stdint.h>
+
+#define __INLINE                        inline
+#include <cmsis_iar.h>
+
+#define __sleep()                       __WFI()
+#define __deep_sleep()                  { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __WFI(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; }
+#define __low_power_mode_off_on_exit()  { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; }
+#define __get_SP_register()             __get_MSP()
+#define __set_SP_register()             __set_MSP()
+#define __get_interrupt_state()         __get_PRIMASK()
+#define __set_interrupt_state(x)        __set_PRIMASK(x)
+#define __enable_interrupt()            __asm("  cpsie i")
+#define __enable_interrupts()           __asm("  cpsie i")
+#define __disable_interrupt()           __asm("  cpsid i")
+#define __disable_interrupts()          __asm("  cpsid i")
+#define __no_operation()                __asm("  nop")
+
+// Intrinsics without ARM equivalents
+#define __bcd_add_short(x,y)            { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __bcd_add_long(x,y)             { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __bcd_add_long_long(x,y)        { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __even_in_range(x,y)            { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __data20_write_char(x,y)        { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __data20_write_short(x,y)       { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __data20_write_long(x,y)        { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __never_executed()              { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __op_code()                     { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __code_distance()               { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __bic_SR_register(x)            { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __bis_SR_register(x)            { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __bis_SR_register_on_exit(x)    { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
+#define __bic_SR_register_on_exit(x)    { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
+
+#elif defined ( __CC_ARM ) /* ARM Compiler */
+
+#define __sleep()                       __wfi
+#define __deep_sleep()                  { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __wfi(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; }
+#define __low_power_mode_off_on_exit()  { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; }
+#define __get_SP_register()             __get_MSP()
+#define __set_SP_register(x)            __set_MSP(x)
+#define __get_interrupt_state()         __get_PRIMASK()
+#define __set_interrupt_state(x)        __set_PRIMASK(x)
+#define __enable_interrupt()            __asm("  cpsie i")
+#define __enable_interrupts()           __asm("  cpsie i")
+#define __disable_interrupt()           __asm("  cpsid i")
+#define __disable_interrupts()          __asm("  cpsid i")
+#define __no_operation()                __asm("  nop")
+
+// Intrinsics without ARM equivalents
+#define __bcd_add_short(x,y)            { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __bcd_add_long(x,y)             { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __bcd_add_long_long(x,y)        { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __even_in_range(x,y)            { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __data20_write_char(x,y)        { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __data20_write_short(x,y)       { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __data20_write_long(x,y)        { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __never_executed()              { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __op_code()                     { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __code_distance()               { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __bic_SR_register(x)            { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __bis_SR_register(x)            { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __bis_SR_register_on_exit(x)    { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
+#define __bic_SR_register_on_exit(x)    { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
+
+#elif defined ( __GNUC__ ) /* GCC Compiler */
+
+#define __sleep()                       __wfi()
+#define __deep_sleep()                  { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __wfi(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; }
+#define __low_power_mode_off_on_exit()  { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; }
+#define __get_SP_register()             __get_MSP()
+#define __set_SP_register(x)            __set_MSP(x)
+#define __get_interrupt_state()         __get_PRIMASK()
+#define __set_interrupt_state(x)        __set_PRIMASK(x)
+#define __enable_interrupt()            __asm("  cpsie i")
+#define __enable_interrupts()           __asm("  cpsie i")
+#define __disable_interrupt()           __asm("  cpsid i")
+#define __disable_interrupts()          __asm("  cpsid i")
+#define __no_operation()                __asm("  nop")
+
+// Intrinsics without ARM equivalents
+#define __bcd_add_short(x,y)            { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __bcd_add_long(x,y)             { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __bcd_add_long_long(x,y)        { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __even_in_range(x,y)            { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __data20_write_char(x,y)        { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __data20_write_short(x,y)       { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __data20_write_long(x,y)        { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __never_executed()              { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __op_code()                     { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __code_distance()               { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __bic_SR_register(x)            { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __bis_SR_register(x)            { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
+#define __bis_SR_register_on_exit(x)    { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
+#define __bic_SR_register_on_exit(x)    { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
+
+#endif
+
+// Intrinsics without ARM equivalents
+#define __low_power_mode_0()            { __sleep(); }
+#define __low_power_mode_1()            { __sleep(); }
+#define __low_power_mode_2()            { __sleep(); }
+#define __low_power_mode_3()            { __deep_sleep(); }
+#define __low_power_mode_4()            { __deep_sleep(); }
+#define __data16_read_addr(x)           (*((volatile uint32_t *)(x)))
+#define __data20_read_char(x)           (*((volatile uint8_t *)(x)))
+#define __data20_read_short(x)          (*((volatile uint16_t *)(x)))
+#define __data20_read_long(x)           (*((volatile uint32_t *)(x)))
+#define __data16_write_addr(x,y)        { (*((volatile uint32_t *)(x))) }
+#define __get_SR_register()             0
+#define __get_SR_register_on_exit()     0
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/interrupt.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/interrupt.c
new file mode 100644
index 000000000..b1fb81d21
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/interrupt.c
@@ -0,0 +1,537 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+/* Standard Includes */
+#include <stdint.h>
+
+/* DriverLib Includes */
+#include <debug.h>
+#include <cpu.h>
+#include <interrupt.h>
+
+//*****************************************************************************
+//
+// This is a mapping between priority grouping encodings and the number of
+// preemption priority bits.
+//
+//*****************************************************************************
+static const uint32_t g_pulPriority[] =
+{ NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6,
+NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4,
+NVIC_APINT_PRIGROUP_5_3, NVIC_APINT_PRIGROUP_6_2,
+NVIC_APINT_PRIGROUP_7_1 };
+
+//*****************************************************************************
+//
+// This is a mapping between interrupt number and the register that contains
+// the priority encoding for that interrupt.
+//
+//*****************************************************************************
+static const uint32_t g_pulRegs[] =
+{ 0, NVIC_SYS_PRI1_R, NVIC_SYS_PRI2_R, NVIC_SYS_PRI3_R, NVIC_PRI0_R,
+NVIC_PRI1_R, NVIC_PRI2_R, NVIC_PRI3_R, NVIC_PRI4_R, NVIC_PRI5_R,
+NVIC_PRI6_R, NVIC_PRI7_R, NVIC_PRI8_R, NVIC_PRI9_R, NVIC_PRI10_R,
+NVIC_PRI11_R, NVIC_PRI12_R, NVIC_PRI13_R, NVIC_PRI14_R, NVIC_PRI15_R };
+
+//*****************************************************************************
+//
+// This is a mapping between interrupt number (for the peripheral interrupts
+// only) and the register that contains the interrupt enable for that
+// interrupt.
+//
+//*****************************************************************************
+static const uint32_t g_pulEnRegs[] =
+{ NVIC_EN0_R, NVIC_EN1_R };
+
+//*****************************************************************************
+//
+// This is a mapping between interrupt number (for the peripheral interrupts
+// only) and the register that contains the interrupt disable for that
+// interrupt.
+//
+//*****************************************************************************
+static const uint32_t g_pulDisRegs[] =
+{ NVIC_DIS0_R, NVIC_DIS1_R };
+
+//*****************************************************************************
+//
+// This is a mapping between interrupt number (for the peripheral interrupts
+// only) and the register that contains the interrupt pend for that interrupt.
+//
+//*****************************************************************************
+static const uint32_t g_pulPendRegs[] =
+{ NVIC_PEND0_R, NVIC_PEND1_R };
+
+//*****************************************************************************
+//
+// This is a mapping between interrupt number (for the peripheral interrupts
+// only) and the register that contains the interrupt unpend for that
+// interrupt.
+//
+//*****************************************************************************
+static const uint32_t g_pulUnpendRegs[] =
+{ NVIC_UNPEND0_R, NVIC_UNPEND1_R };
+
+//*****************************************************************************
+//
+//! \internal
+//! The default interrupt handler.
+//!
+//! This is the default interrupt handler for all interrupts.  It simply loops
+//! forever so that the system state is preserved for observation by a
+//! debugger.  Since interrupts should be disabled before unregistering the
+//! corresponding handler, this should never be called.
+//!
+//! \return None.
+//
+//*****************************************************************************
+static void IntDefaultHandler(void)
+{
+    //
+    // Go into an infinite loop.
+    //
+    while (1)
+    {
+    }
+}
+
+//*****************************************************************************
+//
+// The processor vector table.
+//
+// This contains a list of the handlers for the various interrupt sources in
+// the system.  The layout of this list is defined by the hardware; assertion
+// of an interrupt causes the processor to start executing directly at the
+// address given in the corresponding location in this list.
+//
+//*****************************************************************************
+#if defined(ewarm)
+#pragma data_alignment=1024
+static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS+1])(void) @ "VTABLE";
+#elif defined(ccs)
+#pragma DATA_ALIGN(g_pfnRAMVectors, 1024)
+#pragma DATA_SECTION(g_pfnRAMVectors, ".vtable")
+void (*g_pfnRAMVectors[NUM_INTERRUPTS + 1])(void);
+#else
+static __attribute__((section("vtable")))
+void (*g_pfnRAMVectors[NUM_INTERRUPTS+1])(void) __attribute__((aligned(1024)));
+#endif
+
+bool Interrupt_enableMaster(void)
+{
+    //
+    // Enable processor interrupts.
+    //
+    return (CPU_cpsie());
+}
+
+bool Interrupt_disableMaster(void)
+{
+    //
+    // Disable processor interrupts.
+    //
+    return (CPU_cpsid());
+}
+
+void Interrupt_registerInterrupt(uint32_t interruptNumber,
+        void (*intHandler)(void))
+{
+    uint32_t ulIdx, ulValue;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(interruptNumber < (NUM_INTERRUPTS+1));
+
+    //
+    // Make sure that the RAM vector table is correctly aligned.
+    //
+    ASSERT(((uint32_t) g_pfnRAMVectors & 0x000000ff) == 0);
+
+    //
+    // See if the RAM vector table has been initialized.
+    //
+    if (SCB->VTOR != (uint32_t) g_pfnRAMVectors)
+    {
+        //
+        // Copy the vector table from the beginning of FLASH to the RAM vector
+        // table.
+        //
+        ulValue = SCB->VTOR;
+        for (ulIdx = 0; ulIdx < (NUM_INTERRUPTS + 1); ulIdx++)
+        {
+            g_pfnRAMVectors[ulIdx] = (void (*)(void)) HWREG32(
+                    (ulIdx * 4) + ulValue);
+        }
+
+        //
+        // Point the NVIC at the RAM vector table.
+        //
+        SCB->VTOR = (uint32_t) g_pfnRAMVectors;
+    }
+
+    //
+    // Save the interrupt handler.
+    //
+    g_pfnRAMVectors[interruptNumber] = intHandler;
+}
+
+void Interrupt_unregisterInterrupt(uint32_t interruptNumber)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(interruptNumber < (NUM_INTERRUPTS+1));
+
+    //
+    // Reset the interrupt handler.
+    //
+    g_pfnRAMVectors[interruptNumber] = IntDefaultHandler;
+}
+
+void Interrupt_setPriorityGrouping(uint32_t bits)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(bits < NUM_PRIORITY);
+
+    //
+    // Set the priority grouping.
+    //
+    SCB->AIRCR = SCB_AIRCR_VECTKEY_M | g_pulPriority[bits];
+}
+
+uint32_t Interrupt_getPriorityGrouping(void)
+{
+    uint32_t ulLoop, ulValue;
+
+    //
+    // Read the priority grouping.
+    //
+    ulValue = SCB->AIRCR & NVIC_APINT_PRIGROUP_M;
+
+    //
+    // Loop through the priority grouping values.
+    //
+    for (ulLoop = 0; ulLoop < NUM_PRIORITY; ulLoop++)
+    {
+        //
+        // Stop looping if this value matches.
+        //
+        if (ulValue == g_pulPriority[ulLoop])
+        {
+            break;
+        }
+    }
+
+    //
+    // Return the number of priority bits.
+    //
+    return (ulLoop);
+}
+
+void Interrupt_setPriority(uint32_t interruptNumber, uint8_t priority)
+{
+    uint32_t ulTemp;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((interruptNumber >= 4) && (interruptNumber < (NUM_INTERRUPTS+1)));
+
+    //
+    // Set the interrupt priority.
+    //
+    ulTemp = HWREG32(g_pulRegs[interruptNumber >> 2]);
+    ulTemp &= ~(0xFF << (8 * (interruptNumber & 3)));
+    ulTemp |= priority << (8 * (interruptNumber & 3));
+    HWREG32 (g_pulRegs[interruptNumber >> 2]) = ulTemp;
+}
+
+uint8_t Interrupt_getPriority(uint32_t interruptNumber)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((interruptNumber >= 4) && (interruptNumber < (NUM_INTERRUPTS+1)));
+
+    //
+    // Return the interrupt priority.
+    //
+    return ((HWREG32(g_pulRegs[interruptNumber >> 2])
+            >> (8 * (interruptNumber & 3))) & 0xFF);
+}
+
+void Interrupt_enableInterrupt(uint32_t interruptNumber)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(interruptNumber < (NUM_INTERRUPTS+1));
+
+    //
+    // Determine the interrupt to enable.
+    //
+    if (interruptNumber == FAULT_MPU)
+    {
+        //
+        // Enable the MemManage interrupt.
+        //
+        SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA;
+    } else if (interruptNumber == FAULT_BUS)
+    {
+        //
+        // Enable the bus fault interrupt.
+        //
+        SCB->SHCSR |= SCB_SHCSR_BUSFAULTENA;
+    } else if (interruptNumber == FAULT_USAGE)
+    {
+        //
+        // Enable the usage fault interrupt.
+        //
+        SCB->SHCSR |= SCB_SHCSR_USGFAULTENA;
+    } else if (interruptNumber == FAULT_SYSTICK)
+    {
+        //
+        // Enable the System Tick interrupt.
+        //
+        SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+    } else if (interruptNumber >= 16)
+    {
+        //
+        // Enable the general interrupt.
+        //
+        HWREG32 (g_pulEnRegs[(interruptNumber - 16) / 32]) = 1
+                << ((interruptNumber - 16) & 31);
+    }
+}
+
+void Interrupt_disableInterrupt(uint32_t interruptNumber)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(interruptNumber < (NUM_INTERRUPTS+1));
+
+    //
+    // Determine the interrupt to disable.
+    //
+    if (interruptNumber == FAULT_MPU)
+    {
+        //
+        // Disable the MemManage interrupt.
+        //
+        SCB->SHCSR &= ~(SCB_SHCSR_MEMFAULTENA);
+    } else if (interruptNumber == FAULT_BUS)
+    {
+        //
+        // Disable the bus fault interrupt.
+        //
+        SCB->SHCSR &= ~(SCB_SHCSR_BUSFAULTENA);
+    } else if (interruptNumber == FAULT_USAGE)
+    {
+        //
+        // Disable the usage fault interrupt.
+        //
+        SCB->SHCSR &= ~(SCB_SHCSR_USGFAULTENA);
+    } else if (interruptNumber == FAULT_SYSTICK)
+    {
+        //
+        // Disable the System Tick interrupt.
+        //
+        SysTick->CTRL &= ~(SysTick_CTRL_ENABLE_Msk);
+    } else if (interruptNumber >= 16)
+    {
+        //
+        // Disable the general interrupt.
+        //
+        HWREG32 (g_pulDisRegs[(interruptNumber - 16) / 32]) = 1
+                << ((interruptNumber - 16) & 31);
+    }
+}
+
+bool Interrupt_isEnabled(uint32_t interruptNumber)
+{
+    uint32_t ulRet;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(interruptNumber < (NUM_INTERRUPTS+1));
+
+    //
+    // Initialize the return value.
+    //
+    ulRet = 0;
+
+    //
+    // Determine the interrupt to disable.
+    //
+    if (interruptNumber == FAULT_MPU)
+    {
+        //
+        // Check the MemManage interrupt.
+        //
+        ulRet = SCB->SHCSR & SCB_SHCSR_MEMFAULTENA;
+    } else if (interruptNumber == FAULT_BUS)
+    {
+        //
+        // Check the bus fault interrupt.
+        //
+        ulRet = SCB->SHCSR & SCB_SHCSR_BUSFAULTENA;
+    } else if (interruptNumber == FAULT_USAGE)
+    {
+        //
+        // Check the usage fault interrupt.
+        //
+        ulRet = SCB->SHCSR & SCB_SHCSR_USGFAULTENA;
+    } else if (interruptNumber == FAULT_SYSTICK)
+    {
+        //
+        // Check the System Tick interrupt.
+        //
+        ulRet = SysTick->CTRL & SysTick_CTRL_ENABLE_Msk;
+    } else if (interruptNumber >= 16)
+    {
+        //
+        // Check the general interrupt.
+        //
+        ulRet = HWREG32(g_pulEnRegs[(interruptNumber - 16) / 32])
+                & (1 << ((interruptNumber - 16) & 31));
+    }
+    return (ulRet);
+}
+
+void Interrupt_pendInterrupt(uint32_t interruptNumber)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(interruptNumber < (NUM_INTERRUPTS+1));
+
+    //
+    // Determine the interrupt to pend.
+    //
+    if (interruptNumber == FAULT_NMI)
+    {
+        //
+        // Pend the NMI interrupt.
+        //
+        SCB->ICSR |= SCB_ICSR_NMIPENDSET;
+    } else if (interruptNumber == FAULT_PENDSV)
+    {
+        //
+        // Pend the PendSV interrupt.
+        //
+        SCB->ICSR |= SCB_ICSR_PENDSVSET;
+    } else if (interruptNumber == FAULT_SYSTICK)
+    {
+        //
+        // Pend the SysTick interrupt.
+        //
+        SCB->ICSR |= SCB_ICSR_PENDSTSET;
+    } else if (interruptNumber >= 16)
+    {
+        //
+        // Pend the general interrupt.
+        //
+        HWREG32 (g_pulPendRegs[(interruptNumber - 16) / 32]) = 1
+                << ((interruptNumber - 16) & 31);
+    }
+}
+
+void Interrupt_unpendInterrupt(uint32_t interruptNumber)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(interruptNumber < (NUM_INTERRUPTS+1));
+
+    //
+    // Determine the interrupt to unpend.
+    //
+    if (interruptNumber == FAULT_PENDSV)
+    {
+        //
+        // Unpend the PendSV interrupt.
+        //
+        SCB->ICSR |= SCB_ICSR_PENDSVCLR;
+    } else if (interruptNumber == FAULT_SYSTICK)
+    {
+        //
+        // Unpend the SysTick interrupt.
+        //
+        SCB->ICSR |= SCB_ICSR_PENDSTCLR;
+    } else if (interruptNumber >= 16)
+    {
+        //
+        // Unpend the general interrupt.
+        //
+        HWREG32 (g_pulUnpendRegs[(interruptNumber - 16) / 32]) = 1
+                << ((interruptNumber - 16) & 31);
+    }
+}
+
+void Interrupt_setPriorityMask(uint8_t priorityMask)
+{
+    CPU_basepriSet(priorityMask);
+}
+
+uint8_t Interrupt_getPriorityMask(void)
+{
+    return (CPU_basepriGet());
+}
+
+void Interrupt_setVectorTableAddress(uint32_t addr)
+{
+    SCB->VTOR = addr;
+}
+
+uint32_t Interrupt_getVectorTableAddress(void)
+{
+    return SCB->VTOR;
+}
+
+void Interrupt_enableSleepOnIsrExit(void)
+{
+    SCB->SCR |= SCB_SCR_SLEEPONEXIT;
+}
+
+void Interrupt_disableSleepOnIsrExit(void)
+{
+    SCB->SCR &= ~SCB_SCR_SLEEPONEXIT;
+}
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/interrupt.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/interrupt.h
new file mode 100644
index 000000000..253dd660b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/interrupt.h
@@ -0,0 +1,519 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+
+//*****************************************************************************
+//
+//! \addtogroup interrupt_api
+//! @{
+//
+//*****************************************************************************
+
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <msp.h>
+
+//*****************************************************************************
+//
+// Macro to generate an interrupt priority mask based on the number of bits
+// of priority supported by the hardware.
+//
+//*****************************************************************************
+#define INT_PRIORITY_MASK       ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF)
+#define NUM_PRIORITY            8
+
+#define NVIC_APINT_PRIGROUP_M   0x00000700  // Interrupt Priority Grouping
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000  // Priority group 7.1 split
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100  // Priority group 6.2 split
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200  // Priority group 5.3 split
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300  // Priority group 4.4 split
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400  // Priority group 3.5 split
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500  // Priority group 2.6 split
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600  // Priority group 1.7 split
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700  // Priority group 0.8 split
+#define NVIC_SYS_PRI1_R         0xE000ED18  // System Handler Priority 1
+#define NVIC_SYS_PRI2_R         0xE000ED1C  // System Handler Priority 2
+#define NVIC_SYS_PRI3_R         0xE000ED20  // System Handler Priority 3
+#define NVIC_PRI0_R             0xE000E400  // Interrupt 0-3 Priority
+#define NVIC_PRI1_R             0xE000E404  // Interrupt 4-7 Priority
+#define NVIC_PRI2_R             0xE000E408  // Interrupt 8-11 Priority
+#define NVIC_PRI3_R             0xE000E40C  // Interrupt 12-15 Priority
+#define NVIC_PRI4_R             0xE000E410  // Interrupt 16-19 Priority
+#define NVIC_PRI5_R             0xE000E414  // Interrupt 20-23 Priority
+#define NVIC_PRI6_R             0xE000E418  // Interrupt 24-27 Priority
+#define NVIC_PRI7_R             0xE000E41C  // Interrupt 28-31 Priority
+#define NVIC_PRI8_R             0xE000E420  // Interrupt 32-35 Priority
+#define NVIC_PRI9_R             0xE000E424  // Interrupt 36-39 Priority
+#define NVIC_PRI10_R            0xE000E428  // Interrupt 40-43 Priority
+#define NVIC_PRI11_R            0xE000E42C  // Interrupt 44-47 Priority
+#define NVIC_PRI12_R            0xE000E430  // Interrupt 48-51 Priority
+#define NVIC_PRI13_R            0xE000E434  // Interrupt 52-55 Priority
+#define NVIC_PRI14_R            0xE000E438  // Interrupt 56-59 Priority
+#define NVIC_PRI15_R            0xE000E43C  // Interrupt 60-63 Priority
+#define NVIC_EN0_R              0xE000E100  // Interrupt 0-31 Set Enable
+#define NVIC_EN1_R              0xE000E104  // Interrupt 32-54 Set Enable
+#define NVIC_DIS0_R             0xE000E180  // Interrupt 0-31 Clear Enable
+#define NVIC_DIS1_R             0xE000E184  // Interrupt 32-54 Clear Enable
+#define NVIC_PEND0_R            0xE000E200  // Interrupt 0-31 Set Pending
+#define NVIC_PEND1_R            0xE000E204  // Interrupt 32-54 Set Pending
+#define NVIC_UNPEND0_R          0xE000E280  // Interrupt 0-31 Clear Pending
+#define NVIC_UNPEND1_R          0xE000E284  // Interrupt 32-54 Clear Pending
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! Enables the processor interrupt.
+//!
+//! This function allows the processor to respond to interrupts.  This function
+//! does not affect the set of interrupts enabled in the interrupt controller;
+//! it just gates the single interrupt from the controller to the processor.
+//!
+//! \return Returns \b true if interrupts were disabled when the function was
+//! called or \b false if they were initially enabled.
+//
+//*****************************************************************************
+extern bool Interrupt_enableMaster(void);
+
+//*****************************************************************************
+//
+//! Disables the processor interrupt.
+//!
+//! This function prevents the processor from receiving interrupts.  This
+//! function does not affect the set of interrupts enabled in the interrupt
+//! controller; it just gates the single interrupt from the controller to the
+//! processor.
+//!
+//! \return Returns \b true if interrupts were already disabled when the
+//! function was called or \b false if they were initially enabled.
+//
+//*****************************************************************************
+extern bool Interrupt_disableMaster(void);
+
+//*****************************************************************************
+//
+//! Registers a function to be called when an interrupt occurs.
+//!
+//! \param interruptNumber specifies the interrupt in question.
+//! \param intHandler is a pointer to the function to be called.
+//!
+//! \note The use of this function (directly or indirectly via a peripheral
+//! driver interrupt register function) moves the interrupt vector table from
+//! flash to SRAM.  Therefore, care must be taken when linking the application
+//! to ensure that the SRAM vector table is located at the beginning of SRAM;
+//! otherwise the NVIC does not look in the correct portion of memory for the
+//! vector table (it requires the vector table be on a 1 kB memory alignment).
+//! Normally, the SRAM vector table is so placed via the use of linker scripts.
+//! See the discussion of compile-time versus run-time interrupt handler
+//! registration in the introduction to this chapter.
+//!
+//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
+//! parameter
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void Interrupt_registerInterrupt(uint32_t interruptNumber,
+        void (*intHandler)(void));
+
+//*****************************************************************************
+//
+//! Unregisters the function to be called when an interrupt occurs.
+//!
+//! \param interruptNumber specifies the interrupt in question.
+//!
+//! This function is used to indicate that no handler should be called when the
+//! given interrupt is asserted to the processor.  The interrupt source is
+//! automatically disabled (via Interrupt_disableInterrupt()) if necessary.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
+//! parameter
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void Interrupt_unregisterInterrupt(uint32_t interruptNumber);
+
+//*****************************************************************************
+//
+//! Sets the priority grouping of the interrupt controller.
+//!
+//! \param bits specifies the number of bits of preemptable priority.
+//!
+//! This function specifies the split between preemptable priority levels and
+//! sub-priority levels in the interrupt priority specification.  The range of
+//! the grouping values are dependent upon the hardware implementation; on
+//! the MSP432 family, three bits are available for hardware interrupt
+//! prioritization and therefore priority grouping values of three through
+//! seven have the same effect.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void Interrupt_setPriorityGrouping(uint32_t bits);
+
+//*****************************************************************************
+//
+//! Gets the priority grouping of the interrupt controller.
+//!
+//! This function returns the split between preemptable priority levels and
+//! sub-priority levels in the interrupt priority specification.
+//!
+//! \return The number of bits of preemptable priority.
+//
+//*****************************************************************************
+extern uint32_t Interrupt_getPriorityGrouping(void);
+
+//*****************************************************************************
+//
+//! Sets the priority of an interrupt.
+//!
+//! \param interruptNumber specifies the interrupt in question.
+//! \param priority specifies the priority of the interrupt.
+//!
+//! This function is used to set the priority of an interrupt.  When multiple
+//! interrupts are asserted simultaneously, the ones with the highest priority
+//! are processed before the lower priority interrupts.  Smaller numbers
+//! correspond to higher interrupt priorities; priority 0 is the highest
+//! interrupt priority.
+//!
+//! The hardware priority mechanism only looks at the upper N bits of the
+//! priority level (where N is 3 for the MSP432 family), so any
+//! prioritization must be performed in those bits.  The remaining bits can be
+//! used to sub-prioritize the interrupt sources, and may be used by the
+//! hardware priority mechanism on a future part.  This arrangement allows
+//! priorities to migrate to different NVIC implementations without changing
+//! the gross prioritization of the interrupts.
+//!
+//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
+//! parameter
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void Interrupt_setPriority(uint32_t interruptNumber, uint8_t priority);
+
+//*****************************************************************************
+//
+//! Gets the priority of an interrupt.
+//!
+//! \param interruptNumber specifies the interrupt in question.
+//!
+//! This function gets the priority of an interrupt.  See
+//! Interrupt_setPriority() for a definition of the priority value.
+//!
+//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
+//! parameter
+//!
+//! \return Returns the interrupt priority, or -1 if an invalid interrupt was
+//! specified.
+//
+//*****************************************************************************
+extern uint8_t Interrupt_getPriority(uint32_t interruptNumber);
+
+//*****************************************************************************
+//
+//! Enables an interrupt.
+//!
+//! \param interruptNumber specifies the interrupt to be enabled.
+//!
+//! The specified interrupt is enabled in the interrupt controller.  Other
+//! enables for the interrupt (such as at the peripheral level) are unaffected
+//! by this function.
+//!
+//! Valid values will vary from part to part, so it is important to check the
+//! device specific datasheet, however for MSP432 101 the following values can
+//! be provided:
+//!     - \b FAULT_NMI
+//!     - \b FAULT_HARD
+//!     - \b FAULT_MPU
+//!     - \b FAULT_BUS
+//!     - \b FAULT_USAGE
+//!     - \b FAULT_SVCALL
+//!     - \b FAULT_DEBUG
+//!     - \b FAULT_PENDSV
+//!     - \b FAULT_SYSTICK
+//!     - \b INT_PSS
+//!     - \b INT_CS
+//!     - \b INT_PCM
+//!     - \b INT_WDT_A
+//!     - \b INT_FPU
+//!     - \b INT_FLCTL
+//!     - \b INT_COMP0
+//!     - \b INT_COMP1
+//!     - \b INT_TA0_0
+//!     - \b INT_TA0_N
+//!     - \b INT_TA1_0
+//!     - \b INT_TA1_N
+//!     - \b INT_TA2_0
+//!     - \b INT_TA2_N
+//!     - \b INT_TA3_0
+//!     - \b INT_TA3_N
+//!     - \b INT_EUSCIA0
+//!     - \b INT_EUSCIA1
+//!     - \b INT_EUSCIA2
+//!     - \b INT_EUSCIA3
+//!     - \b INT_EUSCIB0
+//!     - \b INT_EUSCIB1
+//!     - \b INT_EUSCIB2
+//!     - \b INT_EUSCIB3
+//!     - \b INT_ADC14
+//!     - \b INT_T32_INT1
+//!     - \b INT_T32_INT2
+//!     - \b INT_T32_INTC
+//!     - \b INT_AES
+//!     - \b INT_RTCC
+//!     - \b INT_DMA_ERR
+//!     - \b INT_DMA_INT3
+//!     - \b INT_DMA_INT2
+//!     - \b INT_DMA_INT1
+//!     - \b INT_DMA_INT0
+//!     - \b INT_PORT1
+//!     - \b INT_PORT2
+//!     - \b INT_PORT3
+//!     - \b INT_PORT4
+//!     - \b INT_PORT5
+//!     - \b INT_PORT6
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void Interrupt_enableInterrupt(uint32_t interruptNumber);
+
+//*****************************************************************************
+//
+//! Disables an interrupt.
+//!
+//! \param interruptNumber specifies the interrupt to be disabled.
+//!
+//! The specified interrupt is disabled in the interrupt controller.  Other
+//! enables for the interrupt (such as at the peripheral level) are unaffected
+//! by this function.
+//!
+//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
+//! parameter
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void Interrupt_disableInterrupt(uint32_t interruptNumber);
+
+//*****************************************************************************
+//
+//! Returns if a peripheral interrupt is enabled.
+//!
+//! \param interruptNumber specifies the interrupt to check.
+//!
+//! This function checks if the specified interrupt is enabled in the interrupt
+//! controller.
+//!
+//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
+//! parameter
+//!
+//! \return A non-zero value if the interrupt is enabled.
+//
+//*****************************************************************************
+extern bool Interrupt_isEnabled(uint32_t interruptNumber);
+
+//*****************************************************************************
+//
+//! Pends an interrupt.
+//!
+//! \param interruptNumber specifies the interrupt to be pended.
+//!
+//! The specified interrupt is pended in the interrupt controller.  Pending an
+//! interrupt causes the interrupt controller to execute the corresponding
+//! interrupt handler at the next available time, based on the current
+//! interrupt state priorities. For example, if called by a higher priority
+//! interrupt handler, the specified interrupt handler is not called until
+//! after the current interrupt handler has completed execution.  The interrupt
+//! must have been enabled for it to be called.
+//!
+//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
+//! parameter
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void Interrupt_pendInterrupt(uint32_t interruptNumber);
+
+//*****************************************************************************
+//
+//! Un-pends an interrupt.
+//!
+//! \param interruptNumber specifies the interrupt to be un-pended.
+//!
+//! The specified interrupt is un-pended in the interrupt controller.  This
+//! will cause any previously generated interrupts that have not been handled
+//! yet (due to higher priority interrupts or the interrupt no having been
+//! enabled yet) to be discarded.
+//!
+//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
+//! parameter
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void Interrupt_unpendInterrupt(uint32_t interruptNumber);
+
+//*****************************************************************************
+//
+//! Sets the priority masking level
+//!
+//! \param priorityMask is the priority level that is masked.
+//!
+//! This function sets the interrupt priority masking level so that all
+//! interrupts at the specified or lesser priority level are masked.  Masking
+//! interrupts can be used to globally disable a set of interrupts with
+//! priority below a predetermined threshold.  A value of 0 disables priority
+//! masking.
+//!
+//! Smaller numbers correspond to higher interrupt priorities.  So for example
+//! a priority level mask of 4 allows interrupts of priority level 0-3,
+//! and interrupts with a numerical priority of 4 and greater are blocked.
+//!
+//! The hardware priority mechanism only looks at the upper N bits of the
+//! priority level (where N is 3 for the MSP432 family), so any
+//! prioritization must be performed in those bits.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void Interrupt_setPriorityMask(uint8_t priorityMask);
+
+//*****************************************************************************
+//
+//! Gets the priority masking level
+//!
+//! This function gets the current setting of the interrupt priority masking
+//! level.  The value returned is the priority level such that all interrupts
+//! of that and lesser priority are masked.  A value of 0 means that priority
+//! masking is disabled.
+//!
+//! Smaller numbers correspond to higher interrupt priorities.  So for example
+//! a priority level mask of 4 allows interrupts of priority level 0-3,
+//! and interrupts with a numerical priority of 4 and greater are blocked.
+//!
+//! The hardware priority mechanism only looks at the upper N bits of the
+//! priority level (where N is 3 for the MSP432 family), so any
+//! prioritization must be performed in those bits.
+//!
+//! \return Returns the value of the interrupt priority level mask.
+//
+//*****************************************************************************
+extern uint8_t Interrupt_getPriorityMask(void);
+
+//*****************************************************************************
+//
+//! Sets the address of the vector table. This function is for advanced users
+//! who might want to switch between multiple instances of vector tables
+//! (perhaps between flash/ram).
+//!
+//! \param addr is the new address of the vector table.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void Interrupt_setVectorTableAddress(uint32_t addr);
+
+//*****************************************************************************
+//
+//! Returns the address of the interrupt vector table.
+//!
+//! \return Address of the vector table.
+//
+//*****************************************************************************
+extern uint32_t Interrupt_getVectorTableAddress(void);
+
+//*****************************************************************************
+//
+//! Enables the processor to sleep when exiting an ISR. For low power operation,
+//! this is ideal as power cycles are not wasted with the processing required
+//! for waking up from an ISR and going back to sleep.
+//!
+//! \return Address of the vector table.
+//
+//*****************************************************************************
+extern void Interrupt_enableSleepOnIsrExit(void);
+
+//*****************************************************************************
+//
+//! Enables the processor to sleep when exiting an ISR. For low power operation,
+//! this is ideal as power cycles are not wasted with the processing required
+//! for waking up from an ISR and going back to sleep.
+//!
+//! \return Address of the vector table.
+//
+//*****************************************************************************
+extern void Interrupt_disableSleepOnIsrExit(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif // __INTERRUPT_H__
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/mpu.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/mpu.c
new file mode 100644
index 000000000..04bf35ddd
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/mpu.c
@@ -0,0 +1,194 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#include <debug.h>
+#include <interrupt.h>
+#include <mpu.h>
+
+void MPU_enableModule(uint32_t mpuConfig)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(!(mpuConfig & ~(MPU_CONFIG_PRIV_DEFAULT | MPU_CONFIG_HARDFLT_NMI)));
+
+    //
+    // Set the MPU control bits according to the flags passed by the user,
+    // and also set the enable bit.
+    //
+    MPU->CTRL = mpuConfig | MPU_CTRL_ENABLE;
+}
+
+void MPU_disableModule(void)
+{
+    //
+    // Turn off the MPU enable bit.
+    //
+    MPU->CTRL &= ~MPU_CTRL_ENABLE;
+
+}
+
+uint32_t MPU_getRegionCount(void)
+{
+    //
+    // Read the DREGION field of the MPU type register and mask off
+    // the bits of interest to get the count of regions.
+    //
+    return ((MPU->TYPE & MPU_TYPE_DREGION_M) >> NVIC_MPU_TYPE_DREGION_S);
+}
+
+void MPU_enableRegion(uint32_t region)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(region < 8);
+
+    //
+    // Select the region to modify.
+    //
+    MPU->RNR = region;
+
+    //
+    // Modify the enable bit in the region attributes.
+    //
+    MPU->RASR |= MPU_RASR_ENABLE;
+}
+
+void MPU_disableRegion(uint32_t region)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(region < 8);
+
+    //
+    // Select the region to modify.
+    //
+    MPU->RNR = region;
+
+    //
+    // Modify the enable bit in the region attributes.
+    //
+    MPU->RASR &= ~MPU_RASR_ENABLE;
+}
+
+void MPU_setRegion(uint32_t region, uint32_t addr, uint32_t flags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(region < 8);
+
+    //
+    // Program the base address, use the region field to select the
+    // region at the same time.
+    //
+    MPU->RBAR = addr | region | MPU_RBAR_VALID;
+
+    //
+    // Program the region attributes.  Set the TEX field and the S, C,
+    // and B bits to fixed values that are suitable for all Stellaris
+    // memory.
+    //
+    MPU->RASR = (flags & ~(MPU_RASR_TEX_M | MPU_RASR_C)) | MPU_RASR_S
+            | MPU_RASR_B;
+}
+
+void MPU_getRegion(uint32_t region, uint32_t *addr, uint32_t *pflags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(region < 8);
+    ASSERT(addr);
+    ASSERT(pflags);
+
+    //
+    // Select the region to get.
+    //
+    MPU->RNR = region;
+
+    //
+    // Read and store the base address for the region.
+    //
+    *addr = MPU->RBAR & MPU_RBAR_ADDR_M;
+
+    //
+    // Read and store the region attributes.
+    //
+    *pflags = MPU->RASR;
+}
+
+void MPU_registerInterrupt(void (*intHandler)(void))
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(intHandler);
+
+    //
+    // Register the interrupt handler.
+    //
+    Interrupt_registerInterrupt(FAULT_MPU, intHandler);
+
+}
+
+void MPU_unregisterInterrupt(void)
+{
+    //
+    // Unregister the interrupt handler.
+    //
+    Interrupt_unregisterInterrupt(FAULT_MPU);
+}
+
+void MPU_enableInterrupt(void)
+{
+
+    //
+    // Enable the memory management fault.
+    //
+    Interrupt_enableInterrupt(FAULT_MPU);
+
+}
+
+void MPU_disableInterrupt(void)
+{
+    //
+    // Disable the interrupt.
+    //
+    Interrupt_disableInterrupt(FAULT_MPU);
+}
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/mpu.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/mpu.h
new file mode 100644
index 000000000..1b1162c2b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/mpu.h
@@ -0,0 +1,449 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __MPU_H__
+#define __MPU_H__
+
+//*****************************************************************************
+//
+//! \addtogroup mpu_api
+//! @{
+//
+//*****************************************************************************
+
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <msp.h>
+#include <stdint.h>
+
+//*****************************************************************************
+//
+// Flags that can be passed to MPU_enableModule.
+//
+//*****************************************************************************
+#define MPU_CONFIG_PRIV_DEFAULT     MPU_CTRL_PRIVDEFENA
+#define MPU_CONFIG_HARDFLT_NMI      MPU_CTRL_HFNMIENA
+#define MPU_CONFIG_NONE             0
+
+//*****************************************************************************
+//
+// Flags for the region size to be passed to MPU_setRegion.
+//
+//*****************************************************************************
+#define MPU_RGN_SIZE_32B            (4 << 1)
+#define MPU_RGN_SIZE_64B            (5 << 1)
+#define MPU_RGN_SIZE_128B           (6 << 1)
+#define MPU_RGN_SIZE_256B           (7 << 1)
+#define MPU_RGN_SIZE_512B           (8 << 1)
+
+#define MPU_RGN_SIZE_1K             (9 << 1)
+#define MPU_RGN_SIZE_2K             (10 << 1)
+#define MPU_RGN_SIZE_4K             (11 << 1)
+#define MPU_RGN_SIZE_8K             (12 << 1)
+#define MPU_RGN_SIZE_16K            (13 << 1)
+#define MPU_RGN_SIZE_32K            (14 << 1)
+#define MPU_RGN_SIZE_64K            (15 << 1)
+#define MPU_RGN_SIZE_128K           (16 << 1)
+#define MPU_RGN_SIZE_256K           (17 << 1)
+#define MPU_RGN_SIZE_512K           (18 << 1)
+
+#define MPU_RGN_SIZE_1M             (19 << 1)
+#define MPU_RGN_SIZE_2M             (20 << 1)
+#define MPU_RGN_SIZE_4M             (21 << 1)
+#define MPU_RGN_SIZE_8M             (22 << 1)
+#define MPU_RGN_SIZE_16M            (23 << 1)
+#define MPU_RGN_SIZE_32M            (24 << 1)
+#define MPU_RGN_SIZE_64M            (25 << 1)
+#define MPU_RGN_SIZE_128M           (26 << 1)
+#define MPU_RGN_SIZE_256M           (27 << 1)
+#define MPU_RGN_SIZE_512M           (28 << 1)
+
+#define MPU_RGN_SIZE_1G             (29 << 1)
+#define MPU_RGN_SIZE_2G             (30 << 1)
+#define MPU_RGN_SIZE_4G             (31 << 1)
+
+//*****************************************************************************
+//
+// Flags for the permissions to be passed to MPU_setRegion.
+//
+//*****************************************************************************
+#define MPU_RGN_PERM_EXEC           0x00000000
+#define MPU_RGN_PERM_NOEXEC         0x10000000
+#define MPU_RGN_PERM_PRV_NO_USR_NO  0x00000000
+#define MPU_RGN_PERM_PRV_RW_USR_NO  0x01000000
+#define MPU_RGN_PERM_PRV_RW_USR_RO  0x02000000
+#define MPU_RGN_PERM_PRV_RW_USR_RW  0x03000000
+#define MPU_RGN_PERM_PRV_RO_USR_NO  0x05000000
+#define MPU_RGN_PERM_PRV_RO_USR_RO  0x06000000
+
+//*****************************************************************************
+//
+// Flags for the sub-region to be passed to MPU_setRegion.
+//
+//*****************************************************************************
+#define MPU_SUB_RGN_DISABLE_0       0x00000100
+#define MPU_SUB_RGN_DISABLE_1       0x00000200
+#define MPU_SUB_RGN_DISABLE_2       0x00000400
+#define MPU_SUB_RGN_DISABLE_3       0x00000800
+#define MPU_SUB_RGN_DISABLE_4       0x00001000
+#define MPU_SUB_RGN_DISABLE_5       0x00002000
+#define MPU_SUB_RGN_DISABLE_6       0x00004000
+#define MPU_SUB_RGN_DISABLE_7       0x00008000
+
+//*****************************************************************************
+//
+// Flags to enable or disable a region, to be passed to MPU_setRegion.
+//
+//*****************************************************************************
+#define MPU_RGN_ENABLE              1
+#define MPU_RGN_DISABLE             0
+
+#define NVIC_MPU_TYPE_DREGION_S     8
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! Enables and configures the MPU for use.
+//!
+//! \param mpuConfig is the logical OR of the possible configurations.
+//!
+//! This function enables the Cortex-M memory protection unit.  It also
+//! configures the default behavior when in privileged mode and while handling
+//! a hard fault or NMI.  Prior to enabling the MPU, at least one region must
+//! be set by calling MPU_setRegion() or else by enabling the default region for
+//! privileged mode by passing the \b MPU_CONFIG_PRIV_DEFAULT flag to
+//! MPU_enableModule().  Once the MPU is enabled, a memory management fault is
+//! generated for memory access violations.
+//!
+//! The \e mpuConfig parameter should be the logical OR of any of the
+//! following:
+//!
+//! - \b MPU_CONFIG_PRIV_DEFAULT enables the default memory map when in
+//! privileged mode and when no other regions are defined.  If this option
+//! is not enabled, then there must be at least one valid region already
+//! defined when the MPU is enabled.
+//! - \b MPU_CONFIG_HARDFLT_NMI enables the MPU while in a hard fault or NMI
+//! exception handler.  If this option is not enabled, then the MPU is
+//! disabled while in one of these exception handlers and the default
+//! memory map is applied.
+//! - \b MPU_CONFIG_NONE chooses none of the above options.  In this case,
+//! no default memory map is provided in privileged mode, and the MPU is
+//! not enabled in the fault handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void MPU_enableModule(uint32_t mpuConfig);
+
+//*****************************************************************************
+//
+//! Disables the MPU for use.
+//!
+//! This function disables the Cortex-M memory protection unit.  When the
+//! MPU is disabled, the default memory map is used and memory management
+//! faults are not generated.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void MPU_disableModule(void);
+
+//*****************************************************************************
+//
+//! Gets the count of regions supported by the MPU.
+//!
+//! This function is used to get the total number of regions that are supported
+//! by the MPU, including regions that are already programmed.
+//!
+//! \return The number of memory protection regions that are available
+//! for programming using MPU_setRegion().
+//
+//*****************************************************************************
+extern uint32_t MPU_getRegionCount(void);
+
+//*****************************************************************************
+//
+//! Enables a specific region.
+//!
+//! \param region is the region number to enable. Valid values are between
+//!  0 and 7 inclusively.
+//!
+//! This function is used to enable a memory protection region.  The region
+//! should already be configured with the MPU_setRegion() function.  Once
+//! enabled, the memory protection rules of the region are applied and access
+//! violations cause a memory management fault.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void MPU_enableRegion(uint32_t region);
+
+//*****************************************************************************
+//
+//! Disables a specific region.
+//!
+//! \param region is the region number to disable. Valid values are between
+//!  0 and 7 inclusively.
+//!
+//! This function is used to disable a previously enabled memory protection
+//! region.  The region remains configured if it is not overwritten with
+//! another call to MPU_setRegion(), and can be enabled again by calling
+//! MPU_enableRegion().
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void MPU_disableRegion(uint32_t region);
+
+//*****************************************************************************
+//
+//! Sets up the access rules for a specific region.
+//!
+//! \param region is the region number to set up.
+//! \param addr is the base address of the region.  It must be aligned
+//! according to the size of the region specified in flags.
+//! \param flags is a set of flags to define the attributes of the region.
+//!
+//! This function sets up the protection rules for a region.  The region has
+//! a base address and a set of attributes including the size. The base
+//! address parameter, \e addr, must be aligned according to the size, and
+//! the size must be a power of 2.
+//!
+//! \param region is the region number to set. Valid values are between
+//!  0 and 7 inclusively.
+//!
+//! The \e flags parameter is the logical OR of all of the attributes
+//! of the region.  It is a combination of choices for region size,
+//! execute permission, read/write permissions, disabled sub-regions,
+//! and a flag to determine if the region is enabled.
+//!
+//! The size flag determines the size of a region and must be one of the
+//! following:
+//!
+//! - \b MPU_RGN_SIZE_32B
+//! - \b MPU_RGN_SIZE_64B
+//! - \b MPU_RGN_SIZE_128B
+//! - \b MPU_RGN_SIZE_256B
+//! - \b MPU_RGN_SIZE_512B
+//! - \b MPU_RGN_SIZE_1K
+//! - \b MPU_RGN_SIZE_2K
+//! - \b MPU_RGN_SIZE_4K
+//! - \b MPU_RGN_SIZE_8K
+//! - \b MPU_RGN_SIZE_16K
+//! - \b MPU_RGN_SIZE_32K
+//! - \b MPU_RGN_SIZE_64K
+//! - \b MPU_RGN_SIZE_128K
+//! - \b MPU_RGN_SIZE_256K
+//! - \b MPU_RGN_SIZE_512K
+//! - \b MPU_RGN_SIZE_1M
+//! - \b MPU_RGN_SIZE_2M
+//! - \b MPU_RGN_SIZE_4M
+//! - \b MPU_RGN_SIZE_8M
+//! - \b MPU_RGN_SIZE_16M
+//! - \b MPU_RGN_SIZE_32M
+//! - \b MPU_RGN_SIZE_64M
+//! - \b MPU_RGN_SIZE_128M
+//! - \b MPU_RGN_SIZE_256M
+//! - \b MPU_RGN_SIZE_512M
+//! - \b MPU_RGN_SIZE_1G
+//! - \b MPU_RGN_SIZE_2G
+//! - \b MPU_RGN_SIZE_4G
+//!
+//! The execute permission flag must be one of the following:
+//!
+//! - \b MPU_RGN_PERM_EXEC enables the region for execution of code
+//! - \b MPU_RGN_PERM_NOEXEC disables the region for execution of code
+//!
+//! The read/write access permissions are applied separately for the
+//! privileged and user modes.  The read/write access flags must be one
+//! of the following:
+//!
+//! - \b MPU_RGN_PERM_PRV_NO_USR_NO - no access in privileged or user mode
+//! - \b MPU_RGN_PERM_PRV_RW_USR_NO - privileged read/write, user no access
+//! - \b MPU_RGN_PERM_PRV_RW_USR_RO - privileged read/write, user read-only
+//! - \b MPU_RGN_PERM_PRV_RW_USR_RW - privileged read/write, user read/write
+//! - \b MPU_RGN_PERM_PRV_RO_USR_NO - privileged read-only, user no access
+//! - \b MPU_RGN_PERM_PRV_RO_USR_RO - privileged read-only, user read-only
+//!
+//! The region is automatically divided into 8 equally-sized sub-regions by
+//! the MPU.  Sub-regions can only be used in regions of size 256 bytes
+//! or larger.  Any of these 8 sub-regions can be disabled, allowing for
+//! creation of ``holes'' in a region which can be left open, or overlaid
+//! by another region with different attributes.  Any of the 8 sub-regions
+//! can be disabled with a logical OR of any of the following flags:
+//!
+//! - \b MPU_SUB_RGN_DISABLE_0
+//! - \b MPU_SUB_RGN_DISABLE_1
+//! - \b MPU_SUB_RGN_DISABLE_2
+//! - \b MPU_SUB_RGN_DISABLE_3
+//! - \b MPU_SUB_RGN_DISABLE_4
+//! - \b MPU_SUB_RGN_DISABLE_5
+//! - \b MPU_SUB_RGN_DISABLE_6
+//! - \b MPU_SUB_RGN_DISABLE_7
+//!
+//! Finally, the region can be initially enabled or disabled with one of
+//! the following flags:
+//!
+//! - \b MPU_RGN_ENABLE
+//! - \b MPU_RGN_DISABLE
+//!
+//! As an example, to set a region with the following attributes: size of
+//! 32 KB, execution enabled, read-only for both privileged and user, one
+//! sub-region disabled, and initially enabled; the \e flags parameter would
+//! have the following value:
+//!
+//! <code>
+//! (MPU_RGN_SIZE_32K | MPU_RGN_PERM_EXEC | MPU_RGN_PERM_PRV_RO_USR_RO |
+//!  MPU_SUB_RGN_DISABLE_2 | MPU_RGN_ENABLE)
+//! </code>
+//!
+//! \note This function writes to multiple registers and is not protected
+//! from interrupts.  It is possible that an interrupt which accesses a
+//! region may occur while that region is in the process of being changed.
+//! The safest way to handle this is to disable a region before changing it.
+//! Refer to the discussion of this in the API Detailed Description section.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void MPU_setRegion(uint32_t region, uint32_t addr, uint32_t flags);
+
+//*****************************************************************************
+//
+//! Gets the current settings for a specific region.
+//!
+//! \param region is the region number to get. Valid values are between
+//!  0 and 7 inclusively.
+//! \param addr points to storage for the base address of the region.
+//! \param pflags points to the attribute flags for the region.
+//!
+//! This function retrieves the configuration of a specific region.  The
+//! meanings and format of the parameters is the same as that of the
+//! MPU_setRegion() function.
+//!
+//! This function can be used to save the configuration of a region for later
+//! use with the MPU_setRegion() function.  The region's enable state is
+//! preserved in the attributes that are saved.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void MPU_getRegion(uint32_t region, uint32_t *addr, uint32_t *pflags);
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the memory management fault.
+//!
+//! \param intHandler is a pointer to the function to be called when the
+//! memory management fault occurs.
+//!
+//! This function sets and enables the handler to be called when the MPU
+//! generates a memory management fault due to a protection region access
+//! violation.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void MPU_registerInterrupt(void (*intHandler)(void));
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the memory management fault.
+//!
+//! This function disables and clears the handler to be called when a
+//! memory management fault occurs.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void MPU_unregisterInterrupt(void);
+
+//*****************************************************************************
+//
+//! Enables the interrupt for the memory management fault.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void MPU_enableInterrupt(void);
+
+//*****************************************************************************
+//
+//! Disables the interrupt for the memory management fault.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void MPU_disableInterrupt(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif //  __MPU_H__
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pcm.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pcm.c
new file mode 100644
index 000000000..f3c92f5e0
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pcm.c
@@ -0,0 +1,525 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+/* Standard Includes */
+#include <stdint.h>
+
+/* DriverLib Includes */
+#include <pcm.h>
+#include <debug.h>
+#include <interrupt.h>
+#include <cpu.h>
+
+bool PCM_setCoreVoltageLevel(uint_fast8_t voltageLevel)
+{
+    return PCM_setCoreVoltageLevelWithTimeout(voltageLevel, 0);
+}
+
+bool PCM_setCoreVoltageLevelWithTimeout(uint_fast8_t voltageLevel,
+        uint32_t timeOut)
+{
+    uint8_t powerMode, bCurrentVoltageLevel;
+    uint32_t regValue;
+    bool boolTimeout;
+
+    ASSERT(voltageLevel == PCM_VCORE0 || voltageLevel == PCM_VCORE1);
+
+    /* Getting current power mode and level */
+    powerMode = PCM_getPowerMode();
+    bCurrentVoltageLevel = PCM_getCoreVoltageLevel();
+
+    boolTimeout = timeOut > 0 ? true : false;
+
+    /* If we are already at the power mode they requested, return */
+    if (bCurrentVoltageLevel == voltageLevel)
+        return true;
+
+    while (bCurrentVoltageLevel != voltageLevel)
+    {
+        regValue = PCM->rCTL0.r;
+
+        switch (PCM_getPowerState())
+        {
+        case PCM_AM_LF_VCORE1:
+        case PCM_AM_DCDC_VCORE1:
+        case PCM_AM_LDO_VCORE0:
+            PCM->rCTL0.r = (PCM_KEY | (PCM_AM_LDO_VCORE1)
+                    | (regValue & ~(PCMKEY_M | AMR_M)));
+            break;
+        case PCM_AM_LF_VCORE0:
+        case PCM_AM_DCDC_VCORE0:
+        case PCM_AM_LDO_VCORE1:
+            PCM->rCTL0.r = (PCM_KEY | (PCM_AM_LDO_VCORE0)
+                    | (regValue & ~(PCMKEY_M | AMR_M)));
+            break;
+        default:
+            ASSERT(false);
+        }
+
+        while (BITBAND_PERI(PCM->rCTL1.r, PMR_BUSY_OFS))
+        {
+            if (boolTimeout && !(--timeOut))
+                return false;
+
+        }
+
+        bCurrentVoltageLevel = PCM_getCoreVoltageLevel();
+    }
+
+    /* Changing the power mode if we are stuck in LDO mode */
+    if (powerMode != PCM_getPowerMode())
+    {
+        if (powerMode == PCM_DCDC_MODE)
+            return PCM_setPowerMode(PCM_DCDC_MODE);
+        else
+            return PCM_setPowerMode(PCM_LF_MODE);
+    }
+
+    return true;
+
+}
+
+bool PCM_setPowerMode(uint_fast8_t powerMode)
+{
+    return PCM_setPowerModeWithTimeout(powerMode, 0);
+}
+
+uint8_t PCM_getPowerMode(void)
+{
+    uint8_t currentPowerState;
+
+    currentPowerState = PCM_getPowerState();
+
+    switch (currentPowerState)
+    {
+    case PCM_AM_LDO_VCORE0:
+    case PCM_AM_LDO_VCORE1:
+    case PCM_LPM0_LDO_VCORE0:
+    case PCM_LPM0_LDO_VCORE1:
+        return PCM_LDO_MODE;
+    case PCM_AM_DCDC_VCORE0:
+    case PCM_AM_DCDC_VCORE1:
+    case PCM_LPM0_DCDC_VCORE0:
+    case PCM_LPM0_DCDC_VCORE1:
+        return PCM_DCDC_MODE;
+    case PCM_LPM0_LF_VCORE0:
+    case PCM_LPM0_LF_VCORE1:
+    case PCM_AM_LF_VCORE1:
+    case PCM_AM_LF_VCORE0:
+        return PCM_LF_MODE;
+    default:
+        ASSERT(false);
+        return false;
+
+    }
+}
+
+uint8_t PCM_getCoreVoltageLevel(void)
+{
+    uint8_t currentPowerState = PCM_getPowerState();
+
+    switch (currentPowerState)
+    {
+    case PCM_AM_LDO_VCORE0:
+    case PCM_AM_DCDC_VCORE0:
+    case PCM_AM_LF_VCORE0:
+    case PCM_LPM0_LDO_VCORE0:
+    case PCM_LPM0_DCDC_VCORE0:
+    case PCM_LPM0_LF_VCORE0:
+        return PCM_VCORE0;
+    case PCM_AM_LDO_VCORE1:
+    case PCM_AM_DCDC_VCORE1:
+    case PCM_AM_LF_VCORE1:
+    case PCM_LPM0_LDO_VCORE1:
+    case PCM_LPM0_DCDC_VCORE1:
+    case PCM_LPM0_LF_VCORE1:
+        return PCM_VCORE1;
+    case PCM_LPM3:
+        return PCM_VCORELPM3;
+    default:
+        ASSERT(false);
+        return false;
+
+    }
+}
+
+bool PCM_setPowerModeWithTimeout(uint_fast8_t powerMode, uint32_t timeOut)
+{
+    uint8_t bCurrentPowerMode, bCurrentPowerState;
+    uint32_t regValue;
+    bool boolTimeout;
+
+    ASSERT(
+            powerMode == PCM_LDO_MODE || powerMode == PCM_DCDC_MODE
+            || powerMode == PCM_LF_MODE);
+
+    /* Getting Current Power Mode */
+    bCurrentPowerMode = PCM_getPowerMode();
+
+    /* If the power mode being set it the same as the current mode, return */
+    if (powerMode == bCurrentPowerMode)
+        return true;
+
+    bCurrentPowerState = PCM_getPowerState();
+
+    boolTimeout = timeOut > 0 ? true : false;
+
+    /* Go through the while loop while we haven't achieved the power mode */
+    while (bCurrentPowerMode != powerMode)
+    {
+        regValue = PCM->rCTL0.r;
+
+        switch (bCurrentPowerState)
+        {
+        case PCM_AM_DCDC_VCORE0:
+        case PCM_AM_LF_VCORE0:
+            PCM->rCTL0.r = (PCM_KEY | PCM_AM_LDO_VCORE0
+                    | (regValue & ~(PCMKEY_M | AMR_M)));
+            break;
+        case PCM_AM_LF_VCORE1:
+        case PCM_AM_DCDC_VCORE1:
+            PCM->rCTL0.r = (PCM_KEY | PCM_AM_LDO_VCORE1
+                    | (regValue & ~(PCMKEY_M | AMR_M)));
+            break;
+        case PCM_AM_LDO_VCORE1:
+        {
+            if (powerMode == PCM_DCDC_MODE)
+            {
+                PCM->rCTL0.r = (PCM_KEY | PCM_AM_DCDC_VCORE1
+                        | (regValue & ~(PCMKEY_M | AMR_M)));
+            } else if (powerMode == PCM_LF_MODE)
+            {
+                PCM->rCTL0.r = (PCM_KEY | PCM_AM_LF_VCORE1
+                        | (regValue & ~(PCMKEY_M | AMR_M)));
+            } else
+                ASSERT(false);
+
+            break;
+        }
+        case PCM_AM_LDO_VCORE0:
+        {
+            if (powerMode == PCM_DCDC_MODE)
+            {
+                PCM->rCTL0.r = (PCM_KEY | PCM_AM_DCDC_VCORE0
+                        | (regValue & ~(PCMKEY_M | AMR_M)));
+            } else if (powerMode == PCM_LF_MODE)
+            {
+                PCM->rCTL0.r = (PCM_KEY | PCM_AM_LF_VCORE0
+                        | (regValue & ~(PCMKEY_M | AMR_M)));
+            } else
+                ASSERT(false);
+
+            break;
+        }
+        default:
+            ASSERT(false);
+        }
+
+        while (BITBAND_PERI(PCM->rCTL1.r, PMR_BUSY_OFS))
+        {
+            if (boolTimeout && !(--timeOut))
+                return false;
+
+        }
+
+        bCurrentPowerMode = PCM_getPowerMode();
+        bCurrentPowerState = PCM_getPowerState();
+    }
+
+    return true;
+
+}
+
+bool PCM_setPowerState(uint_fast8_t powerState)
+{
+    return PCM_setPowerStateWithTimeout(powerState, 0);
+}
+
+bool PCM_setPowerStateWithTimeout(uint_fast8_t powerState, uint32_t timeout)
+{
+    uint8_t bCurrentPowerState;
+    bCurrentPowerState = PCM_getPowerState();
+
+    ASSERT(
+            powerState == PCM_AM_LDO_VCORE0 || powerState == PCM_AM_LDO_VCORE1
+            || powerState == PCM_AM_DCDC_VCORE0 || powerState == PCM_AM_DCDC_VCORE1
+            || powerState == PCM_AM_LF_VCORE0 || powerState == PCM_AM_LF_VCORE1
+            || powerState == PCM_LPM0_LDO_VCORE0 || powerState == PCM_LPM0_LDO_VCORE1
+            || powerState == PCM_LPM0_DCDC_VCORE0 || powerState == PCM_LPM0_DCDC_VCORE1
+            || powerState == PCM_LPM3 || powerState == PCM_LPM35_VCORE0
+            || powerState == PCM_LPM45);
+
+    if (bCurrentPowerState == powerState)
+        return true;
+
+    switch (powerState)
+    {
+    case PCM_AM_LDO_VCORE0:
+        return (PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE0, timeout)
+                && PCM_setPowerModeWithTimeout(PCM_LDO_MODE, timeout));
+    case PCM_AM_LDO_VCORE1:
+        return (PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE1, timeout)
+                && PCM_setPowerModeWithTimeout(PCM_LDO_MODE, timeout));
+    case PCM_AM_DCDC_VCORE0:
+        return (PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE0, timeout)
+                && PCM_setPowerModeWithTimeout(PCM_DCDC_MODE, timeout));
+    case PCM_AM_DCDC_VCORE1:
+        return (PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE1, timeout)
+                && PCM_setPowerModeWithTimeout(PCM_DCDC_MODE, timeout));
+    case PCM_AM_LF_VCORE0:
+        return (PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE0, timeout)
+                && PCM_setPowerModeWithTimeout(PCM_LF_MODE, timeout));
+    case PCM_AM_LF_VCORE1:
+        return (PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE1, timeout)
+                && PCM_setPowerModeWithTimeout(PCM_LF_MODE, timeout));
+    case PCM_LPM0_LDO_VCORE0:
+        if (!PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE0, timeout)
+                || !PCM_setPowerModeWithTimeout(PCM_LDO_MODE, timeout))
+            break;
+        return PCM_gotoLPM0();
+    case PCM_LPM0_LDO_VCORE1:
+        if (!PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE1, timeout)
+                || !PCM_setPowerModeWithTimeout(PCM_LDO_MODE, timeout))
+            break;
+        return PCM_gotoLPM0();
+    case PCM_LPM0_DCDC_VCORE0:
+        if (!PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE0, timeout)
+                || !PCM_setPowerModeWithTimeout(PCM_DCDC_MODE, timeout))
+            break;
+        return PCM_gotoLPM0();
+    case PCM_LPM0_DCDC_VCORE1:
+        if (!PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE1, timeout)
+                || !PCM_setPowerModeWithTimeout(PCM_DCDC_MODE, timeout))
+            break;
+        return PCM_gotoLPM0();
+    case PCM_LPM0_LF_VCORE0:
+        if (!PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE0, timeout)
+                || !PCM_setPowerModeWithTimeout(PCM_LF_MODE, timeout))
+            break;
+        return PCM_gotoLPM0();
+    case PCM_LPM0_LF_VCORE1:
+        if (!PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE1, timeout)
+                || !PCM_setPowerModeWithTimeout(PCM_LF_MODE, timeout))
+            break;
+        return PCM_gotoLPM0();
+    case PCM_LPM3:
+        return PCM_gotoLPM3();
+    case PCM_LPM45:
+        return PCM_shutdownDevice(PCM_LPM45);
+    case PCM_LPM35_VCORE0:
+        return PCM_shutdownDevice(PCM_LPM35_VCORE0);
+    default:
+        ASSERT(false);
+        return false;
+    }
+
+    return false;
+
+}
+
+bool PCM_shutdownDevice(uint32_t shutdownMode)
+{
+    uint32_t shutdownModeBits = (shutdownMode == PCM_LPM45) ? LPMR_12 : LPMR_10;
+
+    ASSERT(
+            shutdownMode == PCM_SHUTDOWN_PARTIAL
+            || shutdownMode == PCM_SHUTDOWN_COMPLETE);
+
+    /* If a power transition is occuring, return false */
+    if (BITBAND_PERI(PCM->rCTL1.r, PMR_BUSY_OFS))
+        return false;
+
+    /* Initiating the shutdown */
+    HWREG32(SCS_BASE + OFS_SCB_SCR) |= (SCB_SCR_SLEEPDEEP);
+    PCM->rCTL0.r = (PCM_KEY | shutdownModeBits
+            | (PCM->rCTL0.r & ~(PCMKEY_M | LPMR_M)));
+
+    CPU_wfi();
+
+    return true;
+}
+
+bool PCM_gotoLPM0(void)
+{
+
+    /* If we are in the middle of a state transition, return false */
+    if (BITBAND_PERI(PCM->rCTL1.r, PMR_BUSY_OFS))
+        return false;
+
+    HWREG32(SCS_BASE + OFS_SCB_SCR) &= ~(SCB_SCR_SLEEPDEEP);
+
+    CPU_wfi();
+
+    return true;
+}
+
+bool PCM_gotoLPM0InterruptSafe(void)
+{
+
+    bool slHappenedCorrect;
+
+    /* Disabling master interrupts. In Cortex M, if an interrupt is enabled but 
+     master interrupts are disabled and a WFI happens the WFI will
+     immediately exit. */
+    Interrupt_disableMaster();
+
+    slHappenedCorrect = PCM_gotoLPM0();
+
+    /* Enabling and Disabling Interrupts very quickly so that the
+     processor catches any pending interrupts */
+    Interrupt_enableMaster();
+    Interrupt_disableMaster();
+
+    return slHappenedCorrect;
+}
+
+bool PCM_gotoLPM3(void)
+{
+    uint_fast8_t bCurrentPowerState;
+    uint_fast8_t currentPowerMode;
+
+    /* If we are in the middle of a state transition, return false */
+    if (BITBAND_PERI(PCM->rCTL1.r, PMR_BUSY_OFS))
+        return false;
+
+    /* If we are in the middle of a shutdown, return false */
+    if ((PCM->rCTL0.r & LPMR_M) == LPMR_10 || (PCM->rCTL0.r & LPMR_M) == LPMR_12)
+        return false;
+
+    currentPowerMode = PCM_getPowerMode();
+    bCurrentPowerState = PCM_getPowerState();
+
+    if (currentPowerMode == PCM_DCDC_MODE || currentPowerMode == PCM_LF_MODE)
+        PCM_setPowerMode(PCM_LDO_MODE);
+
+    /* Clearing the SDR */
+    PCM->rCTL0.r = (PCM->rCTL0.r & ~(PCMKEY_M | LPMR_M)) | PCM_KEY;
+
+    /* Setting the sleep deep bit */
+    HWREG32(SCS_BASE + OFS_SCB_SCR) |= (SCB_SCR_SLEEPDEEP);
+
+    CPU_wfi();
+
+    HWREG32(SCS_BASE + OFS_SCB_SCR) &= ~(SCB_SCR_SLEEPDEEP);
+
+    return PCM_setPowerState(bCurrentPowerState);
+}
+
+bool PCM_gotoLPM3InterruptSafe(void)
+{
+    bool dslHappenedCorrect;
+
+    /* Disabling master interrupts. In Cortex M, if an interrupt is enabled but 
+     master interrupts are disabled and a WFI happens the WFI will
+     immediately exit. */
+    Interrupt_disableMaster();
+
+    dslHappenedCorrect = PCM_gotoLPM3();
+
+    /* Enabling and Disabling Interrupts very quickly so that the
+     processor catches any pending interrupts */
+    Interrupt_enableMaster();
+    Interrupt_disableMaster();
+
+    return dslHappenedCorrect;
+}
+
+uint8_t PCM_getPowerState(void)
+{
+    return PCM->rCTL0.b.bCPM;
+}
+
+void PCM_enableRudeMode(void)
+{
+
+    PCM->rCTL1.r = (PCM->rCTL1.r & ~(PCMKEY_M)) | PCM_KEY | FORCE_LPM_ENTRY;
+}
+
+void PCM_disableRudeMode(void)
+{
+    PCM->rCTL1.r = (PCM->rCTL1.r & ~(PCMKEY_M | FORCE_LPM_ENTRY)) | PCM_KEY;
+}
+
+void PCM_enableInterrupt(uint32_t flags)
+{
+    PCM->rIE.r |= flags;
+}
+
+void PCM_disableInterrupt(uint32_t flags)
+{
+    PCM->rIE.r &= ~flags;
+}
+
+uint32_t PCM_getInterruptStatus(void)
+{
+    return PCM->rIFG.r;
+}
+
+uint32_t PCM_getEnabledInterruptStatus(void)
+{
+    return PCM_getInterruptStatus() & PCM->rIE.r;
+}
+
+void PCM_clearInterruptFlag(uint32_t flags)
+{
+    PCM->rCLRIFG.r |= flags;
+}
+
+void PCM_registerInterrupt(void (*intHandler)(void))
+{
+    //
+    // Register the interrupt handler, returning an error if an error occurs.
+    //
+    Interrupt_registerInterrupt(INT_PCM, intHandler);
+
+    //
+    // Enable the system control interrupt.
+    //
+    Interrupt_enableInterrupt(INT_PCM);
+}
+
+void PCM_unregisterInterrupt(void)
+{
+    //
+    // Disable the interrupt.
+    //
+    Interrupt_disableInterrupt(INT_PCM);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    Interrupt_unregisterInterrupt(INT_PCM);
+}
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pcm.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pcm.h
new file mode 100644
index 000000000..64bc9d534
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pcm.h
@@ -0,0 +1,595 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __PCM_H__
+#define __PCM_H__
+
+//*****************************************************************************
+//
+//! \addtogroup pcm_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <msp.h>
+
+//*****************************************************************************
+//
+// Control specific variables 
+//
+//*****************************************************************************
+#define PCM_KEY 0x695A0000
+
+/* Power Modes */
+#define PCM_AM_LDO_VCORE0      0x00
+#define PCM_AM_LDO_VCORE1      0x01
+#define PCM_AM_DCDC_VCORE0     0x04
+#define PCM_AM_DCDC_VCORE1     0x05
+#define PCM_AM_LF_VCORE0      0x08
+#define PCM_AM_LF_VCORE1      0x09
+#define PCM_LPM0_LDO_VCORE0    0x10
+#define PCM_LPM0_LDO_VCORE1    0x11
+#define PCM_LPM0_DCDC_VCORE0   0x14
+#define PCM_LPM0_DCDC_VCORE1   0x15
+#define PCM_LPM0_LF_VCORE0    0x18
+#define PCM_LPM0_LF_VCORE1    0x19
+#define PCM_LPM3               0x20
+#define PCM_LPM35_VCORE0       0xC0
+#define PCM_LPM45              0xA0
+
+#define PCM_VCORE0     0x00
+#define PCM_VCORE1     0x01
+#define PCM_VCORELPM3   0x02
+
+#define PCM_LDO_MODE   0x00
+#define PCM_DCDC_MODE  0x01
+#define PCM_LF_MODE   0x02
+
+#define PCM_SHUTDOWN_PARTIAL PCM_LPM35_VCORE0
+#define PCM_SHUTDOWN_COMPLETE PCM_LPM45
+
+#define PCM_DCDCERROR   PCM_INTEN_EN_DCDC_ERROR
+#define PCM_AM_INVALIDTRANSITION  PCM_INTEN_EN_AM_INVALID_TR
+#define PCM_SM_INVALIDCLOCK PCM_INTEN_EN_SM_INVALID_CLK
+#define PCM_SM_INVALIDTRANSITION    PCM_INTEN_EN_SM_INVALID_TR
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+
+//******************************************************************************
+//
+//! Sets the core voltage level (Vcore). The function will take care of all
+//! power state transitions needed to shift between core voltage levels.
+//! Because transitions between voltage levels may require changes power modes,
+//! the power mode might temporarily be change. The power mode will be returned
+//! to the original state (with the new voltage level) at the end of a
+//! successful execution of this function.
+//!
+//! Refer to the device specific data sheet for specifics about core voltage
+//! levels.
+//!
+//! \param voltageLevel The voltage level to be shifted to.
+//!           - \b PCM_VCORE0,
+//!           - \b PCM_VCORE1
+//!
+//! \return true if voltage level set, false otherwise.
+//
+//******************************************************************************
+extern bool PCM_setCoreVoltageLevel(uint_fast8_t voltageLevel);
+
+//******************************************************************************
+//
+//! Returns the current powers state of the system see the
+//! PCM_setCoreVoltageLevel function for specific information about the modes.
+//!
+//! \return The current voltage of the system
+//!
+//! Possible return values include:
+//!     - \b PCM_VCORE0
+//!     - \b PCM_VCORE1
+//!     - \b PCM_VCORELPM3
+//!
+//
+//******************************************************************************
+extern uint8_t PCM_getCoreVoltageLevel(void);
+
+//******************************************************************************
+//
+//! Sets the core voltage level (Vcore). This function will take care of all
+//! power state transitions needed to shift between core voltage levels.
+//! Because transitions between voltage levels may require changes power modes,
+//! the power mode might temporarily be change. The power mode will be returned
+//! to the original state (with the new voltage level) at the end of a
+//! successful execution of this function.
+//!
+//! This function is similar to PCMSetCoreVoltageLevel, however a timeout
+//! mechanism is used.
+//!
+//! Refer to the device specific data sheet for specifics about core voltage
+//! levels.
+//!
+//! \param voltageLevel The voltage level to be shifted to.
+//!           - \b PCM_VCORE0,
+//!           - \b PCM_VCORE1
+//!
+//! \param timeOut Number of loop iterations to timeout when checking for
+//!         power state transitions. This should be used for debugging initial
+//!         power/hardware configurations. After a stable hardware base is
+//!         established, the PCMSetCoreVoltageLevel function should be used
+//!
+//! \return true if voltage level set, false otherwise.
+//
+//******************************************************************************
+extern bool PCM_setCoreVoltageLevelWithTimeout(uint_fast8_t voltageLevel,
+        uint32_t timeOut);
+
+//******************************************************************************
+//
+//! Switches between power modes. This function will take care of all
+//! power state transitions needed to shift between power modes. Note for
+//! changing to DCDC mode, specific hardware considerations are required.
+//!
+//! Refer to the device specific data sheet for specifics about power modes.
+//!
+//! \param powerMode The voltage modes to be shifted to. Valid values are:
+//!           - \b PCM_LDO_MODE,
+//!           - \b PCM_DCDC_MODE,
+//!           - \b PCM_LF_MODE
+//!
+//! \return true if power mode is set, false otherwise.
+//
+//******************************************************************************
+extern bool PCM_setPowerMode(uint_fast8_t powerMode);
+
+//******************************************************************************
+//
+//! Switches between power modes. This function will take care of all
+//! power state transitions needed to shift between power modes. Note for
+//! changing to DCDC mode, specific hardware considerations are required.
+//!
+//! This function is similar to PCMSetPowerMode, however a timeout
+//! mechanism is used.
+//!
+//! Refer to the device specific data sheet for specifics about power modes.
+//!
+//! \param powerMode The voltage modes to be shifted to. Valid values are:
+//!           - \b PCM_LDO_MODE,
+//!           - \b PCM_DCDC_MODE,
+//!           - \b PCM_LF_MODE
+//!
+//! \param timeOut Number of loop iterations to timeout when checking for
+//!         power state transitions. This should be used for debugging initial
+//!         power/hardware configurations. After a stable hardware base is
+//!         established, the PCMSetPowerMode function should be used
+//!
+//! \return true if power mode is set, false otherwise.
+//
+//******************************************************************************
+extern bool PCM_setPowerModeWithTimeout(uint_fast8_t powerMode,
+        uint32_t timeOut);
+
+//******************************************************************************
+//
+//! Returns the current powers state of the system see the \b PCM_setPowerState
+//! function for specific information about the modes.
+//!
+//! \return The current power mode of the system
+//!
+//
+//******************************************************************************
+extern uint8_t PCM_getPowerMode(void);
+
+//******************************************************************************
+//
+//! Switches between power states. This is a convenience function that combines
+//! the functionality of PCMSetPowerMode and PCMSetCoreVoltageLevel as well as
+//! the sleep/LPM3/shutdown functions.
+//!
+//! Refer to the device specific data sheet for specifics about power states.
+//!
+//! \param powerState The voltage modes to be shifted to. Valid values are:
+//!           - \b PCM_AM_LDO_VCORE0,      [Active Mode, LDO, VCORE0]
+//!           - \b PCM_AM_LDO_VCORE1,      [Active Mode, LDO, VCORE1]
+//!           - \b PCM_AM_DCDC_VCORE0,     [Active Mode, DCDC, VCORE0]
+//!           - \b PCM_AM_DCDC_VCORE1,     [Active Mode, DCDC, VCORE1]
+//!           - \b PCM_AM_LF_VCORE0,       [Active Mode, Low Frequency, VCORE0]
+//!           - \b PCM_AM_LF_VCORE1,       [Active Mode, Low Frequency, VCORE1]
+//!           - \b PCM_LPM0_LDO_VCORE0,    [LMP0, LDO, VCORE0]
+//!           - \b PCM_LPM0_LDO_VCORE1,    [LMP0, LDO, VCORE1]
+//!           - \b PCM_LPM0_DCDC_VCORE0,   [LMP0, DCDC, VCORE0]
+//!           - \b PCM_LPM0_DCDC_VCORE1,   [LMP0, DCDC, VCORE1]
+//!           - \b PCM_LPM0_LF_VCORE0,     [LMP0, Low Frequency, VCORE0]
+//!           - \b PCM_LPM0_LF_VCORE1,     [LMP0, Low Frequency, VCORE1]
+//!           - \b PCM_LPM3,               [LPM3]
+//!           - \b PCM_LPM35_VCORE0,       [LPM3.5 VCORE 0]
+//!           - \b PCM_LPM45,              [LPM4.5]
+//!
+//! \return true if power state is set, false otherwise.
+//
+//******************************************************************************
+extern bool PCM_setPowerState(uint_fast8_t powerState);
+
+//******************************************************************************
+//
+//! Switches between power states. This is a convenience function that combines
+//! the functionality of PCMSetPowerMode and PCMSetCoreVoltageLevel as well as
+//! the LPM modes.
+//!
+//! This function is similar to PCMChangePowerState, however a timeout
+//! mechanism is used.
+//!
+//! Refer to the device specific data sheet for specifics about power states.
+//!
+//! \param powerState The voltage modes to be shifted to. Valid values are:
+//!           - \b PCM_AM_LDO_VCORE0,      [Active Mode, LDO, VCORE0]
+//!           - \b PCM_AM_LDO_VCORE1,      [Active Mode, LDO, VCORE1]
+//!           - \b PCM_AM_DCDC_VCORE0,     [Active Mode, DCDC, VCORE0]
+//!           - \b PCM_AM_DCDC_VCORE1,     [Active Mode, DCDC, VCORE1]
+//!           - \b PCM_AM_LF_VCORE0,       [Active Mode, Low Frequency, VCORE0]
+//!           - \b PCM_AM_LF_VCORE1,       [Active Mode, Low Frequency, VCORE1]
+//!           - \b PCM_LPM0_LDO_VCORE0,    [LMP0, LDO, VCORE0]
+//!           - \b PCM_LPM0_LDO_VCORE1,    [LMP0, LDO, VCORE1]
+//!           - \b PCM_LPM0_DCDC_VCORE0,   [LMP0, DCDC, VCORE0]
+//!           - \b PCM_LPM0_DCDC_VCORE1,   [LMP0, DCDC, VCORE1]
+//!           - \b PCM_LPM0_LF_VCORE0,     [LMP0, Low Frequency, VCORE0]
+//!           - \b PCM_LPM0_LF_VCORE1,     [LMP0, Low Frequency, VCORE1]
+//!           - \b PCM_LPM3,               [LPM3]
+//!           - \b PCM_LPM35_VCORE0,       [LPM3.5 VCORE 0]
+//!           - \b PCM_LPM45,              [LPM4.5]
+//!
+//! \param timeout Number of loop iterations to timeout when checking for
+//!         power state transitions. This should be used for debugging initial
+//!         power/hardware configurations. After a stable hardware base is
+//!         established, the PCMSetPowerMode function should be used
+//!
+//! \return true if power state is set, false otherwise. It is important to
+//!         note that if a timeout occurs, false will be returned, however the
+//!         power state at this point is not guaranteed to be the same as the
+//!         state prior to the function call
+//
+//******************************************************************************
+extern bool PCM_setPowerStateWithTimeout(uint_fast8_t powerState,
+        uint32_t timeout);
+
+//******************************************************************************
+//
+//! Returns the current powers state of the system see the PCMChangePowerState
+//! function for specific information about the states.
+//!
+//! Refer to \link PCM_setPowerState \endlink for possible return values.
+//!
+//! \return The current power state of the system
+//
+//******************************************************************************
+extern uint8_t PCM_getPowerState(void);
+
+//******************************************************************************
+//
+//! Transitions the device into LPM3.5/LPM4.5 mode.
+//!
+//! Refer to the device specific data sheet for specifics about shutdown modes.
+//!
+//! The following events will cause a wake up from LPM3.5 mode:
+//! - Device reset
+//! - External reset RST
+//! - Enabled RTC, WDT, and wake-up I/O only interrupt events
+//!
+//! The following events will cause a wake up from the LPM4.5 mode:
+//! - Device reset
+//! - External reset RST
+//! - Wake-up I/O only interrupt events
+//!
+//! \param shutdownMode Specific mode to go to. Valid values are:
+//!            - \b PCM_LPM35_VCORE0
+//!            - \b PCM_LPM45
+//!
+//!
+//! \return false if shutdown state cannot be entered, true otherwise.
+//
+//******************************************************************************
+extern bool PCM_shutdownDevice(uint32_t shutdownMode);
+
+//******************************************************************************
+//
+//! Transitions the device into LPM0.
+//!
+//! Refer to the device specific data sheet for specifics about low power modes.
+//!
+//! \return false if sleep state cannot be entered, true otherwise.
+//
+//******************************************************************************
+extern bool PCM_gotoLPM0(void);
+
+//******************************************************************************
+//
+//! Transitions the device into LPM3
+//!
+//! Refer to the device specific data sheet for specifics about low power modes.
+//! Note that since LPM3 cannot be entered from  a DCDC power modes, the
+//! power mode is first switched to LDO operation (if in DCDC mode), the deep
+//! sleep is entered, and the DCDC mode is restored on wake up.
+//!
+//! \return false if sleep state cannot be entered, true otherwise.
+//
+//******************************************************************************
+extern bool PCM_gotoLPM3(void);
+
+//******************************************************************************
+//
+//! Transitions the device into LPM0 while maintaining a safe
+//! interrupt handling mentality. This function is meant to be used in
+//! situations where the user wants to go to sleep, however does not want
+//! to go to "miss" any interrupts due to the fact that going to DSL is not
+//! an atomic operation. This function will modify the PRIMASK and on exit of
+//! the program the master interrupts will be disabled.
+//!
+//! Refer to the device specific data sheet for specifics about low power modes.
+//!
+//! \return false if sleep state cannot be entered, true otherwise.
+//
+//******************************************************************************
+extern bool PCM_gotoLPM0InterruptSafe(void);
+
+//******************************************************************************
+//
+//! Transitions the device into LPM3 while maintaining a safe
+//! interrupt handling mentality. This function is meant to be used in
+//! situations where the user wants to go to LPM3, however does not want
+//! to go to "miss" any interrupts due to the fact that going to DSL is not
+//! an atomic operation. This function will modify the PRIMASK and on exit of
+//! the program the master interrupts will be disabled.
+//!
+//! Refer to the device specific data sheet for specifics about low power modes.
+//! Note that since LPM3 cannot be entered from  a DCDC power modes, the
+//! power mode is first switched to LDO operation (if in DCDC mode), the deep
+//! sleep is entered, and the DCDC mode is restored on wake up.
+//!
+//! \return false if sleep state cannot be entered, true otherwise.
+//
+//******************************************************************************
+extern bool PCM_gotoLPM3InterruptSafe(void);
+
+//******************************************************************************
+//
+//! Enables "rude mode" entry into LPM3 and shutdown modes. With this mode
+//! enabled, an entry into shutdown or LPM3 will occur even if there are
+//! clock systems active. The system will forcibly  turn off all clock/systems
+//! when going into these modes.
+//!
+//! \return None
+//
+//******************************************************************************
+extern void PCM_enableRudeMode(void);
+
+//******************************************************************************
+//
+//! Disables "rude mode" entry into LPM3 and shutdown modes. With this
+//! mode disabled, an entry into shutdown or LPM3 will wait for any
+//! active clock requests to free up before going into LPM3 or shutdown.
+//!
+//! \return None
+//
+//******************************************************************************
+extern void PCM_disableRudeMode(void);
+
+//*****************************************************************************
+//
+//! Enables individual power control interrupt sources.
+//!
+//! \param flags is a bit mask of the interrupt sources to be enabled.  Must
+//! be a logical OR of:
+//!         - \b PCM_DCDCERROR,
+//!         - \b PCM_AM_INVALIDTRANSITION,
+//!         - \b PCM_SM_INVALIDCLOCK,
+//!         - \b PCM_SM_INVALIDTRANSITION
+//!
+//! This function enables the indicated power control interrupt sources.  Only
+//! the sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! \note The interrupt sources vary based on the part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PCM_enableInterrupt(uint32_t flags);
+
+//*****************************************************************************
+//
+//! Disables individual power control interrupt sources.
+//!
+//! \param flags is a bit mask of the interrupt sources to be enabled.  Must
+//! be a logical OR of:
+//!         - \b PCM_DCDCERROR,
+//!         - \b PCM_AM_INVALIDTRANSITION,
+//!         - \b PCM_SM_INVALIDCLOCK,
+//!         - \b PCM_SM_INVALIDTRANSITION
+//!
+//! This function disables the indicated power control interrupt sources.  Only
+//! the sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! \note The interrupt sources vary based on the part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PCM_disableInterrupt(uint32_t flags);
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \return The current interrupt status, enumerated as a bit field of:
+//!         - \b PCM_DCDCERROR,
+//!         - \b PCM_AM_INVALIDTRANSITION,
+//!         - \b PCM_SM_INVALIDCLOCK,
+//!         - \b PCM_SM_INVALIDTRANSITION
+//!
+//! \note The interrupt sources vary based on the part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//
+//*****************************************************************************
+extern uint32_t PCM_getInterruptStatus(void);
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status masked with the enabled interrupts.
+//! This function is useful to call in ISRs to get a list of pending
+//! interrupts that are actually enabled and could have caused
+//! the ISR.
+//!
+//! \return The current interrupt status, enumerated as a bit field of:
+//!         - \b PCM_DCDCERROR,
+//!         - \b PCM_AM_INVALIDTRANSITION,
+//!         - \b PCM_SM_INVALIDCLOCK,
+//!         - \b PCM_SM_INVALIDTRANSITION
+//!
+//! \note The interrupt sources vary based on the part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//
+//*****************************************************************************
+extern uint32_t PCM_getEnabledInterruptStatus(void);
+
+//*****************************************************************************
+//
+//! Clears power system interrupt sources.
+//!
+//! The specified power system interrupt sources are cleared, so that they no
+//! longer assert.  This function must be called in the interrupt handler to
+//! keep it from being called again immediately upon exit.
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared.  Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \param flags is a bit mask of the interrupt sources to be cleared.  Must
+//! be a logical OR of
+//!         - \b PCM_DCDCERROR,
+//!         - \b PCM_AM_INVALIDTRANSITION,
+//!         - \b PCM_SM_INVALIDCLOCK,
+//!         - \b PCM_SM_INVALIDTRANSITION
+//!
+//! \note The interrupt sources vary based on the part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PCM_clearInterruptFlag(uint32_t flags);
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the power system interrupt.
+//!
+//! \param intHandler is a pointer to the function to be called when the power
+//! system interrupt occurs.
+//!
+//! This function registers the handler to be called when a clock system
+//! interrupt occurs. This function enables the global interrupt in the
+//! interrupt controller; specific PCM  interrupts must be enabled
+//! via PCM_enableInterrupt().  It is the interrupt handler's responsibility to
+//! clear the interrupt source via \link PCM_clearInterruptFlag \endlink .
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PCM_registerInterrupt(void (*intHandler)(void));
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the power system.
+//!
+//! This function unregisters the handler to be called when a power system
+//! interrupt occurs.  This function also masks off the interrupt in the
+//! interrupt controller so that the interrupt handler no longer is called.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PCM_unregisterInterrupt(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif // __PCM_H__
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pmap.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pmap.c
new file mode 100644
index 000000000..98b453045
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pmap.c
@@ -0,0 +1,65 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#include <debug.h>
+#include <pmap.h>
+
+void PMAP_configurePorts(const uint8_t *portMapping, uint8_t pxMAPy,
+        uint8_t numberOfPorts, uint8_t portMapReconfigure)
+{
+	  uint16_t i;
+
+    ASSERT(
+            (portMapReconfigure == PMAP_ENABLE_RECONFIGURATION)
+                    || (portMapReconfigure == PMAP_DISABLE_RECONFIGURATION));
+
+    //Get write-access to port mapping registers:
+    PMAP->rKEYID = PMAP_KEYID_VAL;
+
+    //Enable/Disable reconfiguration during runtime
+    PMAP->rCTL.r = (PMAP->rCTL.r & ~PMAPRECFG) | portMapReconfigure;
+
+    //Configure Port Mapping:
+    
+    for (i = 0; i < numberOfPorts * 8; i++)
+    {
+        HWREG8(PMAP_BASE + i + pxMAPy) = portMapping[i];
+    }
+
+    //Disable write-access to port mapping registers:
+    PMAP->rKEYID = 0;
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pmap.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pmap.h
new file mode 100644
index 000000000..c3f8052df
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pmap.h
@@ -0,0 +1,129 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __PMAP_H__
+#define __PMAP_H__
+
+//*****************************************************************************
+//
+//! \addtogroup pmap_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <msp.h>
+
+//*****************************************************************************
+//
+//The following are values that can be passed to the PMAP_configurePorts() API
+//as the portMapReconfigure parameter.
+//
+//*****************************************************************************
+#define PMAP_ENABLE_RECONFIGURATION     PMAPRECFG
+#define PMAP_DISABLE_RECONFIGURATION    0x00
+
+//*****************************************************************************
+//
+//The following are values that can be passed to the PMAP_configurePorts() API
+//as the portMapReconfigure parameter.
+//
+//*****************************************************************************
+#define P1MAP OFS_P1MAP01
+#define P2MAP OFS_P2MAP01
+#define P3MAP OFS_P3MAP01
+#define P4MAP OFS_P4MAP01
+#define P5MAP OFS_P5MAP01
+#define P6MAP OFS_P6MAP01
+#define P7MAP OFS_P7MAP01
+
+
+//*****************************************************************************
+//
+//Prototypes for the APIs.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! This function configures the MSP432 Port Mapper
+//!
+//! \param portMapping is the pointer to init Data
+//! \param pxMAPy is the Port Mapper to initialize
+//! \param numberOfPorts is the number of Ports to initialize
+//! \param portMapReconfigure is used to enable/disable reconfiguration
+//!             Valid values are
+//!             \b PMAP_ENABLE_RECONFIGURATION
+//!             \b PMAP_DISABLE_RECONFIGURATION [Default value]
+//! Modified registers are \b PMAPKEYID, \b PMAPCTL
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void PMAP_configurePorts(const uint8_t *portMapping, uint8_t pxMAPy,
+        uint8_t numberOfPorts, uint8_t portMapReconfigure);
+
+/* Defines for future devices that might have multiple instances */
+#define PMAP_configurePortsMultipleInstance(a,b,c,d,e) PMAP_configurePorts(b,c,d,e)
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pss.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pss.c
new file mode 100644
index 000000000..249072e31
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pss.c
@@ -0,0 +1,243 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+/* Standard Includes */
+#include <stdint.h>
+
+/* DriverLib Includes */
+#include <pss.h>
+#include <interrupt.h>
+#include <debug.h>
+#include <cpu.h>
+
+static void __PSSUnlock()
+{
+    PSS->rKEY.r = PSS_KEY_VALUE;
+}
+
+static void __PSSLock()
+{
+    PSS->rKEY.r = 0;
+}
+
+void PSS_enableHighSidePinToggle(bool activeLow)
+{
+    __PSSUnlock();
+
+    if (activeLow)
+        PSS->rCTL0.r |= (SVMHOE | SVMHOUTPOLAL);
+    else
+    {
+        BITBAND_PERI(PSS->rCTL0.r, SVMHOUTPOLAL_OFS) = 0;
+        BITBAND_PERI(PSS->rCTL0.r, SVMHOE_OFS) = 1;
+    }
+
+    __PSSLock();
+}
+
+void PSS_disableHighSidePinToggle(void)
+{
+    __PSSUnlock();
+
+    BITBAND_PERI(PSS->rCTL0.r, SVMHOE_OFS) = 0;
+
+    __PSSLock();
+}
+
+void PSS_enableHighSide(void)
+{
+    __PSSUnlock();
+
+    BITBAND_PERI(PSS->rCTL0.r, SVSMHOFF_OFS) = 0;
+
+    __PSSLock();
+}
+
+void PSS_disableHighSide(void)
+{
+    __PSSUnlock();
+
+    BITBAND_PERI(PSS->rCTL0.r, SVSMHOFF_OFS) = 1;
+
+    __PSSLock();
+}
+
+void PSS_setHighSidePerformanceMode(uint_fast8_t powerMode)
+{
+    __PSSUnlock();
+
+    if (powerMode == PSS_FULL_PERFORMANCE_MODE)
+        BITBAND_PERI(PSS->rCTL0.r, SVSMHLP_OFS) = 0;
+    else
+        BITBAND_PERI(PSS->rCTL0.r, SVSMHLP_OFS) = 1;
+
+    __PSSLock();
+}
+
+uint_fast8_t PSS_getHighSidePerformanceMode(void)
+{
+    if (BITBAND_PERI(PSS->rCTL0.r, SVSMHLP_OFS))
+        return PSS_NORMAL_PERFORMANCE_MODE;
+    else
+        return PSS_FULL_PERFORMANCE_MODE;
+}
+
+void PSS_enableHighSideMonitor(void)
+{
+    __PSSUnlock();
+
+    BITBAND_PERI(PSS->rCTL0.r, SVSMHS_OFS) = 1;
+
+    __PSSLock();
+}
+
+void PSS_disableHighSideMonitor(void)
+{
+    __PSSUnlock();
+
+    BITBAND_PERI(PSS->rCTL0.r, SVSMHS_OFS) = 0;
+
+    __PSSLock();
+}
+
+void PSS_setHighSideVoltageTrigger(uint_fast8_t triggerVoltage)
+{
+    __PSSUnlock();
+
+    ASSERT(!(triggerVoltage & 0xF8))
+
+    PSS->rCTL0.b.bSVSMHTH = triggerVoltage & 0x07;
+
+    __PSSLock();
+}
+
+uint_fast8_t PSS_getHighSideVoltageTrigger(void)
+{
+    return PSS->rCTL0.b.bSVSMHTH;
+}
+
+
+void PSS_enableLowSide(void)
+{
+    __PSSUnlock();
+
+    BITBAND_PERI(PSS->rCTL0.r, SVSLOFF_OFS) = 0;
+
+    __PSSLock();
+}
+
+void PSS_disableLowSide(void)
+{
+    __PSSUnlock();
+
+    BITBAND_PERI(PSS->rCTL0.r, SVSLOFF_OFS) = 1;
+
+    __PSSLock();
+}
+
+
+void PSS_setLowSidePerformanceMode(uint_fast8_t ui8PowerMode)
+{
+    __PSSUnlock();
+
+    if (ui8PowerMode == PSS_FULL_PERFORMANCE_MODE)
+        BITBAND_PERI(PSS->rCTL0.r, SVSLLP_OFS) = 0;
+    else
+        BITBAND_PERI(PSS->rCTL0.r, SVSLLP_OFS) = 1;
+
+    __PSSLock();
+}
+
+uint_fast8_t PSS_getLowSidePerformanceMode(void)
+{
+    if (BITBAND_PERI(PSS->rCTL0.r, SVSLLP_OFS))
+        return PSS_NORMAL_PERFORMANCE_MODE;
+    else
+        return PSS_FULL_PERFORMANCE_MODE;
+}
+
+
+void PSS_enableInterrupt(void)
+{
+    __PSSUnlock();
+    BITBAND_PERI(PSS->rIE.r,SVSMHIE_OFS) = 1;
+    __PSSLock();
+}
+
+void PSS_disableInterrupt(void)
+{
+    __PSSUnlock();
+    BITBAND_PERI(PSS->rIE.r,SVSMHIE_OFS) = 0;
+    __PSSLock();
+}
+
+uint32_t PSS_getInterruptStatus(void)
+{
+    return PSS->rIFG.r;
+}
+
+void PSS_clearInterruptFlag(void)
+{
+    __PSSUnlock();
+    BITBAND_PERI(PSS->rCLRIFG.r,CLRSVSMHIFG_OFS) = 0;
+    __PSSLock();
+}
+
+void PSS_registerInterrupt(void (*intHandler)(void))
+{
+    //
+    // Register the interrupt handler, returning an error if an error occurs.
+    //
+    Interrupt_registerInterrupt(INT_PSS, intHandler);
+
+    //
+    // Enable the system control interrupt.
+    //
+    Interrupt_enableInterrupt(INT_PSS);
+}
+
+void PSS_unregisterInterrupt(void)
+{
+    //
+    // Disable the interrupt.
+    //
+    Interrupt_disableInterrupt(INT_PSS);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    Interrupt_unregisterInterrupt(INT_PSS);
+}
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pss.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pss.h
new file mode 100644
index 000000000..5638f4fe4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pss.h
@@ -0,0 +1,340 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __PSS_H__
+#define __PSS_H__
+
+//*****************************************************************************
+//
+//! \addtogroup pss_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <msp.h>
+#include <stdbool.h>
+
+//*****************************************************************************
+//
+// Control specific variables
+//
+//*****************************************************************************
+#define PSS_KEY_VALUE 0x0000695A
+
+#define PSS_SVSMH SVSMHIE
+
+#define PSS_FULL_PERFORMANCE_MODE   0x01
+#define PSS_NORMAL_PERFORMANCE_MODE 0x00
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! Enables output of the High Side interrupt flag on the device \b SVMHOUT pin
+//!
+//! \param activeLow True if the signal should be logic low when SVSMHIFG
+//!     is set. False if signal should be high when \b SVSMHIFG is set.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PSS_enableHighSidePinToggle(bool activeLow);
+
+//*****************************************************************************
+//
+//! Disables output of the High Side interrupt flag on the device \b SVMHOUT pin
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PSS_disableHighSidePinToggle(void);
+
+//*****************************************************************************
+//
+//! Enables high side voltage supervisor/monitor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PSS_enableHighSide(void);
+
+//*****************************************************************************
+//
+//! Disables high side voltage supervisor/monitor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PSS_disableHighSide(void);
+
+//*****************************************************************************
+//
+//! Sets the performance mode of the high side regulator. Full performance
+//! mode allows for the best response times while normal performance mode is
+//! optimized for the lowest possible current consumption.
+//!
+//! \param powerMode is the performance mode to set. Valid values are one of
+//! the following:
+//!     - \b PSS_FULL_PERFORMANCE_MODE,
+//!     - \b PSS_NORMAL_PERFORMANCE_MODE
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PSS_setHighSidePerformanceMode(uint_fast8_t powerMode);
+
+//*****************************************************************************
+//
+//! Gets the performance mode of the high side voltage regulator. Refer to the
+//! user's guide for specific information about information about the different
+//! performance modes.
+//!
+//! \return Performance mode of the voltage regulator
+//
+//*****************************************************************************
+extern uint_fast8_t PSS_getHighSidePerformanceMode(void);
+
+//*****************************************************************************
+//
+//! Sets the high side voltage supervisor to monitor mode
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PSS_enableHighSideMonitor(void);
+
+//*****************************************************************************
+//
+//! Switches the high side of the power supply system to be a supervisor instead
+//! of a monitor
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PSS_disableHighSideMonitor(void);
+
+//*****************************************************************************
+//
+//! Sets the voltage level at which the high side of the device voltage
+//! regulator triggers a reset. This value is represented as an unsigned eight
+//! bit integer where only the lowest three bits are most significant.
+//!
+//! \param triggerVoltage Voltage level in which high side supervisor/monitor
+//!         triggers a reset. See the device specific data sheet for details
+//!         on these voltage levels.
+//!
+//! Typical values will vary from part to part (so it is very important to
+//! check the SVSH section of the data sheet. For reference only, the typical
+//! MSP432 101 values are listed below:
+//!     - 0 --> 1.57V
+//!     - 1 --> 1.62V
+//!     - 2 --> 1.83V
+//!     - 3 --> 2V
+//!     - 4 --> 2.25V
+//!     - 5 --> 2.4V
+//!     - 6 --> 2.6V
+//!     - 7 --> 2.8V
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PSS_setHighSideVoltageTrigger(uint_fast8_t triggerVoltage);
+
+//*****************************************************************************
+//
+//! Returns the voltage level at which the high side of the device voltage
+//! regulator triggers a reset.
+//!
+//! \return The voltage level that the high side voltage supervisor/monitor
+//! triggers a reset. This value is represented as an unsigned eight
+//! bit integer where only the lowest three bits are most significant.
+//! See \link PSS_setHighSideVoltageTrigger \endlink for information regarding
+//! the return value
+//
+//*****************************************************************************
+extern uint_fast8_t PSS_getHighSideVoltageTrigger(void);
+
+//*****************************************************************************
+//
+//! Enables low side voltage supervisor/monitor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PSS_enableLowSide(void);
+
+//*****************************************************************************
+//
+//! Disables low side voltage supervisor/monitor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PSS_disableLowSide(void);
+
+//*****************************************************************************
+//
+//! Sets the performance mode of the high side regulator. Full performance
+//! mode allows for the best response times while normal performance mode is
+//! optimized for the lowest possible current consumption.
+//!
+//! \param ui8PowerMode is the performance mode to set. Valid values are one of
+//! the following:
+//!     - \b PSS_FULL_PERFORMANCE_MODE,
+//!     - \b PSS_NORMAL_PERFORMANCE_MODE
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PSS_setLowSidePerformanceMode(uint_fast8_t ui8PowerMode);
+
+//*****************************************************************************
+//
+//! Gets the performance mode of the low side voltage regulator. Refer to the
+//! user's guide for specific information about information about the different
+//! performance modes.
+//!
+//! \return Performance mode of the voltage regulator
+//
+//*****************************************************************************
+extern uint_fast8_t PSS_getLowSidePerformanceMode(void);
+
+//*****************************************************************************
+//
+//! Enables the power supply system interrupt source.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PSS_enableInterrupt(void);
+
+//*****************************************************************************
+//
+//! Disables the power supply system interrupt source.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PSS_disableInterrupt(void);
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \return The current interrupt status ( \b PSS_SVSMH )
+//!
+//*****************************************************************************
+extern uint32_t PSS_getInterruptStatus(void);
+
+//*****************************************************************************
+//
+//! Clears power supply system interrupt source.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PSS_clearInterruptFlag(void);
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the power supply system interrupt.
+//!
+//! \param intHandler is a pointer to the function to be called when the power
+//! supply system interrupt occurs.
+//!
+//! This function registers the handler to be called when a power supply system
+//! interrupt occurs. This function enables the global interrupt in the
+//! interrupt controller; specific PSS interrupts must be enabled
+//! via PSS_enableInterrupt().  It is the interrupt handler's responsibility to
+//! clear the interrupt source via PSS_clearInterruptFlag().
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PSS_registerInterrupt(void (*intHandler)(void));
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the power supply system
+//!
+//! This function unregisters the handler to be called when a power supply
+//! system interrupt occurs.  This function also masks off the interrupt in the
+//! interrupt controller so that the interrupt handler no longer is called.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PSS_unregisterInterrupt(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif // __PSS_H__
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/ref_a.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/ref_a.c
new file mode 100644
index 000000000..cc3bd0e89
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/ref_a.c
@@ -0,0 +1,116 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#include <ref_a.h>
+#include <debug.h>
+
+void REF_A_setReferenceVoltage(uint_fast8_t referenceVoltageSelect)
+{
+    ASSERT(referenceVoltageSelect <= REF_A_VREF2_5V);
+
+    REF_A->rCTL0.r = (REF_A->rCTL0.r &  ~REFVSEL_3) | referenceVoltageSelect;
+}
+
+void REF_A_disableTempSensor(void)
+{
+    BITBAND_PERI(REF_A->rCTL0.r,REFTCOFF_OFS) = 1;
+}
+
+void REF_A_enableTempSensor(void)
+{
+    BITBAND_PERI(REF_A->rCTL0.r,REFTCOFF_OFS) = 0;
+}
+
+void REF_A_enableReferenceVoltageOutput(void)
+{
+    BITBAND_PERI(REF_A->rCTL0.r,REFOUT_OFS) = 1;
+}
+
+void REF_A_disableReferenceVoltageOutput(void)
+{
+    BITBAND_PERI(REF_A->rCTL0.r,REFOUT_OFS) = 0;
+}
+
+void REF_A_enableReferenceVoltage(void)
+{
+    BITBAND_PERI(REF_A->rCTL0.r,REFON_OFS) = 1;
+}
+
+void REF_A_disableReferenceVoltage(void)
+{
+    BITBAND_PERI(REF_A->rCTL0.r,REFON_OFS) = 0;
+}
+
+uint_fast8_t REF_A_getBandgapMode(void)
+{
+    return (REF_A->rCTL0.r & BGMODE);
+}
+
+bool REF_A_isBandgapActive(void)
+{
+    return BITBAND_PERI(REF_A->rCTL0.r,REFBGACT_OFS);
+}
+
+bool REF_A_isRefGenBusy(void)
+{
+    return BITBAND_PERI(REF_A->rCTL0.r,REFGENBUSY_OFS);
+}
+
+bool REF_A_isRefGenActive(void)
+{
+    return BITBAND_PERI(REF_A->rCTL0.r,REFGENACT_OFS);
+}
+
+bool REF_A_getBufferedBandgapVoltageStatus(void)
+{
+    return BITBAND_PERI(REF_A->rCTL0.r,REFBGRDY_OFS);
+}
+
+bool REF_A_getVariableReferenceVoltageStatus(void)
+{
+    return BITBAND_PERI(REF_A->rCTL0.r,REFGENRDY_OFS);
+}
+
+void REF_A_setReferenceVoltageOneTimeTrigger(void)
+{
+    BITBAND_PERI(REF_A->rCTL0.r,REFGENOT_OFS) = 1;
+}
+
+void REF_A_setBufferedBandgapVoltageOneTimeTrigger(void)
+{
+    BITBAND_PERI(REF_A->rCTL0.r,REFBGOT_OFS) = 1;
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/ref_a.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/ref_a.h
new file mode 100644
index 000000000..e9fe91a0e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/ref_a.h
@@ -0,0 +1,346 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __REF_B_H__
+#define __REF_B_H__
+
+//*****************************************************************************
+//
+//! \addtogroup ref_api
+//! @{
+//
+//*****************************************************************************
+
+#include <msp.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//The following are values that can be passed to Ref_setReferenceVoltage()
+//in the referenceVoltageSelect parameter.
+//
+//*****************************************************************************
+#define REF_A_VREF1_2V  REFVSEL_0
+#define REF_A_VREF1_45V REFVSEL_1
+#define REF_A_VREF2_5V  REFVSEL_3
+
+//*****************************************************************************
+//
+//The following are values that are returned by Ref_getBandgapMode().
+//
+//*****************************************************************************
+#define REF_A_STATICMODE 0x0
+#define REF_A_SAMPLEMODE BGMODE
+
+//*****************************************************************************
+//
+//! Sets the reference voltage for the voltage generator.
+//!
+//! \param referenceVoltageSelect is the desired voltage to generate for a
+//!       reference voltage.
+//!        Valid values are:
+//!        - \b REF_A_VREF1_2V [Default]
+//!        - \b REF_A_VREF1_45V
+//!        - \b REF_A_VREF2_5V
+//!        Modified bits are \b REFVSEL of \b REFCTL0 register.
+//!
+//! This function sets the reference voltage generated by the voltage generator
+//! to be used by other peripherals. This reference voltage will only be valid
+//! while the REF module is in control.
+//! Please note, if the \link REF_A_isRefGenBusy() \endlink returns \b REF_BUSY,
+//! this function  will have no effect.
+//!
+//! \return none
+//
+//*****************************************************************************
+extern void REF_A_setReferenceVoltage(uint_fast8_t referenceVoltageSelect);
+
+//*****************************************************************************
+//
+//! Disables the internal temperature sensor to save power consumption.
+//!
+//! This function is used to turn off the internal temperature sensor to save
+//! on power consumption. The temperature sensor is enabled by default. Please
+//! note, that giving ADC12 module control over the REF module, the state of the
+//! temperature sensor is dependent on the controls of the ADC12 module.
+//! Please note, if the \link REF_A_isRefGenBusy() \endlink  returns
+//! \b REF_A_BUSY, this function will have no effect.
+//!
+//! Modified bits are \b REFTCOFF of \b REFCTL0 register.
+//! \return none
+//
+//*****************************************************************************
+extern void REF_A_disableTempSensor(void);
+
+//*****************************************************************************
+//
+//! Enables the internal temperature sensor.
+//!
+//! This function is used to turn on the internal temperature sensor to use by
+//! other peripherals. The temperature sensor is enabled by default.
+//! Please note, if the \link REF_A_isRefGenBusy() \endlink returns
+//! \b REF_A_BUSY, this function will have no effect.
+//!
+//! Modified bits are \b REFTCOFF of \b REFCTL0 register.
+//!
+//! \return none
+//
+//*****************************************************************************
+extern void REF_A_enableTempSensor(void);
+
+//*****************************************************************************
+//
+//! Outputs the reference voltage to an output pin.
+//!
+//! This function is used to output the reference voltage being generated to an
+//! output pin. Please note, the output pin is device specific. Please note,
+//! that giving ADC12 module control over the REF module, the state of the
+//! reference voltage as an output to a pin is dependent on the controls of the
+//! ADC12 module.
+//! Please note, if the \link REF_A_isRefGenBusy() \endlink returns
+//! \b REF_A_BUSY, this function will have no effect.
+//!
+//! Modified bits are \b REFOUT of \b REFCTL0 register.
+//! \return none
+//
+//*****************************************************************************
+extern void REF_A_enableReferenceVoltageOutput(void);
+
+//*****************************************************************************
+//
+//! Disables the reference voltage as an output to a pin.
+//!
+//! This function is used to disables the reference voltage being generated to
+//! be given to an output pin.
+//! Please note, if the \link REF_A_isRefGenBusy() \endlink returns
+//! \b REF_A_BUSY, this function will have no effect.
+//!
+//! Modified bits are \b REFOUT of \b REFCTL0 register.
+//! \return none
+//
+//*****************************************************************************
+extern void REF_A_disableReferenceVoltageOutput(void);
+
+//*****************************************************************************
+//
+//! Enables the reference voltage to be used by peripherals.
+//!
+//! This function is used to enable the generated reference voltage to be used
+//! other peripherals or by an output pin, if enabled. Please note, that giving
+//! ADC12 module control over the REF module, the state of the reference voltage
+//! is dependent on the controls of the ADC12 module.
+//! Please note, if the \link REF_A_isRefGenBusy() \endlink returns
+//! REF_A_BUSY, this function will have no effect.
+//!
+//! Modified bits are \b REFON of \b REFCTL0 register.
+//! \return none
+//
+//*****************************************************************************
+extern void REF_A_enableReferenceVoltage(void);
+
+//*****************************************************************************
+//
+//! Disables the reference voltage.
+//!
+//! This function is used to disable the generated reference voltage.
+//! Please note, if the \link REF_A_isRefGenBusy() \endlink returns
+//!  \b  REF_A_BUSY, this function will have no effect.
+//!
+//! Modified bits are \b REFON of \b REFCTL0 register.
+//! \return none
+//
+//*****************************************************************************
+extern void REF_A_disableReferenceVoltage(void);
+
+//*****************************************************************************
+//
+//! Returns the bandgap mode of the REF module.
+//!
+//! This function is used to return the bandgap mode of the REF module,
+//! requested by the peripherals using the bandgap. If a peripheral requests
+//! static mode, then the bandgap mode will be static for all modules, whereas
+//! if all of the peripherals using the bandgap request sample mode, then that
+//! will be the mode returned. Sample mode allows the bandgap to be active only
+//! when necessary to save on power consumption, static mode requires the
+//! bandgap to be active until no peripherals are using it anymore.
+//!
+//! \return The bandgap mode of the REF module:
+//!        - \b REF_A_STATICMODE if the bandgap is operating in static mode
+//!        - \b REF_A_SAMPLEMODE if the bandgap is operating in sample mode
+//
+//*****************************************************************************
+extern uint_fast8_t REF_A_getBandgapMode(void);
+
+//*****************************************************************************
+//
+//! Returns the active status of the bandgap in the REF module.
+//!
+//! This function is used to return the active status of the bandgap in the REF
+//! module. If the bandgap is in use by a peripheral, then the status will be
+//! seen as active.
+//!
+//! \return true if the bandgap is being used, false otherwise
+//
+//*****************************************************************************
+extern bool REF_A_isBandgapActive(void);
+
+//*****************************************************************************
+//
+//! Returns the busy status of the reference generator in the REF module.
+//!
+//! This function is used to return the busy status of the reference generator
+//! in the REF module. If the ref. generator is in use by a peripheral, then the
+//! status will be seen as busy.
+//!
+//! \return true if the reference generator is being used, false otherwise.
+//*****************************************************************************
+extern bool REF_A_isRefGenBusy(void);
+
+//*****************************************************************************
+//
+//! Returns the active status of the reference generator in the REF module.
+//!
+//! This function is used to return the active status of the reference generator
+//! in the REF module. If the ref. generator is on and ready to use, then the
+//! status will be seen as active.
+//!
+//! \return true if the reference generator is active, false otherwise.
+//
+//*****************************************************************************
+extern bool REF_A_isRefGenActive(void);
+
+//*****************************************************************************
+//
+//! Returns the busy status of the reference generator in the REF module.
+//!
+//! This function is used to return the buys status of the buffered bandgap
+//! voltage in the REF module. If the ref. generator is on and ready to use,
+//! then the status will be seen as active.
+//!
+//! \return true if the buffered bandgap voltage is ready to be used, false
+//!         otherwise
+//
+//*****************************************************************************
+extern bool REF_A_getBufferedBandgapVoltageStatus(void);
+
+//*****************************************************************************
+//
+//! Returns the busy status of the variable reference voltage in the REF module.
+//!
+//! This function is used to return the buys status of the variable reference
+//! voltage in the REF module. If the ref. generator is on and ready to use,
+//! then the status will be seen as active.
+//!
+//! \return true if the variable bandgap voltage is ready to be used, false
+//!         otherwise
+//
+//*****************************************************************************
+extern bool REF_A_getVariableReferenceVoltageStatus(void);
+
+//*****************************************************************************
+//
+//! Enables the one-time trigger of the reference voltage.
+//!
+//! Triggers the one-time generation of the variable reference voltage.  Once
+//! the reference voltage request is set, this bit is cleared by hardware
+//!
+//! Modified bits are \b REFGENOT of \b REFCTL0 register.
+//!
+//! \return none
+//
+//*****************************************************************************
+extern void REF_A_setReferenceVoltageOneTimeTrigger(void);
+
+//*****************************************************************************
+//
+//! Enables the one-time trigger of the buffered bandgap voltage.
+//!
+//! Triggers the one-time generation of the buffered bandgap voltage.  Once
+//! the buffered bandgap voltage request is set, this bit is cleared by hardware
+//!
+//! Modified bits are \b RefGOT of \b REFCTL0 register.
+//!
+//! \return none
+//
+//*****************************************************************************
+extern void REF_A_setBufferedBandgapVoltageOneTimeTrigger(void);
+
+/* Defines for future devices that might have multiple instances */
+#define REF_A_setReferenceVoltageMultipleInstance(a,b) REF_A_setReferenceVoltage(b)
+#define REF_A_disableTempSensorMultipleInstance(a) REF_A_disableTempSensor()
+#define REF_A_enableTempSensorMultipleInstance(a) REF_A_enableTempSensor()
+#define REF_A_enableReferenceVoltageOutputMultipleInstance(a) REF_A_enableReferenceVoltageOutput()
+#define REF_A_disableReferenceVoltageOutputMultipleInstance(a) REF_A_disableReferenceVoltageOutput()
+#define REF_A_enableReferenceVoltageMultipleInstance(a) REF_A_enableReferenceVoltage()
+#define REF_A_disableReferenceVoltageMultipleInstance(a) REF_A_disableReferenceVoltage()
+#define REF_A_getBandgapModeMultipleInstance(a) REF_A_getBandgapMode()
+#define REF_A_isBandgapActiveMultipleInstance(a) REF_A_isBandgapActive()
+#define REF_A_isRefGenBusyMultipleInstance(a) REF_A_isRefGenBusy()
+#define REF_A_isRefGenActiveMultipleInstance(a) REF_A_isRefGenActive()
+#define REF_A_getBufferedBandgapVoltageStatusMultipleInstance(a) REF_A_getBufferedBandgapVoltageStatus()
+#define REF_A_getVariableReferenceVoltageStatusMultipleInstance(a) REF_A_getVariableReferenceVoltageStatus()
+#define REF_A_setReferenceVoltageOneTimeTriggerMultipleInstance(a) REF_A_setReferenceVoltageOneTimeTrigger()
+#define REF_A_setBufferedBandgapVoltageOneTimeTriggerMultipleInstance(a) REF_A_setBufferedBandgapVoltageOneTimeTrigger()
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif // __REF_A_H__
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/reset.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/reset.c
new file mode 100644
index 000000000..6dbe20b78
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/reset.c
@@ -0,0 +1,99 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#include <reset.h>
+#include <debug.h>
+
+void ResetCtl_initiateSoftReset(void)
+{
+    RSTCTL->rRESET_REQ.r |= (RESET_KEY | RESET_SOFT_RESET);
+}
+
+void ResetCtl_initiateSoftResetWithSource(uint32_t source)
+{
+    RSTCTL->rSOFTRESET_SET.r |= (source);
+}
+
+uint32_t ResetCtl_getSoftResetSource(void)
+{
+    return RSTCTL->rSOFTRESET_STAT.r;
+}
+
+void ResetCtl_clearSoftResetSource(uint32_t mask)
+{
+    RSTCTL->rSOFTRESET_CLR.r |= mask;
+}
+
+void ResetCtl_initiateHardReset(void)
+{
+    RSTCTL->rRESET_REQ.r |= (RESET_KEY | RESET_HARD_RESET);
+}
+
+void ResetCtl_initiateHardResetWithSource(uint32_t source)
+{
+    RSTCTL->rHARDRESET_SET.r |= (source);
+}
+
+uint32_t ResetCtl_getHardResetSource(void)
+{
+    return RSTCTL->rHARDRESET_STAT.r;
+}
+
+void ResetCtl_clearHardResetSource(uint32_t mask)
+{
+    RSTCTL->rHARDRESET_CLR.r |= mask;
+}
+
+uint32_t ResetCtl_getPSSSource(void)
+{
+    return RSTCTL->rPSSRESET_STAT.r;
+}
+
+void ResetCtl_clearPSSFlags(void)
+{
+    RSTCTL->rPSSRESET_CLR.r |= RSTCTL_PSSRESET_CLR_CLR;
+}
+
+uint32_t ResetCtl_getPCMSource(void)
+{
+    return RSTCTL->rPCMRESET_STAT.r;
+}
+
+void ResetCtl_clearPCMFlags(void)
+{
+    RSTCTL->rPCMRESET_CLR.r |= RSTCTL_PCMRESET_CLR_CLR;
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/reset.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/reset.h
new file mode 100644
index 000000000..c8d060c62
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/reset.h
@@ -0,0 +1,345 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __RESET_H__
+#define __RESET_H__
+
+//*****************************************************************************
+//
+//! \addtogroup reset_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <msp.h>
+#include <stdint.h>
+
+//*****************************************************************************
+//
+// Control specific variables 
+//
+//*****************************************************************************
+#define RESET_KEY   0x6900
+#define RESET_HARD_RESET RSTCTL_RESET_REQ_HARD_REQ
+#define RESET_SOFT_RESET RSTCTL_RESET_REQ_SOFT_REQ
+
+#define RESET_SRC_0 RSTCTL_HARDRESET_CLR_SRC0
+#define RESET_SRC_1 RSTCTL_HARDRESET_CLR_SRC1
+#define RESET_SRC_2 RSTCTL_HARDRESET_CLR_SRC2
+#define RESET_SRC_3 RSTCTL_HARDRESET_CLR_SRC3
+#define RESET_SRC_4 RSTCTL_HARDRESET_CLR_SRC4
+#define RESET_SRC_5 RSTCTL_HARDRESET_CLR_SRC5
+#define RESET_SRC_6 RSTCTL_HARDRESET_CLR_SRC6
+#define RESET_SRC_7 RSTCTL_HARDRESET_CLR_SRC7
+#define RESET_SRC_8 RSTCTL_HARDRESET_CLR_SRC8
+#define RESET_SRC_9 RSTCTL_HARDRESET_CLR_SRC9
+#define RESET_SRC_10 RSTCTL_HARDRESET_CLR_SRC10
+#define RESET_SRC_11 RSTCTL_HARDRESET_CLR_SRC11
+#define RESET_SRC_12 RSTCTL_HARDRESET_CLR_SRC12
+#define RESET_SRC_13 RSTCTL_HARDRESET_CLR_SRC13
+#define RESET_SRC_14 RSTCTL_HARDRESET_CLR_SRC14
+#define RESET_SRC_15 RSTCTL_HARDRESET_CLR_SRC15
+
+#define RESET_VCCDET    RSTCTL_PSSRESET_CLR_BGREF
+#define RESET_SVSH_TRIP RSTCTL_PSSRESET_CLR_SVSMH
+#define RESET_SVSL_TRIP RSTCTL_PSSRESET_CLR_SVSL
+#define RESET_BGREF_BAD RSTCTL_PSSRESET_CLR_BGREF
+
+#define RESET_SD0   RSTCTL_PCMRESET_CLR_LPM35
+#define RESET_SD1   RSTCTL_PCMRESET_CLR_LPM45
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! Initiates a soft system reset.
+//!
+//! \return none
+//
+//*****************************************************************************
+extern void ResetCtl_initiateSoftReset(void);
+
+//*****************************************************************************
+//
+//! Initiates a soft system reset with a particular source given. This source
+//! is generic and can be assigned by the user.
+//!
+//! \param source Source of the reset. Valid values are:
+//!             - \b RESET_SRC_0,
+//!             - \b RESET_SRC_1,
+//!             - \b RESET_SRC_2,
+//!             - \b RESET_SRC_3,
+//!             - \b RESET_SRC_4,
+//!             - \b RESET_SRC_5,
+//!             - \b RESET_SRC_6,
+//!             - \b RESET_SRC_7,
+//!             - \b RESET_SRC_8,
+//!             - \b RESET_SRC_9,
+//!             - \b RESET_SRC_10,
+//!             - \b RESET_SRC_11,
+//!             - \b RESET_SRC_12,
+//!             - \b RESET_SRC_13,
+//!             - \b RESET_SRC_14,
+//!             - \b RESET_SRC_15
+//!
+//! \return none
+//
+//*****************************************************************************
+extern void ResetCtl_initiateSoftResetWithSource(uint32_t source);
+
+//*****************************************************************************
+//
+//! Retrieves previous soft reset sources
+//!
+//! \return the bitwise or of previous reset sources. These sources must be
+//! cleared using the \link ResetCtl_clearSoftResetSource \endlink function to
+//! be cleared.
+//! Possible values include:
+//!             - \b RESET_SRC_0,
+//!             - \b RESET_SRC_1,
+//!             - \b RESET_SRC_2,
+//!             - \b RESET_SRC_3,
+//!             - \b RESET_SRC_4,
+//!             - \b RESET_SRC_5,
+//!             - \b RESET_SRC_6,
+//!             - \b RESET_SRC_7,
+//!             - \b RESET_SRC_8,
+//!             - \b RESET_SRC_9,
+//!             - \b RESET_SRC_10,
+//!             - \b RESET_SRC_11,
+//!             - \b RESET_SRC_12,
+//!             - \b RESET_SRC_13,
+//!             - \b RESET_SRC_14,
+//!             - \b RESET_SRC_15
+//
+//*****************************************************************************
+extern uint32_t ResetCtl_getSoftResetSource(void);
+
+//*****************************************************************************
+//
+//! Clears the reset sources associated with at soft reset
+//!
+//! \param mask - Bitwise OR of any of the following values:
+//!             - \b RESET_SRC_0,
+//!             - \b RESET_SRC_1,
+//!             - \b RESET_SRC_2,
+//!             - \b RESET_SRC_3,
+//!             - \b RESET_SRC_4,
+//!             - \b RESET_SRC_5,
+//!             - \b RESET_SRC_6,
+//!             - \b RESET_SRC_7,
+//!             - \b RESET_SRC_8,
+//!             - \b RESET_SRC_9,
+//!             - \b RESET_SRC_10,
+//!             - \b RESET_SRC_11,
+//!             - \b RESET_SRC_12,
+//!             - \b RESET_SRC_13,
+//!             - \b RESET_SRC_14,
+//!             - \b RESET_SRC_15
+//!
+//! \return none
+//
+//*****************************************************************************
+extern void ResetCtl_clearSoftResetSource(uint32_t mask);
+
+//*****************************************************************************
+//
+//! Initiates a hard system reset.
+//!
+//! \return none
+//
+//*****************************************************************************
+extern void ResetCtl_initiateHardReset(void);
+
+//*****************************************************************************
+//
+//! Initiates a hard system reset with a particular source given. This source
+//! is generic and can be assigned by the user.
+//!
+//! \param source - Valid values are one the following values:
+//!             - \b RESET_SRC_0,
+//!             - \b RESET_SRC_1,
+//!             - \b RESET_SRC_2,
+//!             - \b RESET_SRC_3,
+//!             - \b RESET_SRC_4,
+//!             - \b RESET_SRC_5,
+//!             - \b RESET_SRC_6,
+//!             - \b RESET_SRC_7,
+//!             - \b RESET_SRC_8,
+//!             - \b RESET_SRC_9,
+//!             - \b RESET_SRC_10,
+//!             - \b RESET_SRC_11,
+//!             - \b RESET_SRC_12,
+//!             - \b RESET_SRC_13,
+//!             - \b RESET_SRC_14,
+//!             - \b RESET_SRC_15
+//! \return none
+//
+//*****************************************************************************
+extern void ResetCtl_initiateHardResetWithSource(uint32_t source);
+
+//*****************************************************************************
+//
+//! Retrieves previous hard reset sources
+//!
+//! \return the bitwise or of previous reset sources. These sources must be
+//! cleared using the \link ResetCtl_clearHardResetSource \endlink function to
+//! be cleared.
+//! Possible values include:
+//!             - \b RESET_SRC_0,
+//!             - \b RESET_SRC_1,
+//!             - \b RESET_SRC_2,
+//!             - \b RESET_SRC_3,
+//!             - \b RESET_SRC_4,
+//!             - \b RESET_SRC_5,
+//!             - \b RESET_SRC_6,
+//!             - \b RESET_SRC_7,
+//!             - \b RESET_SRC_8,
+//!             - \b RESET_SRC_9,
+//!             - \b RESET_SRC_10,
+//!             - \b RESET_SRC_11,
+//!             - \b RESET_SRC_12,
+//!             - \b RESET_SRC_13,
+//!             - \b RESET_SRC_14,
+//!             - \b RESET_SRC_15
+//
+//*****************************************************************************
+extern uint32_t ResetCtl_getHardResetSource(void);
+
+//*****************************************************************************
+//
+//! Clears the reset sources associated with at hard reset
+//!
+//! \param mask - Bitwise OR of any of the following values:
+//!             - \b RESET_SRC_0,
+//!             - \b RESET_SRC_1,
+//!             - \b RESET_SRC_2,
+//!             - \b RESET_SRC_3,
+//!             - \b RESET_SRC_4,
+//!             - \b RESET_SRC_5,
+//!             - \b RESET_SRC_6,
+//!             - \b RESET_SRC_7,
+//!             - \b RESET_SRC_8,
+//!             - \b RESET_SRC_9,
+//!             - \b RESET_SRC_10,
+//!             - \b RESET_SRC_11,
+//!             - \b RESET_SRC_12,
+//!             - \b RESET_SRC_13,
+//!             - \b RESET_SRC_14,
+//!             - \b RESET_SRC_15
+//!
+//! \return none
+//
+//*****************************************************************************
+extern void ResetCtl_clearHardResetSource(uint32_t mask);
+
+//*****************************************************************************
+//
+//! Indicates the last cause of a power-on reset (POR) due to PSS operation.
+//! Note that the bits returned from this function may be set in different
+//! combinations. When a cold power up occurs, the value of all the values ORed
+//! together could be returned as a cold power up causes these conditions.
+//!
+//! \return  Bitwise OR of any of the following values:
+//!                 - RESET_VCCDET,
+//!                 - RESET_SVSH_TRIP,
+//!                 - RESET_SVSL_TRIP,
+//!                 - RESET_BGREF_BAD
+//
+//*****************************************************************************
+extern uint32_t ResetCtl_getPSSSource(void);
+
+//*****************************************************************************
+//
+//! Clears the  PSS reset source flags
+//!
+//! \return none
+//
+//*****************************************************************************
+extern void ResetCtl_clearPSSFlags(void);
+
+//*****************************************************************************
+//
+//! Indicates the last cause of a power-on reset (POR) due to PCM operation.
+//!
+//! \return  Bitwise OR of any of the following values:
+//!                 - RESET_SD0,
+//!                 - RESET_SD1
+//
+//*****************************************************************************
+extern uint32_t ResetCtl_getPCMSource(void);
+
+//*****************************************************************************
+//
+//! Clears the corresponding PCM reset source flags
+//!
+//! \return none
+//
+//*****************************************************************************
+extern void ResetCtl_clearPCMFlags(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif // __RESET_H__
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rom.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rom.h
new file mode 100644
index 000000000..8fae52521
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rom.h
@@ -0,0 +1,1805 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __ROM_H__
+#define __ROM_H__
+
+//*****************************************************************************
+//
+// Pointers to the main API tables.
+//
+//*****************************************************************************
+#define ROM_APITABLE            ((unsigned long *)0x02000800)
+#define ROM_VERSION             (ROM_APITABLE[0])
+#define ROM_ADC14TABLE          ((unsigned long *)(ROM_APITABLE[1]))
+#define ROM_AES256TABLE         ((unsigned long *)(ROM_APITABLE[2]))
+#define ROM_COMPTABLE           ((unsigned long *)(ROM_APITABLE[3]))
+#define ROM_CRC32TABLE          ((unsigned long *)(ROM_APITABLE[4]))
+#define ROM_CSTABLE             ((unsigned long *)(ROM_APITABLE[5]))
+#define ROM_DMATABLE            ((unsigned long *)(ROM_APITABLE[6]))
+#define ROM_FLASHCTLTABLE       ((unsigned long *)(ROM_APITABLE[7]))
+#define ROM_FPUTABLE            ((unsigned long *)(ROM_APITABLE[8]))
+#define ROM_GPIOTABLE           ((unsigned long *)(ROM_APITABLE[9]))
+#define ROM_I2CTABLE            ((unsigned long *)(ROM_APITABLE[10]))
+#define ROM_INTTABLE            ((unsigned long *)(ROM_APITABLE[11]))
+#define ROM_MPUTABLE            ((unsigned long *)(ROM_APITABLE[12]))
+#define ROM_PCMTABLE            ((unsigned long *)(ROM_APITABLE[13]))
+#define ROM_PMAPTABLE           ((unsigned long *)(ROM_APITABLE[14]))
+#define ROM_PSSTABLE            ((unsigned long *)(ROM_APITABLE[15]))
+#define ROM_REFTABLE            ((unsigned long *)(ROM_APITABLE[16]))
+#define ROM_RESETCTLTABLE       ((unsigned long *)(ROM_APITABLE[17]))
+#define ROM_RTCTABLE            ((unsigned long *)(ROM_APITABLE[18]))
+#define ROM_SPITABLE            ((unsigned long *)(ROM_APITABLE[19]))
+#define ROM_SYSCTLTABLE         ((unsigned long *)(ROM_APITABLE[20]))
+#define ROM_SYSTICKTABLE        ((unsigned long *)(ROM_APITABLE[21]))
+#define ROM_TIMER_ATABLE        ((unsigned long *)(ROM_APITABLE[22]))
+#define ROM_TIMER32TABLE        ((unsigned long *)(ROM_APITABLE[23]))
+#define ROM_UARTTABLE           ((unsigned long *)(ROM_APITABLE[24]))
+#define ROM_WDTTABLE            ((unsigned long *)(ROM_APITABLE[25]))
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the ADC14 API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ADC14_enableModule                                                \
+        ((void (*)(void))ROM_ADC14TABLE[0])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ADC14_disableModule                                               \
+        ((bool (*)(void))ROM_ADC14TABLE[1])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ADC14_initModule                                                  \
+        ((bool (*)(uint32_t clockSource,                                      \
+                   uint32_t clockPredivider,                                  \
+                   uint32_t clockDivider,                                     \
+                   uint32_t internalChannelMask))ROM_ADC14TABLE[2])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ADC14_setResolution                                               \
+        ((void (*)(uint32_t resolution))ROM_ADC14TABLE[3])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ADC14_getResolution                                               \
+        ((uint_fast32_t (*)(void))ROM_ADC14TABLE[4])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ADC14_setSampleHoldTrigger                                        \
+        ((bool (*)(uint32_t source,                                           \
+                   bool invertSignal))ROM_ADC14TABLE[5])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ADC14_setSampleHoldTime                                           \
+        ((bool (*)(uint32_t firstPulseWidth,                                  \
+                   uint32_t secondPulseWidth))ROM_ADC14TABLE[6])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ADC14_configureMultiSequenceMode                                  \
+        ((bool (*)(uint32_t memoryStart,                                      \
+                   uint32_t memoryEnd,                                        \
+                   bool repeatMode))ROM_ADC14TABLE[7])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ADC14_configureSingleSampleMode                                   \
+        ((bool (*)(uint32_t memoryDestination,                                \
+                   bool repeatMode))ROM_ADC14TABLE[8])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ADC14_enableConversion                                            \
+        ((bool (*)(void))ROM_ADC14TABLE[9])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ADC14_disableConversion                                           \
+        ((void (*)(void))ROM_ADC14TABLE[10])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ADC14_isBusy                                                      \
+        ((bool (*)(void))ROM_ADC14TABLE[11])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ADC14_configureConversionMemory                                   \
+        ((bool (*)(uint32_t memorySelect,                                     \
+                   uint32_t refSelect,                                        \
+                   uint32_t channelSelect,                                    \
+                   bool differntialMode))ROM_ADC14TABLE[12])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ADC14_enableComparatorWindow                                      \
+        ((bool (*)(uint32_t memorySelect,                                     \
+                   uint32_t windowSelect))ROM_ADC14TABLE[13])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ADC14_disableComparatorWindow                                     \
+        ((bool (*)(uint32_t memorySelect))ROM_ADC14TABLE[14])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ADC14_setComparatorWindowValue                                    \
+        ((bool (*)(uint32_t window,                                           \
+                   int16_t low,                                               \
+                   int16_t high))ROM_ADC14TABLE[15])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ADC14_setResultFormat                                             \
+        ((bool (*)(uint32_t resultFormat))ROM_ADC14TABLE[16])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ADC14_getResult                                                   \
+        ((uint_fast16_t (*)(uint32_t memorySelect))ROM_ADC14TABLE[17])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ADC14_getMultiSequenceResult                                      \
+        ((void (*)(uint16_t* res))ROM_ADC14TABLE[18])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ADC14_getResultArray                                              \
+        ((void (*)(uint32_t memoryStart,                                      \
+                   uint32_t memoryEnd,                                        \
+                   uint16_t* res))ROM_ADC14TABLE[19])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ADC14_enableReferenceBurst                                        \
+        ((bool (*)(void))ROM_ADC14TABLE[20])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ADC14_disableReferenceBurst                                       \
+        ((bool (*)(void))ROM_ADC14TABLE[21])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ADC14_setPowerMode                                                \
+        ((bool (*)(uint32_t powerMode))ROM_ADC14TABLE[22])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ADC14_enableInterrupt                                             \
+        ((void (*)(uint_fast64_t mask))ROM_ADC14TABLE[23])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ADC14_disableInterrupt                                            \
+        ((void (*)(uint_fast64_t mask))ROM_ADC14TABLE[24])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ADC14_getInterruptStatus                                          \
+        ((uint_fast64_t (*)(void))ROM_ADC14TABLE[25])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ADC14_getEnabledInterruptStatus                                   \
+        ((uint_fast64_t (*)(void))ROM_ADC14TABLE[26])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ADC14_clearInterruptFlag                                          \
+        ((void (*)(uint_fast64_t mask))ROM_ADC14TABLE[27])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ADC14_toggleConversionTrigger                                     \
+        ((bool (*)(void))ROM_ADC14TABLE[28])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ADC14_enableSampleTimer                                           \
+        ((bool (*)(uint32_t multiSampleConvert))ROM_ADC14TABLE[29])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ADC14_disableSampleTimer                                          \
+        ((bool (*)(void))ROM_ADC14TABLE[30])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the AES256 API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_AES256_setCipherKey                                               \
+        ((bool (*)(uint32_t moduleInstance,                                   \
+                   const uint8_t *cipherKey,                                  \
+                   uint_fast16_t keyLength))ROM_AES256TABLE[0])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_AES256_encryptData                                                \
+        ((void (*)(uint32_t moduleInstance,                                   \
+                   const uint8_t *data,                                       \
+                   uint8_t *encryptedData))ROM_AES256TABLE[1])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_AES256_decryptData                                                \
+        ((void (*)(uint32_t moduleInstance,                                   \
+                   const uint8_t *data,                                       \
+                   uint8_t *decryptedData))ROM_AES256TABLE[2])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_AES256_setDecipherKey                                             \
+        ((bool (*)(uint32_t moduleInstance,                                   \
+                   const uint8_t *cipherKey,                                  \
+                   uint_fast16_t keyLength))ROM_AES256TABLE[3])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_AES256_reset                                                      \
+        ((void (*)(uint32_t moduleInstance))ROM_AES256TABLE[4])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_AES256_startEncryptData                                           \
+        ((void (*)(uint32_t moduleInstance,                                   \
+                   const uint8_t *data))ROM_AES256TABLE[5])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_AES256_startDecryptData                                           \
+        ((void (*)(uint32_t moduleInstance,                                   \
+                   const uint8_t *data))ROM_AES256TABLE[6])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_AES256_startSetDecipherKey                                        \
+        ((bool (*)(uint32_t moduleInstance,                                   \
+                   const uint8_t *cipherKey,                                  \
+                   uint_fast16_t keyLength))ROM_AES256TABLE[7])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_AES256_getDataOut                                                 \
+        ((bool (*)(uint32_t moduleInstance,                                   \
+                   uint8_t *outputData))ROM_AES256TABLE[8])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_AES256_isBusy                                                     \
+        ((bool (*)(uint32_t moduleInstance))ROM_AES256TABLE[9])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_AES256_clearErrorFlag                                             \
+        ((void (*)(uint32_t moduleInstance))ROM_AES256TABLE[10])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_AES256_getErrorFlagStatus                                         \
+        ((uint32_t (*)(uint32_t moduleInstance))ROM_AES256TABLE[11])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_AES256_clearInterruptFlag                                         \
+        ((void (*)(uint32_t moduleInstance))ROM_AES256TABLE[12])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_AES256_enableInterrupt                                            \
+        ((void (*)(uint32_t moduleInstance))ROM_AES256TABLE[14])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_AES256_disableInterrupt                                           \
+        ((void (*)(uint32_t moduleInstance))ROM_AES256TABLE[15])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Comp API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_COMP_E_initModule                                                 \
+        ((bool (*)(uint32_t comparator,                                       \
+                   const COMP_E_Config *config))ROM_COMPTABLE[0])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_COMP_E_setReferenceVoltage                                        \
+        ((void (*)(uint32_t comparator,                                       \
+                   uint_fast16_t supplyVoltageReferenceBase,                  \
+                   uint_fast16_t lowerLimitSupplyVoltageFractionOf32,         \
+                   uint_fast16_t upperLimitSupplyVoltageFractionOf32))ROM_COMPTABLE[1])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_COMP_E_setReferenceAccuracy                                       \
+        ((void (*)(uint32_t comparator,                                       \
+                   uint_fast16_t referenceAccuracy))ROM_COMPTABLE[2])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_COMP_E_setPowerMode                                               \
+        ((void (*)(uint32_t comparator,                                       \
+                   uint_fast16_t powerMode))ROM_COMPTABLE[3])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_COMP_E_enableModule                                               \
+        ((void (*)(uint32_t comparator))ROM_COMPTABLE[4])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_COMP_E_disableModule                                              \
+        ((void (*)(uint32_t comparator))ROM_COMPTABLE[5])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_COMP_E_shortInputs                                                \
+        ((void (*)(uint32_t comparator))ROM_COMPTABLE[6])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_COMP_E_unshortInputs                                              \
+        ((void (*)(uint32_t comparator))ROM_COMPTABLE[7])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_COMP_E_disableInputBuffer                                         \
+        ((void (*)(uint32_t comparator,                                       \
+                   uint_fast16_t inputPort))ROM_COMPTABLE[8])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_COMP_E_enableInputBuffer                                          \
+        ((void (*)(uint32_t comparator,                                       \
+                   uint_fast16_t inputPort))ROM_COMPTABLE[9])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_COMP_E_swapIO                                                     \
+        ((void (*)(uint32_t comparator))ROM_COMPTABLE[10])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_COMP_E_outputValue                                                \
+        ((uint8_t (*)(uint32_t comparator))ROM_COMPTABLE[11])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_COMP_E_enableInterrupt                                            \
+        ((void (*)(uint32_t comparator,                                       \
+                   uint_fast16_t mask))ROM_COMPTABLE[12])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_COMP_E_disableInterrupt                                           \
+        ((void (*)(uint32_t comparator,                                       \
+                   uint_fast16_t mask))ROM_COMPTABLE[13])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_COMP_E_clearInterruptFlag                                         \
+        ((void (*)(uint32_t comparator,                                       \
+                   uint_fast16_t mask))ROM_COMPTABLE[14])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_COMP_E_getInterruptStatus                                         \
+        ((uint_fast16_t (*)(uint32_t comparator))ROM_COMPTABLE[15])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_COMP_E_getEnabledInterruptStatus                                  \
+        ((uint_fast16_t (*)(uint32_t comparator))ROM_COMPTABLE[16])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_COMP_E_setInterruptEdgeDirection                                  \
+        ((void (*)(uint32_t comparator,                                       \
+                   uint_fast8_t edgeDirection))ROM_COMPTABLE[17])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_COMP_E_toggleInterruptEdgeDirection                               \
+        ((void (*)(uint32_t comparator))ROM_COMPTABLE[18])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the CRC32 API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_CRC32_setSeed                                                     \
+        ((void (*)(uint32_t seed,                                             \
+                   uint_fast8_t crcType))ROM_CRC32TABLE[0])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_CRC32_set8BitData                                                 \
+        ((void (*)(uint8_t dataIn,                                            \
+                   uint_fast8_t crcType))ROM_CRC32TABLE[1])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_CRC32_set16BitData                                                \
+        ((void (*)(uint16_t dataIn,                                           \
+                   uint_fast8_t crcType))ROM_CRC32TABLE[2])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_CRC32_set32BitData                                                \
+        ((void (*)(uint32_t dataIn))ROM_CRC32TABLE[3])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_CRC32_set8BitDataReversed                                         \
+        ((void (*)(uint8_t dataIn,                                            \
+                   uint_fast8_t crcType))ROM_CRC32TABLE[4])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_CRC32_set16BitDataReversed                                        \
+        ((void (*)(uint16_t dataIn,                                           \
+                   uint_fast8_t crcType))ROM_CRC32TABLE[5])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_CRC32_set32BitDataReversed                                        \
+        ((void (*)(uint32_t dataIn))ROM_CRC32TABLE[6])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_CRC32_getResult                                                   \
+        ((uint32_t (*)(uint_fast8_t crcType))ROM_CRC32TABLE[7])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_CRC32_getResultReversed                                           \
+        ((uint32_t (*)(uint_fast8_t crcType))ROM_CRC32TABLE[8])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the CS API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_CS_enableClockRequest                                             \
+        ((void (*)(uint32_t selectClock))ROM_CSTABLE[2])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_CS_disableClockRequest                                            \
+        ((void (*)(uint32_t selectClock))ROM_CSTABLE[3])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_CS_enableDCOExternalResistor                                      \
+        ((void (*)(void))ROM_CSTABLE[6])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_CS_disableDCOExternalResistor                                     \
+        ((void (*)(void))ROM_CSTABLE[7])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_CS_getEnabledInterruptStatus                                      \
+        ((uint32_t (*)(void))ROM_CSTABLE[10])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_CS_getInterruptStatus                                             \
+        ((uint32_t (*)(void))ROM_CSTABLE[11])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the DMA API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_DMA_enableModule                                                  \
+        ((void (*)(void))ROM_DMATABLE[0])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_DMA_disableModule                                                 \
+        ((void (*)(void))ROM_DMATABLE[1])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_DMA_getErrorStatus                                                \
+        ((uint32_t (*)(void))ROM_DMATABLE[2])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_DMA_clearErrorStatus                                              \
+        ((void (*)(void))ROM_DMATABLE[3])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_DMA_enableChannel                                                 \
+        ((void (*)(uint32_t channelNum))ROM_DMATABLE[4])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_DMA_disableChannel                                                \
+        ((void (*)(uint32_t channelNum))ROM_DMATABLE[5])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_DMA_isChannelEnabled                                              \
+        ((bool (*)(uint32_t channelNum))ROM_DMATABLE[6])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_DMA_setControlBase                                                \
+        ((void (*)(void *controlTable))ROM_DMATABLE[7])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_DMA_getControlBase                                                \
+        ((void* (*)(void))ROM_DMATABLE[8])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_DMA_getControlAlternateBase                                       \
+        ((void* (*)(void))ROM_DMATABLE[9])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_DMA_requestChannel                                                \
+        ((void (*)(uint32_t channelNum))ROM_DMATABLE[10])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_DMA_enableChannelAttribute                                        \
+        ((void (*)(uint32_t channelNum,                                       \
+                   uint32_t attr))ROM_DMATABLE[11])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_DMA_disableChannelAttribute                                       \
+        ((void (*)(uint32_t channelNum,                                       \
+                   uint32_t attr))ROM_DMATABLE[12])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_DMA_getChannelAttribute                                           \
+        ((uint32_t (*)(uint32_t channelNum))ROM_DMATABLE[13])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_DMA_setChannelControl                                             \
+        ((void (*)(uint32_t channelStructIndex,                               \
+                   uint32_t control))ROM_DMATABLE[14])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_DMA_setChannelTransfer                                            \
+        ((void (*)(uint32_t channelStructIndex,                               \
+                   uint32_t mode,                                             \
+                   void *srcAddr,                                             \
+                   void *dstAddr,                                             \
+                   uint32_t transferSize))ROM_DMATABLE[15])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_DMA_setChannelScatterGather                                       \
+        ((void (*)(uint32_t channelNum,                                       \
+                   uint32_t taskCount,                                        \
+                   void *taskList,                                            \
+                   uint32_t isPeriphSG))ROM_DMATABLE[16])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_DMA_getChannelSize                                                \
+        ((uint32_t (*)(uint32_t channelStructIndex))ROM_DMATABLE[17])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_DMA_getChannelMode                                                \
+        ((uint32_t (*)(uint32_t channelStructIndex))ROM_DMATABLE[18])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_DMA_assignChannel                                                 \
+        ((void (*)(uint32_t mapping))ROM_DMATABLE[19])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_DMA_requestSoftwareTransfer                                       \
+        ((void (*)(uint32_t channel))ROM_DMATABLE[20])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_DMA_assignInterrupt                                               \
+        ((void (*)(uint32_t interruptNumber,                                  \
+                   uint32_t channel))ROM_DMATABLE[21])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_DMA_enableInterrupt                                               \
+        ((void (*)(uint32_t interruptNumber))ROM_DMATABLE[22])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_DMA_disableInterrupt                                              \
+        ((void (*)(uint32_t interruptNumber))ROM_DMATABLE[23])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_DMA_getInterruptStatus                                            \
+        ((uint32_t (*)(void))ROM_DMATABLE[24])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_DMA_clearInterruptFlag                                            \
+        ((void (*)(uint32_t intChannel))ROM_DMATABLE[25])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Flash API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_FlashCtl_enableReadBuffering                                      \
+        ((void (*)(uint_fast8_t memoryBank,                                   \
+                   uint_fast8_t accessMethod))ROM_FLASHCTLTABLE[2])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_FlashCtl_disableReadBuffering                                     \
+        ((void (*)(uint_fast8_t memoryBank,                                   \
+                   uint_fast8_t accessMethod))ROM_FLASHCTLTABLE[3])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_FlashCtl_unprotectSector                                          \
+        ((bool (*)(uint_fast8_t memorySpace,                                  \
+                   uint32_t sectorMask))ROM_FLASHCTLTABLE[4])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_FlashCtl_protectSector                                            \
+        ((bool (*)(uint_fast8_t memorySpace,                                  \
+                   uint32_t sectorMask))ROM_FLASHCTLTABLE[5])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_FlashCtl_isSectorProtected                                        \
+        ((bool (*)(uint_fast8_t memorySpace,                                  \
+                   uint32_t sector))ROM_FLASHCTLTABLE[6])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_FlashCtl_setProgramVerification                                   \
+        ((void (*)(uint32_t verificationSetting))ROM_FLASHCTLTABLE[11])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_FlashCtl_clearProgramVerification                                 \
+        ((void (*)(uint32_t verificationSetting))ROM_FLASHCTLTABLE[12])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_FlashCtl_enableWordProgramming                                    \
+        ((void (*)(uint32_t mode))ROM_FLASHCTLTABLE[13])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_FlashCtl_disableWordProgramming                                   \
+        ((void (*)(void))ROM_FLASHCTLTABLE[14])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_FlashCtl_isWordProgrammingEnabled                                 \
+        ((uint32_t (*)(void))ROM_FLASHCTLTABLE[15])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_FlashCtl_enableInterrupt                                          \
+        ((void (*)(uint32_t flags))ROM_FLASHCTLTABLE[16])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_FlashCtl_disableInterrupt                                         \
+        ((void (*)(uint32_t flags))ROM_FLASHCTLTABLE[17])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_FlashCtl_getEnabledInterruptStatus                                \
+        ((uint32_t (*)(void))ROM_FLASHCTLTABLE[18])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_FlashCtl_getInterruptStatus                                       \
+        ((uint32_t (*)(void))ROM_FLASHCTLTABLE[19])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_FlashCtl_clearInterruptFlag                                       \
+        ((void (*)(uint32_t flags))ROM_FLASHCTLTABLE[20])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_FlashCtl_setWaitState                                             \
+        ((void (*)(uint32_t bank,                                             \
+                   uint32_t waitState))ROM_FLASHCTLTABLE[21])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_FlashCtl_getWaitState                                             \
+        ((uint32_t (*)(uint32_t bank))ROM_FLASHCTLTABLE[22])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_FlashCtl_setReadMode                                              \
+        ((bool (*)(uint32_t flashBank,                                        \
+                   uint32_t readMode))ROM_FLASHCTLTABLE[23])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_FlashCtl_getReadMode                                              \
+        ((uint32_t (*)(uint32_t flashBank))ROM_FLASHCTLTABLE[24])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the FPU API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_FPU_enableModule                                                  \
+        ((void (*)(void))ROM_FPUTABLE[0])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_FPU_disableModule                                                 \
+        ((void (*)(void))ROM_FPUTABLE[1])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_FPU_enableStacking                                                \
+        ((void (*)(void))ROM_FPUTABLE[2])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_FPU_enableLazyStacking                                            \
+        ((void (*)(void))ROM_FPUTABLE[3])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_FPU_disableStacking                                               \
+        ((void (*)(void))ROM_FPUTABLE[4])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_FPU_setHalfPrecisionMode                                          \
+        ((void (*)(uint32_t mode))ROM_FPUTABLE[5])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_FPU_setNaNMode                                                    \
+        ((void (*)(uint32_t mode))ROM_FPUTABLE[6])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_FPU_setFlushToZeroMode                                            \
+        ((void (*)(uint32_t mode))ROM_FPUTABLE[7])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_FPU_setRoundingMode                                               \
+        ((void (*)(uint32_t mode))ROM_FPUTABLE[8])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the GPIO API.
+//
+//*****************************************************************************
+
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the I2C API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_initMaster                                                    \
+        ((void (*)(uint32_t moduleInstance,                                   \
+                   const eUSCI_I2C_MasterConfig *config))ROM_I2CTABLE[0])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_enableModule                                                  \
+        ((void (*)(uint32_t moduleInstance))ROM_I2CTABLE[2])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_disableModule                                                 \
+        ((void (*)(uint32_t moduleInstance))ROM_I2CTABLE[3])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_setMode                                                       \
+        ((void (*)(uint32_t moduleInstance,                                   \
+                   uint_fast8_t mode))ROM_I2CTABLE[5])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_slavePutData                                                  \
+        ((void (*)(uint32_t moduleInstance,                                   \
+                   uint8_t transmitData))ROM_I2CTABLE[6])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_slaveGetData                                                  \
+        ((uint8_t (*)(uint32_t moduleInstance))ROM_I2CTABLE[7])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_isBusBusy                                                     \
+        ((uint8_t (*)(uint32_t moduleInstance))ROM_I2CTABLE[8])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_masterSendSingleByte                                          \
+        ((void (*)(uint32_t moduleInstance,                                   \
+                   uint8_t txData))ROM_I2CTABLE[9])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_masterSendSingleByteWithTimeout                               \
+        ((bool (*)(uint32_t moduleInstance,                                   \
+                   uint8_t txData,                                            \
+                   uint32_t timeout))ROM_I2CTABLE[10])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_masterSendMultiByteStart                                      \
+        ((void (*)(uint32_t moduleInstance,                                   \
+                   uint8_t txData))ROM_I2CTABLE[11])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_masterSendMultiByteStartWithTimeout                           \
+        ((bool (*)(uint32_t moduleInstance,                                   \
+                   uint8_t txData,                                            \
+                   uint32_t timeout))ROM_I2CTABLE[12])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_masterSendMultiByteNext                                       \
+        ((void (*)(uint32_t moduleInstance,                                   \
+                   uint8_t txData))ROM_I2CTABLE[13])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_masterSendMultiByteNextWithTimeout                            \
+        ((bool (*)(uint32_t moduleInstance,                                   \
+                   uint8_t txData,                                            \
+                   uint32_t timeout))ROM_I2CTABLE[14])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_masterSendMultiByteFinish                                     \
+        ((void (*)(uint32_t moduleInstance,                                   \
+                   uint8_t txData))ROM_I2CTABLE[15])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_masterSendMultiByteFinishWithTimeout                          \
+        ((bool (*)(uint32_t moduleInstance,                                   \
+                   uint8_t txData,                                            \
+                   uint32_t timeout))ROM_I2CTABLE[16])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_masterSendMultiByteStop                                       \
+        ((void (*)(uint32_t moduleInstance))ROM_I2CTABLE[17])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_masterSendMultiByteStopWithTimeout                            \
+        ((bool (*)(uint32_t moduleInstance,                                   \
+                   uint32_t timeout))ROM_I2CTABLE[18])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_masterReceiveStart                                            \
+        ((void (*)(uint32_t moduleInstance))ROM_I2CTABLE[19])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_masterReceiveMultiByteNext                                    \
+        ((uint8_t (*)(uint32_t moduleInstance))ROM_I2CTABLE[20])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_masterReceiveMultiByteFinish                                  \
+        ((uint8_t (*)(uint32_t moduleInstance))ROM_I2CTABLE[21])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_masterReceiveMultiByteFinishWithTimeout                       \
+        ((bool (*)(uint32_t moduleInstance,                                   \
+                   uint8_t *txData,                                           \
+                   uint32_t timeout))ROM_I2CTABLE[22])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_masterReceiveMultiByteStop                                    \
+        ((void (*)(uint32_t moduleInstance))ROM_I2CTABLE[23])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_masterReceiveSingleByte                                       \
+        ((uint8_t (*)(uint32_t moduleInstance))ROM_I2CTABLE[24])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_masterReceiveSingle                                           \
+        ((uint8_t (*)(uint32_t moduleInstance))ROM_I2CTABLE[25])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_getReceiveBufferAddressForDMA                                 \
+        ((uint32_t (*)(uint32_t moduleInstance))ROM_I2CTABLE[26])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_getTransmitBufferAddressForDMA                                \
+        ((uint32_t (*)(uint32_t moduleInstance))ROM_I2CTABLE[27])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_masterIsStopSent                                              \
+        ((uint8_t (*)(uint32_t moduleInstance))ROM_I2CTABLE[28])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_masterIsStartSent                                             \
+        ((bool (*)(uint32_t moduleInstance))ROM_I2CTABLE[29])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_masterSendStart                                               \
+        ((void (*)(uint32_t moduleInstance))ROM_I2CTABLE[30])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_enableMultiMasterMode                                         \
+        ((void (*)(uint32_t moduleInstance))ROM_I2CTABLE[31])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_disableMultiMasterMode                                        \
+        ((void (*)(uint32_t moduleInstance))ROM_I2CTABLE[32])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_enableInterrupt                                               \
+        ((void (*)(uint32_t moduleInstance,                                   \
+                   uint_fast16_t mask))ROM_I2CTABLE[33])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_disableInterrupt                                              \
+        ((void (*)(uint32_t moduleInstance,                                   \
+                   uint_fast16_t mask))ROM_I2CTABLE[34])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_clearInterruptFlag                                            \
+        ((void (*)(uint32_t moduleInstance,                                   \
+                   uint_fast16_t mask))ROM_I2CTABLE[35])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_getEnabledInterruptStatus                                     \
+        ((uint_fast16_t (*)(uint32_t moduleInstance))ROM_I2CTABLE[37])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_I2C_getMode                                                       \
+        ((uint_fast8_t (*)(uint32_t moduleInstance))ROM_I2CTABLE[38])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Interrupt API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Interrupt_enableMaster                                            \
+        ((bool (*)(void))ROM_INTTABLE[0])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Interrupt_disableMaster                                           \
+        ((bool (*)(void))ROM_INTTABLE[1])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Interrupt_setPriorityGrouping                                     \
+        ((void (*)(uint32_t bits))ROM_INTTABLE[2])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Interrupt_getPriorityGrouping                                     \
+        ((uint32_t (*)(void))ROM_INTTABLE[3])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Interrupt_setPriority                                             \
+        ((void (*)(uint32_t interruptNumber,                                  \
+                   uint8_t priority))ROM_INTTABLE[4])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Interrupt_getPriority                                             \
+        ((uint8_t (*)(uint32_t interruptNumber))ROM_INTTABLE[5])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Interrupt_enableInterrupt                                         \
+        ((void (*)(uint32_t interruptNumber))ROM_INTTABLE[6])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Interrupt_disableInterrupt                                        \
+        ((void (*)(uint32_t interruptNumber))ROM_INTTABLE[7])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Interrupt_isEnabled                                               \
+        ((bool (*)(uint32_t interruptNumber))ROM_INTTABLE[8])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Interrupt_pendInterrupt                                           \
+        ((void (*)(uint32_t interruptNumber))ROM_INTTABLE[9])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Interrupt_setPriorityMask                                         \
+        ((void (*)(uint8_t priorityMask))ROM_INTTABLE[10])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Interrupt_getPriorityMask                                         \
+        ((uint8_t (*)(void))ROM_INTTABLE[11])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Interrupt_setVectorTableAddress                                   \
+        ((void (*)(uint32_t addr))ROM_INTTABLE[12])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Interrupt_getVectorTableAddress                                   \
+        ((uint32_t (*)(void))ROM_INTTABLE[13])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Interrupt_enableSleepOnIsrExit                                    \
+        ((void (*)(void))ROM_INTTABLE[14])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Interrupt_disableSleepOnIsrExit                                   \
+        ((void (*)(void))ROM_INTTABLE[15])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the MPU API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_MPU_enableModule                                                  \
+        ((void (*)(uint32_t mpuConfig))ROM_MPUTABLE[0])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_MPU_disableModule                                                 \
+        ((void (*)(void))ROM_MPUTABLE[1])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_MPU_getRegionCount                                                \
+        ((uint32_t (*)(void))ROM_MPUTABLE[2])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_MPU_enableRegion                                                  \
+        ((void (*)(uint32_t region))ROM_MPUTABLE[3])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_MPU_disableRegion                                                 \
+        ((void (*)(uint32_t region))ROM_MPUTABLE[4])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_MPU_setRegion                                                     \
+        ((void (*)(uint32_t region,                                           \
+                   uint32_t addr,                                             \
+                   uint32_t flags))ROM_MPUTABLE[5])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_MPU_getRegion                                                     \
+        ((void (*)(uint32_t region,                                           \
+                   uint32_t *addr,                                            \
+                   uint32_t *pflags))ROM_MPUTABLE[6])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_MPU_enableInterrupt                                               \
+        ((void (*)(void))ROM_MPUTABLE[7])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_MPU_disableInterrupt                                              \
+        ((void (*)(void))ROM_MPUTABLE[8])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the PCM API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_PCM_setCoreVoltageLevel                                           \
+        ((bool (*)(uint_fast8_t voltageLevel))ROM_PCMTABLE[0])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_PCM_getCoreVoltageLevel                                           \
+        ((uint8_t (*)(void))ROM_PCMTABLE[1])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_PCM_setCoreVoltageLevelWithTimeout                                \
+        ((bool (*)(uint_fast8_t voltageLevel,                                 \
+                   uint32_t timeOut))ROM_PCMTABLE[2])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_PCM_setPowerMode                                                  \
+        ((bool (*)(uint_fast8_t powerMode))ROM_PCMTABLE[3])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_PCM_setPowerModeWithTimeout                                       \
+        ((bool (*)(uint_fast8_t powerMode,                                    \
+                   uint32_t timeOut))ROM_PCMTABLE[4])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_PCM_getPowerMode                                                  \
+        ((uint8_t (*)(void))ROM_PCMTABLE[5])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_PCM_setPowerState                                                 \
+        ((bool (*)(uint_fast8_t powerState))ROM_PCMTABLE[6])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_PCM_getPowerState                                                 \
+        ((uint8_t (*)(void))ROM_PCMTABLE[8])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_PCM_gotoLPM0                                                      \
+        ((bool (*)(void))ROM_PCMTABLE[10])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_PCM_gotoLPM3                                                      \
+        ((bool (*)(void))ROM_PCMTABLE[11])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_PCM_enableInterrupt                                               \
+        ((void (*)(uint32_t flags))ROM_PCMTABLE[12])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_PCM_disableInterrupt                                              \
+        ((void (*)(uint32_t flags))ROM_PCMTABLE[13])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_PCM_getInterruptStatus                                            \
+        ((uint32_t (*)(void))ROM_PCMTABLE[14])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_PCM_getEnabledInterruptStatus                                     \
+        ((uint32_t (*)(void))ROM_PCMTABLE[15])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_PCM_clearInterruptFlag                                            \
+        ((void (*)(uint32_t flags))ROM_PCMTABLE[16])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the PMAP API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_PMAP_configurePorts                                               \
+        ((void (*)(const uint8_t *portMapping,                                \
+                   uint8_t pxMAPy,                                            \
+                   uint8_t numberOfPorts,                                     \
+                   uint8_t portMapReconfigure))ROM_PMAPTABLE[0])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the PSS API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_PSS_enableHighSidePinToggle                                       \
+        ((void (*)(bool activeLow))ROM_PSSTABLE[0])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_PSS_disableHighSidePinToggle                                      \
+        ((void (*)(void))ROM_PSSTABLE[1])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_PSS_enableHighSide                                                \
+        ((void (*)(void))ROM_PSSTABLE[2])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_PSS_disableHighSide                                               \
+        ((void (*)(void))ROM_PSSTABLE[3])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_PSS_setHighSidePerformanceMode                                    \
+        ((void (*)(uint_fast8_t powerMode))ROM_PSSTABLE[6])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_PSS_getHighSidePerformanceMode                                    \
+        ((uint_fast8_t (*)(void))ROM_PSSTABLE[7])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_PSS_enableHighSideMonitor                                         \
+        ((void (*)(void))ROM_PSSTABLE[10])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_PSS_disableHighSideMonitor                                        \
+        ((void (*)(void))ROM_PSSTABLE[11])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_PSS_setHighSideVoltageTrigger                                     \
+        ((void (*)(uint_fast8_t triggerVoltage))ROM_PSSTABLE[12])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_PSS_getHighSideVoltageTrigger                                     \
+        ((uint_fast8_t (*)(void))ROM_PSSTABLE[13])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_PSS_enableInterrupt                                               \
+        ((void (*)(void))ROM_PSSTABLE[14])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_PSS_disableInterrupt                                              \
+        ((void (*)(void))ROM_PSSTABLE[15])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_PSS_getInterruptStatus                                            \
+        ((uint32_t (*)(void))ROM_PSSTABLE[16])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_PSS_clearInterruptFlag                                            \
+        ((void (*)(void))ROM_PSSTABLE[17])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Ref API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_REF_A_setReferenceVoltage                                         \
+        ((void (*)(uint_fast8_t referenceVoltageSelect))ROM_REFTABLE[0])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_REF_A_disableTempSensor                                           \
+        ((void (*)(void))ROM_REFTABLE[1])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_REF_A_enableTempSensor                                            \
+        ((void (*)(void))ROM_REFTABLE[2])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_REF_A_enableReferenceVoltageOutput                                \
+        ((void (*)(void))ROM_REFTABLE[3])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_REF_A_disableReferenceVoltageOutput                               \
+        ((void (*)(void))ROM_REFTABLE[4])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_REF_A_enableReferenceVoltage                                      \
+        ((void (*)(void))ROM_REFTABLE[5])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_REF_A_disableReferenceVoltage                                     \
+        ((void (*)(void))ROM_REFTABLE[6])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_REF_A_getBandgapMode                                              \
+        ((uint_fast8_t (*)(void))ROM_REFTABLE[7])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_REF_A_isBandgapActive                                             \
+        ((bool (*)(void))ROM_REFTABLE[8])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_REF_A_isRefGenBusy                                                \
+        ((bool (*)(void))ROM_REFTABLE[9])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_REF_A_isRefGenActive                                              \
+        ((bool (*)(void))ROM_REFTABLE[10])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_REF_A_getBufferedBandgapVoltageStatus                             \
+        ((bool (*)(void))ROM_REFTABLE[11])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_REF_A_getVariableReferenceVoltageStatus                           \
+        ((bool (*)(void))ROM_REFTABLE[12])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_REF_A_setReferenceVoltageOneTimeTrigger                           \
+        ((void (*)(void))ROM_REFTABLE[13])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_REF_A_setBufferedBandgapVoltageOneTimeTrigger                     \
+        ((void (*)(void))ROM_REFTABLE[14])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the ResetCtl API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ResetCtl_initiateSoftReset                                        \
+        ((void (*)(void))ROM_RESETCTLTABLE[0])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ResetCtl_initiateSoftResetWithSource                              \
+        ((void (*)(uint32_t source))ROM_RESETCTLTABLE[1])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ResetCtl_getSoftResetSource                                       \
+        ((uint32_t (*)(void))ROM_RESETCTLTABLE[2])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ResetCtl_clearSoftResetSource                                     \
+        ((void (*)(uint32_t mask))ROM_RESETCTLTABLE[3])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ResetCtl_initiateHardReset                                        \
+        ((void (*)(void))ROM_RESETCTLTABLE[4])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ResetCtl_initiateHardResetWithSource                              \
+        ((void (*)(uint32_t source))ROM_RESETCTLTABLE[5])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ResetCtl_getHardResetSource                                       \
+        ((uint32_t (*)(void))ROM_RESETCTLTABLE[6])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ResetCtl_clearHardResetSource                                     \
+        ((void (*)(uint32_t mask))ROM_RESETCTLTABLE[7])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ResetCtl_getPSSSource                                             \
+        ((uint32_t (*)(void))ROM_RESETCTLTABLE[8])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ResetCtl_clearPSSFlags                                            \
+        ((void (*)(void))ROM_RESETCTLTABLE[9])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ResetCtl_getPCMSource                                             \
+        ((uint32_t (*)(void))ROM_RESETCTLTABLE[10])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_ResetCtl_clearPCMFlags                                            \
+        ((void (*)(void))ROM_RESETCTLTABLE[11])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the RTC API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_RTC_C_startClock                                                  \
+        ((void (*)(void))ROM_RTCTABLE[0])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_RTC_C_holdClock                                                   \
+        ((void (*)(void))ROM_RTCTABLE[1])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_RTC_C_setCalibrationFrequency                                     \
+        ((void (*)(uint_fast16_t frequencySelect))ROM_RTCTABLE[2])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_RTC_C_setCalibrationData                                          \
+        ((void (*)(uint_fast8_t offsetDirection,                              \
+                   uint_fast8_t offsetValue))ROM_RTCTABLE[3])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_RTC_C_setTemperatureCompensation                                  \
+        ((bool (*)(uint_fast16_t offsetDirection,                             \
+                   uint_fast8_t offsetValue))ROM_RTCTABLE[4])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_RTC_C_initCalendar                                                \
+        ((void (*)(const RTC_C_Calendar *calendarTime,                        \
+                   uint_fast16_t formatSelect))ROM_RTCTABLE[5])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_RTC_C_getCalendarTime                                             \
+        ((RTC_C_Calendar (*)(void))ROM_RTCTABLE[6])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_RTC_C_setCalendarAlarm                                            \
+        ((void (*)(uint_fast8_t minutesAlarm,                                 \
+                   uint_fast8_t hoursAlarm,                                   \
+                   uint_fast8_t dayOfWeekAlarm,                               \
+                   uint_fast8_t dayOfmonthAlarm))ROM_RTCTABLE[7])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_RTC_C_setCalendarEvent                                            \
+        ((void (*)(uint_fast16_t eventSelect))ROM_RTCTABLE[8])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_RTC_C_definePrescaleEvent                                         \
+        ((void (*)(uint_fast8_t prescaleSelect,                               \
+                   uint_fast8_t prescaleEventDivider))ROM_RTCTABLE[9])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_RTC_C_convertBCDToBinary                                          \
+        ((uint16_t (*)(uint16_t valueToConvert))ROM_RTCTABLE[12])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_RTC_C_convertBinaryToBCD                                          \
+        ((uint16_t (*)(uint16_t valueToConvert))ROM_RTCTABLE[13])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_RTC_C_enableInterrupt                                             \
+        ((void (*)(uint8_t interruptMask))ROM_RTCTABLE[14])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_RTC_C_disableInterrupt                                            \
+        ((void (*)(uint8_t interruptMask))ROM_RTCTABLE[15])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_RTC_C_getInterruptStatus                                          \
+        ((uint_fast8_t (*)(void))ROM_RTCTABLE[16])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_RTC_C_getEnabledInterruptStatus                                   \
+        ((uint_fast8_t (*)(void))ROM_RTCTABLE[17])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_RTC_C_clearInterruptFlag                                          \
+        ((void (*)(uint_fast8_t interruptFlagMask))ROM_RTCTABLE[18])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the SPI API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_SPI_initMaster                                                    \
+        ((bool (*)(uint32_t moduleInstance,                                   \
+                   const eUSCI_SPI_MasterConfig *config))ROM_SPITABLE[0])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_SPI_selectFourPinFunctionality                                    \
+        ((void (*)(uint32_t moduleInstance,                                   \
+                   uint_fast8_t select4PinFunctionality))ROM_SPITABLE[1])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_SPI_changeMasterClock                                             \
+        ((void (*)(uint32_t moduleInstance,                                   \
+                   uint32_t clockSourceFrequency,                             \
+                   uint32_t desiredSpiClock))ROM_SPITABLE[2])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_SPI_initSlave                                                     \
+        ((bool (*)(uint32_t moduleInstance,                                   \
+                   const eUSCI_SPI_SlaveConfig *config))ROM_SPITABLE[3])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_SPI_changeClockPhasePolarity                                      \
+        ((void (*)(uint32_t moduleInstance,                                   \
+                   uint_fast16_t clockPhase,                                  \
+                   uint_fast16_t clockPolarity))ROM_SPITABLE[4])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_SPI_transmitData                                                  \
+        ((void (*)(uint32_t moduleInstance,                                   \
+                   uint_fast8_t transmitData))ROM_SPITABLE[5])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_SPI_receiveData                                                   \
+        ((uint8_t (*)(uint32_t moduleInstance))ROM_SPITABLE[6])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_SPI_enableModule                                                  \
+        ((void (*)(uint32_t moduleInstance))ROM_SPITABLE[7])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_SPI_disableModule                                                 \
+        ((void (*)(uint32_t moduleInstance))ROM_SPITABLE[8])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_SPI_getReceiveBufferAddressForDMA                                 \
+        ((uint32_t (*)(uint32_t moduleInstance))ROM_SPITABLE[9])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_SPI_getTransmitBufferAddressForDMA                                \
+        ((uint32_t (*)(uint32_t moduleInstance))ROM_SPITABLE[10])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_SPI_isBusy                                                        \
+        ((uint_fast8_t (*)(uint32_t moduleInstance))ROM_SPITABLE[11])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_SPI_enableInterrupt                                               \
+        ((void (*)(uint32_t moduleInstance,                                   \
+                   uint_fast8_t mask))ROM_SPITABLE[12])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_SPI_disableInterrupt                                              \
+        ((void (*)(uint32_t moduleInstance,                                   \
+                   uint_fast8_t mask))ROM_SPITABLE[13])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_SPI_getEnabledInterruptStatus                                     \
+        ((uint_fast8_t (*)(uint32_t moduleInstance))ROM_SPITABLE[15])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_SPI_clearInterruptFlag                                            \
+        ((void (*)(uint32_t moduleInstance,                                   \
+                   uint_fast8_t mask))ROM_SPITABLE[16])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the SysCtl API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_SysCtl_getSRAMSize                                                \
+        ((uint_least32_t (*)(void))ROM_SYSCTLTABLE[0])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_SysCtl_getFlashSize                                               \
+        ((uint_least32_t (*)(void))ROM_SYSCTLTABLE[1])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_SysCtl_rebootDevice                                               \
+        ((void (*)(void))ROM_SYSCTLTABLE[2])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_SysCtl_enablePeripheralAtCPUHalt                                  \
+        ((void (*)(uint_fast16_t devices))ROM_SYSCTLTABLE[7])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_SysCtl_disablePeripheralAtCPUHalt                                 \
+        ((void (*)(uint_fast16_t devices))ROM_SYSCTLTABLE[8])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_SysCtl_setWDTTimeoutResetType                                     \
+        ((void (*)(uint_fast8_t resetType))ROM_SYSCTLTABLE[9])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_SysCtl_setWDTPasswordViolationResetType                           \
+        ((void (*)(uint_fast8_t resetType))ROM_SYSCTLTABLE[10])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_SysCtl_disableNMISource                                           \
+        ((void (*)(uint_fast8_t flags))ROM_SYSCTLTABLE[11])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_SysCtl_enableNMISource                                            \
+        ((void (*)(uint_fast8_t flags))ROM_SYSCTLTABLE[12])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_SysCtl_getNMISourceStatus                                         \
+        ((uint_fast8_t (*)(void))ROM_SYSCTLTABLE[13])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the SysTick API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_SysTick_enableModule                                              \
+        ((void (*)(void))ROM_SYSTICKTABLE[0])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_SysTick_disableModule                                             \
+        ((void (*)(void))ROM_SYSTICKTABLE[1])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_SysTick_enableInterrupt                                           \
+        ((void (*)(void))ROM_SYSTICKTABLE[2])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_SysTick_disableInterrupt                                          \
+        ((void (*)(void))ROM_SYSTICKTABLE[3])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_SysTick_setPeriod                                                 \
+        ((void (*)(uint32_t period))ROM_SYSTICKTABLE[4])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_SysTick_getPeriod                                                 \
+        ((uint32_t (*)(void))ROM_SYSTICKTABLE[5])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_SysTick_getValue                                                  \
+        ((uint32_t (*)(void))ROM_SYSTICKTABLE[6])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Timer_A API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Timer_A_startCounter                                              \
+        ((void (*)(uint32_t timer,                                            \
+                   uint_fast16_t timerMode))ROM_TIMER_ATABLE[0])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Timer_A_configureContinuousMode                                   \
+        ((void (*)(uint32_t timer,                                            \
+                   const Timer_A_ContinuousModeConfig *config))ROM_TIMER_ATABLE[1])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Timer_A_configureUpMode                                           \
+        ((void (*)(uint32_t timer,                                            \
+                   const Timer_A_UpModeConfig *config))ROM_TIMER_ATABLE[2])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Timer_A_configureUpDownMode                                       \
+        ((void (*)(uint32_t timer,                                            \
+                   const Timer_A_UpDownModeConfig *config))ROM_TIMER_ATABLE[3])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Timer_A_initCapture                                               \
+        ((void (*)(uint32_t timer,                                            \
+                   const Timer_A_CaptureModeConfig *config))ROM_TIMER_ATABLE[4])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Timer_A_initCompare                                               \
+        ((void (*)(uint32_t timer,                                            \
+                   const Timer_A_CompareModeConfig *config))ROM_TIMER_ATABLE[5])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Timer_A_clearTimer                                                \
+        ((void (*)(uint32_t timer))ROM_TIMER_ATABLE[6])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Timer_A_getSynchronizedCaptureCompareInput                        \
+        ((uint_fast8_t (*)(uint32_t timer,                                    \
+                           uint_fast16_t captureCompareRegister,              \
+                           uint_fast16_t synchronizedSetting))ROM_TIMER_ATABLE[7])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Timer_A_getOutputForOutputModeOutBitValue                         \
+        ((uint_fast8_t (*)(uint32_t timer,                                    \
+                           uint_fast16_t captureCompareRegister))ROM_TIMER_ATABLE[8])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Timer_A_getCaptureCompareCount                                    \
+        ((uint_fast16_t (*)(uint32_t timer,                                   \
+                            uint_fast16_t captureCompareRegister))ROM_TIMER_ATABLE[9])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Timer_A_setOutputForOutputModeOutBitValue                         \
+        ((void (*)(uint32_t timer,                                            \
+                   uint_fast16_t captureCompareRegister,                      \
+                   uint_fast8_t outputModeOutBitValue))ROM_TIMER_ATABLE[10])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Timer_A_generatePWM                                               \
+        ((void (*)(uint32_t timer,                                            \
+                   const Timer_A_PWMConfig *config))ROM_TIMER_ATABLE[11])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Timer_A_stopTimer                                                 \
+        ((void (*)(uint32_t timer))ROM_TIMER_ATABLE[12])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Timer_A_setCompareValue                                           \
+        ((void (*)(uint32_t timer,                                            \
+                   uint_fast16_t compareRegister,                             \
+                   uint_fast16_t compareValue))ROM_TIMER_ATABLE[13])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Timer_A_clearInterruptFlag                                        \
+        ((void (*)(uint32_t timer))ROM_TIMER_ATABLE[14])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Timer_A_clearCaptureCompareInterrupt                              \
+        ((void (*)(uint32_t timer,                                            \
+                   uint_fast16_t captureCompareRegister))ROM_TIMER_ATABLE[15])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Timer_A_enableInterrupt                                           \
+        ((void (*)(uint32_t timer))ROM_TIMER_ATABLE[16])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Timer_A_disableInterrupt                                          \
+        ((void (*)(uint32_t timer))ROM_TIMER_ATABLE[17])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Timer_A_getInterruptStatus                                        \
+        ((uint32_t (*)(uint32_t timer))ROM_TIMER_ATABLE[18])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Timer_A_getEnabledInterruptStatus                                 \
+        ((uint32_t (*)(uint32_t timer))ROM_TIMER_ATABLE[19])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Timer_A_enableCaptureCompareInterrupt                             \
+        ((void (*)(uint32_t timer,                                            \
+                   uint_fast16_t captureCompareRegister))ROM_TIMER_ATABLE[20])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Timer_A_disableCaptureCompareInterrupt                            \
+        ((void (*)(uint32_t timer,                                            \
+                   uint_fast16_t captureCompareRegister))ROM_TIMER_ATABLE[21])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Timer_A_getCaptureCompareInterruptStatus                          \
+        (( (*)(,                                                              \
+              ))ROM_TIMER_ATABLE[22])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Timer_A_getCaptureCompareEnabledInterruptStatus                   \
+        ((uint32_t (*)(uint32_t timer,                                        \
+                       uint_fast16_t captureCompareRegister))ROM_TIMER_ATABLE[23])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Timer32 API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Timer32_initModule                                                \
+        ((void (*)(uint32_t timer,                                            \
+                   uint32_t preScaler,                                        \
+                   uint32_t resolution,                                       \
+                   uint32_t mode))ROM_TIMER32TABLE[0])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Timer32_setCount                                                  \
+        ((void (*)(uint32_t timer,                                            \
+                   uint32_t count))ROM_TIMER32TABLE[1])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Timer32_setCountInBackground                                      \
+        ((void (*)(uint32_t timer,                                            \
+                   uint32_t count))ROM_TIMER32TABLE[2])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Timer32_getValue                                                  \
+        ((uint32_t (*)(uint32_t timer))ROM_TIMER32TABLE[3])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Timer32_startTimer                                                \
+        ((void (*)(uint32_t timer,                                            \
+                   bool oneShot))ROM_TIMER32TABLE[4])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Timer32_haltTimer                                                 \
+        ((void (*)(uint32_t timer))ROM_TIMER32TABLE[5])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Timer32_enableInterrupt                                           \
+        ((void (*)(uint32_t timer))ROM_TIMER32TABLE[6])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Timer32_disableInterrupt                                          \
+        ((void (*)(uint32_t timer))ROM_TIMER32TABLE[7])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Timer32_clearInterruptFlag                                        \
+        ((void (*)(uint32_t timer))ROM_TIMER32TABLE[8])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_Timer32_getInterruptStatus                                        \
+        ((uint32_t (*)(uint32_t timer))ROM_TIMER32TABLE[9])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the UART API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_UART_initModule                                                   \
+        ((bool (*)(uint32_t moduleInstance,                                   \
+                   const eUSCI_UART_Config *config))ROM_UARTTABLE[0])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_UART_transmitData                                                 \
+        ((void (*)(uint32_t moduleInstance,                                   \
+                   uint_fast8_t transmitData))ROM_UARTTABLE[1])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_UART_enableModule                                                 \
+        ((void (*)(uint32_t moduleInstance))ROM_UARTTABLE[2])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_UART_disableModule                                                \
+        ((void (*)(uint32_t moduleInstance))ROM_UARTTABLE[3])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_UART_queryStatusFlags                                             \
+        ((uint_fast8_t (*)(uint32_t moduleInstance,                           \
+                           uint_fast8_t mask))ROM_UARTTABLE[4])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_UART_setDormant                                                   \
+        ((void (*)(uint32_t moduleInstance))ROM_UARTTABLE[5])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_UART_resetDormant                                                 \
+        ((void (*)(uint32_t moduleInstance))ROM_UARTTABLE[6])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_UART_transmitAddress                                              \
+        ((void (*)(uint32_t moduleInstance,                                   \
+                   uint_fast8_t transmitAddress))ROM_UARTTABLE[7])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_UART_transmitBreak                                                \
+        ((void (*)(uint32_t moduleInstance))ROM_UARTTABLE[8])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_UART_getReceiveBufferAddressForDMA                                \
+        ((uint32_t (*)(uint32_t moduleInstance))ROM_UARTTABLE[9])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_UART_getTransmitBufferAddressForDMA                               \
+        ((uint32_t (*)(uint32_t moduleInstance))ROM_UARTTABLE[10])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_UART_selectDeglitchTime                                           \
+        ((void (*)(uint32_t moduleInstance,                                   \
+                   uint32_t deglitchTime))ROM_UARTTABLE[11])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_UART_enableInterrupt                                              \
+        ((void (*)(uint32_t moduleInstance,                                   \
+                   uint_fast8_t mask))ROM_UARTTABLE[12])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_UART_disableInterrupt                                             \
+        ((void (*)(uint32_t moduleInstance,                                   \
+                   uint_fast8_t mask))ROM_UARTTABLE[13])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_UART_clearInterruptFlag                                           \
+        ((void (*)(uint32_t moduleInstance,                                   \
+                   uint_fast8_t mask))ROM_UARTTABLE[15])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_UART_receiveData                                                  \
+        ((uint8_t (*)(uint32_t moduleInstance))ROM_UARTTABLE[16])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_UART_getEnabledInterruptStatus                                    \
+        ((uint_fast8_t (*)(uint32_t moduleInstance))ROM_UARTTABLE[17])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the WDT API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_WDT_A_holdTimer                                                   \
+        ((void (*)(void))ROM_WDTTABLE[0])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_WDT_A_startTimer                                                  \
+        ((void (*)(void))ROM_WDTTABLE[1])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_WDT_A_clearTimer                                                  \
+        ((void (*)(void))ROM_WDTTABLE[2])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_WDT_A_initWatchdogTimer                                           \
+        ((void (*)(uint_fast8_t clockSelect,                                  \
+                   uint_fast8_t clockDivider))ROM_WDTTABLE[3])
+#endif
+#if defined(TARGET_IS_MSP432P4XX)
+#define ROM_WDT_A_initIntervalTimer                                           \
+        ((void (*)(uint_fast8_t clockSelect,                                  \
+                   uint_fast8_t clockDivider))ROM_WDTTABLE[4])
+#endif
+
+#endif // __ROM_H__
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rom_map.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rom_map.h
new file mode 100644
index 000000000..5f654c809
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rom_map.h
@@ -0,0 +1,3438 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __ROM_MAP_H__
+#define __ROM_MAP_H__
+
+//*****************************************************************************
+//
+// Macros for the ADC14 API.
+//
+//*****************************************************************************
+#ifdef ROM_ADC14_enableModule
+#define MAP_ADC14_enableModule                                                \
+        ROM_ADC14_enableModule
+#else
+#define MAP_ADC14_enableModule                                                \
+        ADC14_enableModule
+#endif
+#ifdef ROM_ADC14_disableModule
+#define MAP_ADC14_disableModule                                               \
+        ROM_ADC14_disableModule
+#else
+#define MAP_ADC14_disableModule                                               \
+        ADC14_disableModule
+#endif
+#ifdef ROM_ADC14_initModule
+#define MAP_ADC14_initModule                                                  \
+        ROM_ADC14_initModule
+#else
+#define MAP_ADC14_initModule                                                  \
+        ADC14_initModule
+#endif
+#ifdef ROM_ADC14_setResolution
+#define MAP_ADC14_setResolution                                               \
+        ROM_ADC14_setResolution
+#else
+#define MAP_ADC14_setResolution                                               \
+        ADC14_setResolution
+#endif
+#ifdef ROM_ADC14_getResolution
+#define MAP_ADC14_getResolution                                               \
+        ROM_ADC14_getResolution
+#else
+#define MAP_ADC14_getResolution                                               \
+        ADC14_getResolution
+#endif
+#ifdef ROM_ADC14_setSampleHoldTrigger
+#define MAP_ADC14_setSampleHoldTrigger                                        \
+        ROM_ADC14_setSampleHoldTrigger
+#else
+#define MAP_ADC14_setSampleHoldTrigger                                        \
+        ADC14_setSampleHoldTrigger
+#endif
+#ifdef ROM_ADC14_setSampleHoldTime
+#define MAP_ADC14_setSampleHoldTime                                           \
+        ROM_ADC14_setSampleHoldTime
+#else
+#define MAP_ADC14_setSampleHoldTime                                           \
+        ADC14_setSampleHoldTime
+#endif
+#ifdef ROM_ADC14_configureMultiSequenceMode
+#define MAP_ADC14_configureMultiSequenceMode                                  \
+        ROM_ADC14_configureMultiSequenceMode
+#else
+#define MAP_ADC14_configureMultiSequenceMode                                  \
+        ADC14_configureMultiSequenceMode
+#endif
+#ifdef ROM_ADC14_configureSingleSampleMode
+#define MAP_ADC14_configureSingleSampleMode                                   \
+        ROM_ADC14_configureSingleSampleMode
+#else
+#define MAP_ADC14_configureSingleSampleMode                                   \
+        ADC14_configureSingleSampleMode
+#endif
+#ifdef ROM_ADC14_enableConversion
+#define MAP_ADC14_enableConversion                                            \
+        ROM_ADC14_enableConversion
+#else
+#define MAP_ADC14_enableConversion                                            \
+        ADC14_enableConversion
+#endif
+#ifdef ROM_ADC14_disableConversion
+#define MAP_ADC14_disableConversion                                           \
+        ROM_ADC14_disableConversion
+#else
+#define MAP_ADC14_disableConversion                                           \
+        ADC14_disableConversion
+#endif
+#ifdef ROM_ADC14_isBusy
+#define MAP_ADC14_isBusy                                                      \
+        ROM_ADC14_isBusy
+#else
+#define MAP_ADC14_isBusy                                                      \
+        ADC14_isBusy
+#endif
+#ifdef ROM_ADC14_configureConversionMemory
+#define MAP_ADC14_configureConversionMemory                                   \
+        ROM_ADC14_configureConversionMemory
+#else
+#define MAP_ADC14_configureConversionMemory                                   \
+        ADC14_configureConversionMemory
+#endif
+#ifdef ROM_ADC14_enableComparatorWindow
+#define MAP_ADC14_enableComparatorWindow                                      \
+        ROM_ADC14_enableComparatorWindow
+#else
+#define MAP_ADC14_enableComparatorWindow                                      \
+        ADC14_enableComparatorWindow
+#endif
+#ifdef ROM_ADC14_disableComparatorWindow
+#define MAP_ADC14_disableComparatorWindow                                     \
+        ROM_ADC14_disableComparatorWindow
+#else
+#define MAP_ADC14_disableComparatorWindow                                     \
+        ADC14_disableComparatorWindow
+#endif
+#ifdef ROM_ADC14_setComparatorWindowValue
+#define MAP_ADC14_setComparatorWindowValue                                    \
+        ROM_ADC14_setComparatorWindowValue
+#else
+#define MAP_ADC14_setComparatorWindowValue                                    \
+        ADC14_setComparatorWindowValue
+#endif
+#ifdef ROM_ADC14_setResultFormat
+#define MAP_ADC14_setResultFormat                                             \
+        ROM_ADC14_setResultFormat
+#else
+#define MAP_ADC14_setResultFormat                                             \
+        ADC14_setResultFormat
+#endif
+#ifdef ROM_ADC14_getResult
+#define MAP_ADC14_getResult                                                   \
+        ROM_ADC14_getResult
+#else
+#define MAP_ADC14_getResult                                                   \
+        ADC14_getResult
+#endif
+#ifdef ROM_ADC14_getMultiSequenceResult
+#define MAP_ADC14_getMultiSequenceResult                                      \
+        ROM_ADC14_getMultiSequenceResult
+#else
+#define MAP_ADC14_getMultiSequenceResult                                      \
+        ADC14_getMultiSequenceResult
+#endif
+#ifdef ROM_ADC14_getResultArray
+#define MAP_ADC14_getResultArray                                              \
+        ROM_ADC14_getResultArray
+#else
+#define MAP_ADC14_getResultArray                                              \
+        ADC14_getResultArray
+#endif
+#ifdef ROM_ADC14_enableReferenceBurst
+#define MAP_ADC14_enableReferenceBurst                                        \
+        ROM_ADC14_enableReferenceBurst
+#else
+#define MAP_ADC14_enableReferenceBurst                                        \
+        ADC14_enableReferenceBurst
+#endif
+#ifdef ROM_ADC14_disableReferenceBurst
+#define MAP_ADC14_disableReferenceBurst                                       \
+        ROM_ADC14_disableReferenceBurst
+#else
+#define MAP_ADC14_disableReferenceBurst                                       \
+        ADC14_disableReferenceBurst
+#endif
+#ifdef ROM_ADC14_setPowerMode
+#define MAP_ADC14_setPowerMode                                                \
+        ROM_ADC14_setPowerMode
+#else
+#define MAP_ADC14_setPowerMode                                                \
+        ADC14_setPowerMode
+#endif
+#ifdef ROM_ADC14_enableInterrupt
+#define MAP_ADC14_enableInterrupt                                             \
+        ROM_ADC14_enableInterrupt
+#else
+#define MAP_ADC14_enableInterrupt                                             \
+        ADC14_enableInterrupt
+#endif
+#ifdef ROM_ADC14_disableInterrupt
+#define MAP_ADC14_disableInterrupt                                            \
+        ROM_ADC14_disableInterrupt
+#else
+#define MAP_ADC14_disableInterrupt                                            \
+        ADC14_disableInterrupt
+#endif
+#ifdef ROM_ADC14_getInterruptStatus
+#define MAP_ADC14_getInterruptStatus                                          \
+        ROM_ADC14_getInterruptStatus
+#else
+#define MAP_ADC14_getInterruptStatus                                          \
+        ADC14_getInterruptStatus
+#endif
+#ifdef ROM_ADC14_getEnabledInterruptStatus
+#define MAP_ADC14_getEnabledInterruptStatus                                   \
+        ROM_ADC14_getEnabledInterruptStatus
+#else
+#define MAP_ADC14_getEnabledInterruptStatus                                   \
+        ADC14_getEnabledInterruptStatus
+#endif
+#ifdef ROM_ADC14_clearInterruptFlag
+#define MAP_ADC14_clearInterruptFlag                                          \
+        ROM_ADC14_clearInterruptFlag
+#else
+#define MAP_ADC14_clearInterruptFlag                                          \
+        ADC14_clearInterruptFlag
+#endif
+#ifdef ROM_ADC14_toggleConversionTrigger
+#define MAP_ADC14_toggleConversionTrigger                                     \
+        ROM_ADC14_toggleConversionTrigger
+#else
+#define MAP_ADC14_toggleConversionTrigger                                     \
+        ADC14_toggleConversionTrigger
+#endif
+#ifdef ROM_ADC14_enableSampleTimer
+#define MAP_ADC14_enableSampleTimer                                           \
+        ROM_ADC14_enableSampleTimer
+#else
+#define MAP_ADC14_enableSampleTimer                                           \
+        ADC14_enableSampleTimer
+#endif
+#ifdef ROM_ADC14_disableSampleTimer
+#define MAP_ADC14_disableSampleTimer                                          \
+        ROM_ADC14_disableSampleTimer
+#else
+#define MAP_ADC14_disableSampleTimer                                          \
+        ADC14_disableSampleTimer
+#endif
+#ifdef ROM_ADC14_registerInterrupt
+#define MAP_ADC14_registerInterrupt                                           \
+        ROM_ADC14_registerInterrupt
+#else
+#define MAP_ADC14_registerInterrupt                                           \
+        ADC14_registerInterrupt
+#endif
+#ifdef ROM_ADC14_unregisterInterrupt
+#define MAP_ADC14_unregisterInterrupt                                         \
+        ROM_ADC14_unregisterInterrupt
+#else
+#define MAP_ADC14_unregisterInterrupt                                         \
+        ADC14_unregisterInterrupt
+#endif
+
+//*****************************************************************************
+//
+// Macros for the AES256 API.
+//
+//*****************************************************************************
+#ifdef ROM_AES256_setCipherKey
+#define MAP_AES256_setCipherKey                                               \
+        ROM_AES256_setCipherKey
+#else
+#define MAP_AES256_setCipherKey                                               \
+        AES256_setCipherKey
+#endif
+#ifdef ROM_AES256_encryptData
+#define MAP_AES256_encryptData                                                \
+        ROM_AES256_encryptData
+#else
+#define MAP_AES256_encryptData                                                \
+        AES256_encryptData
+#endif
+#ifdef ROM_AES256_decryptData
+#define MAP_AES256_decryptData                                                \
+        ROM_AES256_decryptData
+#else
+#define MAP_AES256_decryptData                                                \
+        AES256_decryptData
+#endif
+#ifdef ROM_AES256_setDecipherKey
+#define MAP_AES256_setDecipherKey                                             \
+        ROM_AES256_setDecipherKey
+#else
+#define MAP_AES256_setDecipherKey                                             \
+        AES256_setDecipherKey
+#endif
+#ifdef ROM_AES256_reset
+#define MAP_AES256_reset                                                      \
+        ROM_AES256_reset
+#else
+#define MAP_AES256_reset                                                      \
+        AES256_reset
+#endif
+#ifdef ROM_AES256_startEncryptData
+#define MAP_AES256_startEncryptData                                           \
+        ROM_AES256_startEncryptData
+#else
+#define MAP_AES256_startEncryptData                                           \
+        AES256_startEncryptData
+#endif
+#ifdef ROM_AES256_startDecryptData
+#define MAP_AES256_startDecryptData                                           \
+        ROM_AES256_startDecryptData
+#else
+#define MAP_AES256_startDecryptData                                           \
+        AES256_startDecryptData
+#endif
+#ifdef ROM_AES256_startSetDecipherKey
+#define MAP_AES256_startSetDecipherKey                                        \
+        ROM_AES256_startSetDecipherKey
+#else
+#define MAP_AES256_startSetDecipherKey                                        \
+        AES256_startSetDecipherKey
+#endif
+#ifdef ROM_AES256_getDataOut
+#define MAP_AES256_getDataOut                                                 \
+        ROM_AES256_getDataOut
+#else
+#define MAP_AES256_getDataOut                                                 \
+        AES256_getDataOut
+#endif
+#ifdef ROM_AES256_isBusy
+#define MAP_AES256_isBusy                                                     \
+        ROM_AES256_isBusy
+#else
+#define MAP_AES256_isBusy                                                     \
+        AES256_isBusy
+#endif
+#ifdef ROM_AES256_clearErrorFlag
+#define MAP_AES256_clearErrorFlag                                             \
+        ROM_AES256_clearErrorFlag
+#else
+#define MAP_AES256_clearErrorFlag                                             \
+        AES256_clearErrorFlag
+#endif
+#ifdef ROM_AES256_getErrorFlagStatus
+#define MAP_AES256_getErrorFlagStatus                                         \
+        ROM_AES256_getErrorFlagStatus
+#else
+#define MAP_AES256_getErrorFlagStatus                                         \
+        AES256_getErrorFlagStatus
+#endif
+#ifdef ROM_AES256_clearInterruptFlag
+#define MAP_AES256_clearInterruptFlag                                         \
+        ROM_AES256_clearInterruptFlag
+#else
+#define MAP_AES256_clearInterruptFlag                                         \
+        AES256_clearInterruptFlag
+#endif
+#ifdef ROM_AES256_getInterruptStatus
+#define MAP_AES256_getInterruptStatus                                         \
+        ROM_AES256_getInterruptStatus
+#else
+#define MAP_AES256_getInterruptStatus                                         \
+        AES256_getInterruptStatus
+#endif
+#ifdef ROM_AES256_enableInterrupt
+#define MAP_AES256_enableInterrupt                                            \
+        ROM_AES256_enableInterrupt
+#else
+#define MAP_AES256_enableInterrupt                                            \
+        AES256_enableInterrupt
+#endif
+#ifdef ROM_AES256_disableInterrupt
+#define MAP_AES256_disableInterrupt                                           \
+        ROM_AES256_disableInterrupt
+#else
+#define MAP_AES256_disableInterrupt                                           \
+        AES256_disableInterrupt
+#endif
+#ifdef ROM_AES256_registerInterrupt
+#define MAP_AES256_registerInterrupt                                          \
+        ROM_AES256_registerInterrupt
+#else
+#define MAP_AES256_registerInterrupt                                          \
+        AES256_registerInterrupt
+#endif
+#ifdef ROM_AES256_unregisterInterrupt
+#define MAP_AES256_unregisterInterrupt                                        \
+        ROM_AES256_unregisterInterrupt
+#else
+#define MAP_AES256_unregisterInterrupt                                        \
+        AES256_unregisterInterrupt
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Comp API.
+//
+//*****************************************************************************
+#ifdef ROM_COMP_E_initModule
+#define MAP_COMP_E_initModule                                                 \
+        ROM_COMP_E_initModule
+#else
+#define MAP_COMP_E_initModule                                                 \
+        COMP_E_initModule
+#endif
+#ifdef ROM_COMP_E_setReferenceVoltage
+#define MAP_COMP_E_setReferenceVoltage                                        \
+        ROM_COMP_E_setReferenceVoltage
+#else
+#define MAP_COMP_E_setReferenceVoltage                                        \
+        COMP_E_setReferenceVoltage
+#endif
+#ifdef ROM_COMP_E_setReferenceAccuracy
+#define MAP_COMP_E_setReferenceAccuracy                                       \
+        ROM_COMP_E_setReferenceAccuracy
+#else
+#define MAP_COMP_E_setReferenceAccuracy                                       \
+        COMP_E_setReferenceAccuracy
+#endif
+#ifdef ROM_COMP_E_setPowerMode
+#define MAP_COMP_E_setPowerMode                                               \
+        ROM_COMP_E_setPowerMode
+#else
+#define MAP_COMP_E_setPowerMode                                               \
+        COMP_E_setPowerMode
+#endif
+#ifdef ROM_COMP_E_enableModule
+#define MAP_COMP_E_enableModule                                               \
+        ROM_COMP_E_enableModule
+#else
+#define MAP_COMP_E_enableModule                                               \
+        COMP_E_enableModule
+#endif
+#ifdef ROM_COMP_E_disableModule
+#define MAP_COMP_E_disableModule                                              \
+        ROM_COMP_E_disableModule
+#else
+#define MAP_COMP_E_disableModule                                              \
+        COMP_E_disableModule
+#endif
+#ifdef ROM_COMP_E_shortInputs
+#define MAP_COMP_E_shortInputs                                                \
+        ROM_COMP_E_shortInputs
+#else
+#define MAP_COMP_E_shortInputs                                                \
+        COMP_E_shortInputs
+#endif
+#ifdef ROM_COMP_E_unshortInputs
+#define MAP_COMP_E_unshortInputs                                              \
+        ROM_COMP_E_unshortInputs
+#else
+#define MAP_COMP_E_unshortInputs                                              \
+        COMP_E_unshortInputs
+#endif
+#ifdef ROM_COMP_E_disableInputBuffer
+#define MAP_COMP_E_disableInputBuffer                                         \
+        ROM_COMP_E_disableInputBuffer
+#else
+#define MAP_COMP_E_disableInputBuffer                                         \
+        COMP_E_disableInputBuffer
+#endif
+#ifdef ROM_COMP_E_enableInputBuffer
+#define MAP_COMP_E_enableInputBuffer                                          \
+        ROM_COMP_E_enableInputBuffer
+#else
+#define MAP_COMP_E_enableInputBuffer                                          \
+        COMP_E_enableInputBuffer
+#endif
+#ifdef ROM_COMP_E_swapIO
+#define MAP_COMP_E_swapIO                                                     \
+        ROM_COMP_E_swapIO
+#else
+#define MAP_COMP_E_swapIO                                                     \
+        COMP_E_swapIO
+#endif
+#ifdef ROM_COMP_E_outputValue
+#define MAP_COMP_E_outputValue                                                \
+        ROM_COMP_E_outputValue
+#else
+#define MAP_COMP_E_outputValue                                                \
+        COMP_E_outputValue
+#endif
+#ifdef ROM_COMP_E_enableInterrupt
+#define MAP_COMP_E_enableInterrupt                                            \
+        ROM_COMP_E_enableInterrupt
+#else
+#define MAP_COMP_E_enableInterrupt                                            \
+        COMP_E_enableInterrupt
+#endif
+#ifdef ROM_COMP_E_disableInterrupt
+#define MAP_COMP_E_disableInterrupt                                           \
+        ROM_COMP_E_disableInterrupt
+#else
+#define MAP_COMP_E_disableInterrupt                                           \
+        COMP_E_disableInterrupt
+#endif
+#ifdef ROM_COMP_E_clearInterruptFlag
+#define MAP_COMP_E_clearInterruptFlag                                         \
+        ROM_COMP_E_clearInterruptFlag
+#else
+#define MAP_COMP_E_clearInterruptFlag                                         \
+        COMP_E_clearInterruptFlag
+#endif
+#ifdef ROM_COMP_E_getInterruptStatus
+#define MAP_COMP_E_getInterruptStatus                                         \
+        ROM_COMP_E_getInterruptStatus
+#else
+#define MAP_COMP_E_getInterruptStatus                                         \
+        COMP_E_getInterruptStatus
+#endif
+#ifdef ROM_COMP_E_getEnabledInterruptStatus
+#define MAP_COMP_E_getEnabledInterruptStatus                                  \
+        ROM_COMP_E_getEnabledInterruptStatus
+#else
+#define MAP_COMP_E_getEnabledInterruptStatus                                  \
+        COMP_E_getEnabledInterruptStatus
+#endif
+#ifdef ROM_COMP_E_setInterruptEdgeDirection
+#define MAP_COMP_E_setInterruptEdgeDirection                                  \
+        ROM_COMP_E_setInterruptEdgeDirection
+#else
+#define MAP_COMP_E_setInterruptEdgeDirection                                  \
+        COMP_E_setInterruptEdgeDirection
+#endif
+#ifdef ROM_COMP_E_toggleInterruptEdgeDirection
+#define MAP_COMP_E_toggleInterruptEdgeDirection                               \
+        ROM_COMP_E_toggleInterruptEdgeDirection
+#else
+#define MAP_COMP_E_toggleInterruptEdgeDirection                               \
+        COMP_E_toggleInterruptEdgeDirection
+#endif
+#ifdef ROM_COMP_E_registerInterrupt
+#define MAP_COMP_E_registerInterrupt                                          \
+        ROM_COMP_E_registerInterrupt
+#else
+#define MAP_COMP_E_registerInterrupt                                          \
+        COMP_E_registerInterrupt
+#endif
+#ifdef ROM_COMP_E_unregisterInterrupt
+#define MAP_COMP_E_unregisterInterrupt                                        \
+        ROM_COMP_E_unregisterInterrupt
+#else
+#define MAP_COMP_E_unregisterInterrupt                                        \
+        COMP_E_unregisterInterrupt
+#endif
+
+//*****************************************************************************
+//
+// Macros for the CRC32 API.
+//
+//*****************************************************************************
+#ifdef ROM_CRC32_setSeed
+#define MAP_CRC32_setSeed                                                     \
+        ROM_CRC32_setSeed
+#else
+#define MAP_CRC32_setSeed                                                     \
+        CRC32_setSeed
+#endif
+#ifdef ROM_CRC32_set8BitData
+#define MAP_CRC32_set8BitData                                                 \
+        ROM_CRC32_set8BitData
+#else
+#define MAP_CRC32_set8BitData                                                 \
+        CRC32_set8BitData
+#endif
+#ifdef ROM_CRC32_set16BitData
+#define MAP_CRC32_set16BitData                                                \
+        ROM_CRC32_set16BitData
+#else
+#define MAP_CRC32_set16BitData                                                \
+        CRC32_set16BitData
+#endif
+#ifdef ROM_CRC32_set32BitData
+#define MAP_CRC32_set32BitData                                                \
+        ROM_CRC32_set32BitData
+#else
+#define MAP_CRC32_set32BitData                                                \
+        CRC32_set32BitData
+#endif
+#ifdef ROM_CRC32_set8BitDataReversed
+#define MAP_CRC32_set8BitDataReversed                                         \
+        ROM_CRC32_set8BitDataReversed
+#else
+#define MAP_CRC32_set8BitDataReversed                                         \
+        CRC32_set8BitDataReversed
+#endif
+#ifdef ROM_CRC32_set16BitDataReversed
+#define MAP_CRC32_set16BitDataReversed                                        \
+        ROM_CRC32_set16BitDataReversed
+#else
+#define MAP_CRC32_set16BitDataReversed                                        \
+        CRC32_set16BitDataReversed
+#endif
+#ifdef ROM_CRC32_set32BitDataReversed
+#define MAP_CRC32_set32BitDataReversed                                        \
+        ROM_CRC32_set32BitDataReversed
+#else
+#define MAP_CRC32_set32BitDataReversed                                        \
+        CRC32_set32BitDataReversed
+#endif
+#ifdef ROM_CRC32_getResult
+#define MAP_CRC32_getResult                                                   \
+        ROM_CRC32_getResult
+#else
+#define MAP_CRC32_getResult                                                   \
+        CRC32_getResult
+#endif
+#ifdef ROM_CRC32_getResultReversed
+#define MAP_CRC32_getResultReversed                                           \
+        ROM_CRC32_getResultReversed
+#else
+#define MAP_CRC32_getResultReversed                                           \
+        CRC32_getResultReversed
+#endif
+
+//*****************************************************************************
+//
+// Macros for the CS API.
+//
+//*****************************************************************************
+#ifdef ROM_CS_initClockSignal
+#define MAP_CS_initClockSignal                                                \
+        ROM_CS_initClockSignal
+#else
+#define MAP_CS_initClockSignal                                                \
+        CS_initClockSignal
+#endif
+#ifdef ROM_CS_setReferenceOscillatorFrequency
+#define MAP_CS_setReferenceOscillatorFrequency                                \
+        ROM_CS_setReferenceOscillatorFrequency
+#else
+#define MAP_CS_setReferenceOscillatorFrequency                                \
+        CS_setReferenceOscillatorFrequency
+#endif
+#ifdef ROM_CS_enableClockRequest
+#define MAP_CS_enableClockRequest                                             \
+        ROM_CS_enableClockRequest
+#else
+#define MAP_CS_enableClockRequest                                             \
+        CS_enableClockRequest
+#endif
+#ifdef ROM_CS_disableClockRequest
+#define MAP_CS_disableClockRequest                                            \
+        ROM_CS_disableClockRequest
+#else
+#define MAP_CS_disableClockRequest                                            \
+        CS_disableClockRequest
+#endif
+#ifdef ROM_CS_setDCOCenteredFrequency
+#define MAP_CS_setDCOCenteredFrequency                                        \
+        ROM_CS_setDCOCenteredFrequency
+#else
+#define MAP_CS_setDCOCenteredFrequency                                        \
+        CS_setDCOCenteredFrequency
+#endif
+#ifdef ROM_CS_tuneDCOFrequency
+#define MAP_CS_tuneDCOFrequency                                               \
+        ROM_CS_tuneDCOFrequency
+#else
+#define MAP_CS_tuneDCOFrequency                                               \
+        CS_tuneDCOFrequency
+#endif
+#ifdef ROM_CS_enableDCOExternalResistor
+#define MAP_CS_enableDCOExternalResistor                                      \
+        ROM_CS_enableDCOExternalResistor
+#else
+#define MAP_CS_enableDCOExternalResistor                                      \
+        CS_enableDCOExternalResistor
+#endif
+#ifdef ROM_CS_disableDCOExternalResistor
+#define MAP_CS_disableDCOExternalResistor                                     \
+        ROM_CS_disableDCOExternalResistor
+#else
+#define MAP_CS_disableDCOExternalResistor                                     \
+        CS_disableDCOExternalResistor
+#endif
+#ifdef ROM_CS_enableInterrupt
+#define MAP_CS_enableInterrupt                                                \
+        ROM_CS_enableInterrupt
+#else
+#define MAP_CS_enableInterrupt                                                \
+        CS_enableInterrupt
+#endif
+#ifdef ROM_CS_disableInterrupt
+#define MAP_CS_disableInterrupt                                               \
+        ROM_CS_disableInterrupt
+#else
+#define MAP_CS_disableInterrupt                                               \
+        CS_disableInterrupt
+#endif
+#ifdef ROM_CS_getEnabledInterruptStatus
+#define MAP_CS_getEnabledInterruptStatus                                      \
+        ROM_CS_getEnabledInterruptStatus
+#else
+#define MAP_CS_getEnabledInterruptStatus                                      \
+        CS_getEnabledInterruptStatus
+#endif
+#ifdef ROM_CS_getInterruptStatus
+#define MAP_CS_getInterruptStatus                                             \
+        ROM_CS_getInterruptStatus
+#else
+#define MAP_CS_getInterruptStatus                                             \
+        CS_getInterruptStatus
+#endif
+#ifdef ROM_CS_setDCOFrequency
+#define MAP_CS_setDCOFrequency                                                \
+        ROM_CS_setDCOFrequency
+#else
+#define MAP_CS_setDCOFrequency                                                \
+        CS_setDCOFrequency
+#endif
+#ifdef ROM_CS_getDCOFrequency
+#define MAP_CS_getDCOFrequency                                                \
+        ROM_CS_getDCOFrequency
+#else
+#define MAP_CS_getDCOFrequency                                                \
+        CS_getDCOFrequency
+#endif
+#ifdef ROM_CS_enableFaultCounter
+#define MAP_CS_enableFaultCounter                                             \
+        ROM_CS_enableFaultCounter
+#else
+#define MAP_CS_enableFaultCounter                                             \
+        CS_enableFaultCounter
+#endif
+#ifdef ROM_CS_disableFaultCounter
+#define MAP_CS_disableFaultCounter                                            \
+        ROM_CS_disableFaultCounter
+#else
+#define MAP_CS_disableFaultCounter                                            \
+        CS_disableFaultCounter
+#endif
+#ifdef ROM_CS_resetFaultCounter
+#define MAP_CS_resetFaultCounter                                              \
+        ROM_CS_resetFaultCounter
+#else
+#define MAP_CS_resetFaultCounter                                              \
+        CS_resetFaultCounter
+#endif
+#ifdef ROM_CS_startFaultCounter
+#define MAP_CS_startFaultCounter                                              \
+        ROM_CS_startFaultCounter
+#else
+#define MAP_CS_startFaultCounter                                              \
+        CS_startFaultCounter
+#endif
+#ifdef ROM_CS_registerInterrupt
+#define MAP_CS_registerInterrupt                                              \
+        ROM_CS_registerInterrupt
+#else
+#define MAP_CS_registerInterrupt                                              \
+        CS_registerInterrupt
+#endif
+#ifdef ROM_CS_unregisterInterrupt
+#define MAP_CS_unregisterInterrupt                                            \
+        ROM_CS_unregisterInterrupt
+#else
+#define MAP_CS_unregisterInterrupt                                            \
+        CS_unregisterInterrupt
+#endif
+#ifdef ROM_CS_clearInterruptFlag
+#define MAP_CS_clearInterruptFlag                                             \
+        ROM_CS_clearInterruptFlag
+#else
+#define MAP_CS_clearInterruptFlag                                             \
+        CS_clearInterruptFlag
+#endif
+#ifdef ROM_CS_getACLK
+#define MAP_CS_getACLK                                                        \
+        ROM_CS_getACLK
+#else
+#define MAP_CS_getACLK                                                        \
+        CS_getACLK
+#endif
+#ifdef ROM_CS_getSMCLK
+#define MAP_CS_getSMCLK                                                       \
+        ROM_CS_getSMCLK
+#else
+#define MAP_CS_getSMCLK                                                       \
+        CS_getSMCLK
+#endif
+#ifdef ROM_CS_getMCLK
+#define MAP_CS_getMCLK                                                        \
+        ROM_CS_getMCLK
+#else
+#define MAP_CS_getMCLK                                                        \
+        CS_getMCLK
+#endif
+#ifdef ROM_CS_getBCLK
+#define MAP_CS_getBCLK                                                        \
+        ROM_CS_getBCLK
+#else
+#define MAP_CS_getBCLK                                                        \
+        CS_getBCLK
+#endif
+#ifdef ROM_CS_getHSMCLK
+#define MAP_CS_getHSMCLK                                                      \
+        ROM_CS_getHSMCLK
+#else
+#define MAP_CS_getHSMCLK                                                      \
+        CS_getHSMCLK
+#endif
+#ifdef ROM_CS_startHFXT
+#define MAP_CS_startHFXT                                                      \
+        ROM_CS_startHFXT
+#else
+#define MAP_CS_startHFXT                                                      \
+        CS_startHFXT
+#endif
+#ifdef ROM_CS_startHFXTWithTimeout
+#define MAP_CS_startHFXTWithTimeout                                           \
+        ROM_CS_startHFXTWithTimeout
+#else
+#define MAP_CS_startHFXTWithTimeout                                           \
+        CS_startHFXTWithTimeout
+#endif
+#ifdef ROM_CS_startLFXT
+#define MAP_CS_startLFXT                                                      \
+        ROM_CS_startLFXT
+#else
+#define MAP_CS_startLFXT                                                      \
+        CS_startLFXT
+#endif
+#ifdef ROM_CS_startLFXTWithTimeout
+#define MAP_CS_startLFXTWithTimeout                                           \
+        ROM_CS_startLFXTWithTimeout
+#else
+#define MAP_CS_startLFXTWithTimeout                                           \
+        CS_startLFXTWithTimeout
+#endif
+#ifdef ROM_CS_setExternalClockSourceFrequency
+#define MAP_CS_setExternalClockSourceFrequency                                \
+        ROM_CS_setExternalClockSourceFrequency
+#else
+#define MAP_CS_setExternalClockSourceFrequency                                \
+        CS_setExternalClockSourceFrequency
+#endif
+
+//*****************************************************************************
+//
+// Macros for the DMA API.
+//
+//*****************************************************************************
+#ifdef ROM_DMA_enableModule
+#define MAP_DMA_enableModule                                                  \
+        ROM_DMA_enableModule
+#else
+#define MAP_DMA_enableModule                                                  \
+        DMA_enableModule
+#endif
+#ifdef ROM_DMA_disableModule
+#define MAP_DMA_disableModule                                                 \
+        ROM_DMA_disableModule
+#else
+#define MAP_DMA_disableModule                                                 \
+        DMA_disableModule
+#endif
+#ifdef ROM_DMA_getErrorStatus
+#define MAP_DMA_getErrorStatus                                                \
+        ROM_DMA_getErrorStatus
+#else
+#define MAP_DMA_getErrorStatus                                                \
+        DMA_getErrorStatus
+#endif
+#ifdef ROM_DMA_clearErrorStatus
+#define MAP_DMA_clearErrorStatus                                              \
+        ROM_DMA_clearErrorStatus
+#else
+#define MAP_DMA_clearErrorStatus                                              \
+        DMA_clearErrorStatus
+#endif
+#ifdef ROM_DMA_enableChannel
+#define MAP_DMA_enableChannel                                                 \
+        ROM_DMA_enableChannel
+#else
+#define MAP_DMA_enableChannel                                                 \
+        DMA_enableChannel
+#endif
+#ifdef ROM_DMA_disableChannel
+#define MAP_DMA_disableChannel                                                \
+        ROM_DMA_disableChannel
+#else
+#define MAP_DMA_disableChannel                                                \
+        DMA_disableChannel
+#endif
+#ifdef ROM_DMA_isChannelEnabled
+#define MAP_DMA_isChannelEnabled                                              \
+        ROM_DMA_isChannelEnabled
+#else
+#define MAP_DMA_isChannelEnabled                                              \
+        DMA_isChannelEnabled
+#endif
+#ifdef ROM_DMA_setControlBase
+#define MAP_DMA_setControlBase                                                \
+        ROM_DMA_setControlBase
+#else
+#define MAP_DMA_setControlBase                                                \
+        DMA_setControlBase
+#endif
+#ifdef ROM_DMA_getControlBase
+#define MAP_DMA_getControlBase                                                \
+        ROM_DMA_getControlBase
+#else
+#define MAP_DMA_getControlBase                                                \
+        DMA_getControlBase
+#endif
+#ifdef ROM_DMA_getControlAlternateBase
+#define MAP_DMA_getControlAlternateBase                                       \
+        ROM_DMA_getControlAlternateBase
+#else
+#define MAP_DMA_getControlAlternateBase                                       \
+        DMA_getControlAlternateBase
+#endif
+#ifdef ROM_DMA_requestChannel
+#define MAP_DMA_requestChannel                                                \
+        ROM_DMA_requestChannel
+#else
+#define MAP_DMA_requestChannel                                                \
+        DMA_requestChannel
+#endif
+#ifdef ROM_DMA_enableChannelAttribute
+#define MAP_DMA_enableChannelAttribute                                        \
+        ROM_DMA_enableChannelAttribute
+#else
+#define MAP_DMA_enableChannelAttribute                                        \
+        DMA_enableChannelAttribute
+#endif
+#ifdef ROM_DMA_disableChannelAttribute
+#define MAP_DMA_disableChannelAttribute                                       \
+        ROM_DMA_disableChannelAttribute
+#else
+#define MAP_DMA_disableChannelAttribute                                       \
+        DMA_disableChannelAttribute
+#endif
+#ifdef ROM_DMA_getChannelAttribute
+#define MAP_DMA_getChannelAttribute                                           \
+        ROM_DMA_getChannelAttribute
+#else
+#define MAP_DMA_getChannelAttribute                                           \
+        DMA_getChannelAttribute
+#endif
+#ifdef ROM_DMA_setChannelControl
+#define MAP_DMA_setChannelControl                                             \
+        ROM_DMA_setChannelControl
+#else
+#define MAP_DMA_setChannelControl                                             \
+        DMA_setChannelControl
+#endif
+#ifdef ROM_DMA_setChannelTransfer
+#define MAP_DMA_setChannelTransfer                                            \
+        ROM_DMA_setChannelTransfer
+#else
+#define MAP_DMA_setChannelTransfer                                            \
+        DMA_setChannelTransfer
+#endif
+#ifdef ROM_DMA_setChannelScatterGather
+#define MAP_DMA_setChannelScatterGather                                       \
+        ROM_DMA_setChannelScatterGather
+#else
+#define MAP_DMA_setChannelScatterGather                                       \
+        DMA_setChannelScatterGather
+#endif
+#ifdef ROM_DMA_getChannelSize
+#define MAP_DMA_getChannelSize                                                \
+        ROM_DMA_getChannelSize
+#else
+#define MAP_DMA_getChannelSize                                                \
+        DMA_getChannelSize
+#endif
+#ifdef ROM_DMA_getChannelMode
+#define MAP_DMA_getChannelMode                                                \
+        ROM_DMA_getChannelMode
+#else
+#define MAP_DMA_getChannelMode                                                \
+        DMA_getChannelMode
+#endif
+#ifdef ROM_DMA_assignChannel
+#define MAP_DMA_assignChannel                                                 \
+        ROM_DMA_assignChannel
+#else
+#define MAP_DMA_assignChannel                                                 \
+        DMA_assignChannel
+#endif
+#ifdef ROM_DMA_requestSoftwareTransfer
+#define MAP_DMA_requestSoftwareTransfer                                       \
+        ROM_DMA_requestSoftwareTransfer
+#else
+#define MAP_DMA_requestSoftwareTransfer                                       \
+        DMA_requestSoftwareTransfer
+#endif
+#ifdef ROM_DMA_assignInterrupt
+#define MAP_DMA_assignInterrupt                                               \
+        ROM_DMA_assignInterrupt
+#else
+#define MAP_DMA_assignInterrupt                                               \
+        DMA_assignInterrupt
+#endif
+#ifdef ROM_DMA_enableInterrupt
+#define MAP_DMA_enableInterrupt                                               \
+        ROM_DMA_enableInterrupt
+#else
+#define MAP_DMA_enableInterrupt                                               \
+        DMA_enableInterrupt
+#endif
+#ifdef ROM_DMA_disableInterrupt
+#define MAP_DMA_disableInterrupt                                              \
+        ROM_DMA_disableInterrupt
+#else
+#define MAP_DMA_disableInterrupt                                              \
+        DMA_disableInterrupt
+#endif
+#ifdef ROM_DMA_getInterruptStatus
+#define MAP_DMA_getInterruptStatus                                            \
+        ROM_DMA_getInterruptStatus
+#else
+#define MAP_DMA_getInterruptStatus                                            \
+        DMA_getInterruptStatus
+#endif
+#ifdef ROM_DMA_clearInterruptFlag
+#define MAP_DMA_clearInterruptFlag                                            \
+        ROM_DMA_clearInterruptFlag
+#else
+#define MAP_DMA_clearInterruptFlag                                            \
+        DMA_clearInterruptFlag
+#endif
+#ifdef ROM_DMA_registerInterrupt
+#define MAP_DMA_registerInterrupt                                             \
+        ROM_DMA_registerInterrupt
+#else
+#define MAP_DMA_registerInterrupt                                             \
+        DMA_registerInterrupt
+#endif
+#ifdef ROM_DMA_unregisterInterrupt
+#define MAP_DMA_unregisterInterrupt                                           \
+        ROM_DMA_unregisterInterrupt
+#else
+#define MAP_DMA_unregisterInterrupt                                           \
+        DMA_unregisterInterrupt
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Flash API.
+//
+//*****************************************************************************
+#ifdef ROM_FlashCtl_disableReadParityCheck
+#define MAP_FlashCtl_disableReadParityCheck                                   \
+        ROM_FlashCtl_disableReadParityCheck
+#else
+#define MAP_FlashCtl_disableReadParityCheck                                   \
+        FlashCtl_disableReadParityCheck
+#endif
+#ifdef ROM_FlashCtl_enableReadBuffering
+#define MAP_FlashCtl_enableReadBuffering                                      \
+        ROM_FlashCtl_enableReadBuffering
+#else
+#define MAP_FlashCtl_enableReadBuffering                                      \
+        FlashCtl_enableReadBuffering
+#endif
+#ifdef ROM_FlashCtl_disableReadBuffering
+#define MAP_FlashCtl_disableReadBuffering                                     \
+        ROM_FlashCtl_disableReadBuffering
+#else
+#define MAP_FlashCtl_disableReadBuffering                                     \
+        FlashCtl_disableReadBuffering
+#endif
+#ifdef ROM_FlashCtl_unprotectSector
+#define MAP_FlashCtl_unprotectSector                                          \
+        ROM_FlashCtl_unprotectSector
+#else
+#define MAP_FlashCtl_unprotectSector                                          \
+        FlashCtl_unprotectSector
+#endif
+#ifdef ROM_FlashCtl_protectSector
+#define MAP_FlashCtl_protectSector                                            \
+        ROM_FlashCtl_protectSector
+#else
+#define MAP_FlashCtl_protectSector                                            \
+        FlashCtl_protectSector
+#endif
+#ifdef ROM_FlashCtl_isSectorProtected
+#define MAP_FlashCtl_isSectorProtected                                        \
+        ROM_FlashCtl_isSectorProtected
+#else
+#define MAP_FlashCtl_isSectorProtected                                        \
+        FlashCtl_isSectorProtected
+#endif
+#ifdef ROM_FlashCtl_verifyMemory
+#define MAP_FlashCtl_verifyMemory                                             \
+        ROM_FlashCtl_verifyMemory
+#else
+#define MAP_FlashCtl_verifyMemory                                             \
+        FlashCtl_verifyMemory
+#endif
+#ifdef ROM_FlashCtl_performMassErase
+#define MAP_FlashCtl_performMassErase                                         \
+        ROM_FlashCtl_performMassErase
+#else
+#define MAP_FlashCtl_performMassErase                                         \
+        FlashCtl_performMassErase
+#endif
+#ifdef ROM_FlashCtl_eraseSector
+#define MAP_FlashCtl_eraseSector                                              \
+        ROM_FlashCtl_eraseSector
+#else
+#define MAP_FlashCtl_eraseSector                                              \
+        FlashCtl_eraseSector
+#endif
+#ifdef ROM_FlashCtl_programMemory
+#define MAP_FlashCtl_programMemory                                            \
+        ROM_FlashCtl_programMemory
+#else
+#define MAP_FlashCtl_programMemory                                            \
+        FlashCtl_programMemory
+#endif
+#ifdef ROM_FlashCtl_setProgramVerification
+#define MAP_FlashCtl_setProgramVerification                                   \
+        ROM_FlashCtl_setProgramVerification
+#else
+#define MAP_FlashCtl_setProgramVerification                                   \
+        FlashCtl_setProgramVerification
+#endif
+#ifdef ROM_FlashCtl_clearProgramVerification
+#define MAP_FlashCtl_clearProgramVerification                                 \
+        ROM_FlashCtl_clearProgramVerification
+#else
+#define MAP_FlashCtl_clearProgramVerification                                 \
+        FlashCtl_clearProgramVerification
+#endif
+#ifdef ROM_FlashCtl_enableWordProgramming
+#define MAP_FlashCtl_enableWordProgramming                                    \
+        ROM_FlashCtl_enableWordProgramming
+#else
+#define MAP_FlashCtl_enableWordProgramming                                    \
+        FlashCtl_enableWordProgramming
+#endif
+#ifdef ROM_FlashCtl_disableWordProgramming
+#define MAP_FlashCtl_disableWordProgramming                                   \
+        ROM_FlashCtl_disableWordProgramming
+#else
+#define MAP_FlashCtl_disableWordProgramming                                   \
+        FlashCtl_disableWordProgramming
+#endif
+#ifdef ROM_FlashCtl_isWordProgrammingEnabled
+#define MAP_FlashCtl_isWordProgrammingEnabled                                 \
+        ROM_FlashCtl_isWordProgrammingEnabled
+#else
+#define MAP_FlashCtl_isWordProgrammingEnabled                                 \
+        FlashCtl_isWordProgrammingEnabled
+#endif
+#ifdef ROM_FlashCtl_enableInterrupt
+#define MAP_FlashCtl_enableInterrupt                                          \
+        ROM_FlashCtl_enableInterrupt
+#else
+#define MAP_FlashCtl_enableInterrupt                                          \
+        FlashCtl_enableInterrupt
+#endif
+#ifdef ROM_FlashCtl_disableInterrupt
+#define MAP_FlashCtl_disableInterrupt                                         \
+        ROM_FlashCtl_disableInterrupt
+#else
+#define MAP_FlashCtl_disableInterrupt                                         \
+        FlashCtl_disableInterrupt
+#endif
+#ifdef ROM_FlashCtl_getEnabledInterruptStatus
+#define MAP_FlashCtl_getEnabledInterruptStatus                                \
+        ROM_FlashCtl_getEnabledInterruptStatus
+#else
+#define MAP_FlashCtl_getEnabledInterruptStatus                                \
+        FlashCtl_getEnabledInterruptStatus
+#endif
+#ifdef ROM_FlashCtl_getInterruptStatus
+#define MAP_FlashCtl_getInterruptStatus                                       \
+        ROM_FlashCtl_getInterruptStatus
+#else
+#define MAP_FlashCtl_getInterruptStatus                                       \
+        FlashCtl_getInterruptStatus
+#endif
+#ifdef ROM_FlashCtl_clearInterruptFlag
+#define MAP_FlashCtl_clearInterruptFlag                                       \
+        ROM_FlashCtl_clearInterruptFlag
+#else
+#define MAP_FlashCtl_clearInterruptFlag                                       \
+        FlashCtl_clearInterruptFlag
+#endif
+#ifdef ROM_FlashCtl_setWaitState
+#define MAP_FlashCtl_setWaitState                                             \
+        ROM_FlashCtl_setWaitState
+#else
+#define MAP_FlashCtl_setWaitState                                             \
+        FlashCtl_setWaitState
+#endif
+#ifdef ROM_FlashCtl_getWaitState
+#define MAP_FlashCtl_getWaitState                                             \
+        ROM_FlashCtl_getWaitState
+#else
+#define MAP_FlashCtl_getWaitState                                             \
+        FlashCtl_getWaitState
+#endif
+#ifdef ROM_FlashCtl_setReadMode
+#define MAP_FlashCtl_setReadMode                                              \
+        ROM_FlashCtl_setReadMode
+#else
+#define MAP_FlashCtl_setReadMode                                              \
+        FlashCtl_setReadMode
+#endif
+#ifdef ROM_FlashCtl_getReadMode
+#define MAP_FlashCtl_getReadMode                                              \
+        ROM_FlashCtl_getReadMode
+#else
+#define MAP_FlashCtl_getReadMode                                              \
+        FlashCtl_getReadMode
+#endif
+#ifdef ROM_FlashCtl_registerInterrupt
+#define MAP_FlashCtl_registerInterrupt                                        \
+        ROM_FlashCtl_registerInterrupt
+#else
+#define MAP_FlashCtl_registerInterrupt                                        \
+        FlashCtl_registerInterrupt
+#endif
+#ifdef ROM_FlashCtl_unregisterInterrupt
+#define MAP_FlashCtl_unregisterInterrupt                                      \
+        ROM_FlashCtl_unregisterInterrupt
+#else
+#define MAP_FlashCtl_unregisterInterrupt                                      \
+        FlashCtl_unregisterInterrupt
+#endif
+
+//*****************************************************************************
+//
+// Macros for the FPU API.
+//
+//*****************************************************************************
+#ifdef ROM_FPU_enableModule
+#define MAP_FPU_enableModule                                                  \
+        ROM_FPU_enableModule
+#else
+#define MAP_FPU_enableModule                                                  \
+        FPU_enableModule
+#endif
+#ifdef ROM_FPU_disableModule
+#define MAP_FPU_disableModule                                                 \
+        ROM_FPU_disableModule
+#else
+#define MAP_FPU_disableModule                                                 \
+        FPU_disableModule
+#endif
+#ifdef ROM_FPU_enableStacking
+#define MAP_FPU_enableStacking                                                \
+        ROM_FPU_enableStacking
+#else
+#define MAP_FPU_enableStacking                                                \
+        FPU_enableStacking
+#endif
+#ifdef ROM_FPU_enableLazyStacking
+#define MAP_FPU_enableLazyStacking                                            \
+        ROM_FPU_enableLazyStacking
+#else
+#define MAP_FPU_enableLazyStacking                                            \
+        FPU_enableLazyStacking
+#endif
+#ifdef ROM_FPU_disableStacking
+#define MAP_FPU_disableStacking                                               \
+        ROM_FPU_disableStacking
+#else
+#define MAP_FPU_disableStacking                                               \
+        FPU_disableStacking
+#endif
+#ifdef ROM_FPU_setHalfPrecisionMode
+#define MAP_FPU_setHalfPrecisionMode                                          \
+        ROM_FPU_setHalfPrecisionMode
+#else
+#define MAP_FPU_setHalfPrecisionMode                                          \
+        FPU_setHalfPrecisionMode
+#endif
+#ifdef ROM_FPU_setNaNMode
+#define MAP_FPU_setNaNMode                                                    \
+        ROM_FPU_setNaNMode
+#else
+#define MAP_FPU_setNaNMode                                                    \
+        FPU_setNaNMode
+#endif
+#ifdef ROM_FPU_setFlushToZeroMode
+#define MAP_FPU_setFlushToZeroMode                                            \
+        ROM_FPU_setFlushToZeroMode
+#else
+#define MAP_FPU_setFlushToZeroMode                                            \
+        FPU_setFlushToZeroMode
+#endif
+#ifdef ROM_FPU_setRoundingMode
+#define MAP_FPU_setRoundingMode                                               \
+        ROM_FPU_setRoundingMode
+#else
+#define MAP_FPU_setRoundingMode                                               \
+        FPU_setRoundingMode
+#endif
+
+//*****************************************************************************
+//
+// Macros for the GPIO API.
+//
+//*****************************************************************************
+#ifdef ROM_GPIO_setAsOutputPin
+#define MAP_GPIO_setAsOutputPin                                               \
+        ROM_GPIO_setAsOutputPin
+#else
+#define MAP_GPIO_setAsOutputPin                                               \
+        GPIO_setAsOutputPin
+#endif
+#ifdef ROM_GPIO_setOutputHighOnPin
+#define MAP_GPIO_setOutputHighOnPin                                           \
+        ROM_GPIO_setOutputHighOnPin
+#else
+#define MAP_GPIO_setOutputHighOnPin                                           \
+        GPIO_setOutputHighOnPin
+#endif
+#ifdef ROM_GPIO_setOutputLowOnPin
+#define MAP_GPIO_setOutputLowOnPin                                            \
+        ROM_GPIO_setOutputLowOnPin
+#else
+#define MAP_GPIO_setOutputLowOnPin                                            \
+        GPIO_setOutputLowOnPin
+#endif
+#ifdef ROM_GPIO_toggleOutputOnPin
+#define MAP_GPIO_toggleOutputOnPin                                            \
+        ROM_GPIO_toggleOutputOnPin
+#else
+#define MAP_GPIO_toggleOutputOnPin                                            \
+        GPIO_toggleOutputOnPin
+#endif
+#ifdef ROM_GPIO_setAsInputPinWithPullDownResistor
+#define MAP_GPIO_setAsInputPinWithPullDownResistor                            \
+        ROM_GPIO_setAsInputPinWithPullDownResistor
+#else
+#define MAP_GPIO_setAsInputPinWithPullDownResistor                            \
+        GPIO_setAsInputPinWithPullDownResistor
+#endif
+#ifdef ROM_GPIO_setAsInputPinWithPullUpResistor
+#define MAP_GPIO_setAsInputPinWithPullUpResistor                              \
+        ROM_GPIO_setAsInputPinWithPullUpResistor
+#else
+#define MAP_GPIO_setAsInputPinWithPullUpResistor                              \
+        GPIO_setAsInputPinWithPullUpResistor
+#endif
+#ifdef ROM_GPIO_setAsPeripheralModuleFunctionOutputPin
+#define MAP_GPIO_setAsPeripheralModuleFunctionOutputPin                       \
+        ROM_GPIO_setAsPeripheralModuleFunctionOutputPin
+#else
+#define MAP_GPIO_setAsPeripheralModuleFunctionOutputPin                       \
+        GPIO_setAsPeripheralModuleFunctionOutputPin
+#endif
+#ifdef ROM_GPIO_setAsPeripheralModuleFunctionInputPin
+#define MAP_GPIO_setAsPeripheralModuleFunctionInputPin                        \
+        ROM_GPIO_setAsPeripheralModuleFunctionInputPin
+#else
+#define MAP_GPIO_setAsPeripheralModuleFunctionInputPin                        \
+        GPIO_setAsPeripheralModuleFunctionInputPin
+#endif
+#ifdef ROM_GPIO_getInputPinValue
+#define MAP_GPIO_getInputPinValue                                             \
+        ROM_GPIO_getInputPinValue
+#else
+#define MAP_GPIO_getInputPinValue                                             \
+        GPIO_getInputPinValue
+#endif
+#ifdef ROM_GPIO_interruptEdgeSelect
+#define MAP_GPIO_interruptEdgeSelect                                          \
+        ROM_GPIO_interruptEdgeSelect
+#else
+#define MAP_GPIO_interruptEdgeSelect                                          \
+        GPIO_interruptEdgeSelect
+#endif
+#ifdef ROM_GPIO_enableInterrupt
+#define MAP_GPIO_enableInterrupt                                              \
+        ROM_GPIO_enableInterrupt
+#else
+#define MAP_GPIO_enableInterrupt                                              \
+        GPIO_enableInterrupt
+#endif
+#ifdef ROM_GPIO_disableInterrupt
+#define MAP_GPIO_disableInterrupt                                             \
+        ROM_GPIO_disableInterrupt
+#else
+#define MAP_GPIO_disableInterrupt                                             \
+        GPIO_disableInterrupt
+#endif
+#ifdef ROM_GPIO_getInterruptStatus
+#define MAP_GPIO_getInterruptStatus                                           \
+        ROM_GPIO_getInterruptStatus
+#else
+#define MAP_GPIO_getInterruptStatus                                           \
+        GPIO_getInterruptStatus
+#endif
+#ifdef ROM_GPIO_clearInterruptFlag
+#define MAP_GPIO_clearInterruptFlag                                           \
+        ROM_GPIO_clearInterruptFlag
+#else
+#define MAP_GPIO_clearInterruptFlag                                           \
+        GPIO_clearInterruptFlag
+#endif
+#ifdef ROM_GPIO_setAsInputPin
+#define MAP_GPIO_setAsInputPin                                                \
+        ROM_GPIO_setAsInputPin
+#else
+#define MAP_GPIO_setAsInputPin                                                \
+        GPIO_setAsInputPin
+#endif
+#ifdef ROM_GPIO_getEnabledInterruptStatus
+#define MAP_GPIO_getEnabledInterruptStatus                                    \
+        ROM_GPIO_getEnabledInterruptStatus
+#else
+#define MAP_GPIO_getEnabledInterruptStatus                                    \
+        GPIO_getEnabledInterruptStatus
+#endif
+#ifdef ROM_GPIO_setDriveStrengthHigh
+#define MAP_GPIO_setDriveStrengthHigh                                         \
+        ROM_GPIO_setDriveStrengthHigh
+#else
+#define MAP_GPIO_setDriveStrengthHigh                                         \
+        GPIO_setDriveStrengthHigh
+#endif
+#ifdef ROM_GPIO_setDriveStrengthLow
+#define MAP_GPIO_setDriveStrengthLow                                          \
+        ROM_GPIO_setDriveStrengthLow
+#else
+#define MAP_GPIO_setDriveStrengthLow                                          \
+        GPIO_setDriveStrengthLow
+#endif
+#ifdef ROM_GPIO_registerInterrupt
+#define MAP_GPIO_registerInterrupt                                            \
+        ROM_GPIO_registerInterrupt
+#else
+#define MAP_GPIO_registerInterrupt                                            \
+        GPIO_registerInterrupt
+#endif
+#ifdef ROM_GPIO_unregisterInterrupt
+#define MAP_GPIO_unregisterInterrupt                                          \
+        ROM_GPIO_unregisterInterrupt
+#else
+#define MAP_GPIO_unregisterInterrupt                                          \
+        GPIO_unregisterInterrupt
+#endif
+
+//*****************************************************************************
+//
+// Macros for the I2C API.
+//
+//*****************************************************************************
+#ifdef ROM_I2C_initMaster
+#define MAP_I2C_initMaster                                                    \
+        ROM_I2C_initMaster
+#else
+#define MAP_I2C_initMaster                                                    \
+        I2C_initMaster
+#endif
+#ifdef ROM_I2C_initSlave
+#define MAP_I2C_initSlave                                                     \
+        ROM_I2C_initSlave
+#else
+#define MAP_I2C_initSlave                                                     \
+        I2C_initSlave
+#endif
+#ifdef ROM_I2C_enableModule
+#define MAP_I2C_enableModule                                                  \
+        ROM_I2C_enableModule
+#else
+#define MAP_I2C_enableModule                                                  \
+        I2C_enableModule
+#endif
+#ifdef ROM_I2C_disableModule
+#define MAP_I2C_disableModule                                                 \
+        ROM_I2C_disableModule
+#else
+#define MAP_I2C_disableModule                                                 \
+        I2C_disableModule
+#endif
+#ifdef ROM_I2C_setSlaveAddress
+#define MAP_I2C_setSlaveAddress                                               \
+        ROM_I2C_setSlaveAddress
+#else
+#define MAP_I2C_setSlaveAddress                                               \
+        I2C_setSlaveAddress
+#endif
+#ifdef ROM_I2C_setMode
+#define MAP_I2C_setMode                                                       \
+        ROM_I2C_setMode
+#else
+#define MAP_I2C_setMode                                                       \
+        I2C_setMode
+#endif
+#ifdef ROM_I2C_slavePutData
+#define MAP_I2C_slavePutData                                                  \
+        ROM_I2C_slavePutData
+#else
+#define MAP_I2C_slavePutData                                                  \
+        I2C_slavePutData
+#endif
+#ifdef ROM_I2C_slaveGetData
+#define MAP_I2C_slaveGetData                                                  \
+        ROM_I2C_slaveGetData
+#else
+#define MAP_I2C_slaveGetData                                                  \
+        I2C_slaveGetData
+#endif
+#ifdef ROM_I2C_isBusBusy
+#define MAP_I2C_isBusBusy                                                     \
+        ROM_I2C_isBusBusy
+#else
+#define MAP_I2C_isBusBusy                                                     \
+        I2C_isBusBusy
+#endif
+#ifdef ROM_I2C_masterSendSingleByte
+#define MAP_I2C_masterSendSingleByte                                          \
+        ROM_I2C_masterSendSingleByte
+#else
+#define MAP_I2C_masterSendSingleByte                                          \
+        I2C_masterSendSingleByte
+#endif
+#ifdef ROM_I2C_masterSendSingleByteWithTimeout
+#define MAP_I2C_masterSendSingleByteWithTimeout                               \
+        ROM_I2C_masterSendSingleByteWithTimeout
+#else
+#define MAP_I2C_masterSendSingleByteWithTimeout                               \
+        I2C_masterSendSingleByteWithTimeout
+#endif
+#ifdef ROM_I2C_masterSendMultiByteStart
+#define MAP_I2C_masterSendMultiByteStart                                      \
+        ROM_I2C_masterSendMultiByteStart
+#else
+#define MAP_I2C_masterSendMultiByteStart                                      \
+        I2C_masterSendMultiByteStart
+#endif
+#ifdef ROM_I2C_masterSendMultiByteStartWithTimeout
+#define MAP_I2C_masterSendMultiByteStartWithTimeout                           \
+        ROM_I2C_masterSendMultiByteStartWithTimeout
+#else
+#define MAP_I2C_masterSendMultiByteStartWithTimeout                           \
+        I2C_masterSendMultiByteStartWithTimeout
+#endif
+#ifdef ROM_I2C_masterSendMultiByteNext
+#define MAP_I2C_masterSendMultiByteNext                                       \
+        ROM_I2C_masterSendMultiByteNext
+#else
+#define MAP_I2C_masterSendMultiByteNext                                       \
+        I2C_masterSendMultiByteNext
+#endif
+#ifdef ROM_I2C_masterSendMultiByteNextWithTimeout
+#define MAP_I2C_masterSendMultiByteNextWithTimeout                            \
+        ROM_I2C_masterSendMultiByteNextWithTimeout
+#else
+#define MAP_I2C_masterSendMultiByteNextWithTimeout                            \
+        I2C_masterSendMultiByteNextWithTimeout
+#endif
+#ifdef ROM_I2C_masterSendMultiByteFinish
+#define MAP_I2C_masterSendMultiByteFinish                                     \
+        ROM_I2C_masterSendMultiByteFinish
+#else
+#define MAP_I2C_masterSendMultiByteFinish                                     \
+        I2C_masterSendMultiByteFinish
+#endif
+#ifdef ROM_I2C_masterSendMultiByteFinishWithTimeout
+#define MAP_I2C_masterSendMultiByteFinishWithTimeout                          \
+        ROM_I2C_masterSendMultiByteFinishWithTimeout
+#else
+#define MAP_I2C_masterSendMultiByteFinishWithTimeout                          \
+        I2C_masterSendMultiByteFinishWithTimeout
+#endif
+#ifdef ROM_I2C_masterSendMultiByteStop
+#define MAP_I2C_masterSendMultiByteStop                                       \
+        ROM_I2C_masterSendMultiByteStop
+#else
+#define MAP_I2C_masterSendMultiByteStop                                       \
+        I2C_masterSendMultiByteStop
+#endif
+#ifdef ROM_I2C_masterSendMultiByteStopWithTimeout
+#define MAP_I2C_masterSendMultiByteStopWithTimeout                            \
+        ROM_I2C_masterSendMultiByteStopWithTimeout
+#else
+#define MAP_I2C_masterSendMultiByteStopWithTimeout                            \
+        I2C_masterSendMultiByteStopWithTimeout
+#endif
+#ifdef ROM_I2C_masterReceiveStart
+#define MAP_I2C_masterReceiveStart                                            \
+        ROM_I2C_masterReceiveStart
+#else
+#define MAP_I2C_masterReceiveStart                                            \
+        I2C_masterReceiveStart
+#endif
+#ifdef ROM_I2C_masterReceiveMultiByteNext
+#define MAP_I2C_masterReceiveMultiByteNext                                    \
+        ROM_I2C_masterReceiveMultiByteNext
+#else
+#define MAP_I2C_masterReceiveMultiByteNext                                    \
+        I2C_masterReceiveMultiByteNext
+#endif
+#ifdef ROM_I2C_masterReceiveMultiByteFinish
+#define MAP_I2C_masterReceiveMultiByteFinish                                  \
+        ROM_I2C_masterReceiveMultiByteFinish
+#else
+#define MAP_I2C_masterReceiveMultiByteFinish                                  \
+        I2C_masterReceiveMultiByteFinish
+#endif
+#ifdef ROM_I2C_masterReceiveMultiByteFinishWithTimeout
+#define MAP_I2C_masterReceiveMultiByteFinishWithTimeout                       \
+        ROM_I2C_masterReceiveMultiByteFinishWithTimeout
+#else
+#define MAP_I2C_masterReceiveMultiByteFinishWithTimeout                       \
+        I2C_masterReceiveMultiByteFinishWithTimeout
+#endif
+#ifdef ROM_I2C_masterReceiveMultiByteStop
+#define MAP_I2C_masterReceiveMultiByteStop                                    \
+        ROM_I2C_masterReceiveMultiByteStop
+#else
+#define MAP_I2C_masterReceiveMultiByteStop                                    \
+        I2C_masterReceiveMultiByteStop
+#endif
+#ifdef ROM_I2C_masterReceiveSingleByte
+#define MAP_I2C_masterReceiveSingleByte                                       \
+        ROM_I2C_masterReceiveSingleByte
+#else
+#define MAP_I2C_masterReceiveSingleByte                                       \
+        I2C_masterReceiveSingleByte
+#endif
+#ifdef ROM_I2C_masterReceiveSingle
+#define MAP_I2C_masterReceiveSingle                                           \
+        ROM_I2C_masterReceiveSingle
+#else
+#define MAP_I2C_masterReceiveSingle                                           \
+        I2C_masterReceiveSingle
+#endif
+#ifdef ROM_I2C_getReceiveBufferAddressForDMA
+#define MAP_I2C_getReceiveBufferAddressForDMA                                 \
+        ROM_I2C_getReceiveBufferAddressForDMA
+#else
+#define MAP_I2C_getReceiveBufferAddressForDMA                                 \
+        I2C_getReceiveBufferAddressForDMA
+#endif
+#ifdef ROM_I2C_getTransmitBufferAddressForDMA
+#define MAP_I2C_getTransmitBufferAddressForDMA                                \
+        ROM_I2C_getTransmitBufferAddressForDMA
+#else
+#define MAP_I2C_getTransmitBufferAddressForDMA                                \
+        I2C_getTransmitBufferAddressForDMA
+#endif
+#ifdef ROM_I2C_masterIsStopSent
+#define MAP_I2C_masterIsStopSent                                              \
+        ROM_I2C_masterIsStopSent
+#else
+#define MAP_I2C_masterIsStopSent                                              \
+        I2C_masterIsStopSent
+#endif
+#ifdef ROM_I2C_masterIsStartSent
+#define MAP_I2C_masterIsStartSent                                             \
+        ROM_I2C_masterIsStartSent
+#else
+#define MAP_I2C_masterIsStartSent                                             \
+        I2C_masterIsStartSent
+#endif
+#ifdef ROM_I2C_masterSendStart
+#define MAP_I2C_masterSendStart                                               \
+        ROM_I2C_masterSendStart
+#else
+#define MAP_I2C_masterSendStart                                               \
+        I2C_masterSendStart
+#endif
+#ifdef ROM_I2C_enableMultiMasterMode
+#define MAP_I2C_enableMultiMasterMode                                         \
+        ROM_I2C_enableMultiMasterMode
+#else
+#define MAP_I2C_enableMultiMasterMode                                         \
+        I2C_enableMultiMasterMode
+#endif
+#ifdef ROM_I2C_disableMultiMasterMode
+#define MAP_I2C_disableMultiMasterMode                                        \
+        ROM_I2C_disableMultiMasterMode
+#else
+#define MAP_I2C_disableMultiMasterMode                                        \
+        I2C_disableMultiMasterMode
+#endif
+#ifdef ROM_I2C_enableInterrupt
+#define MAP_I2C_enableInterrupt                                               \
+        ROM_I2C_enableInterrupt
+#else
+#define MAP_I2C_enableInterrupt                                               \
+        I2C_enableInterrupt
+#endif
+#ifdef ROM_I2C_disableInterrupt
+#define MAP_I2C_disableInterrupt                                              \
+        ROM_I2C_disableInterrupt
+#else
+#define MAP_I2C_disableInterrupt                                              \
+        I2C_disableInterrupt
+#endif
+#ifdef ROM_I2C_clearInterruptFlag
+#define MAP_I2C_clearInterruptFlag                                            \
+        ROM_I2C_clearInterruptFlag
+#else
+#define MAP_I2C_clearInterruptFlag                                            \
+        I2C_clearInterruptFlag
+#endif
+#ifdef ROM_I2C_getInterruptStatus
+#define MAP_I2C_getInterruptStatus                                            \
+        ROM_I2C_getInterruptStatus
+#else
+#define MAP_I2C_getInterruptStatus                                            \
+        I2C_getInterruptStatus
+#endif
+#ifdef ROM_I2C_getEnabledInterruptStatus
+#define MAP_I2C_getEnabledInterruptStatus                                     \
+        ROM_I2C_getEnabledInterruptStatus
+#else
+#define MAP_I2C_getEnabledInterruptStatus                                     \
+        I2C_getEnabledInterruptStatus
+#endif
+#ifdef ROM_I2C_getMode
+#define MAP_I2C_getMode                                                       \
+        ROM_I2C_getMode
+#else
+#define MAP_I2C_getMode                                                       \
+        I2C_getMode
+#endif
+#ifdef ROM_I2C_registerInterrupt
+#define MAP_I2C_registerInterrupt                                             \
+        ROM_I2C_registerInterrupt
+#else
+#define MAP_I2C_registerInterrupt                                             \
+        I2C_registerInterrupt
+#endif
+#ifdef ROM_I2C_unregisterInterrupt
+#define MAP_I2C_unregisterInterrupt                                           \
+        ROM_I2C_unregisterInterrupt
+#else
+#define MAP_I2C_unregisterInterrupt                                           \
+        I2C_unregisterInterrupt
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Interrupt API.
+//
+//*****************************************************************************
+#ifdef ROM_Interrupt_enableMaster
+#define MAP_Interrupt_enableMaster                                            \
+        ROM_Interrupt_enableMaster
+#else
+#define MAP_Interrupt_enableMaster                                            \
+        Interrupt_enableMaster
+#endif
+#ifdef ROM_Interrupt_disableMaster
+#define MAP_Interrupt_disableMaster                                           \
+        ROM_Interrupt_disableMaster
+#else
+#define MAP_Interrupt_disableMaster                                           \
+        Interrupt_disableMaster
+#endif
+#ifdef ROM_Interrupt_setPriorityGrouping
+#define MAP_Interrupt_setPriorityGrouping                                     \
+        ROM_Interrupt_setPriorityGrouping
+#else
+#define MAP_Interrupt_setPriorityGrouping                                     \
+        Interrupt_setPriorityGrouping
+#endif
+#ifdef ROM_Interrupt_getPriorityGrouping
+#define MAP_Interrupt_getPriorityGrouping                                     \
+        ROM_Interrupt_getPriorityGrouping
+#else
+#define MAP_Interrupt_getPriorityGrouping                                     \
+        Interrupt_getPriorityGrouping
+#endif
+#ifdef ROM_Interrupt_setPriority
+#define MAP_Interrupt_setPriority                                             \
+        ROM_Interrupt_setPriority
+#else
+#define MAP_Interrupt_setPriority                                             \
+        Interrupt_setPriority
+#endif
+#ifdef ROM_Interrupt_getPriority
+#define MAP_Interrupt_getPriority                                             \
+        ROM_Interrupt_getPriority
+#else
+#define MAP_Interrupt_getPriority                                             \
+        Interrupt_getPriority
+#endif
+#ifdef ROM_Interrupt_enableInterrupt
+#define MAP_Interrupt_enableInterrupt                                         \
+        ROM_Interrupt_enableInterrupt
+#else
+#define MAP_Interrupt_enableInterrupt                                         \
+        Interrupt_enableInterrupt
+#endif
+#ifdef ROM_Interrupt_disableInterrupt
+#define MAP_Interrupt_disableInterrupt                                        \
+        ROM_Interrupt_disableInterrupt
+#else
+#define MAP_Interrupt_disableInterrupt                                        \
+        Interrupt_disableInterrupt
+#endif
+#ifdef ROM_Interrupt_isEnabled
+#define MAP_Interrupt_isEnabled                                               \
+        ROM_Interrupt_isEnabled
+#else
+#define MAP_Interrupt_isEnabled                                               \
+        Interrupt_isEnabled
+#endif
+#ifdef ROM_Interrupt_pendInterrupt
+#define MAP_Interrupt_pendInterrupt                                           \
+        ROM_Interrupt_pendInterrupt
+#else
+#define MAP_Interrupt_pendInterrupt                                           \
+        Interrupt_pendInterrupt
+#endif
+#ifdef ROM_Interrupt_setPriorityMask
+#define MAP_Interrupt_setPriorityMask                                         \
+        ROM_Interrupt_setPriorityMask
+#else
+#define MAP_Interrupt_setPriorityMask                                         \
+        Interrupt_setPriorityMask
+#endif
+#ifdef ROM_Interrupt_getPriorityMask
+#define MAP_Interrupt_getPriorityMask                                         \
+        ROM_Interrupt_getPriorityMask
+#else
+#define MAP_Interrupt_getPriorityMask                                         \
+        Interrupt_getPriorityMask
+#endif
+#ifdef ROM_Interrupt_setVectorTableAddress
+#define MAP_Interrupt_setVectorTableAddress                                   \
+        ROM_Interrupt_setVectorTableAddress
+#else
+#define MAP_Interrupt_setVectorTableAddress                                   \
+        Interrupt_setVectorTableAddress
+#endif
+#ifdef ROM_Interrupt_getVectorTableAddress
+#define MAP_Interrupt_getVectorTableAddress                                   \
+        ROM_Interrupt_getVectorTableAddress
+#else
+#define MAP_Interrupt_getVectorTableAddress                                   \
+        Interrupt_getVectorTableAddress
+#endif
+#ifdef ROM_Interrupt_enableSleepOnIsrExit
+#define MAP_Interrupt_enableSleepOnIsrExit                                    \
+        ROM_Interrupt_enableSleepOnIsrExit
+#else
+#define MAP_Interrupt_enableSleepOnIsrExit                                    \
+        Interrupt_enableSleepOnIsrExit
+#endif
+#ifdef ROM_Interrupt_disableSleepOnIsrExit
+#define MAP_Interrupt_disableSleepOnIsrExit                                   \
+        ROM_Interrupt_disableSleepOnIsrExit
+#else
+#define MAP_Interrupt_disableSleepOnIsrExit                                   \
+        Interrupt_disableSleepOnIsrExit
+#endif
+#ifdef ROM_Interrupt_registerInterrupt
+#define MAP_Interrupt_registerInterrupt                                       \
+        ROM_Interrupt_registerInterrupt
+#else
+#define MAP_Interrupt_registerInterrupt                                       \
+        Interrupt_registerInterrupt
+#endif
+
+//*****************************************************************************
+//
+// Macros for the MPU API.
+//
+//*****************************************************************************
+#ifdef ROM_MPU_enableModule
+#define MAP_MPU_enableModule                                                  \
+        ROM_MPU_enableModule
+#else
+#define MAP_MPU_enableModule                                                  \
+        MPU_enableModule
+#endif
+#ifdef ROM_MPU_disableModule
+#define MAP_MPU_disableModule                                                 \
+        ROM_MPU_disableModule
+#else
+#define MAP_MPU_disableModule                                                 \
+        MPU_disableModule
+#endif
+#ifdef ROM_MPU_getRegionCount
+#define MAP_MPU_getRegionCount                                                \
+        ROM_MPU_getRegionCount
+#else
+#define MAP_MPU_getRegionCount                                                \
+        MPU_getRegionCount
+#endif
+#ifdef ROM_MPU_enableRegion
+#define MAP_MPU_enableRegion                                                  \
+        ROM_MPU_enableRegion
+#else
+#define MAP_MPU_enableRegion                                                  \
+        MPU_enableRegion
+#endif
+#ifdef ROM_MPU_disableRegion
+#define MAP_MPU_disableRegion                                                 \
+        ROM_MPU_disableRegion
+#else
+#define MAP_MPU_disableRegion                                                 \
+        MPU_disableRegion
+#endif
+#ifdef ROM_MPU_setRegion
+#define MAP_MPU_setRegion                                                     \
+        ROM_MPU_setRegion
+#else
+#define MAP_MPU_setRegion                                                     \
+        MPU_setRegion
+#endif
+#ifdef ROM_MPU_getRegion
+#define MAP_MPU_getRegion                                                     \
+        ROM_MPU_getRegion
+#else
+#define MAP_MPU_getRegion                                                     \
+        MPU_getRegion
+#endif
+#ifdef ROM_MPU_enableInterrupt
+#define MAP_MPU_enableInterrupt                                               \
+        ROM_MPU_enableInterrupt
+#else
+#define MAP_MPU_enableInterrupt                                               \
+        MPU_enableInterrupt
+#endif
+#ifdef ROM_MPU_disableInterrupt
+#define MAP_MPU_disableInterrupt                                              \
+        ROM_MPU_disableInterrupt
+#else
+#define MAP_MPU_disableInterrupt                                              \
+        MPU_disableInterrupt
+#endif
+#ifdef ROM_MPU_registerInterrupt
+#define MAP_MPU_registerInterrupt                                             \
+        ROM_MPU_registerInterrupt
+#else
+#define MAP_MPU_registerInterrupt                                             \
+        MPU_registerInterrupt
+#endif
+#ifdef ROM_MPU_unregisterInterrupt
+#define MAP_MPU_unregisterInterrupt                                           \
+        ROM_MPU_unregisterInterrupt
+#else
+#define MAP_MPU_unregisterInterrupt                                           \
+        MPU_unregisterInterrupt
+#endif
+
+//*****************************************************************************
+//
+// Macros for the PCM API.
+//
+//*****************************************************************************
+#ifdef ROM_PCM_setCoreVoltageLevel
+#define MAP_PCM_setCoreVoltageLevel                                           \
+        ROM_PCM_setCoreVoltageLevel
+#else
+#define MAP_PCM_setCoreVoltageLevel                                           \
+        PCM_setCoreVoltageLevel
+#endif
+#ifdef ROM_PCM_getCoreVoltageLevel
+#define MAP_PCM_getCoreVoltageLevel                                           \
+        ROM_PCM_getCoreVoltageLevel
+#else
+#define MAP_PCM_getCoreVoltageLevel                                           \
+        PCM_getCoreVoltageLevel
+#endif
+#ifdef ROM_PCM_setCoreVoltageLevelWithTimeout
+#define MAP_PCM_setCoreVoltageLevelWithTimeout                                \
+        ROM_PCM_setCoreVoltageLevelWithTimeout
+#else
+#define MAP_PCM_setCoreVoltageLevelWithTimeout                                \
+        PCM_setCoreVoltageLevelWithTimeout
+#endif
+#ifdef ROM_PCM_setPowerMode
+#define MAP_PCM_setPowerMode                                                  \
+        ROM_PCM_setPowerMode
+#else
+#define MAP_PCM_setPowerMode                                                  \
+        PCM_setPowerMode
+#endif
+#ifdef ROM_PCM_setPowerModeWithTimeout
+#define MAP_PCM_setPowerModeWithTimeout                                       \
+        ROM_PCM_setPowerModeWithTimeout
+#else
+#define MAP_PCM_setPowerModeWithTimeout                                       \
+        PCM_setPowerModeWithTimeout
+#endif
+#ifdef ROM_PCM_getPowerMode
+#define MAP_PCM_getPowerMode                                                  \
+        ROM_PCM_getPowerMode
+#else
+#define MAP_PCM_getPowerMode                                                  \
+        PCM_getPowerMode
+#endif
+#ifdef ROM_PCM_setPowerState
+#define MAP_PCM_setPowerState                                                 \
+        ROM_PCM_setPowerState
+#else
+#define MAP_PCM_setPowerState                                                 \
+        PCM_setPowerState
+#endif
+#ifdef ROM_PCM_setPowerStateWithTimeout
+#define MAP_PCM_setPowerStateWithTimeout                                      \
+        ROM_PCM_setPowerStateWithTimeout
+#else
+#define MAP_PCM_setPowerStateWithTimeout                                      \
+        PCM_setPowerStateWithTimeout
+#endif
+#ifdef ROM_PCM_getPowerState
+#define MAP_PCM_getPowerState                                                 \
+        ROM_PCM_getPowerState
+#else
+#define MAP_PCM_getPowerState                                                 \
+        PCM_getPowerState
+#endif
+#ifdef ROM_PCM_shutdownDevice
+#define MAP_PCM_shutdownDevice                                                \
+        ROM_PCM_shutdownDevice
+#else
+#define MAP_PCM_shutdownDevice                                                \
+        PCM_shutdownDevice
+#endif
+#ifdef ROM_PCM_gotoLPM0
+#define MAP_PCM_gotoLPM0                                                      \
+        ROM_PCM_gotoLPM0
+#else
+#define MAP_PCM_gotoLPM0                                                      \
+        PCM_gotoLPM0
+#endif
+#ifdef ROM_PCM_gotoLPM3
+#define MAP_PCM_gotoLPM3                                                      \
+        ROM_PCM_gotoLPM3
+#else
+#define MAP_PCM_gotoLPM3                                                      \
+        PCM_gotoLPM3
+#endif
+#ifdef ROM_PCM_enableInterrupt
+#define MAP_PCM_enableInterrupt                                               \
+        ROM_PCM_enableInterrupt
+#else
+#define MAP_PCM_enableInterrupt                                               \
+        PCM_enableInterrupt
+#endif
+#ifdef ROM_PCM_disableInterrupt
+#define MAP_PCM_disableInterrupt                                              \
+        ROM_PCM_disableInterrupt
+#else
+#define MAP_PCM_disableInterrupt                                              \
+        PCM_disableInterrupt
+#endif
+#ifdef ROM_PCM_getInterruptStatus
+#define MAP_PCM_getInterruptStatus                                            \
+        ROM_PCM_getInterruptStatus
+#else
+#define MAP_PCM_getInterruptStatus                                            \
+        PCM_getInterruptStatus
+#endif
+#ifdef ROM_PCM_getEnabledInterruptStatus
+#define MAP_PCM_getEnabledInterruptStatus                                     \
+        ROM_PCM_getEnabledInterruptStatus
+#else
+#define MAP_PCM_getEnabledInterruptStatus                                     \
+        PCM_getEnabledInterruptStatus
+#endif
+#ifdef ROM_PCM_clearInterruptFlag
+#define MAP_PCM_clearInterruptFlag                                            \
+        ROM_PCM_clearInterruptFlag
+#else
+#define MAP_PCM_clearInterruptFlag                                            \
+        PCM_clearInterruptFlag
+#endif
+#ifdef ROM_PCM_enableRudeMode
+#define MAP_PCM_enableRudeMode                                                \
+        ROM_PCM_enableRudeMode
+#else
+#define MAP_PCM_enableRudeMode                                                \
+        PCM_enableRudeMode
+#endif
+#ifdef ROM_PCM_disableRudeMode
+#define MAP_PCM_disableRudeMode                                               \
+        ROM_PCM_disableRudeMode
+#else
+#define MAP_PCM_disableRudeMode                                               \
+        PCM_disableRudeMode
+#endif
+#ifdef ROM_PCM_gotoLPM0InterruptSafe
+#define MAP_PCM_gotoLPM0InterruptSafe                                         \
+        ROM_PCM_gotoLPM0InterruptSafe
+#else
+#define MAP_PCM_gotoLPM0InterruptSafe                                         \
+        PCM_gotoLPM0InterruptSafe
+#endif
+#ifdef ROM_PCM_gotoLPM3InterruptSafe
+#define MAP_PCM_gotoLPM3InterruptSafe                                         \
+        ROM_PCM_gotoLPM3InterruptSafe
+#else
+#define MAP_PCM_gotoLPM3InterruptSafe                                         \
+        PCM_gotoLPM3InterruptSafe
+#endif
+#ifdef ROM_PCM_registerInterrupt
+#define MAP_PCM_registerInterrupt                                             \
+        ROM_PCM_registerInterrupt
+#else
+#define MAP_PCM_registerInterrupt                                             \
+        PCM_registerInterrupt
+#endif
+#ifdef ROM_PCM_unregisterInterrupt
+#define MAP_PCM_unregisterInterrupt                                           \
+        ROM_PCM_unregisterInterrupt
+#else
+#define MAP_PCM_unregisterInterrupt                                           \
+        PCM_unregisterInterrupt
+#endif
+
+//*****************************************************************************
+//
+// Macros for the PMAP API.
+//
+//*****************************************************************************
+#ifdef ROM_PMAP_configurePorts
+#define MAP_PMAP_configurePorts                                               \
+        ROM_PMAP_configurePorts
+#else
+#define MAP_PMAP_configurePorts                                               \
+        PMAP_configurePorts
+#endif
+
+//*****************************************************************************
+//
+// Macros for the PSS API.
+//
+//*****************************************************************************
+#ifdef ROM_PSS_enableHighSidePinToggle
+#define MAP_PSS_enableHighSidePinToggle                                       \
+        ROM_PSS_enableHighSidePinToggle
+#else
+#define MAP_PSS_enableHighSidePinToggle                                       \
+        PSS_enableHighSidePinToggle
+#endif
+#ifdef ROM_PSS_disableHighSidePinToggle
+#define MAP_PSS_disableHighSidePinToggle                                      \
+        ROM_PSS_disableHighSidePinToggle
+#else
+#define MAP_PSS_disableHighSidePinToggle                                      \
+        PSS_disableHighSidePinToggle
+#endif
+#ifdef ROM_setLowSidePerformanceMode 
+#define MAP_PSS_setLowSidePerformanceMode                                      \
+        ROM_PSS_setLowSidePerformanceMode 
+#else
+#define MAP_PSS_setLowSidePerformanceMode                                      \
+        PSS_setLowSidePerformanceMode 
+#endif
+#ifdef ROM_getLowSidePerformanceMode 
+#define MAP_PSS_getLowSidePerformanceMode                                      \
+        ROM_PSS_getLowSidePerformanceMode 
+#else
+#define MAP_PSS_getLowSidePerformanceMode                                      \
+        PSS_getLowSidePerformanceMode 
+#endif
+#ifdef ROM_PSS_disableLowSide
+#define MAP_PSS_disableLowSide                                                 \
+        ROM_PSS_disableLowSide
+#else
+#define MAP_PSS_disableLowSide                                                 \
+        PSS_disableLowSide
+#endif
+#ifdef ROM_PSS_enableLowSide
+#define MAP_PSS_enableLowSide                                                 \
+        ROM_PSS_enableLowSide
+#else
+#define MAP_PSS_enableLowSide                                                 \
+        PSS_enableLowSide
+#endif
+#ifdef ROM_PSS_enableHighSide
+#define MAP_PSS_enableHighSide                                                \
+        ROM_PSS_enableHighSide
+#else
+#define MAP_PSS_enableHighSide                                                \
+        PSS_enableHighSide
+#endif
+#ifdef ROM_PSS_disableHighSide
+#define MAP_PSS_disableHighSide                                               \
+        ROM_PSS_disableHighSide
+#else
+#define MAP_PSS_disableHighSide                                               \
+        PSS_disableHighSide
+#endif
+#ifdef ROM_PSS_setHighSidePerformanceMode
+#define MAP_PSS_setHighSidePerformanceMode                                    \
+        ROM_PSS_setHighSidePerformanceMode
+#else
+#define MAP_PSS_setHighSidePerformanceMode                                    \
+        PSS_setHighSidePerformanceMode
+#endif
+#ifdef ROM_PSS_getHighSidePerformanceMode
+#define MAP_PSS_getHighSidePerformanceMode                                    \
+        ROM_PSS_getHighSidePerformanceMode
+#else
+#define MAP_PSS_getHighSidePerformanceMode                                    \
+        PSS_getHighSidePerformanceMode
+#endif
+#ifdef ROM_PSS_enableHighSideMonitor
+#define MAP_PSS_enableHighSideMonitor                                         \
+        ROM_PSS_enableHighSideMonitor
+#else
+#define MAP_PSS_enableHighSideMonitor                                         \
+        PSS_enableHighSideMonitor
+#endif
+#ifdef ROM_PSS_disableHighSideMonitor
+#define MAP_PSS_disableHighSideMonitor                                        \
+        ROM_PSS_disableHighSideMonitor
+#else
+#define MAP_PSS_disableHighSideMonitor                                        \
+        PSS_disableHighSideMonitor
+#endif
+#ifdef ROM_PSS_setHighSideVoltageTrigger
+#define MAP_PSS_setHighSideVoltageTrigger                                     \
+        ROM_PSS_setHighSideVoltageTrigger
+#else
+#define MAP_PSS_setHighSideVoltageTrigger                                     \
+        PSS_setHighSideVoltageTrigger
+#endif
+#ifdef ROM_PSS_getHighSideVoltageTrigger
+#define MAP_PSS_getHighSideVoltageTrigger                                     \
+        ROM_PSS_getHighSideVoltageTrigger
+#else
+#define MAP_PSS_getHighSideVoltageTrigger                                     \
+        PSS_getHighSideVoltageTrigger
+#endif
+#ifdef ROM_PSS_enableInterrupt
+#define MAP_PSS_enableInterrupt                                               \
+        ROM_PSS_enableInterrupt
+#else
+#define MAP_PSS_enableInterrupt                                               \
+        PSS_enableInterrupt
+#endif
+#ifdef ROM_PSS_disableInterrupt
+#define MAP_PSS_disableInterrupt                                              \
+        ROM_PSS_disableInterrupt
+#else
+#define MAP_PSS_disableInterrupt                                              \
+        PSS_disableInterrupt
+#endif
+#ifdef ROM_PSS_getInterruptStatus
+#define MAP_PSS_getInterruptStatus                                            \
+        ROM_PSS_getInterruptStatus
+#else
+#define MAP_PSS_getInterruptStatus                                            \
+        PSS_getInterruptStatus
+#endif
+#ifdef ROM_PSS_clearInterruptFlag
+#define MAP_PSS_clearInterruptFlag                                            \
+        ROM_PSS_clearInterruptFlag
+#else
+#define MAP_PSS_clearInterruptFlag                                            \
+        PSS_clearInterruptFlag
+#endif
+#ifdef ROM_PSS_registerInterrupt
+#define MAP_PSS_registerInterrupt                                             \
+        ROM_PSS_registerInterrupt
+#else
+#define MAP_PSS_registerInterrupt                                             \
+        PSS_registerInterrupt
+#endif
+#ifdef ROM_PSS_unregisterInterrupt
+#define MAP_PSS_unregisterInterrupt                                           \
+        ROM_PSS_unregisterInterrupt
+#else
+#define MAP_PSS_unregisterInterrupt                                           \
+        PSS_unregisterInterrupt
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Ref API.
+//
+//*****************************************************************************
+#ifdef ROM_REF_A_setReferenceVoltage
+#define MAP_REF_A_setReferenceVoltage                                         \
+        ROM_REF_A_setReferenceVoltage
+#else
+#define MAP_REF_A_setReferenceVoltage                                         \
+        REF_A_setReferenceVoltage
+#endif
+#ifdef ROM_REF_A_disableTempSensor
+#define MAP_REF_A_disableTempSensor                                           \
+        ROM_REF_A_disableTempSensor
+#else
+#define MAP_REF_A_disableTempSensor                                           \
+        REF_A_disableTempSensor
+#endif
+#ifdef ROM_REF_A_enableTempSensor
+#define MAP_REF_A_enableTempSensor                                            \
+        ROM_REF_A_enableTempSensor
+#else
+#define MAP_REF_A_enableTempSensor                                            \
+        REF_A_enableTempSensor
+#endif
+#ifdef ROM_REF_A_enableReferenceVoltageOutput
+#define MAP_REF_A_enableReferenceVoltageOutput                                \
+        ROM_REF_A_enableReferenceVoltageOutput
+#else
+#define MAP_REF_A_enableReferenceVoltageOutput                                \
+        REF_A_enableReferenceVoltageOutput
+#endif
+#ifdef ROM_REF_A_disableReferenceVoltageOutput
+#define MAP_REF_A_disableReferenceVoltageOutput                               \
+        ROM_REF_A_disableReferenceVoltageOutput
+#else
+#define MAP_REF_A_disableReferenceVoltageOutput                               \
+        REF_A_disableReferenceVoltageOutput
+#endif
+#ifdef ROM_REF_A_enableReferenceVoltage
+#define MAP_REF_A_enableReferenceVoltage                                      \
+        ROM_REF_A_enableReferenceVoltage
+#else
+#define MAP_REF_A_enableReferenceVoltage                                      \
+        REF_A_enableReferenceVoltage
+#endif
+#ifdef ROM_REF_A_disableReferenceVoltage
+#define MAP_REF_A_disableReferenceVoltage                                     \
+        ROM_REF_A_disableReferenceVoltage
+#else
+#define MAP_REF_A_disableReferenceVoltage                                     \
+        REF_A_disableReferenceVoltage
+#endif
+#ifdef ROM_REF_A_getBandgapMode
+#define MAP_REF_A_getBandgapMode                                              \
+        ROM_REF_A_getBandgapMode
+#else
+#define MAP_REF_A_getBandgapMode                                              \
+        REF_A_getBandgapMode
+#endif
+#ifdef ROM_REF_A_isBandgapActive
+#define MAP_REF_A_isBandgapActive                                             \
+        ROM_REF_A_isBandgapActive
+#else
+#define MAP_REF_A_isBandgapActive                                             \
+        REF_A_isBandgapActive
+#endif
+#ifdef ROM_REF_A_isRefGenBusy
+#define MAP_REF_A_isRefGenBusy                                                \
+        ROM_REF_A_isRefGenBusy
+#else
+#define MAP_REF_A_isRefGenBusy                                                \
+        REF_A_isRefGenBusy
+#endif
+#ifdef ROM_REF_A_isRefGenActive
+#define MAP_REF_A_isRefGenActive                                              \
+        ROM_REF_A_isRefGenActive
+#else
+#define MAP_REF_A_isRefGenActive                                              \
+        REF_A_isRefGenActive
+#endif
+#ifdef ROM_REF_A_getBufferedBandgapVoltageStatus
+#define MAP_REF_A_getBufferedBandgapVoltageStatus                             \
+        ROM_REF_A_getBufferedBandgapVoltageStatus
+#else
+#define MAP_REF_A_getBufferedBandgapVoltageStatus                             \
+        REF_A_getBufferedBandgapVoltageStatus
+#endif
+#ifdef ROM_REF_A_getVariableReferenceVoltageStatus
+#define MAP_REF_A_getVariableReferenceVoltageStatus                           \
+        ROM_REF_A_getVariableReferenceVoltageStatus
+#else
+#define MAP_REF_A_getVariableReferenceVoltageStatus                           \
+        REF_A_getVariableReferenceVoltageStatus
+#endif
+#ifdef ROM_REF_A_setReferenceVoltageOneTimeTrigger
+#define MAP_REF_A_setReferenceVoltageOneTimeTrigger                           \
+        ROM_REF_A_setReferenceVoltageOneTimeTrigger
+#else
+#define MAP_REF_A_setReferenceVoltageOneTimeTrigger                           \
+        REF_A_setReferenceVoltageOneTimeTrigger
+#endif
+#ifdef ROM_REF_A_setBufferedBandgapVoltageOneTimeTrigger
+#define MAP_REF_A_setBufferedBandgapVoltageOneTimeTrigger                     \
+        ROM_REF_A_setBufferedBandgapVoltageOneTimeTrigger
+#else
+#define MAP_REF_A_setBufferedBandgapVoltageOneTimeTrigger                     \
+        REF_A_setBufferedBandgapVoltageOneTimeTrigger
+#endif
+
+//*****************************************************************************
+//
+// Macros for the ResetCtl API.
+//
+//*****************************************************************************
+#ifdef ROM_ResetCtl_initiateSoftReset
+#define MAP_ResetCtl_initiateSoftReset                                        \
+        ROM_ResetCtl_initiateSoftReset
+#else
+#define MAP_ResetCtl_initiateSoftReset                                        \
+        ResetCtl_initiateSoftReset
+#endif
+#ifdef ROM_ResetCtl_initiateSoftResetWithSource
+#define MAP_ResetCtl_initiateSoftResetWithSource                              \
+        ROM_ResetCtl_initiateSoftResetWithSource
+#else
+#define MAP_ResetCtl_initiateSoftResetWithSource                              \
+        ResetCtl_initiateSoftResetWithSource
+#endif
+#ifdef ROM_ResetCtl_getSoftResetSource
+#define MAP_ResetCtl_getSoftResetSource                                       \
+        ROM_ResetCtl_getSoftResetSource
+#else
+#define MAP_ResetCtl_getSoftResetSource                                       \
+        ResetCtl_getSoftResetSource
+#endif
+#ifdef ROM_ResetCtl_clearSoftResetSource
+#define MAP_ResetCtl_clearSoftResetSource                                     \
+        ROM_ResetCtl_clearSoftResetSource
+#else
+#define MAP_ResetCtl_clearSoftResetSource                                     \
+        ResetCtl_clearSoftResetSource
+#endif
+#ifdef ROM_ResetCtl_initiateHardReset
+#define MAP_ResetCtl_initiateHardReset                                        \
+        ROM_ResetCtl_initiateHardReset
+#else
+#define MAP_ResetCtl_initiateHardReset                                        \
+        ResetCtl_initiateHardReset
+#endif
+#ifdef ROM_ResetCtl_initiateHardResetWithSource
+#define MAP_ResetCtl_initiateHardResetWithSource                              \
+        ROM_ResetCtl_initiateHardResetWithSource
+#else
+#define MAP_ResetCtl_initiateHardResetWithSource                              \
+        ResetCtl_initiateHardResetWithSource
+#endif
+#ifdef ROM_ResetCtl_getHardResetSource
+#define MAP_ResetCtl_getHardResetSource                                       \
+        ROM_ResetCtl_getHardResetSource
+#else
+#define MAP_ResetCtl_getHardResetSource                                       \
+        ResetCtl_getHardResetSource
+#endif
+#ifdef ROM_ResetCtl_clearHardResetSource
+#define MAP_ResetCtl_clearHardResetSource                                     \
+        ROM_ResetCtl_clearHardResetSource
+#else
+#define MAP_ResetCtl_clearHardResetSource                                     \
+        ResetCtl_clearHardResetSource
+#endif
+#ifdef ROM_ResetCtl_getPSSSource
+#define MAP_ResetCtl_getPSSSource                                             \
+        ROM_ResetCtl_getPSSSource
+#else
+#define MAP_ResetCtl_getPSSSource                                             \
+        ResetCtl_getPSSSource
+#endif
+#ifdef ROM_ResetCtl_clearPSSFlags
+#define MAP_ResetCtl_clearPSSFlags                                            \
+        ROM_ResetCtl_clearPSSFlags
+#else
+#define MAP_ResetCtl_clearPSSFlags                                            \
+        ResetCtl_clearPSSFlags
+#endif
+#ifdef ROM_ResetCtl_getPCMSource
+#define MAP_ResetCtl_getPCMSource                                             \
+        ROM_ResetCtl_getPCMSource
+#else
+#define MAP_ResetCtl_getPCMSource                                             \
+        ResetCtl_getPCMSource
+#endif
+#ifdef ROM_ResetCtl_clearPCMFlags
+#define MAP_ResetCtl_clearPCMFlags                                            \
+        ROM_ResetCtl_clearPCMFlags
+#else
+#define MAP_ResetCtl_clearPCMFlags                                            \
+        ResetCtl_clearPCMFlags
+#endif
+
+//*****************************************************************************
+//
+// Macros for the RTC API.
+//
+//*****************************************************************************
+#ifdef ROM_RTC_C_startClock
+#define MAP_RTC_C_startClock                                                  \
+        ROM_RTC_C_startClock
+#else
+#define MAP_RTC_C_startClock                                                  \
+        RTC_C_startClock
+#endif
+#ifdef ROM_RTC_C_holdClock
+#define MAP_RTC_C_holdClock                                                   \
+        ROM_RTC_C_holdClock
+#else
+#define MAP_RTC_C_holdClock                                                   \
+        RTC_C_holdClock
+#endif
+#ifdef ROM_RTC_C_setCalibrationFrequency
+#define MAP_RTC_C_setCalibrationFrequency                                     \
+        ROM_RTC_C_setCalibrationFrequency
+#else
+#define MAP_RTC_C_setCalibrationFrequency                                     \
+        RTC_C_setCalibrationFrequency
+#endif
+#ifdef ROM_RTC_C_setCalibrationData
+#define MAP_RTC_C_setCalibrationData                                          \
+        ROM_RTC_C_setCalibrationData
+#else
+#define MAP_RTC_C_setCalibrationData                                          \
+        RTC_C_setCalibrationData
+#endif
+#ifdef ROM_RTC_C_setTemperatureCompensation
+#define MAP_RTC_C_setTemperatureCompensation                                  \
+        ROM_RTC_C_setTemperatureCompensation
+#else
+#define MAP_RTC_C_setTemperatureCompensation                                  \
+        RTC_C_setTemperatureCompensation
+#endif
+#ifdef ROM_RTC_C_initCalendar
+#define MAP_RTC_C_initCalendar                                                \
+        ROM_RTC_C_initCalendar
+#else
+#define MAP_RTC_C_initCalendar                                                \
+        RTC_C_initCalendar
+#endif
+#ifdef ROM_RTC_C_getCalendarTime
+#define MAP_RTC_C_getCalendarTime                                             \
+        ROM_RTC_C_getCalendarTime
+#else
+#define MAP_RTC_C_getCalendarTime                                             \
+        RTC_C_getCalendarTime
+#endif
+#ifdef ROM_RTC_C_setCalendarAlarm
+#define MAP_RTC_C_setCalendarAlarm                                            \
+        ROM_RTC_C_setCalendarAlarm
+#else
+#define MAP_RTC_C_setCalendarAlarm                                            \
+        RTC_C_setCalendarAlarm
+#endif
+#ifdef ROM_RTC_C_setCalendarEvent
+#define MAP_RTC_C_setCalendarEvent                                            \
+        ROM_RTC_C_setCalendarEvent
+#else
+#define MAP_RTC_C_setCalendarEvent                                            \
+        RTC_C_setCalendarEvent
+#endif
+#ifdef ROM_RTC_C_definePrescaleEvent
+#define MAP_RTC_C_definePrescaleEvent                                         \
+        ROM_RTC_C_definePrescaleEvent
+#else
+#define MAP_RTC_C_definePrescaleEvent                                         \
+        RTC_C_definePrescaleEvent
+#endif
+#ifdef ROM_RTC_C_getPrescaleValue
+#define MAP_RTC_C_getPrescaleValue                                            \
+        ROM_RTC_C_getPrescaleValue
+#else
+#define MAP_RTC_C_getPrescaleValue                                            \
+        RTC_C_getPrescaleValue
+#endif
+#ifdef ROM_RTC_C_setPrescaleValue
+#define MAP_RTC_C_setPrescaleValue                                            \
+        ROM_RTC_C_setPrescaleValue
+#else
+#define MAP_RTC_C_setPrescaleValue                                            \
+        RTC_C_setPrescaleValue
+#endif
+#ifdef ROM_RTC_C_convertBCDToBinary
+#define MAP_RTC_C_convertBCDToBinary                                          \
+        ROM_RTC_C_convertBCDToBinary
+#else
+#define MAP_RTC_C_convertBCDToBinary                                          \
+        RTC_C_convertBCDToBinary
+#endif
+#ifdef ROM_RTC_C_convertBinaryToBCD
+#define MAP_RTC_C_convertBinaryToBCD                                          \
+        ROM_RTC_C_convertBinaryToBCD
+#else
+#define MAP_RTC_C_convertBinaryToBCD                                          \
+        RTC_C_convertBinaryToBCD
+#endif
+#ifdef ROM_RTC_C_enableInterrupt
+#define MAP_RTC_C_enableInterrupt                                             \
+        ROM_RTC_C_enableInterrupt
+#else
+#define MAP_RTC_C_enableInterrupt                                             \
+        RTC_C_enableInterrupt
+#endif
+#ifdef ROM_RTC_C_disableInterrupt
+#define MAP_RTC_C_disableInterrupt                                            \
+        ROM_RTC_C_disableInterrupt
+#else
+#define MAP_RTC_C_disableInterrupt                                            \
+        RTC_C_disableInterrupt
+#endif
+#ifdef ROM_RTC_C_getInterruptStatus
+#define MAP_RTC_C_getInterruptStatus                                          \
+        ROM_RTC_C_getInterruptStatus
+#else
+#define MAP_RTC_C_getInterruptStatus                                          \
+        RTC_C_getInterruptStatus
+#endif
+#ifdef ROM_RTC_C_getEnabledInterruptStatus
+#define MAP_RTC_C_getEnabledInterruptStatus                                   \
+        ROM_RTC_C_getEnabledInterruptStatus
+#else
+#define MAP_RTC_C_getEnabledInterruptStatus                                   \
+        RTC_C_getEnabledInterruptStatus
+#endif
+#ifdef ROM_RTC_C_clearInterruptFlag
+#define MAP_RTC_C_clearInterruptFlag                                          \
+        ROM_RTC_C_clearInterruptFlag
+#else
+#define MAP_RTC_C_clearInterruptFlag                                          \
+        RTC_C_clearInterruptFlag
+#endif
+#ifdef ROM_RTC_C_registerInterrupt
+#define MAP_RTC_C_registerInterrupt                                           \
+        ROM_RTC_C_registerInterrupt
+#else
+#define MAP_RTC_C_registerInterrupt                                           \
+        RTC_C_registerInterrupt
+#endif
+#ifdef ROM_RTC_C_unregisterInterrupt
+#define MAP_RTC_C_unregisterInterrupt                                         \
+        ROM_RTC_C_unregisterInterrupt
+#else
+#define MAP_RTC_C_unregisterInterrupt                                         \
+        RTC_C_unregisterInterrupt
+#endif
+
+//*****************************************************************************
+//
+// Macros for the SPI API.
+//
+//*****************************************************************************
+#ifdef ROM_SPI_initMaster
+#define MAP_SPI_initMaster                                                    \
+        ROM_SPI_initMaster
+#else
+#define MAP_SPI_initMaster                                                    \
+        SPI_initMaster
+#endif
+#ifdef ROM_SPI_selectFourPinFunctionality
+#define MAP_SPI_selectFourPinFunctionality                                    \
+        ROM_SPI_selectFourPinFunctionality
+#else
+#define MAP_SPI_selectFourPinFunctionality                                    \
+        SPI_selectFourPinFunctionality
+#endif
+#ifdef ROM_SPI_changeMasterClock
+#define MAP_SPI_changeMasterClock                                             \
+        ROM_SPI_changeMasterClock
+#else
+#define MAP_SPI_changeMasterClock                                             \
+        SPI_changeMasterClock
+#endif
+#ifdef ROM_SPI_initSlave
+#define MAP_SPI_initSlave                                                     \
+        ROM_SPI_initSlave
+#else
+#define MAP_SPI_initSlave                                                     \
+        SPI_initSlave
+#endif
+#ifdef ROM_SPI_changeClockPhasePolarity
+#define MAP_SPI_changeClockPhasePolarity                                      \
+        ROM_SPI_changeClockPhasePolarity
+#else
+#define MAP_SPI_changeClockPhasePolarity                                      \
+        SPI_changeClockPhasePolarity
+#endif
+#ifdef ROM_SPI_transmitData
+#define MAP_SPI_transmitData                                                  \
+        ROM_SPI_transmitData
+#else
+#define MAP_SPI_transmitData                                                  \
+        SPI_transmitData
+#endif
+#ifdef ROM_SPI_receiveData
+#define MAP_SPI_receiveData                                                   \
+        ROM_SPI_receiveData
+#else
+#define MAP_SPI_receiveData                                                   \
+        SPI_receiveData
+#endif
+#ifdef ROM_SPI_enableModule
+#define MAP_SPI_enableModule                                                  \
+        ROM_SPI_enableModule
+#else
+#define MAP_SPI_enableModule                                                  \
+        SPI_enableModule
+#endif
+#ifdef ROM_SPI_disableModule
+#define MAP_SPI_disableModule                                                 \
+        ROM_SPI_disableModule
+#else
+#define MAP_SPI_disableModule                                                 \
+        SPI_disableModule
+#endif
+#ifdef ROM_SPI_getReceiveBufferAddressForDMA
+#define MAP_SPI_getReceiveBufferAddressForDMA                                 \
+        ROM_SPI_getReceiveBufferAddressForDMA
+#else
+#define MAP_SPI_getReceiveBufferAddressForDMA                                 \
+        SPI_getReceiveBufferAddressForDMA
+#endif
+#ifdef ROM_SPI_getTransmitBufferAddressForDMA
+#define MAP_SPI_getTransmitBufferAddressForDMA                                \
+        ROM_SPI_getTransmitBufferAddressForDMA
+#else
+#define MAP_SPI_getTransmitBufferAddressForDMA                                \
+        SPI_getTransmitBufferAddressForDMA
+#endif
+#ifdef ROM_SPI_isBusy
+#define MAP_SPI_isBusy                                                        \
+        ROM_SPI_isBusy
+#else
+#define MAP_SPI_isBusy                                                        \
+        SPI_isBusy
+#endif
+#ifdef ROM_SPI_enableInterrupt
+#define MAP_SPI_enableInterrupt                                               \
+        ROM_SPI_enableInterrupt
+#else
+#define MAP_SPI_enableInterrupt                                               \
+        SPI_enableInterrupt
+#endif
+#ifdef ROM_SPI_disableInterrupt
+#define MAP_SPI_disableInterrupt                                              \
+        ROM_SPI_disableInterrupt
+#else
+#define MAP_SPI_disableInterrupt                                              \
+        SPI_disableInterrupt
+#endif
+#ifdef ROM_SPI_getInterruptStatus
+#define MAP_SPI_getInterruptStatus                                            \
+        ROM_SPI_getInterruptStatus
+#else
+#define MAP_SPI_getInterruptStatus                                            \
+        SPI_getInterruptStatus
+#endif
+#ifdef ROM_SPI_getEnabledInterruptStatus
+#define MAP_SPI_getEnabledInterruptStatus                                     \
+        ROM_SPI_getEnabledInterruptStatus
+#else
+#define MAP_SPI_getEnabledInterruptStatus                                     \
+        SPI_getEnabledInterruptStatus
+#endif
+#ifdef ROM_SPI_clearInterruptFlag
+#define MAP_SPI_clearInterruptFlag                                            \
+        ROM_SPI_clearInterruptFlag
+#else
+#define MAP_SPI_clearInterruptFlag                                            \
+        SPI_clearInterruptFlag
+#endif
+#ifdef ROM_SPI_registerInterrupt
+#define MAP_SPI_registerInterrupt                                             \
+        ROM_SPI_registerInterrupt
+#else
+#define MAP_SPI_registerInterrupt                                             \
+        SPI_registerInterrupt
+#endif
+#ifdef ROM_SPI_unregisterInterrupt
+#define MAP_SPI_unregisterInterrupt                                           \
+        ROM_SPI_unregisterInterrupt
+#else
+#define MAP_SPI_unregisterInterrupt                                           \
+        SPI_unregisterInterrupt
+#endif
+
+//*****************************************************************************
+//
+// Macros for the SysCtl API.
+//
+//*****************************************************************************
+#ifdef ROM_SysCtl_getSRAMSize
+#define MAP_SysCtl_getSRAMSize                                                \
+        ROM_SysCtl_getSRAMSize
+#else
+#define MAP_SysCtl_getSRAMSize                                                \
+        SysCtl_getSRAMSize
+#endif
+#ifdef ROM_SysCtl_getFlashSize
+#define MAP_SysCtl_getFlashSize                                               \
+        ROM_SysCtl_getFlashSize
+#else
+#define MAP_SysCtl_getFlashSize                                               \
+        SysCtl_getFlashSize
+#endif
+#ifdef ROM_SysCtl_rebootDevice
+#define MAP_SysCtl_rebootDevice                                               \
+        ROM_SysCtl_rebootDevice
+#else
+#define MAP_SysCtl_rebootDevice                                               \
+        SysCtl_rebootDevice
+#endif
+#ifdef ROM_SysCtl_enableSRAMBank
+#define MAP_SysCtl_enableSRAMBank                                             \
+        ROM_SysCtl_enableSRAMBank
+#else
+#define MAP_SysCtl_enableSRAMBank                                             \
+        SysCtl_enableSRAMBank
+#endif
+#ifdef ROM_SysCtl_disableSRAMBank
+#define MAP_SysCtl_disableSRAMBank                                            \
+        ROM_SysCtl_disableSRAMBank
+#else
+#define MAP_SysCtl_disableSRAMBank                                            \
+        SysCtl_disableSRAMBank
+#endif
+#ifdef ROM_SysCtl_enableSRAMBankRetention
+#define MAP_SysCtl_enableSRAMBankRetention                                    \
+        ROM_SysCtl_enableSRAMBankRetention
+#else
+#define MAP_SysCtl_enableSRAMBankRetention                                    \
+        SysCtl_enableSRAMBankRetention
+#endif
+#ifdef ROM_SysCtl_disableSRAMBankRetention
+#define MAP_SysCtl_disableSRAMBankRetention                                   \
+        ROM_SysCtl_disableSRAMBankRetention
+#else
+#define MAP_SysCtl_disableSRAMBankRetention                                   \
+        SysCtl_disableSRAMBankRetention
+#endif
+#ifdef ROM_SysCtl_enablePeripheralAtCPUHalt
+#define MAP_SysCtl_enablePeripheralAtCPUHalt                                  \
+        ROM_SysCtl_enablePeripheralAtCPUHalt
+#else
+#define MAP_SysCtl_enablePeripheralAtCPUHalt                                  \
+        SysCtl_enablePeripheralAtCPUHalt
+#endif
+#ifdef ROM_SysCtl_disablePeripheralAtCPUHalt
+#define MAP_SysCtl_disablePeripheralAtCPUHalt                                 \
+        ROM_SysCtl_disablePeripheralAtCPUHalt
+#else
+#define MAP_SysCtl_disablePeripheralAtCPUHalt                                 \
+        SysCtl_disablePeripheralAtCPUHalt
+#endif
+#ifdef ROM_SysCtl_setWDTTimeoutResetType
+#define MAP_SysCtl_setWDTTimeoutResetType                                     \
+        ROM_SysCtl_setWDTTimeoutResetType
+#else
+#define MAP_SysCtl_setWDTTimeoutResetType                                     \
+        SysCtl_setWDTTimeoutResetType
+#endif
+#ifdef ROM_SysCtl_setWDTPasswordViolationResetType
+#define MAP_SysCtl_setWDTPasswordViolationResetType                           \
+        ROM_SysCtl_setWDTPasswordViolationResetType
+#else
+#define MAP_SysCtl_setWDTPasswordViolationResetType                           \
+        SysCtl_setWDTPasswordViolationResetType
+#endif
+#ifdef ROM_SysCtl_disableNMISource
+#define MAP_SysCtl_disableNMISource                                           \
+        ROM_SysCtl_disableNMISource
+#else
+#define MAP_SysCtl_disableNMISource                                           \
+        SysCtl_disableNMISource
+#endif
+#ifdef ROM_SysCtl_enableNMISource
+#define MAP_SysCtl_enableNMISource                                            \
+        ROM_SysCtl_enableNMISource
+#else
+#define MAP_SysCtl_enableNMISource                                            \
+        SysCtl_enableNMISource
+#endif
+#ifdef ROM_SysCtl_getNMISourceStatus
+#define MAP_SysCtl_getNMISourceStatus                                         \
+        ROM_SysCtl_getNMISourceStatus
+#else
+#define MAP_SysCtl_getNMISourceStatus                                         \
+        SysCtl_getNMISourceStatus
+#endif
+#ifdef ROM_SysCtl_getTempCalibrationConstant
+#define MAP_SysCtl_getTempCalibrationConstant                                 \
+        ROM_SysCtl_getTempCalibrationConstant
+#else
+#define MAP_SysCtl_getTempCalibrationConstant                                 \
+        SysCtl_getTempCalibrationConstant
+#endif
+
+//*****************************************************************************
+//
+// Macros for the SysTick API.
+//
+//*****************************************************************************
+#ifdef ROM_SysTick_enableModule
+#define MAP_SysTick_enableModule                                              \
+        ROM_SysTick_enableModule
+#else
+#define MAP_SysTick_enableModule                                              \
+        SysTick_enableModule
+#endif
+#ifdef ROM_SysTick_disableModule
+#define MAP_SysTick_disableModule                                             \
+        ROM_SysTick_disableModule
+#else
+#define MAP_SysTick_disableModule                                             \
+        SysTick_disableModule
+#endif
+#ifdef ROM_SysTick_enableInterrupt
+#define MAP_SysTick_enableInterrupt                                           \
+        ROM_SysTick_enableInterrupt
+#else
+#define MAP_SysTick_enableInterrupt                                           \
+        SysTick_enableInterrupt
+#endif
+#ifdef ROM_SysTick_disableInterrupt
+#define MAP_SysTick_disableInterrupt                                          \
+        ROM_SysTick_disableInterrupt
+#else
+#define MAP_SysTick_disableInterrupt                                          \
+        SysTick_disableInterrupt
+#endif
+#ifdef ROM_SysTick_setPeriod
+#define MAP_SysTick_setPeriod                                                 \
+        ROM_SysTick_setPeriod
+#else
+#define MAP_SysTick_setPeriod                                                 \
+        SysTick_setPeriod
+#endif
+#ifdef ROM_SysTick_getPeriod
+#define MAP_SysTick_getPeriod                                                 \
+        ROM_SysTick_getPeriod
+#else
+#define MAP_SysTick_getPeriod                                                 \
+        SysTick_getPeriod
+#endif
+#ifdef ROM_SysTick_getValue
+#define MAP_SysTick_getValue                                                  \
+        ROM_SysTick_getValue
+#else
+#define MAP_SysTick_getValue                                                  \
+        SysTick_getValue
+#endif
+#ifdef ROM_SysTick_registerInterrupt
+#define MAP_SysTick_registerInterrupt                                         \
+        ROM_SysTick_registerInterrupt
+#else
+#define MAP_SysTick_registerInterrupt                                         \
+        SysTick_registerInterrupt
+#endif
+#ifdef ROM_SysTick_unregisterInterrupt
+#define MAP_SysTick_unregisterInterrupt                                       \
+        ROM_SysTick_unregisterInterrupt
+#else
+#define MAP_SysTick_unregisterInterrupt                                       \
+        SysTick_unregisterInterrupt
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Timer_A API.
+//
+//*****************************************************************************
+#ifdef ROM_Timer_A_startCounter
+#define MAP_Timer_A_startCounter                                              \
+        ROM_Timer_A_startCounter
+#else
+#define MAP_Timer_A_startCounter                                              \
+        Timer_A_startCounter
+#endif
+#ifdef ROM_Timer_A_configureContinuousMode
+#define MAP_Timer_A_configureContinuousMode                                   \
+        ROM_Timer_A_configureContinuousMode
+#else
+#define MAP_Timer_A_configureContinuousMode                                   \
+        Timer_A_configureContinuousMode
+#endif
+#ifdef ROM_Timer_A_configureUpMode
+#define MAP_Timer_A_configureUpMode                                           \
+        ROM_Timer_A_configureUpMode
+#else
+#define MAP_Timer_A_configureUpMode                                           \
+        Timer_A_configureUpMode
+#endif
+#ifdef ROM_Timer_A_configureUpDownMode
+#define MAP_Timer_A_configureUpDownMode                                       \
+        ROM_Timer_A_configureUpDownMode
+#else
+#define MAP_Timer_A_configureUpDownMode                                       \
+        Timer_A_configureUpDownMode
+#endif
+#ifdef ROM_Timer_A_initCapture
+#define MAP_Timer_A_initCapture                                               \
+        ROM_Timer_A_initCapture
+#else
+#define MAP_Timer_A_initCapture                                               \
+        Timer_A_initCapture
+#endif
+#ifdef ROM_Timer_A_initCompare
+#define MAP_Timer_A_initCompare                                               \
+        ROM_Timer_A_initCompare
+#else
+#define MAP_Timer_A_initCompare                                               \
+        Timer_A_initCompare
+#endif
+#ifdef ROM_Timer_A_clearTimer
+#define MAP_Timer_A_clearTimer                                                \
+        ROM_Timer_A_clearTimer
+#else
+#define MAP_Timer_A_clearTimer                                                \
+        Timer_A_clearTimer
+#endif
+#ifdef ROM_Timer_A_getSynchronizedCaptureCompareInput
+#define MAP_Timer_A_getSynchronizedCaptureCompareInput                        \
+        ROM_Timer_A_getSynchronizedCaptureCompareInput
+#else
+#define MAP_Timer_A_getSynchronizedCaptureCompareInput                        \
+        Timer_A_getSynchronizedCaptureCompareInput
+#endif
+#ifdef ROM_Timer_A_getOutputForOutputModeOutBitValue
+#define MAP_Timer_A_getOutputForOutputModeOutBitValue                         \
+        ROM_Timer_A_getOutputForOutputModeOutBitValue
+#else
+#define MAP_Timer_A_getOutputForOutputModeOutBitValue                         \
+        Timer_A_getOutputForOutputModeOutBitValue
+#endif
+#ifdef ROM_Timer_A_getCaptureCompareCount
+#define MAP_Timer_A_getCaptureCompareCount                                    \
+        ROM_Timer_A_getCaptureCompareCount
+#else
+#define MAP_Timer_A_getCaptureCompareCount                                    \
+        Timer_A_getCaptureCompareCount
+#endif
+#ifdef ROM_Timer_A_setOutputForOutputModeOutBitValue
+#define MAP_Timer_A_setOutputForOutputModeOutBitValue                         \
+        ROM_Timer_A_setOutputForOutputModeOutBitValue
+#else
+#define MAP_Timer_A_setOutputForOutputModeOutBitValue                         \
+        Timer_A_setOutputForOutputModeOutBitValue
+#endif
+#ifdef ROM_Timer_A_generatePWM
+#define MAP_Timer_A_generatePWM                                               \
+        ROM_Timer_A_generatePWM
+#else
+#define MAP_Timer_A_generatePWM                                               \
+        Timer_A_generatePWM
+#endif
+#ifdef ROM_Timer_A_stopTimer
+#define MAP_Timer_A_stopTimer                                                 \
+        ROM_Timer_A_stopTimer
+#else
+#define MAP_Timer_A_stopTimer                                                 \
+        Timer_A_stopTimer
+#endif
+#ifdef ROM_Timer_A_setCompareValue
+#define MAP_Timer_A_setCompareValue                                           \
+        ROM_Timer_A_setCompareValue
+#else
+#define MAP_Timer_A_setCompareValue                                           \
+        Timer_A_setCompareValue
+#endif
+#ifdef ROM_Timer_A_clearInterruptFlag
+#define MAP_Timer_A_clearInterruptFlag                                        \
+        ROM_Timer_A_clearInterruptFlag
+#else
+#define MAP_Timer_A_clearInterruptFlag                                        \
+        Timer_A_clearInterruptFlag
+#endif
+#ifdef ROM_Timer_A_clearCaptureCompareInterrupt
+#define MAP_Timer_A_clearCaptureCompareInterrupt                              \
+        ROM_Timer_A_clearCaptureCompareInterrupt
+#else
+#define MAP_Timer_A_clearCaptureCompareInterrupt                              \
+        Timer_A_clearCaptureCompareInterrupt
+#endif
+#ifdef ROM_Timer_A_enableInterrupt
+#define MAP_Timer_A_enableInterrupt                                           \
+        ROM_Timer_A_enableInterrupt
+#else
+#define MAP_Timer_A_enableInterrupt                                           \
+        Timer_A_enableInterrupt
+#endif
+#ifdef ROM_Timer_A_disableInterrupt
+#define MAP_Timer_A_disableInterrupt                                          \
+        ROM_Timer_A_disableInterrupt
+#else
+#define MAP_Timer_A_disableInterrupt                                          \
+        Timer_A_disableInterrupt
+#endif
+#ifdef ROM_Timer_A_getInterruptStatus
+#define MAP_Timer_A_getInterruptStatus                                        \
+        ROM_Timer_A_getInterruptStatus
+#else
+#define MAP_Timer_A_getInterruptStatus                                        \
+        Timer_A_getInterruptStatus
+#endif
+#ifdef ROM_Timer_A_getEnabledInterruptStatus
+#define MAP_Timer_A_getEnabledInterruptStatus                                 \
+        ROM_Timer_A_getEnabledInterruptStatus
+#else
+#define MAP_Timer_A_getEnabledInterruptStatus                                 \
+        Timer_A_getEnabledInterruptStatus
+#endif
+#ifdef ROM_Timer_A_enableCaptureCompareInterrupt
+#define MAP_Timer_A_enableCaptureCompareInterrupt                             \
+        ROM_Timer_A_enableCaptureCompareInterrupt
+#else
+#define MAP_Timer_A_enableCaptureCompareInterrupt                             \
+        Timer_A_enableCaptureCompareInterrupt
+#endif
+#ifdef ROM_Timer_A_disableCaptureCompareInterrupt
+#define MAP_Timer_A_disableCaptureCompareInterrupt                            \
+        ROM_Timer_A_disableCaptureCompareInterrupt
+#else
+#define MAP_Timer_A_disableCaptureCompareInterrupt                            \
+        Timer_A_disableCaptureCompareInterrupt
+#endif
+#ifdef ROM_Timer_A_getCaptureCompareInterruptStatus
+#define MAP_Timer_A_getCaptureCompareInterruptStatus                          \
+        ROM_Timer_A_getCaptureCompareInterruptStatus
+#else
+#define MAP_Timer_A_getCaptureCompareInterruptStatus                          \
+        Timer_A_getCaptureCompareInterruptStatus
+#endif
+#ifdef ROM_Timer_A_getCaptureCompareEnabledInterruptStatus
+#define MAP_Timer_A_getCaptureCompareEnabledInterruptStatus                   \
+        ROM_Timer_A_getCaptureCompareEnabledInterruptStatus
+#else
+#define MAP_Timer_A_getCaptureCompareEnabledInterruptStatus                   \
+        Timer_A_getCaptureCompareEnabledInterruptStatus
+#endif
+#ifdef ROM_Timer_A_registerInterrupt
+#define MAP_Timer_A_registerInterrupt                                         \
+        ROM_Timer_A_registerInterrupt
+#else
+#define MAP_Timer_A_registerInterrupt                                         \
+        Timer_A_registerInterrupt
+#endif
+#ifdef ROM_Timer_A_unregisterInterrupt
+#define MAP_Timer_A_unregisterInterrupt                                       \
+        ROM_Timer_A_unregisterInterrupt
+#else
+#define MAP_Timer_A_unregisterInterrupt                                       \
+        Timer_A_unregisterInterrupt
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Timer32 API.
+//
+//*****************************************************************************
+#ifdef ROM_Timer32_initModule
+#define MAP_Timer32_initModule                                                \
+        ROM_Timer32_initModule
+#else
+#define MAP_Timer32_initModule                                                \
+        Timer32_initModule
+#endif
+#ifdef ROM_Timer32_setCount
+#define MAP_Timer32_setCount                                                  \
+        ROM_Timer32_setCount
+#else
+#define MAP_Timer32_setCount                                                  \
+        Timer32_setCount
+#endif
+#ifdef ROM_Timer32_setCountInBackground
+#define MAP_Timer32_setCountInBackground                                      \
+        ROM_Timer32_setCountInBackground
+#else
+#define MAP_Timer32_setCountInBackground                                      \
+        Timer32_setCountInBackground
+#endif
+#ifdef ROM_Timer32_getValue
+#define MAP_Timer32_getValue                                                  \
+        ROM_Timer32_getValue
+#else
+#define MAP_Timer32_getValue                                                  \
+        Timer32_getValue
+#endif
+#ifdef ROM_Timer32_startTimer
+#define MAP_Timer32_startTimer                                                \
+        ROM_Timer32_startTimer
+#else
+#define MAP_Timer32_startTimer                                                \
+        Timer32_startTimer
+#endif
+#ifdef ROM_Timer32_haltTimer
+#define MAP_Timer32_haltTimer                                                 \
+        ROM_Timer32_haltTimer
+#else
+#define MAP_Timer32_haltTimer                                                 \
+        Timer32_haltTimer
+#endif
+#ifdef ROM_Timer32_enableInterrupt
+#define MAP_Timer32_enableInterrupt                                           \
+        ROM_Timer32_enableInterrupt
+#else
+#define MAP_Timer32_enableInterrupt                                           \
+        Timer32_enableInterrupt
+#endif
+#ifdef ROM_Timer32_disableInterrupt
+#define MAP_Timer32_disableInterrupt                                          \
+        ROM_Timer32_disableInterrupt
+#else
+#define MAP_Timer32_disableInterrupt                                          \
+        Timer32_disableInterrupt
+#endif
+#ifdef ROM_Timer32_clearInterruptFlag
+#define MAP_Timer32_clearInterruptFlag                                        \
+        ROM_Timer32_clearInterruptFlag
+#else
+#define MAP_Timer32_clearInterruptFlag                                        \
+        Timer32_clearInterruptFlag
+#endif
+#ifdef ROM_Timer32_getInterruptStatus
+#define MAP_Timer32_getInterruptStatus                                        \
+        ROM_Timer32_getInterruptStatus
+#else
+#define MAP_Timer32_getInterruptStatus                                        \
+        Timer32_getInterruptStatus
+#endif
+#ifdef ROM_Timer32_registerInterrupt
+#define MAP_Timer32_registerInterrupt                                         \
+        ROM_Timer32_registerInterrupt
+#else
+#define MAP_Timer32_registerInterrupt                                         \
+        Timer32_registerInterrupt
+#endif
+#ifdef ROM_Timer32_unregisterInterrupt
+#define MAP_Timer32_unregisterInterrupt                                       \
+        ROM_Timer32_unregisterInterrupt
+#else
+#define MAP_Timer32_unregisterInterrupt                                       \
+        Timer32_unregisterInterrupt
+#endif
+
+//*****************************************************************************
+//
+// Macros for the UART API.
+//
+//*****************************************************************************
+#ifdef ROM_UART_initModule
+#define MAP_UART_initModule                                                   \
+        ROM_UART_initModule
+#else
+#define MAP_UART_initModule                                                   \
+        UART_initModule
+#endif
+#ifdef ROM_UART_transmitData
+#define MAP_UART_transmitData                                                 \
+        ROM_UART_transmitData
+#else
+#define MAP_UART_transmitData                                                 \
+        UART_transmitData
+#endif
+#ifdef ROM_UART_enableModule
+#define MAP_UART_enableModule                                                 \
+        ROM_UART_enableModule
+#else
+#define MAP_UART_enableModule                                                 \
+        UART_enableModule
+#endif
+#ifdef ROM_UART_disableModule
+#define MAP_UART_disableModule                                                \
+        ROM_UART_disableModule
+#else
+#define MAP_UART_disableModule                                                \
+        UART_disableModule
+#endif
+#ifdef ROM_UART_queryStatusFlags
+#define MAP_UART_queryStatusFlags                                             \
+        ROM_UART_queryStatusFlags
+#else
+#define MAP_UART_queryStatusFlags                                             \
+        UART_queryStatusFlags
+#endif
+#ifdef ROM_UART_setDormant
+#define MAP_UART_setDormant                                                   \
+        ROM_UART_setDormant
+#else
+#define MAP_UART_setDormant                                                   \
+        UART_setDormant
+#endif
+#ifdef ROM_UART_resetDormant
+#define MAP_UART_resetDormant                                                 \
+        ROM_UART_resetDormant
+#else
+#define MAP_UART_resetDormant                                                 \
+        UART_resetDormant
+#endif
+#ifdef ROM_UART_transmitAddress
+#define MAP_UART_transmitAddress                                              \
+        ROM_UART_transmitAddress
+#else
+#define MAP_UART_transmitAddress                                              \
+        UART_transmitAddress
+#endif
+#ifdef ROM_UART_transmitBreak
+#define MAP_UART_transmitBreak                                                \
+        ROM_UART_transmitBreak
+#else
+#define MAP_UART_transmitBreak                                                \
+        UART_transmitBreak
+#endif
+#ifdef ROM_UART_getReceiveBufferAddressForDMA
+#define MAP_UART_getReceiveBufferAddressForDMA                                \
+        ROM_UART_getReceiveBufferAddressForDMA
+#else
+#define MAP_UART_getReceiveBufferAddressForDMA                                \
+        UART_getReceiveBufferAddressForDMA
+#endif
+#ifdef ROM_UART_getTransmitBufferAddressForDMA
+#define MAP_UART_getTransmitBufferAddressForDMA                               \
+        ROM_UART_getTransmitBufferAddressForDMA
+#else
+#define MAP_UART_getTransmitBufferAddressForDMA                               \
+        UART_getTransmitBufferAddressForDMA
+#endif
+#ifdef ROM_UART_selectDeglitchTime
+#define MAP_UART_selectDeglitchTime                                           \
+        ROM_UART_selectDeglitchTime
+#else
+#define MAP_UART_selectDeglitchTime                                           \
+        UART_selectDeglitchTime
+#endif
+#ifdef ROM_UART_enableInterrupt
+#define MAP_UART_enableInterrupt                                              \
+        ROM_UART_enableInterrupt
+#else
+#define MAP_UART_enableInterrupt                                              \
+        UART_enableInterrupt
+#endif
+#ifdef ROM_UART_disableInterrupt
+#define MAP_UART_disableInterrupt                                             \
+        ROM_UART_disableInterrupt
+#else
+#define MAP_UART_disableInterrupt                                             \
+        UART_disableInterrupt
+#endif
+#ifdef ROM_UART_getInterruptStatus
+#define MAP_UART_getInterruptStatus                                           \
+        ROM_UART_getInterruptStatus
+#else
+#define MAP_UART_getInterruptStatus                                           \
+        UART_getInterruptStatus
+#endif
+#ifdef ROM_UART_clearInterruptFlag
+#define MAP_UART_clearInterruptFlag                                           \
+        ROM_UART_clearInterruptFlag
+#else
+#define MAP_UART_clearInterruptFlag                                           \
+        UART_clearInterruptFlag
+#endif
+#ifdef ROM_UART_receiveData
+#define MAP_UART_receiveData                                                  \
+        ROM_UART_receiveData
+#else
+#define MAP_UART_receiveData                                                  \
+        UART_receiveData
+#endif
+#ifdef ROM_UART_getEnabledInterruptStatus
+#define MAP_UART_getEnabledInterruptStatus                                    \
+        ROM_UART_getEnabledInterruptStatus
+#else
+#define MAP_UART_getEnabledInterruptStatus                                    \
+        UART_getEnabledInterruptStatus
+#endif
+#ifdef ROM_UART_registerInterrupt
+#define MAP_UART_registerInterrupt                                            \
+        ROM_UART_registerInterrupt
+#else
+#define MAP_UART_registerInterrupt                                            \
+        UART_registerInterrupt
+#endif
+#ifdef ROM_UART_unregisterInterrupt
+#define MAP_UART_unregisterInterrupt                                          \
+        ROM_UART_unregisterInterrupt
+#else
+#define MAP_UART_unregisterInterrupt                                          \
+        UART_unregisterInterrupt
+#endif
+
+//*****************************************************************************
+//
+// Macros for the WDT API.
+//
+//*****************************************************************************
+#ifdef ROM_WDT_A_holdTimer
+#define MAP_WDT_A_holdTimer                                                   \
+        ROM_WDT_A_holdTimer
+#else
+#define MAP_WDT_A_holdTimer                                                   \
+        WDT_A_holdTimer
+#endif
+#ifdef ROM_WDT_A_startTimer
+#define MAP_WDT_A_startTimer                                                  \
+        ROM_WDT_A_startTimer
+#else
+#define MAP_WDT_A_startTimer                                                  \
+        WDT_A_startTimer
+#endif
+#ifdef ROM_WDT_A_clearTimer
+#define MAP_WDT_A_clearTimer                                                  \
+        ROM_WDT_A_clearTimer
+#else
+#define MAP_WDT_A_clearTimer                                                  \
+        WDT_A_clearTimer
+#endif
+#ifdef ROM_WDT_A_initWatchdogTimer
+#define MAP_WDT_A_initWatchdogTimer                                           \
+        ROM_WDT_A_initWatchdogTimer
+#else
+#define MAP_WDT_A_initWatchdogTimer                                           \
+        WDT_A_initWatchdogTimer
+#endif
+#ifdef ROM_WDT_A_initIntervalTimer
+#define MAP_WDT_A_initIntervalTimer                                           \
+        ROM_WDT_A_initIntervalTimer
+#else
+#define MAP_WDT_A_initIntervalTimer                                           \
+        WDT_A_initIntervalTimer
+#endif
+#ifdef ROM_WDT_A_registerInterrupt
+#define MAP_WDT_A_registerInterrupt                                           \
+        ROM_WDT_A_registerInterrupt
+#else
+#define MAP_WDT_A_registerInterrupt                                           \
+        WDT_A_registerInterrupt
+#endif
+#ifdef ROM_WDT_A_unregisterInterrupt
+#define MAP_WDT_A_unregisterInterrupt                                         \
+        ROM_WDT_A_unregisterInterrupt
+#else
+#define MAP_WDT_A_unregisterInterrupt                                         \
+        WDT_A_unregisterInterrupt
+#endif
+
+#endif // __ROM_MAP_H__
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rtc_c.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rtc_c.c
new file mode 100644
index 000000000..6f90093be
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rtc_c.c
@@ -0,0 +1,338 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#include <rtc_c.h>
+#include <interrupt.h>
+#include <debug.h>
+
+void RTC_C_startClock(void)
+{
+    RTC_C->rCTL0.b.bKEY = RTCKEY_H;
+    BITBAND_PERI(RTC_C->rCTL13.r, RTCHOLD_OFS) = 0;
+    BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
+}
+
+void RTC_C_holdClock(void)
+{
+    RTC_C->rCTL0.b.bKEY = RTCKEY_H;
+    BITBAND_PERI(RTC_C->rCTL13.r, RTCHOLD_OFS) = 1;
+    BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
+}
+
+void RTC_C_setCalibrationFrequency(uint_fast16_t frequencySelect)
+{
+    RTC_C->rCTL0.b.bKEY = RTCKEY_H;
+    RTC_C->rCTL13.r = (RTC_C->rCTL13.r & ~(RTCCALF_3)) | frequencySelect;
+    BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
+}
+
+void RTC_C_setCalibrationData(uint_fast8_t offsetDirection,
+        uint_fast8_t offsetValue)
+{
+    RTC_C->rCTL0.b.bKEY = RTCKEY_H;
+    RTC_C->rOCAL.r = offsetValue + offsetDirection;
+    BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
+}
+
+bool RTC_C_setTemperatureCompensation(uint_fast16_t offsetDirection,
+        uint_fast8_t offsetValue)
+{
+    while (!BITBAND_PERI(RTC_C->rTCMP.r, RTCTCRDY_OFS))
+        ;
+
+    RTC_C->rTCMP.r = offsetValue + offsetDirection;
+
+    if (BITBAND_PERI(RTC_C->rTCMP.r, RTCTCOK_OFS))
+        return true;
+    else
+        return false;
+}
+
+void RTC_C_initCalendar(const RTC_C_Calendar *calendarTime,
+        uint_fast16_t formatSelect)
+{
+    RTC_C->rCTL0.b.bKEY = RTCKEY_H;
+
+    BITBAND_PERI(RTC_C->rCTL13.r, RTCHOLD_OFS) = 1;
+
+    if (formatSelect)
+        BITBAND_PERI(RTC_C->rCTL13.r, RTCBCD_OFS) = 1;
+    else
+        BITBAND_PERI(RTC_C->rCTL13.r, RTCBCD_OFS) = 0;
+
+    RTC_C->rTIM0.b.bSEC = calendarTime->seconds;
+    RTC_C->rTIM0.b.bMIN = calendarTime->minutes;
+    RTC_C->rTIM1.b.bHOUR = calendarTime->hours;
+    RTC_C->rTIM1.b.bDOW = calendarTime->dayOfWeek;
+    RTC_C->rDATE.b.bDAY = calendarTime->dayOfmonth;
+    RTC_C->rDATE.b.bMON = calendarTime->month;
+    RTC_C->rYEAR.r = calendarTime->year;
+
+    BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
+}
+
+RTC_C_Calendar RTC_C_getCalendarTime(void)
+{
+    RTC_C_Calendar tempCal;
+
+    while (!(BITBAND_PERI(RTC_C->rCTL13.r, RTCRDY_OFS)))
+        ;
+
+    tempCal.seconds = RTC_C->rTIM0.b.bSEC;
+    tempCal.minutes = RTC_C->rTIM0.b.bMIN;
+    tempCal.hours = RTC_C->rTIM1.b.bHOUR;
+    tempCal.dayOfWeek = RTC_C->rTIM1.b.bDOW;
+    tempCal.dayOfmonth = RTC_C->rDATE.b.bDAY;
+    tempCal.month = RTC_C->rDATE.b.bMON;
+    tempCal.year = RTC_C->rYEAR.r;
+
+    return (tempCal);
+}
+
+void RTC_C_setCalendarAlarm(uint_fast8_t minutesAlarm, uint_fast8_t hoursAlarm,
+        uint_fast8_t dayOfWeekAlarm, uint_fast8_t dayOfmonthAlarm)
+{
+    //Each of these is XORed with 0x80 to turn on if an integer is passed,
+    //or turn OFF if RTC_ALARM_OFF (0x80) is passed.
+    HWREG8(RTC_C_BASE + OFS_RTCAMINHR) = (minutesAlarm ^ 0x80);
+    HWREG8(RTC_C_BASE + OFS_RTCAMINHR + 1) = (hoursAlarm ^ 0x80);
+    HWREG8(RTC_C_BASE + OFS_RTCADOWDAY) = (dayOfWeekAlarm ^ 0x80);
+    HWREG8(RTC_C_BASE + OFS_RTCADOWDAY + 1) = (dayOfmonthAlarm ^ 0x80);
+}
+
+void RTC_C_setCalendarEvent(uint_fast16_t eventSelect)
+{
+    RTC_C->rCTL0.b.bKEY = RTCKEY_H;
+    RTC_C->rCTL13.r = (RTC_C->rCTL13.r & ~(RTCTEV_3)) | eventSelect;
+    BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
+}
+
+void RTC_C_definePrescaleEvent(uint_fast8_t prescaleSelect,
+        uint_fast8_t prescaleEventDivider)
+{
+    HWREG8(RTC_C_BASE + OFS_RTCPS0CTL + prescaleSelect) &= ~(RT0IP_7);
+    HWREG8(RTC_C_BASE + OFS_RTCPS0CTL + prescaleSelect) |=
+            prescaleEventDivider;
+}
+
+uint_fast8_t RTC_C_getPrescaleValue(uint_fast8_t prescaleSelect)
+{
+    if (RTC_C_PRESCALE_0 == prescaleSelect)
+    {
+        return (RTC_C->rPS.b.bRT0PS);
+    } else if (RTC_C_PRESCALE_1 == prescaleSelect)
+    {
+        return (RTC_C->rPS.b.bRT1PS);
+    } else
+    {
+        return (0);
+    }
+}
+
+void RTC_C_setPrescaleValue(uint_fast8_t prescaleSelect,
+        uint_fast8_t prescaleCounterValue)
+{
+    RTC_C->rCTL0.b.bKEY = RTCKEY_H;
+
+    if (RTC_C_PRESCALE_0 == prescaleSelect)
+    {
+        RTC_C->rPS.b.bRT0PS = prescaleCounterValue;
+    } else if (RTC_C_PRESCALE_1 == prescaleSelect)
+    {
+        RTC_C->rPS.b.bRT1PS = prescaleCounterValue;
+    }
+
+    BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
+}
+
+uint16_t RTC_C_convertBCDToBinary(uint16_t valueToConvert)
+{
+    RTC_C->rBCD2BIN = valueToConvert;
+    return (RTC_C->rBCD2BIN);
+}
+
+uint16_t RTC_C_convertBinaryToBCD(uint16_t valueToConvert)
+{
+    RTC_C->rBIN2BCD = valueToConvert;
+    return (RTC_C->rBIN2BCD);
+}
+
+void RTC_C_enableInterrupt(uint8_t interruptMask)
+{
+    if (interruptMask & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE))
+    {
+        RTC_C->rCTL0.r = RTCKEY | (interruptMask
+                & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE));
+        BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
+    }
+
+    if (interruptMask & RTC_C_PRESCALE_TIMER0_INTERRUPT)
+    {
+        BITBAND_PERI(RTC_C->rPS0CTL.r,RT0PSIE_OFS) = 1;
+    }
+
+    if (interruptMask & RTC_C_PRESCALE_TIMER1_INTERRUPT)
+    {
+        BITBAND_PERI(RTC_C->rPS1CTL.r,RT1PSIE_OFS) = 1;
+    }
+}
+
+void RTC_C_disableInterrupt(uint8_t interruptMask)
+{
+    if (interruptMask & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE))
+    {
+        RTC_C->rCTL0.r = RTCKEY
+                | (RTC_C->rCTL0.r
+                        & ~((interruptMask | RTCKEY_M)
+                                & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE)));
+        BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
+    }
+
+    if (interruptMask & RTC_C_PRESCALE_TIMER0_INTERRUPT)
+    {
+        BITBAND_PERI(RTC_C->rPS0CTL.r,RT0PSIE_OFS) = 0;
+    }
+
+    if (interruptMask & RTC_C_PRESCALE_TIMER1_INTERRUPT)
+    {
+        BITBAND_PERI(RTC_C->rPS1CTL.r,RT1PSIE_OFS) = 0;
+    }
+}
+
+uint_fast8_t RTC_C_getInterruptStatus(void)
+{
+    uint_fast8_t tempInterruptFlagMask = 0x00;
+    uint_fast8_t interruptFlagMask = RTC_C_TIME_EVENT_INTERRUPT
+            | RTC_C_CLOCK_ALARM_INTERRUPT | RTC_C_CLOCK_READ_READY_INTERRUPT
+            | RTC_C_PRESCALE_TIMER0_INTERRUPT | RTC_C_PRESCALE_TIMER1_INTERRUPT
+            | RTC_C_OSCILLATOR_FAULT_INTERRUPT;
+
+    tempInterruptFlagMask |= (RTC_C->rCTL0.r & (interruptFlagMask >> 4));
+
+    tempInterruptFlagMask = tempInterruptFlagMask << 4;
+
+    if (interruptFlagMask & RTC_C_PRESCALE_TIMER0_INTERRUPT)
+    {
+        if (BITBAND_PERI(RTC_C->rPS0CTL.r, RT0PSIFG_OFS))
+        {
+            tempInterruptFlagMask |= RTC_C_PRESCALE_TIMER0_INTERRUPT;
+        }
+    }
+
+    if (interruptFlagMask & RTC_C_PRESCALE_TIMER1_INTERRUPT)
+    {
+        if (BITBAND_PERI(RTC_C->rPS1CTL.r, RT1PSIFG_OFS))
+        {
+            tempInterruptFlagMask |= RTC_C_PRESCALE_TIMER1_INTERRUPT;
+        }
+    }
+
+    return (tempInterruptFlagMask);
+}
+
+uint_fast8_t RTC_C_getEnabledInterruptStatus(void)
+{
+
+    uint32_t intStatus = RTC_C_getInterruptStatus();
+
+    if (!BITBAND_PERI(RTC_C->rCTL0.r, RTCOFIE_OFS))
+    {
+        intStatus &= ~RTC_C_OSCILLATOR_FAULT_INTERRUPT;
+    }
+
+    if (!BITBAND_PERI(RTC_C->rCTL0.r, RTCTEVIE_OFS))
+    {
+        intStatus &= ~RTC_C_TIME_EVENT_INTERRUPT;
+    }
+
+    if (!BITBAND_PERI(RTC_C->rCTL0.r, RTCAIE_OFS))
+    {
+        intStatus &= ~RTC_C_CLOCK_ALARM_INTERRUPT;
+    }
+
+    if (!BITBAND_PERI(RTC_C->rCTL0.r, RTCRDYIE_OFS))
+    {
+        intStatus &= ~RTC_C_CLOCK_READ_READY_INTERRUPT;
+    }
+
+    if (!BITBAND_PERI(RTC_C->rPS0CTL, RT0PSIE_OFS))
+    {
+        intStatus &= ~RTC_C_PRESCALE_TIMER0_INTERRUPT;
+    }
+
+    if (!BITBAND_PERI(RTC_C->rPS1CTL.r, RT1PSIE_OFS))
+    {
+        intStatus &= ~RTC_C_PRESCALE_TIMER1_INTERRUPT;
+    }
+
+    return intStatus;
+}
+
+void RTC_C_clearInterruptFlag(uint_fast8_t interruptFlagMask)
+{
+    if (interruptFlagMask
+            & (RTC_C_TIME_EVENT_INTERRUPT + RTC_C_CLOCK_ALARM_INTERRUPT
+                    + RTC_C_CLOCK_READ_READY_INTERRUPT
+                    + RTC_C_OSCILLATOR_FAULT_INTERRUPT))
+    {
+        RTC_C->rCTL0.r = RTCKEY
+                | (RTC_C->rCTL0.r & ~((interruptFlagMask >> 4) | RTCKEY_M));
+        BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
+    }
+
+    if (interruptFlagMask & RTC_C_PRESCALE_TIMER0_INTERRUPT)
+    {
+        BITBAND_PERI(RTC_C->rPS0CTL.r,RT0PSIFG_OFS) = 0;
+    }
+
+    if (interruptFlagMask & RTC_C_PRESCALE_TIMER1_INTERRUPT)
+    {
+        BITBAND_PERI(RTC_C->rPS1CTL.r, RT1PSIFG_OFS) = 0;
+    }
+}
+
+void RTC_C_registerInterrupt(void (*intHandler)(void))
+{
+    Interrupt_registerInterrupt(INT_RTC_C, intHandler);
+    Interrupt_enableInterrupt(INT_RTC_C);
+}
+
+void RTC_C_unregisterInterrupt(void)
+{
+    Interrupt_disableInterrupt(INT_RTC_C);
+    Interrupt_unregisterInterrupt(INT_RTC_C);
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rtc_c.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rtc_c.h
new file mode 100644
index 000000000..6786d4afa
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rtc_c.h
@@ -0,0 +1,661 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef RTC_C_H_
+#define RTC_C_H_
+
+//*****************************************************************************
+//
+//! \addtogroup rtc_api
+//! @{
+//
+//*****************************************************************************
+
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <msp.h>
+
+//*****************************************************************************
+//
+//The following is a struct that can be passed to RTC_CalendarInit() in the
+//CalendarTime parameter, as well as returned by RTC_getCalendarTime()
+//
+//*****************************************************************************
+typedef struct _RTC_C_Calendar
+{
+    uint_fast8_t seconds;
+    uint_fast8_t minutes;
+    uint_fast8_t hours;
+    uint_fast8_t dayOfWeek;
+    uint_fast8_t dayOfmonth;
+    uint_fast8_t month;
+    uint_fast16_t year;
+} RTC_C_Calendar;
+
+//*****************************************************************************
+//
+//The following are values that can be passed to RTC_setCalibrationData()
+//
+//*****************************************************************************
+#define RTC_C_CALIBRATIONFREQ_OFF   (RTCCALF_0)
+#define RTC_C_CALIBRATIONFREQ_512HZ (RTCCALF_1)
+#define RTC_C_CALIBRATIONFREQ_256HZ (RTCCALF_2)
+#define RTC_C_CALIBRATIONFREQ_1HZ   (RTCCALF_3)
+
+//*****************************************************************************
+//
+//The following are values that can be passed to RTC_setCalibrationData()
+//
+//*****************************************************************************
+#define RTC_C_CALIBRATION_DOWN1PPM  ( !(RTCOCALS) )
+#define RTC_C_CALIBRATION_UP1PPM    (RTCOCALS)
+
+//*****************************************************************************
+//
+//The following are values that can be passed to
+//RTC_setTemperatureCompensation()
+//
+//*****************************************************************************
+#define RTC_C_COMPENSATION_DOWN1PPM  ( !(RTCTCMPS) )
+#define RTC_C_COMPENSATION_UP1PPM    (RTCTCMPS)
+
+//*****************************************************************************
+//
+//The following are values that can be passed to RTC_iniRTC_Calendar()
+//
+//*****************************************************************************
+#define RTC_C_FORMAT_BINARY  ( !(RTCBCD) )
+#define RTC_C_FORMAT_BCD     (RTCBCD)
+
+//*****************************************************************************
+//
+//The following is a value that can be passed to RTC_seRTC_CalendarAlarm()
+//
+//*****************************************************************************
+#define RTC_C_ALARMCONDITION_OFF  (0x80)
+
+//*****************************************************************************
+//
+//The following are values that can be passed to RTC_seRTC_CalendarEvent()
+//in the eventSelect parameter.
+//
+//*****************************************************************************
+#define RTC_C_CALENDAREVENT_MINUTECHANGE  (RTCTEV_0)
+#define RTC_C_CALENDAREVENT_HOURCHANGE    (RTCTEV_1)
+#define RTC_C_CALENDAREVENT_NOON          (RTCTEV_2)
+#define RTC_C_CALENDAREVENT_MIDNIGHT      (RTCTEV_3)
+
+//*****************************************************************************
+//
+//The following are values that can be passed to RTC_definePrescaleEvent()
+//
+//*****************************************************************************
+#define RTC_C_PRESCALE_0  (0x0)
+#define RTC_C_PRESCALE_1  (0x1)
+
+//*****************************************************************************
+//
+//The following are values that can be passed to RTC_definePrescaleEvent()
+//in the prescaleEventDivider parameter.
+//
+//*****************************************************************************
+#define RTC_C_PSEVENTDIVIDER_2   (RT0IP_0)
+#define RTC_C_PSEVENTDIVIDER_4   (RT0IP_1)
+#define RTC_C_PSEVENTDIVIDER_8   (RT0IP_2)
+#define RTC_C_PSEVENTDIVIDER_16  (RT0IP_3)
+#define RTC_C_PSEVENTDIVIDER_32  (RT0IP_4)
+#define RTC_C_PSEVENTDIVIDER_64  (RT0IP_5)
+#define RTC_C_PSEVENTDIVIDER_128 (RT0IP_6)
+#define RTC_C_PSEVENTDIVIDER_256 (RT0IP_7)
+
+//*****************************************************************************
+//
+//The following are values that can be passed to the interrupt functions
+//
+//*****************************************************************************
+#define RTC_C_OSCILLATOR_FAULT_INTERRUPT  RTCOFIE
+#define RTC_C_TIME_EVENT_INTERRUPT        RTCTEVIE
+#define RTC_C_CLOCK_ALARM_INTERRUPT       RTCAIE
+#define RTC_C_CLOCK_READ_READY_INTERRUPT  RTCRDYIE
+#define RTC_C_PRESCALE_TIMER0_INTERRUPT   0x02
+#define RTC_C_PRESCALE_TIMER1_INTERRUPT   0x01
+
+//*****************************************************************************
+//
+//! Starts the RTC.
+//!
+//! This function clears the RTC main hold bit to allow the RTC to function.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void RTC_C_startClock(void);
+
+//*****************************************************************************
+//
+//! Holds the RTC.
+//!
+//! This function sets the RTC main hold bit to disable RTC functionality.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void RTC_C_holdClock(void);
+
+//*****************************************************************************
+//
+//! Allows and Sets the frequency output to RTCLK pin for calibration
+//! measurement.
+//!
+//! \param frequencySelect is the frequency output to RTCLK.
+//!        Valid values are
+//!        - \b   RTC_C_CALIBRATIONFREQ_OFF - turn off calibration
+//!                                                 output [Default]
+//!        - \b   RTC_C_CALIBRATIONFREQ_512HZ - output signal at 512Hz
+//!                                                     for calibration
+//!        - \b   RTC_C_CALIBRATIONFREQ_256HZ - output signal at 256Hz
+//!                                                     for calibration
+//!        - \b   RTC_C_CALIBRATIONFREQ_1HZ - output signal at 1Hz
+//!                                                     for calibration
+//!
+//! This function sets a frequency to measure at the RTCLK output pin. After
+//! testing the set frequency, the calibration could be set accordingly.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void RTC_C_setCalibrationFrequency(uint_fast16_t frequencySelect);
+
+//*****************************************************************************
+//
+//! Sets the specified calibration for the RTC.
+//!
+//! \param offsetDirection is the direction that the calibration offset will
+//!        go. Valid values are
+//!        - \b   RTC_C_CALIBRATION_DOWN1PPM - calibrate at steps of -1
+//!        - \b   RTC_C_CALIBRATION_UP1PPM - calibrat at steps of +1
+//! \param offsetValue is the value that the offset will be a factor of; a
+//!       valid value is any integer from 1-240.
+//!
+//! This function sets the calibration offset to make the RTC as accurate as
+//! possible. The offsetDirection can be either +1-ppm or -1-ppm, and the
+//! offsetValue should be from 1-240 and is multiplied by the direction setting
+//! (i.e. +1-ppm * 8 (offsetValue) = +8-ppm).
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void RTC_C_setCalibrationData(uint_fast8_t offsetDirection,
+        uint_fast8_t offsetValue);
+
+//*****************************************************************************
+//
+//! Sets the specified temperature compensation for the RTC.
+//!
+//! \param offsetDirection is the direction that the calibration offset will
+//!        go. Valid values are
+//!        - \b   RTC_C_COMPENSATION_DOWN1PPM - calibrate at steps of -1
+//!        - \b   RTC_C_COMPENSATION_UP1PPM - calibrate at steps of +1
+//! \param offsetValue is the value that the offset will be a factor of; a
+//!       value is any integer from 1-240.
+//!
+//! This function sets the calibration offset to make the RTC as accurate as
+//! possible. The offsetDirection can be either +1-ppm or -1-ppm, and the
+//! offsetValue should be from 1-240 and is multiplied by the direction setting
+//! (i.e. +1-ppm * 8 (offsetValue) = +8-ppm).
+//!
+//! \return true if calibration was set, false if it could not be set
+//!
+//
+//*****************************************************************************
+extern bool RTC_C_setTemperatureCompensation(uint_fast16_t offsetDirection,
+        uint_fast8_t offsetValue);
+
+//*****************************************************************************
+//
+//! Initializes the settings to operate the RTC in Calendar mode.
+//!
+//! \param calendarTime is the structure containing the values for the Calendar
+//!       to be initialized to.
+//!        Valid values should be of type Calendar and should contain the
+//!        following members and corresponding values:
+//!        - \b   seconds between 0-59
+//!        - \b   minutes between 0-59
+//!        - \b   hours between 0-24
+//!        - \b   dayOfWeek between 0-6
+//!        - \b   dayOfmonth between 0-31
+//!        - \b   year between 0-4095
+//!        \note Values beyond the ones specified may result in eradic behavior.
+//! \param formatSelect is the format for the Calendar registers to use.
+//!        Valid values are
+//!        - \b   RTC_FORMAT_BINARY [Default]
+//!        - \b   RTC_FORMAT_BCD
+//!
+//! This function initializes the Calendar mode of the RTC module.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void RTC_C_initCalendar(const RTC_C_Calendar *calendarTime,
+        uint_fast16_t formatSelect);
+
+//*****************************************************************************
+//
+//! Returns the Calendar Time stored in the Calendar registers of the RTC.
+//!
+//!
+//! This function returns the current Calendar time in the form of a Calendar
+//! structure.
+//!
+//! \return A Calendar structure containing the current time.
+//
+//*****************************************************************************
+extern RTC_C_Calendar RTC_C_getCalendarTime(void);
+
+//*****************************************************************************
+//
+//! Sets and Enables the desired Calendar Alarm settings.
+//!
+//! \param minutesAlarm is the alarm condition for the minutes.
+//!        Valid values are
+//!        - An integer between 0-59, OR
+//!        - \b   RTC_C_ALARMCONDITION_OFF [Default]
+//! \param hoursAlarm is the alarm condition for the hours.
+//!        Valid values are
+//!        - An integer between 0-24, OR
+//!        - \b   RTC_C_ALARMCONDITION_OFF [Default]
+//! \param dayOfWeekAlarm is the alarm condition for the day of week.
+//!        Valid values are
+//!        - An integer between 0-6, OR
+//!        - \b   RTC_C_ALARMCONDITION_OFF [Default]
+//! \param dayOfmonthAlarm is the alarm condition for the day of the month.
+//!        Valid values are
+//!        - An integer between 0-31, OR
+//!        - \b   RTC_C_ALARMCONDITION_OFF [Default]
+//!
+//! This function sets a Calendar interrupt condition to assert the RTCAIFG
+//! interrupt flag. The condition is a logical and of all of the parameters.
+//! For example if the minutes and hours alarm is set, then the interrupt will
+//! only assert when the minutes AND the hours change to the specified setting.
+//! Use the RTC_ALARM_OFF for any alarm settings that should not be apart of
+//! the alarm condition.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void RTC_C_setCalendarAlarm(uint_fast8_t minutesAlarm,
+        uint_fast8_t hoursAlarm, uint_fast8_t dayOfWeekAlarm,
+        uint_fast8_t dayOfmonthAlarm);
+
+//*****************************************************************************
+//
+//! Sets a single specified Calendar interrupt condition.
+//!
+//! \param eventSelect is the condition selected.
+//!        Valid values are
+//!        - \b   RTC_C_CALENDAREVENT_MINUTECHANGE - assert interrupt on every
+//!             minute
+//!        - \b   RTC_C_CALENDAREVENT_HOURCHANGE - assert interrupt on every hour
+//!        - \b   RTC_C_CALENDAREVENT_NOON - assert interrupt when hour is 12
+//!        - \b   RTC_C_CALENDAREVENT_MIDNIGHT - assert interrupt when hour is 0
+//!
+//! This function sets a specified event to assert the RTCTEVIFG interrupt. This
+//! interrupt is independent from the Calendar alarm interrupt.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void RTC_C_setCalendarEvent(uint_fast16_t eventSelect);
+
+//*****************************************************************************
+//
+//! Sets up an interrupt condition for the selected Prescaler.
+//!
+//! \param prescaleSelect is the prescaler to define an interrupt for.
+//!        Valid values are
+//!        - \b   RTC_C_PRESCALE_0
+//!        - \b   RTC_C_PRESCALE_1
+//! \param prescaleEventDivider is a divider to specify when an interrupt can
+//!       occur based on the clock source of the selected prescaler.
+//!       (Does not affect timer of the selected prescaler).
+//!       Valid values are
+//!       - \b   RTC_C_PSEVENTDIVIDER_2 [Default]
+//!       - \b   RTC_C_PSEVENTDIVIDER_4
+//!       - \b   RTC_C_PSEVENTDIVIDER_8
+//!       - \b   RTC_C_PSEVENTDIVIDER_16
+//!       - \b   RTC_C_PSEVENTDIVIDER_32
+//!       - \b   RTC_C_PSEVENTDIVIDER_64
+//!       - \b   RTC_C_PSEVENTDIVIDER_128
+//!       - \b   RTC_C_PSEVENTDIVIDER_256
+//!
+//! This function sets the condition for an interrupt to assert based on the
+//! individual prescalers.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void RTC_C_definePrescaleEvent(uint_fast8_t prescaleSelect,
+        uint_fast8_t prescaleEventDivider);
+
+//*****************************************************************************
+//
+//! Returns the selected Prescaler value.
+//!
+//! \param prescaleSelect is the prescaler to obtain the value of.
+//!        Valid values are
+//!        - \b   RTC_C_PRESCALE_0
+//!        - \b   RTC_C_PRESCALE_1
+//!
+//! This function returns the value of the selected prescale counter register.
+//! The counter should be held before reading. If in counter mode, the
+//! individual prescaler can be held, while in Calendar mode the whole RTC must
+//! be held.
+//!
+//! \return The value of the specified Prescaler count register
+//
+//*****************************************************************************
+extern uint_fast8_t RTC_C_getPrescaleValue(uint_fast8_t prescaleSelect);
+
+//*****************************************************************************
+//
+//! Sets the selected Prescaler value.
+//!
+//! \param prescaleSelect is the prescaler to set the value for.
+//!        Valid values are
+//!        - \b   RTC_C_PRESCALE_0
+//!        - \b   RTC_C_PRESCALE_1
+//! \param prescaleCounterValue is the specified value to set the prescaler to;
+//!       a valid value is any integer from 0-255.
+//!
+//! This function sets the prescale counter value. Before setting the prescale
+//! counter, it should be held.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void RTC_C_setPrescaleValue(uint_fast8_t prescaleSelect,
+        uint_fast8_t prescaleCounterValue);
+
+//*****************************************************************************
+//
+//! Returns the given BCD value in Binary Format
+//!
+//! \param valueToConvert is the raw value in BCD format to convert to
+//!        Binary.
+//!
+//! This function converts BCD values to Binary format.
+//!
+//! \return The Binary version of the valueToConvert parameter.
+//
+//*****************************************************************************
+extern uint16_t RTC_C_convertBCDToBinary(uint16_t valueToConvert);
+
+//*****************************************************************************
+//
+//! Returns the given Binary value in BCD Format
+//!
+
+//! \param valueToConvert is the raw value in Binary format to convert to
+//!        BCD.
+//!
+//! This function converts Binary values to BCD format.
+//!
+//! \return The BCD version of the valueToConvert parameter.
+//
+//*****************************************************************************
+extern uint16_t RTC_C_convertBinaryToBCD(uint16_t valueToConvert);
+
+//*****************************************************************************
+//
+//! Enables selected RTC interrupt sources.
+//!
+//! \param interruptMask is a bit mask of the interrupts to enable.
+//!        Mask Value is the logical OR of any of the following
+//!        - \b  RTC_C_TIME_EVENT_INTERRUPT - asserts when counter overflows in
+//!             counter mode or when Calendar event condition defined by
+//!             defineCalendarEvent() is met.
+//!        - \b  RTC_C_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in
+//!             Calendar mode is met.
+//!        - \b  RTC_C_CLOCK_READ_READY_INTERRUPT - asserts when Calendar
+//!             registers are settled.
+//!        - \b  RTC_C_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0
+//!             event condition is met.
+//!        - \b  RTC_C_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1
+//!             event condition is met.
+//!        - \b  RTC_C_OSCILLATOR_FAULT_INTERRUPT - asserts if there is
+//!             a problem with the 32kHz oscillator, while the RTC is running.
+//!
+//! This function enables the selected RTC interrupt source.  Only the sources
+//! that are enabled can be reflected to the processor interrupt; disabled
+//! sources have no effect on the processor.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void RTC_C_enableInterrupt(uint8_t interruptMask);
+
+//*****************************************************************************
+//
+//! Disables selected RTC interrupt sources.
+//!
+//! \param interruptMask is a bit mask of the interrupts to disable.
+//!        Mask Value is the logical OR of any of the following
+//!        - \b  RTC_C_TIME_EVENT_INTERRUPT - asserts when counter overflows in
+//!             counter mode or when Calendar event condition defined by
+//!             defineCalendarEvent() is met.
+//!        - \b  RTC_C_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in
+//!             Calendar mode is met.
+//!        - \b  RTC_CLOCK_READ_READY_INTERRUPT - asserts when Calendar
+//!             registers are settled.
+//!        - \b  RTC_C_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0
+//!             event condition is met.
+//!        - \b  RTC_C_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1
+//!             event condition is met.
+//!        - \b  RTC_C_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a
+//!             problem with the 32kHz oscillator, while the RTC is running.
+//!
+//! This function disables the selected RTC interrupt source.  Only the sources
+//! that are enabled can be reflected to the processor interrupt; disabled
+//! sources have no effect on the processor.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void RTC_C_disableInterrupt(uint8_t interruptMask);
+
+//*****************************************************************************
+//
+//! Returns the status of the interrupts flags.
+//!
+//! \return A bit mask of the selected interrupt flag's status.
+//!        Mask Value is the logical OR of any of the following
+//!        - \b  RTC_C_TIME_EVENT_INTERRUPT - asserts when counter overflows in
+//!             counter mode or when Calendar event condition defined by
+//!             defineCalendarEvent() is met.
+//!        - \b  RTC_C_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in
+//!             Calendar mode is met.
+//!        - \b  RTC_C_CLOCK_READ_READY_INTERRUPT - asserts when Calendar
+//!             registers are settled.
+//!        - \b  RTC_C_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0
+//!             event condition is met.
+//!        - \b  RTC_C_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1
+//!             event condition is met.
+//!        - \b  RTC_C_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a
+//!             problem with the 32kHz oscillator, while the RTC is running.
+//
+//*****************************************************************************
+extern uint_fast8_t RTC_C_getInterruptStatus(void);
+
+//*****************************************************************************
+//
+//! Returns the status of the interrupts flags masked with the enabled
+//! interrupts.  This function is useful to call in ISRs to get a
+//! list of pending interrupts that are actually enabled and could have caused
+//! the ISR.
+//!
+//! \return A bit mask of the selected interrupt flag's status.
+//!        Mask Value is the logical OR of any of the following
+//!        - \b  RTC_TIME_EVENT_INTERRUPT - asserts when counter overflows in
+//!             counter mode or when Calendar event condition defined by
+//!             defineCalendarEvent() is met.
+//!        - \b  RTC_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in
+//!             Calendar mode is met.
+//!        - \b  RTC_CLOCK_READ_READY_INTERRUPT - asserts when Calendar
+//!             registers are settled.
+//!        - \b  RTC_C_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0
+//!             event condition is met.
+//!        - \b  RTC_C_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1
+//!             event condition is met.
+//!        - \b  RTC_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a problem
+//!             with the 32kHz oscillator, while the RTC is running.
+//
+//*****************************************************************************
+extern uint_fast8_t RTC_C_getEnabledInterruptStatus(void);
+
+//*****************************************************************************
+//
+//! Clears selected RTC interrupt flags.
+//!
+//! \param interruptFlagMask is a bit mask of the interrupt flags to be
+//!        cleared. Mask Value is the logical OR of any of the following
+//!        - \b  RTC_C_TIME_EVENT_INTERRUPT - asserts when counter overflows in
+//!             counter mode or when Calendar event condition defined by
+//!             defineCalendarEvent() is met.
+//!        - \b  RTC_C_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in
+//!             Calendar mode is met.
+//!        - \b  RTC_C_CLOCK_READ_READY_INTERRUPT - asserts when Calendar
+//!             registers are settled.
+//!        - \b  RTC_C_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0
+//!             event condition is met.
+//!        - \b  RTC_C_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1
+//!             event condition is met.
+//!        - \b  RTC_C_OSCILLATOR_FAULT_INTERRUPT - asserts if there is
+//!             a problem with the 32kHz oscillator, while the RTC is running.
+//!
+//! This function clears the RTC interrupt flag is cleared, so that it no longer
+//! asserts.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void RTC_C_clearInterruptFlag(uint_fast8_t interruptFlagMask);
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the RTC interrupt.
+//!
+//! \param intHandler is a pointer to the function to be called when the
+//! RTC interrupt occurs.
+//!
+//! This function registers the handler to be called when a RTC
+//! interrupt occurs. This function enables the global interrupt in the
+//! interrupt controller; specific AES interrupts must be enabled
+//! via RTC_enableInterrupt().  It is the interrupt handler's responsibility to
+//! clear the interrupt source via RTC_clearInterruptFlag().
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void RTC_C_registerInterrupt(void (*intHandler)(void));
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the RTC interrupt
+//!
+//! This function unregisters the handler to be called when RTC
+//! interrupt occurs.  This function also masks off the interrupt in the
+//! interrupt controller so that the interrupt handler no longer is called.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void RTC_C_unregisterInterrupt(void);
+
+/* Defines for future devices that might have multiple instances */
+#define RTC_C_startClockMultipleInstance(a) RTC_C_startClock()
+#define RTC_C_holdClockMultipleInstance(a) RTC_C_holdClock()
+#define RTC_C_setCalibrationFrequencyMultipleInstance(a,b) RTC_C_setCalibrationFrequency(b)
+#define RTC_C_setCalibrationDataMultipleInstance(a,b,c) RTC_C_setCalibrationData(b,c)
+#define RTC_C_setTemperatureCompensationMultipleInstance(a,b,c) RTC_C_setTemperatureCompensation(b,c)
+#define RTC_C_initCalendarMultipleInstance(a,b,c) RTC_C_initCalendar(b,c)
+#define RTC_C_getCalendarTimeMultipleInstance(a) RTC_C_getCalendarTime()
+#define RTC_C_setCalendarAlarmMultipleInstance(a,b,c,d,e) RTC_C_setCalendarAlarm(b,c,d,e)
+#define RTC_C_setCalendarEventMultipleInstance(a,b) RTC_C_setCalendarEvent(b)
+#define RTC_C_definePrescaleEventMultipleInstance(a,b,c) RTC_C_definePrescaleEvent(b,c)
+#define RTC_C_getPrescaleValueMultipleInstance(a,b) RTC_C_getPrescaleValue(b)
+#define RTC_C_setPrescaleValueMultipleInstance(a,b,c) RTC_C_setPrescaleValue(b,c)
+#define RTC_C_convertBCDToBinaryMultipleInstance(a,b) RTC_C_convertBCDToBinary(b)
+#define RTC_C_convertBinaryToBCDMultipleInstance(a,b) RTC_C_convertBinaryToBCD(b)
+#define RTC_C_enableInterruptMultipleInstance(a,b) RTC_C_enableInterrupt(b)
+#define RTC_C_disableInterruptMultipleInstance(a,b) RTC_C_disableInterrupt(b)
+#define RTC_C_getInterruptStatusMultipleInstance(a) RTC_C_getInterruptStatus()
+#define RTC_C_getEnabledInterruptStatusMultipleInstance(a) RTC_C_getEnabledInterruptStatus()
+#define RTC_C_clearInterruptFlagMultipleInstance(a,b) RTC_C_clearInterruptFlag(b)
+#define RTC_C_registerInterruptMultipleInstance(a,b) RTC_C_registerInterrupt(b)
+#define RTC_C_unregisterInterruptMultipleInstance(a) RTC_C_unregisterInterrupt()
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif /* RTC_H */
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/spi.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/spi.c
new file mode 100644
index 000000000..b782564cd
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/spi.c
@@ -0,0 +1,1363 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#include <spi.h>
+#include <interrupt.h>
+#include <debug.h>
+#include <eusci.h>
+
+static bool is_A_Module(uint32_t module)
+{
+    if (module == EUSCI_A0_MODULE || module == EUSCI_A1_MODULE
+#ifdef EUSCI_A2_MODULE
+            || module == EUSCI_A2_MODULE
+#endif
+#ifdef EUSCI_A3_MODULE
+            || module == EUSCI_A3_MODULE
+#endif
+    )
+        return true;
+    else
+        return false;
+}
+
+bool SPI_initMaster(uint32_t moduleInstance, const eUSCI_SPI_MasterConfig *config)
+{
+    if (is_A_Module(moduleInstance))
+    {
+        ASSERT(
+                (EUSCI_A_SPI_CLOCKSOURCE_ACLK == config->selectClockSource)
+                || (EUSCI_A_SPI_CLOCKSOURCE_SMCLK
+                        == config->selectClockSource));
+
+        ASSERT(
+                (EUSCI_A_SPI_MSB_FIRST == config->msbFirst)
+                || (EUSCI_A_SPI_LSB_FIRST == config->msbFirst));
+
+        ASSERT(
+                (EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
+                        == config->clockPhase)
+                || (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
+                        == config->clockPhase));
+
+        ASSERT(
+                (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
+                        == config->clockPolarity)
+                || (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW
+                        == config->clockPolarity));
+
+        ASSERT(
+                (EUSCI_A_SPI_3PIN == config->spiMode)
+                || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH
+                        == config->spiMode)
+                || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW
+                        == config->spiMode));
+
+        //Disable the USCI Module
+        BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
+
+        /*
+         * Configure as SPI master mode.
+         * Clock phase select, polarity, msb
+         * UCMST = Master mode
+         * UCSYNC = Synchronous mode
+         * UCMODE_0 = 3-pin SPI
+         */
+        EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r =
+                (EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r
+                        & ~(UCSSEL_3 + UCCKPH + UCCKPL + UC7BIT + UCMSB + UCMST
+                                + UCMODE_3 + UCSYNC))
+                        | (config->selectClockSource + config->msbFirst
+                                + config->clockPhase + config->clockPolarity
+                                + UCMST + UCSYNC + config->spiMode);
+
+        EUSCI_A_CMSIS(moduleInstance)->rBRW =
+                (uint16_t) (config->clockSourceFrequency
+                        / config->desiredSpiClock);
+
+        //No modulation
+        EUSCI_A_CMSIS(moduleInstance)->rMCTLW.r = 0;
+
+        return true;
+    } else
+    {
+        ASSERT(
+                (EUSCI_B_SPI_CLOCKSOURCE_ACLK == config->selectClockSource)
+                || (EUSCI_B_SPI_CLOCKSOURCE_SMCLK
+                        == config->selectClockSource));
+
+        ASSERT(
+                (EUSCI_B_SPI_MSB_FIRST == config->msbFirst)
+                || (EUSCI_B_SPI_LSB_FIRST == config->msbFirst));
+
+        ASSERT(
+                (EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
+                        == config->clockPhase)
+                || (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
+                        == config->clockPhase));
+
+        ASSERT(
+                (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
+                        == config->clockPolarity)
+                || (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW
+                        == config->clockPolarity));
+
+        ASSERT(
+                (EUSCI_B_SPI_3PIN == config->spiMode)
+                || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH
+                        == config->spiMode)
+                || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW
+                        == config->spiMode));
+
+        //Disable the USCI Module
+        BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
+
+        /*
+         * Configure as SPI master mode.
+         * Clock phase select, polarity, msb
+         * UCMST = Master mode
+         * UCSYNC = Synchronous mode
+         * UCMODE_0 = 3-pin SPI
+         */
+        EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r =
+                (EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r
+                        & ~(UCSSEL_3 + UCCKPH + UCCKPL + UC7BIT + UCMSB + UCMST
+                                + UCMODE_3 + UCSYNC))
+                        | (config->selectClockSource + config->msbFirst
+                                + config->clockPhase + config->clockPolarity
+                                + UCMST + UCSYNC + config->spiMode);
+
+        EUSCI_B_CMSIS(moduleInstance)->rBRW =
+                (uint16_t) (config->clockSourceFrequency
+                        / config->desiredSpiClock);
+
+        return true;
+    }
+
+}
+
+void SPI_selectFourPinFunctionality(uint32_t moduleInstance,
+        uint_fast8_t select4PinFunctionality)
+{
+    if (is_A_Module(moduleInstance))
+    {
+        EUSCI_A_SPI_select4PinFunctionality(moduleInstance,
+                select4PinFunctionality);
+    } else
+    {
+        EUSCI_B_SPI_select4PinFunctionality(moduleInstance,
+                select4PinFunctionality);
+    }
+
+}
+
+void SPI_changeMasterClock(uint32_t moduleInstance,
+        uint32_t clockSourceFrequency, uint32_t desiredSpiClock)
+{
+    if (is_A_Module(moduleInstance))
+    {
+        EUSCI_A_SPI_masterChangeClock(moduleInstance, clockSourceFrequency,
+                desiredSpiClock);
+    } else
+    {
+        EUSCI_B_SPI_masterChangeClock(moduleInstance, clockSourceFrequency,
+                desiredSpiClock);
+    }
+
+}
+
+bool SPI_initSlave(uint32_t moduleInstance, const eUSCI_SPI_SlaveConfig *config)
+{
+    if (is_A_Module(moduleInstance))
+    {
+        ASSERT(
+                (EUSCI_A_SPI_MSB_FIRST == config->msbFirst)
+                || (EUSCI_A_SPI_LSB_FIRST == config->msbFirst));
+
+        ASSERT(
+                (EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
+                        == config->clockPhase)
+                || (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
+                        == config->clockPhase));
+
+        ASSERT(
+                (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
+                        == config->clockPolarity)
+                || (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW
+                        == config->clockPolarity));
+
+        ASSERT(
+                (EUSCI_A_SPI_3PIN == config->spiMode)
+                || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH
+                        == config->spiMode)
+                || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW
+                        == config->spiMode));
+
+        //Disable USCI Module
+        BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
+
+        //Reset OFS_UCAxCTLW0 register
+        EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r =
+                (EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r
+                        & ~(UCMSB + UC7BIT + UCMST + UCCKPL + UCCKPH + UCMODE_3))
+                        | (config->clockPhase + config->clockPolarity
+                                + config->msbFirst + UCSYNC + config->spiMode);
+
+        return true;
+    } else
+    {
+        ASSERT(
+                (EUSCI_B_SPI_MSB_FIRST == config->msbFirst)
+                || (EUSCI_B_SPI_LSB_FIRST == config->msbFirst));
+
+        ASSERT(
+                (EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
+                        == config->clockPhase)
+                || (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
+                        == config->clockPhase));
+
+        ASSERT(
+                (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
+                        == config->clockPolarity)
+                || (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW
+                        == config->clockPolarity));
+
+        ASSERT(
+                (EUSCI_B_SPI_3PIN == config->spiMode)
+                || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH
+                        == config->spiMode)
+                || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW
+                        == config->spiMode));
+
+        //Disable USCI Module
+        BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
+
+        //Reset OFS_UCBxCTLW0 register
+        EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r =
+                (EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r
+                        & ~(UCMSB + UC7BIT + UCMST + UCCKPL + UCCKPH + UCMODE_3))
+                        | (config->clockPhase + config->clockPolarity
+                                + config->msbFirst + UCSYNC + config->spiMode);
+
+        return true;
+    }
+
+}
+
+void SPI_changeClockPhasePolarity(uint32_t moduleInstance,
+        uint_fast16_t clockPhase, uint_fast16_t clockPolarity)
+{
+    if (is_A_Module(moduleInstance))
+    {
+        EUSCI_A_SPI_changeClockPhasePolarity(moduleInstance, clockPhase,
+                clockPolarity);
+    } else
+    {
+        EUSCI_B_SPI_changeClockPhasePolarity(moduleInstance, clockPhase,
+                clockPolarity);
+    }
+
+}
+
+void SPI_transmitData(uint32_t moduleInstance, uint_fast8_t transmitData)
+{
+    if (is_A_Module(moduleInstance))
+    {
+        EUSCI_A_SPI_transmitData(moduleInstance, transmitData);
+    } else
+    {
+        EUSCI_B_SPI_transmitData(moduleInstance, transmitData);
+    }
+
+}
+
+uint8_t SPI_receiveData(uint32_t moduleInstance)
+{
+    if (is_A_Module(moduleInstance))
+    {
+        return EUSCI_A_SPI_receiveData(moduleInstance);
+    } else
+    {
+        return EUSCI_B_SPI_receiveData(moduleInstance);
+    }
+
+}
+
+void SPI_enableModule(uint32_t moduleInstance)
+{
+    if (is_A_Module(moduleInstance))
+    {
+        EUSCI_A_SPI_enable(moduleInstance);
+    } else
+    {
+        EUSCI_B_SPI_enable(moduleInstance);
+    }
+
+}
+
+void SPI_disableModule(uint32_t moduleInstance)
+{
+    if (is_A_Module(moduleInstance))
+    {
+        EUSCI_A_SPI_disable(moduleInstance);
+    } else
+    {
+        EUSCI_B_SPI_disable(moduleInstance);
+    }
+
+}
+
+uint32_t SPI_getReceiveBufferAddressForDMA(uint32_t moduleInstance)
+{
+    if (is_A_Module(moduleInstance))
+    {
+        return EUSCI_A_SPI_getReceiveBufferAddressForDMA(moduleInstance);
+    } else
+    {
+        return EUSCI_B_SPI_getReceiveBufferAddressForDMA(moduleInstance);
+    }
+
+}
+
+uint32_t SPI_getTransmitBufferAddressForDMA(uint32_t moduleInstance)
+{
+    if (is_A_Module(moduleInstance))
+    {
+        return EUSCI_A_SPI_getTransmitBufferAddressForDMA(moduleInstance);
+    } else
+    {
+        return EUSCI_B_SPI_getTransmitBufferAddressForDMA(moduleInstance);
+    }
+
+}
+
+uint_fast8_t SPI_isBusy(uint32_t moduleInstance)
+{
+    if (is_A_Module(moduleInstance))
+    {
+        return EUSCI_A_SPI_isBusy(moduleInstance);
+    } else
+    {
+        return EUSCI_B_SPI_isBusy(moduleInstance);
+    }
+
+}
+
+void SPI_enableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
+{
+    if (is_A_Module(moduleInstance))
+    {
+        EUSCI_A_SPI_enableInterrupt(moduleInstance, mask);
+    } else
+    {
+        EUSCI_B_SPI_enableInterrupt(moduleInstance, mask);
+    }
+
+}
+
+void SPI_disableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
+{
+    if (is_A_Module(moduleInstance))
+    {
+        EUSCI_A_SPI_disableInterrupt(moduleInstance, mask);
+    } else
+    {
+        EUSCI_B_SPI_disableInterrupt(moduleInstance, mask);
+    }
+
+}
+
+uint_fast8_t SPI_getInterruptStatus(uint32_t moduleInstance, uint16_t mask)
+{
+    if (is_A_Module(moduleInstance))
+    {
+        return EUSCI_A_SPI_getInterruptStatus(moduleInstance, mask);
+    } else
+    {
+        return EUSCI_B_SPI_getInterruptStatus(moduleInstance, mask);
+    }
+
+}
+
+uint_fast8_t SPI_getEnabledInterruptStatus(uint32_t moduleInstance)
+{
+    if (is_A_Module(moduleInstance))
+    {
+        return SPI_getInterruptStatus(moduleInstance,
+                EUSCI_SPI_TRANSMIT_INTERRUPT | EUSCI_SPI_RECEIVE_INTERRUPT)
+                & HWREG16(moduleInstance + OFS_UCA0IE);
+    } else
+    {
+        return SPI_getInterruptStatus(moduleInstance,
+                EUSCI_SPI_TRANSMIT_INTERRUPT | EUSCI_SPI_RECEIVE_INTERRUPT)
+                & HWREG16(moduleInstance + OFS_UCB0IE);
+
+    }
+}
+
+void SPI_clearInterruptFlag(uint32_t moduleInstance, uint_fast8_t mask)
+{
+    if (is_A_Module(moduleInstance))
+    {
+        EUSCI_A_SPI_clearInterruptFlag(moduleInstance, mask);
+    } else
+    {
+        EUSCI_B_SPI_clearInterruptFlag(moduleInstance, mask);
+    }
+
+}
+
+void SPI_registerInterrupt(uint32_t moduleInstance, void (*intHandler)(void))
+{
+    switch (moduleInstance)
+    {
+    case EUSCI_A0_MODULE:
+        Interrupt_registerInterrupt(INT_EUSCIA0, intHandler);
+        Interrupt_enableInterrupt(INT_EUSCIA0);
+        break;
+    case EUSCI_A1_MODULE:
+        Interrupt_registerInterrupt(INT_EUSCIA1, intHandler);
+        Interrupt_enableInterrupt(INT_EUSCIA1);
+        break;
+#ifdef EUSCI_A2_MODULE
+    case EUSCI_A2_MODULE:
+        Interrupt_registerInterrupt(INT_EUSCIA2, intHandler);
+        Interrupt_enableInterrupt(INT_EUSCIA2);
+        break;
+#endif
+#ifdef EUSCI_A3_MODULE
+    case EUSCI_A3_MODULE:
+        Interrupt_registerInterrupt(INT_EUSCIA3, intHandler);
+        Interrupt_enableInterrupt(INT_EUSCIA3);
+        break;
+#endif
+    case EUSCI_B0_MODULE:
+        Interrupt_registerInterrupt(INT_EUSCIB0, intHandler);
+        Interrupt_enableInterrupt(INT_EUSCIB0);
+        break;
+    case EUSCI_B1_MODULE:
+        Interrupt_registerInterrupt(INT_EUSCIB1, intHandler);
+        Interrupt_enableInterrupt(INT_EUSCIB1);
+        break;
+#ifdef EUSCI_B2_MODULE
+    case EUSCI_B2_MODULE:
+        Interrupt_registerInterrupt(INT_EUSCIB2, intHandler);
+        Interrupt_enableInterrupt(INT_EUSCIB2);
+        break;
+#endif
+#ifdef EUSCI_B3_MODULE
+    case EUSCI_B3_MODULE:
+        Interrupt_registerInterrupt(INT_EUSCIB3, intHandler);
+        Interrupt_enableInterrupt(INT_EUSCIB3);
+        break;
+#endif
+    default:
+        ASSERT(false);
+    }
+}
+
+void SPI_unregisterInterrupt(uint32_t moduleInstance)
+{
+    switch (moduleInstance)
+    {
+    case EUSCI_A0_MODULE:
+        Interrupt_disableInterrupt(INT_EUSCIA0);
+        Interrupt_unregisterInterrupt(INT_EUSCIA0);
+        break;
+    case EUSCI_A1_MODULE:
+        Interrupt_disableInterrupt(INT_EUSCIA1);
+        Interrupt_unregisterInterrupt(INT_EUSCIA1);
+        break;
+#ifdef EUSCI_A2_MODULE
+    case EUSCI_A2_MODULE:
+        Interrupt_disableInterrupt(INT_EUSCIA2);
+        Interrupt_unregisterInterrupt(INT_EUSCIA2);
+        break;
+#endif
+#ifdef EUSCI_A3_MODULE
+    case EUSCI_A3_MODULE:
+        Interrupt_disableInterrupt(INT_EUSCIA3);
+        Interrupt_unregisterInterrupt(INT_EUSCIA3);
+        break;
+#endif
+    case EUSCI_B0_MODULE:
+        Interrupt_disableInterrupt(INT_EUSCIB0);
+        Interrupt_unregisterInterrupt(INT_EUSCIB0);
+        break;
+    case EUSCI_B1_MODULE:
+        Interrupt_disableInterrupt(INT_EUSCIB1);
+        Interrupt_unregisterInterrupt(INT_EUSCIB1);
+        break;
+#ifdef EUSCI_B2_MODULE
+    case EUSCI_B2_MODULE:
+        Interrupt_disableInterrupt(INT_EUSCIB2);
+        Interrupt_unregisterInterrupt(INT_EUSCIB2);
+        break;
+#endif
+#ifdef EUSCI_B3_MODULE
+    case EUSCI_B3_MODULE:
+        Interrupt_disableInterrupt(INT_EUSCIB3);
+        Interrupt_unregisterInterrupt(INT_EUSCIB3);
+        break;
+#endif
+    default:
+        ASSERT(false);
+    }
+
+}
+
+/* Backwards Compatibility Layer */
+
+//*****************************************************************************
+//
+//! \brief Selects 4Pin Functionality
+//!
+//! This function should be invoked only in 4-wire mode. Invoking this function
+//! has no effect in 3-wire mode.
+//!
+//! \param baseAddress is the base address of the EUSCI_B_SPI module.
+//! \param select4PinFunctionality selects 4 pin functionality
+//!        Valid values are:
+//!        - \b EUSCI_B_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS
+//!        - \b EUSCI_B_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE
+//!
+//! Modified bits are \b UCSTEM of \b UCAxCTLW0 register.
+//!
+//! \return None
+//
+//*****************************************************************************
+void EUSCI_B_SPI_select4PinFunctionality(uint32_t baseAddress,
+        uint8_t select4PinFunctionality)
+{
+    ASSERT(
+            (EUSCI_B_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS
+                    == select4PinFunctionality)
+            || (EUSCI_B_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE
+                    == select4PinFunctionality));
+
+    EUSCI_B_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_B_CMSIS(baseAddress)->rCTLW0.r
+            & ~UCSTEM) | select4PinFunctionality;
+}
+
+//*****************************************************************************
+//
+//! \brief Initializes the SPI Master clock. At the end of this function call,
+//! SPI module is left enabled.
+//!
+//! \param baseAddress is the base address of the EUSCI_B_SPI module.
+//! \param clockSourceFrequency is the frequency of the slected clock source
+//! \param desiredSpiClock is the desired clock rate for SPI communication
+//!
+//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register.
+//!
+//! \return None
+//
+//*****************************************************************************
+void EUSCI_B_SPI_masterChangeClock(uint32_t baseAddress,
+        uint32_t clockSourceFrequency, uint32_t desiredSpiClock)
+{
+    //Disable the USCI Module
+    BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
+
+    EUSCI_B_CMSIS(baseAddress)->rBRW = (uint16_t) (clockSourceFrequency
+            / desiredSpiClock);
+
+    //Reset the UCSWRST bit to enable the USCI Module
+    BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0;
+}
+
+//*****************************************************************************
+//
+//! \brief Initializes the SPI Slave block.
+//!
+//! Upon successful initialization of the SPI slave block, this function will
+//! have initailized the slave block, but the SPI Slave block still remains
+//! disabled and must be enabled with EUSCI_B_SPI_enable()
+//!
+//! \param baseAddress is the base address of the EUSCI_B_SPI Slave module.
+//! \param msbFirst controls the direction of the receive and transmit shift
+//!        register.
+//!        Valid values are:
+//!        - \b EUSCI_B_SPI_MSB_FIRST
+//!        - \b EUSCI_B_SPI_LSB_FIRST [Default]
+//! \param clockPhase is clock phase select.
+//!        Valid values are:
+//!        - \b EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
+//!           [Default]
+//!        - \b EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
+//! \param clockPolarity is clock polarity select
+//!        Valid values are:
+//!        - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
+//!        - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]
+//! \param spiMode is SPI mode select
+//!        Valid values are:
+//!        - \b EUSCI_B_SPI_3PIN
+//!        - \b EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH
+//!        - \b EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW
+//!
+//! Modified bits are \b UCMSB, \b UCMST, \b UC7BIT, \b UCCKPL, \b UCCKPH, \b
+//! UCMODE and \b UCSWRST of \b UCAxCTLW0 register.
+//!
+//! \return STATUS_SUCCESS
+//
+//*****************************************************************************
+bool EUSCI_B_SPI_slaveInit(uint32_t baseAddress, uint16_t msbFirst,
+        uint16_t clockPhase, uint16_t clockPolarity, uint16_t spiMode)
+{
+    ASSERT(
+            (EUSCI_B_SPI_MSB_FIRST == msbFirst)
+            || (EUSCI_B_SPI_LSB_FIRST == msbFirst));
+
+    ASSERT(
+            (EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
+                    == clockPhase)
+            || (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
+                    == clockPhase));
+
+    ASSERT(
+            (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity)
+            || (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW
+                    == clockPolarity));
+
+    ASSERT(
+            (EUSCI_B_SPI_3PIN == spiMode)
+            || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH == spiMode)
+            || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW == spiMode));
+
+    //Disable USCI Module
+    BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
+
+    //Reset OFS_UCBxCTLW0 register
+    EUSCI_B_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_B_CMSIS(baseAddress)->rCTLW0.r
+            & ~(UCMSB + UC7BIT + UCMST + UCCKPL + UCCKPH + UCMODE_3))
+            | (clockPhase + clockPolarity + msbFirst + UCSYNC + spiMode);
+
+    return true;
+}
+
+//*****************************************************************************
+//
+//! \brief Changes the SPI colock phase and polarity. At the end of this
+//! function call, SPI module is left enabled.
+//!
+//! \param baseAddress is the base address of the EUSCI_B_SPI module.
+//! \param clockPhase is clock phase select.
+//!        Valid values are:
+//!        - \b EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
+//!           [Default]
+//!        - \b EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
+//! \param clockPolarity is clock polarity select
+//!        Valid values are:
+//!        - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
+//!        - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]
+//!
+//! Modified bits are \b UCCKPL, \b UCCKPH and \b UCSWRST of \b UCAxCTLW0
+//! register.
+//!
+//! \return None
+//
+//*****************************************************************************
+void EUSCI_B_SPI_changeClockPhasePolarity(uint32_t baseAddress,
+        uint16_t clockPhase, uint16_t clockPolarity)
+{
+
+    ASSERT(
+            (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity)
+            || (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW
+                    == clockPolarity));
+
+    ASSERT(
+            (EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
+                    == clockPhase)
+            || (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
+                    == clockPhase));
+
+    //Disable the USCI Module
+    BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
+
+    EUSCI_B_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_B_CMSIS(baseAddress)->rCTLW0.r
+            & ~(UCCKPH + UCCKPL)) | (clockPhase + clockPolarity);
+
+    //Reset the UCSWRST bit to enable the USCI Module
+    BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0;
+}
+
+//*****************************************************************************
+//
+//! \brief Transmits a byte from the SPI Module.
+//!
+//! This function will place the supplied data into SPI trasmit data register
+//! to start transmission.
+//!
+//! \param baseAddress is the base address of the EUSCI_B_SPI module.
+//! \param transmitData data to be transmitted from the SPI module
+//!
+//! \return None
+//
+//*****************************************************************************
+void EUSCI_B_SPI_transmitData(uint32_t baseAddress, uint8_t transmitData)
+{
+    EUSCI_B_CMSIS(baseAddress)->rTXBUF.r = transmitData;
+}
+
+//*****************************************************************************
+//
+//! \brief Receives a byte that has been sent to the SPI Module.
+//!
+//! This function reads a byte of data from the SPI receive data Register.
+//!
+//! \param baseAddress is the base address of the EUSCI_B_SPI module.
+//!
+//! \return Returns the byte received from by the SPI module, cast as an
+//!         uint8_t.
+//
+//*****************************************************************************
+uint8_t EUSCI_B_SPI_receiveData(uint32_t baseAddress)
+{
+    return EUSCI_B_CMSIS(baseAddress)->rRXBUF.r;
+}
+
+//*****************************************************************************
+//
+//! \brief Enables individual SPI interrupt sources.
+//!
+//! Enables the indicated SPI interrupt sources.  Only the sources that are
+//! enabled can be reflected to the processor interrupt; disabled sources have
+//! no effect on the processor. Does not clear interrupt flags.
+//!
+//! \param baseAddress is the base address of the EUSCI_B_SPI module.
+//! \param mask is the bit mask of the interrupt sources to be enabled.
+//!        Mask value is the logical OR of any of the following:
+//!        - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT
+//!        - \b EUSCI_B_SPI_RECEIVE_INTERRUPT
+//!
+//! Modified bits of \b UCAxIFG register and bits of \b UCAxIE register.
+//!
+//! \return None
+//
+//*****************************************************************************
+void EUSCI_B_SPI_enableInterrupt(uint32_t baseAddress, uint8_t mask)
+{
+    ASSERT(
+            !(mask
+                    & ~(EUSCI_B_SPI_RECEIVE_INTERRUPT
+                            | EUSCI_B_SPI_TRANSMIT_INTERRUPT)));
+
+    EUSCI_B_CMSIS(baseAddress)->rIE.r |= mask;
+}
+
+//*****************************************************************************
+//
+//! \brief Disables individual SPI interrupt sources.
+//!
+//! Disables the indicated SPI interrupt sources. Only the sources that are
+//! enabled can be reflected to the processor interrupt; disabled sources have
+//! no effect on the processor.
+//!
+//! \param baseAddress is the base address of the EUSCI_B_SPI module.
+//! \param mask is the bit mask of the interrupt sources to be disabled.
+//!        Mask value is the logical OR of any of the following:
+//!        - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT
+//!        - \b EUSCI_B_SPI_RECEIVE_INTERRUPT
+//!
+//! Modified bits of \b UCAxIE register.
+//!
+//! \return None
+//
+//*****************************************************************************
+void EUSCI_B_SPI_disableInterrupt(uint32_t baseAddress, uint8_t mask)
+{
+    ASSERT(
+            !(mask
+                    & ~(EUSCI_B_SPI_RECEIVE_INTERRUPT
+                            | EUSCI_B_SPI_TRANSMIT_INTERRUPT)));
+
+    EUSCI_B_CMSIS(baseAddress)->rIE.r &= ~mask;
+}
+
+//*****************************************************************************
+//
+//! \brief Gets the current SPI interrupt status.
+//!
+//! This returns the interrupt status for the SPI module based on which flag is
+//! passed.
+//!
+//! \param baseAddress is the base address of the EUSCI_B_SPI module.
+//! \param mask is the masked interrupt flag status to be returned.
+//!        Mask value is the logical OR of any of the following:
+//!        - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT
+//!        - \b EUSCI_B_SPI_RECEIVE_INTERRUPT
+//!
+//! \return Logical OR of any of the following:
+//!         - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT
+//!         - \b EUSCI_B_SPI_RECEIVE_INTERRUPT
+//!         \n indicating the status of the masked interrupts
+//
+//*****************************************************************************
+uint8_t EUSCI_B_SPI_getInterruptStatus(uint32_t baseAddress, uint8_t mask)
+{
+    ASSERT(
+            !(mask
+                    & ~(EUSCI_B_SPI_RECEIVE_INTERRUPT
+                            | EUSCI_B_SPI_TRANSMIT_INTERRUPT)));
+
+    return EUSCI_B_CMSIS(baseAddress)->rIFG.r & mask;
+}
+
+//*****************************************************************************
+//
+//! \brief Clears the selected SPI interrupt status flag.
+//!
+//! \param baseAddress is the base address of the EUSCI_B_SPI module.
+//! \param mask is the masked interrupt flag to be cleared.
+//!        Mask value is the logical OR of any of the following:
+//!        - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT
+//!        - \b EUSCI_B_SPI_RECEIVE_INTERRUPT
+//!
+//! Modified bits of \b UCAxIFG register.
+//!
+//! \return None
+//
+//*****************************************************************************
+void EUSCI_B_SPI_clearInterruptFlag(uint32_t baseAddress, uint8_t mask)
+{
+    ASSERT(
+            !(mask
+                    & ~(EUSCI_B_SPI_RECEIVE_INTERRUPT
+                            | EUSCI_B_SPI_TRANSMIT_INTERRUPT)));
+
+    EUSCI_B_CMSIS(baseAddress)->rIFG.r &= ~mask;
+}
+
+//*****************************************************************************
+//
+//! \brief Enables the SPI block.
+//!
+//! This will enable operation of the SPI block.
+//!
+//! \param baseAddress is the base address of the EUSCI_B_SPI module.
+//!
+//! Modified bits are \b UCSWRST of \b UCBxCTLW0 register.
+//!
+//! \return None
+//
+//*****************************************************************************
+void EUSCI_B_SPI_enable(uint32_t baseAddress)
+{
+    //Reset the UCSWRST bit to enable the USCI Module
+    BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0;
+}
+
+//*****************************************************************************
+//
+//! \brief Disables the SPI block.
+//!
+//! This will disable operation of the SPI block.
+//!
+//! \param baseAddress is the base address of the EUSCI_B_SPI module.
+//!
+//! Modified bits are \b UCSWRST of \b UCBxCTLW0 register.
+//!
+//! \return None
+//
+//*****************************************************************************
+void EUSCI_B_SPI_disable(uint32_t baseAddress)
+{
+    //Set the UCSWRST bit to disable the USCI Module
+    BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
+}
+
+//*****************************************************************************
+//
+//! \brief Returns the address of the RX Buffer of the SPI for the DMA module.
+//!
+//! Returns the address of the SPI RX Buffer. This can be used in conjunction
+//! with the DMA to store the received data directly to memory.
+//!
+//! \param baseAddress is the base address of the EUSCI_B_SPI module.
+//!
+//! \return the address of the RX Buffer
+//
+//*****************************************************************************
+uint32_t EUSCI_B_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress)
+{
+    return baseAddress + OFS_UCB0RXBUF;
+}
+
+//*****************************************************************************
+//
+//! \brief Returns the address of the TX Buffer of the SPI for the DMA module.
+//!
+//! Returns the address of the SPI TX Buffer. This can be used in conjunction
+//! with the DMA to obtain transmitted data directly from memory.
+//!
+//! \param baseAddress is the base address of the EUSCI_B_SPI module.
+//!
+//! \return the address of the TX Buffer
+//
+//*****************************************************************************
+uint32_t EUSCI_B_SPI_getTransmitBufferAddressForDMA(uint32_t baseAddress)
+{
+    return baseAddress + OFS_UCB0TXBUF;
+}
+
+//*****************************************************************************
+//
+//! \brief Indicates whether or not the SPI bus is busy.
+//!
+//! This function returns an indication of whether or not the SPI bus is
+//! busy.This function checks the status of the bus via UCBBUSY bit
+//!
+//! \param baseAddress is the base address of the EUSCI_B_SPI module.
+//!
+//! \return true if busy, false otherwise
+//
+//*****************************************************************************
+bool EUSCI_B_SPI_isBusy(uint32_t baseAddress)
+{
+    //Return the bus busy status.
+    return BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rSTATW.r, UCBBUSY_OFS);
+}
+
+//*****************************************************************************
+//
+//! \brief Selects 4Pin Functionality
+//!
+//! This function should be invoked only in 4-wire mode. Invoking this function
+//! has no effect in 3-wire mode.
+//!
+//! \param baseAddress is the base address of the EUSCI_A_SPI module.
+//! \param select4PinFunctionality selects 4 pin functionality
+//!        Valid values are:
+//!        - \b EUSCI_A_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS
+//!        - \b EUSCI_A_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE
+//!
+//! Modified bits are \b UCSTEM of \b UCAxCTLW0 register.
+//!
+//! \return None
+//
+//*****************************************************************************
+void EUSCI_A_SPI_select4PinFunctionality(uint32_t baseAddress,
+        uint8_t select4PinFunctionality)
+{
+    ASSERT(
+            (EUSCI_A_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS
+                    == select4PinFunctionality)
+            || (EUSCI_A_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE
+                    == select4PinFunctionality));
+
+    EUSCI_A_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_A_CMSIS(baseAddress)->rCTLW0.r
+            & ~UCSTEM) | select4PinFunctionality;
+}
+
+//*****************************************************************************
+//
+//! \brief Initializes the SPI Master clock. At the end of this function call,
+//! SPI module is left enabled.
+//!
+//! \param baseAddress is the base address of the EUSCI_A_SPI module.
+//! \param clockSourceFrequency is the frequency of the slected clock source
+//! \param desiredSpiClock is the desired clock rate for SPI communication
+//!
+//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register.
+//!
+//! \return None
+//
+//*****************************************************************************
+void EUSCI_A_SPI_masterChangeClock(uint32_t baseAddress,
+        uint32_t clockSourceFrequency, uint32_t desiredSpiClock)
+{
+    //Disable the USCI Module
+    BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
+
+    EUSCI_A_CMSIS(baseAddress)->rBRW = (uint16_t) (clockSourceFrequency
+            / desiredSpiClock);
+
+    //Reset the UCSWRST bit to enable the USCI Module
+    BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0;
+}
+
+//*****************************************************************************
+//
+//! \brief Initializes the SPI Slave block.
+//!
+//! Upon successful initialization of the SPI slave block, this function will
+//! have initailized the slave block, but the SPI Slave block still remains
+//! disabled and must be enabled with EUSCI_A_SPI_enable()
+//!
+//! \param baseAddress is the base address of the EUSCI_A_SPI Slave module.
+//! \param msbFirst controls the direction of the receive and transmit shift
+//!        register.
+//!        Valid values are:
+//!        - \b EUSCI_A_SPI_MSB_FIRST
+//!        - \b EUSCI_A_SPI_LSB_FIRST [Default]
+//! \param clockPhase is clock phase select.
+//!        Valid values are:
+//!        - \b EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
+//!           [Default]
+//!        - \b EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
+//! \param clockPolarity is clock polarity select
+//!        Valid values are:
+//!        - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
+//!        - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]
+//! \param spiMode is SPI mode select
+//!        Valid values are:
+//!        - \b EUSCI_A_SPI_3PIN
+//!        - \b EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH
+//!        - \b EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW
+//!
+//! Modified bits are \b UCMSB, \b UCMST, \b UC7BIT, \b UCCKPL, \b UCCKPH, \b
+//! UCMODE and \b UCSWRST of \b UCAxCTLW0 register.
+//!
+//! \return STATUS_SUCCESS
+//
+//*****************************************************************************
+bool EUSCI_A_SPI_slaveInit(uint32_t baseAddress, uint16_t msbFirst,
+        uint16_t clockPhase, uint16_t clockPolarity, uint16_t spiMode)
+{
+    ASSERT(
+            (EUSCI_A_SPI_MSB_FIRST == msbFirst)
+            || (EUSCI_A_SPI_LSB_FIRST == msbFirst));
+
+    ASSERT(
+            (EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
+                    == clockPhase)
+            || (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
+                    == clockPhase));
+
+    ASSERT(
+            (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity)
+            || (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW
+                    == clockPolarity));
+
+    ASSERT(
+            (EUSCI_A_SPI_3PIN == spiMode)
+            || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH == spiMode)
+            || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW == spiMode));
+
+    //Disable USCI Module
+    BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
+
+    //Reset OFS_UCAxCTLW0 register
+    EUSCI_A_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_A_CMSIS(baseAddress)->rCTLW0.r
+            & ~(UCMSB + UC7BIT + UCMST + UCCKPL + UCCKPH + UCMODE_3))
+            | (clockPhase + clockPolarity + msbFirst + UCSYNC + spiMode);
+
+    return true;
+}
+
+//*****************************************************************************
+//
+//! \brief Changes the SPI colock phase and polarity. At the end of this
+//! function call, SPI module is left enabled.
+//!
+//! \param baseAddress is the base address of the EUSCI_A_SPI module.
+//! \param clockPhase is clock phase select.
+//!        Valid values are:
+//!        - \b EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
+//!           [Default]
+//!        - \b EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
+//! \param clockPolarity is clock polarity select
+//!        Valid values are:
+//!        - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
+//!        - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]
+//!
+//! Modified bits are \b UCCKPL, \b UCCKPH and \b UCSWRST of \b UCAxCTLW0
+//! register.
+//!
+//! \return None
+//
+//*****************************************************************************
+void EUSCI_A_SPI_changeClockPhasePolarity(uint32_t baseAddress,
+        uint16_t clockPhase, uint16_t clockPolarity)
+{
+
+    ASSERT(
+            (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity)
+            || (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW
+                    == clockPolarity));
+
+    ASSERT(
+            (EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
+                    == clockPhase)
+            || (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
+                    == clockPhase));
+
+    //Disable the USCI Module
+    BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
+
+    EUSCI_A_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_A_CMSIS(baseAddress)->rCTLW0.r
+            & ~(UCCKPH + UCCKPL)) | (clockPhase + clockPolarity);
+
+    //Reset the UCSWRST bit to enable the USCI Module
+    BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0;
+}
+
+//*****************************************************************************
+//
+//! \brief Transmits a byte from the SPI Module.
+//!
+//! This function will place the supplied data into SPI trasmit data register
+//! to start transmission.
+//!
+//! \param baseAddress is the base address of the EUSCI_A_SPI module.
+//! \param transmitData data to be transmitted from the SPI module
+//!
+//! \return None
+//
+//*****************************************************************************
+void EUSCI_A_SPI_transmitData(uint32_t baseAddress, uint8_t transmitData)
+{
+    EUSCI_A_CMSIS(baseAddress)->rTXBUF.r = transmitData;
+}
+
+//*****************************************************************************
+//
+//! \brief Receives a byte that has been sent to the SPI Module.
+//!
+//! This function reads a byte of data from the SPI receive data Register.
+//!
+//! \param baseAddress is the base address of the EUSCI_A_SPI module.
+//!
+//! \return Returns the byte received from by the SPI module, cast as an
+//!         uint8_t.
+//
+//*****************************************************************************
+uint8_t EUSCI_A_SPI_receiveData(uint32_t baseAddress)
+{
+    return EUSCI_A_CMSIS(baseAddress)->rRXBUF.r;
+}
+
+//*****************************************************************************
+//
+//! \brief Enables individual SPI interrupt sources.
+//!
+//! Enables the indicated SPI interrupt sources.  Only the sources that are
+//! enabled can be reflected to the processor interrupt; disabled sources have
+//! no effect on the processor. Does not clear interrupt flags.
+//!
+//! \param baseAddress is the base address of the EUSCI_A_SPI module.
+//! \param mask is the bit mask of the interrupt sources to be enabled.
+//!        Mask value is the logical OR of any of the following:
+//!        - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT
+//!        - \b EUSCI_A_SPI_RECEIVE_INTERRUPT
+//!
+//! Modified bits of \b UCAxIFG register and bits of \b UCAxIE register.
+//!
+//! \return None
+//
+//*****************************************************************************
+void EUSCI_A_SPI_enableInterrupt(uint32_t baseAddress, uint8_t mask)
+{
+    ASSERT(
+            !(mask
+                    & ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
+                            | EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
+
+    EUSCI_A_CMSIS(baseAddress)->rIE.r |= mask;
+}
+
+//*****************************************************************************
+//
+//! \brief Disables individual SPI interrupt sources.
+//!
+//! Disables the indicated SPI interrupt sources. Only the sources that are
+//! enabled can be reflected to the processor interrupt; disabled sources have
+//! no effect on the processor.
+//!
+//! \param baseAddress is the base address of the EUSCI_A_SPI module.
+//! \param mask is the bit mask of the interrupt sources to be disabled.
+//!        Mask value is the logical OR of any of the following:
+//!        - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT
+//!        - \b EUSCI_A_SPI_RECEIVE_INTERRUPT
+//!
+//! Modified bits of \b UCAxIE register.
+//!
+//! \return None
+//
+//*****************************************************************************
+void EUSCI_A_SPI_disableInterrupt(uint32_t baseAddress, uint8_t mask)
+{
+    ASSERT(
+            !(mask
+                    & ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
+                            | EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
+
+    EUSCI_A_CMSIS(baseAddress)->rIE.r &= ~mask;
+}
+
+//*****************************************************************************
+//
+//! \brief Gets the current SPI interrupt status.
+//!
+//! This returns the interrupt status for the SPI module based on which flag is
+//! passed.
+//!
+//! \param baseAddress is the base address of the EUSCI_A_SPI module.
+//! \param mask is the masked interrupt flag status to be returned.
+//!        Mask value is the logical OR of any of the following:
+//!        - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT
+//!        - \b EUSCI_A_SPI_RECEIVE_INTERRUPT
+//!
+//! \return Logical OR of any of the following:
+//!         - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT
+//!         - \b EUSCI_A_SPI_RECEIVE_INTERRUPT
+//!         \n indicating the status of the masked interrupts
+//
+//*****************************************************************************
+uint8_t EUSCI_A_SPI_getInterruptStatus(uint32_t baseAddress, uint8_t mask)
+{
+    ASSERT(
+            !(mask
+                    & ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
+                            | EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
+
+    return EUSCI_A_CMSIS(baseAddress)->rIFG.r & mask;
+}
+
+//*****************************************************************************
+//
+//! \brief Clears the selected SPI interrupt status flag.
+//!
+//! \param baseAddress is the base address of the EUSCI_A_SPI module.
+//! \param mask is the masked interrupt flag to be cleared.
+//!        Mask value is the logical OR of any of the following:
+//!        - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT
+//!        - \b EUSCI_A_SPI_RECEIVE_INTERRUPT
+//!
+//! Modified bits of \b UCAxIFG register.
+//!
+//! \return None
+//
+//*****************************************************************************
+void EUSCI_A_SPI_clearInterruptFlag(uint32_t baseAddress, uint8_t mask)
+{
+    ASSERT(
+            !(mask
+                    & ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
+                            | EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
+
+    EUSCI_A_CMSIS(baseAddress)->rIFG.r &= ~mask;
+}
+
+//*****************************************************************************
+//
+//! \brief Enables the SPI block.
+//!
+//! This will enable operation of the SPI block.
+//!
+//! \param baseAddress is the base address of the EUSCI_A_SPI module.
+//!
+//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register.
+//!
+//! \return None
+//
+//*****************************************************************************
+void EUSCI_A_SPI_enable(uint32_t baseAddress)
+{
+    //Reset the UCSWRST bit to enable the USCI Module
+    BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0;
+}
+
+//*****************************************************************************
+//
+//! \brief Disables the SPI block.
+//!
+//! This will disable operation of the SPI block.
+//!
+//! \param baseAddress is the base address of the EUSCI_A_SPI module.
+//!
+//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register.
+//!
+//! \return None
+//
+//*****************************************************************************
+void EUSCI_A_SPI_disable(uint32_t baseAddress)
+{
+    //Set the UCSWRST bit to disable the USCI Module
+    BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
+}
+
+//*****************************************************************************
+//
+//! \brief Returns the address of the RX Buffer of the SPI for the DMA module.
+//!
+//! Returns the address of the SPI RX Buffer. This can be used in conjunction
+//! with the DMA to store the received data directly to memory.
+//!
+//! \param baseAddress is the base address of the EUSCI_A_SPI module.
+//!
+//! \return the address of the RX Buffer
+//
+//*****************************************************************************
+uint32_t EUSCI_A_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress)
+{
+    return baseAddress + OFS_UCA0RXBUF;
+}
+
+//*****************************************************************************
+//
+//! \brief Returns the address of the TX Buffer of the SPI for the DMA module.
+//!
+//! Returns the address of the SPI TX Buffer. This can be used in conjunction
+//! with the DMA to obtain transmitted data directly from memory.
+//!
+//! \param baseAddress is the base address of the EUSCI_A_SPI module.
+//!
+//! \return the address of the TX Buffer
+//
+//*****************************************************************************
+uint32_t EUSCI_A_SPI_getTransmitBufferAddressForDMA(uint32_t baseAddress)
+{
+    return baseAddress + OFS_UCA0TXBUF;
+}
+
+//*****************************************************************************
+//
+//! \brief Indicates whether or not the SPI bus is busy.
+//!
+//! This function returns an indication of whether or not the SPI bus is
+//! busy.This function checks the status of the bus via UCBBUSY bit
+//!
+//! \param baseAddress is the base address of the EUSCI_A_SPI module.
+//!
+//! \return true if busy, false otherwise
+//*****************************************************************************
+bool EUSCI_A_SPI_isBusy(uint32_t baseAddress)
+{
+    //Return the bus busy status.
+    return BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rSTATW.r, UCBBUSY_OFS);
+}
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/spi.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/spi.h
new file mode 100644
index 000000000..d874494d7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/spi.h
@@ -0,0 +1,822 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef SPI_H_
+#define SPI_H_
+
+//*****************************************************************************
+//
+//! \addtogroup spi_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <msp.h>
+#include "eusci.h"
+
+/* Configuration Defines */
+#define EUSCI_SPI_CLOCKSOURCE_ACLK    UCSSEL__ACLK
+#define EUSCI_SPI_CLOCKSOURCE_SMCLK   UCSSEL__SMCLK
+
+#define EUSCI_SPI_MSB_FIRST    UCMSB
+#define EUSCI_SPI_LSB_FIRST    0x00
+
+#define EUSCI_SPI_BUSY        UCBUSY
+#define EUSCI_SPI_NOT_BUSY    0x00
+
+#define EUSCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT    0x00
+#define EUSCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT    UCCKPH
+
+#define EUSCI_SPI_3PIN                      UCMODE_0
+#define EUSCI_SPI_4PIN_UCxSTE_ACTIVE_HIGH   UCMODE_1
+#define EUSCI_SPI_4PIN_UCxSTE_ACTIVE_LOW    UCMODE_2
+
+#define EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH    UCCKPL
+#define EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW     0x00
+
+#define EUSCI_SPI_TRANSMIT_INTERRUPT    UCTXIE
+#define EUSCI_SPI_RECEIVE_INTERRUPT     UCRXIE
+
+#define EUSCI_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE           UCSTEM
+#define EUSCI_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS    0x00
+
+//*****************************************************************************
+//
+//! \typedef eUSCI_SPI_MasterConfig
+//! \brief Type definition for \link _eUSCI_SPI_MasterConfig \endlink structure
+//!
+//! \struct _eUSCI_SPI_MasterConfig
+//! \brief Configuration structure for master mode in the \b SPI module. See
+//!          \link SPI_initMaster \endlink for parameter documentation.
+//
+//*****************************************************************************
+typedef struct _eUSCI_SPI_MasterConfig
+{
+    uint_fast8_t selectClockSource;
+    uint32_t clockSourceFrequency;
+    uint32_t desiredSpiClock;
+    uint_fast16_t msbFirst;
+    uint_fast16_t clockPhase;
+    uint_fast16_t clockPolarity;
+    uint_fast16_t spiMode;
+} eUSCI_SPI_MasterConfig;
+
+//*****************************************************************************
+//
+//! \typedef eUSCI_SPI_SlaveConfig
+//! \brief Type definition for \link _eUSCI_SPI_SlaveConfig \endlink structure
+//!
+//! \struct _eUSCI_SPI_SlaveConfig
+//! \brief Configuration structure for slave mode in the \b SPI module. See
+//!          \link SPI_initSlave \endlink for parameter documentation.
+//
+//*****************************************************************************
+typedef struct _eUSCI_SPI_SlaveConfig
+{
+    uint_fast16_t msbFirst;
+    uint_fast16_t clockPhase;
+    uint_fast16_t clockPolarity;
+    uint_fast16_t spiMode;
+} eUSCI_SPI_SlaveConfig;
+
+//*****************************************************************************
+//
+//! Initializes the SPI Master block.
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//! \param config Configuration structure for SPI master mode
+//!
+//! <hr>
+//! <b>Configuration options for \link eUSCI_SPI_MasterConfig \endlink structure.</b>
+//! <hr>
+//!
+//! \param selectClockSource selects clock source. Valid values are
+//!         - \b  EUSCI_SPI_CLOCKSOURCE_ACLK
+//!         - \b  EUSCI_SPI_CLOCKSOURCE_SMCLK
+//! \param clockSourceFrequency is the frequency of the selected clock source
+//! \param desiredSpiClock is the desired clock rate for SPI communication
+//! \param msbFirst controls the direction of the receive and transmit shift
+//!      register. Valid values are
+//!         - \b  EUSCI_SPI_MSB_FIRST
+//!         - \b  EUSCI_SPI_LSB_FIRST [Default Value]
+//! \param clockPhase is clock phase select.
+//!         Valid values are
+//!         - \b  EUSCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
+//!                                                          [Default Value]
+//!         - \b  EUSCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
+//! \param clockPolarity is clock polarity select.
+//!         Valid values are
+//!         - \b  EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
+//!         - \b  EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW  [Default Value]
+//! \param spiMode is SPI mode select.
+//!         Valid values are
+//!         - \b  EUSCI_SPI_3PIN [Default Value]
+//!         - \b  EUSCI_SPI_4PIN_UCxSTE_ACTIVE_HIGH
+//!         - \b  EUSCI_SPI_4PIN_UCxSTE_ACTIVE_LOW
+//! Upon successful initialization of the SPI master block, this function
+//! will have set the bus speed for the master, but the SPI Master block
+//! still remains disabled and must be enabled with SPI_enableModule()
+//!
+//! Modified bits are \b UCCKPH, \b UCCKPL, \b UC7BIT, \b UCMSB,\b UCSSELx,
+//! \b UCSWRST bits of \b UCAxCTLW0 register
+//!
+//! \return true
+//
+//*****************************************************************************
+extern bool SPI_initMaster(uint32_t moduleInstance,
+        const eUSCI_SPI_MasterConfig *config);
+
+//*****************************************************************************
+//
+//! Selects 4Pin Functionality
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!
+//! \param select4PinFunctionality selects Clock source. Valid values are
+//!         - \b EUSCI_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS
+//!         - \b EUSCI_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE
+//! This function should be invoked only in 4-wire mode. Invoking this function
+//! has no effect in 3-wire mode.
+//!
+//! Modified bits are \b UCSTEM bit of \b UCAxCTLW0 register
+//!
+//! \return true
+//
+//*****************************************************************************
+extern void SPI_selectFourPinFunctionality(uint32_t moduleInstance,
+        uint_fast8_t select4PinFunctionality);
+
+//*****************************************************************************
+//
+//! Initializes the SPI Master clock.At the end of this function call, SPI
+//! module is left enabled.
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!
+//! \param clockSourceFrequency is the frequency of the selected clock source
+//! \param desiredSpiClock is the desired clock rate for SPI communication.
+//!
+//! Modified bits are \b UCSWRST bit of \b UCAxCTLW0 register and
+//! \b UCAxBRW register
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void SPI_changeMasterClock(uint32_t moduleInstance,
+        uint32_t clockSourceFrequency, uint32_t desiredSpiClock);
+
+//*****************************************************************************
+//
+//! Initializes the SPI Slave block.
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//! \param config Configuration structure for SPI slave mode
+//!
+//! <hr>
+//! <b>Configuration options for \link eUSCI_SPI_SlaveConfig \endlink structure.</b>
+//! <hr>
+//!
+//! \param msbFirst controls the direction of the receive and transmit shift
+//!      register. Valid values are
+//!         - \b  EUSCI_SPI_MSB_FIRST
+//!         - \b  EUSCI_SPI_LSB_FIRST [Default Value]
+//! \param clockPhase is clock phase select.
+//!         Valid values are
+//!         - \b  EUSCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
+//!                                                          [Default Value]
+//!         - \b  EUSCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
+//! \param clockPolarity is clock polarity select.
+//!         Valid values are
+//!         - \b  EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
+//!         - \b  EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default Value]
+//! \param spiMode is SPI mode select.
+//!         Valid values are
+//!         - \b  EUSCI_SPI_3PIN [Default Value]
+//!         - \b  EUSCI_SPI_4PIN_UCxSTE_ACTIVE_HIGH
+//!         - \b  EUSCI_SPI_4PIN_UCxSTE_ACTIVE_LOW
+//! Upon successful initialization of the SPI slave block, this function
+//! will have initialized the slave block, but the SPI Slave block
+//! still remains disabled and must be enabled with SPI_enableModule()
+//!
+//! Modified bits are \b UCMSB, \b UC7BIT, \b UCMST, \b UCCKPL, \b UCCKPH,
+//! \b UCMODE, \b UCSWRST bits of \b UCAxCTLW0
+//!
+//! \return true
+//*****************************************************************************
+extern bool SPI_initSlave(uint32_t moduleInstance,
+        const eUSCI_SPI_SlaveConfig *config);
+
+//*****************************************************************************
+//
+//! Changes the SPI clock phase and polarity.At the end of this function call,
+//! SPI module is left enabled.
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!
+//! \param clockPhase is clock phase select.
+//!         Valid values are:
+//!             - \b EUSCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
+//!                                                          [Default Value]
+//!             - \b EUSCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
+//! \param clockPolarity is clock polarity select.
+//!         Valid values are:
+//!             - \b EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
+//!             - \b EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW  [Default Value]
+//!
+//! Modified bits are \b UCSWRST, \b UCCKPH, \b UCCKPL, \b UCSWRST bits of
+//! \b UCAxCTLW0
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void SPI_changeClockPhasePolarity(uint32_t moduleInstance,
+        uint_fast16_t clockPhase, uint_fast16_t clockPolarity);
+
+//*****************************************************************************
+//
+//! Transmits a byte from the SPI Module.
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!
+//! \param transmitData data to be transmitted from the SPI module
+//!
+//! This function will place the supplied data into SPI transmit data register
+//! to start transmission
+//!
+//! Modified register is \b UCAxTXBUF
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void SPI_transmitData(uint32_t moduleInstance,
+        uint_fast8_t transmitData);
+
+//*****************************************************************************
+//
+//! Receives a byte that has been sent to the SPI Module.
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!
+//!
+//! This function reads a byte of data from the SPI receive data Register.
+//!
+//! \return Returns the byte received from by the SPI module, cast as an
+//! uint8_t.
+//
+//*****************************************************************************
+extern uint8_t SPI_receiveData(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Enables the SPI block.
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!
+//!
+//! This will enable operation of the SPI block.
+//! Modified bits are \b UCSWRST bit of \b UCAxCTLW0 register.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void SPI_enableModule(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Disables the SPI block.
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!
+//!
+//! This will disable operation of the SPI block.
+//!
+//! Modified bits are \b UCSWRST bit of \b UCAxCTLW0 register.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void SPI_disableModule(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Returns the address of the RX Buffer of the SPI for the DMA module.
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!
+//!
+//! Returns the address of the SPI RX Buffer. This can be used in conjunction
+//! with the DMA to store the received data directly to memory.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern uint32_t SPI_getReceiveBufferAddressForDMA(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Returns the address of the TX Buffer of the SPI for the DMA module.
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!
+//!
+//! Returns the address of the SPI TX Buffer. This can be used in conjunction
+//! with the DMA to obtain transmitted data directly from memory.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern uint32_t SPI_getTransmitBufferAddressForDMA(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Indicates whether or not the SPI bus is busy.
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!
+//!
+//! This function returns an indication of whether or not the SPI bus is
+//! busy.This function checks the status of the bus via UCBBUSY bit
+//!
+//! \return EUSCI_SPI_BUSY if the SPI module transmitting or receiving
+//! is busy; otherwise, returns EUSCI_SPI_NOT_BUSY.
+//
+//*****************************************************************************
+extern uint_fast8_t SPI_isBusy(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Enables individual SPI interrupt sources.
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!
+//! \param mask is the bit mask of the interrupt sources to be enabled.
+//!
+//! Enables the indicated SPI interrupt sources.  Only the sources that
+//! are enabled can be reflected to the processor interrupt; disabled sources
+//! have no effect on the processor.
+//!
+//! The mask parameter is the logical OR of any of the following:
+//!       - \b EUSCI_SPI_RECEIVE_INTERRUPT Receive interrupt
+//!       - \b EUSCI_SPI_TRANSMIT_INTERRUPT Transmit interrupt
+//!
+//! Modified registers are \b UCAxIFG and \b UCAxIE
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void SPI_enableInterrupt(uint32_t moduleInstance, uint_fast8_t mask);
+
+//*****************************************************************************
+//
+//! Disables individual SPI interrupt sources.
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!
+//! \param mask is the bit mask of the interrupt sources to be
+//! disabled.
+//!
+//! Disables the indicated SPI interrupt sources.  Only the sources that
+//! are enabled can be reflected to the processor interrupt; disabled sources
+//! have no effect on the processor.
+//!
+//! The mask parameter is the logical OR of any of the following:
+//!       - \b EUSCI_SPI_RECEIVE_INTERRUPT Receive interrupt
+//!       - \b EUSCI_SPI_TRANSMIT_INTERRUPT Transmit interrupt
+//!
+//! Modified register is \b UCAxIE
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void SPI_disableInterrupt(uint32_t moduleInstance, uint_fast8_t mask);
+
+//*****************************************************************************
+//
+//! Gets the current SPI interrupt status.
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//! \param mask Mask of interrupt to filter. This can include:
+//!          - \b EUSCI_SPI_RECEIVE_INTERRUPT -Receive interrupt
+//!          - \b EUSCI_SPI_TRANSMIT_INTERRUPT - Transmit interrupt
+//!
+//! Modified registers are \b UCAxIFG.
+//!
+//! \return The current interrupt status as the mask of the set flags
+//! Mask parameter can be either any of the following selection:
+//! - \b EUSCI_SPI_RECEIVE_INTERRUPT -Receive interrupt
+//! - \b EUSCI_SPI_TRANSMIT_INTERRUPT - Transmit interrupt
+//
+//*****************************************************************************
+extern uint_fast8_t SPI_getInterruptStatus(uint32_t moduleInstance,
+        uint16_t mask);
+
+//*****************************************************************************
+//
+//! Gets the current SPI interrupt status masked with the enabled interrupts.
+//! This function is useful to call in ISRs to get a list of pending
+//! interrupts that are actually enabled and could have caused
+//! the ISR.
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!
+//! Modified registers are \b UCAxIFG.
+//!
+//! \return The current interrupt status as the mask of the set flags
+//! Mask parameter can be either any of the following selection:
+//! - \b EUSCI_SPI_RECEIVE_INTERRUPT -Receive interrupt
+//! - \b EUSCI_SPI_TRANSMIT_INTERRUPT - Transmit interrupt
+//
+//*****************************************************************************
+extern uint_fast8_t SPI_getEnabledInterruptStatus(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Clears the selected SPI interrupt status flag.
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!
+//! \param mask is the masked interrupt flag to be cleared.
+//!
+//! The mask parameter is the logical OR of any of the following:
+//! - \b EUSCI_SPI_RECEIVE_INTERRUPT -Receive interrupt
+//! - \b EUSCI_SPI_TRANSMIT_INTERRUPT - Transmit interrupt
+//! Modified registers are \b UCAxIFG.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void SPI_clearInterruptFlag(uint32_t moduleInstance, uint_fast8_t mask);
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the timer capture compare interrupt.
+//!
+//! \param moduleInstance is the instance of the eUSCI (SPI) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!  It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//! \param intHandler is a pointer to the function to be called when the
+//! timer capture compare interrupt occurs.
+//!
+//! This function registers the handler to be called when a timer
+//! interrupt occurs. This function enables the global interrupt in the
+//! interrupt controller; specific SPI interrupts must be enabled
+//! via SPI_enableInterrupt().  It is the interrupt handler's responsibility to
+//! clear the interrupt source via SPI_clearInterruptFlag().
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void SPI_registerInterrupt(uint32_t moduleInstance,
+        void (*intHandler)(void));
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the timer
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!         - \b EUSCI_B0_MODULE
+//!         - \b EUSCI_B1_MODULE
+//!         - \b EUSCI_B2_MODULE
+//!         - \b EUSCI_B3_MODULE
+//!
+//! This function unregisters the handler to be called when timer
+//! interrupt occurs.  This function also masks off the interrupt in the
+//! interrupt controller so that the interrupt handler no longer is called.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void SPI_unregisterInterrupt(uint32_t moduleInstance);
+
+/* Backwards Compatibility Layer */
+#define EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT            0x00
+#define EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT          UCCKPH
+
+#define EUSCI_B_SPI_MSB_FIRST                                             UCMSB
+#define EUSCI_B_SPI_LSB_FIRST                                              0x00
+
+#define EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH                        UCCKPL
+#define EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW                           0x00
+
+#define EUSCI_B_SPI_CLOCKSOURCE_ACLK                               UCSSEL__ACLK
+#define EUSCI_B_SPI_CLOCKSOURCE_SMCLK                             UCSSEL__SMCLK
+
+#define EUSCI_B_SPI_3PIN                                               UCMODE_0
+#define EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH                            UCMODE_1
+#define EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW                             UCMODE_2
+
+#define EUSCI_B_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS                   0x00
+#define EUSCI_B_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE                        UCSTEM
+
+#define EUSCI_B_SPI_TRANSMIT_INTERRUPT                                   UCTXIE
+#define EUSCI_B_SPI_RECEIVE_INTERRUPT                                    UCRXIE
+
+#define EUSCI_B_SPI_BUSY                                                 UCBUSY
+#define EUSCI_B_SPI_NOT_BUSY                                               0x00
+
+#define EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT            0x00
+#define EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT          UCCKPH
+
+#define EUSCI_A_SPI_MSB_FIRST                                             UCMSB
+#define EUSCI_A_SPI_LSB_FIRST                                              0x00
+
+#define EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH                        UCCKPL
+#define EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW                           0x00
+
+#define EUSCI_A_SPI_CLOCKSOURCE_ACLK                               UCSSEL__ACLK
+#define EUSCI_A_SPI_CLOCKSOURCE_SMCLK                             UCSSEL__SMCLK
+
+#define EUSCI_A_SPI_3PIN                                               UCMODE_0
+#define EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH                            UCMODE_1
+#define EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW                             UCMODE_2
+
+#define EUSCI_A_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS                   0x00
+#define EUSCI_A_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE                        UCSTEM
+
+#define EUSCI_A_SPI_TRANSMIT_INTERRUPT                                   UCTXIE
+#define EUSCI_A_SPI_RECEIVE_INTERRUPT                                    UCRXIE
+
+#define EUSCI_A_SPI_BUSY                                                 UCBUSY
+#define EUSCI_A_SPI_NOT_BUSY                                               0x00
+
+extern void EUSCI_A_SPI_select4PinFunctionality(uint32_t baseAddress,
+        uint8_t select4PinFunctionality);
+extern void EUSCI_A_SPI_masterChangeClock(uint32_t baseAddress,
+        uint32_t clockSourceFrequency, uint32_t desiredSpiClock);
+extern bool EUSCI_A_SPI_slaveInit(uint32_t baseAddress, uint16_t msbFirst,
+        uint16_t clockPhase, uint16_t clockPolarity, uint16_t spiMode);
+extern void EUSCI_A_SPI_changeClockPhasePolarity(uint32_t baseAddress,
+        uint16_t clockPhase, uint16_t clockPolarity);
+extern void EUSCI_A_SPI_transmitData(uint32_t baseAddress,
+        uint8_t transmitData);
+extern uint8_t EUSCI_A_SPI_receiveData(uint32_t baseAddress);
+extern void EUSCI_A_SPI_enableInterrupt(uint32_t baseAddress, uint8_t mask);
+extern void EUSCI_A_SPI_disableInterrupt(uint32_t baseAddress, uint8_t mask);
+extern uint8_t EUSCI_A_SPI_getInterruptStatus(uint32_t baseAddress,
+        uint8_t mask);
+extern void EUSCI_A_SPI_clearInterruptFlag(uint32_t baseAddress, uint8_t mask);
+extern void EUSCI_A_SPI_enable(uint32_t baseAddress);
+extern void EUSCI_A_SPI_disable(uint32_t baseAddress);
+extern uint32_t EUSCI_A_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress);
+extern uint32_t EUSCI_A_SPI_getTransmitBufferAddressForDMA(
+        uint32_t baseAddress);
+extern bool EUSCI_A_SPI_isBusy(uint32_t baseAddress);
+extern void EUSCI_B_SPI_select4PinFunctionality(uint32_t baseAddress,
+        uint8_t select4PinFunctionality);
+extern void EUSCI_B_SPI_masterChangeClock(uint32_t baseAddress,
+        uint32_t clockSourceFrequency, uint32_t desiredSpiClock);
+extern bool EUSCI_B_SPI_slaveInit(uint32_t baseAddress, uint16_t msbFirst,
+        uint16_t clockPhase, uint16_t clockPolarity, uint16_t spiMode);
+extern void EUSCI_B_SPI_changeClockPhasePolarity(uint32_t baseAddress,
+        uint16_t clockPhase, uint16_t clockPolarity);
+extern void EUSCI_B_SPI_transmitData(uint32_t baseAddress,
+        uint8_t transmitData);
+extern uint8_t EUSCI_B_SPI_receiveData(uint32_t baseAddress);
+extern void EUSCI_B_SPI_enableInterrupt(uint32_t baseAddress, uint8_t mask);
+extern void EUSCI_B_SPI_disableInterrupt(uint32_t baseAddress, uint8_t mask);
+extern uint8_t EUSCI_B_SPI_getInterruptStatus(uint32_t baseAddress,
+        uint8_t mask);
+extern void EUSCI_B_SPI_clearInterruptFlag(uint32_t baseAddress, uint8_t mask);
+extern void EUSCI_B_SPI_enable(uint32_t baseAddress);
+extern void EUSCI_B_SPI_disable(uint32_t baseAddress);
+extern uint32_t EUSCI_B_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress);
+extern uint32_t EUSCI_B_SPI_getTransmitBufferAddressForDMA(
+        uint32_t baseAddress);
+extern bool EUSCI_B_SPI_isBusy(uint32_t baseAddress);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif /* SPI_H_ */
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/sysctl.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/sysctl.c
new file mode 100644
index 000000000..abc6bc9f1
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/sysctl.c
@@ -0,0 +1,239 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+/* Standard Includes */
+#include <stdint.h>
+#include <stdbool.h>
+
+/* DriverLib Includes */
+#include <sysctl.h>
+#include <debug.h>
+
+#ifdef DEBUG
+
+static bool SysCtlSRAMBankValid(uint8_t sramBank)
+{
+    return(
+            sramBank == SYSCTL_SRAM_BANK7 ||
+            sramBank == SYSCTL_SRAM_BANK6 ||
+            sramBank == SYSCTL_SRAM_BANK5 ||
+            sramBank == SYSCTL_SRAM_BANK4 ||
+            sramBank == SYSCTL_SRAM_BANK3 ||
+            sramBank == SYSCTL_SRAM_BANK2 ||
+            sramBank == SYSCTL_SRAM_BANK1
+    );
+}
+
+static bool SysCtlSRAMBankValidRet(uint8_t sramBank)
+{
+    sramBank &= ~(SYSCTL_SRAM_BANK7 & SYSCTL_SRAM_BANK6 &
+            SYSCTL_SRAM_BANK5 & SYSCTL_SRAM_BANK4 &
+            SYSCTL_SRAM_BANK3 & SYSCTL_SRAM_BANK2 &
+            SYSCTL_SRAM_BANK1);
+
+    return (sramBank == 0);
+}
+
+static bool SysCtlPeripheralIsValid (uint16_t hwPeripheral)
+{
+    hwPeripheral &= ~(SYSCTL_PERIPH_DMA & SYSCTL_PERIPH_WDT &
+            SYSCTL_PERIPH_ADC & SYSCTL_PERIPH_EUSCIB3 &
+            SYSCTL_PERIPH_EUSCIB2 & SYSCTL_PERIPH_EUSCIB1 &
+            SYSCTL_PERIPH_EUSCIB0 & SYSCTL_PERIPH_EUSCIA3 &
+            SYSCTL_PERIPH_EUSCIA2 & SYSCTL_PERIPH_EUSCIA1 &
+            SYSCTL_PERIPH_EUSCIA0 & SYSCTL_PERIPH_TIMER32_0_MODULE &
+            SYSCTL_PERIPH_TIMER16_3 & SYSCTL_PERIPH_TIMER16_2 &
+            SYSCTL_PERIPH_TIMER16_2 & SYSCTL_PERIPH_TIMER16_1 &
+            SYSCTL_PERIPH_TIMER16_0);
+
+    return (hwPeripheral == 0);
+}
+#endif
+
+uint_least32_t SysCtl_getSRAMSize(void)
+{
+    return SYSCTL->rSRAM_SIZE;
+}
+
+uint_least32_t SysCtl_getFlashSize(void)
+{
+    return SYSCTL->rFLASH_SIZE;
+}
+
+void SysCtl_disableNMISource(uint_fast8_t flags)
+{
+    SYSCTL->rNMI_CTLSTAT.r &= ~(flags);
+}
+
+void SysCtl_enableNMISource(uint_fast8_t flags)
+{
+    SYSCTL->rNMI_CTLSTAT.r |= flags;
+}
+
+uint_fast8_t SysCtl_getNMISourceStatus(void)
+{
+    return SYSCTL->rNMI_CTLSTAT.r;
+}
+
+void SysCtl_enableSRAMBank(uint_fast8_t sramBank)
+{
+    ASSERT(SysCtlSRAMBankValid(sramBank));
+
+    /* Waiting for SRAM Ready Bit to be set */
+    while (!SYSCTL->rSRAM_BANKEN.b.bSRAM_RDY)
+        ;
+
+    SYSCTL->rSRAM_BANKEN.r = (sramBank | SYSCTL_SRAM_BANKEN_BNK0_EN);
+}
+
+void SysCtl_disableSRAMBank(uint_fast8_t sramBank)
+{
+    ASSERT(SysCtlSRAMBankValid(sramBank));
+
+    /* Waiting for SRAM Ready Bit to be set */
+    while (!SYSCTL->rSRAM_BANKEN.b.bSRAM_RDY)
+        ;      
+
+    switch (sramBank)
+    {
+    case SYSCTL_SRAM_BANK7:
+        sramBank = SYSCTL_SRAM_BANK6 +  SYSCTL_SRAM_BANK5 + SYSCTL_SRAM_BANK4
+                        + SYSCTL_SRAM_BANK3 + SYSCTL_SRAM_BANK2 
+                        + SYSCTL_SRAM_BANK1;
+        break;
+    case SYSCTL_SRAM_BANK6:
+        sramBank =   SYSCTL_SRAM_BANK5 + SYSCTL_SRAM_BANK4
+                        + SYSCTL_SRAM_BANK3 + SYSCTL_SRAM_BANK2 
+                        + SYSCTL_SRAM_BANK1;
+        break;
+    case SYSCTL_SRAM_BANK5:
+        sramBank =   SYSCTL_SRAM_BANK4 + SYSCTL_SRAM_BANK3  
+                + SYSCTL_SRAM_BANK2 + SYSCTL_SRAM_BANK1;
+        break;
+    case SYSCTL_SRAM_BANK4:
+        sramBank =   SYSCTL_SRAM_BANK3 + SYSCTL_SRAM_BANK2 
+                        + SYSCTL_SRAM_BANK1;
+        break;
+    case SYSCTL_SRAM_BANK3:
+        sramBank =   SYSCTL_SRAM_BANK2 + SYSCTL_SRAM_BANK1;
+        break;
+    case SYSCTL_SRAM_BANK2:
+        sramBank = SYSCTL_SRAM_BANK1;
+        break;
+    case SYSCTL_SRAM_BANK1:
+        sramBank = 0;
+        break;
+    default:
+        return;
+    }
+
+    SYSCTL->rSRAM_BANKEN.r = (sramBank | SYSCTL_SRAM_BANKEN_BNK0_EN);
+}
+
+void SysCtl_enableSRAMBankRetention(uint_fast8_t sramBank)
+{
+    ASSERT(SysCtlSRAMBankValidRet(sramBank));
+
+    /* Waiting for SRAM Ready Bit to be set */
+    while (!SYSCTL->rSRAM_BANKRET.b.bSRAM_RDY)
+        ;
+
+    SYSCTL->rSRAM_BANKRET.r |= sramBank;
+}
+
+void SysCtl_disableSRAMBankRetention(uint_fast8_t sramBank)
+{
+    ASSERT(SysCtlSRAMBankValidRet(sramBank));
+
+    /* Waiting for SRAM Ready Bit to be set */
+    while (!SYSCTL->rSRAM_BANKRET.b.bSRAM_RDY)
+        ;
+
+    SYSCTL->rSRAM_BANKRET.r &= ~sramBank;
+}
+
+void SysCtl_rebootDevice(void)
+{
+    SYSCTL->rREBOOT_CTL.r = (SYSCTL_REBOOT_CTL_REBOOT | SYSCTL_REBOOT_KEY);
+}
+
+void SysCtl_enablePeripheralAtCPUHalt(uint_fast16_t devices)
+{
+    ASSERT(SysCtlPeripheralIsValid(devices));
+    SYSCTL->rPERIHALT_CTL.r &= ~devices;
+}
+
+void SysCtl_disablePeripheralAtCPUHalt(uint_fast16_t devices)
+{
+    ASSERT(SysCtlPeripheralIsValid(devices));
+    SYSCTL->rPERIHALT_CTL.r |= devices;
+}
+
+void SysCtl_setWDTTimeoutResetType(uint_fast8_t resetType)
+{
+    if (resetType)
+        SYSCTL->rWDTRESET_CTL.r |=
+                SYSCTL_WDTRESET_CTL_TIMEOUT;
+    else
+        SYSCTL->rWDTRESET_CTL.r &= ~SYSCTL_WDTRESET_CTL_TIMEOUT;
+}
+
+void SysCtl_setWDTPasswordViolationResetType(uint_fast8_t resetType)
+{
+    ASSERT(resetType <= SYSCTL_HARD_RESET);
+
+    if (resetType)
+        SYSCTL->rWDTRESET_CTL.r |=
+                SYSCTL_WDTRESET_CTL_VIOLATION;
+    else
+        SYSCTL->rWDTRESET_CTL.r &= ~SYSCTL_WDTRESET_CTL_VIOLATION;
+}
+
+void SysCtl_enableGlitchFilter(void)
+{
+    SYSCTL->rDIO_GLTFLT_CTL.r |= SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN;
+}
+
+void SysCtl_disableGlitchFilter(void)
+{
+    SYSCTL->rDIO_GLTFLT_CTL.r &= ~SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN;
+}
+
+uint_fast16_t SysCtl_getTempCalibrationConstant(uint32_t refVoltage,
+        uint32_t temperature)
+{
+    return HWREG16(TLV_BASE + refVoltage + temperature);
+}
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/sysctl.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/sysctl.h
new file mode 100644
index 000000000..1e32a9e57
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/sysctl.h
@@ -0,0 +1,448 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __SYSCTL_H__
+#define __SYSCTL_H__
+
+//*****************************************************************************
+//
+//! \addtogroup sysctl_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <msp.h>
+
+//*****************************************************************************
+//
+// Control specific variables 
+//
+//*****************************************************************************
+#define SYSCTL_SRAM_BANK7 SYSCTL_SRAM_BANKEN_BNK7_EN
+#define SYSCTL_SRAM_BANK6 SYSCTL_SRAM_BANKEN_BNK6_EN
+#define SYSCTL_SRAM_BANK5 SYSCTL_SRAM_BANKEN_BNK5_EN
+#define SYSCTL_SRAM_BANK4 SYSCTL_SRAM_BANKEN_BNK4_EN
+#define SYSCTL_SRAM_BANK3 SYSCTL_SRAM_BANKEN_BNK3_EN
+#define SYSCTL_SRAM_BANK2 SYSCTL_SRAM_BANKEN_BNK2_EN
+#define SYSCTL_SRAM_BANK1 SYSCTL_SRAM_BANKEN_BNK1_EN
+
+#define SYSCTL_HARD_RESET 1
+#define SYSCTL_SOFT_RESET 0
+
+#define SYSCTL_PERIPH_DMA SYSCTL_PERIHALT_CTL_DMA
+#define SYSCTL_PERIPH_WDT SYSCTL_PERIHALT_CTL_WDT
+#define SYSCTL_PERIPH_ADC SYSCTL_PERIHALT_CTL_ADC
+#define SYSCTL_PERIPH_EUSCIB3 SYSCTL_PERIHALT_CTL_EUB3
+#define SYSCTL_PERIPH_EUSCIB2 SYSCTL_PERIHALT_CTL_EUB2
+#define SYSCTL_PERIPH_EUSCIB1 SYSCTL_PERIHALT_CTL_EUB1
+#define SYSCTL_PERIPH_EUSCIB0 SYSCTL_PERIHALT_CTL_EUB0
+#define SYSCTL_PERIPH_EUSCIA3 SYSCTL_PERIHALT_CTL_EUA3
+#define SYSCTL_PERIPH_EUSCIA2 SYSCTL_PERIHALT_CTL_EUA2
+#define SYSCTL_PERIPH_EUSCIA1 SYSCTL_PERIHALT_CTL_EUA1
+#define SYSCTL_PERIPH_EUSCIA0 SYSCTL_PERIHALT_CTL_EUA0
+#define SYSCTL_PERIPH_TIMER32_0_MODULE SYSCTL_PERIHALT_CTL_T32_0
+#define SYSCTL_PERIPH_TIMER16_3 SYSCTL_PERIHALT_CTL_T16_3
+#define SYSCTL_PERIPH_TIMER16_2 SYSCTL_PERIHALT_CTL_T16_2
+#define SYSCTL_PERIPH_TIMER16_1 SYSCTL_PERIHALT_CTL_T16_1
+#define SYSCTL_PERIPH_TIMER16_0 SYSCTL_PERIHALT_CTL_T16_0
+
+#define SYSCTL_NMIPIN_SRC SYSCTL_NMI_CTLSTAT_PIN_SRC
+#define SYSCTL_PCM_SRC SYSCTL_NMI_CTLSTAT_PCM_SRC
+#define SYSCTL_PSS_SRC SYSCTL_NMI_CTLSTAT_PSS_SRC
+#define SYSCTL_CS_SRC SYSCTL_NMI_CTLSTAT_CS_SRC
+
+#define SYSCTL_REBOOT_KEY   0x6900
+
+#define SYSCTL_1_2V_REF        OFS_TLV_ADC14_REF1P2V_TS30C
+#define SYSCTL_1_45V_REF       OFS_TLV_ADC14_REF1P45V_TS30C
+#define SYSCTL_2_5V_REF        OFS_TLV_ADC14_REF2P5V_TS30C
+
+#define SYSCTL_85_DEGREES_C    0
+#define SYSCTL_30_DEGREES_C    16
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! Gets the size of the SRAM.
+//!
+//! \return The total number of bytes of SRAM.
+//
+//*****************************************************************************
+extern uint_least32_t SysCtl_getSRAMSize(void);
+
+//*****************************************************************************
+//
+//! Gets the size of the flash.
+//!
+//! \return The total number of bytes of flash.
+//
+//*****************************************************************************
+extern uint_least32_t SysCtl_getFlashSize(void);
+
+//*****************************************************************************
+//
+//! Reboots the device and causes the device to re-initialize itself.
+//!
+//! \return This function does not return.
+//
+//*****************************************************************************
+extern void SysCtl_rebootDevice(void);
+
+//*****************************************************************************
+//
+//! Enables a set of banks in the SRAM. This can be used to optimize power
+//! consumption when every SRAM bank isn't needed. It is important to note
+//! that when a  higher bank is enabled, all of the SRAM banks below that bank
+//! are also enabled. For example, if the user enables SYSCTL_SRAM_BANK7,
+//! the banks SYSCTL_SRAM_BANK1 through SYSCTL_SRAM_BANK7 will be enabled
+//! (SRAM_BANK0 is reserved and always enabled).
+//!
+//! \param sramBank The SRAM bank tier to enable.
+//!        Must be only one of the following values:
+//!                 - \b SYSCTL_SRAM_BANK1,
+//!                 - \b SYSCTL_SRAM_BANK2,
+//!                 - \b SYSCTL_SRAM_BANK3,
+//!                 - \b SYSCTL_SRAM_BANK4,
+//!                 - \b SYSCTL_SRAM_BANK5,
+//!                 - \b SYSCTL_SRAM_BANK6,
+//!                 - \b SYSCTL_SRAM_BANK7
+//!
+//! \note \b SYSCTL_SRAM_BANK0 is reserved and always enabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void SysCtl_enableSRAMBank(uint_fast8_t sramBank);
+
+//*****************************************************************************
+//
+//! Disables a set of banks in the SRAM. This can be used to optimize power
+//! consumption when every SRAM bank isn't needed. It is important to note
+//! that when a  higher bank is disabled, all of the SRAM banks above that bank
+//! are also disabled. For example, if the user disables SYSCTL_SRAM_BANK5,
+//! the banks SYSCTL_SRAM_BANK6 through SYSCTL_SRAM_BANK7 will be disabled.
+//!
+//! \param sramBank The SRAM bank tier to disable.
+//!        Must be only one of the following values:
+//!                 - \b SYSCTL_SRAM_BANK1,
+//!                 - \b SYSCTL_SRAM_BANK2,
+//!                 - \b SYSCTL_SRAM_BANK3,
+//!                 - \b SYSCTL_SRAM_BANK4,
+//!                 - \b SYSCTL_SRAM_BANK5,
+//!                 - \b SYSCTL_SRAM_BANK6,
+//!                 - \b SYSCTL_SRAM_BANK7
+//!
+//! \note \b SYSCTL_SRAM_BANK0 is reserved and always enabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void SysCtl_disableSRAMBank(uint_fast8_t sramBank);
+
+//*****************************************************************************
+//
+//! Enables retention of the specified SRAM bank register when the device goes
+//! into LPM3 mode. When the system is placed in LPM3 mode, the SRAM
+//! banks specified with this function will be placed into retention mode. By
+//! default, retention of every SRAM bank except SYSCTL_SRAM_BANK0 (reserved) is
+//! disabled. Retention of individual banks can be set without the restrictions
+//! of the enable/disable functions.
+//!
+//! \param sramBank The SRAM banks to enable retention
+//!        Can be a bitwise OR of the following values:
+//!                 - \b SYSCTL_SRAM_BANK1,
+//!                 - \b SYSCTL_SRAM_BANK2,
+//!                 - \b SYSCTL_SRAM_BANK3,
+//!                 - \b SYSCTL_SRAM_BANK4,
+//!                 - \b SYSCTL_SRAM_BANK5,
+//!                 - \b SYSCTL_SRAM_BANK6,
+//!                 - \b SYSCTL_SRAM_BANK7
+//! \note  \b SYSCTL_SRAM_BANK0 is reserved and retention is always enabled.
+//!
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void SysCtl_enableSRAMBankRetention(uint_fast8_t sramBank);
+
+//*****************************************************************************
+//
+//! Disables retention of the specified SRAM bank register when the device goes
+//! into LPM3 mode. When the system is placed in LPM3 mode, the SRAM
+//! banks specified with this function will not be placed into retention mode.
+//! By default, retention of every SRAM bank except SYSCTL_SRAM_BANK0 (reserved)
+//! is disabled. Retention of individual banks can be set without the
+//! restrictions of the enable/disable SRAM bank functions.
+//!
+//! \param sramBank The SRAM banks to disable retention
+//!        Can be a bitwise OR of the following values:
+//!                 - \b SYSCTL_SRAM_BANK1,
+//!                 - \b SYSCTL_SRAM_BANK2,
+//!                 - \b SYSCTL_SRAM_BANK3,
+//!                 - \b SYSCTL_SRAM_BANK4,
+//!                 - \b SYSCTL_SRAM_BANK5,
+//!                 - \b SYSCTL_SRAM_BANK6,
+//!                 - \b SYSCTL_SRAM_BANK7
+//! \note  \b SYSCTL_SRAM_BANK0 is reserved and retention is always enabled.
+//!
+//! \return None.
+//
+//
+//*****************************************************************************
+extern void SysCtl_disableSRAMBankRetention(uint_fast8_t sramBank);
+
+//*****************************************************************************
+//
+//! Makes it so that the provided peripherals will either halt execution after
+//! a CPU HALT. Parameters in this function can be combined to account for
+//! multiple peripherals. By default, all peripherals keep running after a
+//! CPU HALT.
+//!
+//! \param devices The peripherals to continue running after a CPU HALT
+//!         This can be a bitwise OR of the following values:
+//!                 - \b SYSCTL_PERIPH_DMA,
+//!                 - \b SYSCTL_PERIPH_WDT,
+//!                 - \b SYSCTL_PERIPH_ADC,
+//!                 - \b SYSCTL_PERIPH_EUSCIB3,
+//!                 - \b SYSCTL_PERIPH_EUSCIB2,
+//!                 - \b SYSCTL_PERIPH_EUSCIB1
+//!                 - \b SYSCTL_PERIPH_EUSCIB0,
+//!                 - \b SYSCTL_PERIPH_EUSCIA3,
+//!                 - \b SYSCTL_PERIPH_EUSCIA2
+//!                 - \b SYSCTL_PERIPH_EUSCIA1,
+//!                 - \b SYSCTL_PERIPH_EUSCIA0,
+//!                 - \b SYSCTL_PERIPH_TIMER32_0_MODULE,
+//!                 - \b SYSCTL_PERIPH_TIMER16_3,
+//!                 - \b SYSCTL_PERIPH_TIMER16_2,
+//!                 - \b SYSCTL_PERIPH_TIMER16_1,
+//!                 - \b SYSCTL_PERIPH_TIMER16_0
+//!
+//! \return None.
+//
+//
+//*****************************************************************************
+extern void SysCtl_enablePeripheralAtCPUHalt(uint_fast16_t devices);
+
+//*****************************************************************************
+//
+//! Makes it so that the provided peripherals will either halt execution after
+//! a CPU HALT. Parameters in this function can be combined to account for
+//! multiple peripherals. By default, all peripherals keep running after a
+//! CPU HALT.
+//!
+//! \param devices The peripherals to disable after a CPU HALT
+//!
+//! The \e devices parameter can be a bitwise OR of the following values:
+//!         This can be a bitwise OR of the following values:
+//!                 - \b SYSCTL_PERIPH_DMA,
+//!                 - \b SYSCTL_PERIPH_WDT,
+//!                 - \b SYSCTL_PERIPH_ADC,
+//!                 - \b SYSCTL_PERIPH_EUSCIB3,
+//!                 - \b SYSCTL_PERIPH_EUSCIB2,
+//!                 - \b SYSCTL_PERIPH_EUSCIB1
+//!                 - \b SYSCTL_PERIPH_EUSCIB0,
+//!                 - \b SYSCTL_PERIPH_EUSCIA3,
+//!                 - \b SYSCTL_PERIPH_EUSCIA2
+//!                 - \b SYSCTL_PERIPH_EUSCIA1,
+//!                 - \b SYSCTL_PERIPH_EUSCIA0,
+//!                 - \b SYSCTL_PERIPH_TIMER32_0_MODULE,
+//!                 - \b SYSCTL_PERIPH_TIMER16_3,
+//!                 - \b SYSCTL_PERIPH_TIMER16_2,
+//!                 - \b SYSCTL_PERIPH_TIMER16_1,
+//!                 - \b SYSCTL_PERIPH_TIMER16_0
+//!
+//! \return None.
+//
+//
+//*****************************************************************************
+extern void SysCtl_disablePeripheralAtCPUHalt(uint_fast16_t devices);
+
+//*****************************************************************************
+//
+//! Sets the type of RESET that happens when a watchdog timeout occurs.
+//!
+//! \param resetType The type of reset to set
+//!
+//! The \e resetType parameter must be only one of the following values:
+//!         - \b SYSCTL_HARD_RESET,
+//!         - \b SYSCTL_SOFT_RESET
+//!
+//! \return None.
+//
+//
+//*****************************************************************************
+extern void SysCtl_setWDTTimeoutResetType(uint_fast8_t resetType);
+
+//*****************************************************************************
+//
+//! Sets the type of RESET that happens when a watchdog password violation
+//! occurs.
+//!
+//! \param resetType The type of reset to set
+//!
+//! The \e resetType parameter must be only one of the following values:
+//!         - \b SYSCTL_HARD_RESET,
+//!         - \b SYSCTL_SOFT_RESET
+//!
+//! \return None.
+//
+//
+//*****************************************************************************
+extern void SysCtl_setWDTPasswordViolationResetType(uint_fast8_t resetType);
+
+//*****************************************************************************
+//
+//! Disables NMIs for the provided modules. When disabled, a NMI flag will not
+//! occur when a fault condition comes from the corresponding modules.
+//!
+//! \param flags The NMI sources to disable
+//! Can be a bitwise OR of the following parameters:
+//!         - \b SYSCTL_NMIPIN_SRC,
+//!         - \b SYSCTL_PCM_SRC,
+//!         - \b SYSCTL_PSS_SRC,
+//!         - \b SYSCTL_CS_SRC
+//!
+//
+//*****************************************************************************
+extern void SysCtl_disableNMISource(uint_fast8_t flags);
+
+//*****************************************************************************
+//
+//! Enables NMIs for the provided modules. When enabled, a NMI flag will
+//! occur when a fault condition comes from the corresponding modules.
+//!
+//! \param flags The NMI sources to enable
+//! Can be a bitwise OR of the following parameters:
+//!         - \b SYSCTL_NMIPIN_SRC,
+//!         - \b SYSCTL_PCM_SRC,
+//!         - \b SYSCTL_PSS_SRC,
+//!         - \b SYSCTL_CS_SRC
+//!
+//
+//*****************************************************************************
+extern void SysCtl_enableNMISource(uint_fast8_t flags);
+
+//*****************************************************************************
+//
+//! Returns the current sources of NMIs that are enabled
+//!
+//! \return Bitwise OR of NMI flags that are enabled
+//
+//*****************************************************************************
+extern uint_fast8_t SysCtl_getNMISourceStatus(void);
+
+//*****************************************************************************
+//
+//! Enables glitch suppression on the reset pin of the device. Refer to the
+//! device data sheet for specific information about glitch suppression
+//!
+//! \return None.
+//
+//
+//*****************************************************************************
+extern void SysCtl_enableGlitchFilter(void);
+
+//*****************************************************************************
+//
+//! Disables glitch suppression on the reset pin of the device. Refer to the
+//! device data sheet for specific information about glitch suppression
+//!
+//! \return None.
+//
+//
+//*****************************************************************************
+extern void SysCtl_disableGlitchFilter(void);
+
+//*****************************************************************************
+//
+//! Retrieves the calibration constant of the temperature sensor to be used
+//! in temperature calculation.
+//!
+//! \param refVoltage Reference voltage being used.
+//!
+//! The \e resetType parameter must be only one of the following values:
+//!         - \b SYSCTL_1_2V_REF
+//!         - \b SYSCTL_1_45V_REF
+//!         - \b SYSCTL_2_5V_REF
+//!
+//! \param temperature is the calibration temperature that the user wants to be
+//!     returned.
+//!
+//! The \e temperature parameter must be only one of the following values:
+//!         - \b SYSCTL_30_DEGREES_C
+//!         - \b SYSCTL_85_DEGREES_C
+//!
+//! \return None.
+//
+//
+//*****************************************************************************
+extern uint_fast16_t SysCtl_getTempCalibrationConstant(uint32_t refVoltage,
+        uint32_t temperature);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif // __SYSCTL_H__
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/systick.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/systick.c
new file mode 100644
index 000000000..519baae73
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/systick.c
@@ -0,0 +1,118 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#include <debug.h>
+#include <interrupt.h>
+#include <systick.h>
+
+void SysTick_enableModule(void)
+{
+    //
+    // Enable SysTick.
+    //
+    SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
+}
+
+void SysTick_disableModule(void)
+{
+    //
+    // Disable SysTick.
+    //
+    SysTick->CTRL &= ~(SysTick_CTRL_ENABLE_Msk);
+}
+
+void SysTick_registerInterrupt(void (*intHandler)(void))
+{
+    //
+    // Register the interrupt handler, returning an error if an error occurs.
+    //
+    Interrupt_registerInterrupt(FAULT_SYSTICK, intHandler);
+
+}
+
+void SysTick_unregisterInterrupt(void)
+{
+
+    //
+    // Unregister the interrupt handler.
+    //
+    Interrupt_unregisterInterrupt(FAULT_SYSTICK);
+}
+
+void SysTick_enableInterrupt(void)
+{
+    //
+    // Enable the SysTick interrupt.
+    //
+    SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
+}
+
+void SysTick_disableInterrupt(void)
+{
+    //
+    // Disable the SysTick interrupt.
+    //
+    SysTick->CTRL &= ~(SysTick_CTRL_TICKINT_Msk);
+}
+
+void SysTick_setPeriod(uint32_t period)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((period > 0) && (period <= 16777216));
+
+    //
+    // Set the period of the SysTick counter.
+    //
+    SysTick->LOAD = period - 1;
+}
+
+uint32_t SysTick_getPeriod(void)
+{
+    //
+    // Return the period of the SysTick counter.
+    //
+    return (SysTick->LOAD + 1);
+}
+
+uint32_t SysTick_getValue(void)
+{
+    //
+    // Return the current value of the SysTick counter.
+    //
+    return (SysTick->VAL);
+}
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/systick.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/systick.h
new file mode 100644
index 000000000..d18c8eab2
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/systick.h
@@ -0,0 +1,219 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __SYSTICK_H__
+#define __SYSTICK_H__
+
+//*****************************************************************************
+//
+//! \addtogroup systick_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+#include <stdint.h>
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! Enables the SysTick counter.
+//!
+//! This function starts the SysTick counter.  If an interrupt handler has been
+//! registered, it is called when the SysTick counter rolls over.
+//!
+//! \note Calling this function causes the SysTick counter to (re)commence
+//! counting from its current value.  The counter is not automatically reloaded
+//! with the period as specified in a previous call to SysTick_setPeriod().  If
+//! an immediate reload is required, the \b NVIC_ST_CURRENT register must be
+//! written to force the reload.  Any write to this register clears the SysTick
+//! counter to 0 and causes a reload with the supplied period on the next
+//! clock.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void SysTick_enableModule(void);
+
+//*****************************************************************************
+//
+//! Disables the SysTick counter.
+//!
+//! This function stops the SysTick counter.  If an interrupt handler has been
+//! registered, it is not called until SysTick is restarted.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void SysTick_disableModule(void);
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the SysTick interrupt.
+//!
+//! \param intHandler is a pointer to the function to be called when the
+//! SysTick interrupt occurs.
+//!
+//! This function registers the handler to be called when a SysTick interrupt
+//! occurs.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void SysTick_registerInterrupt(void (*intHandler)(void));
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the SysTick interrupt.
+//!
+//! This function unregisters the handler to be called when a SysTick interrupt
+//! occurs.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void SysTick_unregisterInterrupt(void);
+
+//*****************************************************************************
+//
+//! Enables the SysTick interrupt.
+//!
+//! This function enables the SysTick interrupt, allowing it to be
+//! reflected to the processor.
+//!
+//! \note The SysTick interrupt handler is not required to clear the SysTick
+//! interrupt source because it is cleared automatically by the NVIC when the
+//! interrupt handler is called.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void SysTick_enableInterrupt(void);
+
+//*****************************************************************************
+//
+//! Disables the SysTick interrupt.
+//!
+//! This function disables the SysTick interrupt, preventing it from being
+//! reflected to the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void SysTick_disableInterrupt(void);
+
+//*****************************************************************************
+//
+//! Sets the period of the SysTick counter.
+//!
+//! \param period is the number of clock ticks in each period of the SysTick
+//! counter and must be between 1 and 16,777,216, inclusive.
+//!
+//! This function sets the rate at which the SysTick counter wraps, which
+//! equates to the number of processor clocks between interrupts.
+//!
+//! \note Calling this function does not cause the SysTick counter to reload
+//! immediately.  If an immediate reload is required, the \b NVIC_ST_CURRENT
+//! register must be written.  Any write to this register clears the SysTick
+//! counter to 0 and causes a reload with the \e period supplied here on
+//! the next clock after SysTick is enabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void SysTick_setPeriod(uint32_t period);
+
+//*****************************************************************************
+//
+//! Gets the period of the SysTick counter.
+//!
+//! This function returns the rate at which the SysTick counter wraps, which
+//! equates to the number of processor clocks between interrupts.
+//!
+//! \return Returns the period of the SysTick counter.
+//
+//*****************************************************************************
+extern uint32_t SysTick_getPeriod(void);
+
+//*****************************************************************************
+//
+//! Gets the current value of the SysTick counter.
+//!
+//! This function returns the current value of the SysTick counter, which is
+//! a value between the period - 1 and zero, inclusive.
+//!
+//! \return Returns the current value of the SysTick counter.
+//
+//*****************************************************************************
+extern uint32_t SysTick_getValue(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif // __SYSTICK_H__
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer32.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer32.c
new file mode 100644
index 000000000..437786708
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer32.c
@@ -0,0 +1,148 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#include <timer32.h>
+#include <interrupt.h>
+#include <debug.h>
+
+void Timer32_initModule(uint32_t timer, uint32_t preScaler, uint32_t resolution,
+        uint32_t mode)
+{
+    /* Setting up one shot or continuous mode */
+    if (mode == TIMER32_PERIODIC_MODE)
+        HWREGBIT8(timer + OFS_TIMER32_CONTROL1, TIMER32_CONTROL1_MODE_OFS) = 1;
+    else if (mode == TIMER32_FREE_RUN_MODE)
+        HWREGBIT8(timer + OFS_TIMER32_CONTROL1, TIMER32_CONTROL1_MODE_OFS) = 0;
+    else
+        ASSERT(false);
+
+    /* Setting the resolution of the timer */
+    if (resolution == TIMER32_1_MODULE6BIT)
+        HWREGBIT8(timer + OFS_TIMER32_CONTROL1, TIMER32_CONTROL1_SIZE_OFS) = 0;
+    else if (resolution == TIMER32_32BIT)
+        HWREGBIT8(timer + OFS_TIMER32_CONTROL1, TIMER32_CONTROL1_SIZE_OFS) = 1;
+    else
+        ASSERT(false);
+
+    /* Setting the PreScaler */
+    ASSERT(
+            resolution == TIMER32_PRESCALER_1
+            || resolution == TIMER32_PRESCALER_16
+            || resolution == TIMER32_PRESCALER_256);
+
+    HWREG32(timer + OFS_TIMER32_CONTROL1) =
+            (HWREG32(timer + OFS_TIMER32_CONTROL1)
+                    & ~TIMER32_CONTROL1_PRESCALE_M) | preScaler;
+
+}
+
+void Timer32_setCount(uint32_t timer, uint32_t count)
+{
+    if (!HWREGBIT32(timer + OFS_TIMER32_CONTROL1,
+            TIMER32_CONTROL1_SIZE_OFS) && (count > UINT16_MAX))
+        HWREG32(timer + OFS_TIMER32_LOAD1) = UINT16_MAX;
+    else
+        HWREG32(timer + OFS_TIMER32_LOAD1) = count;
+}
+
+void Timer32_setCountInBackground(uint32_t timer, uint32_t count)
+{
+    if (!HWREGBIT32(timer + OFS_TIMER32_CONTROL1,
+            TIMER32_CONTROL1_SIZE_OFS) && (count > UINT16_MAX))
+        HWREG32(timer + OFS_TIMER32_BGLOAD1) = UINT16_MAX;
+    else
+        HWREG32(timer + OFS_TIMER32_BGLOAD1) = count;
+}
+
+uint32_t Timer32_getValue(uint32_t timer)
+{
+    return HWREG32(timer + OFS_TIMER32_VALUE1);
+}
+
+void Timer32_startTimer(uint32_t timer, bool oneShot)
+{
+    ASSERT(timer == TIMER32_0_MODULE || timer == TIMER32_1_MODULE);
+
+    if (oneShot)
+        HWREGBIT8(timer + OFS_TIMER32_CONTROL1, TIMER32_CONTROL1_ONESHOT_OFS) =
+                1;
+    else
+        HWREGBIT8(timer + OFS_TIMER32_CONTROL1, TIMER32_CONTROL1_ONESHOT_OFS) =
+                0;
+
+    HWREG32(timer + OFS_TIMER32_CONTROL1) |= TIMER32_CONTROL1_ENABLE;
+}
+
+void Timer32_haltTimer(uint32_t timer)
+{
+    ASSERT(timer == TIMER32_0_MODULE || timer == TIMER32_1_MODULE);
+
+    HWREG32(timer + OFS_TIMER32_CONTROL1) &= ~TIMER32_CONTROL1_ENABLE;
+}
+
+void Timer32_enableInterrupt(uint32_t timer)
+{
+    HWREG32(timer + OFS_TIMER32_CONTROL1) |= TIMER32_CONTROL1_IE;
+}
+
+void Timer32_disableInterrupt(uint32_t timer)
+{
+    HWREG32(timer + OFS_TIMER32_CONTROL1) &= ~TIMER32_CONTROL1_IE;
+}
+
+void Timer32_clearInterruptFlag(uint32_t timer)
+{
+    HWREG32(timer + OFS_TIMER32_INTCLR1) |= 0x01;
+}
+
+uint32_t Timer32_getInterruptStatus(uint32_t timer)
+{
+    return HWREG32(timer + OFS_TIMER32_MIS1);
+}
+
+void Timer32_registerInterrupt(uint32_t timerInterrupt,
+        void (*intHandler)(void))
+{
+    Interrupt_registerInterrupt(timerInterrupt, intHandler);
+    Interrupt_enableInterrupt(timerInterrupt);
+}
+
+void Timer32_unregisterInterrupt(uint32_t timerInterrupt)
+{
+    Interrupt_disableInterrupt(timerInterrupt);
+    Interrupt_unregisterInterrupt(timerInterrupt);
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer32.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer32.h
new file mode 100644
index 000000000..4fdd0fbd9
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer32.h
@@ -0,0 +1,359 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef TIMER32_H_
+#define TIMER32_H_
+
+//*****************************************************************************
+//
+//! \addtogroup timer32_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+#include <stdint.h>
+#include <stdbool.h>
+#include <msp.h>
+
+//*****************************************************************************
+//
+// Control specific variables
+//
+//*****************************************************************************
+#define TIMER_OFFSET    0x020
+
+#define TIMER32_0_MODULE   TIMER32_BASE
+#define TIMER32_1_MODULE   (TIMER32_BASE + OFS_TIMER32_LOAD2)
+
+#define TIMER32_0_INTERRUPT         INT_T32_INT1
+#define TIMER32_1_INTERRUPT         INT_T32_INT2
+#define TIMER32_COMBINED_INTERRUPT  INT_T32_INTC
+
+#define TIMER32_1_MODULE6BIT           0x00
+#define TIMER32_32BIT           0x01
+
+#define TIMER32_PRESCALER_1      0x00
+#define TIMER32_PRESCALER_16     0x04
+#define TIMER32_PRESCALER_256    0x08
+
+#define TIMER32_FREE_RUN_MODE   0x00
+#define TIMER32_PERIODIC_MODE   0x01
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! Initializes the Timer32 module
+//!
+//! \param timer is the instance of the Timer32 module.
+//! Valid parameters must be one of the following values:
+//!         - \b TIMER32_0_MODULE
+//!         - \b TIMER32_1_MODULE
+//!
+//! \param preScaler is the prescaler (or divider) to apply to the clock
+//! source given to the Timer32 module.
+//!         Valid values are
+//!         - \b TIMER32_PRESCALER_1 [DEFAULT]
+//!         - \b TIMER32_PRESCALER_16
+//!         - \b TIMER32_PRESCALER_256
+//! \param resolution is the bit resolution of the Timer32 module.
+//!         Valid values are
+//!         - \b TIMER32_1_MODULE6BIT [DEFAULT]
+//!         - \b TIMER32_32BIT
+//! \param mode selects between free run and periodic mode. In free run
+//! mode, the value of the timer is reset to UINT16_MAX (for 16-bit mode) or
+//! UINT32_MAX (for 16-bit mode) when the timer reaches zero. In periodic mode,
+//! the timer is reset to the value set by the Timer32_setCount function.
+//!         Valid values are
+//!         - \b TIMER32_FREE_RUN_MODE [DEFAULT]
+//!         - \b TIMER32_PERIODIC_MODE
+//!
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void Timer32_initModule(uint32_t timer, uint32_t preScaler,
+        uint32_t resolution, uint32_t mode);
+
+//*****************************************************************************
+//
+//! Sets the count of the timer and resets the current value to the value
+//! passed. This value is set on the next rising edge of the clock provided to
+//! the timer module
+//!
+//! \param timer is the instance of the Timer32 module.
+//! Valid parameters must be one of the following values:
+//!         - \b TIMER32_0_MODULE
+//!         - \b TIMER32_1_MODULE
+//! \param count Value of the timer to set. Note that
+//! if the timer is in 16-bit mode and a value is passed in that exceeds
+//! UINT16_MAX, the value will be truncated to UINT16_MAX.
+//!
+//! Also note that if the timer is operating in periodic mode, the value passed
+//! into this function will represent the new period of the timer (the value
+//! which is reloaded into the timer each time it reaches a zero value).
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void Timer32_setCount(uint32_t timer, uint32_t count);
+
+//*****************************************************************************
+//
+//! Sets the count of the timer without resetting the current value. When the
+//! current value of the timer reaches zero, the value passed into this function
+//! will be set as the new count value.
+//!
+//! \param timer is the instance of the Timer32 module.
+//! Valid parameters must be one of the following values:
+//!         - \b TIMER32_0_MODULE
+//!         - \b TIMER32_1_MODULE
+//! \param count Value of the timer to set in the background. Note that
+//! if the timer is in 16-bit mode and a value is passed in that exceeds
+//! UINT16_MAX, the value will be truncated to UINT16_MAX.
+//!
+//! Also note that if the timer is operating in periodic mode, the value passed
+//! into this function will represent the new period of the timer (the value
+//! which is reloaded into the timer each time it reaches a zero value).
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void Timer32_setCountInBackground(uint32_t timer, uint32_t count);
+
+//*****************************************************************************
+//
+//! Returns the current value of the timer.
+//!
+//! \param timer is the instance of the Timer32 module.
+//! Valid parameters must be one of the following values:
+//!         - \b TIMER32_0_MODULE
+//!         - \b TIMER32_1_MODULE
+//!
+//! \return The current count of the timer.
+//
+//*****************************************************************************
+extern uint32_t Timer32_getValue(uint32_t timer);
+
+//*****************************************************************************
+//
+//! Starts the timer. The Timer32_initModule function should be called (in
+//! conjunction with Timer32_setCount if periodic mode is desired) prior to
+//  starting the timer.
+//!
+//! \param timer is the instance of the Timer32 module.
+//! Valid parameters must be one of the following values:
+//!         - \b TIMER32_0_MODULE
+//!         - \b TIMER32_1_MODULE
+//!
+//! \param oneShot sets whether the Timer32 module operates in one shot
+//!  or continuous mode. In one shot mode, the timer will halt when a zero is
+//!  reached and stay halted until either:
+//!         - The user calls the Timer32PeriodSet function
+//!         - The Timer32_initModule is called to reinitialize the timer with one-shot
+//!             mode disabled.
+//!
+//! A true value will cause the timer to operate in one shot mode while a false
+//! value will cause the timer to operate in continuous mode
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void Timer32_startTimer(uint32_t timer, bool oneShot);
+
+//*****************************************************************************
+//
+//! Halts the timer. Current count and setting values are preserved.
+//!
+//! \param timer is the instance of the Timer32 module.
+//! Valid parameters must be one of the following values:
+//!         - \b TIMER32_0_MODULE
+//!         - \b TIMER32_1_MODULE
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void Timer32_haltTimer(uint32_t timer);
+
+//*****************************************************************************
+//
+//! Enables a Timer32 interrupt source.
+//!
+//! \param timer is the instance of the Timer32 module.
+//! Valid parameters must be one of the following values:
+//!         - \b TIMER32_0_MODULE
+//!         - \b TIMER32_1_MODULE
+//!
+//! Enables the indicated Timer32 interrupt source.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void Timer32_enableInterrupt(uint32_t timer);
+
+//*****************************************************************************
+//
+//! Disables a Timer32 interrupt source.
+//!
+//! \param timer is the instance of the Timer32 module.
+//! Valid parameters must be one of the following values:
+//!         - \b TIMER32_0_MODULE
+//!         - \b TIMER32_1_MODULE
+//!
+//! Disables the indicated Timer32 interrupt source.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void Timer32_disableInterrupt(uint32_t timer);
+
+//*****************************************************************************
+//
+//! Clears Timer32 interrupt source.
+//!
+//! \param timer is the instance of the Timer32 module.
+//! Valid parameters must be one of the following values:
+//!         - \b TIMER32_0_MODULE
+//!         - \b TIMER32_1_MODULE
+//!
+//! The Timer32 interrupt source is cleared, so that it no longer asserts.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void Timer32_clearInterruptFlag(uint32_t timer);
+
+//*****************************************************************************
+//
+//! Gets the current Timer32 interrupt status.
+//!
+//! \param timer is the instance of the Timer32 module.
+//! Valid parameters must be one of the following values:
+//!         - \b TIMER32_0_MODULE
+//!         - \b TIMER32_1_MODULE
+//!
+//! This returns the interrupt status for the Timer32 module. A positive value
+//! will indicate that an interrupt is pending while a zero value will indicate
+//! that no interrupt is pending.
+//!
+//! \return The current interrupt status
+//
+//*****************************************************************************
+extern uint32_t Timer32_getInterruptStatus(uint32_t timer);
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for Timer32 interrupts.
+//!
+//! \param timerInterrupt is the specific interrupt to register. For the
+//! Timer32 module, there are a total of three different interrupts: one
+//! interrupt for each two Timer32 modules, and a "combined" interrupt which
+//! is a logical OR of each individual Timer32 interrupt.
+//!         - \b TIMER32_0_INTERRUPT
+//!         - \b TIMER32_1_INTERRUPT
+//!         - \b TIMER32_COMBINED_INTERRUPT
+//!
+//! \param intHandler is a pointer to the function to be called when the
+//! Timer32 interrupt occurs.
+//!
+//! This function registers the handler to be called when an Timer32
+//! interrupt occurs. This function enables the global interrupt in the
+//! interrupt controller; specific Timer32 interrupts must be enabled
+//! via Timer32_enableInterrupt().  It is the interrupt handler's
+//! responsibility to clear the interrupt source
+//! via Timer32_clearInterruptFlag().
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void Timer32_registerInterrupt(uint32_t timerInterrupt,
+        void (*intHandler)(void));
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the Timer32 interrupt.
+//!
+//! \param timerInterrupt is the specific interrupt to register. For the
+//! Timer32 module, there are a total of three different interrupts: one
+//! interrupt for each two Timer32 modules, and a "combined" interrupt which
+//! is a logical OR of each individual Timer32 interrupt.
+//!         - \b TIMER32_0_INTERRUPT
+//!         - \b TIMER32_1_INTERRUPT
+//!         - \b TIMER32_COMBINED_INTERRUPT
+//!
+//! This function unregisters the handler to be called when a Timer32
+//! interrupt occurs.  This function also masks off the interrupt in the
+//! interrupt controller so that the interrupt handler no longer is called.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void Timer32_unregisterInterrupt(uint32_t timerInterrupt);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif /* TIMER32_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer_a.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer_a.c
new file mode 100644
index 000000000..d8ec5bb42
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer_a.c
@@ -0,0 +1,796 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#include <timer_a.h>
+#include <interrupt.h>
+#include <debug.h>
+
+static void privateTimer_AProcessClockSourceDivider(uint32_t timer,
+        uint16_t clockSourceDivider)
+{
+    TIMER_A_CMSIS(timer)->rCTL.r &= ~ID__8;
+    TIMER_A_CMSIS(timer)->rEX0.r &= ~TAIDEX_7;
+
+    switch (clockSourceDivider)
+    {
+    case TIMER_A_CLOCKSOURCE_DIVIDER_1:
+    case TIMER_A_CLOCKSOURCE_DIVIDER_2:
+        TIMER_A_CMSIS(timer)->rCTL.r |= ((clockSourceDivider - 1) << 6);
+        TIMER_A_CMSIS(timer)->rEX0.r = TAIDEX_0;
+        break;
+    case TIMER_A_CLOCKSOURCE_DIVIDER_4:
+        TIMER_A_CMSIS(timer)->rCTL.r |= ID__4;
+        TIMER_A_CMSIS(timer)->rEX0.r = TAIDEX_0;
+        break;
+    case TIMER_A_CLOCKSOURCE_DIVIDER_8:
+        TIMER_A_CMSIS(timer)->rCTL.r |= ID__8;
+        TIMER_A_CMSIS(timer)->rEX0.r = TAIDEX_0;
+        break;
+    case TIMER_A_CLOCKSOURCE_DIVIDER_3:
+    case TIMER_A_CLOCKSOURCE_DIVIDER_5:
+    case TIMER_A_CLOCKSOURCE_DIVIDER_6:
+    case TIMER_A_CLOCKSOURCE_DIVIDER_7:
+        TIMER_A_CMSIS(timer)->rCTL.r |= ID__1;
+        TIMER_A_CMSIS(timer)->rEX0.r = (clockSourceDivider - 1);
+        break;
+
+    case TIMER_A_CLOCKSOURCE_DIVIDER_10:
+    case TIMER_A_CLOCKSOURCE_DIVIDER_12:
+    case TIMER_A_CLOCKSOURCE_DIVIDER_14:
+    case TIMER_A_CLOCKSOURCE_DIVIDER_16:
+        TIMER_A_CMSIS(timer)->rCTL.r |= ID__2;
+        TIMER_A_CMSIS(timer)->rEX0.r = (clockSourceDivider / 2 - 1);
+        break;
+
+    case TIMER_A_CLOCKSOURCE_DIVIDER_20:
+    case TIMER_A_CLOCKSOURCE_DIVIDER_24:
+    case TIMER_A_CLOCKSOURCE_DIVIDER_28:
+    case TIMER_A_CLOCKSOURCE_DIVIDER_32:
+        TIMER_A_CMSIS(timer)->rCTL.r |= ID__4;
+        TIMER_A_CMSIS(timer)->rEX0.r = (clockSourceDivider / 4 - 1);
+        break;
+    case TIMER_A_CLOCKSOURCE_DIVIDER_40:
+    case TIMER_A_CLOCKSOURCE_DIVIDER_48:
+    case TIMER_A_CLOCKSOURCE_DIVIDER_56:
+    case TIMER_A_CLOCKSOURCE_DIVIDER_64:
+        TIMER_A_CMSIS(timer)->rCTL.r |= ID__8;
+        TIMER_A_CMSIS(timer)->rEX0.r = (clockSourceDivider / 8 - 1);
+        break;
+    }
+}
+
+void Timer_A_startCounter(uint32_t timer, uint_fast16_t timerMode)
+{
+    ASSERT(
+            (TIMER_A_UPDOWN_MODE == timerMode)
+            || (TIMER_A_CONTINUOUS_MODE == timerMode)
+            || (TIMER_A_UP_MODE == timerMode));
+
+    TIMER_A_CMSIS(timer)->rCTL.r |= timerMode;
+}
+
+void Timer_A_configureContinuousMode(uint32_t timer,
+        const Timer_A_ContinuousModeConfig *config)
+{
+    ASSERT(
+            (TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK == config->clockSource)
+            || (TIMER_A_CLOCKSOURCE_ACLK == config->clockSource)
+            || (TIMER_A_CLOCKSOURCE_SMCLK == config->clockSource)
+            || (TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK
+                    == config->clockSource));
+
+    ASSERT(
+            (TIMER_A_DO_CLEAR == config->timerClear)
+            || (TIMER_A_SKIP_CLEAR == config->timerClear));
+
+    ASSERT(
+            (TIMER_A_TAIE_INTERRUPT_ENABLE == config->timerInterruptEnable_TAIE)
+            || (TIMER_A_TAIE_INTERRUPT_DISABLE
+                    == config->timerInterruptEnable_TAIE));
+
+    ASSERT(
+            (TIMER_A_CLOCKSOURCE_DIVIDER_1 == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_2
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_4
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_8
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_3
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_5
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_6
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_7
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_10
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_12
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_14
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_16
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_20
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_24
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_28
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_32
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_40
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_48
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_56
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_64
+                    == config->clockSourceDivider));
+
+    privateTimer_AProcessClockSourceDivider(timer, config->clockSourceDivider);
+
+    TIMER_A_CMSIS(timer)->rCTL.r = (TIMER_A_CMSIS(timer)->rCTL.r
+            & ~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK
+                    + TIMER_A_UPDOWN_MODE + TIMER_A_DO_CLEAR
+                    + TIMER_A_TAIE_INTERRUPT_ENABLE))
+            | (config->clockSource + config->timerClear
+                    + config->timerInterruptEnable_TAIE);
+}
+
+void Timer_A_configureUpMode(uint32_t timer, const Timer_A_UpModeConfig *config)
+{
+    ASSERT(
+            (TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK == config->clockSource)
+            || (TIMER_A_CLOCKSOURCE_ACLK == config->clockSource)
+            || (TIMER_A_CLOCKSOURCE_SMCLK == config->clockSource)
+            || (TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK
+                    == config->clockSource));
+
+    ASSERT(
+            (TIMER_A_DO_CLEAR == config->timerClear)
+            || (TIMER_A_SKIP_CLEAR == config->timerClear));
+
+    ASSERT(
+            (TIMER_A_DO_CLEAR == config->timerClear)
+            || (TIMER_A_SKIP_CLEAR == config->timerClear));
+
+    privateTimer_AProcessClockSourceDivider(timer, config->clockSourceDivider);
+
+    TIMER_A_CMSIS(timer)->rCTL.r &=
+            ~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + TIMER_A_UPDOWN_MODE
+                    + TIMER_A_DO_CLEAR + TIMER_A_TAIE_INTERRUPT_ENABLE);
+
+    TIMER_A_CMSIS(timer)->rCTL.r |= (config->clockSource + config->timerClear
+            + config->timerInterruptEnable_TAIE);
+
+    if (TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE
+            == config->captureCompareInterruptEnable_CCR0_CCIE)
+        BITBAND_PERI(TIMER_A_CMSIS(timer)->rCCTL0.r,CCIE_OFS) = 1;
+    else
+        BITBAND_PERI(TIMER_A_CMSIS(timer)->rCCTL0.r,CCIE_OFS) = 0;
+
+    TIMER_A_CMSIS(timer)->rCCR0 = config->timerPeriod;
+}
+
+void Timer_A_configureUpDownMode(uint32_t timer,
+        const Timer_A_UpDownModeConfig *config)
+{
+    ASSERT(
+            (TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK == config->clockSource)
+            || (TIMER_A_CLOCKSOURCE_ACLK == config->clockSource)
+            || (TIMER_A_CLOCKSOURCE_SMCLK == config->clockSource)
+            || (TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK
+                    == config->clockSource));
+
+    ASSERT(
+            (TIMER_A_DO_CLEAR == config->timerClear)
+            || (TIMER_A_SKIP_CLEAR == config->timerClear));
+
+    ASSERT(
+            (TIMER_A_DO_CLEAR == config->timerClear)
+            || (TIMER_A_SKIP_CLEAR == config->timerClear));
+
+    privateTimer_AProcessClockSourceDivider(timer, config->clockSourceDivider);
+
+    TIMER_A_CMSIS(timer)->rCTL.r &=
+            ~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + TIMER_A_UPDOWN_MODE
+                    + TIMER_A_DO_CLEAR + TIMER_A_TAIE_INTERRUPT_ENABLE);
+
+    TIMER_A_CMSIS(timer)->rCTL.r |= (config->clockSource + TIMER_A_STOP_MODE
+            + config->timerClear + config->timerInterruptEnable_TAIE);
+    if (TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE
+            == config->captureCompareInterruptEnable_CCR0_CCIE)
+        BITBAND_PERI(TIMER_A_CMSIS(timer)->rCCTL0.r,CCIE_OFS) = 1;
+    else
+        BITBAND_PERI(TIMER_A_CMSIS(timer)->rCCTL0.r,CCIE_OFS) = 0;
+
+    TIMER_A_CMSIS(timer)->rCCR0 = config->timerPeriod;
+}
+
+void Timer_A_initCapture(uint32_t timer,
+        const Timer_A_CaptureModeConfig *config)
+{
+    ASSERT(
+            (TIMER_A_CAPTURECOMPARE_REGISTER_0 == config->captureRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_1
+                    == config->captureRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_2
+                    == config->captureRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_3
+                    == config->captureRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_4
+                    == config->captureRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_5
+                    == config->captureRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_6
+                    == config->captureRegister));
+
+    ASSERT(
+            (TIMER_A_CAPTUREMODE_NO_CAPTURE == config->captureMode)
+            || (TIMER_A_CAPTUREMODE_RISING_EDGE == config->captureMode)
+            || (TIMER_A_CAPTUREMODE_FALLING_EDGE == config->captureMode)
+            || (TIMER_A_CAPTUREMODE_RISING_AND_FALLING_EDGE
+                    == config->captureMode));
+
+    ASSERT(
+            (TIMER_A_CAPTURE_INPUTSELECT_CCIxA == config->captureInputSelect)
+            || (TIMER_A_CAPTURE_INPUTSELECT_CCIxB
+                    == config->captureInputSelect)
+            || (TIMER_A_CAPTURE_INPUTSELECT_GND
+                    == config->captureInputSelect)
+            || (TIMER_A_CAPTURE_INPUTSELECT_Vcc
+                    == config->captureInputSelect));
+
+    ASSERT(
+            (TIMER_A_CAPTURE_ASYNCHRONOUS == config->synchronizeCaptureSource)
+            || (TIMER_A_CAPTURE_SYNCHRONOUS
+                    == config->synchronizeCaptureSource));
+
+    ASSERT(
+            (TIMER_A_CAPTURECOMPARE_INTERRUPT_DISABLE
+                    == config->captureInterruptEnable)
+            || (TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE
+                    == config->captureInterruptEnable));
+
+    ASSERT(
+            (TIMER_A_OUTPUTMODE_OUTBITVALUE == config->captureOutputMode)
+            || (TIMER_A_OUTPUTMODE_SET == config->captureOutputMode)
+            || (TIMER_A_OUTPUTMODE_TOGGLE_RESET
+                    == config->captureOutputMode)
+            || (TIMER_A_OUTPUTMODE_SET_RESET
+                    == config->captureOutputMode)
+            || (TIMER_A_OUTPUTMODE_TOGGLE == config->captureOutputMode)
+            || (TIMER_A_OUTPUTMODE_RESET == config->captureOutputMode)
+            || (TIMER_A_OUTPUTMODE_TOGGLE_SET
+                    == config->captureOutputMode)
+            || (TIMER_A_OUTPUTMODE_RESET_SET
+                    == config->captureOutputMode));
+
+    if (TIMER_A_CAPTURECOMPARE_REGISTER_0 == config->captureRegister)
+    {
+        //CaptureCompare register 0 only supports certain modes
+        ASSERT(
+                (TIMER_A_OUTPUTMODE_OUTBITVALUE == config->captureOutputMode)
+                || (TIMER_A_OUTPUTMODE_SET == config->captureOutputMode)
+                || (TIMER_A_OUTPUTMODE_TOGGLE
+                        == config->captureOutputMode)
+                || (TIMER_A_OUTPUTMODE_RESET
+                        == config->captureOutputMode));
+    }
+
+    HWREG16(timer + config->captureRegister) =
+            (HWREG16(timer + config->captureRegister)
+                    & ~(TIMER_A_CAPTUREMODE_RISING_AND_FALLING_EDGE
+                            | TIMER_A_CAPTURE_INPUTSELECT_Vcc
+                            | TIMER_A_CAPTURE_SYNCHRONOUS | TIMER_A_DO_CLEAR
+                            | TIMER_A_TAIE_INTERRUPT_ENABLE | CM_3))
+                    | (config->captureMode | config->captureInputSelect
+                            | config->synchronizeCaptureSource
+                            | config->captureInterruptEnable
+                            | config->captureOutputMode | CAP);
+}
+
+void Timer_A_initCompare(uint32_t timer,
+        const Timer_A_CompareModeConfig *config)
+{
+    ASSERT(
+            (TIMER_A_CAPTURECOMPARE_REGISTER_0 == config->compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_1
+                    == config->compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_2
+                    == config->compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_3
+                    == config->compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_4
+                    == config->compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_5
+                    == config->compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_6
+                    == config->compareRegister));
+
+    ASSERT(
+            (TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE
+                    == config->compareInterruptEnable)
+            || (TIMER_A_CAPTURECOMPARE_INTERRUPT_DISABLE
+                    == config->compareInterruptEnable));
+
+    ASSERT(
+            (TIMER_A_OUTPUTMODE_OUTBITVALUE == config->compareOutputMode)
+            || (TIMER_A_OUTPUTMODE_SET == config->compareOutputMode)
+            || (TIMER_A_OUTPUTMODE_TOGGLE_RESET
+                    == config->compareOutputMode)
+            || (TIMER_A_OUTPUTMODE_SET_RESET
+                    == config->compareOutputMode)
+            || (TIMER_A_OUTPUTMODE_TOGGLE == config->compareOutputMode)
+            || (TIMER_A_OUTPUTMODE_RESET == config->compareOutputMode)
+            || (TIMER_A_OUTPUTMODE_TOGGLE_SET
+                    == config->compareOutputMode)
+            || (TIMER_A_OUTPUTMODE_RESET_SET
+                    == config->compareOutputMode));
+
+    if (TIMER_A_CAPTURECOMPARE_REGISTER_0 == config->compareRegister)
+    {
+        //CaptureCompare register 0 only supports certain modes
+        ASSERT(
+                (TIMER_A_OUTPUTMODE_OUTBITVALUE == config->compareOutputMode)
+                || (TIMER_A_OUTPUTMODE_SET == config->compareOutputMode)
+                || (TIMER_A_OUTPUTMODE_TOGGLE
+                        == config->compareOutputMode)
+                || (TIMER_A_OUTPUTMODE_RESET
+                        == config->compareOutputMode));
+    }
+
+    HWREG16(timer + config->compareRegister) =
+            (HWREG16(timer + config->compareRegister)
+                    & ~(TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE
+                            | TIMER_A_OUTPUTMODE_RESET_SET | CAP))
+                    | (config->compareInterruptEnable
+                            + config->compareOutputMode);
+
+    HWREG16(timer + config->compareRegister + OFS_TA0R) = config->compareValue;
+}
+
+uint16_t Timer_A_getCounterValue(uint32_t timer)
+{
+    uint16_t voteOne, voteTwo, res;
+
+    voteTwo = TIMER_A_CMSIS(timer)->rR;
+
+    do
+    {
+        voteOne = voteTwo;
+        voteTwo = TIMER_A_CMSIS(timer)->rR;
+
+        if (voteTwo > voteOne)
+            res = voteTwo - voteOne;
+        else if (voteOne > voteTwo)
+            res = voteOne - voteTwo;
+        else
+            res = 0;
+
+    } while (res > TIMER_A_THRESHOLD);
+
+    return voteTwo;
+
+}
+
+void Timer_A_clearTimer(uint32_t timer)
+{
+    BITBAND_PERI(TIMER_A_CMSIS(timer)->rCTL.r , TACLR_OFS) = 1;
+}
+
+uint_fast8_t Timer_A_getSynchronizedCaptureCompareInput(uint32_t timer,
+        uint_fast16_t captureCompareRegister, uint_fast16_t synchronizedSetting)
+{
+    ASSERT(
+            (TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_1
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_2
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_3
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_4
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_5
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_6
+                    == captureCompareRegister));
+
+    ASSERT(
+            (TIMER_A_READ_CAPTURE_COMPARE_INPUT == synchronizedSetting)
+            || (TIMER_A_READ_SYNCHRONIZED_CAPTURECOMPAREINPUT
+                    == synchronizedSetting));
+
+    if (HWREG16(timer + captureCompareRegister) & synchronizedSetting)
+        return TIMER_A_CAPTURECOMPARE_INPUT_HIGH;
+    else
+        return TIMER_A_CAPTURECOMPARE_INPUT_LOW;
+}
+
+uint_fast8_t Timer_A_getOutputForOutputModeOutBitValue(uint32_t timer,
+        uint_fast16_t captureCompareRegister)
+{
+    ASSERT(
+            (TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_1
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_2
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_3
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_4
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_5
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_6
+                    == captureCompareRegister));
+
+    if (HWREGBIT16(timer + captureCompareRegister, OUT_OFS))
+        return TIMER_A_OUTPUTMODE_OUTBITVALUE_HIGH;
+    else
+        return TIMER_A_OUTPUTMODE_OUTBITVALUE_LOW;
+}
+
+uint_fast16_t Timer_A_getCaptureCompareCount(uint32_t timer,
+        uint_fast16_t captureCompareRegister)
+{
+    ASSERT(
+            (TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_1
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_2
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_3
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_4
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_5
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_6
+                    == captureCompareRegister));
+
+    return HWREG16(timer + OFS_TA0R + captureCompareRegister);
+}
+
+void Timer_A_setOutputForOutputModeOutBitValue(uint32_t timer,
+        uint_fast16_t captureCompareRegister,
+        uint_fast8_t outputModeOutBitValue)
+{
+    TIMER_A_setOutputForOutputModeOutBitValue(timer, captureCompareRegister,
+            outputModeOutBitValue);
+}
+
+void Timer_A_generatePWM(uint32_t timer, const Timer_A_PWMConfig *config)
+{
+    ASSERT(
+            (TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK == config->clockSource)
+            || (TIMER_A_CLOCKSOURCE_ACLK == config->clockSource)
+            || (TIMER_A_CLOCKSOURCE_SMCLK == config->clockSource)
+            || (TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK
+                    == config->clockSource));
+
+    ASSERT(
+            (TIMER_A_CAPTURECOMPARE_REGISTER_0 == config->compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_1
+                    == config->compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_2
+                    == config->compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_3
+                    == config->compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_4
+                    == config->compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_5
+                    == config->compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_6
+                    == config->compareRegister));
+
+    ASSERT(
+            (TIMER_A_OUTPUTMODE_OUTBITVALUE == config->compareOutputMode)
+            || (TIMER_A_OUTPUTMODE_SET == config->compareOutputMode)
+            || (TIMER_A_OUTPUTMODE_TOGGLE_RESET
+                    == config->compareOutputMode)
+            || (TIMER_A_OUTPUTMODE_SET_RESET
+                    == config->compareOutputMode)
+            || (TIMER_A_OUTPUTMODE_TOGGLE == config->compareOutputMode)
+            || (TIMER_A_OUTPUTMODE_RESET == config->compareOutputMode)
+            || (TIMER_A_OUTPUTMODE_TOGGLE_SET
+                    == config->compareOutputMode)
+            || (TIMER_A_OUTPUTMODE_RESET_SET
+                    == config->compareOutputMode));
+
+    privateTimer_AProcessClockSourceDivider(timer, config->clockSourceDivider);
+
+    TIMER_A_CMSIS(timer)->rCTL.r &=
+            ~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + TIMER_A_UPDOWN_MODE
+                    + TIMER_A_DO_CLEAR + TIMER_A_TAIE_INTERRUPT_ENABLE);
+
+    TIMER_A_CMSIS(timer)->rCTL.r |= (config->clockSource + TIMER_A_UP_MODE
+            + TIMER_A_DO_CLEAR);
+
+    TIMER_A_CMSIS(timer)->rCCR0 = config->timerPeriod;
+
+    HWREG16(timer + OFS_TA0CCTL0) &= ~(TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE
+            + TIMER_A_OUTPUTMODE_RESET_SET);
+    HWREG16(timer + config->compareRegister) |= config->compareOutputMode;
+
+    HWREG16(timer + config->compareRegister + OFS_TA0R) = config->dutyCycle;
+}
+
+void Timer_A_stopTimer(uint32_t timer)
+{
+    TIMER_A_CMSIS(timer)->rCTL.r &= ~MC_3;
+}
+
+void Timer_A_setCompareValue(uint32_t timer, uint_fast16_t compareRegister,
+        uint_fast16_t compareValue)
+{
+    ASSERT(
+            (TIMER_A_CAPTURECOMPARE_REGISTER_0 == compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_1 == compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_2 == compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_3 == compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_4 == compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_5 == compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_6 == compareRegister));
+
+    HWREG16(timer + compareRegister + OFS_TA0R) = compareValue;
+}
+
+void Timer_A_clearInterruptFlag(uint32_t timer)
+{
+    BITBAND_PERI(TIMER_A_CMSIS(timer)->rCTL.r,TAIFG_OFS) = 0;
+}
+
+void Timer_A_clearCaptureCompareInterrupt(uint32_t timer,
+        uint_fast16_t captureCompareRegister)
+{
+    ASSERT(
+            (TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_1
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_2
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_3
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_4
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_5
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_6
+                    == captureCompareRegister));
+
+    HWREGBIT16(timer + captureCompareRegister, CCIFG_OFS) = 0;
+}
+
+void Timer_A_enableInterrupt(uint32_t timer)
+{
+    BITBAND_PERI(TIMER_A_CMSIS(timer)->rCTL.r,TAIE_OFS) = 1;
+}
+
+void Timer_A_disableInterrupt(uint32_t timer)
+{
+    BITBAND_PERI(TIMER_A_CMSIS(timer)->rCTL.r,TAIE_OFS) = 0;
+}
+
+uint32_t Timer_A_getInterruptStatus(uint32_t timer)
+{
+    return TIMER_A_CMSIS(timer)->rCTL.b.bIFG;
+}
+
+void Timer_A_enableCaptureCompareInterrupt(uint32_t timer,
+        uint_fast16_t captureCompareRegister)
+{
+    ASSERT(
+            (TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_1
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_2
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_3
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_4
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_5
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_6
+                    == captureCompareRegister));
+
+    HWREGBIT16(timer + captureCompareRegister, CCIE_OFS) = 1;
+}
+
+void Timer_A_disableCaptureCompareInterrupt(uint32_t timer,
+        uint_fast16_t captureCompareRegister)
+{
+    ASSERT(
+            (TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_1
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_2
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_3
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_4
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_5
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_6
+                    == captureCompareRegister));
+                    
+    HWREGBIT16(timer + captureCompareRegister, CCIE_OFS) = 0;
+}
+
+uint32_t Timer_A_getCaptureCompareInterruptStatus(uint32_t timer,
+        uint_fast16_t captureCompareRegister, uint_fast16_t mask)
+{
+    return HWREG16(timer + captureCompareRegister) & mask;
+}
+
+uint32_t Timer_A_getEnabledInterruptStatus(uint32_t timer)
+{
+    if (TIMER_A_CMSIS(timer)->rCTL.r & TAIE)
+    {
+        return Timer_A_getInterruptStatus(timer);
+    } else
+    {
+        return 0;
+    }
+
+}
+
+uint32_t Timer_A_getCaptureCompareEnabledInterruptStatus(uint32_t timer,
+        uint_fast16_t captureCompareRegister)
+{
+    if (HWREGBIT16(timer + captureCompareRegister, CCIE_OFS))
+        return Timer_A_getCaptureCompareInterruptStatus(timer,
+                captureCompareRegister,
+                TIMER_A_CAPTURE_OVERFLOW |
+                TIMER_A_CAPTURECOMPARE_INTERRUPT_FLAG);
+    else
+        return 0;
+}
+
+void Timer_A_registerInterrupt(uint32_t timer, uint_fast8_t interruptSelect,
+        void (*intHandler)(void))
+{
+    if (interruptSelect == TIMER_A_CCR0_INTERRUPT)
+    {
+        switch (timer)
+        {
+        case TIMER_A0_MODULE:
+            Interrupt_registerInterrupt(INT_TA0_0, intHandler);
+            Interrupt_enableInterrupt(INT_TA0_0);
+            break;
+        case TIMER_A1_MODULE:
+            Interrupt_registerInterrupt(INT_TA1_0, intHandler);
+            Interrupt_enableInterrupt(INT_TA1_0);
+            break;
+        case TIMER_A2_MODULE:
+            Interrupt_registerInterrupt(INT_TA2_0, intHandler);
+            Interrupt_enableInterrupt(INT_TA2_0);
+            break;
+        case TIMER_A3_MODULE:
+            Interrupt_registerInterrupt(INT_TA3_0, intHandler);
+            Interrupt_enableInterrupt(INT_TA3_0);
+            break;
+        default:
+            ASSERT(false);
+        }
+    } else if (interruptSelect == TIMER_A_CCRX_AND_OVERFLOW_INTERRUPT)
+    {
+        switch (timer)
+        {
+        case TIMER_A0_MODULE:
+            Interrupt_registerInterrupt(INT_TA0_N, intHandler);
+            Interrupt_enableInterrupt(INT_TA0_N);
+            break;
+        case TIMER_A1_MODULE:
+            Interrupt_registerInterrupt(INT_TA1_N, intHandler);
+            Interrupt_enableInterrupt(INT_TA1_N);
+            break;
+        case TIMER_A2_MODULE:
+            Interrupt_registerInterrupt(INT_TA2_N, intHandler);
+            Interrupt_enableInterrupt(INT_TA2_N);
+            break;
+        case TIMER_A3_MODULE:
+            Interrupt_registerInterrupt(INT_TA3_N, intHandler);
+            Interrupt_enableInterrupt(INT_TA3_N);
+            break;
+        default:
+            ASSERT(false);
+        }
+    } else
+    {
+        ASSERT(false);
+    }
+}
+
+void Timer_A_unregisterInterrupt(uint32_t timer, uint_fast8_t interruptSelect)
+{
+    if (interruptSelect == TIMER_A_CCR0_INTERRUPT)
+    {
+        switch (timer)
+        {
+        case TIMER_A0_MODULE:
+            Interrupt_disableInterrupt(INT_TA0_0);
+            Interrupt_unregisterInterrupt(INT_TA0_0);
+            break;
+        case TIMER_A1_MODULE:
+            Interrupt_disableInterrupt(INT_TA1_0);
+            Interrupt_unregisterInterrupt(INT_TA1_0);
+            break;
+        case TIMER_A2_MODULE:
+            Interrupt_disableInterrupt(INT_TA2_0);
+            Interrupt_unregisterInterrupt(INT_TA2_0);
+            break;
+        case TIMER_A3_MODULE:
+            Interrupt_disableInterrupt(INT_TA3_0);
+            Interrupt_unregisterInterrupt(INT_TA3_0);
+            break;
+        default:
+            ASSERT(false);
+        }
+    } else if (interruptSelect == TIMER_A_CCRX_AND_OVERFLOW_INTERRUPT)
+    {
+        switch (timer)
+        {
+        case TIMER_A0_MODULE:
+            Interrupt_disableInterrupt(INT_TA0_N);
+            Interrupt_unregisterInterrupt(INT_TA0_N);
+            break;
+        case TIMER_A1_MODULE:
+            Interrupt_disableInterrupt(INT_TA1_N);
+            Interrupt_unregisterInterrupt(INT_TA1_N);
+            break;
+        case TIMER_A2_MODULE:
+            Interrupt_disableInterrupt(INT_TA2_N);
+            Interrupt_unregisterInterrupt(INT_TA2_N);
+            break;
+        case TIMER_A3_MODULE:
+            Interrupt_disableInterrupt(INT_TA3_N);
+            Interrupt_unregisterInterrupt(INT_TA3_N);
+            break;
+        default:
+            ASSERT(false);
+        }
+    } else
+    {
+        ASSERT(false);
+    }
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer_a.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer_a.h
new file mode 100644
index 000000000..6fe7f177e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer_a.h
@@ -0,0 +1,1306 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef TIMERA_H_
+#define TIMERA_H_
+
+//*****************************************************************************
+//
+//! \addtogroup timera_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+#include <stdint.h>
+#include <msp.h>
+#include <stdbool.h>
+
+//*****************************************************************************
+//
+// Timer_A Specific Parameters
+//
+//*****************************************************************************
+#define TIMER_A_CMSIS(x) ((TIMER_A0_Type *) x)
+
+#define TIMER_A_CCR0_INTERRUPT              0x00
+#define TIMER_A_CCRX_AND_OVERFLOW_INTERRUPT 0x01
+
+//*****************************************************************************
+//
+//! \typedef Timer_A_ContinuousModeConfig
+//! \brief Type definition for \link _Timer_A_ContinuousModeConfig \endlink
+//!     structure
+//!
+//! \struct _Timer_A_ContinuousModeConfig
+//! \brief Configuration structure for continuous mode in the \b Timer_A module.
+//!         See \link Timer_A_configureContinuousMode \endlink for parameter
+//!                 documentation.
+//
+//*****************************************************************************
+typedef struct _Timer_A_ContinuousModeConfig
+{
+    uint_fast16_t clockSource;
+    uint_fast16_t clockSourceDivider;
+    uint_fast16_t timerInterruptEnable_TAIE;
+    uint_fast16_t timerClear;
+} Timer_A_ContinuousModeConfig;
+
+//*****************************************************************************
+//
+//! \typedef Timer_A_UpModeConfig
+//! \brief Type definition for \link _Timer_A_UpModeConfig \endlink
+//!     structure
+//!
+//! \struct _Timer_A_UpModeConfig
+//! \brief Configuration structure for Up mode in the \b Timer_A module. See
+//!          \link Timer_A_configureUpMode \endlink for parameter
+//!                 documentation.
+//
+//*****************************************************************************
+typedef struct _Timer_A_UpModeConfig
+{
+    uint_fast16_t clockSource;
+    uint_fast16_t clockSourceDivider;
+    uint_fast16_t timerPeriod;
+    uint_fast16_t timerInterruptEnable_TAIE;
+    uint_fast16_t captureCompareInterruptEnable_CCR0_CCIE;
+    uint_fast16_t timerClear;
+} Timer_A_UpModeConfig;
+
+//*****************************************************************************
+//
+//! \typedef Timer_A_UpDownModeConfig
+//! \brief Type definition for \link _Timer_A_UpDownModeConfig \endlink
+//!     structure
+//!
+//! \struct _Timer_A_UpDownModeConfig
+//! \brief Configuration structure for UpDown mode in the \b Timer_A module. See
+//!          \link Timer_A_configureUpDownMode \endlink for parameter
+//!                 documentation.
+//
+//*****************************************************************************
+typedef struct _Timer_A_UpDownModeConfig
+{
+    uint_fast16_t clockSource;
+    uint_fast16_t clockSourceDivider;
+    uint_fast16_t timerPeriod;
+    uint_fast16_t timerInterruptEnable_TAIE;
+    uint_fast16_t captureCompareInterruptEnable_CCR0_CCIE;
+    uint_fast16_t timerClear;
+} Timer_A_UpDownModeConfig;
+
+//*****************************************************************************
+//
+//! \typedef Timer_A_CaptureModeConfig
+//! \brief Type definition for \link _Timer_A_CaptureModeConfig \endlink
+//!     structure
+//!
+//! \struct _Timer_A_CaptureModeConfig
+//! \brief Configuration structure for capture mode in the \b Timer_A module.
+//!         See  \link Timer_A_initCapture \endlink for parameter
+//!                 documentation.
+//
+//*****************************************************************************
+typedef struct _Timer_A_CaptureModeConfig
+{
+    uint_fast16_t captureRegister;
+    uint_fast16_t captureMode;
+    uint_fast16_t captureInputSelect;
+    uint_fast16_t synchronizeCaptureSource;
+    uint_fast8_t captureInterruptEnable;
+    uint_fast16_t captureOutputMode;
+} Timer_A_CaptureModeConfig;
+
+//*****************************************************************************
+//
+//! \typedef Timer_A_CompareModeConfig
+//! \brief Type definition for \link _Timer_A_CompareModeConfig \endlink
+//!     structure
+//!
+//! \struct _Timer_A_CompareModeConfig
+//! \brief Configuration structure for compare mode in the \b Timer_A module.
+//!          See \link Timer_A_initCompare \endlink for parameter
+//!                 documentation.
+//
+//*****************************************************************************
+typedef struct _Timer_A_CompareModeConfig
+{
+    uint_fast16_t compareRegister;
+    uint_fast16_t compareInterruptEnable;
+    uint_fast16_t compareOutputMode;
+    uint_fast16_t compareValue;
+} Timer_A_CompareModeConfig;
+
+//*****************************************************************************
+//
+//! \typedef Timer_A_PWMConfig
+//! \brief Type definition for \link _Timer_A_PWMConfig \endlink
+//!     structure
+//!
+//! \struct _Timer_A_PWMConfig
+//! \brief Configuration structure for PWM mode in the \b Timer_A module. See
+//!          \link Timer_A_generatePWM \endlink for parameter
+//!                 documentation.
+//
+//*****************************************************************************
+typedef struct _Timer_A_PWMConfig
+{
+    uint_fast16_t clockSource;
+    uint_fast16_t clockSourceDivider;
+    uint_fast16_t timerPeriod;
+    uint_fast16_t compareRegister;
+    uint_fast16_t compareOutputMode;
+    uint_fast16_t dutyCycle;
+} Timer_A_PWMConfig;
+
+
+//*****************************************************************************
+//
+// The following is a parameter determines the maximum difference in counts of
+// the TAxR register for a majority vote
+//
+//*****************************************************************************
+#define TIMER_A_THRESHOLD                                                     50
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the clockSourceDivider
+// parameter
+//
+//*****************************************************************************
+#define TIMER_A_CLOCKSOURCE_DIVIDER_1                                      0x01
+#define TIMER_A_CLOCKSOURCE_DIVIDER_2                                      0x02
+#define TIMER_A_CLOCKSOURCE_DIVIDER_4                                      0x04
+#define TIMER_A_CLOCKSOURCE_DIVIDER_8                                      0x08
+#define TIMER_A_CLOCKSOURCE_DIVIDER_3                                      0x03
+#define TIMER_A_CLOCKSOURCE_DIVIDER_5                                      0x05
+#define TIMER_A_CLOCKSOURCE_DIVIDER_6                                      0x06
+#define TIMER_A_CLOCKSOURCE_DIVIDER_7                                      0x07
+#define TIMER_A_CLOCKSOURCE_DIVIDER_10                                     0x0A
+#define TIMER_A_CLOCKSOURCE_DIVIDER_12                                     0x0C
+#define TIMER_A_CLOCKSOURCE_DIVIDER_14                                     0x0E
+#define TIMER_A_CLOCKSOURCE_DIVIDER_16                                     0x10
+#define TIMER_A_CLOCKSOURCE_DIVIDER_20                                     0x14
+#define TIMER_A_CLOCKSOURCE_DIVIDER_24                                     0x18
+#define TIMER_A_CLOCKSOURCE_DIVIDER_28                                     0x1C
+#define TIMER_A_CLOCKSOURCE_DIVIDER_32                                     0x20
+#define TIMER_A_CLOCKSOURCE_DIVIDER_40                                     0x28
+#define TIMER_A_CLOCKSOURCE_DIVIDER_48                                     0x30
+#define TIMER_A_CLOCKSOURCE_DIVIDER_56                                     0x38
+#define TIMER_A_CLOCKSOURCE_DIVIDER_64                                     0x40
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the timerMode parameter
+//
+//*****************************************************************************
+#define TIMER_A_STOP_MODE                                                  MC_0
+#define TIMER_A_UP_MODE                                                    MC_1
+#define TIMER_A_CONTINUOUS_MODE                                            MC_2
+#define TIMER_A_UPDOWN_MODE                                                MC_3
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the timerClear parameter
+//
+//*****************************************************************************
+#define TIMER_A_DO_CLEAR                                                  TACLR
+#define TIMER_A_SKIP_CLEAR                                                 0x00
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the clockSource parameter
+//
+//*****************************************************************************
+#define TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK                        TASSEL__TACLK
+#define TIMER_A_CLOCKSOURCE_ACLK                                   TASSEL__ACLK
+#define TIMER_A_CLOCKSOURCE_SMCLK                                 TASSEL__SMCLK
+#define TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK               TASSEL__INCLK
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the timerInterruptEnable_TAIE
+// parameter
+//
+//*****************************************************************************
+#define TIMER_A_TAIE_INTERRUPT_ENABLE                                      TAIE
+#define TIMER_A_TAIE_INTERRUPT_DISABLE                                     0x00
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the
+// captureCompareInterruptEnable_CCR0_CCIE parameter
+//
+//*****************************************************************************
+#define TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE                                 CCIE
+#define TIMER_A_CCIE_CCR0_INTERRUPT_DISABLE                                0x00
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the captureInterruptEnable
+// parameter
+//
+//*****************************************************************************
+#define TIMER_A_CAPTURECOMPARE_INTERRUPT_DISABLE                           0x00
+#define TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE                            CCIE
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the captureInputSelect
+// parameter
+//
+//*****************************************************************************
+#define TIMER_A_CAPTURE_INPUTSELECT_CCIxA                                CCIS_0
+#define TIMER_A_CAPTURE_INPUTSELECT_CCIxB                                CCIS_1
+#define TIMER_A_CAPTURE_INPUTSELECT_GND                                  CCIS_2
+#define TIMER_A_CAPTURE_INPUTSELECT_Vcc                                  CCIS_3
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the compareOutputMode
+// parameter
+//
+//*****************************************************************************
+#define TIMER_A_OUTPUTMODE_OUTBITVALUE                                 OUTMOD_0
+#define TIMER_A_OUTPUTMODE_SET                                         OUTMOD_1
+#define TIMER_A_OUTPUTMODE_TOGGLE_RESET                                OUTMOD_2
+#define TIMER_A_OUTPUTMODE_SET_RESET                                   OUTMOD_3
+#define TIMER_A_OUTPUTMODE_TOGGLE                                      OUTMOD_4
+#define TIMER_A_OUTPUTMODE_RESET                                       OUTMOD_5
+#define TIMER_A_OUTPUTMODE_TOGGLE_SET                                  OUTMOD_6
+#define TIMER_A_OUTPUTMODE_RESET_SET                                   OUTMOD_7
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the compareRegister parameter
+//
+//*****************************************************************************
+#define TIMER_A_CAPTURECOMPARE_REGISTER_0                                  0x02
+#define TIMER_A_CAPTURECOMPARE_REGISTER_1                                  0x04
+#define TIMER_A_CAPTURECOMPARE_REGISTER_2                                  0x06
+#define TIMER_A_CAPTURECOMPARE_REGISTER_3                                  0x08
+#define TIMER_A_CAPTURECOMPARE_REGISTER_4                                  0x0A
+#define TIMER_A_CAPTURECOMPARE_REGISTER_5                                  0x0C
+#define TIMER_A_CAPTURECOMPARE_REGISTER_6                                  0x0E
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the captureMode parameter
+//
+//*****************************************************************************
+#define TIMER_A_CAPTUREMODE_NO_CAPTURE                                     CM_0
+#define TIMER_A_CAPTUREMODE_RISING_EDGE                                    CM_1
+#define TIMER_A_CAPTUREMODE_FALLING_EDGE                                   CM_2
+#define TIMER_A_CAPTUREMODE_RISING_AND_FALLING_EDGE                        CM_3
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the synchronizeCaptureSource
+// parameter
+//
+//*****************************************************************************
+#define TIMER_A_CAPTURE_ASYNCHRONOUS                                       0x00
+#define TIMER_A_CAPTURE_SYNCHRONOUS                                         SCS
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the mask parameter
+//
+//*****************************************************************************
+#define TIMER_A_CAPTURE_OVERFLOW                                            COV
+#define TIMER_A_CAPTURECOMPARE_INTERRUPT_FLAG                             CCIFG
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the synchronized parameter
+//
+//*****************************************************************************
+#define TIMER_A_READ_SYNCHRONIZED_CAPTURECOMPAREINPUT                      SCCI
+#define TIMER_A_READ_CAPTURE_COMPARE_INPUT                                  CCI
+
+
+#define TIMER_A_CAPTURECOMPARE_INPUT_HIGH                                  0x01
+#define TIMER_A_CAPTURECOMPARE_INPUT_LOW                                   0x00
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the outputModeOutBitValue
+// parameter
+//
+//*****************************************************************************
+#define TIMER_A_OUTPUTMODE_OUTBITVALUE_HIGH                                 OUT
+#define TIMER_A_OUTPUTMODE_OUTBITVALUE_LOW                                 0x00
+
+//*****************************************************************************
+//
+// The following are values that can be passed toThe following are values that
+// can be returned by the interrupt functions
+//
+//*****************************************************************************
+#define TIMER_A_INTERRUPT_NOT_PENDING                                      0x00
+#define TIMER_A_INTERRUPT_PENDING                                          0x01
+
+
+/* Convenience function for setting the PWM Duty Cycle */
+#define Timer_A_setDutyCycle(timer,dutyCycle) \
+                Timer_A_setCompareValue(timer,dutyCycle)
+
+//*****************************************************************************
+//
+//Prototypes for the APIs.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! Starts Timer_A counter
+//!
+//! \param timer is the instance of the Timer_A module. Valid parameters
+//! vary from part to part, but can include:
+//!         - \b TIMER_A0_MODULE
+//!         - \b TIMER_A1_MODULE
+//!         - \b TIMER_A2_MODULE
+//!         - \b TIMER_A3_MODULE
+//! \param timerMode selects Clock source. Valid values are
+//!       - \b TIMER_A_CONTINUOUS_MODE [Default value]
+//!       - \b TIMER_A_UPDOWN_MODE
+//!       - \b TIMER_A_UP_MODE
+//!
+//! \note This function assumes that the timer has been previously configured
+//! using Timer_A_configureContinuousMode,  Timer_A_configureUpMode or
+//! Timer_A_configureUpDownMode.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void Timer_A_startCounter(uint32_t timer, uint_fast16_t timerMode);
+
+//*****************************************************************************
+//
+//! Configures Timer_A in continuous mode.
+//!
+//! \param timer is the instance of the Timer_A module. Valid parameters
+//! vary from part to part, but can include:
+//!         - \b TIMER_A0_MODULE
+//!         - \b TIMER_A1_MODULE
+//!         - \b TIMER_A2_MODULE
+//!         - \b TIMER_A3_MODULE
+//! \param config Configuration structure for Timer_A continuous mode
+//!
+//! <hr>
+//! <b>Configuration options for \link Timer_A_ContinuousModeConfig \endlink
+//!         structure.</b>
+//! <hr>
+//!
+//! \param clockSource selects Clock source. Valid values are
+//!       - \b TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK [Default value]
+//!       - \b TIMER_A_CLOCKSOURCE_ACLK
+//!       - \b TIMER_A_CLOCKSOURCE_SMCLK
+//!       - \b TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK
+//! \param timerInterruptEnable_TAIE is the divider for Clock source.
+//!       Valid values are:
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_1 [Default value]
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_2
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_4
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_8
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_3
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_5
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_6
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_7
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_10
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_12
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_14
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_16
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_20
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_24
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_28
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_32
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_40
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_48
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_56
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_64
+//! \param timerInterruptEnable_TAIE is to enable or disable Timer_A
+//!        interrupt. Valid values are
+//!      - \b TIMER_A_TAIE_INTERRUPT_ENABLE
+//!      - \b TIMER_A_TAIE_INTERRUPT_DISABLE [Default value]
+//! \param timerClear decides if Timer_A clock divider, count direction,
+//!        count need to be reset. Valid values are
+//!      - \b TIMER_A_DO_CLEAR
+//!      - \b TIMER_A_SKIP_CLEAR [Default value]
+//!
+//! \note This API does not start the timer. Timer needs to be started when
+//! required using the Timer_A_startCounter API.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void Timer_A_configureContinuousMode(uint32_t timer,
+        const Timer_A_ContinuousModeConfig *config);
+
+//*****************************************************************************
+//
+//! Configures Timer_A in up mode.
+//!
+//! \param timer is the instance of the Timer_A module. Valid parameters
+//! vary from part to part, but can include:
+//!         - \b TIMER_A0_MODULE
+//!         - \b TIMER_A1_MODULE
+//!         - \b TIMER_A2_MODULE
+//!         - \b TIMER_A3_MODULE
+//! \param config Configuration structure for Timer_A Up mode
+//!
+//! <hr>
+//! <b>Configuration options for \link Timer_A_UpModeConfig \endlink
+//!         structure.</b>
+//! <hr>
+//! \param clockSource selects Clock source. Valid values are
+//!       - \b TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK [Default value]
+//!       - \b TIMER_A_CLOCKSOURCE_ACLK
+//!       - \b TIMER_A_CLOCKSOURCE_SMCLK
+//!       - \b TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK
+//! \param clockSourceDivider is the divider for Clock source. Valid values
+//!         are:
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_1 [Default value]
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_2
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_4
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_8
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_3
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_5
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_6
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_7
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_10
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_12
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_14
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_16
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_20
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_24
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_28
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_32
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_40
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_48
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_56
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_64
+//! \param timerPeriod is the specified Timer_A period. This is the value
+//!         that gets written into the CCR0. Limited to 16 bits[uint16_t]
+//! \param timerInterruptEnable_TAIE is to enable or disable Timer_A
+//!        interrupt. Valid values are:
+//!      - \b TIMER_A_TAIE_INTERRUPT_ENABLE and
+//!      - \b TIMER_A_TAIE_INTERRUPT_DISABLE [Default value]
+//! \param captureCompareInterruptEnable_CCR0_CCIE is to enable or disable
+//!         Timer_A CCR0 captureComapre interrupt. Valid values are
+//!      - \b TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE and
+//!      - \b TIMER_A_CCIE_CCR0_INTERRUPT_DISABLE [Default value]
+//! \param timerClear decides if Timer_A clock divider, count direction,
+//!        count need to be reset. Valid values are
+//!      - \b TIMER_A_DO_CLEAR
+//!      - \b TIMER_A_SKIP_CLEAR [Default value]
+//!
+//!\note This API does not start the timer. Timer needs to be started when
+//!required using the Timer_A_startCounter API.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void Timer_A_configureUpMode(uint32_t timer,
+        const Timer_A_UpModeConfig *config);
+
+//*****************************************************************************
+//
+//! Configures Timer_A in up down mode.
+//!
+//! \param timer is the instance of the Timer_A module. Valid parameters
+//! vary from part to part, but can include:
+//!         - \b TIMER_A0_MODULE
+//!         - \b TIMER_A1_MODULE
+//!         - \b TIMER_A2_MODULE
+//!         - \b TIMER_A3_MODULE
+//! \param config Configuration structure for Timer_A UpDown mode
+//!
+//! <hr>
+//! <b>Configuration options for \link Timer_A_UpDownModeConfig \endlink
+//!         structure.</b>
+//! <hr>
+//! \param clockSource selects Clock source. Valid values are
+//!       - \b TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK [Default value]
+//!       - \b TIMER_A_CLOCKSOURCE_ACLK
+//!       - \b TIMER_A_CLOCKSOURCE_SMCLK
+//!       - \b TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK
+//! \param clockSourceDivider is the divider for Clock source. Valid values
+//!         are:
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_1 [Default value]
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_2
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_4
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_8
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_3
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_5
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_6
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_7
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_10
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_12
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_14
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_16
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_20
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_24
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_28
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_32
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_40
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_48
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_56
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_64
+//! \param timerPeriod is the specified Timer_A period
+//! \param timerInterruptEnable_TAIE is to enable or disable Timer_A
+//!         interrupt.
+//!        Valid values are
+//!      - \b TIMER_A_TAIE_INTERRUPT_ENABLE
+//!      - \b TIMER_A_TAIE_INTERRUPT_DISABLE [Default value]
+//! \param captureCompareInterruptEnable_CCR0_CCIE is to enable or disable
+//!         Timer_A CCR0 captureComapre interrupt. Valid values are
+//!      - \b TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE and
+//!      - \b TIMER_A_CCIE_CCR0_INTERRUPT_DISABLE [Default value]
+//! \param timerClear decides if Timer_A clock divider, count direction, count
+//!        need to be reset. Valid values are
+//!      - \b TIMER_A_DO_CLEAR
+//!      - \b TIMER_A_SKIP_CLEAR [Default value]
+//!
+//!This API does not start the timer. Timer needs to be started when required
+//!using the Timer_A_startCounter API.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void Timer_A_configureUpDownMode(uint32_t timer,
+        const Timer_A_UpDownModeConfig *config);
+
+//*****************************************************************************
+//
+//! Initializes Capture Mode
+//!
+//! \param timer is the instance of the Timer_A module. Valid parameters
+//! vary from part to part, but can include:
+//!         - \b TIMER_A0_MODULE
+//!         - \b TIMER_A1_MODULE
+//!         - \b TIMER_A2_MODULE
+//!         - \b TIMER_A3_MODULE
+//! \param config Configuration structure for Timer_A capture mode
+//!
+//! <hr>
+//! <b>Configuration options for \link Timer_A_CaptureModeConfig \endlink
+//!         structure.</b>
+//! <hr>
+//! \param captureRegister selects the Capture register being used. Valid
+//!     values are
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_0
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_1
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_2
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_3
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_4
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_5
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_6
+//!    \n Refer to datasheet to ensure the device has the capture compare
+//!    register being used
+//! \param captureMode is the capture mode selected. Valid values are
+//!      - \b TIMER_A_CAPTUREMODE_NO_CAPTURE [Default value]
+//!      - \b TIMER_A_CAPTUREMODE_RISING_EDGE
+//!      - \b TIMER_A_CAPTUREMODE_FALLING_EDGE
+//!      - \b TIMER_A_CAPTUREMODE_RISING_AND_FALLING_EDGE
+//! \param captureInputSelect decides the Input Select
+//!      - \b TIMER_A_CAPTURE_INPUTSELECT_CCIxA [Default value]
+//!      - \b TIMER_A_CAPTURE_INPUTSELECT_CCIxB
+//!      - \b TIMER_A_CAPTURE_INPUTSELECT_GND
+//!      - \b TIMER_A_CAPTURE_INPUTSELECT_Vcc
+//! \param synchronizeCaptureSource decides if capture source should be
+//!         synchronized with timer clock
+//!        Valid values are
+//!      - \b TIMER_A_CAPTURE_ASYNCHRONOUS [Default value]
+//!      - \b TIMER_A_CAPTURE_SYNCHRONOUS
+//! \param captureInterruptEnable is to enable or disable
+//!         timer captureComapre interrupt. Valid values are
+//!      - \b TIMER_A_CAPTURECOMPARE_INTERRUPT_DISABLE [Default value]
+//!      - \b TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE
+//! \param captureOutputMode specifies the ouput mode. Valid values are
+//!      - \b TIMER_A_OUTPUTMODE_OUTBITVALUE [Default value],
+//!      - \b TIMER_A_OUTPUTMODE_SET,
+//!      - \b TIMER_A_OUTPUTMODE_TOGGLE_RESET,
+//!      - \b TIMER_A_OUTPUTMODE_SET_RESET
+//!      - \b TIMER_A_OUTPUTMODE_TOGGLE,
+//!      - \b TIMER_A_OUTPUTMODE_RESET,
+//!      - \b TIMER_A_OUTPUTMODE_TOGGLE_SET,
+//!      - \b TIMER_A_OUTPUTMODE_RESET_SET
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void Timer_A_initCapture(uint32_t timer,
+        const Timer_A_CaptureModeConfig *config);
+
+//*****************************************************************************
+//
+//! Initializes Compare Mode
+//!
+//! \param timer is the instance of the Timer_A module. Valid parameters
+//! vary from part to part, but can include:
+//!         - \b TIMER_A0_MODULE
+//!         - \b TIMER_A1_MODULE
+//!         - \b TIMER_A2_MODULE
+//!         - \b TIMER_A3_MODULE
+//! \param config Configuration structure for Timer_A compare mode
+//!
+//! <hr>
+//! <b>Configuration options for \link Timer_A_CompareModeConfig \endlink
+//!         structure.</b>
+//! <hr>
+//! \param compareRegister selects the Capture register being used. Valid
+//!     values are
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_0
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_1
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_2
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_3
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_4
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_5
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_6
+//!    \n Refer to datasheet to ensure the device has the capture compare
+//!    register being used
+//! \param compareInterruptEnable is to enable or disable
+//!         timer captureComapre interrupt. Valid values are
+//!      - \b TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE and
+//!      - \b TIMER_A_CAPTURECOMPARE_INTERRUPT_DISABLE [Default value]
+//! \param compareOutputMode specifies the output mode. Valid values are
+//!      - \b TIMER_A_OUTPUTMODE_OUTBITVALUE [Default value],
+//!      - \b TIMER_A_OUTPUTMODE_SET,
+//!      - \b TIMER_A_OUTPUTMODE_TOGGLE_RESET,
+//!      - \b TIMER_A_OUTPUTMODE_SET_RESET
+//!      - \b TIMER_A_OUTPUTMODE_TOGGLE,
+//!      - \b TIMER_A_OUTPUTMODE_RESET,
+//!      - \b TIMER_A_OUTPUTMODE_TOGGLE_SET,
+//!      - \b TIMER_A_OUTPUTMODE_RESET_SET
+//! \param compareValue is the count to be compared with in compare mode
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void Timer_A_initCompare(uint32_t timer,
+        const Timer_A_CompareModeConfig *config);
+
+//*****************************************************************************
+//
+//! Reset/Clear the timer clock divider, count direction, count
+//!
+//! \param timer is the instance of the Timer_A module. Valid parameters
+//! vary from part to part, but can include:
+//!         - \b TIMER_A0_MODULE
+//!         - \b TIMER_A1_MODULE
+//!         - \b TIMER_A2_MODULE
+//!         - \b TIMER_A3_MODULE
+//!
+//! \returns None
+//
+//*****************************************************************************
+extern void Timer_A_clearTimer(uint32_t timer);
+
+//*****************************************************************************
+//
+//! Get synchronized capture compare input
+//!
+//! \param timer is the instance of the Timer_A module. Valid parameters
+//! vary from part to part, but can include:
+//!         - \b TIMER_A0_MODULE
+//!         - \b TIMER_A1_MODULE
+//!         - \b TIMER_A2_MODULE
+//!         - \b TIMER_A3_MODULE
+//! \param captureCompareRegister selects the Capture register being used.
+//!     Valid values are
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_0
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_1
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_2
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_3
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_4
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_5
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_6
+//!    \n Refer to datasheet to ensure the device has the capture compare
+//!    register being used
+//! \param synchronizedSetting is to select type of capture compare input.
+//!         Valid values are
+//!      - \b TIMER_A_READ_CAPTURE_COMPARE_INPUT
+//!      - \b TIMER_A_READ_SYNCHRONIZED_CAPTURECOMPAREINPUT
+//!
+//! \return \b TIMER_A_CAPTURECOMPARE_INPUT_HIGH or
+//!       - \b TIMER_A_CAPTURECOMPARE_INPUT_LOW
+//
+//*****************************************************************************
+extern uint_fast8_t Timer_A_getSynchronizedCaptureCompareInput(uint32_t timer,
+        uint_fast16_t captureCompareRegister,
+        uint_fast16_t synchronizedSetting);
+
+//*****************************************************************************
+//
+//! Get ouput bit for output mode
+//!
+//! \param timer is the instance of the Timer_A module. Valid parameters
+//! vary from part to part, but can include:
+//!         - \b TIMER_A0_MODULE
+//!         - \b TIMER_A1_MODULE
+//!         - \b TIMER_A2_MODULE
+//!         - \b TIMER_A3_MODULE
+//! \param captureCompareRegister selects the Capture register being used.
+//!     Valid values are
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_0
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_1
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_2
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_3
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_4
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_5
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_6
+//!    \n Refer to datasheet to ensure the device has the capture compare
+//!    register being used
+//!
+//! \return \b TIMER_A_OUTPUTMODE_OUTBITVALUE_HIGH or
+//!       - \b TIMER_A_OUTPUTMODE_OUTBITVALUE_LOW
+//
+//*****************************************************************************
+extern uint_fast8_t Timer_A_getOutputForOutputModeOutBitValue(uint32_t timer,
+        uint_fast16_t captureCompareRegister);
+
+//*****************************************************************************
+//
+//! Get current capture compare count
+//!
+//! \param timer is the instance of the Timer_A module. Valid parameters
+//! vary from part to part, but can include:
+//!         - \b TIMER_A0_MODULE
+//!         - \b TIMER_A1_MODULE
+//!         - \b TIMER_A2_MODULE
+//!         - \b TIMER_A3_MODULE
+//! \param captureCompareRegister selects the Capture register being used.
+//!     Valid values are
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_0
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_1
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_2
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_3
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_4
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_5
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_6
+//!    \n Refer to datasheet to ensure the device has the capture compare
+//!    register being used
+//!
+//! \return current count as uint16_t
+//
+//*****************************************************************************
+extern uint_fast16_t Timer_A_getCaptureCompareCount(uint32_t timer,
+        uint_fast16_t captureCompareRegister);
+
+//*****************************************************************************
+//
+//! Set ouput bit for output mode
+//!
+//! \param timer is the instance of the Timer_A module. Valid parameters
+//! vary from part to part, but can include:
+//!         - \b TIMER_A0_MODULE
+//!         - \b TIMER_A1_MODULE
+//!         - \b TIMER_A2_MODULE
+//!         - \b TIMER_A3_MODULE
+//! \param captureCompareRegister selects the Capture register being used.
+//!     are
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_0
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_1
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_2
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_3
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_4
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_5
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_6
+//!    \n Refer to datasheet to ensure the device has the capture compare
+//!    register being used
+//! \param outputModeOutBitValue the value to be set for out bit.
+//!     Valid values are:
+//!                    - \b TIMER_A_OUTPUTMODE_OUTBITVALUE_HIGH
+//!                    - \b TIMER_A_OUTPUTMODE_OUTBITVALUE_LOW
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void Timer_A_setOutputForOutputModeOutBitValue(uint32_t timer,
+        uint_fast16_t captureCompareRegister,
+        uint_fast8_t outputModeOutBitValue);
+
+//*****************************************************************************
+//
+//! Generate a PWM with timer running in up mode
+//!
+//! \param timer is the instance of the Timer_A module. Valid parameters
+//! vary from part to part, but can include:
+//!         - \b TIMER_A0_MODULE
+//!         - \b TIMER_A1_MODULE
+//!         - \b TIMER_A2_MODULE
+//!         - \b TIMER_A3_MODULE
+//! \param config Configuration structure for Timer_A PWM mode
+//!
+//! <hr>
+//! <b>Configuration options for \link Timer_A_PWMConfig \endlink
+//!         structure.</b>
+//! <hr>
+//! \param clockSource selects Clock source. Valid values are
+//!       - \b TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK
+//!       - \b TIMER_A_CLOCKSOURCE_ACLK
+//!       - \b TIMER_A_CLOCKSOURCE_SMCLK
+//!       - \b TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK
+//! \param clockSourceDivider is the divider for Clock source. Valid values
+//!         are
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_1
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_2
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_4
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_8
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_3
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_5
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_6
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_7
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_10
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_12
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_14
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_16
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_20
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_24
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_28
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_32
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_40
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_48
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_56
+//!      - \b TIMER_A_CLOCKSOURCE_DIVIDER_64
+//! \param timerPeriod selects the desired timer period
+//! \param compareRegister selects the compare register being used.
+//!     Valid values are
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_0
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_1
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_2
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_3
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_4
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_5
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_6
+//!    <br>\n Refer to datasheet to ensure the device has the capture compare
+//!    register being used
+//! \param compareOutputMode specifies the ouput mode. Valid values are:
+//!      - \b TIMER_A_OUTPUTMODE_OUTBITVALUE,
+//!      - \b TIMER_A_OUTPUTMODE_SET,
+//!      - \b TIMER_A_OUTPUTMODE_TOGGLE_RESET,
+//!      - \b TIMER_A_OUTPUTMODE_SET_RESET
+//!      - \b TIMER_A_OUTPUTMODE_TOGGLE,
+//!      - \b TIMER_A_OUTPUTMODE_RESET,
+//!      - \b TIMER_A_OUTPUTMODE_TOGGLE_SET,
+//!      - \b TIMER_A_OUTPUTMODE_RESET_SET
+//! \param dutyCycle specifies the dutycycle for the generated waveform
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void Timer_A_generatePWM(uint32_t timer,
+                                const Timer_A_PWMConfig *config);
+
+//*****************************************************************************
+//
+//! Stops the timer
+//!
+//! \param timer is the instance of the Timer_A module. Valid parameters
+//! vary from part to part, but can include:
+//!         - \b TIMER_A0_MODULE
+//!         - \b TIMER_A1_MODULE
+//!         - \b TIMER_A2_MODULE
+//!         - \b TIMER_A3_MODULE
+//!
+//! \returns None
+//
+//*****************************************************************************
+extern void Timer_A_stopTimer(uint32_t timer);
+
+//*****************************************************************************
+//
+//! Sets the value of the capture-compare register
+//!
+//! \param timer is the instance of the Timer_A module. Valid parameters
+//! vary from part to part, but can include:
+//!         - \b TIMER_A0_MODULE
+//!         - \b TIMER_A1_MODULE
+//!         - \b TIMER_A2_MODULE
+//!         - \b TIMER_A3_MODULE
+//! \param compareRegister selects the Capture register being used. Valid
+//!     values are
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_0
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_1
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_2
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_3
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_4
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_5
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_6
+//!    <br>\n Refer to datasheet to ensure the device has the capture compare
+//!     register being used
+//! \param compareValue is the count to be compared with in compare mode
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void Timer_A_setCompareValue(uint32_t timer,
+        uint_fast16_t compareRegister, uint_fast16_t compareValue);
+
+//*****************************************************************************
+//
+//! Returns the current value of the specified timer. Note that according to
+//! the Timer A user guide, reading the value of the counter is unreliable
+//! if the system clock is asynchronous from the timer clock. The API addresses
+//! this concern by reading the timer count register twice and then determining
+//! the integrity of the value. If the two values are within 10 timer counts
+//! of each other, the value is deemed safe and returned. If not, the process
+//! is repeated until a reliable timer value is determined.
+//!
+//! \param timer is the instance of the Timer_A module. Valid parameters
+//! vary from part to part, but can include:
+//!         - \b TIMER_A0_MODULE
+//!         - \b TIMER_A1_MODULE
+//!         - \b TIMER_A2_MODULE
+//!         - \b TIMER_A3_MODULE
+//!
+//! \returns The value of the specified timer
+//
+//*****************************************************************************
+extern uint16_t Timer_A_getCounterValue(uint32_t timer);
+
+//*****************************************************************************
+//
+//! Clears the Timer TAIFG interrupt flag
+//!
+//! \param timer is the instance of the Timer_A module. Valid parameters
+//! vary from part to part, but can include:
+//!         - \b TIMER_A0_MODULE
+//!         - \b TIMER_A1_MODULE
+//!         - \b TIMER_A2_MODULE
+//!         - \b TIMER_A3_MODULE
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void Timer_A_clearInterruptFlag(uint32_t timer);
+
+//*****************************************************************************
+//
+//! Clears the capture-compare interrupt flag
+//!
+//! \param timer is the instance of the Timer_A module. Valid parameters
+//! vary from part to part, but can include:
+//!         - \b TIMER_A0_MODULE
+//!         - \b TIMER_A1_MODULE
+//!         - \b TIMER_A2_MODULE
+//!         - \b TIMER_A3_MODULE
+//! \param captureCompareRegister selects the Capture-compare register being
+//! used. Valid values are
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_0
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_1
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_2
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_3
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_4
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_5
+//!   - \b TIMER_A_CAPTURECOMPARE_REGISTER_6
+//!    <br>Refer to the datasheet to ensure the device has the capture compare
+//!    register being used
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void Timer_A_clearCaptureCompareInterrupt(uint32_t timer,
+        uint_fast16_t captureCompareRegister);
+
+//*****************************************************************************
+//
+//! Enable timer interrupt
+//!
+//! \param timer is the instance of the Timer_A module. Valid parameters
+//! vary from part to part, but can include:
+//!         - \b TIMER_A0_MODULE
+//!         - \b TIMER_A1_MODULE
+//!         - \b TIMER_A2_MODULE
+//!         - \b TIMER_A3_MODULE
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void Timer_A_enableInterrupt(uint32_t timer);
+
+//*****************************************************************************
+//
+//! Disable timer interrupt
+//!
+//! \param timer is the instance of the Timer_A module. Valid parameters
+//! vary from part to part, but can include:
+//!         - \b TIMER_A0_MODULE
+//!         - \b TIMER_A1_MODULE
+//!         - \b TIMER_A2_MODULE
+//!         - \b TIMER_A3_MODULE
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void Timer_A_disableInterrupt(uint32_t timer);
+
+//*****************************************************************************
+//
+//! Get timer interrupt status
+//!
+//! \param timer is the instance of the Timer_A module. Valid parameters
+//! vary from part to part, but can include:
+//!         - \b TIMER_A0_MODULE
+//!         - \b TIMER_A1_MODULE
+//!         - \b TIMER_A2_MODULE
+//!         - \b TIMER_A3_MODULE
+//!
+//! \return uint32_t. Return interrupt status. Valid values are
+//!       - \b TIMER_A_INTERRUPT_PENDING
+//!       - \b TIMER_A_INTERRUPT_NOT_PENDING
+//
+//*****************************************************************************
+extern uint32_t Timer_A_getInterruptStatus(uint32_t timer);
+
+//*****************************************************************************
+//
+//! Get timer interrupt status masked with the enabled interrupts.
+//! This function is useful to call in ISRs to get a list of pending
+//! interrupts that are actually enabled and could have caused
+//! the ISR.
+//!
+//! \param timer is the instance of the Timer_A module. Valid parameters
+//! vary from part to part, but can include:
+//!         - \b TIMER_A0_MODULE
+//!         - \b TIMER_A1_MODULE
+//!         - \b TIMER_A2_MODULE
+//!         - \b TIMER_A3_MODULE
+//!
+//! \return uint32_t. Return interrupt status. Valid values are
+//!       - \b TIMER_A_INTERRUPT_PENDING
+//!       - \b TIMER_A_INTERRUPT_NOT_PENDING
+//
+//*****************************************************************************
+extern uint32_t Timer_A_getEnabledInterruptStatus(uint32_t timer);
+
+//*****************************************************************************
+//
+//! Enable capture compare interrupt
+//!
+//! \param timer is the instance of the Timer_A module. Valid parameters
+//! vary from part to part, but can include:
+//!         - \b TIMER_A0_MODULE
+//!         - \b TIMER_A1_MODULE
+//!         - \b TIMER_A2_MODULE
+//!         - \b TIMER_A3_MODULE
+//! \param captureCompareRegister is the selected capture compare register
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void Timer_A_enableCaptureCompareInterrupt(uint32_t timer,
+        uint_fast16_t captureCompareRegister);
+
+//*****************************************************************************
+//
+//! Disable capture compare interrupt
+//!
+//! \param timer is the instance of the Timer_A module. Valid parameters
+//! vary from part to part, but can include:
+//!         - \b TIMER_A0_MODULE
+//!         - \b TIMER_A1_MODULE
+//!         - \b TIMER_A2_MODULE
+//!         - \b TIMER_A3_MODULE
+//! \param captureCompareRegister is the selected capture compare register
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void Timer_A_disableCaptureCompareInterrupt(uint32_t timer,
+        uint_fast16_t captureCompareRegister);
+
+//*****************************************************************************
+//
+//! Return capture compare interrupt status
+//!
+//! \param timer is the instance of the Timer_A module. Valid parameters
+//! vary from part to part, but can include:
+//!         - \b TIMER_A0_MODULE
+//!         - \b TIMER_A1_MODULE
+//!         - \b TIMER_A2_MODULE
+//!         - \b TIMER_A3_MODULE
+//! \param captureCompareRegister is the selected capture compare register
+//!
+//! \param mask is the mask for the interrupt status
+//!        Mask value is the logical OR of any of the following:
+//!        - \b TIMER_A_CAPTURE_OVERFLOW
+//!        - \b TIMER_A_CAPTURECOMPARE_INTERRUPT_FLAG
+//!
+//! \returns uint32_t. The mask of the set flags.
+//!         Valid values is an OR of
+//!       - \b TIMER_A_CAPTURE_OVERFLOW,
+//!       - \b TIMER_A_CAPTURECOMPARE_INTERRUPT_FLAG
+//
+//*****************************************************************************
+uint32_t Timer_A_getCaptureCompareInterruptStatus(uint32_t timer,
+        uint_fast16_t captureCompareRegister, uint_fast16_t mask);
+
+//*****************************************************************************
+//
+//! Return capture compare interrupt status masked with the enabled interrupts.
+//! This function is useful to call in ISRs to get a list of pending
+//! interrupts that are actually enabled and could have caused
+//! the ISR.
+//!
+//! \param timer is the instance of the Timer_A module. Valid parameters
+//! vary from part to part, but can include:
+//!         - \b TIMER_A0_MODULE
+//!         - \b TIMER_A1_MODULE
+//!         - \b TIMER_A2_MODULE
+//!         - \b TIMER_A3_MODULE
+//! \param captureCompareRegister is the selected capture compare register
+//!
+//! \returns uint32_t. The mask of the set flags.
+//!         Valid values is an OR of
+//!       - \b TIMER_A_CAPTURE_OVERFLOW,
+//!       - \b TIMER_A_CAPTURECOMPARE_INTERRUPT_FLAG
+//
+//*****************************************************************************
+extern uint32_t Timer_A_getCaptureCompareEnabledInterruptStatus(uint32_t timer,
+        uint_fast16_t captureCompareRegister);
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the timer capture compare interrupt.
+//!
+//! \param timer is the instance of the Timer_A module. Valid parameters
+//! vary from part to part, but can include:
+//!         - \b TIMER_A0_MODULE
+//!         - \b TIMER_A1_MODULE
+//!         - \b TIMER_A2_MODULE
+//!         - \b TIMER_A3_MODULE
+//!
+//! \param interruptSelect Selects which timer interrupt handler to
+//! register. For the timer module, there are two separate interrupt handlers
+//! that can be registered:
+//!         - \b TIMER_A_CCR0_INTERRUPT Corresponds to the interrupt for CCR0
+//!         - \b TIMER_A_CCRX_AND_OVERFLOW_INTERRUPT Corresponds to the
+//!          interrupt for CCR1-6, as well as the overflow interrupt.
+//!
+//! \param intHandler is a pointer to the function to be called when the
+//! timer capture compare interrupt occurs.
+//!
+//! This function registers the handler to be called when a timer
+//! interrupt occurs. This function enables the global interrupt in the
+//! interrupt controller; specific Timer_Ainterrupts must be enabled
+//! via Timer_A_enableInterrupt().  It is the interrupt handler's
+//! responsibility to clear the interrupt source
+//! via Timer_A_clearCaptureCompareInterrupt().
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void Timer_A_registerInterrupt(uint32_t timer,
+        uint_fast8_t interruptSelect, void (*intHandler)(void));
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the timer
+//!
+//! \param timer is the instance of the Timer_A module. Valid parameters
+//! vary from part to part, but can include:
+//!         - \b TIMER_A0_MODULE
+//!         - \b TIMER_A1_MODULE
+//!         - \b TIMER_A2_MODULE
+//!         - \b TIMER_A3_MODULE
+//!
+//! \param interruptSelect Selects which timer interrupt handler to
+//! register. For the timer module, there are two separate interrupt handlers
+//! that can be registered:
+//!         - \b TIMER_A_CCR0_INTERRUPT Corresponds to the interrupt for CCR0
+//!         - \b TIMER_A_CCRX_AND_OVERFLOW_INTERRUPT Corresponds to the
+//!          interrupt for CCR1-6, as well as the overflow interrupt.
+//!
+//! This function unregisters the handler to be called when timer
+//! interrupt occurs.  This function also masks off the interrupt in the
+//! interrupt controller so that the interrupt handler no longer is called.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void Timer_A_unregisterInterrupt(uint32_t timer,
+        uint_fast8_t interruptSelect);
+
+/* Backwards Compatibility Layer */
+#define TIMER_A_startCounter Timer_A_startCounter
+#define TIMER_A_clearTimerInterruptFlag Timer_A_clearInterruptFlag
+#define TIMER_A_clearCaptureCompareInterruptFlag Timer_A_clearCaptureCompareInterrupt
+#define TIMER_A_getCounterValue Timer_A_getCounterValue
+#define TIMER_A_setCompareValue Timer_A_setCompareValue
+#define TIMER_A_stop Timer_A_stopTimer
+#define TIMER_A_setOutputForOutputModeOutBitValue Timer_A_setOutputForOutputModeOutBitValue
+#define TIMER_A_enableInterrupt Timer_A_enableInterrupt
+#define TIMER_A_disableInterrupt Timer_A_disableInterrupt
+#define TIMER_A_getInterruptStatus Timer_A_getInterruptStatus
+#define TIMER_A_enableCaptureCompareInterrupt Timer_A_enableCaptureCompareInterrupt
+#define TIMER_A_disableCaptureCompareInterrupt Timer_A_disableCaptureCompareInterrupt
+#define TIMER_A_getCaptureCompareInterruptStatus Timer_A_getCaptureCompareInterruptStatus
+#define TIMER_A_clear Timer_A_clearTimer
+#define TIMER_A_getSynchronizedCaptureCompareInput Timer_A_getSynchronizedCaptureCompareInput
+#define TIMER_A_getCaptureCompareCount  Timer_A_getCaptureCompareCount
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif /* TIMERA_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/uart.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/uart.c
new file mode 100644
index 000000000..a3fb2ea71
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/uart.c
@@ -0,0 +1,396 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#include <uart.h>
+#include <interrupt.h>
+#include <debug.h>
+#include <eusci.h>
+
+bool UART_initModule(uint32_t moduleInstance, const eUSCI_UART_Config *config)
+{
+    bool retVal = true;
+
+    ASSERT(
+            (EUSCI_A_UART_MODE == config->uartMode)
+            || (EUSCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE
+                    == config->uartMode)
+            || (EUSCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE
+                    == config->uartMode)
+            || (EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE
+                    == config->uartMode));
+
+    ASSERT(
+            (EUSCI_A_UART_CLOCKSOURCE_ACLK == config->selectClockSource)
+            || (EUSCI_A_UART_CLOCKSOURCE_SMCLK
+                    == config->selectClockSource));
+
+    ASSERT(
+            (EUSCI_A_UART_MSB_FIRST == config->msborLsbFirst)
+            || (EUSCI_A_UART_LSB_FIRST == config->msborLsbFirst));
+
+    ASSERT(
+            (EUSCI_A_UART_ONE_STOP_BIT == config->numberofStopBits)
+            || (EUSCI_A_UART_TWO_STOP_BITS == config->numberofStopBits));
+
+    ASSERT(
+            (EUSCI_A_UART_NO_PARITY == config->parity)
+            || (EUSCI_A_UART_ODD_PARITY == config->parity)
+            || (EUSCI_A_UART_EVEN_PARITY == config->parity));
+
+    /* Disable the USCI Module */
+    BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
+
+    /* Clock source select */
+    EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r =
+            (EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r & ~UCSSEL_3)
+                    | config->selectClockSource;
+
+    /* MSB, LSB select */
+    if (config->msborLsbFirst)
+        BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCMSB_OFS) = 1;
+    else
+        BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCMSB_OFS) = 0;
+
+    /* UCSPB = 0(1 stop bit) OR 1(2 stop bits) */
+    if (config->numberofStopBits)
+        BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCSPB_OFS) = 1;
+    else
+        BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCSPB_OFS) = 0;
+
+    /* Parity */
+    switch (config->parity)
+    {
+    case EUSCI_A_UART_NO_PARITY:
+        BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCPEN_OFS) = 0;
+        break;
+    case EUSCI_A_UART_ODD_PARITY:
+        BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCPEN_OFS) = 1;
+        BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCPAR_OFS) = 0;
+        break;
+    case EUSCI_A_UART_EVEN_PARITY:
+        BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCPEN_OFS) = 1;
+        BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCPAR_OFS) = 1;
+        break;
+    }
+
+    /* BaudRate Control Register */
+    EUSCI_A_CMSIS(moduleInstance)->rBRW = config->clockPrescalar;
+    EUSCI_A_CMSIS(moduleInstance)->rMCTLW.r = ((config->secondModReg << 8)
+            + (config->firstModReg << 4) + config->overSampling);
+
+    /* Asynchronous mode & 8 bit character select & clear mode */
+    EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r =
+            (EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r
+                    & ~(UCSYNC | UC7BIT | UCMODE_3 | UCRXEIE | UCBRKIE | UCDORM
+                            | UCTXADDR | UCTXBRK)) | config->uartMode;
+
+    return retVal;
+}
+
+void UART_transmitData(uint32_t moduleInstance, uint_fast8_t transmitData)
+{
+    /* If interrupts are not used, poll for flags */
+    if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
+        while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
+            ;
+
+    EUSCI_A_CMSIS(moduleInstance)->rTXBUF.r = transmitData;
+}
+
+uint8_t UART_receiveData(uint32_t moduleInstance)
+{
+    /* If interrupts are not used, poll for flags */
+    if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rIE.r, UCRXIE_OFS))
+        while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rIFG.r, UCRXIFG_OFS))
+            ;
+
+    return EUSCI_A_CMSIS(moduleInstance)->rRXBUF.r;
+}
+
+void UART_enableModule(uint32_t moduleInstance)
+{
+    /* Reset the UCSWRST bit to enable the USCI Module */
+    BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 0;
+}
+
+void UART_disableModule(uint32_t moduleInstance)
+{
+    /* Set the UCSWRST bit to disable the USCI Module */
+    BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
+}
+
+uint_fast8_t UART_queryStatusFlags(uint32_t moduleInstance, uint_fast8_t mask)
+{
+    ASSERT(
+            0x00 != mask
+            && (EUSCI_A_UART_LISTEN_ENABLE + EUSCI_A_UART_FRAMING_ERROR
+                    + EUSCI_A_UART_OVERRUN_ERROR
+                    + EUSCI_A_UART_PARITY_ERROR
+                    + EUSCI_A_UART_BREAK_DETECT
+                    + EUSCI_A_UART_RECEIVE_ERROR
+                    + EUSCI_A_UART_ADDRESS_RECEIVED
+                    + EUSCI_A_UART_IDLELINE + EUSCI_A_UART_BUSY));
+
+    return EUSCI_A_CMSIS(moduleInstance)->rSTATW.r & mask;
+}
+
+void UART_setDormant(uint32_t moduleInstance)
+{
+    BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCDORM_OFS) = 1;
+}
+
+void UART_resetDormant(uint32_t moduleInstance)
+{
+    BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCDORM_OFS) = 0;
+}
+
+void UART_transmitAddress(uint32_t moduleInstance, uint_fast8_t transmitAddress)
+{
+    /* Set UCTXADDR bit */
+    BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCTXADDR_OFS) = 1;
+
+    /* Place next byte to be sent into the transmit buffer */
+    EUSCI_A_CMSIS(moduleInstance)->rTXBUF.r = transmitAddress;
+}
+
+void UART_transmitBreak(uint32_t moduleInstance)
+{
+    /* Set UCTXADDR bit */
+    BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCTXBRK_OFS) = 1;
+
+    /* If current mode is automatic baud-rate detection */
+    if (EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE
+            == (EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r
+                    & EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE))
+        EUSCI_A_CMSIS(moduleInstance)->rTXBUF.r =
+        EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC;
+    else
+        EUSCI_A_CMSIS(moduleInstance)->rTXBUF.r = DEFAULT_SYNC;
+
+    /* If interrupts are not used, poll for flags */
+    if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
+        while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
+            ;
+}
+
+uint32_t UART_getReceiveBufferAddressForDMA(uint32_t moduleInstance)
+{
+    return moduleInstance + OFS_UCA0RXBUF;
+}
+
+uint32_t UART_getTransmitBufferAddressForDMA(uint32_t moduleInstance)
+{
+    return moduleInstance + OFS_UCA0TXBUF;
+}
+
+void UART_selectDeglitchTime(uint32_t moduleInstance, uint32_t deglitchTime)
+{
+    ASSERT(
+            (EUSCI_A_UART_DEGLITCH_TIME_2ns == deglitchTime)
+            || (EUSCI_A_UART_DEGLITCH_TIME_50ns == deglitchTime)
+            || (EUSCI_A_UART_DEGLITCH_TIME_100ns == deglitchTime)
+            || (EUSCI_A_UART_DEGLITCH_TIME_200ns == deglitchTime));
+
+    EUSCI_A_CMSIS(moduleInstance)->rCTLW1.r =
+            (EUSCI_A_CMSIS(moduleInstance)->rCTLW1.r & ~(UCGLIT_M))
+                    | deglitchTime;
+
+}
+
+void UART_enableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
+{
+    uint8_t locMask;
+
+    ASSERT(
+            !(mask
+                    & ~(EUSCI_A_UART_RECEIVE_INTERRUPT
+                            | EUSCI_A_UART_TRANSMIT_INTERRUPT
+                            | EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
+                            | EUSCI_A_UART_BREAKCHAR_INTERRUPT
+                            | EUSCI_A_UART_STARTBIT_INTERRUPT
+                            | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT)));
+
+    locMask = (mask
+            & (EUSCI_A_UART_RECEIVE_INTERRUPT | EUSCI_A_UART_TRANSMIT_INTERRUPT
+                    | EUSCI_A_UART_STARTBIT_INTERRUPT
+                    | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT));
+
+    EUSCI_A_CMSIS(moduleInstance)->rIE.r |= locMask;
+
+    locMask = (mask
+            & (EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
+                    | EUSCI_A_UART_BREAKCHAR_INTERRUPT));
+    EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r |= locMask;
+}
+
+void UART_disableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
+{
+    uint8_t locMask;
+
+    ASSERT(
+            !(mask
+                    & ~(EUSCI_A_UART_RECEIVE_INTERRUPT
+                            | EUSCI_A_UART_TRANSMIT_INTERRUPT
+                            | EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
+                            | EUSCI_A_UART_BREAKCHAR_INTERRUPT
+                            | EUSCI_A_UART_STARTBIT_INTERRUPT
+                            | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT)));
+
+    locMask = (mask
+            & (EUSCI_A_UART_RECEIVE_INTERRUPT | EUSCI_A_UART_TRANSMIT_INTERRUPT
+                    | EUSCI_A_UART_STARTBIT_INTERRUPT
+                    | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT));
+    EUSCI_A_CMSIS(moduleInstance)->rIE.r &= ~locMask;
+
+    locMask = (mask
+            & (EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
+                    | EUSCI_A_UART_BREAKCHAR_INTERRUPT));
+    EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r &= ~locMask;
+}
+
+uint_fast8_t UART_getInterruptStatus(uint32_t moduleInstance, uint8_t mask)
+{
+    ASSERT(
+            !(mask
+                    & ~(EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG
+                            | EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG
+                            | EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG
+                            | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG)));
+
+    return EUSCI_A_CMSIS(moduleInstance)->rIFG.r & mask;
+}
+
+uint_fast8_t UART_getEnabledInterruptStatus(uint32_t moduleInstance)
+{
+    uint_fast8_t intStatus = UART_getInterruptStatus(moduleInstance,
+    EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG | EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG);
+    uint_fast8_t intEnabled = EUSCI_A_CMSIS(moduleInstance)->rIE.r;
+
+    if (!(intEnabled & EUSCI_A_UART_RECEIVE_INTERRUPT))
+    {
+        intStatus &= ~EUSCI_A_UART_RECEIVE_INTERRUPT;
+    }
+
+    if (!(intEnabled & EUSCI_A_UART_TRANSMIT_INTERRUPT))
+    {
+        intStatus &= ~EUSCI_A_UART_TRANSMIT_INTERRUPT;
+    }
+
+    intEnabled = EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r;
+
+    if (!(intEnabled & EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT))
+    {
+        intStatus &= ~EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT;
+    }
+
+    if (!(intEnabled & EUSCI_A_UART_BREAKCHAR_INTERRUPT))
+    {
+        intStatus &= ~EUSCI_A_UART_BREAKCHAR_INTERRUPT;
+    }
+
+    return intStatus;
+}
+
+void UART_clearInterruptFlag(uint32_t moduleInstance, uint_fast8_t mask)
+{
+    ASSERT(
+            !(mask
+                    & ~(EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG
+                            | EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG
+                            | EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG
+                            | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG)));
+
+    //Clear the UART interrupt source.
+    EUSCI_A_CMSIS(moduleInstance)->rIFG.r &= ~(mask);
+}
+
+void UART_registerInterrupt(uint32_t moduleInstance, void (*intHandler)(void))
+{
+    switch (moduleInstance)
+    {
+    case EUSCI_A0_MODULE:
+        Interrupt_registerInterrupt(INT_EUSCIA0, intHandler);
+        Interrupt_enableInterrupt(INT_EUSCIA0);
+        break;
+    case EUSCI_A1_MODULE:
+        Interrupt_registerInterrupt(INT_EUSCIA1, intHandler);
+        Interrupt_enableInterrupt(INT_EUSCIA1);
+        break;
+#ifdef EUSCI_A2_MODULE
+    case EUSCI_A2_MODULE:
+        Interrupt_registerInterrupt(INT_EUSCIA2, intHandler);
+        Interrupt_enableInterrupt(INT_EUSCIA2);
+        break;
+#endif
+#ifdef EUSCI_A3_MODULE
+    case EUSCI_A3_MODULE:
+        Interrupt_registerInterrupt(INT_EUSCIA3, intHandler);
+        Interrupt_enableInterrupt(INT_EUSCIA3);
+        break;
+#endif
+    default:
+        ASSERT(false);
+    }
+}
+
+void UART_unregisterInterrupt(uint32_t moduleInstance)
+{
+    switch (moduleInstance)
+    {
+    case EUSCI_A0_MODULE:
+        Interrupt_disableInterrupt(INT_EUSCIA0);
+        Interrupt_unregisterInterrupt(INT_EUSCIA0);
+        break;
+    case EUSCI_A1_MODULE:
+        Interrupt_disableInterrupt(INT_EUSCIA1);
+        Interrupt_unregisterInterrupt(INT_EUSCIA1);
+        break;
+#ifdef EUSCI_A2_MODULE
+    case EUSCI_A2_MODULE:
+        Interrupt_disableInterrupt(INT_EUSCIA2);
+        Interrupt_unregisterInterrupt(INT_EUSCIA2);
+        break;
+#endif
+#ifdef EUSCI_A3_MODULE
+    case EUSCI_A3_MODULE:
+        Interrupt_disableInterrupt(INT_EUSCIA3);
+        Interrupt_unregisterInterrupt(INT_EUSCIA3);
+        break;
+#endif
+    default:
+        ASSERT(false);
+    }
+}
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/uart.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/uart.h
new file mode 100644
index 000000000..d9f9899b6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/uart.h
@@ -0,0 +1,760 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef UART_H_
+#define UART_H_
+
+//*****************************************************************************
+//
+//! \addtogroup uart_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include <msp.h>
+#include "eusci.h"
+
+#define DEFAULT_SYNC                                                       0x00
+#define EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC                                0x55
+
+#define EUSCI_A_UART_NO_PARITY                                             0x00
+#define EUSCI_A_UART_ODD_PARITY                                            0x01
+#define EUSCI_A_UART_EVEN_PARITY                                           0x02
+
+#define EUSCI_A_UART_MSB_FIRST                                            UCMSB
+#define EUSCI_A_UART_LSB_FIRST                                             0x00
+
+#define EUSCI_A_UART_MODE                                              UCMODE_0
+#define EUSCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE                    UCMODE_1
+#define EUSCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE                  UCMODE_2
+#define EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE                 UCMODE_3
+
+#define EUSCI_A_UART_CLOCKSOURCE_SMCLK                            UCSSEL__SMCLK
+#define EUSCI_A_UART_CLOCKSOURCE_ACLK                              UCSSEL__ACLK
+
+#define EUSCI_A_UART_ONE_STOP_BIT                                          0x00
+#define EUSCI_A_UART_TWO_STOP_BITS                                        UCSPB
+
+#define EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION                      0x01
+#define EUSCI_A_UART_LOW_FREQUENCY_BAUDRATE_GENERATION                     0x00
+
+#define EUSCI_A_UART_RECEIVE_INTERRUPT                                   UCRXIE
+#define EUSCI_A_UART_TRANSMIT_INTERRUPT                                  UCTXIE
+#define EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT                    UCRXEIE
+#define EUSCI_A_UART_BREAKCHAR_INTERRUPT                                UCBRKIE
+#define EUSCI_A_UART_STARTBIT_INTERRUPT                                 UCSTTIE
+#define EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT                      UCTXCPTIE
+
+#define EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG                             UCRXIFG
+#define EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG                            UCTXIFG
+#define EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG                           UCSTTIFG
+#define EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG                UCTXCPTIFG
+
+#define EUSCI_A_UART_LISTEN_ENABLE                                     UCLISTEN
+#define EUSCI_A_UART_FRAMING_ERROR                                         UCFE
+#define EUSCI_A_UART_OVERRUN_ERROR                                         UCOE
+#define EUSCI_A_UART_PARITY_ERROR                                          UCPE
+#define EUSCI_A_UART_BREAK_DETECT                                         UCBRK
+#define EUSCI_A_UART_RECEIVE_ERROR                                      UCRXERR
+#define EUSCI_A_UART_ADDRESS_RECEIVED                                    UCADDR
+#define EUSCI_A_UART_IDLELINE                                            UCIDLE
+#define EUSCI_A_UART_BUSY                                                UCBUSY
+
+#define EUSCI_A_UART_DEGLITCH_TIME_2ns                                     0x00
+#define EUSCI_A_UART_DEGLITCH_TIME_50ns                                 0x0001
+#define EUSCI_A_UART_DEGLITCH_TIME_100ns                                0x0002
+#define EUSCI_A_UART_DEGLITCH_TIME_200ns                    (0x0001 + 0x0002)
+
+//*****************************************************************************
+//
+//! \typedef eUSCI_eUSCI_UART_Config
+//! \brief Type definition for \link _eUSCI_UART_Config \endlink
+//!     structure
+//!
+//! \struct _eUSCI_eUSCI_UART_Config
+//! \brief Configuration structure for compare mode in the \b UART module. See
+//!          \link UART_initModule \endlink for parameter
+//!                 documentation.
+//
+//*****************************************************************************
+typedef struct _eUSCI_eUSCI_UART_Config
+{
+    uint_fast8_t selectClockSource;
+    uint_fast16_t clockPrescalar;
+    uint_fast8_t firstModReg;
+    uint_fast8_t secondModReg;
+    uint_fast8_t parity;
+    uint_fast16_t msborLsbFirst;
+    uint_fast16_t numberofStopBits;
+    uint_fast16_t uartMode;
+    uint_fast8_t overSampling;
+} eUSCI_UART_Config;
+
+//*****************************************************************************
+//
+//! Initialization routine for the UART block. The values to be written
+//! into the UCAxBRW and UCAxMCTLW registers should be pre-computed and passed
+//! into the initialization function
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//! \param config Configuration structure for the UART module
+//!
+//! <hr>
+//! <b>Configuration options for \link eUSCI_UART_Config \endlink
+//!         structure.</b>
+//! <hr>
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode.
+//! \param selectClockSource selects Clock source. Valid values are
+//!       - \b EUSCI_A_UART_CLOCKSOURCE_SMCLK
+//!       - \b EUSCI_A_UART_CLOCKSOURCE_ACLK
+//! \param clockPrescalar is the value to be written into UCBRx bits
+//! \param firstModReg  is First modulation stage register setting. This
+//!     value is a pre-calculated value which can be obtained from the Device
+//!     User Guide.This value is written into UCBRFx bits of UCAxMCTLW.
+//! \param secondModReg is Second modulation stage register setting.
+//!     This value is a pre-calculated value which can be obtained from the
+//!     Device User Guide. This value is written into UCBRSx bits of
+//!     UCAxMCTLW.
+//! \param parity is the desired parity. Valid values are
+//!      - \b EUSCI_A_UART_NO_PARITY  [Default Value],
+//!      - \b EUSCI_A_UART_ODD_PARITY,
+//!      - \b EUSCI_A_UART_EVEN_PARITY
+//! \param msborLsbFirst controls direction of receive and transmit shift
+//!     register. Valid values are
+//!      - \b EUSCI_A_UART_MSB_FIRST
+//!      - \b EUSCI_A_UART_LSB_FIRST [Default Value]
+//! \param numberofStopBits indicates one/two STOP bits
+//!      Valid values are
+//!      - \b EUSCI_A_UART_ONE_STOP_BIT [Default Value]
+//!      - \b EUSCI_A_UART_TWO_STOP_BITS
+//! \param uartMode selects the mode of operation
+//!      Valid values are
+//!      - \b EUSCI_A_UART_MODE  [Default Value],
+//!      - \b EUSCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE,
+//!      - \b EUSCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE,
+//!      - \b EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE
+//! \param overSampling indicates low frequency or oversampling baud
+//!      generation
+//!     Valid values are
+//!      - \b EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION
+//!      - \b EUSCI_A_UART_LOW_FREQUENCY_BAUDRATE_GENERATION
+//!
+//! Upon successful initialization of the UART block, this function
+//! will have initialized the module, but the UART block still remains
+//! disabled and must be enabled with UART_enableModule()
+//!
+//! Refer to
+//! <a href="http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSP430BaudRateConverter/index.html">
+//! this calculator </a> for help on calculating values for the parameters.
+//!
+//! Modified bits are \b UCPEN, \b UCPAR, \b UCMSB, \b UC7BIT, \b UCSPB,
+//! \b UCMODEx, \b UCSYNC bits of \b UCAxCTL0 and \b UCSSELx,
+//! \b UCSWRST bits of \b UCAxCTL1
+//!
+//! \return true or
+//!         STATUS_FAIL of the initialization process
+//
+//*****************************************************************************
+extern bool UART_initModule(uint32_t moduleInstance,
+        const eUSCI_UART_Config *config);
+
+//*****************************************************************************
+//
+//! Transmits a byte from the UART Module.
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode
+//! \param transmitData data to be transmitted from the UART module
+//!
+//! This function will place the supplied data into UART transmit data register
+//! to start transmission
+//!
+//! Modified register is \b UCAxTXBUF
+//! \return None.
+//
+//*****************************************************************************
+extern void UART_transmitData(uint32_t moduleInstance,
+        uint_fast8_t transmitData);
+
+//*****************************************************************************
+//
+//! Receives a byte that has been sent to the UART Module.
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as  EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode
+//!
+//! This function reads a byte of data from the UART receive data Register.
+//!
+//! Modified register is \b UCAxRXBUF
+//!
+//! \return Returns the byte received from by the UART module, cast as an
+//! uint8_t.
+//
+//*****************************************************************************
+extern uint8_t UART_receiveData(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Enables the UART block.
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode
+//!
+//! This will enable operation of the UART block.
+//!
+//! Modified register is \b UCAxCTL1
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void UART_enableModule(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Disables the UART block.
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode
+//!
+//! This will disable operation of the UART block.
+//!
+//! Modified register is \b UCAxCTL1
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void UART_disableModule(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Gets the current UART status flags.
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode
+//! \param mask is the masked interrupt flag status to be returned.
+//!
+//! This returns the status for the UART  module based on which
+//! flag is passed. mask parameter can be either any of the following
+//! selection.
+//! - \b EUSCI_A_UART_LISTEN_ENABLE
+//! - \b EUSCI_A_UART_FRAMING_ERROR
+//! - \b EUSCI_A_UART_OVERRUN_ERROR
+//! - \b EUSCI_A_UART_PARITY_ERROR
+//! - \b eUARTBREAK_DETECT
+//! - \b EUSCI_A_UART_RECEIVE_ERROR
+//! - \b EUSCI_A_UART_ADDRESS_RECEIVED
+//! - \b EUSCI_A_UART_IDLELINE
+//! - \b EUSCI_A_UART_BUSY
+//!
+//! Modified register is \b UCAxSTAT
+//!
+//! \return the masked status flag
+//
+//*****************************************************************************
+extern uint_fast8_t UART_queryStatusFlags(uint32_t moduleInstance,
+        uint_fast8_t mask);
+
+//*****************************************************************************
+//
+//! Sets the UART module in dormant mode
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode
+//!
+//! Puts USCI in sleep mode
+//! Only characters that are preceded by an idle-line or with address bit set
+//! UCRXIFG. In UART mode with automatic baud-rate detection, only the
+//! combination of a break and synch field sets UCRXIFG.
+//!
+//! Modified register is \b UCAxCTL1
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void UART_setDormant(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Re-enables UART module from dormant mode
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode
+//!
+//! Not dormant. All received characters set UCRXIFG.
+//!
+//! Modified bits are \b UCDORM of \b UCAxCTL1 register.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void UART_resetDormant(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Transmits the next byte to be transmitted marked as address depending on
+//! selected multiprocessor mode
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode
+//! \param transmitAddress is the next byte to be transmitted
+//!
+//! Modified register is \b UCAxCTL1, \b UCAxTXBUF
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void UART_transmitAddress(uint32_t moduleInstance,
+        uint_fast8_t transmitAddress);
+
+//*****************************************************************************
+//
+//! Transmit break. Transmits a break with the next write to the transmit
+//! buffer. In UART mode with automatic baud-rate detection,
+//! EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC(0x55) must be written into UCAxTXBUF to
+//! generate the required break/synch fields.
+//! Otherwise, DEFAULT_SYNC(0x00) must be written into the transmit buffer.
+//! Also ensures module is ready for transmitting the next data
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  asEUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode
+//!
+//! Modified register is \b UCAxCTL1, \b UCAxTXBUF
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void UART_transmitBreak(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Returns the address of the RX Buffer of the UART for the DMA module.
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode
+//!
+//! Returns the address of the UART RX Buffer. This can be used in conjunction
+//! with the DMA to store the received data directly to memory.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern uint32_t UART_getReceiveBufferAddressForDMA(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Returns the address of the TX Buffer of the UART for the DMA module.
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode
+//!
+//! Returns the address of the UART TX Buffer. This can be used in conjunction
+//! with the DMA to obtain transmitted data directly from memory.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern uint32_t UART_getTransmitBufferAddressForDMA(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Sets the deglitch time
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode
+//! \param deglitchTime is the selected deglitch time
+//!     Valid values are
+//!         - \b EUSCI_A_UART_DEGLITCH_TIME_2ns
+//!         - \b EUSCI_A_UART_DEGLITCH_TIME_50ns
+//!         - \b EUSCI_A_UART_DEGLITCH_TIME_100ns
+//!         - \b EUSCI_A_UART_DEGLITCH_TIME_200ns
+//!
+//!
+//! Returns the address of the UART TX Buffer. This can be used in conjunction
+//! with the DMA to obtain transmitted data directly from memory.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void UART_selectDeglitchTime(uint32_t moduleInstance,
+        uint32_t deglitchTime);
+
+//*****************************************************************************
+//
+//! Enables individual UART interrupt sources.
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode
+//! \param mask is the bit mask of the interrupt sources to be enabled.
+//!
+//! Enables the indicated UART interrupt sources.  The interrupt flag is first
+//! and then the corresponding interrupt is enabled. Only the sources that
+//! are enabled can be reflected to the processor interrupt; disabled sources
+//! have no effect on the processor.
+//!
+//! The mask parameter is the logical OR of any of the following:
+//! - \b EUSCI_A_UART_RECEIVE_INTERRUPT -Receive interrupt
+//! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT - Transmit interrupt
+//! - \b EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT - Receive
+//!                             erroneous-character interrupt enable
+//! - \b EUSCI_A_UART_BREAKCHAR_INTERRUPT - Receive break character interrupt
+//!                                           enable
+//!
+//! Modified register is \b UCAxIFG, \b UCAxIE and \b UCAxCTL1
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void UART_enableInterrupt(uint32_t moduleInstance, uint_fast8_t mask);
+
+//*****************************************************************************
+//
+//! Disables individual UART interrupt sources.
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode
+//! \param mask is the bit mask of the interrupt sources to be
+//! disabled.
+//!
+//! Disables the indicated UART interrupt sources.  Only the sources that
+//! are enabled can be reflected to the processor interrupt; disabled sources
+//! have no effect on the processor.
+//!
+//! The mask parameter is the logical OR of any of the following:
+//! - \b EUSCI_A_UART_RECEIVE_INTERRUPT -Receive interrupt
+//! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT - Transmit interrupt
+//! - \b EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT - Receive
+//!                             erroneous-character interrupt enable
+//! - \b EUSCI_A_UART_BREAKCHAR_INTERRUPT - Receive break character interrupt
+//!                                             enable
+//!
+//! Modified register is \b UCAxIFG, \b UCAxIE and \b UCAxCTL1
+//! \return None.
+//
+//*****************************************************************************
+extern void UART_disableInterrupt(uint32_t moduleInstance, uint_fast8_t mask);
+
+//*****************************************************************************
+//
+//! Gets the current UART interrupt status.
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode
+//! \param mask is the masked interrupt flag status to be returned.
+//!        Mask value is the logical OR of any of the following:
+//!        - \b EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG
+//!        - \b EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG
+//!        - \b EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG
+//!        - \b EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG
+//!
+//!
+//! \return The current interrupt status as an ORed bit mask:
+//! - \b EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG -Receive interrupt flag
+//! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG - Transmit interrupt flag
+//
+//*****************************************************************************
+extern uint_fast8_t UART_getInterruptStatus(uint32_t moduleInstance,
+        uint8_t mask);
+
+//*****************************************************************************
+//
+//! Gets the current UART interrupt status masked with the enabled interrupts.
+//! This function is useful to call in ISRs to get a list of pending
+//! interrupts that are actually enabled and could have caused
+//! the ISR.
+
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode
+//!
+//! \return The current interrupt status as an ORed bit mask:
+//! - \b EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG -Receive interrupt flag
+//! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG - Transmit interrupt flag
+//
+//*****************************************************************************
+extern uint_fast8_t UART_getEnabledInterruptStatus(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Clears UART interrupt sources.
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode
+//! \param mask is a bit mask of the interrupt sources to be cleared.
+//!
+//! The UART interrupt source is cleared, so that it no longer asserts.
+//! The highest interrupt flag is automatically cleared when an interrupt vector
+//! generator is used.
+//!
+//! The mask parameter has the same definition as the mask parameter to
+//! EUSCI_A_UART_enableInterrupt().
+//!
+//! Modified register is \b UCAxIFG
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void UART_clearInterruptFlag(uint32_t moduleInstance, uint_fast8_t mask);
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for UART interrupts.
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode.
+//!
+//! \param intHandler is a pointer to the function to be called when the
+//! timer capture compare interrupt occurs.
+//!
+//! This function registers the handler to be called when an UART
+//! interrupt occurs. This function enables the global interrupt in the
+//! interrupt controller; specific UART interrupts must be enabled
+//! via UART_enableInterrupt().  It is the interrupt handler's responsibility to
+//! clear the interrupt source via UART_clearInterruptFlag().
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void UART_registerInterrupt(uint32_t moduleInstance,
+        void (*intHandler)(void));
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the UART module
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_MODULE
+//!         - \b EUSCI_A1_MODULE
+//!         - \b EUSCI_A2_MODULE
+//!         - \b EUSCI_A3_MODULE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode.
+//!
+//! This function unregisters the handler to be called when timer
+//! interrupt occurs.  This function also masks off the interrupt in the
+//! interrupt controller so that the interrupt handler no longer is called.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void UART_unregisterInterrupt(uint32_t moduleInstance);
+
+/* Backwards Compatibility Layer */
+#define EUSCI_A_UART_transmitData UART_transmitData
+#define EUSCI_A_UART_receiveData UART_receiveData
+#define EUSCI_A_UART_enableInterrupt UART_enableInterrupt
+#define EUSCI_A_UART_disableInterrupt UART_disableInterrupt
+#define EUSCI_A_UART_getInterruptStatus UART_getInterruptStatus
+#define EUSCI_A_UART_clearInterruptFlag UART_clearInterruptFlag
+#define EUSCI_A_UART_enable UART_enableModule
+#define EUSCI_A_UART_disable UART_disableModule
+#define EUSCI_A_UART_queryStatusFlags UART_queryStatusFlags
+#define EUSCI_A_UART_setDormant UART_setDormant
+#define EUSCI_A_UART_resetDormant UART_resetDormant
+#define EUSCI_A_UART_transmitAddress UART_transmitAddress
+#define EUSCI_A_UART_transmitBreak UART_transmitBreak
+#define EUSCI_A_UART_getReceiveBufferAddressForDMA UART_getReceiveBufferAddressForDMA
+#define EUSCI_A_UART_getTransmitBufferAddressForDMA UART_getTransmitBufferAddressForDMA
+#define EUSCI_A_UART_selectDeglitchTime UART_selectDeglitchTime
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif /* UART_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/wdt_a.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/wdt_a.c
new file mode 100644
index 000000000..b3b3b8591
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/wdt_a.c
@@ -0,0 +1,119 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+/* Standard Includes */
+#include <stdint.h>
+
+/* DriverLib Includes */
+#include <wdt_a.h>
+#include <debug.h>
+#include <interrupt.h>
+
+void WDT_A_holdTimer(void)
+{
+    //Set Hold bit
+    uint8_t newWDTStatus = (WDT_A->rCTL.r | WDTHOLD);
+
+    WDT_A->rCTL.r = WDTPW + newWDTStatus;
+}
+
+void WDT_A_startTimer(void)
+{
+    //Reset Hold bit
+    uint8_t newWDTStatus = (WDT_A->rCTL.r & ~(WDTHOLD));
+
+    WDT_A->rCTL.r = WDTPW + newWDTStatus;
+}
+
+void WDT_A_clearTimer(void)
+{
+    //Set Counter Clear bit
+    uint8_t newWDTStatus = (WDT_A->rCTL.r | WDTCNTCL);
+
+    WDT_A->rCTL.r = WDTPW + newWDTStatus;
+}
+
+void WDT_A_initWatchdogTimer(uint_fast8_t clockSelect,
+        uint_fast8_t clockIterations)
+{
+    WDT_A->rCTL.r = WDTPW + WDTCNTCL + WDTHOLD +
+            clockSelect + clockIterations;
+}
+
+void WDT_A_initIntervalTimer(uint_fast8_t clockSelect,
+        uint_fast8_t clockIterations)
+{
+
+    WDT_A->rCTL.r = WDTPW + WDTCNTCL + WDTHOLD + WDTTMSEL
+            + clockSelect + clockIterations;
+}
+
+void WDT_A_setPasswordViolationReset(uint_fast8_t resetType)
+{
+    SysCtl_setWDTPasswordViolationResetType(resetType);
+}
+
+void WDT_A_setTimeoutReset(uint_fast8_t resetType)
+{
+    SysCtl_setWDTTimeoutResetType(resetType);
+}
+
+void WDT_A_registerInterrupt(void (*intHandler)(void))
+{
+    //
+    // Register the interrupt handler, returning an error if an error occurs.
+    //
+    Interrupt_registerInterrupt(INT_WDT_A, intHandler);
+
+    //
+    // Enable the system control interrupt.
+    //
+    Interrupt_enableInterrupt (INT_WDT_A);
+}
+
+void WDT_A_unregisterInterrupt(void)
+{
+    //
+    // Disable the interrupt.
+    //
+    Interrupt_disableInterrupt (INT_WDT_A);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    Interrupt_unregisterInterrupt(INT_WDT_A);
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/wdt_a.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/wdt_a.h
new file mode 100644
index 000000000..3c215bd61
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/wdt_a.h
@@ -0,0 +1,296 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v01_04_00_18 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __WATCHDOG_H__
+#define __WATCHDOG_H__
+
+//*****************************************************************************
+//
+//! \addtogroup wdt_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <msp.h>
+#include <stdint.h>
+#include "sysctl.h"
+
+#define WDT_A_HARD_RESET SYSCTL_HARD_RESET
+#define WDT_A_SOFT_RESET SYSCTL_SOFT_RESET
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the clockSelect parameter for
+// functions: WDT_A_watchdogTimerInit(), and WDT_A_intervalTimerInit().
+//
+//*****************************************************************************
+#define WDT_A_CLOCKSOURCE_SMCLK                                     (WDTSSEL_0)
+#define WDT_A_CLOCKSOURCE_ACLK                                      (WDTSSEL_1)
+#define WDT_A_CLOCKSOURCE_VLOCLK                                    (WDTSSEL_2)
+#define WDT_A_CLOCKSOURCE_XCLK                                      (WDTSSEL_3)
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the clockDivider parameter
+// for functions: WDT_A_watchdogTimerInit(), and WDT_A_intervalTimerInit().
+//
+//*****************************************************************************
+#define WDT_A_CLOCKDIVIDER_2G                                         (WDTIS_0)
+#define WDT_A_CLOCKDIVIDER_128M                                       (WDTIS_1)
+#define WDT_A_CLOCKDIVIDER_8192K                                      (WDTIS_2)
+#define WDT_A_CLOCKDIVIDER_512K                                       (WDTIS_3)
+#define WDT_A_CLOCKDIVIDER_32K                                        (WDTIS_4)
+#define WDT_A_CLOCKDIVIDER_8192                                       (WDTIS_5)
+#define WDT_A_CLOCKDIVIDER_512                                        (WDTIS_6)
+#define WDT_A_CLOCKDIVIDER_64                                         (WDTIS_7)
+#define WDT_A_CLOCKITERATIONS_2G    WDT_A_CLOCKDIVIDER_2G
+#define WDT_A_CLOCKITERATIONS_128M  WDT_A_CLOCKDIVIDER_128M
+#define WDT_A_CLOCKITERATIONS_8192K WDT_A_CLOCKDIVIDER_8192K
+#define WDT_A_CLOCKITERATIONS_512K  WDT_A_CLOCKDIVIDER_512K
+#define WDT_A_CLOCKITERATIONS_32K   WDT_A_CLOCKDIVIDER_32K
+#define WDT_A_CLOCKITERATIONS_8192  WDT_A_CLOCKDIVIDER_8192
+#define WDT_A_CLOCKITERATIONS_512   WDT_A_CLOCKDIVIDER_512
+#define WDT_A_CLOCKITERATIONS_64    WDT_A_CLOCKDIVIDER_64
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! Holds the Watchdog Timer.
+//!
+//! This function stops the watchdog timer from running. This way no interrupt
+//! or PUC is asserted.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void WDT_A_holdTimer(void);
+
+//*****************************************************************************
+//
+//! Starts the Watchdog Timer.
+//!
+//! This function starts the watchdog timer functionality to start counting.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void WDT_A_startTimer(void);
+
+//*****************************************************************************
+//
+//! Clears the timer counter of the Watchdog Timer.
+//!
+//! This function clears the watchdog timer count to 0x0000h. This function
+//! is used to "service the dog" when operating in watchdog mode.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void WDT_A_clearTimer(void);
+
+//*****************************************************************************
+//
+//! Sets the clock source for the Watchdog Timer in watchdog mode.
+//!
+//! \param clockSelect is the clock source that the watchdog timer will use.
+//!        Valid values are
+//!        - \b WDT_A_CLOCKSOURCE_SMCLK [Default]
+//!        - \b WDT_A_CLOCKSOURCE_ACLK
+//!        - \b WDT_A_CLOCKSOURCE_VLOCLK
+//!        - \b WDT_A_CLOCKSOURCE_XCLK
+//! \param clockIterations is the number of clock iterations for a watchdog
+//!         timeout.
+//!        Valid values are
+//!        - \b WDT_A_CLOCKITERATIONS_2G [Default]
+//!        - \b WDT_A_CLOCKITERATIONS_128M
+//!        - \b WDT_A_CLOCKITERATIONS_8192K
+//!        - \b WDT_A_CLOCKITERATIONS_512K
+//!        - \b WDT_A_CLOCKITERATIONS_32K
+//!        - \b WDT_A_CLOCKITERATIONS_8192
+//!        - \b WDT_A_CLOCKITERATIONS_512
+//!        - \b WDT_A_CLOCKITERATIONS_64
+//!
+//! This function sets the watchdog timer in watchdog mode, which will cause a
+//! PUC when the timer overflows. When in the mode, a PUC can be avoided with a
+//! call to WDT_A_resetTimer() before the timer runs out.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void WDT_A_initWatchdogTimer(uint_fast8_t clockSelect,
+        uint_fast8_t clockDivider);
+
+//*****************************************************************************
+//
+//! Sets the clock source for the Watchdog Timer in timer interval mode.
+//!
+//! \param clockSelect is the clock source that the watchdog timer will use.
+//!        Valid values are
+//!        - \b WDT_A_CLOCKSOURCE_SMCLK [Default]
+//!        - \b WDT_A_CLOCKSOURCE_ACLK
+//!        - \b WDT_A_CLOCKSOURCE_VLOCLK
+//!        - \b WDT_A_CLOCKSOURCE_XCLK
+//! \param clockIterations is the number of clock iterations for a watchdog
+//!         interval.
+//!        Valid values are
+//!        - \b WDT_A_CLOCKITERATIONS_2G [Default]
+//!        - \b WDT_A_CLOCKITERATIONS_128M
+//!        - \b WDT_A_CLOCKITERATIONS_8192K
+//!        - \b WDT_A_CLOCKITERATIONS_512K
+//!        - \b WDT_A_CLOCKITERATIONS_32K
+//!        - \b WDT_A_CLOCKITERATIONS_8192
+//!        - \b WDT_A_CLOCKITERATIONS_512
+//!        - \b WDT_A_CLOCKITERATIONS_64
+//!
+//! This function sets the watchdog timer as timer interval mode, which will
+//! assert an interrupt without causing a PUC.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void WDT_A_initIntervalTimer(uint_fast8_t clockSelect,
+        uint_fast8_t clockDivider);
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the watchdog interrupt.
+//!
+//! \param intHandler is a pointer to the function to be called when the
+//! watchdog interrupt occurs.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void WDT_A_registerInterrupt(void (*intHandler)(void));
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the watchdog.
+//!
+//! This function unregisters the handler to be called when a watchdog
+//! interrupt occurs.  This function also masks off the interrupt in the
+//! interrupt controller so that the interrupt handler no longer is called.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void WDT_A_unregisterInterrupt(void);
+
+//*****************************************************************************
+//
+//! Sets the type of RESET that happens when a watchdog password violation
+//! occurs.
+//!
+//! \param resetType The type of reset to set
+//!
+//! The \e resetType parameter must be only one of the following values:
+//!     - \b WDT_A_HARD_RESET
+//!     - \b WDT_A_SOFT_RESET
+//!
+//! \return None.
+//
+//
+//*****************************************************************************
+extern void WDT_A_setPasswordViolationReset(uint_fast8_t resetType);
+
+//*****************************************************************************
+//
+//! Sets the type of RESET that happens when a watchdog timeout occurs.
+//!
+//! \param resetType The type of reset to set
+//!
+//! The \e resetType parameter must be only one of the following values:
+//!     - \b WDT_A_HARD_RESET
+//!     - \b WDT_A_SOFT_RESET
+//!
+//! \return None.
+//
+//
+//*****************************************************************************
+extern void WDT_A_setTimeoutReset(uint_fast8_t resetType);
+
+/* Defines for future devices that might have multiple instances */
+#define WDT_A_holdTimerMultipleTimer(a)  WDT_A_holdTimer()
+#define WDT_A_startTimerMultipleTimer(a) WDT_A_startTimer()
+#define WDT_A_resetTimerMultipleTimer(a) WDT_A_resetTimer()
+#define WDT_A_initWatchdogTimerMultipleTimer(a,b,c) WDT_A_initWatchdogTimer(b,c)
+#define WDT_A_initIntervalTimerMultipleTimer(a,b,c) WDT_A_initIntervalTimer(b,c)
+#define WDT_A_registerInterruptMultipleTimer(a,b) WDT_A_registerInterrupt(b)
+#define WDT_A_unregisterInterruptMultipleTimer(a) WDT_A_unregisterInterrupt()
+
+/* Backwards compatibility layer */
+#define WDT_A_hold WDT_A_holdTimerMultipleTimer
+#define WDT_A_start WDT_A_startTimerMultipleTimer
+#define WDT_A_resetTimer WDT_A_resetTimerMultipleTimer
+#define WDT_A_watchdogTimerInit WDT_A_initWatchdogTimerMultipleTimer
+#define WDT_A_intervalTimerInit WDT_A_initIntervalTimerMultipleTimer
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif // __WATCHDOG_H__
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/main.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/main.c
new file mode 100644
index 000000000..926cc6f4e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/main.c
@@ -0,0 +1,212 @@
+/*
+    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/******************************************************************************
+ * This project provides two demo applications.  A simple blinky style project,
+ * and a more comprehensive test and demo application.  The
+ * configCREATE_SIMPLE_TICKLESS_DEMO setting (defined in FreeRTOSConfig.h) is
+ * used to select between the two.  The simply blinky demo is implemented and
+ * described in main_blinky.c.  The more comprehensive test and demo application
+ * is implemented and described in main_full.c.
+ *
+ * The comprehensive demo uses FreeRTOS+CLI to create a simple command line 
+ * interface through a UART.
+ *
+ * The blinky demo uses FreeRTOS's tickless idle mode to reduce power 
+ * consumption.  See the notes on the web page below regarding the difference
+ * in power saving that can be achieved between using the generic tickless
+ * implementation (as used by the blinky demo) and a tickless implementation
+ * that is tailored specifically to the MSP432.
+ * 
+ * This file implements the code that is not demo specific.
+ *
+ * See http://www.FreeRTOS.org/TI_MSP432_Free_RTOS_Demo.html for instructions.
+ *
+ */
+
+/* Standard includes. */
+#include <stdio.h>
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Set up the hardware ready to run this demo.
+ */
+static void prvSetupHardware( void );
+
+/*
+ * main_blinky() is used when configCREATE_SIMPLE_TICKLESS_DEMO is set to 1.
+ * main_full() is used when configCREATE_SIMPLE_TICKLESS_DEMO is set to 0.
+ */
+extern void main_blinky( void );
+extern void main_full( void );
+
+/*-----------------------------------------------------------*/
+
+int main( void )
+{
+	/* See http://www.FreeRTOS.org/TI_MSP432_Free_RTOS_Demo.html for instructions. */
+	
+	/* Prepare the hardware to run this demo. */
+	prvSetupHardware();
+
+	/* The configCREATE_SIMPLE_TICKLESS_DEMO setting is described at the top
+	of this file. */
+	#if configCREATE_SIMPLE_TICKLESS_DEMO == 1
+	{
+		main_blinky();
+	}
+	#else
+	{
+		main_full();
+	}
+	#endif
+
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupHardware( void )
+{
+extern void FPU_enableModule( void );
+	
+	/* The clocks are not configured here, but inside main_full() and
+	main_blinky() as the full demo uses a fast clock and the blinky demo uses
+	a slow clock. */
+
+	/* Stop the watchdog timer. */
+	MAP_WDT_A_holdTimer();
+	
+	/* Ensure the FPU is enabled. */
+	FPU_enableModule();
+
+	/* Selecting P1.2 and P1.3 in UART mode and P1.0 as output (LED) */
+	MAP_GPIO_setAsPeripheralModuleFunctionInputPin( GPIO_PORT_P1, GPIO_PIN2 | GPIO_PIN3, GPIO_PRIMARY_MODULE_FUNCTION );
+	MAP_GPIO_setOutputLowOnPin( GPIO_PORT_P1, GPIO_PIN0 );
+	MAP_GPIO_setAsOutputPin( GPIO_PORT_P1, GPIO_PIN0 );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationMallocFailedHook( void )
+{
+	/* vApplicationMallocFailedHook() will only be called if
+	configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h.  It is a hook
+	function that will get called if a call to pvPortMalloc() fails.
+	pvPortMalloc() is called internally by the kernel whenever a task, queue,
+	timer or semaphore is created.  It is also called by various parts of the
+	demo application.  If heap_1.c or heap_2.c are used, then the size of the
+	heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
+	FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
+	to query the size of free heap space that remains (although it does not
+	provide information on how the remaining heap might be fragmented). */
+	taskDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationIdleHook( void )
+{
+	/* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set
+	to 1 in FreeRTOSConfig.h.  It will be called on each iteration of the idle
+	task.  It is essential that code added to this hook function never attempts
+	to block in any way (for example, call xQueueReceive() with a block time
+	specified, or call vTaskDelay()).  If the application makes use of the
+	vTaskDelete() API function (as this demo application does) then it is also
+	important that vApplicationIdleHook() is permitted to return to its calling
+	function, because it is the responsibility of the idle task to clean up
+	memory allocated by the kernel to any task that has since been deleted. */
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )
+{
+	( void ) pcTaskName;
+	( void ) pxTask;
+
+	/* Run time stack overflow checking is performed if
+	configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2.  This hook
+	function is called if a stack overflow is detected. */
+	taskDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void *malloc( size_t xSize )
+{
+	/* There should not be a heap defined, so trap any attempts to call
+	malloc. */
+	Interrupt_disableMaster();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/settings/RTOSDemo.Debug.cspy.bat b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.Debug.cspy.bat
index bdc6773d8..6db2db535 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/settings/RTOSDemo.Debug.cspy.bat
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.Debug.cspy.bat
@@ -19,6 +19,22 @@
 @REM 
 
 
-"C:\DevTools\IAR Systems\Embedded Workbench 7.0\common\bin\cspybat" "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\bin\armproc.dll" "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\bin\armjlink.dll"  %1 --plugin "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\bin\armbat.dll" --device_macro "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\config\debugger\ST\STM32F4xx.dmac" --flash_loader "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\config\flashloader\ST\FlashSTM32F7xxx.board" --backend -B "--endian=little" "--cpu=Cortex-M7" "--fpu=VFPv5_sp" "-p" "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\CONFIG\debugger\ST\STM32F7xxx.ddf" "--drv_verify_download" "--semihosting=none" "--device=STM32F7xxx" "--drv_communication=USB0" "--drv_interface_speed=auto" "--jlink_initial_speed=1000" "--jlink_reset_strategy=0,0" "--drv_catch_exceptions=0x000" "--drv_swo_clock_setup=0,0,2000000" 
+@echo off 
 
+if not "%1" == "" goto debugFile 
 
+@echo on 
+
+"C:\DevTools\IAR Systems\Embedded Workbench 7.2\common\bin\cspybat" -f "C:\E\temp\FreeRTOSv8.2.1\clean\FreeRTOS\Demo\CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil\settings\RTOSDemo.Debug.general.xcl" --backend -f "C:\E\temp\FreeRTOSv8.2.1\clean\FreeRTOS\Demo\CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil\settings\RTOSDemo.Debug.driver.xcl" 
+
+@echo off 
+goto end 
+
+:debugFile 
+
+@echo on 
+
+"C:\DevTools\IAR Systems\Embedded Workbench 7.2\common\bin\cspybat" -f "C:\E\temp\FreeRTOSv8.2.1\clean\FreeRTOS\Demo\CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil\settings\RTOSDemo.Debug.general.xcl" "--debug_file=%1" --backend -f "C:\E\temp\FreeRTOSv8.2.1\clean\FreeRTOS\Demo\CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil\settings\RTOSDemo.Debug.driver.xcl" 
+
+@echo off 
+:end
+\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/settings/RTOSDemo.crun b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.crun
index 5bb5acca4..5bb5acca4 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/settings/RTOSDemo.crun
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.crun
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.dbgdt b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.dbgdt
new file mode 100644
index 000000000..f93bb8a1b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.dbgdt
@@ -0,0 +1,87 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<Project>
+  <Desktop>
+    <Static>
+      <Debug-Log>
+        
+        
+      <ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1622</ColumnWidth1></Debug-Log>
+      <Build>
+        <ColumnWidth0>20</ColumnWidth0>
+        <ColumnWidth1>1216</ColumnWidth1>
+        <ColumnWidth2>324</ColumnWidth2>
+        <ColumnWidth3>81</ColumnWidth3>
+      </Build>
+      <Workspace>
+        <ColumnWidths>
+          
+          
+          
+          
+        <Column0>233</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
+      </Workspace>
+      <Disassembly>
+        <col-names>
+          
+          
+        <item>Disassembly</item><item>_I0</item></col-names>
+        <col-widths>
+          
+          
+        <item>500</item><item>20</item></col-widths>
+        <DisasmHistory><item>0</item></DisasmHistory>
+        
+        
+      <PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><ShowCodeCoverage>1</ShowCodeCoverage><ShowInstrProfiling>1</ShowInstrProfiling></Disassembly>
+    <Register><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows></Register></Static>
+    <Windows>
+      
+      
+      
+    <Wnd1>
+        <Tabs>
+          <Tab>
+            <Identity>TabID-24437-20285</Identity>
+            <TabName>Debug Log</TabName>
+            <Factory>Debug-Log</Factory>
+            <Session/>
+          </Tab>
+          <Tab>
+            <Identity>TabID-23914-20295</Identity>
+            <TabName>Build</TabName>
+            <Factory>Build</Factory>
+            <Session/>
+          </Tab>
+        </Tabs>
+        
+      <SelectedTab>0</SelectedTab></Wnd1><Wnd4>
+        <Tabs>
+          <Tab>
+            <Identity>TabID-2417-20288</Identity>
+            <TabName>Workspace</TabName>
+            <Factory>Workspace</Factory>
+            <Session>
+              
+            <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/Full_Demo</ExpandedNode></NodeDict></Session>
+          </Tab>
+        </Tabs>
+        
+      <SelectedTab>0</SelectedTab></Wnd4><Wnd5><Tabs><Tab><Identity>TabID-18267-27197</Identity><TabName>Disassembly</TabName><Factory>Disassembly</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd5></Windows>
+    <Editor>
+      
+      
+      
+      
+    <Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\main.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>128</YPos2><SelStart2>5940</SelStart2><SelEnd2>5940</SelEnd2></Tab><ActiveTab>0</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
+    <Positions>
+      
+      
+      
+      
+      
+    <Top><Row0><Sizes><Toolbar-00359FA0><key>iaridepm.enu1</key></Toolbar-00359FA0></Sizes></Row0><Row1><Sizes><Toolbar-0D2EC0B0><key>debuggergui.enu1</key></Toolbar-0D2EC0B0></Sizes></Row1><Row2><Sizes><Toolbar-0D2DBAF8><key>armjet.enu1</key></Toolbar-0D2DBAF8></Sizes></Row2></Top><Left><Row0><Sizes><Wnd4><Rect><Top>-2</Top><Left>-2</Left><Bottom>585</Bottom><Right>307</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203252</sizeHorzCY><sizeVertCX>183929</sizeVertCX><sizeVertCY>596545</sizeVertCY></Rect></Wnd4></Sizes></Row0></Left><Right><Row0><Sizes><Wnd5><Rect><Top>-2</Top><Left>-2</Left><Bottom>585</Bottom><Right>198</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203252</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>596545</sizeVertCY></Rect></Wnd5></Sizes></Row0></Right><Bottom><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>307</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>309</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>314024</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203252</sizeVertCY></Rect></Wnd1></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>
+  </Desktop>
+</Project>
+
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.dni b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.dni
new file mode 100644
index 000000000..4f6bf46be
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.dni
@@ -0,0 +1,146 @@
+[Stack]
+FillEnabled=0
+OverflowWarningsEnabled=1
+WarningThreshold=90
+SpWarningsEnabled=1
+WarnLogOnly=1
+UseTrigger=1
+TriggerName=main
+LimitSize=0
+ByteLimit=50
+[PlDriver]
+MemConfigValue=
+FirstRun=0
+[PlCacheRanges]
+CustomRanges0=0 0 536870912 1 0
+CustomRangesText0=Code
+CustomRanges1=0 536870912 33554432 0 0
+CustomRangesText1=SRAM
+CustomRanges2=0 570425344 33554432 0 0
+CustomRangesText2=bit-banding
+CustomRanges3=0 1073741824 33554432 2 0
+CustomRangesText3=Peripheral
+CustomRanges4=0 1107296256 33554432 2 0
+CustomRangesText4=bit-banding
+CustomRanges5=0 3758096384 536870912 2 0
+CustomRangesText5=Private peripheral
+[Jet]
+JetConnSerialNo=73866
+JetConnFoundProbes=
+DisableInterrupts=0
+MultiCoreRunAll=0
+OnlineReset=Software
+PrevWtdReset=System
+[DebugChecksum]
+Checksum=701872400
+[Exceptions]
+StopOnUncaught=_ 0
+StopOnThrow=_ 0
+[CallStack]
+ShowArgs=0
+[Disassembly]
+MixedMode=1
+[SWOManager]
+SamplingDivider=8192
+OverrideClock=0
+CpuClock=696008061
+SwoClock=560889384
+DataLogMode=0
+ItmPortsEnabled=63
+ItmTermIOPorts=1
+ItmLogPorts=0
+ItmLogFile=$PROJ_DIR$\ITM.log
+PowerForcePC=1
+PowerConnectPC=1
+[ArmDriver]
+EnableCache=1
+[JLinkDriver]
+CStepIntDis=_ 0
+[CodeCoverage]
+Enabled=_ 0
+[SWOTraceHWSettings]
+OverrideDefaultClocks=0
+CpuClock=12000000
+ClockAutoDetect=1
+ClockWanted=7500000
+JtagSpeed=6000000
+Prescaler=2
+TimeStampPrescIndex=0
+TimeStampPrescData=0
+PcSampCYCTAP=1
+PcSampPOSTCNT=15
+PcSampIndex=0
+DataLogMode=0
+ITMportsEnable=0
+ITMportsTermIO=0
+ITMportsLogFile=0
+ITMlogFile=$PROJ_DIR$\ITM.log
+[Breakpoints]
+Count=0
+[Trace2]
+Enabled=0
+ShowSource=0
+[SWOTraceWindow]
+ForcedPcSampling=0
+ForcedInterruptLogs=0
+ForcedItmLogs=0
+EventCPI=0
+EventEXC=0
+EventFOLD=0
+EventLSU=0
+EventSLEEP=0
+[PowerLog]
+LogEnabled=0
+GraphEnabled=0
+ShowTimeLog=1
+ShowTimeSum=0
+Title_0=I0
+Symbol_0=0 4 1
+LiveEnabled=0
+LiveFile=PowerLogLive.log
+[DataLog]
+LogEnabled=0
+SumEnabled=0
+GraphEnabled=0
+ShowTimeLog=1
+ShowTimeSum=1
+[EventLog]
+LogEnabled=0
+SumEnabled=0
+GraphEnabled=0
+ShowTimeLog=1
+ShowTimeSum=1
+SumSortOrder=0
+[InterruptLog]
+LogEnabled=0
+SumEnabled=0
+GraphEnabled=0
+ShowTimeLog=1
+ShowTimeSum=1
+SumSortOrder=0
+[CallStackLog]
+Enabled=0
+[DriverProfiling]
+Enabled=0
+Mode=3
+Graph=0
+Symbiont=0
+Exclusions=
+[PowerProbe]
+Frequency=10000
+Probe0=I0
+ProbeSetup0=2 1 1 2 0 0
+[Log file]
+LoggingEnabled=_ 0
+LogFile=_ ""
+Category=_ 0
+[TermIOLog]
+LoggingEnabled=_ 0
+LogFile=_ ""
+[Disassemble mode]
+mode=0
+[Breakpoints2]
+Count=0
+[Aliases]
+Count=0
+SuppressDialog=0
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.wsdt b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.wsdt
new file mode 100644
index 000000000..24a90c003
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.wsdt
@@ -0,0 +1,66 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<Workspace>
+  <ConfigDictionary>
+    
+  <CurrentConfigs><Project>RTOSDemo/IAR_Debug</Project></CurrentConfigs></ConfigDictionary>
+  <Desktop>
+    <Static>
+      <Workspace>
+        <ColumnWidths>
+          
+          
+          
+          
+        <Column0>307</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
+      </Workspace>
+      <Build>
+        
+        
+        
+        
+      <ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1216</ColumnWidth1><ColumnWidth2>324</ColumnWidth2><ColumnWidth3>81</ColumnWidth3></Build>
+    <Debug-Log><ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1622</ColumnWidth1></Debug-Log><TerminalIO/><Find-in-Files><ColumnWidth0>497</ColumnWidth0><ColumnWidth1>82</ColumnWidth1><ColumnWidth2>746</ColumnWidth2><ColumnWidth3>331</ColumnWidth3></Find-in-Files><Select-Ambiguous-Definitions><ColumnWidth0>664</ColumnWidth0><ColumnWidth1>94</ColumnWidth1><ColumnWidth2>1138</ColumnWidth2></Select-Ambiguous-Definitions><Find-All-Declarations><ColumnWidth0>580</ColumnWidth0><ColumnWidth1>82</ColumnWidth1><ColumnWidth2>994</ColumnWidth2></Find-All-Declarations></Static>
+    <Windows>
+      
+      
+    <Wnd1>
+        <Tabs>
+          <Tab>
+            <Identity>TabID-2476-27879</Identity>
+            <TabName>Workspace</TabName>
+            <Factory>Workspace</Factory>
+            <Session>
+              
+            <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode></NodeDict></Session>
+          </Tab>
+        </Tabs>
+        
+      <SelectedTab>0</SelectedTab></Wnd1><Wnd3>
+        <Tabs>
+          <Tab>
+            <Identity>TabID-28448-28006</Identity>
+            <TabName>Build</TabName>
+            <Factory>Build</Factory>
+            <Session/>
+          </Tab>
+        <Tab><Identity>TabID-6453-17552</Identity><TabName>Debug Log</TabName><Factory>Debug-Log</Factory><Session/></Tab><Tab><Identity>TabID-23164-8214</Identity><TabName>Find in Files</TabName><Factory>Find-in-Files</Factory><Session/></Tab><Tab><Identity>TabID-26948-371</Identity><TabName>Ambiguous Definitions</TabName><Factory>Select-Ambiguous-Definitions</Factory><Session/></Tab><Tab><Identity>TabID-26862-26832</Identity><TabName>Declarations</TabName><Factory>Find-All-Declarations</Factory><Session/></Tab></Tabs>
+        
+      <SelectedTab>0</SelectedTab></Wnd3></Windows>
+    <Editor>
+      
+      
+      
+      
+    <Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\main.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>61</YPos2><SelStart2>5940</SelStart2><SelEnd2>5940</SelEnd2></Tab><ActiveTab>0</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
+    <Positions>
+      
+      
+      
+      
+      
+    <Top><Row0><Sizes><Toolbar-010D90F0><key>iaridepm.enu1</key></Toolbar-010D90F0></Sizes></Row0></Top><Left><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>587</Bottom><Right>381</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203252</sizeHorzCY><sizeVertCX>227976</sizeVertCX><sizeVertCY>598577</sizeVertCY></Rect></Wnd1></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>353</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>355</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>360772</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203252</sizeVertCY></Rect></Wnd3></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>
+  </Desktop>
+</Workspace>
+
+
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/settings/RTOSDemo.wspos b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.wspos
index cd790b7cf..cd790b7cf 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/settings/RTOSDemo.wspos
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.wspos
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/settings/RTOSDemo_Debug.jlink b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo_Debug.jlink
index 706cf39a9..706cf39a9 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/settings/RTOSDemo_Debug.jlink
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo_Debug.jlink
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/CCS/MSP432P401R.ccxml b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/CCS/MSP432P401R.ccxml
new file mode 100644
index 000000000..98d3e3399
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/CCS/MSP432P401R.ccxml
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<configurations XML_version="1.2" id="configurations_0">
+    <configuration XML_version="1.2" id="configuration_0">
+        <instance XML_version="1.2" desc="Texas Instruments XDS110 USB Debug Probe" href="connections/TIXDS110_Connection.xml" id="Texas Instruments XDS110 USB Debug Probe" xml="TIXDS110_Connection.xml" xmlpath="connections"/>
+        <connection XML_version="1.2" id="Texas Instruments XDS110 USB Debug Probe">
+            <instance XML_version="1.2" href="drivers/tixds510cs_dap.xml" id="drivers" xml="tixds510cs_dap.xml" xmlpath="drivers"/>
+            <instance XML_version="1.2" href="drivers/tixds510cortexM.xml" id="drivers" xml="tixds510cortexM.xml" xmlpath="drivers"/>
+            <platform XML_version="1.2" id="platform_0">
+                <instance XML_version="1.2" desc="MSP432P401R" href="devices/msp432p401r.xml" id="MSP432P401R" xml="msp432p401r.xml" xmlpath="devices"/>
+            </platform>
+        </connection>
+    </configuration>
+</configurations>
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/CCS/msp432_startup_ccs.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/CCS/msp432_startup_ccs.c
new file mode 100644
index 000000000..31d6dded3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/CCS/msp432_startup_ccs.c
@@ -0,0 +1,206 @@
+//*****************************************************************************
+//
+// Copyright (C) 2012 - 2014 Texas Instruments Incorporated - http://www.ti.com/ 
+//
+// Redistribution and use in source and binary forms, with or without 
+// modification, are permitted provided that the following conditions 
+// are met:
+//
+//  Redistributions of source code must retain the above copyright 
+//  notice, this list of conditions and the following disclaimer.
+//
+//  Redistributions in binary form must reproduce the above copyright
+//  notice, this list of conditions and the following disclaimer in the 
+//  documentation and/or other materials provided with the   
+//  distribution.
+//
+//  Neither the name of Texas Instruments Incorporated nor the names of
+//  its contributors may be used to endorse or promote products derived
+//  from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+//
+// MSP432 Family Interrupt Vector Table for CGT
+//
+//****************************************************************************
+
+#include <stdint.h>
+#include <driverlib.h>
+
+/* Forward declaration of the default fault handlers. */
+static void resetISR(void);
+static void nmiISR(void);
+static void faultISR(void);
+static void defaultISR(void);
+
+
+/* External declaration for the reset handler that is to be called when the */
+/* processor is started                                                     */
+extern void _c_int00(void);
+
+
+/* Linker variable that marks the top of the stack. */
+extern unsigned long __STACK_END;
+
+
+/* External declarations for the FreeRTOS interrupt handlers. */
+extern void xPortSysTickHandler( void );
+extern void vPortSVCHandler( void );
+extern void xPortPendSVHandler( void );
+
+/* External declarations for the peripheral interrupts handlers used by the
+demo application. */
+extern void vUART_Handler( void );
+extern void vT32_0_Handler( void );
+extern void vT32_1_Handler( void );
+
+/* Intrrupt vector table.  Note that the proper constructs must be placed on this to  */
+/* ensure that it ends up at physical address 0x0000.0000 or at the start of          */
+/* the program if located at a start address other than 0.                            */
+#pragma DATA_SECTION(interruptVectors, ".intvecs")
+void (* const interruptVectors[])(void) =
+{
+    (void (*)(void))((uint32_t)&__STACK_END),
+                                            /* The initial stack pointer */
+    resetISR,                               /* The reset handler         */
+    nmiISR,                                 /* The NMI handler           */
+    faultISR,                               /* The hard fault handler    */
+    defaultISR,                             /* The MPU fault handler     */
+    defaultISR,                             /* The bus fault handler     */
+    defaultISR,                             /* The usage fault handler   */
+    0,                                      /* Reserved                  */
+    0,                                      /* Reserved                  */
+    0,                                      /* Reserved                  */
+    0,                                      /* Reserved                  */
+	vPortSVCHandler,                        /* SVCall handler            */
+    defaultISR,                             /* Debug monitor handler     */
+    0,                                      /* Reserved                  */
+	xPortPendSVHandler,                     /* The PendSV handler        */
+	xPortSysTickHandler,                    /* The SysTick handler       */
+    defaultISR,                             /* PSS ISR                   */
+    defaultISR,                             /* CS ISR                    */
+    defaultISR,                             /* PCM ISR                   */
+    defaultISR,                             /* WDT ISR                   */
+    defaultISR,                             /* FPU ISR                   */
+    defaultISR,                             /* FLCTL ISR                 */
+    defaultISR,                             /* COMP0 ISR                 */
+    defaultISR,                             /* COMP1 ISR                 */
+    defaultISR,                             /* TA0_0 ISR                 */
+    defaultISR,                             /* TA0_N ISR                 */
+	defaultISR,                             /* TA1_0 ISR                 */
+    defaultISR,                             /* TA1_N ISR                 */
+	defaultISR,                             /* TA2_0 ISR                 */
+    defaultISR,                             /* TA2_N ISR                 */
+    defaultISR,                             /* TA3_0 ISR                 */
+    defaultISR,                             /* TA3_N ISR                 */
+	vUART_Handler,                        /* EUSCIA0 ISR               */
+    defaultISR,                             /* EUSCIA1 ISR               */
+    defaultISR,                             /* EUSCIA2 ISR               */
+    defaultISR,                             /* EUSCIA3 ISR               */
+    defaultISR,                             /* EUSCIB0 ISR               */
+    defaultISR,                             /* EUSCIB1 ISR               */
+    defaultISR,                             /* EUSCIB2 ISR               */
+    defaultISR,                             /* EUSCIB3 ISR               */
+    defaultISR,                             /* ADC14 ISR                 */
+	vT32_0_Handler,                         /* T32_INT1 ISR              */
+	vT32_1_Handler,                         /* T32_INT2 ISR              */
+    defaultISR,                             /* T32_INTC ISR              */
+    defaultISR,                             /* AES ISR                   */
+    defaultISR,                             /* RTC ISR                   */
+    defaultISR,                             /* DMA_ERR ISR               */
+    defaultISR,                             /* DMA_INT3 ISR              */
+    defaultISR,                             /* DMA_INT2 ISR              */
+    defaultISR,                             /* DMA_INT1 ISR              */
+    defaultISR,                             /* DMA_INT0 ISR              */
+	defaultISR,                             /* PORT1 ISR                 */
+    defaultISR,                             /* PORT2 ISR                 */
+    defaultISR,                             /* PORT3 ISR                 */
+    defaultISR,                             /* PORT4 ISR                 */
+    defaultISR,                             /* PORT5 ISR                 */
+    defaultISR,                             /* PORT6 ISR                 */
+    defaultISR,                             /* Reserved 41               */
+    defaultISR,                             /* Reserved 42               */
+    defaultISR,                             /* Reserved 43               */
+    defaultISR,                             /* Reserved 44               */
+    defaultISR,                             /* Reserved 45               */
+    defaultISR,                             /* Reserved 46               */
+    defaultISR,                             /* Reserved 47               */
+    defaultISR,                             /* Reserved 48               */
+    defaultISR,                             /* Reserved 49               */
+    defaultISR,                             /* Reserved 50               */
+    defaultISR,                             /* Reserved 51               */
+    defaultISR,                             /* Reserved 52               */
+    defaultISR,                             /* Reserved 53               */
+    defaultISR,                             /* Reserved 54               */
+    defaultISR,                             /* Reserved 55               */
+    defaultISR,                             /* Reserved 56               */
+    defaultISR,                             /* Reserved 57               */
+    defaultISR,                             /* Reserved 58               */
+    defaultISR,                             /* Reserved 59               */
+    defaultISR,                             /* Reserved 60               */
+    defaultISR,                             /* Reserved 61               */
+    defaultISR,                             /* Reserved 62               */
+    defaultISR,                             /* Reserved 63               */
+    defaultISR                              /* Reserved 64               */
+};
+
+
+/* This is the code that gets called when the processor first starts execution */
+/* following a reset event.  Only the absolutely necessary set is performed,   */
+/* after which the application supplied entry() routine is called.  Any fancy  */
+/* actions (such as making decisions based on the reset cause register, and    */
+/* resetting the bits in that register) are left solely in the hands of the    */
+/* application.                                                                */
+void resetISR(void)
+{
+    /* Jump to the CCS C Initialization Routine. */
+	MAP_WDT_A_holdTimer();
+    __asm("    .global _c_int00\n"
+          "    b.w     _c_int00");
+}
+
+
+/* This is the code that gets called when the processor receives a NMI.  This  */
+/* simply enters an infinite loop, preserving the system state for examination */
+/* by a debugger.                                                              */
+static void nmiISR(void)
+{
+    /* Enter an infinite loop. */
+    while(1)
+    {
+    }
+}
+
+
+/* This is the code that gets called when the processor receives a fault        */
+/* interrupt.  This simply enters an infinite loop, preserving the system state */
+/* for examination by a debugger.                                               */
+static void faultISR(void)
+{
+    /* Enter an infinite loop. */
+    while(1)
+    {
+    }
+}
+
+
+/* This is the code that gets called when the processor receives an unexpected  */
+/* interrupt.  This simply enters an infinite loop, preserving the system state */
+/* for examination by a debugger.                                               */
+static void defaultISR(void)
+{
+    /* Enter an infinite loop. */
+    while(1)
+    {
+    }
+}
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/CCS/msp432p401r.cmd b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/CCS/msp432p401r.cmd
new file mode 100644
index 000000000..d93a7573e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/CCS/msp432p401r.cmd
@@ -0,0 +1,84 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+*  Redistributions of source code must retain the above copyright
+*  notice, this list of conditions and the following disclaimer.
+*
+*  Redistributions in binary form must reproduce the above copyright
+*  notice, this list of conditions and the following disclaimer in the
+*  documentation and/or other materials provided with the
+*  distribution.
+*
+*  Neither the name of Texas Instruments Incorporated nor the names of
+*  its contributors may be used to endorse or promote products derived
+*  from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* Default linker command file for Texas Instruments MSP432P401R
+*
+* File creation date: 2015-01-20
+*
+*****************************************************************************/
+
+--retain=interruptVectors
+--retain=flashMailbox
+
+MEMORY
+{
+    MAIN       (RX) : origin = 0x00000000, length = 0x00040000
+    INFO       (RX) : origin = 0x00200000, length = 0x00004000
+    SRAM_CODE  (RWX): origin = 0x01000000, length = 0x00010000
+    SRAM_DATA  (RW) : origin = 0x20000000, length = 0x00010000
+}
+
+/* The following command line options are set as part of the CCS project.    */
+/* If you are building using the command line, or for some reason want to    */
+/* define them here, you can uncomment and modify these lines as needed.     */
+/* If you are using CCS for building, it is probably better to make any such */
+/* modifications in your CCS project and leave this file alone.              */
+/*                                                                           */
+/* A heap size of 1024 bytes is recommended when you plan to use printf()    */
+/* for debug output to the console window.                                   */
+/*                                                                           */
+/* --heap_size=1024                                                          */
+/* --stack_size=512                                                          */
+/* --library=rtsv7M4_T_le_eabi.lib                                           */
+
+/* Section allocation in memory */
+
+SECTIONS
+{
+    .intvecs:   > 0x00000000
+    .text   :   > MAIN
+    .const  :   > MAIN
+    .cinit  :   > MAIN
+    .pinit  :   > MAIN
+
+    .flashMailbox : > 0x00200000
+
+    .vtable :   > 0x20000000
+    .data   :   > SRAM_DATA
+    .bss    :   > SRAM_DATA
+    .sysmem :   > SRAM_DATA
+    .stack  :   > SRAM_DATA (HIGH)
+}
+
+/* Symbolic definition of the WDTCTL register for RTS */
+WDTCTL_SYM = 0x4000480C;
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/CCS/printf-stdarg.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/CCS/printf-stdarg.c
new file mode 100644
index 000000000..a25cab6ce
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/CCS/printf-stdarg.c
@@ -0,0 +1,312 @@
+/*
+	Copyright 2001, 2002 Georges Menie (www.menie.org)
+	stdarg version contributed by Christian Ettinger
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU Lesser General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+/*
+	putchar is the only external dependency for this file,
+	if you have a working putchar, leave it commented out.
+	If not, uncomment the define below and
+	replace outbyte(c) by your own function call.
+
+*/
+
+#define putchar(c) c
+
+#include <stdarg.h>
+
+static int tiny_print( char **out, const char *format, va_list args, unsigned int buflen );
+
+static void printchar(char **str, int c, char *buflimit)
+{
+	//extern int putchar(int c);
+
+	if (str) {
+		if( buflimit == ( char * ) 0 ) {
+			/* Limit of buffer not known, write charater to buffer. */
+			**str = (char)c;
+			++(*str);
+		}
+		else if( ( ( unsigned long ) *str ) < ( ( unsigned long ) buflimit ) ) {
+			/* Withing known limit of buffer, write character. */
+			**str = (char)c;
+			++(*str);
+		}
+	}
+	else
+	{
+		(void)putchar(c);
+	}
+}
+
+#define PAD_RIGHT 1
+#define PAD_ZERO 2
+
+static int prints(char **out, const char *string, int width, int pad, char *buflimit)
+{
+	register int pc = 0, padchar = ' ';
+
+	if (width > 0) {
+		register int len = 0;
+		register const char *ptr;
+		for (ptr = string; *ptr; ++ptr) ++len;
+		if (len >= width) width = 0;
+		else width -= len;
+		if (pad & PAD_ZERO) padchar = '0';
+	}
+	if (!(pad & PAD_RIGHT)) {
+		for ( ; width > 0; --width) {
+			printchar (out, padchar, buflimit);
+			++pc;
+		}
+	}
+	for ( ; *string ; ++string) {
+		printchar (out, *string, buflimit);
+		++pc;
+	}
+	for ( ; width > 0; --width) {
+		printchar (out, padchar, buflimit);
+		++pc;
+	}
+
+	return pc;
+}
+
+/* the following should be enough for 32 bit int */
+#define PRINT_BUF_LEN 12
+
+static int printi(char **out, int i, int b, int sg, int width, int pad, int letbase, char *buflimit)
+{
+	char print_buf[PRINT_BUF_LEN];
+	register char *s;
+	register int t, neg = 0, pc = 0;
+	register unsigned int u = (unsigned int)i;
+
+	if (i == 0) {
+		print_buf[0] = '0';
+		print_buf[1] = '\0';
+		return prints (out, print_buf, width, pad, buflimit);
+	}
+
+	if (sg && b == 10 && i < 0) {
+		neg = 1;
+		u = (unsigned int)-i;
+	}
+
+	s = print_buf + PRINT_BUF_LEN-1;
+	*s = '\0';
+
+	while (u) {
+		t = (unsigned int)u % b;
+		if( t >= 10 )
+			t += letbase - '0' - 10;
+		*--s = (char)(t + '0');
+		u /= b;
+	}
+
+	if (neg) {
+		if( width && (pad & PAD_ZERO) ) {
+			printchar (out, '-', buflimit);
+			++pc;
+			--width;
+		}
+		else {
+			*--s = '-';
+		}
+	}
+
+	return pc + prints (out, s, width, pad, buflimit);
+}
+
+static int tiny_print( char **out, const char *format, va_list args, unsigned int buflen )
+{
+	register int width, pad;
+	register int pc = 0;
+	char scr[2], *buflimit;
+
+	if( buflen == 0 ){
+		buflimit = ( char * ) 0;
+	}
+	else {
+		/* Calculate the last valid buffer space, leaving space for the NULL
+		terminator. */
+		buflimit = ( *out ) + ( buflen - 1 );
+	}
+
+	for (; *format != 0; ++format) {
+		if (*format == '%') {
+			++format;
+			width = pad = 0;
+			if (*format == '\0') break;
+			if (*format == '%') goto out;
+			if (*format == '-') {
+				++format;
+				pad = PAD_RIGHT;
+			}
+			while (*format == '0') {
+				++format;
+				pad |= PAD_ZERO;
+			}
+			for ( ; *format >= '0' && *format <= '9'; ++format) {
+				width *= 10;
+				width += *format - '0';
+			}
+			if( *format == 's' ) {
+				register char *s = (char *)va_arg( args, int );
+				pc += prints (out, s?s:"(null)", width, pad, buflimit);
+				continue;
+			}
+			if( *format == 'd' ) {
+				pc += printi (out, va_arg( args, int ), 10, 1, width, pad, 'a', buflimit);
+				continue;
+			}
+			if( *format == 'x' ) {
+				pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'a', buflimit);
+				continue;
+			}
+			if( *format == 'X' ) {
+				pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'A', buflimit);
+				continue;
+			}
+			if( *format == 'u' ) {
+				pc += printi (out, va_arg( args, int ), 10, 0, width, pad, 'a', buflimit);
+				continue;
+			}
+			if( *format == 'c' ) {
+				/* char are converted to int then pushed on the stack */
+				scr[0] = (char)va_arg( args, int );
+				scr[1] = '\0';
+				pc += prints (out, scr, width, pad, buflimit);
+				continue;
+			}
+		}
+		else {
+		out:
+			printchar (out, *format, buflimit);
+			++pc;
+		}
+	}
+	if (out) **out = '\0';
+	va_end( args );
+	return pc;
+}
+
+int printf(const char *format, ...)
+{
+        va_list args;
+
+        va_start( args, format );
+        return tiny_print( 0, format, args, 0 );
+}
+
+int sprintf(char *out, const char *format, ...)
+{
+        va_list args;
+
+        va_start( args, format );
+        return tiny_print( &out, format, args, 0 );
+}
+
+
+int snprintf( char *buf, unsigned int count, const char *format, ... )
+{
+        va_list args;
+
+        ( void ) count;
+
+        va_start( args, format );
+        return tiny_print( &buf, format, args, count );
+}
+
+
+#ifdef TEST_PRINTF
+int main(void)
+{
+	char *ptr = "Hello world!";
+	char *np = 0;
+	int i = 5;
+	unsigned int bs = sizeof(int)*8;
+	int mi;
+	char buf[80];
+
+	mi = (1 << (bs-1)) + 1;
+	printf("%s\n", ptr);
+	printf("printf test\n");
+	printf("%s is null pointer\n", np);
+	printf("%d = 5\n", i);
+	printf("%d = - max int\n", mi);
+	printf("char %c = 'a'\n", 'a');
+	printf("hex %x = ff\n", 0xff);
+	printf("hex %02x = 00\n", 0);
+	printf("signed %d = unsigned %u = hex %x\n", -3, -3, -3);
+	printf("%d %s(s)%", 0, "message");
+	printf("\n");
+	printf("%d %s(s) with %%\n", 0, "message");
+	sprintf(buf, "justif: \"%-10s\"\n", "left"); printf("%s", buf);
+	sprintf(buf, "justif: \"%10s\"\n", "right"); printf("%s", buf);
+	sprintf(buf, " 3: %04d zero padded\n", 3); printf("%s", buf);
+	sprintf(buf, " 3: %-4d left justif.\n", 3); printf("%s", buf);
+	sprintf(buf, " 3: %4d right justif.\n", 3); printf("%s", buf);
+	sprintf(buf, "-3: %04d zero padded\n", -3); printf("%s", buf);
+	sprintf(buf, "-3: %-4d left justif.\n", -3); printf("%s", buf);
+	sprintf(buf, "-3: %4d right justif.\n", -3); printf("%s", buf);
+
+	return 0;
+}
+
+/*
+ * if you compile this file with
+ *   gcc -Wall $(YOUR_C_OPTIONS) -DTEST_PRINTF -c printf.c
+ * you will get a normal warning:
+ *   printf.c:214: warning: spurious trailing `%' in format
+ * this line is testing an invalid % at the end of the format string.
+ *
+ * this should display (on 32bit int machine) :
+ *
+ * Hello world!
+ * printf test
+ * (null) is null pointer
+ * 5 = 5
+ * -2147483647 = - max int
+ * char a = 'a'
+ * hex ff = ff
+ * hex 00 = 00
+ * signed -3 = unsigned 4294967293 = hex fffffffd
+ * 0 message(s)
+ * 0 message(s) with %
+ * justif: "left      "
+ * justif: "     right"
+ *  3: 0003 zero padded
+ *  3: 3    left justif.
+ *  3:    3 right justif.
+ * -3: -003 zero padded
+ * -3: -3   left justif.
+ * -3:   -3 right justif.
+ */
+
+#endif
+
+
+/* To keep linker happy. */
+int	write( int i, char* c, int n)
+{
+	(void)i;
+	(void)n;
+	(void)c;
+	return 0;
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/IAR/msp432_startup_ewarm.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/IAR/msp432_startup_ewarm.c
new file mode 100644
index 000000000..fe3c4d204
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/IAR/msp432_startup_ewarm.c
@@ -0,0 +1,226 @@
+#include <stdint.h>
+#include <msp.h>
+
+//*****************************************************************************
+//
+// Enable the IAR extensions for this source file.
+//
+//*****************************************************************************
+#pragma language=extended
+
+//*****************************************************************************
+//
+// Forward declaration of the default fault handlers.
+//
+//*****************************************************************************
+void resetISR(void);
+static void nmiSR(void);
+static void faultISR(void);
+static void intDefaultHandler(void);
+
+//*****************************************************************************
+//
+// External declaration for the interrupt handler used by the application.
+//
+//*****************************************************************************
+extern void SysTick_Handler( void );
+extern void PendSV_Handler( void );
+extern void SVC_Handler( void );
+extern void vUART_Handler( void );
+extern void vT32_0_Handler( void );
+extern void vT32_1_Handler( void );
+//*****************************************************************************
+//
+// The entry point for the application startup code.
+//
+//*****************************************************************************
+extern void __iar_program_start(void);
+
+//*****************************************************************************
+//
+// Reserve space for the system stack.
+//
+//*****************************************************************************
+static uint32_t systemStack[128] @ ".noinit";
+
+//*****************************************************************************
+//
+// A union that describes the entries of the vector table.  The union is needed
+// since the first entry is the stack pointer and the remainder are function
+// pointers.
+//
+//*****************************************************************************
+typedef union
+{
+    void (*handler)(void);
+    uint32_t ptr;
+}
+uVectorEntry;
+
+//*****************************************************************************
+//
+// The vector table.  Note that the proper constructs must be placed on this to
+// ensure that it ends up at physical address 0x0000.0000.
+//
+//*****************************************************************************
+__root const uVectorEntry __vector_table[] @ ".intvec" =
+{
+    { .ptr = (uint32_t)systemStack + sizeof(systemStack) },
+                                            // The initial stack pointer
+    resetISR,                               // The reset handler
+    nmiSR,                                  // The NMI handler
+    faultISR,                               // The hard fault handler
+    intDefaultHandler,                             // The MPU fault handler
+    intDefaultHandler,                             // The bus fault handler
+    intDefaultHandler,                             // The usage fault handler
+    0,                                      // Reserved
+    0,                                      // Reserved
+    0,                                      // Reserved
+    0,                                      // Reserved
+    SVC_Handler,                             // SVCall handler
+    intDefaultHandler,                             // Debug monitor handler
+    0,                                      // Reserved
+    PendSV_Handler,                             // The PendSV handler
+    SysTick_Handler,                            // The SysTick handler
+    intDefaultHandler,                             // PSS ISR
+    intDefaultHandler,                             // CS ISR
+    intDefaultHandler,                             // PCM ISR
+    intDefaultHandler,                             // WDT ISR
+    intDefaultHandler,                             // FPU ISR
+    intDefaultHandler,                             // FLCTL ISR
+    intDefaultHandler,                             // COMP0 ISR
+    intDefaultHandler,                             // COMP1 ISR
+    intDefaultHandler,                             // TA0_0 ISR
+    intDefaultHandler,                             // TA0_N ISR
+    intDefaultHandler,                            // TA1_0 ISR
+    intDefaultHandler,                             // TA1_N ISR
+    intDefaultHandler,                            // TA2_0 ISR
+    intDefaultHandler,                             // TA2_N ISR
+    intDefaultHandler,                             // TA3_0 ISR
+    intDefaultHandler,                             // TA3_N ISR
+    vUART_Handler,                            // EUSCIA0 ISR
+    intDefaultHandler,                             // EUSCIA1 ISR
+    intDefaultHandler,                             // EUSCIA2 ISR
+    intDefaultHandler,                             // EUSCIA3 ISR
+    intDefaultHandler,                             // EUSCIB0 ISR
+    intDefaultHandler,                             // EUSCIB1 ISR
+    intDefaultHandler,                             // EUSCIB2 ISR
+    intDefaultHandler,                             // EUSCIB3 ISR
+    intDefaultHandler,                             // ADC14 ISR
+    vT32_0_Handler,                                // T32_INT1 ISR
+    vT32_1_Handler,                                // T32_INT2 ISR
+    intDefaultHandler,                             // T32_INTC ISR
+    intDefaultHandler,                             // AES ISR
+    intDefaultHandler,                             // RTC ISR
+    intDefaultHandler,                             // DMA_ERR ISR
+    intDefaultHandler,                             // DMA_INT3 ISR
+    intDefaultHandler,                             // DMA_INT2 ISR
+    intDefaultHandler,                             // DMA_INT1 ISR
+    intDefaultHandler,                             // DMA_INT0 ISR
+    intDefaultHandler,                        // PORT1 ISR
+    intDefaultHandler,                             // PORT2 ISR
+    intDefaultHandler,                             // PORT3 ISR
+    intDefaultHandler,                             // PORT4 ISR
+    intDefaultHandler,                             // PORT5 ISR
+    intDefaultHandler,                             // PORT6 ISR
+    intDefaultHandler,                             // Reserved 41
+    intDefaultHandler,                             // Reserved 42
+    intDefaultHandler,                             // Reserved 43
+    intDefaultHandler,                             // Reserved 44
+    intDefaultHandler,                             // Reserved 45
+    intDefaultHandler,                             // Reserved 46
+    intDefaultHandler,                             // Reserved 47
+    intDefaultHandler,                             // Reserved 48
+    intDefaultHandler,                             // Reserved 49
+    intDefaultHandler,                             // Reserved 50
+    intDefaultHandler,                             // Reserved 51
+    intDefaultHandler,                             // Reserved 52
+    intDefaultHandler,                             // Reserved 53
+    intDefaultHandler,                             // Reserved 54
+    intDefaultHandler,                             // Reserved 55
+    intDefaultHandler,                             // Reserved 56
+    intDefaultHandler,                             // Reserved 57
+    intDefaultHandler,                             // Reserved 58
+    intDefaultHandler,                             // Reserved 59
+    intDefaultHandler,                             // Reserved 60
+    intDefaultHandler,                             // Reserved 61
+    intDefaultHandler,                             // Reserved 62
+    intDefaultHandler,                             // Reserved 63
+    intDefaultHandler                              // Reserved 64
+};
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor first starts execution
+// following a reset event.  Only the absolutely necessary set is performed,
+// after which the application supplied entry() routine is called.  Any fancy
+// actions (such as making decisions based on the reset cause register, and
+// resetting the bits in that register) are left solely in the hands of the
+// application.
+//
+//*****************************************************************************
+void
+resetISR(void)
+{
+
+    WDTCTL = WDTPW | WDTHOLD;               // Stop WDT
+
+    //
+    // Call the application's entry point.
+    //
+    __iar_program_start();
+}
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor receives a NMI.  This
+// simply enters an infinite loop, preserving the system state for examination
+// by a debugger.
+//
+//*****************************************************************************
+static void
+nmiSR(void)
+{
+    //
+    // Enter an infinite loop.
+    //
+    while(1)
+    {
+    }
+}
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor receives a fault
+// interrupt.  This simply enters an infinite loop, preserving the system state
+// for examination by a debugger.
+//
+//*****************************************************************************
+static void
+faultISR(void)
+{
+    //
+    // Enter an infinite loop.
+    //
+    while(1)
+    {
+    }
+}
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor receives an unexpected
+// interrupt.  This simply enters an infinite loop, preserving the system state
+// for examination by a debugger.
+//
+//*****************************************************************************
+static void
+intDefaultHandler(void)
+{
+    //
+    // Go into an infinite loop.
+    //
+    while(1)
+    {
+    }
+}
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/Keil/startup_MSP432P4.s b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/Keil/startup_MSP432P4.s
new file mode 100644
index 000000000..2d84037dd
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/Keil/startup_MSP432P4.s
@@ -0,0 +1,201 @@
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000200
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+				IMPORT	vUART_Handler
+				IMPORT	vT32_0_Handler
+				IMPORT	vT32_1_Handler
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     IntDefault_Handler        ; PSS ISR
+                DCD     IntDefault_Handler        ; CS ISR 
+                DCD     IntDefault_Handler        ; PCM ISR
+                DCD     IntDefault_Handler        ; WDT ISR
+                DCD     IntDefault_Handler        ; FPU ISR
+                DCD     IntDefault_Handler        ; FLCTL ISR
+                DCD     IntDefault_Handler        ; COMP0 ISR
+                DCD     IntDefault_Handler        ; COMP1 ISR
+                DCD     IntDefault_Handler        ; TA0_0 ISR 
+                DCD     IntDefault_Handler        ; TA0_N ISR
+                DCD     IntDefault_Handler        ; TA1_0 ISR
+                DCD     IntDefault_Handler        ; TA1_N ISR
+                DCD     IntDefault_Handler        ; TA2_0 ISR
+                DCD     IntDefault_Handler        ; TA2_N ISR
+                DCD     IntDefault_Handler        ; TA3_0 ISR
+                DCD     IntDefault_Handler        ; TA3_N ISR
+                DCD     vUART_Handler             ; EUSCIA0 ISR
+                DCD     IntDefault_Handler        ; EUSCIA1 ISR
+                DCD     IntDefault_Handler        ; EUSCIA2 ISR
+                DCD     IntDefault_Handler        ; EUSCIA3 ISR
+                DCD     IntDefault_Handler        ; EUSCIB0 ISR
+                DCD     IntDefault_Handler        ; EUSCIB1 ISR
+                DCD     IntDefault_Handler        ; EUSCIB2 ISR
+                DCD     IntDefault_Handler        ; EUSCIB3 ISR
+                DCD     IntDefault_Handler        ; ADC12 ISR
+                DCD     vT32_0_Handler            ; T32_INT1 ISR
+                DCD     vT32_1_Handler            ; T32_INT2 ISR
+                DCD     IntDefault_Handler        ; T32_INTC ISR
+                DCD     IntDefault_Handler        ; AES ISR
+                DCD     IntDefault_Handler        ; RTC ISR
+                DCD     IntDefault_Handler        ; DMA_ERR ISR
+                DCD     IntDefault_Handler        ; DMA_INT3 ISR
+                DCD     IntDefault_Handler        ; DMA_INT2 ISR
+                DCD     IntDefault_Handler        ; DMA_INT1 ISR
+                DCD     IntDefault_Handler        ; DMA_INT0 ISR
+                DCD     IntDefault_Handler        ; PORT1 ISR
+                DCD     IntDefault_Handler        ; PORT2 ISR
+                DCD     IntDefault_Handler        ; PORT3 ISR
+                DCD     IntDefault_Handler        ; PORT4 ISR
+                DCD     IntDefault_Handler        ; PORT5 ISR
+                DCD     IntDefault_Handler        ; PORT6 ISR
+                DCD     IntDefault_Handler        ; Reserved 41
+                DCD     IntDefault_Handler        ; Reserved 42
+                DCD     IntDefault_Handler        ; Reserved 43
+                DCD     IntDefault_Handler        ; Reserved 44
+                DCD     IntDefault_Handler        ; Reserved 45
+                DCD     IntDefault_Handler        ; Reserved 46
+                DCD     IntDefault_Handler        ; Reserved 47
+                DCD     IntDefault_Handler        ; Reserved 48
+                DCD     IntDefault_Handler        ; Reserved 49
+                DCD     IntDefault_Handler        ; Reserved 50
+                DCD     IntDefault_Handler        ; Reserved 51
+                DCD     IntDefault_Handler        ; Reserved 52
+                DCD     IntDefault_Handler        ; Reserved 53
+                DCD     IntDefault_Handler        ; Reserved 54
+                DCD     IntDefault_Handler        ; Reserved 55
+                DCD     IntDefault_Handler        ; Reserved 56
+                DCD     IntDefault_Handler        ; Reserved 57
+                DCD     IntDefault_Handler        ; Reserved 58
+                DCD     IntDefault_Handler        ; Reserved 59
+                DCD     IntDefault_Handler        ; Reserved 60
+                DCD     IntDefault_Handler        ; Reserved 61
+                DCD     IntDefault_Handler        ; Reserved 62
+                DCD     IntDefault_Handler        ; Reserved 63
+                DCD     IntDefault_Handler        ; Reserved 64
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+IntDefault_Handler PROC
+                EXPORT  IntDefault_Handler        [WEAK]
+                B       .
+                ENDP
+
+                ALIGN
+
+                
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/Keil/system_MSP432P4.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/Keil/system_MSP432P4.c
new file mode 100644
index 000000000..b82206424
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/Keil/system_MSP432P4.c
@@ -0,0 +1,68 @@
+//*****************************************************************************
+//
+// Copyright (C) 2012 - 2014 Texas Instruments Incorporated - http://www.ti.com/ 
+//
+// Redistribution and use in source and binary forms, with or without 
+// modification, are permitted provided that the following conditions 
+// are met:
+//
+//  Redistributions of source code must retain the above copyright 
+//  notice, this list of conditions and the following disclaimer.
+//
+//  Redistributions in binary form must reproduce the above copyright
+//  notice, this list of conditions and the following disclaimer in the 
+//  documentation and/or other materials provided with the   
+//  distribution.
+//
+//  Neither the name of Texas Instruments Incorporated nor the names of
+//  its contributors may be used to endorse or promote products derived
+//  from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// MSP432 Startup File
+//
+// File creation date: 2014-07-08
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include "msp432.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __SYSTEM_CLOCK    (2000000)
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;  /*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  Initialize the system
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+	WDT_A->rCTL.r = WDTPW + WDTHOLD;
+}
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Blinky_Demo/main_blinky.c
index b2d55da41..b2d55da41 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/Blinky_Demo/main_blinky.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Blinky_Demo/main_blinky.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/FreeRTOSConfig.h
index 485682531..485682531 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/FreeRTOSConfig.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/FreeRTOSConfig.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Full_Demo/IntQueueTimer.c
index caf151531..caf151531 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/Full_Demo/IntQueueTimer.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Full_Demo/IntQueueTimer.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Full_Demo/IntQueueTimer.h
index 528e6fdfb..528e6fdfb 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/Full_Demo/IntQueueTimer.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Full_Demo/IntQueueTimer.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/Full_Demo/RegTest.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Full_Demo/RegTest.c
index 3a2bbfad4..3a2bbfad4 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/Full_Demo/RegTest.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Full_Demo/RegTest.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/Full_Demo/RegTest.s b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Full_Demo/RegTest.s
index a24d27ae0..a24d27ae0 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/Full_Demo/RegTest.s
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Full_Demo/RegTest.s
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/Full_Demo/main_full.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Full_Demo/main_full.c
index 730b72bd7..730b72bd7 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/Full_Demo/main_full.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Full_Demo/main_full.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/JLinkSettings.ini b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/JLinkSettings.ini
index 4722ca16d..4722ca16d 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/JLinkSettings.ini
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/JLinkSettings.ini
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/RTE/RTE_Components.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTE/RTE_Components.h
index d1d509ed5..d1d509ed5 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/RTE/RTE_Components.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTE/RTE_Components.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/RTOSDemo.ewd b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.ewd
index 7495986d0..7495986d0 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/RTOSDemo.ewd
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.ewd
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/RTOSDemo.ewp b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.ewp
index fd1663bc1..3e2aa4647 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/RTOSDemo.ewp
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.ewp
@@ -60,12 +60,12 @@
         </option>
         <option>
           <name>FPU</name>
-          <version>3</version>
-          <state>7</state>
+          <version>4</version>
+          <state>9</state>
         </option>
         <option>
           <name>OGCoreOrChip</name>
-          <state>0</state>
+          <state>1</state>
         </option>
         <option>
           <name>GRuntimeLibSelect</name>
@@ -87,7 +87,7 @@
         </option>
         <option>
           <name>OGLastSavedByProductVersion</name>
-          <state>7.30.4.8186</state>
+          <state>7.40.1.8463</state>
         </option>
         <option>
           <name>GeneralEnableMisra</name>
@@ -99,7 +99,7 @@
         </option>
         <option>
           <name>OGChipSelectEditMenu</name>
-          <state>default	None</state>
+          <state>ATSAMV71Q21	Atmel ATSAMV71Q21</state>
         </option>
         <option>
           <name>GenLowLevelInterface</name>
@@ -310,7 +310,7 @@
           <state>$PROJ_DIR$\Full_Demo</state>
           <state>$PROJ_DIR$\..\Common\include</state>
           <state>$PROJ_DIR$\..\..\Source\include</state>
-          <state>C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Source\portable\IAR\ARM_CM7\r0p1</state>
+          <state>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM7\r0p1</state>
         </option>
         <option>
           <name>CCStdIncCheck</name>
@@ -1013,7 +1013,7 @@
         </option>
         <option>
           <name>FPU</name>
-          <version>3</version>
+          <version>4</version>
           <state>0</state>
         </option>
         <option>
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/RTOSDemo.ewt b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.ewt
index cf404a77f..cf404a77f 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/RTOSDemo.ewt
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.ewt
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/RTOSDemo.eww b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.eww
index 239a9381e..239a9381e 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/RTOSDemo.eww
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.eww
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/RTOSDemo.uvoptx b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.uvoptx
index 39c48192f..39c48192f 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/RTOSDemo.uvoptx
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.uvoptx
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/RTOSDemo.uvprojx b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.uvprojx
index 404fee89c..404fee89c 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/RTOSDemo.uvprojx
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.uvprojx
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/board.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/board.h
index a048e49d0..a048e49d0 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/board.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/board.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/CS2100.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/CS2100.h
index 6e4c4abb1..6e4c4abb1 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/CS2100.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/CS2100.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/at25_spi.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/at25_spi.h
index bc36b229e..bc36b229e 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/at25_spi.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/at25_spi.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/at25d.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/at25d.h
index 067c35864..067c35864 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/at25d.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/at25d.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/bmp.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/bmp.h
index 76bda4c80..76bda4c80 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/bmp.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/bmp.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/board_lowlevel.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/board_lowlevel.h
index 2ccb82c22..2ccb82c22 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/board_lowlevel.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/board_lowlevel.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/board_memories.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/board_memories.h
index 029dea13e..029dea13e 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/board_memories.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/board_memories.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/dbg_console.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/dbg_console.h
index bf045ffbe..bf045ffbe 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/dbg_console.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/dbg_console.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/frame_buffer.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/frame_buffer.h
index 08114e62b..08114e62b 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/frame_buffer.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/frame_buffer.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/gmacb_phy.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/gmacb_phy.h
index cb67ce8eb..cb67ce8eb 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/gmacb_phy.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/gmacb_phy.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/gmii.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/gmii.h
index e7d05d1a0..e7d05d1a0 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/gmii.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/gmii.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/hamming.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/hamming.h
index df66e380c..df66e380c 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/hamming.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/hamming.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/ili9488.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/ili9488.h
index d9868fd3d..d9868fd3d 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/ili9488.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/ili9488.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/ili9488_reg.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/ili9488_reg.h
index c656260eb..c656260eb 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/ili9488_reg.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/ili9488_reg.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/lcd_color.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/lcd_color.h
index 684934dc2..684934dc2 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/lcd_color.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/lcd_color.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/lcd_draw.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/lcd_draw.h
index e9b6cbf5f..e9b6cbf5f 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/lcd_draw.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/lcd_draw.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/lcd_font.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/lcd_font.h
index 64667ddba..64667ddba 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/lcd_font.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/lcd_font.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/lcd_font10x14.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/lcd_font10x14.h
index a4886154f..a4886154f 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/lcd_font10x14.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/lcd_font10x14.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/lcd_gimp_image.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/lcd_gimp_image.h
index 9ea6436b9..9ea6436b9 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/lcd_gimp_image.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/lcd_gimp_image.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/lcdd.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/lcdd.h
index c548a4f99..c548a4f99 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/lcdd.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/lcdd.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/led.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/led.h
index 4f7da31a3..4f7da31a3 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/led.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/led.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/math.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/math.h
index a05f0352f..a05f0352f 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/math.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/math.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/omnivision.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/omnivision.h
index 577b7dc6e..577b7dc6e 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/omnivision.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/omnivision.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/ov.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/ov.h
index 929039cc3..929039cc3 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/ov.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/ov.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/ovyuv.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/ovyuv.h
index 6bf2d8e9b..6bf2d8e9b 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/ovyuv.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/ovyuv.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/s25fl1.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/s25fl1.h
index d6270deb7..d6270deb7 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/s25fl1.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/s25fl1.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/s25fl1_qspi.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/s25fl1_qspi.h
index a439893c3..a439893c3 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/s25fl1_qspi.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/s25fl1_qspi.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/syscalls.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/syscalls.h
index 10e81a373..10e81a373 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/syscalls.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/syscalls.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/timetick.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/timetick.h
index fdeb9beac..fdeb9beac 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/timetick.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/timetick.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/wav.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/wav.h
index be75b9157..be75b9157 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/wav.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/wav.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/wm8904.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/wm8904.h
index 065d69d48..065d69d48 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/include/wm8904.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/include/wm8904.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/qspi_flash.icf b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/qspi_flash.icf
index bbcd2051e..bbcd2051e 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/qspi_flash.icf
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/qspi_flash.icf
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv7-ek-flash.mac b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv7-ek-flash.mac
index 608087654..608087654 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv7-ek-flash.mac
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv7-ek-flash.mac
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv7-ek-sram.mac b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv7-ek-sram.mac
index c1d99cffa..c1d99cffa 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv7-ek-sram.mac
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv7-ek-sram.mac
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv70j19_flash.icf b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv70j19_flash.icf
index 781e7bf6e..781e7bf6e 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv70j19_flash.icf
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv70j19_flash.icf
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv70j19_sram.icf b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv70j19_sram.icf
index 1d5f8e24a..1d5f8e24a 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv70j19_sram.icf
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv70j19_sram.icf
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv70j20_flash.icf b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv70j20_flash.icf
index ef598ec8c..ef598ec8c 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv70j20_flash.icf
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv70j20_flash.icf
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv70j20_sram.icf b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv70j20_sram.icf
index f6830f3fc..f6830f3fc 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv70j20_sram.icf
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv70j20_sram.icf
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv70n19_flash.icf b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv70n19_flash.icf
index 2388a7ee4..2388a7ee4 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv70n19_flash.icf
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv70n19_flash.icf
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv70n19_sram.icf b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv70n19_sram.icf
index c854e3aa7..c854e3aa7 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv70n19_sram.icf
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv70n19_sram.icf
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv70n20_flash.icf b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv70n20_flash.icf
index 3107959e2..3107959e2 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv70n20_flash.icf
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv70n20_flash.icf
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv70n20_sram.icf b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv70n20_sram.icf
index f6830f3fc..f6830f3fc 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv70n20_sram.icf
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv70n20_sram.icf
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv70q19_flash.icf b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv70q19_flash.icf
index ef598ec8c..ef598ec8c 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv70q19_flash.icf
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv70q19_flash.icf
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv70q19_sram.icf b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv70q19_sram.icf
index f6830f3fc..f6830f3fc 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv70q19_sram.icf
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv70q19_sram.icf
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv70q20_flash.icf b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv70q20_flash.icf
index 2388a7ee4..2388a7ee4 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv70q20_flash.icf
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv70q20_flash.icf
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv70q20_sram.icf b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv70q20_sram.icf
index c854e3aa7..c854e3aa7 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv70q20_sram.icf
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv70q20_sram.icf
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71j19_flash.icf b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71j19_flash.icf
index 781e7bf6e..781e7bf6e 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71j19_flash.icf
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71j19_flash.icf
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71j19_sram.icf b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71j19_sram.icf
index 1d5f8e24a..1d5f8e24a 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71j19_sram.icf
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71j19_sram.icf
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71j20_flash.icf b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71j20_flash.icf
index ef598ec8c..ef598ec8c 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71j20_flash.icf
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71j20_flash.icf
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71j20_sram.icf b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71j20_sram.icf
index f6830f3fc..f6830f3fc 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71j20_sram.icf
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71j20_sram.icf
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71j21_flash.icf b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71j21_flash.icf
index 97827fb19..97827fb19 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71j21_flash.icf
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71j21_flash.icf
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71j21_sram.icf b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71j21_sram.icf
index c854e3aa7..c854e3aa7 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71j21_sram.icf
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71j21_sram.icf
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71n19_flash.icf b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71n19_flash.icf
index 2388a7ee4..2388a7ee4 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71n19_flash.icf
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71n19_flash.icf
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71n19_sram.icf b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71n19_sram.icf
index c854e3aa7..c854e3aa7 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71n19_sram.icf
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71n19_sram.icf
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71n20_flash.icf b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71n20_flash.icf
index 781e7bf6e..781e7bf6e 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71n20_flash.icf
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71n20_flash.icf
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71n20_sram.icf b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71n20_sram.icf
index 1d5f8e24a..1d5f8e24a 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71n20_sram.icf
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71n20_sram.icf
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71n21_flash.icf b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71n21_flash.icf
index ce5d7b5aa..ce5d7b5aa 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71n21_flash.icf
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71n21_flash.icf
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71n21_sram.icf b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71n21_sram.icf
index 1d5f8e24a..1d5f8e24a 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71n21_sram.icf
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71n21_sram.icf
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71q19_flash.icf b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71q19_flash.icf
index 3107959e2..3107959e2 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71q19_flash.icf
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71q19_flash.icf
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71q19_sram.icf b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71q19_sram.icf
index f6830f3fc..f6830f3fc 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71q19_sram.icf
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71q19_sram.icf
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71q20_flash.icf b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71q20_flash.icf
index 2388a7ee4..2388a7ee4 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71q20_flash.icf
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71q20_flash.icf
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71q20_sram.icf b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71q20_sram.icf
index c854e3aa7..c854e3aa7 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71q20_sram.icf
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71q20_sram.icf
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71q21_flash.icf b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71q21_flash.icf
index 97827fb19..97827fb19 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71q21_flash.icf
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71q21_flash.icf
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71q21_sram.icf b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71q21_sram.icf
index 2e5d9e432..2e5d9e432 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/samv71q21_sram.icf
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/samv71q21_sram.icf
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/startup_sam.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/startup_sam.c
index 8bc9e3847..8bc9e3847 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/IAR/startup_sam.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/IAR/startup_sam.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/mdk/flash.sct b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/mdk/flash.sct
index 2155fe357..2155fe357 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/mdk/flash.sct
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/mdk/flash.sct
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/mdk/retarget.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/mdk/retarget.c
index 5c21cc2b0..5c21cc2b0 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/mdk/retarget.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/mdk/retarget.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/mdk/samv7-sram.ini b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/mdk/samv7-sram.ini
index 2403ad346..2403ad346 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/mdk/samv7-sram.ini
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/mdk/samv7-sram.ini
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/mdk/sram.sct b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/mdk/sram.sct
index 126e16366..126e16366 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/mdk/sram.sct
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/mdk/sram.sct
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/mdk/startup_sam.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/mdk/startup_sam.c
index fde41d61c..fde41d61c 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/mdk/startup_sam.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/mdk/startup_sam.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/mdk/workaround.s b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/mdk/workaround.s
index aa08c7ee0..aa08c7ee0 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/mdk/workaround.s
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/mdk/workaround.s
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/system_sam.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/system_sam.c
index e6430d7f3..e6430d7f3 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/resources/system_sam.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/resources/system_sam.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/CS2100.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/CS2100.c
index fdab05f65..fdab05f65 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/CS2100.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/CS2100.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/at25_spi.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/at25_spi.c
index 762696b5e..762696b5e 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/at25_spi.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/at25_spi.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/at25d.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/at25d.c
index cfdd40d30..cfdd40d30 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/at25d.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/at25d.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/board_lowlevel.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/board_lowlevel.c
index 7a3891654..7a3891654 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/board_lowlevel.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/board_lowlevel.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/board_memories.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/board_memories.c
index 4cf374356..4cf374356 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/board_memories.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/board_memories.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/dbg_console.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/dbg_console.c
index 7ec9ff496..7ec9ff496 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/dbg_console.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/dbg_console.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/gmacb_phy.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/gmacb_phy.c
index ada9179f0..ada9179f0 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/gmacb_phy.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/gmacb_phy.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/hamming.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/hamming.c
index d17b1eb7e..d17b1eb7e 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/hamming.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/hamming.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/ili9488.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/ili9488.c
index f54c609e9..f54c609e9 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/ili9488.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/ili9488.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/lcd_draw.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/lcd_draw.c
index db30bee68..db30bee68 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/lcd_draw.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/lcd_draw.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/lcd_font.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/lcd_font.c
index 468c68f37..468c68f37 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/lcd_font.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/lcd_font.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/lcd_font10x14.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/lcd_font10x14.c
index 470743369..470743369 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/lcd_font10x14.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/lcd_font10x14.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/lcd_fontsize.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/lcd_fontsize.c
index 237114ee4..237114ee4 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/lcd_fontsize.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/lcd_fontsize.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/lcdd.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/lcdd.c
index f5a9a4551..f5a9a4551 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/lcdd.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/lcdd.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/led.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/led.c
index 9da11f40f..9da11f40f 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/led.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/led.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/math.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/math.c
index e70ebeb83..e70ebeb83 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/math.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/math.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/omnivision.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/omnivision.c
index fbb631f63..fbb631f63 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/omnivision.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/omnivision.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/ov.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/ov.c
index 134b30321..134b30321 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/ov.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/ov.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/ov2640_config.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/ov2640_config.c
index c28c6e45e..c28c6e45e 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/ov2640_config.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/ov2640_config.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/ov2643_config.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/ov2643_config.c
index 904830fc7..904830fc7 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/ov2643_config.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/ov2643_config.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/ov5640_config.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/ov5640_config.c
index d9b5b9d81..d9b5b9d81 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/ov5640_config.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/ov5640_config.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/ov7740_config.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/ov7740_config.c
index 8fac279b2..8fac279b2 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/ov7740_config.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/ov7740_config.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/ov9740_config.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/ov9740_config.c
index c730bb153..c730bb153 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/ov9740_config.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/ov9740_config.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/s25fl1.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/s25fl1.c
index dbfdafaa3..dbfdafaa3 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/s25fl1.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/s25fl1.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/s25fl1_qspi.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/s25fl1_qspi.c
index d084f2e59..d084f2e59 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/s25fl1_qspi.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/s25fl1_qspi.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/syscalls.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/syscalls.c
index 39291fa63..39291fa63 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/syscalls.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/syscalls.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/trace.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/trace.c
index 7ba2b24e2..7ba2b24e2 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/trace.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/trace.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/wav.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/wav.c
index 2a74b0391..2a74b0391 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/wav.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/wav.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/wm8904.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/wm8904.c
index c1266f68a..c1266f68a 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libboard_samv7-ek/source/wm8904.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libboard_samv7-ek/source/wm8904.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/chip.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/chip.h
index 432d3ee03..432d3ee03 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/chip.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/chip.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/acc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/acc.h
index b60cc43f1..b60cc43f1 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/acc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/acc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/adc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/adc.h
index 9ecce25d3..9ecce25d3 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/adc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/adc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/aes.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/aes.h
index d67940b0d..d67940b0d 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/aes.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/aes.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/afe_dma.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/afe_dma.h
index 591199305..591199305 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/afe_dma.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/afe_dma.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/afec.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/afec.h
index df4364afc..df4364afc 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/afec.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/afec.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/can.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/can.h
index b594dc049..b594dc049 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/can.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/can.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/cmsis/ARM.CMSIS.pdsc b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/ARM.CMSIS.pdsc
index 66b1f5b9a..66b1f5b9a 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/cmsis/ARM.CMSIS.pdsc
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/ARM.CMSIS.pdsc
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/cmsis/CMSIS/Include/arm_common_tables.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/CMSIS/Include/arm_common_tables.h
index c7818749e..c7818749e 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/cmsis/CMSIS/Include/arm_common_tables.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/CMSIS/Include/arm_common_tables.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/cmsis/CMSIS/Include/arm_const_structs.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/CMSIS/Include/arm_const_structs.h
index 55295ddad..55295ddad 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/cmsis/CMSIS/Include/arm_const_structs.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/CMSIS/Include/arm_const_structs.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/cmsis/CMSIS/Include/arm_math.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/CMSIS/Include/arm_math.h
index 919611602..919611602 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/cmsis/CMSIS/Include/arm_math.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/CMSIS/Include/arm_math.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/cmsis/CMSIS/Include/core_cm0.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/CMSIS/Include/core_cm0.h
index c5c820efc..c5c820efc 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/cmsis/CMSIS/Include/core_cm0.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/CMSIS/Include/core_cm0.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/cmsis/CMSIS/Include/core_cm0plus.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/CMSIS/Include/core_cm0plus.h
index f835ee091..f835ee091 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/cmsis/CMSIS/Include/core_cm0plus.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/CMSIS/Include/core_cm0plus.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/cmsis/CMSIS/Include/core_cm3.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/CMSIS/Include/core_cm3.h
index c8145652f..c8145652f 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/cmsis/CMSIS/Include/core_cm3.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/CMSIS/Include/core_cm3.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/cmsis/CMSIS/Include/core_cm4.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/CMSIS/Include/core_cm4.h
index 36f637ee7..36f637ee7 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/cmsis/CMSIS/Include/core_cm4.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/CMSIS/Include/core_cm4.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/cmsis/CMSIS/Include/core_cm4_simd.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/CMSIS/Include/core_cm4_simd.h
index bee997ed6..bee997ed6 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/cmsis/CMSIS/Include/core_cm4_simd.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/CMSIS/Include/core_cm4_simd.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/cmsis/CMSIS/Include/core_cm7.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/CMSIS/Include/core_cm7.h
index 40336c3ce..40336c3ce 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/cmsis/CMSIS/Include/core_cm7.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/CMSIS/Include/core_cm7.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/cmsis/CMSIS/Include/core_cmFunc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/CMSIS/Include/core_cmFunc.h
index 8b37e0e74..8b37e0e74 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/cmsis/CMSIS/Include/core_cmFunc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/CMSIS/Include/core_cmFunc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/cmsis/CMSIS/Include/core_cmInstr.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/CMSIS/Include/core_cmInstr.h
index 86066313b..86066313b 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/cmsis/CMSIS/Include/core_cmInstr.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/CMSIS/Include/core_cmInstr.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/cmsis/CMSIS/Include/core_cmSimd.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/CMSIS/Include/core_cmSimd.h
index bd092a7ce..bd092a7ce 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/cmsis/CMSIS/Include/core_cmSimd.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/CMSIS/Include/core_cmSimd.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/cmsis/CMSIS/Include/core_sc000.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/CMSIS/Include/core_sc000.h
index 03e361424..03e361424 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/cmsis/CMSIS/Include/core_sc000.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/CMSIS/Include/core_sc000.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/cmsis/CMSIS/Include/core_sc300.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/CMSIS/Include/core_sc300.h
index 3b5e570fd..3b5e570fd 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/cmsis/CMSIS/Include/core_sc300.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/CMSIS/Include/core_sc300.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/dac_dma.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/dac_dma.h
index 1ea173acc..1ea173acc 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/dac_dma.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/dac_dma.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/dacc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/dacc.h
index ce92fe292..ce92fe292 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/dacc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/dacc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/efc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/efc.h
index 21bc53105..21bc53105 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/efc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/efc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/exceptions.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/exceptions.h
index 70eab196d..70eab196d 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/exceptions.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/exceptions.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/flashd.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/flashd.h
index 7274e9d0d..7274e9d0d 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/flashd.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/flashd.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/gmac.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/gmac.h
index 9cc380828..9cc380828 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/gmac.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/gmac.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/gmacd.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/gmacd.h
index 2f776e392..2f776e392 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/gmacd.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/gmacd.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/hsmci.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/hsmci.h
index ffff415fb..ffff415fb 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/hsmci.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/hsmci.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/icm.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/icm.h
index 25221bcbc..25221bcbc 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/icm.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/icm.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/isi.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/isi.h
index da81ce75e..da81ce75e 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/isi.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/isi.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/mcid.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/mcid.h
index b600be4de..b600be4de 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/mcid.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/mcid.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/mediaLB.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/mediaLB.h
index bcf68b7c0..bcf68b7c0 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/mediaLB.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/mediaLB.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/mpu.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/mpu.h
index a4d2d43af..a4d2d43af 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/mpu.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/mpu.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/pio.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/pio.h
index 4d185eb00..4d185eb00 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/pio.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/pio.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/pio_capture.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/pio_capture.h
index fe90617ae..fe90617ae 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/pio_capture.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/pio_capture.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/pio_it.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/pio_it.h
index 83ef4dc9a..83ef4dc9a 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/pio_it.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/pio_it.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/pmc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/pmc.h
index 9ea71b59a..9ea71b59a 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/pmc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/pmc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/pwmc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/pwmc.h
index d91a6e790..d91a6e790 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/pwmc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/pwmc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/qspi.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/qspi.h
index e60aa8aa6..e60aa8aa6 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/qspi.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/qspi.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/qspi_dma.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/qspi_dma.h
index 9c86b9fdc..9c86b9fdc 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/qspi_dma.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/qspi_dma.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/rstc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/rstc.h
index 367bf4683..367bf4683 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/rstc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/rstc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/rtc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/rtc.h
index e14a29cec..e14a29cec 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/rtc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/rtc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/rtt.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/rtt.h
index 5a3e44c43..5a3e44c43 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/rtt.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/rtt.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_acc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_acc.h
index 8944734cb..8944734cb 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_acc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_acc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_aes.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_aes.h
index a62c6899a..a62c6899a 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_aes.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_aes.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_afec.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_afec.h
index 6e45ac97c..6e45ac97c 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_afec.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_afec.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_chipid.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_chipid.h
index 3802cd309..3802cd309 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_chipid.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_chipid.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_dacc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_dacc.h
index 6f4e2f957..6f4e2f957 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_dacc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_dacc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_efc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_efc.h
index 47c676351..47c676351 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_efc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_efc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_gmac.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_gmac.h
index a0ce0a972..a0ce0a972 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_gmac.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_gmac.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_gpbr.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_gpbr.h
index a8052fc49..a8052fc49 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_gpbr.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_gpbr.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_hsmci.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_hsmci.h
index c68111aa6..c68111aa6 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_hsmci.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_hsmci.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_icm.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_icm.h
index 37d539369..37d539369 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_icm.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_icm.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_isi.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_isi.h
index 78c236da5..78c236da5 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_isi.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_isi.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_matrix.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_matrix.h
index 30ddefbd6..30ddefbd6 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_matrix.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_matrix.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_pio.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_pio.h
index bb6b174f4..bb6b174f4 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_pio.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_pio.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_pmc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_pmc.h
index 46a69fb51..46a69fb51 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_pmc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_pmc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_pwm.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_pwm.h
index c2f8aabed..c2f8aabed 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_pwm.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_pwm.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_qspi.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_qspi.h
index 415e486fb..415e486fb 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_qspi.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_qspi.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_rstc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_rstc.h
index fd3a1e323..fd3a1e323 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_rstc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_rstc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_rtc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_rtc.h
index 41aa1018c..41aa1018c 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_rtc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_rtc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_rtt.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_rtt.h
index 86568cd7e..86568cd7e 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_rtt.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_rtt.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_sdramc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_sdramc.h
index cc23e225b..cc23e225b 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_sdramc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_sdramc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_smc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_smc.h
index 028a9c91e..028a9c91e 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_smc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_smc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_spi.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_spi.h
index 2e8c4d09b..2e8c4d09b 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_spi.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_spi.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_ssc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_ssc.h
index c42dcc3d4..c42dcc3d4 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_ssc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_ssc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_supc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_supc.h
index 53c1e9ef4..53c1e9ef4 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_supc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_supc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_tc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_tc.h
index 83cf4f4ba..83cf4f4ba 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_tc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_tc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_trng.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_trng.h
index 24cd38c2a..24cd38c2a 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_trng.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_trng.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_twi.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_twi.h
index 9a40cd38b..9a40cd38b 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_twi.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_twi.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_twihs.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_twihs.h
index 30c296330..30c296330 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_twihs.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_twihs.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_uart.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_uart.h
index c9dbf8e82..c9dbf8e82 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_uart.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_uart.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_uotghs.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_uotghs.h
index 884a668dd..884a668dd 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_uotghs.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_uotghs.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_usart.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_usart.h
index 18fa01422..18fa01422 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_usart.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_usart.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_wdt.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_wdt.h
index 3a34c5653..3a34c5653 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_wdt.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_wdt.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_xdmac.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_xdmac.h
index 90dc14477..90dc14477 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/component/component_xdmac.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_xdmac.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_acc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_acc.h
index ee8d224e7..ee8d224e7 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_acc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_acc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_aes.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_aes.h
index 63fdb02d1..63fdb02d1 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_aes.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_aes.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_afec0.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_afec0.h
index f3bbf3837..f3bbf3837 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_afec0.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_afec0.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_afec1.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_afec1.h
index cd55bc3e5..cd55bc3e5 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_afec1.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_afec1.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_chipid.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_chipid.h
index 3b040b3ba..3b040b3ba 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_chipid.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_chipid.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_dacc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_dacc.h
index 0e396482a..0e396482a 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_dacc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_dacc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_efc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_efc.h
index 7dd536613..7dd536613 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_efc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_efc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_gmac.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_gmac.h
index 7ca16d90f..7ca16d90f 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_gmac.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_gmac.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_gpbr.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_gpbr.h
index 120340f04..120340f04 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_gpbr.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_gpbr.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_hsmci.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_hsmci.h
index fd2590807..fd2590807 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_hsmci.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_hsmci.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_icm.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_icm.h
index 2ebf37104..2ebf37104 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_icm.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_icm.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_isi.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_isi.h
index 10ac068e7..10ac068e7 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_isi.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_isi.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_matrix.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_matrix.h
index c71a85f04..c71a85f04 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_matrix.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_matrix.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_pioa.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_pioa.h
index 838ff9b90..838ff9b90 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_pioa.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_pioa.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_piob.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_piob.h
index 5a6e48704..5a6e48704 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_piob.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_piob.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_pioc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_pioc.h
index a75521d3f..a75521d3f 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_pioc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_pioc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_piod.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_piod.h
index beec52f0f..beec52f0f 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_piod.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_piod.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_pioe.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_pioe.h
index e674696c0..e674696c0 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_pioe.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_pioe.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_pmc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_pmc.h
index 3edc7e867..3edc7e867 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_pmc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_pmc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_pwm0.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_pwm0.h
index e0c650554..e0c650554 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_pwm0.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_pwm0.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_pwm1.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_pwm1.h
index a57ce1caf..a57ce1caf 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_pwm1.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_pwm1.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_qspi.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_qspi.h
index 49eaf0967..49eaf0967 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_qspi.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_qspi.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_rstc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_rstc.h
index 969cb2f71..969cb2f71 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_rstc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_rstc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_rtc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_rtc.h
index a16370d99..a16370d99 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_rtc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_rtc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_rtt.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_rtt.h
index 95a85c2a8..95a85c2a8 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_rtt.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_rtt.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_sdramc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_sdramc.h
index edb017193..edb017193 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_sdramc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_sdramc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_smc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_smc.h
index da260c87f..da260c87f 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_smc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_smc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_spi0.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_spi0.h
index baef0363b..baef0363b 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_spi0.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_spi0.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_spi1.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_spi1.h
index a99761a90..a99761a90 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_spi1.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_spi1.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_ssc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_ssc.h
index cacb4e781..cacb4e781 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_ssc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_ssc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_supc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_supc.h
index 9d4bc471d..9d4bc471d 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_supc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_supc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_tc0.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_tc0.h
index 5bad5429f..5bad5429f 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_tc0.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_tc0.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_tc1.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_tc1.h
index aa027fdde..aa027fdde 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_tc1.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_tc1.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_tc2.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_tc2.h
index dc523241f..dc523241f 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_tc2.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_tc2.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_tc3.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_tc3.h
index fa9c215fe..fa9c215fe 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_tc3.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_tc3.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_trng.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_trng.h
index d9565ec31..d9565ec31 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_trng.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_trng.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_twi0.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_twi0.h
index dacf72c9c..dacf72c9c 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_twi0.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_twi0.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_twi1.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_twi1.h
index 5d6a7e381..5d6a7e381 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_twi1.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_twi1.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_twi2.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_twi2.h
index d4297ba08..d4297ba08 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_twi2.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_twi2.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_uart0.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_uart0.h
index c22bd7268..c22bd7268 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_uart0.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_uart0.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_uart1.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_uart1.h
index fdc9da3bd..fdc9da3bd 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_uart1.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_uart1.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_uart2.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_uart2.h
index dafba883b..dafba883b 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_uart2.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_uart2.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_uart3.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_uart3.h
index 166d73b72..166d73b72 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_uart3.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_uart3.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_uart4.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_uart4.h
index 13708291d..13708291d 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_uart4.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_uart4.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_usart0.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_usart0.h
index addd3aec9..addd3aec9 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_usart0.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_usart0.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_usart1.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_usart1.h
index 7fdd8e0ed..7fdd8e0ed 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_usart1.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_usart1.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_usart2.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_usart2.h
index f196505e8..f196505e8 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_usart2.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_usart2.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_usbhs.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_usbhs.h
index ca35edf80..ca35edf80 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_usbhs.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_usbhs.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_wdt0.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_wdt0.h
index 4d0428385..4d0428385 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_wdt0.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_wdt0.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_wdt1.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_wdt1.h
index d8b4afc05..d8b4afc05 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_wdt1.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_wdt1.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_xdmac.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_xdmac.h
index 7a08554af..7a08554af 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_xdmac.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/instance/instance_xdmac.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/pio/pio_samv70j19.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/pio/pio_samv70j19.h
index fd22eab43..fd22eab43 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/pio/pio_samv70j19.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/pio/pio_samv70j19.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/pio/pio_samv70j20.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/pio/pio_samv70j20.h
index 93f6afc11..93f6afc11 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/pio/pio_samv70j20.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/pio/pio_samv70j20.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/pio/pio_samv70n19.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/pio/pio_samv70n19.h
index 83fb6f58b..83fb6f58b 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/pio/pio_samv70n19.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/pio/pio_samv70n19.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/pio/pio_samv70n20.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/pio/pio_samv70n20.h
index df2c66403..df2c66403 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/pio/pio_samv70n20.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/pio/pio_samv70n20.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/pio/pio_samv70q19.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/pio/pio_samv70q19.h
index bb2fbbae1..bb2fbbae1 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/pio/pio_samv70q19.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/pio/pio_samv70q19.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/pio/pio_samv70q20.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/pio/pio_samv70q20.h
index 87cce7ac2..87cce7ac2 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/pio/pio_samv70q20.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/pio/pio_samv70q20.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/pio/pio_samv71j19.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/pio/pio_samv71j19.h
index 06c52f917..06c52f917 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/pio/pio_samv71j19.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/pio/pio_samv71j19.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/pio/pio_samv71j20.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/pio/pio_samv71j20.h
index 2c44fdba6..2c44fdba6 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/pio/pio_samv71j20.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/pio/pio_samv71j20.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/pio/pio_samv71j21.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/pio/pio_samv71j21.h
index 6ba26f303..6ba26f303 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/pio/pio_samv71j21.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/pio/pio_samv71j21.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/pio/pio_samv71n19.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/pio/pio_samv71n19.h
index 64514acb7..64514acb7 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/pio/pio_samv71n19.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/pio/pio_samv71n19.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/pio/pio_samv71n20.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/pio/pio_samv71n20.h
index c33078002..c33078002 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/pio/pio_samv71n20.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/pio/pio_samv71n20.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/pio/pio_samv71n21.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/pio/pio_samv71n21.h
index 0c5a75a48..0c5a75a48 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/pio/pio_samv71n21.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/pio/pio_samv71n21.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/pio/pio_samv71q19.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/pio/pio_samv71q19.h
index 84cd00f4e..84cd00f4e 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/pio/pio_samv71q19.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/pio/pio_samv71q19.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/pio/pio_samv71q20.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/pio/pio_samv71q20.h
index 6b21c08f9..6b21c08f9 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/pio/pio_samv71q20.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/pio/pio_samv71q20.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/pio/pio_samv71q21.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/pio/pio_samv71q21.h
index 58b975190..58b975190 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/pio/pio_samv71q21.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/pio/pio_samv71q21.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/sam.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/sam.h
index 80aed0ba2..80aed0ba2 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/sam.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/sam.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/samv70j19.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/samv70j19.h
index d17f908d1..d17f908d1 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/samv70j19.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/samv70j19.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/samv70j20.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/samv70j20.h
index b10287fc9..b10287fc9 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/samv70j20.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/samv70j20.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/samv70n19.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/samv70n19.h
index c9471a1ac..c9471a1ac 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/samv70n19.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/samv70n19.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/samv70n20.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/samv70n20.h
index df60d9644..df60d9644 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/samv70n20.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/samv70n20.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/samv70q19.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/samv70q19.h
index 99d5d907d..99d5d907d 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/samv70q19.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/samv70q19.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/samv70q20.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/samv70q20.h
index 546ec0a1c..546ec0a1c 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/samv70q20.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/samv70q20.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/samv71j19.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/samv71j19.h
index 6a90361d1..6a90361d1 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/samv71j19.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/samv71j19.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/samv71j20.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/samv71j20.h
index 398549ce0..398549ce0 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/samv71j20.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/samv71j20.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/samv71j21.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/samv71j21.h
index d747df143..d747df143 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/samv71j21.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/samv71j21.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/samv71n19.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/samv71n19.h
index 0ee2f4b4d..0ee2f4b4d 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/samv71n19.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/samv71n19.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/samv71n20.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/samv71n20.h
index 55544fbcc..55544fbcc 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/samv71n20.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/samv71n20.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/samv71n21.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/samv71n21.h
index 32bef2bee..32bef2bee 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/samv71n21.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/samv71n21.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/samv71q19.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/samv71q19.h
index e1e64ee75..e1e64ee75 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/samv71q19.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/samv71q19.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/samv71q20.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/samv71q20.h
index fcc89a9bf..fcc89a9bf 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/samv71q20.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/samv71q20.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/samv71q21.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/samv71q21.h
index 24263cb2c..24263cb2c 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/samv71q21.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/samv71q21.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/system_sam.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/system_sam.h
index 9f9bb0e57..9f9bb0e57 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/system_sam.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/system_sam.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/sdramc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/sdramc.h
index 875706092..875706092 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/sdramc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/sdramc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/smc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/smc.h
index c75368059..c75368059 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/smc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/smc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/spi.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/spi.h
index eddcd4fb0..eddcd4fb0 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/spi.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/spi.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/spi_dma.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/spi_dma.h
index dff814cc6..dff814cc6 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/spi_dma.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/spi_dma.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/ssc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/ssc.h
index fb66189c8..fb66189c8 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/ssc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/ssc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/supc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/supc.h
index a26a65bfa..a26a65bfa 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/supc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/supc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/tc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/tc.h
index 68cdd2d37..68cdd2d37 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/tc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/tc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/timetick.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/timetick.h
index fdeb9beac..fdeb9beac 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/timetick.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/timetick.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/trace.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/trace.h
index 4c3270a12..4c3270a12 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/trace.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/trace.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/trng.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/trng.h
index 7e87637e8..7e87637e8 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/trng.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/trng.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/twi.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/twi.h
index 9e3835543..9e3835543 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/twi.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/twi.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/twid.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/twid.h
index 301d2a75d..301d2a75d 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/twid.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/twid.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/uart.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/uart.h
index c5989d547..c5989d547 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/uart.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/uart.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/uart_dma.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/uart_dma.h
index 8e1fac2ff..8e1fac2ff 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/uart_dma.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/uart_dma.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/udphs.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/udphs.h
index 93de7001a..93de7001a 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/udphs.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/udphs.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/usart.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/usart.h
index 3cd82dcd7..3cd82dcd7 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/usart.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/usart.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/usart_dma.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/usart_dma.h
index 1c9633e68..1c9633e68 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/usart_dma.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/usart_dma.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/video.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/video.h
index f0bb6f9ff..f0bb6f9ff 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/video.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/video.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/wdt.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/wdt.h
index 1a2789b34..1a2789b34 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/wdt.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/wdt.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/xdma_hardware_interface.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/xdma_hardware_interface.h
index da8d7e36b..da8d7e36b 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/xdma_hardware_interface.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/xdma_hardware_interface.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/xdmac.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/xdmac.h
index b82c4497a..b82c4497a 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/xdmac.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/xdmac.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/xdmad.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/xdmad.h
index c2ea67ef4..c2ea67ef4 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/xdmad.h
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/xdmad.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/USBDCallbacks_Initialized.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/USBDCallbacks_Initialized.c
index 985bd09c6..985bd09c6 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/USBDCallbacks_Initialized.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/USBDCallbacks_Initialized.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/USBDCallbacks_Resumed.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/USBDCallbacks_Resumed.c
index 68cc8fda1..68cc8fda1 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/USBDCallbacks_Resumed.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/USBDCallbacks_Resumed.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/USBDCallbacks_Suspended.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/USBDCallbacks_Suspended.c
index 018b9d18e..018b9d18e 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/USBDCallbacks_Suspended.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/USBDCallbacks_Suspended.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/USBD_HAL.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/USBD_HAL.c
index b84cc4d00..b84cc4d00 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/USBD_HAL.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/USBD_HAL.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/acc.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/acc.c
index 7a825dec4..7a825dec4 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/acc.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/acc.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/aes.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/aes.c
index 57d4e4c4c..57d4e4c4c 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/aes.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/aes.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/afe_dma.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/afe_dma.c
index a6638b80a..a6638b80a 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/afe_dma.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/afe_dma.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/afec.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/afec.c
index 60318e38d..60318e38d 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/afec.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/afec.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/can.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/can.c
index 0ef9d5c2c..0ef9d5c2c 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/can.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/can.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/dac_dma.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/dac_dma.c
index 05dab14d7..05dab14d7 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/dac_dma.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/dac_dma.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/dacc.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/dacc.c
index a929d031c..a929d031c 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/dacc.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/dacc.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/efc.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/efc.c
index 5d3ed0931..5d3ed0931 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/efc.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/efc.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/exceptions.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/exceptions.c
index bd3deef9a..bd3deef9a 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/exceptions.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/exceptions.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/flashd.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/flashd.c
index 60da2cc9b..60da2cc9b 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/flashd.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/flashd.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/gmac.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/gmac.c
index 051de667a..051de667a 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/gmac.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/gmac.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/gmacd.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/gmacd.c
index d5fd27f7d..d5fd27f7d 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/gmacd.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/gmacd.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/hsmci.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/hsmci.c
index d5e06440c..d5e06440c 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/hsmci.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/hsmci.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/icm.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/icm.c
index 370f2d424..370f2d424 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/icm.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/icm.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/isi.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/isi.c
index 14e7e19d4..14e7e19d4 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/isi.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/isi.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/mcid_dma.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/mcid_dma.c
index 0a722c2e5..0a722c2e5 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/mcid_dma.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/mcid_dma.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/mediaLB.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/mediaLB.c
index 992e7198f..992e7198f 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/mediaLB.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/mediaLB.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/mpu.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/mpu.c
index a53736ac3..a53736ac3 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/mpu.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/mpu.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/pio.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/pio.c
index 087aa7846..087aa7846 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/pio.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/pio.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/pio_capture.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/pio_capture.c
index a8da01595..a8da01595 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/pio_capture.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/pio_capture.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/pio_it.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/pio_it.c
index 543923a18..543923a18 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/pio_it.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/pio_it.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/pmc.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/pmc.c
index 35074cd51..35074cd51 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/pmc.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/pmc.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/pwmc.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/pwmc.c
index a9f348e7d..a9f348e7d 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/pwmc.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/pwmc.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/qspi.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/qspi.c
index b0ec601ab..b0ec601ab 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/qspi.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/qspi.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/qspi_dma.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/qspi_dma.c
index 4d88db942..4d88db942 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/qspi_dma.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/qspi_dma.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/rstc.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/rstc.c
index af5c3fe7a..af5c3fe7a 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/rstc.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/rstc.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/rtc.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/rtc.c
index c30c9d5c2..c30c9d5c2 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/rtc.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/rtc.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/rtt.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/rtt.c
index 8aca550ae..8aca550ae 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/rtt.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/rtt.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/sdramc.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/sdramc.c
index d3297ac51..d3297ac51 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/sdramc.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/sdramc.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/smc.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/smc.c
index 60b6b97dd..60b6b97dd 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/smc.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/smc.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/spi.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/spi.c
index e15094f47..e15094f47 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/spi.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/spi.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/spi_dma.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/spi_dma.c
index ac76513e0..ac76513e0 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/spi_dma.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/spi_dma.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/ssc.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/ssc.c
index 8b8b28520..8b8b28520 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/ssc.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/ssc.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/supc.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/supc.c
index 54113a28f..54113a28f 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/supc.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/supc.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/tc.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/tc.c
index be076e1b3..be076e1b3 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/tc.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/tc.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/timetick.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/timetick.c
index c2d201e59..c2d201e59 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/timetick.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/timetick.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/trng.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/trng.c
index 5a4237d17..5a4237d17 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/trng.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/trng.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/twi.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/twi.c
index 9ac6b6272..9ac6b6272 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/twi.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/twi.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/twid.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/twid.c
index 15454fcc5..15454fcc5 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/twid.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/twid.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/uart.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/uart.c
index ccd5e2d52..ccd5e2d52 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/uart.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/uart.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/uart_dma.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/uart_dma.c
index 4bb77c83c..4bb77c83c 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/uart_dma.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/uart_dma.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/usart.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/usart.c
index c69fe7cd9..c69fe7cd9 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/usart.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/usart.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/usart_dma.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/usart_dma.c
index 806606acd..806606acd 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/usart_dma.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/usart_dma.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/wdt.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/wdt.c
index 07187b92c..07187b92c 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/wdt.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/wdt.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/xdma_hardware_interface.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/xdma_hardware_interface.c
index caf4f2e91..caf4f2e91 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/xdma_hardware_interface.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/xdma_hardware_interface.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/xdmac.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/xdmac.c
index da1e44ac3..da1e44ac3 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/xdmac.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/xdmac.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/xdmad.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/xdmad.c
index 3cf6a2ed4..3cf6a2ed4 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/source/xdmad.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/xdmad.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/main.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/main.c
index 168f1d983..168f1d983 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/main.c
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/main.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/settings/RTOSDemo.Debug.cspy.bat b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo.Debug.cspy.bat
index b53e8f8b9..3f1fe57d2 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/settings/RTOSDemo.Debug.cspy.bat
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo.Debug.cspy.bat
@@ -19,6 +19,22 @@
 @REM 
 
 
-"C:\DevTools\IAR Systems\Embedded Workbench 7.0\common\bin\cspybat" "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\bin\armproc.dll" "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\bin\armjlink.dll"  %1 --plugin "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\bin\armbat.dll" --macro "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M7_SAMV71_Xplained\libboard_samv7-ek\resources\IAR\samv7-ek-sram.mac" --backend -B "--endian=little" "--cpu=Cortex-M7" "--fpu=VFPv5_sp" "--drv_verify_download" "--semihosting=none" "--drv_communication=USB0" "--drv_interface_speed=auto" "--jlink_initial_speed=32" "--jlink_reset_strategy=0,0" "--drv_interface=SWD" "--drv_catch_exceptions=0x000" "--drv_swo_clock_setup=0,0,2000000" 
+@echo off 
 
+if not "%1" == "" goto debugFile 
 
+@echo on 
+
+"C:\DevTools\IAR Systems\Embedded Workbench 7.2\common\bin\cspybat" -f "C:\E\temp\FreeRTOSv8.2.1\clean\FreeRTOS\Demo\CORTEX_M7_SAMV71_Xplained_IAR_Keil\settings\RTOSDemo.Debug.general.xcl" --backend -f "C:\E\temp\FreeRTOSv8.2.1\clean\FreeRTOS\Demo\CORTEX_M7_SAMV71_Xplained_IAR_Keil\settings\RTOSDemo.Debug.driver.xcl" 
+
+@echo off 
+goto end 
+
+:debugFile 
+
+@echo on 
+
+"C:\DevTools\IAR Systems\Embedded Workbench 7.2\common\bin\cspybat" -f "C:\E\temp\FreeRTOSv8.2.1\clean\FreeRTOS\Demo\CORTEX_M7_SAMV71_Xplained_IAR_Keil\settings\RTOSDemo.Debug.general.xcl" "--debug_file=%1" --backend -f "C:\E\temp\FreeRTOSv8.2.1\clean\FreeRTOS\Demo\CORTEX_M7_SAMV71_Xplained_IAR_Keil\settings\RTOSDemo.Debug.driver.xcl" 
+
+@echo off 
+:end
+\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/settings/RTOSDemo.crun b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo.crun
index 5bb5acca4..5bb5acca4 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/settings/RTOSDemo.crun
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo.crun
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/settings/RTOSDemo.dbgdt b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo.dbgdt
index 45940b67f..45940b67f 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/settings/RTOSDemo.dbgdt
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo.dbgdt
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/settings/RTOSDemo.dni b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo.dni
index 5a44c98b0..5a44c98b0 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/settings/RTOSDemo.dni
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo.dni
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/settings/RTOSDemo.wsdt b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo.wsdt
index f72ae751f..a92c77bbe 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/settings/RTOSDemo.wsdt
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo.wsdt
@@ -28,7 +28,7 @@
     <Windows>
       
       
-    <Wnd0>
+    <Wnd1>
         <Tabs>
           <Tab>
             <Identity>TabID-23288-9694</Identity>
@@ -40,7 +40,7 @@
           </Tab>
         </Tabs>
         
-      <SelectedTab>0</SelectedTab></Wnd0><Wnd1>
+      <SelectedTab>0</SelectedTab></Wnd1><Wnd4>
         <Tabs>
           <Tab>
             <Identity>TabID-13649-20313</Identity>
@@ -56,7 +56,7 @@
           </Tab>
         <Tab><Identity>TabID-30315-19856</Identity><TabName>Find in Files</TabName><Factory>Find-in-Files</Factory><Session/></Tab></Tabs>
         
-      <SelectedTab>0</SelectedTab></Wnd1></Windows>
+      <SelectedTab>0</SelectedTab></Wnd4></Windows>
     <Editor>
       
       
@@ -69,7 +69,7 @@
       
       
       
-    <Top><Row0><Sizes><Toolbar-00CD8F90><key>iaridepm.enu1</key></Toolbar-00CD8F90></Sizes></Row0><Row1><Sizes/></Row1></Top><Left><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>770</Bottom><Right>272</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>174</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>176829</sizeHorzCY><sizeVertCX>163095</sizeVertCX><sizeVertCY>784553</sizeVertCY></Rect></Wnd0></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>170</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>172</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>174797</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>176829</sizeVertCY></Rect></Wnd1></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>
+    <Top><Row0><Sizes><Toolbar-002A90F0><key>iaridepm.enu1</key></Toolbar-002A90F0></Sizes></Row0></Top><Left><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>770</Bottom><Right>272</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>174</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>176829</sizeHorzCY><sizeVertCX>163095</sizeVertCX><sizeVertCY>784553</sizeVertCY></Rect></Wnd1></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd4><Rect><Top>-2</Top><Left>-2</Left><Bottom>170</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>172</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>174797</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>176829</sizeVertCY></Rect></Wnd4></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>
   </Desktop>
 </Workspace>
 
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo.wspos b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo.wspos
new file mode 100644
index 000000000..cd790b7cf
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo.wspos
@@ -0,0 +1,2 @@
+[MainWindow]
+WindowPlacement=_ 515 5 1615 901 3
diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/settings/RTOSDemo_Debug.jlink b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo_Debug.jlink
index de1b137f3..de1b137f3 100644
--- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/settings/RTOSDemo_Debug.jlink
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo_Debug.jlink
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/settings/RTOSDemo.wspos b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/settings/RTOSDemo.wspos
deleted file mode 100644
index 873f953f2..000000000
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/settings/RTOSDemo.wspos
+++ /dev/null
@@ -1,2 +0,0 @@
-[MainWindow]
-WindowPlacement=_ 16 0 1116 896 3
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Blinky_Demo/main_blinky.c
index 935f4d243..88224713e 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/Blinky_Demo/main_blinky.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Blinky_Demo/main_blinky.c
@@ -123,7 +123,7 @@ the queue empty. */
 #define mainQUEUE_LENGTH					( 1 )
 
 /* The LED is used to show the demo status. */
-#define mainTOGGLE_LED()	HAL_GPIO_TogglePin( GPIOG, GPIO_PIN_6 )
+#define mainTOGGLE_LED()	HAL_GPIO_TogglePin( GPIOF, GPIO_PIN_10 )
 
 /*-----------------------------------------------------------*/
 
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h
index 76948dc7b..675a47b1a 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f746xx.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   CMSIS STM32F746xx Device Peripheral Access Layer Header File.
   *
   *          This file contains:
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/CMSIS/Device/ST/STM32F7xx/Include/stm32f756xx.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Device/ST/STM32F7xx/Include/stm32f756xx.h
index 1b1ad95ff..733850265 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/CMSIS/Device/ST/STM32F7xx/Include/stm32f756xx.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Device/ST/STM32F7xx/Include/stm32f756xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f756xx.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   CMSIS STM32F756xx Device Peripheral Access Layer Header File.
   *
   *          This file contains:
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h
index 11f4d1e13..84251f2de 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   CMSIS STM32F7xx Device Peripheral Access Layer Header File.           
   *            
   *          The file is the unique include file that the application programmer
@@ -95,12 +95,12 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS Device version number V0.2.0
+  * @brief CMSIS Device version number V1.0.0RC1
   */
-#define __STM32F7xx_CMSIS_DEVICE_VERSION_MAIN   (0x00) /*!< [31:24] main version */
-#define __STM32F7xx_CMSIS_DEVICE_VERSION_SUB1   (0x02) /*!< [23:16] sub1 version */
+#define __STM32F7xx_CMSIS_DEVICE_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32F7xx_CMSIS_DEVICE_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version */
 #define __STM32F7xx_CMSIS_DEVICE_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
-#define __STM32F7xx_CMSIS_DEVICE_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
+#define __STM32F7xx_CMSIS_DEVICE_VERSION_RC     (0x01) /*!< [7:0]  release candidate */ 
 #define __STM32F7xx_CMSIS_DEVICE_VERSION        ((__STM32F7xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
                                                 |(__STM32F7xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
                                                 |(__STM32F7xx_CMSIS_DEVICE_VERSION_SUB2 << 8 )\
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h
index 86e8b3355..2dddae018 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f4xx.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   CMSIS Cortex-M7 Device System Source File for STM32F7xx devices.       
   ******************************************************************************  
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/CMSIS/Include/arm_common_tables.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/arm_common_tables.h
index 06a634878..06a634878 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/CMSIS/Include/arm_common_tables.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/arm_common_tables.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/CMSIS/Include/arm_const_structs.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/arm_const_structs.h
index 21c79d692..21c79d692 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/CMSIS/Include/arm_const_structs.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/arm_const_structs.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/CMSIS/Include/arm_math.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/arm_math.h
index 9a1519c41..9a1519c41 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/CMSIS/Include/arm_math.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/arm_math.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/CMSIS/Include/core_cm0.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cm0.h
index dbc4e22d4..dbc4e22d4 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/CMSIS/Include/core_cm0.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cm0.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/CMSIS/Include/core_cm0plus.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cm0plus.h
index 4d7facfa0..4d7facfa0 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/CMSIS/Include/core_cm0plus.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cm0plus.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/CMSIS/Include/core_cm3.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cm3.h
index d41ac3f0b..d41ac3f0b 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/CMSIS/Include/core_cm3.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cm3.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/CMSIS/Include/core_cm4.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cm4.h
index 827dc3847..827dc3847 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/CMSIS/Include/core_cm4.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cm4.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/CMSIS/Include/core_cm7.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cm7.h
index 64436103b..64436103b 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/CMSIS/Include/core_cm7.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cm7.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/CMSIS/Include/core_cmFunc.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cmFunc.h
index a1bd88c2c..a1bd88c2c 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/CMSIS/Include/core_cmFunc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cmFunc.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/CMSIS/Include/core_cmInstr.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cmInstr.h
index cabf4a02d..cabf4a02d 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/CMSIS/Include/core_cmInstr.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cmInstr.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/CMSIS/Include/core_cmSimd.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cmSimd.h
index 046656175..046656175 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/CMSIS/Include/core_cmSimd.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cmSimd.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/CMSIS/Include/core_sc000.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_sc000.h
index 5a0635d2a..5a0635d2a 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/CMSIS/Include/core_sc000.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_sc000.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/CMSIS/Include/core_sc300.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_sc300.h
index d82eab978..d82eab978 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/CMSIS/Include/core_sc300.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_sc300.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/DTCM-RAM.ini b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/DTCM-RAM.ini
index 6eab8b36f..6eab8b36f 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/DTCM-RAM.ini
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/DTCM-RAM.ini
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/FreeRTOSConfig.h
index 924eb1781..924eb1781 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/FreeRTOSConfig.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/FreeRTOSConfig.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Full_Demo/IntQueueTimer.c
index 5364860e0..5364860e0 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/Full_Demo/IntQueueTimer.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Full_Demo/IntQueueTimer.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Full_Demo/IntQueueTimer.h
new file mode 100644
index 000000000..528e6fdfb
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Full_Demo/IntQueueTimer.h
@@ -0,0 +1,78 @@
+/*
+    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+#ifndef INT_QUEUE_TIMER_H
+#define INT_QUEUE_TIMER_H
+
+void vInitialiseTimerForIntQueueTest( void );
+BaseType_t xTimer0Handler( void );
+BaseType_t xTimer1Handler( void );
+
+#endif
+
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/Full_Demo/RegTest_IAR.s b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Full_Demo/RegTest_IAR.s
index a24d27ae0..a24d27ae0 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/Full_Demo/RegTest_IAR.s
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Full_Demo/RegTest_IAR.s
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/Full_Demo/RegTest_Keil.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Full_Demo/RegTest_Keil.c
index 3a2bbfad4..3a2bbfad4 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/Full_Demo/RegTest_Keil.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Full_Demo/RegTest_Keil.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/Full_Demo/main_full.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Full_Demo/main_full.c
index e0546b870..5767ddda4 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/Full_Demo/main_full.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Full_Demo/main_full.c
@@ -169,7 +169,7 @@ purpose of ensuring parameters are passed into tasks correctly. */
 #define mainTIMER_TEST_PERIOD				( 50 )
 
 /* The LED is used to show the demo status. */
-#define mainTOGGLE_LED()	HAL_GPIO_TogglePin( GPIOG, GPIO_PIN_6 )
+#define mainTOGGLE_LED()	HAL_GPIO_TogglePin( GPIOF, GPIO_PIN_10 )
 
 /*-----------------------------------------------------------*/
 
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/JLinkSettings.ini b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/JLinkSettings.ini
index 706cf39a9..706cf39a9 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/JLinkSettings.ini
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/JLinkSettings.ini
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/RTOSDemo.ewd b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/RTOSDemo.ewd
index b41c36ab4..b41c36ab4 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/RTOSDemo.ewd
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/RTOSDemo.ewd
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/RTOSDemo.ewp b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/RTOSDemo.ewp
index 363b1aba1..49159e030 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/RTOSDemo.ewp
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/RTOSDemo.ewp
@@ -60,8 +60,8 @@
         </option>
         <option>
           <name>FPU</name>
-          <version>3</version>
-          <state>7</state>
+          <version>4</version>
+          <state>9</state>
         </option>
         <option>
           <name>OGCoreOrChip</name>
@@ -87,7 +87,7 @@
         </option>
         <option>
           <name>OGLastSavedByProductVersion</name>
-          <state>7.30.4.8186</state>
+          <state>7.40.1.8463</state>
         </option>
         <option>
           <name>GeneralEnableMisra</name>
@@ -99,7 +99,7 @@
         </option>
         <option>
           <name>OGChipSelectEditMenu</name>
-          <state>STM32F7xxx	ST STM32F7xxx</state>
+          <state>STM32F756NG	ST STM32F756NG</state>
         </option>
         <option>
           <name>GenLowLevelInterface</name>
@@ -147,7 +147,7 @@
         </option>
         <option>
           <name>OGUseCmsis</name>
-          <state>1</state>
+          <state>0</state>
         </option>
         <option>
           <name>OGUseCmsisDspLib</name>
@@ -1012,7 +1012,7 @@
         </option>
         <option>
           <name>FPU</name>
-          <version>3</version>
+          <version>4</version>
           <state>0</state>
         </option>
         <option>
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/RTOSDemo.eww b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/RTOSDemo.eww
new file mode 100644
index 000000000..239a9381e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/RTOSDemo.eww
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\RTOSDemo.ewp</path>
+  </project>
+  <batchBuild/>
+</workspace>
+
+
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/RTOSDemo.uvopt b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/RTOSDemo.uvopt
index ec61e0755..ec61e0755 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/RTOSDemo.uvopt
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/RTOSDemo.uvopt
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/RTOSDemo.uvproj b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/RTOSDemo.uvproj
index ac704bd38..ac704bd38 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/RTOSDemo.uvproj
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/RTOSDemo.uvproj
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/Legacy/stm32_hal_legacy.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/Legacy/stm32_hal_legacy.h
index fb7ef2148..57e74f1fa 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/Legacy/stm32_hal_legacy.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/Legacy/stm32_hal_legacy.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32_hal_legacy.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   This file contains aliases definition for the STM32Cube HAL constants 
   *          macros and functions maintained for legacy purpose.
   ******************************************************************************
@@ -277,6 +277,15 @@
   */
 #define GET_GPIO_SOURCE                           GPIO_GET_INDEX
 #define GET_GPIO_INDEX                            GPIO_GET_INDEX
+
+#if defined(STM32F4)
+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDIO
+#endif
+
+#if defined(STM32F7)
+#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC
+#endif
+
 /**
   * @}
   */
@@ -1944,6 +1953,32 @@
 #define __HAL_RCC_OTGFS_FORCE_RESET    __HAL_RCC_USB_OTG_FS_FORCE_RESET
 #define __HAL_RCC_OTGFS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
 
+#if defined(STM32F4)
+#define __HAL_RCC_SDMMC1_CLK_ENABLE        __HAL_RCC_SDIO_CLK_ENABLE
+#define __HAL_RCC_SDMMC1_FORCE_RESET       __HAL_RCC_SDIO_FORCE_RESET
+#define __HAL_RCC_SDMMC1_RELEASE_RESET     __HAL_RCC_SDIO_RELEASE_RESET
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE  __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDMMC1_CLK_ENABLE        __HAL_RCC_SDIO_CLK_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_DISABLE       __HAL_RCC_SDIO_CLK_DISABLE
+#define RCC_PERIPHCLK_SDMMC1               RCC_PERIPHCLK_SDIO
+#define __HAL_RCC_SDMMC1_CONFIG            __HAL_RCC_SDIO_CONFIG
+#define __HAL_RCC_GET_SDMMC1_SOURCE        __HAL_RCC_GET_SDIO_SOURCE
+#endif
+
+#if defined(STM32F7)
+#define __HAL_RCC_SDIO_CLK_ENABLE        __HAL_RCC_SDMMC1_CLK_ENABLE
+#define __HAL_RCC_SDIO_FORCE_RESET       __HAL_RCC_SDMMC1_FORCE_RESET
+#define __HAL_RCC_SDIO_RELEASE_RESET     __HAL_RCC_SDMMC1_RELEASE_RESET
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE  __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDIO_CLK_ENABLE        __HAL_RCC_SDMMC1_CLK_ENABLE
+#define __HAL_RCC_SDIO_CLK_DISABLE       __HAL_RCC_SDMMC1_CLK_DISABLE
+#define RCC_PERIPHCLK_SDIO               RCC_PERIPHCLK_SDMMC1
+#define __HAL_RCC_SDIO_CONFIG            __HAL_RCC_SDMMC1_CONFIG
+#define __HAL_RCC_GET_SDIO_SOURCE        __HAL_RCC_GET_SDMMC1_SOURCE	
+#endif
+
 #define __HAL_RCC_I2SCLK            __HAL_RCC_I2S_CONFIG
 #define __HAL_RCC_I2SCLK_CONFIG     __HAL_RCC_I2S_CONFIG
 
@@ -2069,7 +2104,50 @@
 
 #define SD_OCR_CID_CSD_OVERWRIETE   SD_OCR_CID_CSD_OVERWRITE
 #define SD_CMD_SD_APP_STAUS         SD_CMD_SD_APP_STATUS
-  
+
+#if defined(STM32F4)
+#define  SD_SDMMC_FUNCTION_BUSY     SD_SDIO_FUNCTION_BUSY     
+#define  SD_SDMMC_FUNCTION_FAILED   SD_SDIO_FUNCTION_FAILED   
+#define  SD_SDMMC_UNKNOWN_FUNCTION  SD_SDIO_UNKNOWN_FUNCTION  
+#define  SD_CMD_SDMMC_SEN_OP_COND   SD_CMD_SDIO_SEN_OP_COND   
+#define  SD_CMD_SDMMC_RW_DIRECT     SD_CMD_SDIO_RW_DIRECT     
+#define  SD_CMD_SDMMC_RW_EXTENDED   SD_CMD_SDIO_RW_EXTENDED   
+#define  __HAL_SD_SDMMC_ENABLE      __HAL_SD_SDIO_ENABLE      
+#define  __HAL_SD_SDMMC_DISABLE     __HAL_SD_SDIO_DISABLE     
+#define  __HAL_SD_SDMMC_DMA_ENABLE  __HAL_SD_SDIO_DMA_ENABLE  
+#define  __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL  
+#define  __HAL_SD_SDMMC_ENABLE_IT   __HAL_SD_SDIO_ENABLE_IT   
+#define  __HAL_SD_SDMMC_DISABLE_IT  __HAL_SD_SDIO_DISABLE_IT  
+#define  __HAL_SD_SDMMC_GET_FLAG    __HAL_SD_SDIO_GET_FLAG    
+#define  __HAL_SD_SDMMC_CLEAR_FLAG  __HAL_SD_SDIO_CLEAR_FLAG  
+#define  __HAL_SD_SDMMC_GET_IT      __HAL_SD_SDIO_GET_IT      
+#define  __HAL_SD_SDMMC_CLEAR_IT    __HAL_SD_SDIO_CLEAR_IT    
+#define  SDMMC_STATIC_FLAGS         SDIO_STATIC_FLAGS	       
+#define  SDMMC_CMD0TIMEOUT          SDIO_CMD0TIMEOUT	       
+#define  SD_SDMMC_SEND_IF_COND      SD_SDIO_SEND_IF_COND	   
+#endif
+
+#if defined(STM32F7)
+#define  SD_SDIO_FUNCTION_BUSY     SD_SDMMC_FUNCTION_BUSY    
+#define  SD_SDIO_FUNCTION_FAILED   SD_SDMMC_FUNCTION_FAILED  
+#define  SD_SDIO_UNKNOWN_FUNCTION  SD_SDMMC_UNKNOWN_FUNCTION
+#define  SD_CMD_SDIO_SEN_OP_COND   SD_CMD_SDMMC_SEN_OP_COND
+#define  SD_CMD_SDIO_RW_DIRECT     SD_CMD_SDMMC_RW_DIRECT
+#define  SD_CMD_SDIO_RW_EXTENDED   SD_CMD_SDMMC_RW_EXTENDED
+#define  __HAL_SD_SDIO_ENABLE      __HAL_SD_SDMMC_ENABLE
+#define  __HAL_SD_SDIO_DISABLE     __HAL_SD_SDMMC_DISABLE
+#define  __HAL_SD_SDIO_DMA_ENABLE  __HAL_SD_SDMMC_DMA_ENABLE
+#define  __HAL_SD_SDIO_DMA_DISABL  __HAL_SD_SDMMC_DMA_DISABLE
+#define  __HAL_SD_SDIO_ENABLE_IT   __HAL_SD_SDMMC_ENABLE_IT
+#define  __HAL_SD_SDIO_DISABLE_IT  __HAL_SD_SDMMC_DISABLE_IT
+#define  __HAL_SD_SDIO_GET_FLAG    __HAL_SD_SDMMC_GET_FLAG
+#define  __HAL_SD_SDIO_CLEAR_FLAG  __HAL_SD_SDMMC_CLEAR_FLAG
+#define  __HAL_SD_SDIO_GET_IT      __HAL_SD_SDMMC_GET_IT
+#define  __HAL_SD_SDIO_CLEAR_IT    __HAL_SD_SDMMC_CLEAR_IT
+#define  SDIO_STATIC_FLAGS	      SDMMC_STATIC_FLAGS
+#define  SDIO_CMD0TIMEOUT	      SDMMC_CMD0TIMEOUT
+#define  SD_SDIO_SEND_IF_COND	  SD_SDMMC_SEND_IF_COND
+#endif
 /**
   * @}
   */
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal.h
index 6ac68bd29..fc9f0e392 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   This file contains all the functions prototypes for the HAL 
   *          module driver.
   ******************************************************************************
@@ -142,12 +142,12 @@ void HAL_ResumeTick(void);
 uint32_t HAL_GetHalVersion(void);
 uint32_t HAL_GetREVID(void);
 uint32_t HAL_GetDEVID(void);
-void HAL_EnableDBGSleepMode(void);
-void HAL_DisableDBGSleepMode(void);
-void HAL_EnableDBGStopMode(void);
-void HAL_DisableDBGStopMode(void);
-void HAL_EnableDBGStandbyMode(void);
-void HAL_DisableDBGStandbyMode(void);
+void HAL_DBGMCU_EnableDBGSleepMode(void);
+void HAL_DBGMCU_DisableDBGSleepMode(void);
+void HAL_DBGMCU_EnableDBGStopMode(void);
+void HAL_DBGMCU_DisableDBGStopMode(void);
+void HAL_DBGMCU_EnableDBGStandbyMode(void);
+void HAL_DBGMCU_DisableDBGStandbyMode(void);
 void HAL_EnableCompensationCell(void);
 void HAL_DisableCompensationCell(void);
 void HAL_EnableFMCMemorySwapping(void);
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_adc.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_adc.h
index 02fdaad37..c3058f88f 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_adc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_adc.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_adc.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of ADC HAL extension module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_adc_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_adc_ex.h
index e32ee8168..97ff9dc36 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_adc_ex.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_adc_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_adc.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of ADC HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_can.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_can.h
index db3ce0e46..5f34f1ace 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_can.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_can.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_can.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of CAN HAL module.
   ******************************************************************************
   * @attention
@@ -354,9 +354,7 @@ typedef struct
   */
 #define CAN_FILTER_FIFO0             ((uint8_t)0x00)  /*!< Filter FIFO 0 assignment for filter x */
 #define CAN_FILTER_FIFO1             ((uint8_t)0x01)  /*!< Filter FIFO 1 assignment for filter x */
-/* Legacy defines */
-#define CAN_FilterFIFO0  CAN_FILTER_FIFO0
-#define CAN_FilterFIFO1  CAN_FILTER_FIFO1
+
 /**
   * @}
   */
@@ -452,11 +450,6 @@ typedef struct
 #define CAN_IT_BOF                  ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt         */
 #define CAN_IT_LEC                  ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
 #define CAN_IT_ERR                  ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt           */
-
-/* Flags named as Interrupts : kept only for FW compatibility */
-#define CAN_IT_RQCP0   CAN_IT_TME
-#define CAN_IT_RQCP1   CAN_IT_TME
-#define CAN_IT_RQCP2   CAN_IT_TME
 /**
   * @}
   */
@@ -709,9 +702,6 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
 /** @defgroup CAN_Private_Constants CAN Private Constants
   * @{
   */
-#define CAN_TXSTATUS_FAILED         ((uint8_t)0x00)  /*!< CAN transmission failed */
-#define CAN_TXSTATUS_OK             ((uint8_t)0x01)  /*!< CAN transmission succeeded */
-#define CAN_TXSTATUS_PENDING        ((uint8_t)0x02)  /*!< CAN transmission pending */
 #define CAN_TXSTATUS_NOMAILBOX      ((uint8_t)0x04)  /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
 #define CAN_FLAG_MASK  ((uint32_t)0x000000FF)
 /**
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_cec.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_cec.h
index c368e673f..f1f0b8d05 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_cec.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_cec.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_cec.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of CEC HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_conf_template.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_conf_template.h
index dd38aaa33..08f0bfe75 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_conf_template.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_conf_template.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_conf_template.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   HAL configuration template file. 
   *          This file should be copied to the application folder and renamed
   *          to stm32f7xx_hal_conf.h.
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_cortex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_cortex.h
index f9087f134..4cd926ef9 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_cortex.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_cortex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_cortex.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of CORTEX HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_crc.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_crc.h
index d14e2f84f..7adaca642 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_crc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_crc.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_crc.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of CRC HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_crc_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_crc_ex.h
index 492a20a5b..b42c4fb9b 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_crc_ex.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_crc_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_crc_ex.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of CRC HAL extension module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_cryp.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_cryp.h
index 209a068e4..041063fee 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_cryp.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_cryp.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_cryp.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of CRYP HAL module.
   ******************************************************************************
   * @attention
@@ -139,6 +139,8 @@ typedef enum
   
 typedef struct
 {
+      CRYP_TypeDef             *Instance;        /*!< CRYP registers base address */
+
       CRYP_InitTypeDef         Init;             /*!< CRYP required parameters */
 
       uint8_t                  *pCrypInBuffPtr;  /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
@@ -263,25 +265,29 @@ typedef struct
 
 /**
   * @brief  Enable/Disable the CRYP peripheral.
+  * @param  __HANDLE__: specifies the CRYP handle.
   * @retval None
   */
-#define __HAL_CRYP_ENABLE()  (CRYP->CR |=  CRYP_CR_CRYPEN)
-#define __HAL_CRYP_DISABLE() (CRYP->CR &=  ~CRYP_CR_CRYPEN)
+#define __HAL_CRYP_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  CRYP_CR_CRYPEN)
+#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &=  ~CRYP_CR_CRYPEN)
 
 /**
   * @brief  Flush the data FIFO.
+  * @param  __HANDLE__: specifies the CRYP handle.
   * @retval None
   */
-#define __HAL_CRYP_FIFO_FLUSH() (CRYP->CR |=  CRYP_CR_FFLUSH)
+#define __HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |=  CRYP_CR_FFLUSH)
 
 /**
   * @brief  Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC.
+  * @param  __HANDLE__: specifies the CRYP handle.
   * @param  MODE: The algorithm mode.
   * @retval None
   */
-#define __HAL_CRYP_SET_MODE(MODE)  CRYP->CR |= (uint32_t)(MODE)
+#define __HAL_CRYP_SET_MODE(__HANDLE__, MODE)  ((__HANDLE__)->Instance->CR |= (uint32_t)(MODE))
 
 /** @brief  Check whether the specified CRYP flag is set or not.
+  * @param  __HANDLE__: specifies the CRYP handle.
   * @param  __FLAG__: specifies the flag to check.
   *         This parameter can be one of the following values:
   *            @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data 
@@ -295,31 +301,34 @@ typedef struct
   * @retval The new state of __FLAG__ (TRUE or FALSE).
   */
 
-#define __HAL_CRYP_GET_FLAG(__FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01)?(((CRYP->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
-                                                 (((CRYP->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
+#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
+                                                 ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
 
 /** @brief  Check whether the specified CRYP interrupt is set or not.
+  * @param  __HANDLE__: specifies the CRYP handle.
   * @param  __INTERRUPT__: specifies the interrupt to check.
   *         This parameter can be one of the following values:
   *            @arg CRYP_IT_INRIS: Input FIFO service raw interrupt is pending
   *            @arg CRYP_IT_OUTRIS: Output FIFO service raw interrupt is pending
   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
   */
-#define __HAL_CRYP_GET_IT(__INTERRUPT__) ((CRYP->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
 
 /**
   * @brief  Enable the CRYP interrupt.
+  * @param  __HANDLE__: specifies the CRYP handle.
   * @param  __INTERRUPT__: CRYP Interrupt.
   * @retval None
   */
-#define __HAL_CRYP_ENABLE_IT(__INTERRUPT__) ((CRYP->IMSCR) |= (__INTERRUPT__))
+#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))
 
 /**
   * @brief  Disable the CRYP interrupt.
+  * @param  __HANDLE__: specifies the CRYP handle.
   * @param  __INTERRUPT__: CRYP interrupt.
   * @retval None
   */
-#define __HAL_CRYP_DISABLE_IT(__INTERRUPT__) ((CRYP->IMSCR) &= ~(__INTERRUPT__))
+#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))
 
 /**
   * @}
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_cryp_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_cryp_ex.h
index 94879e2c7..1e5c91b19 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_cryp_ex.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_cryp_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_cryp_ex.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of CRYP HAL Extension module.
   ******************************************************************************
   * @attention
@@ -97,12 +97,13 @@
 /**
   * @brief  Set the phase: Init, header, payload, final. 
   *         This is relevant only for GCM and CCM modes.
+  * @param  __HANDLE__: specifies the CRYP handle.
   * @param  __PHASE__: The phase.
   * @retval None
   */
-#define __HAL_CRYP_SET_PHASE(__PHASE__)  do{CRYP->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\
-                                            CRYP->CR |= (uint32_t)(__PHASE__);\
-                                           }while(0)
+#define __HAL_CRYP_SET_PHASE(__HANDLE__, __PHASE__)  do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\
+                                                        (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
+                                                       }while(0)
 
 /**
   * @}
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_dac.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dac.h
index 81f4a7987..af134eba0 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_dac.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dac.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dac.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of DAC HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_dac_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dac_ex.h
index 2dc0ad29a..739388e35 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_dac_ex.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dac_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dac.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of DAC HAL Extension module.
   ******************************************************************************
   * @attention
@@ -93,15 +93,6 @@
   * @}
   */
 
-/** @defgroup DACEx_wave_Format DAC Wave Format
-  * @{
-  */
-#define DAC_WAVE_NOISE                     ((uint32_t)DAC_CR_WAVE1_0)
-#define DAC_WAVE_TRIANGLE                  ((uint32_t)DAC_CR_WAVE1_1)
-/**
-  * @}
-  */
-
 /**
   * @}
   */
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_dcmi.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dcmi.h
index 41085c312..1cc6c12b5 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_dcmi.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dcmi.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dcmi.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of DCMI HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_dcmi_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dcmi_ex.h
index 0041403b5..14298fe28 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_dcmi_ex.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dcmi_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dcmi_ex.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of DCMI Extension HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_def.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_def.h
index ccb74864a..186f2c71a 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_def.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_def.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_def.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   This file contains HAL common defines, enumeration, macros and 
   *          structures definitions. 
   ******************************************************************************
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_dma.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dma.h
index 1e6d1e95c..0a071cbdf 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_dma.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dma.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dma.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of DMA HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_dma2d.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dma2d.h
index 9fe0a01e7..fec7cc1a5 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_dma2d.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dma2d.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dma2d.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of DMA2D HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_dma_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dma_ex.h
index 69d5250d9..40d647039 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_dma_ex.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dma_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dma_ex.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of DMA HAL extension module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_eth.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_eth.h
index 0e9b80c08..36d422ea8 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_eth.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_eth.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_eth.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of ETH HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_flash.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_flash.h
index 2b5bd8a7c..525026cba 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_flash.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_flash.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_flash.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of FLASH HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_flash_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_flash_ex.h
index eb912ad33..dc6efb17f 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_flash_ex.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_flash_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_flash_ex.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of FLASH HAL Extension module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_gpio.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_gpio.h
index 2e3cec03c..66ce94155 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_gpio.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_gpio.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_gpio.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of GPIO HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_gpio_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_gpio_ex.h
index 11c09a996..2a76e5e64 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_gpio_ex.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_gpio_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_gpio_ex.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of GPIO HAL Extension module.
   ******************************************************************************
   * @attention
@@ -50,20 +50,20 @@
   * @{
   */
 
-/** @addtogroup GPIO 
+/** @defgroup GPIOEx GPIOEx
   * @{
   */ 
 
 /* Exported types ------------------------------------------------------------*/
 
 /* Exported constants --------------------------------------------------------*/
-/** @addtogroup GPIO_Exported_Constants
+/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants
   * @{
   */
   
 /** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection
   * @{
-  */
+  */  
 
 /** 
   * @brief   AF 0 selection  
@@ -201,7 +201,7 @@
   */
 
 /* Exported macro ------------------------------------------------------------*/
-/** @addtogroup GPIO_Exported_Macros
+/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros
   * @{
   */
 /**
@@ -209,19 +209,19 @@
   */
 
 /* Exported functions --------------------------------------------------------*/ 
-/** @addtogroup GPIO_Exported_Functions
+/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions
   * @{
   */
 /**
   * @}
   */
-
 /* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
-/** @addtogroup GPIO_Private_Constants
+/** @defgroup GPIOEx_Private_Constants GPIO Private Constants
   * @{
   */
+
 /**
   * @brief   GPIO pin available on the platform
   */
@@ -244,10 +244,10 @@
   */
 
 /* Private macros ------------------------------------------------------------*/
-/** @addtogroup GPIO_Private_Macros
+/** @defgroup GPIOEx_Private_Macros GPIO Private Macros
   * @{
   */
-/** @defgroup GPIO_Get_Port_Index GPIO Get Port Index
+/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index
   * @{
   */
 #define GPIO_GET_INDEX(__GPIOx__)   (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
@@ -276,9 +276,9 @@
 			(((__INSTANCE__) == GPIOJ) && (((__PIN__) & (GPIOJ_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOJ_PIN_AVAILABLE)) == (GPIOJ_PIN_AVAILABLE))) || \
 			(((__INSTANCE__) == GPIOK) && (((__PIN__) & (GPIOK_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOK_PIN_AVAILABLE)) == (GPIOK_PIN_AVAILABLE))) || \
 			(((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE))))
-/** @defgroup GPIO_IS_Alternate_function_selection GPIO Check Alternate Function
+/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function
   * @{
-  */  
+  */   
 #define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF1_TIM1)        || \
                           ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
                           ((AF) == GPIO_AF0_MCO)       || ((AF) == GPIO_AF1_TIM2)       || \
@@ -318,7 +318,7 @@
   */
 
 /* Private functions ---------------------------------------------------------*/
-/** @addtogroup GPIO_Private_Functions
+/** @defgroup GPIOEx_Private_Functions GPIO Private Functions
   * @{
   */
 
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_hash.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_hash.h
index cc851d2a6..9595a3592 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_hash.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_hash.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_hash.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of HASH HAL module.
   ******************************************************************************
   * @attention
@@ -243,16 +243,6 @@ typedef struct
 #define __HAL_HASH_GET_FLAG(__FLAG__) ((HASH->SR & (__FLAG__)) == (__FLAG__))
 
 /**
-  * @brief  Macros for HMAC finish.
-  * @param  None
-  * @retval None
-  */
-#define HAL_HMAC_MD5_Finish          HAL_HASH_MD5_Finish
-#define HAL_HMAC_SHA1_Finish         HAL_HASH_SHA1_Finish
-#define HAL_HMAC_SHA224_Finish       HAL_HASH_SHA224_Finish
-#define HAL_HMAC_SHA256_Finish       HAL_HASH_SHA256_Finish
-
-/**
   * @brief  Enable the multiple DMA mode. 
   *         This feature is available only in STM32F429x and STM32F439x devices.
   * @retval None
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_hash_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_hash_ex.h
index 55cd70df6..be0a0b3f4 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_hash_ex.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_hash_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_hash_ex.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of HASH HAL Extension module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_hcd.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_hcd.h
index aba9c05b6..b002488eb 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_hcd.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_hcd.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_hcd.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of HCD HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_i2c.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_i2c.h
index a6e754c3c..1e6cdc050 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_i2c.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_i2c.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_i2c.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of I2C HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_i2c_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_i2c_ex.h
index 9e69a6d30..3ca8d18a3 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_i2c_ex.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_i2c_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_i2c_ex.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of I2C HAL Extension module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_i2s.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_i2s.h
index a5a26d092..9b8859a91 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_i2s.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_i2s.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_i2s.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of I2S HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_irda.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_irda.h
index 00888db6f..3aa2f0f9d 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_irda.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_irda.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_irda.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of IRDA HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_irda_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_irda_ex.h
index fe9441dd6..490be91f6 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_irda_ex.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_irda_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_irda_ex.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of IRDA HAL Extension module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_iwdg.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_iwdg.h
index 46ad22f11..b344f386c 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_iwdg.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_iwdg.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_iwdg.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of IWDG HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_lptim.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_lptim.h
index d523f48b8..933edbdac 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_lptim.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_lptim.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_lptim.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of LPTIM HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_ltdc.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_ltdc.h
index e2355ff53..ae8bf95cb 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_ltdc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_ltdc.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_ltdc.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of LTDC HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_nand.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_nand.h
index bd714438d..863202272 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_nand.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_nand.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_nand.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of NAND HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_nor.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_nor.h
index fcb7435ab..b66a998b6 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_nor.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_nor.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_nor.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of NOR HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_pcd.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_pcd.h
index e4aa2f672..258aff085 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_pcd.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_pcd.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_pcd.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of PCD HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_pcd_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_pcd_ex.h
index 3fce1b383..7be7e920f 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_pcd_ex.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_pcd_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_pcd_ex.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of PCD HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_pwr.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_pwr.h
index 2af69d181..5b0c632d9 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_pwr.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_pwr.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_pwr.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of PWR HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_pwr_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_pwr_ex.h
index 033542f89..4daef8999 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_pwr_ex.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_pwr_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_pwr_ex.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of PWR HAL Extension module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_qspi.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_qspi.h
index d0f9e4374..59d1d5a73 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_qspi.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_qspi.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_qspi.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of QSPI HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_rcc.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_rcc.h
index 1797f174f..a7d0c8edc 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_rcc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_rcc.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_rcc.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of RCC HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_rcc_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_rcc_ex.h
index 35f781090..71bdeedec 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_rcc_ex.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_rcc_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_rcc_ex.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of RCC HAL Extension module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_rng.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_rng.h
index a0ca3cf39..e798979a5 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_rng.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_rng.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_rng.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of RNG HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_rtc.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_rtc.h
index 909630959..3cf94b953 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_rtc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_rtc.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_rtc.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of RTC HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_rtc_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_rtc_ex.h
index d5e6f9617..ba78c032d 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_rtc_ex.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_rtc_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_rtc_ex.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of RTC HAL Extension module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_sai.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_sai.h
index 8d1a98cb2..897616ff1 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_sai.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_sai.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_sai.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of SAI HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_sai_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_sai_ex.h
index c874ac7a3..f50030642 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_sai_ex.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_sai_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_sai_ex.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of SAI Extension HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_sd.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_sd.h
index 8ba70cb6c..48455c06d 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_sd.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_sd.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_sd.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of SD HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_sdram.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_sdram.h
index 28b0ab766..0c0bae435 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_sdram.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_sdram.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_sdram.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of SDRAM HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_smartcard.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_smartcard.h
index 43e7efad5..3af5fe215 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_smartcard.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_smartcard.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_smartcard.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of SMARTCARD HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_smartcard_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_smartcard_ex.h
index 849f71a1a..b7031612c 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_smartcard_ex.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_smartcard_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_smartcard_ex.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of SMARTCARD HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_spdifrx.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_spdifrx.h
index 201de7897..e0b633739 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_spdifrx.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_spdifrx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_spdifrx.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of SPDIFRX HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_spi.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_spi.h
index 898a2e7b9..29bc4bba2 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_spi.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_spi.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_spi.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of SPI HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_sram.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_sram.h
index 8a183ea3f..0c369f590 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_sram.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_sram.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_sram.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of SRAM HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_tim.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_tim.h
index cc095428a..73e3a8764 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_tim.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_tim.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_tim.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of TIM HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_tim_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_tim_ex.h
index f8e31ca84..27c49052a 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_tim_ex.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_tim_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_tim_ex.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of TIM HAL Extension module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_uart.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_uart.h
index b9c389b64..938fade77 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_uart.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_uart.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_uart.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of UART HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_uart_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_uart_ex.h
index 9f37eca21..2ee1aa504 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_uart_ex.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_uart_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_uart_ex.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of UART HAL Extension module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_usart.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_usart.h
index f15b69b5f..12fd6f8ac 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_usart.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_usart.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_usart.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of USART HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_usart_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_usart_ex.h
index ee4fde1c3..d1efcf2cb 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_usart_ex.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_usart_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_usart_ex.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of USART HAL Extension module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_wwdg.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_wwdg.h
index cd5f68ca9..b734f078a 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_hal_wwdg.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_wwdg.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_wwdg.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of WWDG HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_ll_fmc.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_ll_fmc.h
index 873bfb466..f07dcaeeb 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_ll_fmc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_ll_fmc.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_ll_fmc.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of FMC HAL module.
   ******************************************************************************
   * @attention
@@ -461,7 +461,7 @@ typedef struct
   uint32_t ContinuousClock;              /*!< Enables or disables the FMC clock output to external memory devices.
                                               This parameter is only enabled through the FMC_BCR1 register, and don't care 
                                               through FMC_BCR2..4 registers.
-                                              This parameter can be a value of @ref FMC_CONTINUOUS_Clock                  */
+                                              This parameter can be a value of @ref FMC_Continous_Clock                  */
 
   uint32_t WriteFifo;                    /*!< Enables or disables the write FIFO used by the FMC controller.
                                               This parameter is only enabled through the FMC_BCR1 register, and don't care 
@@ -809,7 +809,7 @@ typedef struct
   * @}
   */
   
-/** @defgroup FMC_Continous_Clock FMC Continous Clock
+/** @defgroup FMC_Continous_Clock FMC Continuous Clock
   * @{
   */
 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY          ((uint32_t)0x00000000)
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_ll_sdmmc.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_ll_sdmmc.h
index 05a61dee8..61ef151f9 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_ll_sdmmc.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_ll_sdmmc.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_ll_sdmmc.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of SDMMC HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_ll_usb.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_ll_usb.h
index 657542701..d72d1daff 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/include/stm32f7xx_ll_usb.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_ll_usb.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_ll_usb.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Header file of USB Core HAL module.
   ******************************************************************************
   * @attention
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal.c
index a481e86eb..29fa2cf84 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   HAL module driver.
   *          This is the common part of the HAL initialization
   *
@@ -65,12 +65,12 @@
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
 /**
- * @brief STM32F7xx HAL Driver version number V0.1.0
+ * @brief STM32F7xx HAL Driver version number V1.0.0RC1
    */
-#define __STM32F7xx_HAL_VERSION_MAIN   (0x00) /*!< [31:24] main version */
-#define __STM32F7xx_HAL_VERSION_SUB1   (0x01) /*!< [23:16] sub1 version */
+#define __STM32F7xx_HAL_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32F7xx_HAL_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version */
 #define __STM32F7xx_HAL_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
-#define __STM32F7xx_HAL_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
+#define __STM32F7xx_HAL_VERSION_RC     (0x01) /*!< [7:0]  release candidate */ 
 #define __STM32F7xx_HAL_VERSION         ((__STM32F7xx_HAL_VERSION_MAIN << 24)\
                                         |(__STM32F7xx_HAL_VERSION_SUB1 << 16)\
                                         |(__STM32F7xx_HAL_VERSION_SUB2 << 8 )\
@@ -374,7 +374,7 @@ uint32_t HAL_GetDEVID(void)
   * @brief  Enable the Debug Module during SLEEP mode
   * @retval None
   */
-void HAL_EnableDBGSleepMode(void)
+void HAL_DBGMCU_EnableDBGSleepMode(void)
 {
   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
 }
@@ -383,7 +383,7 @@ void HAL_EnableDBGSleepMode(void)
   * @brief  Disable the Debug Module during SLEEP mode
   * @retval None
   */
-void HAL_DisableDBGSleepMode(void)
+void HAL_DBGMCU_DisableDBGSleepMode(void)
 {
   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
 }
@@ -392,7 +392,7 @@ void HAL_DisableDBGSleepMode(void)
   * @brief  Enable the Debug Module during STOP mode
   * @retval None
   */
-void HAL_EnableDBGStopMode(void)
+void HAL_DBGMCU_EnableDBGStopMode(void)
 {
   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
 }
@@ -401,7 +401,7 @@ void HAL_EnableDBGStopMode(void)
   * @brief  Disable the Debug Module during STOP mode
   * @retval None
   */
-void HAL_DisableDBGStopMode(void)
+void HAL_DBGMCU_DisableDBGStopMode(void)
 {
   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
 }
@@ -410,7 +410,7 @@ void HAL_DisableDBGStopMode(void)
   * @brief  Enable the Debug Module during STANDBY mode
   * @retval None
   */
-void HAL_EnableDBGStandbyMode(void)
+void HAL_DBGMCU_EnableDBGStandbyMode(void)
 {
   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
 }
@@ -419,7 +419,7 @@ void HAL_EnableDBGStandbyMode(void)
   * @brief  Disable the Debug Module during STANDBY mode
   * @retval None
   */
-void HAL_DisableDBGStandbyMode(void)
+void HAL_DBGMCU_DisableDBGStandbyMode(void)
 {
   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
 }
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_adc.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_adc.c
index 42cdfc71f..9c4a00806 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_adc.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_adc.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_adc.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   This file provides firmware functions to manage the following 
   *          functionalities of the Analog to Digital Convertor (ADC) peripheral:
   *           + Initialization and de-initialization functions
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_adc_ex.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_adc_ex.c
index 227f894f3..430e09bfb 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_adc_ex.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_adc_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_adc_ex.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   This file provides firmware functions to manage the following 
   *          functionalities of the ADC extension peripheral:
   *           + Extended features functions
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_can.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_can.c
index c26d5b26e..7746630e4 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_can.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_can.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_can.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   CAN HAL module driver.
   *
   *          This file provides firmware functions to manage the following 
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_cec.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_cec.c
index b7c6ac375..c3af66e3d 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_cec.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_cec.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_cec.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   CEC HAL module driver.
   * 
   *          This file provides firmware functions to manage the following 
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_cortex.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_cortex.c
index 26f29f08c..ff866e928 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_cortex.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_cortex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_cortex.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   CORTEX HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the CORTEX:
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_crc.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_crc.c
index c1d7d7e57..dad4db206 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_crc.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_crc.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_crc.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   CRC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Cyclic Redundancy Check (CRC) peripheral:
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_crc_ex.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_crc_ex.c
index 63de13b1e..fdd38d7ad 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_crc_ex.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_crc_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_crc_ex.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Extended CRC HAL module driver.
   *    
   *          This file provides firmware functions to manage the following 
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_cryp.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_cryp.c
index 7ad596371..fe1063f5a 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_cryp.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_cryp.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_cryp.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   CRYP HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Cryptography (CRYP) peripheral:
@@ -23,7 +23,7 @@
       The CRYP HAL driver can be used as follows:
 
       (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
-         (##) Enable the CRYP interface clock using __CRYP_CLK_ENABLE()
+         (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
          (##) In case of using interrupts (e.g. HAL_CRYP_AESECB_Encrypt_IT())
              (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
              (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
@@ -161,7 +161,7 @@ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
   
   /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
      in the DMACR register */
-  CRYP->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
+  hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
   
   /* Call input data transfer complete callback */
   HAL_CRYP_InCpltCallback(hcryp);
@@ -178,10 +178,10 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
   
   /* Disable the DMA transfer for output FIFO request by resetting the DOEN bit
      in the DMACR register */
-  CRYP->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
+  hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
   
   /* Disable CRYP */
-  __HAL_CRYP_DISABLE();
+  __HAL_CRYP_DISABLE(hcryp);
   
   /* Change the CRYP state to ready */
   hcryp->State = HAL_CRYP_STATE_READY;
@@ -218,43 +218,43 @@ static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySiz
   {
   case CRYP_KEYSIZE_256B:
     /* Key Initialisation */
-    CRYP->K0LR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K0LR = __REV(*(uint32_t*)(keyaddr));
     keyaddr+=4;
-    CRYP->K0RR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K0RR = __REV(*(uint32_t*)(keyaddr));
     keyaddr+=4;
-    CRYP->K1LR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
     keyaddr+=4;
-    CRYP->K1RR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
     keyaddr+=4;
-    CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
     keyaddr+=4;
-    CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
     keyaddr+=4;
-    CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
     keyaddr+=4;
-    CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
     break;
   case CRYP_KEYSIZE_192B:
-    CRYP->K1LR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
     keyaddr+=4;
-    CRYP->K1RR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
     keyaddr+=4;
-    CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
     keyaddr+=4;
-    CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
     keyaddr+=4;
-    CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
     keyaddr+=4;
-    CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
     break;
   case CRYP_KEYSIZE_128B:       
-    CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
     keyaddr+=4;
-    CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
     keyaddr+=4;
-    CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
     keyaddr+=4;
-    CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
     break;
   default:
     break;
@@ -276,24 +276,24 @@ static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, u
   switch(IVSize)
   {
   case CRYP_KEYSIZE_128B:
-    CRYP->IV0LR = __REV(*(uint32_t*)(ivaddr));
+    hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
     ivaddr+=4;
-    CRYP->IV0RR = __REV(*(uint32_t*)(ivaddr));
+    hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
     ivaddr+=4;
-    CRYP->IV1LR = __REV(*(uint32_t*)(ivaddr));
+    hcryp->Instance->IV1LR = __REV(*(uint32_t*)(ivaddr));
     ivaddr+=4;
-    CRYP->IV1RR = __REV(*(uint32_t*)(ivaddr));
+    hcryp->Instance->IV1RR = __REV(*(uint32_t*)(ivaddr));
     break;
     /* Whatever key size 192 or 256, Init vector is written in IV0LR and IV0RR */
   case CRYP_KEYSIZE_192B:
-    CRYP->IV0LR = __REV(*(uint32_t*)(ivaddr));
+    hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
     ivaddr+=4;
-    CRYP->IV0RR = __REV(*(uint32_t*)(ivaddr));
+    hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
     break;
   case CRYP_KEYSIZE_256B:
-    CRYP->IV0LR = __REV(*(uint32_t*)(ivaddr));
+    hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
     ivaddr+=4;
-    CRYP->IV0RR = __REV(*(uint32_t*)(ivaddr));
+    hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
     break;
   default:
     break;
@@ -307,6 +307,7 @@ static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, u
   * @param  Input: Pointer to the Input buffer
   * @param  Ilength: Length of the Input buffer, must be a multiple of 16.
   * @param  Output: Pointer to the returned buffer
+  * @param  Timeout: Timeout value
   * @retval None
   */
 static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
@@ -320,19 +321,19 @@ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* In
   for(i=0; (i < Ilength); i+=16)
   {
     /* Write the Input block in the IN FIFO */
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR  = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
     
     /* Get tick */
     tickstart = HAL_GetTick();
 
-    while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE))
+    while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
     {    
       /* Check for the Timeout */
       if(Timeout != HAL_MAX_DELAY)
@@ -350,13 +351,13 @@ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* In
       }
     }
     /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
   }
   /* Return function status */
@@ -384,15 +385,15 @@ static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8
   for(i=0; (i < Ilength); i+=8)
   {
     /* Write the Input block in the IN FIFO */
-    CRYP->DR  = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
     
     /* Get tick */
     tickstart = HAL_GetTick();
     
-    while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE))
+    while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
     {
       /* Check for the Timeout */
       if(Timeout != HAL_MAX_DELAY)
@@ -410,9 +411,9 @@ static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8
       }
     }
     /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
   }
   /* Return function status */
@@ -441,19 +442,19 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin
   hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
   
   /* Enable CRYP */
-  __HAL_CRYP_ENABLE();
+  __HAL_CRYP_ENABLE(hcryp);
   
   /* Enable the DMA In DMA Stream */
-  HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&CRYP->DR, Size/4);
-  
+  HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DR, Size/4);
+
   /* Enable In DMA request */
-  CRYP->DMACR = (CRYP_DMACR_DIEN);
+  hcryp->Instance->DMACR = (CRYP_DMACR_DIEN);
   
   /* Enable the DMA Out DMA Stream */
-  HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&CRYP->DOUT, outputaddr, Size/4);
+  HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size/4);
   
   /* Enable Out DMA request */
-  CRYP->DMACR |= CRYP_DMACR_DOEN;
+  hcryp->Instance->DMACR |= CRYP_DMACR_DOEN;
  
 }
 
@@ -470,14 +471,14 @@ static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
   if(hcryp->Phase == HAL_CRYP_PHASE_READY)
   {
     /* Set the CRYP peripheral in AES ECB mode */
-    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_DES_ECB | Direction);
+    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_DES_ECB | Direction);
     
     /* Set the key */
-    CRYP->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));
-    CRYP->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4));
+    hcryp->Instance->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));
+    hcryp->Instance->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4));
     
     /* Flush FIFO */
-    __HAL_CRYP_FIFO_FLUSH();
+    __HAL_CRYP_FIFO_FLUSH(hcryp);
     
     /* Set the phase */
     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -497,17 +498,17 @@ static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
   if(hcryp->Phase == HAL_CRYP_PHASE_READY)
   {
     /* Set the CRYP peripheral in AES ECB mode */
-    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_DES_CBC | Direction);
+    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_DES_CBC | Direction);
     
     /* Set the key */
-    CRYP->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));
-    CRYP->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4));
+    hcryp->Instance->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));
+    hcryp->Instance->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4));
     
     /* Set the Initialization Vector */
     CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);
     
     /* Flush FIFO */
-    __HAL_CRYP_FIFO_FLUSH();
+    __HAL_CRYP_FIFO_FLUSH(hcryp);
     
     /* Set the phase */
     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -527,13 +528,13 @@ static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
   if(hcryp->Phase == HAL_CRYP_PHASE_READY)
   {
     /* Set the CRYP peripheral in AES ECB mode */
-    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_TDES_ECB | Direction);
+    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_TDES_ECB | Direction);
     
     /* Set the key */
     CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);
     
     /* Flush FIFO */
-    __HAL_CRYP_FIFO_FLUSH();
+    __HAL_CRYP_FIFO_FLUSH(hcryp);
     
     /* Set the phase */
     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -553,7 +554,7 @@ static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
   if(hcryp->Phase == HAL_CRYP_PHASE_READY)
   {
     /* Set the CRYP peripheral in AES CBC mode */
-    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_TDES_CBC | Direction);
+    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_TDES_CBC | Direction);
     
     /* Set the key */
     CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);
@@ -562,7 +563,7 @@ static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
     CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);
     
     /* Flush FIFO */
-    __HAL_CRYP_FIFO_FLUSH();
+    __HAL_CRYP_FIFO_FLUSH(hcryp);
     
     /* Set the phase */
     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -617,6 +618,8 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
     
   if(hcryp->State == HAL_CRYP_STATE_RESET)
   {
+    /* Allocate lock resource and initialize it */
+    hcryp->Lock = HAL_UNLOCKED;
     /* Init the low level hardware */
     HAL_CRYP_MspInit(hcryp);
   }
@@ -666,7 +669,7 @@ HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
   hcryp->CrypOutCount = 0;
   
   /* Disable the CRYP Peripheral Clock */
-  __HAL_CRYP_DISABLE();
+  __HAL_CRYP_DISABLE(hcryp);
   
   /* DeInit the low level hardware: CLOCK, NVIC.*/
   HAL_CRYP_MspDeInit(hcryp);
@@ -756,20 +759,20 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
     CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
     
     /* Set the CRYP peripheral in AES ECB mode */
-    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB);
+    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);
     
     /* Flush FIFO */
-    __HAL_CRYP_FIFO_FLUSH();
+    __HAL_CRYP_FIFO_FLUSH(hcryp);
     
     /* Enable CRYP */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Set the phase */
     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
   }
   
     /* Write Plain Data and Get Cypher Data */
-    if(CRYP_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+    if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
     {
       return HAL_TIMEOUT;
     }
@@ -810,16 +813,16 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
     CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
     
     /* Set the CRYP peripheral in AES ECB mode */
-    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC);
+    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);
     
     /* Set the Initialization Vector */
     CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
     
     /* Flush FIFO */
-    __HAL_CRYP_FIFO_FLUSH();
+    __HAL_CRYP_FIFO_FLUSH(hcryp);
     
     /* Enable CRYP */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Set the phase */
     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -867,16 +870,16 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
     CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
     
     /* Set the CRYP peripheral in AES ECB mode */
-    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR);
+    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);
     
     /* Set the Initialization Vector */
     CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
     
     /* Flush FIFO */
-    __HAL_CRYP_FIFO_FLUSH();
+    __HAL_CRYP_FIFO_FLUSH(hcryp);
     
     /* Enable CRYP */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Set the phase */
     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -928,15 +931,15 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC
     CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
     
     /* Set the CRYP peripheral in AES Key mode */
-    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
     
     /* Enable CRYP */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Get tick */ 
     tickstart = HAL_GetTick();
 
-    while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))
+    while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
     {
       /* Check for the Timeout */
       if(Timeout != HAL_MAX_DELAY)
@@ -955,18 +958,18 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC
     }
     
     /* Disable CRYP */
-    __HAL_CRYP_DISABLE();
+    __HAL_CRYP_DISABLE(hcryp);
     
     /* Reset the ALGOMODE bits*/
     CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
     
     /* Set the CRYP peripheral in AES ECB decryption mode */
-    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
+    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
     /* Flush FIFO */
-    __HAL_CRYP_FIFO_FLUSH();
+    __HAL_CRYP_FIFO_FLUSH(hcryp);
     
     /* Enable CRYP */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Set the phase */
     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -1016,15 +1019,15 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC
     CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
     
     /* Set the CRYP peripheral in AES Key mode */
-    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
     
     /* Enable CRYP */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Get tick */ 
     tickstart = HAL_GetTick();
 
-    while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))
+    while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
     {
       /* Check for the Timeout */
       if(Timeout != HAL_MAX_DELAY)
@@ -1046,16 +1049,16 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC
     CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
     
     /* Set the CRYP peripheral in AES CBC decryption mode */
-    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
+    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
     
     /* Set the Initialization Vector */
     CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
     
     /* Flush FIFO */
-    __HAL_CRYP_FIFO_FLUSH();
+    __HAL_CRYP_FIFO_FLUSH(hcryp);
     
     /* Enable CRYP */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Set the phase */
     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -1103,16 +1106,16 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC
     CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
     
     /* Set the CRYP peripheral in AES CTR mode */
-    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
+    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
     
     /* Set the Initialization Vector */
     CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
     
     /* Flush FIFO */
-    __HAL_CRYP_FIFO_FLUSH();
+    __HAL_CRYP_FIFO_FLUSH(hcryp);
     
     /* Enable CRYP */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Set the phase */
     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -1168,60 +1171,60 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
       CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
       
       /* Set the CRYP peripheral in AES ECB mode */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB);
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);
       
       /* Flush FIFO */
-      __HAL_CRYP_FIFO_FLUSH();
+      __HAL_CRYP_FIFO_FLUSH(hcryp);
       
      /* Set the phase */
      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
     }
     
     /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
     
     /* Enable CRYP */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Return function status */
     return HAL_OK;
   }
-  else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
   {
     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
     /* Write the Input block in the IN FIFO */
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR  = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     hcryp->pCrypInBuffPtr += 16;
     hcryp->CrypInCount -= 16;
     if(hcryp->CrypInCount == 0)
     {
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
       /* Call the Input data transfer complete callback */
       HAL_CRYP_InCpltCallback(hcryp);
     }
   }
-  else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
   {
     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
     /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     hcryp->pCrypOutBuffPtr += 16;
     hcryp->CrypOutCount -= 16;
     if(hcryp->CrypOutCount == 0)
     {
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
       /* Process Locked */
       __HAL_UNLOCK(hcryp);
       /* Change the CRYP state */
@@ -1269,62 +1272,62 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
       CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
       
       /* Set the CRYP peripheral in AES CBC mode */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC);
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);
       
       /* Set the Initialization Vector */
       CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
       
       /* Flush FIFO */
-      __HAL_CRYP_FIFO_FLUSH();
+      __HAL_CRYP_FIFO_FLUSH(hcryp);
       
      /* Set the phase */
      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
     }
     /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
     
     /* Enable CRYP */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Return function status */
     return HAL_OK;
   }
-  else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
   {
     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
     /* Write the Input block in the IN FIFO */
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR  = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     hcryp->pCrypInBuffPtr += 16;
     hcryp->CrypInCount -= 16;
     if(hcryp->CrypInCount == 0)
     {
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
       /* Call the Input data transfer complete callback */
       HAL_CRYP_InCpltCallback(hcryp);
     }
   }
-  else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
   {
     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
     /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     hcryp->pCrypOutBuffPtr += 16;
     hcryp->CrypOutCount -= 16;
     if(hcryp->CrypOutCount == 0)
     {
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
       /* Process Locked */
       __HAL_UNLOCK(hcryp);
       /* Change the CRYP state */
@@ -1372,62 +1375,62 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
       CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
       
       /* Set the CRYP peripheral in AES CTR mode */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR);
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);
       
       /* Set the Initialization Vector */
       CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
       
       /* Flush FIFO */
-      __HAL_CRYP_FIFO_FLUSH();
+      __HAL_CRYP_FIFO_FLUSH(hcryp);
       
      /* Set the phase */
      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
     }
     /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
     
     /* Enable CRYP */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Return function status */
     return HAL_OK;
   }
-  else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
   {
     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
     /* Write the Input block in the IN FIFO */
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR  = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     hcryp->pCrypInBuffPtr += 16;
     hcryp->CrypInCount -= 16;
     if(hcryp->CrypInCount == 0)
     {
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
       /* Call the Input data transfer complete callback */
       HAL_CRYP_InCpltCallback(hcryp);
     }
   }
-  else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
   {
     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
     /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     hcryp->pCrypOutBuffPtr += 16;
     hcryp->CrypOutCount -= 16;
     if(hcryp->CrypOutCount == 0)
     {
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
       /* Process Unlocked */
       __HAL_UNLOCK(hcryp);
       /* Change the CRYP state */
@@ -1478,14 +1481,14 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
     CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
     
     /* Set the CRYP peripheral in AES Key mode */
-    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
     /* Enable CRYP */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Get tick */ 
     tickstart = HAL_GetTick();
 
-    while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))
+    while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
     {
       /* Check for the Timeout */
       if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
@@ -1504,60 +1507,60 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
     CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
     
     /* Set the CRYP peripheral in AES ECB decryption mode */
-    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
+    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
     
     /* Flush FIFO */
-    __HAL_CRYP_FIFO_FLUSH();
+    __HAL_CRYP_FIFO_FLUSH(hcryp);
     
      /* Set the phase */
      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
   }
      
     /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
     
     /* Enable CRYP */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Return function status */
     return HAL_OK;
   }
-  else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
   {
     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
     /* Write the Input block in the IN FIFO */
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR  = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     hcryp->pCrypInBuffPtr += 16;
     hcryp->CrypInCount -= 16;
     if(hcryp->CrypInCount == 0)
     {
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
       /* Call the Input data transfer complete callback */
       HAL_CRYP_InCpltCallback(hcryp);
     }
   }
-  else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
   {
     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
     /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     hcryp->pCrypOutBuffPtr += 16;
     hcryp->CrypOutCount -= 16;
     if(hcryp->CrypOutCount == 0)
     {
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
       /* Process Unlocked */
       __HAL_UNLOCK(hcryp);
       /* Change the CRYP state */
@@ -1608,15 +1611,15 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
       CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
       
       /* Set the CRYP peripheral in AES Key mode */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
       
       /* Enable CRYP */
-      __HAL_CRYP_ENABLE();
+      __HAL_CRYP_ENABLE(hcryp);
       
     /* Get tick */
     tickstart = HAL_GetTick();
 
-    while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))
+    while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
     {
       /* Check for the Timeout */
       if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
@@ -1635,66 +1638,66 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
       CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
     
       /* Set the CRYP peripheral in AES CBC decryption mode */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
     
       /* Set the Initialization Vector */
       CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
     
       /* Flush FIFO */
-      __HAL_CRYP_FIFO_FLUSH();
+      __HAL_CRYP_FIFO_FLUSH(hcryp);
     
       /* Enable CRYP */
-      __HAL_CRYP_ENABLE();
+      __HAL_CRYP_ENABLE(hcryp);
       
       /* Set the phase */
       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
     }
     
     /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
     
     /* Enable CRYP */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Return function status */
     return HAL_OK;
   }
-  else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
   {
     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
     /* Write the Input block in the IN FIFO */
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR  = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     hcryp->pCrypInBuffPtr += 16;
     hcryp->CrypInCount -= 16;
     if(hcryp->CrypInCount == 0)
     {
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
       /* Call the Input data transfer complete callback */
       HAL_CRYP_InCpltCallback(hcryp);
     }
   }
-  else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
   {
     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
     /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     hcryp->pCrypOutBuffPtr += 16;
     hcryp->CrypOutCount -= 16;
     if(hcryp->CrypOutCount == 0)
     {
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
       /* Process Unlocked */
       __HAL_UNLOCK(hcryp);
       /* Change the CRYP state */
@@ -1743,63 +1746,63 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
       CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
       
       /* Set the CRYP peripheral in AES CTR mode */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
       
       /* Set the Initialization Vector */
       CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
       
       /* Flush FIFO */
-      __HAL_CRYP_FIFO_FLUSH();
+      __HAL_CRYP_FIFO_FLUSH(hcryp);
       
       /* Set the phase */
       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
     }
     
     /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
     
     /* Enable CRYP */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Return function status */
     return HAL_OK;
   }
-  else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
   {
     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
     /* Write the Input block in the IN FIFO */
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR  = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     hcryp->pCrypInBuffPtr += 16;
     hcryp->CrypInCount -= 16;
     if(hcryp->CrypInCount == 0)
     {
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
       /* Call the Input data transfer complete callback */
       HAL_CRYP_InCpltCallback(hcryp);
     }
   }
-  else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
   {
     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
     /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     hcryp->pCrypOutBuffPtr += 16;
     hcryp->CrypOutCount -= 16;
     if(hcryp->CrypOutCount == 0)
     {
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
       /* Process Unlocked */
       __HAL_UNLOCK(hcryp);
       /* Change the CRYP state */
@@ -1845,10 +1848,10 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
       CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
       
       /* Set the CRYP peripheral in AES ECB mode */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB);
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);
       
       /* Flush FIFO */
-      __HAL_CRYP_FIFO_FLUSH();
+      __HAL_CRYP_FIFO_FLUSH(hcryp);
       
      /* Set the phase */
      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -1900,13 +1903,13 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
       CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
       
       /* Set the CRYP peripheral in AES ECB mode */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC);
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);
       
       /* Set the Initialization Vector */
       CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
       
       /* Flush FIFO */
-      __HAL_CRYP_FIFO_FLUSH();
+      __HAL_CRYP_FIFO_FLUSH(hcryp);
       
        /* Set the phase */
        hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -1958,13 +1961,13 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
       CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
       
       /* Set the CRYP peripheral in AES ECB mode */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR);
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);
       
       /* Set the Initialization Vector */
       CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
       
       /* Flush FIFO */
-      __HAL_CRYP_FIFO_FLUSH();
+      __HAL_CRYP_FIFO_FLUSH(hcryp);
       
        /* Set the phase */
        hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -2018,15 +2021,15 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
     CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
     
     /* Set the CRYP peripheral in AES Key mode */
-    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
     
     /* Enable CRYP */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Get tick */
     tickstart = HAL_GetTick();
     
-    while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))
+    while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
     {
       /* Check for the Timeout */
       if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
@@ -2045,10 +2048,10 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
     CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
     
     /* Set the CRYP peripheral in AES ECB decryption mode */
-    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
+    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
     
     /* Flush FIFO */
-    __HAL_CRYP_FIFO_FLUSH();
+    __HAL_CRYP_FIFO_FLUSH(hcryp);
     
      /* Set the phase */
      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -2102,15 +2105,15 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
       CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
       
       /* Set the CRYP peripheral in AES Key mode */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
       
       /* Enable CRYP */
-      __HAL_CRYP_ENABLE();
+      __HAL_CRYP_ENABLE(hcryp);
       
       /* Get tick */
       tickstart = HAL_GetTick();
 
-      while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))
+      while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
       {
         /* Check for the Timeout */
         if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
@@ -2129,13 +2132,13 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
       CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
       
       /* Set the CRYP peripheral in AES CBC decryption mode */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
       
       /* Set the Initialization Vector */
       CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
       
       /* Flush FIFO */
-      __HAL_CRYP_FIFO_FLUSH();
+      __HAL_CRYP_FIFO_FLUSH(hcryp);
       
       /* Set the phase */
       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -2188,13 +2191,13 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
       CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
       
       /* Set the CRYP peripheral in AES CTR mode */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
       
       /* Set the Initialization Vector */
       CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
       
       /* Flush FIFO */
-      __HAL_CRYP_FIFO_FLUSH();
+      __HAL_CRYP_FIFO_FLUSH(hcryp);
       
       /* Set the phase */
       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -2261,7 +2264,7 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
   CRYP_SetDESECBMode(hcryp, 0);
   
   /* Enable CRYP */
-  __HAL_CRYP_ENABLE();
+  __HAL_CRYP_ENABLE(hcryp);
   
   /* Write Plain Data and Get Cypher Data */
   if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
@@ -2301,7 +2304,7 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
   CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);
   
   /* Enable CRYP */
-  __HAL_CRYP_ENABLE();
+  __HAL_CRYP_ENABLE(hcryp);
   
   /* Write Plain Data and Get Cypher Data */
   if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
@@ -2341,7 +2344,7 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
   CRYP_SetDESCBCMode(hcryp, 0);
   
   /* Enable CRYP */
-  __HAL_CRYP_ENABLE();
+  __HAL_CRYP_ENABLE(hcryp);
   
   /* Write Plain Data and Get Cypher Data */
   if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
@@ -2381,7 +2384,7 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
   CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);
   
   /* Enable CRYP */
-  __HAL_CRYP_ENABLE();
+  __HAL_CRYP_ENABLE(hcryp);
   
   /* Write Plain Data and Get Cypher Data */
   if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
@@ -2430,47 +2433,47 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
     CRYP_SetDESECBMode(hcryp, 0);
     
     /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
     
     /* Enable CRYP */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Return function status */
     return HAL_OK;
   }
-  else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
   {
     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
     /* Write the Input block in the IN FIFO */
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     
     hcryp->pCrypInBuffPtr += 8;
     hcryp->CrypInCount -= 8;
     if(hcryp->CrypInCount == 0)
     {
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
       /* Call the Input data transfer complete callback */
       HAL_CRYP_InCpltCallback(hcryp);
     }
   }
-  else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
   {
     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
     /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     
     hcryp->pCrypOutBuffPtr += 8;
     hcryp->CrypOutCount -= 8;
     if(hcryp->CrypOutCount == 0)
     {
       /* Disable IT */
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
       /* Disable CRYP */
-      __HAL_CRYP_DISABLE();
+      __HAL_CRYP_DISABLE(hcryp);
       /* Process Unlocked */
       __HAL_UNLOCK(hcryp);
       /* Change the CRYP state */
@@ -2515,48 +2518,48 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
     CRYP_SetDESCBCMode(hcryp, 0);
     
     /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
     
     /* Enable CRYP */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Return function status */
     return HAL_OK;
   }
   
-  else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
   {
     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
     /* Write the Input block in the IN FIFO */
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
 
     hcryp->pCrypInBuffPtr += 8;
     hcryp->CrypInCount -= 8;
     if(hcryp->CrypInCount == 0)
     {
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
       /* Call the Input data transfer complete callback */
       HAL_CRYP_InCpltCallback(hcryp);
     }
   }
-  else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
   {
     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
     /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
 
     hcryp->pCrypOutBuffPtr += 8;
     hcryp->CrypOutCount -= 8;
     if(hcryp->CrypOutCount == 0)
     {
       /* Disable IT */
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
       /* Disable CRYP */
-      __HAL_CRYP_DISABLE();
+      __HAL_CRYP_DISABLE(hcryp);
       /* Process Unlocked */
       __HAL_UNLOCK(hcryp);
       /* Change the CRYP state */
@@ -2601,47 +2604,47 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
     CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);
     
     /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
     
     /* Enable CRYP */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Return function status */
     return HAL_OK;
   }
-  else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
   {
     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
     /* Write the Input block in the IN FIFO */
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     
     hcryp->pCrypInBuffPtr += 8;
     hcryp->CrypInCount -= 8;
     if(hcryp->CrypInCount == 0)
     {
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
       /* Call the Input data transfer complete callback */
       HAL_CRYP_InCpltCallback(hcryp);
     }
   }
-  else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
   {
     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
     /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
 
     hcryp->pCrypOutBuffPtr += 8;
     hcryp->CrypOutCount -= 8;
     if(hcryp->CrypOutCount == 0)
     {
       /* Disable IT */
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
       /* Disable CRYP */
-      __HAL_CRYP_DISABLE();
+      __HAL_CRYP_DISABLE(hcryp);
       /* Process Unlocked */
       __HAL_UNLOCK(hcryp);
       /* Change the CRYP state */
@@ -2686,47 +2689,47 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
     CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);
     
     /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
     
     /* Enable CRYP */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Return function status */
     return HAL_OK;
   }
-  else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
   {
     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
     /* Write the Input block in the IN FIFO */
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
 
     hcryp->pCrypInBuffPtr += 8;
     hcryp->CrypInCount -= 8;
     if(hcryp->CrypInCount == 0)
     {
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
       /* Call the Input data transfer complete callback */
       HAL_CRYP_InCpltCallback(hcryp);
     }
   }
-  else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
   {
     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
     /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
 
     hcryp->pCrypOutBuffPtr += 8;
     hcryp->CrypOutCount -= 8;
     if(hcryp->CrypOutCount == 0)
     {
       /* Disable IT */
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
       /* Disable CRYP */
-      __HAL_CRYP_DISABLE();
+      __HAL_CRYP_DISABLE(hcryp);
       /* Process Unlocked */
       __HAL_UNLOCK(hcryp);
       /* Change the CRYP state */
@@ -2958,7 +2961,7 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *p
   CRYP_SetTDESECBMode(hcryp, 0);
   
   /* Enable CRYP */
-  __HAL_CRYP_ENABLE();
+  __HAL_CRYP_ENABLE(hcryp);
   
   /* Write Plain Data and Get Cypher Data */
   if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
@@ -2999,7 +3002,7 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *p
   CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);
   
   /* Enable CRYP */
-  __HAL_CRYP_ENABLE();
+  __HAL_CRYP_ENABLE(hcryp);
   
   /* Write Cypher Data and Get Plain Data */
   if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
@@ -3040,7 +3043,7 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *p
   CRYP_SetTDESCBCMode(hcryp, 0);
   
   /* Enable CRYP */
-  __HAL_CRYP_ENABLE();
+  __HAL_CRYP_ENABLE(hcryp);
   
   /* Write Plain Data and Get Cypher Data */
   if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
@@ -3081,7 +3084,7 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *p
   CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);
   
   /* Enable CRYP */
-  __HAL_CRYP_ENABLE();
+  __HAL_CRYP_ENABLE(hcryp);
   
   /* Write Cypher Data and Get Plain Data */
   if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
@@ -3130,47 +3133,47 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
     CRYP_SetTDESECBMode(hcryp, 0);
     
     /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
     
     /* Enable CRYP */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Return function status */
     return HAL_OK;
   }
-  else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
   {
     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
     /* Write the Input block in the IN FIFO */
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
 
     hcryp->pCrypInBuffPtr += 8;
     hcryp->CrypInCount -= 8;
     if(hcryp->CrypInCount == 0)
     {
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
       /* Call the Input data transfer complete callback */
       HAL_CRYP_InCpltCallback(hcryp);
     }
   }
-  else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
   {
     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
     /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
 
     hcryp->pCrypOutBuffPtr += 8;
     hcryp->CrypOutCount -= 8;
     if(hcryp->CrypOutCount == 0)
     {
       /* Disable IT */
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
       /* Disable CRYP */
-      __HAL_CRYP_DISABLE();
+      __HAL_CRYP_DISABLE(hcryp);
       /* Process Unlocked */
       __HAL_UNLOCK(hcryp);
       /* Change the CRYP state */
@@ -3215,46 +3218,46 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
     CRYP_SetTDESCBCMode(hcryp, 0);
     
     /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
     
     /* Enable CRYP */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Return function status */
     return HAL_OK;
   }
-  else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
   {
     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
     /* Write the Input block in the IN FIFO */
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
 
     hcryp->pCrypInBuffPtr += 8;
     hcryp->CrypInCount -= 8;
     if(hcryp->CrypInCount == 0)
     {
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
       /* Call the Input data transfer complete callback */
       HAL_CRYP_InCpltCallback(hcryp);
     }
   }
-  else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
   {
     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
     /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
         
     hcryp->pCrypOutBuffPtr += 8;
     hcryp->CrypOutCount -= 8;
     if(hcryp->CrypOutCount == 0)
     {
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
       /* Disable CRYP */
-      __HAL_CRYP_DISABLE();
+      __HAL_CRYP_DISABLE(hcryp);
       /* Process Unlocked */
       __HAL_UNLOCK(hcryp);
       /* Change the CRYP state */
@@ -3299,46 +3302,46 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
     CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);
     
     /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
     
     /* Enable CRYP */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Return function status */
     return HAL_OK;
   }
-  else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
   {
     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
     /* Write the Input block in the IN FIFO */
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
 
     hcryp->pCrypInBuffPtr += 8;
     hcryp->CrypInCount -= 8;
     if(hcryp->CrypInCount == 0)
     {
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
       /* Call the Input data transfer complete callback */
       HAL_CRYP_InCpltCallback(hcryp);
     }
   }
-  else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
   {
     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
     /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
 
     hcryp->pCrypOutBuffPtr += 8;
     hcryp->CrypOutCount -= 8;
     if(hcryp->CrypOutCount == 0)
     {
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
       /* Disable CRYP */
-      __HAL_CRYP_DISABLE();
+      __HAL_CRYP_DISABLE(hcryp);
       /* Process Unlocked */
       __HAL_UNLOCK(hcryp);
       /* Change the CRYP state */
@@ -3383,46 +3386,46 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
     CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);
     
     /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
     
     /* Enable CRYP */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Return function status */
     return HAL_OK;
   }
-  else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
   {
     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
     /* Write the Input block in the IN FIFO */
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
 
     hcryp->pCrypInBuffPtr += 8;
     hcryp->CrypInCount -= 8;
     if(hcryp->CrypInCount == 0)
     {
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
       /* Call the Input data transfer complete callback */
       HAL_CRYP_InCpltCallback(hcryp);
     }
   }
-  else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
   {
     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
     /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
 
     hcryp->pCrypOutBuffPtr += 8;
     hcryp->CrypOutCount -= 8;
     if(hcryp->CrypOutCount == 0)
     {
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
       /* Disable CRYP */
-      __HAL_CRYP_DISABLE();
+      __HAL_CRYP_DISABLE(hcryp);
       /* Process Unlocked */
       __HAL_UNLOCK(hcryp);
       /* Change the CRYP state */
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_cryp_ex.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_cryp_ex.c
index b3796dbf1..9df705254 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_cryp_ex.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_cryp_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_cryp_ex.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Extended CRYP HAL module driver
   *          This file provides firmware functions to manage the following 
   *          functionalities of CRYP extension peripheral:
@@ -16,7 +16,7 @@
     [..]
     The CRYP Extension HAL driver can be used as follows:
     (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
-        (##) Enable the CRYP interface clock using __CRYP_CLK_ENABLE()
+        (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
         (##) In case of using interrupts (e.g. HAL_CRYPEx_AESGCM_Encrypt_IT())
             (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
             (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
@@ -156,7 +156,7 @@ static void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma)
   
   /* Disable the DMA transfer for input Fifo request by resetting the DIEN bit
      in the DMACR register */
-  CRYP->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
+  hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
   
   /* Call input data transfer complete callback */
   HAL_CRYP_InCpltCallback(hcryp);
@@ -173,10 +173,10 @@ static void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma)
   
   /* Disable the DMA transfer for output Fifo request by resetting the DOEN bit
      in the DMACR register */
-  CRYP->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
+  hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
   
   /* Enable the CRYP peripheral */
-  __HAL_CRYP_DISABLE();
+  __HAL_CRYP_DISABLE(hcryp);
   
   /* Change the CRYP peripheral state */
   hcryp->State = HAL_CRYP_STATE_READY;
@@ -213,43 +213,43 @@ static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32
   {
   case CRYP_KEYSIZE_256B:
     /* Key Initialisation */
-    CRYP->K0LR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K0LR = __REV(*(uint32_t*)(keyaddr));
     keyaddr+=4;
-    CRYP->K0RR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K0RR = __REV(*(uint32_t*)(keyaddr));
     keyaddr+=4;
-    CRYP->K1LR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
     keyaddr+=4;
-    CRYP->K1RR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
     keyaddr+=4;
-    CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
     keyaddr+=4;
-    CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
     keyaddr+=4;
-    CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
     keyaddr+=4;
-    CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
     break;
   case CRYP_KEYSIZE_192B:
-    CRYP->K1LR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
     keyaddr+=4;
-    CRYP->K1RR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
     keyaddr+=4;
-    CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
     keyaddr+=4;
-    CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
     keyaddr+=4;
-    CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
     keyaddr+=4;
-    CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
     break;
   case CRYP_KEYSIZE_128B:       
-    CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
     keyaddr+=4;
-    CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
     keyaddr+=4;
-    CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
     keyaddr+=4;
-    CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));
+    hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
     break;
   default:
     break;
@@ -267,13 +267,13 @@ static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *Init
 {
   uint32_t ivaddr = (uint32_t)InitVector;
   
-  CRYP->IV0LR = __REV(*(uint32_t*)(ivaddr));
+  hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
   ivaddr+=4;
-  CRYP->IV0RR = __REV(*(uint32_t*)(ivaddr));
+  hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
   ivaddr+=4;
-  CRYP->IV1LR = __REV(*(uint32_t*)(ivaddr));
+  hcryp->Instance->IV1LR = __REV(*(uint32_t*)(ivaddr));
   ivaddr+=4;
-  CRYP->IV1RR = __REV(*(uint32_t*)(ivaddr));
+  hcryp->Instance->IV1RR = __REV(*(uint32_t*)(ivaddr));
 }
 
 /**
@@ -296,19 +296,19 @@ static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, ui
   for(i=0; (i < Ilength); i+=16)
   {
     /* Write the Input block in the IN FIFO */
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR  = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
     
     /* Get tick */
     tickstart = HAL_GetTick();
  
-    while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE))
+    while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
     {
       /* Check for the Timeout */
       if(Timeout != HAL_MAX_DELAY)
@@ -326,13 +326,13 @@ static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, ui
       }
     }
     /* Read the Output block from the OUT FIFO */
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
   }
   /* Return function status */
@@ -358,16 +358,16 @@ static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp,
   if(hcryp->Init.HeaderSize != 0)
   {
     /* Select header phase */
-    __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
+    __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
     /* Enable the CRYP peripheral */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     for(loopcounter = 0; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=16)
     {
       /* Get tick */
       tickstart = HAL_GetTick();
       
-      while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
+      while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
       {
         /* Check for the Timeout */
         if(Timeout != HAL_MAX_DELAY)
@@ -385,13 +385,13 @@ static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp,
         }
       }
       /* Write the Input block in the IN FIFO */
-      CRYP->DR = *(uint32_t*)(headeraddr);
+      hcryp->Instance->DR = *(uint32_t*)(headeraddr);
       headeraddr+=4;
-      CRYP->DR = *(uint32_t*)(headeraddr);
+      hcryp->Instance->DR = *(uint32_t*)(headeraddr);
       headeraddr+=4;
-      CRYP->DR = *(uint32_t*)(headeraddr);
+      hcryp->Instance->DR = *(uint32_t*)(headeraddr);
       headeraddr+=4;
-      CRYP->DR = *(uint32_t*)(headeraddr);
+      hcryp->Instance->DR = *(uint32_t*)(headeraddr);
       headeraddr+=4;
     }
     
@@ -400,7 +400,7 @@ static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp,
     /* Get tick */
     tickstart = HAL_GetTick();
 
-    while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+    while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
     {
       /* Check for the Timeout */
       if(Timeout != HAL_MAX_DELAY)
@@ -444,19 +444,19 @@ static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t input
   hcryp->hdmaout->XferErrorCallback = CRYPEx_GCMCCM_DMAError;
   
   /* Enable the CRYP peripheral */
-  __HAL_CRYP_ENABLE();
+  __HAL_CRYP_ENABLE(hcryp);
   
   /* Enable the DMA In DMA Stream */
-  HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&CRYP->DR, Size/4);
+  HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DR, Size/4);
   
   /* Enable In DMA request */
-  CRYP->DMACR = CRYP_DMACR_DIEN;
+  hcryp->Instance->DMACR = CRYP_DMACR_DIEN;
   
   /* Enable the DMA Out DMA Stream */
-  HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&CRYP->DOUT, outputaddr, Size/4);
+  HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size/4);
   
   /* Enable Out DMA request */
-  CRYP->DMACR |= CRYP_DMACR_DOEN;
+  hcryp->Instance->DMACR |= CRYP_DMACR_DOEN;
 }
 
 /**
@@ -602,26 +602,26 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *
     CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
     
     /* Set the CRYP peripheral in AES CCM mode */
-    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
+    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
     
     /* Set the Initialization Vector */
     CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
     
     /* Select init phase */
-    __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
+    __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
     
     b0addr = (uint32_t)blockb0;
     /* Write the blockb0 block in the IN FIFO */
-    CRYP->DR = *(uint32_t*)(b0addr);
+    hcryp->Instance->DR = *(uint32_t*)(b0addr);
     b0addr+=4;
-    CRYP->DR = *(uint32_t*)(b0addr);
+    hcryp->Instance->DR = *(uint32_t*)(b0addr);
     b0addr+=4;
-    CRYP->DR = *(uint32_t*)(b0addr);
+    hcryp->Instance->DR = *(uint32_t*)(b0addr);
     b0addr+=4;
-    CRYP->DR = *(uint32_t*)(b0addr);
+    hcryp->Instance->DR = *(uint32_t*)(b0addr);
     
     /* Enable the CRYP peripheral */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Get tick */
     tickstart = HAL_GetTick();
@@ -647,17 +647,17 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *
     if(headersize != 0)
     {
       /* Select header phase */
-      __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
+      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
       
       /* Enable the CRYP peripheral */
-      __HAL_CRYP_ENABLE();
+      __HAL_CRYP_ENABLE(hcryp);
       
       for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
       {
         /* Get tick */
         tickstart = HAL_GetTick();
 
-        while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
+        while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
         {
           {
             /* Check for the Timeout */
@@ -677,20 +677,20 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *
           }
         }
         /* Write the header block in the IN FIFO */
-        CRYP->DR = *(uint32_t*)(headeraddr);
+        hcryp->Instance->DR = *(uint32_t*)(headeraddr);
         headeraddr+=4;
-        CRYP->DR = *(uint32_t*)(headeraddr);
+        hcryp->Instance->DR = *(uint32_t*)(headeraddr);
         headeraddr+=4;
-        CRYP->DR = *(uint32_t*)(headeraddr);
+        hcryp->Instance->DR = *(uint32_t*)(headeraddr);
         headeraddr+=4;
-        CRYP->DR = *(uint32_t*)(headeraddr);
+        hcryp->Instance->DR = *(uint32_t*)(headeraddr);
         headeraddr+=4;
       }
       
       /* Get tick */
       tickstart = HAL_GetTick();
 
-      while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+      while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
       {
         /* Check for the Timeout */
         if(Timeout != HAL_MAX_DELAY)
@@ -717,13 +717,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *
     hcryp->Init.pScratch[15] &= 0xfe;
     
     /* Select payload phase once the header phase is performed */
-    __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+    __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
     
     /* Flush FIFO */
-    __HAL_CRYP_FIFO_FLUSH();
+    __HAL_CRYP_FIFO_FLUSH(hcryp);
     
     /* Enable the CRYP peripheral */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Set the phase */
     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -773,16 +773,16 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *
     CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
     
     /* Set the CRYP peripheral in AES GCM mode */
-    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
+    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
     
     /* Set the Initialization Vector */
     CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
     
     /* Flush FIFO */
-    __HAL_CRYP_FIFO_FLUSH();
+    __HAL_CRYP_FIFO_FLUSH(hcryp);
     
     /* Enable the CRYP peripheral */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Get tick */
     tickstart = HAL_GetTick();
@@ -812,16 +812,16 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *
     }
     
     /* Disable the CRYP peripheral */
-    __HAL_CRYP_DISABLE();
+    __HAL_CRYP_DISABLE(hcryp);
     
     /* Select payload phase once the header phase is performed */
-    __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+    __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
     
     /* Flush FIFO */
-    __HAL_CRYP_FIFO_FLUSH();
+    __HAL_CRYP_FIFO_FLUSH(hcryp);
     
     /* Enable the CRYP peripheral */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Set the phase */
     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -871,16 +871,16 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *
     CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
     
     /* Set the CRYP peripheral in AES GCM decryption mode */
-    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
+    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
     
     /* Set the Initialization Vector */
     CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
     
     /* Flush FIFO */
-    __HAL_CRYP_FIFO_FLUSH();
+    __HAL_CRYP_FIFO_FLUSH(hcryp);
     
     /* Enable the CRYP peripheral */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Get tick */
     tickstart = HAL_GetTick();
@@ -909,13 +909,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *
       return HAL_TIMEOUT;
     }
     /* Disable the CRYP peripheral */
-    __HAL_CRYP_DISABLE();
+    __HAL_CRYP_DISABLE(hcryp);
     
     /* Select payload phase once the header phase is performed */
-    __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+    __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
     
     /* Enable the CRYP peripheral */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Set the phase */
     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -966,48 +966,48 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint32_t S
     hcryp->Phase = HAL_CRYP_PHASE_FINAL;
     
     /* Disable CRYP to start the final phase */
-    __HAL_CRYP_DISABLE();
+    __HAL_CRYP_DISABLE(hcryp);
     
     /* Select final phase */
-    __HAL_CRYP_SET_PHASE(CRYP_PHASE_FINAL);
+    __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_FINAL);
     
     /* Enable the CRYP peripheral */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Write the number of bits in header (64 bits) followed by the number of bits
        in the payload */
     if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
     {
-      CRYP->DR = __RBIT(headerlength >> 32);
-      CRYP->DR = __RBIT(headerlength);
-      CRYP->DR = __RBIT(inputlength >> 32);
-      CRYP->DR = __RBIT(inputlength);
+      hcryp->Instance->DR = __RBIT(headerlength >> 32);
+      hcryp->Instance->DR = __RBIT(headerlength);
+      hcryp->Instance->DR = __RBIT(inputlength >> 32);
+      hcryp->Instance->DR = __RBIT(inputlength);
     }
     else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
     {
-      CRYP->DR = __REV(headerlength >> 32);
-      CRYP->DR = __REV(headerlength);
-      CRYP->DR = __REV(inputlength >> 32);
-      CRYP->DR = __REV(inputlength);
+      hcryp->Instance->DR = __REV(headerlength >> 32);
+      hcryp->Instance->DR = __REV(headerlength);
+      hcryp->Instance->DR = __REV(inputlength >> 32);
+      hcryp->Instance->DR = __REV(inputlength);
     }
     else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
     {
-      CRYP->DR = __ROR((uint32_t)(headerlength >> 32), 16);
-      CRYP->DR = __ROR((uint32_t)headerlength, 16);
-      CRYP->DR = __ROR((uint32_t)(inputlength >> 32), 16);
-      CRYP->DR = __ROR((uint32_t)inputlength, 16);
+      hcryp->Instance->DR = __ROR((uint32_t)(headerlength >> 32), 16);
+      hcryp->Instance->DR = __ROR((uint32_t)headerlength, 16);
+      hcryp->Instance->DR = __ROR((uint32_t)(inputlength >> 32), 16);
+      hcryp->Instance->DR = __ROR((uint32_t)inputlength, 16);
     }
     else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
     {
-      CRYP->DR = (uint32_t)(headerlength >> 32);
-      CRYP->DR = (uint32_t)(headerlength);
-      CRYP->DR = (uint32_t)(inputlength >> 32);
-      CRYP->DR = (uint32_t)(inputlength);
+      hcryp->Instance->DR = (uint32_t)(headerlength >> 32);
+      hcryp->Instance->DR = (uint32_t)(headerlength);
+      hcryp->Instance->DR = (uint32_t)(inputlength >> 32);
+      hcryp->Instance->DR = (uint32_t)(inputlength);
     }
     /* Get tick */
     tickstart = HAL_GetTick();
 
-    while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE))
+    while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
     {
       /* Check for the Timeout */
       if(Timeout != HAL_MAX_DELAY)
@@ -1026,13 +1026,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint32_t S
     }
     
     /* Read the Auth TAG in the IN FIFO */
-    *(uint32_t*)(tagaddr) = CRYP->DOUT;
+    *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
     tagaddr+=4;
-    *(uint32_t*)(tagaddr) = CRYP->DOUT;
+    *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
     tagaddr+=4;
-    *(uint32_t*)(tagaddr) = CRYP->DOUT;
+    *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
     tagaddr+=4;
-    *(uint32_t*)(tagaddr) = CRYP->DOUT;
+    *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
   }
   
   /* Change the CRYP peripheral state */
@@ -1075,27 +1075,27 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *A
     hcryp->Phase = HAL_CRYP_PHASE_FINAL;
     
     /* Disable CRYP to start the final phase */
-    __HAL_CRYP_DISABLE();
+    __HAL_CRYP_DISABLE(hcryp);
     
     /* Select final phase */
-    __HAL_CRYP_SET_PHASE(CRYP_PHASE_FINAL);
+    __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_FINAL);
     
     /* Enable the CRYP peripheral */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Write the counter block in the IN FIFO */
-    CRYP->DR = *(uint32_t*)ctraddr;
+    hcryp->Instance->DR = *(uint32_t*)ctraddr;
     ctraddr+=4;
-    CRYP->DR = *(uint32_t*)ctraddr;
+    hcryp->Instance->DR = *(uint32_t*)ctraddr;
     ctraddr+=4;
-    CRYP->DR = *(uint32_t*)ctraddr;
+    hcryp->Instance->DR = *(uint32_t*)ctraddr;
     ctraddr+=4;
-    CRYP->DR = *(uint32_t*)ctraddr;
+    hcryp->Instance->DR = *(uint32_t*)ctraddr;
     
     /* Get tick */
     tickstart = HAL_GetTick();
 
-    while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE))
+    while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
     {
       /* Check for the Timeout */
       if(Timeout != HAL_MAX_DELAY)
@@ -1114,10 +1114,10 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *A
     }
     
     /* Read the Auth TAG in the IN FIFO */
-    temptag[0] = CRYP->DOUT;
-    temptag[1] = CRYP->DOUT;
-    temptag[2] = CRYP->DOUT;
-    temptag[3] = CRYP->DOUT;
+    temptag[0] = hcryp->Instance->DOUT;
+    temptag[1] = hcryp->Instance->DOUT;
+    temptag[2] = hcryp->Instance->DOUT;
+    temptag[3] = hcryp->Instance->DOUT;
   }
   
   /* Copy temporary authentication TAG in user TAG buffer */
@@ -1250,26 +1250,26 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *
     CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
     
     /* Set the CRYP peripheral in AES CCM mode */
-    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
+    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
     
     /* Set the Initialization Vector */
     CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
     
     /* Select init phase */
-    __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
+    __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
     
     b0addr = (uint32_t)blockb0;
     /* Write the blockb0 block in the IN FIFO */
-    CRYP->DR = *(uint32_t*)(b0addr);
+    hcryp->Instance->DR = *(uint32_t*)(b0addr);
     b0addr+=4;
-    CRYP->DR = *(uint32_t*)(b0addr);
+    hcryp->Instance->DR = *(uint32_t*)(b0addr);
     b0addr+=4;
-    CRYP->DR = *(uint32_t*)(b0addr);
+    hcryp->Instance->DR = *(uint32_t*)(b0addr);
     b0addr+=4;
-    CRYP->DR = *(uint32_t*)(b0addr);
+    hcryp->Instance->DR = *(uint32_t*)(b0addr);
     
     /* Enable the CRYP peripheral */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Get tick */
     tickstart = HAL_GetTick();
@@ -1295,17 +1295,17 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *
     if(headersize != 0)
     {
       /* Select header phase */
-      __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
+      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
       
       /* Enable Crypto processor */
-      __HAL_CRYP_ENABLE();
+      __HAL_CRYP_ENABLE(hcryp);
       
       for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
       {
         /* Get tick */
         tickstart = HAL_GetTick();
 
-        while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
+        while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
         {
           /* Check for the Timeout */
           if(Timeout != HAL_MAX_DELAY)
@@ -1323,20 +1323,20 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *
           }
         }
         /* Write the header block in the IN FIFO */
-        CRYP->DR = *(uint32_t*)(headeraddr);
+        hcryp->Instance->DR = *(uint32_t*)(headeraddr);
         headeraddr+=4;
-        CRYP->DR = *(uint32_t*)(headeraddr);
+        hcryp->Instance->DR = *(uint32_t*)(headeraddr);
         headeraddr+=4;
-        CRYP->DR = *(uint32_t*)(headeraddr);
+        hcryp->Instance->DR = *(uint32_t*)(headeraddr);
         headeraddr+=4;
-        CRYP->DR = *(uint32_t*)(headeraddr);
+        hcryp->Instance->DR = *(uint32_t*)(headeraddr);
         headeraddr+=4;
       }
       
       /* Get tick */
       tickstart = HAL_GetTick();
 
-      while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+      while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
       {
       /* Check for the Timeout */
         if(Timeout != HAL_MAX_DELAY)
@@ -1362,13 +1362,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *
     /* Reset bit 0 */
     hcryp->Init.pScratch[15] &= 0xfe;
     /* Select payload phase once the header phase is performed */
-    __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+    __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
     
     /* Flush FIFO */
-    __HAL_CRYP_FIFO_FLUSH();
+    __HAL_CRYP_FIFO_FLUSH(hcryp);
     
     /* Enable the CRYP peripheral */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Set the phase */
     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -1426,16 +1426,16 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
       CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
       
       /* Set the CRYP peripheral in AES GCM mode */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
       
       /* Set the Initialization Vector */
       CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
       
       /* Flush FIFO */
-      __HAL_CRYP_FIFO_FLUSH();
+      __HAL_CRYP_FIFO_FLUSH(hcryp);
       
       /* Enable CRYP to start the init phase */
-      __HAL_CRYP_ENABLE();
+      __HAL_CRYP_ENABLE(hcryp);
       
      /* Get tick */
      tickstart = HAL_GetTick();
@@ -1463,13 +1463,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
         return HAL_TIMEOUT;
       }
       /* Disable the CRYP peripheral */
-      __HAL_CRYP_DISABLE();
+      __HAL_CRYP_DISABLE(hcryp);
       
       /* Select payload phase once the header phase is performed */
-      __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
       
       /* Flush FIFO */
-      __HAL_CRYP_FIFO_FLUSH();
+      __HAL_CRYP_FIFO_FLUSH(hcryp);
       
       /* Set the phase */
       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -1478,9 +1478,9 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
     if(Size != 0)
     {
       /* Enable Interrupts */
-      __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+      __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
       /* Enable the CRYP peripheral */
-      __HAL_CRYP_ENABLE();
+      __HAL_CRYP_ENABLE(hcryp);
     }
     else
     {
@@ -1492,42 +1492,42 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
     /* Return function status */
     return HAL_OK;
   }
-  else if (__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
   {
     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
     /* Write the Input block in the IN FIFO */
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR  = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     hcryp->pCrypInBuffPtr += 16;
     hcryp->CrypInCount -= 16;
     if(hcryp->CrypInCount == 0)
     {
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
       /* Call the Input data transfer complete callback */
       HAL_CRYP_InCpltCallback(hcryp);
     }
   }
-  else if (__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
   {
     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
     /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     hcryp->pCrypOutBuffPtr += 16;
     hcryp->CrypOutCount -= 16;
     if(hcryp->CrypOutCount == 0)
     {
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
       /* Process Unlocked */
       __HAL_UNLOCK(hcryp);
       /* Change the CRYP peripheral state */
@@ -1662,26 +1662,26 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
       CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
       
       /* Set the CRYP peripheral in AES CCM mode */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
       
       /* Set the Initialization Vector */
       CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
       
       /* Select init phase */
-      __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
+      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
       
       b0addr = (uint32_t)blockb0;
       /* Write the blockb0 block in the IN FIFO */
-      CRYP->DR = *(uint32_t*)(b0addr);
+      hcryp->Instance->DR = *(uint32_t*)(b0addr);
       b0addr+=4;
-      CRYP->DR = *(uint32_t*)(b0addr);
+      hcryp->Instance->DR = *(uint32_t*)(b0addr);
       b0addr+=4;
-      CRYP->DR = *(uint32_t*)(b0addr);
+      hcryp->Instance->DR = *(uint32_t*)(b0addr);
       b0addr+=4;
-      CRYP->DR = *(uint32_t*)(b0addr);
+      hcryp->Instance->DR = *(uint32_t*)(b0addr);
       
       /* Enable the CRYP peripheral */
-      __HAL_CRYP_ENABLE();
+      __HAL_CRYP_ENABLE(hcryp);
       
      /* Get tick */
      tickstart = HAL_GetTick();
@@ -1704,17 +1704,17 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
       if(headersize != 0)
       {
         /* Select header phase */
-        __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
+        __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
         
         /* Enable Crypto processor */
-        __HAL_CRYP_ENABLE();
+        __HAL_CRYP_ENABLE(hcryp);
         
         for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
         {
          /* Get tick */
          tickstart = HAL_GetTick();
 
-          while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
+          while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
           {
             /* Check for the Timeout */
             if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
@@ -1729,20 +1729,20 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
             }
           }
           /* Write the header block in the IN FIFO */
-          CRYP->DR = *(uint32_t*)(headeraddr);
+          hcryp->Instance->DR = *(uint32_t*)(headeraddr);
           headeraddr+=4;
-          CRYP->DR = *(uint32_t*)(headeraddr);
+          hcryp->Instance->DR = *(uint32_t*)(headeraddr);
           headeraddr+=4;
-          CRYP->DR = *(uint32_t*)(headeraddr);
+          hcryp->Instance->DR = *(uint32_t*)(headeraddr);
           headeraddr+=4;
-          CRYP->DR = *(uint32_t*)(headeraddr);
+          hcryp->Instance->DR = *(uint32_t*)(headeraddr);
           headeraddr+=4;
         }
 
         /* Get tick */
         tickstart = HAL_GetTick();
 
-        while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+        while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
         {
           /* Check for the Timeout */
           if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
@@ -1766,10 +1766,10 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
       hcryp->Init.pScratch[15] &= 0xfe;
       
       /* Select payload phase once the header phase is performed */
-      __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
       
       /* Flush FIFO */
-      __HAL_CRYP_FIFO_FLUSH();
+      __HAL_CRYP_FIFO_FLUSH(hcryp);
       
       /* Set the phase */
       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -1778,9 +1778,9 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
     if(Size != 0)
     {
       /* Enable Interrupts */
-      __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+      __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
       /* Enable the CRYP peripheral */
-      __HAL_CRYP_ENABLE();
+      __HAL_CRYP_ENABLE(hcryp);
     }
     else
     {
@@ -1791,42 +1791,42 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
     /* Return function status */
     return HAL_OK;
   }
-  else if (__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
   {
     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
     /* Write the Input block in the IN FIFO */
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR  = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     hcryp->pCrypInBuffPtr += 16;
     hcryp->CrypInCount -= 16;
     if(hcryp->CrypInCount == 0)
     {
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
       /* Call Input transfer complete callback */
       HAL_CRYP_InCpltCallback(hcryp);
     }
   }
-  else if (__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
   {
     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
     /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     hcryp->pCrypOutBuffPtr += 16;
     hcryp->CrypOutCount -= 16;
     if(hcryp->CrypOutCount == 0)
     {
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
       /* Process Unlocked */
       __HAL_UNLOCK(hcryp);
       /* Change the CRYP peripheral state */
@@ -1876,16 +1876,16 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
       CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
       
       /* Set the CRYP peripheral in AES GCM decryption mode */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
       
       /* Set the Initialization Vector */
       CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
       
       /* Flush FIFO */
-      __HAL_CRYP_FIFO_FLUSH();
+      __HAL_CRYP_FIFO_FLUSH(hcryp);
       
       /* Enable CRYP to start the init phase */
-      __HAL_CRYP_ENABLE();
+      __HAL_CRYP_ENABLE(hcryp);
 
         /* Get tick */
         tickstart = HAL_GetTick();
@@ -1911,10 +1911,10 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
         return HAL_TIMEOUT;
       }
       /* Disable the CRYP peripheral */
-      __HAL_CRYP_DISABLE();
+      __HAL_CRYP_DISABLE(hcryp);
       
       /* Select payload phase once the header phase is performed */
-      __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
       
       /* Set the phase */
       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -1923,9 +1923,9 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
     if(Size != 0)
     {
       /* Enable Interrupts */
-      __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+      __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
       /* Enable the CRYP peripheral */
-      __HAL_CRYP_ENABLE();
+      __HAL_CRYP_ENABLE(hcryp);
     }
     else
     {
@@ -1938,42 +1938,42 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
     /* Return function status */
     return HAL_OK;
   }
-  else if (__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
   {
     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
     /* Write the Input block in the IN FIFO */
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR  = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     hcryp->pCrypInBuffPtr += 16;
     hcryp->CrypInCount -= 16;
     if(hcryp->CrypInCount == 0)
     {
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
       /* Call the Input data transfer complete callback */
       HAL_CRYP_InCpltCallback(hcryp);
     }
   }
-  else if (__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
   {
     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
     /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     hcryp->pCrypOutBuffPtr += 16;
     hcryp->CrypOutCount -= 16;
     if(hcryp->CrypOutCount == 0)
     {
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
       /* Process Unlocked */
       __HAL_UNLOCK(hcryp);
       /* Change the CRYP peripheral state */
@@ -2108,26 +2108,26 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
       CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
       
       /* Set the CRYP peripheral in AES CCM mode */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
       
       /* Set the Initialization Vector */
       CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
       
       /* Select init phase */
-      __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
+      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
       
       b0addr = (uint32_t)blockb0;
       /* Write the blockb0 block in the IN FIFO */
-      CRYP->DR = *(uint32_t*)(b0addr);
+      hcryp->Instance->DR = *(uint32_t*)(b0addr);
       b0addr+=4;
-      CRYP->DR = *(uint32_t*)(b0addr);
+      hcryp->Instance->DR = *(uint32_t*)(b0addr);
       b0addr+=4;
-      CRYP->DR = *(uint32_t*)(b0addr);
+      hcryp->Instance->DR = *(uint32_t*)(b0addr);
       b0addr+=4;
-      CRYP->DR = *(uint32_t*)(b0addr);
+      hcryp->Instance->DR = *(uint32_t*)(b0addr);
       
       /* Enable the CRYP peripheral */
-      __HAL_CRYP_ENABLE();
+      __HAL_CRYP_ENABLE(hcryp);
 
       /* Get tick */
       tickstart = HAL_GetTick();
@@ -2150,17 +2150,17 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
       if(headersize != 0)
       {
         /* Select header phase */
-        __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
+        __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
         
         /* Enable Crypto processor */
-        __HAL_CRYP_ENABLE();
+        __HAL_CRYP_ENABLE(hcryp);
         
         for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
         {
          /* Get tick */
          tickstart = HAL_GetTick();
 
-          while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
+          while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
           {
             /* Check for the Timeout */
             if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
@@ -2175,20 +2175,20 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
             }
           }
           /* Write the header block in the IN FIFO */
-          CRYP->DR = *(uint32_t*)(headeraddr);
+          hcryp->Instance->DR = *(uint32_t*)(headeraddr);
           headeraddr+=4;
-          CRYP->DR = *(uint32_t*)(headeraddr);
+          hcryp->Instance->DR = *(uint32_t*)(headeraddr);
           headeraddr+=4;
-          CRYP->DR = *(uint32_t*)(headeraddr);
+          hcryp->Instance->DR = *(uint32_t*)(headeraddr);
           headeraddr+=4;
-          CRYP->DR = *(uint32_t*)(headeraddr);
+          hcryp->Instance->DR = *(uint32_t*)(headeraddr);
           headeraddr+=4;
         }
 
         /* Get tick */
         tickstart = HAL_GetTick();
 
-        while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+        while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
         {
           /* Check for the Timeout */
           if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
@@ -2211,60 +2211,60 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
       /* Reset bit 0 */
       hcryp->Init.pScratch[15] &= 0xfe;
       /* Select payload phase once the header phase is performed */
-      __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
       
       /* Flush FIFO */
-      __HAL_CRYP_FIFO_FLUSH();
+      __HAL_CRYP_FIFO_FLUSH(hcryp);
       
       /* Set the phase */
       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
     }
     
     /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
     
     /* Enable the CRYP peripheral */
-    __HAL_CRYP_ENABLE();
+    __HAL_CRYP_ENABLE(hcryp);
     
     /* Return function status */
     return HAL_OK;
   }
-  else if (__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
   {
     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
     /* Write the Input block in the IN FIFO */
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR  = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
     inputaddr+=4;
-    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
     hcryp->pCrypInBuffPtr += 16;
     hcryp->CrypInCount -= 16;
     if(hcryp->CrypInCount == 0)
     {
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
       /* Call the Input data transfer complete callback */
       HAL_CRYP_InCpltCallback(hcryp);
     }
   }
-  else if (__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
   {
     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
     /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     outputaddr+=4;
-    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
     hcryp->pCrypOutBuffPtr += 16;
     hcryp->CrypOutCount -= 16;
     if(hcryp->CrypOutCount == 0)
     {
-      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
       /* Process Unlocked */
       __HAL_UNLOCK(hcryp);
       /* Change the CRYP peripheral state */
@@ -2311,16 +2311,16 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8
       CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
       
       /* Set the CRYP peripheral in AES GCM mode */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
       
       /* Set the Initialization Vector */
       CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
       
       /* Flush FIFO */
-      __HAL_CRYP_FIFO_FLUSH();
+      __HAL_CRYP_FIFO_FLUSH(hcryp);
       
       /* Enable CRYP to start the init phase */
-      __HAL_CRYP_ENABLE();
+      __HAL_CRYP_ENABLE(hcryp);
       
       /* Get tick */
       tickstart = HAL_GetTick();
@@ -2340,7 +2340,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8
         }
       }
       /* Flush FIFO */
-      __HAL_CRYP_FIFO_FLUSH();
+      __HAL_CRYP_FIFO_FLUSH(hcryp);
       
       /* Set the header phase */
       if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)
@@ -2348,13 +2348,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8
         return HAL_TIMEOUT;
       }
       /* Disable the CRYP peripheral */
-      __HAL_CRYP_DISABLE();
+      __HAL_CRYP_DISABLE(hcryp);
       
       /* Select payload phase once the header phase is performed */
-      __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
       
       /* Flush FIFO */
-      __HAL_CRYP_FIFO_FLUSH();
+      __HAL_CRYP_FIFO_FLUSH(hcryp);
       
       /* Set the phase */
       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -2501,26 +2501,26 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8
       CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
       
       /* Set the CRYP peripheral in AES CCM mode */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
       
       /* Set the Initialization Vector */
       CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
       
       /* Select init phase */
-      __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
+      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
       
       b0addr = (uint32_t)blockb0;
       /* Write the blockb0 block in the IN FIFO */
-      CRYP->DR = *(uint32_t*)(b0addr);
+      hcryp->Instance->DR = *(uint32_t*)(b0addr);
       b0addr+=4;
-      CRYP->DR = *(uint32_t*)(b0addr);
+      hcryp->Instance->DR = *(uint32_t*)(b0addr);
       b0addr+=4;
-      CRYP->DR = *(uint32_t*)(b0addr);
+      hcryp->Instance->DR = *(uint32_t*)(b0addr);
       b0addr+=4;
-      CRYP->DR = *(uint32_t*)(b0addr);
+      hcryp->Instance->DR = *(uint32_t*)(b0addr);
       
       /* Enable the CRYP peripheral */
-      __HAL_CRYP_ENABLE();
+      __HAL_CRYP_ENABLE(hcryp);
       
       /* Get tick */
       tickstart = HAL_GetTick();
@@ -2543,17 +2543,17 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8
       if(headersize != 0)
       {
         /* Select header phase */
-        __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
+        __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
         
         /* Enable Crypto processor */
-        __HAL_CRYP_ENABLE();
+        __HAL_CRYP_ENABLE(hcryp);
         
         for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
         {
          /* Get tick */
          tickstart = HAL_GetTick();
 
-          while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
+          while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
           {
             /* Check for the Timeout */
             if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
@@ -2568,20 +2568,20 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8
             }
           }
           /* Write the header block in the IN FIFO */
-          CRYP->DR = *(uint32_t*)(headeraddr);
+          hcryp->Instance->DR = *(uint32_t*)(headeraddr);
           headeraddr+=4;
-          CRYP->DR = *(uint32_t*)(headeraddr);
+          hcryp->Instance->DR = *(uint32_t*)(headeraddr);
           headeraddr+=4;
-          CRYP->DR = *(uint32_t*)(headeraddr);
+          hcryp->Instance->DR = *(uint32_t*)(headeraddr);
           headeraddr+=4;
-          CRYP->DR = *(uint32_t*)(headeraddr);
+          hcryp->Instance->DR = *(uint32_t*)(headeraddr);
           headeraddr+=4;
         }
         
         /* Get tick */
         tickstart = HAL_GetTick();
 
-        while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+        while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
         {
           /* Check for the Timeout */
           if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
@@ -2605,10 +2605,10 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8
       hcryp->Init.pScratch[15] &= 0xfe;
       
       /* Select payload phase once the header phase is performed */
-      __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
       
       /* Flush FIFO */
-      __HAL_CRYP_FIFO_FLUSH();
+      __HAL_CRYP_FIFO_FLUSH(hcryp);
       
       /* Set the phase */
       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -2662,13 +2662,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8
       CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
       
       /* Set the CRYP peripheral in AES GCM decryption mode */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
       
       /* Set the Initialization Vector */
       CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
       
       /* Enable CRYP to start the init phase */
-      __HAL_CRYP_ENABLE();
+      __HAL_CRYP_ENABLE(hcryp);
       
       /* Get tick */
       tickstart = HAL_GetTick();
@@ -2694,10 +2694,10 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8
         return HAL_TIMEOUT;
       }
       /* Disable the CRYP peripheral */
-      __HAL_CRYP_DISABLE();
+      __HAL_CRYP_DISABLE(hcryp);
       
       /* Select payload phase once the header phase is performed */
-      __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
       
       /* Set the phase */
       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
@@ -2845,26 +2845,26 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8
       CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
       
       /* Set the CRYP peripheral in AES CCM mode */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
       
       /* Set the Initialization Vector */
       CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
       
       /* Select init phase */
-      __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
+      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
       
       b0addr = (uint32_t)blockb0;
       /* Write the blockb0 block in the IN FIFO */
-      CRYP->DR = *(uint32_t*)(b0addr);
+      hcryp->Instance->DR = *(uint32_t*)(b0addr);
       b0addr+=4;
-      CRYP->DR = *(uint32_t*)(b0addr);
+      hcryp->Instance->DR = *(uint32_t*)(b0addr);
       b0addr+=4;
-      CRYP->DR = *(uint32_t*)(b0addr);
+      hcryp->Instance->DR = *(uint32_t*)(b0addr);
       b0addr+=4;
-      CRYP->DR = *(uint32_t*)(b0addr);
+      hcryp->Instance->DR = *(uint32_t*)(b0addr);
       
       /* Enable the CRYP peripheral */
-      __HAL_CRYP_ENABLE();
+      __HAL_CRYP_ENABLE(hcryp);
       
       /* Get tick */
       tickstart = HAL_GetTick();
@@ -2889,17 +2889,17 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8
       if(headersize != 0)
       {
         /* Select header phase */
-        __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
+        __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
         
         /* Enable Crypto processor */
-        __HAL_CRYP_ENABLE();
+        __HAL_CRYP_ENABLE(hcryp);
         
         for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
         {
          /* Get tick */
          tickstart = HAL_GetTick();
  
-          while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
+          while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
           {
             /* Check for the Timeout */
             if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
@@ -2914,20 +2914,20 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8
             }
           }
           /* Write the header block in the IN FIFO */
-          CRYP->DR = *(uint32_t*)(headeraddr);
+          hcryp->Instance->DR = *(uint32_t*)(headeraddr);
           headeraddr+=4;
-          CRYP->DR = *(uint32_t*)(headeraddr);
+          hcryp->Instance->DR = *(uint32_t*)(headeraddr);
           headeraddr+=4;
-          CRYP->DR = *(uint32_t*)(headeraddr);
+          hcryp->Instance->DR = *(uint32_t*)(headeraddr);
           headeraddr+=4;
-          CRYP->DR = *(uint32_t*)(headeraddr);
+          hcryp->Instance->DR = *(uint32_t*)(headeraddr);
           headeraddr+=4;
         }
         
         /* Get tick */
         tickstart = HAL_GetTick();
 
-        while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+        while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
         {
           /* Check for the Timeout */
           if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
@@ -2950,10 +2950,10 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8
       /* Reset bit 0 */
       hcryp->Init.pScratch[15] &= 0xfe;
       /* Select payload phase once the header phase is performed */
-      __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
       
       /* Flush FIFO */
-      __HAL_CRYP_FIFO_FLUSH();
+      __HAL_CRYP_FIFO_FLUSH(hcryp);
       
       /* Set the phase */
       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_dac.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dac.c
index a243cb44f..355033cb6 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_dac.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dac.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dac.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   DAC HAL module driver.
   *         This file provides firmware functions to manage the following 
   *         functionalities of the Digital to Analog Converter (DAC) peripheral:
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_dac_ex.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dac_ex.c
index a3c5481bb..899a14a92 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_dac_ex.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dac_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dac_ex.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Extended DAC HAL module driver.
   *         This file provides firmware functions to manage the following 
   *         functionalities of DAC extension peripheral:
@@ -154,10 +154,8 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32
   hdac->State = HAL_DAC_STATE_BUSY;
   
   /* Enable the selected wave generation for the selected DAC channel */
-  MODIFY_REG(hdac->Instance->CR, \
-             ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << Channel, \
-             (DAC_WAVE_TRIANGLE | Amplitude) << Channel);
-  
+  MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
+
   /* Change DAC state */
   hdac->State = HAL_DAC_STATE_READY;
   
@@ -205,9 +203,7 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t
   hdac->State = HAL_DAC_STATE_BUSY;
   
   /* Enable the selected wave generation for the selected DAC channel */
-  MODIFY_REG(hdac->Instance->CR, \
-             ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << Channel, \
-             (DAC_WAVE_NOISE | Amplitude) << Channel);
+  MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
   
   /* Change DAC state */
   hdac->State = HAL_DAC_STATE_READY;
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_dcmi.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dcmi.c
index 1747e820a..95c7fd065 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_dcmi.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dcmi.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dcmi.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   DCMI HAL module driver
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Digital Camera Interface (DCMI) peripheral:
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_dcmi_ex.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dcmi_ex.c
index cb0dea227..ef58cb726 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_dcmi_ex.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dcmi_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dcmi_ex.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   DCMI Extension HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of DCMI extension peripheral:
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_dma.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dma.c
index e9762a59b..c773dac11 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_dma.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dma.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dma.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   DMA HAL module driver.
   *    
   *          This file provides firmware functions to manage the following 
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_dma2d.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dma2d.c
index db78a3fb9..50333f067 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_dma2d.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dma2d.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dma2d.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   DMA2D HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the DMA2D peripheral:
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_dma_ex.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dma_ex.c
index 6f218b5b3..109be75d8 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_dma_ex.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dma_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_dma_ex.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   DMA Extension HAL module driver
   *         This file provides firmware functions to manage the following 
   *         functionalities of the DMA Extension peripheral:
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_eth.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_eth.c
index 0d07eccea..1bbf8f9c0 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_eth.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_eth.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_eth.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   ETH HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Ethernet (ETH) peripheral:
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_flash.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_flash.c
index f63465247..3d2ae6607 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_flash.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_flash.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_flash.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   FLASH HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the internal FLASH memory:
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_flash_ex.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_flash_ex.c
index e6686b01d..bada74b33 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_flash_ex.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_flash_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_flash_ex.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Extended FLASH HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the FLASH extension peripheral:
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_gpio.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_gpio.c
index 8d63648cf..73696d6b8 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_gpio.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_gpio.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_gpio.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   GPIO HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
@@ -348,7 +348,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
       /*------------------------- EXTI Mode Configuration --------------------*/
       tmp = SYSCFG->EXTICR[position >> 2];
       tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
-      if(tmp == ((uint32_t)(GET_GPIO_SOURCE(GPIOx)) << (4 * (position & 0x03))))
+      if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))))
       {
         /* Configure the External Interrupt or event for the current IO */
         tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_hash.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_hash.c
index 1b0d08596..bfc98150b 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_hash.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_hash.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_hash.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   HASH HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the HASH peripheral:
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_hash_ex.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_hash_ex.c
index 798dbf2b2..51b0c95f2 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_hash_ex.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_hash_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_hash_ex.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   HASH HAL Extension module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of HASH peripheral:
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_hcd.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_hcd.c
index 07b40006c..5b6bb9d12 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_hcd.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_hcd.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_hcd.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   HCD HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the USB Peripheral Controller:
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_i2c.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_i2c.c
index 8aea9fbc7..e4a2a33d2 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_i2c.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_i2c.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_i2c.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   I2C HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_i2c_ex.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_i2c_ex.c
index a143f774f..bcde7b0d9 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_i2c_ex.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_i2c_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_i2c_ex.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   I2C Extended HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of I2C Extended peripheral:
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_i2s.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_i2s.c
index f0a660f88..32747201b 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_i2s.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_i2s.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_i2s.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   I2S HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Integrated Interchip Sound (I2S) peripheral:
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_irda.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_irda.c
index 74f67bb01..aa6d89f20 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_irda.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_irda.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_irda.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   IRDA HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the IrDA SIR ENDEC block (IrDA):
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_iwdg.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_iwdg.c
index 9b7a56921..a156715f5 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_iwdg.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_iwdg.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_iwdg.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   IWDG HAL module driver.
   *    
   *          This file provides firmware functions to manage the following 
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_lptim.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_lptim.c
index df45fe9ac..22d635d0a 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_lptim.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_lptim.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_lptim.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   LPTIM HAL module driver.
   *    
   *          This file provides firmware functions to manage the following 
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_ltdc.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_ltdc.c
index a640ff4e4..319533d5f 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_ltdc.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_ltdc.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_ltdc.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   LTDC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the LTDC peripheral:
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_msp_template.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_msp_template.c
index 58826c1ca..9251f39f5 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_msp_template.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_msp_template.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_msp_template.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   HAL MSP module.
   *          This file template is located in the HAL folder and should be copied 
   *          to the user folder.
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_nand.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_nand.c
index cd6995fc3..5e96d330e 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_nand.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_nand.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_nand.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   NAND HAL module driver.
   *          This file provides a generic firmware to drive NAND memories mounted 
   *          as external device.
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_nor.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_nor.c
index 55d4f0415..8c8eda803 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_nor.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_nor.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_nor.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   NOR HAL module driver.
   *          This file provides a generic firmware to drive NOR memories mounted 
   *          as external device.
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_pcd.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_pcd.c
index 1a73138d0..0bfcf7c6d 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_pcd.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_pcd.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_pcd.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   PCD HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the USB Peripheral Controller:
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_pcd_ex.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_pcd_ex.c
index c3d5efa9c..e1093c2a4 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_pcd_ex.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_pcd_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_pcd_ex.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   PCD HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the USB Peripheral Controller:
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_pwr.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_pwr.c
index 55a88dbb3..60960295b 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_pwr.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_pwr.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_pwr.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   PWR HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Power Controller (PWR) peripheral:
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_pwr_ex.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_pwr_ex.c
index 73560f873..c25cbaf8f 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_pwr_ex.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_pwr_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_pwr_ex.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Extended PWR HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of PWR extension peripheral:           
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_qspi.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_qspi.c
index baf2af5d3..f14eae5dc 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_qspi.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_qspi.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_qspi.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   QSPI HAL module driver.
   *
   *          This file provides firmware functions to manage the following 
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_rcc.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_rcc.c
index 32914987d..c475fe2a8 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_rcc.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_rcc.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_rcc.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   RCC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Reset and Clock Control (RCC) peripheral:
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_rcc_ex.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_rcc_ex.c
index 72eded3c9..349361705 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_rcc_ex.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_rcc_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_rcc_ex.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   Extension RCC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities RCC extension peripheral:
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_rng.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_rng.c
index aaa99b9c2..c698ea755 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_rng.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_rng.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_rng.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   RNG HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Random Number Generator (RNG) peripheral:
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_rtc.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_rtc.c
index ea6fb3180..a54b197a1 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_rtc.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_rtc.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_rtc.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   RTC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Real Time Clock (RTC) peripheral:
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_rtc_ex.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_rtc_ex.c
index 8dcf97d30..d985e0adf 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_rtc_ex.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_rtc_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_rtc_ex.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   RTC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Real Time Clock (RTC) Extension peripheral:
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_sai.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_sai.c
index b207e951c..6a47fe21c 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_sai.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_sai.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_sai.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   SAI HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Serial Audio Interface (SAI) peripheral:
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_sai_ex.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_sai_ex.c
index 3021a62fe..d06ff65ac 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_sai_ex.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_sai_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_sai_ex.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   SAI Extension HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of SAI extension peripheral:
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_sd.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_sd.c
index 3acf1c09a..990c1711b 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_sd.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_sd.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_sd.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   SD card HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Secure Digital (SD) peripheral:
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_sdram.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_sdram.c
index 59b40ef60..ed3d83e90 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_sdram.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_sdram.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_sdram.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   SDRAM HAL module driver.
   *          This file provides a generic firmware to drive SDRAM memories mounted 
   *          as external device.
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_smartcard.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_smartcard.c
index 9a6edf0ec..d71274851 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_smartcard.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_smartcard.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_smartcard.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   SMARTCARD HAL module driver.
   *          This file provides firmware functions to manage the following
   *          functionalities of the SMARTCARD peripheral:
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_smartcard_ex.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_smartcard_ex.c
index d17bcde28..f0ebcf6f1 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_smartcard_ex.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_smartcard_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_smartcard_ex.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   SMARTCARD HAL module driver.
   *
   *          This file provides extended firmware functions to manage the following 
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_spdifrx.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_spdifrx.c
index 0b3e2346c..e88e320a9 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_spdifrx.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_spdifrx.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_spdifrx.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   This file provides firmware functions to manage the following 
   *          functionalities of the SPDIFRX audio interface:
   *           + Initialization and Configuration
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_spi.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_spi.c
index 4edfa09af..a0dc0dfb3 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_spi.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_spi.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_spi.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   SPI HAL module driver.
   *    
   *          This file provides firmware functions to manage the following 
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_sram.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_sram.c
index d7aad5ce8..2d839d7b7 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_sram.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_sram.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_sram.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   SRAM HAL module driver.
   *          This file provides a generic firmware to drive SRAM memories  
   *          mounted as external device.
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_tim.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_tim.c
index 088b4472a..d7b18cef1 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_tim.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_tim.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_tim.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   TIM HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Timer (TIM) peripheral:
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_tim_ex.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_tim_ex.c
index 5f5d5cdb1..a0e997fc7 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_tim_ex.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_tim_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_tim_ex.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   TIM HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Timer extension peripheral:
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_uart.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_uart.c
index 0e1717e89..081017259 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_uart.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_uart.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_uart.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   UART HAL module driver.
   *
   *          This file provides firmware functions to manage the following 
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_usart.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_usart.c
index 534eaed88..a9bc475a8 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_usart.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_usart.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_usart.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   USART HAL module driver.
   *
   *          This file provides firmware functions to manage the following 
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_wwdg.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_wwdg.c
index 93e3a5c9b..7fff72493 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_hal_wwdg.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_wwdg.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_wwdg.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   WWDG HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Window Watchdog (WWDG) peripheral:
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_ll_fmc.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_ll_fmc.c
index 8645ce00a..62c60bc37 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_ll_fmc.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_ll_fmc.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_ll_fmc.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   FMC Low Layer HAL module driver.
   *    
   *          This file provides firmware functions to manage the following 
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_ll_sdmmc.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_ll_sdmmc.c
index 36c151b53..f97c30076 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_ll_sdmmc.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_ll_sdmmc.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_ll_sdmmc.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   SDMMC Low Layer HAL module driver.
   *    
   *          This file provides firmware functions to manage the following 
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_ll_usb.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_ll_usb.c
index 004c65831..9a136bb47 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/ST_Library/stm32f7xx_ll_usb.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_ll_usb.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_ll_usb.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   USB Low Layer HAL module driver.
   *    
   *          This file provides firmware functions to manage the following 
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/System_IAR/startup_stm32f756xx.s b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_IAR/startup_stm32f756xx.s
index ae1776f40..20f27e43f 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/System_IAR/startup_stm32f756xx.s
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_IAR/startup_stm32f756xx.s
@@ -1,8 +1,8 @@
 ;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
 ;* File Name          : startup_stm32f756xx.s
 ;* Author             : MCD Application Team
-;* Version            : V0.3.0
-;* Date               : 06-March-2015
+;* Version            : V1.0.0RC1
+;* Date               : 24-March-2015
 ;* Description        : STM32F756xx devices vector table for EWARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/System_IAR/stm32f756xx_flash.icf b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_IAR/stm32f756xx_flash.icf
index c55a69518..c55a69518 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/System_IAR/stm32f756xx_flash.icf
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_IAR/stm32f756xx_flash.icf
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/System_IAR/stm32f7xx_hal_msp.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_IAR/stm32f7xx_hal_msp.c
index 0bfa44e01..0bfa44e01 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/System_IAR/stm32f7xx_hal_msp.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_IAR/stm32f7xx_hal_msp.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/System_IAR/stm32f7xx_it.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_IAR/stm32f7xx_it.c
index 3611b6571..3611b6571 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/System_IAR/stm32f7xx_it.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_IAR/stm32f7xx_it.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/System_IAR/stm32f7xx_it.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_IAR/stm32f7xx_it.h
index b5414dc08..b5414dc08 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/System_IAR/stm32f7xx_it.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_IAR/stm32f7xx_it.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/System_Keil/system_stm32f7xx.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_IAR/system_stm32f7xx.c
index 952383511..8e7934173 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/System_Keil/system_stm32f7xx.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_IAR/system_stm32f7xx.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f7xx.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
   *
   *   This file provides two functions and one global variable to be called from 
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/System_Keil/startup_stm32f756xx.s b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_Keil/startup_stm32f756xx.s
index f10d50e94..72746b293 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/System_Keil/startup_stm32f756xx.s
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_Keil/startup_stm32f756xx.s
@@ -1,8 +1,8 @@
 ;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
 ;* File Name          : startup_stm32f756xx.s
 ;* Author             : MCD Application Team
-;* Version            : V0.3.0
-;* Date               : 06-March-2015
+;* Version            : V1.0.0RC1
+;* Date               : 24-March-2015
 ;* Description        : STM32F756xx devices vector table for MDK-ARM toolchain. 
 ;*                      This module performs:
 ;*                      - Set the initial SP
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/System_Keil/stm32f7xx_hal_msp.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_Keil/stm32f7xx_hal_msp.c
index 0bfa44e01..0bfa44e01 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/System_Keil/stm32f7xx_hal_msp.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_Keil/stm32f7xx_hal_msp.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/System_Keil/stm32f7xx_it.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_Keil/stm32f7xx_it.c
index 3611b6571..3611b6571 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/System_Keil/stm32f7xx_it.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_Keil/stm32f7xx_it.c
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/System_Keil/stm32f7xx_it.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_Keil/stm32f7xx_it.h
index b5414dc08..b5414dc08 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/System_Keil/stm32f7xx_it.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_Keil/stm32f7xx_it.h
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/System_IAR/system_stm32f7xx.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_Keil/system_stm32f7xx.c
index 952383511..8e7934173 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/System_IAR/system_stm32f7xx.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_Keil/system_stm32f7xx.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f7xx.c
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    06-March-2015
+  * @version V1.0.0RC1
+  * @date    24-March-2015
   * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
   *
   *   This file provides two functions and one global variable to be called from 
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/main.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/main.c
index 057b8493c..25481cb6c 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/main.c
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/main.c
@@ -172,12 +172,13 @@ GPIO_InitTypeDef  GPIO_InitStruct;
 	/* Enable GPIOB  Clock (to be able to program the configuration
 	registers) and configure for LED output. */
 	__GPIOG_CLK_ENABLE();
+	__HAL_RCC_GPIOF_CLK_ENABLE();
 
-	GPIO_InitStruct.Pin = GPIO_PIN_6;
+	GPIO_InitStruct.Pin = GPIO_PIN_10;
 	GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 	GPIO_InitStruct.Pull = GPIO_PULLUP;
-	GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
-	HAL_GPIO_Init( GPIOG, &GPIO_InitStruct );
+	GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
+	HAL_GPIO_Init( GPIOF, &GPIO_InitStruct );
 
 	/* MCO2 : Pin PC9 */
 	HAL_RCC_MCOConfig( RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_1 );
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/settings/RTOSDemo.Debug.cspy.bat b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/settings/RTOSDemo.Debug.cspy.bat
new file mode 100644
index 000000000..4503386b2
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/settings/RTOSDemo.Debug.cspy.bat
@@ -0,0 +1,40 @@
+@REM This batch file has been generated by the IAR Embedded Workbench
+@REM C-SPY Debugger, as an aid to preparing a command line for running
+@REM the cspybat command line utility using the appropriate settings.
+@REM
+@REM Note that this file is generated every time a new debug session
+@REM is initialized, so you may want to move or rename the file before
+@REM making changes.
+@REM
+@REM You can launch cspybat by typing the name of this batch file followed
+@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).
+@REM
+@REM Read about available command line parameters in the C-SPY Debugging
+@REM Guide. Hints about additional command line parameters that may be
+@REM useful in specific cases:
+@REM   --download_only   Downloads a code image without starting a debug
+@REM                     session afterwards.
+@REM   --silent          Omits the sign-on message.
+@REM   --timeout         Limits the maximum allowed execution time.
+@REM 
+
+
+@echo off 
+
+if not "%1" == "" goto debugFile 
+
+@echo on 
+
+"C:\DevTools\IAR Systems\Embedded Workbench 7.2\common\bin\cspybat" -f "C:\E\temp\FreeRTOSv8.2.1\clean\FreeRTOS\Demo\CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil\settings\RTOSDemo.Debug.general.xcl" --backend -f "C:\E\temp\FreeRTOSv8.2.1\clean\FreeRTOS\Demo\CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil\settings\RTOSDemo.Debug.driver.xcl" 
+
+@echo off 
+goto end 
+
+:debugFile 
+
+@echo on 
+
+"C:\DevTools\IAR Systems\Embedded Workbench 7.2\common\bin\cspybat" -f "C:\E\temp\FreeRTOSv8.2.1\clean\FreeRTOS\Demo\CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil\settings\RTOSDemo.Debug.general.xcl" "--debug_file=%1" --backend -f "C:\E\temp\FreeRTOSv8.2.1\clean\FreeRTOS\Demo\CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil\settings\RTOSDemo.Debug.driver.xcl" 
+
+@echo off 
+:end
+\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/settings/RTOSDemo.crun b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/settings/RTOSDemo.crun
new file mode 100644
index 000000000..5bb5acca4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/settings/RTOSDemo.crun
@@ -0,0 +1,16 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<crun>
+  <version>1</version>
+  <filter_entries>
+    <filter index="0" type="default">
+      <type>*</type>
+      <start_file>*</start_file>
+      <end_file>*</end_file>
+      <action_debugger>0</action_debugger>
+      <action_log>1</action_log>
+    </filter>
+  </filter_entries>
+</crun>
+
+
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/settings/RTOSDemo.dbgdt b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/settings/RTOSDemo.dbgdt
index 8fbf202fb..8fbf202fb 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/settings/RTOSDemo.dbgdt
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/settings/RTOSDemo.dbgdt
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/settings/RTOSDemo.dni b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/settings/RTOSDemo.dni
index a4685b40c..cf2595eb3 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/settings/RTOSDemo.dni
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/settings/RTOSDemo.dni
@@ -55,6 +55,9 @@ ShowArgs=0
 MixedMode=1
 [JLinkDriver]
 CStepIntDis=_ 0
+WatchCond=_ 0
+Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0
+Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0
 [Trace2]
 Enabled=0
 ShowSource=0
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/settings/RTOSDemo.wsdt b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/settings/RTOSDemo.wsdt
index a8c208159..c57c9bf00 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/settings/RTOSDemo.wsdt
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/settings/RTOSDemo.wsdt
@@ -29,7 +29,7 @@
     <Windows>
       
       
-    <Wnd0>
+    <Wnd2>
         <Tabs>
           <Tab>
             <Identity>TabID-18739-8840</Identity>
@@ -41,7 +41,7 @@
           </Tab>
         </Tabs>
         
-      <SelectedTab>0</SelectedTab></Wnd0><Wnd1>
+      <SelectedTab>0</SelectedTab></Wnd2><Wnd3>
         <Tabs>
           <Tab>
             <Identity>TabID-19869-16187</Identity>
@@ -57,7 +57,7 @@
           </Tab>
         </Tabs>
         
-      <SelectedTab>0</SelectedTab></Wnd1></Windows>
+      <SelectedTab>0</SelectedTab></Wnd3></Windows>
     <Editor>
       
       
@@ -70,7 +70,7 @@
       
       
       
-    <Top><Row0><Sizes><Toolbar-026D8F98><key>iaridepm.enu1</key></Toolbar-026D8F98></Sizes></Row0><Row1><Sizes/></Row1></Top><Left><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>619</Bottom><Right>377</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203252</sizeHorzCY><sizeVertCX>225595</sizeVertCX><sizeVertCY>631098</sizeVertCY></Rect></Wnd0></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>321</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>323</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>328252</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203252</sizeVertCY></Rect></Wnd1></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>
+    <Top><Row0><Sizes><Toolbar-028190F0><key>iaridepm.enu1</key></Toolbar-028190F0></Sizes></Row0></Top><Left><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>619</Bottom><Right>377</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203252</sizeHorzCY><sizeVertCX>225595</sizeVertCX><sizeVertCY>631098</sizeVertCY></Rect></Wnd2></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>321</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>323</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>328252</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203252</sizeVertCY></Rect></Wnd3></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>
   </Desktop>
 </Workspace>
 
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/settings/RTOSDemo.wspos b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/settings/RTOSDemo.wspos
new file mode 100644
index 000000000..cd790b7cf
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/settings/RTOSDemo.wspos
@@ -0,0 +1,2 @@
+[MainWindow]
+WindowPlacement=_ 515 5 1615 901 3
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/settings/RTOSDemo_Debug.jlink b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/settings/RTOSDemo_Debug.jlink
new file mode 100644
index 000000000..706cf39a9
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/settings/RTOSDemo_Debug.jlink
@@ -0,0 +1,35 @@
+[BREAKPOINTS]
+ForceImpTypeAny = 0
+ShowInfoWin = 1
+EnableFlashBP = 2
+BPDuringExecution = 0
+[CFI]
+CFISize = 0x00
+CFIAddr = 0x00
+[CPU]
+OverrideMemMap = 0
+AllowSimulation = 1
+ScriptFile=""
+[FLASH]
+CacheExcludeSize = 0x00
+CacheExcludeAddr = 0x00
+MinNumBytesFlashDL = 0
+SkipProgOnCRCMatch = 1
+VerifyDownload = 1
+AllowCaching = 1
+EnableFlashDL = 2
+Override = 1
+Device="Unspecified"
+[GENERAL]
+WorkRAMSize = 0x00
+WorkRAMAddr = 0x00
+RAMUsageLimit = 0x00
+[SWO]
+SWOLogFile=""
+[MEM]
+RdOverrideOrMask = 0x00
+RdOverrideAndMask = 0xFFFFFFFF
+RdOverrideAddr = 0xFFFFFFFF
+WrOverrideOrMask = 0x00
+WrOverrideAndMask = 0xFFFFFFFF
+WrOverrideAddr = 0xFFFFFFFF
diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/stm32f7xx_hal_conf.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/stm32f7xx_hal_conf.h
index 016e8f300..016e8f300 100644
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/stm32f7xx_hal_conf.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/stm32f7xx_hal_conf.h
diff --git a/FreeRTOS/Demo/Common/Minimal/TaskNotify.c b/FreeRTOS/Demo/Common/Minimal/TaskNotify.c
index 48182b948..c06d9822b 100644
--- a/FreeRTOS/Demo/Common/Minimal/TaskNotify.c
+++ b/FreeRTOS/Demo/Common/Minimal/TaskNotify.c
@@ -147,7 +147,7 @@ static void prvSingleTaskTests( void )
 {
 const TickType_t xTicksToWait = pdMS_TO_TICKS( 100UL );
 BaseType_t xReturned;
-uint32_t ulNotifiedValue, ulLoop, ulNotifyingValue;
+uint32_t ulNotifiedValue, ulLoop, ulNotifyingValue, ulPreviousValue, ulExpectedValue;
 TickType_t xTimeOnEntering;
 const uint32_t ulFirstNotifiedConst = 100001UL, ulSecondNotifiedValueConst = 5555UL, ulMaxLoops = 5UL;
 const uint32_t ulBit0 = 0x01UL, ulBit1 = 0x02UL;
@@ -172,12 +172,15 @@ const uint32_t ulBit0 = 0x01UL, ulBit1 = 0x02UL;
 	Check no blocking when notifications are pending.  First notify itself -
 	this would not be a normal thing to do and is done here for test purposes
 	only. */
-	xReturned = xTaskNotify( xTaskToNotify, ulFirstNotifiedConst, eSetValueWithoutOverwrite );
+	xReturned = xTaskNotifyAndQuery( xTaskToNotify, ulFirstNotifiedConst, eSetValueWithoutOverwrite, &ulPreviousValue );
 
 	/* Even through the 'without overwrite' action was used the update should
 	have been successful. */
 	configASSERT( xReturned == pdPASS );
 
+	/* No bits should have been pending previously. */
+	configASSERT( ulPreviousValue == 0 );
+
 	/* The task should now have a notification pending, and so not time out. */
 	xTimeOnEntering = xTaskGetTickCount();
 	xReturned = xTaskNotifyWait( ULONG_MAX, 0, &ulNotifiedValue, xTicksToWait );
@@ -351,6 +354,28 @@ const uint32_t ulBit0 = 0x01UL, ulBit1 = 0x02UL;
 
 
 
+
+	/*--------------------------------------------------------------------------
+	Now try querying the previus value while notifying a task. */
+	xTaskNotifyAndQuery( xTaskToNotify, 0x00, eSetBits, &ulPreviousValue );
+	configASSERT( ulNotifiedValue == ( ULONG_MAX & ~( ulBit0 | ulBit1 ) ) );
+
+	/* Clear all bits. */
+	xTaskNotifyWait( 0x00, ULONG_MAX, &ulNotifiedValue, 0 );
+	xTaskNotifyAndQuery( xTaskToNotify, 0x00, eSetBits, &ulPreviousValue );
+	configASSERT( ulPreviousValue == 0 );
+
+	ulExpectedValue = 0;
+	for( ulLoop = 0x01; ulLoop < 0x80UL; ulLoop <<= 1UL )
+	{
+		/* Set the next bit up, and expect to receive the last bits set (so
+		the previous value will not yet have the bit being set this time
+		around). */
+		xTaskNotifyAndQuery( xTaskToNotify, ulLoop, eSetBits, &ulPreviousValue );
+		configASSERT( ulExpectedValue == ulPreviousValue );
+		ulExpectedValue |= ulLoop;
+	}
+
 	/* Incremented to show the task is still running. */
 	ulNotifyCycleCount++;
 
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/base_microblaze_design_wrapper.bit b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/base_microblaze_design_wrapper.bit
deleted file mode 100644
index 6fdb600f4..000000000
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/base_microblaze_design_wrapper.bit
+++ /dev/null
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/IMPORTANT_Build_Instructions.url b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/IMPORTANT_Build_Instructions.url
new file mode 100644
index 000000000..8eb875e71
--- /dev/null
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/IMPORTANT_Build_Instructions.url
@@ -0,0 +1,5 @@
+[{000214A0-0000-0000-C000-000000000046}]
+Prop3=19,2
+[InternetShortcut]
+URL=http://www.freertos.org/RTOS-Xilinx-Microblaze-KC705.html
+IDList=
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/Full_Demo/RegisterTests.S b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/Full_Demo/RegisterTests.S
index a0cc6fe3b..7f84f0397 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/Full_Demo/RegisterTests.S
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/Full_Demo/RegisterTests.S
@@ -82,7 +82,6 @@ detected an error. */
 .extern ulRegTest1LoopCounter
 .extern ulRegTest2LoopCounter
 
-#warning Does not seem to test the floating point context register.
 /*-----------------------------------------------------------*/
 
 .section .text
diff --git a/FreeRTOS/Source/include/task.h b/FreeRTOS/Source/include/task.h
index 0377ef95b..672769a90 100644
--- a/FreeRTOS/Source/include/task.h
+++ b/FreeRTOS/Source/include/task.h
@@ -1462,13 +1462,19 @@ void vTaskGetRunTimeStats( char *pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e9
  *	updated.  ulValue is not used and xTaskNotify() always returns pdPASS in
  *	this case.
  *
+ *  pulPreviousNotificationValue -
+ *  Can be used to pass out the subject task's notification value before any
+ *  bits are modified by the notify function.
+ *
  * @return Dependent on the value of eAction.  See the description of the
  * eAction parameter.
  *
  * \defgroup xTaskNotify xTaskNotify
  * \ingroup TaskNotifications
  */
-BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction );
+BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue );
+#define xTaskNotify( xTaskToNotify, ulValue, eAction ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL )
+#define xTaskNotifyAndQuery( xTaskToNotify, ulValue, eAction, pulPreviousNotifyValue ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) )
 
 /**
  * task. h
diff --git a/FreeRTOS/Source/tasks.c b/FreeRTOS/Source/tasks.c
index adf0a16f4..426ee2d59 100644
--- a/FreeRTOS/Source/tasks.c
+++ b/FreeRTOS/Source/tasks.c
@@ -4101,7 +4101,7 @@ TickType_t uxReturn;
 
 #if( configUSE_TASK_NOTIFICATIONS == 1 )
 
-	BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction )
+	BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue )
 	{
 	TCB_t * pxTCB;
 	eNotifyValue eOriginalNotifyState;
@@ -4112,6 +4112,11 @@ TickType_t uxReturn;
 
 		taskENTER_CRITICAL();
 		{
+			if( pulPreviousNotificationValue != NULL )
+			{
+				*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
+			}
+
 			eOriginalNotifyState = pxTCB->eNotifyState;
 
 			pxTCB->eNotifyState = eNotified;
author	rtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>	2015-03-24 15:24:49 +0000
committer	rtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>	2015-03-24 15:24:49 +0000
commit	6a044a9948792ca7c04735a3acc6895155395cea (patch)
tree	b5eeb477555eb4eb3a23998e459e75a26e2b8404
parent	f1eee1f450212c4525b896633b3c501b192877dc (diff)
download	freertos-6a044a9948792ca7c04735a3acc6895155395cea.tar.gz