diff options
| author | richardbarry <richardbarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2> | 2013-09-03 15:26:05 +0000 |
|---|---|---|
| committer | richardbarry <richardbarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2> | 2013-09-03 15:26:05 +0000 |
| commit | ca9bbbfe5ca316604c072def6cec6b2f984e1672 (patch) | |
| tree | a632aca032f3e7d366090edb5b5efe645ea72a86 | |
| parent | 0307b5804dda9d9b6a28cd24196bb7d06fba3e16 (diff) | |
| download | freertos-ca9bbbfe5ca316604c072def6cec6b2f984e1672.tar.gz | |
Update the Keil XMC4500 demo project to include build configurations for the XMC4200 and XMC4400 application boards.
git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2021 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
15 files changed, 5698 insertions, 960 deletions
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/FreeRTOSConfig.h index b3e227122..e1e30d39c 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/FreeRTOSConfig.h @@ -89,7 +89,7 @@ extern uint32_t SystemCoreClock; #define configTICK_RATE_HZ ( ( portTickType ) 1000 )
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 )
-#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 40960 ) )
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 22800 ) )
#define configMAX_TASK_NAME_LEN ( 10 )
#define configUSE_TRACE_FACILITY 1
#define configUSE_16_BIT_TICKS 0
@@ -158,5 +158,39 @@ standard names. */ #define xPortPendSVHandler PendSV_Handler
#define xPortSysTickHandler SysTick_Handler
+
+/* Demo application specific settings. */
+#if defined( PART_XMC4500 )
+ /* Hardware includes. */
+ #include "XMC4500.h"
+ #include "System_XMC4500.h"
+
+ /* Configure pin P3.9 for the LED. */
+ #define configCONFIGURE_LED() ( PORT3->IOCR8 = 0x00008000 )
+ /* To toggle the single LED */
+ #define configTOGGLE_LED() ( PORT3->OMR = 0x02000200 )
+#elif defined( PART_XMC4400 )
+ /* Hardware includes. */
+ #include "XMC4400.h"
+ #include "System_XMC4200.h"
+
+ /* Configure pin P5.2 for the LED. */
+ #define configCONFIGURE_LED() ( PORT5->IOCR0 = 0x00800000 )
+ /* To toggle the single LED */
+ #define configTOGGLE_LED() ( PORT5->OMR = 0x00040004 )
+#elif defined( PART_XMC4200 )
+ /* Hardware includes. */
+ #include "XMC4200.h"
+ #include "System_XMC4200.h"
+
+ /* Configure pin P2.1 for the LED. */
+ #define configCONFIGURE_LED() PORT2->IOCR0 = 0x00008000; PORT2->HWSEL &= ~0x0000000cUL
+ /* To toggle the single LED */
+ #define configTOGGLE_LED() ( PORT2->OMR = 0x00020002 )
+#else
+ #error Part number not specified in project options
+#endif
+
+
#endif /* FREERTOS_CONFIG_H */
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RTOSDemo.uvopt b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RTOSDemo.uvopt index 8f6913c4f..adb4267af 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RTOSDemo.uvopt +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RTOSDemo.uvopt @@ -21,7 +21,7 @@ </DaveTm> <Target> - <TargetName>RTOSDemo</TargetName> + <TargetName>RTOSDemo - XMC4500</TargetName> <ToolsetNumber>0x4</ToolsetNumber> <ToolsetName>ARM-ADS</ToolsetName> <TargetOption> @@ -73,30 +73,40 @@ <OPTFL> <tvExp>1</tvExp> <tvExpOptDlg>0</tvExpOptDlg> - <IsCurrentTarget>1</IsCurrentTarget> + <IsCurrentTarget>0</IsCurrentTarget> </OPTFL> - <CpuCode>0</CpuCode> + <CpuCode>255</CpuCode> <Books> <Book> <Number>0</Number> <Title>Data Sheet</Title> - <Path>DATASHTS\Infineon\comming.pdf</Path> + <Path>DATASHTS\Infineon\XMC4500\xmc4500_ds.pdf</Path> </Book> <Book> <Number>1</Number> <Title>User Manual</Title> - <Path>DATASHTS\Infineon\comming.pdf</Path> + <Path>DATASHTS\Infineon\XMC4500\xmc4500_um.pdf</Path> + </Book> + <Book> + <Number>2</Number> + <Title>Technical Reference Manual</Title> + <Path>datashts\arm\cortex_m4\r0p1\DDI0439C_CORTEX_M4_R0P1_TRM.PDF</Path> + </Book> + <Book> + <Number>3</Number> + <Title>Generic User Guide</Title> + <Path>datashts\arm\cortex_m4\r0p1\DUI0553A_CORTEX_M4_DGUG.PDF</Path> </Book> </Books> <DllOpt> <SimDllName>SARMCM3.DLL</SimDllName> - <SimDllArguments>-MPU</SimDllArguments> - <SimDlgDllName>DARMP1.DLL</SimDlgDllName> - <SimDlgDllArguments>-pLPC1785</SimDlgDllArguments> + <SimDllArguments>-MPU -REMAP</SimDllArguments> + <SimDlgDllName>DCM.DLL</SimDlgDllName> + <SimDlgDllArguments>-pCM4</SimDlgDllArguments> <TargetDllName>SARMCM3.DLL</TargetDllName> <TargetDllArguments>-MPU</TargetDllArguments> - <TargetDlgDllName>TARMP1.DLL</TargetDlgDllName> - <TargetDlgDllArguments>-pLPC1785</TargetDlgDllArguments> + <TargetDlgDllName>TCM.DLL</TargetDlgDllName> + <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments> </DllOpt> <DebugOpt> <uSim>0</uSim> @@ -115,6 +125,7 @@ <tRmem>1</tRmem> <tRfunc>0</tRfunc> <tRbox>1</tRbox> + <tRtrace>0</tRtrace> <sRunDeb>0</sRunDeb> <sLrtime>0</sLrtime> <nTsel>1</nTsel> @@ -139,7 +150,7 @@ <SetRegEntry> <Number>0</Number> <Key>DLGTARM</Key> - <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(350=-1,-1,-1,-1,0)(250=-1,-1,-1,-1,0)(270=-1,-1,-1,-1,0)(314=-1,-1,-1,-1,0)(292=-1,-1,-1,-1,0)(303=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(410=-1,-1,-1,-1,0)(320=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(362=-1,-1,-1,-1,0)(363=-1,-1,-1,-1,0)(364=-1,-1,-1,-1,0)(365=-1,-1,-1,-1,0)(366=-1,-1,-1,-1,0)(367=-1,-1,-1,-1,0)(332=-1,-1,-1,-1,0)(333=-1,-1,-1,-1,0)(334=-1,-1,-1,-1,0)(335=-1,-1,-1,-1,0)(336=-1,-1,-1,-1,0)(337=-1,-1,-1,-1,0)(345=-1,-1,-1,-1,0)(346=-1,-1,-1,-1,0)(390=-1,-1,-1,-1,0)(381=-1,-1,-1,-1,0)(382=-1,-1,-1,-1,0)(383=-1,-1,-1,-1,0)(384=-1,-1,-1,-1,0)(385=-1,-1,-1,-1,0)(197=-1,-1,-1,-1,0)(198=-1,-1,-1,-1,0)(191=-1,-1,-1,-1,0)(192=-1,-1,-1,-1,0)(261=-1,-1,-1,-1,0)(262=-1,-1,-1,-1,0)(263=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(141=-1,-1,-1,-1,0)(142=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(400=-1,-1,-1,-1,0)(370=-1,-1,-1,-1,0)(280=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)</Name> + <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=120,149,354,683,0)(1012=-1,-1,-1,-1,0)</Name> </SetRegEntry> <SetRegEntry> <Number>0</Number> @@ -149,7 +160,7 @@ <SetRegEntry> <Number>0</Number> <Key>DLGUARM</Key> - <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name> + <Name>(105=-1,-1,-1,-1,0)</Name> </SetRegEntry> <SetRegEntry> <Number>0</Number> @@ -159,41 +170,217 @@ <SetRegEntry> <Number>0</Number> <Key>UL2CM3</Key> - <Name>-UM1129BUE -O142 -S9 -C0 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("Unknown JTAG device") -D01(001DB083) -L01(8) -TO16 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD10000000 -FC800 -FN2 -FF0XMC4500 -FS0C000000 -FL0100000 -FF1XMC4500c -FS18000000 -FL1100000</Name> + <Name>-UM0356BUE -O751 -S9 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO16 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FN2 -FC800 -FD20000000 -FF0XMC4500_1024 -FF1XMC4500c_1024 -FL0100000 -FL1100000 -FS0C000000 -FS18000000</Name> </SetRegEntry> </TargetDriverDllRegistry> - <Breakpoint> - <Bp> + <Breakpoint/> + <WatchWindow1> + <Ww> + <count>0</count> + <WinNumber>1</WinNumber> + <ItemText>xTickCount</ItemText> + </Ww> + </WatchWindow1> + <MemoryWindow1> + <Mm> + <WinNumber>1</WinNumber> + <SubType>5</SubType> + <ItemText>0x0C000000</ItemText> + </Mm> + </MemoryWindow1> + <Tracepoint> + <THDelay>0</THDelay> + </Tracepoint> + <DebugFlag> + <trace>0</trace> + <periodic>1</periodic> + <aLwin>1</aLwin> + <aCover>0</aCover> + <aSer1>0</aSer1> + <aSer2>0</aSer2> + <aPa>0</aPa> + <viewmode>1</viewmode> + <vrSel>0</vrSel> + <aSym>0</aSym> + <aTbox>0</aTbox> + <AscS1>0</AscS1> + <AscS2>0</AscS2> + <AscS3>0</AscS3> + <aSer3>0</aSer3> + <eProf>0</eProf> + <aLa>0</aLa> + <aPa1>0</aPa1> + <AscS4>0</AscS4> + <aSer4>0</aSer4> + <StkLoc>0</StkLoc> + <TrcWin>0</TrcWin> + <newCpu>0</newCpu> + <uProt>0</uProt> + </DebugFlag> + <LintExecutable></LintExecutable> + <LintConfigFile></LintConfigFile> + </TargetOption> + </Target> + + <Target> + <TargetName>RTOSDemo - XMC4400</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <CLKADS>12000000</CLKADS> + <OPTTT> + <gFlags>1</gFlags> + <BeepAtEnd>1</BeepAtEnd> + <RunSim>1</RunSim> + <RunTarget>0</RunTarget> + </OPTTT> + <OPTHX> + <HexSelection>1</HexSelection> + <FlashByte>65535</FlashByte> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + </OPTHX> + <OPTLEX> + <PageWidth>79</PageWidth> + <PageLength>66</PageLength> + <TabStop>8</TabStop> + <ListingPath>.\</ListingPath> + </OPTLEX> + <ListingPage> + <CreateCListing>1</CreateCListing> + <CreateAListing>1</CreateAListing> + <CreateLListing>1</CreateLListing> + <CreateIListing>0</CreateIListing> + <AsmCond>1</AsmCond> + <AsmSymb>1</AsmSymb> + <AsmXref>0</AsmXref> + <CCond>1</CCond> + <CCode>0</CCode> + <CListInc>0</CListInc> + <CSymb>0</CSymb> + <LinkerCodeListing>0</LinkerCodeListing> + </ListingPage> + <OPTXL> + <LMap>1</LMap> + <LComments>1</LComments> + <LGenerateSymbols>1</LGenerateSymbols> + <LLibSym>1</LLibSym> + <LLines>1</LLines> + <LLocSym>1</LLocSym> + <LPubSym>1</LPubSym> + <LXref>0</LXref> + <LExpSel>0</LExpSel> + </OPTXL> + <OPTFL> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <IsCurrentTarget>0</IsCurrentTarget> + </OPTFL> + <CpuCode>255</CpuCode> + <Books> + <Book> <Number>0</Number> - <Type>0</Type> - <LineNumber>244</LineNumber> - <EnabledFlag>1</EnabledFlag> - <Address>201327524</Address> - <ByteObject>0</ByteObject> - <ManyObjects>0</ManyObjects> - <SizeOfObject>0</SizeOfObject> - <BreakByAccess>0</BreakByAccess> - <BreakIfRCount>1</BreakIfRCount> - <Filename></Filename> - <ExecCommand></ExecCommand> - <Expression>\\RTOSDemo\RegTest.c\244</Expression> - </Bp> - <Bp> + <Title>Data Sheet</Title> + <Path>DATASHTS\Infineon\XMC4400\xmc4400_ds.pdf</Path> + </Book> + <Book> <Number>1</Number> - <Type>0</Type> - <LineNumber>61</LineNumber> - <EnabledFlag>1</EnabledFlag> - <Address>201327124</Address> - <ByteObject>0</ByteObject> - <ManyObjects>0</ManyObjects> - <SizeOfObject>0</SizeOfObject> - <BreakByAccess>0</BreakByAccess> - <BreakIfRCount>1</BreakIfRCount> - <Filename></Filename> - <ExecCommand></ExecCommand> - <Expression>\\RTOSDemo\RegTest.c\61</Expression> - </Bp> - </Breakpoint> + <Title>User Manual</Title> + <Path>DATASHTS\Infineon\XMC4400\xmc4400_ds.pdf</Path> + </Book> + <Book> + <Number>2</Number> + <Title>Technical Reference Manual</Title> + <Path>datashts\arm\cortex_m4\r0p1\DDI0439C_CORTEX_M4_R0P1_TRM.PDF</Path> + </Book> + <Book> + <Number>3</Number> + <Title>Generic User Guide</Title> + <Path>datashts\arm\cortex_m4\r0p1\DUI0553A_CORTEX_M4_DGUG.PDF</Path> + </Book> + </Books> + <DllOpt> + <SimDllName>SARMCM3.DLL</SimDllName> + <SimDllArguments>-MPU -REMAP</SimDllArguments> + <SimDlgDllName>DCM.DLL</SimDlgDllName> + <SimDlgDllArguments>-pCM4</SimDlgDllArguments> + <TargetDllName>SARMCM3.DLL</TargetDllName> + <TargetDllArguments>-MPU</TargetDllArguments> + <TargetDlgDllName>TCM.DLL</TargetDlgDllName> + <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments> + </DllOpt> + <DebugOpt> + <uSim>0</uSim> + <uTrg>1</uTrg> + <sLdApp>1</sLdApp> + <sGomain>1</sGomain> + <sRbreak>1</sRbreak> + <sRwatch>1</sRwatch> + <sRmem>1</sRmem> + <sRfunc>1</sRfunc> + <sRbox>1</sRbox> + <tLdApp>1</tLdApp> + <tGomain>1</tGomain> + <tRbreak>1</tRbreak> + <tRwatch>1</tRwatch> + <tRmem>1</tRmem> + <tRfunc>0</tRfunc> + <tRbox>1</tRbox> + <tRtrace>0</tRtrace> + <sRunDeb>0</sRunDeb> + <sLrtime>0</sLrtime> + <nTsel>7</nTsel> + <sDll></sDll> + <sDllPa></sDllPa> + <sDlgDll></sDlgDll> + <sDlgPa></sDlgPa> + <sIfile></sIfile> + <tDll></tDll> + <tDllPa></tDllPa> + <tDlgDll></tDlgDll> + <tDlgPa></tDlgPa> + <tIfile></tIfile> + <pMon>Segger\JL2CM3.dll</pMon> + </DebugOpt> + <TargetDriverDllRegistry> + <SetRegEntry> + <Number>0</Number> + <Key>JL2CM3</Key> + <Name>-U591000334 -O78 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8009 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC800 -FN1 -FF0XMC4200_4100_256 -FS0C000000 -FL040000</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGDARM</Key> + <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(350=-1,-1,-1,-1,0)(250=-1,-1,-1,-1,0)(270=-1,-1,-1,-1,0)(314=-1,-1,-1,-1,0)(292=-1,-1,-1,-1,0)(303=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(410=-1,-1,-1,-1,0)(320=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(362=-1,-1,-1,-1,0)(363=-1,-1,-1,-1,0)(364=-1,-1,-1,-1,0)(365=-1,-1,-1,-1,0)(366=-1,-1,-1,-1,0)(367=-1,-1,-1,-1,0)(332=-1,-1,-1,-1,0)(333=-1,-1,-1,-1,0)(334=-1,-1,-1,-1,0)(335=-1,-1,-1,-1,0)(336=-1,-1,-1,-1,0)(337=-1,-1,-1,-1,0)(345=-1,-1,-1,-1,0)(346=-1,-1,-1,-1,0)(390=-1,-1,-1,-1,0)(381=-1,-1,-1,-1,0)(382=-1,-1,-1,-1,0)(383=-1,-1,-1,-1,0)(384=-1,-1,-1,-1,0)(385=-1,-1,-1,-1,0)(197=-1,-1,-1,-1,0)(198=-1,-1,-1,-1,0)(191=-1,-1,-1,-1,0)(192=-1,-1,-1,-1,0)(199=-1,-1,-1,-1,0)(261=-1,-1,-1,-1,0)(262=-1,-1,-1,-1,0)(263=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(141=-1,-1,-1,-1,0)(142=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(400=-1,-1,-1,-1,0)(370=-1,-1,-1,-1,0)(280=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGTARM</Key> + <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMDBGFLAGS</Key> + <Name>-T0</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGUARM</Key> + <Name>/</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>ULP2CM3</Key> + <Name>-UP1048084 -O143 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("Unknown JTAG device") -D01(001DB083) -L01(8) -TO18 -TC10000000 -TP28 -TDX0 -TDD0 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD10000000 -FC800 -FN2 -FF0XMC4500 -FS0C000000 -FL0100000 -FF1XMC4500c -FS18000000 -FL1100000</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>UL2CM3</Key> + <Name> -FN2 -FC800 -FD20000000 -FF0XMC4400_512 -FF1XMC4400c_512 -FL080000 -FL180000 -FS0C000000 -FS18000000</Name> + </SetRegEntry> + </TargetDriverDllRegistry> + <Breakpoint/> <MemoryWindow1> <Mm> <WinNumber>1</WinNumber> @@ -201,6 +388,215 @@ <ItemText>0x0C000000</ItemText> </Mm> </MemoryWindow1> + <Tracepoint> + <THDelay>0</THDelay> + </Tracepoint> + <DebugFlag> + <trace>0</trace> + <periodic>1</periodic> + <aLwin>1</aLwin> + <aCover>0</aCover> + <aSer1>0</aSer1> + <aSer2>0</aSer2> + <aPa>0</aPa> + <viewmode>1</viewmode> + <vrSel>0</vrSel> + <aSym>0</aSym> + <aTbox>0</aTbox> + <AscS1>0</AscS1> + <AscS2>0</AscS2> + <AscS3>0</AscS3> + <aSer3>0</aSer3> + <eProf>0</eProf> + <aLa>0</aLa> + <aPa1>0</aPa1> + <AscS4>0</AscS4> + <aSer4>0</aSer4> + <StkLoc>0</StkLoc> + <TrcWin>0</TrcWin> + <newCpu>0</newCpu> + <uProt>0</uProt> + </DebugFlag> + <LintExecutable></LintExecutable> + <LintConfigFile></LintConfigFile> + <SystemViewers> + <Entry> + <Name>System Viewer\PORT2</Name> + <WinId>35905</WinId> + </Entry> + </SystemViewers> + </TargetOption> + </Target> + + <Target> + <TargetName>RTOSDemo - XMC4200</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <CLKADS>12000000</CLKADS> + <OPTTT> + <gFlags>1</gFlags> + <BeepAtEnd>1</BeepAtEnd> + <RunSim>1</RunSim> + <RunTarget>0</RunTarget> + </OPTTT> + <OPTHX> + <HexSelection>1</HexSelection> + <FlashByte>65535</FlashByte> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + </OPTHX> + <OPTLEX> + <PageWidth>79</PageWidth> + <PageLength>66</PageLength> + <TabStop>8</TabStop> + <ListingPath>.\</ListingPath> + </OPTLEX> + <ListingPage> + <CreateCListing>1</CreateCListing> + <CreateAListing>1</CreateAListing> + <CreateLListing>1</CreateLListing> + <CreateIListing>0</CreateIListing> + <AsmCond>1</AsmCond> + <AsmSymb>1</AsmSymb> + <AsmXref>0</AsmXref> + <CCond>1</CCond> + <CCode>0</CCode> + <CListInc>0</CListInc> + <CSymb>0</CSymb> + <LinkerCodeListing>0</LinkerCodeListing> + </ListingPage> + <OPTXL> + <LMap>1</LMap> + <LComments>1</LComments> + <LGenerateSymbols>1</LGenerateSymbols> + <LLibSym>1</LLibSym> + <LLines>1</LLines> + <LLocSym>1</LLocSym> + <LPubSym>1</LPubSym> + <LXref>0</LXref> + <LExpSel>0</LExpSel> + </OPTXL> + <OPTFL> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <IsCurrentTarget>1</IsCurrentTarget> + </OPTFL> + <CpuCode>255</CpuCode> + <Books> + <Book> + <Number>0</Number> + <Title>Data Sheet</Title> + <Path>DATASHTS\Infineon\XMC4200-4100\XMC4200-4100_ds.pdf</Path> + </Book> + <Book> + <Number>1</Number> + <Title>User Manual</Title> + <Path>DATASHTS\Infineon\XMC4200-4100\XMC4200-4100_ds.pdf</Path> + </Book> + <Book> + <Number>2</Number> + <Title>Technical Reference Manual</Title> + <Path>datashts\arm\cortex_m4\r0p1\DDI0439C_CORTEX_M4_R0P1_TRM.PDF</Path> + </Book> + <Book> + <Number>3</Number> + <Title>Generic User Guide</Title> + <Path>datashts\arm\cortex_m4\r0p1\DUI0553A_CORTEX_M4_DGUG.PDF</Path> + </Book> + </Books> + <DllOpt> + <SimDllName>SARMCM3.DLL</SimDllName> + <SimDllArguments>-MPU -REMAP</SimDllArguments> + <SimDlgDllName>DCM.DLL</SimDlgDllName> + <SimDlgDllArguments>-pCM4</SimDlgDllArguments> + <TargetDllName>SARMCM3.DLL</TargetDllName> + <TargetDllArguments>-MPU</TargetDllArguments> + <TargetDlgDllName>TCM.DLL</TargetDlgDllName> + <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments> + </DllOpt> + <DebugOpt> + <uSim>0</uSim> + <uTrg>1</uTrg> + <sLdApp>1</sLdApp> + <sGomain>1</sGomain> + <sRbreak>1</sRbreak> + <sRwatch>1</sRwatch> + <sRmem>1</sRmem> + <sRfunc>1</sRfunc> + <sRbox>1</sRbox> + <tLdApp>1</tLdApp> + <tGomain>1</tGomain> + <tRbreak>1</tRbreak> + <tRwatch>1</tRwatch> + <tRmem>1</tRmem> + <tRfunc>0</tRfunc> + <tRbox>1</tRbox> + <tRtrace>0</tRtrace> + <sRunDeb>0</sRunDeb> + <sLrtime>0</sLrtime> + <nTsel>7</nTsel> + <sDll></sDll> + <sDllPa></sDllPa> + <sDlgDll></sDlgDll> + <sDlgPa></sDlgPa> + <sIfile></sIfile> + <tDll></tDll> + <tDllPa></tDllPa> + <tDlgDll></tDlgDll> + <tDlgPa></tDlgPa> + <tIfile></tIfile> + <pMon>Segger\JL2CM3.dll</pMon> + </DebugOpt> + <TargetDriverDllRegistry> + <SetRegEntry> + <Number>0</Number> + <Key>JL2CM3</Key> + <Name>-U591000435 -O78 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8009 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC800 -FN1 -FF0XMC4200_4100_256 -FS0C000000 -FL040000</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGDARM</Key> + <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(350=-1,-1,-1,-1,0)(250=-1,-1,-1,-1,0)(270=-1,-1,-1,-1,0)(314=-1,-1,-1,-1,0)(292=-1,-1,-1,-1,0)(303=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(410=-1,-1,-1,-1,0)(320=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(362=-1,-1,-1,-1,0)(363=-1,-1,-1,-1,0)(364=-1,-1,-1,-1,0)(365=-1,-1,-1,-1,0)(366=-1,-1,-1,-1,0)(367=-1,-1,-1,-1,0)(332=-1,-1,-1,-1,0)(333=-1,-1,-1,-1,0)(334=-1,-1,-1,-1,0)(335=-1,-1,-1,-1,0)(336=-1,-1,-1,-1,0)(337=-1,-1,-1,-1,0)(345=-1,-1,-1,-1,0)(346=-1,-1,-1,-1,0)(390=-1,-1,-1,-1,0)(381=-1,-1,-1,-1,0)(382=-1,-1,-1,-1,0)(383=-1,-1,-1,-1,0)(384=-1,-1,-1,-1,0)(385=-1,-1,-1,-1,0)(197=-1,-1,-1,-1,0)(198=-1,-1,-1,-1,0)(191=-1,-1,-1,-1,0)(192=-1,-1,-1,-1,0)(199=-1,-1,-1,-1,0)(261=-1,-1,-1,-1,0)(262=-1,-1,-1,-1,0)(263=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(141=-1,-1,-1,-1,0)(142=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(400=-1,-1,-1,-1,0)(370=-1,-1,-1,-1,0)(280=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGTARM</Key> + <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMDBGFLAGS</Key> + <Name>-T0</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGUARM</Key> + <Name>/</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>ULP2CM3</Key> + <Name>-UP1048084 -O143 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("Unknown JTAG device") -D01(001DB083) -L01(8) -TO18 -TC10000000 -TP28 -TDX0 -TDD0 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD10000000 -FC800 -FN2 -FF0XMC4500 -FS0C000000 -FL0100000 -FF1XMC4500c -FS18000000 -FL1100000</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>UL2CM3</Key> + <Name>-FD20000000 -FC800 -FN2 -FF0XMC4200_4100_256 -FS0C000000 -FL040000 -FF1XMC4200_4100c_256 -FS18000000 -FL140000)</Name> + </SetRegEntry> + </TargetDriverDllRegistry> + <Breakpoint/> + <MemoryWindow1> + <Mm> + <WinNumber>1</WinNumber> + <SubType>5</SubType> + <ItemText>0x0C000000</ItemText> + </Mm> + </MemoryWindow1> + <Tracepoint> + <THDelay>0</THDelay> + </Tracepoint> <DebugFlag> <trace>0</trace> <periodic>1</periodic> @@ -237,19 +633,22 @@ <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> <cbSel>0</cbSel> + <RteFlg>0</RteFlg> <File> <GroupNumber>1</GroupNumber> <FileNumber>1</FileNumber> <FileType>2</FileType> <tvExp>0</tvExp> <Focus>0</Focus> - <ColumnNumber>0</ColumnNumber> + <ColumnNumber>61</ColumnNumber> <tvExpOptDlg>0</tvExpOptDlg> - <TopLine>213</TopLine> - <CurrentLine>213</CurrentLine> + <TopLine>0</TopLine> + <CurrentLine>0</CurrentLine> <bDave2>0</bDave2> <PathWithFileName>.\startup_XMC4500.s</PathWithFileName> <FilenameWithoutPath>startup_XMC4500.s</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> </File> <File> <GroupNumber>1</GroupNumber> @@ -257,101 +656,179 @@ <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> - <ColumnNumber>32</ColumnNumber> + <ColumnNumber>0</ColumnNumber> <tvExpOptDlg>0</tvExpOptDlg> <TopLine>0</TopLine> <CurrentLine>0</CurrentLine> <bDave2>0</bDave2> <PathWithFileName>.\System_XMC4500.c</PathWithFileName> <FilenameWithoutPath>System_XMC4500.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>1</GroupNumber> + <FileNumber>3</FileNumber> + <FileType>2</FileType> + <tvExp>0</tvExp> + <Focus>0</Focus> + <ColumnNumber>0</ColumnNumber> + <tvExpOptDlg>0</tvExpOptDlg> + <TopLine>279</TopLine> + <CurrentLine>288</CurrentLine> + <bDave2>0</bDave2> + <PathWithFileName>.\startup_XMC4200.s</PathWithFileName> + <FilenameWithoutPath>startup_XMC4200.s</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>1</GroupNumber> + <FileNumber>4</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <Focus>0</Focus> + <ColumnNumber>0</ColumnNumber> + <tvExpOptDlg>0</tvExpOptDlg> + <TopLine>0</TopLine> + <CurrentLine>0</CurrentLine> + <bDave2>0</bDave2> + <PathWithFileName>.\system_XMC4200.c</PathWithFileName> + <FilenameWithoutPath>system_XMC4200.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>1</GroupNumber> + <FileNumber>5</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <Focus>0</Focus> + <ColumnNumber>20</ColumnNumber> + <tvExpOptDlg>0</tvExpOptDlg> + <TopLine>0</TopLine> + <CurrentLine>0</CurrentLine> + <bDave2>0</bDave2> + <PathWithFileName>.\system_XMC4400.c</PathWithFileName> + <FilenameWithoutPath>system_XMC4400.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>1</GroupNumber> + <FileNumber>6</FileNumber> + <FileType>2</FileType> + <tvExp>0</tvExp> + <Focus>0</Focus> + <ColumnNumber>0</ColumnNumber> + <tvExpOptDlg>0</tvExpOptDlg> + <TopLine>0</TopLine> + <CurrentLine>0</CurrentLine> + <bDave2>0</bDave2> + <PathWithFileName>.\startup_XMC4400.s</PathWithFileName> + <FilenameWithoutPath>startup_XMC4400.s</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> </File> </Group> <Group> <GroupName>Demo_Source</GroupName> - <tvExp>1</tvExp> + <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> <cbSel>0</cbSel> + <RteFlg>0</RteFlg> <File> <GroupNumber>2</GroupNumber> - <FileNumber>3</FileNumber> + <FileNumber>7</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> - <ColumnNumber>44</ColumnNumber> + <ColumnNumber>0</ColumnNumber> <tvExpOptDlg>0</tvExpOptDlg> <TopLine>64</TopLine> - <CurrentLine>90</CurrentLine> + <CurrentLine>140</CurrentLine> <bDave2>0</bDave2> <PathWithFileName>.\main.c</PathWithFileName> <FilenameWithoutPath>main.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> </File> <File> <GroupNumber>2</GroupNumber> - <FileNumber>4</FileNumber> + <FileNumber>8</FileNumber> <FileType>5</FileType> <tvExp>0</tvExp> <Focus>0</Focus> - <ColumnNumber>47</ColumnNumber> + <ColumnNumber>34</ColumnNumber> <tvExpOptDlg>0</tvExpOptDlg> - <TopLine>0</TopLine> - <CurrentLine>0</CurrentLine> + <TopLine>143</TopLine> + <CurrentLine>187</CurrentLine> <bDave2>0</bDave2> <PathWithFileName>.\FreeRTOSConfig.h</PathWithFileName> <FilenameWithoutPath>FreeRTOSConfig.h</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> </File> <File> <GroupNumber>2</GroupNumber> - <FileNumber>5</FileNumber> + <FileNumber>9</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> <ColumnNumber>0</ColumnNumber> <tvExpOptDlg>0</tvExpOptDlg> - <TopLine>235</TopLine> - <CurrentLine>244</CurrentLine> + <TopLine>0</TopLine> + <CurrentLine>0</CurrentLine> <bDave2>0</bDave2> <PathWithFileName>.\RegTest.c</PathWithFileName> <FilenameWithoutPath>RegTest.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> </File> <File> <GroupNumber>2</GroupNumber> - <FileNumber>6</FileNumber> + <FileNumber>10</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> - <ColumnNumber>0</ColumnNumber> + <ColumnNumber>16</ColumnNumber> <tvExpOptDlg>0</tvExpOptDlg> - <TopLine>50</TopLine> - <CurrentLine>54</CurrentLine> + <TopLine>241</TopLine> + <CurrentLine>274</CurrentLine> <bDave2>0</bDave2> <PathWithFileName>.\main_full.c</PathWithFileName> <FilenameWithoutPath>main_full.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> </File> <File> <GroupNumber>2</GroupNumber> - <FileNumber>7</FileNumber> + <FileNumber>11</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> <ColumnNumber>0</ColumnNumber> <tvExpOptDlg>0</tvExpOptDlg> - <TopLine>53</TopLine> - <CurrentLine>53</CurrentLine> + <TopLine>123</TopLine> + <CurrentLine>141</CurrentLine> <bDave2>0</bDave2> <PathWithFileName>.\main_blinky.c</PathWithFileName> <FilenameWithoutPath>main_blinky.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> </File> </Group> <Group> <GroupName>FreeRTOS_Source</GroupName> - <tvExp>1</tvExp> + <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> <cbSel>0</cbSel> + <RteFlg>0</RteFlg> <File> <GroupNumber>3</GroupNumber> - <FileNumber>8</FileNumber> + <FileNumber>12</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -362,10 +839,12 @@ <bDave2>0</bDave2> <PathWithFileName>..\..\Source\timers.c</PathWithFileName> <FilenameWithoutPath>timers.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> </File> <File> <GroupNumber>3</GroupNumber> - <FileNumber>9</FileNumber> + <FileNumber>13</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -376,24 +855,28 @@ <bDave2>0</bDave2> <PathWithFileName>..\..\Source\list.c</PathWithFileName> <FilenameWithoutPath>list.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> </File> <File> <GroupNumber>3</GroupNumber> - <FileNumber>10</FileNumber> + <FileNumber>14</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> - <ColumnNumber>39</ColumnNumber> + <ColumnNumber>0</ColumnNumber> <tvExpOptDlg>0</tvExpOptDlg> - <TopLine>430</TopLine> - <CurrentLine>438</CurrentLine> + <TopLine>0</TopLine> + <CurrentLine>0</CurrentLine> <bDave2>0</bDave2> <PathWithFileName>..\..\Source\queue.c</PathWithFileName> <FilenameWithoutPath>queue.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> </File> <File> <GroupNumber>3</GroupNumber> - <FileNumber>11</FileNumber> + <FileNumber>15</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -404,10 +887,12 @@ <bDave2>0</bDave2> <PathWithFileName>..\..\Source\tasks.c</PathWithFileName> <FilenameWithoutPath>tasks.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> </File> <File> <GroupNumber>3</GroupNumber> - <FileNumber>12</FileNumber> + <FileNumber>16</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -416,12 +901,14 @@ <TopLine>0</TopLine> <CurrentLine>0</CurrentLine> <bDave2>0</bDave2> - <PathWithFileName>..\..\Source\portable\MemMang\heap_2.c</PathWithFileName> - <FilenameWithoutPath>heap_2.c</FilenameWithoutPath> + <PathWithFileName>..\..\Source\portable\RVDS\ARM_CM4F\port.c</PathWithFileName> + <FilenameWithoutPath>port.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> </File> <File> <GroupNumber>3</GroupNumber> - <FileNumber>13</FileNumber> + <FileNumber>17</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -430,19 +917,22 @@ <TopLine>0</TopLine> <CurrentLine>0</CurrentLine> <bDave2>0</bDave2> - <PathWithFileName>..\..\Source\portable\RVDS\ARM_CM4F\port.c</PathWithFileName> - <FilenameWithoutPath>port.c</FilenameWithoutPath> + <PathWithFileName>..\..\Source\portable\MemMang\heap_4.c</PathWithFileName> + <FilenameWithoutPath>heap_4.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> </File> </Group> <Group> <GroupName>Common_Demo_Source</GroupName> - <tvExp>1</tvExp> + <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> <cbSel>0</cbSel> + <RteFlg>0</RteFlg> <File> <GroupNumber>4</GroupNumber> - <FileNumber>14</FileNumber> + <FileNumber>18</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -453,38 +943,28 @@ <bDave2>0</bDave2> <PathWithFileName>..\Common\Minimal\semtest.c</PathWithFileName> <FilenameWithoutPath>semtest.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> </File> <File> <GroupNumber>4</GroupNumber> - <FileNumber>15</FileNumber> + <FileNumber>19</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> <ColumnNumber>0</ColumnNumber> <tvExpOptDlg>0</tvExpOptDlg> - <TopLine>0</TopLine> - <CurrentLine>0</CurrentLine> + <TopLine>195</TopLine> + <CurrentLine>203</CurrentLine> <bDave2>0</bDave2> <PathWithFileName>..\Common\Minimal\sp_flop.c</PathWithFileName> <FilenameWithoutPath>sp_flop.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> </File> <File> <GroupNumber>4</GroupNumber> - <FileNumber>16</FileNumber> - <FileType>1</FileType> - <tvExp>0</tvExp> - <Focus>0</Focus> - <ColumnNumber>0</ColumnNumber> - <tvExpOptDlg>0</tvExpOptDlg> - <TopLine>0</TopLine> - <CurrentLine>0</CurrentLine> - <bDave2>0</bDave2> - <PathWithFileName>..\Common\Minimal\BlockQ.c</PathWithFileName> - <FilenameWithoutPath>BlockQ.c</FilenameWithoutPath> - </File> - <File> - <GroupNumber>4</GroupNumber> - <FileNumber>17</FileNumber> + <FileNumber>20</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -495,10 +975,12 @@ <bDave2>0</bDave2> <PathWithFileName>..\Common\Minimal\blocktim.c</PathWithFileName> <FilenameWithoutPath>blocktim.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> </File> <File> <GroupNumber>4</GroupNumber> - <FileNumber>18</FileNumber> + <FileNumber>21</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -509,24 +991,12 @@ <bDave2>0</bDave2> <PathWithFileName>..\Common\Minimal\countsem.c</PathWithFileName> <FilenameWithoutPath>countsem.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> </File> <File> <GroupNumber>4</GroupNumber> - <FileNumber>19</FileNumber> - <FileType>1</FileType> - <tvExp>0</tvExp> - <Focus>0</Focus> - <ColumnNumber>0</ColumnNumber> - <tvExpOptDlg>0</tvExpOptDlg> - <TopLine>0</TopLine> - <CurrentLine>0</CurrentLine> - <bDave2>0</bDave2> - <PathWithFileName>..\Common\Minimal\death.c</PathWithFileName> - <FilenameWithoutPath>death.c</FilenameWithoutPath> - </File> - <File> - <GroupNumber>4</GroupNumber> - <FileNumber>20</FileNumber> + <FileNumber>22</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -537,10 +1007,12 @@ <bDave2>0</bDave2> <PathWithFileName>..\Common\Minimal\dynamic.c</PathWithFileName> <FilenameWithoutPath>dynamic.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> </File> <File> <GroupNumber>4</GroupNumber> - <FileNumber>21</FileNumber> + <FileNumber>23</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <Focus>0</Focus> @@ -551,34 +1023,8 @@ <bDave2>0</bDave2> <PathWithFileName>..\Common\Minimal\GenQTest.c</PathWithFileName> <FilenameWithoutPath>GenQTest.c</FilenameWithoutPath> - </File> - <File> - <GroupNumber>4</GroupNumber> - <FileNumber>22</FileNumber> - <FileType>1</FileType> - <tvExp>0</tvExp> - <Focus>0</Focus> - <ColumnNumber>0</ColumnNumber> - <tvExpOptDlg>0</tvExpOptDlg> - <TopLine>0</TopLine> - <CurrentLine>0</CurrentLine> - <bDave2>0</bDave2> - <PathWithFileName>..\Common\Minimal\integer.c</PathWithFileName> - <FilenameWithoutPath>integer.c</FilenameWithoutPath> - </File> - <File> - <GroupNumber>4</GroupNumber> - <FileNumber>23</FileNumber> - <FileType>1</FileType> - <tvExp>0</tvExp> - <Focus>0</Focus> - <ColumnNumber>0</ColumnNumber> - <tvExpOptDlg>0</tvExpOptDlg> - <TopLine>0</TopLine> - <CurrentLine>0</CurrentLine> - <bDave2>0</bDave2> - <PathWithFileName>..\Common\Minimal\PollQ.c</PathWithFileName> - <FilenameWithoutPath>PollQ.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> </File> <File> <GroupNumber>4</GroupNumber> @@ -593,36 +1039,9 @@ <bDave2>0</bDave2> <PathWithFileName>..\Common\Minimal\recmutex.c</PathWithFileName> <FilenameWithoutPath>recmutex.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> </File> </Group> - <MDIGroups> - <Orientation>1</Orientation> - <ActiveMDIGroup>0</ActiveMDIGroup> - <MDIGroup> - <Size>100</Size> - <ActiveTab>2</ActiveTab> - <Documents> - <Doc> - <Name>.\main_blinky.c</Name> - <ColumnNumber>0</ColumnNumber> - <TopLine>53</TopLine> - <CurrentLine>53</CurrentLine> - </Doc> - <Doc> - <Name>.\main_full.c</Name> - <ColumnNumber>0</ColumnNumber> - <TopLine>50</TopLine> - <CurrentLine>54</CurrentLine> - </Doc> - <Doc> - <Name>.\main.c</Name> - <ColumnNumber>44</ColumnNumber> - <TopLine>64</TopLine> - <CurrentLine>90</CurrentLine> - </Doc> - </Documents> - </MDIGroup> - </MDIGroups> - </ProjectOpt> diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RTOSDemo.uvproj b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RTOSDemo.uvproj index 8032729fd..a9854674f 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RTOSDemo.uvproj +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RTOSDemo.uvproj @@ -7,19 +7,19 @@ <Targets> <Target> - <TargetName>RTOSDemo</TargetName> + <TargetName>RTOSDemo - XMC4500</TargetName> <ToolsetNumber>0x4</ToolsetNumber> <ToolsetName>ARM-ADS</ToolsetName> <TargetOption> <TargetCommonOption> - <Device>XMC4500</Device> + <Device>XMC4500-1024</Device> <Vendor>Infineon</Vendor> - <Cpu>IRAM(0x10000000-0x1000FFFF) IRAM2(0x20000000-0x2000FFFF) IROM(0x0C000000-0x0C0FFFFF) IROM2(0x08000000-0x080FFFFF) CLOCK(12000000) CPUTYPE("Cortex-M4")</Cpu> + <Cpu>IRAM(0x20000000-0x2000FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x0C000000-0x0C0FFFFF) IROM2(0x08000000-0x080FFFFF) CLOCK(12000000) CPUTYPE("Cortex-M4") FPU2</Cpu> <FlashUtilSpec></FlashUtilSpec> <StartupFile>"STARTUP\Infineon\XMC4500\startup_XMC4500.s" ("Infineon XMC4500 Startup Code")</StartupFile> - <FlashDriverDll>UL2CM3(-FD10000000 -FC800 -FN2 -FF0XMC4500 -FS0C000000 -FL0100000 -FF1XMC4500c -FS18000000 -FL1100000)</FlashDriverDll> - <DeviceId>0</DeviceId> - <RegisterFile>XMC4500.H</RegisterFile> + <FlashDriverDll>UL2CM3(-FD20000000 -FC800 -FN2 -FF0XMC4500_1024 -FS0C000000 -FL0100000 -FF1XMC4500c_1024 -FS18000000 -FL1100000)</FlashDriverDll> + <DeviceId>6264</DeviceId> + <RegisterFile>XMC4500.h</RegisterFile> <MemoryEnv></MemoryEnv> <Cmp></Cmp> <Asm></Asm> @@ -61,6 +61,8 @@ <UserProg2Name></UserProg2Name> <UserProg1Dos16Mode>0</UserProg1Dos16Mode> <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopU1X>0</nStopU1X> + <nStopU2X>0</nStopU2X> </BeforeCompile> <BeforeMake> <RunUserProg1>0</RunUserProg1> @@ -98,13 +100,13 @@ </CommonProperty> <DllOption> <SimDllName>SARMCM3.DLL</SimDllName> - <SimDllArguments>-MPU</SimDllArguments> - <SimDlgDll>DARMP1.DLL</SimDlgDll> - <SimDlgDllArguments>-pLPC1785</SimDlgDllArguments> + <SimDllArguments>-MPU -REMAP</SimDllArguments> + <SimDlgDll>DCM.DLL</SimDlgDll> + <SimDlgDllArguments>-pCM4</SimDlgDllArguments> <TargetDllName>SARMCM3.DLL</TargetDllName> <TargetDllArguments>-MPU</TargetDllArguments> - <TargetDlgDll>TARMP1.DLL</TargetDlgDll> - <TargetDlgDllArguments>-pLPC1785</TargetDlgDllArguments> + <TargetDlgDll>TCM.DLL</TargetDlgDll> + <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments> </DllOption> <DebugOption> <OPTHX> @@ -134,6 +136,7 @@ <RestoreMemoryDisplay>1</RestoreMemoryDisplay> <RestoreFunctions>0</RestoreFunctions> <RestoreToolbox>1</RestoreToolbox> + <RestoreTracepoints>0</RestoreTracepoints> </Target> <RunDebugAfterBuild>0</RunDebugAfterBuild> <TargetSelection>1</TargetSelection> @@ -162,8 +165,9 @@ <Capability>1</Capability> <DriverSelection>4096</DriverSelection> </Flash1> + <bUseTDR>1</bUseTDR> <Flash2>BIN\UL2CM3.DLL</Flash2> - <Flash3>"" ()</Flash3> + <Flash3></Flash3> <Flash4></Flash4> </Utilities> <TargetArmAds> @@ -204,7 +208,7 @@ <hadIRAM>1</hadIRAM> <hadXRAM>0</hadXRAM> <uocXRam>0</uocXRam> - <RvdsVP>0</RvdsVP> + <RvdsVP>2</RvdsVP> <hadIRAM2>1</hadIRAM2> <hadIROM2>1</hadIROM2> <StupSel>8</StupSel> @@ -263,7 +267,7 @@ </Ocm6> <IRAM> <Type>0</Type> - <StartAddress>0x10000000</StartAddress> + <StartAddress>0x20000000</StartAddress> <Size>0x10000</Size> </IRAM> <IROM> @@ -318,12 +322,12 @@ </OCR_RVCT8> <OCR_RVCT9> <Type>0</Type> - <StartAddress>0x10000000</StartAddress> + <StartAddress>0x20000000</StartAddress> <Size>0x10000</Size> </OCR_RVCT9> <OCR_RVCT10> <Type>0</Type> - <StartAddress>0x20000000</StartAddress> + <StartAddress>0x10000000</StartAddress> <Size>0x10000</Size> </OCR_RVCT10> </OnChipMemories> @@ -342,6 +346,7 @@ <Rwpi>0</Rwpi> <wLevel>0</wLevel> <uThumb>0</uThumb> + <uSurpInc>0</uSurpInc> <VariousControls> <MiscControls>--cpu Cortex-M4.fp --no_allow_fpreg_for_nonfpdata</MiscControls> <Define>rvkdm PART_XMC4500</Define> @@ -357,6 +362,7 @@ <SplitLS>0</SplitLS> <SwStkChk>0</SwStkChk> <NoWarn>0</NoWarn> + <uSurpInc>0</uSurpInc> <VariousControls> <MiscControls></MiscControls> <Define></Define> @@ -396,6 +402,176 @@ <FileType>1</FileType> <FilePath>.\System_XMC4500.c</FilePath> </File> + <File> + <FileName>startup_XMC4200.s</FileName> + <FileType>2</FileType> + <FilePath>.\startup_XMC4200.s</FilePath> + <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>0</IncludeInBuild> + <AlwaysBuild>2</AlwaysBuild> + <GenerateAssemblyFile>2</GenerateAssemblyFile> + <AssembleAssemblyFile>2</AssembleAssemblyFile> + <PublicsOnly>2</PublicsOnly> + <StopOnExitCode>11</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + </CommonProperty> + <FileArmAds> + <Aads> + <interw>2</interw> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <thumb>2</thumb> + <SplitLS>2</SplitLS> + <SwStkChk>2</SwStkChk> + <NoWarn>2</NoWarn> + <uSurpInc>2</uSurpInc> + <VariousControls> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Aads> + </FileArmAds> + </FileOption> + </File> + <File> + <FileName>system_XMC4200.c</FileName> + <FileType>1</FileType> + <FilePath>.\system_XMC4200.c</FilePath> + <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>0</IncludeInBuild> + <AlwaysBuild>2</AlwaysBuild> + <GenerateAssemblyFile>2</GenerateAssemblyFile> + <AssembleAssemblyFile>2</AssembleAssemblyFile> + <PublicsOnly>2</PublicsOnly> + <StopOnExitCode>11</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + </CommonProperty> + <FileArmAds> + <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <VariousControls> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Cads> + </FileArmAds> + </FileOption> + </File> + <File> + <FileName>system_XMC4400.c</FileName> + <FileType>1</FileType> + <FilePath>.\system_XMC4400.c</FilePath> + <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>0</IncludeInBuild> + <AlwaysBuild>2</AlwaysBuild> + <GenerateAssemblyFile>2</GenerateAssemblyFile> + <AssembleAssemblyFile>2</AssembleAssemblyFile> + <PublicsOnly>2</PublicsOnly> + <StopOnExitCode>11</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + </CommonProperty> + <FileArmAds> + <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <VariousControls> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Cads> + </FileArmAds> + </FileOption> + </File> + <File> + <FileName>startup_XMC4400.s</FileName> + <FileType>2</FileType> + <FilePath>.\startup_XMC4400.s</FilePath> + <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>0</IncludeInBuild> + <AlwaysBuild>2</AlwaysBuild> + <GenerateAssemblyFile>2</GenerateAssemblyFile> + <AssembleAssemblyFile>2</AssembleAssemblyFile> + <PublicsOnly>2</PublicsOnly> + <StopOnExitCode>11</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + </CommonProperty> + <FileArmAds> + <Aads> + <interw>2</interw> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <thumb>2</thumb> + <SplitLS>2</SplitLS> + <SwStkChk>2</SwStkChk> + <NoWarn>2</NoWarn> + <uSurpInc>2</uSurpInc> + <VariousControls> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Aads> + </FileArmAds> + </FileOption> + </File> </Files> </Group> <Group> @@ -452,14 +628,14 @@ <FilePath>..\..\Source\tasks.c</FilePath> </File> <File> - <FileName>heap_2.c</FileName> + <FileName>port.c</FileName> <FileType>1</FileType> - <FilePath>..\..\Source\portable\MemMang\heap_2.c</FilePath> + <FilePath>..\..\Source\portable\RVDS\ARM_CM4F\port.c</FilePath> </File> <File> - <FileName>port.c</FileName> + <FileName>heap_4.c</FileName> <FileType>1</FileType> - <FilePath>..\..\Source\portable\RVDS\ARM_CM4F\port.c</FilePath> + <FilePath>..\..\Source\portable\MemMang\heap_4.c</FilePath> </File> </Files> </Group> @@ -477,11 +653,6 @@ <FilePath>..\Common\Minimal\sp_flop.c</FilePath> </File> <File> - <FileName>BlockQ.c</FileName> - <FileType>1</FileType> - <FilePath>..\Common\Minimal\BlockQ.c</FilePath> - </File> - <File> <FileName>blocktim.c</FileName> <FileType>1</FileType> <FilePath>..\Common\Minimal\blocktim.c</FilePath> @@ -492,9 +663,679 @@ <FilePath>..\Common\Minimal\countsem.c</FilePath> </File> <File> - <FileName>death.c</FileName> + <FileName>dynamic.c</FileName> + <FileType>1</FileType> + <FilePath>..\Common\Minimal\dynamic.c</FilePath> + </File> + <File> + <FileName>GenQTest.c</FileName> + <FileType>1</FileType> + <FilePath>..\Common\Minimal\GenQTest.c</FilePath> + </File> + <File> + <FileName>recmutex.c</FileName> + <FileType>1</FileType> + <FilePath>..\Common\Minimal\recmutex.c</FilePath> + </File> + </Files> + </Group> + </Groups> + </Target> + <Target> + <TargetName>RTOSDemo - XMC4400</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <TargetCommonOption> + <Device>XMC4400-512</Device> + <Vendor>Infineon</Vendor> + <Cpu>IRAM(0x20000000-0x20007FFF) IRAM2(0x1FFFC000-0x1FFFFFFF) IROM(0x0C000000-0x0C07FFFF) IROM2(0x08000000-0x0807FFFF) CLOCK(12000000) CPUTYPE("Cortex-M4") FPU2</Cpu> + <FlashUtilSpec></FlashUtilSpec> + <StartupFile>"STARTUP\Infineon\XMC4400\startup_XMC4400.s" ("Infineon XMC4400 Startup Code")</StartupFile> + <FlashDriverDll>UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN2 -FF0XMC4400_512 -FS0C000000 -FL080000 -FF1XMC4400c_512 -FS18000000 -FL180000)</FlashDriverDll> + <DeviceId>6644</DeviceId> + <RegisterFile>XMC4400.h</RegisterFile> + <MemoryEnv></MemoryEnv> + <Cmp></Cmp> + <Asm></Asm> + <Linker></Linker> + <OHString></OHString> + <InfinionOptionDll></InfinionOptionDll> + <SLE66CMisc></SLE66CMisc> + <SLE66AMisc></SLE66AMisc> + <SLE66LinkerMisc></SLE66LinkerMisc> + <SFDFile>SFD\Infineon\XMC4400\xmc4400.SFR</SFDFile> + <UseEnv>0</UseEnv> + <BinPath></BinPath> + <IncludePath></IncludePath> + <LibPath></LibPath> + <RegisterFilePath>Infineon\XMC4400\</RegisterFilePath> + <DBRegisterFilePath>Infineon\XMC4400\</DBRegisterFilePath> + <TargetStatus> + <Error>0</Error> + <ExitCodeStop>0</ExitCodeStop> + <ButtonStop>0</ButtonStop> + <NotGenerated>0</NotGenerated> + <InvalidFlash>1</InvalidFlash> + </TargetStatus> + <OutputDirectory>.\Flash\</OutputDirectory> + <OutputName>RTOSDemo</OutputName> + <CreateExecutable>1</CreateExecutable> + <CreateLib>0</CreateLib> + <CreateHexFile>0</CreateHexFile> + <DebugInformation>1</DebugInformation> + <BrowseInformation>1</BrowseInformation> + <ListingPath>.\</ListingPath> + <HexFormatSelection>1</HexFormatSelection> + <Merge32K>0</Merge32K> + <CreateBatchFile>0</CreateBatchFile> + <BeforeCompile> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopU1X>0</nStopU1X> + <nStopU2X>0</nStopU2X> + </BeforeCompile> + <BeforeMake> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + </BeforeMake> + <AfterMake> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + </AfterMake> + <SelectedForBatchBuild>0</SelectedForBatchBuild> + <SVCSIdString></SVCSIdString> + </TargetCommonOption> + <CommonProperty> + <UseCPPCompiler>0</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + </CommonProperty> + <DllOption> + <SimDllName>SARMCM3.DLL</SimDllName> + <SimDllArguments>-MPU -REMAP</SimDllArguments> + <SimDlgDll>DCM.DLL</SimDlgDll> + <SimDlgDllArguments>-pCM4</SimDlgDllArguments> + <TargetDllName>SARMCM3.DLL</TargetDllName> + <TargetDllArguments>-MPU</TargetDllArguments> + <TargetDlgDll>TCM.DLL</TargetDlgDll> + <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments> + </DllOption> + <DebugOption> + <OPTHX> + <HexSelection>1</HexSelection> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + <Oh166RecLen>16</Oh166RecLen> + </OPTHX> + <Simulator> + <UseSimulator>0</UseSimulator> + <LoadApplicationAtStartup>1</LoadApplicationAtStartup> + <RunToMain>1</RunToMain> + <RestoreBreakpoints>1</RestoreBreakpoints> + <RestoreWatchpoints>1</RestoreWatchpoints> + <RestoreMemoryDisplay>1</RestoreMemoryDisplay> + <RestoreFunctions>1</RestoreFunctions> + <RestoreToolbox>1</RestoreToolbox> + <LimitSpeedToRealTime>0</LimitSpeedToRealTime> + </Simulator> + <Target> + <UseTarget>1</UseTarget> + <LoadApplicationAtStartup>1</LoadApplicationAtStartup> + <RunToMain>1</RunToMain> + <RestoreBreakpoints>1</RestoreBreakpoints> + <RestoreWatchpoints>1</RestoreWatchpoints> + <RestoreMemoryDisplay>1</RestoreMemoryDisplay> + <RestoreFunctions>0</RestoreFunctions> + <RestoreToolbox>1</RestoreToolbox> + <RestoreTracepoints>0</RestoreTracepoints> + </Target> + <RunDebugAfterBuild>0</RunDebugAfterBuild> + <TargetSelection>7</TargetSelection> + <SimDlls> + <CpuDll></CpuDll> + <CpuDllArguments></CpuDllArguments> + <PeripheralDll></PeripheralDll> + <PeripheralDllArguments></PeripheralDllArguments> + <InitializationFile></InitializationFile> + </SimDlls> + <TargetDlls> + <CpuDll></CpuDll> + <CpuDllArguments></CpuDllArguments> + <PeripheralDll></PeripheralDll> + <PeripheralDllArguments></PeripheralDllArguments> + <InitializationFile></InitializationFile> + <Driver>Segger\JL2CM3.dll</Driver> + </TargetDlls> + </DebugOption> + <Utilities> + <Flash1> + <UseTargetDll>1</UseTargetDll> + <UseExternalTool>0</UseExternalTool> + <RunIndependent>0</RunIndependent> + <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> + <Capability>1</Capability> + <DriverSelection>4096</DriverSelection> + </Flash1> + <bUseTDR>1</bUseTDR> + <Flash2>BIN\UL2CM3.DLL</Flash2> + <Flash3></Flash3> + <Flash4></Flash4> + </Utilities> + <TargetArmAds> + <ArmAdsMisc> + <GenerateListings>0</GenerateListings> + <asHll>1</asHll> + <asAsm>1</asAsm> + <asMacX>1</asMacX> + <asSyms>1</asSyms> + <asFals>1</asFals> + <asDbgD>1</asDbgD> + <asForm>1</asForm> + <ldLst>0</ldLst> + <ldmm>1</ldmm> + <ldXref>1</ldXref> + <BigEnd>0</BigEnd> + <AdsALst>1</AdsALst> + <AdsACrf>1</AdsACrf> + <AdsANop>0</AdsANop> + <AdsANot>0</AdsANot> + <AdsLLst>1</AdsLLst> + <AdsLmap>1</AdsLmap> + <AdsLcgr>1</AdsLcgr> + <AdsLsym>1</AdsLsym> + <AdsLszi>1</AdsLszi> + <AdsLtoi>1</AdsLtoi> + <AdsLsun>1</AdsLsun> + <AdsLven>1</AdsLven> + <AdsLsxf>1</AdsLsxf> + <RvctClst>0</RvctClst> + <GenPPlst>0</GenPPlst> + <AdsCpuType>"Cortex-M4"</AdsCpuType> + <RvctDeviceName></RvctDeviceName> + <mOS>0</mOS> + <uocRom>0</uocRom> + <uocRam>0</uocRam> + <hadIROM>1</hadIROM> + <hadIRAM>1</hadIRAM> + <hadXRAM>0</hadXRAM> + <uocXRam>0</uocXRam> + <RvdsVP>2</RvdsVP> + <hadIRAM2>1</hadIRAM2> + <hadIROM2>1</hadIROM2> + <StupSel>8</StupSel> + <useUlib>1</useUlib> + <EndSel>0</EndSel> + <uLtcg>0</uLtcg> + <RoSelD>3</RoSelD> + <RwSelD>3</RwSelD> + <CodeSel>0</CodeSel> + <OptFeed>0</OptFeed> + <NoZi1>0</NoZi1> + <NoZi2>0</NoZi2> + <NoZi3>0</NoZi3> + <NoZi4>0</NoZi4> + <NoZi5>0</NoZi5> + <Ro1Chk>0</Ro1Chk> + <Ro2Chk>0</Ro2Chk> + <Ro3Chk>0</Ro3Chk> + <Ir1Chk>1</Ir1Chk> + <Ir2Chk>0</Ir2Chk> + <Ra1Chk>0</Ra1Chk> + <Ra2Chk>0</Ra2Chk> + <Ra3Chk>0</Ra3Chk> + <Im1Chk>1</Im1Chk> + <Im2Chk>0</Im2Chk> + <OnChipMemories> + <Ocm1> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm1> + <Ocm2> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm2> + <Ocm3> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm3> + <Ocm4> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm4> + <Ocm5> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm5> + <Ocm6> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm6> + <IRAM> + <Type>0</Type> + <StartAddress>0x20000000</StartAddress> + <Size>0x8000</Size> + </IRAM> + <IROM> + <Type>1</Type> + <StartAddress>0xc000000</StartAddress> + <Size>0x80000</Size> + </IROM> + <XRAM> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </XRAM> + <OCR_RVCT1> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT1> + <OCR_RVCT2> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT2> + <OCR_RVCT3> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT3> + <OCR_RVCT4> + <Type>1</Type> + <StartAddress>0xc000000</StartAddress> + <Size>0x80000</Size> + </OCR_RVCT4> + <OCR_RVCT5> + <Type>1</Type> + <StartAddress>0x8000000</StartAddress> + <Size>0x80000</Size> + </OCR_RVCT5> + <OCR_RVCT6> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT6> + <OCR_RVCT7> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT7> + <OCR_RVCT8> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT8> + <OCR_RVCT9> + <Type>0</Type> + <StartAddress>0x20000000</StartAddress> + <Size>0x8000</Size> + </OCR_RVCT9> + <OCR_RVCT10> + <Type>0</Type> + <StartAddress>0x1fffc000</StartAddress> + <Size>0x4000</Size> + </OCR_RVCT10> + </OnChipMemories> + <RvctStartVector></RvctStartVector> + </ArmAdsMisc> + <Cads> + <interw>1</interw> + <Optim>1</Optim> + <oTime>0</oTime> + <SplitLS>0</SplitLS> + <OneElfS>0</OneElfS> + <Strict>0</Strict> + <EnumInt>0</EnumInt> + <PlainCh>0</PlainCh> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <wLevel>0</wLevel> + <uThumb>0</uThumb> + <uSurpInc>0</uSurpInc> + <VariousControls> + <MiscControls>--cpu Cortex-M4.fp --no_allow_fpreg_for_nonfpdata</MiscControls> + <Define>rvkdm PART_XMC4400</Define> + <Undefine></Undefine> + <IncludePath>..\CORTEX_M4F_Infineon_XMC4500_Keil;..\..\Source\include;..\..\Source\portable\RVDS\ARM_CM4F;..\Common\include</IncludePath> + </VariousControls> + </Cads> + <Aads> + <interw>1</interw> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <thumb>0</thumb> + <SplitLS>0</SplitLS> + <SwStkChk>0</SwStkChk> + <NoWarn>0</NoWarn> + <uSurpInc>0</uSurpInc> + <VariousControls> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Aads> + <LDads> + <umfTarg>1</umfTarg> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <noStLib>0</noStLib> + <RepFail>1</RepFail> + <useFile>0</useFile> + <TextAddressRange>0x0C000000</TextAddressRange> + <DataAddressRange>0x10000000</DataAddressRange> + <ScatterFile></ScatterFile> + <IncludeLibs></IncludeLibs> + <IncludeLibsPath></IncludeLibsPath> + <Misc>--entry=Reset_Handler</Misc> + <LinkerInputFile></LinkerInputFile> + <DisabledWarnings></DisabledWarnings> + </LDads> + </TargetArmAds> + </TargetOption> + <Groups> + <Group> + <GroupName>Startup</GroupName> + <Files> + <File> + <FileName>startup_XMC4500.s</FileName> + <FileType>2</FileType> + <FilePath>.\startup_XMC4500.s</FilePath> + <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>0</IncludeInBuild> + <AlwaysBuild>2</AlwaysBuild> + <GenerateAssemblyFile>2</GenerateAssemblyFile> + <AssembleAssemblyFile>2</AssembleAssemblyFile> + <PublicsOnly>2</PublicsOnly> + <StopOnExitCode>11</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + </CommonProperty> + <FileArmAds> + <Aads> + <interw>2</interw> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <thumb>2</thumb> + <SplitLS>2</SplitLS> + <SwStkChk>2</SwStkChk> + <NoWarn>2</NoWarn> + <uSurpInc>2</uSurpInc> + <VariousControls> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Aads> + </FileArmAds> + </FileOption> + </File> + <File> + <FileName>System_XMC4500.c</FileName> + <FileType>1</FileType> + <FilePath>.\System_XMC4500.c</FilePath> + <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>0</IncludeInBuild> + <AlwaysBuild>2</AlwaysBuild> + <GenerateAssemblyFile>2</GenerateAssemblyFile> + <AssembleAssemblyFile>2</AssembleAssemblyFile> + <PublicsOnly>2</PublicsOnly> + <StopOnExitCode>11</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + </CommonProperty> + <FileArmAds> + <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <VariousControls> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Cads> + </FileArmAds> + </FileOption> + </File> + <File> + <FileName>startup_XMC4200.s</FileName> + <FileType>2</FileType> + <FilePath>.\startup_XMC4200.s</FilePath> + <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>0</IncludeInBuild> + <AlwaysBuild>2</AlwaysBuild> + <GenerateAssemblyFile>2</GenerateAssemblyFile> + <AssembleAssemblyFile>2</AssembleAssemblyFile> + <PublicsOnly>2</PublicsOnly> + <StopOnExitCode>11</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + </CommonProperty> + <FileArmAds> + <Aads> + <interw>2</interw> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <thumb>2</thumb> + <SplitLS>2</SplitLS> + <SwStkChk>2</SwStkChk> + <NoWarn>2</NoWarn> + <uSurpInc>2</uSurpInc> + <VariousControls> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Aads> + </FileArmAds> + </FileOption> + </File> + <File> + <FileName>system_XMC4200.c</FileName> + <FileType>1</FileType> + <FilePath>.\system_XMC4200.c</FilePath> + <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>0</IncludeInBuild> + <AlwaysBuild>2</AlwaysBuild> + <GenerateAssemblyFile>2</GenerateAssemblyFile> + <AssembleAssemblyFile>2</AssembleAssemblyFile> + <PublicsOnly>2</PublicsOnly> + <StopOnExitCode>11</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + </CommonProperty> + <FileArmAds> + <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <VariousControls> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Cads> + </FileArmAds> + </FileOption> + </File> + <File> + <FileName>system_XMC4400.c</FileName> + <FileType>1</FileType> + <FilePath>.\system_XMC4400.c</FilePath> + </File> + <File> + <FileName>startup_XMC4400.s</FileName> + <FileType>2</FileType> + <FilePath>.\startup_XMC4400.s</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>Demo_Source</GroupName> + <Files> + <File> + <FileName>main.c</FileName> + <FileType>1</FileType> + <FilePath>.\main.c</FilePath> + </File> + <File> + <FileName>FreeRTOSConfig.h</FileName> + <FileType>5</FileType> + <FilePath>.\FreeRTOSConfig.h</FilePath> + </File> + <File> + <FileName>RegTest.c</FileName> + <FileType>1</FileType> + <FilePath>.\RegTest.c</FilePath> + </File> + <File> + <FileName>main_full.c</FileName> + <FileType>1</FileType> + <FilePath>.\main_full.c</FilePath> + </File> + <File> + <FileName>main_blinky.c</FileName> + <FileType>1</FileType> + <FilePath>.\main_blinky.c</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>FreeRTOS_Source</GroupName> + <Files> + <File> + <FileName>timers.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\Source\timers.c</FilePath> + </File> + <File> + <FileName>list.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\Source\list.c</FilePath> + </File> + <File> + <FileName>queue.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\Source\queue.c</FilePath> + </File> + <File> + <FileName>tasks.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\Source\tasks.c</FilePath> + </File> + <File> + <FileName>port.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\Source\portable\RVDS\ARM_CM4F\port.c</FilePath> + </File> + <File> + <FileName>heap_4.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\Source\portable\MemMang\heap_4.c</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>Common_Demo_Source</GroupName> + <Files> + <File> + <FileName>semtest.c</FileName> + <FileType>1</FileType> + <FilePath>..\Common\Minimal\semtest.c</FilePath> + </File> + <File> + <FileName>sp_flop.c</FileName> + <FileType>1</FileType> + <FilePath>..\Common\Minimal\sp_flop.c</FilePath> + </File> + <File> + <FileName>blocktim.c</FileName> + <FileType>1</FileType> + <FilePath>..\Common\Minimal\blocktim.c</FilePath> + </File> + <File> + <FileName>countsem.c</FileName> <FileType>1</FileType> - <FilePath>..\Common\Minimal\death.c</FilePath> + <FilePath>..\Common\Minimal\countsem.c</FilePath> </File> <File> <FileName>dynamic.c</FileName> @@ -507,14 +1348,679 @@ <FilePath>..\Common\Minimal\GenQTest.c</FilePath> </File> <File> - <FileName>integer.c</FileName> + <FileName>recmutex.c</FileName> <FileType>1</FileType> - <FilePath>..\Common\Minimal\integer.c</FilePath> + <FilePath>..\Common\Minimal\recmutex.c</FilePath> + </File> + </Files> + </Group> + </Groups> + </Target> + <Target> + <TargetName>RTOSDemo - XMC4200</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <TargetCommonOption> + <Device>XMC4200-256</Device> + <Vendor>Infineon</Vendor> + <Cpu>IRAM(0x20000000-0x20005FFF) IRAM2(0x1FFFE000-0x1FFFFFFF) IROM(0x0C000000-0x0C03FFFF) IROM2(0x08000000-0x0803FFFF) CLOCK(12000000) CPUTYPE("Cortex-M4") FPU2</Cpu> + <FlashUtilSpec></FlashUtilSpec> + <StartupFile>"STARTUP\Infineon\XMC4200-4100\startup_XMC4200.s" ("Infineon XMC4200/4100 Startup Code")</StartupFile> + <FlashDriverDll>UL2CM3(-FD20000000 -FC800 -FN2 -FF0XMC4200_4100_256 -FS0C000000 -FL040000 -FF1XMC4200_4100c_256 -FS18000000 -FL140000)</FlashDriverDll> + <DeviceId>6705</DeviceId> + <RegisterFile>XMC4200.h</RegisterFile> + <MemoryEnv></MemoryEnv> + <Cmp></Cmp> + <Asm></Asm> + <Linker></Linker> + <OHString></OHString> + <InfinionOptionDll></InfinionOptionDll> + <SLE66CMisc></SLE66CMisc> + <SLE66AMisc></SLE66AMisc> + <SLE66LinkerMisc></SLE66LinkerMisc> + <SFDFile>SFD\Infineon\XMC4200-4100\xmc4200.SFR</SFDFile> + <UseEnv>0</UseEnv> + <BinPath></BinPath> + <IncludePath></IncludePath> + <LibPath></LibPath> + <RegisterFilePath>Infineon\XMC4200-4100\</RegisterFilePath> + <DBRegisterFilePath>Infineon\XMC4200-4100\</DBRegisterFilePath> + <TargetStatus> + <Error>0</Error> + <ExitCodeStop>0</ExitCodeStop> + <ButtonStop>0</ButtonStop> + <NotGenerated>0</NotGenerated> + <InvalidFlash>1</InvalidFlash> + </TargetStatus> + <OutputDirectory>.\Flash\</OutputDirectory> + <OutputName>RTOSDemo</OutputName> + <CreateExecutable>1</CreateExecutable> + <CreateLib>0</CreateLib> + <CreateHexFile>0</CreateHexFile> + <DebugInformation>1</DebugInformation> + <BrowseInformation>1</BrowseInformation> + <ListingPath>.\</ListingPath> + <HexFormatSelection>1</HexFormatSelection> + <Merge32K>0</Merge32K> + <CreateBatchFile>0</CreateBatchFile> + <BeforeCompile> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopU1X>0</nStopU1X> + <nStopU2X>0</nStopU2X> + </BeforeCompile> + <BeforeMake> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + </BeforeMake> + <AfterMake> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + </AfterMake> + <SelectedForBatchBuild>0</SelectedForBatchBuild> + <SVCSIdString></SVCSIdString> + </TargetCommonOption> + <CommonProperty> + <UseCPPCompiler>0</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + </CommonProperty> + <DllOption> + <SimDllName>SARMCM3.DLL</SimDllName> + <SimDllArguments>-MPU -REMAP</SimDllArguments> + <SimDlgDll>DCM.DLL</SimDlgDll> + <SimDlgDllArguments>-pCM4</SimDlgDllArguments> + <TargetDllName>SARMCM3.DLL</TargetDllName> + <TargetDllArguments>-MPU</TargetDllArguments> + <TargetDlgDll>TCM.DLL</TargetDlgDll> + <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments> + </DllOption> + <DebugOption> + <OPTHX> + <HexSelection>1</HexSelection> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + <Oh166RecLen>16</Oh166RecLen> + </OPTHX> + <Simulator> + <UseSimulator>0</UseSimulator> + <LoadApplicationAtStartup>1</LoadApplicationAtStartup> + <RunToMain>1</RunToMain> + <RestoreBreakpoints>1</RestoreBreakpoints> + <RestoreWatchpoints>1</RestoreWatchpoints> + <RestoreMemoryDisplay>1</RestoreMemoryDisplay> + <RestoreFunctions>1</RestoreFunctions> + <RestoreToolbox>1</RestoreToolbox> + <LimitSpeedToRealTime>0</LimitSpeedToRealTime> + </Simulator> + <Target> + <UseTarget>1</UseTarget> + <LoadApplicationAtStartup>1</LoadApplicationAtStartup> + <RunToMain>1</RunToMain> + <RestoreBreakpoints>1</RestoreBreakpoints> + <RestoreWatchpoints>1</RestoreWatchpoints> + <RestoreMemoryDisplay>1</RestoreMemoryDisplay> + <RestoreFunctions>0</RestoreFunctions> + <RestoreToolbox>1</RestoreToolbox> + <RestoreTracepoints>0</RestoreTracepoints> + </Target> + <RunDebugAfterBuild>0</RunDebugAfterBuild> + <TargetSelection>7</TargetSelection> + <SimDlls> + <CpuDll></CpuDll> + <CpuDllArguments></CpuDllArguments> + <PeripheralDll></PeripheralDll> + <PeripheralDllArguments></PeripheralDllArguments> + <InitializationFile></InitializationFile> + </SimDlls> + <TargetDlls> + <CpuDll></CpuDll> + <CpuDllArguments></CpuDllArguments> + <PeripheralDll></PeripheralDll> + <PeripheralDllArguments></PeripheralDllArguments> + <InitializationFile></InitializationFile> + <Driver>Segger\JL2CM3.dll</Driver> + </TargetDlls> + </DebugOption> + <Utilities> + <Flash1> + <UseTargetDll>1</UseTargetDll> + <UseExternalTool>0</UseExternalTool> + <RunIndependent>0</RunIndependent> + <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> + <Capability>1</Capability> + <DriverSelection>4096</DriverSelection> + </Flash1> + <bUseTDR>1</bUseTDR> + <Flash2>BIN\UL2CM3.DLL</Flash2> + <Flash3>"" ()</Flash3> + <Flash4></Flash4> + </Utilities> + <TargetArmAds> + <ArmAdsMisc> + <GenerateListings>0</GenerateListings> + <asHll>1</asHll> + <asAsm>1</asAsm> + <asMacX>1</asMacX> + <asSyms>1</asSyms> + <asFals>1</asFals> + <asDbgD>1</asDbgD> + <asForm>1</asForm> + <ldLst>0</ldLst> + <ldmm>1</ldmm> + <ldXref>1</ldXref> + <BigEnd>0</BigEnd> + <AdsALst>1</AdsALst> + <AdsACrf>1</AdsACrf> + <AdsANop>0</AdsANop> + <AdsANot>0</AdsANot> + <AdsLLst>1</AdsLLst> + <AdsLmap>1</AdsLmap> + <AdsLcgr>1</AdsLcgr> + <AdsLsym>1</AdsLsym> + <AdsLszi>1</AdsLszi> + <AdsLtoi>1</AdsLtoi> + <AdsLsun>1</AdsLsun> + <AdsLven>1</AdsLven> + <AdsLsxf>1</AdsLsxf> + <RvctClst>0</RvctClst> + <GenPPlst>0</GenPPlst> + <AdsCpuType>"Cortex-M4"</AdsCpuType> + <RvctDeviceName></RvctDeviceName> + <mOS>0</mOS> + <uocRom>0</uocRom> + <uocRam>0</uocRam> + <hadIROM>1</hadIROM> + <hadIRAM>1</hadIRAM> + <hadXRAM>0</hadXRAM> + <uocXRam>0</uocXRam> + <RvdsVP>2</RvdsVP> + <hadIRAM2>1</hadIRAM2> + <hadIROM2>1</hadIROM2> + <StupSel>8</StupSel> + <useUlib>1</useUlib> + <EndSel>0</EndSel> + <uLtcg>0</uLtcg> + <RoSelD>3</RoSelD> + <RwSelD>3</RwSelD> + <CodeSel>0</CodeSel> + <OptFeed>0</OptFeed> + <NoZi1>0</NoZi1> + <NoZi2>0</NoZi2> + <NoZi3>0</NoZi3> + <NoZi4>0</NoZi4> + <NoZi5>0</NoZi5> + <Ro1Chk>0</Ro1Chk> + <Ro2Chk>0</Ro2Chk> + <Ro3Chk>0</Ro3Chk> + <Ir1Chk>1</Ir1Chk> + <Ir2Chk>0</Ir2Chk> + <Ra1Chk>0</Ra1Chk> + <Ra2Chk>0</Ra2Chk> + <Ra3Chk>0</Ra3Chk> + <Im1Chk>1</Im1Chk> + <Im2Chk>0</Im2Chk> + <OnChipMemories> + <Ocm1> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm1> + <Ocm2> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm2> + <Ocm3> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm3> + <Ocm4> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm4> + <Ocm5> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm5> + <Ocm6> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm6> + <IRAM> + <Type>0</Type> + <StartAddress>0x20000000</StartAddress> + <Size>0x6000</Size> + </IRAM> + <IROM> + <Type>1</Type> + <StartAddress>0xc000000</StartAddress> + <Size>0x40000</Size> + </IROM> + <XRAM> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </XRAM> + <OCR_RVCT1> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT1> + <OCR_RVCT2> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT2> + <OCR_RVCT3> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT3> + <OCR_RVCT4> + <Type>1</Type> + <StartAddress>0xc000000</StartAddress> + <Size>0x40000</Size> + </OCR_RVCT4> + <OCR_RVCT5> + <Type>1</Type> + <StartAddress>0x8000000</StartAddress> + <Size>0x40000</Size> + </OCR_RVCT5> + <OCR_RVCT6> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT6> + <OCR_RVCT7> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT7> + <OCR_RVCT8> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT8> + <OCR_RVCT9> + <Type>0</Type> + <StartAddress>0x20000000</StartAddress> + <Size>0x6000</Size> + </OCR_RVCT9> + <OCR_RVCT10> + <Type>0</Type> + <StartAddress>0x1fffe000</StartAddress> + <Size>0x2000</Size> + </OCR_RVCT10> + </OnChipMemories> + <RvctStartVector></RvctStartVector> + </ArmAdsMisc> + <Cads> + <interw>1</interw> + <Optim>1</Optim> + <oTime>0</oTime> + <SplitLS>0</SplitLS> + <OneElfS>0</OneElfS> + <Strict>0</Strict> + <EnumInt>0</EnumInt> + <PlainCh>0</PlainCh> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <wLevel>0</wLevel> + <uThumb>0</uThumb> + <uSurpInc>0</uSurpInc> + <VariousControls> + <MiscControls>--cpu Cortex-M4.fp --no_allow_fpreg_for_nonfpdata</MiscControls> + <Define>rvkdm PART_XMC4200</Define> + <Undefine></Undefine> + <IncludePath>..\CORTEX_M4F_Infineon_XMC4500_Keil;..\..\Source\include;..\..\Source\portable\RVDS\ARM_CM4F;..\Common\include</IncludePath> + </VariousControls> + </Cads> + <Aads> + <interw>1</interw> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <thumb>0</thumb> + <SplitLS>0</SplitLS> + <SwStkChk>0</SwStkChk> + <NoWarn>0</NoWarn> + <uSurpInc>0</uSurpInc> + <VariousControls> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Aads> + <LDads> + <umfTarg>1</umfTarg> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <noStLib>0</noStLib> + <RepFail>1</RepFail> + <useFile>0</useFile> + <TextAddressRange>0x0C000000</TextAddressRange> + <DataAddressRange>0x10000000</DataAddressRange> + <ScatterFile></ScatterFile> + <IncludeLibs></IncludeLibs> + <IncludeLibsPath></IncludeLibsPath> + <Misc>--entry=Reset_Handler</Misc> + <LinkerInputFile></LinkerInputFile> + <DisabledWarnings></DisabledWarnings> + </LDads> + </TargetArmAds> + </TargetOption> + <Groups> + <Group> + <GroupName>Startup</GroupName> + <Files> + <File> + <FileName>startup_XMC4500.s</FileName> + <FileType>2</FileType> + <FilePath>.\startup_XMC4500.s</FilePath> + <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>0</IncludeInBuild> + <AlwaysBuild>2</AlwaysBuild> + <GenerateAssemblyFile>2</GenerateAssemblyFile> + <AssembleAssemblyFile>2</AssembleAssemblyFile> + <PublicsOnly>2</PublicsOnly> + <StopOnExitCode>11</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + </CommonProperty> + <FileArmAds> + <Aads> + <interw>2</interw> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <thumb>2</thumb> + <SplitLS>2</SplitLS> + <SwStkChk>2</SwStkChk> + <NoWarn>2</NoWarn> + <uSurpInc>2</uSurpInc> + <VariousControls> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Aads> + </FileArmAds> + </FileOption> + </File> + <File> + <FileName>System_XMC4500.c</FileName> + <FileType>1</FileType> + <FilePath>.\System_XMC4500.c</FilePath> + <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>0</IncludeInBuild> + <AlwaysBuild>2</AlwaysBuild> + <GenerateAssemblyFile>2</GenerateAssemblyFile> + <AssembleAssemblyFile>2</AssembleAssemblyFile> + <PublicsOnly>2</PublicsOnly> + <StopOnExitCode>11</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + </CommonProperty> + <FileArmAds> + <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <VariousControls> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Cads> + </FileArmAds> + </FileOption> + </File> + <File> + <FileName>startup_XMC4200.s</FileName> + <FileType>2</FileType> + <FilePath>.\startup_XMC4200.s</FilePath> + </File> + <File> + <FileName>system_XMC4200.c</FileName> + <FileType>1</FileType> + <FilePath>.\system_XMC4200.c</FilePath> + </File> + <File> + <FileName>system_XMC4400.c</FileName> + <FileType>1</FileType> + <FilePath>.\system_XMC4400.c</FilePath> + <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>0</IncludeInBuild> + <AlwaysBuild>2</AlwaysBuild> + <GenerateAssemblyFile>2</GenerateAssemblyFile> + <AssembleAssemblyFile>2</AssembleAssemblyFile> + <PublicsOnly>2</PublicsOnly> + <StopOnExitCode>11</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + </CommonProperty> + <FileArmAds> + <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <VariousControls> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Cads> + </FileArmAds> + </FileOption> + </File> + <File> + <FileName>startup_XMC4400.s</FileName> + <FileType>2</FileType> + <FilePath>.\startup_XMC4400.s</FilePath> + <FileOption> + <CommonProperty> + <UseCPPCompiler>2</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>0</IncludeInBuild> + <AlwaysBuild>2</AlwaysBuild> + <GenerateAssemblyFile>2</GenerateAssemblyFile> + <AssembleAssemblyFile>2</AssembleAssemblyFile> + <PublicsOnly>2</PublicsOnly> + <StopOnExitCode>11</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + </CommonProperty> + <FileArmAds> + <Aads> + <interw>2</interw> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <thumb>2</thumb> + <SplitLS>2</SplitLS> + <SwStkChk>2</SwStkChk> + <NoWarn>2</NoWarn> + <uSurpInc>2</uSurpInc> + <VariousControls> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Aads> + </FileArmAds> + </FileOption> + </File> + </Files> + </Group> + <Group> + <GroupName>Demo_Source</GroupName> + <Files> + <File> + <FileName>main.c</FileName> + <FileType>1</FileType> + <FilePath>.\main.c</FilePath> + </File> + <File> + <FileName>FreeRTOSConfig.h</FileName> + <FileType>5</FileType> + <FilePath>.\FreeRTOSConfig.h</FilePath> + </File> + <File> + <FileName>RegTest.c</FileName> + <FileType>1</FileType> + <FilePath>.\RegTest.c</FilePath> + </File> + <File> + <FileName>main_full.c</FileName> + <FileType>1</FileType> + <FilePath>.\main_full.c</FilePath> + </File> + <File> + <FileName>main_blinky.c</FileName> + <FileType>1</FileType> + <FilePath>.\main_blinky.c</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>FreeRTOS_Source</GroupName> + <Files> + <File> + <FileName>timers.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\Source\timers.c</FilePath> + </File> + <File> + <FileName>list.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\Source\list.c</FilePath> </File> <File> - <FileName>PollQ.c</FileName> + <FileName>queue.c</FileName> <FileType>1</FileType> - <FilePath>..\Common\Minimal\PollQ.c</FilePath> + <FilePath>..\..\Source\queue.c</FilePath> + </File> + <File> + <FileName>tasks.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\Source\tasks.c</FilePath> + </File> + <File> + <FileName>port.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\Source\portable\RVDS\ARM_CM4F\port.c</FilePath> + </File> + <File> + <FileName>heap_4.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\Source\portable\MemMang\heap_4.c</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>Common_Demo_Source</GroupName> + <Files> + <File> + <FileName>semtest.c</FileName> + <FileType>1</FileType> + <FilePath>..\Common\Minimal\semtest.c</FilePath> + </File> + <File> + <FileName>sp_flop.c</FileName> + <FileType>1</FileType> + <FilePath>..\Common\Minimal\sp_flop.c</FilePath> + </File> + <File> + <FileName>blocktim.c</FileName> + <FileType>1</FileType> + <FilePath>..\Common\Minimal\blocktim.c</FilePath> + </File> + <File> + <FileName>countsem.c</FileName> + <FileType>1</FileType> + <FilePath>..\Common\Minimal\countsem.c</FilePath> + </File> + <File> + <FileName>dynamic.c</FileName> + <FileType>1</FileType> + <FilePath>..\Common\Minimal\dynamic.c</FilePath> + </File> + <File> + <FileName>GenQTest.c</FileName> + <FileType>1</FileType> + <FilePath>..\Common\Minimal\GenQTest.c</FilePath> </File> <File> <FileName>recmutex.c</FileName> diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/System_XMC4500.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/System_XMC4500.c index 12b6f4b32..06fd3aca6 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/System_XMC4500.c +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/System_XMC4500.c @@ -1,47 +1,47 @@ -/******************************************************************************
+/**************************************************************************//**
* @file system_XMC4500.c
- * @brief Device specific initialization for the XMC4500-Series according to CMSIS
- * @version V2.2
- * @date 20. January 2012
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File
+ * for the Infineon XMC4500 Device Series
+ * @version V3.0.1 Alpha
+ * @date 17. September 2012
*
* @note
- * Copyright (C) 2011 Infineon Technologies AG. All rights reserved.
-
+ * Copyright (C) 2011 ARM Limited. All rights reserved.
*
* @par
- * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers.
- * This file can be freely distributed within development tools that are supporting such microcontrollers.
-
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
- *
******************************************************************************/
-#include "System_XMC4500.h"
+#include "system_XMC4500.h"
#include <XMC4500.h>
/*----------------------------------------------------------------------------
- Define clocks is located in System_XMC4500.h
- *----------------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
/*!< System Clock Frequency (Core Clock)*/
-uint32_t SystemCoreClock = CLOCK_OSC_HP;
+uint32_t SystemCoreClock;
+
+/* clock definitions, do not modify! */
+#define SCU_CLOCK_CRYSTAL 1
+#define SCU_CLOCK_BACK_UP_FACTORY 2
+#define SCU_CLOCK_BACK_UP_AUTOMATIC 3
+
+
+#define HIB_CLOCK_FOSI 1
+#define HIB_CLOCK_OSCULP 2
+
+
-/*----------------------------------------------------------------------------
- Keil pragma to prevent warnings
- *----------------------------------------------------------------------------*/
-#if defined(__ARMCC_VERSION)
-#pragma diag_suppress 177
-#endif
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
@@ -63,7 +63,7 @@ uint32_t SystemCoreClock = CLOCK_OSC_HP; //
// <e> Main Clock Configuration
// <o1.0..1> CPU clock divider
-// <0=> fCPU = fSYS
+// <0=> fCPU = fSYS
// <1=> fCPU = fSYS / 2
// <o2.0..1> Peripheral Bus clock divider
// <0=> fPB = fCPU
@@ -73,25 +73,93 @@ uint32_t SystemCoreClock = CLOCK_OSC_HP; // <1=> fCCU = fCPU / 2
//
// </e>
-//
+//
*/
#define SCU_CLOCK_SETUP 1
#define SCU_CPUCLKCR_DIV 0x00000000
#define SCU_PBCLKCR_DIV 0x00000000
#define SCU_CCUCLKCR_DIV 0x00000000
-
-
+/* not avalible in config wizzard*/
+/*
+* mandatory clock parameters **************************************************
+*
+* source for clock generation
+* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input)
+*
+**************************************************************************************/
+// Selection of imput lock for PLL
+/*************************************************************************************/
+#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL
+//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY
+//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC
+
+/*************************************************************************************/
+// Standby clock selection for Backup clock source trimming
+/*************************************************************************************/
+#define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP
+//#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI
+
+/*************************************************************************************/
+// Global clock parameters
+/*************************************************************************************/
+#define CLOCK_FSYS 120000000
+#define CLOCK_CRYSTAL_FREQUENCY 12000000
+#define CLOCK_BACK_UP 24000000
+
+/*************************************************************************************/
+/* OSC_HP setup parameters */
+/*************************************************************************************/
+#define SCU_OSC_HP_MODE 0xF0
+#define SCU_OSCHPWDGDIV 2
+
+/*************************************************************************************/
+/* MAIN PLL setup parameters */
+/*************************************************************************************/
+//Divider settings for external crystal @ 12 MHz
+/*************************************************************************************/
+#define SCU_PLL_K1DIV 1
+#define SCU_PLL_K2DIV 3
+#define SCU_PLL_PDIV 1
+#define SCU_PLL_NDIV 79
+
+/*************************************************************************************/
+//Divider settings for use of backup clock source trimmed
+/*************************************************************************************/
+//#define SCU_PLL_K1DIV 1
+//#define SCU_PLL_K2DIV 3
+//#define SCU_PLL_PDIV 3
+//#define SCU_PLL_NDIV 79
+/*************************************************************************************/
/*--------------------- USB CLOCK Configuration ---------------------------
//
// <e> USB Clock Configuration
//
// </e>
-//
+//
*/
#define SCU_USB_CLOCK_SETUP 0
+/* not avalible in config wizzard*/
+#define SCU_USBPLL_PDIV 0
+#define SCU_USBPLL_NDIV 31
+#define SCU_USBDIV 3
+
+/*--------------------- Flash Wait State Configuration -------------------------------
+//
+// <e> Flash Wait State Configuration
+// <o1.0..3> Flash Wait State
+// <0=> 3 WS
+// <1=> 4 WS
+// <2=> 5 WS
+// <3=> 6 WS
+// </e>
+//
+*/
+
+#define PMU_FLASH 1
+#define PMU_FLASH_WS 0x00000000
/*--------------------- CLOCKOUT Configuration -------------------------------
@@ -99,20 +167,32 @@ uint32_t SystemCoreClock = CLOCK_OSC_HP; // <e> Clock OUT Configuration
// <o1.0..1> Clockout Source Selection
// <0=> System Clock
-// <2=> USB Clock
+// <2=> Divided value of USB PLL output
// <3=> Divided value of PLL Clock
-// <o2.0..1> Clockout Pin Selection
+// <o2.0..4> Clockout divider <1-10><#-1>
+// <o3.0..1> Clockout Pin Selection
// <0=> P1.15
// <1=> P0.8
-//
+//
//
// </e>
-//
+//
*/
-#define SCU_CLOCKOUT_SETUP 0 // recommended to keep disabled
-#define SCU_CLOCKOUT_SOURCE 0x00000000
-#define SCU_CLOCKOUT_PIN 0x00000000
+#define SCU_CLOCKOUT_SETUP 0
+#define SCU_CLOCKOUT_SOURCE 0x00000003
+#define SCU_CLOCKOUT_DIV 0x00000009
+#define SCU_CLOCKOUT_PIN 0x00000001
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+/*!< System Clock Frequency (Core Clock)*/
+#if SCU_CLOCK_SETUP
+uint32_t SystemCoreClock = CLOCK_FSYS;
+#else
+uint32_t SystemCoreClock = CLOCK_BACK_UP;
+#endif
/*----------------------------------------------------------------------------
static functions declarations
@@ -122,240 +202,429 @@ static int SystemClockSetup(void); #endif
#if (SCU_USB_CLOCK_SETUP == 1)
-static void USBClockSetup(void);
+static int USBClockSetup(void);
#endif
+
/**
* @brief Setup the microcontroller system.
- * Initialize the PLL and update the
+ * Initialize the PLL and update the
* SystemCoreClock variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
-/* Setup the WDT */
-#if (WDT_SETUP == 1)
-WDT->CTR &= ~WDTENB_nVal;
-#endif
+int temp;
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
(3UL << 11*2) ); /* set CP11 Full Access */
#endif
-/* Disable branch prediction - PCON.PBS = 1 */
-PREF->PCON |= (PREF_PCON_PBS_Msk);
-
/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */
SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);
+/* Setup the WDT */
+#if WDT_SETUP
+
+WDT->CTR &= ~WDTENB_nVal;
+
+#endif
+
+/* Setup the Flash Wait State */
+#if PMU_FLASH
+temp = FLASH0->FCON;
+temp &= ~FLASH_FCON_WSPFLASH_Msk;
+temp |= PMU_FLASH_WS+3;
+FLASH0->FCON = temp;
+#endif
+
+
/* Setup the clockout */
-/* README README README README README README README README README README */
-/*
- * Please use the CLOCKOUT feature with diligence. Use this only if you know
- * what you are doing.
- *
- * You must be aware that the settings below can potentially be in conflict
- * with DAVE code generation engine preferences.
- *
- * Even worse, the setting below configures the ports as output ports while in
- * reality, the board on which this chip is mounted may have a source driving
- * the ports.
- *
- * So use this feature only when you are absolutely sure that the port must
- * indeed be configured as an output AND you are NOT linking this startup code
- * with code that was generated by DAVE code engine.
- */
-#if (SCU_CLOCKOUT_SETUP == 1)
+#if SCU_CLOCKOUT_SETUP
+
SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE;
+/*set PLL div for clkout */
+SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16;
if (SCU_CLOCKOUT_PIN) {
- PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */
- PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);
- }
-else PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */
+ PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */
+ PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);
+ //PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */
+ }
+else {
+ PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */
+ //PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */
+ }
+
#endif
-/* Setup the System clock */
-#if (SCU_CLOCK_SETUP == 1)
+
+/* Setup the System clock */
+#if SCU_CLOCK_SETUP
SystemClockSetup();
#endif
-/* Setup the USB PL */
-#if (SCU_USB_CLOCK_SETUP == 1)
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/
+
+
+/* Setup the USB PL */
+#if SCU_USB_CLOCK_SETUP
USBClockSetup();
#endif
+
+
}
/**
* @brief Update SystemCoreClock according to Clock Register Values
- * @note -
+ * @note -
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
+unsigned int PDIV;
+unsigned int NDIV;
+unsigned int K2DIV;
+unsigned int long VCO;
+
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
-SystemCoreClock = SYSTEM_FREQUENCY;/*!< System Clock Frequency (Core Clock)*/
+if (SCU_CLK->SYSCLKCR == 0x00010000)
+{
+ if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){
+ /* check if PLL is locked */
+ /* read back divider settings */
+ PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1;
+ NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1;
+ K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1;
+
+ if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){
+ /* the selected clock is the Backup clock fofi */
+ VCO = (CLOCK_BACK_UP/PDIV)*NDIV;
+ SystemCoreClock = VCO/K2DIV;
+ /* in case the sysclock div is used */
+ SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);
+
+ }
+ else
+ {
+ /* the selected clock is the PLL external oscillator */
+ VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV;
+ SystemCoreClock = VCO/K2DIV;
+ /* in case the sysclock div is used */
+ SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);
+ }
+
+
+ }
+}
+else
+{
+SystemCoreClock = CLOCK_BACK_UP;
+}
+
}
/**
* @brief -
- * @note -
+ * @note -
* @param None
* @retval None
*/
#if (SCU_CLOCK_SETUP == 1)
static int SystemClockSetup(void)
{
-/* enable PLL first */
- SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk |
- SCU_PLL_PLLCON0_PLLPWD_Msk);
-
-/* Enable OSC_HP */
- if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)
- {
- /* Enable the OSC_HP*/
- SCU_OSC->OSCHPCTRL = (OSC_HP_MODE<<4);
- /* Setup OSC WDG devider */
- SCU_OSC->OSCHPCTRL |= (OSCHPWDGDIV<<16);
- /* Select external OSC as PLL input */
- SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;
- /* Restart OSC Watchdog */
- SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
-
- do
- {
- ; /* here a timeout need to be added */
- }while(!( (SCU_PLL->PLLSTAT) &
- (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |
- SCU_PLL_PLLSTAT_PLLSP_Msk)
- )
- );
-
- }
-
-/* Setup Main PLL */
- /* Select FOFI as system clock */
- if(SCU_CLK->SYSCLKCR != 0X000000)
- SCU_CLK->SYSCLKCR = 0x00000000; /*Select FOFI*/
-
- /* Go to bypass the Main PLL */
- SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;
+int temp;
+unsigned int long VCO;
+int stepping_K2DIV;
- /* disconnect OSC_HP to PLL */
- SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;
+/* this weak function enables DAVE3 clock App usage */
+if(AllowPLLInitByStartup()){
- /* Setup devider settings for main PLL */
- SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) |
- (PLL_K2DIV_STEP_1<<16) | (PLL_PDIV<<24));
-
- /* we may have to set OSCDISCDIS */
- SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
+/* check if PLL is switched on */
+if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){
+/* enable PLL first */
+ SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
- /* connect OSC_HP to PLL */
- SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;
+}
- /* restart PLL Lock detection */
- SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;
+/* Enable OSC_HP if not already on*/
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)
+ {
+ /********************************************************************************************************************/
+ /* Use external crystal for PLL clock input */
+ /********************************************************************************************************************/
- /* wait for PLL Lock */
- while (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk));
+ if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){
+ SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/
+ /* setup OSC WDG devider */
+ SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);
+ /* select external OSC as PLL input */
+ SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;
+ /* restart OSC Watchdog */
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
+
+ /* Timeout for wait loop ~150ms */
+ /********************************/
+ SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ do
+ {
+ ;/* wait for ~150ms */
+ }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));
- /* Go back to the Main PLL */
- SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
+ if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)
+ return(0);/* Return Error */
- /*********************************************************
- here we need to setup the system clock divider
- *********************************************************/
+ }
+ }
+ else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)
+ {
+ /********************************************************************************************************************/
+ /* Use factory trimming Back-up clock for PLL clock input */
+ /********************************************************************************************************************/
+ /* PLL Back up clock selected */
+ SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
+
+ }
+ else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC)
+ {
+ /********************************************************************************************************************/
+ /* Use automatic trimming Back-up clock for PLL clock input */
+ /********************************************************************************************************************/
+ /* check for HIB Domain enabled */
+ if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)
+ SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/
+
+ /* check for HIB Domain is not in reset state */
+ if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1)
+ SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/
+
+ /* PLL Back up clock selected */
+ SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
+
+ if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI)
+ {
+ /****************************************************************************************************************/
+ /* Use fOSI as source of the standby clock */
+ /****************************************************************************************************************/
+ SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
+
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;
+ for(temp=0;temp<=0xFFFF;temp++);
+
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
+ }
+ else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP)
+ {
+ /****************************************************************************************************************/
+ /* Use fULP as source of the standby clock */
+ /****************************************************************************************************************/
+ /*check OSCUL if running correct*/
+ if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0)
+ {
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk);
+
+ SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/
+ /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/
+ /* select OSCUL clock for RTC*/
+ SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk;
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
+ /*enable OSCULP WDG Alarm Enable*/
+ SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
+ /*wait now for clock is stable */
+ do
+ {
+ SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);
+ for(temp=0;temp<=0xFFFF;temp++);
+ }
+ while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk);
+
+ SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);
+ }
+ // now OSCULP is running and can be used
+ SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
+
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;
+ /*TRIAL for delay loop*/
+ for(temp=0;temp<=0xFFFF;temp++);
+
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
+ /*TRIAL for delay loop*/
+ for(temp=0;temp<=0xFFFF;temp++);
+
+ }
+ }
- SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;
- SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV;
- SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;
+ /********************************************************************************************************************/
+ /* Setup and look the main PLL */
+ /********************************************************************************************************************/
+
+if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){
+ /* Systen is still running from internal clock */
+ /* select FOFI as system clock */
+ if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/
+
+
+ /*calulation for stepping*/
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+ if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
+ VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+
+ stepping_K2DIV = (VCO/24000000)-1;
+ /* Go to bypass the Main PLL */
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;
+ /* disconnect OSC_HP to PLL */
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;
+ /* Setup devider settings for main PLL */
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
+ /* we may have to set OSCDISCDIS */
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
+ /* connect OSC_HP to PLL */
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;
+ /* restart PLL Lock detection */
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;
+ /* wait for PLL Lock */
+ /* setup time out loop */
+ /* Timeout for wait loo ~150ms */
+ /********************************/
+ SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+
+ while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500));
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
+
+ if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk)
+ {
+ /* Go back to the Main PLL */
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;
+ }
+ else return(0);
+
+
+ /*********************************************************
+ here we need to setup the system clock divider
+ *********************************************************/
+
+ SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;
+ SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV;
+ SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;
+
+
+ /* Switch system clock to PLL */
+ SCU_CLK->SYSCLKCR |= 0x00010000;
+
+ /* we may have to reset OSCDISCDIS */
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
+
+
+ /*********************************************************/
+ /* Delay for next K2 step ~50µs */
+ /*********************************************************/
+ SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+
+ while (SysTick->VAL >= 100); /* wait for ~50µs */
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
+ /*********************************************************/
+
+ /*********************************************************
+ here the ramp up of the system clock starts FSys < 60MHz
+ *********************************************************/
+ if (CLOCK_FSYS > 60000000){
+ /*calulation for stepping*/
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+ if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
+ VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+
+ stepping_K2DIV = (VCO/60000000)-1;
+
+ /* Setup devider settings for main PLL */
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
+ }
+ else
+ {
+ /* Setup devider settings for main PLL */
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
+ SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
+ return(1);
+ }
+
+ /*********************************************************/
+ /* Delay for next K2 step ~50µs */
+ /*********************************************************/
+ SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+
+ while (SysTick->VAL >= 100); /* wait for ~50µs */
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
+ /********************************/
- /* Switch system clock to PLL */
- SCU_CLK->SYSCLKCR |= 0x00010000;
-
/*********************************************************
- here the ramp up of the system clock starts
- *********************************************************/
- /* Delay for next K2 step ~50µs */
- /********************************/
- /* Set reload register */
- SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;
-
- /* Load the SysTick Counter Value */
- SysTick->VAL = 0;
-
- /* Enable SysTick IRQ and SysTick Timer */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_ENABLE_Msk;
-
- /* wait for ~50µs */
- while (SysTick->VAL >= 100);
-
- /* Stop SysTick Timer */
- SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
- /********************************/
-
- /* Setup devider settings for main PLL */
- SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) |
- (PLL_K2DIV_STEP_2<<16) | (PLL_PDIV<<24));
-
- /* Delay for next K2 step ~50µs */
- /********************************/
- SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;
-
- /* Load the SysTick Counter Value */
- SysTick->VAL = 0;
-
- /* Enable SysTick IRQ and SysTick Timer */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
-
- /* Wait for ~50µs */
- while (SysTick->VAL >= 100);
-
- /* Stop SysTick Timer */
- SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
- /********************************/
-
- /* Setup devider settings for main PLL */
- SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) |
- (PLL_K2DIV_STEP_3<<16) | (PLL_PDIV<<24));
-
- /* Delay for next K2 step ~50µs */
- /********************************/
- SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;
-
- /* Load the SysTick Counter Value */
- SysTick->VAL = 0;
-
- /* Enable SysTick IRQ and SysTick Timer */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
-
- /* Wait for ~50µs */
- while (SysTick->VAL >= 100);
-
- /* Stop SysTick Timer */
- SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
- /********************************/
-
- /* Setup devider settings for main PLL */
- SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | (PLL_K2DIV<<16) |
- (PLL_PDIV<<24));
-
- /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
- SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk |
- SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;
-
+ here the ramp up of the system clock starts FSys < 90MHz
+ *********************************************************/
+ if (CLOCK_FSYS > 90000000){
+ /*calulation for stepping*/
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+ if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
+ VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+
+ stepping_K2DIV = (VCO/90000000)-1;
+
+ /* Setup devider settings for main PLL */
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
+ }
+ else
+ {
+ /* Setup devider settings for main PLL */
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
+ SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
+ return(1);
+ }
+
+ /*********************************************************/
+ /* Delay for next K2 step ~50µs */
+ /*********************************************************/
+ SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+
+ while (SysTick->VAL >= 100); /* wait for ~50µs */
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
+ /********************************/
+
+ /* Setup devider settings for main PLL */
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
+
+ SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
+ }
+ }/* end this weak function enables DAVE3 clock App usage */
return(1);
}
@@ -363,40 +632,50 @@ static int SystemClockSetup(void) /**
* @brief -
- * @note -
+ * @note -
* @param None
* @retval None
*/
-#if(SCU_USB_CLOCK_SETUP == 1)
-static void USBClockSetup(void)
+#if (SCU_USB_CLOCK_SETUP == 1)
+static int USBClockSetup(void)
{
-/* enable PLL first */
- SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk |
- SCU_PLL_USBPLLCON_PLLPWD_Msk);
+/* this weak function enables DAVE3 clock App usage */
+if(AllowPLLInitByStartup()){
+
+ /* check if PLL is switched on */
+if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){
+ /* enable PLL first */
+ SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);
+}
/* check and if not already running enable OSC_HP */
- if(!((SCU_PLL->PLLSTAT) &
- (SCU_PLL_PLLSTAT_PLLHV_Msk |
- SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)))
- {
- if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)
- {
-
- SCU_OSC->OSCHPCTRL = (OSC_HP_MODE<<4); /*enable the OSC_HP*/
+ if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){
+ /* check if Main PLL is switched on for OSC WD*/
+ if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){
+ /* enable PLL first */
+ SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
+ }
+ SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/
/* setup OSC WDG devider */
- SCU_OSC->OSCHPCTRL |= (OSCHPWDGDIV<<16);
- /* select external OSC as PLL input */
- SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;
+ SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);
/* restart OSC Watchdog */
- SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
-
- do
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
+
+ /* Timeout for wait loop ~150ms */
+ /********************************/
+ SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ do
{
- ; /* here a timeout need to be added */
- }while(!((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk |
- SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)));
-
- }
+ ;/* wait for ~150ms */
+ }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));
+
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
+ if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)
+ return(0);/* Return Error */
+
}
@@ -406,7 +685,9 @@ static void USBClockSetup(void) /* disconnect OSC_FI to PLL */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;
/* Setup devider settings for main PLL */
- SCU_PLL->USBPLLCON = ((USBPLL_NDIV<<8) | (USBPLL_PDIV<<24));
+ SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24));
+ /* Setup USBDIV settings USB clock */
+ SCU_CLK->USBCLKCR = SCU_USBDIV;
/* we may have to set OSCDISCDIS */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;
/* connect OSC_FI to PLL */
@@ -415,5 +696,10 @@ static void USBClockSetup(void) SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;
/* wait for PLL Lock */
while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk));
- }
+
+ }/* end this weak function enables DAVE3 clock App usage */
+ return(1);
+
+}
#endif
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/System_XMC4500.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/System_XMC4500.h new file mode 100644 index 000000000..73eb6d590 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/System_XMC4500.h @@ -0,0 +1,114 @@ +/**************************************************************************//**
+ * @file system_XMC4500.h
+ * @brief Header file for the XMC4500-Series systeminit
+ *
+ * @version V1.6
+ * @date 23. October 2012
+ *
+ * @note
+ * Copyright (C) 2011 Infineon Technologies AG. All rights reserved.
+
+ *
+ * @par
+ * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers.
+ * This file can be freely distributed within development tools that are supporting such microcontrollers.
+
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_XMC4500_H
+#define __SYSTEM_XMC4500_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+extern void SystemInit (void);
+
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/* this weak function enables DAVE3 clock App usage */
+extern uint32_t AllowPLLInitByStartup(void);
+
+
+/* clock definitions, do not modify! */
+#define SCU_CLOCK_CRYSTAL 1
+
+
+
+/*
+ * mandatory clock parameters **************************************************
+ */
+/* source for clock generation
+ * range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input)
+ * mandatory for old system_xmc4500.c files - please do not remove!!!
+ **************************************************************************************/
+
+#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL
+#define CLOCK_OSC_HP 24000000
+#define CLOCK_BACK_UP 24000000
+#define CLOCK_CRYSTAL_FREQUENCY 12000000
+#define SYSTEM_FREQUENCY 120000000
+
+/* OSC_HP setup parameters */
+#define OSC_HP_MODE 0
+#define OSCHPWDGDIV 2
+
+/* MAIN PLL setup parameters */
+
+
+#define PLL_K1DIV 1
+#define PLL_K2DIV 3
+#define PLL_PDIV 1
+#define PLL_NDIV 79
+
+
+
+#define PLL_K2DIV_STEP_1 19 //PLL output is 24Mhz
+#define PLL_K2DIV_STEP_2 7 //PLL output to 60Mhz
+#define PLL_K2DIV_STEP_3 4 //PLL output to 96Mhz
+
+
+
+#define USBPLL_PDIV 1
+#define USBPLL_NDIV 15
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main.c index 89d41e945..8d415a924 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main.c +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main.c @@ -92,13 +92,9 @@ #include "FreeRTOS.h"
#include "task.h"
-/* Hardware includes. */
-#include "XMC4500.h"
-#include "System_XMC4500.h"
-
/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,
or 0 to run the more comprehensive test and demo application. */
-#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1
+#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0
/*-----------------------------------------------------------*/
@@ -141,12 +137,6 @@ static void prvSetupHardware( void ) {
extern void SystemCoreClockUpdate( void );
- /* Ensure SystemCoreClock variable is set. */
- SystemCoreClockUpdate();
-
- /* Configure pin P3.9 for the LED. */
- PORT3->IOCR8 = 0x00008000;
-
/* Ensure all priority bits are assigned as preemption priority bits. */
NVIC_SetPriorityGrouping( 0 );
}
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main_blinky.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main_blinky.c index cbc2ba905..83d8398d8 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main_blinky.c +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main_blinky.c @@ -107,10 +107,6 @@ #include "task.h"
#include "semphr.h"
-/* Hardware includes. */
-#include "XMC4500.h"
-#include "System_XMC4500.h"
-
/* Priorities at which the tasks are created. */
#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
@@ -129,9 +125,6 @@ functionality. */ #define mainQUEUE_SEND_PARAMETER ( 0x1111UL )
#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL )
-/* To toggle the single LED */
-#define mainTOGGLE_LED() ( PORT3->OMR = 0x02000200 )
-
/*-----------------------------------------------------------*/
/*
@@ -146,11 +139,6 @@ static void prvQueueSendTask( void *pvParameters ); */
void main_blinky( void );
-/*
- * The hardware only has a single LED. Simply toggle it.
- */
-extern void vMainToggleLED( void );
-
/*-----------------------------------------------------------*/
/* The queue used by both tasks. */
@@ -235,7 +223,7 @@ unsigned long ulReceivedValue; is it the expected value? If it is, toggle the LED. */
if( ulReceivedValue == 100UL )
{
- mainTOGGLE_LED();
+ configTOGGLE_LED();
ulReceivedValue = 0U;
}
}
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main_full.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main_full.c index ded660a6e..b93e72df2 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main_full.c +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main_full.c @@ -124,10 +124,6 @@ #include "recmutex.h"
#include "death.h"
-/* Hardware includes. */
-#include "XMC4500.h"
-#include "System_XMC4500.h"
-
/* Priorities for the demo application tasks. */
#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL )
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )
@@ -135,9 +131,6 @@ #define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )
#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )
-/* To toggle the single LED */
-#define mainTOGGLE_LED() ( PORT3->OMR = 0x02000200 )
-
/* A block time of zero simply means "don't block". */
#define mainDONT_BLOCK ( 0UL )
@@ -183,14 +176,11 @@ xTimerHandle xCheckTimer = NULL; /* Start all the other standard demo/test tasks. The have not particular
functionality, but do demonstrate how to use the FreeRTOS API and test the
kernel port. */
- vStartIntegerMathTasks( tskIDLE_PRIORITY );
vStartDynamicPriorityTasks();
- vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
vCreateBlockTimeTasks();
vStartCountingSemaphoreTasks();
vStartGenericQueueTasks( tskIDLE_PRIORITY );
vStartRecursiveMutexTasks();
- vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
vStartMathTasks( mainFLOP_TASK_PRIORITY );
@@ -213,11 +203,6 @@ xTimerHandle xCheckTimer = NULL; xTimerStart( xCheckTimer, mainDONT_BLOCK );
}
- /* The set of tasks created by the following function call have to be
- created last as they keep account of the number of tasks they expect to see
- running. */
- vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );
-
/* Start the scheduler. */
vTaskStartScheduler();
@@ -244,21 +229,11 @@ unsigned long ulErrorFound = pdFALSE; ulErrorFound = pdTRUE;
}
- if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
- {
- ulErrorFound = pdTRUE;
- }
-
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
}
- if( xAreBlockingQueuesStillRunning() != pdTRUE )
- {
- ulErrorFound = pdTRUE;
- }
-
if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
@@ -274,16 +249,6 @@ unsigned long ulErrorFound = pdFALSE; ulErrorFound = pdTRUE;
}
- if( xIsCreateTaskStillRunning() != pdTRUE )
- {
- ulErrorFound = pdTRUE;
- }
-
- if( xArePollingQueuesStillRunning() != pdTRUE )
- {
- ulErrorFound = pdTRUE;
- }
-
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
@@ -306,7 +271,7 @@ unsigned long ulErrorFound = pdFALSE; /* Toggle the check LED to give an indication of the system status. If
the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then
everything is ok. A faster toggle indicates an error. */
- mainTOGGLE_LED();
+ configTOGGLE_LED();
/* Have any errors been latch in ulErrorFound? If so, shorten the
period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds.
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/startup_XMC4200.s b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/startup_XMC4200.s new file mode 100644 index 000000000..a246e4302 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/startup_XMC4200.s @@ -0,0 +1,455 @@ +;*****************************************************************************/
+; * @file startup_XMC4200.s
+; * @brief CMSIS Cortex-M4 Core Device Startup File for
+; * Infineon XMC4200 Device Series
+; * @version V1.00
+; * @date 05. February 2013
+; *
+; * @note
+; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.
+; *
+; * @par
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * @par
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+
+;/* ********************* Version History *********************************** */
+;/* ***************************************************************************
+; V0.1 , September 2012, First version
+; V1.0 , February 2013, FIX for CPU prefetch bug implemented
+;**************************************************************************** */
+
+
+;* <<< Use Configuration Wizard in Context Menu >>>
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+;/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */
+;/*
+; * STEP_AB and below have the prefetch functional deviation (Errata id: PMU_CM.001).
+; * A veneer defined below will first
+; * be executed which in turn branches to the final exception handler.
+; *
+; * In addition to defining the veneers, the vector table must for these buggy
+; * devices contain the veneers.
+; */
+
+;set WORKAROUND_PMU_CM001 under Options for target - Asm - Define
+;or use define below
+ GBLL WORKAROUND_PMU_CM001
+
+;/* A macro to setup a vector table entry based on STEP ID */
+ IF :DEF:WORKAROUND_PMU_CM001
+ MACRO
+ ExcpVector $Handler
+ DCD $Handler._Veneer
+ MEND
+ ELSE
+ MACRO
+ ExcpVector $Handler
+ DCD $Handler
+ MEND
+ ENDIF
+
+;/* A macro to ease definition of the various handlers based on STEP ID */
+ IF :DEF:WORKAROUND_PMU_CM001
+
+ ;/* First define the final exception handler */
+ MACRO
+ ExcpHandler $Handler_Func
+$Handler_Func\
+ PROC
+ EXPORT $Handler_Func [WEAK]
+ B .
+ ENDP
+
+ ;/* And then define a veneer that will branch to the final excp handler */
+$Handler_Func._Veneer\
+ PROC
+ EXPORT $Handler_Func._Veneer [WEAK]
+ LDR R0, =$Handler_Func
+ PUSH {LR}
+ BLX R0
+ POP {PC}
+ ALIGN
+ LTORG
+ ENDP
+ MEND
+
+ ELSE
+
+ ;/* No prefetch bug, hence define only the final exception handler */
+ MACRO
+ ExcpHandler $Handler_Func
+$Handler_Func\
+ PROC
+ EXPORT $Handler_Func [WEAK]
+ B .
+ ENDP
+ MEND
+
+ ENDIF
+;/* ============= END OF MACRO DEFINITION MACRO DEFINITION ================== */
+
+
+;* ================== START OF VECTOR TABLE DEFINITION ====================== */
+;* Vector Table - This gets programed into VTOR register */
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+
+
+__Vectors
+ DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+
+ ExcpVector NMI_Handler ; NMI Handler
+ ExcpVector HardFault_Handler ; Hard Fault Handler
+ ExcpVector MemManage_Handler ; MPU Fault Handler
+ ExcpVector BusFault_Handler ; Bus Fault Handler
+ ExcpVector UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ ExcpVector DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; Interrupt Handlers for Service Requests (SR) from XMC4200 Peripherals
+ ExcpVector SCU_0_IRQHandler ; Handler name for SR SCU_0
+ ExcpVector ERU0_0_IRQHandler ; Handler name for SR ERU0_0
+ ExcpVector ERU0_1_IRQHandler ; Handler name for SR ERU0_1
+ ExcpVector ERU0_2_IRQHandler ; Handler name for SR ERU0_2
+ ExcpVector ERU0_3_IRQHandler ; Handler name for SR ERU0_3
+ ExcpVector ERU1_0_IRQHandler ; Handler name for SR ERU1_0
+ ExcpVector ERU1_1_IRQHandler ; Handler name for SR ERU1_1
+ ExcpVector ERU1_2_IRQHandler ; Handler name for SR ERU1_2
+ ExcpVector ERU1_3_IRQHandler ; Handler name for SR ERU1_3
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ ExcpVector PMU0_0_IRQHandler ; Handler name for SR PMU0_0
+ DCD 0 ; Reserved
+ ExcpVector VADC0_C0_0_IRQHandler ; Handler name for SR VADC0_C0_0
+ ExcpVector VADC0_C0_1_IRQHandler ; Handler name for SR VADC0_C0_1
+ ExcpVector VADC0_C0_2_IRQHandler ; Handler name for SR VADC0_C0_1
+ ExcpVector VADC0_C0_3_IRQHandler ; Handler name for SR VADC0_C0_3
+ ExcpVector VADC0_G0_0_IRQHandler ; Handler name for SR VADC0_G0_0
+ ExcpVector VADC0_G0_1_IRQHandler ; Handler name for SR VADC0_G0_1
+ ExcpVector VADC0_G0_2_IRQHandler ; Handler name for SR VADC0_G0_2
+ ExcpVector VADC0_G0_3_IRQHandler ; Handler name for SR VADC0_G0_3
+ ExcpVector VADC0_G1_0_IRQHandler ; Handler name for SR VADC0_G1_0
+ ExcpVector VADC0_G1_1_IRQHandler ; Handler name for SR VADC0_G1_1
+ ExcpVector VADC0_G1_2_IRQHandler ; Handler name for SR VADC0_G1_2
+ ExcpVector VADC0_G1_3_IRQHandler ; Handler name for SR VADC0_G1_3
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ ExcpVector DAC0_0_IRQHandler ; Handler name for SR DAC0_0
+ ExcpVector DAC0_1_IRQHandler ; Handler name for SR DAC0_1
+ ExcpVector CCU40_0_IRQHandler ; Handler name for SR CCU40_0
+ ExcpVector CCU40_1_IRQHandler ; Handler name for SR CCU40_1
+ ExcpVector CCU40_2_IRQHandler ; Handler name for SR CCU40_2
+ ExcpVector CCU40_3_IRQHandler ; Handler name for SR CCU40_3
+ ExcpVector CCU41_0_IRQHandler ; Handler name for SR CCU41_0
+ ExcpVector CCU41_1_IRQHandler ; Handler name for SR CCU41_1
+ ExcpVector CCU41_2_IRQHandler ; Handler name for SR CCU41_2
+ ExcpVector CCU41_3_IRQHandler ; Handler name for SR CCU41_3
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ ExcpVector CCU80_0_IRQHandler ; Handler name for SR CCU80_0
+ ExcpVector CCU80_1_IRQHandler ; Handler name for SR CCU80_1
+ ExcpVector CCU80_2_IRQHandler ; Handler name for SR CCU80_2
+ ExcpVector CCU80_3_IRQHandler ; Handler name for SR CCU80_3
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ ExcpVector POSIF0_0_IRQHandler ; Handler name for SR POSIF0_0
+ ExcpVector POSIF0_1_IRQHandler ; Handler name for SR POSIF0_1
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ ExcpVector HRPWM_0_IRQHandler ; Handler name for SR HRPWM_0
+ ExcpVector HRPWM_1_IRQHandler ; Handler name for SR HRPWM_1
+ ExcpVector HRPWM_2_IRQHandler ; Handler name for SR HRPWM_2
+ ExcpVector HRPWM_3_IRQHandler ; Handler name for SR HRPWM_3
+ ExcpVector CAN0_0_IRQHandler ; Handler name for SR CAN0_0
+ ExcpVector CAN0_1_IRQHandler ; Handler name for SR CAN0_1
+ ExcpVector CAN0_2_IRQHandler ; Handler name for SR CAN0_2
+ ExcpVector CAN0_3_IRQHandler ; Handler name for SR CAN0_3
+ ExcpVector CAN0_4_IRQHandler ; Handler name for SR CAN0_4
+ ExcpVector CAN0_5_IRQHandler ; Handler name for SR CAN0_5
+ ExcpVector CAN0_6_IRQHandler ; Handler name for SR CAN0_6
+ ExcpVector CAN0_7_IRQHandler ; Handler name for SR CAN0_7
+ ExcpVector USIC0_0_IRQHandler ; Handler name for SR USIC0_0
+ ExcpVector USIC0_1_IRQHandler ; Handler name for SR USIC0_1
+ ExcpVector USIC0_2_IRQHandler ; Handler name for SR USIC0_2
+ ExcpVector USIC0_3_IRQHandler ; Handler name for SR USIC0_3
+ ExcpVector USIC0_4_IRQHandler ; Handler name for SR USIC0_4
+ ExcpVector USIC0_5_IRQHandler ; Handler name for SR USIC0_5
+ ExcpVector USIC1_0_IRQHandler ; Handler name for SR USIC1_0
+ ExcpVector USIC1_1_IRQHandler ; Handler name for SR USIC1_1
+ ExcpVector USIC1_2_IRQHandler ; Handler name for SR USIC1_2
+ ExcpVector USIC1_3_IRQHandler ; Handler name for SR USIC1_3
+ ExcpVector USIC1_4_IRQHandler ; Handler name for SR USIC1_4
+ ExcpVector USIC1_5_IRQHandler ; Handler name for SR USIC1_5
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ ExcpVector LEDTS0_0_IRQHandler ; Handler name for SR LEDTS0_0
+ DCD 0 ; Reserved
+ ExcpVector FCE0_0_IRQHandler ; Handler name for SR FCE0_0
+ ExcpVector GPDMA0_0_IRQHandler ; Handler name for SR GPDMA0_0
+ DCD 0 ; Reserved
+ ExcpVector USB0_0_IRQHandler ; Handler name for SR USB0_0
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+;* ================== END OF VECTOR TABLE DEFINITION ======================= */
+
+;* ================== START OF VECTOR ROUTINES ============================= */
+
+ AREA |.text|, CODE, READONLY
+
+;* Reset Handler */
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ ; Remap vector table
+ LDR R0, =__Vectors
+ LDR R1, =0xE000ED08 ;*VTOR register
+ STR R0,[R1]
+
+ ;* C routines are likely to be called. Setup the stack now
+ LDR SP,=__initial_sp
+
+ LDR R0, = SystemInit
+ BLX R0
+
+ ;SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is
+ ;weakly defined here though for a potential override.
+
+ LDR R0, = SystemInit_DAVE3
+ BLX R0
+
+ ;* Reset stack pointer before zipping off to user application
+ LDR SP,=__initial_sp
+
+ LDR R0, =__main
+ BX R0
+
+ ALIGN
+ ENDP
+
+
+
+
+;* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */
+
+
+
+;/* Default exception Handlers - Users may override this default functionality by
+; defining handlers of the same name in their C code */
+
+ ExcpHandler NMI_Handler
+ ExcpHandler HardFault_Handler
+ ExcpHandler MemManage_Handler
+ ExcpHandler BusFault_Handler
+ ExcpHandler UsageFault_Handler
+ ExcpHandler SVC_Handler
+ ExcpHandler DebugMon_Handler
+ ExcpHandler PendSV_Handler
+ ExcpHandler SysTick_Handler
+
+;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */
+
+;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */
+
+;* IRQ Handlers */
+ ExcpHandler SCU_0_IRQHandler
+ ExcpHandler ERU0_0_IRQHandler
+ ExcpHandler ERU0_1_IRQHandler
+ ExcpHandler ERU0_2_IRQHandler
+ ExcpHandler ERU0_3_IRQHandler
+ ExcpHandler ERU1_0_IRQHandler
+ ExcpHandler ERU1_1_IRQHandler
+ ExcpHandler ERU1_2_IRQHandler
+ ExcpHandler ERU1_3_IRQHandler
+ ExcpHandler PMU0_0_IRQHandler
+ ExcpHandler VADC0_C0_0_IRQHandler
+ ExcpHandler VADC0_C0_1_IRQHandler
+ ExcpHandler VADC0_C0_2_IRQHandler
+ ExcpHandler VADC0_C0_3_IRQHandler
+ ExcpHandler VADC0_G0_0_IRQHandler
+ ExcpHandler VADC0_G0_1_IRQHandler
+ ExcpHandler VADC0_G0_2_IRQHandler
+ ExcpHandler VADC0_G0_3_IRQHandler
+ ExcpHandler VADC0_G1_0_IRQHandler
+ ExcpHandler VADC0_G1_1_IRQHandler
+ ExcpHandler VADC0_G1_2_IRQHandler
+ ExcpHandler VADC0_G1_3_IRQHandler
+ ExcpHandler DAC0_0_IRQHandler
+ ExcpHandler DAC0_1_IRQHandler
+ ExcpHandler CCU40_0_IRQHandler
+ ExcpHandler CCU40_1_IRQHandler
+ ExcpHandler CCU40_2_IRQHandler
+ ExcpHandler CCU40_3_IRQHandler
+ ExcpHandler CCU41_0_IRQHandler
+ ExcpHandler CCU41_1_IRQHandler
+ ExcpHandler CCU41_2_IRQHandler
+ ExcpHandler CCU41_3_IRQHandler
+ ExcpHandler CCU80_0_IRQHandler
+ ExcpHandler CCU80_1_IRQHandler
+ ExcpHandler CCU80_2_IRQHandler
+ ExcpHandler CCU80_3_IRQHandler
+ ExcpHandler POSIF0_0_IRQHandler
+ ExcpHandler POSIF0_1_IRQHandler
+ ExcpHandler HRPWM_0_IRQHandler
+ ExcpHandler HRPWM_1_IRQHandler
+ ExcpHandler HRPWM_2_IRQHandler
+ ExcpHandler HRPWM_3_IRQHandler
+ ExcpHandler CAN0_0_IRQHandler
+ ExcpHandler CAN0_1_IRQHandler
+ ExcpHandler CAN0_2_IRQHandler
+ ExcpHandler CAN0_3_IRQHandler
+ ExcpHandler CAN0_4_IRQHandler
+ ExcpHandler CAN0_5_IRQHandler
+ ExcpHandler CAN0_6_IRQHandler
+ ExcpHandler CAN0_7_IRQHandler
+ ExcpHandler USIC0_0_IRQHandler
+ ExcpHandler USIC0_1_IRQHandler
+ ExcpHandler USIC0_2_IRQHandler
+ ExcpHandler USIC0_3_IRQHandler
+ ExcpHandler USIC0_4_IRQHandler
+ ExcpHandler USIC0_5_IRQHandler
+ ExcpHandler USIC1_0_IRQHandler
+ ExcpHandler USIC1_1_IRQHandler
+ ExcpHandler USIC1_2_IRQHandler
+ ExcpHandler USIC1_3_IRQHandler
+ ExcpHandler USIC1_4_IRQHandler
+ ExcpHandler USIC1_5_IRQHandler
+ ExcpHandler LEDTS0_0_IRQHandler
+ ExcpHandler FCE0_0_IRQHandler
+ ExcpHandler GPDMA0_0_IRQHandler
+ ExcpHandler USB0_0_IRQHandler
+
+;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */
+
+;* Definition of the default weak SystemInit_DAVE3 function.
+;* This function will be called by the CMSIS SystemInit function.
+;* If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3
+;* which will overule this weak definition
+SystemInit_DAVE3 PROC
+ EXPORT SystemInit_DAVE3 [WEAK]
+ NOP
+ BX LR
+ ENDP
+
+;* Definition of the default weak DAVE3 function for clock App usage.
+;* AllowPLLInitByStartup Handler */
+AllowPLLInitByStartup PROC
+ EXPORT AllowPLLInitByStartup [WEAK]
+ MOV R0,#1
+ BX LR
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
+;******************* Copyright (C) 2009-2013 ARM Limited *****END OF FILE*****
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/startup_XMC4400.s b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/startup_XMC4400.s new file mode 100644 index 000000000..cebede580 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/startup_XMC4400.s @@ -0,0 +1,486 @@ +;*****************************************************************************/
+; * @file startup_XMC4400.s
+; * @brief CMSIS Cortex-M4 Core Device Startup File for
+; * Infineon XMC4400 Device Series
+; * @version V1.00
+; * @date 05. February 2013
+; *
+; * @note
+; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.
+; *
+; * @par
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * @par
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+
+;/* ********************* Version History *********************************** */
+;/* ***************************************************************************
+; V0.2 , August 2012, First version
+; V1.0 , February 2013, FIX for CPU prefetch bug implemented
+;**************************************************************************** */
+
+
+;* <<< Use Configuration Wizard in Context Menu >>>
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+;/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */
+;/*
+; * STEP_AB and below have the prefetch functional deviation (Errata id: PMU_CM.001).
+; * A veneer defined below will first
+; * be executed which in turn branches to the final exception handler.
+; *
+; * In addition to defining the veneers, the vector table must for these buggy
+; * devices contain the veneers.
+; */
+
+;set WORKAROUND_PMU_CM001 under Options for target - Asm - Define
+;or use define below
+ GBLL WORKAROUND_PMU_CM001
+
+;/* A macro to setup a vector table entry based on STEP ID */
+ IF :DEF:WORKAROUND_PMU_CM001
+ MACRO
+ ExcpVector $Handler
+ DCD $Handler._Veneer
+ MEND
+ ELSE
+ MACRO
+ ExcpVector $Handler
+ DCD $Handler
+ MEND
+ ENDIF
+
+;/* A macro to ease definition of the various handlers based on STEP ID */
+ IF :DEF:WORKAROUND_PMU_CM001
+
+ ;/* First define the final exception handler */
+ MACRO
+ ExcpHandler $Handler_Func
+$Handler_Func\
+ PROC
+ EXPORT $Handler_Func [WEAK]
+ B .
+ ENDP
+
+ ;/* And then define a veneer that will branch to the final excp handler */
+$Handler_Func._Veneer\
+ PROC
+ EXPORT $Handler_Func._Veneer [WEAK]
+ LDR R0, =$Handler_Func
+ PUSH {LR}
+ BLX R0
+ POP {PC}
+ ALIGN
+ LTORG
+ ENDP
+ MEND
+
+ ELSE
+
+ ;/* No prefetch bug, hence define only the final exception handler */
+ MACRO
+ ExcpHandler $Handler_Func
+$Handler_Func\
+ PROC
+ EXPORT $Handler_Func [WEAK]
+ B .
+ ENDP
+ MEND
+
+ ENDIF
+;/* ============= END OF MACRO DEFINITION MACRO DEFINITION ================== */
+
+
+;* ================== START OF VECTOR TABLE DEFINITION ====================== */
+;* Vector Table - This gets programed into VTOR register */
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+
+
+__Vectors
+ DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+
+ ExcpVector NMI_Handler ; NMI Handler
+ ExcpVector HardFault_Handler ; Hard Fault Handler
+ ExcpVector MemManage_Handler ; MPU Fault Handler
+ ExcpVector BusFault_Handler ; Bus Fault Handler
+ ExcpVector UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ ExcpVector DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; Interrupt Handlers for Service Requests (SR) from XMC4400 Peripherals
+ ExcpVector SCU_0_IRQHandler ; Handler name for SR SCU_0
+ ExcpVector ERU0_0_IRQHandler ; Handler name for SR ERU0_0
+ ExcpVector ERU0_1_IRQHandler ; Handler name for SR ERU0_1
+ ExcpVector ERU0_2_IRQHandler ; Handler name for SR ERU0_2
+ ExcpVector ERU0_3_IRQHandler ; Handler name for SR ERU0_3
+ ExcpVector ERU1_0_IRQHandler ; Handler name for SR ERU1_0
+ ExcpVector ERU1_1_IRQHandler ; Handler name for SR ERU1_1
+ ExcpVector ERU1_2_IRQHandler ; Handler name for SR ERU1_2
+ ExcpVector ERU1_3_IRQHandler ; Handler name for SR ERU1_3
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ ExcpVector PMU0_0_IRQHandler ; Handler name for SR PMU0_0
+ DCD 0 ; Reserved
+ ExcpVector VADC0_C0_0_IRQHandler ; Handler name for SR VADC0_C0_0
+ ExcpVector VADC0_C0_1_IRQHandler ; Handler name for SR VADC0_C0_1
+ ExcpVector VADC0_C0_2_IRQHandler ; Handler name for SR VADC0_C0_1
+ ExcpVector VADC0_C0_3_IRQHandler ; Handler name for SR VADC0_C0_3
+ ExcpVector VADC0_G0_0_IRQHandler ; Handler name for SR VADC0_G0_0
+ ExcpVector VADC0_G0_1_IRQHandler ; Handler name for SR VADC0_G0_1
+ ExcpVector VADC0_G0_2_IRQHandler ; Handler name for SR VADC0_G0_2
+ ExcpVector VADC0_G0_3_IRQHandler ; Handler name for SR VADC0_G0_3
+ ExcpVector VADC0_G1_0_IRQHandler ; Handler name for SR VADC0_G1_0
+ ExcpVector VADC0_G1_1_IRQHandler ; Handler name for SR VADC0_G1_1
+ ExcpVector VADC0_G1_2_IRQHandler ; Handler name for SR VADC0_G1_2
+ ExcpVector VADC0_G1_3_IRQHandler ; Handler name for SR VADC0_G1_3
+ ExcpVector VADC0_G2_0_IRQHandler ; Handler name for SR VADC0_G2_0
+ ExcpVector VADC0_G2_1_IRQHandler ; Handler name for SR VADC0_G2_1
+ ExcpVector VADC0_G2_2_IRQHandler ; Handler name for SR VADC0_G2_2
+ ExcpVector VADC0_G2_3_IRQHandler ; Handler name for SR VADC0_G2_3
+ ExcpVector VADC0_G3_0_IRQHandler ; Handler name for SR VADC0_G3_0
+ ExcpVector VADC0_G3_1_IRQHandler ; Handler name for SR VADC0_G3_1
+ ExcpVector VADC0_G3_2_IRQHandler ; Handler name for SR VADC0_G3_2
+ ExcpVector VADC0_G3_3_IRQHandler ; Handler name for SR VADC0_G3_3
+ ExcpVector DSD0_0_IRQHandler ; Handler name for SR DSD0_0
+ ExcpVector DSD0_1_IRQHandler ; Handler name for SR DSD0_1
+ ExcpVector DSD0_2_IRQHandler ; Handler name for SR DSD0_2
+ ExcpVector DSD0_3_IRQHandler ; Handler name for SR DSD0_3
+ ExcpVector DSD0_4_IRQHandler ; Handler name for SR DSD0_4
+ ExcpVector DSD0_5_IRQHandler ; Handler name for SR DSD0_5
+ ExcpVector DSD0_6_IRQHandler ; Handler name for SR DSD0_6
+ ExcpVector DSD0_7_IRQHandler ; Handler name for SR DSD0_7
+ ExcpVector DAC0_0_IRQHandler ; Handler name for SR DAC0_0
+ ExcpVector DAC0_1_IRQHandler ; Handler name for SR DAC0_1
+ ExcpVector CCU40_0_IRQHandler ; Handler name for SR CCU40_0
+ ExcpVector CCU40_1_IRQHandler ; Handler name for SR CCU40_1
+ ExcpVector CCU40_2_IRQHandler ; Handler name for SR CCU40_2
+ ExcpVector CCU40_3_IRQHandler ; Handler name for SR CCU40_3
+ ExcpVector CCU41_0_IRQHandler ; Handler name for SR CCU41_0
+ ExcpVector CCU41_1_IRQHandler ; Handler name for SR CCU41_1
+ ExcpVector CCU41_2_IRQHandler ; Handler name for SR CCU41_2
+ ExcpVector CCU41_3_IRQHandler ; Handler name for SR CCU41_3
+ ExcpVector CCU42_0_IRQHandler ; Handler name for SR CCU42_0
+ ExcpVector CCU42_1_IRQHandler ; Handler name for SR CCU42_1
+ ExcpVector CCU42_2_IRQHandler ; Handler name for SR CCU42_2
+ ExcpVector CCU42_3_IRQHandler ; Handler name for SR CCU42_3
+ ExcpVector CCU43_0_IRQHandler ; Handler name for SR CCU43_0
+ ExcpVector CCU43_1_IRQHandler ; Handler name for SR CCU43_1
+ ExcpVector CCU43_2_IRQHandler ; Handler name for SR CCU43_2
+ ExcpVector CCU43_3_IRQHandler ; Handler name for SR CCU43_3
+ ExcpVector CCU80_0_IRQHandler ; Handler name for SR CCU80_0
+ ExcpVector CCU80_1_IRQHandler ; Handler name for SR CCU80_1
+ ExcpVector CCU80_2_IRQHandler ; Handler name for SR CCU80_2
+ ExcpVector CCU80_3_IRQHandler ; Handler name for SR CCU80_3
+ ExcpVector CCU81_0_IRQHandler ; Handler name for SR CCU81_0
+ ExcpVector CCU81_1_IRQHandler ; Handler name for SR CCU81_1
+ ExcpVector CCU81_2_IRQHandler ; Handler name for SR CCU81_2
+ ExcpVector CCU81_3_IRQHandler ; Handler name for SR CCU81_3
+ ExcpVector POSIF0_0_IRQHandler ; Handler name for SR POSIF0_0
+ ExcpVector POSIF0_1_IRQHandler ; Handler name for SR POSIF0_1
+ ExcpVector POSIF1_0_IRQHandler ; Handler name for SR POSIF1_0
+ ExcpVector POSIF1_1_IRQHandler ; Handler name for SR POSIF1_1
+ ExcpVector HRPWM_0_IRQHandler ; Handler name for SR HRPWM_0
+ ExcpVector HRPWM_1_IRQHandler ; Handler name for SR HRPWM_1
+ ExcpVector HRPWM_2_IRQHandler ; Handler name for SR HRPWM_2
+ ExcpVector HRPWM_3_IRQHandler ; Handler name for SR HRPWM_3
+ ExcpVector CAN0_0_IRQHandler ; Handler name for SR CAN0_0
+ ExcpVector CAN0_1_IRQHandler ; Handler name for SR CAN0_1
+ ExcpVector CAN0_2_IRQHandler ; Handler name for SR CAN0_2
+ ExcpVector CAN0_3_IRQHandler ; Handler name for SR CAN0_3
+ ExcpVector CAN0_4_IRQHandler ; Handler name for SR CAN0_4
+ ExcpVector CAN0_5_IRQHandler ; Handler name for SR CAN0_5
+ ExcpVector CAN0_6_IRQHandler ; Handler name for SR CAN0_6
+ ExcpVector CAN0_7_IRQHandler ; Handler name for SR CAN0_7
+ ExcpVector USIC0_0_IRQHandler ; Handler name for SR USIC0_0
+ ExcpVector USIC0_1_IRQHandler ; Handler name for SR USIC0_1
+ ExcpVector USIC0_2_IRQHandler ; Handler name for SR USIC0_2
+ ExcpVector USIC0_3_IRQHandler ; Handler name for SR USIC0_3
+ ExcpVector USIC0_4_IRQHandler ; Handler name for SR USIC0_4
+ ExcpVector USIC0_5_IRQHandler ; Handler name for SR USIC0_5
+ ExcpVector USIC1_0_IRQHandler ; Handler name for SR USIC1_0
+ ExcpVector USIC1_1_IRQHandler ; Handler name for SR USIC1_1
+ ExcpVector USIC1_2_IRQHandler ; Handler name for SR USIC1_2
+ ExcpVector USIC1_3_IRQHandler ; Handler name for SR USIC1_3
+ ExcpVector USIC1_4_IRQHandler ; Handler name for SR USIC1_4
+ ExcpVector USIC1_5_IRQHandler ; Handler name for SR USIC1_5
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ ExcpVector LEDTS0_0_IRQHandler ; Handler name for SR LEDTS0_0
+ DCD 0 ; Reserved
+ ExcpVector FCE0_0_IRQHandler ; Handler name for SR FCE0_0
+ ExcpVector GPDMA0_0_IRQHandler ; Handler name for SR GPDMA0_0
+ DCD 0 ; Reserved
+ ExcpVector USB0_0_IRQHandler ; Handler name for SR USB0_0
+ ExcpVector ETH0_0_IRQHandler ; Handler name for SR ETH0_0
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+;* ================== END OF VECTOR TABLE DEFINITION ======================= */
+
+;* ================== START OF VECTOR ROUTINES ============================= */
+
+ AREA |.text|, CODE, READONLY
+
+;* Reset Handler */
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ ; Remap vector table
+ LDR R0, =__Vectors
+ LDR R1, =0xE000ED08 ;*VTOR register
+ STR R0,[R1]
+
+ ;* C routines are likely to be called. Setup the stack now
+ LDR SP,=__initial_sp
+
+ LDR R0, = SystemInit
+ BLX R0
+
+ ;SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is
+ ;weakly defined here though for a potential override.
+
+ LDR R0, = SystemInit_DAVE3
+ BLX R0
+
+ ;* Reset stack pointer before zipping off to user application
+ LDR SP,=__initial_sp
+
+ LDR R0, =__main
+ BX R0
+
+ ALIGN
+ ENDP
+
+
+
+
+;* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */
+
+
+
+;/* Default exception Handlers - Users may override this default functionality by
+; defining handlers of the same name in their C code */
+
+ ExcpHandler NMI_Handler
+ ExcpHandler HardFault_Handler
+ ExcpHandler MemManage_Handler
+ ExcpHandler BusFault_Handler
+ ExcpHandler UsageFault_Handler
+ ExcpHandler SVC_Handler
+ ExcpHandler DebugMon_Handler
+ ExcpHandler PendSV_Handler
+ ExcpHandler SysTick_Handler
+
+;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */
+
+;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */
+
+;* IRQ Handlers */
+ ExcpHandler SCU_0_IRQHandler
+ ExcpHandler ERU0_0_IRQHandler
+ ExcpHandler ERU0_1_IRQHandler
+ ExcpHandler ERU0_2_IRQHandler
+ ExcpHandler ERU0_3_IRQHandler
+ ExcpHandler ERU1_0_IRQHandler
+ ExcpHandler ERU1_1_IRQHandler
+ ExcpHandler ERU1_2_IRQHandler
+ ExcpHandler ERU1_3_IRQHandler
+ ExcpHandler PMU0_0_IRQHandler
+ ExcpHandler VADC0_C0_0_IRQHandler
+ ExcpHandler VADC0_C0_1_IRQHandler
+ ExcpHandler VADC0_C0_2_IRQHandler
+ ExcpHandler VADC0_C0_3_IRQHandler
+ ExcpHandler VADC0_G0_0_IRQHandler
+ ExcpHandler VADC0_G0_1_IRQHandler
+ ExcpHandler VADC0_G0_2_IRQHandler
+ ExcpHandler VADC0_G0_3_IRQHandler
+ ExcpHandler VADC0_G1_0_IRQHandler
+ ExcpHandler VADC0_G1_1_IRQHandler
+ ExcpHandler VADC0_G1_2_IRQHandler
+ ExcpHandler VADC0_G1_3_IRQHandler
+ ExcpHandler VADC0_G2_0_IRQHandler
+ ExcpHandler VADC0_G2_1_IRQHandler
+ ExcpHandler VADC0_G2_2_IRQHandler
+ ExcpHandler VADC0_G2_3_IRQHandler
+ ExcpHandler VADC0_G3_0_IRQHandler
+ ExcpHandler VADC0_G3_1_IRQHandler
+ ExcpHandler VADC0_G3_2_IRQHandler
+ ExcpHandler VADC0_G3_3_IRQHandler
+ ExcpHandler DSD0_0_IRQHandler
+ ExcpHandler DSD0_1_IRQHandler
+ ExcpHandler DSD0_2_IRQHandler
+ ExcpHandler DSD0_3_IRQHandler
+ ExcpHandler DSD0_4_IRQHandler
+ ExcpHandler DSD0_5_IRQHandler
+ ExcpHandler DSD0_6_IRQHandler
+ ExcpHandler DSD0_7_IRQHandler
+ ExcpHandler DAC0_0_IRQHandler
+ ExcpHandler DAC0_1_IRQHandler
+ ExcpHandler CCU40_0_IRQHandler
+ ExcpHandler CCU40_1_IRQHandler
+ ExcpHandler CCU40_2_IRQHandler
+ ExcpHandler CCU40_3_IRQHandler
+ ExcpHandler CCU41_0_IRQHandler
+ ExcpHandler CCU41_1_IRQHandler
+ ExcpHandler CCU41_2_IRQHandler
+ ExcpHandler CCU41_3_IRQHandler
+ ExcpHandler CCU42_0_IRQHandler
+ ExcpHandler CCU42_1_IRQHandler
+ ExcpHandler CCU42_2_IRQHandler
+ ExcpHandler CCU42_3_IRQHandler
+ ExcpHandler CCU43_0_IRQHandler
+ ExcpHandler CCU43_1_IRQHandler
+ ExcpHandler CCU43_2_IRQHandler
+ ExcpHandler CCU43_3_IRQHandler
+ ExcpHandler CCU80_0_IRQHandler
+ ExcpHandler CCU80_1_IRQHandler
+ ExcpHandler CCU80_2_IRQHandler
+ ExcpHandler CCU80_3_IRQHandler
+ ExcpHandler CCU81_0_IRQHandler
+ ExcpHandler CCU81_1_IRQHandler
+ ExcpHandler CCU81_2_IRQHandler
+ ExcpHandler CCU81_3_IRQHandler
+ ExcpHandler POSIF0_0_IRQHandler
+ ExcpHandler POSIF0_1_IRQHandler
+ ExcpHandler POSIF1_0_IRQHandler
+ ExcpHandler POSIF1_1_IRQHandler
+ ExcpHandler HRPWM_0_IRQHandler
+ ExcpHandler HRPWM_1_IRQHandler
+ ExcpHandler HRPWM_2_IRQHandler
+ ExcpHandler HRPWM_3_IRQHandler
+ ExcpHandler CAN0_0_IRQHandler
+ ExcpHandler CAN0_1_IRQHandler
+ ExcpHandler CAN0_2_IRQHandler
+ ExcpHandler CAN0_3_IRQHandler
+ ExcpHandler CAN0_4_IRQHandler
+ ExcpHandler CAN0_5_IRQHandler
+ ExcpHandler CAN0_6_IRQHandler
+ ExcpHandler CAN0_7_IRQHandler
+ ExcpHandler USIC0_0_IRQHandler
+ ExcpHandler USIC0_1_IRQHandler
+ ExcpHandler USIC0_2_IRQHandler
+ ExcpHandler USIC0_3_IRQHandler
+ ExcpHandler USIC0_4_IRQHandler
+ ExcpHandler USIC0_5_IRQHandler
+ ExcpHandler USIC1_0_IRQHandler
+ ExcpHandler USIC1_1_IRQHandler
+ ExcpHandler USIC1_2_IRQHandler
+ ExcpHandler USIC1_3_IRQHandler
+ ExcpHandler USIC1_4_IRQHandler
+ ExcpHandler USIC1_5_IRQHandler
+ ExcpHandler LEDTS0_0_IRQHandler
+ ExcpHandler FCE0_0_IRQHandler
+ ExcpHandler GPDMA0_0_IRQHandler
+ ExcpHandler USB0_0_IRQHandler
+ ExcpHandler ETH0_0_IRQHandler
+
+;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */
+
+;* Definition of the default weak SystemInit_DAVE3 function.
+;* This function will be called by the CMSIS SystemInit function.
+;* If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3
+;* which will overule this weak definition
+SystemInit_DAVE3 PROC
+ EXPORT SystemInit_DAVE3 [WEAK]
+ NOP
+ BX LR
+ ENDP
+
+;* Definition of the default weak DAVE3 function for clock App usage.
+;* AllowPLLInitByStartup Handler */
+AllowPLLInitByStartup PROC
+ EXPORT AllowPLLInitByStartup [WEAK]
+ MOV R0,#1
+ BX LR
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
+;******************* Copyright (C) 2009-2013 ARM Limited *****END OF FILE*****
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/startup_XMC4500.s b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/startup_XMC4500.s index 0f409e2c8..1f2422253 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/startup_XMC4500.s +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/startup_XMC4500.s @@ -1,12 +1,12 @@ -;*****************************************************************************/ +;*****************************************************************************/
; * @file startup_XMC4500.s
; * @brief CMSIS Cortex-M4 Core Device Startup File for
; * Infineon XMC4500 Device Series
-; * @version V1.03
-; * @date 16. Jan. 2012
+; * @version V1.20
+; * @date 05. February 2013
; *
; * @note
-; * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
@@ -21,10 +21,17 @@ ; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
- - -;* <<< Use Configuration Wizard in Context Menu >>> - +
+;/* ********************* Version History *********************************** */
+;/* ***************************************************************************
+; V1.00 , February 2012, First version
+; V1.10 , August 2012, Adding Dave3 init function call
+; V1.20 , February 2013, FIX for CPU prefetch bug implemented
+;**************************************************************************** */
+
+
+;* <<< Use Configuration Wizard in Context Menu >>>
+
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
@@ -52,490 +59,421 @@ __heap_limit PRESERVE8
THUMB
- -;* ================== START OF VECTOR TABLE DEFINITION ====================== */ -;* Vector Table - This gets programed into VTOR register */ +
+;/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */
+;/*
+; * STEP_AB and below have the prefetch functional deviation (Errata id: PMU_CM.001).
+; * A veneer defined below will first
+; * be executed which in turn branches to the final exception handler.
+; *
+; * In addition to defining the veneers, the vector table must for these buggy
+; * devices contain the veneers.
+; */
+
+;set WORKAROUND_PMU_CM001 under Options for target - Asm - Define
+;or use define below
+ GBLL WORKAROUND_PMU_CM001
+
+;/* A macro to setup a vector table entry based on STEP ID */
+ IF :DEF:WORKAROUND_PMU_CM001
+ MACRO
+ ExcpVector $Handler
+ DCD $Handler._Veneer
+ MEND
+ ELSE
+ MACRO
+ ExcpVector $Handler
+ DCD $Handler
+ MEND
+ ENDIF
+
+;/* A macro to ease definition of the various handlers based on STEP ID */
+ IF :DEF:WORKAROUND_PMU_CM001
+
+ ;/* First define the final exception handler */
+ MACRO
+ ExcpHandler $Handler_Func
+$Handler_Func\
+ PROC
+ EXPORT $Handler_Func [WEAK]
+ B .
+ ENDP
+
+ ;/* And then define a veneer that will branch to the final excp handler */
+$Handler_Func._Veneer\
+ PROC
+ EXPORT $Handler_Func._Veneer [WEAK]
+ LDR R0, =$Handler_Func
+ PUSH {LR}
+ BLX R0
+ POP {PC}
+ ALIGN
+ LTORG
+ ENDP
+ MEND
+
+ ELSE
+
+ ;/* No prefetch bug, hence define only the final exception handler */
+ MACRO
+ ExcpHandler $Handler_Func
+$Handler_Func\
+ PROC
+ EXPORT $Handler_Func [WEAK]
+ B .
+ ENDP
+ MEND
+
+ ENDIF
+;/* ============= END OF MACRO DEFINITION MACRO DEFINITION ================== */
+
+
+;* ================== START OF VECTOR TABLE DEFINITION ====================== */
+;* Vector Table - This gets programed into VTOR register */
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
- -__Vectors - DCD __initial_sp ;* Top of Stack */ - DCD Reset_Handler ;* Reset Handler */ - DCD NMI_Handler ;* NMI Handler */ - DCD HardFault_Handler ;* Hard Fault Handler */ - DCD MemManage_Handler ;* MPU Fault Handler */ - DCD BusFault_Handler ;* Bus Fault Handler */ - DCD UsageFault_Handler ;* Usage Fault Handler */ - DCD 0 ;* Reserved */ - DCD 0 ;* Reserved */ - DCD 0 ;* Reserved */ - DCD 0 ;* Reserved */ - DCD SVC_Handler ;* SVCall Handler */ - DCD DebugMon_Handler ;* Debug Monitor Handler */ - DCD 0 ;* Reserved */ - DCD PendSV_Handler ;* PendSV Handler */ - DCD SysTick_Handler ;* SysTick Handler */ - - ;* Interrupt Handlers for Service Requests (SR) from XMC4500 Peripherals */ - DCD SCU_0_IRQHandler ;* Handler name for SR SCU_0 */ - DCD ERU0_0_IRQHandler ;* Handler name for SR ERU0_0 */ - DCD ERU0_1_IRQHandler ;* Handler name for SR ERU0_1 */ - DCD ERU0_2_IRQHandler ;* Handler name for SR ERU0_2 */ - DCD ERU0_3_IRQHandler ;* Handler name for SR ERU0_3 */ - DCD ERU1_0_IRQHandler ;* Handler name for SR ERU1_0 */ - DCD ERU1_1_IRQHandler ;* Handler name for SR ERU1_1 */ - DCD ERU1_2_IRQHandler ;* Handler name for SR ERU1_2 */ - DCD ERU1_3_IRQHandler ;* Handler name for SR ERU1_3 */ - DCD 0 ;* Not Available */ - DCD 0 ;* Not Available */ - DCD 0 ;* Not Available */ - DCD PMU0_0_IRQHandler ;* Handler name for SR PMU0_0 */ - DCD 0 ;* Not Available */ - DCD VADC0_C0_0_IRQHandler ;* Handler name for SR VADC0_C0_0 */ - DCD VADC0_C0_1_IRQHandler ;* Handler name for SR VADC0_C0_1 */ - DCD VADC0_C0_2_IRQHandler ;* Handler name for SR VADC0_C0_1 */ - DCD VADC0_C0_3_IRQHandler ;* Handler name for SR VADC0_C0_3 */ - DCD VADC0_G0_0_IRQHandler ;* Handler name for SR VADC0_G0_0 */ - DCD VADC0_G0_1_IRQHandler ;* Handler name for SR VADC0_G0_1 */ - DCD VADC0_G0_2_IRQHandler ;* Handler name for SR VADC0_G0_2 */ - DCD VADC0_G0_3_IRQHandler ;* Handler name for SR VADC0_G0_3 */ - DCD VADC0_G1_0_IRQHandler ;* Handler name for SR VADC0_G1_0 */ - DCD VADC0_G1_1_IRQHandler ;* Handler name for SR VADC0_G1_1 */ - DCD VADC0_G1_2_IRQHandler ;* Handler name for SR VADC0_G1_2 */ - DCD VADC0_G1_3_IRQHandler ;* Handler name for SR VADC0_G1_3 */ - DCD VADC0_G2_0_IRQHandler ;* Handler name for SR VADC0_G2_0 */ - DCD VADC0_G2_1_IRQHandler ;* Handler name for SR VADC0_G2_1 */ - DCD VADC0_G2_2_IRQHandler ;* Handler name for SR VADC0_G2_2 */ - DCD VADC0_G2_3_IRQHandler ;* Handler name for SR VADC0_G2_3 */ - DCD VADC0_G3_0_IRQHandler ;* Handler name for SR VADC0_G3_0 */ - DCD VADC0_G3_1_IRQHandler ;* Handler name for SR VADC0_G3_1 */ - DCD VADC0_G3_2_IRQHandler ;* Handler name for SR VADC0_G3_2 */ - DCD VADC0_G3_3_IRQHandler ;* Handler name for SR VADC0_G3_3 */ - DCD DSD0_0_IRQHandler ;* Handler name for SR DSD0_0 */ - DCD DSD0_1_IRQHandler ;* Handler name for SR DSD0_1 */ - DCD DSD0_2_IRQHandler ;* Handler name for SR DSD0_2 */ - DCD DSD0_3_IRQHandler ;* Handler name for SR DSD0_3 */ - DCD DSD0_4_IRQHandler ;* Handler name for SR DSD0_4 */ - DCD DSD0_5_IRQHandler ;* Handler name for SR DSD0_5 */ - DCD DSD0_6_IRQHandler ;* Handler name for SR DSD0_6 */ - DCD DSD0_7_IRQHandler ;* Handler name for SR DSD0_7 */ - DCD DAC0_0_IRQHandler ;* Handler name for SR DAC0_0 */ - DCD DAC0_1_IRQHandler ;* Handler name for SR DAC0_0 */ - DCD CCU40_0_IRQHandler ;* Handler name for SR CCU40_0 */ - DCD CCU40_1_IRQHandler ;* Handler name for SR CCU40_1 */ - DCD CCU40_2_IRQHandler ;* Handler name for SR CCU40_2 */ - DCD CCU40_3_IRQHandler ;* Handler name for SR CCU40_3 */ - DCD CCU41_0_IRQHandler ;* Handler name for SR CCU41_0 */ - DCD CCU41_1_IRQHandler ;* Handler name for SR CCU41_1 */ - DCD CCU41_2_IRQHandler ;* Handler name for SR CCU41_2 */ - DCD CCU41_3_IRQHandler ;* Handler name for SR CCU41_3 */ - DCD CCU42_0_IRQHandler ;* Handler name for SR CCU42_0 */ - DCD CCU42_1_IRQHandler ;* Handler name for SR CCU42_1 */ - DCD CCU42_2_IRQHandler ;* Handler name for SR CCU42_2 */ - DCD CCU42_3_IRQHandler ;* Handler name for SR CCU42_3 */ - DCD CCU43_0_IRQHandler ;* Handler name for SR CCU43_0 */ - DCD CCU43_1_IRQHandler ;* Handler name for SR CCU43_1 */ - DCD CCU43_2_IRQHandler ;* Handler name for SR CCU43_2 */ - DCD CCU43_3_IRQHandler ;* Handler name for SR CCU43_3 */ - DCD CCU80_0_IRQHandler ;* Handler name for SR CCU80_0 */ - DCD CCU80_1_IRQHandler ;* Handler name for SR CCU80_1 */ - DCD CCU80_2_IRQHandler ;* Handler name for SR CCU80_2 */ - DCD CCU80_3_IRQHandler ;* Handler name for SR CCU80_3 */ - DCD CCU81_0_IRQHandler ;* Handler name for SR CCU81_0 */ - DCD CCU81_1_IRQHandler ;* Handler name for SR CCU81_1 */ - DCD CCU81_2_IRQHandler ;* Handler name for SR CCU81_2 */ - DCD CCU81_3_IRQHandler ;* Handler name for SR CCU81_3 */ - DCD POSIF0_0_IRQHandler ;* Handler name for SR POSIF0_0 */ - DCD POSIF0_1_IRQHandler ;* Handler name for SR POSIF0_1 */ - DCD POSIF1_0_IRQHandler ;* Handler name for SR POSIF1_0 */ - DCD POSIF1_1_IRQHandler ;* Handler name for SR POSIF1_1 */ - DCD 0 ;* Not Available */ - DCD 0 ;* Not Available */ - DCD 0 ;* Not Available */ - DCD 0 ;* Not Available */ - DCD CAN0_0_IRQHandler ;* Handler name for SR CAN0_0 */ - DCD CAN0_1_IRQHandler ;* Handler name for SR CAN0_1 */ - DCD CAN0_2_IRQHandler ;* Handler name for SR CAN0_2 */ - DCD CAN0_3_IRQHandler ;* Handler name for SR CAN0_3 */ - DCD CAN0_4_IRQHandler ;* Handler name for SR CAN0_4 */ - DCD CAN0_5_IRQHandler ;* Handler name for SR CAN0_5 */ - DCD CAN0_6_IRQHandler ;* Handler name for SR CAN0_6 */ - DCD CAN0_7_IRQHandler ;* Handler name for SR CAN0_7 */ - DCD USIC0_0_IRQHandler ;* Handler name for SR USIC0_0 */ - DCD USIC0_1_IRQHandler ;* Handler name for SR USIC0_1 */ - DCD USIC0_2_IRQHandler ;* Handler name for SR USIC0_2 */ - DCD USIC0_3_IRQHandler ;* Handler name for SR USIC0_3 */ - DCD USIC0_4_IRQHandler ;* Handler name for SR USIC0_4 */ - DCD USIC0_5_IRQHandler ;* Handler name for SR USIC0_5 */ - DCD USIC1_0_IRQHandler ;* Handler name for SR USIC1_0 */ - DCD USIC1_1_IRQHandler ;* Handler name for SR USIC1_1 */ - DCD USIC1_2_IRQHandler ;* Handler name for SR USIC1_2 */ - DCD USIC1_3_IRQHandler ;* Handler name for SR USIC1_3 */ - DCD USIC1_4_IRQHandler ;* Handler name for SR USIC1_4 */ - DCD USIC1_5_IRQHandler ;* Handler name for SR USIC1_5 */ - DCD USIC2_0_IRQHandler ;* Handler name for SR USIC2_0 */ - DCD USIC2_1_IRQHandler ;* Handler name for SR USIC2_1 */ - DCD USIC2_2_IRQHandler ;* Handler name for SR USIC2_2 */ - DCD USIC2_3_IRQHandler ;* Handler name for SR USIC2_3 */ - DCD USIC2_4_IRQHandler ;* Handler name for SR USIC2_4 */ - DCD USIC2_5_IRQHandler ;* Handler name for SR USIC2_5 */ - DCD LEDTS0_0_IRQHandler ;* Handler name for SR LEDTS0_0 */ - DCD 0 ;* Not Available */ - DCD FCE0_0_IRQHandler ;* Handler name for SR FCE0_0 */ - DCD GPDMA0_0_IRQHandler ;* Handler name for SR GPDMA0_0 */ - DCD SDMMC0_0_IRQHandler ;* Handler name for SR SDMMC0_0 */ - DCD USB0_0_IRQHandler ;* Handler name for SR USB0_0 */ - DCD ETH0_0_IRQHandler ;* Handler name for SR ETH0_0 */ - DCD 0 ;* Not Available */ - DCD GPDMA1_0_IRQHandler ;* Handler name for SR GPDMA1_0 */ - DCD 0 ;* Not Available */ +
+__Vectors
+ DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+
+ ExcpVector NMI_Handler ; NMI Handler
+ ExcpVector HardFault_Handler ; Hard Fault Handler
+ ExcpVector MemManage_Handler ; MPU Fault Handler
+ ExcpVector BusFault_Handler ; Bus Fault Handler
+ ExcpVector UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ ExcpVector DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; Interrupt Handlers for Service Requests (SR) from XMC4500 Peripherals
+ ExcpVector SCU_0_IRQHandler ; Handler name for SR SCU_0
+ ExcpVector ERU0_0_IRQHandler ; Handler name for SR ERU0_0
+ ExcpVector ERU0_1_IRQHandler ; Handler name for SR ERU0_1
+ ExcpVector ERU0_2_IRQHandler ; Handler name for SR ERU0_2
+ ExcpVector ERU0_3_IRQHandler ; Handler name for SR ERU0_3
+ ExcpVector ERU1_0_IRQHandler ; Handler name for SR ERU1_0
+ ExcpVector ERU1_1_IRQHandler ; Handler name for SR ERU1_1
+ ExcpVector ERU1_2_IRQHandler ; Handler name for SR ERU1_2
+ ExcpVector ERU1_3_IRQHandler ; Handler name for SR ERU1_3
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ ExcpVector PMU0_0_IRQHandler ; Handler name for SR PMU0_0
+ DCD 0 ; Reserved
+ ExcpVector VADC0_C0_0_IRQHandler ; Handler name for SR VADC0_C0_0
+ ExcpVector VADC0_C0_1_IRQHandler ; Handler name for SR VADC0_C0_1
+ ExcpVector VADC0_C0_2_IRQHandler ; Handler name for SR VADC0_C0_1
+ ExcpVector VADC0_C0_3_IRQHandler ; Handler name for SR VADC0_C0_3
+ ExcpVector VADC0_G0_0_IRQHandler ; Handler name for SR VADC0_G0_0
+ ExcpVector VADC0_G0_1_IRQHandler ; Handler name for SR VADC0_G0_1
+ ExcpVector VADC0_G0_2_IRQHandler ; Handler name for SR VADC0_G0_2
+ ExcpVector VADC0_G0_3_IRQHandler ; Handler name for SR VADC0_G0_3
+ ExcpVector VADC0_G1_0_IRQHandler ; Handler name for SR VADC0_G1_0
+ ExcpVector VADC0_G1_1_IRQHandler ; Handler name for SR VADC0_G1_1
+ ExcpVector VADC0_G1_2_IRQHandler ; Handler name for SR VADC0_G1_2
+ ExcpVector VADC0_G1_3_IRQHandler ; Handler name for SR VADC0_G1_3
+ ExcpVector VADC0_G2_0_IRQHandler ; Handler name for SR VADC0_G2_0
+ ExcpVector VADC0_G2_1_IRQHandler ; Handler name for SR VADC0_G2_1
+ ExcpVector VADC0_G2_2_IRQHandler ; Handler name for SR VADC0_G2_2
+ ExcpVector VADC0_G2_3_IRQHandler ; Handler name for SR VADC0_G2_3
+ ExcpVector VADC0_G3_0_IRQHandler ; Handler name for SR VADC0_G3_0
+ ExcpVector VADC0_G3_1_IRQHandler ; Handler name for SR VADC0_G3_1
+ ExcpVector VADC0_G3_2_IRQHandler ; Handler name for SR VADC0_G3_2
+ ExcpVector VADC0_G3_3_IRQHandler ; Handler name for SR VADC0_G3_3
+ ExcpVector DSD0_0_IRQHandler ; Handler name for SR DSD0_0
+ ExcpVector DSD0_1_IRQHandler ; Handler name for SR DSD0_1
+ ExcpVector DSD0_2_IRQHandler ; Handler name for SR DSD0_2
+ ExcpVector DSD0_3_IRQHandler ; Handler name for SR DSD0_3
+ ExcpVector DSD0_4_IRQHandler ; Handler name for SR DSD0_4
+ ExcpVector DSD0_5_IRQHandler ; Handler name for SR DSD0_5
+ ExcpVector DSD0_6_IRQHandler ; Handler name for SR DSD0_6
+ ExcpVector DSD0_7_IRQHandler ; Handler name for SR DSD0_7
+ ExcpVector DAC0_0_IRQHandler ; Handler name for SR DAC0_0
+ ExcpVector DAC0_1_IRQHandler ; Handler name for SR DAC0_1
+ ExcpVector CCU40_0_IRQHandler ; Handler name for SR CCU40_0
+ ExcpVector CCU40_1_IRQHandler ; Handler name for SR CCU40_1
+ ExcpVector CCU40_2_IRQHandler ; Handler name for SR CCU40_2
+ ExcpVector CCU40_3_IRQHandler ; Handler name for SR CCU40_3
+ ExcpVector CCU41_0_IRQHandler ; Handler name for SR CCU41_0
+ ExcpVector CCU41_1_IRQHandler ; Handler name for SR CCU41_1
+ ExcpVector CCU41_2_IRQHandler ; Handler name for SR CCU41_2
+ ExcpVector CCU41_3_IRQHandler ; Handler name for SR CCU41_3
+ ExcpVector CCU42_0_IRQHandler ; Handler name for SR CCU42_0
+ ExcpVector CCU42_1_IRQHandler ; Handler name for SR CCU42_1
+ ExcpVector CCU42_2_IRQHandler ; Handler name for SR CCU42_2
+ ExcpVector CCU42_3_IRQHandler ; Handler name for SR CCU42_3
+ ExcpVector CCU43_0_IRQHandler ; Handler name for SR CCU43_0
+ ExcpVector CCU43_1_IRQHandler ; Handler name for SR CCU43_1
+ ExcpVector CCU43_2_IRQHandler ; Handler name for SR CCU43_2
+ ExcpVector CCU43_3_IRQHandler ; Handler name for SR CCU43_3
+ ExcpVector CCU80_0_IRQHandler ; Handler name for SR CCU80_0
+ ExcpVector CCU80_1_IRQHandler ; Handler name for SR CCU80_1
+ ExcpVector CCU80_2_IRQHandler ; Handler name for SR CCU80_2
+ ExcpVector CCU80_3_IRQHandler ; Handler name for SR CCU80_3
+ ExcpVector CCU81_0_IRQHandler ; Handler name for SR CCU81_0
+ ExcpVector CCU81_1_IRQHandler ; Handler name for SR CCU81_1
+ ExcpVector CCU81_2_IRQHandler ; Handler name for SR CCU81_2
+ ExcpVector CCU81_3_IRQHandler ; Handler name for SR CCU81_3
+ ExcpVector POSIF0_0_IRQHandler ; Handler name for SR POSIF0_0
+ ExcpVector POSIF0_1_IRQHandler ; Handler name for SR POSIF0_1
+ ExcpVector POSIF1_0_IRQHandler ; Handler name for SR POSIF1_0
+ ExcpVector POSIF1_1_IRQHandler ; Handler name for SR POSIF1_1
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ ExcpVector CAN0_0_IRQHandler ; Handler name for SR CAN0_0
+ ExcpVector CAN0_1_IRQHandler ; Handler name for SR CAN0_1
+ ExcpVector CAN0_2_IRQHandler ; Handler name for SR CAN0_2
+ ExcpVector CAN0_3_IRQHandler ; Handler name for SR CAN0_3
+ ExcpVector CAN0_4_IRQHandler ; Handler name for SR CAN0_4
+ ExcpVector CAN0_5_IRQHandler ; Handler name for SR CAN0_5
+ ExcpVector CAN0_6_IRQHandler ; Handler name for SR CAN0_6
+ ExcpVector CAN0_7_IRQHandler ; Handler name for SR CAN0_7
+ ExcpVector USIC0_0_IRQHandler ; Handler name for SR USIC0_0
+ ExcpVector USIC0_1_IRQHandler ; Handler name for SR USIC0_1
+ ExcpVector USIC0_2_IRQHandler ; Handler name for SR USIC0_2
+ ExcpVector USIC0_3_IRQHandler ; Handler name for SR USIC0_3
+ ExcpVector USIC0_4_IRQHandler ; Handler name for SR USIC0_4
+ ExcpVector USIC0_5_IRQHandler ; Handler name for SR USIC0_5
+ ExcpVector USIC1_0_IRQHandler ; Handler name for SR USIC1_0
+ ExcpVector USIC1_1_IRQHandler ; Handler name for SR USIC1_1
+ ExcpVector USIC1_2_IRQHandler ; Handler name for SR USIC1_2
+ ExcpVector USIC1_3_IRQHandler ; Handler name for SR USIC1_3
+ ExcpVector USIC1_4_IRQHandler ; Handler name for SR USIC1_4
+ ExcpVector USIC1_5_IRQHandler ; Handler name for SR USIC1_5
+ ExcpVector USIC2_0_IRQHandler ; Handler name for SR USIC2_0
+ ExcpVector USIC2_1_IRQHandler ; Handler name for SR USIC2_1
+ ExcpVector USIC2_2_IRQHandler ; Handler name for SR USIC2_2
+ ExcpVector USIC2_3_IRQHandler ; Handler name for SR USIC2_3
+ ExcpVector USIC2_4_IRQHandler ; Handler name for SR USIC2_4
+ ExcpVector USIC2_5_IRQHandler ; Handler name for SR USIC2_5
+ ExcpVector LEDTS0_0_IRQHandler ; Handler name for SR LEDTS0_0
+ DCD 0 ; Reserved
+ ExcpVector FCE0_0_IRQHandler ; Handler name for SR FCE0_0
+ ExcpVector GPDMA0_0_IRQHandler ; Handler name for SR GPDMA0_0
+ ExcpVector SDMMC0_0_IRQHandler ; Handler name for SR SDMMC0_0
+ ExcpVector USB0_0_IRQHandler ; Handler name for SR USB0_0
+ ExcpVector ETH0_0_IRQHandler ; Handler name for SR ETH0_0
+ DCD 0 ; Reserved
+ ExcpVector GPDMA1_0_IRQHandler ; Handler name for SR GPDMA1_0
+ DCD 0 ; Reserved
__Vectors_End
-__Vectors_Size EQU __Vectors_End - __Vectors - -;* ================== END OF VECTOR TABLE DEFINITION ======================= */ - +__Vectors_Size EQU __Vectors_End - __Vectors
+
+;* ================== END OF VECTOR TABLE DEFINITION ======================= */
+
;* ================== START OF VECTOR ROUTINES ============================= */
- +
AREA |.text|, CODE, READONLY
- -;* Reset Handler */ +
+;* Reset Handler */
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
+ IMPORT SystemInit
IMPORT __main
- ; Remap vector table - LDR R0, =__Vectors + ; Remap vector table
+ LDR R0, =__Vectors
LDR R1, =0xE000ED08 ;*VTOR register
- STR R0,[R1] - - ; switch off branch prediction required in A11 step to use cached memory - LDR R0,=0x58004000 ;PREF_PCON - LDR R1,[R0] - ORR R1,R1,#0x00010000 - STR R1,[R0]
-
- ; Clear existing parity errors if any required in A11 step - LDR R0,=0x50004150 ;SCU_GCU_PEFLAG - LDR R1,=0xFFFFFFFF - STR R1,[R0] - - ; Disable parity required in A11 step - LDR R0,=0x5000413C ; SCU_GCU_PEEN - MOV R1,#0 - STR R1,[R0] - - ;enable un-aligned memory access
- LDR R1, =0xE000ED14
- LDR.W R0,[R1,#0x0]
- BIC R0,R0,#0x8
- STR.W R0,[R1,#0x0]
-
-
- ;* C routines are likely to be called. Setup the stack now
+ STR R0,[R1]
+
+ ;* C routines are likely to be called. Setup the stack now
LDR SP,=__initial_sp
- - LDR R0, = SystemInit - BLX R0 - -
- ;* Reset stack pointer before zipping off to user application + LDR R0, = SystemInit
+ BLX R0
+
+ ;SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is
+ ;weakly defined here though for a potential override.
+
+ LDR R0, = SystemInit_DAVE3
+ BLX R0
+
+ ;* Reset stack pointer before zipping off to user application
LDR SP,=__initial_sp
- - LDR R0, =__main +
+ LDR R0, =__main
BX R0
+ ALIGN
ENDP
- - -;* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */ - -;* Default exception Handlers - Users may override this default functionality by - -NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
- -;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */ - -;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */ - -;* IRQ Handlers */ - EXPORT SCU_0_IRQHandler [WEAK] - EXPORT ERU0_0_IRQHandler [WEAK] - EXPORT ERU0_1_IRQHandler [WEAK] - EXPORT ERU0_2_IRQHandler [WEAK] - EXPORT ERU0_3_IRQHandler [WEAK] - EXPORT ERU1_0_IRQHandler [WEAK] - EXPORT ERU1_1_IRQHandler [WEAK] - EXPORT ERU1_2_IRQHandler [WEAK] - EXPORT ERU1_3_IRQHandler [WEAK] - EXPORT PMU0_0_IRQHandler [WEAK] - EXPORT VADC0_C0_0_IRQHandler [WEAK] - EXPORT VADC0_C0_1_IRQHandler [WEAK] - EXPORT VADC0_C0_2_IRQHandler [WEAK] - EXPORT VADC0_C0_3_IRQHandler [WEAK] - EXPORT VADC0_G0_0_IRQHandler [WEAK] - EXPORT VADC0_G0_1_IRQHandler [WEAK] - EXPORT VADC0_G0_2_IRQHandler [WEAK] - EXPORT VADC0_G0_3_IRQHandler [WEAK] - EXPORT VADC0_G1_0_IRQHandler [WEAK] - EXPORT VADC0_G1_1_IRQHandler [WEAK] - EXPORT VADC0_G1_2_IRQHandler [WEAK] - EXPORT VADC0_G1_3_IRQHandler [WEAK] - EXPORT VADC0_G2_0_IRQHandler [WEAK] - EXPORT VADC0_G2_1_IRQHandler [WEAK] - EXPORT VADC0_G2_2_IRQHandler [WEAK] - EXPORT VADC0_G2_3_IRQHandler [WEAK] - EXPORT VADC0_G3_0_IRQHandler [WEAK] - EXPORT VADC0_G3_1_IRQHandler [WEAK] - EXPORT VADC0_G3_2_IRQHandler [WEAK] - EXPORT VADC0_G3_3_IRQHandler [WEAK] - EXPORT DSD0_0_IRQHandler [WEAK] - EXPORT DSD0_1_IRQHandler [WEAK] - EXPORT DSD0_2_IRQHandler [WEAK] - EXPORT DSD0_3_IRQHandler [WEAK] - EXPORT DSD0_4_IRQHandler [WEAK] - EXPORT DSD0_5_IRQHandler [WEAK] - EXPORT DSD0_6_IRQHandler [WEAK] - EXPORT DSD0_7_IRQHandler [WEAK] - EXPORT DAC0_0_IRQHandler [WEAK] - EXPORT DAC0_1_IRQHandler [WEAK] - EXPORT CCU40_0_IRQHandler [WEAK] - EXPORT CCU40_1_IRQHandler [WEAK] - EXPORT CCU40_2_IRQHandler [WEAK] - EXPORT CCU40_3_IRQHandler [WEAK] - EXPORT CCU41_0_IRQHandler [WEAK] - EXPORT CCU41_1_IRQHandler [WEAK] - EXPORT CCU41_2_IRQHandler [WEAK] - EXPORT CCU41_3_IRQHandler [WEAK] - EXPORT CCU42_0_IRQHandler [WEAK] - EXPORT CCU42_1_IRQHandler [WEAK] - EXPORT CCU42_2_IRQHandler [WEAK] - EXPORT CCU42_3_IRQHandler [WEAK] - EXPORT CCU43_0_IRQHandler [WEAK] - EXPORT CCU43_1_IRQHandler [WEAK] - EXPORT CCU43_2_IRQHandler [WEAK] - EXPORT CCU43_3_IRQHandler [WEAK] - EXPORT CCU80_0_IRQHandler [WEAK] - EXPORT CCU80_1_IRQHandler [WEAK] - EXPORT CCU80_2_IRQHandler [WEAK] - EXPORT CCU80_3_IRQHandler [WEAK] - EXPORT CCU81_0_IRQHandler [WEAK] - EXPORT CCU81_1_IRQHandler [WEAK] - EXPORT CCU81_2_IRQHandler [WEAK] - EXPORT CCU81_3_IRQHandler [WEAK] - EXPORT POSIF0_0_IRQHandler [WEAK] - EXPORT POSIF0_1_IRQHandler [WEAK] - EXPORT POSIF1_0_IRQHandler [WEAK] - EXPORT POSIF1_1_IRQHandler [WEAK] - EXPORT CAN0_0_IRQHandler [WEAK] - EXPORT CAN0_1_IRQHandler [WEAK] - EXPORT CAN0_2_IRQHandler [WEAK] - EXPORT CAN0_3_IRQHandler [WEAK] - EXPORT CAN0_4_IRQHandler [WEAK] - EXPORT CAN0_5_IRQHandler [WEAK] - EXPORT CAN0_6_IRQHandler [WEAK] - EXPORT CAN0_7_IRQHandler [WEAK] - EXPORT USIC0_0_IRQHandler [WEAK] - EXPORT USIC0_1_IRQHandler [WEAK] - EXPORT USIC0_2_IRQHandler [WEAK] - EXPORT USIC0_3_IRQHandler [WEAK] - EXPORT USIC0_4_IRQHandler [WEAK] - EXPORT USIC0_5_IRQHandler [WEAK] - EXPORT USIC1_0_IRQHandler [WEAK] - EXPORT USIC1_1_IRQHandler [WEAK] - EXPORT USIC1_2_IRQHandler [WEAK] - EXPORT USIC1_3_IRQHandler [WEAK] - EXPORT USIC1_4_IRQHandler [WEAK] - EXPORT USIC1_5_IRQHandler [WEAK] - EXPORT USIC2_0_IRQHandler [WEAK] - EXPORT USIC2_1_IRQHandler [WEAK] - EXPORT USIC2_2_IRQHandler [WEAK] - EXPORT USIC2_3_IRQHandler [WEAK] - EXPORT USIC2_4_IRQHandler [WEAK] - EXPORT USIC2_5_IRQHandler [WEAK] - EXPORT LEDTS0_0_IRQHandler [WEAK] - EXPORT FCE0_0_IRQHandler [WEAK] - EXPORT GPDMA0_0_IRQHandler [WEAK] - EXPORT SDMMC0_0_IRQHandler [WEAK] - EXPORT USB0_0_IRQHandler [WEAK] - EXPORT ETH0_0_IRQHandler [WEAK] - EXPORT GPDMA1_0_IRQHandler [WEAK]
-
- -SCU_0_IRQHandler -ERU0_0_IRQHandler -ERU0_1_IRQHandler -ERU0_2_IRQHandler -ERU0_3_IRQHandler -ERU1_0_IRQHandler -ERU1_1_IRQHandler -ERU1_2_IRQHandler -ERU1_3_IRQHandler -PMU0_0_IRQHandler -VADC0_C0_0_IRQHandler -VADC0_C0_1_IRQHandler -VADC0_C0_2_IRQHandler -VADC0_C0_3_IRQHandler -VADC0_G0_0_IRQHandler -VADC0_G0_1_IRQHandler -VADC0_G0_2_IRQHandler -VADC0_G0_3_IRQHandler -VADC0_G1_0_IRQHandler -VADC0_G1_1_IRQHandler -VADC0_G1_2_IRQHandler -VADC0_G1_3_IRQHandler -VADC0_G2_0_IRQHandler -VADC0_G2_1_IRQHandler -VADC0_G2_2_IRQHandler -VADC0_G2_3_IRQHandler -VADC0_G3_0_IRQHandler -VADC0_G3_1_IRQHandler -VADC0_G3_2_IRQHandler -VADC0_G3_3_IRQHandler -DSD0_0_IRQHandler -DSD0_1_IRQHandler -DSD0_2_IRQHandler -DSD0_3_IRQHandler -DSD0_4_IRQHandler -DSD0_5_IRQHandler -DSD0_6_IRQHandler -DSD0_7_IRQHandler -DAC0_0_IRQHandler -DAC0_1_IRQHandler -CCU40_0_IRQHandler -CCU40_1_IRQHandler -CCU40_2_IRQHandler -CCU40_3_IRQHandler -CCU41_0_IRQHandler -CCU41_1_IRQHandler -CCU41_2_IRQHandler -CCU41_3_IRQHandler -CCU42_0_IRQHandler -CCU42_1_IRQHandler -CCU42_2_IRQHandler -CCU42_3_IRQHandler -CCU43_0_IRQHandler -CCU43_1_IRQHandler -CCU43_2_IRQHandler -CCU43_3_IRQHandler -CCU80_0_IRQHandler -CCU80_1_IRQHandler -CCU80_2_IRQHandler -CCU80_3_IRQHandler -CCU81_0_IRQHandler -CCU81_1_IRQHandler -CCU81_2_IRQHandler -CCU81_3_IRQHandler -POSIF0_0_IRQHandler -POSIF0_1_IRQHandler -POSIF1_0_IRQHandler -POSIF1_1_IRQHandler -CAN0_0_IRQHandler -CAN0_1_IRQHandler -CAN0_2_IRQHandler -CAN0_3_IRQHandler -CAN0_4_IRQHandler -CAN0_5_IRQHandler -CAN0_6_IRQHandler -CAN0_7_IRQHandler -USIC0_0_IRQHandler -USIC0_1_IRQHandler -USIC0_2_IRQHandler -USIC0_3_IRQHandler -USIC0_4_IRQHandler -USIC0_5_IRQHandler -USIC1_0_IRQHandler -USIC1_1_IRQHandler -USIC1_2_IRQHandler -USIC1_3_IRQHandler -USIC1_4_IRQHandler -USIC1_5_IRQHandler -USIC2_0_IRQHandler -USIC2_1_IRQHandler -USIC2_2_IRQHandler -USIC2_3_IRQHandler -USIC2_4_IRQHandler -USIC2_5_IRQHandler -LEDTS0_0_IRQHandler -FCE0_0_IRQHandler -GPDMA0_0_IRQHandler -SDMMC0_0_IRQHandler -USB0_0_IRQHandler -ETH0_0_IRQHandler -GPDMA1_0_IRQHandler
- - -;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */ - -;* Definition of the default weak SystemInit_DAVE3 function. -;* This function will be called by the CMSIS SystemInit function. -;* If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3 -;* which will overule this weak definition - -;*SystemInit_DAVE3 -;* NOP -;* BX LR - +
+
+
+
+;* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */
+
+
+
+;/* Default exception Handlers - Users may override this default functionality by
+; defining handlers of the same name in their C code */
+
+ ExcpHandler NMI_Handler
+ ExcpHandler HardFault_Handler
+ ExcpHandler MemManage_Handler
+ ExcpHandler BusFault_Handler
+ ExcpHandler UsageFault_Handler
+ ExcpHandler SVC_Handler
+ ExcpHandler DebugMon_Handler
+ ExcpHandler PendSV_Handler
+ ExcpHandler SysTick_Handler
+
+;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */
+
+;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */
+
+;* IRQ Handlers */
+ ExcpHandler SCU_0_IRQHandler
+ ExcpHandler ERU0_0_IRQHandler
+ ExcpHandler ERU0_1_IRQHandler
+ ExcpHandler ERU0_2_IRQHandler
+ ExcpHandler ERU0_3_IRQHandler
+ ExcpHandler ERU1_0_IRQHandler
+ ExcpHandler ERU1_1_IRQHandler
+ ExcpHandler ERU1_2_IRQHandler
+ ExcpHandler ERU1_3_IRQHandler
+ ExcpHandler PMU0_0_IRQHandler
+ ExcpHandler VADC0_C0_0_IRQHandler
+ ExcpHandler VADC0_C0_1_IRQHandler
+ ExcpHandler VADC0_C0_2_IRQHandler
+ ExcpHandler VADC0_C0_3_IRQHandler
+ ExcpHandler VADC0_G0_0_IRQHandler
+ ExcpHandler VADC0_G0_1_IRQHandler
+ ExcpHandler VADC0_G0_2_IRQHandler
+ ExcpHandler VADC0_G0_3_IRQHandler
+ ExcpHandler VADC0_G1_0_IRQHandler
+ ExcpHandler VADC0_G1_1_IRQHandler
+ ExcpHandler VADC0_G1_2_IRQHandler
+ ExcpHandler VADC0_G1_3_IRQHandler
+ ExcpHandler VADC0_G2_0_IRQHandler
+ ExcpHandler VADC0_G2_1_IRQHandler
+ ExcpHandler VADC0_G2_2_IRQHandler
+ ExcpHandler VADC0_G2_3_IRQHandler
+ ExcpHandler VADC0_G3_0_IRQHandler
+ ExcpHandler VADC0_G3_1_IRQHandler
+ ExcpHandler VADC0_G3_2_IRQHandler
+ ExcpHandler VADC0_G3_3_IRQHandler
+ ExcpHandler DSD0_0_IRQHandler
+ ExcpHandler DSD0_1_IRQHandler
+ ExcpHandler DSD0_2_IRQHandler
+ ExcpHandler DSD0_3_IRQHandler
+ ExcpHandler DSD0_4_IRQHandler
+ ExcpHandler DSD0_5_IRQHandler
+ ExcpHandler DSD0_6_IRQHandler
+ ExcpHandler DSD0_7_IRQHandler
+ ExcpHandler DAC0_0_IRQHandler
+ ExcpHandler DAC0_1_IRQHandler
+ ExcpHandler CCU40_0_IRQHandler
+ ExcpHandler CCU40_1_IRQHandler
+ ExcpHandler CCU40_2_IRQHandler
+ ExcpHandler CCU40_3_IRQHandler
+ ExcpHandler CCU41_0_IRQHandler
+ ExcpHandler CCU41_1_IRQHandler
+ ExcpHandler CCU41_2_IRQHandler
+ ExcpHandler CCU41_3_IRQHandler
+ ExcpHandler CCU42_0_IRQHandler
+ ExcpHandler CCU42_1_IRQHandler
+ ExcpHandler CCU42_2_IRQHandler
+ ExcpHandler CCU42_3_IRQHandler
+ ExcpHandler CCU43_0_IRQHandler
+ ExcpHandler CCU43_1_IRQHandler
+ ExcpHandler CCU43_2_IRQHandler
+ ExcpHandler CCU43_3_IRQHandler
+ ExcpHandler CCU80_0_IRQHandler
+ ExcpHandler CCU80_1_IRQHandler
+ ExcpHandler CCU80_2_IRQHandler
+ ExcpHandler CCU80_3_IRQHandler
+ ExcpHandler CCU81_0_IRQHandler
+ ExcpHandler CCU81_1_IRQHandler
+ ExcpHandler CCU81_2_IRQHandler
+ ExcpHandler CCU81_3_IRQHandler
+ ExcpHandler POSIF0_0_IRQHandler
+ ExcpHandler POSIF0_1_IRQHandler
+ ExcpHandler POSIF1_0_IRQHandler
+ ExcpHandler POSIF1_1_IRQHandler
+ ExcpHandler CAN0_0_IRQHandler
+ ExcpHandler CAN0_1_IRQHandler
+ ExcpHandler CAN0_2_IRQHandler
+ ExcpHandler CAN0_3_IRQHandler
+ ExcpHandler CAN0_4_IRQHandler
+ ExcpHandler CAN0_5_IRQHandler
+ ExcpHandler CAN0_6_IRQHandler
+ ExcpHandler CAN0_7_IRQHandler
+ ExcpHandler USIC0_0_IRQHandler
+ ExcpHandler USIC0_1_IRQHandler
+ ExcpHandler USIC0_2_IRQHandler
+ ExcpHandler USIC0_3_IRQHandler
+ ExcpHandler USIC0_4_IRQHandler
+ ExcpHandler USIC0_5_IRQHandler
+ ExcpHandler USIC1_0_IRQHandler
+ ExcpHandler USIC1_1_IRQHandler
+ ExcpHandler USIC1_2_IRQHandler
+ ExcpHandler USIC1_3_IRQHandler
+ ExcpHandler USIC1_4_IRQHandler
+ ExcpHandler USIC1_5_IRQHandler
+ ExcpHandler USIC2_0_IRQHandler
+ ExcpHandler USIC2_1_IRQHandler
+ ExcpHandler USIC2_2_IRQHandler
+ ExcpHandler USIC2_3_IRQHandler
+ ExcpHandler USIC2_4_IRQHandler
+ ExcpHandler USIC2_5_IRQHandler
+ ExcpHandler LEDTS0_0_IRQHandler
+ ExcpHandler FCE0_0_IRQHandler
+ ExcpHandler GPDMA0_0_IRQHandler
+ ExcpHandler SDMMC0_0_IRQHandler
+ ExcpHandler USB0_0_IRQHandler
+ ExcpHandler ETH0_0_IRQHandler
+ ExcpHandler GPDMA1_0_IRQHandler
+
+;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */
+
+;* Definition of the default weak SystemInit_DAVE3 function.
+;* This function will be called by the CMSIS SystemInit function.
+;* If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3
+;* which will overule this weak definition
+SystemInit_DAVE3 PROC
+ EXPORT SystemInit_DAVE3 [WEAK]
+ NOP
+ BX LR
+ ENDP
+
+;* Definition of the default weak DAVE3 function for clock App usage.
+;* AllowPLLInitByStartup Handler */
+AllowPLLInitByStartup PROC
+ EXPORT AllowPLLInitByStartup [WEAK]
+ MOV R0,#1
+ BX LR
+ ENDP
+
+ ALIGN
+
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
- IF :DEF:__MICROLIB
-
+ IF :DEF:__MICROLIB
+
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
-
+
ELSE
-
+
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
-
+
__user_initial_stackheap
LDR R0, = Heap_Mem
@@ -544,12 +482,10 @@ __user_initial_stackheap LDR R3, = Stack_Mem
BX LR
+ ALIGN
ENDIF
- ALIGN
END
-;******************* (C) COPYRIGHT 2011 Infineon Techonlogies *****END OF FILE*****
-
- +;******************* Copyright (C) 2009-2013 ARM Limited *****END OF FILE*****
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/system_XMC4200.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/system_XMC4200.c new file mode 100644 index 000000000..4b7f348f2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/system_XMC4200.c @@ -0,0 +1,708 @@ +/**************************************************************************//**
+ * @file system_XMC4200.c
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File
+ * for the Infineon XMC4000 Device Series
+ * @version V3.0.1 Alpha
+ * @date 26. September 2012
+ *
+ * @note
+ * Copyright (C) 2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include <system_XMC4200.h>
+#include <XMC4200.h>
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+/*!< System Clock Frequency (Core Clock)*/
+uint32_t SystemCoreClock;
+
+/* clock definitions, do not modify! */
+#define SCU_CLOCK_CRYSTAL 1
+#define SCU_CLOCK_BACK_UP_FACTORY 2
+#define SCU_CLOCK_BACK_UP_AUTOMATIC 3
+
+
+#define HIB_CLOCK_FOSI 1
+#define HIB_CLOCK_OSCULP 2
+
+
+
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+
+
+/*--------------------- Watchdog Configuration -------------------------------
+//
+// <e> Watchdog Configuration
+// <o1.0> Disable Watchdog
+//
+// </e>
+*/
+#define WDT_SETUP 1
+#define WDTENB_nVal 0x00000001
+
+/*--------------------- CLOCK Configuration -------------------------------
+//
+// <e> Main Clock Configuration
+// <o1.0..1> CPU clock divider
+// <0=> fCPU = fSYS
+// <1=> fCPU = fSYS / 2
+// <o2.0..1> Peripheral Bus clock divider
+// <0=> fPB = fCPU
+// <1=> fPB = fCPU / 2
+// <o3.0..1> CCU Bus clock divider
+// <0=> fCCU = fCPU
+// <1=> fCCU = fCPU / 2
+//
+// </e>
+//
+*/
+
+#define SCU_CLOCK_SETUP 1
+#define SCU_CPUCLKCR_DIV 0x00000000
+#define SCU_PBCLKCR_DIV 0x00000000
+#define SCU_CCUCLKCR_DIV 0x00000000
+/* not avalible in config wizzard*/
+/*
+* mandatory clock parameters **************************************************
+*
+* source for clock generation
+* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input)
+*
+**************************************************************************************/
+// Selection of imput lock for PLL
+/*************************************************************************************/
+#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL
+//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY
+//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC
+
+/*************************************************************************************/
+// Standby clock selection for Backup clock source trimming
+/*************************************************************************************/
+#define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP
+//#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI
+
+/*************************************************************************************/
+// Global clock parameters
+/*************************************************************************************/
+#define CLOCK_FSYS 80000000
+#define CLOCK_CRYSTAL_FREQUENCY 12000000
+#define CLOCK_BACK_UP 24000000
+
+/*************************************************************************************/
+/* OSC_HP setup parameters */
+/*************************************************************************************/
+#define SCU_OSC_HP_MODE 0xF0
+#define SCU_OSCHPWDGDIV 2
+
+/*************************************************************************************/
+/* MAIN PLL setup parameters */
+/*************************************************************************************/
+//Divider settings for external crystal @ 12 MHz
+/*************************************************************************************/
+#define SCU_PLL_K1DIV 1
+#define SCU_PLL_K1DIV 1
+#define SCU_PLL_K2DIV 5
+#define SCU_PLL_PDIV 1
+#define SCU_PLL_NDIV 79
+
+/*************************************************************************************/
+//Divider settings for use of backup clock source trimmed
+/*************************************************************************************/
+//#define SCU_PLL_K1DIV 1
+//#define SCU_PLL_K2DIV 5
+//#define SCU_PLL_PDIV 3
+//#define SCU_PLL_NDIV 79
+/*************************************************************************************/
+
+
+/*--------------------- USB CLOCK Configuration ---------------------------
+//
+// <e> USB Clock Configuration
+//
+// </e>
+//
+*/
+
+#define SCU_USB_CLOCK_SETUP 0
+/* not avalible in config wizzard*/
+#define SCU_USBPLL_PDIV 0
+#define SCU_USBPLL_NDIV 31
+#define SCU_USBDIV 3
+
+/*--------------------- Flash Wait State Configuration -------------------------------
+//
+// <e> Flash Wait State Configuration
+// <o1.0..3> Flash Wait State
+// <0=> 3 WS
+// <1=> 4 WS
+// <2=> 5 WS
+// <3=> 6 WS
+// </e>
+//
+*/
+
+#define PMU_FLASH 1
+#define PMU_FLASH_WS 0x00000000
+
+
+/*--------------------- CLOCKOUT Configuration -------------------------------
+//
+// <e> Clock OUT Configuration
+// <o1.0..1> Clockout Source Selection
+// <0=> System Clock
+// <2=> Divided value of USB PLL output
+// <3=> Divided value of PLL Clock
+// <o2.0..4> Clockout divider <1-10><#-1>
+// <o3.0..1> Clockout Pin Selection
+// <0=> P1.15
+// <1=> P0.8
+//
+//
+// </e>
+//
+*/
+
+#define SCU_CLOCKOUT_SETUP 0
+#define SCU_CLOCKOUT_SOURCE 0x00000000
+#define SCU_CLOCKOUT_DIV 0x00000009
+#define SCU_CLOCKOUT_PIN 0x00000001
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+/*!< System Clock Frequency (Core Clock)*/
+#if SCU_CLOCK_SETUP
+uint32_t SystemCoreClock = CLOCK_FSYS;
+#else
+uint32_t SystemCoreClock = CLOCK_BACK_UP;
+#endif
+
+/*----------------------------------------------------------------------------
+ static functions declarations
+ *----------------------------------------------------------------------------*/
+#if (SCU_CLOCK_SETUP == 1)
+static int SystemClockSetup(void);
+#endif
+
+#if (SCU_USB_CLOCK_SETUP == 1)
+static int USBClockSetup(void);
+#endif
+
+
+/**
+ * @brief Setup the microcontroller system.
+ * Initialize the PLL and update the
+ * SystemCoreClock variable.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+int temp;
+
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
+ (3UL << 11*2) ); /* set CP11 Full Access */
+#endif
+
+/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */
+SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);
+
+/* Setup the WDT */
+#if WDT_SETUP
+
+WDT->CTR &= ~WDTENB_nVal;
+
+#endif
+
+
+/* Setup the Flash Wait State */
+#if PMU_FLASH
+temp = FLASH0->FCON;
+temp &= ~FLASH_FCON_WSPFLASH_Msk;
+temp |= PMU_FLASH_WS+3;
+FLASH0->FCON = temp;
+#endif
+
+
+/* Setup the clockout */
+#if SCU_CLOCKOUT_SETUP
+
+SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE;
+/*set PLL div for clkout */
+SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16;
+
+if (SCU_CLOCKOUT_PIN) {
+ PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */
+ PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);
+ PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */
+ }
+else {
+ PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */
+ PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */
+ }
+
+#endif
+
+
+/* Setup the System clock */
+#if SCU_CLOCK_SETUP
+SystemClockSetup();
+#endif
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/
+
+
+/* Setup the USB PL */
+#if SCU_USB_CLOCK_SETUP
+USBClockSetup();
+#endif
+
+
+
+}
+
+
+/**
+ * @brief Update SystemCoreClock according to Clock Register Values
+ * @note -
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate(void)
+{
+unsigned int PDIV;
+unsigned int NDIV;
+unsigned int K2DIV;
+unsigned int long VCO;
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+if (SCU_CLK->SYSCLKCR == 0x00010000)
+{
+ if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){
+ /* check if PLL is locked */
+ /* read back divider settings */
+ PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1;
+ NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1;
+ K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1;
+
+ if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){
+ /* the selected clock is the Backup clock fofi */
+ VCO = (CLOCK_BACK_UP/PDIV)*NDIV;
+ SystemCoreClock = VCO/K2DIV;
+ /* in case the sysclock div is used */
+ SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);
+
+ }
+ else
+ {
+ /* the selected clock is the PLL external oscillator */
+ VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV;
+ SystemCoreClock = VCO/K2DIV;
+ /* in case the sysclock div is used */
+ SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);
+ }
+
+
+ }
+}
+else
+{
+SystemCoreClock = CLOCK_BACK_UP;
+}
+
+
+}
+
+
+/**
+ * @brief -
+ * @note -
+ * @param None
+ * @retval None
+ */
+#if (SCU_CLOCK_SETUP == 1)
+static int SystemClockSetup(void)
+{
+int temp;
+unsigned int long VCO;
+int stepping_K2DIV;
+
+/* this weak function enables DAVE3 clock App usage */
+if(AllowPLLInitByStartup()){
+
+/* check if PLL is switched on */
+if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){
+/* enable PLL first */
+ SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
+
+}
+
+/* Enable OSC_HP if not already on*/
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)
+ {
+ /********************************************************************************************************************/
+ /* Use external crystal for PLL clock input */
+ /********************************************************************************************************************/
+
+ if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){
+ SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/
+ /* setup OSC WDG devider */
+ SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);
+ /* select external OSC as PLL input */
+ SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;
+ /* restart OSC Watchdog */
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
+
+ /* Timeout for wait loop ~150ms */
+ /********************************/
+ SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ do
+ {
+ ;/* wait for ~150ms */
+ }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));
+
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
+ if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)
+ return(0);/* Return Error */
+
+ }
+ }
+ else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)
+ {
+ /********************************************************************************************************************/
+ /* Use factory trimming Back-up clock for PLL clock input */
+ /********************************************************************************************************************/
+ /* PLL Back up clock selected */
+ SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
+
+ }
+ else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC)
+ {
+ /********************************************************************************************************************/
+ /* Use automatic trimming Back-up clock for PLL clock input */
+ /********************************************************************************************************************/
+ /* check for HIB Domain enabled */
+ if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)
+ SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/
+
+ /* check for HIB Domain is not in reset state */
+ if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1)
+ SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/
+
+ /* PLL Back up clock selected */
+ SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
+
+ if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI)
+ {
+ /****************************************************************************************************************/
+ /* Use fOSI as source of the standby clock */
+ /****************************************************************************************************************/
+ SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
+
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;
+ for(temp=0;temp<=0xFFFF;temp++);
+
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
+ }
+ else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP)
+ {
+ /****************************************************************************************************************/
+ /* Use fULP as source of the standby clock */
+ /****************************************************************************************************************/
+ /*check OSCUL if running correct*/
+ if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0)
+ {
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk);
+
+ SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/
+ /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/
+ /* select OSCUL clock for RTC*/
+ SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk;
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
+ /*enable OSCULP WDG Alarm Enable*/
+ SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
+ /*wait now for clock is stable */
+ do
+ {
+ SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);
+ for(temp=0;temp<=0xFFFF;temp++);
+ }
+ while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk);
+
+ SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);
+ }
+ // now OSCULP is running and can be used
+ SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
+
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;
+ /*TRIAL for delay loop*/
+ for(temp=0;temp<=0xFFFF;temp++);
+
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
+ /*TRIAL for delay loop*/
+ for(temp=0;temp<=0xFFFF;temp++);
+
+ }
+ }
+
+ /********************************************************************************************************************/
+ /* Setup and look the main PLL */
+ /********************************************************************************************************************/
+
+if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){
+ /* Systen is still running from internal clock */
+ /* select FOFI as system clock */
+ if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/
+
+
+ /*calulation for stepping*/
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+ if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
+ VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+
+ stepping_K2DIV = (VCO/24000000)-1;
+ /* Go to bypass the Main PLL */
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;
+ /* disconnect OSC_HP to PLL */
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;
+ /* Setup devider settings for main PLL */
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
+ /* we may have to set OSCDISCDIS */
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
+ /* connect OSC_HP to PLL */
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;
+ /* restart PLL Lock detection */
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;
+ /* wait for PLL Lock */
+ /* setup time out loop */
+ /* Timeout for wait loo ~150ms */
+ /********************************/
+ SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+
+ while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500));
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
+
+ if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk)
+ {
+ /* Go back to the Main PLL */
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;
+ }
+ else return(0);
+
+
+ /*********************************************************
+ here we need to setup the system clock divider
+ *********************************************************/
+
+ SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;
+ SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV;
+ SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;
+
+
+ /* Switch system clock to PLL */
+ SCU_CLK->SYSCLKCR |= 0x00010000;
+
+ /* we may have to reset OSCDISCDIS */
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
+
+
+ /*********************************************************/
+ /* Delay for next K2 step ~50µs */
+ /*********************************************************/
+ SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+
+ while (SysTick->VAL >= 100); /* wait for ~50µs */
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
+ /*********************************************************/
+
+ /*********************************************************
+ here the ramp up of the system clock starts FSys < 60MHz
+ *********************************************************/
+ if (CLOCK_FSYS > 60000000){
+ /*calulation for stepping*/
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+ if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
+ VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+
+ stepping_K2DIV = (VCO/60000000)-1;
+
+ /* Setup devider settings for main PLL */
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
+ }
+ else
+ {
+ /* Setup devider settings for main PLL */
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
+ SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
+ return(1);
+ }
+
+ /*********************************************************/
+ /* Delay for next K2 step ~50µs */
+ /*********************************************************/
+ SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+
+ while (SysTick->VAL >= 100); /* wait for ~50µs */
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
+ /********************************/
+
+ /*********************************************************
+ here the ramp up of the system clock starts FSys < 90MHz
+ *********************************************************/
+ if (CLOCK_FSYS > 90000000){
+ /*calulation for stepping*/
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+ if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
+ VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+
+ stepping_K2DIV = (VCO/90000000)-1;
+
+ /* Setup devider settings for main PLL */
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
+ }
+ else
+ {
+ /* Setup devider settings for main PLL */
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
+ SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
+ return(1);
+ }
+
+ /*********************************************************/
+ /* Delay for next K2 step ~50µs */
+ /*********************************************************/
+ SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+
+ while (SysTick->VAL >= 100); /* wait for ~50µs */
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
+ /********************************/
+
+ /* Setup devider settings for main PLL */
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
+
+ SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
+ }
+ }/* end this weak function enables DAVE3 clock App usage */
+ return(1);
+
+}
+#endif
+
+/**
+ * @brief -
+ * @note -
+ * @param None
+ * @retval None
+ */
+#if (SCU_USB_CLOCK_SETUP == 1)
+static int USBClockSetup(void)
+{
+/* this weak function enables DAVE3 clock App usage */
+if(AllowPLLInitByStartup()){
+
+/* check if PLL is switched on */
+if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){
+ /* enable PLL first */
+ SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);
+}
+
+/* check and if not already running enable OSC_HP */
+ if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){
+ /* check if Main PLL is switched on for OSC WD*/
+ if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){
+ /* enable PLL first */
+ SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
+ }
+ SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/
+ /* setup OSC WDG devider */
+ SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);
+ /* restart OSC Watchdog */
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
+
+ /* Timeout for wait loop ~150ms */
+ /********************************/
+ SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ do
+ {
+ ;/* wait for ~150ms */
+ }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));
+
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
+ if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)
+ return(0);/* Return Error */
+
+ }
+
+
+/* Setup USB PLL */
+ /* Go to bypass the Main PLL */
+ SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;
+ /* disconnect OSC_FI to PLL */
+ SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;
+ /* Setup devider settings for main PLL */
+ SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24));
+ /* Setup USBDIV settings USB clock */
+ SCU_CLK->USBCLKCR = SCU_USBDIV;
+ /* we may have to set OSCDISCDIS */
+ SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;
+ /* connect OSC_FI to PLL */
+ SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;
+ /* restart PLL Lock detection */
+ SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;
+ /* wait for PLL Lock */
+ while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk));
+
+ }/* end this weak function enables DAVE3 clock App usage */
+ return(1);
+
+}
+#endif
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/system_XMC4200.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/system_XMC4200.h new file mode 100644 index 000000000..33d38c1a7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/system_XMC4200.h @@ -0,0 +1,72 @@ +/**************************************************************************//**
+ * @file system_XMC4200.h
+ * @brief Header file for the XMC4200-Series systeminit
+ *
+ * @version V1.0
+ * @date 27. August 2012
+ *
+ * @note
+ * Copyright (C) 2011 Infineon Technologies AG. All rights reserved.
+
+ *
+ * @par
+ * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers.
+ * This file can be freely distributed within development tools that are supporting such microcontrollers.
+
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_XMC4200_H
+#define __SYSTEM_XMC4200_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+extern void SystemInit (void);
+
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/* this weak function enables DAVE3 clock App usage */
+extern uint32_t AllowPLLInitByStartup(void);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/system_XMC4400.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/system_XMC4400.c new file mode 100644 index 000000000..dfbbf9e8d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/system_XMC4400.c @@ -0,0 +1,707 @@ +/**************************************************************************//**
+ * @file system_XMC4400.c
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File
+ * for the Infineon XMC4500 Device Series
+ * @version V3.0.1 Alpha
+ * @date 17. September 2012
+ *
+ * @note
+ * Copyright (C) 2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include <system_XMC4400.h>
+#include <XMC4400.h>
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+/*!< System Clock Frequency (Core Clock)*/
+uint32_t SystemCoreClock;
+
+/* clock definitions, do not modify! */
+#define SCU_CLOCK_CRYSTAL 1
+#define SCU_CLOCK_BACK_UP_FACTORY 2
+#define SCU_CLOCK_BACK_UP_AUTOMATIC 3
+
+
+#define HIB_CLOCK_FOSI 1
+#define HIB_CLOCK_OSCULP 2
+
+
+
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+
+
+/*--------------------- Watchdog Configuration -------------------------------
+//
+// <e> Watchdog Configuration
+// <o1.0> Disable Watchdog
+//
+// </e>
+*/
+#define WDT_SETUP 1
+#define WDTENB_nVal 0x00000001
+
+/*--------------------- CLOCK Configuration -------------------------------
+//
+// <e> Main Clock Configuration
+// <o1.0..1> CPU clock divider
+// <0=> fCPU = fSYS
+// <1=> fCPU = fSYS / 2
+// <o2.0..1> Peripheral Bus clock divider
+// <0=> fPB = fCPU
+// <1=> fPB = fCPU / 2
+// <o3.0..1> CCU Bus clock divider
+// <0=> fCCU = fCPU
+// <1=> fCCU = fCPU / 2
+//
+// </e>
+//
+*/
+
+#define SCU_CLOCK_SETUP 1
+#define SCU_CPUCLKCR_DIV 0x00000000
+#define SCU_PBCLKCR_DIV 0x00000000
+#define SCU_CCUCLKCR_DIV 0x00000000
+/* not avalible in config wizzard*/
+/*
+* mandatory clock parameters **************************************************
+*
+* source for clock generation
+* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input)
+*
+**************************************************************************************/
+// Selection of imput lock for PLL
+/*************************************************************************************/
+#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL
+//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY
+//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC
+
+/*************************************************************************************/
+// Standby clock selection for Backup clock source trimming
+/*************************************************************************************/
+#define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP
+//#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI
+
+/*************************************************************************************/
+// Global clock parameters
+/*************************************************************************************/
+#define CLOCK_FSYS 120000000
+#define CLOCK_CRYSTAL_FREQUENCY 12000000
+#define CLOCK_BACK_UP 24000000
+
+/*************************************************************************************/
+/* OSC_HP setup parameters */
+/*************************************************************************************/
+#define SCU_OSC_HP_MODE 0xF0
+#define SCU_OSCHPWDGDIV 2
+
+/*************************************************************************************/
+/* MAIN PLL setup parameters */
+/*************************************************************************************/
+//Divider settings for external crystal @ 12 MHz
+/*************************************************************************************/
+#define SCU_PLL_K1DIV 1
+#define SCU_PLL_K2DIV 3
+#define SCU_PLL_PDIV 1
+#define SCU_PLL_NDIV 79
+
+/*************************************************************************************/
+//Divider settings for use of backup clock source trimmed
+/*************************************************************************************/
+//#define SCU_PLL_K1DIV 1
+//#define SCU_PLL_K2DIV 3
+//#define SCU_PLL_PDIV 3
+//#define SCU_PLL_NDIV 79
+/*************************************************************************************/
+
+
+/*--------------------- USB CLOCK Configuration ---------------------------
+//
+// <e> USB Clock Configuration
+//
+// </e>
+//
+*/
+
+#define SCU_USB_CLOCK_SETUP 0
+/* not avalible in config wizzard*/
+#define SCU_USBPLL_PDIV 0
+#define SCU_USBPLL_NDIV 31
+#define SCU_USBDIV 3
+
+/*--------------------- Flash Wait State Configuration -------------------------------
+//
+// <e> Flash Wait State Configuration
+// <o1.0..3> Flash Wait State
+// <0=> 3 WS
+// <1=> 4 WS
+// <2=> 5 WS
+// <3=> 6 WS
+// </e>
+//
+*/
+
+#define PMU_FLASH 1
+#define PMU_FLASH_WS 0x00000000
+
+
+/*--------------------- CLOCKOUT Configuration -------------------------------
+//
+// <e> Clock OUT Configuration
+// <o1.0..1> Clockout Source Selection
+// <0=> System Clock
+// <2=> Divided value of USB PLL output
+// <3=> Divided value of PLL Clock
+// <o2.0..4> Clockout divider <1-10><#-1>
+// <o3.0..1> Clockout Pin Selection
+// <0=> P1.15
+// <1=> P0.8
+//
+//
+// </e>
+//
+*/
+
+#define SCU_CLOCKOUT_SETUP 0
+#define SCU_CLOCKOUT_SOURCE 0x00000000
+#define SCU_CLOCKOUT_DIV 0x00000009
+#define SCU_CLOCKOUT_PIN 0x00000001
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+/*!< System Clock Frequency (Core Clock)*/
+#if SCU_CLOCK_SETUP
+uint32_t SystemCoreClock = CLOCK_FSYS;
+#else
+uint32_t SystemCoreClock = CLOCK_BACK_UP;
+#endif
+
+/*----------------------------------------------------------------------------
+ static functions declarations
+ *----------------------------------------------------------------------------*/
+#if (SCU_CLOCK_SETUP == 1)
+static int SystemClockSetup(void);
+#endif
+
+#if (SCU_USB_CLOCK_SETUP == 1)
+static int USBClockSetup(void);
+#endif
+
+
+/**
+ * @brief Setup the microcontroller system.
+ * Initialize the PLL and update the
+ * SystemCoreClock variable.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+int temp;
+
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
+ (3UL << 11*2) ); /* set CP11 Full Access */
+#endif
+
+/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */
+SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);
+
+/* Setup the WDT */
+#if WDT_SETUP
+
+WDT->CTR &= ~WDTENB_nVal;
+
+#endif
+
+
+/* Setup the Flash Wait State */
+#if PMU_FLASH
+temp = FLASH0->FCON;
+temp &= ~FLASH_FCON_WSPFLASH_Msk;
+temp |= PMU_FLASH_WS+3;
+FLASH0->FCON = temp;
+#endif
+
+
+/* Setup the clockout */
+#if SCU_CLOCKOUT_SETUP
+
+SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE;
+/*set PLL div for clkout */
+SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16;
+
+if (SCU_CLOCKOUT_PIN) {
+ PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */
+ PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);
+ PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */
+ }
+else {
+ PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */
+ PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */
+ }
+
+#endif
+
+
+/* Setup the System clock */
+#if SCU_CLOCK_SETUP
+SystemClockSetup();
+#endif
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/
+
+
+/* Setup the USB PL */
+#if SCU_USB_CLOCK_SETUP
+USBClockSetup();
+#endif
+
+
+
+}
+
+
+/**
+ * @brief Update SystemCoreClock according to Clock Register Values
+ * @note -
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate(void)
+{
+unsigned int PDIV;
+unsigned int NDIV;
+unsigned int K2DIV;
+unsigned int long VCO;
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+if (SCU_CLK->SYSCLKCR == 0x00010000)
+{
+ if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){
+ /* check if PLL is locked */
+ /* read back divider settings */
+ PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1;
+ NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1;
+ K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1;
+
+ if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){
+ /* the selected clock is the Backup clock fofi */
+ VCO = (CLOCK_BACK_UP/PDIV)*NDIV;
+ SystemCoreClock = VCO/K2DIV;
+ /* in case the sysclock div is used */
+ SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);
+
+ }
+ else
+ {
+ /* the selected clock is the PLL external oscillator */
+ VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV;
+ SystemCoreClock = VCO/K2DIV;
+ /* in case the sysclock div is used */
+ SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);
+ }
+
+
+ }
+}
+else
+{
+SystemCoreClock = CLOCK_BACK_UP;
+}
+
+
+}
+
+
+/**
+ * @brief -
+ * @note -
+ * @param None
+ * @retval None
+ */
+#if (SCU_CLOCK_SETUP == 1)
+static int SystemClockSetup(void)
+{
+int temp;
+unsigned int long VCO;
+int stepping_K2DIV;
+
+/* this weak function enables DAVE3 clock App usage */
+if(AllowPLLInitByStartup()){
+
+/* check if PLL is switched on */
+if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){
+/* enable PLL first */
+ SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
+
+}
+
+/* Enable OSC_HP if not already on*/
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)
+ {
+ /********************************************************************************************************************/
+ /* Use external crystal for PLL clock input */
+ /********************************************************************************************************************/
+
+ if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){
+ SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/
+ /* setup OSC WDG devider */
+ SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);
+ /* select external OSC as PLL input */
+ SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;
+ /* restart OSC Watchdog */
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
+
+ /* Timeout for wait loop ~150ms */
+ /********************************/
+ SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ do
+ {
+ ;/* wait for ~150ms */
+ }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));
+
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
+ if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)
+ return(0);/* Return Error */
+
+ }
+ }
+ else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)
+ {
+ /********************************************************************************************************************/
+ /* Use factory trimming Back-up clock for PLL clock input */
+ /********************************************************************************************************************/
+ /* PLL Back up clock selected */
+ SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
+
+ }
+ else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC)
+ {
+ /********************************************************************************************************************/
+ /* Use automatic trimming Back-up clock for PLL clock input */
+ /********************************************************************************************************************/
+ /* check for HIB Domain enabled */
+ if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)
+ SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/
+
+ /* check for HIB Domain is not in reset state */
+ if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1)
+ SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/
+
+ /* PLL Back up clock selected */
+ SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
+
+ if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI)
+ {
+ /****************************************************************************************************************/
+ /* Use fOSI as source of the standby clock */
+ /****************************************************************************************************************/
+ SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
+
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;
+ for(temp=0;temp<=0xFFFF;temp++);
+
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
+ }
+ else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP)
+ {
+ /****************************************************************************************************************/
+ /* Use fULP as source of the standby clock */
+ /****************************************************************************************************************/
+ /*check OSCUL if running correct*/
+ if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0)
+ {
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk);
+
+ SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/
+ /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/
+ /* select OSCUL clock for RTC*/
+ SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk;
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
+ /*enable OSCULP WDG Alarm Enable*/
+ SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
+ /*wait now for clock is stable */
+ do
+ {
+ SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);
+ for(temp=0;temp<=0xFFFF;temp++);
+ }
+ while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk);
+
+ SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);
+ }
+ // now OSCULP is running and can be used
+ SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
+
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;
+ /*TRIAL for delay loop*/
+ for(temp=0;temp<=0xFFFF;temp++);
+
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
+ /*TRIAL for delay loop*/
+ for(temp=0;temp<=0xFFFF;temp++);
+
+ }
+ }
+
+ /********************************************************************************************************************/
+ /* Setup and look the main PLL */
+ /********************************************************************************************************************/
+
+if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){
+ /* Systen is still running from internal clock */
+ /* select FOFI as system clock */
+ if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/
+
+
+ /*calulation for stepping*/
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+ if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
+ VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+
+ stepping_K2DIV = (VCO/24000000)-1;
+ /* Go to bypass the Main PLL */
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;
+ /* disconnect OSC_HP to PLL */
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;
+ /* Setup devider settings for main PLL */
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
+ /* we may have to set OSCDISCDIS */
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
+ /* connect OSC_HP to PLL */
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;
+ /* restart PLL Lock detection */
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;
+ /* wait for PLL Lock */
+ /* setup time out loop */
+ /* Timeout for wait loo ~150ms */
+ /********************************/
+ SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+
+ while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500));
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
+
+ if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk)
+ {
+ /* Go back to the Main PLL */
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;
+ }
+ else return(0);
+
+
+ /*********************************************************
+ here we need to setup the system clock divider
+ *********************************************************/
+
+ SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;
+ SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV;
+ SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;
+
+
+ /* Switch system clock to PLL */
+ SCU_CLK->SYSCLKCR |= 0x00010000;
+
+ /* we may have to reset OSCDISCDIS */
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
+
+
+ /*********************************************************/
+ /* Delay for next K2 step ~50µs */
+ /*********************************************************/
+ SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+
+ while (SysTick->VAL >= 100); /* wait for ~50µs */
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
+ /*********************************************************/
+
+ /*********************************************************
+ here the ramp up of the system clock starts FSys < 60MHz
+ *********************************************************/
+ if (CLOCK_FSYS > 60000000){
+ /*calulation for stepping*/
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+ if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
+ VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+
+ stepping_K2DIV = (VCO/60000000)-1;
+
+ /* Setup devider settings for main PLL */
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
+ }
+ else
+ {
+ /* Setup devider settings for main PLL */
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
+ SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
+ return(1);
+ }
+
+ /*********************************************************/
+ /* Delay for next K2 step ~50µs */
+ /*********************************************************/
+ SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+
+ while (SysTick->VAL >= 100); /* wait for ~50µs */
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
+ /********************************/
+
+ /*********************************************************
+ here the ramp up of the system clock starts FSys < 90MHz
+ *********************************************************/
+ if (CLOCK_FSYS > 90000000){
+ /*calulation for stepping*/
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+ if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
+ VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
+
+ stepping_K2DIV = (VCO/90000000)-1;
+
+ /* Setup devider settings for main PLL */
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
+ }
+ else
+ {
+ /* Setup devider settings for main PLL */
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
+ SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
+ return(1);
+ }
+
+ /*********************************************************/
+ /* Delay for next K2 step ~50µs */
+ /*********************************************************/
+ SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+
+ while (SysTick->VAL >= 100); /* wait for ~50µs */
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
+ /********************************/
+
+ /* Setup devider settings for main PLL */
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
+
+ SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
+ }
+ }/* end this weak function enables DAVE3 clock App usage */
+ return(1);
+
+}
+#endif
+
+/**
+ * @brief -
+ * @note -
+ * @param None
+ * @retval None
+ */
+#if (SCU_USB_CLOCK_SETUP == 1)
+static int USBClockSetup(void)
+{
+/* this weak function enables DAVE3 clock App usage */
+if(AllowPLLInitByStartup()){
+
+/* check if PLL is switched on */
+if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){
+ /* enable PLL first */
+ SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);
+}
+
+/* check and if not already running enable OSC_HP */
+ if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){
+ /* check if Main PLL is switched on for OSC WD*/
+ if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){
+ /* enable PLL first */
+ SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
+ }
+ SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/
+ /* setup OSC WDG devider */
+ SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);
+ /* restart OSC Watchdog */
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
+
+ /* Timeout for wait loop ~150ms */
+ /********************************/
+ SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ do
+ {
+ ;/* wait for ~150ms */
+ }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));
+
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
+ if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)
+ return(0);/* Return Error */
+
+ }
+
+
+/* Setup USB PLL */
+ /* Go to bypass the Main PLL */
+ SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;
+ /* disconnect OSC_FI to PLL */
+ SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;
+ /* Setup devider settings for main PLL */
+ SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24));
+ /* Setup USBDIV settings USB clock */
+ SCU_CLK->USBCLKCR = SCU_USBDIV;
+ /* we may have to set OSCDISCDIS */
+ SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;
+ /* connect OSC_FI to PLL */
+ SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;
+ /* restart PLL Lock detection */
+ SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;
+ /* wait for PLL Lock */
+ while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk));
+
+ }/* end this weak function enables DAVE3 clock App usage */
+ return(1);
+
+}
+#endif
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/system_XMC4400.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/system_XMC4400.h new file mode 100644 index 000000000..953e1b099 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/system_XMC4400.h @@ -0,0 +1,72 @@ +/**************************************************************************//**
+ * @file system_XMC4400.h
+ * @brief Header file for the XMC4400-Series systeminit
+ *
+ * @version V1.0
+ * @date 17. August 2012
+ *
+ * @note
+ * Copyright (C) 2011 Infineon Technologies AG. All rights reserved.
+
+ *
+ * @par
+ * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers.
+ * This file can be freely distributed within development tools that are supporting such microcontrollers.
+
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_XMC4400_H
+#define __SYSTEM_XMC4400_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+extern void SystemInit (void);
+
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/* this weak function enables DAVE3 clock App usage */
+extern uint32_t AllowPLLInitByStartup(void);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif
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