diff options
| author | richardbarry <richardbarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2> | 2012-08-11 21:34:11 +0000 |
|---|---|---|
| committer | richardbarry <richardbarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2> | 2012-08-11 21:34:11 +0000 |
| commit | f279ebee719fa6bda3f91061819e6b42051c7395 (patch) | |
| tree | c2ef3f908508343c26551949d5f947009cda3291 /FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC | |
| parent | 24ce9d9c87e6b7b23f0915e1a91fb4a5bd2f7c3d (diff) | |
| download | freertos-f279ebee719fa6bda3f91061819e6b42051c7395.tar.gz | |
Add FreeRTOS-Plus directory.
git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@1765 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
Diffstat (limited to 'FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC')
113 files changed, 31060 insertions, 0 deletions
diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/FreeRTOSConfig.h b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/FreeRTOSConfig.h new file mode 100644 index 000000000..b4f403087 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/FreeRTOSConfig.h @@ -0,0 +1,132 @@ +/*
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
+
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+ >>>NOTE<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details. You should have received a copy of the GNU General Public
+ License and the FreeRTOS license exception along with FreeRTOS; if not it
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained
+ by writing to Richard Barry, contact details for whom are available on the
+ FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong? *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, training, latest information,
+ license and contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool.
+
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
+ the code with commercial support, indemnification, and middleware, under
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
+ provide a safety engineered and independently SIL3 certified version under
+ the SafeRTOS brand: http://www.SafeRTOS.com.
+*/
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+#include <xparameters.h>
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION 1
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 250 )
+#define configCPU_CLOCK_HZ ( ( unsigned long ) XPAR_CPU_PPC440_CORE_CLOCK_FREQ_HZ ) /* Clock setup from start.asm in the demo application. */
+#define configTICK_RATE_HZ ( (portTickType) 1000 )
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 6 )
+#define configTOTAL_HEAP_SIZE ( (size_t) (80 * 1024) )
+#define configMAX_TASK_NAME_LEN ( 20 )
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configUSE_TRACE_FACILITY 0
+#define configCHECK_FOR_STACK_OVERFLOW 2
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configUSE_APPLICATION_TASK_TAG 1
+#define configUSE_FPU 0
+
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 4 )
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskCleanUpResources 1
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vResumeFromISR 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 1
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 1
+#define configUSE_RECURSIVE_MUTEXES 1
+
+
+#if configUSE_FPU == 1
+ /* Include the header that define the traceTASK_SWITCHED_IN() and
+ traceTASK_SWITCHED_OUT() macros to save and restore the floating
+ point registers for tasks that have requested this behaviour. */
+ #include "FPU_Macros.h"
+#endif
+
+#endif /* FREERTOS_CONFIG_H */
+
+
diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld new file mode 100644 index 000000000..f4fc3bbc7 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld @@ -0,0 +1,226 @@ +/*******************************************************************/
+/* */
+/* This file is automatically generated by linker script generator.*/
+/* */
+/* Version: Xilinx EDK 11.1 EDK_L.29.1 */
+/* */
+/* Copyright (c) 2004 Xilinx, Inc. All rights reserved. */
+/* */
+/* Description : PowerPC440 Linker Script */
+/* */
+/*******************************************************************/
+
+_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400;
+_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x400;
+
+/* Define Memories in the system */
+
+MEMORY
+{
+ DDR2_SDRAM_C_MEM_BASEADDR : ORIGIN = 0x00000000, LENGTH = 0x10000000
+ SRAM_C_MEM0_BASEADDR : ORIGIN = 0xF8000000, LENGTH = 0x00100000
+ xps_bram_if_cntlr_1 : ORIGIN = 0xFFFFE000, LENGTH = 0x00001F00
+}
+
+/* Specify the default entry point to the program */
+
+ENTRY(_boot)
+STARTUP(boot.o)
+
+/* Define the sections, and where they are mapped in memory */
+
+SECTIONS
+{
+.vectors : {
+ __vectors_start = .;
+ *(.vectors)
+ __vectors_end = .;
+} > SRAM_C_MEM0_BASEADDR
+
+.text : {
+ *(.text)
+ *(.text.*)
+ *(.gnu.linkonce.t.*)
+} > SRAM_C_MEM0_BASEADDR
+
+.init : {
+ KEEP (*(.init))
+} > SRAM_C_MEM0_BASEADDR
+
+.fini : {
+ KEEP (*(.fini))
+} > SRAM_C_MEM0_BASEADDR
+
+.rodata : {
+ __rodata_start = .;
+ *(.rodata)
+ *(.rodata.*)
+ *(.gnu.linkonce.r.*)
+ __rodata_end = .;
+} > SRAM_C_MEM0_BASEADDR
+
+.rodata1 : {
+ __rodata1_start = .;
+ *(.rodata1)
+ *(.rodata1.*)
+ __rodata1_end = .;
+} > SRAM_C_MEM0_BASEADDR
+
+.sdata2 : {
+ __sdata2_start = .;
+ *(.sdata2)
+ *(.sdata2.*)
+ *(.gnu.linkonce.s2.*)
+ __sdata2_end = .;
+} > SRAM_C_MEM0_BASEADDR
+
+.sbss2 : {
+ __sbss2_start = .;
+ *(.sbss2)
+ *(.sbss2.*)
+ *(.gnu.linkonce.sb2.*)
+ __sbss2_end = .;
+} > SRAM_C_MEM0_BASEADDR
+
+.data : {
+ __data_start = .;
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d.*)
+ __data_end = .;
+} > SRAM_C_MEM0_BASEADDR
+
+.data1 : {
+ __data1_start = .;
+ *(.data1)
+ *(.data1.*)
+ __data1_end = .;
+} > SRAM_C_MEM0_BASEADDR
+
+.got : {
+ *(.got)
+} > SRAM_C_MEM0_BASEADDR
+
+.got1 : {
+ *(.got1)
+} > SRAM_C_MEM0_BASEADDR
+
+.got2 : {
+ *(.got2)
+} > SRAM_C_MEM0_BASEADDR
+
+.ctors : {
+ __CTOR_LIST__ = .;
+ ___CTORS_LIST___ = .;
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ ___CTORS_END___ = .;
+} > SRAM_C_MEM0_BASEADDR
+
+.dtors : {
+ __DTOR_LIST__ = .;
+ ___DTORS_LIST___ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ ___DTORS_END___ = .;
+} > SRAM_C_MEM0_BASEADDR
+
+.fixup : {
+ __fixup_start = .;
+ *(.fixup)
+ __fixup_end = .;
+} > SRAM_C_MEM0_BASEADDR
+
+.eh_frame : {
+ *(.eh_frame)
+} > SRAM_C_MEM0_BASEADDR
+
+.jcr : {
+ *(.jcr)
+} > SRAM_C_MEM0_BASEADDR
+
+.gcc_except_table : {
+ *(.gcc_except_table)
+} > SRAM_C_MEM0_BASEADDR
+
+.sdata : {
+ __sdata_start = .;
+ *(.sdata)
+ *(.sdata.*)
+ *(.gnu.linkonce.s.*)
+ __sdata_end = .;
+} > SRAM_C_MEM0_BASEADDR
+
+.sbss : {
+ __sbss_start = .;
+ *(.sbss)
+ *(.sbss.*)
+ *(.gnu.linkonce.sb.*)
+ *(.scommon)
+ __sbss_end = .;
+} > SRAM_C_MEM0_BASEADDR
+
+.tdata : {
+ __tdata_start = .;
+ *(.tdata)
+ *(.tdata.*)
+ *(.gnu.linkonce.td.*)
+ __tdata_end = .;
+} > SRAM_C_MEM0_BASEADDR
+
+.tbss : {
+ __tbss_start = .;
+ *(.tbss)
+ *(.tbss.*)
+ *(.gnu.linkonce.tb.*)
+ __tbss_end = .;
+} > SRAM_C_MEM0_BASEADDR
+
+.bss : {
+ __bss_start = .;
+ *(.bss)
+ *(.bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end = .;
+} > SRAM_C_MEM0_BASEADDR
+
+.boot0 0xFFFFFF00 : {
+ __boot0_start = .;
+ *(.boot0)
+ __boot0_end = .;
+}
+
+.boot 0xFFFFFFFC : {
+ __boot_start = .;
+ *(.boot)
+ __boot_end = .;
+}
+
+/* Generate Stack and Heap Sections */
+
+.stack : {
+ _stack_end = .;
+ . += _STACK_SIZE;
+ . = ALIGN(16);
+ __stack = .;
+} > SRAM_C_MEM0_BASEADDR
+
+.heap : {
+ . = ALIGN(16);
+ _heap_start = .;
+ . += _HEAP_SIZE;
+ . = ALIGN(16);
+ _heap_end = .;
+ _end = .;
+} > SRAM_C_MEM0_BASEADDR
+
+}
+
diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c new file mode 100644 index 000000000..f308e90f2 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c @@ -0,0 +1,261 @@ +/*
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
+
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+ >>>NOTE<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details. You should have received a copy of the GNU General Public
+ License and the FreeRTOS license exception along with FreeRTOS; if not it
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained
+ by writing to Richard Barry, contact details for whom are available on the
+ FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong? *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, training, latest information,
+ license and contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool.
+
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
+ the code with commercial support, indemnification, and middleware, under
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
+ provide a safety engineered and independently SIL3 certified version under
+ the SafeRTOS brand: http://www.SafeRTOS.com.
+*/
+
+/*
+ * Tests the floating point context save and restore mechanism.
+ *
+ * Two tasks are created - each of which is allocated a buffer of
+ * portNO_FLOP_REGISTERS_TO_SAVE 32bit variables into which the flop context
+ * of the task is saved when the task is switched out, and from which the
+ * flop context of the task is restored when the task is switch in. Prior to
+ * the tasks being created each position in the two buffers is filled with a
+ * unique value - this way the flop context of each task is different.
+ *
+ * The two test tasks never block so are always in either the Running or
+ * Ready state. They execute at the lowest priority so will get pre-empted
+ * regularly, although the yield frequently so will not get much execution
+ * time. The lack of execution time is not a problem as its only the
+ * switching in and out that is being tested.
+ *
+ * Whenever a task is moved from the Ready to the Running state its flop
+ * context will be loaded from the buffer, but while the task is in the
+ * Running state the buffer is not used and can contain any value - in this
+ * case and for test purposes the task itself clears the buffer to zero.
+ * The next time the task is moved out of the Running state into the
+ * Ready state the flop context will once more get saved to the buffer -
+ * overwriting the zeros.
+ *
+ * Therefore whenever the task is not in the Running state its buffer contains
+ * the most recent values of its floating point registers - the zeroing out
+ * of the buffer while the task was executing being used to ensure the values
+ * the buffer contains are not stale.
+ *
+ * When neither test task is in the Running state the buffers should contain
+ * the unique values allocated before the tasks were created. If so then
+ * the floating point context has been maintained. This check is performed
+ * by the 'check' task (defined in main.c) by calling
+ * xAreFlopRegisterTestsStillRunning().
+ *
+ * The test tasks also increment a value each time they execute.
+ * xAreFlopRegisterTestsStillRunning() also checks that this value has changed
+ * since it last ran to ensure the test tasks are still getting processing time.
+ */
+
+/* Standard includes files. */
+#include <string.h>
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------*/
+
+#define flopNUMBER_OF_TASKS 2
+#define flopSTART_VALUE ( 0x1 )
+
+/*-----------------------------------------------------------*/
+
+/* The two test tasks as described at the top of this file. */
+static void vFlopTest1( void *pvParameters );
+static void vFlopTest2( void *pvParameters );
+
+/*-----------------------------------------------------------*/
+
+/* Buffers into which the flop registers will be saved. There is a buffer for
+both tasks. */
+static volatile unsigned long ulFlopRegisters[ flopNUMBER_OF_TASKS ][ portNO_FLOP_REGISTERS_TO_SAVE ];
+
+/* Variables that are incremented by the tasks to indicate that they are still
+running. */
+static volatile unsigned long ulFlop1CycleCount = 0, ulFlop2CycleCount = 0;
+
+/*-----------------------------------------------------------*/
+
+void vStartFlopRegTests( void )
+{
+xTaskHandle xTaskJustCreated;
+unsigned portBASE_TYPE x, y, z = flopSTART_VALUE;
+
+ /* Fill the arrays into which the flop registers are to be saved with
+ known values. These are the values that will be written to the flop
+ registers when the tasks start, and as the tasks do not perform any
+ flop operations the values should never change. Each position in the
+ buffer contains a different value so the flop context of each task
+ will be different. */
+ for( x = 0; x < flopNUMBER_OF_TASKS; x++ )
+ {
+ for( y = 0; y < ( portNO_FLOP_REGISTERS_TO_SAVE - 1); y++ )
+ {
+ ulFlopRegisters[ x ][ y ] = z;
+ z++;
+ }
+ }
+
+
+ /* Create the first task. */
+ xTaskCreate( vFlopTest1, ( signed char * ) "flop1", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, &xTaskJustCreated );
+
+ /* The task tag value is a value that can be associated with a task, but
+ is not used by the scheduler itself. Its use is down to the application so
+ it makes a convenient place in this case to store the pointer to the buffer
+ into which the flop context of the task will be stored. The first created
+ task uses ulFlopRegisters[ 0 ], the second ulFlopRegisters[ 1 ]. */
+ vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 0 ][ 0 ] ) );
+
+ /* Do the same for the second task. */
+ xTaskCreate( vFlopTest2, ( signed char * ) "flop2", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, &xTaskJustCreated );
+ vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 1 ][ 0 ] ) );
+}
+/*-----------------------------------------------------------*/
+
+static void vFlopTest1( void *pvParameters )
+{
+ /* Just to remove compiler warning. */
+ ( void ) pvParameters;
+
+ for( ;; )
+ {
+ /* The values from the buffer should have now been written to the flop
+ registers. Clear the buffer to ensure the same values then get written
+ back the next time the task runs. Being preempted during this memset
+ could cause the test to fail, hence the critical section. */
+ portENTER_CRITICAL();
+ memset( ( void * ) ulFlopRegisters[ 0 ], 0x00, ( portNO_FLOP_REGISTERS_TO_SAVE * sizeof( unsigned portBASE_TYPE ) ) );
+ portEXIT_CRITICAL();
+
+ /* We don't have to do anything other than indicate that we are
+ still running. */
+ ulFlop1CycleCount++;
+ taskYIELD();
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void vFlopTest2( void *pvParameters )
+{
+ /* Just to remove compiler warning. */
+ ( void ) pvParameters;
+
+ for( ;; )
+ {
+ /* The values from the buffer should have now been written to the flop
+ registers. Clear the buffer to ensure the same values then get written
+ back the next time the task runs. */
+ portENTER_CRITICAL();
+ memset( ( void * ) ulFlopRegisters[ 1 ], 0x00, ( portNO_FLOP_REGISTERS_TO_SAVE * sizeof( unsigned portBASE_TYPE ) ) );
+ portEXIT_CRITICAL();
+
+ /* We don't have to do anything other than indicate that we are
+ still running. */
+ ulFlop2CycleCount++;
+ taskYIELD();
+ }
+}
+/*-----------------------------------------------------------*/
+
+portBASE_TYPE xAreFlopRegisterTestsStillRunning( void )
+{
+portBASE_TYPE xReturn = pdPASS;
+unsigned portBASE_TYPE x, y, z = flopSTART_VALUE;
+static unsigned long ulLastFlop1CycleCount = 0, ulLastFlop2CycleCount = 0;
+
+ /* Called from the 'check' task.
+
+ The flop tasks cannot be currently running, check their saved registers
+ are as expected. The tests tasks do not perform any flop operations so
+ their registers should be as per their initial setting. */
+ for( x = 0; x < flopNUMBER_OF_TASKS; x++ )
+ {
+ for( y = 0; y < ( portNO_FLOP_REGISTERS_TO_SAVE - 1 ); y++ )
+ {
+ if( ulFlopRegisters[ x ][ y ] != z )
+ {
+ xReturn = pdFAIL;
+ break;
+ }
+
+ z++;
+ }
+ }
+
+ /* Check both tasks have actually been swapped in and out since this function
+ last executed. */
+ if( ulFlop1CycleCount == ulLastFlop1CycleCount )
+ {
+ xReturn = pdFAIL;
+ }
+
+ if( ulFlop2CycleCount == ulLastFlop2CycleCount )
+ {
+ xReturn = pdFAIL;
+ }
+
+ ulLastFlop1CycleCount = ulFlop1CycleCount;
+ ulLastFlop2CycleCount = ulFlop2CycleCount;
+
+ return xReturn;
+}
+
diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.h b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.h new file mode 100644 index 000000000..99b2d77cb --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.h @@ -0,0 +1,73 @@ +/*
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
+
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+ >>>NOTE<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details. You should have received a copy of the GNU General Public
+ License and the FreeRTOS license exception along with FreeRTOS; if not it
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained
+ by writing to Richard Barry, contact details for whom are available on the
+ FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong? *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, training, latest information,
+ license and contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool.
+
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
+ the code with commercial support, indemnification, and middleware, under
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
+ provide a safety engineered and independently SIL3 certified version under
+ the SafeRTOS brand: http://www.SafeRTOS.com.
+*/
+
+#ifndef FLOP_REG_TEST_H
+#define FLOP_REG_TEST_H
+
+void vStartFlopRegTests( void );
+portBASE_TYPE xAreFlopRegisterTestsStillRunning( void );
+
+#endif
diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c new file mode 100644 index 000000000..44eb0becc --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c @@ -0,0 +1,417 @@ +/*
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
+
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+ >>>NOTE<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details. You should have received a copy of the GNU General Public
+ License and the FreeRTOS license exception along with FreeRTOS; if not it
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained
+ by writing to Richard Barry, contact details for whom are available on the
+ FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong? *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, training, latest information,
+ license and contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool.
+
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
+ the code with commercial support, indemnification, and middleware, under
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
+ provide a safety engineered and independently SIL3 certified version under
+ the SafeRTOS brand: http://www.SafeRTOS.com.
+*/
+
+/*
+ * Creates eight tasks, each of which loops continuously performing a
+ * floating point calculation.
+ *
+ * All the tasks run at the idle priority and never block or yield. This causes
+ * all eight tasks to time slice with the idle task. Running at the idle priority
+ * means that these tasks will get pre-empted any time another task is ready to run
+ * or a time slice occurs. More often than not the pre-emption will occur mid
+ * calculation, creating a good test of the schedulers context switch mechanism - a
+ * calculation producing an unexpected result could be a symptom of a corruption in
+ * the context of a task.
+ *
+ * This file demonstrates the use of the task tag and traceTASK_SWITCHED_IN and
+ * traceTASK_SWITCHED_OUT macros to save and restore the floating point context.
+ */
+
+#include <stdlib.h>
+#include <math.h>
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo program include files. */
+#include "flop.h"
+
+/* Misc. definitions. */
+#define mathSTACK_SIZE configMINIMAL_STACK_SIZE
+#define mathNUMBER_OF_TASKS ( 8 )
+
+/* Four tasks, each of which performs a different floating point calculation.
+Each of the four is created twice. */
+static portTASK_FUNCTION_PROTO( vCompetingMathTask1, pvParameters );
+static portTASK_FUNCTION_PROTO( vCompetingMathTask2, pvParameters );
+static portTASK_FUNCTION_PROTO( vCompetingMathTask3, pvParameters );
+static portTASK_FUNCTION_PROTO( vCompetingMathTask4, pvParameters );
+
+/* These variables are used to check that all the tasks are still running. If a
+task gets a calculation wrong it will stop incrementing its check variable. */
+static volatile unsigned short usTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned short ) 0 };
+
+/* Buffers into which the flop registers will be saved. There is a buffer for
+each task created within this file. Zeroing out this array is the normal and
+safe option as this will cause the task to start with all zeros in its flop
+context. */
+static unsigned long ulFlopRegisters[ mathNUMBER_OF_TASKS ][ portNO_FLOP_REGISTERS_TO_SAVE ];
+
+/*-----------------------------------------------------------*/
+
+void vStartMathTasks( unsigned portBASE_TYPE uxPriority )
+{
+xTaskHandle xTaskJustCreated;
+portBASE_TYPE x, y;
+
+ /* Place known values into the buffers into which the flop registers are
+ to be saved. This is for debug purposes only, it is not normally
+ required. The last position in each array is left at zero as the status
+ register will be loaded from there.
+
+ It is intended that these values can be viewed being loaded into the
+ flop registers when a task is started - however the Insight debugger
+ does not seem to want to show the flop register values. */
+ for( x = 0; x < mathNUMBER_OF_TASKS; x++ )
+ {
+ for( y = 0; y < ( portNO_FLOP_REGISTERS_TO_SAVE - 1 ); y++ )
+ {
+ ulFlopRegisters[ x ][ y ] = ( x + 1 );
+ }
+ }
+
+ /* Create the first task - passing it the address of the check variable
+ that it is going to increment. This check variable is used as an
+ indication that the task is still running. */
+ xTaskCreate( vCompetingMathTask1, ( signed char * ) "Math1", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, &xTaskJustCreated );
+
+ /* The task tag value is a value that can be associated with a task, but
+ is not used by the scheduler itself. Its use is down to the application so
+ it makes a convenient place in this case to store the pointer to the buffer
+ into which the flop context of the task will be stored. The first created
+ task uses ulFlopRegisters[ 0 ], the second ulFlopRegisters[ 1 ], etc. */
+ vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 0 ][ 0 ] ) );
+
+ /* Create another 7 tasks, allocating a buffer for each. */
+ xTaskCreate( vCompetingMathTask2, ( signed char * ) "Math2", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, &xTaskJustCreated );
+ vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 1 ][ 0 ] ) );
+
+ xTaskCreate( vCompetingMathTask3, ( signed char * ) "Math3", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, &xTaskJustCreated );
+ vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 2 ][ 0 ] ) );
+
+ xTaskCreate( vCompetingMathTask4, ( signed char * ) "Math4", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, &xTaskJustCreated );
+ vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 3 ][ 0 ] ) );
+
+ xTaskCreate( vCompetingMathTask1, ( signed char * ) "Math5", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, &xTaskJustCreated );
+ vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 4 ][ 0 ] ) );
+
+ xTaskCreate( vCompetingMathTask2, ( signed char * ) "Math6", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, &xTaskJustCreated );
+ vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 5 ][ 0 ] ) );
+
+ xTaskCreate( vCompetingMathTask3, ( signed char * ) "Math7", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, &xTaskJustCreated );
+ vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 6 ][ 0 ] ) );
+
+ xTaskCreate( vCompetingMathTask4, ( signed char * ) "Math8", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, &xTaskJustCreated );
+ vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 7 ][ 0 ] ) );
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( vCompetingMathTask1, pvParameters )
+{
+volatile portFLOAT ff1, ff2, ff3, ff4;
+volatile unsigned short *pusTaskCheckVariable;
+volatile portFLOAT fAnswer;
+short sError = pdFALSE;
+
+ ff1 = 123.4567F;
+ ff2 = 2345.6789F;
+ ff3 = -918.222F;
+
+ fAnswer = ( ff1 + ff2 ) * ff3;
+
+ /* The variable this task increments to show it is still running is passed in
+ as the parameter. */
+ pusTaskCheckVariable = ( unsigned short * ) pvParameters;
+
+ /* Keep performing a calculation and checking the result against a constant. */
+ for(;;)
+ {
+ ff1 = 123.4567F;
+ ff2 = 2345.6789F;
+ ff3 = -918.222F;
+
+ ff4 = ( ff1 + ff2 ) * ff3;
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ /* If the calculation does not match the expected constant, stop the
+ increment of the check variable. */
+ if( fabs( ff4 - fAnswer ) > 0.001F )
+ {
+ sError = pdTRUE;
+ }
+
+ if( sError == pdFALSE )
+ {
+ /* If the calculation has always been correct, increment the check
+ variable so we know this task is still running okay. */
+ ( *pusTaskCheckVariable )++;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ }
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( vCompetingMathTask2, pvParameters )
+{
+volatile portFLOAT ff1, ff2, ff3, ff4;
+volatile unsigned short *pusTaskCheckVariable;
+volatile portFLOAT fAnswer;
+short sError = pdFALSE;
+
+ ff1 = -389.38F;
+ ff2 = 32498.2F;
+ ff3 = -2.0001F;
+
+ fAnswer = ( ff1 / ff2 ) * ff3;
+
+
+ /* The variable this task increments to show it is still running is passed in
+ as the parameter. */
+ pusTaskCheckVariable = ( unsigned short * ) pvParameters;
+
+ /* Keep performing a calculation and checking the result against a constant. */
+ for( ;; )
+ {
+ ff1 = -389.38F;
+ ff2 = 32498.2F;
+ ff3 = -2.0001F;
+
+ ff4 = ( ff1 / ff2 ) * ff3;
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ /* If the calculation does not match the expected constant, stop the
+ increment of the check variable. */
+ if( fabs( ff4 - fAnswer ) > 0.001F )
+ {
+ sError = pdTRUE;
+ }
+
+ if( sError == pdFALSE )
+ {
+ /* If the calculation has always been correct, increment the check
+ variable so we know
+ this task is still running okay. */
+ ( *pusTaskCheckVariable )++;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+ }
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( vCompetingMathTask3, pvParameters )
+{
+volatile portFLOAT *pfArray, fTotal1, fTotal2, fDifference;
+volatile unsigned short *pusTaskCheckVariable;
+const size_t xArraySize = 10;
+size_t xPosition;
+short sError = pdFALSE;
+
+ /* The variable this task increments to show it is still running is passed in
+ as the parameter. */
+ pusTaskCheckVariable = ( unsigned short * ) pvParameters;
+
+ pfArray = ( portFLOAT * ) pvPortMalloc( xArraySize * sizeof( portFLOAT ) );
+
+ /* Keep filling an array, keeping a running total of the values placed in the
+ array. Then run through the array adding up all the values. If the two totals
+ do not match, stop the check variable from incrementing. */
+ for( ;; )
+ {
+ fTotal1 = 0.0F;
+ fTotal2 = 0.0F;
+
+ for( xPosition = 0; xPosition < xArraySize; xPosition++ )
+ {
+ pfArray[ xPosition ] = ( portFLOAT ) xPosition + 5.5F;
+ fTotal1 += ( portFLOAT ) xPosition + 5.5F;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ for( xPosition = 0; xPosition < xArraySize; xPosition++ )
+ {
+ fTotal2 += pfArray[ xPosition ];
+ }
+
+ fDifference = fTotal1 - fTotal2;
+ if( fabs( fDifference ) > 0.001F )
+ {
+ sError = pdTRUE;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ if( sError == pdFALSE )
+ {
+ /* If the calculation has always been correct, increment the check
+ variable so we know this task is still running okay. */
+ ( *pusTaskCheckVariable )++;
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( vCompetingMathTask4, pvParameters )
+{
+volatile portFLOAT *pfArray, fTotal1, fTotal2, fDifference;
+volatile unsigned short *pusTaskCheckVariable;
+const size_t xArraySize = 10;
+size_t xPosition;
+short sError = pdFALSE;
+
+ /* The variable this task increments to show it is still running is passed in
+ as the parameter. */
+ pusTaskCheckVariable = ( unsigned short * ) pvParameters;
+
+ pfArray = ( portFLOAT * ) pvPortMalloc( xArraySize * sizeof( portFLOAT ) );
+
+ /* Keep filling an array, keeping a running total of the values placed in the
+ array. Then run through the array adding up all the values. If the two totals
+ do not match, stop the check variable from incrementing. */
+ for( ;; )
+ {
+ fTotal1 = 0.0F;
+ fTotal2 = 0.0F;
+
+ for( xPosition = 0; xPosition < xArraySize; xPosition++ )
+ {
+ pfArray[ xPosition ] = ( portFLOAT ) xPosition * 12.123F;
+ fTotal1 += ( portFLOAT ) xPosition * 12.123F;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ for( xPosition = 0; xPosition < xArraySize; xPosition++ )
+ {
+ fTotal2 += pfArray[ xPosition ];
+ }
+
+ fDifference = fTotal1 - fTotal2;
+ if( fabs( fDifference ) > 0.001F )
+ {
+ sError = pdTRUE;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ if( sError == pdFALSE )
+ {
+ /* If the calculation has always been correct, increment the check
+ variable so we know this task is still running okay. */
+ ( *pusTaskCheckVariable )++;
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+/* This is called to check that all the created tasks are still running. */
+portBASE_TYPE xAreMathsTaskStillRunning( void )
+{
+/* Keep a history of the check variables so we know if they have been incremented
+since the last call. */
+static unsigned short usLastTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned short ) 0 };
+portBASE_TYPE xReturn = pdTRUE, xTask;
+
+ /* Check the maths tasks are still running by ensuring their check variables
+ are still incrementing. */
+ for( xTask = 0; xTask < mathNUMBER_OF_TASKS; xTask++ )
+ {
+ if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] )
+ {
+ /* The check has not incremented so an error exists. */
+ xReturn = pdFALSE;
+ }
+
+ usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ];
+ }
+
+ return xReturn;
+}
+
+
+
diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/main.c b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/main.c new file mode 100644 index 000000000..6061eff1c --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/main.c @@ -0,0 +1,722 @@ +/*
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
+
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+ >>>NOTE<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details. You should have received a copy of the GNU General Public
+ License and the FreeRTOS license exception along with FreeRTOS; if not it
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained
+ by writing to Richard Barry, contact details for whom are available on the
+ FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong? *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, training, latest information,
+ license and contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool.
+
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
+ the code with commercial support, indemnification, and middleware, under
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
+ provide a safety engineered and independently SIL3 certified version under
+ the SafeRTOS brand: http://www.SafeRTOS.com.
+*/
+
+/*
+ * Creates all the demo application tasks, then starts the scheduler. The WEB
+ * documentation provides more details of the demo application tasks.
+ *
+ * In addition to the standard demo tasks, the follow demo specific tasks are
+ * create:
+ *
+ * The "Check" task. This only executes every three seconds but has the highest
+ * priority so is guaranteed to get processor time. Its main function is to
+ * check that all the other tasks are still operational. Most tasks maintain
+ * a unique count that is incremented each time the task successfully completes
+ * its function. Should any error occur within such a task the count is
+ * permanently halted. The check task inspects the count of each task to ensure
+ * it has changed since the last time the check task executed. If all the count
+ * variables have changed all the tasks are still executing error free, and the
+ * check task toggles the onboard LED. Should any task contain an error at any time
+ * the LED toggle rate will change from 3 seconds to 500ms.
+ *
+ * The "Register Check" tasks. These tasks fill the CPU registers with known
+ * values, then check that each register still contains the expected value, the
+ * discovery of an unexpected value being indicative of an error in the RTOS
+ * context switch mechanism. The register check tasks operate at low priority
+ * so are switched in and out frequently.
+ *
+ */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Xilinx library includes. */
+#include "xcache_l.h"
+#include "xintc.h"
+
+/* Demo application includes. */
+#include "flash.h"
+#include "integer.h"
+#include "comtest2.h"
+#include "semtest.h"
+#include "BlockQ.h"
+#include "dynamic.h"
+#include "GenQTest.h"
+#include "QPeek.h"
+#include "blocktim.h"
+#include "death.h"
+#include "partest.h"
+#include "countsem.h"
+#include "recmutex.h"
+#include "flop.h"
+#include "flop-reg-test.h"
+
+/* Priorities assigned to the demo tasks. */
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 )
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )
+#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
+#define mainQUEUE_BLOCK_PRIORITY ( tskIDLE_PRIORITY + 1 )
+#define mainDEATH_PRIORITY ( tskIDLE_PRIORITY + 1 )
+#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
+#define mainGENERIC_QUEUE_PRIORITY ( tskIDLE_PRIORITY )
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 )
+#define mainFLOP_PRIORITY ( tskIDLE_PRIORITY )
+
+/* The first LED used by the COM test and check tasks respectively. */
+#define mainCOM_TEST_LED ( 4 )
+#define mainCHECK_TEST_LED ( 3 )
+
+/* The baud rate used by the comtest tasks is set by the hardware, so the
+baud rate parameters passed into the comtest initialisation has no effect. */
+#define mainBAUD_SET_IN_HARDWARE ( 0 )
+
+/* Delay periods used by the check task. If no errors have been found then
+the check LED will toggle every mainNO_ERROR_CHECK_DELAY milliseconds. If an
+error has been found at any time then the toggle rate will increase to
+mainERROR_CHECK_DELAY milliseconds. */
+#define mainNO_ERROR_CHECK_DELAY ( ( portTickType ) 3000 / portTICK_RATE_MS )
+#define mainERROR_CHECK_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS )
+
+
+/*
+ * The tasks defined within this file - described within the comments at the
+ * head of this page.
+ */
+static void prvRegTestTask1( void *pvParameters );
+static void prvRegTestTask2( void *pvParameters );
+static void prvErrorChecks( void *pvParameters );
+
+/*
+ * Called by the 'check' task to inspect all the standard demo tasks within
+ * the system, as described within the comments at the head of this page.
+ */
+static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void );
+
+/*
+ * Perform any hardware initialisation required by the demo application.
+ */
+static void prvSetupHardware( void );
+
+/*-----------------------------------------------------------*/
+
+/* xRegTestStatus will get set to pdFAIL by the regtest tasks if they
+discover an unexpected value. */
+static volatile unsigned portBASE_TYPE xRegTestStatus = pdPASS;
+
+/* Counters used to ensure the regtest tasks are still running. */
+static volatile unsigned long ulRegTest1Counter = 0UL, ulRegTest2Counter = 0UL;
+
+/*-----------------------------------------------------------*/
+
+int main( void )
+{
+
+ /* Must be called prior to installing any interrupt handlers! */
+ vPortSetupInterruptController();
+
+ /* In this case prvSetupHardware() just enables the caches and and
+ configures the IO ports for the LED outputs. */
+ prvSetupHardware();
+
+ /* Start the standard demo application tasks. Note that the baud rate used
+ by the comtest tasks is set by the hardware, so the baud rate parameter
+ passed has no effect. */
+ vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
+ vStartIntegerMathTasks( tskIDLE_PRIORITY );
+ vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainBAUD_SET_IN_HARDWARE, mainCOM_TEST_LED );
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
+ vStartBlockingQueueTasks ( mainQUEUE_BLOCK_PRIORITY );
+ vStartDynamicPriorityTasks();
+ vStartGenericQueueTasks( mainGENERIC_QUEUE_PRIORITY );
+ vStartQueuePeekTasks();
+ vCreateBlockTimeTasks();
+ vStartCountingSemaphoreTasks();
+ vStartRecursiveMutexTasks();
+
+ #if ( configUSE_FPU == 1 )
+ {
+ /* A different project is provided that has configUSE_FPU set to 1
+ in order to demonstrate all the settings required to use the floating
+ point unit. If you wish to use the floating point unit do not start
+ with this project. */
+ vStartMathTasks( mainFLOP_PRIORITY );
+ vStartFlopRegTests();
+ }
+ #endif
+
+ /* Create the tasks defined within this file. */
+ xTaskCreate( prvRegTestTask1, ( signed char * ) "Regtest1", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+ xTaskCreate( prvRegTestTask2, ( signed char * ) "Regtest2", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+ xTaskCreate( prvErrorChecks, ( signed char * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
+
+ /* The suicide tasks must be started last as they record the number of other
+ tasks that exist within the system. The value is then used to ensure at run
+ time the number of tasks that exists is within expected bounds. */
+ vCreateSuicidalTasks( mainDEATH_PRIORITY );
+
+ /* Now start the scheduler. Following this call the created tasks should
+ be executing. */
+ vTaskStartScheduler();
+
+ /* vTaskStartScheduler() will only return if an error occurs while the
+ idle task is being created. */
+ for( ;; );
+
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void )
+{
+portBASE_TYPE lReturn = pdPASS;
+static unsigned long ulLastRegTest1Counter= 0UL, ulLastRegTest2Counter = 0UL;
+
+ /* The demo tasks maintain a count that increments every cycle of the task
+ provided that the task has never encountered an error. This function
+ checks the counts maintained by the tasks to ensure they are still being
+ incremented. A count remaining at the same value between calls therefore
+ indicates that an error has been detected. */
+
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
+ {
+ lReturn = pdFAIL;
+ }
+
+ if( xAreComTestTasksStillRunning() != pdTRUE )
+ {
+ lReturn = pdFAIL;
+ }
+
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )
+ {
+ lReturn = pdFAIL;
+ }
+
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )
+ {
+ lReturn = pdFAIL;
+ }
+
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
+ {
+ lReturn = pdFAIL;
+ }
+
+ if( xIsCreateTaskStillRunning() != pdTRUE )
+ {
+ lReturn = pdFAIL;
+ }
+
+ if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
+ {
+ lReturn = pdFAIL;
+ }
+
+ if( xAreGenericQueueTasksStillRunning() != pdTRUE )
+ {
+ lReturn = pdFAIL;
+ }
+
+ if( xAreQueuePeekTasksStillRunning() != pdTRUE )
+ {
+ lReturn = pdFAIL;
+ }
+
+ if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE )
+ {
+ lReturn = pdFAIL;
+ }
+
+ if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
+ {
+ lReturn = pdFAIL;
+ }
+
+ #if ( configUSE_FPU == 1 )
+ if( xAreMathsTaskStillRunning() != pdTRUE )
+ {
+ lReturn = pdFAIL;
+ }
+
+ if( xAreFlopRegisterTestsStillRunning() != pdTRUE )
+ {
+ lReturn = pdFAIL;
+ }
+ #endif
+
+ /* Have the register test tasks found any errors? */
+ if( xRegTestStatus != pdPASS )
+ {
+ lReturn = pdFAIL;
+ }
+
+ /* Are the register test tasks still looping? */
+ if( ulLastRegTest1Counter == ulRegTest1Counter )
+ {
+ lReturn = pdFAIL;
+ }
+ else
+ {
+ ulLastRegTest1Counter = ulRegTest1Counter;
+ }
+
+ if( ulLastRegTest2Counter == ulRegTest2Counter )
+ {
+ lReturn = pdFAIL;
+ }
+ else
+ {
+ ulLastRegTest2Counter = ulRegTest2Counter;
+ }
+
+ return lReturn;
+}
+/*-----------------------------------------------------------*/
+
+static void prvErrorChecks( void *pvParameters )
+{
+portTickType xDelayPeriod = mainNO_ERROR_CHECK_DELAY, xLastExecutionTime;
+volatile unsigned portBASE_TYPE uxFreeStack;
+
+ /* Just to remove compiler warning. */
+ ( void ) pvParameters;
+
+ /* This call is just to demonstrate the use of the function - nothing is
+ done with the value. You would expect the stack high water mark to be
+ lower (the function to return a larger value) here at function entry than
+ later following calls to other functions. */
+ uxFreeStack = uxTaskGetStackHighWaterMark( NULL );
+
+ /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()
+ works correctly. */
+ xLastExecutionTime = xTaskGetTickCount();
+
+ /* Cycle for ever, delaying then checking all the other tasks are still
+ operating without error. */
+ for( ;; )
+ {
+ /* Again just for demo purposes - uxFreeStack should have a lower value
+ here than following the call to uxTaskGetStackHighWaterMark() on the
+ task entry. */
+ uxFreeStack = uxTaskGetStackHighWaterMark( NULL );
+
+ /* Wait until it is time to check again. The time we wait here depends
+ on whether an error has been detected or not. When an error is
+ detected the time is shortened resulting in a faster LED flash rate. */
+ vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod );
+
+ /* See if the other tasks are all ok. */
+ if( prvCheckOtherTasksAreStillRunning() != pdPASS )
+ {
+ /* An error occurred in one of the tasks so shorten the delay
+ period - which has the effect of increasing the frequency of the
+ LED toggle. */
+ xDelayPeriod = mainERROR_CHECK_DELAY;
+ }
+
+ /* Flash! */
+ vParTestToggleLED( mainCHECK_TEST_LED );
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupHardware( void )
+{
+ XCache_EnableICache( 0x80000000 );
+ XCache_EnableDCache( 0x80000000 );
+
+ /* Setup the IO port for use with the LED outputs. */
+ vParTestInitialise();
+}
+/*-----------------------------------------------------------*/
+
+void prvRegTest1Pass( void )
+{
+ /* Called from the inline assembler - this cannot be static
+ otherwise it can get optimised away. */
+ ulRegTest1Counter++;
+}
+/*-----------------------------------------------------------*/
+
+void prvRegTest2Pass( void )
+{
+ /* Called from the inline assembler - this cannot be static
+ otherwise it can get optimised away. */
+ ulRegTest2Counter++;
+}
+/*-----------------------------------------------------------*/
+
+void prvRegTestFail( void )
+{
+ /* Called from the inline assembler - this cannot be static
+ otherwise it can get optimised away. */
+ xRegTestStatus = pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+static void prvRegTestTask1( void *pvParameters )
+{
+ /* Just to remove compiler warning. */
+ ( void ) pvParameters;
+
+ /* The first register test task as described at the top of this file. The
+ values used in the registers are different to those use in the second
+ register test task. Also, unlike the second register test task, this task
+ yields between setting the register values and subsequently checking the
+ register values. */
+ asm volatile
+ (
+ "RegTest1Start: \n\t" \
+ " \n\t" \
+ " li 0, 301 \n\t" \
+ " mtspr 256, 0 #USPRG0 \n\t" \
+ " li 0, 501 \n\t" \
+ " mtspr 8, 0 #LR \n\t" \
+ " li 0, 4 \n\t" \
+ " mtspr 1, 0 #XER \n\t" \
+ " \n\t" \
+ " li 0, 1 \n\t" \
+ " li 2, 2 \n\t" \
+ " li 3, 3 \n\t" \
+ " li 4, 4 \n\t" \
+ " li 5, 5 \n\t" \
+ " li 6, 6 \n\t" \
+ " li 7, 7 \n\t" \
+ " li 8, 8 \n\t" \
+ " li 9, 9 \n\t" \
+ " li 10, 10 \n\t" \
+ " li 11, 11 \n\t" \
+ " li 12, 12 \n\t" \
+ " li 13, 13 \n\t" \
+ " li 14, 14 \n\t" \
+ " li 15, 15 \n\t" \
+ " li 16, 16 \n\t" \
+ " li 17, 17 \n\t" \
+ " li 18, 18 \n\t" \
+ " li 19, 19 \n\t" \
+ " li 20, 20 \n\t" \
+ " li 21, 21 \n\t" \
+ " li 22, 22 \n\t" \
+ " li 23, 23 \n\t" \
+ " li 24, 24 \n\t" \
+ " li 25, 25 \n\t" \
+ " li 26, 26 \n\t" \
+ " li 27, 27 \n\t" \
+ " li 28, 28 \n\t" \
+ " li 29, 29 \n\t" \
+ " li 30, 30 \n\t" \
+ " li 31, 31 \n\t" \
+ " \n\t" \
+ " sc \n\t" \
+ " nop \n\t" \
+ " \n\t" \
+ " cmpwi 0, 1 \n\t" \
+ " bne RegTest1Fail \n\t" \
+ " cmpwi 2, 2 \n\t" \
+ " bne RegTest1Fail \n\t" \
+ " cmpwi 3, 3 \n\t" \
+ " bne RegTest1Fail \n\t" \
+ " cmpwi 4, 4 \n\t" \
+ " bne RegTest1Fail \n\t" \
+ " cmpwi 5, 5 \n\t" \
+ " bne RegTest1Fail \n\t" \
+ " cmpwi 6, 6 \n\t" \
+ " bne RegTest1Fail \n\t" \
+ " cmpwi 7, 7 \n\t" \
+ " bne RegTest1Fail \n\t" \
+ " cmpwi 8, 8 \n\t" \
+ " bne RegTest1Fail \n\t" \
+ " cmpwi 9, 9 \n\t" \
+ " bne RegTest1Fail \n\t" \
+ " cmpwi 10, 10 \n\t" \
+ " bne RegTest1Fail \n\t" \
+ " cmpwi 11, 11 \n\t" \
+ " bne RegTest1Fail \n\t" \
+ " cmpwi 12, 12 \n\t" \
+ " bne RegTest1Fail \n\t" \
+ " cmpwi 13, 13 \n\t" \
+ " bne RegTest1Fail \n\t" \
+ " cmpwi 14, 14 \n\t" \
+ " bne RegTest1Fail \n\t" \
+ " cmpwi 15, 15 \n\t" \
+ " bne RegTest1Fail \n\t" \
+ " cmpwi 16, 16 \n\t" \
+ " bne RegTest1Fail \n\t" \
+ " cmpwi 17, 17 \n\t" \
+ " bne RegTest1Fail \n\t" \
+ " cmpwi 18, 18 \n\t" \
+ " bne RegTest1Fail \n\t" \
+ " cmpwi 19, 19 \n\t" \
+ " bne RegTest1Fail \n\t" \
+ " cmpwi 20, 20 \n\t" \
+ " bne RegTest1Fail \n\t" \
+ " cmpwi 21, 21 \n\t" \
+ " bne RegTest1Fail \n\t" \
+ " cmpwi 22, 22 \n\t" \
+ " bne RegTest1Fail \n\t" \
+ " cmpwi 23, 23 \n\t" \
+ " bne RegTest1Fail \n\t" \
+ " cmpwi 24, 24 \n\t" \
+ " bne RegTest1Fail \n\t" \
+ " cmpwi 25, 25 \n\t" \
+ " bne RegTest1Fail \n\t" \
+ " cmpwi 26, 26 \n\t" \
+ " bne RegTest1Fail \n\t" \
+ " cmpwi 27, 27 \n\t" \
+ " bne RegTest1Fail \n\t" \
+ " cmpwi 28, 28 \n\t" \
+ " bne RegTest1Fail \n\t" \
+ " cmpwi 29, 29 \n\t" \
+ " bne RegTest1Fail \n\t" \
+ " cmpwi 30, 30 \n\t" \
+ " bne RegTest1Fail \n\t" \
+ " cmpwi 31, 31 \n\t" \
+ " bne RegTest1Fail \n\t" \
+ " \n\t" \
+ " mfspr 0, 256 #USPRG0 \n\t" \
+ " cmpwi 0, 301 \n\t" \
+ " bne RegTest1Fail \n\t" \
+ " mfspr 0, 8 #LR \n\t" \
+ " cmpwi 0, 501 \n\t" \
+ " bne RegTest1Fail \n\t" \
+ " mfspr 0, 1 #XER \n\t" \
+ " cmpwi 0, 4 \n\t" \
+ " bne RegTest1Fail \n\t" \
+ " \n\t" \
+ " bl prvRegTest1Pass \n\t" \
+ " b RegTest1Start \n\t" \
+ " \n\t" \
+ "RegTest1Fail: \n\t" \
+ " \n\t" \
+ " \n\t" \
+ " bl prvRegTestFail \n\t" \
+ " b RegTest1Start \n\t" \
+ );
+}
+/*-----------------------------------------------------------*/
+
+static void prvRegTestTask2( void *pvParameters )
+{
+ /* Just to remove compiler warning. */
+ ( void ) pvParameters;
+
+ /* The second register test task as described at the top of this file.
+ Note that this task fills the registers with different values to the
+ first register test task. */
+ asm volatile
+ (
+ "RegTest2Start: \n\t" \
+ " \n\t" \
+ " li 0, 300 \n\t" \
+ " mtspr 256, 0 #USPRG0 \n\t" \
+ " li 0, 500 \n\t" \
+ " mtspr 8, 0 #LR \n\t" \
+ " li 0, 4 \n\t" \
+ " mtspr 1, 0 #XER \n\t" \
+ " \n\t" \
+ " li 0, 11 \n\t" \
+ " li 2, 12 \n\t" \
+ " li 3, 13 \n\t" \
+ " li 4, 14 \n\t" \
+ " li 5, 15 \n\t" \
+ " li 6, 16 \n\t" \
+ " li 7, 17 \n\t" \
+ " li 8, 18 \n\t" \
+ " li 9, 19 \n\t" \
+ " li 10, 110 \n\t" \
+ " li 11, 111 \n\t" \
+ " li 12, 112 \n\t" \
+ " li 13, 113 \n\t" \
+ " li 14, 114 \n\t" \
+ " li 15, 115 \n\t" \
+ " li 16, 116 \n\t" \
+ " li 17, 117 \n\t" \
+ " li 18, 118 \n\t" \
+ " li 19, 119 \n\t" \
+ " li 20, 120 \n\t" \
+ " li 21, 121 \n\t" \
+ " li 22, 122 \n\t" \
+ " li 23, 123 \n\t" \
+ " li 24, 124 \n\t" \
+ " li 25, 125 \n\t" \
+ " li 26, 126 \n\t" \
+ " li 27, 127 \n\t" \
+ " li 28, 128 \n\t" \
+ " li 29, 129 \n\t" \
+ " li 30, 130 \n\t" \
+ " li 31, 131 \n\t" \
+ " \n\t" \
+ " cmpwi 0, 11 \n\t" \
+ " bne RegTest2Fail \n\t" \
+ " cmpwi 2, 12 \n\t" \
+ " bne RegTest2Fail \n\t" \
+ " cmpwi 3, 13 \n\t" \
+ " bne RegTest2Fail \n\t" \
+ " cmpwi 4, 14 \n\t" \
+ " bne RegTest2Fail \n\t" \
+ " cmpwi 5, 15 \n\t" \
+ " bne RegTest2Fail \n\t" \
+ " cmpwi 6, 16 \n\t" \
+ " bne RegTest2Fail \n\t" \
+ " cmpwi 7, 17 \n\t" \
+ " bne RegTest2Fail \n\t" \
+ " cmpwi 8, 18 \n\t" \
+ " bne RegTest2Fail \n\t" \
+ " cmpwi 9, 19 \n\t" \
+ " bne RegTest2Fail \n\t" \
+ " cmpwi 10, 110 \n\t" \
+ " bne RegTest2Fail \n\t" \
+ " cmpwi 11, 111 \n\t" \
+ " bne RegTest2Fail \n\t" \
+ " cmpwi 12, 112 \n\t" \
+ " bne RegTest2Fail \n\t" \
+ " cmpwi 13, 113 \n\t" \
+ " bne RegTest2Fail \n\t" \
+ " cmpwi 14, 114 \n\t" \
+ " bne RegTest2Fail \n\t" \
+ " cmpwi 15, 115 \n\t" \
+ " bne RegTest2Fail \n\t" \
+ " cmpwi 16, 116 \n\t" \
+ " bne RegTest2Fail \n\t" \
+ " cmpwi 17, 117 \n\t" \
+ " bne RegTest2Fail \n\t" \
+ " cmpwi 18, 118 \n\t" \
+ " bne RegTest2Fail \n\t" \
+ " cmpwi 19, 119 \n\t" \
+ " bne RegTest2Fail \n\t" \
+ " cmpwi 20, 120 \n\t" \
+ " bne RegTest2Fail \n\t" \
+ " cmpwi 21, 121 \n\t" \
+ " bne RegTest2Fail \n\t" \
+ " cmpwi 22, 122 \n\t" \
+ " bne RegTest2Fail \n\t" \
+ " cmpwi 23, 123 \n\t" \
+ " bne RegTest2Fail \n\t" \
+ " cmpwi 24, 124 \n\t" \
+ " bne RegTest2Fail \n\t" \
+ " cmpwi 25, 125 \n\t" \
+ " bne RegTest2Fail \n\t" \
+ " cmpwi 26, 126 \n\t" \
+ " bne RegTest2Fail \n\t" \
+ " cmpwi 27, 127 \n\t" \
+ " bne RegTest2Fail \n\t" \
+ " cmpwi 28, 128 \n\t" \
+ " bne RegTest2Fail \n\t" \
+ " cmpwi 29, 129 \n\t" \
+ " bne RegTest2Fail \n\t" \
+ " cmpwi 30, 130 \n\t" \
+ " bne RegTest2Fail \n\t" \
+ " cmpwi 31, 131 \n\t" \
+ " bne RegTest2Fail \n\t" \
+ " \n\t" \
+ " mfspr 0, 256 #USPRG0 \n\t" \
+ " cmpwi 0, 300 \n\t" \
+ " bne RegTest2Fail \n\t" \
+ " mfspr 0, 8 #LR \n\t" \
+ " cmpwi 0, 500 \n\t" \
+ " bne RegTest2Fail \n\t" \
+ " mfspr 0, 1 #XER \n\t" \
+ " cmpwi 0, 4 \n\t" \
+ " bne RegTest2Fail \n\t" \
+ " \n\t" \
+ " bl prvRegTest2Pass \n\t" \
+ " b RegTest2Start \n\t" \
+ " \n\t" \
+ "RegTest2Fail: \n\t" \
+ " \n\t" \
+ " \n\t" \
+ " bl prvRegTestFail \n\t" \
+ " b RegTest2Start \n\t" \
+ );
+}
+/*-----------------------------------------------------------*/
+
+/* This hook function will get called if there is a suspected stack overflow.
+An overflow can cause the task name to be corrupted, in which case the task
+handle needs to be used to determine the offending task. */
+void vApplicationStackOverflowHook( xTaskHandle xTask, signed char *pcTaskName );
+void vApplicationStackOverflowHook( xTaskHandle xTask, signed char *pcTaskName )
+{
+/* To prevent the optimiser removing the variables. */
+volatile xTaskHandle xTaskIn = xTask;
+volatile signed char *pcTaskNameIn = pcTaskName;
+
+ /* Remove compiler warnings. */
+ ( void ) xTaskIn;
+ ( void ) pcTaskNameIn;
+
+ /* The following three calls are simply to stop compiler warnings about the
+ functions not being used - they are called from the inline assembly. */
+ prvRegTest1Pass();
+ prvRegTest2Pass();
+ prvRegTestFail();
+
+ for( ;; );
+}
+
+
+
diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c new file mode 100644 index 000000000..9ea0119cb --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c @@ -0,0 +1,185 @@ +/*
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
+
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+ >>>NOTE<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details. You should have received a copy of the GNU General Public
+ License and the FreeRTOS license exception along with FreeRTOS; if not it
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained
+ by writing to Richard Barry, contact details for whom are available on the
+ FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong? *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, training, latest information,
+ license and contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool.
+
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
+ the code with commercial support, indemnification, and middleware, under
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
+ provide a safety engineered and independently SIL3 certified version under
+ the SafeRTOS brand: http://www.SafeRTOS.com.
+*/
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* Demo application includes. */
+#include "partest.h"
+
+/* Library includes. */
+#include "xparameters.h"
+#include "xgpio_l.h"
+
+/* Misc hardware specific definitions. */
+#define partstALL_AS_OUTPUT 0x00
+#define partstCHANNEL_1 0x01
+#define partstMAX_8BIT_LED 0x07
+
+/* The outputs are split into two IO sections, these variables maintain the
+current value of either section. */
+static unsigned portBASE_TYPE uxCurrentOutput8Bit, uxCurrentOutput5Bit;
+
+/*-----------------------------------------------------------*/
+/*
+ * Setup the IO for the LED outputs.
+ */
+void vParTestInitialise( void )
+{
+ /* Set both sets of LED's on the demo board to outputs. */
+ XGpio_mSetDataDirection( XPAR_LEDS_8BIT_BASEADDR, partstCHANNEL_1, partstALL_AS_OUTPUT );
+ XGpio_mSetDataDirection( XPAR_LEDS_POSITIONS_BASEADDR, partstCHANNEL_1, partstALL_AS_OUTPUT );
+
+ /* Start with all outputs off. */
+ uxCurrentOutput8Bit = 0;
+ XGpio_mSetDataReg( XPAR_LEDS_8BIT_BASEADDR, partstCHANNEL_1, 0x00 );
+ uxCurrentOutput5Bit = 0;
+ XGpio_mSetDataReg( XPAR_LEDS_POSITIONS_BASEADDR, partstCHANNEL_1, 0x00 );
+}
+/*-----------------------------------------------------------*/
+
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
+{
+unsigned portBASE_TYPE uxBaseAddress, *puxCurrentValue;
+
+ portENTER_CRITICAL();
+ {
+ /* Which IO section does the LED being set/cleared belong to? The
+ 8 bit or 5 bit outputs? */
+ if( uxLED <= partstMAX_8BIT_LED )
+ {
+ uxBaseAddress = XPAR_LEDS_8BIT_BASEADDR;
+ puxCurrentValue = &uxCurrentOutput5Bit;
+ }
+ else
+ {
+ uxBaseAddress = XPAR_LEDS_POSITIONS_BASEADDR;
+ puxCurrentValue = &uxCurrentOutput8Bit;
+ uxLED -= partstMAX_8BIT_LED;
+ }
+
+ /* Setup the bit mask accordingly. */
+ uxLED = 0x01 << uxLED;
+
+ /* Maintain the current output value. */
+ if( xValue )
+ {
+ *puxCurrentValue |= uxLED;
+ }
+ else
+ {
+ *puxCurrentValue &= ~uxLED;
+ }
+
+ /* Write the value to the port. */
+ XGpio_mSetDataReg( uxBaseAddress, partstCHANNEL_1, *puxCurrentValue );
+ }
+ portEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
+{
+unsigned portBASE_TYPE uxBaseAddress, *puxCurrentValue;
+
+ portENTER_CRITICAL();
+ {
+ /* Which IO section does the LED being toggled belong to? The
+ 8 bit or 5 bit outputs? */
+ if( uxLED <= partstMAX_8BIT_LED )
+ {
+
+ uxBaseAddress = XPAR_LEDS_8BIT_BASEADDR;
+ puxCurrentValue = &uxCurrentOutput5Bit;
+ }
+ else
+ {
+ uxBaseAddress = XPAR_LEDS_POSITIONS_BASEADDR;
+ puxCurrentValue = &uxCurrentOutput8Bit;
+ uxLED -= partstMAX_8BIT_LED;
+ }
+
+ /* Setup the bit mask accordingly. */
+ uxLED = 0x01 << uxLED;
+
+ /* Maintain the current output value. */
+ if( *puxCurrentValue & uxLED )
+ {
+ *puxCurrentValue &= ~uxLED;
+ }
+ else
+ {
+ *puxCurrentValue |= uxLED;
+ }
+
+ /* Write the value to the port. */
+ XGpio_mSetDataReg(uxBaseAddress, partstCHANNEL_1, *puxCurrentValue );
+ }
+ portEXIT_CRITICAL();
+}
+
+
diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c new file mode 100644 index 000000000..de24f713c --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c @@ -0,0 +1,250 @@ +/*
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
+
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+ >>>NOTE<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details. You should have received a copy of the GNU General Public
+ License and the FreeRTOS license exception along with FreeRTOS; if not it
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained
+ by writing to Richard Barry, contact details for whom are available on the
+ FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong? *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, training, latest information,
+ license and contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool.
+
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
+ the code with commercial support, indemnification, and middleware, under
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
+ provide a safety engineered and independently SIL3 certified version under
+ the SafeRTOS brand: http://www.SafeRTOS.com.
+*/
+
+
+/*
+ BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART
+*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "queue.h"
+#include "task.h"
+
+/* Demo application includes. */
+#include "serial.h"
+
+/* Library includes. */
+#include "xparameters.h"
+#include "xuartlite.h"
+#include "xuartlite_l.h"
+
+/*-----------------------------------------------------------*/
+
+/* Queues used to hold received characters, and characters waiting to be
+transmitted. */
+static xQueueHandle xRxedChars;
+static xQueueHandle xCharsForTx;
+
+/* Structure that maintains information on the UART being used. */
+static XUartLite xUART;
+
+/*
+ * Sample UART interrupt handler. Note this is used to demonstrate the kernel
+ * features and test the port - it is not intended to represent an efficient
+ * implementation.
+ */
+static void vSerialISR( XUartLite *pxUART );
+
+/*-----------------------------------------------------------*/
+
+xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
+{
+ /* NOTE: The baud rate used by this driver is determined by the hardware
+ parameterization of the UART Lite peripheral, and the baud value passed to
+ this function has no effect. */
+ ( void ) ulWantedBaud;
+
+ /* Create the queues used to hold Rx and Tx characters. */
+ xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
+ xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
+
+ /* Only initialise the UART if the queues were created correctly. */
+ if( ( xRxedChars != NULL ) && ( xCharsForTx != NULL ) )
+ {
+
+ XUartLite_Initialize( &xUART, XPAR_RS232_UART_1_DEVICE_ID );
+ XUartLite_ResetFifos( &xUART );
+ XUartLite_DisableInterrupt( &xUART );
+
+ if( xPortInstallInterruptHandler( XPAR_XPS_INTC_0_RS232_UART_1_INTERRUPT_INTR, ( XInterruptHandler )vSerialISR, (void *)&xUART ) == pdPASS )
+ {
+ /* xPortInstallInterruptHandler() could fail if
+ vPortSetupInterruptController() has not been called prior to this
+ function. */
+ XUartLite_EnableInterrupt( &xUART );
+ }
+ }
+
+ /* There is only one port so the handle is not used. */
+ return ( xComPortHandle ) 0;
+}
+/*-----------------------------------------------------------*/
+
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, portTickType xBlockTime )
+{
+ /* The port handle is not required as this driver only supports one UART. */
+ ( void ) pxPort;
+
+ /* Get the next character from the buffer. Return false if no characters
+ are available, or arrive before xBlockTime expires. */
+ if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
+ {
+ return pdTRUE;
+ }
+ else
+ {
+ return pdFALSE;
+ }
+}
+/*-----------------------------------------------------------*/
+
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, portTickType xBlockTime )
+{
+portBASE_TYPE xReturn = pdTRUE;
+
+ /* Just to remove compiler warning. */
+ ( void ) pxPort;
+
+ portENTER_CRITICAL();
+ {
+ /* If the UART FIFO is full we can block posting the new data on the
+ Tx queue. */
+ if( XUartLite_mIsTransmitFull( XPAR_RS232_UART_1_BASEADDR ) )
+ {
+ if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
+ {
+ xReturn = pdFAIL;
+ }
+ }
+ /* Otherwise, if there is data already in the queue we should add the
+ new data to the back of the queue to ensure the sequencing is
+ maintained. */
+ else if( uxQueueMessagesWaiting( xCharsForTx ) )
+ {
+ if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
+ {
+ xReturn = pdFAIL;
+ }
+ }
+ /* If the UART FIFO is not full and there is no data already in the
+ queue we can write directly to the FIFO without disrupting the
+ sequence. */
+ else
+ {
+ XIo_Out32( XPAR_RS232_UART_1_BASEADDR + XUL_TX_FIFO_OFFSET, cOutChar );
+ }
+ }
+ portEXIT_CRITICAL();
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vSerialClose( xComPortHandle xPort )
+{
+ /* Not supported as not required by the demo application. */
+ ( void ) xPort;
+}
+/*-----------------------------------------------------------*/
+
+static void vSerialISR( XUartLite *pxUART )
+{
+unsigned long ulISRStatus;
+portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE, lDidSomething;
+char cChar;
+
+ /* Just to remove compiler warning. */
+ ( void ) pxUART;
+
+ do
+ {
+ lDidSomething = pdFALSE;
+
+ ulISRStatus = XIo_In32( XPAR_RS232_UART_1_BASEADDR + XUL_STATUS_REG_OFFSET );
+
+ if( ( ulISRStatus & XUL_SR_RX_FIFO_VALID_DATA ) != 0 )
+ {
+ /* A character is available - place it in the queue of received
+ characters. This might wake a task that was blocked waiting for
+ data. */
+ cChar = ( char ) XIo_In32( XPAR_RS232_UART_1_BASEADDR + XUL_RX_FIFO_OFFSET );
+ xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken );
+ lDidSomething = pdTRUE;
+ }
+
+ if( ( ulISRStatus & XUL_SR_TX_FIFO_EMPTY ) != 0 )
+ {
+ /* There is space in the FIFO - if there are any characters queue for
+ transmission they can be sent to the UART now. This might unblock a
+ task that was waiting for space to become available on the Tx queue. */
+ if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE )
+ {
+ XIo_Out32( XPAR_RS232_UART_1_BASEADDR + XUL_TX_FIFO_OFFSET, cChar );
+ lDidSomething = pdTRUE;
+ }
+ }
+ } while( lDidSomething == pdTRUE );
+
+ /* If we woke any tasks we may require a context switch. */
+ if( xHigherPriorityTaskWoken )
+ {
+ portYIELD_FROM_ISR();
+ }
+}
+
+
+
diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/Version_Changes.log b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/Version_Changes.log new file mode 100644 index 000000000..bcb2b8bc6 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/Version_Changes.log @@ -0,0 +1,15 @@ + The following files will be modified: + system.mhs + system.mss + +-------------------------------------- + The following changes will be made: + Core ppc440mc_ddr2 2.00.a will be replaced by 2.00.b + Core clock_generator 3.00.a will be replaced by 3.01.a + + Driver cpu_ppc440 1.00.b will be replaced by 1.01.a + Driver iic 1.14.a will be replaced by 1.15.a +-------------------------------------- + The following changes need to be made manually by the user: + Core plbv46_pcie 3.00.b needs to be replaced by 4.01.a + Core xps_ethernetlite 2.01.a needs to be replaced by 3.00.a diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtSvgBLKD_Dimensions.xsl b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtSvgBLKD_Dimensions.xsl new file mode 100644 index 000000000..bf9bf9488 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtSvgBLKD_Dimensions.xsl @@ -0,0 +1,173 @@ +<?xml version="1.0" standalone="no"?> +<xsl:stylesheet version="1.0" + xmlns:svg="http://www.w3.org/2000/svg" + xmlns:xsl="http://www.w3.org/1999/XSL/Transform" + xmlns:exsl="http://exslt.org/common" + xmlns:xlink="http://www.w3.org/1999/xlink"> + +<xsl:output method="xml" version="1.0" encoding="UTF-8" indent="yes" + doctype-public="-//W3C//DTD SVG 1.0//EN" + doctype-system="http://www.w3.org/TR/SVG/DTD/svg10.dtd"/> + +<!-- + ====================================================== + BUS INTERFACE DIMENSIONS + ====================================================== +--> + +<xsl:variable name="BLKD_BIF_H" select="16"/> +<xsl:variable name="BLKD_BIF_W" select="32"/> + +<xsl:variable name="BLKD_BIFC_H" select="24"/> +<xsl:variable name="BLKD_BIFC_W" select="24"/> + +<xsl:variable name="BLKD_BIFC_dx" select="ceiling($BLKD_BIFC_W div 5)"/> +<xsl:variable name="BLKD_BIFC_dy" select="ceiling($BLKD_BIFC_H div 5)"/> +<xsl:variable name="BLKD_BIFC_Hi" select="($BLKD_BIFC_H - ($BLKD_BIFC_dy * 2))"/> +<xsl:variable name="BLKD_BIFC_Wi" select="($BLKD_BIFC_W - ($BLKD_BIFC_dx * 2))"/> + +<xsl:variable name="BLKD_BIF_TYPE_ONEWAY" select="'OneWay'"/> + +<!-- + ====================================================== + GLOLBAL BUS INTERFACE DIMENSIONS + (Define for global MdtSVG_BifShapes.xsl which is used across all + diagrams to define the shapes of bifs the same across all diagrams) + ====================================================== +--> + +<xsl:variable name="BIF_H" select="$BLKD_BIF_H"/> +<xsl:variable name="BIF_W" select="$BLKD_BIF_W"/> + +<xsl:variable name="BIFC_H" select="$BLKD_BIFC_H"/> +<xsl:variable name="BIFC_W" select="$BLKD_BIFC_W"/> + +<xsl:variable name="BIFC_dx" select="$BLKD_BIFC_dx"/> +<xsl:variable name="BIFC_dy" select="$BLKD_BIFC_dy"/> + +<xsl:variable name="BIFC_Hi" select="$BLKD_BIFC_Hi"/> +<xsl:variable name="BIFC_Wi" select="$BLKD_BIFC_Wi"/> + + +<!-- + ====================================================== + BUS DIMENSIONS + ====================================================== +--> + +<xsl:variable name="BLKD_P2P_BUS_W" select="($BLKD_BUS_ARROW_H - ($BLKD_BUS_ARROW_G * 2))"/> +<xsl:variable name="BLKD_SBS_LANE_H" select="($BLKD_MOD_H + ($BLKD_BIF_H * 2))"/> +<xsl:variable name="BLKD_BUS_LANE_W" select="($BLKD_BIF_W + ($BLKD_MOD_BIF_GAP_H * 2))"/> +<xsl:variable name="BLKD_BUS_ARROW_W" select="ceiling($BLKD_BIFC_W div 3)"/> +<xsl:variable name="BLKD_BUS_ARROW_H" select="ceiling($BLKD_BIFC_H div 2)"/> +<xsl:variable name="BLKD_BUS_ARROW_G" select="ceiling($BLKD_BIFC_W div 12)"/> + + +<!-- + ====================================================== + IO PORT DIMENSIONS + ====================================================== +--> + +<xsl:variable name="BLKD_IOP_H" select="16"/> +<xsl:variable name="BLKD_IOP_W" select="16"/> +<xsl:variable name="BLKD_IOP_SPC" select="12"/> + + +<!-- + ====================================================== + INTERRUPT NOTATION DIMENSIONS + ====================================================== +--> + +<xsl:variable name="BLKD_INTR_W" select="18"/> +<xsl:variable name="BLKD_INTR_H" select="18"/> + +<!-- + ====================================================== + MODULE DIMENSIONS + ====================================================== +--> + +<xsl:variable name="BLKD_MOD_IO_GAP" select="8"/> + +<xsl:variable name="BLKD_MOD_W" select="( ($BLKD_BIF_W * 2) + ($BLKD_MOD_BIF_GAP_H * 1) + ($BLKD_MOD_LANE_W * 2))"/> +<xsl:variable name="BLKD_MOD_H" select="($BLKD_MOD_LABEL_H + ($BLKD_BIF_H * 1) + ($BLKD_MOD_BIF_GAP_V * 1) + ($BLKD_MOD_LANE_H * 2))"/> + +<xsl:variable name="BLKD_MOD_BIF_GAP_H" select="ceiling($BLKD_BIF_H div 4)"/> +<xsl:variable name="BLKD_MOD_BIF_GAP_V" select="ceiling($BLKD_BIFC_H div 2)"/> + +<xsl:variable name="BLKD_MOD_LABEL_W" select="(($BLKD_BIF_W * 2) + $BLKD_MOD_BIF_GAP_H)"/> +<xsl:variable name="BLKD_MOD_LABEL_H" select="(($BLKD_BIF_H * 2) + ceiling($BLKD_BIF_H div 3))"/> + +<xsl:variable name="BLKD_MOD_LANE_W" select="ceiling($BLKD_BIF_W div 3)"/> +<xsl:variable name="BLKD_MOD_LANE_H" select="ceiling($BLKD_BIF_H div 4)"/> + +<xsl:variable name="BLKD_MOD_EDGE_W" select="ceiling($BLKD_MOD_LANE_W div 2)"/> +<xsl:variable name="BLKD_MOD_SHAPES_G" select="($BLKD_BIF_W + $BLKD_BIF_W)"/> + +<xsl:variable name="BLKD_MOD_BKTLANE_H" select="$BLKD_BIF_H"/> +<xsl:variable name="BLKD_MOD_BKTLANE_W" select="$BLKD_BIF_H"/> + +<xsl:variable name="BLKD_MOD_BUCKET_G" select="ceiling($BLKD_BIF_W div 2)"/> + +<xsl:variable name="BLKD_MPMC_MOD_H" select="(($BLKD_BIF_H * 1) + ($BLKD_MOD_BIF_GAP_V * 2) + ($BLKD_MOD_LANE_H * 2))"/> + + +<!-- + ====================================================== + GLOBAL DIAGRAM DIMENSIONS + ====================================================== +--> + +<xsl:variable name="BLKD_IORCHAN_H" select="$BLKD_BIF_H"/> +<xsl:variable name="BLKD_IORCHAN_W" select="$BLKD_BIF_H"/> + +<xsl:variable name="BLKD_PRTCHAN_H" select="($BLKD_BIF_H * 2) + ceiling($BLKD_BIF_H div 2)"/> +<xsl:variable name="BLKD_PRTCHAN_W" select="($BLKD_BIF_H * 2) + ceiling($BLKD_BIF_H div 2) + 8"/> + +<xsl:variable name="BLKD_DRAWAREA_MIN_W" select="(($BLKD_MOD_BKTLANE_W * 2) + (($BLKD_MOD_W * 3) + ($BLKD_MOD_BUCKET_G * 2)))"/> + +<xsl:variable name="BLKD_INNER_X" select="($BLKD_PRTCHAN_W + $BLKD_IORCHAN_W + $BLKD_INNER_GAP)"/> +<xsl:variable name="BLKD_INNER_Y" select="($BLKD_PRTCHAN_H + $BLKD_IORCHAN_H + $BLKD_INNER_GAP)"/> +<xsl:variable name="BLKD_INNER_GAP" select="ceiling($BLKD_MOD_W div 2)"/> + +<xsl:variable name="BLKD_SBS2IP_GAP" select="$BLKD_MOD_H"/> +<xsl:variable name="BLKD_BRIDGE_GAP" select="($BLKD_BUS_LANE_W * 4)"/> +<xsl:variable name="BLKD_IP2UNK_GAP" select="$BLKD_MOD_H"/> +<xsl:variable name="BLKD_PROC2SBS_GAP" select="($BLKD_BIF_H * 2)"/> +<xsl:variable name="BLKD_IOR2PROC_GAP" select="$BLKD_BIF_W"/> +<xsl:variable name="BLKD_MPMC2PROC_GAP" select="($BLKD_BIF_H * 2)"/> +<xsl:variable name="BLKD_SPECS2KEY_GAP" select="$BLKD_BIF_W"/> +<xsl:variable name="BLKD_DRAWAREA2KEY_GAP" select="ceiling($BLKD_BIF_W div 3)"/> + +<xsl:variable name="BLKD_KEY_H" select="250"/> +<xsl:variable name="BLKD_KEY_W" select="($BLKD_DRAWAREA_MIN_W + ceiling($BLKD_DRAWAREA_MIN_W div 2.5))"/> + + +<xsl:variable name="BLKD_SPECS_H" select="100"/> +<xsl:variable name="BLKD_SPECS_W" select="300"/> + + + +<xsl:variable name="BLKD_BKT_MODS_PER_ROW" select="3"/> + +<!-- +<xsl:template name="Print_Dimensions"> + <xsl:message>MOD_LABEL_W : <xsl:value-of select="$MOD_LABEL_W"/></xsl:message> + <xsl:message>MOD_LABEL_H : <xsl:value-of select="$MOD_LABEL_H"/></xsl:message> + + <xsl:message>MOD_LANE_W : <xsl:value-of select="$MOD_LANE_W"/></xsl:message> + <xsl:message>MOD_LANE_H : <xsl:value-of select="$MOD_LANE_H"/></xsl:message> + + <xsl:message>MOD_EDGE_W : <xsl:value-of select="$MOD_EDGE_W"/></xsl:message> + <xsl:message>MOD_SHAPES_G : <xsl:value-of select="$MOD_SHAPES_G"/></xsl:message> + + <xsl:message>MOD_BKTLANE_W : <xsl:value-of select="$MOD_BKTLANE_W"/></xsl:message> + <xsl:message>MOD_BKTLANE_H : <xsl:value-of select="$MOD_BKTLANE_H"/></xsl:message> + <xsl:message>MOD_BUCKET_G : <xsl:value-of select="$MOD_BUCKET_G"/></xsl:message> + +</xsl:template> +--> + +</xsl:stylesheet> diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtSvgDiag_Colors.xsl b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtSvgDiag_Colors.xsl new file mode 100644 index 000000000..8de3842e4 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtSvgDiag_Colors.xsl @@ -0,0 +1,134 @@ +<?xml version="1.0" standalone="no"?> +<xsl:stylesheet version="1.0" + xmlns:svg="http://www.w3.org/2000/svg" + xmlns:xsl="http://www.w3.org/1999/XSL/Transform" + xmlns:exsl="http://exslt.org/common" + xmlns:xlink="http://www.w3.org/1999/xlink"> + +<xsl:variable name="COL_RED" select="'#AA0000'"/> +<xsl:variable name="COL_GRAY" select="'#E1E1E1'"/> +<xsl:variable name="COL_XLNX" select="'#AA0017'"/> +<xsl:variable name="COL_BLACK" select="'#000000'"/> +<xsl:variable name="COL_WHITE" select="'#FFFFFF'"/> +<xsl:variable name="COL_YELLOW" select="'#FFFFDD'"/> +<xsl:variable name="COL_YELLOW_LT" select="'#FFFFEE'"/> + +<xsl:variable name="COL_BG" select="'#CCCCCC'"/> +<xsl:variable name="COL_BG_LT" select="'#EEEEEE'"/> +<xsl:variable name="COL_BG_UNK" select="'#DDDDDD'"/> + +<xsl:variable name="COL_PROC_BG" select="'#FFCCCC'"/> +<xsl:variable name="COL_PROC_BG_MB" select="'#222222'"/> +<xsl:variable name="COL_PROC_BG_PP" select="'#90001C'"/> +<xsl:variable name="COL_PROC_BG_USR" select="'#666699'"/> + +<xsl:variable name="COL_MPMC_BG" select="'#8B0800'"/> + +<xsl:variable name="COL_MOD_BG" select="'#F0F0F0'"/> +<xsl:variable name="COL_MOD_SPRT" select="'#888888'"/> +<xsl:variable name="COL_MOD_MPRT" select="'#888888'"/> + + +<xsl:variable name="COL_IORING" select="'#000088'"/> +<xsl:variable name="COL_IORING_LT" select="'#CCCCFF'"/> +<xsl:variable name="COL_SYSPRT" select="'#0000BB'"/> + +<!-- +<xsl:variable name="COL_INTR_0" select="'#FF9900'"/> +<xsl:variable name="COL_INTR_1" select="'#00CCCC'"/> +<xsl:variable name="COL_INTR_2" select="'#33FF33'"/> +<xsl:variable name="COL_INTR_3" select="'#FF00CC'"/> +<xsl:variable name="COL_INTR_4" select="'#99FF33'"/> +<xsl:variable name="COL_INTR_5" select="'#0066CC'"/> +<xsl:variable name="COL_INTR_6" select="'#9933FF'"/> +<xsl:variable name="COL_INTR_7" select="'#3300FF'"/> +<xsl:variable name="COL_INTR_8" select="'#00FF33'"/> +<xsl:variable name="COL_INTR_9" select="'#FF3333'"/> +--> + +<xsl:variable name="COL_INTCS"> + <INTCCOLOR INDEX="0" RGB="#FF9900"/> + <INTCCOLOR INDEX="1" RGB="#00CCCC"/> + <INTCCOLOR INDEX="2" RGB="#33FF33"/> + <INTCCOLOR INDEX="3" RGB="#FF00CC"/> + <INTCCOLOR INDEX="4" RGB="#99FF33"/> + <INTCCOLOR INDEX="5" RGB="#0066CC"/> + <INTCCOLOR INDEX="6" RGB="#9933FF"/> + <INTCCOLOR INDEX="7" RGB="#3300FF"/> + <INTCCOLOR INDEX="8" RGB="#00FF33"/> + <INTCCOLOR INDEX="9" RGB="#FF3333"/> +</xsl:variable> + +<xsl:variable name="COL_BUSSTDS"> + + <BUSCOLOR BUSSTD="XIL" RGB="#990066" RGB_LT="#CC3399"/> + <BUSCOLOR BUSSTD="OCM" RGB="#0000DD" RGB_LT="#9999DD"/> + <BUSCOLOR BUSSTD="OPB" RGB="#339900" RGB_LT="#CCDDCC"/> + <BUSCOLOR BUSSTD="LMB" RGB="#7777FF" RGB_LT="#DDDDFF"/> + <BUSCOLOR BUSSTD="FSL" RGB="#CC00CC" RGB_LT="#FFBBFF"/> + <BUSCOLOR BUSSTD="DCR" RGB="#6699FF" RGB_LT="#BBDDFF"/> + <BUSCOLOR BUSSTD="FCB" RGB="#8C00FF" RGB_LT="#CCCCFF"/> + <BUSCOLOR BUSSTD="PLB" RGB="#FF5500" RGB_LT="#FFBB00"/> + <BUSCOLOR BUSSTD="PLBV34" RGB="#FF5500" RGB_LT="#FFBB00"/> + <BUSCOLOR BUSSTD="PLBV34_P2P" RGB="#FF5500" RGB_LT="#FFBB00"/> + <BUSCOLOR BUSSTD="PLBV46" RGB="#BB9955" RGB_LT="#FFFFDD"/> + <BUSCOLOR BUSSTD="PLBV46_P2P" RGB="#BB9955" RGB_LT="#FFFFDD"/> + +<!-- + <BUSCOLOR BUSSTD="PLBV46" RGB="#9966FF" RGB_LT="#CCCCFF"/> + <BUSCOLOR BUSSTD="PLBV46_P2P" RGB="#9966FF" RGB_LT="#CCCCFF"/> + <BUSCOLOR BUSSTD="PLB" RGB="#FFAA33" RGB_LT="#FFEE33"/> + <BUSCOLOR BUSSTD="PLBV46" RGB="#FF5500" RGB_LT="#FFBB00"/> + <BUSCOLOR BUSSTD="PLBV46_P2P" RGB="#FF5500" RGB_LT="#FFBB00"/> +--> + + <BUSCOLOR BUSSTD="TARGET" RGB="#009999" RGB_LT="#00CCCC"/> + <BUSCOLOR BUSSTD="INITIATOR" RGB="#009999" RGB_LT="#00CCCC"/> + + <BUSCOLOR BUSSTD="USER" RGB="#009999" RGB_LT="#00CCCC"/> + <BUSCOLOR BUSSTD="KEY" RGB="#444444" RGB_LT="#888888"/> + +</xsl:variable> + +<xsl:template name="F_BusStd2RGB"> + <xsl:param name="iBusStd" select="'USER'"/> + + <xsl:choose> + <xsl:when test="exsl:node-set($COL_BUSSTDS)/BUSCOLOR[(@BUSSTD = $iBusStd)]/@RGB"> + <xsl:value-of select="exsl:node-set($COL_BUSSTDS)/BUSCOLOR[(@BUSSTD = $iBusStd)]/@RGB"/> + </xsl:when> + <xsl:otherwise> + <xsl:value-of select="exsl:node-set($COL_BUSSTDS)/BUSCOLOR[(@BUSSTD = 'USER')]/@RGB"/> + </xsl:otherwise> + </xsl:choose> +</xsl:template> + +<xsl:template name="F_BusStd2RGB_LT"> + <xsl:param name="iBusStd" select="'USER'"/> + + <xsl:choose> + <xsl:when test="exsl:node-set($COL_BUSSTDS)/BUSCOLOR[(@BUSSTD = $iBusStd)]/@RGB_LT"> + <xsl:value-of select="exsl:node-set($COL_BUSSTDS)/BUSCOLOR[(@BUSSTD = $iBusStd)]/@RGB_LT"/> + </xsl:when> + <xsl:otherwise> + <xsl:value-of select="exsl:node-set($COL_BUSSTDS)/BUSCOLOR[(@BUSSTD = 'USER')]/@RGB_LT"/> + </xsl:otherwise> + </xsl:choose> +</xsl:template> + +<xsl:template name="F_IntcIdx2RGB"> + <xsl:param name="iIntcIdx" select="'0'"/> + + <xsl:variable name="index_" select="$iIntcIdx mod 9"/> + + <xsl:choose> + <xsl:when test="exsl:node-set($COL_INTCS)/INTCCOLOR[(@INDEX = $index_)]/@RGB"> + <xsl:value-of select="exsl:node-set($COL_INTCS)/INTCCOLOR[(@INDEX = $index_)]/@RGB"/> + </xsl:when> + <xsl:otherwise> + <xsl:value-of select="exsl:node-set($COL_INTCS)/INTCCOLOR[(@INDEX = '0')]/@RGB"/> + </xsl:otherwise> + </xsl:choose> +</xsl:template> + +</xsl:stylesheet> diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtSvgDiag_Globals.xsl b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtSvgDiag_Globals.xsl new file mode 100644 index 000000000..990af6c6b --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtSvgDiag_Globals.xsl @@ -0,0 +1,46 @@ +<?xml version="1.0" standalone="no"?> +<xsl:stylesheet version="1.0" + xmlns:svg="http://www.w3.org/2000/svg" + xmlns:xsl="http://www.w3.org/1999/XSL/Transform" + xmlns:exsl="http://exslt.org/common" + xmlns:xlink="http://www.w3.org/1999/xlink"> + +<xsl:output method="xml" version="1.0" encoding="UTF-8" indent="yes" + doctype-public="-//W3C//DTD SVG 1.0//EN" + doctype-system="http://www.w3.org/TR/SVG/DTD/svg10.dtd"/> + +<xsl:variable name="G_ROOT" select="/"/> + +<xsl:variable name="G_BIFTYPES"> + + <BIFTYPE TYPE="SLAVE"/> + <BIFTYPE TYPE="MASTER"/> + <BIFTYPE TYPE="MASTER_SLAVE"/> + + <BIFTYPE TYPE="TARGET"/> + <BIFTYPE TYPE="INITIATOR"/> + + <BIFTYPE TYPE="MONITOR"/> + + <BIFTYPE TYPE="USER"/> + +</xsl:variable> + +<xsl:variable name="G_BUSSTDS"> + + <BUSSTD NAME="XIL"/> + <BUSSTD NAME="OCM"/> + <BUSSTD NAME="OPB"/> + <BUSSTD NAME="LMB"/> + <BUSSTD NAME="FSL"/> + <BUSSTD NAME="DCR"/> + <BUSSTD NAME="FCB"/> + <BUSSTD NAME="PLB"/> + <BUSSTD NAME="PLBV46"/> + <BUSSTD NAME="PLBV46_P2P"/> + + <BUSSTD NAME="USER"/> +</xsl:variable> + + +</xsl:stylesheet> diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtSvgDiag_StyleDefs.xsl b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtSvgDiag_StyleDefs.xsl new file mode 100644 index 000000000..db7f0f354 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtSvgDiag_StyleDefs.xsl @@ -0,0 +1,580 @@ +<?xml version="1.0" standalone="no"?> +<xsl:stylesheet version="1.0" + xmlns:svg="http://www.w3.org/2000/svg" + xmlns:xsl="http://www.w3.org/1999/XSL/Transform" + xmlns:exsl="http://exslt.org/common" + xmlns:xlink="http://www.w3.org/1999/xlink"> + +<xsl:output method="xml" version="1.0" encoding="UTF-8" indent="yes" + doctype-public="-//W3C//DTD SVG 1.0//EN" + doctype-system="http://www.w3.org/TR/SVG/DTD/svg10.dtd"/> + +<!-- + ====================================================== + Function to put TEXT CSS and other Internal + Styling properties directly into the output + svg. The Qt 4.3 Renderer + cannot handle separate CSS StyleSheets + ====================================================== +--> +<xsl:template name="F_WriteText"> + + <xsl:param name="iClass" select="'_UNKNOWN_'"/> + <xsl:param name="iText" select="' '"/> + <xsl:param name="iX" select="'0'"/> + <xsl:param name="iY" select="'0'"/> + +<!-- + <xsl:message>TEXT <xsl:value-of select="$iText"/></xsl:message> + <xsl:message>CLASS <xsl:value-of select="$iClass"/></xsl:message> +--> + + <xsl:element name="text"> + <xsl:attribute name="x"><xsl:value-of select="$iX"/></xsl:attribute> + <xsl:attribute name="y"><xsl:value-of select="$iY"/></xsl:attribute> + + <xsl:choose> + + <xsl:when test="$iClass = 'sharedbus_label'"> + <xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute> + <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute> + <xsl:attribute name="font-size"><xsl:value-of select="'12pt'"/></xsl:attribute> + <xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute> + <xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute> + <xsl:attribute name="text-anchor"><xsl:value-of select="'start'"/></xsl:attribute> + <xsl:attribute name="font-family"><xsl:value-of select="'Verdana Courier Arial Helvetica san-serif'"/></xsl:attribute> + </xsl:when> + + <xsl:when test="$iClass = 'p2pbus_label'"> + <xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute> + <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute> + <xsl:attribute name="font-size"><xsl:value-of select="'8pt'"/></xsl:attribute> + <xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute> + <xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute> + <xsl:attribute name="text-anchor"><xsl:value-of select="'start'"/></xsl:attribute> + <xsl:attribute name="font-family"><xsl:value-of select="'Verdana Courier Arial Helvetica san-serif'"/></xsl:attribute> + </xsl:when> + + <xsl:when test="$iClass = 'p2pbus_label_horiz'"> + <xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute> + <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute> + <xsl:attribute name="font-size"><xsl:value-of select="'12pt'"/></xsl:attribute> + <xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute> + <xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute> + <xsl:attribute name="text-anchor"><xsl:value-of select="'start'"/></xsl:attribute> + <xsl:attribute name="writing-mode"><xsl:value-of select="'tb'"/></xsl:attribute> + <xsl:attribute name="font-family"><xsl:value-of select="'Verdana Courier Arial Helvetica san-serif'"/></xsl:attribute> + </xsl:when> + + + <xsl:when test="$iClass = 'bif_label'"> + <xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute> + <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute> + <xsl:attribute name="font-size"><xsl:value-of select="'10pt'"/></xsl:attribute> + <xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute> + <xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute> + <xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute> + <xsl:attribute name="font-family"><xsl:value-of select="'Verdana Courier Arial Helvetica san-serif'"/></xsl:attribute> + </xsl:when> + + <xsl:when test="$iClass = 'bc_ipinst'"> + <xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute> + <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute> + <xsl:attribute name="font-size"><xsl:value-of select="'10pt'"/></xsl:attribute> + <xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute> + <xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute> + <xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute> + <xsl:attribute name="font-family"><xsl:value-of select="'Courier Arial Helvetica san-serif'"/></xsl:attribute> + </xsl:when> + + <xsl:when test="$iClass = 'bc_iptype'"> + <xsl:attribute name="fill"><xsl:value-of select="$COL_XLNX"/></xsl:attribute> + <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute> + <xsl:attribute name="font-size"><xsl:value-of select="'10pt'"/></xsl:attribute> + <xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute> + <xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute> + <xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute> + <xsl:attribute name="font-family"><xsl:value-of select="'Verdana Arial Helvetica san-serif'"/></xsl:attribute> + </xsl:when> + + <xsl:when test="$iClass = 'iogrp_label'"> + <xsl:attribute name="fill"><xsl:value-of select="$COL_IORING"/></xsl:attribute> + <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute> + <xsl:attribute name="font-size"><xsl:value-of select="'10pt'"/></xsl:attribute> + <xsl:attribute name="font-style"><xsl:value-of select="'normal'"/></xsl:attribute> + <xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute> + <xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute> + <xsl:attribute name="font-family"><xsl:value-of select="'Verdana Arial Helvetica san-serif'"/></xsl:attribute> + </xsl:when> + + <xsl:when test="$iClass = 'mpmc_title'"> + <xsl:attribute name="fill"><xsl:value-of select="$COL_WHITE"/></xsl:attribute> + <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute> + <xsl:attribute name="font-size"><xsl:value-of select="'16pt'"/></xsl:attribute> + <xsl:attribute name="font-style"><xsl:value-of select="'oblique'"/></xsl:attribute> + <xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute> + <xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute> + <xsl:attribute name="font-family"><xsl:value-of select="'Arial Helvetica san-serif'"/></xsl:attribute> + </xsl:when> + + <xsl:when test="$iClass = 'mpmc_biflabel'"> + <xsl:attribute name="fill"><xsl:value-of select="$COL_WHITE"/></xsl:attribute> + <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute> + <xsl:attribute name="font-size"><xsl:value-of select="'8pt'"/></xsl:attribute> + <xsl:attribute name="font-style"><xsl:value-of select="'normal'"/></xsl:attribute> + <xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute> + <xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute> + <xsl:attribute name="font-family"><xsl:value-of select="'Verdana Arial Helvetica san-serif'"/></xsl:attribute> + </xsl:when> + + <xsl:when test="$iClass = 'intr_symbol'"> + <xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute> + <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute> + <xsl:attribute name="font-size"><xsl:value-of select="'10pt'"/></xsl:attribute> + <xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute> + <xsl:attribute name="text-anchor"><xsl:value-of select="'start'"/></xsl:attribute> + <xsl:attribute name="font-family"><xsl:value-of select="'Arial Helvetica san-serif'"/></xsl:attribute> + </xsl:when> + + <xsl:when test="$iClass = 'bkt_label'"> + <xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute> + <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute> + <xsl:attribute name="font-size"><xsl:value-of select="'9pt'"/></xsl:attribute> + <xsl:attribute name="font-style"><xsl:value-of select="'normal'"/></xsl:attribute> + <xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute> + <xsl:attribute name="text-anchor"><xsl:value-of select="'start'"/></xsl:attribute> + <xsl:attribute name="font-family"><xsl:value-of select="'Arial Helvetica san-serif'"/></xsl:attribute> + </xsl:when> + + <xsl:when test="$iClass = 'ipclass_label'"> + <xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute> + <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute> + <xsl:attribute name="font-size"><xsl:value-of select="'9pt'"/></xsl:attribute> + <xsl:attribute name="font-style"><xsl:value-of select="'normal'"/></xsl:attribute> + <xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute> + <xsl:attribute name="text-anchor"><xsl:value-of select="'start'"/></xsl:attribute> + <xsl:attribute name="font-family"><xsl:value-of select="'Arial Helvetica san-serif'"/></xsl:attribute> + </xsl:when> + + <xsl:when test="$iClass = 'key_header'"> + <xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute> + <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute> + <xsl:attribute name="font-size"><xsl:value-of select="'10pt'"/></xsl:attribute> + <xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute> + <xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute> + <xsl:attribute name="font-family"><xsl:value-of select="'Arial Helvetica san-serif'"/></xsl:attribute> + </xsl:when> + + <xsl:when test="$iClass = 'key_title'"> + <xsl:attribute name="fill"><xsl:value-of select="$COL_XLNX"/></xsl:attribute> + <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute> + <xsl:attribute name="font-size"><xsl:value-of select="'14pt'"/></xsl:attribute> + <xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute> + <xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute> + <xsl:attribute name="font-family"><xsl:value-of select="'Arial Helvetica san-serif'"/></xsl:attribute> + </xsl:when> + + <xsl:when test="$iClass = 'key_label'"> + <xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute> + <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute> + <xsl:attribute name="font-size"><xsl:value-of select="'10pt'"/></xsl:attribute> + <xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute> + <xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute> + <xsl:attribute name="text-anchor"><xsl:value-of select="'start'"/></xsl:attribute> + <xsl:attribute name="font-family"><xsl:value-of select="'Verdana Arial Helvetica san-serif'"/></xsl:attribute> + </xsl:when> + + <xsl:when test="$iClass = 'key_label_small'"> + <xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute> + <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute> + <xsl:attribute name="font-size"><xsl:value-of select="'8pt'"/></xsl:attribute> + <xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute> + <xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute> + <xsl:attribute name="text-anchor"><xsl:value-of select="'start'"/></xsl:attribute> + <xsl:attribute name="font-family"><xsl:value-of select="'Verdana Arial Helvetica san-serif'"/></xsl:attribute> + </xsl:when> + + + <xsl:when test="$iClass = 'key_label_ul'"> + <xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute> + <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute> + <xsl:attribute name="font-size"><xsl:value-of select="'10pt'"/></xsl:attribute> + <xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute> + <xsl:attribute name="font-weight"><xsl:value-of select="'bold'"/></xsl:attribute> + <xsl:attribute name="text-anchor"><xsl:value-of select="'start'"/></xsl:attribute> + <xsl:attribute name="text-decoration"><xsl:value-of select="'underline'"/></xsl:attribute> + <xsl:attribute name="font-family"><xsl:value-of select="'Verdana Arial Helvetica san-serif'"/></xsl:attribute> + </xsl:when> + + + <xsl:when test="$iClass = 'ipd_portlabel'"> + <xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute> + <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute> + <xsl:attribute name="font-size"><xsl:value-of select="'8pt'"/></xsl:attribute> + <xsl:attribute name="font-style"><xsl:value-of select="'normal'"/></xsl:attribute> + <xsl:attribute name="font-weight"><xsl:value-of select="'bold'"/></xsl:attribute> + <xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute> + <xsl:attribute name="font-family"><xsl:value-of select="'Verdana Arial Helvetica san-serif'"/></xsl:attribute> + </xsl:when> + + <xsl:when test="$iClass = 'ipd_biflabel'"> + <xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute> + <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute> + <xsl:attribute name="font-size"><xsl:value-of select="'8pt'"/></xsl:attribute> + <xsl:attribute name="font-style"><xsl:value-of select="'normal'"/></xsl:attribute> + <xsl:attribute name="font-weight"><xsl:value-of select="'bold'"/></xsl:attribute> + <xsl:attribute name="font-family"><xsl:value-of select="'Verdana Arial Helvetica san-serif'"/></xsl:attribute> + </xsl:when> + + <xsl:when test="$iClass = 'ipd_iptype'"> + <xsl:attribute name="fill"><xsl:value-of select="$COL_XLNX"/></xsl:attribute> + <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute> + <xsl:attribute name="font-size"><xsl:value-of select="'8pt'"/></xsl:attribute> + <xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute> + <xsl:attribute name="font-weight"><xsl:value-of select="'bold'"/></xsl:attribute> + <xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute> + <xsl:attribute name="font-family"><xsl:value-of select="'Verdana Arial Helvetica san-serif'"/></xsl:attribute> + </xsl:when> + + <xsl:when test="$iClass = 'ipd_ipname'"> + <xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute> + <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute> + <xsl:attribute name="font-size"><xsl:value-of select="'8pt'"/></xsl:attribute> + <xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute> + <xsl:attribute name="font-weight"><xsl:value-of select="'bold'"/></xsl:attribute> + <xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute> + <xsl:attribute name="font-family"><xsl:value-of select="'Courier Arial Helvetica san-serif'"/></xsl:attribute> + </xsl:when> + + <xsl:when test="$iClass = 'blkd_spec_name'"> + <xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute> + <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute> + <xsl:attribute name="font-size"><xsl:value-of select="'10pt'"/></xsl:attribute> + <xsl:attribute name="font-weight"><xsl:value-of select="'bold'"/></xsl:attribute> + <xsl:attribute name="text-anchor"><xsl:value-of select="'start'"/></xsl:attribute> + <xsl:attribute name="font-family"><xsl:value-of select="'Arial Helvetica san-serif'"/></xsl:attribute> + </xsl:when> + + <xsl:when test="$iClass = 'blkd_spec_value_mid'"> + <xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute> + <xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute> + <xsl:attribute name="font-size"><xsl:value-of select="'10pt'"/></xsl:attribute> + <xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute> + <xsl:attribute name="font-weight"><xsl:value-of select="'bold'"/></xsl:attribute> + <xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute> + <xsl:attribute name="font-family"><xsl:value-of select="'Courier Arial Helvetica san-serif'"/></xsl:attribute> + </xsl:when> + + <xsl:otherwise><xsl:message>UNKNOWN Text style class <xsl:value-of select="$iClass"/></xsl:message></xsl:otherwise> + </xsl:choose> + + <xsl:value-of select="$iText"/> + </xsl:element> + +</xsl:template> + +</xsl:stylesheet> + +<!-- + text.ioplblgrp { + fill: #000088; + stroke: none; + font-size: 10pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + text.iplabel { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: 800; + text-anchor: middle; + font-family: Courier Arial Helvetica sans-serif; + } + + text.iptype { + fill: #AA0017; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.busintlabel { + fill: #810017; + stroke: none; + font-size: 7pt; + font-style: italic; + font-weight: 900; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.mpmcbiflabel { + fill: #FFFFFF; + stroke: none; + font-size: 6pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.buslabel { + fill: #CC3333; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + + + text.ipclass { + fill: #000000; + stroke: none; + font-size: 7pt; + font-style: normal; + font-weight: bold; + text-anchor: start; + font-family: Times Arial Helvetica sans-serif; + } + + text.procclass { + fill: #000000; + stroke: none; + font-size: 7pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: Times Arial Helvetica sans-serif; + } + + + text.portlabel { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.ipdbiflbl { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: normal; + font-weight: bold; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.mmMHeader { + fill: #FFFFFF; + stroke: none; + font-size: 10pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.mmSHeader { + fill: #810017; + stroke: none; + font-size: 10pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + + + text.dbglabel { + fill: #555555; + stroke: none; + font-size: 8pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + font-family: Times Arial Helvetica sans-serif; + } + + text.iopnumb { + fill: #555555; + stroke: none; + font-size: 10pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + + + tspan.iopgrp { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + baseline-shift:super; + font-family: Arial Courier san-serif; + } + + + text.biflabel { + fill: #000000; + stroke: none; + font-size: 6pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + + } + + text.p2pbuslabel { + fill: #000000; + stroke: none; + font-size: 10pt; + font-style: italic; + font-weight: bold; + text-anchor: start; + writing-mode: tb; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.mpbuslabel { + fill: #000000; + stroke: none; + font-size: 6pt; + font-style: italic; + font-weight: bold; + text-anchor: start; + writing-mode: tb; + font-family: Verdana Arial Helvetica sans-serif; + } + + + text.sharedbuslabel { + fill: #000000; + stroke: none; + font-size: 10pt; + font-style: italic; + font-weight: bold; + text-anchor: start; + font-family: Verdana Arial Helvetica sans-serif; + } + + + text.splitbustxt { + fill: #000000; + stroke: none; + font-size: 6pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: sans-serif; + } + + text.horizp2pbuslabel { + fill: #000000; + stroke: none; + font-size: 6pt; + font-style: italic; + font-weight: bold; + text-anchor: start; + font-family: Verdana Arial Helvetica sans-serif; + } + + + + text.keytitle { + fill: #AA0017; + stroke: none; + font-size: 12pt; + font-weight: bold; + text-anchor: middle; + font-family: Arial Helvetica sans-serif; + } + + text.keyheader { + fill: #000000; + stroke: none; + font-size: 10pt; + font-weight: bold; + text-anchor: middle; + font-family: Arial Helvetica sans-serif; + } + + text.keylabel { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: start; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.keylblul { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: start; + text-decoration: underline; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.specsheader { + fill: #000000; + stroke: none; + font-size: 10pt; + font-weight: bold; + text-anchor: start; + font-family: Arial Helvetica sans-serif; + } + + text.specsvalue { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: start; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.specsvaluemid { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.intrsymbol { + fill: #000000; + stroke: none; + font-size: 8pt; + font-weight: bold; + text-anchor: start; + font-family: Arial Helvetica sans-serif; + } + +-->
\ No newline at end of file diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtTinySvgBLKD_BusLaneSpaces.xsl b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtTinySvgBLKD_BusLaneSpaces.xsl new file mode 100644 index 000000000..cf3864ebc --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtTinySvgBLKD_BusLaneSpaces.xsl @@ -0,0 +1,2757 @@ +<?xml version="1.0" standalone="no"?> + +<xsl:stylesheet version="1.0" + xmlns:svg="http://www.w3.org/2000/svg" + xmlns:xsl="http://www.w3.org/1999/XSL/Transform" + xmlns:math="http://exslt.org/math" + xmlns:exsl="http://exslt.org/common" + xmlns:xlink="http://www.w3.org/1999/xlink" + extension-element-prefixes="math"> + +<xsl:output method="xml" version="1.0" encoding="UTF-8" indent="yes" + doctype-public="-//W3C//DTD SVG 1.0//EN" + doctype-system="http://www.w3.org/TR/SVG/DTD/svg10.dtd"/> + + +<!-- + =========================================================== + Handle Bucket connections to the shared busses. + =========================================================== +--> + +<xsl:template name="BCLaneSpace_BucketToSharedBus"> + + <xsl:param name="iBusStd" select="'NONE'"/> + <xsl:param name="iBifType" select="'NONE'"/> + <xsl:param name="iBusName" select="'NONE'"/> + <xsl:param name="iStackToEast" select="'NONE'"/> + <xsl:param name="iStackToWest" select="'NONE'"/> + <xsl:param name="iStackToEast_W" select="0"/> + <xsl:param name="iStackToWest_W" select="0"/> + <xsl:param name="iLaneInSpace_X" select="0"/> + <xsl:param name="iSpaceSharedBus_Y" select="0"/> + +<!-- + <xsl:message>Stack To East <xsl:value-of select="$iStackToEast"/></xsl:message> + <xsl:message>Stack to West <xsl:value-of select="$iStackToWest"/></xsl:message> + <xsl:message>Stack to East Width <xsl:value-of select="$iStackToEast_W"/></xsl:message> + <xsl:message>Stack to West Width <xsl:value-of select="$iStackToWest_W"/></xsl:message> + <xsl:message>Shared Bus Y <xsl:value-of select="$iSpaceSharedBus_Y"/></xsl:message> + <xsl:message>Lane in space X <xsl:value-of select="$iLaneInSpace_X"/></xsl:message> +--> + + <xsl:variable name="busColor_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="$iBusStd"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="sbs_idx_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE= $iBusName)]/@BUS_INDEX"/> + <xsl:variable name="sbs_name_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET[(@BUS_INDEX = $sbs_idx_)]/@BUSNAME"/> + + <xsl:variable name="sbs_bc_y_" select="($iSpaceSharedBus_Y + ($sbs_idx_ * $BLKD_SBS_LANE_H))"/> + + <xsl:variable name="bktshp_hori_idx_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET[(@BUS_INDEX = $sbs_idx_)]/@STACK_HORIZ_INDEX"/> + <xsl:variable name="bktshp_vert_idx_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET[(@BUS_INDEX = $sbs_idx_)]/@SHAPE_VERTI_INDEX"/> + + <xsl:variable name="space_W_"> + <xsl:call-template name="F_Calc_Space_Width"> + <xsl:with-param name="iStackToEast" select="$iStackToEast"/> + <xsl:with-param name="iStackToWest" select="$iStackToWest"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name ="extSpaceWest_W_" select="ceiling($iStackToWest_W div 2)"/> + <xsl:variable name ="extSpaceEast_W_" select="ceiling($iStackToEast_W div 2)"/> + +<!-- + <xsl:message>Ext Shape to West <xsl:value-of select="$extSpaceWest_W_"/></xsl:message> + <xsl:message>Ext Shape to East <xsl:value-of select="$extSpaceEast_W_"/></xsl:message> +--> + <xsl:variable name="bktshp_Y_"> + <xsl:call-template name="F_Calc_Stack_Shape_Y"> + <xsl:with-param name="iHorizIdx" select="$bktshp_hori_idx_"/> + <xsl:with-param name="iVertiIdx" select="$bktshp_vert_idx_"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="sbsStack_H_diff_"> + <xsl:choose> + <xsl:when test=" (($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))">0</xsl:when> + <xsl:when test="not(($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))"> + + <xsl:variable name="stackToWest_AbvSbs_H_"> + <xsl:call-template name="F_Calc_Stack_AbvSbs_Height"> + <xsl:with-param name="iStackIdx" select="$iStackToWest"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="stackToEast_AbvSbs_H_"> + <xsl:call-template name="F_Calc_Stack_AbvSbs_Height"> + <xsl:with-param name="iStackIdx" select="$iStackToEast"/> + </xsl:call-template> + </xsl:variable> + +<!-- + <xsl:message>stack to west H <xsl:value-of select="$stackToWest_AbvSbs_H_"/></xsl:message> + <xsl:message>stack to east H <xsl:value-of select="$stackToEast_AbvSbs_H_"/></xsl:message> +--> + <xsl:if test="($stackToWest_AbvSbs_H_ > $stackToEast_AbvSbs_H_)"> + <xsl:value-of select="($stackToWest_AbvSbs_H_ - $stackToEast_AbvSbs_H_)"/> + </xsl:if> + + <xsl:if test="not($stackToWest_AbvSbs_H_ > $stackToEast_AbvSbs_H_)">0</xsl:if> + </xsl:when> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="vert_line_x_" select="($iLaneInSpace_X + ceiling($BLKD_BIFC_W div 2))"/> + <xsl:variable name="vert_line_y1_" select="($iSpaceSharedBus_Y + ($sbs_idx_ * $BLKD_SBS_LANE_H) + ceiling($BLKD_BIFC_W div 2))"/> + <xsl:variable name="vert_line_y2_" select="($bktshp_Y_ + ceiling($BLKD_MOD_W div 2) + $sbsStack_H_diff_)"/> + <xsl:variable name="bcInSpace_X_" select="($iLaneInSpace_X + ceiling($BLKD_BIFC_W div 2) - ceiling($BLKD_BUS_ARROW_W div 2))"/> + + +<!-- + <xsl:message>Shared Bus Y <xsl:value-of select="$G_SharedBus_Y"/></xsl:message> + <xsl:message>Vert Bus Y <xsl:value-of select="$vert_line_y1_"/></xsl:message> + <xsl:message>vert y1 <xsl:value-of select="$vert_line_y1_"/></xsl:message> + <xsl:message>vert y2 <xsl:value-of select="$vert_line_y2_"/></xsl:message> +--> + + <xsl:variable name="horz_line_y_" select="$vert_line_y2_"/> + <xsl:variable name="horz_line_x1_" select="$vert_line_x_"/> + <xsl:variable name="horz_line_x2_" select="($space_W_ + $extSpaceWest_W_ + $extSpaceEast_W_)"/> + + <xsl:variable name="v_bus_ul_x_" select="$vert_line_x_"/> + <xsl:variable name="v_bus_ul_y_" select="$vert_line_y1_"/> + <xsl:variable name="v_bus_width_" select="$BLKD_P2P_BUS_W"/> + + <xsl:variable name="v_bus_height_" select="(($vert_line_y2_ - $vert_line_y1_) - ceiling($BLKD_BIFC_H div 2))"/> + + <xsl:variable name="h_bus_ul_x_" select="$v_bus_ul_x_"/> + <xsl:variable name="h_bus_ul_y_" select="$vert_line_y2_ - $BLKD_BIFC_H + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_P2P_BUS_W div 2)"/> + <xsl:variable name="h_bus_width_" select="ceiling($space_W_ div 2) + $extSpaceEast_W_"/> + <xsl:variable name="h_bus_height_" select="$BLKD_P2P_BUS_W"/> + +<!-- + <xsl:variable name="h_bus_width_" select="($space_W_ + ceiling(($extSpaceWest_W_ + $extSpaceEast_W_) div 2) - $BLKD_BIFC_W)"/> + <xsl:message>v bus x <xsl:value-of select="$v_bus_ul_x_"/></xsl:message> + <xsl:message>v bus y <xsl:value-of select="$v_bus_ul_y_"/></xsl:message> + <xsl:message>v bus w <xsl:value-of select="$v_bus_width_"/></xsl:message> + <xsl:message>v bus y1 <xsl:value-of select="$vert_line_y1_"/></xsl:message> + <xsl:message>v bus y2 <xsl:value-of select="$vert_line_y2_"/></xsl:message> + <xsl:message>v bus h <xsl:value-of select="$v_bus_height_"/></xsl:message> + <xsl:message>h bus w <xsl:value-of select="$h_bus_width_"/></xsl:message> +--> + + + <!-- Draw rectangular parts of the bus --> + <rect x="{$v_bus_ul_x_}" + y="{$v_bus_ul_y_ - 2}" + width= "{$v_bus_width_}" + height="{$v_bus_height_}" + style="stroke:none; fill:{$busColor_}"/> + + <rect x="{$h_bus_ul_x_}" + y="{$h_bus_ul_y_ - 5}" + width= "{$h_bus_width_}" + height="{$h_bus_height_}" + style="stroke:none; fill:{$busColor_}"/> +<!-- +--> + +</xsl:template> + +<!-- + =========================================================== + Handle Processor's Shared bus connections. + =========================================================== +--> + +<xsl:template name="BCLaneSpace_ProcBifToSharedBus"> + + <xsl:param name="iBusStd" select="'NONE'"/> + <xsl:param name="iBusName" select="'NONE'"/> + <xsl:param name="iBifType" select="'NONE'"/> + <xsl:param name="iStackToEast" select="'NONE'"/> + <xsl:param name="iStackToWest" select="'NONE'"/> + <xsl:param name="iStackToEast_W" select="0"/> + <xsl:param name="iStackToWest_W" select="0"/> + <xsl:param name="iLaneInSpace_X" select="0"/> + <xsl:param name="iSpaceSharedBus_Y" select="0"/> + +<!-- + <xsl:message>Proc Bus Std <xsl:value-of select="$iBusStd"/></xsl:message> + <xsl:message>Proc Bus Name <xsl:value-of select="$iBusName"/></xsl:message> + <xsl:message>Proc Bif Type <xsl:value-of select="$iBifType"/></xsl:message> +--> + + <xsl:variable name="busColor_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="$iBusStd"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="sbs_idx_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE= $iBusName)]/@BUS_INDEX"/> + <xsl:variable name="sbs_bc_y_" select="($iSpaceSharedBus_Y + ($sbs_idx_ * $BLKD_SBS_LANE_H))"/> + <xsl:variable name="procInst_" select="BUSCONN/@INSTANCE"/> + + +<!-- + <xsl:message>Shared Bus Idx <xsl:value-of select="$sbs_idx_"/></xsl:message> + <xsl:message>Proc inst <xsl:value-of select="$procInst_"/></xsl:message> +--> + + <xsl:variable name="procBif_Y_" select="((($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * BUSCONN/@BIF_Y) + ($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V))"/> + <xsl:variable name="procBifName_" select="BUSCONN/@BUSINTERFACE"/> + <xsl:variable name="procBifSide_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $procInst_)]/BUSINTERFACE[(@NAME = $procBifName_)]/@BIF_X"/> + <xsl:variable name="procBifType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $procInst_)]/BUSINTERFACE[(@NAME = $procBifName_)]/@TYPE"/> + + <xsl:variable name="procshp_hori_idx_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $procInst_)]/@STACK_HORIZ_INDEX"/> + <xsl:variable name="procshp_vert_idx_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $procInst_)]/@SHAPE_VERTI_INDEX"/> + + <xsl:variable name="space_W_"> + <xsl:call-template name="F_Calc_Space_Width"> + <xsl:with-param name="iStackToEast" select="$iStackToEast"/> + <xsl:with-param name="iStackToWest" select="$iStackToWest"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name ="extSpaceWest_W_" select="ceiling($iStackToWest_W div 2)"/> + <xsl:variable name ="extSpaceEast_W_" select="ceiling($iStackToEast_W div 2)"/> + + +<!-- + <xsl:message>Ext Space to West <xsl:value-of select="$extSpaceWest_W_"/></xsl:message> + <xsl:message>Ext Space to East <xsl:value-of select="$extSpaceEast_W_"/></xsl:message> + + <xsl:message>Ext Space to East <xsl:value-of select="$extSpaceEast_W_"/></xsl:message> + <xsl:message>Stack horiz <xsl:value-of select="$procshp_hori_idx_"/></xsl:message> + <xsl:message>Stack verti <xsl:value-of select="$procshp_vert_idx_"/></xsl:message> + <xsl:message>Proc Bif Y <xsl:value-of select="$procBif_Y_"/></xsl:message> +--> + + <xsl:variable name="procshp_Y_"> + <xsl:call-template name="F_Calc_Stack_Shape_Y"> + <xsl:with-param name="iHorizIdx" select="$procshp_hori_idx_"/> + <xsl:with-param name="iVertiIdx" select="$procshp_vert_idx_"/> + </xsl:call-template> + </xsl:variable> + + + <xsl:variable name="procStack_H_diff_"> + <xsl:choose> + <xsl:when test=" (($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))">0</xsl:when> + <xsl:when test="not(($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))"> + + <xsl:variable name="stackToWest_AbvSbs_H_"> + <xsl:call-template name="F_Calc_Stack_AbvSbs_Height"> + <xsl:with-param name="iStackIdx" select="$iStackToWest"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="stackToEast_AbvSbs_H_"> + <xsl:call-template name="F_Calc_Stack_AbvSbs_Height"> + <xsl:with-param name="iStackIdx" select="$iStackToEast"/> + </xsl:call-template> + </xsl:variable> + +<!-- + <xsl:message>stack to west H <xsl:value-of select="$stackToWest_AbvSbs_H_"/></xsl:message> + <xsl:message>stack to east H <xsl:value-of select="$stackToEast_AbvSbs_H_"/></xsl:message> +--> + <xsl:choose> + <xsl:when test="(($procshp_hori_idx_ = $iStackToEast) and ($stackToWest_AbvSbs_H_ > $stackToEast_AbvSbs_H_))"> + <xsl:value-of select="($stackToWest_AbvSbs_H_ - $stackToEast_AbvSbs_H_)"/> + </xsl:when> + <xsl:when test="(($procshp_hori_idx_ = $iStackToWest) and ($stackToEast_AbvSbs_H_ > $stackToWest_AbvSbs_H_))"> + <xsl:value-of select="($stackToEast_AbvSbs_H_ - $stackToWest_AbvSbs_H_)"/> + </xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + </xsl:when> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="bc_Y_" select="($procshp_Y_ + $procBif_Y_ + ceiling($BIF_H div 2) + $procStack_H_diff_) - ceiling($BLKD_BIFC_H div 2)"/> +<!-- + <xsl:variable name="bc_x_" select="($laneInSpace_X + ceiling($BLKD_BIFC_W div 2))"/> + <xsl:variable name="bc_x_" select="0"/> + <xsl:message>Test</xsl:message> +--> + + <xsl:variable name="bc_X_"> + <xsl:choose> + <xsl:when test="$procBifSide_ = '0'"> + <xsl:value-of select="($space_W_ + $extSpaceWest_W_ + $extSpaceEast_W_ - (ceiling($BLKD_MOD_W div 2) + $BLKD_BIFC_W))"/> +<!-- + <xsl:value-of select="($space_W_ + $extSpaceWest_W_ + $extSpaceEast_W_)"/> + <xsl:value-of select="($space_W_ - ceiling($BLKD_MOD_W div 2))"/> + <xsl:value-of select="$space_W_ + $extSpaceEast_W_"/> + <xsl:value-of select="($space_W_ + $extSpaceWest_W_ + $extSpaceEast_W_ - (ceiling($BLKD_MOD_W div 2) + $BLKD_BIFC_W))"/> +--> + </xsl:when> + <xsl:when test="$procBifSide_ = '1'"> + <xsl:value-of select="ceiling($BLKD_MOD_W div 2)"/> + </xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <!-- Place the bus connectijon --> + <use x="{$bc_X_}" y="{$bc_Y_}" xlink:href="#{$iBusStd}_busconn_{$procBifType_}"/> +<!-- +--> + <xsl:variable name="vert_line_x_" select="($iLaneInSpace_X + ceiling($BLKD_BIFC_W div 2))"/> + <xsl:variable name="vert_line_y1_" select="($procshp_Y_ + $procBif_Y_ + ceiling($BLKD_BIF_H div 2) + $procStack_H_diff_)"/> + <xsl:variable name="vert_line_y2_" select="($iSpaceSharedBus_Y + ($sbs_idx_ * $BLKD_SBS_LANE_H) + ceiling($BLKD_BIFC_W div 2))"/> + +<!-- + <xsl:message>Vert line Y1 <xsl:value-of select="$vert_line_y1_"/></xsl:message> + <xsl:message>Vert line Y2 <xsl:value-of select="$vert_line_y2_"/></xsl:message> +--> + + <xsl:variable name="v_bus_ul_y_"> + <xsl:choose> + <xsl:when test="$vert_line_y1_ > $vert_line_y2_"> + <xsl:value-of select="$vert_line_y2_"/> + </xsl:when> + <xsl:when test="$vert_line_y2_ > $vert_line_y1_"> + <xsl:value-of select="$vert_line_y1_"/> + </xsl:when> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="v_bus_ul_x_"> + <xsl:choose> + <xsl:when test="@ORIENTED='WEST'"> + <xsl:value-of select="($vert_line_x_ + $BLKD_MOD_BIF_GAP_H)"/> + </xsl:when> + <xsl:when test="@ORIENTED='EAST'"> + <xsl:value-of select="($vert_line_x_ - $BLKD_MOD_BIF_GAP_H)"/> + </xsl:when> + </xsl:choose> + </xsl:variable> + + + <xsl:variable name="v_bus_width_" select="$BLKD_P2P_BUS_W"/> + <xsl:variable name="v_bus_height_"> + <xsl:choose> + <xsl:when test="$vert_line_y1_ > $vert_line_y2_"> + <xsl:value-of select="($vert_line_y1_ - $vert_line_y2_) - $BLKD_P2P_BUS_W"/> + </xsl:when> + <xsl:when test="$vert_line_y2_ > $vert_line_y1_"> + <xsl:value-of select="($vert_line_y2_ - $vert_line_y1_) - $BLKD_P2P_BUS_W"/> + </xsl:when> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="h_bus_ul_x_"> + <xsl:choose> + <xsl:when test="@ORIENTED='WEST'"> + <xsl:value-of select="($bc_X_ + $BLKD_BIFC_W - ceiling(($BLKD_BIFC_W - $BLKD_BIFC_Wi) div 2))"/> +<!-- + <xsl:value-of select="$v_bus_ul_x_"/> +--> + </xsl:when> + <xsl:when test="@ORIENTED='EAST'"> + <xsl:value-of select="$v_bus_ul_x_"/> + </xsl:when> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="h_bus_ul_y_"> + <xsl:choose> + <xsl:when test="$vert_line_y1_ > $vert_line_y2_"> + <xsl:value-of select="$vert_line_y2_ - ceiling($BLKD_P2P_BUS_W div 2)"/> + </xsl:when> + <xsl:when test="$vert_line_y2_ > $vert_line_y1_"> + <xsl:value-of select="$vert_line_y1_ - ceiling($BLKD_P2P_BUS_W div 2)"/> + </xsl:when> + </xsl:choose> + </xsl:variable> + + + <xsl:variable name="h_bus_height_" select="$BLKD_P2P_BUS_W"/> + <xsl:variable name="h_bus_width_"> + <xsl:choose> + <xsl:when test="@ORIENTED='WEST'"> + <xsl:value-of select="$v_bus_ul_x_ - $h_bus_ul_x_ + $BLKD_P2P_BUS_W"/> + </xsl:when> + <xsl:when test="@ORIENTED='EAST'"> + <xsl:value-of select="($bc_X_ - $v_bus_ul_x_) + ceiling(($BLKD_BIFC_W - $BLKD_BIFC_Wi) div 2) + 1"/> + </xsl:when> + </xsl:choose> + </xsl:variable> + +<!-- + <xsl:if test="(@ORIENTED = 'WEST')"> + </xsl:if> + + <xsl:message>bc_X_ <xsl:value-of select="$bc_X_"/></xsl:message> + <xsl:message>v_bus_ul_x <xsl:value-of select="$v_bus_ul_x_"/></xsl:message> + <xsl:message>h_bus_width <xsl:value-of select="$h_bus_width_"/></xsl:message> + <xsl:message>h_bus_ul_y <xsl:value-of select="$h_bus_ul_y_"/></xsl:message> +--> + + <rect x="{$v_bus_ul_x_}" + y="{$v_bus_ul_y_ + 2}" + width= "{$v_bus_width_}" + height="{$v_bus_height_}" + style="stroke:none; fill:{$busColor_}"/> + + <rect x="{$h_bus_ul_x_}" + y="{$h_bus_ul_y_}" + width= "{$h_bus_width_}" + height="{$h_bus_height_}" + style="stroke:none; fill:{$busColor_}"/> +</xsl:template> + +<!-- + =========================================================== + Handle non Processor Sharedebus connections. + =========================================================== +--> + +<xsl:template name="BCLaneSpace_NonProcBifToSharedBus"> + + <xsl:param name="iBusStd" select="'NONE'"/> + <xsl:param name="iBifType" select="'NONE'"/> + <xsl:param name="iBusName" select="'NONE'"/> + <xsl:param name="iStackToEast" select="'NONE'"/> + <xsl:param name="iStackToWest" select="'NONE'"/> + <xsl:param name="iStackToEast_W" select="0"/> + <xsl:param name="iStackToWest_W" select="0"/> + <xsl:param name="iLaneInSpace_X" select="0"/> + <xsl:param name="iSpaceSharedBus_Y" select="0"/> + + + <xsl:variable name="sbs_idx_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE= $iBusName)]/@BUS_INDEX"/> + <xsl:variable name="sbs_bc_y_" select="($iSpaceSharedBus_Y + ($sbs_idx_ * $BLKD_SBS_LANE_H))"/> +<!-- + <xsl:variable name="sbs_bc_y_" select="($G_SharedBus_Y + ($sbs_idx_ * $BLKD_SBS_LANE_H))"/> +--> + + <xsl:variable name="cmplxInst_" select="BUSCONN/@INSTANCE"/> + + <xsl:variable name="cmplxBif_Y_" select="((($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * BUSCONN/@BIF_Y) + ($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V))"/> + <xsl:variable name="cmplxBifName_" select="BUSCONN/@BUSINTERFACE"/> + <xsl:variable name="cmplxBifSide_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $cmplxInst_)]/BUSINTERFACE[(@NAME = $cmplxBifName_)]/@BIF_X"/> + <xsl:variable name="cmplxBifType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $cmplxInst_)]/BUSINTERFACE[(@NAME = $cmplxBifName_)]/@TYPE"/> + + <xsl:variable name="cmplxshp_hori_idx_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(MODULE[(@INSTANCE = $cmplxInst_)])]/@STACK_HORIZ_INDEX"/> + <xsl:variable name="cmplxshp_vert_idx_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(MODULE[(@INSTANCE = $cmplxInst_)])]/@SHAPE_VERTI_INDEX"/> + + <xsl:variable name="is_abvSbs_" select="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[MODULE[(@INSTANCE = $cmplxInst_)]]/@IS_ABVSBS)"/> + <xsl:variable name="is_blwSbs_" select="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[MODULE[(@INSTANCE = $cmplxInst_)]]/@IS_BLWSBS)"/> + +<!-- + <xsl:message>iStackToEast <xsl:value-of select="$iStackToEast"/></xsl:message> + <xsl:message>iStackToWest <xsl:value-of select="$iStackToWest"/></xsl:message> + <xsl:message><xsl:value-of select="$cmplxInst_"/> : <xsl:value-of select="$is_blwSbs_"/></xsl:message> + <xsl:message><xsl:value-of select="$cmplxInst_"/> : <xsl:value-of select="$is_abvSbs_"/></xsl:message> + <xsl:message><xsl:value-of select="$cmplxInst_"/> : <xsl:value-of select="$is_blwSbs_"/></xsl:message> + <xsl:message><xsl:value-of select="$cmplxInst_"/> : <xsl:value-of select="$is_abvSbs_"/></xsl:message> + <xsl:message>Stack horiz <xsl:value-of select="$cmplxshp_hori_idx_"/></xsl:message> + <xsl:message>Stack verti <xsl:value-of select="$cmplxshp_vert_idx_"/></xsl:message> + <xsl:message>Proc Bif Y <xsl:value-of select="$procBif_Y_"/></xsl:message> +--> + + + <xsl:variable name="busColor_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="$iBusStd"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="space_W_"> + <xsl:call-template name="F_Calc_Space_Width"> + <xsl:with-param name="iStackToEast" select="$iStackToEast"/> + <xsl:with-param name="iStackToWest" select="$iStackToWest"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name ="extSpaceWest_W_" select="ceiling($iStackToWest_W div 2)"/> + <xsl:variable name ="extSpaceEast_W_" select="ceiling($iStackToEast_W div 2)"/> + + <xsl:variable name="cmplxshp_Y_"> + <xsl:call-template name="F_Calc_Stack_Shape_Y"> + <xsl:with-param name="iHorizIdx" select="$cmplxshp_hori_idx_"/> + <xsl:with-param name="iVertiIdx" select="$cmplxshp_vert_idx_"/> + </xsl:call-template> + </xsl:variable> + +<!-- + <xsl:message>Complex shape Y <xsl:value-of select="$cmplxshp_Y_"/></xsl:message> +--> + + <xsl:variable name="stackToEast_"> + <xsl:choose> + <xsl:when test="not($iStackToEast = 'NONE')"><xsl:value-of select="$iStackToEast"/></xsl:when> + <xsl:otherwise>NONE</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="stackToWest_"> + <xsl:choose> + <xsl:when test=" not($iStackToWest = 'NONE')"><xsl:value-of select="$iStackToWest"/></xsl:when> + <xsl:when test="(not($iStackToEast = 'NONE') and not($iStackToEast = '0'))"><xsl:value-of select="($iStackToEast - 1)"/></xsl:when> + <xsl:otherwise>NONE</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + + <xsl:variable name="cmplxStack_H_diff_"> + <xsl:choose> + <xsl:when test=" (($stackToEast_ = 'NONE') or ($stackToWest_ = 'NONE'))">0</xsl:when> + <xsl:when test="not(($stackToEast_ = 'NONE') or ($stackToWest_ = 'NONE'))"> + + <xsl:variable name="stackToWest_AbvSbs_H_"> + <xsl:call-template name="F_Calc_Stack_AbvSbs_Height"> + <xsl:with-param name="iStackIdx" select="$stackToWest_"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="stackToEast_AbvSbs_H_"> + <xsl:call-template name="F_Calc_Stack_AbvSbs_Height"> + <xsl:with-param name="iStackIdx" select="$stackToEast_"/> + </xsl:call-template> + </xsl:variable> + +<!-- + <xsl:message>stack to west H <xsl:value-of select="$stackToWest_AbvSbs_H_"/></xsl:message> + <xsl:message>stack to east H <xsl:value-of select="$stackToEast_AbvSbs_H_"/></xsl:message> +--> + <xsl:choose> + <xsl:when test="(($cmplxshp_hori_idx_ = $stackToEast_) and ($stackToWest_AbvSbs_H_ > $stackToEast_AbvSbs_H_))"> + <xsl:value-of select="($stackToWest_AbvSbs_H_ - $stackToEast_AbvSbs_H_)"/> + </xsl:when> + <xsl:when test="(($cmplxshp_hori_idx_ = $stackToWest_) and ($stackToEast_AbvSbs_H_ > $stackToWest_AbvSbs_H_))"> + <xsl:value-of select="($stackToEast_AbvSbs_H_ - $stackToWest_AbvSbs_H_)"/> + </xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + + </xsl:when> + </xsl:choose> + </xsl:variable> + + + <xsl:variable name="bc_Y_" select="($cmplxshp_Y_ + $cmplxBif_Y_ + ceiling($BIF_H div 2) + $cmplxStack_H_diff_) - ceiling($BLKD_BIFC_H div 2)"/> + + +<!-- + <xsl:message>Sstack H Diff <xsl:value-of select="$cmplxStack_H_diff_"/></xsl:message> + <xsl:message>BC Y <xsl:value-of select="$bc_Y_"/></xsl:message> + <xsl:variable name="bc_x_" select="($laneInSpace_X + ceiling($BLKD_BIFC_W div 2))"/> + <xsl:variable name="bc_x_" select="0"/> +--> + <xsl:variable name="bc_X_"> + <xsl:choose> + <xsl:when test="$cmplxBifSide_ = '0'"> + <xsl:value-of select="($space_W_ + $extSpaceWest_W_ + $extSpaceEast_W_ - (ceiling($BLKD_MOD_W div 2) + $BLKD_BIFC_W))"/> + </xsl:when> + <xsl:when test="$cmplxBifSide_ = '1'"> + <xsl:value-of select="ceiling($BLKD_MOD_W div 2)"/> + </xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <use x="{$bc_X_}" y="{$bc_Y_}" xlink:href="#{$iBusStd}_busconn_{$cmplxBifType_}"/> + + <xsl:variable name="vert_line_x_" select="($iLaneInSpace_X + ceiling($BLKD_BIFC_W div 2))"/> + <xsl:variable name="vert_line_y1_" select="($cmplxshp_Y_ + $cmplxBif_Y_ + ceiling($BLKD_BIF_H div 2) + $cmplxStack_H_diff_)"/> + <xsl:variable name="vert_line_y2_" select="($iSpaceSharedBus_Y + ($sbs_idx_ * $BLKD_SBS_LANE_H) + ceiling($BLKD_BIFC_W div 2))"/> + + <xsl:variable name="v_bus_ul_y_"> + <xsl:choose> + <xsl:when test="$vert_line_y1_ > $vert_line_y2_"> + <xsl:value-of select="$vert_line_y2_"/> + </xsl:when> + <xsl:when test="$vert_line_y2_ > $vert_line_y1_"> + <xsl:value-of select="$vert_line_y1_"/> + </xsl:when> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="v_bus_ul_x_"> + <xsl:choose> + <xsl:when test="@ORIENTED='WEST'"> + <xsl:value-of select="($vert_line_x_ + $BLKD_MOD_BIF_GAP_H)"/> + </xsl:when> + <xsl:when test="@ORIENTED='EAST'"> + <xsl:value-of select="($vert_line_x_ - $BLKD_MOD_BIF_GAP_H)"/> + </xsl:when> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="v_bus_width_" select="$BLKD_P2P_BUS_W"/> + <xsl:variable name="v_bus_height_"> + <xsl:choose> + <xsl:when test="$vert_line_y1_ > $vert_line_y2_"> + <xsl:value-of select="($vert_line_y1_ - $vert_line_y2_) - $BLKD_P2P_BUS_W + 8"/> + </xsl:when> + <xsl:when test="$vert_line_y2_ > $vert_line_y1_"> + <xsl:value-of select="($vert_line_y2_ - $vert_line_y1_) - $BLKD_P2P_BUS_W + 8"/> + </xsl:when> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="h_bus_ul_x_"> + <xsl:choose> + <xsl:when test="@ORIENTED='WEST'"> + <xsl:value-of select="($bc_X_ + $BLKD_BIFC_W - ceiling(($BLKD_BIFC_W - $BLKD_BIFC_Wi) div 2))"/> + </xsl:when> + <xsl:when test="@ORIENTED='EAST'"> + <xsl:value-of select="$v_bus_ul_x_"/> + </xsl:when> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="h_bus_ul_y_"> + <xsl:choose> + + <xsl:when test="($is_blwSbs_ = 'TRUE') and ($vert_line_y1_ > $vert_line_y2_)"> + <xsl:value-of select="$vert_line_y1_ - ceiling($BLKD_P2P_BUS_W div 2)"/> + </xsl:when> + <xsl:when test="($is_blwSbs_ = 'TRUE') and ($vert_line_y2_ > $vert_line_y1_)"> + <xsl:value-of select="$vert_line_y2_ - ceiling($BLKD_P2P_BUS_W div 2)"/> + </xsl:when> + + <xsl:when test="($is_abvSbs_ = 'TRUE') and ($vert_line_y1_ > $vert_line_y2_)"> + <xsl:value-of select="$vert_line_y2_ - ceiling($BLKD_P2P_BUS_W div 2)"/> + </xsl:when> + <xsl:when test="($is_abvSbs_ = 'TRUE') and ($vert_line_y2_ > $vert_line_y1_)"> + <xsl:value-of select="$vert_line_y1_ - ceiling($BLKD_P2P_BUS_W div 2)"/> + </xsl:when> + + </xsl:choose> + </xsl:variable> + + + <xsl:variable name="h_bus_height_" select="$BLKD_P2P_BUS_W"/> + <xsl:variable name="h_bus_width_"> + <xsl:choose> + <xsl:when test="@ORIENTED='WEST'"> + <xsl:value-of select="$v_bus_ul_x_ - $h_bus_ul_x_ + $BLKD_P2P_BUS_W"/> + </xsl:when> + <xsl:when test="@ORIENTED='EAST'"> + <xsl:value-of select="($bc_X_ - $v_bus_ul_x_) + ceiling(($BLKD_BIFC_W - $BLKD_BIFC_Wi) div 2) + 1"/> + </xsl:when> + </xsl:choose> + </xsl:variable> + + + <rect x="{$v_bus_ul_x_}" + y="{$v_bus_ul_y_ - 2}" + width= "{$v_bus_width_}" + height="{$v_bus_height_}" + style="stroke:none; fill:{$busColor_}"/> + + <rect x="{$h_bus_ul_x_}" + y="{$h_bus_ul_y_}" + width= "{$h_bus_width_}" + height="{$h_bus_height_}" + style="stroke:none; fill:{$busColor_}"/> + +</xsl:template> + +<!-- + =========================================================== + Handle connections from processors to Memory UNITs + =========================================================== +--> + + +<xsl:template name="BCLaneSpace_ProcBifToMemoryUnit"> + + <xsl:param name="iBusStd" select="'NONE'"/> + <xsl:param name="iBusName" select="'NONE'"/> + <xsl:param name="iBifType" select="'NONE'"/> + <xsl:param name="iStackToEast" select="'NONE'"/> + <xsl:param name="iStackToWest" select="'NONE'"/> + <xsl:param name="iStackToEast_W" select="0"/> + <xsl:param name="iStackToWest_W" select="0"/> + <xsl:param name="iLaneInSpace_X" select="0"/> + + <xsl:variable name="bcInSpace_X_" select="$iLaneInSpace_X"/> + <xsl:variable name="procInstance_" select="BUSCONN[@IS_PROCCONN]/@INSTANCE"/> + <xsl:variable name="mem_procshp_hori_idx_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $procInstance_)]/@STACK_HORIZ_INDEX"/> + <xsl:variable name="mem_procshp_vert_idx_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $procInstance_)]/@SHAPE_VERTI_INDEX"/> + + <xsl:variable name="mem_procshp_Y_"> + <xsl:call-template name="F_Calc_Stack_Shape_Y"> + <xsl:with-param name="iHorizIdx" select="$mem_procshp_hori_idx_"/> + <xsl:with-param name="iVertiIdx" select="$mem_procshp_vert_idx_"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="busColor_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="$iBusStd"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="space_W_"> + <xsl:call-template name="F_Calc_Space_Width"> + <xsl:with-param name="iStackToEast" select="$iStackToEast"/> + <xsl:with-param name="iStackToWest" select="$iStackToWest"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name ="extSpaceWest_W_" select="ceiling($iStackToWest_W div 2)"/> + <xsl:variable name ="extSpaceEast_W_" select="ceiling($iStackToEast_W div 2)"/> + + <xsl:variable name="cmplxStack_H_diff_"> + <xsl:choose> + <xsl:when test=" (($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))">0</xsl:when> + <xsl:when test="not(($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))"> + + <xsl:variable name="stackToWest_AbvSbs_H_"> + <xsl:call-template name="F_Calc_Stack_AbvSbs_Height"> + <xsl:with-param name="iStackIdx" select="$iStackToWest"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="stackToEast_AbvSbs_H_"> + <xsl:call-template name="F_Calc_Stack_AbvSbs_Height"> + <xsl:with-param name="iStackIdx" select="$iStackToEast"/> + </xsl:call-template> + </xsl:variable> + +<!-- + <xsl:message>stack to west H <xsl:value-of select="$stackToWest_AbvSbs_H_"/></xsl:message> + <xsl:message>stack to east H <xsl:value-of select="$stackToEast_AbvSbs_H_"/></xsl:message> +--> + <xsl:choose> + <xsl:when test="(($mem_procshp_hori_idx_ = $iStackToEast) and ($stackToWest_AbvSbs_H_ > $stackToEast_AbvSbs_H_))"> + <xsl:value-of select="($stackToWest_AbvSbs_H_ - $stackToEast_AbvSbs_H_)"/> + </xsl:when> + <xsl:when test="(($mem_procshp_hori_idx_ = $iStackToWest) and ($stackToEast_AbvSbs_H_ > $stackToWest_AbvSbs_H_))"> + <xsl:value-of select="($stackToEast_AbvSbs_H_ - $stackToWest_AbvSbs_H_)"/> + </xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + + </xsl:when> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="mem_procStack_H_diff_"> + <xsl:choose> + <xsl:when test=" (($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))">0</xsl:when> + <xsl:when test="not(($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))"> + + <xsl:variable name="stackToWest_AbvSbs_H_"> + <xsl:call-template name="F_Calc_Stack_AbvSbs_Height"> + <xsl:with-param name="iStackIdx" select="$iStackToWest"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="stackToEast_AbvSbs_H_"> + <xsl:call-template name="F_Calc_Stack_AbvSbs_Height"> + <xsl:with-param name="iStackIdx" select="$iStackToEast"/> + </xsl:call-template> + </xsl:variable> + +<!-- + <xsl:message>stack to west H <xsl:value-of select="$stackToWest_AbvSbs_H_"/></xsl:message> + <xsl:message>stack to east H <xsl:value-of select="$stackToEast_AbvSbs_H_"/></xsl:message> +--> + <xsl:choose> + <xsl:when test="(($mem_procshp_hori_idx_ = $iStackToEast) and ($stackToWest_AbvSbs_H_ > $stackToEast_AbvSbs_H_))"> + <xsl:value-of select="($stackToWest_AbvSbs_H_ - $stackToEast_AbvSbs_H_)"/> + </xsl:when> + <xsl:when test="(($mem_procshp_hori_idx_ = $iStackToWest) and ($stackToEast_AbvSbs_H_ > $stackToWest_AbvSbs_H_))"> + <xsl:value-of select="($stackToEast_AbvSbs_H_ - $stackToWest_AbvSbs_H_)"/> + </xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + + </xsl:when> + </xsl:choose> + </xsl:variable> + + <!-- Store the conns in a variable --> + <xsl:variable name="memConn_heights_"> + + <xsl:for-each select="BUSCONN"> + + <xsl:variable name="bifName_" select="@BUSINTERFACE"/> + + + <xsl:choose> + <xsl:when test="@IS_PROCCONN and @BIF_Y"> + + <xsl:variable name="procBif_Y_" select="((($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * @BIF_Y) + ($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V))"/> + <xsl:variable name="procBifType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $procInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@TYPE"/> + <xsl:variable name="procBusName_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $procInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BUSNAME"/> + <xsl:variable name="procBifSide_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $procInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BIF_X"/> + <xsl:variable name="bcProc_Y_" select="($mem_procshp_Y_ + $procBif_Y_ + ceiling($BLKD_BIF_H div 2) - ceiling($BLKD_BIFC_H div 2) + $mem_procStack_H_diff_)"/> + <xsl:variable name="bcProc_X_"> + <xsl:choose> + <xsl:when test="$procBifSide_ = '0'"> + <xsl:value-of select="($space_W_ + $extSpaceWest_W_ + $extSpaceEast_W_ - (ceiling($BLKD_MOD_W div 2) + $BLKD_BIFC_W))"/> + </xsl:when> + <xsl:when test="$procBifSide_ = '1'"> + <xsl:value-of select="ceiling($BLKD_MOD_W div 2)"/> + </xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <MEMCONN X="{$bcProc_X_}" Y="{$bcProc_Y_}" BUSNAME="{$procBusName_}" BUSSTD="{$iBusStd}" TYPE="{$procBifType_}" BIFSIDE="{$procBifSide_}"/> + + </xsl:when> + + <xsl:otherwise> + + <xsl:variable name="memcInstance_" select="@INSTANCE"/> + <xsl:variable name="memcshp_vert_idx_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[MODULE[(@INSTANCE = $memcInstance_)]]/@SHAPE_VERTI_INDEX"/> + <xsl:variable name="memcBifSide_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $memcInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BIF_X"/> + <xsl:variable name="memcBif_Y_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $memcInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BIF_Y"/> + + <xsl:variable name="memshp_Y_"> + <xsl:call-template name="F_Calc_Stack_Shape_Y"> + <xsl:with-param name="iHorizIdx" select="$mem_procshp_hori_idx_"/> + <xsl:with-param name="iVertiIdx" select="$memcshp_vert_idx_"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="memcMOD_W_" select="(($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[MODULE[(@INSTANCE = $memcInstance_)]]/@MODS_W) * $BLKD_MOD_W)"/> + + <xsl:variable name="procBif_Y_" select="((($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * @BIF_Y) + ($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V))"/> + + <xsl:variable name="memcConn_Y_"> + <xsl:choose> + <xsl:when test="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[MODULE[(@INSTANCE = $memcInstance_)]]/@MODS_H = 1)"> + <xsl:value-of select="($memshp_Y_ + ($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V) + ($memcBif_Y_ * ($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V)) + ceiling($BIF_H div 2) - ceiling($BLKD_BIFC_H div 2) + $cmplxStack_H_diff_)"/> + </xsl:when> + <xsl:otherwise> + <xsl:value-of select="($memshp_Y_ + $BLKD_MOD_H + $BLKD_MOD_LANE_H + ($memcBif_Y_ * ($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V)) + ceiling($BLKD_BIF_H div 2) - ceiling($BLKD_BIFC_H div 2) + $cmplxStack_H_diff_)"/> + </xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="memcConn_X_"> + <xsl:choose> + <xsl:when test="$memcBifSide_ = '0'"> + <xsl:value-of select="($space_W_ + $extSpaceWest_W_ + $extSpaceEast_W_ - (ceiling($memcMOD_W_ div 2) + $BLKD_BIFC_W))"/> + </xsl:when> + <xsl:when test="$memcBifSide_ = '1'"> + <xsl:value-of select="ceiling($memcMOD_W_ div 2)"/> + </xsl:when> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="memcBifType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $memcInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@TYPE"/> + <xsl:variable name="memcBusName_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $memcInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BUSNAME"/> + + <MEMCONN X="{$memcConn_X_}" Y="{$memcConn_Y_}" BUSNAME="{$memcBusName_}" BUSSTD="{$iBusStd}" TYPE="{$memcBifType_}" BIFSIDE="{$memcBifSide_}"/> + + </xsl:otherwise> + </xsl:choose> + </xsl:for-each> + </xsl:variable> + + + <!-- Draw the busconnection and horizontal lines.--> + <xsl:for-each select="exsl:node-set($memConn_heights_)/MEMCONN"> + + <xsl:variable name="bus_x_" select="($bcInSpace_X_ + ceiling($BLKD_BIFC_W div 2))"/> + <xsl:variable name="bus_y_" select="@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_P2P_BUS_W div 2)"/> + + <xsl:variable name="adjusted_X_"> + <xsl:choose> + <xsl:when test="((@X < ($bus_x_ + $BLKD_BUS_ARROW_W)) and (@BIFSIDE ='0'))"> + <xsl:value-of select="(@X + $BLKD_P2P_BUS_W)"/> + </xsl:when> + <xsl:otherwise> + <xsl:value-of select="@X"/> + </xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="h_bus_ul_x_dx_"> + <xsl:choose> + <xsl:when test="((@X < ($bus_x_ + $BLKD_BUS_ARROW_W)) and (@BIFSIDE='0'))"> + <xsl:value-of select="$BLKD_P2P_BUS_W"/> + </xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="h_bus_ul_x_"> + <xsl:choose> + <xsl:when test="@BIFSIDE='0'"> + <xsl:value-of select="($bus_x_ - $h_bus_ul_x_dx_)"/> + </xsl:when> + <xsl:when test="@BIFSIDE='1'"> + <xsl:value-of select="(@X + $BLKD_BIFC_W + $BLKD_BUS_ARROW_W)"/> + </xsl:when> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="h_bus_ul_y_" select="$bus_y_"/> + + <xsl:variable name="h_bus_height_" select="$BLKD_P2P_BUS_W"/> + <xsl:variable name="h_bus_width_"> + <xsl:choose> + <xsl:when test="@BIFSIDE='0'"> + <xsl:value-of select="($adjusted_X_ - $bus_x_ - $BLKD_BUS_ARROW_W)"/> + </xsl:when> + <xsl:when test="@BIFSIDE='1'"> + <xsl:value-of select="$bus_x_ - $h_bus_ul_x_"/> + </xsl:when> + </xsl:choose> + </xsl:variable> + + <!-- Place the bus connection --> + <use x="{@X}" y="{@Y}" xlink:href="#{@BUSSTD}_busconn_{@TYPE}"/> + + <!-- Draw the arrow --> + <xsl:choose> + <xsl:when test="@BIFSIDE='0'"> + <use x="{@X - $BLKD_BUS_ARROW_W}" y="{@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_BUS_ARROW_H div 2)}" xlink:href="#{@BUSSTD}_BusArrowEast"/> + </xsl:when> + <xsl:when test="@BIFSIDE='1'"> + <use x="{(@X + $BLKD_BIFC_W)}" y="{@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_BUS_ARROW_H div 2)}" xlink:href="#{@BUSSTD}_BusArrowWest"/> + </xsl:when> + </xsl:choose> + + + <!-- Draw the horizontal part of the bus --> + <rect x="{$h_bus_ul_x_}" + y="{$h_bus_ul_y_}" + width= "{$h_bus_width_}" + height="{$h_bus_height_}" + style="stroke:none; fill:{$busColor_}"/> + </xsl:for-each> + + <xsl:variable name="busTop_" select="math:min(exsl:node-set($memConn_heights_)/MEMCONN/@Y)"/> + <xsl:variable name="busBot_" select="math:max(exsl:node-set($memConn_heights_)/MEMCONN/@Y)"/> + <xsl:variable name="busName_" select="exsl:node-set($memConn_heights_)/MEMCONN/@BUSNAME"/> + <xsl:variable name="busSide_" select="exsl:node-set($memConn_heights_)/MEMCONN/@BIFSIDE"/> + <xsl:variable name="leftmost_x_" select="math:min(exsl:node-set($memConn_heights_)/MEMCONN/@X)"/> + +<!-- Hack to fix CR473515 --> + <xsl:variable name="v_bus_x_dx_"> + <xsl:choose> + <xsl:when test="(($busSide_ = '0') and (($leftmost_x_ - ($bcInSpace_X_ + $BLKD_P2P_BUS_W)) <= $BLKD_P2P_BUS_W))">-4</xsl:when> + <xsl:otherwise><xsl:value-of select="$BLKD_P2P_BUS_W"/></xsl:otherwise> + </xsl:choose> + </xsl:variable> + + + <xsl:variable name="v_bus_y_" select="$busTop_ + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_P2P_BUS_W div 2)"/> + <xsl:variable name="v_bus_x_"> + <xsl:choose> + <xsl:when test="$busSide_ ='0'"> + <xsl:value-of select="($bcInSpace_X_ + $v_bus_x_dx_)"/> + </xsl:when> + <xsl:when test="$busSide_ ='1'"> + <xsl:value-of select="($bcInSpace_X_ + $BLKD_P2P_BUS_W)"/> + </xsl:when> + </xsl:choose> + </xsl:variable> + + <!-- Draw the vertical part of the bus --> + <rect x="{$v_bus_x_}" + y="{$v_bus_y_}" + width= "{$BLKD_P2P_BUS_W}" + height="{($busBot_ - $busTop_) + $BLKD_P2P_BUS_W}" + style="stroke:none; fill:{$busColor_}"/> + +<!-- Hack to fix CR473515 --> + <xsl:if test="($busSide_ ='0')"> + <rect x="{$v_bus_x_}" + y="{$v_bus_y_ + ($busBot_ - $busTop_)}" + width= "{$BLKD_P2P_BUS_W * 2}" + height="{$BLKD_P2P_BUS_W}" + style="stroke:none; fill:{$busColor_}"/> + </xsl:if> + +<!-- + <xsl:message>v_bus_x <xsl:value-of select="$v_bus_x_"/></xsl:message> +--> + + <!-- Place the bus label.--> +<!-- + <text class="p2pbuslabel" + x="{$bcInSpace_X_ + $BLKD_BUS_ARROW_W + ceiling($BLKD_BUS_ARROW_W div 2) + ceiling($BLKD_BUS_ARROW_W div 4) + 6}" + y="{$busTop_ + ($BLKD_BUS_ARROW_H * 3)}"> + <xsl:value-of select="$busName_"/> + </text> +--> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="($bcInSpace_X_ + $BLKD_BUS_ARROW_W + ceiling($BLKD_BUS_ARROW_W div 2) + ceiling($BLKD_BUS_ARROW_W div 4) + 6)"/> + <xsl:with-param name="iY" select="($busTop_ + ($BLKD_BUS_ARROW_H * 3))"/> + <xsl:with-param name="iText" select="$busName_"/> + <xsl:with-param name="iClass" select="'p2pbus_label'"/> + </xsl:call-template> + +</xsl:template> + + +<!-- + =========================================================== + Handle generic Point to Point connections + =========================================================== +--> + +<xsl:template name="BCLaneSpace_PointToPoint"> + + <xsl:param name="iBusStd" select="'NONE'"/> + <xsl:param name="iBifType" select="'NONE'"/> + <xsl:param name="iBusName" select="'NONE'"/> + <xsl:param name="iStackToEast" select="'NONE'"/> + <xsl:param name="iStackToWest" select="'NONE'"/> + <xsl:param name="iStackToEast_W" select="0"/> + <xsl:param name="iStackToWest_W" select="0"/> + <xsl:param name="iLaneInSpace_X" select="0"/> + + <xsl:variable name="busColor_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="$iBusStd"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="busColor_lt_"> + <xsl:call-template name="F_BusStd2RGB_LT"> + <xsl:with-param name="iBusStd" select="$iBusStd"/> + </xsl:call-template> + </xsl:variable> + + + <xsl:variable name="space_W_"> + <xsl:call-template name="F_Calc_Space_Width"> + <xsl:with-param name="iStackToEast" select="$iStackToEast"/> + <xsl:with-param name="iStackToWest" select="$iStackToWest"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name ="extSpaceWest_W_" select="ceiling($iStackToWest_W div 2)"/> + <xsl:variable name ="extSpaceEast_W_" select="ceiling($iStackToEast_W div 2)"/> + + <xsl:variable name="bcInSpace_X_" select="($iLaneInSpace_X + ceiling($BLKD_BIFC_W div 2) - ceiling($BLKD_BUS_ARROW_W div 2))"/> + <xsl:variable name="p2pInstance_" select="BUSCONN[(@BIF_Y)]/@INSTANCE"/> + + <xsl:variable name="p2pshp_hori_idx_"> + <xsl:choose> + <xsl:when test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $p2pInstance_)]"> + <xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $p2pInstance_)]/@STACK_HORIZ_INDEX"/> + </xsl:when> + <xsl:otherwise> + <xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(MODULE[(@INSTANCE = $p2pInstance_)])]/@STACK_HORIZ_INDEX"/> + </xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="p2pshp_vert_idx_"> + <xsl:choose> + <xsl:when test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $p2pInstance_)]"> + <xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $p2pInstance_)]/@SHAPE_VERTI_INDEX"/> + </xsl:when> + <xsl:otherwise> + <xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(MODULE[(@INSTANCE = $p2pInstance_)])]/@SHAPE_VERTI_INDEX"/> + </xsl:otherwise> + </xsl:choose> + </xsl:variable> + +<!-- + <xsl:variable name="p2pshp_hori_idx_" select="/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $procInstance_)]/@STACK_HORIZ_INDEX"/> + <xsl:variable name="p2pshp_vert_idx_" select="/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $procInstance_)]/@SHAPE_VERTI_INDEX"/> +--> + + <xsl:variable name="p2pshp_Y_"> + <xsl:call-template name="F_Calc_Stack_Shape_Y"> + <xsl:with-param name="iHorizIdx" select="$p2pshp_hori_idx_"/> + <xsl:with-param name="iVertiIdx" select="$p2pshp_vert_idx_"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="cmplxStack_H_diff_"> + <xsl:choose> + <xsl:when test=" (($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))">0</xsl:when> + <xsl:when test="not(($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))"> + + <xsl:variable name="stackToWest_AbvSbs_H_"> + <xsl:call-template name="F_Calc_Stack_AbvSbs_Height"> + <xsl:with-param name="iStackIdx" select="$iStackToWest"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="stackToEast_AbvSbs_H_"> + <xsl:call-template name="F_Calc_Stack_AbvSbs_Height"> + <xsl:with-param name="iStackIdx" select="$iStackToEast"/> + </xsl:call-template> + </xsl:variable> + +<!-- + <xsl:message>stack to west H <xsl:value-of select="$stackToWest_AbvSbs_H_"/></xsl:message> + <xsl:message>stack to east H <xsl:value-of select="$stackToEast_AbvSbs_H_"/></xsl:message> +--> + <xsl:choose> + <xsl:when test="(($p2pshp_hori_idx_ = $iStackToEast) and ($stackToWest_AbvSbs_H_ > $stackToEast_AbvSbs_H_))"> + <xsl:value-of select="($stackToWest_AbvSbs_H_ - $stackToEast_AbvSbs_H_)"/> + </xsl:when> + <xsl:when test="(($p2pshp_hori_idx_ = $iStackToWest) and ($stackToEast_AbvSbs_H_ > $stackToWest_AbvSbs_H_))"> + <xsl:value-of select="($stackToEast_AbvSbs_H_ - $stackToWest_AbvSbs_H_)"/> + </xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + + </xsl:when> + </xsl:choose> + </xsl:variable> + + + <xsl:variable name="procStack_H_diff_"> + <xsl:choose> + <xsl:when test=" (($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))">0</xsl:when> + <xsl:when test="not(($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))"> + + <xsl:variable name="stackToWest_AbvSbs_H_"> + <xsl:call-template name="F_Calc_Stack_AbvSbs_Height"> + <xsl:with-param name="iStackIdx" select="$iStackToWest"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="stackToEast_AbvSbs_H_"> + <xsl:call-template name="F_Calc_Stack_AbvSbs_Height"> + <xsl:with-param name="iStackIdx" select="$iStackToEast"/> + </xsl:call-template> + </xsl:variable> + +<!-- + <xsl:message>stack to west H <xsl:value-of select="$stackToWest_AbvSbs_H_"/></xsl:message> + <xsl:message>stack to east H <xsl:value-of select="$stackToEast_AbvSbs_H_"/></xsl:message> +--> + <xsl:choose> + <xsl:when test="(($p2pshp_hori_idx_ = $iStackToEast) and ($stackToWest_AbvSbs_H_ > $stackToEast_AbvSbs_H_))"> + <xsl:value-of select="($stackToWest_AbvSbs_H_ - $stackToEast_AbvSbs_H_)"/> + </xsl:when> + <xsl:when test="(($p2pshp_hori_idx_ = $iStackToWest) and ($stackToEast_AbvSbs_H_ > $stackToWest_AbvSbs_H_))"> + <xsl:value-of select="($stackToEast_AbvSbs_H_ - $stackToWest_AbvSbs_H_)"/> + </xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + + </xsl:when> + </xsl:choose> + </xsl:variable> + + + + <!-- Store the conns in a variable --> + <xsl:variable name="p2pConn_heights_"> + + <xsl:for-each select="BUSCONN"> + + <xsl:variable name="bifName_" select="@BUSINTERFACE"/> + + <xsl:choose> + <xsl:when test="@IS_PROCCONN and @BIF_Y"> + +<!-- + <xsl:message>Proc <xsl:value-of select="$procInstance_"/></xsl:message> +--> + <xsl:variable name="procBif_Y_" select="((($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * @BIF_Y) + ($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V))"/> + <xsl:variable name="procBifType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $p2pInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@TYPE"/> + <xsl:variable name="procBusName_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $p2pInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BUSNAME"/> + <xsl:variable name="procBifSide_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $p2pInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BIF_X"/> + + <xsl:variable name="bcProc_Y_" select="($p2pshp_Y_ + $procBif_Y_ + ceiling($BIF_H div 2) - ceiling($BLKD_BIFC_H div 2) + $procStack_H_diff_)"/> + <xsl:variable name="bcProc_X_"> + <xsl:choose> + <xsl:when test="$procBifSide_ = '0'"> + <xsl:value-of select="($space_W_ + $extSpaceWest_W_ + $extSpaceEast_W_ - (ceiling($BLKD_MOD_W div 2) + $BLKD_BIFC_W))"/> + </xsl:when> + <xsl:when test="$procBifSide_ = '1'"> + <xsl:value-of select="ceiling($BLKD_MOD_W div 2)"/> + </xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <P2PCONN X="{$bcProc_X_}" Y="{$bcProc_Y_}" BUSNAME= "{$procBusName_}" BUSSTD="{$iBusStd}" TYPE="{$procBifType_}" BIFSIDE="{$procBifSide_}"/> + +<!-- + <xsl:message>bcProc_X_ <xsl:value-of select="$bcProc_X_"/></xsl:message> + <xsl:message>bcProc_Y_ <xsl:value-of select="$bcProc_Y_"/></xsl:message> + <P2PCONN X="{$bcInSpace_X_}" Y="{$bcProc_Y_}" BUSSTD="{$busStd}" TYPE="{$procBifType_}" BIFSIDE="{$procBifSide_}" STACK_ID=""/> +--> + </xsl:when> + + <xsl:otherwise> + + <xsl:variable name="modInstance_" select="@INSTANCE"/> + <xsl:variable name="modshp_vert_idx_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[MODULE[(@INSTANCE = $modInstance_)]]/@SHAPE_VERTI_INDEX"/> + <xsl:variable name="modBifSide_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $modInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BIF_X"/> + <xsl:variable name="modBif_Y_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $modInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BIF_Y"/> + <xsl:variable name="modBc_Y_" select="((($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * $modBif_Y_) + ($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V))"/> + +<!-- + <xsl:message>Memory Instance <xsl:value-of select="$procInstance_"/></xsl:message> +--> + + <xsl:variable name="modshp_Y_"> + <xsl:call-template name="F_Calc_Stack_Shape_Y"> + <xsl:with-param name="iHorizIdx" select="$p2pshp_hori_idx_"/> + <xsl:with-param name="iVertiIdx" select="$modshp_vert_idx_"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="modBifType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $modInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@TYPE"/> + <xsl:variable name="modBusName_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $modInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BUSNAME"/> + <xsl:variable name="bcMod_Y_" select="($modshp_Y_ + $modBc_Y_ + ceiling($BLKD_BIF_H div 2) - ceiling($BLKD_BIFC_H div 2) + $cmplxStack_H_diff_)"/> + <xsl:variable name="bcMod_X_"> + <xsl:choose> + <xsl:when test="$modBifSide_ = '0'"> + <xsl:value-of select="($space_W_ + $extSpaceWest_W_ + $extSpaceEast_W_ - (ceiling($BLKD_MOD_W div 2) + $BLKD_BIFC_W))"/> + </xsl:when> + <xsl:when test="$modBifSide_ = '1'"> + <xsl:value-of select="ceiling($BLKD_MOD_W div 2)"/> + </xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + </xsl:variable> + +<!-- + <xsl:message>Bc Bif Y <xsl:value-of select="$modBif_Y_"/></xsl:message> + <xsl:message>Bc Mod Y <xsl:value-of select="$modBc_Y_"/></xsl:message> + <xsl:message>Bc Mod X <xsl:value-of select="$bcMod_X_"/></xsl:message> + <P2PCONN X="{$bcInSpace_X_}" Y="{$bcMod_Y_}" BUSSTD="{$busStd}" TYPE="{$modBifType_}" BIFSIDE="{$modBifSide_}"/> +--> + <P2PCONN X="{$bcMod_X_}" Y="{$bcMod_Y_}" BUSNAME="{$modBusName_}" BUSSTD="{$iBusStd}" TYPE="{$modBifType_}" BIFSIDE="{$modBifSide_}"/> + + </xsl:otherwise> + + </xsl:choose> + </xsl:for-each> + </xsl:variable> + + + <xsl:variable name="busTop_" select="math:min(exsl:node-set($p2pConn_heights_)/P2PCONN/@Y)"/> + <xsl:variable name="busBot_" select="math:max(exsl:node-set($p2pConn_heights_)/P2PCONN/@Y)"/> + <xsl:variable name="v_bus_y_" select="$busTop_ + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_P2P_BUS_W div 2)"/> + <xsl:variable name="busName_" select="exsl:node-set($p2pConn_heights_)/P2PCONN/@BUSNAME"/> + <xsl:variable name="busStd_" select="exsl:node-set($p2pConn_heights_)/P2PCONN/@BUSSTD"/> +<!-- +--> + <!-- Draw the vertical part of the bus --> + <xsl:if test="$busStd_ = 'PLBV46_P2P'"> + <rect x="{$bcInSpace_X_ + $BLKD_P2P_BUS_W}" + y="{$v_bus_y_}" + width= "{$BLKD_P2P_BUS_W}" + height="{($busBot_ - $busTop_) + $BLKD_P2P_BUS_W}" + style="stroke:{$COL_WHITE};stroke-width:1.5;fill:{$busColor_}"/> + </xsl:if> + + <xsl:if test="not($busStd_ = 'PLBV46_P2P')"> + <rect x="{$bcInSpace_X_ + $BLKD_P2P_BUS_W}" + y="{$v_bus_y_}" + width= "{$BLKD_P2P_BUS_W}" + height="{($busBot_ - $busTop_) + $BLKD_P2P_BUS_W}" + style="stroke:none;fill:{$busColor_}"/> + </xsl:if> + +<!-- --> + +<!-- + style="stroke:{$busColor_lt_};stroke-width:1;stroke-opacity:0.9;fill-opacity:2.0;fill:{$busColor_}"/> +--> + + <!-- Place the bus label.--> +<!-- + <text class="p2pbuslabel" + x="{$bcInSpace_X_ + $BLKD_BUS_ARROW_W + ceiling($BLKD_BUS_ARROW_W div 2) + ceiling($BLKD_BUS_ARROW_W div 4) + 6}" + y="{$busTop_ + ($BLKD_BUS_ARROW_H * 3)}"> + <xsl:value-of select="$busName_"/> + </text> +--> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="($bcInSpace_X_ + $BLKD_BUS_ARROW_W + ceiling($BLKD_BUS_ARROW_W div 2) + ceiling($BLKD_BUS_ARROW_W div 4) + 6)"/> + <xsl:with-param name="iY" select="($busTop_ + ($BLKD_BUS_ARROW_H * 3))"/> + <xsl:with-param name="iText" select="$busName_"/> + <xsl:with-param name="iClass" select="'p2pbus_label'"/> + </xsl:call-template> + + <!-- Draw the busconnection and horizontal lines.--> + <xsl:for-each select="exsl:node-set($p2pConn_heights_)/P2PCONN"> + + <xsl:variable name="bus_x_" select="($bcInSpace_X_ + ceiling($BLKD_BIFC_W div 2))"/> + <xsl:variable name="bus_y_" select="@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_P2P_BUS_W div 2)"/> + + <xsl:variable name="h_bus_ul_x_"> + <xsl:choose> + <xsl:when test="@BIFSIDE='0'"> + <xsl:value-of select="$bus_x_"/> + </xsl:when> + <xsl:when test="@BIFSIDE='1'"> + <xsl:value-of select="(@X + $BLKD_BIFC_W + $BLKD_BUS_ARROW_W) - 1"/> + </xsl:when> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="h_bus_ul_y_" select="$bus_y_"/> + + <xsl:variable name="h_bus_height_" select="$BLKD_P2P_BUS_W"/> + <xsl:variable name="h_bus_width_"> +<!-- + <xsl:message>BIFSIDE <xsl:value-of select="@BIFSIDE"/></xsl:message> + <xsl:message>BUSSTD <xsl:value-of select="@BUSSTD"/></xsl:message> + <xsl:message>TYPE <xsl:value-of select="@TYPE"/></xsl:message> +--> + <xsl:choose> + <xsl:when test="@BIFSIDE='0'"> + <xsl:value-of select="(@X - $bus_x_ - $BLKD_BUS_ARROW_W)"/> + </xsl:when> + <xsl:when test="@BIFSIDE='1'"> + <xsl:value-of select="$bus_x_ - $h_bus_ul_x_ + 1"/> + </xsl:when> + + </xsl:choose> + </xsl:variable> + + <!-- Draw Bus connection--> + <use x="{@X}" y="{@Y}" xlink:href="#{@BUSSTD}_busconn_{@TYPE}"/> + + <!-- Draw the arrow --> + <xsl:choose> + <xsl:when test="((@BIFSIDE='0') and not((@BUSSTD = 'FSL') and ((@TYPE = 'INITIATOR') or (@TYPE = 'MASTER'))))"> + <use x="{@X - $BLKD_BUS_ARROW_W}" y="{@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_BUS_ARROW_H div 2)}" xlink:href="#{@BUSSTD}_BusArrowEast"/> + </xsl:when> + <xsl:when test="((@BIFSIDE='1') and not((@BUSSTD = 'FSL') and ((@TYPE = 'INITIATOR') or (@TYPE = 'MASTER'))))"> + <use x="{(@X + $BLKD_BIFC_W)}" y="{@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_BUS_ARROW_H div 2)}" xlink:href="#{@BUSSTD}_BusArrowWest"/> + </xsl:when> + + <xsl:when test="((@BIFSIDE='0') and ((@BUSSTD = 'FSL') and ((@TYPE = 'INITIATOR') or (@TYPE = 'MASTER'))))"> + <use x="{@X - $BLKD_BUS_ARROW_W}" y="{@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_BUS_ARROW_H div 2)}" xlink:href="#{@BUSSTD}_BusArrowHInitiator"/> + </xsl:when> + + <xsl:when test="((@BIFSIDE='1') and ((@BUSSTD = 'FSL') and ((@TYPE = 'INITIATOR') or (@TYPE = 'MASTER'))))"> + <use x="{(@X + $BLKD_BIFC_W)}" y="{@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_BUS_ARROW_H div 2)}" xlink:href="#{@BUSSTD}_BusArrowHInitiator"/> + </xsl:when> + + </xsl:choose> + + <!-- Draw the horizontal part of the bus --> + <rect x="{$h_bus_ul_x_}" + y="{$h_bus_ul_y_}" + width= "{$h_bus_width_}" + height="{$h_bus_height_}" + style="stroke:none; fill:{$busColor_}"/> + + </xsl:for-each> + +<!-- + <xsl:variable name="busTop_" select="math:min(exsl:node-set($p2pConn_heights_)/P2PCONN/@Y)"/> + <xsl:variable name="busBot_" select="math:max(exsl:node-set($p2pConn_heights_)/P2PCONN/@Y)"/> + <xsl:variable name="v_bus_y_" select="$busTop_ + ceiling($BLKD_BIFC_H div 2) - ceiling($P2P_BUS_W div 2)"/> + <xsl:variable name="busName_" select="exsl:node-set($p2pConn_heights_)/P2PCONN/@BUSNAME"/> +--> + <!-- Draw the vertical part of the bus --> +<!-- + <rect x="{$bcInSpace_X_ + $P2P_BUS_W}" + y="{$v_bus_y_}" + width= "{$P2P_BUS_W}" + height="{($busBot_ - $busTop_) + $P2P_BUS_W}" + style="stroke:{$COL_WHITE};stroke-width:1;stroke-opacity:0.9;fill-opacity:2.0;fill:{$busColor_}"/> +--> + +<!-- + style="stroke:{$busColor_lt_};stroke-width:1;stroke-opacity:0.9;fill-opacity:2.0;fill:{$busColor_}"/> +--> + <!-- Place the bus label.--> +<!-- + <text class="p2pbuslabel" + x="{$bcInSpace_X_ + $BLKD_BUS_ARROW_W + ceiling($BLKD_BUS_ARROW_W div 2) + ceiling($BLKD_BUS_ARROW_W div 4) + 6}" + y="{$busTop_ + ($BLKD_BUS_ARROW_H * 3)}"> + <xsl:value-of select="$busName_"/> + </text> +--> + + +</xsl:template> + + + +<!-- + =========================================================== + Handle MultiStack Point to Point connections + =========================================================== +--> + +<xsl:template name="BCLaneSpace_MultiStack_PointToPoint"> + + <xsl:param name="iBusStd" select="'NONE'"/> + <xsl:param name="iBusName" select="'NONE'"/> + <xsl:param name="iBifType" select="'NONE'"/> + <xsl:param name="iStackToEast" select="'NONE'"/> + <xsl:param name="iStackToWest" select="'NONE'"/> + <xsl:param name="iStackToEast_W" select="0"/> + <xsl:param name="iStackToWest_W" select="0"/> + <xsl:param name="iLaneInSpace_X" select="0"/> + +<!-- + <xsl:message>Stack To East <xsl:value-of select="$iStackToEast"/></xsl:message> + <xsl:message>Stack to West <xsl:value-of select="$iStackToWest"/></xsl:message> + <xsl:message>Stack to East Width <xsl:value-of select="$iStackToEast_W"/></xsl:message> + <xsl:message>Stack to West Width <xsl:value-of select="$iStackToWest_W"/></xsl:message> + <xsl:message>Lane in space X <xsl:value-of select="$iLaneInSpace_X"/></xsl:message> + <xsl:message>Shared Bus Y <xsl:value-of select="$iSpaceSharedBus_Y"/></xsl:message> +--> + + <xsl:variable name="busColor_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="$iBusStd"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="space_W_"> + <xsl:call-template name="F_Calc_Space_Width"> + <xsl:with-param name="iStackToEast" select="$iStackToEast"/> + <xsl:with-param name="iStackToWest" select="$iStackToWest"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name ="extSpaceWest_W_" select="ceiling($iStackToWest_W div 2)"/> + <xsl:variable name ="extSpaceEast_W_" select="ceiling($iStackToEast_W div 2)"/> + + <!-- Store the connections in a variable --> + <xsl:variable name="bcInSpace_X_" select="($iLaneInSpace_X + ceiling($BLKD_BIFC_W div 2) - ceiling($BLKD_BUS_ARROW_W div 2))"/> + + <xsl:variable name="multiConns_"> + + <xsl:for-each select="BUSCONN"> + + <xsl:variable name="bifName_" select="@BUSINTERFACE"/> + <xsl:variable name="multiInstance_" select="@INSTANCE"/> + <xsl:variable name="mulshp_hori_idx_"> + <xsl:choose> + <xsl:when test="@IS_PROCCONN"> + <xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $multiInstance_)]/@STACK_HORIZ_INDEX"/> + </xsl:when> + <xsl:otherwise> + <xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(MODULE[(@INSTANCE = $multiInstance_)])]/@STACK_HORIZ_INDEX"/> + </xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="mulshp_vert_idx_"> + <xsl:choose> + <xsl:when test="@IS_PROCCONN"> + <xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $multiInstance_)]/@SHAPE_VERTI_INDEX"/> + </xsl:when> + <xsl:otherwise> + <xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(MODULE[(@INSTANCE = $multiInstance_)])]/@SHAPE_VERTI_INDEX"/> + </xsl:otherwise> + </xsl:choose> + </xsl:variable> + +<!-- + <xsl:message>Shape Horiz <xsl:value-of select="$mulshp_hori_idx_"/></xsl:message> + <xsl:message>Shape Verti <xsl:value-of select="$mulshp_vert_idx_"/></xsl:message> +--> + + <xsl:variable name="mulshp_Y_"> + <xsl:call-template name="F_Calc_Stack_Shape_Y"> + <xsl:with-param name="iHorizIdx" select="$mulshp_hori_idx_"/> + <xsl:with-param name="iVertiIdx" select="$mulshp_vert_idx_"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="cmplxStack_H_diff_"> + <xsl:choose> + <xsl:when test=" (($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))">0</xsl:when> + <xsl:when test="not(($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))"> + + <xsl:variable name="stackToWest_AbvSbs_H_"> + <xsl:call-template name="F_Calc_Stack_AbvSbs_Height"> + <xsl:with-param name="iStackIdx" select="$iStackToWest"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="stackToEast_AbvSbs_H_"> + <xsl:call-template name="F_Calc_Stack_AbvSbs_Height"> + <xsl:with-param name="iStackIdx" select="$iStackToEast"/> + </xsl:call-template> + </xsl:variable> + +<!-- + <xsl:message>stack to west H <xsl:value-of select="$stackToWest_AbvSbs_H_"/></xsl:message> + <xsl:message>stack to east H <xsl:value-of select="$stackToEast_AbvSbs_H_"/></xsl:message> +--> + <xsl:choose> + <xsl:when test="(($mulshp_hori_idx_ = $iStackToEast) and ($stackToWest_AbvSbs_H_ > $stackToEast_AbvSbs_H_))"> + <xsl:value-of select="($stackToWest_AbvSbs_H_ - $stackToEast_AbvSbs_H_)"/> + </xsl:when> + <xsl:when test="(($mulshp_hori_idx_ = $iStackToWest) and ($stackToEast_AbvSbs_H_ > $stackToWest_AbvSbs_H_))"> + <xsl:value-of select="($stackToEast_AbvSbs_H_ - $stackToWest_AbvSbs_H_)"/> + </xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + + </xsl:when> + </xsl:choose> + </xsl:variable> + + + <xsl:variable name="procStack_H_diff_"> + <xsl:choose> + <xsl:when test=" (($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))">0</xsl:when> + <xsl:when test="not(($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))"> + + <xsl:variable name="stackToWest_AbvSbs_H_"> + <xsl:call-template name="F_Calc_Stack_AbvSbs_Height"> + <xsl:with-param name="iStackIdx" select="$iStackToWest"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="stackToEast_AbvSbs_H_"> + <xsl:call-template name="F_Calc_Stack_AbvSbs_Height"> + <xsl:with-param name="iStackIdx" select="$iStackToEast"/> + </xsl:call-template> + </xsl:variable> + +<!-- + <xsl:message>stack to west H <xsl:value-of select="$stackToWest_AbvSbs_H_"/></xsl:message> + <xsl:message>stack to east H <xsl:value-of select="$stackToEast_AbvSbs_H_"/></xsl:message> +--> + <xsl:choose> + <xsl:when test="(($mulshp_hori_idx_ = $iStackToEast) and ($stackToWest_AbvSbs_H_ > $stackToEast_AbvSbs_H_))"> + <xsl:value-of select="($stackToWest_AbvSbs_H_ - $stackToEast_AbvSbs_H_)"/> + </xsl:when> + <xsl:when test="(($mulshp_hori_idx_ = $iStackToWest) and ($stackToEast_AbvSbs_H_ > $stackToWest_AbvSbs_H_))"> + <xsl:value-of select="($stackToEast_AbvSbs_H_ - $stackToWest_AbvSbs_H_)"/> + </xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + + </xsl:when> + </xsl:choose> + </xsl:variable> + + <xsl:choose> + + <xsl:when test="@IS_PROCCONN and @BIF_Y"> + + <xsl:variable name="procBif_Y_" select="((($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * @BIF_Y) + ($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V))"/> + + <xsl:variable name="procBifType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $multiInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@TYPE"/> + <xsl:variable name="procBusName_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $multiInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BUSNAME"/> + <xsl:variable name="procBifSide_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $multiInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BIF_X"/> + + <xsl:variable name="bcProc_Y_" select="($mulshp_Y_ + $procBif_Y_ + ceiling($BLKD_BIF_H div 2) - ceiling($BLKD_BIFC_H div 2) + $procStack_H_diff_)"/> + + <xsl:variable name="bcProc_X_"> + <xsl:choose> + <xsl:when test="$procBifSide_ = '0'"> + <xsl:value-of select="($space_W_ + $extSpaceWest_W_ + $extSpaceEast_W_ - (ceiling($BLKD_MOD_W div 2) + $BLKD_BIFC_W))"/> +<!-- + <xsl:value-of select="($space_W_ + $extSpaceWest_W_ + $extSpaceEast_W_ - ceiling($BLKD_MOD_W div 2))"/> +--> + </xsl:when> + <xsl:when test="$procBifSide_ = '1'"> + <xsl:value-of select="ceiling($BLKD_MOD_W div 2)"/> + </xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <MULTICONN X="{$bcProc_X_}" Y="{$bcProc_Y_}" BUSNAME="{$procBusName_}" BUSSTD="{$iBusStd}" TYPE="{$procBifType_}" BIFSIDE="{$procBifSide_}" IS_PROC="TRUE"/> + </xsl:when> + + <xsl:otherwise> + + <xsl:variable name="modType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $multiInstance_)]/@MODCLASS"/> + <xsl:variable name="modBif_Y_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $multiInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BIF_Y"/> + <xsl:variable name="modBifSide_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $multiInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BIF_X"/> + <xsl:variable name="modBusStd_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $multiInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BUSSTD"/> + <xsl:variable name="memcMOD_W_" select="(($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[MODULE[(@INSTANCE = $multiInstance_)]]/@MODS_W) * $BLKD_MOD_W)"/> + + <xsl:variable name="modBc_Y_"> + <xsl:choose> + <xsl:when test="($modType_ = 'MEMORY_CNTLR') and (($modBusStd_ = 'LMB') or ($modBusStd_= 'OCM'))"> + <xsl:value-of select="$BLKD_MOD_H + $BLKD_MOD_LANE_H + ((($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * $modBif_Y_))"/> + </xsl:when> + <xsl:otherwise> + <xsl:value-of select="((($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * $modBif_Y_) + ($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V))"/> + </xsl:otherwise> + </xsl:choose> + </xsl:variable> +<!-- + <xsl:message><xsl:value-of select="$multiInstance_"/>.<xsl:value-of select="$bifName_"/>:Y = <xsl:value-of select="$modBif_Y_"/></xsl:message> + <xsl:message><xsl:value-of select="$multiInstance_"/>.<xsl:value-of select="$bifName_"/>:BcY = <xsl:value-of select="$modBc_Y_"/></xsl:message> + <xsl:message><xsl:value-of select="$multiInstance_"/>.<xsl:value-of select="$bifName_"/>:TcY = <xsl:value-of select="($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V)"/></xsl:message> +--> + + <xsl:variable name="modBifType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $multiInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@TYPE"/> + <xsl:variable name="modBusName_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $multiInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BUSNAME"/> + +<!-- + <xsl:variable name="bcMod_Y_" select="($mulshp_Y_ + $modBc_Y_ + ceiling($BLKD_BIF_H div 2) - ceiling($BLKD_BIFC_H div 2))"/> +--> + <xsl:variable name="bcMod_Y_" select="($mulshp_Y_ + $modBc_Y_ + ceiling($BLKD_BIF_H div 2) - ceiling($BLKD_BIFC_H div 2) + $cmplxStack_H_diff_)"/> + + <xsl:variable name="bcMod_X_"> + <xsl:choose> + <xsl:when test="$modBifSide_ = '0'"> + <xsl:value-of select="($space_W_ + $extSpaceWest_W_ + $extSpaceEast_W_ - (ceiling($memcMOD_W_ div 2) + $BLKD_BIFC_W))"/> +<!-- + --> + </xsl:when> + <xsl:when test="$modBifSide_ = '1'"> + <xsl:value-of select="ceiling($memcMOD_W_ div 2)"/> + </xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + + <MULTICONN X="{$bcMod_X_}" Y="{$bcMod_Y_}" BUSNAME="{$modBusName_}" BUSSTD="{$iBusStd}" TYPE="{$modBifType_}" BIFSIDE="{$modBifSide_}" IS_MOD="TRUE"/> +<!-- + <MULTICONN X="{$bcInSpace_X_}" Y="{$bcMod_Y_}" BUSSTD="{$busStd}" TYPE="{$modBifType_}" BIFSIDE="{$modBifSide_}"/> +--> + + </xsl:otherwise> + </xsl:choose> + </xsl:for-each> + </xsl:variable> + + <!-- Draw the busconnection and horizontal lines.--> + <xsl:for-each select="exsl:node-set($multiConns_)/MULTICONN"> + + <xsl:variable name="bus_x_" select="($bcInSpace_X_ + ceiling($BLKD_BIFC_W div 2))"/> + <xsl:variable name="bus_y_" select="@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_P2P_BUS_W div 2)"/> + +<!-- + <xsl:value-of select="$bus_x_"/> +--> + <xsl:variable name="h_bus_ul_x_"> + <xsl:choose> + <xsl:when test="@BIFSIDE='0' and (@IS_PROC)"> + <xsl:value-of select="$bus_x_ - $BLKD_P2P_BUS_W"/> + </xsl:when> + <xsl:when test="@BIFSIDE='0' and (@IS_MOD)"> + <xsl:value-of select="$bus_x_ - $BLKD_P2P_BUS_W"/> + </xsl:when> + <xsl:when test="@BIFSIDE='1' and (@IS_PROC)"> + <xsl:value-of select="(@X + $BLKD_BIFC_W + $BLKD_BUS_ARROW_W)"/> + </xsl:when> + <xsl:when test="@BIFSIDE='1' and (@IS_MOD)"> + <xsl:value-of select="(@X + $BLKD_BIFC_W + $BLKD_BUS_ARROW_W)"/> + </xsl:when> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="h_bus_ul_y_" select="$bus_y_"/> + <xsl:variable name="h_bus_height_" select="$BLKD_P2P_BUS_W"/> + <xsl:variable name="h_bus_width_"> +<!-- + <xsl:message>BUSSTD <xsl:value-of select="@BUSSTD"/></xsl:message> + <xsl:message>BIFSIDE <xsl:value-of select="@BIFSIDE"/></xsl:message> + <xsl:message>TYPE <xsl:value-of select="@TYPE"/></xsl:message> +--> + <xsl:choose> + <xsl:when test="@BIFSIDE='0' and (@IS_PROC)"> + <xsl:value-of select="(@X - $bus_x_ - $BLKD_P2P_BUS_W)"/> + </xsl:when> + <xsl:when test="@BIFSIDE='0' and (@IS_MOD)"> + <xsl:value-of select="(@X - $bus_x_ - $BLKD_BUS_ARROW_W)"/> + </xsl:when> + <xsl:when test="@BIFSIDE='1' and (@IS_PROC)"> + <xsl:value-of select="$bus_x_ - $h_bus_ul_x_ - $BLKD_BUS_ARROW_W - $BLKD_P2P_BUS_W"/> + </xsl:when> + <xsl:when test="@BIFSIDE='1' and (@IS_MOD)"> + <xsl:value-of select="$BLKD_P2P_BUS_W + $BLKD_BUS_ARROW_W "/> +<!-- + <xsl:value-of select="$bus_x_ - $h_bus_ul_x_"/> + --> + </xsl:when> + </xsl:choose> + </xsl:variable> + + +<!-- + <xsl:message>h_bus_x_ <xsl:value-of select="$h_bus_ul_x_"/></xsl:message> + <xsl:message>BIFSIDE <xsl:value-of select="@BIFSIDE"/></xsl:message> + <xsl:message>h_bus_width_ <xsl:value-of select="$h_bus_width_"/></xsl:message> + --> + + <!-- Draw the horizontal part of the bus --> + <xsl:if test="($h_bus_width_ > 0)"> + <rect x="{$h_bus_ul_x_}" + y="{$h_bus_ul_y_}" + width= "{$h_bus_width_}" + height="{$h_bus_height_}" + style="stroke:none; fill:{$busColor_}"/> + </xsl:if> + + + <!-- Draw the arrow --> + <xsl:choose> + <xsl:when test="((@BIFSIDE='0') and not((@BUSSTD = 'FSL') and ((@TYPE = 'INITIATOR') or (@TYPE = 'MASTER'))))"> + <use x="{@X - $BLKD_BUS_ARROW_W}" y="{@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_BUS_ARROW_H div 2)}" xlink:href="#{@BUSSTD}_BusArrowEast"/> + </xsl:when> + <xsl:when test="((@BIFSIDE='1') and not((@BUSSTD = 'FSL') and ((@TYPE = 'INITIATOR') or (@TYPE = 'MASTER'))))"> + <use x="{(@X + $BLKD_BIFC_W)}" y="{@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_BUS_ARROW_H div 2)}" xlink:href="#{@BUSSTD}_BusArrowWest"/> + </xsl:when> + + <xsl:when test="((@BIFSIDE='0') and ((@BUSSTD = 'FSL') and ((@TYPE = 'INITIATOR') or (@TYPE = 'MASTER'))))"> + <use x="{@X - $BLKD_BUS_ARROW_W}" y="{@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_BUS_ARROW_H div 2)}" xlink:href="#{@BUSSTD}_BusArrowHInitiator"/> + </xsl:when> + + <xsl:when test="((@BIFSIDE='1') and ((@BUSSTD = 'FSL') and ((@TYPE = 'INITIATOR') or (@TYPE = 'MASTER'))))"> + <use x="{(@X + $BLKD_BIFC_W)}" y="{@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_BUS_ARROW_H div 2)}" xlink:href="#{@BUSSTD}_BusArrowHInitiator"/> + </xsl:when> + + </xsl:choose> + + <use x="{@X}" y="{@Y}" xlink:href="#{@BUSSTD}_busconn_{@TYPE}"/> + + + </xsl:for-each> + + <xsl:variable name="busTop_" select="math:min(exsl:node-set($multiConns_)/MULTICONN/@Y)"/> + <xsl:variable name="busBot_" select="math:max(exsl:node-set($multiConns_)/MULTICONN/@Y)"/> + <xsl:variable name="v_bus_y_" select="$busTop_ + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_P2P_BUS_W div 2)"/> + <xsl:variable name="busName_" select="exsl:node-set($multiConns_)/MULTICONN/@BUSNAME"/> + +<!-- +--> + <!-- Draw the vertical part of the bus --> + <rect x="{$bcInSpace_X_ - $BLKD_P2P_BUS_W}" + y="{$v_bus_y_}" + width= "{$BLKD_P2P_BUS_W}" + height="{($busBot_ - $busTop_) + $BLKD_P2P_BUS_W}" + style="stroke:none; fill:{$busColor_}"/> +<!-- + <xsl:message>v_bus_x_ <xsl:value-of select="($bcInSpace_X_ + $BLKD_P2P_BUS_W)"/></xsl:message> + --> + + <!-- Place the bus label.--> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="($bcInSpace_X_ + $BLKD_BUS_ARROW_W + ceiling($BLKD_BUS_ARROW_W div 2) + ceiling($BLKD_BUS_ARROW_W div 4) + 6)"/> + <xsl:with-param name="iY" select="($busTop_ + ($BLKD_BUS_ARROW_H * 3))"/> + <xsl:with-param name="iText" select="$busName_"/> + <xsl:with-param name="iClass" select="'p2pbus_label'"/> + </xsl:call-template> + +</xsl:template> + + +<!-- + =========================================================== + Handle Processor to processor connections + =========================================================== +--> +<xsl:template name="BCLaneSpace_ProcToProc"> + + <xsl:param name="iBusStd" select="'NONE'"/> + <xsl:param name="iBusName" select="'NONE'"/> + <xsl:param name="iBifType" select="'NONE'"/> + <xsl:param name="iStackToEast" select="'NONE'"/> + <xsl:param name="iStackToWest" select="'NONE'"/> + <xsl:param name="iStackToEast_W" select="0"/> + <xsl:param name="iStackToWest_W" select="0"/> + <xsl:param name="iLaneInSpace_X" select="0"/> + + <xsl:variable name="busColor_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="$iBusStd"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="space_W_"> + <xsl:call-template name="F_Calc_Space_Width"> + <xsl:with-param name="iStackToEast" select="$iStackToEast"/> + <xsl:with-param name="iStackToWest" select="$iStackToWest"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name ="extSpaceWest_W_" select="ceiling($iStackToWest_W div 2)"/> + <xsl:variable name ="extSpaceEast_W_" select="ceiling($iStackToEast_W div 2)"/> + + <xsl:variable name="pr2pr_StackToWest_" select="math:min(BUSCONN/@STACK_HORIZ_INDEX)"/> + <xsl:variable name="pr2pr_StackToEast_" select="math:max(BUSCONN/@STACK_HORIZ_INDEX)"/> + <xsl:variable name="proc2procConn_heights_"> + + <xsl:for-each select="BUSCONN"> + + <xsl:variable name="procInstance_" select="@INSTANCE"/> + <xsl:variable name="bifName_" select="@BUSINTERFACE"/> + <xsl:variable name="procshp_hori_idx_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $procInstance_)]/@STACK_HORIZ_INDEX"/> + <xsl:variable name="procshp_vert_idx_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $procInstance_)]/@SHAPE_VERTI_INDEX"/> + <xsl:variable name="procshp_Y_"> + <xsl:call-template name="F_Calc_Stack_Shape_Y"> + <xsl:with-param name="iHorizIdx" select="$procshp_hori_idx_"/> + <xsl:with-param name="iVertiIdx" select="$procshp_vert_idx_"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="procStack_H_diff_"> + <xsl:choose> + <xsl:when test=" (($pr2pr_StackToEast_ = 'NONE') or ($pr2pr_StackToWest_ = 'NONE'))">0</xsl:when> + <xsl:when test="not(($pr2pr_StackToEast_ = 'NONE') or ($pr2pr_StackToWest_ = 'NONE'))"> + + <xsl:variable name="stackToWest_AbvSbs_H_"> + <xsl:call-template name="F_Calc_Stack_AbvSbs_Height"> + <xsl:with-param name="iStackIdx" select="$pr2pr_StackToWest_"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="stackToEast_AbvSbs_H_"> + <xsl:call-template name="F_Calc_Stack_AbvSbs_Height"> + <xsl:with-param name="iStackIdx" select="$pr2pr_StackToEast_"/> + </xsl:call-template> + </xsl:variable> +<!-- + <xsl:message>stack to west H <xsl:value-of select="$stackToWest_AbvSbs_H_"/></xsl:message> + <xsl:message>stack to east H <xsl:value-of select="$stackToEast_AbvSbs_H_"/></xsl:message> +--> + <xsl:choose> + <xsl:when test="(($procshp_hori_idx_ = $pr2pr_StackToEast_) and ($stackToWest_AbvSbs_H_ > $stackToEast_AbvSbs_H_))"> + <xsl:value-of select="($stackToWest_AbvSbs_H_ - $stackToEast_AbvSbs_H_)"/> + </xsl:when> + <xsl:when test="(($procshp_hori_idx_ = $pr2pr_StackToWest_) and ($stackToEast_AbvSbs_H_ > $stackToWest_AbvSbs_H_))"> + <xsl:value-of select="($stackToEast_AbvSbs_H_ - $stackToWest_AbvSbs_H_)"/> + </xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + + </xsl:when> + </xsl:choose> + </xsl:variable> + + <!-- Store the conns in a variable --> + <xsl:variable name="procBif_Y_" select="((($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * @BIF_Y) + ($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V))"/> + + <xsl:variable name="procBifType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $procInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@TYPE"/> + <xsl:variable name="procBifSide_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $procInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BIF_X"/> + + <xsl:variable name="bcInSpace_X_"> + <xsl:choose> + <xsl:when test="$procBifSide_ = '1'"><xsl:value-of select="ceiling($BLKD_MOD_W div 2)"/></xsl:when> + <xsl:when test="$procBifSide_ = '0'"><xsl:value-of select="($space_W_ + $extSpaceWest_W_ + $extSpaceEast_W_ - ceiling($BLKD_MOD_W div 2) - $BLKD_BIFC_W)"/></xsl:when> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="bcProc_Y_" select="($procshp_Y_ + $procBif_Y_ + ceiling($BLKD_BIF_H div 2) - ceiling($BLKD_BIFC_H div 2) + $procStack_H_diff_)"/> +<!-- + <xsl:message>Conn X <xsl:value-of select="$bcInSpace_X_"/></xsl:message> + <xsl:message>Conn Y <xsl:value-of select="$bcProc_Y_"/></xsl:message> +--> + + <PR2PRCONN X="{$bcInSpace_X_}" Y="{$bcProc_Y_}" BUSSTD="{$iBusStd}" TYPE="{$procBifType_}" BIFSIDE="{$procBifSide_}" SHAPE_ID="{$procshp_hori_idx_}"/> + </xsl:for-each> + </xsl:variable> + + <xsl:variable name="pr2prLeft_" select="math:min(exsl:node-set($proc2procConn_heights_)/PR2PRCONN/@SHAPE_ID)"/> + <xsl:variable name="pr2prRght_" select="math:max(exsl:node-set($proc2procConn_heights_)/PR2PRCONN/@SHAPE_ID)"/> + + <xsl:variable name="pr2pr_stack_Left_X_"> + <xsl:call-template name="F_Calc_Stack_X"> + <xsl:with-param name="iStackIdx" select="$pr2prLeft_"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="pr2pr_stack_Rght_X_"> + <xsl:call-template name="F_Calc_Stack_X"> + <xsl:with-param name="iStackIdx" select="$pr2prRght_"/> + </xsl:call-template> + </xsl:variable> + +<!-- + <xsl:message>Left stack X <xsl:value-of select="$pr2pr_stack_Left_X_"/></xsl:message> + <xsl:message>Rght stack X <xsl:value-of select="$pr2pr_stack_Rght_X_"/></xsl:message> +--> + <xsl:variable name="pr2pr_space_W_" select="($pr2pr_stack_Rght_X_ - $pr2pr_stack_Left_X_)"/> + + + <xsl:variable name="pr2pr_extStackEast_W_"> + <xsl:call-template name="F_Calc_Stack_Width"> + <xsl:with-param name="iStackIdx" select="$pr2prRght_"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="pr2pr_extStackWest_W_"> + <xsl:call-template name="F_Calc_Stack_Width"> + <xsl:with-param name="iStackIdx" select="$pr2prLeft_"/> + </xsl:call-template> + </xsl:variable> + +<!-- + <xsl:message>Space W <xsl:value-of select="$pr2pr_space_W_"/></xsl:message> + <xsl:message>Rght stack <xsl:value-of select="$pr2pr_extStackEast_W_"/></xsl:message> + <xsl:message>Left stack <xsl:value-of select="$pr2pr_extStackWest_W_"/></xsl:message> +--> + + <xsl:variable name="connLeft_X_" select="ceiling($BLKD_MOD_W div 2)"/> + <xsl:variable name="connRght_X_" select="($pr2pr_space_W_ - ceiling($pr2pr_extStackWest_W_ div 2) + ceiling($pr2pr_extStackEast_W_ div 2) - ceiling($BLKD_MOD_W div 2) - $BLKD_BIFC_W)"/> + + <!-- Draw the busconnections .--> + <xsl:for-each select="exsl:node-set($proc2procConn_heights_)/PR2PRCONN"> + <xsl:variable name="conn_X_"> + <xsl:choose> + <xsl:when test="@BIFSIDE = '1'"><xsl:value-of select="ceiling($BLKD_MOD_W div 2)"/></xsl:when> + <xsl:when test="@BIFSIDE = '0'"><xsl:value-of select="($pr2pr_space_W_ - ceiling($pr2pr_extStackWest_W_ div 2) + ceiling($pr2pr_extStackEast_W_ div 2) - ceiling($BLKD_MOD_W div 2) - $BLKD_BIFC_W)"/></xsl:when> +<!-- + <xsl:when test="@BIFSIDE = '0'"><xsl:value-of select="($pr2pr_space_W_ + $pr2pr_extStackWest_W_ + $pr2pr_extStackEast_W_ - ceiling($BLKD_MOD_W div 2) - $BLKD_BIFC_W)"/></xsl:when> +--> + </xsl:choose> + </xsl:variable> + + + <use x="{$conn_X_}" y="{@Y}" xlink:href="#{@BUSSTD}_busconn_{@TYPE}"/> + </xsl:for-each> + + <xsl:variable name="bc_Y_" select="math:min(exsl:node-set($proc2procConn_heights_)/PR2PRCONN/@Y)"/> + <xsl:variable name="bcLeft_" select="math:min(exsl:node-set($proc2procConn_heights_)/PR2PRCONN/@X)"/> + <xsl:variable name="bcRght_" select="math:max(exsl:node-set($proc2procConn_heights_)/PR2PRCONN/@X)"/> + + <xsl:variable name="leftType_" select="(exsl:node-set($proc2procConn_heights_)/PR2PRCONN[(@X = $bcLeft_)]/@TYPE)"/> + <xsl:variable name="rghtType_" select="(exsl:node-set($proc2procConn_heights_)/PR2PRCONN[(@X = $bcRght_)]/@TYPE)"/> + + <xsl:call-template name="Draw_Proc2ProcBus"> + <xsl:with-param name="iBc_Y" select="$bc_Y_"/> + <xsl:with-param name="iBusStd" select="$iBusStd"/> + <xsl:with-param name="iBusName" select="$iBusName"/> + <xsl:with-param name="iLeftType" select="$leftType_"/> + <xsl:with-param name="iRghtType" select="$rghtType_"/> + <xsl:with-param name="iBcLeft_X" select="$connLeft_X_ + $BLKD_BIFC_W"/> + <xsl:with-param name="iBcRght_X" select="$connRght_X_"/> + </xsl:call-template> + +</xsl:template> + +<!-- + =========================================================== + Handle connections to the MPMC + =========================================================== +--> +<xsl:template name="BCLaneSpace_ToStandAloneMPMC"> + + <xsl:param name="iBusStd" select="'NONE'"/> + <xsl:param name="iBusName" select="'NONE'"/> + <xsl:param name="iBifType" select="'NONE'"/> + <xsl:param name="iStackToEast" select="'NONE'"/> + <xsl:param name="iStackToWest" select="'NONE'"/> + <xsl:param name="iStackToEast_W" select="0"/> + <xsl:param name="iStackToWest_W" select="0"/> + <xsl:param name="iLaneInSpace_X" select="0"/> + + <xsl:variable name="busColor_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="$iBusStd"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="busColor_lt_"> + <xsl:call-template name="F_BusStd2RGB_LT"> + <xsl:with-param name="iBusStd" select="$iBusStd"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="space_W_"> + <xsl:call-template name="F_Calc_Space_Width"> + <xsl:with-param name="iStackToEast" select="$iStackToEast"/> + <xsl:with-param name="iStackToWest" select="$iStackToWest"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name ="extSpaceWest_W_" select="ceiling($iStackToWest_W div 2)"/> + <xsl:variable name ="extSpaceEast_W_" select="ceiling($iStackToEast_W div 2)"/> + + <xsl:variable name="bcInSpace_X_" select="($iLaneInSpace_X + ceiling($BLKD_BIFC_W div 2) - ceiling($BLKD_BUS_ARROW_W div 2))"/> + <xsl:variable name="p2pInstance_" select="BUSCONN[(@BIF_Y)]/@INSTANCE"/> + + <xsl:variable name="p2pshp_hori_idx_"> + <xsl:choose> + <xsl:when test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $p2pInstance_)]"> + <xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $p2pInstance_)]/@STACK_HORIZ_INDEX"/> + </xsl:when> + <xsl:otherwise> + <xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(MODULE[(@INSTANCE = $p2pInstance_)])]/@STACK_HORIZ_INDEX"/> + </xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="p2pshp_vert_idx_"> + <xsl:choose> + <xsl:when test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $p2pInstance_)]"> + <xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $p2pInstance_)]/@SHAPE_VERTI_INDEX"/> + </xsl:when> + <xsl:otherwise> + <xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(MODULE[(@INSTANCE = $p2pInstance_)])]/@SHAPE_VERTI_INDEX"/> + </xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="p2pshp_Y_"> + <xsl:call-template name="F_Calc_Stack_Shape_Y"> + <xsl:with-param name="iHorizIdx" select="$p2pshp_hori_idx_"/> + <xsl:with-param name="iVertiIdx" select="$p2pshp_vert_idx_"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="cmplxStack_H_diff_"> + <xsl:choose> + <xsl:when test=" (($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))">0</xsl:when> + <xsl:when test="not(($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))"> + + <xsl:variable name="stackToWest_AbvSbs_H_"> + <xsl:call-template name="F_Calc_Stack_AbvSbs_Height"> + <xsl:with-param name="iStackIdx" select="$iStackToWest"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="stackToEast_AbvSbs_H_"> + <xsl:call-template name="F_Calc_Stack_AbvSbs_Height"> + <xsl:with-param name="iStackIdx" select="$iStackToEast"/> + </xsl:call-template> + </xsl:variable> + +<!-- + <xsl:message>stack to west H <xsl:value-of select="$stackToWest_AbvSbs_H_"/></xsl:message> + <xsl:message>stack to east H <xsl:value-of select="$stackToEast_AbvSbs_H_"/></xsl:message> +--> + + <xsl:choose> + <xsl:when test="(($p2pshp_hori_idx_ = $iStackToEast) and ($stackToWest_AbvSbs_H_ > $stackToEast_AbvSbs_H_))"> + <xsl:value-of select="($stackToWest_AbvSbs_H_ - $stackToEast_AbvSbs_H_)"/> + </xsl:when> + <xsl:when test="(($p2pshp_hori_idx_ = $iStackToWest) and ($stackToEast_AbvSbs_H_ > $stackToWest_AbvSbs_H_))"> + <xsl:value-of select="($stackToEast_AbvSbs_H_ - $stackToWest_AbvSbs_H_)"/> + </xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + + </xsl:when> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="procStack_H_diff_"> + <xsl:choose> + <xsl:when test=" (($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))">0</xsl:when> + <xsl:when test="not(($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))"> + + <xsl:variable name="stackToWest_AbvSbs_H_"> + <xsl:call-template name="F_Calc_Stack_AbvSbs_Height"> + <xsl:with-param name="iStackIdx" select="$iStackToWest"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="stackToEast_AbvSbs_H_"> + <xsl:call-template name="F_Calc_Stack_AbvSbs_Height"> + <xsl:with-param name="iStackIdx" select="$iStackToEast"/> + </xsl:call-template> + </xsl:variable> + +<!-- + <xsl:message>stack to west H <xsl:value-of select="$stackToWest_AbvSbs_H_"/></xsl:message> + <xsl:message>stack to east H <xsl:value-of select="$stackToEast_AbvSbs_H_"/></xsl:message> +--> + <xsl:choose> + <xsl:when test="(($p2pshp_hori_idx_ = $iStackToEast) and ($stackToWest_AbvSbs_H_ > $stackToEast_AbvSbs_H_))"> + <xsl:value-of select="($stackToWest_AbvSbs_H_ - $stackToEast_AbvSbs_H_)"/> + </xsl:when> + <xsl:when test="(($p2pshp_hori_idx_ = $iStackToWest) and ($stackToEast_AbvSbs_H_ > $stackToWest_AbvSbs_H_))"> + <xsl:value-of select="($stackToEast_AbvSbs_H_ - $stackToWest_AbvSbs_H_)"/> + </xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + + </xsl:when> + </xsl:choose> + </xsl:variable> + + + + <!-- Store the conns in a variable --> + <xsl:variable name="p2pConn_heights_"> + + <xsl:for-each select="BUSCONN"> + + <xsl:variable name="bifName_" select="@BUSINTERFACE"/> + + <xsl:choose> + <xsl:when test="@IS_PROCCONN and @BIF_Y"> + +<!-- + <xsl:message>Proc <xsl:value-of select="$procInstance_"/></xsl:message> +--> + <xsl:variable name="procBif_Y_" select="((($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * @BIF_Y) + ($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V))"/> + <xsl:variable name="procBifType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $p2pInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@TYPE"/> + <xsl:variable name="procBusName_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $p2pInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BUSNAME"/> + <xsl:variable name="procBifSide_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $p2pInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BIF_X"/> + + <xsl:variable name="bcProc_Y_" select="($p2pshp_Y_ + $procBif_Y_ + ceiling($BIF_H div 2) - ceiling($BLKD_BIFC_H div 2) + $procStack_H_diff_)"/> + <xsl:variable name="bcProc_X_"> + <xsl:choose> + <xsl:when test="$procBifSide_ = '0'"> + <xsl:value-of select="($space_W_ + $extSpaceWest_W_ + $extSpaceEast_W_ - (ceiling($BLKD_MOD_W div 2) + $BLKD_BIFC_W))"/> + </xsl:when> + <xsl:when test="$procBifSide_ = '1'"> + <xsl:value-of select="ceiling($BLKD_MOD_W div 2)"/> + </xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <P2PCONN X="{$bcProc_X_}" Y="{$bcProc_Y_}" BUSNAME= "{$procBusName_}" BUSSTD="{$iBusStd}" TYPE="{$procBifType_}" BIFSIDE="{$procBifSide_}"/> + + </xsl:when> + + <xsl:otherwise> + + <xsl:variable name="modInstance_" select="@INSTANCE"/> + <xsl:variable name="modshp_vert_idx_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[MODULE[(@INSTANCE = $modInstance_)]]/@SHAPE_VERTI_INDEX"/> + <xsl:variable name="modBifSide_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $modInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BIF_X"/> + <xsl:variable name="modBif_Y_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $modInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BIF_Y"/> + <xsl:variable name="modBc_Y_" select="((($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * $modBif_Y_) + ($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V))"/> + +<!-- + <xsl:message>Memory Instance <xsl:value-of select="$procInstance_"/></xsl:message> +--> + + <xsl:variable name="modshp_Y_"> + <xsl:call-template name="F_Calc_Stack_Shape_Y"> + <xsl:with-param name="iHorizIdx" select="$p2pshp_hori_idx_"/> + <xsl:with-param name="iVertiIdx" select="$modshp_vert_idx_"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="modBifType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $modInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@TYPE"/> + <xsl:variable name="modBusName_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $modInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BUSNAME"/> + <xsl:variable name="bcMod_Y_" select="($modshp_Y_ + $modBc_Y_ + ceiling($BLKD_BIF_H div 2) - ceiling($BLKD_BIFC_H div 2) + $cmplxStack_H_diff_)"/> + <xsl:variable name="bcMod_X_"> + <xsl:choose> + <xsl:when test="$modBifSide_ = '0'"> + <xsl:value-of select="($space_W_ + $extSpaceWest_W_ + $extSpaceEast_W_ - (ceiling($BLKD_MOD_W div 2) + $BLKD_BIFC_W))"/> + </xsl:when> + <xsl:when test="$modBifSide_ = '1'"> + <xsl:value-of select="ceiling($BLKD_MOD_W div 2)"/> + </xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <P2PCONN X="{$bcMod_X_}" Y="{$bcMod_Y_}" BUSNAME="{$modBusName_}" BUSSTD="{$iBusStd}" TYPE="{$modBifType_}" BIFSIDE="{$modBifSide_}"/> + + </xsl:otherwise> + + </xsl:choose> + </xsl:for-each> + </xsl:variable> + + + <xsl:variable name="busTop_" select="math:min(exsl:node-set($p2pConn_heights_)/P2PCONN/@Y)"/> + <xsl:variable name="busBot_" select="math:max(exsl:node-set($p2pConn_heights_)/P2PCONN/@Y)"/> + <xsl:variable name="v_bus_y_" select="$busTop_ + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_P2P_BUS_W div 2)"/> + + <xsl:variable name="busName_" select="exsl:node-set($p2pConn_heights_)/P2PCONN/@BUSNAME"/> + <xsl:variable name="busStd_" select="exsl:node-set($p2pConn_heights_)/P2PCONN/@BUSSTD"/> + + <!-- Draw the vertical part of the bus --> + <!-- Place the bus label.--> + <!-- Draw the busconnection and horizontal lines.--> + <xsl:for-each select="exsl:node-set($p2pConn_heights_)/P2PCONN"> + + <xsl:variable name="bus_x_" select="($bcInSpace_X_ + ceiling($BLKD_BIFC_W div 2))"/> + <xsl:variable name="bus_y_" select="@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_P2P_BUS_W div 2)"/> + + <xsl:variable name="h_bus_ul_x_"> + <xsl:choose> + <xsl:when test="@BIFSIDE='0'"> + <xsl:value-of select="$bus_x_"/> + </xsl:when> + <xsl:when test="@BIFSIDE='1'"> + <xsl:value-of select="(@X + $BLKD_BIFC_W + $BLKD_BUS_ARROW_W) - 1"/> + </xsl:when> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="h_bus_ul_y_" select="$bus_y_"/> + + <xsl:variable name="h_bus_height_" select="$BLKD_P2P_BUS_W"/> + <xsl:variable name="h_bus_width_"> + <xsl:choose> + <xsl:when test="@BIFSIDE='0'"> + <xsl:value-of select="(@X - $bus_x_ - $BLKD_BUS_ARROW_W)"/> + </xsl:when> + <xsl:when test="@BIFSIDE='1'"> + <xsl:value-of select="$bus_x_ - $h_bus_ul_x_ + 1"/> + </xsl:when> + + </xsl:choose> + </xsl:variable> + + <!-- Draw Bus connection--> + <use x="{@X}" y="{@Y}" xlink:href="#{@BUSSTD}_busconn_{@TYPE}"/> + + <!-- Draw the arrow --> + <xsl:choose> + <xsl:when test="((@BIFSIDE='0') and not((@BUSSTD = 'FSL') and ((@TYPE = 'INITIATOR') or (@TYPE = 'MASTER'))))"> + <use x="{@X - $BLKD_BUS_ARROW_W}" y="{@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_BUS_ARROW_H div 2)}" xlink:href="#{@BUSSTD}_BusArrowEast"/> + </xsl:when> + <xsl:when test="((@BIFSIDE='1') and not((@BUSSTD = 'FSL') and ((@TYPE = 'INITIATOR') or (@TYPE = 'MASTER'))))"> + <use x="{(@X + $BLKD_BIFC_W)}" y="{@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_BUS_ARROW_H div 2)}" xlink:href="#{@BUSSTD}_BusArrowWest"/> + </xsl:when> + + <xsl:when test="((@BIFSIDE='0') and ((@BUSSTD = 'FSL') and ((@TYPE = 'INITIATOR') or (@TYPE = 'MASTER'))))"> + <use x="{@X - $BLKD_BUS_ARROW_W}" y="{@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_BUS_ARROW_H div 2)}" xlink:href="#{@BUSSTD}_BusArrowHInitiator"/> + </xsl:when> + + <xsl:when test="((@BIFSIDE='1') and ((@BUSSTD = 'FSL') and ((@TYPE = 'INITIATOR') or (@TYPE = 'MASTER'))))"> + <use x="{(@X + $BLKD_BIFC_W)}" y="{@Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_BUS_ARROW_H div 2)}" xlink:href="#{@BUSSTD}_BusArrowHInitiator"/> + </xsl:when> + + </xsl:choose> + + <!-- Draw the horizontal part of the bus --> + <rect x="{$h_bus_ul_x_}" + y="{$h_bus_ul_y_}" + width= "{$h_bus_width_}" + height="{$h_bus_height_}" + + style="stroke:none; fill:{$busColor_}"/> + + <!-- + Draw the vertical part of the bus. The MPMC BIF and the top arrow will + be added later when the main drawing happens. + --> + <xsl:variable name="v_bus_ul_x_"> + <xsl:choose> + <xsl:when test="@BIFSIDE='0'"><xsl:value-of select="($h_bus_ul_x_)"/></xsl:when> + <xsl:when test="@BIFSIDE='1'"><xsl:value-of select="($h_bus_ul_x_ + $h_bus_width_ - $BLKD_P2P_BUS_W)"/></xsl:when> + </xsl:choose> + </xsl:variable> + + <rect x="{$v_bus_ul_x_}" + y="0" + width= "{$BLKD_P2P_BUS_W}" + height="{$h_bus_ul_y_}" + style="stroke:none; fill:{$busColor_}"/> + </xsl:for-each> + +</xsl:template> + + + +<!-- + ====================================================================== + Handle Split connections, (connections that go between adjacent stacks) + ====================================================================== +--> + +<xsl:template name="BCLaneSpace_SplitConn"> + + <xsl:param name="iBusStd" select="'NONE'"/> + <xsl:param name="iBusName" select="'NONE'"/> + <xsl:param name="iBifType" select="'NONE'"/> + <xsl:param name="iStackToEast" select="'NONE'"/> + <xsl:param name="iStackToWest" select="'NONE'"/> + <xsl:param name="iStackToEast_W" select="0"/> + <xsl:param name="iStackToWest_W" select="0"/> + <xsl:param name="iLaneInSpace_X" select="0"/> + + <xsl:variable name="busColor_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="$iBusStd"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="space_W_"> + <xsl:call-template name="F_Calc_Space_Width"> + <xsl:with-param name="iStackToEast" select="$iStackToEast"/> + <xsl:with-param name="iStackToWest" select="$iStackToWest"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name ="extSpaceWest_W_" select="ceiling($iStackToWest_W div 2)"/> + <xsl:variable name ="extSpaceEast_W_" select="ceiling($iStackToEast_W div 2)"/> + + + <xsl:variable name="bifName_" select="BUSCONN/@BUSINTERFACE"/> + <xsl:variable name="shpInstance_" select="BUSCONN/@INSTANCE"/> + +<!-- + <xsl:message>Found a split connection on <xsl:value-of select="$shpInstance_"/></xsl:message> +--> + + + <xsl:variable name="shp_hori_idx_"> + + <xsl:choose> + <xsl:when test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $shpInstance_)]"> + <xsl:value-of select="/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $shpInstance_)]/@STACK_HORIZ_INDEX"/> + </xsl:when> + + <xsl:when test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(MODULE[(@INSTANCE = $shpInstance_)])]"> + <xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(MODULE[(@INSTANCE = $shpInstance_)])]/@STACK_HORIZ_INDEX"/> + </xsl:when> + <xsl:otherwise>_unknown_</xsl:otherwise> + </xsl:choose> + + </xsl:variable> + + <xsl:variable name="shp_vert_idx_"> + + <xsl:choose> + <xsl:when test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $shpInstance_)]"> + <xsl:value-of select="/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $shpInstance_)]/@SHAPE_VERTI_INDEX"/> + </xsl:when> + + <xsl:when test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(MODULE[(@INSTANCE = $shpInstance_)])]"> + <xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(MODULE[(@INSTANCE = $shpInstance_)])]/@SHAPE_VERTI_INDEX"/> + </xsl:when> + <xsl:otherwise>_unknown_</xsl:otherwise> + </xsl:choose> + + </xsl:variable> + + <xsl:variable name="splitshp_Width_"> + + <xsl:choose> + <xsl:when test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $shpInstance_)]"> + <xsl:value-of select="$BLKD_MOD_W"/> + </xsl:when> + + <xsl:when test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(MODULE[(@INSTANCE = $shpInstance_)])]/@MODS_W"> +<!-- + <xsl:message>Using mods width on <xsl:value-of select="$shpInstance_"/></xsl:message> +--> + <xsl:value-of select="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(MODULE[(@INSTANCE = $shpInstance_)])]/@MODS_W * $BLKD_MOD_W)"/> + </xsl:when> + <xsl:otherwise> + <xsl:value-of select="$BLKD_MOD_W"/> + </xsl:otherwise> + </xsl:choose> + + </xsl:variable> + +<!-- + <xsl:message>Found width of <xsl:value-of select="$splitshp_Width_"/></xsl:message> +--> + + + <xsl:variable name="splitshp_Y_"> + <xsl:call-template name="F_Calc_Stack_Shape_Y"> + <xsl:with-param name="iHorizIdx" select="$shp_hori_idx_"/> + <xsl:with-param name="iVertiIdx" select="$shp_vert_idx_"/> + </xsl:call-template> + </xsl:variable> + + + <xsl:variable name="splitStack_H_diff_"> + <xsl:choose> + <xsl:when test=" (($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))">0</xsl:when> + <xsl:when test="not(($iStackToEast = 'NONE') or ($iStackToWest = 'NONE'))"> + + <xsl:variable name="stackToWest_AbvSbs_H_"> + <xsl:call-template name="F_Calc_Stack_AbvSbs_Height"> + <xsl:with-param name="iStackIdx" select="$iStackToWest"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="stackToEast_AbvSbs_H_"> + <xsl:call-template name="F_Calc_Stack_AbvSbs_Height"> + <xsl:with-param name="iStackIdx" select="$iStackToEast"/> + </xsl:call-template> + </xsl:variable> + + <xsl:choose> + <xsl:when test="(($shp_hori_idx_ = $iStackToEast) and ($stackToWest_AbvSbs_H_ > $stackToEast_AbvSbs_H_))"> + <xsl:value-of select="($stackToWest_AbvSbs_H_ - $stackToEast_AbvSbs_H_)"/> + </xsl:when> + <xsl:when test="(($shp_hori_idx_ = $iStackToWest) and ($stackToEast_AbvSbs_H_ > $stackToWest_AbvSbs_H_))"> + <xsl:value-of select="($stackToEast_AbvSbs_H_ - $stackToWest_AbvSbs_H_)"/> + </xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + + </xsl:when> + </xsl:choose> + </xsl:variable> + + + <xsl:variable name="splitBif_Y_" select="((($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * BUSCONN/@BIF_Y) + ($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V))"/> + <xsl:variable name="splitBusStd_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $shpInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BUSSTD"/> + <xsl:variable name="splitBifType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $shpInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@TYPE"/> + <xsl:variable name="splitBifSide_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $shpInstance_)]/BUSINTERFACE[(@NAME = $bifName_)]/@BIF_X"/> + + <xsl:variable name="bcInSpace_X_"> + <xsl:choose> + <xsl:when test="$splitBifSide_ = '1'"><xsl:value-of select="ceiling($splitshp_Width_ div 2)"/></xsl:when> + <xsl:when test="$splitBifSide_ = '0'"><xsl:value-of select="($space_W_ + $extSpaceWest_W_ + $extSpaceEast_W_ - ceiling($splitshp_Width_ div 2) - $BLKD_BIFC_W)"/></xsl:when> + </xsl:choose> + + </xsl:variable> + + <xsl:variable name="bcBus_X_"> + <xsl:choose> + <xsl:when test="$splitBifSide_ = '1'"><xsl:value-of select="$bcInSpace_X_"/></xsl:when> + <xsl:when test="$splitBifSide_ = '0'"><xsl:value-of select="($space_W_ + $extSpaceWest_W_ + $extSpaceEast_W_ - ceiling($BLKD_MOD_W div 2) - $BLKD_BIFC_W)"/></xsl:when> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="bcSplit_Y_"> + <xsl:choose> + <xsl:when test="(BUSCONN/@IS_MEMCONN) and (($splitBusStd_ = 'LMB') or ($splitBusStd_ = 'OCM'))"> +<!-- + <xsl:message>Found memory conn split connection on <xsl:value-of select="$shpInstance_"/> </xsl:message> +--> + <xsl:value-of select="($splitshp_Y_ + $BLKD_MOD_H + $BLKD_MOD_BIF_GAP_V + (BUSCONN/@BIF_Y * ($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V)) + ceiling($BLKD_BIF_H div 2) - ceiling($BLKD_BIFC_H div 2) + $splitStack_H_diff_)"/> + </xsl:when> + <xsl:otherwise> + <xsl:value-of select="($splitshp_Y_ + $splitBif_Y_ + ceiling($BLKD_BIF_H div 2) - ceiling($BLKD_BIFC_H div 2) + $splitStack_H_diff_)"/> + </xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <use x="{$bcInSpace_X_}" y="{$bcSplit_Y_}" xlink:href="#{@BUSSTD}_busconn_{$splitBifType_}"/> + + + <xsl:call-template name="Draw_SplitConnBus"> + <xsl:with-param name="iBc_Y" select="$bcSplit_Y_"/> + <xsl:with-param name="iBc_X" select="$bcInSpace_X_"/> + <xsl:with-param name="iBusStd" select="$iBusStd"/> + <xsl:with-param name="iBc_Type" select="$splitBifType_"/> + <xsl:with-param name="iBc_Side" select="$splitBifSide_"/> + <xsl:with-param name="iBusName" select="$iBusName"/> + </xsl:call-template> + + +</xsl:template> + + +<xsl:template name="Define_BusLaneSpace"> + + <xsl:param name="iStackToEast" select="'NONE'"/> + <xsl:param name="iStackToWest" select="'NONE'"/> + +<!-- + <xsl:message>Input Stack to West <xsl:value-of select="$iStackToWest"/></xsl:message> + <xsl:message>Input Stack to East <xsl:value-of select="$iStackToEast"/></xsl:message> +--> + + <xsl:variable name="stackToEast_"> + <xsl:choose> + <xsl:when test="not($iStackToEast = 'NONE')"><xsl:value-of select="$iStackToEast"/></xsl:when> + <xsl:otherwise>NONE</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="stackToWest_"> + <xsl:choose> + <xsl:when test=" not($iStackToWest = 'NONE')"><xsl:value-of select="$iStackToWest"/></xsl:when> + <xsl:when test="(not($iStackToEast = 'NONE') and not($iStackToEast = '0'))"><xsl:value-of select="($iStackToEast - 1)"/></xsl:when> + <xsl:otherwise>NONE</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="spaceAbvSbs_H_"> + <xsl:call-template name="F_Calc_Space_AbvSbs_Height"> + <xsl:with-param name="iStackToEast" select="$iStackToEast"/> + <xsl:with-param name="iStackToWest" select="$iStackToWest"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="spaceBlwSbs_H_"> + <xsl:call-template name="F_Calc_Space_BlwSbs_Height"> + <xsl:with-param name="iStackToEast" select="$iStackToEast"/> + <xsl:with-param name="iStackToWest" select="$iStackToWest"/> + </xsl:call-template> + </xsl:variable> + + + <xsl:variable name="space_H_" select="($spaceAbvSbs_H_ + $BLKD_PROC2SBS_GAP + $G_Total_SharedBus_H + $spaceBlwSbs_H_)"/> + <xsl:variable name="space_W_"> + <xsl:call-template name="F_Calc_Space_Width"> + <xsl:with-param name="iStackToEast" select="$iStackToEast"/> + <xsl:with-param name="iStackToWest" select="$iStackToWest"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="spaceSharedBus_Y_" select="$spaceAbvSbs_H_ + $BLKD_PROC2SBS_GAP"/> + + <xsl:variable name="space_name_"> + <xsl:call-template name="F_generate_Space_Name"> + <xsl:with-param name="iStackToEast" select="$stackToEast_"/> + <xsl:with-param name="iStackToWest" select="$stackToWest_"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name = "stackToWest_W_"> + <xsl:choose> + <xsl:when test="(($iStackToEast = '0') and ($iStackToWest = 'NONE'))">0</xsl:when> + <xsl:when test="(($iStackToEast = 'NONE') and not($iStackToWest = 'NONE'))"> + <xsl:call-template name="F_Calc_Stack_Width"> + <xsl:with-param name="iStackIdx" select="$iStackToWest"/> + </xsl:call-template> + </xsl:when> + <xsl:when test="(not($iStackToEast = '0') and not($iStackToEast = 'NONE') and ($iStackToWest = 'NONE'))"> + <xsl:call-template name="F_Calc_Stack_Width"> + <xsl:with-param name="iStackIdx" select="($iStackToEast - 1)"/> + </xsl:call-template> + </xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name = "stackToEast_W_"> + <xsl:call-template name="F_Calc_Stack_Width"> + <xsl:with-param name="iStackIdx" select="$iStackToEast"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name ="extSpaceWest_W_" select="ceiling($stackToWest_W_ div 2)"/> + <xsl:variable name ="extSpaceEast_W_" select="ceiling($stackToEast_W_ div 2)"/> + + <g id="{$space_name_}"> + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE[((@EAST = $iStackToEast) or (($iStackToEast = 'NONE') and (@WEST = $iStackToWest)))]/BUSCONNLANE[@BUSSTD and @BUSNAME]"> + + <xsl:variable name="busStd_" select="@BUSSTD"/> + <xsl:variable name="busName_" select="@BUSNAME"/> + <xsl:variable name="lane_X_" select="@BUSLANE_X"/> + + <xsl:variable name="eastBusLane_X_"> + <xsl:choose> + <xsl:when test="(@BUSLANE_X = 0)"><xsl:value-of select="@BUSLANE_X"/></xsl:when> + <xsl:otherwise><xsl:value-of select="(@BUSLANE_X - 1)"/></xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="laneInSpace_X_"> + <xsl:choose> + <xsl:when test="(@ORIENTED = 'EAST')"> + <xsl:value-of select="($extSpaceWest_W_ + ($eastBusLane_X_ * $BLKD_BUS_LANE_W) - $BLKD_BUS_ARROW_W - $BLKD_P2P_BUS_W)"/> + </xsl:when> + <xsl:otherwise><xsl:value-of select="($extSpaceWest_W_ + (@BUSLANE_X * $BLKD_BUS_LANE_W))"/></xsl:otherwise> + </xsl:choose> + </xsl:variable> + + + <xsl:variable name="busColor_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="@BUSSTD"/> + </xsl:call-template> + </xsl:variable> + + <xsl:choose> +<!-- + =========================================================== + Handle Bucket connections to the shared busses. + =========================================================== +--> + <xsl:when test="@BUSLANE_X and @IS_BKTCONN and BUSCONN[@TYPE] and $G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $busName_)]/@BUS_INDEX"> + <xsl:call-template name="BCLaneSpace_BucketToSharedBus"> + <xsl:with-param name="iBusName" select="$busName_"/> + <xsl:with-param name="iBusStd" select="$busStd_"/> + <xsl:with-param name="iBifType" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $busName_)]/BUSINTERFACE/@TYPE"/> + <xsl:with-param name="iStackToEast" select="$stackToEast_"/> + <xsl:with-param name="iStackToWest" select="$stackToWest_"/> + <xsl:with-param name="iStackToEast_W" select="$stackToEast_W_"/> + <xsl:with-param name="iStackToWest_W" select="$stackToWest_W_"/> + <xsl:with-param name="iLaneInSpace_X" select="$laneInSpace_X_"/> + <xsl:with-param name="iSpaceSharedBus_Y" select="$spaceSharedBus_Y_"/> + </xsl:call-template> + </xsl:when> + +<!-- + =========================================================== + Handle Processor's Shared bus connections. + =========================================================== +--> + <xsl:when test="@BUSLANE_X and @IS_SBSCONN and not(@IS_MPMCCONN) and BUSCONN[@BIF_Y and @IS_PROCCONN and @INSTANCE and @BUSINTERFACE] and $G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $busName_)]/@BUS_INDEX"> + <xsl:call-template name="BCLaneSpace_ProcBifToSharedBus"> + <xsl:with-param name="iBusStd" select="$busStd_"/> + <xsl:with-param name="iBusName" select="$busName_"/> + <xsl:with-param name="iBifType" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $busName_)]/BUSINTERFACE/@TYPE"/> + <xsl:with-param name="iStackToEast" select="$stackToEast_"/> + <xsl:with-param name="iStackToWest" select="$stackToWest_"/> + <xsl:with-param name="iStackToEast_W" select="$stackToEast_W_"/> + <xsl:with-param name="iStackToWest_W" select="$stackToWest_W_"/> + <xsl:with-param name="iLaneInSpace_X" select="$laneInSpace_X_"/> + <xsl:with-param name="iSpaceSharedBus_Y" select="$spaceSharedBus_Y_"/> + </xsl:call-template> +<!-- +--> + </xsl:when> + +<!-- + =========================================================== + Handle non Processor Shared Bus connections. + =========================================================== +--> + <xsl:when test="@BUSLANE_X and @IS_SBSCONN and not(@IS_MPMCCONN) and BUSCONN[@BIF_Y and not(@IS_PROCCONN) and @INSTANCE and @BUSINTERFACE] and /EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $busName_)]/@BUS_INDEX"> + <xsl:call-template name="BCLaneSpace_NonProcBifToSharedBus"> + <xsl:with-param name="iBusStd" select="$busStd_"/> + <xsl:with-param name="iBusName" select="$busName_"/> + <xsl:with-param name="iBifType" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $busName_)]/BUSINTERFACE/@TYPE"/> + <xsl:with-param name="iStackToEast" select="$stackToEast_"/> + <xsl:with-param name="iStackToWest" select="$stackToWest_"/> + <xsl:with-param name="iStackToEast_W" select="$stackToEast_W_"/> + <xsl:with-param name="iStackToWest_W" select="$stackToWest_W_"/> + <xsl:with-param name="iLaneInSpace_X" select="$laneInSpace_X_"/> + <xsl:with-param name="iSpaceSharedBus_Y" select="$spaceSharedBus_Y_"/> + </xsl:call-template> +<!-- +--> + </xsl:when> + +<!-- + =========================================================== + Handle connections from processors to Memory UNITs + =========================================================== +--> + <xsl:when test="@BUSLANE_X and @IS_MEMCONN and not(@IS_MULTISTK) and BUSCONN[@BIF_Y and @IS_PROCCONN and not(@IS_SPLITCONN) and @INSTANCE and @BUSINTERFACE]"> + <xsl:call-template name="BCLaneSpace_ProcBifToMemoryUnit"> + <xsl:with-param name="iBusStd" select="$busStd_"/> + <xsl:with-param name="iBusName" select="$busName_"/> + <xsl:with-param name="iBifType" select="BUSCONN/@TYPE"/> + <xsl:with-param name="iStackToEast" select="$stackToEast_"/> + <xsl:with-param name="iStackToWest" select="$stackToWest_"/> + <xsl:with-param name="iStackToEast_W" select="$stackToEast_W_"/> + <xsl:with-param name="iStackToWest_W" select="$stackToWest_W_"/> + <xsl:with-param name="iLaneInSpace_X" select="$laneInSpace_X_"/> + </xsl:call-template> +<!-- +--> + </xsl:when> + + +<!-- + =========================================================== + Handle generic Point to Point connections + =========================================================== +--> + <xsl:when test="@BUSLANE_X and not(@IS_MULTISTK) and not(@IS_MPMCCONN) and not(@IS_MEMCONN) and not(@IS_SBSCONN) and BUSCONN[@BIF_Y and @INSTANCE and @BUSINTERFACE and not(@IS_SPLITCONN)]"> + <xsl:call-template name="BCLaneSpace_PointToPoint"> + <xsl:with-param name="iBusStd" select="$busStd_"/> + <xsl:with-param name="iBusName" select="$busName_"/> + <xsl:with-param name="iBifType" select="BUSCONN/@TYPE"/> + <xsl:with-param name="iStackToEast" select="$stackToEast_"/> + <xsl:with-param name="iStackToWest" select="$stackToWest_"/> + <xsl:with-param name="iStackToEast_W" select="$stackToEast_W_"/> + <xsl:with-param name="iStackToWest_W" select="$stackToWest_W_"/> + <xsl:with-param name="iLaneInSpace_X" select="$laneInSpace_X_"/> + </xsl:call-template> +<!-- +--> + </xsl:when> + +<!-- + =========================================================== + Handle MultiStack Point to Point connections + =========================================================== +--> + <xsl:when test="@BUSLANE_X and (@IS_MULTISTK) and not(@IS_SBSCONN) and BUSCONN[@BIF_Y and @IS_PROCCONN and @INSTANCE and @BUSINTERFACE]"> + <xsl:call-template name="BCLaneSpace_MultiStack_PointToPoint"> + <xsl:with-param name="iBusStd" select="$busStd_"/> + <xsl:with-param name="iBusName" select="$busName_"/> + <xsl:with-param name="iBifType" select="BUSCONN/@TYPE"/> + <xsl:with-param name="iStackToEast" select="$stackToEast_"/> + <xsl:with-param name="iStackToWest" select="$stackToWest_"/> + <xsl:with-param name="iStackToEast_W" select="$stackToEast_W_"/> + <xsl:with-param name="iStackToWest_W" select="$stackToWest_W_"/> + <xsl:with-param name="iLaneInSpace_X" select="$laneInSpace_X_"/> + </xsl:call-template> + </xsl:when> + +<!-- + =========================================================== + Handle Processor to processor connections + =========================================================== +--> +<!-- +--> + <xsl:when test="(@IS_PROC2PROC and (count(BUSCONN[@BIF_Y and @INSTANCE and @BUSINTERFACE]) = 2))"> + <xsl:call-template name="BCLaneSpace_ProcToProc"> + <xsl:with-param name="iBusStd" select="$busStd_"/> + <xsl:with-param name="iBusName" select="$busName_"/> + <xsl:with-param name="iBifType" select="BUSCONN/@TYPE"/> + <xsl:with-param name="iStackToEast" select="$stackToEast_"/> + <xsl:with-param name="iStackToWest" select="$stackToWest_"/> + <xsl:with-param name="iStackToEast_W" select="$stackToEast_W_"/> + <xsl:with-param name="iStackToWest_W" select="$stackToWest_W_"/> + <xsl:with-param name="iLaneInSpace_X" select="$laneInSpace_X_"/> + </xsl:call-template> + </xsl:when> + +<!-- + =========================================================== + Handle connections to the StandAlone MPMC + =========================================================== +--> + <xsl:when test="@BUSLANE_X and (@IS_MPMCCONN) and not(@IS_SBSCONN) and BUSCONN[(@BIF_Y and @INSTANCE and @BUSINTERFACE)]"> +<!-- +--> + <xsl:call-template name="BCLaneSpace_ToStandAloneMPMC"> + <xsl:with-param name="iBusStd" select="$busStd_"/> + <xsl:with-param name="iBusName" select="$busName_"/> + <xsl:with-param name="iBifType" select="BUSCONN/@TYPE"/> + <xsl:with-param name="iStackToEast" select="$stackToEast_"/> + <xsl:with-param name="iStackToWest" select="$stackToWest_"/> + <xsl:with-param name="iStackToEast_W" select="$stackToEast_W_"/> + <xsl:with-param name="iStackToWest_W" select="$stackToWest_W_"/> + <xsl:with-param name="iLaneInSpace_X" select="$laneInSpace_X_"/> + </xsl:call-template> + </xsl:when> + +<!-- + =========================================================== + Handle Split connections, (connections that go between non adjacent stacks) + =========================================================== +--> + <xsl:when test="(BUSCONN[@BIF_Y and @INSTANCE and @BUSINTERFACE and @IS_SPLITCONN])"> + <xsl:call-template name="BCLaneSpace_SplitConn"> + <xsl:with-param name="iBusStd" select="$busStd_"/> + <xsl:with-param name="iBusName" select="$busName_"/> + <xsl:with-param name="iBifType" select="BUSCONN/@TYPE"/> + <xsl:with-param name="iStackToEast" select="$stackToEast_"/> + <xsl:with-param name="iStackToWest" select="$stackToWest_"/> + <xsl:with-param name="iStackToEast_W" select="$stackToEast_W_"/> + <xsl:with-param name="iStackToWest_W" select="$stackToWest_W_"/> + <xsl:with-param name="iLaneInSpace_X" select="$laneInSpace_X_"/> + </xsl:call-template> +<!-- +--> + </xsl:when> + + </xsl:choose> + + </xsl:for-each> + </g> + +</xsl:template> + +<xsl:template name="Define_BusLaneSpaces"> + + <xsl:variable name="lastStack_" select="(/EDKSYSTEM/BLKDIAGRAM/@STACK_HORIZ_WIDTH) - 1"/> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE[@EAST]"> + <xsl:sort select="@EAST" data-type="number"/> + + <xsl:call-template name="Define_BusLaneSpace"> + <xsl:with-param name="iStackToEast" select="@EAST"/> + </xsl:call-template> + </xsl:for-each> + +<!-- + <xsl:message>Last Stack <xsl:value-of select="$lastStack_"/></xsl:message> +--> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE[(@WEST = $lastStack_)]"> + <xsl:call-template name="Define_BusLaneSpace"> + <xsl:with-param name="iStackToWest" select="$lastStack_"/> + </xsl:call-template> + </xsl:for-each> + +</xsl:template> + +</xsl:stylesheet>
\ No newline at end of file diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtTinySvgBLKD_Busses.xsl b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtTinySvgBLKD_Busses.xsl new file mode 100644 index 000000000..3fc2afe86 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtTinySvgBLKD_Busses.xsl @@ -0,0 +1,534 @@ +<?xml version="1.0" standalone="no"?> +<xsl:stylesheet version="1.0" + xmlns:svg="http://www.w3.org/2000/svg" + xmlns:xsl="http://www.w3.org/1999/XSL/Transform" + xmlns:exsl="http://exslt.org/common" + xmlns:xlink="http://www.w3.org/1999/xlink"> + +<xsl:output method="xml" version="1.0" encoding="UTF-8" indent="yes" + doctype-public="-//W3C//DTD SVG 1.0//EN" + doctype-system="http://www.w3.org/TR/SVG/DTD/svg10.dtd"/> + + + +<xsl:template name="Define_Busses"> +<!-- + <xsl:param name="drawarea_w" select="500"/> + <xsl:param name="drawarea_h" select="500"/> +--> + + <xsl:for-each select="exsl:node-set($COL_BUSSTDS)/BUSCOLOR"> + + <xsl:call-template name="Define_BusArrowsEastWest"> + <xsl:with-param name="iBusStd" select="@BUSSTD"/> + </xsl:call-template> + + <xsl:call-template name="Define_BusArrowsNorthSouth"> + <xsl:with-param name="iBusStd" select="@BUSSTD"/> + </xsl:call-template> + + <xsl:call-template name="Define_SplitBusses"> + <xsl:with-param name="iBusStd" select="@BUSSTD"/> + </xsl:call-template> + + </xsl:for-each> + + <xsl:call-template name="Define_SharedBus"> + <xsl:with-param name="iBusStd" select="'PLB'"/> + </xsl:call-template> + + <xsl:call-template name="Define_SharedBus"> + <xsl:with-param name="iBusStd" select="'PLBV46'"/> + </xsl:call-template> + + <xsl:call-template name="Define_SharedBus"> + <xsl:with-param name="iBusStd" select="'OPB'"/> + </xsl:call-template> + + <xsl:call-template name="Define_SharedBus_Group"/> + +</xsl:template> + +<xsl:template name="Define_BusArrowsEastWest"> + <xsl:param name="iBusStd" select="'PLB'"/> + + <xsl:variable name="busStdColor_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="$iBusStd"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="busStdColor_lt_"> + <xsl:call-template name="F_BusStd2RGB_LT"> + <xsl:with-param name="iBusStd" select="$iBusStd"/> + </xsl:call-template> + </xsl:variable> + + <g id="{$iBusStd}_BusArrowEast"> + <path class="bus" + d="M 0,0 + L {$BLKD_BUS_ARROW_W}, {ceiling($BLKD_BUS_ARROW_H div 2)} + L 0,{$BLKD_BUS_ARROW_H}, + Z" style="stroke:none; fill:{$busStdColor_}"/> + </g> + + <g id="{$iBusStd}_BusArrowWest"> + <use x="0" y="0" xlink:href="#{$iBusStd}_BusArrowEast" transform="scale(-1,1) translate({$BLKD_BUS_ARROW_W * -1},0)"/> + </g> + + <g id="{$iBusStd}_BusArrowHInitiator"> + <rect x="0" + y="{$BLKD_BUS_ARROW_G}" + width= "{$BLKD_BUS_ARROW_W}" + height="{$BLKD_P2P_BUS_W}" + style="stroke:none; fill:{$busStdColor_}"/> + </g> + +</xsl:template> + +<!-- + <xsl:param name="bus_col" select="'OPB'"/> +--> + +<xsl:template name="Define_BusArrowsNorthSouth"> + <xsl:param name="iBusStd" select="'PLB'"/> + + <xsl:variable name="busStdColor_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="$iBusStd"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="busStdColor_lt_"> + <xsl:call-template name="F_BusStd2RGB_LT"> + <xsl:with-param name="iBusStd" select="$iBusStd"/> + </xsl:call-template> + </xsl:variable> + + <g id="{$iBusStd}_BusArrowSouth"> + <path class="bus" + d="M 0,0 + L {$BLKD_BUS_ARROW_H},0 + L {ceiling($BLKD_BUS_ARROW_H div 2)}, {$BLKD_BUS_ARROW_W} + Z" style="stroke:none; fill:{$busStdColor_}"/> + </g> + + <g id="{$iBusStd}_BusArrowNorth"> + <use x="0" y="0" xlink:href="#{$iBusStd}_BusArrowSouth" transform="scale(1,-1) translate(0,{$BLKD_BUS_ARROW_H * -1})"/> + </g> + + <g id="{$iBusStd}_BusArrowInitiator"> + <rect x="{$BLKD_BUS_ARROW_G}" + y="0" + width= "{$BLKD_BUS_ARROW_W - ($BLKD_BUS_ARROW_G * 2)}" + height="{$BLKD_BUS_ARROW_H}" + style="stroke:none; fill:{$busStdColor_}"/> + </g> + +</xsl:template> + + +<xsl:template name="Draw_P2PBus"> + + <xsl:param name="iBusX" select="0"/> + <xsl:param name="iBusTop" select="0"/> + <xsl:param name="iBusBot" select="0"/> + <xsl:param name="iBusStd" select="'_bstd_'"/> + <xsl:param name="iBusName" select="'_p2pbus_'"/> + <xsl:param name="iBotBifType" select="'_unk_'"/> + <xsl:param name="iTopBifType" select="'_unk_'"/> + + <xsl:variable name="busStdColor_"> + <xsl:choose> + + <xsl:when test="@BUSSTD"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="@BUSSTD"/> + </xsl:call-template> + </xsl:when> + + <xsl:when test="not($iBusStd = '_bstd_')"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="$iBusStd"/> + </xsl:call-template> + </xsl:when> + + <xsl:otherwise> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="'TRS'"/> + </xsl:call-template> + </xsl:otherwise> + + </xsl:choose> + </xsl:variable> + + <xsl:variable name="p2pH_" select="($iBusBot - $iBusTop) - ($BLKD_BUS_ARROW_H * 2)"/> + + <xsl:variable name="botArrow_"> + <xsl:choose> + <xsl:when test="((($iBotBifType = 'INITIATOR') or ($iBotBifType = 'MASTER')) and ($iBusStd = 'FSL'))">BusArrowInitiator</xsl:when> + <xsl:otherwise>BusArrowSouth</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="topArrow_"> + <xsl:choose> + <xsl:when test="((($iTopBifType = 'INITIATOR') or ($iTopBifType = 'MASTER')) and ($iBusStd = 'FSL'))">BusArrowInitiator</xsl:when> + <xsl:otherwise>BusArrowNorth</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:if test="@BUSSTD"> + <use x="{($iBusX + ceiling($BLKD_BIFC_W div 2)) - ceiling($BLKD_BUS_ARROW_W div 2)}" + y="{$iBusTop + ($BLKD_BIFC_H - $BLKD_BUS_ARROW_H) + $BLKD_BUS_ARROW_H}" + xlink:href="#{@BUSSTD}_{$topArrow_}"/> + + <use x="{($iBusX + ceiling($BLKD_BIFC_W div 2)) - ceiling($BLKD_BUS_ARROW_W div 2)}" + y="{$iBusBot - $BLKD_BUS_ARROW_H}" + xlink:href="#{@BUSSTD}_{$botArrow_}"/> + </xsl:if> + + <xsl:if test="(not(@BUSSTD) and not($iBusStd = '_bstd_'))"> + <use x="{($iBusX + ceiling($BLKD_BIFC_W div 2)) - ceiling($BLKD_BUS_ARROW_W div 2)}" + y="{$iBusTop + ($BLKD_BIFC_H - $BLKD_BUS_ARROW_H) + $BLKD_BUS_ARROW_H}" + xlink:href="#{$iBusStd}_{$topArrow_}"/> + + <use x="{($iBusX + ceiling($BLKD_BIFC_W div 2)) - ceiling($BLKD_BUS_ARROW_W div 2)}" + y="{$iBusBot - $BLKD_BUS_ARROW_H}" + xlink:href="#{$iBusStd}_{$botArrow_}"/> + </xsl:if> + + + <rect x="{($iBusX + ceiling($BLKD_BIFC_W div 2)) - ceiling($BLKD_BUS_ARROW_W div 2) + $BLKD_BUS_ARROW_G}" + y="{$iBusTop + $BLKD_BIFC_H + $BLKD_BUS_ARROW_H}" + height= "{$p2pH_ - ($BLKD_BUS_ARROW_H * 2)}" + width="{$BLKD_BUS_ARROW_W - ($BLKD_BUS_ARROW_G * 2)}" + style="stroke:none; fill:{$busStdColor_}"/> + +<!-- + <text class="p2pbuslabel" + x="{$iBusX + $BLKD_BUS_ARROW_W + ceiling($BLKD_BUS_ARROW_W div 2) + ceiling($BLKD_BUS_ARROW_W div 4) + 4}" + y="{$iBusTop + ($BLKD_BUS_ARROW_H * 3)}"> + <xsl:value-of select="$iBusName"/> + </text> +--> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="($iBusX + $BLKD_BUS_ARROW_W + ceiling($BLKD_BUS_ARROW_W div 2) + ceiling($BLKD_BUS_ARROW_W div 4) + 4)"/> + <xsl:with-param name="iY" select="($iBusTop + ($BLKD_BUS_ARROW_H * 3))"/> + <xsl:with-param name="iText" select="$iBusName"/> + <xsl:with-param name="iClass" select="'p2pbus_label'"/> + </xsl:call-template> + + <xsl:if test="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iBusName)]/@GROUP"> +<!-- + <text class="ioplblgrp" + x="{$iBusX + $BLKD_BUS_ARROW_W + ceiling($BLKD_BUS_ARROW_W div 2) + ceiling($BLKD_BUS_ARROW_W div 4) + 6}" + y="{$iBusTop + ($BLKD_BUS_ARROW_H * 10)}"> + <xsl:value-of select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iBusName)]/@GROUP"/> + </text> +--> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="(iBusX + $BLKD_BUS_ARROW_W + ceiling($BLKD_BUS_ARROW_W div 2) + ceiling($BLKD_BUS_ARROW_W div 4) + 6)"/> + <xsl:with-param name="iY" select="($iBusTop + ($BLKD_BUS_ARROW_H * 10))"/> + <xsl:with-param name="iText" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iBusName)]/@GROUP"/> + <xsl:with-param name="iClass" select="'iogrp_label'"/> + </xsl:call-template> + + </xsl:if> + +</xsl:template> + + +<xsl:template name="Draw_Proc2ProcBus"> + + <xsl:param name="iBc_Y" select="0"/> + <xsl:param name="iBusStd" select="'_bstd_'"/> + <xsl:param name="iBusName" select="'_p2pbus_'"/> + <xsl:param name="iBcLeft_X" select="0"/> + <xsl:param name="iBcRght_X" select="0"/> + <xsl:param name="iLeftBifType" select="'_unk_'"/> + <xsl:param name="iRghtBifType" select="'_unk_'"/> + + <xsl:variable name="busStdColor_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="$iBusStd"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="pr2pr_W_" select="($iBcRght_X - $iBcLeft_X)"/> + + <xsl:variable name="leftArrow_"> + <xsl:choose> + <xsl:when test="((($iLeftBifType = 'INITIATOR') or ($iLeftBifType = 'MASTER')) and ($iBusStd = 'FSL'))">BusArrowHInitiator</xsl:when> + <xsl:otherwise>BusArrowWest</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="rghtArrow_"> + <xsl:choose> + <xsl:when test="((($iRghtBifType = 'INITIATOR') or ($iRghtBifType = 'MASTER')) and ($iBusStd = 'FSL'))">BusArrowHInitiator</xsl:when> + <xsl:otherwise>BusArrowEast</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + + <xsl:variable name="bus_Y_" select="($iBc_Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_BUS_ARROW_H div 2))"/> + + <use x="{$iBcLeft_X}" y="{$bus_Y_}" xlink:href="#{$iBusStd}_{$leftArrow_}"/> + <use x="{$iBcRght_X - $BLKD_BUS_ARROW_W}" y="{$bus_Y_}" xlink:href="#{$iBusStd}_{$rghtArrow_}"/> + + <rect x="{$iBcLeft_X + $BLKD_BUS_ARROW_W}" + y="{$bus_Y_ + $BLKD_BUS_ARROW_G}" + width= "{$pr2pr_W_ - (2 * $BLKD_BUS_ARROW_W)}" + height="{$BLKD_BUS_ARROW_H - (2 * $BLKD_BUS_ARROW_G)}" style="stroke:none; fill:{$busStdColor_}"/> + +<!-- + <text class="horizp2pbuslabel" + x="{$iBcLeft_X + $BLKD_BUS_ARROW_W + ceiling($BLKD_BUS_ARROW_W div 2) + ceiling($BLKD_BUS_ARROW_W div 4) + 4}" + y="{($bus_Y_)}"><xsl:value-of select="$iBusName"/></text> + + <text class="horizp2pbuslabel" + x="{$iBcRght_X - (string-length($iBusName) * 8)}" + y="{($bus_Y_)}"><xsl:value-of select="$iBusName"/></text> +--> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="($iBcLeft_X + $BLKD_BUS_ARROW_W + ceiling($BLKD_BUS_ARROW_W div 2) + ceiling($BLKD_BUS_ARROW_W div 4) + 4)"/> + <xsl:with-param name="iY" select="$bus_Y_"/> + <xsl:with-param name="iText" select="$iBusName"/> + <xsl:with-param name="iClass" select="'p2pbus_label'"/> + </xsl:call-template> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="(iBcRght_X - (string-length($iBusName) * 8))"/> + <xsl:with-param name="iY" select="$bus_Y_"/> + <xsl:with-param name="iText" select="$iBusName"/> + <xsl:with-param name="iClass" select="'p2pbus_label'"/> + </xsl:call-template> + +</xsl:template> + + +<xsl:template name="Draw_SplitConnBus"> + + <xsl:param name="iBc_X" select="0"/> + <xsl:param name="iBc_Y" select="0"/> + <xsl:param name="iBc_Type" select="'_unk_'"/> + <xsl:param name="iBc_Side" select="'_unk_'"/> + <xsl:param name="iBusStd" select="'_bstd_'"/> + <xsl:param name="iBusName" select="'_p2pbus_'"/> + + <xsl:variable name="busStdColor_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="$iBusStd"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="connArrow_"> + <xsl:choose> + <xsl:when test="((($iBc_Type = 'INITIATOR') or ($iBc_Type = 'MASTER')) and ($iBusStd = 'FSL'))">BusArrowHInitiator</xsl:when> + <xsl:otherwise>BusArrowEast</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="arrow_Y_" select="($iBc_Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_BUS_ARROW_H div 2))"/> + + <xsl:variable name="bus_X_"> + <xsl:choose> + <xsl:when test="$iBc_Side = '0'"><xsl:value-of select="($iBc_X - ($BLKD_BUS_ARROW_W * 2))"/></xsl:when> + <xsl:when test="$iBc_Side = '1'"><xsl:value-of select="($iBc_X + $BLKD_BIFC_W + $BLKD_BUS_ARROW_W)"/></xsl:when> + </xsl:choose> + </xsl:variable> + +<!-- + <use x="{$bus_X_}" y="{$arrow_Y_}" xlink:href="#{$busStd}_BusArrowHInitiator"/> +--> + + <xsl:variable name="arrow_X_"> + <xsl:choose> + <xsl:when test="$iBc_Side = '0'"><xsl:value-of select="($iBc_X - $BLKD_BUS_ARROW_W)"/></xsl:when> + <xsl:when test="$iBc_Side = '1'"><xsl:value-of select="($iBc_X + $BLKD_BIFC_W)"/></xsl:when> + </xsl:choose> + </xsl:variable> + <xsl:choose> + <xsl:when test="(($iBusStd = 'FSL') and (($iBc_Type = 'MASTER') or ($iBc_Type = 'INITIATOR')))"> + <use x="{$arrow_X_}" y="{$arrow_Y_}" xlink:href="#{$iBusStd}_{$connArrow_}"/> + <use x="{$bus_X_}" y="{$arrow_Y_}" xlink:href="#{$iBusStd}_BusArrowHInitiator"/> + </xsl:when> + <xsl:when test="(($iBc_Side = '1') and not($iBusStd = 'FSL') and (($iBc_Type = 'MASTER') or ($iBc_Type = 'INITIATOR')))"> + <use x="{$arrow_X_ - $BLKD_BIFC_W}" y="{$arrow_Y_}" xlink:href="#{$iBusStd}_SplitBus_WEST"/> + </xsl:when> + <xsl:when test="(($iBc_Side = '1') and (($iBc_Type = 'SLAVE') or ($iBc_Type = 'TARGET') or ($iBc_Type = 'USER')))"> + <use x="{$arrow_X_}" y="{$arrow_Y_}" xlink:href="#{$iBusStd}_SplitBus_EAST"/> + </xsl:when> + <xsl:otherwise> + <use x="{$arrow_X_}" y="{$arrow_Y_}" xlink:href="#{$iBusStd}_{$connArrow_}"/> + <use x="{$bus_X_}" y="{$arrow_Y_}" xlink:href="#{$iBusStd}_BusArrowHInitiator"/> + </xsl:otherwise> + </xsl:choose> + + <xsl:variable name="text_X_"> + <xsl:choose> + <xsl:when test="$iBc_Side = '0'"><xsl:value-of select="($bus_X_ - $BLKD_BUS_ARROW_W - (string-length($iBusName) * 5))"/></xsl:when> + <xsl:when test="$iBc_Side = '1'"><xsl:value-of select="($bus_X_ + $BLKD_BUS_ARROW_W)"/></xsl:when> + </xsl:choose> + </xsl:variable> + + +<!-- + <text class="horizp2pbuslabel" + x="{$text_X_}" + y="{($arrow_Y_)}"> + <xsl:value-of select="$iBusName"/> + </text> +--> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="$text_X_"/> + <xsl:with-param name="iY" select="$arrow_Y_"/> + <xsl:with-param name="iText" select="$iBusName"/> + <xsl:with-param name="iClass" select="'p2pbus_label'"/> + </xsl:call-template> + +</xsl:template> + + +<xsl:template name="Define_SharedBus"> + + <xsl:param name="iBusStd" select="'PLB46'"/> + + <xsl:variable name="sharedbus_w_" select="($G_Total_DrawArea_W - ($BLKD_INNER_GAP * 2))"/> + + <xsl:variable name="busStdColor_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="$iBusStd"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="busStdColor_lt_"> + <xsl:call-template name="F_BusStd2RGB_LT"> + <xsl:with-param name="iBusStd" select="$iBusStd"/> + </xsl:call-template> + </xsl:variable> + + <g id="{$iBusStd}_SharedBus"> + <use x="0" y="0" xlink:href="#{$iBusStd}_BusArrowWest"/> + <use x="{$sharedbus_w_ - $BLKD_BUS_ARROW_W}" y="0" xlink:href="#{$iBusStd}_BusArrowEast"/> + + <rect x="{$BLKD_BUS_ARROW_W}" + y="{$BLKD_BUS_ARROW_G}" + width= "{$sharedbus_w_ - ($BLKD_BUS_ARROW_W * 2)}" + height="{$BLKD_BUS_ARROW_H - (2 * $BLKD_BUS_ARROW_G)}" style="stroke:none; fill:{$busStdColor_}"/> + </g> +</xsl:template> + + +<xsl:template name="Define_SplitBusses"> + + <xsl:param name="iBusStd" select="'FSL'"/> + + <xsl:variable name="busStdColor_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="$iBusStd"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="bifc_r_" select="ceiling($BLKD_BIFC_W div 3)"/> + + <g id="{$iBusStd}_SplitBus_EAST"> + <use x="0" y="0" xlink:href="#{$iBusStd}_BusArrowWest"/> + + <rect x="{$BLKD_BUS_ARROW_W}" + y="{$BLKD_BUS_ARROW_G}" + width= "{$BLKD_BIFC_W}" + height="{$BLKD_BUS_ARROW_H - (2 * $BLKD_BUS_ARROW_G)}" style="stroke:none; fill:{$busStdColor_}"/> + + </g> + + <xsl:variable name="splbus_w_" select="($BLKD_BUS_ARROW_W + $BLKD_BIFC_W + $BLKD_BIFC_Wi)"/> + + <g id="{$iBusStd}_SplitBus_WEST"> + <use x="0" y="0" xlink:href="#{$iBusStd}_SplitBus_EAST" transform="scale(-1,1) translate({$splbus_w_ * -1},0)"/> + </g> + + <g id="{$iBusStd}_SplitBus_OneWay"> + + <rect x="0" + y="{$BLKD_BUS_ARROW_G}" + width= "{($BLKD_BUS_ARROW_W * 2)}" + height="{$BLKD_BUS_ARROW_H - (2 * $BLKD_BUS_ARROW_G)}" style="stroke:none; fill:{$busStdColor_}"/> + + <rect x="{($BLKD_BUS_ARROW_W * 2)}" + y="0" + width= "{$BLKD_BUS_ARROW_H}" + height="{$BLKD_BUS_ARROW_H}" style="stroke:none; fill:{$busStdColor_}"/> + + </g> +</xsl:template> + + +<xsl:template name="Define_SharedBus_Group"> + +<!-- The Bridges go into the shared bus shape --> + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BRIDGESHAPES/MODULE"> + + <xsl:variable name="modInst_" select="@INSTANCE"/> + <xsl:variable name="modType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $modInst_)]/@MODTYPE"/> + + <xsl:call-template name="Define_Peripheral"> + <xsl:with-param name="iModVori" select="'normal'"/> + <xsl:with-param name="iModInst" select="$modInst_"/> + <xsl:with-param name="iModType" select="$modType_"/> + </xsl:call-template> + + </xsl:for-each> + +<g id="group_sharedBusses"> + + <!-- Draw the shared bus shapes first --> + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSSHAPES/MODULE"> + <xsl:variable name="instance_" select="@INSTANCE"/> + + <xsl:variable name="busStd_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $instance_)]/@BUSSTD"/> + <xsl:variable name="busIndex_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $instance_)]/@BUS_INDEX"/> + + <xsl:variable name="busY_" select="($busIndex_ * $BLKD_SBS_LANE_H)"/> + + <use x="0" y="{$busY_}" xlink:href="#{$busStd_}_SharedBus"/> + +<!-- + <text class="sharedbuslabel" + x="8" + y="{$busY_ + $BLKD_BUS_ARROW_H + 10}"> + <xsl:value-of select="$instance_"/> + </text> +--> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="'8'"/> + <xsl:with-param name="iY" select="($busY_ + $BLKD_BUS_ARROW_H + 10)"/> + <xsl:with-param name="iText" select="$instance_"/> + <xsl:with-param name="iClass" select="'sharedbus_label'"/> + </xsl:call-template> + </xsl:for-each> + +</g> + +<g id="KEY_SharedBus"> + <use x="0" y="0" xlink:href="#KEY_BusArrowWest"/> + <use x="30" y="0" xlink:href="#KEY_BusArrowEast"/> + + <xsl:variable name="key_col_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="'KEY'"/> + </xsl:call-template> + </xsl:variable> + + <rect x="{$BLKD_BUS_ARROW_W}" + y="{$BLKD_BUS_ARROW_G}" + width= "{30 - $BLKD_BUS_ARROW_W}" + height="{$BLKD_BUS_ARROW_H - (2 * $BLKD_BUS_ARROW_G)}" style="stroke:none; fill:{$key_col_}"/> +</g> + +</xsl:template> + +</xsl:stylesheet> diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtTinySvgBLKD_Functions.xsl b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtTinySvgBLKD_Functions.xsl new file mode 100644 index 000000000..b91a5790e --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtTinySvgBLKD_Functions.xsl @@ -0,0 +1,1110 @@ +<?xml version="1.0" standalone="no"?> + +<xsl:stylesheet version="1.0" + xmlns:svg="http://www.w3.org/2000/svg" + xmlns:xsl="http://www.w3.org/1999/XSL/Transform" + xmlns:math="http://exslt.org/math" + xmlns:exsl="http://exslt.org/common" + xmlns:xlink="http://www.w3.org/1999/xlink" + extension-element-prefixes="math"> + +<xsl:output method="xml" version="1.0" encoding="UTF-8" indent="yes" + doctype-public="-//W3C//DTD SVG 1.0//EN" + doctype-system="http://www.w3.org/TR/SVG/DTD/svg10.dtd"/> + +<xsl:template name="F_Calc_Proc_Height"> + <xsl:param name="iProcInst" select="_processor_"/> + + <xsl:variable name="tot_bifs_h_"> + <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $iProcInst)]/@BIFS_H)">0</xsl:if> + + <xsl:if test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $iProcInst)]/@BIFS_H"> + <xsl:variable name="bifs_h_" select="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $iProcInst)]/@BIFS_H)"/> + <xsl:value-of select="(($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_H) * $bifs_h_)"/> + </xsl:if> + </xsl:variable> + + <xsl:value-of select="(($BLKD_MOD_LANE_H * 2) + $tot_bifs_h_ + ($BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_H))"/> +</xsl:template> + +<xsl:template name="F_Calc_Max_Proc_Height"> + + <!-- Store the heights in a variable --> + <xsl:variable name="proc_heights_"> + + <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE)"> + <PROC HEIGHT="0"/> + </xsl:if> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE"> + <xsl:variable name="procInst_" select="@INSTANCE"/> + <xsl:variable name="proc_height_"> + <xsl:call-template name="F_Calc_Proc_Height"> + <xsl:with-param name="iProcInst" select="$procInst_"/> + </xsl:call-template> + </xsl:variable> + +<!-- + <xsl:message>Found Proc height as <xsl:value-of select="$proc_height_"/></xsl:message> +--> + <PROC HEIGHT="{$proc_height_}"/> + </xsl:for-each> + </xsl:variable> + + <!-- Return the max of them --> +<!-- + <xsl:message>Found Proc ax as <xsl:value-of select="math:max(exsl:node-set($proc_heights_)/PROC/@HEIGHT)"/></xsl:message> +--> + + <xsl:value-of select="math:max(exsl:node-set($proc_heights_)/PROC/@HEIGHT)"/> +</xsl:template> + + +<xsl:template name="F_Calc_Proc_MemoryUnits_Height"> + <xsl:param name="iProcInst" select="_processor_"/> + + <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@PROCESSOR = $iProcInst) and (@MODCLASS = 'MEMORY_UNIT'))])">0</xsl:if> + + <xsl:if test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@PROCESSOR = $iProcInst) and (@MODCLASS='MEMORY_UNIT'))]"> + + <xsl:variable name="peri_gap_"> + <xsl:choose> + <xsl:when test="not(@CSTACK_INDEX)"> + <xsl:value-of select="$BLKD_BIF_H"/> + </xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + + <!-- Store the all memory unit heights in a variable --> + <xsl:variable name="memU_heights_"> + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@PROCESSOR = $iProcInst) and (@MODCLASS='MEMORY_UNIT'))]"> +<!-- + <xsl:variable name="unitId_" select="@PSTACK_MODS_Y"/> +--> + <xsl:variable name="unitHeight_"> + <xsl:call-template name="F_Calc_MemoryUnit_Height"> + <xsl:with-param name="iShapeId" select="@SHAPE_ID"/> + </xsl:call-template> + </xsl:variable> + + <MEM_UNIT HEIGHT="{$unitHeight_ + $peri_gap_}"/> + </xsl:for-each> + </xsl:variable> + + <xsl:value-of select="sum(exsl:node-set($memU_heights_)/MEM_UNIT/@HEIGHT)"/> + </xsl:if> +</xsl:template> + + +<xsl:template name="F_Calc_Proc_Peripherals_Height"> + <xsl:param name="iProcInst" select="_processor_"/> + + <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@PROCESSOR = $iProcInst) and not(@MODCLASS = 'MEMORY_UNIT'))])">0</xsl:if> + + <xsl:if test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@PROCESSOR = $iProcInst) and not(@MODCLASS='MEMORY_UNIT'))]"> + + <xsl:variable name="peri_gap_"> + <xsl:if test="@CSTACK_INDEX"> + <xsl:value-of select="$BLKD_BIF_H"/> + </xsl:if> + <xsl:if test="not(@IS_CSTACK)">0</xsl:if> + </xsl:variable> + + <!-- Store the all peripheral heights in a variable --> + <xsl:variable name="peri_heights_"> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@PROCESSOR = $iProcInst) and not(@MODCLASS='MEMORY_UNIT'))]"> + <xsl:for-each select="MODULE"> +<!-- + <xsl:message><xsl:value-of select="@INSTANCE"/></xsl:message> +--> + <xsl:variable name="peri_height_"> + <xsl:call-template name="F_Calc_PeriShape_Height"> + <xsl:with-param name="iShapeInst" select="@INSTANCE"/> + </xsl:call-template> + </xsl:variable> + <PERI HEIGHT="{$peri_height_ + $peri_gap_}"/> + </xsl:for-each> + </xsl:for-each> + </xsl:variable> + + <xsl:value-of select="sum(exsl:node-set($peri_heights_)/PERI/@HEIGHT)"/> + </xsl:if> +</xsl:template> + + +<xsl:template name="F_Calc_Space_AbvSbs_Height"> + <xsl:param name="iStackToEast" select="'NONE'"/> + <xsl:param name="iStackToWest" select="'NONE'"/> + + + <xsl:variable name = "stackAbvSbs_West_H_"> + <xsl:choose> + <xsl:when test="(($iStackToEast = '0') and ($iStackToWest = 'NONE'))">0</xsl:when> + <xsl:when test="(($iStackToEast = 'NONE') and not($iStackToWest = 'NONE'))"> + <xsl:call-template name="F_Calc_Stack_AbvSbs_Height"> + <xsl:with-param name="iStackIdx" select="$iStackToWest"/> + </xsl:call-template> + </xsl:when> + <xsl:when test="(not($iStackToEast = '0') and ($iStackToWest = 'NONE'))"> + <xsl:call-template name="F_Calc_Stack_AbvSbs_Height"> + <xsl:with-param name="iStackIdx" select="($iStackToEast - 1)"/> + </xsl:call-template> + </xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name = "stackAbvSbs_East_H_"> + <xsl:call-template name="F_Calc_Stack_AbvSbs_Height"> + <xsl:with-param name="iStackIdx" select="$iStackToEast"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="stackAbvSbs_heights_"> + <STACK HEIGHT="{$stackAbvSbs_East_H_}"/> + <STACK HEIGHT="{$stackAbvSbs_West_H_}"/> + </xsl:variable> + + <xsl:value-of select="math:max(exsl:node-set($stackAbvSbs_heights_)/STACK/@HEIGHT)"/> +</xsl:template> + + +<xsl:template name="F_Calc_Space_BlwSbs_Height"> + <xsl:param name="iStackToEast" select="'NONE'"/> + <xsl:param name="iStackToWest" select="'NONE'"/> + + <xsl:variable name = "stackBlwSbs_West_H_"> + <xsl:choose> + <xsl:when test="(($iStackToEast = '0') and ($iStackToWest = 'NONE'))">0</xsl:when> + <xsl:when test="(($iStackToEast = 'NONE') and not($iStackToWest = 'NONE'))"> + <xsl:call-template name="F_Calc_Stack_BlwSbs_Height"> + <xsl:with-param name="iStackIdx" select="$iStackToWest"/> + </xsl:call-template> + </xsl:when> + <xsl:when test="(not($iStackToEast = '0') and ($iStackToWest = 'NONE'))"> + <xsl:call-template name="F_Calc_Stack_BlwSbs_Height"> + <xsl:with-param name="iStackIdx" select="($iStackToEast - 1)"/> + </xsl:call-template> + </xsl:when> + </xsl:choose> + </xsl:variable> + + + <xsl:variable name = "stackBlwSbs_East_H_"> + <xsl:call-template name="F_Calc_Stack_BlwSbs_Height"> + <xsl:with-param name="iStackIdx" select="$iStackToEast"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="stackBlwSbs_heights_"> + <STACK HEIGHT="{$stackBlwSbs_East_H_}"/> + <STACK HEIGHT="{$stackBlwSbs_West_H_}"/> + </xsl:variable> + + <xsl:value-of select="math:max(exsl:node-set($stackBlwSbs_heights_)/STACK/@HEIGHT)"/> +</xsl:template> + + + +<xsl:template name="F_Calc_Stack_AbvSbs_Height"> + <xsl:param name="iStackIdx" select="100"/> +<!-- + <xsl:message>^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^</xsl:message> +--> + + <xsl:if test="(not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@STACK_HORIZ_INDEX = $iStackIdx) and (@IS_ABVSBS))]) and + not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@STACK_HORIZ_INDEX = $iStackIdx)]))"><xsl:value-of select="$BLKD_PROC2SBS_GAP"/></xsl:if> + + <xsl:if test="(($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@STACK_HORIZ_INDEX = $iStackIdx) and (@IS_ABVSBS))]) or + ($G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[ (@STACK_HORIZ_INDEX = $iStackIdx)]))"> + +<!-- + <xsl:variable name="peri_gap_"> + <xsl:value-of select="$BLKD_BIF_H"/> + <xsl:choose> + <xsl:when test="(@SHAPE_VERTI_INDEX)"> + </xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + </xsl:variable> +--> + +<!-- + <xsl:message>The gap is <xsl:value-of select="$peri_gap_"/></xsl:message> + <xsl:message>The gap is <xsl:value-of select="$peri_gap_"/></xsl:message> + <xsl:message>================================</xsl:message> + <xsl:message>================================</xsl:message> + <xsl:message>This is above <xsl:value-of select="@INSTANCE"/></xsl:message> + <xsl:message><xsl:value-of select="@INSTANCE"/> : <xsl:value-of select="$peri_height_"/></xsl:message> +--> + + + <!-- Store the all peripheral heights in a variable --> + <xsl:variable name="peri_heights_"> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@STACK_HORIZ_INDEX = $iStackIdx) and not(@MODCLASS = 'MEMORY_UNIT') and (@IS_ABVSBS))]"> + <xsl:for-each select="MODULE"> +<!-- + <xsl:message>This is above <xsl:value-of select="@INSTANCE"/></xsl:message> +--> + + <xsl:variable name="peri_height_"> +<!-- + <xsl:call-template name="F_Calc_Shape_Height"> + <xsl:with-param name="shapeId" select="@SHAPE_ID"/> + </xsl:call-template> +--> + + <xsl:call-template name="F_Calc_PeriShape_Height"> + <xsl:with-param name="iShapeInst" select="@INSTANCE"/> + </xsl:call-template> + </xsl:variable> + + <PERI HEIGHT="{$peri_height_ + $BLKD_BIF_H}"/> + </xsl:for-each> + </xsl:for-each> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@STACK_HORIZ_INDEX = $iStackIdx) and (@MODCLASS = 'MEMORY_UNIT') and (@IS_ABVSBS))]"> + + <xsl:variable name="memu_height_"> + <xsl:call-template name="F_Calc_MemoryUnit_Height"> + <xsl:with-param name="iShapeId" select="@SHAPE_ID"/> + </xsl:call-template> + </xsl:variable> + +<!-- + <xsl:message>Mem_Unit : <xsl:value-of select="@SHAPE_ID"/> : <xsl:value-of select="$memu_height_ + $peri_gap_"/></xsl:message> +--> + <PERI HEIGHT="{$memu_height_ + $BLKD_BIF_H}"/> + + </xsl:for-each> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[((@STACK_HORIZ_INDEX = $iStackIdx) and (@IS_ABVSBS))]"> + + <xsl:variable name="proc_height_"> + <xsl:call-template name="F_Calc_PeriShape_Height"> + <xsl:with-param name="iShapeInst" select="@INSTANCE"/> + </xsl:call-template> + </xsl:variable> + +<!-- + <xsl:message>===================================</xsl:message> + <xsl:message>Processor : <xsl:value-of select="@INSTANCE"/> : <xsl:value-of select="$peri_height_ + $peri_gap_"/></xsl:message> + <PERI HEIGHT="{$proc_height_ + $BLKD_PROC2SBS_GAP }"/> +--> + <PERI HEIGHT="{$proc_height_ + $BLKD_BIF_H}"/> + + </xsl:for-each> + + </xsl:variable> + +<!-- + <xsl:message><xsl:value-of select="@INSTANCE"/> : <xsl:value-of select="$peri_height_ + $peri_gap_"/></xsl:message> + <xsl:message>================================</xsl:message> +--> + +<!-- + <xsl:message>^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^</xsl:message> +--> + <xsl:value-of select="sum(exsl:node-set($peri_heights_)/PERI/@HEIGHT)"/> + </xsl:if> + +</xsl:template> + +<xsl:template name="F_Calc_Stack_BlwSbs_Height"> + <xsl:param name="iStackIdx" select="100"/> + + <!-- Store the all peripheral heights in a variable --> + <xsl:variable name="stack_heights_"> + + <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@STACK_HORIZ_INDEX = $iStackIdx) and (@IS_BLWSBS))])"> + <STACKSHAPE HEIGHT="0"/> + </xsl:if> + + <xsl:if test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@STACK_HORIZ_INDEX = $iStackIdx) and (@IS_BLWSBS))]"> + + <xsl:variable name="peri_gap_"> + <xsl:choose> + <xsl:when test="(@SHAPE_VERTI_INDEX)"> + <xsl:value-of select="$BLKD_BIF_H"/> + </xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@STACK_HORIZ_INDEX = $iStackIdx) and not(@MODCLASS = 'MEMORY_UNIT') and (@IS_BLWSBS))]"> + <xsl:for-each select="MODULE"> +<!-- + <xsl:message>This is below <xsl:value-of select="@INSTANCE"/></xsl:message> +--> + <xsl:variable name="peri_height_"> + <xsl:call-template name="F_Calc_PeriShape_Height"> + <xsl:with-param name="iShapeInst" select="@INSTANCE"/> + </xsl:call-template> + </xsl:variable> + + <STACKSHAPE HEIGHT="{$peri_height_ + $peri_gap_}"/> + </xsl:for-each> + </xsl:for-each> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@STACK_HORIZ_INDEX = $iStackIdx) and (@MODCLASS = 'MEMORY_UNIT') and (@IS_BLWSBS))]"> + + <xsl:variable name="memu_height_"> + <xsl:call-template name="F_Calc_MemoryUnit_Height"> + <xsl:with-param name="iShapeId" select="@SHAPE_ID"/> + </xsl:call-template> + </xsl:variable> + + <STACKSHAPE HEIGHT="{$memu_height_ + $peri_gap_}"/> + +<!-- + <xsl:message>Mem_Unit : <xsl:value-of select="@SHAPE_ID"/> : <xsl:value-of select="$memu_height_ + $peri_gap_"/></xsl:message> +--> + + </xsl:for-each> + </xsl:if> + + <xsl:variable name="sbsBuckets_H_"> + <xsl:call-template name="F_Calc_Stack_SbsBuckets_Height"> + <xsl:with-param name="iStackIdx" select="$iStackIdx"/> + </xsl:call-template> + </xsl:variable> + + <STACKSHAPE HEIGHT="{$sbsBuckets_H_}"/> +<!-- + <xsl:message>Sbs Bucket H : <xsl:value-of select="$sbsBuckets_H_"/></xsl:message> +--> + </xsl:variable> + +<!-- + <xsl:message>vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv</xsl:message> +--> + <xsl:value-of select="sum(exsl:node-set($stack_heights_)/STACKSHAPE/@HEIGHT)"/> + +</xsl:template> + + +<xsl:template name="F_Calc_Stack_SbsBuckets_Height"> + <xsl:param name="iStackIdx" select="1000"/> + + <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET[(@STACK_HORIZ_INDEX = $iStackIdx)])">0</xsl:if> + + <xsl:if test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET[(@STACK_HORIZ_INDEX = $iStackIdx)]"> + + <!-- Store the all buckets heights in a variable --> + <xsl:variable name="bkt_heights_"> + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET[(@STACK_HORIZ_INDEX = $iStackIdx)]"> + + <xsl:variable name="bkt_height_"> + <xsl:call-template name="F_Calc_SbsBucket_Height"> + <xsl:with-param name="iBucketId" select="@BUS_INDEX"/> + </xsl:call-template> + </xsl:variable> +<!-- + <xsl:message>Found shared buckets height as <xsl:value-of select="$bkt_height_"/></xsl:message> +--> + <BKT HEIGHT="{$bkt_height_ + $BLKD_BIF_H}"/> + </xsl:for-each> + </xsl:variable> + + <xsl:value-of select="sum(exsl:node-set($bkt_heights_)/BKT/@HEIGHT)"/> + </xsl:if> +</xsl:template> + + +<xsl:template name="F_Calc_Max_Stack_BlwSbs_Height"> + + <!-- Store the heights in a variable --> + <xsl:variable name="blwSbs_heights_"> + + <!-- Default, in case there are no modules or ports --> + <BLW HEIGHT="0"/> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE[(@EAST < $G_ROOT/EDKSYSTEM/BLKDIAGRAM/@STACK_HORIZ_WIDTH)]"> + +<!-- + <xsl:message>Found a space of index <xsl:value-of select="@EAST"/></xsl:message> +--> + + <xsl:variable name="stack_height_"> + <xsl:call-template name="F_Calc_Stack_BlwSbs_Height"> + <xsl:with-param name="iStackIdx" select="@EAST"/> + </xsl:call-template> + </xsl:variable> + + + <BLW HEIGHT="{$stack_height_}"/> + + </xsl:for-each> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE[(@WEST = ($G_ROOT/EDKSYSTEM/BLKDIAGRAM/@STACK_HORIZ_WIDTH -1))]"> + +<!-- + <xsl:message>Last stack of index <xsl:value-of select="@WEST"/></xsl:message> +--> + + <xsl:variable name="stack_height_"> + <xsl:call-template name="F_Calc_Stack_BlwSbs_Height"> + <xsl:with-param name="iStackIdx" select="@WEST"/> + </xsl:call-template> + </xsl:variable> + + + <BLW HEIGHT="{$stack_height_}"/> + + </xsl:for-each> + + + </xsl:variable> + +<!-- + <xsl:message>Found Blw Sbs max as <xsl:value-of select="math:max(exsl:node-set($blwSbs_heights_)/BLW/@HEIGHT)"/></xsl:message> +--> + <!-- Return the max of them --> + <xsl:value-of select="math:max(exsl:node-set($blwSbs_heights_)/BLW/@HEIGHT)"/> +</xsl:template> + + +<xsl:template name="F_Calc_Max_Stack_AbvSbs_Height"> + + <!-- Store the heights in a variable --> + <xsl:variable name="abvSbs_heights_"> + + <!-- Default, in case there are no modules or ports --> + <ABV HEIGHT="0"/> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE[(@EAST < $G_ROOT/EDKSYSTEM/BLKDIAGRAM/@STACK_HORIZ_WIDTH)]"> + +<!-- + <xsl:message>Found a space of index <xsl:value-of select="@EAST"/></xsl:message> +--> + + <xsl:variable name="stack_height_"> + <xsl:call-template name="F_Calc_Stack_AbvSbs_Height"> + <xsl:with-param name="iStackIdx" select="@EAST"/> + </xsl:call-template> + </xsl:variable> + +<!-- + <xsl:message>Found stack of width <xsl:value-of select="$stack_width_"/></xsl:message> + <xsl:message>==============================</xsl:message> +--> + + <ABV HEIGHT="{$stack_height_}"/> + + </xsl:for-each> + + + </xsl:variable> + +<!-- + <xsl:message>Found Blw Sbs max as <xsl:value-of select="math:max(exsl:node-set($blwSbs_heights_)/BLW/@HEIGHT)"/></xsl:message> +--> + <!-- Return the max of them --> + <xsl:value-of select="math:max(exsl:node-set($abvSbs_heights_)/ABV/@HEIGHT)"/> +</xsl:template> + + +<xsl:template name="F_Calc_MultiProc_Stack_Height"> + <xsl:param name="iMPStack_Blkd_X" select="100"/> + + <xsl:variable name="mpStk_ShpHeights_"> + <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@HAS_MULTIPROCCONNS) and (@PSTACK_BLKD_X = $iMPStack_Blkd_X))])"> + <MPSHAPE HEIGHT="0"/> + </xsl:if> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@HAS_MULTIPROCCONNS) and (@PSTACK_BLKD_X = $iMPStack_Blkd_X))]"> + <xsl:variable name="shpClass_" select="@MODCLASS"/> + <xsl:variable name="shpHeight_"> + <xsl:choose> + <xsl:when test="$shpClass_ = 'PERIPHERAL'"> +<!-- + <xsl:message>Found Multi Proc Peripheral</xsl:message> +--> + <xsl:call-template name="F_Calc_PeriShape_Height"> + <xsl:with-param name="iShapeInst" select="MODULE/@INSTANCE"/> + </xsl:call-template> + </xsl:when> + <xsl:when test="$shpClass_ = 'MEMORY_UNIT'"> +<!-- + <xsl:message>Found Multi Proc Memory Unit</xsl:message> +--> + <xsl:call-template name="F_Calc_MemoryUnit_Height"> + <xsl:with-param name="iShapeIndex" select="@CSHAPE_INDEX"/> + </xsl:call-template> + </xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + </xsl:variable> + +<!-- + <xsl:message>Found <xsl:value-of select="$shpHeight_"/></xsl:message> +--> + + <MPSHAPE HEIGHT="{$shpHeight_}"/> + </xsl:for-each> + </xsl:variable> + +<!-- + <xsl:message>Found stack of height <xsl:value-of select="sum(exsl:node-set($mpStk_ShpHeights_)/MPSHAPE/@HEIGHT)"/></xsl:message> +--> + + <xsl:value-of select="sum(exsl:node-set($mpStk_ShpHeights_)/MPSHAPE/@HEIGHT)"/> +</xsl:template> + +<xsl:template name="F_Calc_Max_MultiProc_Stack_Height"> + + <!-- Store the heights in a variable --> + + <xsl:variable name="mpStks_Heights_"> + <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE)"> + <MPSTK HEIGHT="0"/> + </xsl:if> + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@PSTACK_BLKD_X)]"> + <xsl:variable name="mpstack_height_"> + <xsl:call-template name="F_Calc_MultiProc_Stack_Height"> + <xsl:with-param name="iMPStack_Blkd_X" select="(@PSTACK_BLKD_X + 1)"/> + </xsl:call-template> + </xsl:variable> + +<!-- + <xsl:message>Found <xsl:value-of select="$mpstack_height_"/></xsl:message> +--> + <MPSTK HEIGHT="{$mpstack_height_}"/> + </xsl:for-each> + + </xsl:variable> + + <!-- Return the max of them --> + <xsl:value-of select="math:max(exsl:node-set($mpStks_Heights_)/MPSTK/@HEIGHT)"/> + +</xsl:template> + + + +<xsl:template name="F_Calc_Stack_Shape_Y"> + + <xsl:param name="iHorizIdx" select="100"/> + <xsl:param name="iVertiIdx" select="100"/> + + +<!-- + <xsl:param name="sbsGap" select="0"/> + <xsl:variable name="numSBSs_" select="count($G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSSHAPES/MODULE)"/> + <xsl:variable name="sbs_LANE_H_" select="($numSBSs_ * $BLKD_SBS_LANE_H)"/> + <xsl:variable name="sbsGap_" select="($BLKD_PROC2SBS_GAP + $sbs_LANE_H_)"/> +--> + + <xsl:variable name="sbsGap_" select="((count($G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSSHAPES/MODULE) * $BLKD_SBS_LANE_H) + $BLKD_PROC2SBS_GAP)"/> + + <xsl:if test="(not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@STACK_HORIZ_INDEX = $iHorizIdx) and ((@SHAPE_VERTI_INDEX = $iVertiIdx) or ($iVertiIdx = 100)))]) and + not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET[( (@STACK_HORIZ_INDEX = $iHorizIdx) and ((@SHAPE_VERTI_INDEX = $iVertiIdx) or ($iVertiIdx = 100)))]) and + not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[( (@STACK_HORIZ_INDEX = $iHorizIdx) and ((@SHAPE_VERTI_INDEX = $iVertiIdx) or ($iVertiIdx = 100)))]))">0</xsl:if> + + +<!-- + <xsl:if test="(not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@STACK_HORIZ_INDEX = $iHorizIdx) and ((@SHAPE_VERTI_INDEX = $iVertiIdx) or ($iVertiIdx = 100)))]) and + not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET[( (@STACK_HORIZ_INDEX = $iHorizIdx) and ((@SHAPE_VERTI_INDEX = $iVertiIdx) or ($iVertiIdx = 100)))]) and + not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[( (@STACK_HORIZ_INDEX = $iHorizIdx) and ((@SHAPE_VERTI_INDEX = $iVertiIdx) or ($iVertiIdx = 100)))]))"> + <xsl:message>Something is missing </xsl:message> + </xsl:if> +--> + + <xsl:if test="(($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@STACK_HORIZ_INDEX = $iHorizIdx) and ((@SHAPE_VERTI_INDEX = $iVertiIdx) or ($iVertiIdx = 100)))]) or + ($G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET[( (@STACK_HORIZ_INDEX = $iHorizIdx) and ((@SHAPE_VERTI_INDEX = $iVertiIdx) or ($iVertiIdx = 100)))]) or + ($G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[( (@STACK_HORIZ_INDEX = $iHorizIdx) and ((@SHAPE_VERTI_INDEX = $iVertiIdx) or ($iVertiIdx = 100)))]))"> + <!-- Store the spaces above this one in a variable --> + <xsl:variable name="spaces_above_"> + + <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@STACK_HORIZ_INDEX = $iHorizIdx) and (@SHAPE_VERTI_INDEX < $iVertiIdx))])"> + <SPACE HEIGHT="0"/> + </xsl:if> + + <!-- Store the height of all peripherals and memory units above this one--> + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@STACK_HORIZ_INDEX = $iHorizIdx) and (@SHAPE_VERTI_INDEX < $iVertiIdx))]"> + + <xsl:if test="not(@MODCLASS='MEMORY_UNIT')"> + <xsl:variable name="peri_height_"> + <xsl:call-template name="F_Calc_Shape_Height"> + <xsl:with-param name="iShapeId" select="@SHAPE_ID"/> + </xsl:call-template> + </xsl:variable> +<!-- + <xsl:message>Found peri height <xsl:value-of select="$peri_height_"/></xsl:message> +--> + <SPACE HEIGHT="{$peri_height_ + $BLKD_BIF_H}"/> + </xsl:if> + + <xsl:if test="(@MODCLASS='MEMORY_UNIT')"> + <xsl:variable name="memu_height_"> + <xsl:call-template name="F_Calc_MemoryUnit_Height"> + <xsl:with-param name="iShapeId" select="@SHAPE_ID"/> + </xsl:call-template> + </xsl:variable> +<!-- + <xsl:message>Found unit height <xsl:value-of select="$memu_height_"/></xsl:message> +--> + <SPACE HEIGHT="{$memu_height_ + $BLKD_BIF_H}"/> + </xsl:if> + + </xsl:for-each> + + <!-- Store the height of all the processors above this one--> + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[((@STACK_HORIZ_INDEX = $iHorizIdx) and (@SHAPE_VERTI_INDEX < $iVertiIdx))]"> + <xsl:variable name="proc_height_"> + <xsl:call-template name="F_Calc_PeriShape_Height"> + <xsl:with-param name="iShapeInst" select="@INSTANCE"/> + </xsl:call-template> + </xsl:variable> + +<!-- + <xsl:message>Found Proc height <xsl:value-of select="$proc_height_ + $BLKD_BIF_H"/></xsl:message> +--> + <SPACE HEIGHT="{$proc_height_ + $BLKD_BIF_H}"/> + </xsl:for-each> + + <!-- If its a peripheral that is below the shared busses, or its a shared bus bucket --> + <!-- add the height of the shared busses and the processor. --> + <xsl:if test="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@STACK_HORIZ_INDEX = $iHorizIdx) and (@SHAPE_VERTI_INDEX = $iVertiIdx))]/@IS_BLWSBS)"> + <SPACE HEIGHT="{$sbsGap_}"/> + </xsl:if> + <xsl:if test="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET[((@STACK_HORIZ_INDEX = $iHorizIdx) and (@SHAPE_VERTI_INDEX = $iVertiIdx))])"> + <SPACE HEIGHT="{$sbsGap_}"/> + </xsl:if> + + <!-- Store the height of all shared bus buckets above this one--> + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET[((@STACK_HORIZ_INDEX = $iHorizIdx) and (@SHAPE_VERTI_INDEX < $iVertiIdx))]"> + <xsl:variable name="bkt_height_"> + <xsl:call-template name="F_Calc_SbsBucket_Height"> + <xsl:with-param name="iBucketId" select="@BUS_INDEX"/> + </xsl:call-template> + </xsl:variable> + +<!-- + <xsl:message>Found bucket height <xsl:value-of select="$bkt_height_ + $BLKD_BIF_H"/></xsl:message> +--> + + <SPACE HEIGHT="{$bkt_height_ + $BLKD_BIF_H}"/> + </xsl:for-each> + + </xsl:variable> + + <xsl:value-of select="sum(exsl:node-set($spaces_above_)/SPACE/@HEIGHT)"/> + </xsl:if> + +</xsl:template> + + +<xsl:template name="F_Calc_Max_BusConnLane_BifY"> + + <xsl:param name="iBusName" select="'_busname_'"/> + + <!-- Store the heights in a variable --> + <xsl:variable name="busConnYs_"> + + <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE/BUSCONNS/BUSCONNLANE/BUSCONN)"> + <BUSCONNY HEIGHT="0"/> + </xsl:if> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE/BUSCONNS/BUSCONNLANE[(@BUSNAME = $iBusName)]/BUSCONN"> + + <xsl:variable name="peri_cstk_y_"> + <xsl:call-template name="F_Calc_CStackShapesAbv_Height"> + <xsl:with-param name="iCStackIndex" select="../@CSTACK_INDEX"/> + <xsl:with-param name="ICStackModY" select="@CSTACK_MODS_Y"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="peri_bif_dy_"> + <xsl:value-of select="(($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_H) * @BIF_Y)"/> + </xsl:variable> + + <xsl:variable name="peri_bc_y_"> + <xsl:value-of select="($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_H + $peri_bif_dy_ + ceiling($BLKD_BIF_H div 2)) - ceiling($BLKD_BIFC_H div 2)"/> + </xsl:variable> + +<!-- + <xsl:message>Found a busconn lane</xsl:message> +--> + <BUSCONNY HEIGHT="{$peri_cstk_y_ + $peri_bif_dy_ + $peri_bc_y_}"/> + </xsl:for-each> + + </xsl:variable> + + <!-- Return the max of them --> + <xsl:value-of select="math:max(exsl:node-set($busConnYs_)/BUSCONNY/@HEIGHT)"/> + +</xsl:template> + + +<xsl:template name="F_Calc_Min_BusConnLane_BifY"> + + <xsl:param name="iBusName" select="'_busname_'"/> + + <!-- Store the heights in a variable --> + <xsl:variable name="busConnYs_"> + + <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE/BUSCONNS/BUSCONNLANE/BUSCONN)"> + <BUSCONNY HEIGHT="0"/> + </xsl:if> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE/BUSCONNS/BUSCONNLANE[(@BUSNAME = $iBusName)]/BUSCONN"> + + <xsl:variable name="peri_cstk_y_"> + <xsl:call-template name="F_Calc_CStackShapesAbv_Height"> + <xsl:with-param name="iCStackIndex" select="../@CSTACK_INDEX"/> + <xsl:with-param name="iCStackModY" select="@CSTACK_MODS_Y"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="peri_bif_dy_"> + <xsl:value-of select="(($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_H) * @BIF_Y)"/> + </xsl:variable> + + <xsl:variable name="peri_bc_y_"> + <xsl:value-of select="($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_H + $peri_bif_dy_ + ceiling($BLKD_BIF_H div 2)) - ceiling($BLKD_BIFC_H div 2)"/> + </xsl:variable> + +<!-- + <xsl:message>Found a busconn lane</xsl:message> +--> + <BUSCONNY HEIGHT="{$peri_cstk_y_ + $peri_bc_y_}"/> + </xsl:for-each> + + </xsl:variable> + + <!-- Return the min of them --> + <xsl:value-of select="math:min(exsl:node-set($busConnYs_)/BUSCONNY/@HEIGHT)"/> + +</xsl:template> + +<xsl:template name="F_Calc_Stack_Height"> + <xsl:param name="iStackIdx" select="100"/> + +<!-- + <xsl:message>Calculating height for Stack Index <xsl:value-of select="$iStackIdx"/></xsl:message> +--> + + + <xsl:variable name="stack_height_"> + <!-- if this is called with no vert index of a shape + it defaults to the total height of the stack --> + <xsl:call-template name="F_Calc_Stack_Shape_Y"> + <xsl:with-param name="iHorizIdx" select="$iStackIdx"/> + </xsl:call-template> + </xsl:variable> + +<!-- + <xsl:message>Calculated height for Stack as <xsl:value-of select="$stack_height_"/></xsl:message> +--> + <xsl:value-of select="$stack_height_"/> +</xsl:template> + +<!-- +--> + + +<xsl:template name="F_Calc_Stack_Width"> + <xsl:param name="iStackIdx" select="100"/> + +<!-- + <xsl:message>=============Stack Idx <xsl:value-of select="$iStackIdx"/>====</xsl:message> +--> + <xsl:variable name="shape_widths_"> + + <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[@STACK_HORIZ_INDEX = $iStackIdx])"> + <SHAPE WIDTH="0"/> + </xsl:if> + + <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[@STACK_HORIZ_INDEX = $iStackIdx])"> + <SHAPE WIDTH="0"/> + </xsl:if> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@STACK_HORIZ_INDEX = $iStackIdx)]"> +<!-- + <xsl:variable name="proc_w_"> + <xsl:value-of select="$BLKD_MOD_W"/> + </xsl:variable> + <xsl:message>Found processor of width <xsl:value-of select="$proc_w_"/></xsl:message> +--> + <SHAPE WIDTH="{$BLKD_MOD_W}"/> + </xsl:for-each> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@STACK_HORIZ_INDEX = $iStackIdx)]"> + + <xsl:variable name="shpClass_" select="@MODCLASS"/> + <xsl:variable name="shape_w_"> + <xsl:choose> + + <xsl:when test="$shpClass_ = 'PERIPHERAL'"> + <xsl:value-of select="$BLKD_MOD_W"/> + </xsl:when> + + <xsl:when test="$shpClass_ = 'MEMORY_UNIT'"> + <xsl:value-of select="($BLKD_MOD_W * @MODS_W)"/> + </xsl:when> + + <xsl:otherwise>0</xsl:otherwise> + + </xsl:choose> + </xsl:variable> + +<!-- + <xsl:message>Found shape width <xsl:value-of select="$shape_w_"/></xsl:message> +--> + + <SHAPE WIDTH="{$shape_w_}"/> + </xsl:for-each> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET[(@STACK_HORIZ_INDEX = $iStackIdx)]"> + <xsl:variable name="bucket_w_"> + <xsl:value-of select="(($BLKD_MOD_BKTLANE_W * 2) + (($BLKD_MOD_W * @MODS_W) + ($BLKD_MOD_BUCKET_G * (@MODS_W - 1))))"/> + </xsl:variable> + +<!-- + <xsl:message>Found bucket of width <xsl:value-of select="$bucket_w_"/></xsl:message> +--> + <SHAPE WIDTH="{$bucket_w_}"/> + </xsl:for-each> + + </xsl:variable> + + <xsl:value-of select="math:max(exsl:node-set($shape_widths_)/SHAPE/@WIDTH)"/> +</xsl:template> + + +<xsl:template name="F_Calc_Stack_X"> + <xsl:param name="iStackIdx" select="0"/> +<!-- + <xsl:message>Looking for stack indexes less than <xsl:value-of select="$iStackIdx"/></xsl:message> +--> + + <!-- Store the stack widths in a variable --> + <xsl:variable name="stackspace_widths_"> + + <xsl:if test="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/@STACK_HORIZ_WIDTH = $iStackIdx)"> + <STACKSPACE WIDTH="{$BLKD_BUS_LANE_W}"/> + </xsl:if> + + <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES[(@STACK_HORIZ_INDEX < $iStackIdx)])"> + <STACKSPACE WIDTH="0"/> + </xsl:if> + + <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES[(@STACK_HORIZ_INDEX < $iStackIdx)])"> + <STACKSPACE WIDTH="0"/> + </xsl:if> + + <xsl:if test="not($G_ROOT/EDKSYSTEM/SBSBUCKETS/SBSBUCKET[(@STACK_HORIZ_INDEX < $iStackIdx)])"> + <STACKSPACE WIDTH="0"/> + </xsl:if> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE[(@EAST <= $iStackIdx)]"> + +<!-- + <xsl:message>==============================</xsl:message> + <xsl:message>Found a space of index <xsl:value-of select="@EAST"/></xsl:message> + <xsl:message>Bus lane space width <xsl:value-of select="@BUSLANES_W"/></xsl:message> + <xsl:message>Bus lane space is <xsl:value-of select="$space_width_"/></xsl:message> + <xsl:variable name="space_width_" select="($BLKD_BUS_LANE_W * @BUSLANES_W)"/> +--> + + <xsl:variable name="East_"> + <xsl:choose> + <xsl:when test="@EAST"><xsl:value-of select="@EAST"/></xsl:when> + <xsl:otherwise>'NONE'</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="West_"> + <xsl:choose> + <xsl:when test="@WEST"><xsl:value-of select="@WEST"/></xsl:when> + <xsl:otherwise>NONE</xsl:otherwise> + </xsl:choose> + </xsl:variable> + +<!-- + <xsl:message>1 - West_ <xsl:value-of select="$West_"/></xsl:message> + <xsl:message>1 - East_ <xsl:value-of select="$East_"/></xsl:message> +--> + <xsl:variable name="space_width_"> + <xsl:call-template name="F_Calc_Space_Width"> + <xsl:with-param name="iStackToWest" select="$West_"/> + <xsl:with-param name="iStackToEast" select="$East_"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="stack_width_"> + <xsl:if test="not(@EAST = $iStackIdx)"> + <xsl:call-template name="F_Calc_Stack_Width"> + <xsl:with-param name="iStackIdx" select="@EAST"/> + </xsl:call-template> + </xsl:if> + <xsl:if test="(@EAST = $iStackIdx)">0</xsl:if> + </xsl:variable> +<!-- + <xsl:message>Found stack of width <xsl:value-of select="$stack_width_"/></xsl:message> + <xsl:message>==============================</xsl:message> +--> + <STACKSPACE WIDTH="{$stack_width_ + $space_width_}"/> + + </xsl:for-each> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE[(not(@EAST) and (@WEST = ($iStackIdx -1)))]"> + <xsl:variable name="space_width_" select="($BLKD_BUS_LANE_W * @BUSLANES_W)"/> +<!-- + <xsl:message>Found end space of <xsl:value-of select="$space_width_"/></xsl:message> +--> + <STACKSPACE WIDTH="{$space_width_}"/> + </xsl:for-each> + + + </xsl:variable> + + <xsl:value-of select="sum(exsl:node-set($stackspace_widths_)/STACKSPACE/@WIDTH)"/> + +</xsl:template> + +<xsl:template name="F_Calc_Space_Width"> + + <xsl:param name="iStackToWest" select="'NONE'"/> + <xsl:param name="iStackToEast" select="'NONE'"/> + +<!-- + <xsl:message>Stack to West <xsl:value-of select="$stackToWest"/></xsl:message> + <xsl:message>Stack to East <xsl:value-of select="$stackToEast"/></xsl:message> +--> + + <xsl:variable name="spaceWidth_"> + <xsl:choose> + <xsl:when test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE[((@EAST = $iStackToEast) or (not($iStackToWest = 'NONE') and (@WEST = $iStackToWest)))]"> + <xsl:value-of select="((($G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE[((@EAST = $iStackToEast) or (not($iStackToWest = 'NONE') and (@WEST = $iStackToWest)))]/@BUSLANES_W) + 1) * $BLKD_BUS_LANE_W)"/> + </xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + </xsl:variable> + +<!-- + <xsl:message>Space width <xsl:value-of select="$spaceWidth_"/></xsl:message> +--> + + <xsl:value-of select="$spaceWidth_"/> +</xsl:template> + + +<xsl:template name="F_Calc_Space_X"> + + <xsl:param name="iStackToWest" select="'NONE'"/> + <xsl:param name="iStackToEast" select="'NONE'"/> + +<!-- + <xsl:message>Stack East <xsl:value-of select="$stackToEast"/></xsl:message> + <xsl:message>Stack West <xsl:value-of select="$stackToWest"/></xsl:message> +--> + + <!-- Store the stack widths in a variable --> + +<!-- + <xsl:message>Looking for stack indexes less than <xsl:value-of select="$stackIdx"/></xsl:message> +--> + + <xsl:variable name="stackspace_widths_"> + + <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES[(@STACK_HORIZ_INDEX < $iStackToEast)])"> + <STACKSPACE WIDTH="0"/> + </xsl:if> + + <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES[(@STACK_HORIZ_INDEX < $iStackToEast)])"> + <STACKSPACE WIDTH="0"/> + </xsl:if> + + <xsl:if test="not($G_ROOT/EDKSYSTEM/SBSBUCKETS/SBSBUCKET[(@STACK_HORIZ_INDEX < $iStackToEast)])"> + <STACKSPACE WIDTH="0"/> + </xsl:if> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE[((@EAST < $iStackToEast) or (not($iStackToWest = 'NONE') and (@EAST <= $iStackToWest)))]"> + +<!-- + <xsl:message>==============================</xsl:message> + <xsl:message>Found a space of index <xsl:value-of select="@EAST"/></xsl:message> +--> + + <xsl:variable name="East_"> + <xsl:choose> + <xsl:when test="@EAST"><xsl:value-of select="@EAST"/></xsl:when> + <xsl:otherwise>'NONE'</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="West_"> + <xsl:choose> + <xsl:when test="@WEST"><xsl:value-of select="@WEST"/></xsl:when> + <xsl:otherwise>NONE</xsl:otherwise> + </xsl:choose> + </xsl:variable> +<!-- + <xsl:message>2 - West_ <xsl:value-of select="$West_"/></xsl:message> + <xsl:message>2 - East_ <xsl:value-of select="$East_"/></xsl:message> + --> + <xsl:variable name="space_width_"> + <xsl:call-template name="F_Calc_Space_Width"> + <xsl:with-param name="iStackToWest" select="$West_"/> + <xsl:with-param name="iStackToEast" select="$East_"/> + </xsl:call-template> + </xsl:variable> + +<!-- + <xsl:variable name="space_width_" select="($BLKD_BUS_LANE_W * @BUSLANES_W)"/> + <xsl:message>Bus lane space width <xsl:value-of select="@BUSLANES_W"/></xsl:message> + <xsl:message>Bus lane space is <xsl:value-of select="$space_width_"/></xsl:message> +--> + + <xsl:variable name="stack_width_"> + <xsl:call-template name="F_Calc_Stack_Width"> + <xsl:with-param name="iStackIdx" select="@EAST"/> + </xsl:call-template> + </xsl:variable> + +<!-- + <xsl:message>Found stack of width <xsl:value-of select="$stack_width_"/></xsl:message> + <xsl:message>==============================</xsl:message> +--> + + <STACKSPACE WIDTH="{$stack_width_ + $space_width_}"/> + </xsl:for-each> + </xsl:variable> + + <xsl:variable name = "stackToWest_W_"> + <xsl:choose> + <xsl:when test="(($iStackToEast = '0') and ($iStackToWest = 'NONE'))">0</xsl:when> + <xsl:when test="(($iStackToEast = 'NONE') and not($iStackToWest = 'NONE'))"> + <xsl:call-template name="F_Calc_Stack_Width"> + <xsl:with-param name="iStackIdx" select="$iStackToWest"/> + </xsl:call-template> + </xsl:when> + <xsl:when test="(not($iStackToEast = '0') and ($iStackToWest = 'NONE'))"> + <xsl:call-template name="F_Calc_Stack_Width"> + <xsl:with-param name="iStackIdx" select="($iStackToEast - 1)"/> + </xsl:call-template> + </xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + </xsl:variable> + +<!-- + <xsl:variable name = "stackToEast_W_"> + <xsl:call-template name="F_Calc_Stack_Width"> + <xsl:with-param name="stackIdx" select="$stackToEast"/> + </xsl:call-template> + </xsl:variable> + <xsl:variable name ="extSpaceEast_W_" select="ceiling($stackToEast_W_ div 2)"/> +--> + + <xsl:variable name ="extSpaceWest_W_" select="ceiling($stackToWest_W_ div 2)"/> + + <xsl:value-of select="sum(exsl:node-set($stackspace_widths_)/STACKSPACE/@WIDTH) - $extSpaceWest_W_"/> +</xsl:template> + +</xsl:stylesheet> diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtTinySvgBLKD_Globals.xsl b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtTinySvgBLKD_Globals.xsl new file mode 100644 index 000000000..9d6fe70b1 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtTinySvgBLKD_Globals.xsl @@ -0,0 +1,115 @@ +<?xml version="1.0" standalone="no"?> +<xsl:stylesheet version="1.0" + xmlns:svg="http://www.w3.org/2000/svg" + xmlns:xsl="http://www.w3.org/1999/XSL/Transform" + xmlns:exsl="http://exslt.org/common" + xmlns:xlink="http://www.w3.org/1999/xlink"> + +<xsl:output method="xml" version="1.0" encoding="UTF-8" indent="yes" + doctype-public="-//W3C//DTD SVG 1.0//EN" + doctype-system="http://www.w3.org/TR/SVG/DTD/svg10.dtd"/> + +<!-- + =========================================================================== + CALCULATE GLOBAL VARIABLES BASED ON BLKDIAGRAM DEF IN INPUT XML + =========================================================================== +--> + +<xsl:variable name="G_Total_StandAloneMpmc_H"> + <xsl:if test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/MPMCSHAPE"> + <xsl:value-of select="($BLKD_MPMC_MOD_H + $BLKD_MPMC2PROC_GAP)"/> + </xsl:if> + <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/MPMCSHAPE)">0</xsl:if> +</xsl:variable> + +<xsl:variable name="G_Max_Stack_BlwSbs_H"> + <xsl:call-template name="F_Calc_Max_Stack_BlwSbs_Height"/> +</xsl:variable> + +<xsl:variable name="G_Max_Stack_AbvSbs_H"> + <xsl:call-template name="F_Calc_Max_Stack_AbvSbs_Height"/> +</xsl:variable> + +<xsl:variable name="G_Total_Stacks_W"> + <xsl:call-template name="F_Calc_Stack_X"> + <xsl:with-param name="iStackIdx" select="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/@STACK_HORIZ_WIDTH)"/> + </xsl:call-template> +</xsl:variable> + +<xsl:variable name="G_NumOfSharedBusses" select="count($G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSSHAPES/MODULE)"/> +<xsl:variable name="G_Total_SharedBus_H" select="($G_NumOfSharedBusses * $BLKD_SBS_LANE_H)"/> + +<xsl:variable name="G_NumOfBridges" select="count($G_ROOT/EDKSYSTEM/BLKDIAGRAM/BRIDGESHAPES/MODULE)"/> +<xsl:variable name="G_Total_Bridges_W" select="(($G_NumOfBridges * ($BLKD_MOD_W + ($BLKD_BUS_LANE_W * 2))) + $BLKD_BRIDGE_GAP)"/> + +<xsl:variable name="G_Total_DrawArea_CLC" select="($G_Total_Stacks_W + $G_Total_Bridges_W + ($BLKD_INNER_GAP * 2))"/> + +<xsl:variable name="G_Total_DrawArea_W"> + <xsl:if test="$G_Total_DrawArea_CLC > ($BLKD_KEY_W + $BLKD_SPECS_W + $BLKD_SPECS2KEY_GAP)"> + <xsl:value-of select="$G_Total_DrawArea_CLC"/> + </xsl:if> + <xsl:if test="not($G_Total_DrawArea_CLC > ($BLKD_KEY_W + $BLKD_SPECS2KEY_GAP + $BLKD_SPECS_W))"> + <xsl:value-of select="($BLKD_KEY_W + $BLKD_SPECS_W + $BLKD_SPECS2KEY_GAP)"/> + </xsl:if> +</xsl:variable> + +<xsl:variable name="G_IpBucketMods_H"> + <xsl:if test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/IPBUCKET/@MODS_H"><xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/IPBUCKET/@MODS_H"/></xsl:if> + <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/IPBUCKET/@MODS_H)">0</xsl:if> +</xsl:variable> +<xsl:variable name="G_Total_IpBucket_H" select="($G_IpBucketMods_H * ($BLKD_MOD_H + $BLKD_BIF_H))"/> + +<xsl:variable name="G_Total_UnkBucket_H"> + <xsl:if test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/UNKBUCKET"> + + <xsl:variable name="unkBucketMods_H_"> + <xsl:if test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/UNKBUCKET/@MODS_H"><xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/UNKBUCKET/@MODS_H"/></xsl:if> + <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/UNKBUCKET/@MODS_H)">0</xsl:if> + </xsl:variable> + + <xsl:variable name="total_UnkMod_H_" select="($unkBucketMods_H_ * ($BLKD_MOD_H + $BLKD_BIF_H))"/> + + <xsl:variable name="unkBucketBifs_H_"> + <xsl:if test="/EDKSYSTEM/BLKDIAGRAM/UNKBUCKET/@BIFS_H"><xsl:value-of select="/EDKSYSTEM/BLKDIAGRAM/UNKBUCKET/@BIFS_H"/></xsl:if> + <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/UNKBUCKET/@BIFS_H)">0</xsl:if> + </xsl:variable> + + <xsl:variable name="total_UnkBif_H_" select="($unkBucketBifs_H_ * ($BLKD_MOD_H + $BLKD_BIF_H))"/> + + <xsl:value-of select="($total_UnkBif_H_ + $total_UnkMod_H_)"/> + </xsl:if> + + <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/UNKBUCKET)">0</xsl:if> +</xsl:variable> + +<xsl:variable name="G_SharedBus_Y" select="($BLKD_INNER_Y + $G_Total_StandAloneMpmc_H + $G_Max_Stack_AbvSbs_H + $BLKD_PROC2SBS_GAP)"/> + +<!-- =========================================================================== + Calculate the width of the Block Diagram based on the total number of + buslanes and modules in the design. If there are no buslanes or modules, + a default width, just wide enough to display the KEY and SPECS is used + =========================================================================== --> +<xsl:variable name="G_Total_Blkd_W" select="($G_Total_DrawArea_W + (($BLKD_PRTCHAN_W + $BLKD_IORCHAN_W)* 2))"/> +<xsl:variable name="G_Total_Diag_W" select="$G_Total_Blkd_W"/> + +<!-- =========================================================================== --> +<!-- Calculate the height of the Block Diagram based on the total number of --> +<!-- buslanes and modules in the design. Take into account special shapes such --> +<!-- as MultiProc shapes. --> +<!-- =========================================================================== --> + + +<xsl:variable name="G_Total_DrawArea_H" select="($G_Total_StandAloneMpmc_H + $G_Max_Stack_AbvSbs_H + $BLKD_PROC2SBS_GAP + $G_Total_SharedBus_H + $G_Max_Stack_BlwSbs_H + $BLKD_SBS2IP_GAP + $G_Total_IpBucket_H + $BLKD_IP2UNK_GAP + $G_Total_UnkBucket_H + ($BLKD_INNER_GAP * 2))"/> +<xsl:variable name="G_Total_Blkd_H" select="($G_Total_DrawArea_H + (($BLKD_PRTCHAN_H + $BLKD_IORCHAN_H)* 2))"/> + +<xsl:variable name="G_Total_Diag_H"> + <xsl:if test="($IN_TESTMODE = 'TRUE')"> + <xsl:message>Generating Blkdiagram in TestMode </xsl:message> + <xsl:value-of select="$G_Total_Blkd_H"/> + </xsl:if> + <xsl:if test="(not($IN_TESTMODE) or ($IN_TESTMODE = 'FALSE'))"> + <xsl:value-of select="($G_Total_Blkd_H + $BLKD_DRAWAREA2KEY_GAP + $BLKD_KEY_H)"/> + </xsl:if> +</xsl:variable> + +</xsl:stylesheet> diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtTinySvgBLKD_IOPorts.xsl b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtTinySvgBLKD_IOPorts.xsl new file mode 100644 index 000000000..ec0c0e54e --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtTinySvgBLKD_IOPorts.xsl @@ -0,0 +1,490 @@ +<?xml version="1.0" standalone="no"?> +<xsl:stylesheet version="1.0" + xmlns:svg="http://www.w3.org/2000/svg" + xmlns:xsl="http://www.w3.org/1999/XSL/Transform" + xmlns:math="http://exslt.org/math" + xmlns:exsl="http://exslt.org/common" + xmlns:xlink="http://www.w3.org/1999/xlink" + extension-element-prefixes="math"> + +<xsl:output method="xml" version="1.0" encoding="UTF-8" indent="yes" + doctype-public="-//W3C//DTD SVG 1.0//EN" + doctype-system="http://www.w3.org/TR/SVG/DTD/svg10.dtd"/> + + +<!-- ======================= DEF BLOCK =============================== --> +<xsl:template name="Define_IOPorts"> + + <xsl:variable name="key_col_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="'KEY'"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="key_lt_col_"> + <xsl:call-template name="F_BusStd2RGB_LT"> + <xsl:with-param name="iBusStd" select="'KEY'"/> + </xsl:call-template> + </xsl:variable> + + <g id="G_IOPort"> + <rect + x="0" + y="0" + width= "{$BLKD_IOP_W}" + height="{$BLKD_IOP_H}" style="fill:{$COL_IORING_LT}; stroke:{$COL_IORING}; stroke-width:1"/> + + <path class="ioport" + d="M 0,0 + L {$BLKD_IOP_W},{ceiling($BLKD_IOP_H div 2)} + L 0,{$BLKD_IOP_H} + Z" style="stroke:none; fill:{$COL_SYSPRT}"/> + </g> + + <g id="G_BIPort"> + <rect + x="0" + y="0" + width= "{$BLKD_IOP_W}" + height="{$BLKD_IOP_H}" style="fill:{$COL_IORING_LT}; stroke:{$COL_IORING}; stroke-width:1"/> + + <path class="btop" + d="M 0,{ceiling($BLKD_IOP_H div 2)} + {ceiling($BLKD_IOP_W div 2)},0 + {$BLKD_IOP_W},{ceiling($BLKD_IOP_H div 2)} + Z" style="stroke:none; fill:{$COL_SYSPRT}"/> + + <path class="bbot" + d="M 0,{ceiling($BLKD_IOP_H div 2)} + {ceiling($BLKD_IOP_W div 2)},{$BLKD_IOP_H} + {$BLKD_IOP_W},{ceiling($BLKD_IOP_H div 2)} + Z" style="stroke:none; fill:{$COL_SYSPRT}"/> + + </g> + + <g id="KEY_IOPort"> + <rect + x="0" + y="0" + width= "{$BLKD_IOP_W}" + height="{$BLKD_IOP_H}" style="fill:{$key_lt_col_}; stroke:none;"/> + + <path class="ioport" + d="M 0,0 + L {$BLKD_IOP_W},{ceiling($BLKD_IOP_H div 2)} + L 0,{$BLKD_IOP_H} + Z" style="stroke:none; fill:{$key_col_}"/> + </g> + + <g id="KEY_BIPort"> + <rect + x="0" + y="0" + width= "{$BLKD_IOP_W}" + height="{$BLKD_IOP_H}" style="fill:{$key_lt_col_}; stroke:none;"/> + + <path class="btop" + d="M 0,{ceiling($BLKD_IOP_H div 2)} + {ceiling($BLKD_IOP_W div 2)},0 + {$BLKD_IOP_W},{ceiling($BLKD_IOP_H div 2)} + Z" style="stroke:none; fill:{$key_col_}"/> + + <path class="bbot" + d="M 0,{ceiling($BLKD_IOP_H div 2)} + {ceiling($BLKD_IOP_W div 2)},{$BLKD_IOP_H} + {$BLKD_IOP_W},{ceiling($BLKD_IOP_H div 2)} + Z" style="stroke:none; fill:{$key_col_}"/> + </g> + + <g id="KEY_INPort"> + <use x="0" y="0" xlink:href="#KEY_IOPort"/> + <rect + x="{$BLKD_IOP_W}" + y="0" + width= "{ceiling($BLKD_IOP_W div 2)}" + height="{$BLKD_IOP_H}" style="fill:{$COL_SYSPRT}; stroke:none;"/> + </g> + + <g id="KEY_OUTPort"> + <use x="0" y="0" xlink:href="#KEY_IOPort" transform="scale(-1,1) translate({$BLKD_IOP_W * -1},0)"/> + <rect + x="{$BLKD_IOP_W}" + y="0" + width= "{ceiling($BLKD_IOP_W div 2)}" + height="{$BLKD_IOP_H}" style="fill:{$COL_SYSPRT}; stroke:none;"/> + </g> + + <g id="KEY_INOUTPort"> + <use x="0" y="0" xlink:href="#KEY_BIPort"/> + <rect + x="{$BLKD_IOP_W}" + y="0" + width= "{ceiling($BLKD_IOP_W div 2)}" + height="{$BLKD_IOP_H}" style="fill:{$COL_SYSPRT}; stroke:none;"/> + </g> +</xsl:template> + +<!-- ======================= DRAW BLOCK =============================== --> + +<xsl:template name="Draw_IOPorts"> + + <xsl:variable name="ports_count_" select="count($G_ROOT/EDKSYSTEM/EXTERNALPORTS/PORT)"/> + + <xsl:if test="($ports_count_ > 30)"> + <xsl:call-template name="Draw_IOPorts_4Sides"/> + </xsl:if> + + <xsl:if test="($ports_count_ <= 30)"> + <xsl:call-template name="Draw_IOPorts_2Sides"/> + </xsl:if> +</xsl:template> + +<xsl:template name="Draw_IOPorts_2Sides"> + + <xsl:variable name="ports_count_" select="count($G_ROOT/EDKSYSTEM/EXTERNALPORTS/PORT)"/> + <xsl:variable name="ports_per_side_" select="ceiling($ports_count_ div 2)"/> + + <xsl:variable name="h_ofs_"> + <xsl:value-of select="$BLKD_PRTCHAN_W + ceiling(($G_Total_DrawArea_W - (($ports_per_side_ * $BLKD_IOP_W) + (($ports_per_side_ - 1) * $BLKD_IOP_SPC))) div 2)"/> + </xsl:variable> + + <xsl:variable name="v_ofs_"> + <xsl:value-of select="$BLKD_PRTCHAN_H + ceiling(($G_Total_DrawArea_H - (($ports_per_side_ * $BLKD_IOP_H) + (($ports_per_side_ - 1) * $BLKD_IOP_SPC))) div 2)"/> + </xsl:variable> + + + <xsl:for-each select="EXTERNALPORTS/PORT"> + <xsl:sort data-type="number" select="@INDEX" order="ascending"/> + + <xsl:variable name="poffset_" select="0"/> + <xsl:variable name="pcount_" select="$poffset_ + (position() -1)"/> + + <xsl:variable name="pdir_"> + <xsl:choose> + <xsl:when test="(@DIR='I' or @DIR='IN' or @DIR='INPUT')">I</xsl:when> + <xsl:when test="(@DIR='O' or @DIR='OUT' or @DIR='OUTPUT')">O</xsl:when> + <xsl:when test="(@DIR='IO' or @DIR='INOUT')">B</xsl:when> + <xsl:otherwise>I</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="pside_"> + <xsl:choose> + <xsl:when test="($pcount_ >= ($ports_per_side_ * 0) and ($pcount_ < ($ports_per_side_ * 1)))">W</xsl:when> + <xsl:when test="($pcount_ >= ($ports_per_side_ * 1) and ($pcount_ < ($ports_per_side_ * 2)))">E</xsl:when> + <xsl:otherwise>D</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="pdec_"> + <xsl:choose> + <xsl:when test="($pside_ = 'W')"><xsl:value-of select="($ports_per_side_ * 0)"/></xsl:when> + <xsl:when test="($pside_ = 'E')"><xsl:value-of select="($ports_per_side_ * 1)"/></xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="px_"> + <xsl:choose> + <xsl:when test="($pside_ = 'W')"><xsl:value-of select="($BLKD_PRTCHAN_W - $BLKD_IOP_W)"/></xsl:when> + <xsl:when test="($pside_ = 'S')"><xsl:value-of select="($h_ofs_ + (((position() - 1) - $pdec_) * ($BLKD_IOP_SPC + $BLKD_IOP_W)) - 2)"/></xsl:when> + <xsl:when test="($pside_ = 'E')"><xsl:value-of select="($BLKD_PRTCHAN_W + ($BLKD_IORCHAN_W * 2) + $G_Total_DrawArea_W)"/></xsl:when> + <xsl:when test="($pside_ = 'N')"><xsl:value-of select="($h_ofs_ + (((position() - 1) - $pdec_) * ($BLKD_IOP_SPC + $BLKD_IOP_W)))"/></xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="py_"> + <xsl:choose> + <xsl:when test="($pside_ = 'W')"><xsl:value-of select="($v_ofs_ + (((position() - 1) - $pdec_) * ($BLKD_IOP_SPC + $BLKD_IOP_H)))"/></xsl:when> + <xsl:when test="($pside_ = 'S')"><xsl:value-of select="($BLKD_PRTCHAN_H + ($BLKD_IORCHAN_H * 2) + $G_Total_DrawArea_H)"/></xsl:when> + <xsl:when test="($pside_ = 'E')"><xsl:value-of select="($v_ofs_ + (((position() - 1) - $pdec_) * ($BLKD_IOP_SPC + $BLKD_IOP_H)))"/></xsl:when> + <xsl:when test="($pside_ = 'N')"><xsl:value-of select="($BLKD_PRTCHAN_H - $BLKD_IOP_H)"/></xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="prot_"> + <xsl:choose> + <xsl:when test="(($pside_ = 'W') and ($pdir_ = 'I'))">0</xsl:when> + <xsl:when test="(($pside_ = 'S') and ($pdir_ = 'I'))">-90</xsl:when> + <xsl:when test="(($pside_ = 'E') and ($pdir_ = 'I'))">180</xsl:when> + <xsl:when test="(($pside_ = 'N') and ($pdir_ = 'I'))">90</xsl:when> + + <xsl:when test="(($pside_ = 'W') and ($pdir_ = 'O'))">180</xsl:when> + <xsl:when test="(($pside_ = 'S') and ($pdir_ = 'O'))">90</xsl:when> + <xsl:when test="(($pside_ = 'E') and ($pdir_ = 'O'))">0</xsl:when> + <xsl:when test="(($pside_ = 'N') and ($pdir_ = 'O'))">-90</xsl:when> + + <xsl:when test="(($pside_ = 'W') and ($pdir_ = 'B'))">0</xsl:when> + <xsl:when test="(($pside_ = 'S') and ($pdir_ = 'B'))">0</xsl:when> + <xsl:when test="(($pside_ = 'E') and ($pdir_ = 'B'))">0</xsl:when> + <xsl:when test="(($pside_ = 'N') and ($pdir_ = 'B'))">0</xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + + <xsl:variable name="txo_"> + <xsl:choose> + <xsl:when test="($pside_ = 'W')">-10</xsl:when> + <xsl:when test="($pside_ = 'S')">6</xsl:when> + <xsl:when test="($pside_ = 'E')"><xsl:value-of select="(($BLKD_IOP_W * 2) - 4)"/></xsl:when> + <xsl:when test="($pside_ = 'N')">6</xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="tyo_"> + <xsl:choose> + <xsl:when test="($pside_ = 'W')"><xsl:value-of select="ceiling($BLKD_IOP_H div 2) + 6"/></xsl:when> + <xsl:when test="($pside_ = 'S')"><xsl:value-of select="($BLKD_IOP_H * 2) + 4"/></xsl:when> + <xsl:when test="($pside_ = 'E')"><xsl:value-of select="ceiling($BLKD_IOP_H div 2) + 6"/></xsl:when> + <xsl:when test="($pside_ = 'N')">-2</xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:if test="$pdir_ = 'B'"> + <use x="{$px_}" + y="{$py_}" + id="{@NAME}" + xlink:href="#G_BIPort" + transform="rotate({$prot_},{$px_ + ceiling($BLKD_IOP_W div 2)},{$py_ + ceiling($BLKD_IOP_H div 2)})"/> + </xsl:if> + + <xsl:if test="(($pside_ = 'S') and not($pdir_ = 'B'))"> + <rect + x="{$px_}" + y="{$py_}" + width= "{$BLKD_IOP_W}" + height="{$BLKD_IOP_H}" style="stroke:{$COL_IORING}; stroke-width:1"/> + </xsl:if> + + <xsl:if test="not($pdir_ = 'B')"> + <use x="{$px_}" + y="{$py_}" + id="{@NAME}" + xlink:href="#G_IOPort" + transform="rotate({$prot_},{$px_ + ceiling($BLKD_IOP_W div 2)},{$py_ + ceiling($BLKD_IOP_H div 2)})"/> + </xsl:if> + + <text class="iopnumb" + x="{$px_ + $txo_}" + y="{$py_ + $tyo_}"> + <xsl:value-of select="@INDEX"/><tspan class="iopgrp"><xsl:value-of select="@GROUP"/></tspan> + </text> + + </xsl:for-each> + +</xsl:template> + + +<xsl:template name="Draw_IOPorts_4Sides"> + + <xsl:variable name="ports_count_" select="count($G_ROOT/EDKSYSTEM/EXTERNALPORTS/PORT)"/> + <xsl:variable name="ports_per_side_" select="ceiling($ports_count_ div 4)"/> + + <xsl:variable name="h_ofs_"> + <xsl:value-of select="$BLKD_PRTCHAN_W + ceiling(($G_Total_DrawArea_W - (($ports_per_side_ * $BLKD_IOP_W) + (($ports_per_side_ - 1) * $BLKD_IOP_SPC))) div 2)"/> + </xsl:variable> + + <xsl:variable name="v_ofs_"> + <xsl:value-of select="$BLKD_PRTCHAN_H + ceiling(($G_Total_DrawArea_H - (($ports_per_side_ * $BLKD_IOP_H) + (($ports_per_side_ - 1) * $BLKD_IOP_SPC))) div 2)"/> + </xsl:variable> + + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/EXTERNALPORTS/PORT"> + <xsl:sort data-type="number" select="@INDEX" order="ascending"/> + + <xsl:variable name="poffset_" select="0"/> + <xsl:variable name="pcount_" select="$poffset_ + (position() -1)"/> + + <xsl:variable name="pdir_"> + <xsl:choose> + <xsl:when test="(@DIR='I' or @DIR='IN' or @DIR='INPUT')">I</xsl:when> + <xsl:when test="(@DIR='O' or @DIR='OUT' or @DIR='OUTPUT')">O</xsl:when> + <xsl:when test="(@DIR='IO' or @DIR='INOUT')">B</xsl:when> + <xsl:otherwise>I</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="pside_"> + <xsl:choose> + <xsl:when test="($pcount_ >= ($ports_per_side_ * 0) and ($pcount_ < ($ports_per_side_ * 1)))">W</xsl:when> + <xsl:when test="($pcount_ >= ($ports_per_side_ * 1) and ($pcount_ < ($ports_per_side_ * 2)))">S</xsl:when> + <xsl:when test="($pcount_ >= ($ports_per_side_ * 2) and ($pcount_ < ($ports_per_side_ * 3)))">E</xsl:when> + <xsl:when test="($pcount_ >= ($ports_per_side_ * 3) and ($pcount_ < ($ports_per_side_ * 4)))">N</xsl:when> + <xsl:otherwise>D</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="pdec_"> + <xsl:choose> + <xsl:when test="($pside_ = 'W')"><xsl:value-of select="($ports_per_side_ * 0)"/></xsl:when> + <xsl:when test="($pside_ = 'S')"><xsl:value-of select="($ports_per_side_ * 1)"/></xsl:when> + <xsl:when test="($pside_ = 'E')"><xsl:value-of select="($ports_per_side_ * 2)"/></xsl:when> + <xsl:when test="($pside_ = 'N')"><xsl:value-of select="($ports_per_side_ * 3)"/></xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="px_"> + <xsl:choose> + <xsl:when test="($pside_ = 'W')"><xsl:value-of select="($BLKD_PRTCHAN_W - $BLKD_IOP_W)"/></xsl:when> + <xsl:when test="($pside_ = 'S')"><xsl:value-of select="($h_ofs_ + (((position() - 1) - $pdec_) * ($BLKD_IOP_SPC + $BLKD_IOP_W)) - 2)"/></xsl:when> + <xsl:when test="($pside_ = 'E')"><xsl:value-of select="($BLKD_PRTCHAN_W + ($BLKD_IORCHAN_W * 2) + $G_Total_DrawArea_W)"/></xsl:when> + <xsl:when test="($pside_ = 'N')"><xsl:value-of select="($h_ofs_ + (((position() - 1) - $pdec_) * ($BLKD_IOP_SPC + $BLKD_IOP_W)))"/></xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="py_"> + <xsl:choose> + <xsl:when test="($pside_ = 'W')"><xsl:value-of select="($v_ofs_ + (((position() - 1) - $pdec_) * ($BLKD_IOP_SPC + $BLKD_IOP_H)))"/></xsl:when> + <xsl:when test="($pside_ = 'S')"><xsl:value-of select="($BLKD_PRTCHAN_H + ($BLKD_IORCHAN_H * 2) + $G_Total_DrawArea_H)"/></xsl:when> + <xsl:when test="($pside_ = 'E')"><xsl:value-of select="($v_ofs_ + (((position() - 1) - $pdec_) * ($BLKD_IOP_SPC + $BLKD_IOP_H)))"/></xsl:when> + <xsl:when test="($pside_ = 'N')"><xsl:value-of select="($BLKD_PRTCHAN_H - $BLKD_IOP_H)"/></xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + + <xsl:variable name="prot_"> + <xsl:choose> + <xsl:when test="(($pside_ = 'W') and ($pdir_ = 'I'))">0</xsl:when> + <xsl:when test="(($pside_ = 'S') and ($pdir_ = 'I'))">-90</xsl:when> + <xsl:when test="(($pside_ = 'E') and ($pdir_ = 'I'))">180</xsl:when> + <xsl:when test="(($pside_ = 'N') and ($pdir_ = 'I'))">90</xsl:when> + + <xsl:when test="(($pside_ = 'W') and ($pdir_ = 'O'))">180</xsl:when> + <xsl:when test="(($pside_ = 'S') and ($pdir_ = 'O'))">90</xsl:when> + <xsl:when test="(($pside_ = 'E') and ($pdir_ = 'O'))">0</xsl:when> + <xsl:when test="(($pside_ = 'N') and ($pdir_ = 'O'))">-90</xsl:when> + + <xsl:when test="(($pside_ = 'W') and ($pdir_ = 'B'))">0</xsl:when> + <xsl:when test="(($pside_ = 'S') and ($pdir_ = 'B'))">0</xsl:when> + <xsl:when test="(($pside_ = 'E') and ($pdir_ = 'B'))">0</xsl:when> + <xsl:when test="(($pside_ = 'N') and ($pdir_ = 'B'))">0</xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="txo_"> + <xsl:choose> + <xsl:when test="($pside_ = 'W')">-14</xsl:when> + <xsl:when test="($pside_ = 'S')">8</xsl:when> + <xsl:when test="($pside_ = 'E')"><xsl:value-of select="(($BLKD_IOP_W * 2) - 4)"/></xsl:when> + <xsl:when test="($pside_ = 'N')">8</xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="tyo_"> + <xsl:choose> + <xsl:when test="($pside_ = 'W')"><xsl:value-of select="ceiling($BLKD_IOP_H div 2) + 6"/></xsl:when> + <xsl:when test="($pside_ = 'S')"><xsl:value-of select="($BLKD_IOP_H * 2) + 4"/></xsl:when> + <xsl:when test="($pside_ = 'E')"><xsl:value-of select="ceiling($BLKD_IOP_H div 2) + 6"/></xsl:when> + <xsl:when test="($pside_ = 'N')">-2</xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:if test="$pdir_ = 'B'"> + <use x="{$px_}" + y="{$py_}" + id="{@NAME}" + xlink:href="#G_BIPort" + transform="rotate({$prot_},{$px_ + ceiling($BLKD_IOP_W div 2)},{$py_ + ceiling($BLKD_IOP_H div 2)})"/> + </xsl:if> + + <xsl:if test="(($pside_ = 'S') and not($pdir_ = 'B'))"> + <rect + x="{$px_}" + y="{$py_}" + width= "{$BLKD_IOP_W}" + height="{$BLKD_IOP_H}" style="stroke:{$COL_IORING}; stroke-width:1"/> + </xsl:if> + + <xsl:if test="not($pdir_ = 'B')"> + <use x="{$px_}" + y="{$py_}" + id="{@NAME}" + xlink:href="#G_IOPort" + transform="rotate({$prot_},{$px_ + ceiling($BLKD_IOP_W div 2)},{$py_ + ceiling($BLKD_IOP_H div 2)})"/> + </xsl:if> + + <text class="iopnumb" + x="{$px_ + $txo_}" + y="{$py_ + $tyo_}"><xsl:value-of select="@INDEX"/><tspan class="iopgrp"><xsl:value-of select="@GROUP"/></tspan> + </text> + + </xsl:for-each> + +</xsl:template> + +<xsl:template name="Define_ExtPortsTable"> + +<!-- + <xsl:if test="$oriented_= 'WEST'"><xsl:value-of select="$proc2procX_ - (string-length(@BUSNAME) * 6)"/></xsl:if> + <xsl:variable name="max_name_" select="math:max(string-length($G_ROOT/EDKSYSTEM/EXTERNALPORTS/PORT/@NAME))"/> + <xsl:variable name="max_sgnm_" select="math:max(string-length($G_ROOT/EDKSYSTEM/EXTERNALPORTS/PORT/@SIGNAME))"/> + + <xsl:message>MAX NAME <xsl:value-of select="$max_name_"/></xsl:message> + <xsl:message>MAX SIG <xsl:value-of select="$max_sgnm_"/></xsl:message> +--> + + <xsl:variable name="ext_ports_"> + <xsl:if test="not($G_ROOT/EDKSYSTEM/EXTERNALPORTS/PORT)"> + <EXTPORT NAME="__none__" SIGNAME="__none_" NAMELEN="0" SIGLEN="0"/> + </xsl:if> + <xsl:if test="$G_ROOT/EDKSYSTEM/EXTERNALPORTS/PORT"> + <xsl:for-each select="$G_ROOT/EDKSYSTEM/EXTERNALPORTS/PORT"> + <EXTPORT NAME="{@NAME}" SIGNAME="{@SIGNAME}" NAMELEN="{string-length(@NAME)}" SIGLEN="{string-length(@SIGNAME)}"/> + </xsl:for-each> + </xsl:if> + </xsl:variable> + + <xsl:variable name="max_name_" select="math:max(exsl:node-set($ext_ports_)/EXTPORT/@NAMELEN)"/> + <xsl:variable name="max_sign_" select="math:max(exsl:node-set($ext_ports_)/EXTPORT/@SIGLEN)"/> + + <xsl:variable name="h_font_" select="12"/> + <xsl:variable name="w_font_" select="12"/> + + <xsl:variable name="w_num_" select="($w_font_ * 5)"/> + <xsl:variable name="w_dir_" select="($w_font_ * 3)"/> + <xsl:variable name="w_lsbmsb_" select="($w_font_ * 9)"/> + <xsl:variable name="w_attr_" select="($w_font_ * 4)"/> + <xsl:variable name="w_name_" select="($w_font_ * $max_name_)"/> + <xsl:variable name="w_sign_" select="($w_font_ * $max_sign_)"/> + + <xsl:variable name="w_table_" select="($w_num_ + $w_name_ + $w_dir_ + $w_sign_ + $w_attr_)"/> + +<!-- + <xsl:message>MAX NAME <xsl:value-of select="$max_name_"/></xsl:message> + <xsl:message>MAX SIG <xsl:value-of select="$max_sign_"/></xsl:message> + + <xsl:message>W NUM <xsl:value-of select="$w_num_"/></xsl:message> + <xsl:message>W DIR <xsl:value-of select="$w_dir_"/></xsl:message> + <xsl:message>W NAM <xsl:value-of select="$w_name_"/></xsl:message> + <xsl:message>W SIG <xsl:value-of select="$w_sign_"/></xsl:message> + <xsl:message>W ATT <xsl:value-of select="$w_attr_"/></xsl:message> + + <xsl:message>W TABLE <xsl:value-of select="$w_table_"/></xsl:message> +--> + + <g id="BlkDiagram_ExtPortsTable"> + <rect + x="0" + y="0" + width= "{$w_table_}" + height="{$h_font_}" style="fill:{$COL_RED}; stroke:none; stroke-width:1"/> + </g> + + + +</xsl:template> + +<!-- ======================= END MAIN BLOCK =========================== --> + +</xsl:stylesheet> diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtTinySvgBLKD_Main.xsl b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtTinySvgBLKD_Main.xsl new file mode 100644 index 000000000..a2f9a4480 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtTinySvgBLKD_Main.xsl @@ -0,0 +1,1549 @@ +<?xml version="1.0" standalone="no"?> + +<xsl:stylesheet version="1.0" + xmlns:svg="http://www.w3.org/2000/svg" + xmlns:exsl="http://exslt.org/common" + xmlns:xsl="http://www.w3.org/1999/XSL/Transform" + xmlns:math="http://exslt.org/math" + xmlns:xlink="http://www.w3.org/1999/xlink" + extension-element-prefixes="math"> + + +<!-- + =============================================== + INCLUDES + =============================================== + --> +<xsl:include href="MdtSvgBLKD_Dimensions.xsl"/> + +<xsl:include href="MdtSvgDiag_Colors.xsl"/> +<xsl:include href="MdtSvgDiag_Globals.xsl"/> +<xsl:include href="MdtSvgDiag_StyleDefs.xsl"/> + +<xsl:include href="MdtTinySvgDiag_BifShapes.xsl"/> + +<xsl:include href="MdtTinySvgBLKD_IOPorts.xsl"/> +<xsl:include href="MdtTinySvgBLKD_Busses.xsl"/> +<xsl:include href="MdtTinySvgBLKD_Globals.xsl"/> +<xsl:include href="MdtTinySvgBLKD_Functions.xsl"/> +<xsl:include href="MdtTinySvgBLKD_Peripherals.xsl"/> +<xsl:include href="MdtTinySvgBLKD_Processors.xsl"/> +<xsl:include href="MdtTinySvgBLKD_BusLaneSpaces.xsl"/> + +<xsl:output method="xml" version="1.0" encoding="UTF-8" indent="yes" + doctype-public="-//W3C//DTD SVG 1.0//EN" + doctype-system="svg10.dtd"/> + +<!-- + =============================================== + PARAMETERS + =============================================== + --> + +<xsl:param name="ADD_VIEWBOX" select="'FALSE'"/> +<xsl:param name="IN_TESTMODE" select="'FALSE'"/> + +<!-- +<xsl:param name="CSS_SVG_DIAGRAMS" select="'MdtSvgDiag_StyleDefs.css'"/> +<xsl:param name="CSS_SVG_DIAGRAMS" select="'__INTERNAL__'"/> + --> + +<!-- + ====================================================== + MAIN BLOCKDIAGRAM TEMPLATE + ====================================================== +--> +<xsl:template match="EDKSYSTEM[not(BLKDIAGRAM)]"> + <xsl:message>ERROT: Project is missing BLKDIAGRAM Element. Cannot generate.</xsl:message> +</xsl:template> + +<xsl:template match="EDKSYSTEM[BLKDIAGRAM]"> + +<!-- +<xsl:message>STCK_W is <xsl:value-of select="$G_Total_Stacks_W"/></xsl:message> +<xsl:message>BRDG_W is <xsl:value-of select="$G_Total_Bridges_W"/></xsl:message> +<xsl:message>MPMC is <xsl:value-of select="$G_Total_StandAloneMpmc_H"/></xsl:message> +<xsl:message>MPMC is <xsl:value-of select="$G_Total_StandAloneMpmc_H"/></xsl:message> +<xsl:message>MABV is <xsl:value-of select="$G_Max_Stack_AbvSbs_H"/></xsl:message> +<xsl:message>MBLW is <xsl:value-of select="$G_Max_Stack_BlwSbs_H"/></xsl:message> +<xsl:message>IPBK is <xsl:value-of select="$G_Total_IpBucket_H"/></xsl:message> +<xsl:message>Blkd Total is <xsl:value-of select="$blkd_H_"/></xsl:message> +<xsl:message>max abv is <xsl:value-of select="$max_Stack_AbvSbs_H_"/></xsl:message> +<xsl:message>max blw is <xsl:value-of select="$max_Stack_BlwSbs_H_"/></xsl:message> +<xsl:message>Ip Bkt is <xsl:value-of select="$totalIpBkt_H_"/></xsl:message> +<xsl:message>Sbs is <xsl:value-of select="$totalSbs_H_"/></xsl:message> +<xsl:message>Unk Bkt is <xsl:value-of select="$totalUnkBkt_H_"/></xsl:message> +<xsl:message>Blkd DrawArea height as <xsl:value-of select="$total_DrawArea_H_"/></xsl:message> +--> + +<!--specify a css for the file --> +<!-- +<xsl:processing-instruction name="xml-stylesheet">href="<xsl:value-of select="$CSS_SVG_DIAGRAMS"/>" type="text/css"</xsl:processing-instruction> +<xsl:variable name="BLKD_ZOOM_Y"> + <xsl:choose> + <xsl:when test="($ADD_VIEWBOX = 'TRUE')"> + <xsl:value-of select="($G_Total_Diag_H * 2)"/> + </xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> +</xsl:variable> + --> + +<xsl:text> </xsl:text> +<!-- +<svg width="{$G_Total_Diag_W}" height="{$G_Total_Diag_H}" viewBox="0 0 0 {$BLKD_ZOOM_Y}"> +--> +<svg width="{$G_Total_Diag_W}" height="{$G_Total_Diag_H}"> +<!-- + =============================================== + Layout All the various definitions + =============================================== +--> + <defs> + + <!-- IO Port Defs --> + <xsl:call-template name="Define_IOPorts"/> + + <!-- BIF Defs --> + <xsl:call-template name="Define_ConnectedBifTypes"/> + + <!-- Bus Defs --> + <xsl:call-template name="Define_Busses"/> + + <!-- Shared Bus Buckets Defs --> + <xsl:call-template name="Define_SBSBuckets"/> + + <!-- IP Bucket Defs --> + <xsl:call-template name="Define_IPBucket"/> + + <!-- Stack Defs --> + <xsl:call-template name="Define_AllStacks"/> + + <!-- Space Defs --> + <xsl:call-template name="Define_BusLaneSpaces"/> + + <!-- Main MPMC Defs --> + <xsl:if test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/MPMCSHAPE"> + <xsl:call-template name="Define_StandAlone_MPMC"/> + </xsl:if> + + <!-- Diagram Key Definition --> + <xsl:call-template name="Define_BlkDiagram_Key"/> + + <!-- Diagram Specs Definition --> + <xsl:call-template name="Define_BlkDiagram_Specs"> + <xsl:with-param name="iArch" select="SYSTEMINFO/@ARCH"/> + <xsl:with-param name="iPart" select="SYSTEMINFO/@PART"/> + <xsl:with-param name="iTimeStamp" select="@TIMESTAMP"/> + <xsl:with-param name="iEdkVersion" select="@EDKVERSION"/> + </xsl:call-template> + + </defs> + +<!-- =============================================== --> +<!-- Draw Outlines --> +<!-- =============================================== --> + + <!-- The surrounding black liner --> + <rect x="0" + y="0" + width ="{$G_Total_Diag_W}" + height="{$G_Total_Diag_H}" style="fill:{$COL_WHITE}; stroke:{$COL_BLACK};stroke-width:4"/> + + <!-- The outer IO channel --> + <rect x="{$BLKD_PRTCHAN_W}" + y="{$BLKD_PRTCHAN_H}" + width= "{$G_Total_Blkd_W - ($BLKD_PRTCHAN_W * 2)}" + height="{$G_Total_Blkd_H - ($BLKD_PRTCHAN_H * 2)}" style="fill:{$COL_IORING}"/> + + <!-- The Diagram's drawing area --> + <rect x="{$BLKD_PRTCHAN_W + $BLKD_IORCHAN_W}" + y="{$BLKD_PRTCHAN_H + $BLKD_IORCHAN_H}" + width= "{$G_Total_DrawArea_W}" + height="{$G_Total_DrawArea_H}" rx="8" ry="8" style="fill:{$COL_BG}"/> + +<!-- =============================================== --> +<!-- Draw All the various components --> +<!-- =============================================== --> + + <!-- Layout the IO Ports --> +<!-- + <xsl:if test="(not($IN_TESTMODE) or ($IN_TESTMODE = 'FALSE'))"> + <xsl:call-template name="Draw_IOPorts"/> + </xsl:if> + --> + + <!-- Layout the Shapes --> + <xsl:call-template name="Draw_BlkDiagram_Shapes"/> + +</svg> + +<!-- ======================= END MAIN SVG BLOCK =============================== --> +</xsl:template> + +<xsl:template name="Draw_BlkDiagram_Shapes"> + + <!-- + =========================================================== + Draw the Stand Alone MPMC, (if any) + =========================================================== + --> + <xsl:if test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/MPMCSHAPE"> + + <xsl:variable name="mpmc_inst_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/MPMCSHAPE/@INSTANCE"/> + <use x="{$BLKD_INNER_X}" y="{$BLKD_INNER_Y}" xlink:href="#mpmcmodule_{$mpmc_inst_}"/> + + <!-- + =========================================================== + Draw the connections to the Stand Alone MPMC + =========================================================== + --> + <xsl:call-template name="Draw_BlkDiagram_StandAloneMpmcConnections"/> + </xsl:if> + + <!-- + =========================================================== + Draw the Stacks + =========================================================== + --> + <xsl:call-template name="Draw_BlkDiagram_Stacks"/> + + + + <!-- + =========================================================== + Draw the Bus Lane Spaces + =========================================================== + --> + <xsl:call-template name="Draw_BlkDiagram_BusLaneSpaces"/> + + + <!-- + =========================================================== + Draw the shared busses + =========================================================== + --> + <use x="{$BLKD_INNER_X}" y="{$G_SharedBus_Y}" xlink:href="#group_sharedBusses"/> + + <!-- + =========================================================== + Draw the Bridges + =========================================================== + --> + <xsl:call-template name="Draw_BlkDiagram_Bridges"/> + + + <!-- + =========================================================== + Draw the Ip Bucket + =========================================================== + --> + <xsl:call-template name="Draw_BlkDiagram_IPBucket"/> + + + <!-- + =========================================================== + Draw the Key + =========================================================== + --> + <xsl:if test="(not($IN_TESTMODE) or ($IN_TESTMODE = 'FALSE'))"> + <use x="{$G_Total_Blkd_W - $BLKD_KEY_W - $BLKD_PRTCHAN_W}" y="{$G_Total_Blkd_H + $BLKD_DRAWAREA2KEY_GAP - 8}" xlink:href="#BlkDiagram_Key"/> + </xsl:if> + + <!-- + =========================================================== + Draw the Specs + =========================================================== + --> + <xsl:if test="(not($IN_TESTMODE) or ($IN_TESTMODE = 'FALSE'))"> + <use x="{$BLKD_PRTCHAN_W}" y="{$G_Total_Blkd_H + $BLKD_DRAWAREA2KEY_GAP - 8}" xlink:href="#BlkDiagram_Specs"/> + </xsl:if> + + <!-- + ************************************************************ + *************** DONE DRAWING BLOCK DIAGRAM ************** + ************************************************************ + --> + +</xsl:template> + + +<!-- ======================================================================= --> +<!-- FUNCTION TEMPLATE --> +<!-- --> +<!-- Draw stacks on the Block Diagram --> +<!-- ======================================================================= --> +<xsl:template name="Draw_BlkDiagram_Stacks"> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE[(@EAST < $G_ROOT/EDKSYSTEM/BLKDIAGRAM/@STACK_HORIZ_WIDTH)]"> + + <xsl:variable name="stack_line_x_"> + <xsl:call-template name="F_Calc_Stack_X"> + <xsl:with-param name="iStackIdx" select="@EAST"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="stack_abv_sbs_"> + <xsl:call-template name="F_Calc_Stack_AbvSbs_Height"> + <xsl:with-param name="iStackIdx" select="@EAST"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="bridges_w_" select="(($G_NumOfBridges * ($BLKD_MOD_W + ($BLKD_BUS_LANE_W * 2))) + $BLKD_BRIDGE_GAP)"/> + + <xsl:variable name="stack_y_" select="($G_SharedBus_Y - $stack_abv_sbs_ - $BLKD_PROC2SBS_GAP)"/> + <xsl:variable name="stack_x_" select="($BLKD_INNER_X + $stack_line_x_ + $bridges_w_)"/> + + <xsl:variable name="stack_name_"> + <xsl:call-template name="F_generate_Stack_Name"> + <xsl:with-param name="iHorizIdx" select="@EAST"/> + </xsl:call-template> + </xsl:variable> + + <use x="{$stack_x_}" y="{$stack_y_}" xlink:href="#{$stack_name_}"/> + + </xsl:for-each> + +</xsl:template> + +<xsl:template name="Draw_BlkDiagram_StandAloneMpmcConnections"> + + <xsl:variable name="mpmcInst_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/MPMCSHAPE/@INSTANCE"/> + <xsl:variable name="lastStack_" select="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/@STACK_HORIZ_WIDTH) - 1"/> + + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE"> + <xsl:variable name="currentLane_" select="position()"/> +<!-- + <xsl:message>Current lane <xsl:value-of select="$currentLane_"/></xsl:message> +--> + <xsl:variable name="stackToEast_"> + <xsl:choose> + <xsl:when test="not(@WEST = $lastStack_)"><xsl:value-of select="@EAST"/></xsl:when> + <xsl:when test=" (@WEST = $lastStack_)"><xsl:value-of select="'NONE'"/></xsl:when> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="stackToWest_"> + <xsl:choose> + <xsl:when test="not(@WEST = $lastStack_)"><xsl:value-of select="'NONE'"/></xsl:when> + <xsl:when test=" (@WEST = $lastStack_)"><xsl:value-of select="@WEST"/></xsl:when> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="spaceAbvSbs_H_"> + <xsl:call-template name="F_Calc_Space_AbvSbs_Height"> + <xsl:with-param name="iStackToEast" select="$stackToEast_"/> + <xsl:with-param name="iStackToWest" select="$stackToWest_"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="space_y_" select="($G_SharedBus_Y - $spaceAbvSbs_H_ - $BLKD_PROC2SBS_GAP)"/> + +<!-- + <xsl:message>Stack To East <xsl:value-of select="$stackToEast_"/></xsl:message> + <xsl:message>Stack To West <xsl:value-of select="$stackToWest_"/></xsl:message> + <xsl:variable name="space_X_"> + <xsl:call-template name="F_Calc_Space_X"> + <xsl:with-param name="iStackToEast" select="$stackToEast_"/> + <xsl:with-param name="iStackToWest" select="$stackToWest_"/> + </xsl:call-template> + </xsl:variable> + <xsl:variable name="space_y_" select="($G_SharedBus_Y - $spaceAbvSbs_H_ - $BLKD_PROC2SBS_GAP)"/> + <xsl:variable name="space_x_" select="($BLKD_INNER_X + $G_Total_Bridges_W + $space_line_x_)"/> +--> + + + <xsl:for-each select="BUSCONNLANE[@IS_MPMCCONN]"> + +<!-- + <xsl:variable name="bifSide_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = BUSCONN/@INSTANCE)]/BUSINTERFACE[(@BUSNAME = @BUSNAME)]/@BIF_X"/> +--> + <xsl:variable name="bifInst_" select="BUSCONN/@INSTANCE"/> + <xsl:variable name="busName_" select="@BUSNAME"/> + <xsl:variable name="bifSide_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $bifInst_)]/BUSINTERFACE[(@BUSNAME = $busName_)]/@BIF_X"/> + + <xsl:variable name="mpmcBifName_"> + <xsl:choose> + <xsl:when test=" (@IS_SBSCONN)"><xsl:value-of select="BUSCONN/@BUSINTERFACE"/></xsl:when> + <xsl:when test="not(@IS_SBSCONN)"><xsl:value-of select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $mpmcInst_)]/BUSINTERFACE[(@BUSNAME = $busName_)]/@NAME"/></xsl:when> + <xsl:otherwise><xsl:value-of select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $mpmcInst_)]/BUSINTERFACE[(@BUSNAME = $busName_)]/@NAME"/></xsl:otherwise> + </xsl:choose> + </xsl:variable> + +<!-- + <xsl:message>MPMC Bif Name <xsl:value-of select="$mpmcBifName_"/></xsl:message> + <xsl:message>Bif Side <xsl:value-of select="$bifSide_"/></xsl:message> + <xsl:message>Bus Name <xsl:value-of select="@BUSNAME"/></xsl:message> + <xsl:message>Instance <xsl:value-of select="$bifInst_"/></xsl:message> + <xsl:message>Space line x <xsl:value-of select="$space_line_X_"/></xsl:message> +--> + + <xsl:variable name="space_line_X_"> + <xsl:call-template name="F_Calc_Space_X"> + <xsl:with-param name="iStackToEast" select="$stackToEast_"/> + <xsl:with-param name="iStackToWest" select="$stackToWest_"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="space_X_" select="($BLKD_INNER_X + $G_Total_Bridges_W + $space_line_X_)"/> + + <xsl:variable name = "stackToWest_W_"> + <xsl:choose> + <xsl:when test="(($stackToEast_ = '0') and ($stackToWest_ = 'NONE'))">0</xsl:when> + <xsl:when test="(($stackToEast_ = 'NONE') and not($stackToWest_ = 'NONE'))"> + <xsl:call-template name="F_Calc_Stack_Width"> + <xsl:with-param name="iStackIdx" select="$stackToWest_"/> + </xsl:call-template> + </xsl:when> + <xsl:when test="(not($stackToEast_ = '0') and not($stackToEast_ = 'NONE') and ($stackToWest_ = 'NONE'))"> + <xsl:call-template name="F_Calc_Stack_Width"> + <xsl:with-param name="iStackIdx" select="($stackToEast_ - 1)"/> + </xsl:call-template> + </xsl:when> + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name = "stackToEast_W_"> + <xsl:call-template name="F_Calc_Stack_Width"> + <xsl:with-param name="iStackIdx" select="$stackToEast_"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name ="extSpaceWest_W_" select="ceiling($stackToWest_W_ div 2)"/> + <xsl:variable name ="extSpaceEast_W_" select="ceiling($stackToEast_W_ div 2)"/> + <xsl:variable name="laneInSpace_X_"> + <xsl:choose> + <xsl:when test="(@ORIENTED = 'EAST')"> + <xsl:value-of select="($extSpaceWest_W_ + (@BUSLANE_X * $BLKD_BUS_LANE_W) - $BLKD_BUS_LANE_W - $BLKD_BUS_ARROW_W - $BLKD_P2P_BUS_W)"/> + </xsl:when> + <xsl:otherwise><xsl:value-of select="($extSpaceWest_W_ + (@BUSLANE_X * $BLKD_BUS_LANE_W))"/></xsl:otherwise> + </xsl:choose> + </xsl:variable> + + + <xsl:variable name="lane_X_" select="($space_X_ + $laneInSpace_X_)"/> + + <xsl:variable name="mpmcBifType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $mpmcInst_)]/BUSINTERFACE[(@NAME = $mpmcBifName_)]/@TYPE"/> + + <!-- + <xsl:variable name="bc_X_" select="($lane_X_ + ceiling($BLKD_BIFC_W div 2) - ceiling($BLKD_BUS_ARROW_W div 2))"/> + <xsl:variable name="bc_X_" select="($lane_X_ + ceiling($BLKD_BIFC_W div 2) - ceiling($BLKD_BUS_ARROW_W div 2))"/> + <xsl:variable name="bc_X_" select="($lane_X_ + ceiling($BLKD_BIFC_W div 2))"/> + --> + + <xsl:variable name="bc_Y_" select="($BLKD_INNER_Y + $BLKD_MPMC_MOD_H)"/> + <xsl:variable name="bc_X_" > + <xsl:choose> + <xsl:when test="($bifSide_ = '0')"><xsl:value-of select="($lane_X_ + ceiling($BLKD_BIFC_W div 2))"/></xsl:when> + <xsl:when test="($bifSide_ = '1')"><xsl:value-of select="($lane_X_ + $BLKD_BIFC_dx)"/></xsl:when> + <xsl:otherwise> <xsl:value-of select="($lane_X_ + ceiling($BLKD_BIFC_W div 2))"/></xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="busColor_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="@BUSSTD"/> + </xsl:call-template> + </xsl:variable> + + <!-- Place the MPMC bif label --> + <xsl:variable name="bcl_X_" select="($bc_X_ + ceiling($BLKD_BIFC_W div 2) - ceiling($BLKD_BIF_W div 2))"/> + <xsl:variable name="bcl_Y_" select="($bc_Y_ - $BLKD_BIF_H - $BLKD_MOD_BIF_GAP_H)"/> + <use x="{$bcl_X_}" y="{$bcl_Y_}" xlink:href="#{@BUSSTD}_BifLabel"/> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="($bcl_X_ + ceiling($BLKD_BIF_W div 2))"/> + <xsl:with-param name="iY" select="($bcl_Y_ + ceiling($BLKD_BIF_H div 2) + 3)"/> + <xsl:with-param name="iText" select="$mpmcBifName_"/> + <xsl:with-param name="iClass" select="'mpmc_biflabel'"/> + </xsl:call-template> + + + <!-- Place the MPMC bif --> + <use x="{$bc_X_}" y="{$bc_Y_}" xlink:href="#{@BUSSTD}_busconn_{$mpmcBifType_}"/> + + <xsl:variable name="bcArrow_X_" select="($bc_X_ + ceiling($BLKD_BIFC_W div 2) - ceiling($BLKD_BUS_ARROW_H div 2))"/> + <xsl:variable name="bcArrow_Y_" select="($bc_Y_ + $BLKD_BIFC_H - 3)"/> + + <!-- Place the MPMC Arrow --> + <use x="{$bcArrow_X_}" y="{$bcArrow_Y_}" xlink:href="#{@BUSSTD}_BusArrowNorth"/> + + <!-- + Place a block to cover the gap btw MPMC and top of Bus Lane Space, or to the correct SBS + For non SBS connections a vertical block will already have been drawn to the top of the + space. + --> + + <xsl:variable name="sbsDy_"> + <xsl:choose> + <xsl:when test="@IS_SBSCONN"><xsl:value-of select="2 + ($G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $busName_)]/@BUS_INDEX * $BLKD_SBS_LANE_H)"/></xsl:when> + <xsl:when test="not(@IS_SBSCONN)">0</xsl:when> + <xsl:otherwise>0></xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="mpmcBusHeight_"> + <xsl:choose> + <xsl:when test="(@IS_SBSCONN)"><xsl:value-of select="($G_SharedBus_Y - ($bcArrow_Y_ + $BLKD_BUS_ARROW_W + 4) + $sbsDy_)"/></xsl:when> + <xsl:when test="not(@IS_SBSCONN)"> + <xsl:choose> + <xsl:when test="($space_y_ >= ($bcArrow_Y_ + $BLKD_BUS_ARROW_W + 4 + $sbsDy_))"> + <xsl:value-of select="($space_y_ - ($bcArrow_Y_ + $BLKD_BUS_ARROW_W + 4 + $sbsDy_))"/> + </xsl:when> + <xsl:when test="($space_y_ < ($bcArrow_Y_ + $BLKD_BUS_ARROW_W + 4 + $sbsDy_))"> + <xsl:value-of select="(($bcArrow_Y_ + $BLKD_BUS_ARROW_W + 4 + $sbsDy_) - $space_y_)"/> + </xsl:when> + </xsl:choose> + </xsl:when> + <xsl:otherwise><xsl:value-of select="$BLKD_BIFC_H"/></xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <rect x="{$bcArrow_X_ + $BLKD_BUS_ARROW_G}" + y="{$bcArrow_Y_ + $BLKD_BUS_ARROW_W + 4}" + width= "{$BLKD_P2P_BUS_W}" + height="{$mpmcBusHeight_}" + style="stroke:none; fill:{$busColor_}"/> + + <!-- place the bus label here --> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="($bcArrow_X_ + $BLKD_BUS_ARROW_W + 6)"/> + <xsl:with-param name="iY" select="($bcArrow_Y_ + ceiling($mpmcBusHeight_ div 2) + 6)"/> + <xsl:with-param name="iText" select="$busName_"/> + <xsl:with-param name="iClass" select="'p2pbus_label'"/> + </xsl:call-template> + + </xsl:for-each> + </xsl:for-each> + +</xsl:template> + + +<!-- ======================================================================= --> +<!-- FUNCTION TEMPLATE --> +<!-- --> +<!-- Draw bus lane spaces on the Block Diagram --> +<!-- ======================================================================= --> +<xsl:template name="Draw_BlkDiagram_BusLaneSpaces"> + + <xsl:variable name="lastStack_" select="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/@STACK_HORIZ_WIDTH) - 1"/> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE[@EAST]"> + <xsl:sort select="@EAST" data-type="number"/> + + <xsl:call-template name="Draw_BlkDiagram_BusLaneSpace"> + <xsl:with-param name="iStackToEast" select="@EAST"/> + </xsl:call-template> + </xsl:for-each> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE[(@WEST = $lastStack_)]"> + <xsl:call-template name="Draw_BlkDiagram_BusLaneSpace"> + <xsl:with-param name="iStackToWest" select="$lastStack_"/> + </xsl:call-template> + </xsl:for-each> + +</xsl:template> + +<xsl:template name="Draw_BlkDiagram_BusLaneSpace"> + + <xsl:param name="iStackToEast" select="'NONE'"/> + <xsl:param name="iStackToWest" select="'NONE'"/> + + <xsl:variable name="spaceAbvSbs_H_"> + <xsl:call-template name="F_Calc_Space_AbvSbs_Height"> + <xsl:with-param name="iStackToEast" select="$iStackToEast"/> + <xsl:with-param name="iStackToWest" select="$iStackToWest"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="spaceBlwSbs_H_"> + <xsl:call-template name="F_Calc_Space_BlwSbs_Height"> + <xsl:with-param name="iStackToEast" select="$iStackToEast"/> + <xsl:with-param name="iStackToWest" select="$iStackToWest"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="space_line_x_"> + <xsl:call-template name="F_Calc_Space_X"> + <xsl:with-param name="iStackToEast" select="$iStackToEast"/> + <xsl:with-param name="iStackToWest" select="$iStackToWest"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="space_y_" select="($G_SharedBus_Y - $spaceAbvSbs_H_ - $BLKD_PROC2SBS_GAP)"/> + <xsl:variable name="space_x_" select="($BLKD_INNER_X + $G_Total_Bridges_W + $space_line_x_)"/> + + <xsl:variable name="stackToEast_"> + <xsl:choose> + <xsl:when test="not($iStackToEast = 'NONE')"><xsl:value-of select="$iStackToEast"/></xsl:when> + <xsl:otherwise>NONE</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="stackToWest_"> + <xsl:choose> + <xsl:when test=" not($iStackToWest = 'NONE')"><xsl:value-of select="$iStackToWest"/></xsl:when> + <xsl:when test="(not($iStackToEast = 'NONE') and not($iStackToEast = '0'))"><xsl:value-of select="($iStackToEast - 1)"/></xsl:when> + <xsl:otherwise>NONE</xsl:otherwise> + </xsl:choose> + </xsl:variable> + + + <xsl:variable name="space_Name_"> + <xsl:call-template name="F_generate_Space_Name"> + <xsl:with-param name="iStackToEast" select="$stackToEast_"/> + <xsl:with-param name="iStackToWest" select="$stackToWest_"/> + </xsl:call-template> + </xsl:variable> + +<!-- + <xsl:message>StackToEast is <xsl:value-of select="$iStackToEast"/></xsl:message> + <xsl:message>StackToWest is <xsl:value-of select="$iStackToWest"/></xsl:message> + <xsl:message>SpaceName is <xsl:value-of select="$space_Name_"/></xsl:message> +--> + + <use x="{$space_x_}" y="{$space_y_}" xlink:href="#{$space_Name_}"/> + +</xsl:template> + + +<!-- =========================================================================== --> +<!-- FUNCTION TEMPLATE --> +<!-- --> +<!-- Draw Bridges on the Block Diagram --> +<!-- =========================================================================== --> +<xsl:template name="Draw_BlkDiagram_Bridges"> + + <!-- First save all the bridge indexs in a variable --> + <xsl:variable name="bridgeShapes_"> + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BRIDGESHAPES/MODULE/BUSCONNS[(@ORIENTED = 'WEST')]/BUSCONN"> + <BRIDGE BUS_INDEX="{@BUS_INDEX}" INSTANCE="{../../@INSTANCE}" POSITION="{(position() -1)}"/> + <BRIDGECONN BUS_INDEX="{@BUS_INDEX}" INSTANCE="{../../@INSTANCE}" ORIENTED="{../@ORIENTED}" POSITION="{(position() - 1)}" BUSSTD="{@BUSSTD}" TYPE="{@TYPE}"/> + <!-- So both bus conns have same position.... --> + <xsl:if test="../../BUSCONNS[(@ORIENTED = 'EAST')]"> + <BRIDGECONN BUS_INDEX="{../../BUSCONNS[(@ORIENTED ='EAST')]/BUSCONN/@BUS_INDEX}" INSTANCE="{../../@INSTANCE}" ORIENTED="EAST" POSITION="{(position() - 1)}" BUSSTD="{../../BUSCONNS[(@ORIENTED = 'EAST')]/BUSCONN/@BUSSTD}" TYPE="{../../BUSCONNS[(@ORIENTED = 'EAST')]/BUSCONN/@TYPE}"/> + </xsl:if> + </xsl:for-each> + </xsl:variable> +<!-- + <xsl:message>Found an east connection on <xsl:value-of select="../../@INSTANCE"/></xsl:message> +--> + <!-- Now layout the bridge shapes between the shared busses --> + <xsl:for-each select="exsl:node-set($bridgeShapes_)/BRIDGE"> + <xsl:sort select="@POSITION" data-type="number"/> + + <xsl:variable name="brdgPosition_" select="@POSITION"/> + <xsl:variable name="brdgInstance_" select="@INSTANCE"/> + + <xsl:variable name="min_bus_idx_" select="math:min(exsl:node-set($bridgeShapes_)/BRIDGECONN[(@POSITION = $brdgPosition_)]/@BUS_INDEX)"/> +<!-- + <xsl:variable name="max_bus_idx_" select="math:max(exsl:node-set($bridgeShapes_)/BRIDGECONN[(@POSITION = $brdgPosition_)]/@BUS_INDEX)"/> + + <xsl:message>Maximum index <xsl:value-of select="$max_bus_idx_"/></xsl:message> + <xsl:message>Minimum index <xsl:value-of select="$min_bus_idx_"/></xsl:message> +--> + + + <xsl:variable name="brdg_X_" select="($BLKD_INNER_X + $BLKD_BRIDGE_GAP + $BLKD_BUS_LANE_W + (@POSITION * ($BLKD_MOD_W + ($BLKD_BUS_LANE_W * 2))))"/> + <xsl:variable name="brdg_Y_" select="($G_SharedBus_Y + ($min_bus_idx_ * $BLKD_SBS_LANE_H) + ceiling($BLKD_SBS_LANE_H div 2) - ceiling($BLKD_MOD_H div 2))"/> + + <use x="{$brdg_X_}" y="{$brdg_Y_}" xlink:href="#symbol_{$brdgInstance_}"/> + </xsl:for-each> + + + +<!-- + <xsl:message>Found <xsl:value-of select="count(exsl:node-set($bridgeShapes_)/BRIDGECONN)"/> busconns </xsl:message> + <xsl:message>Drawing connection for bridge <xsl:value-of select="$brdgInstance_"/> at <xsl:value-of select="@POSITION"/> </xsl:message> +--> + + <xsl:for-each select="exsl:node-set($bridgeShapes_)/BRIDGECONN"> + <xsl:sort select="@POSITION" data-type="number"/> + + <xsl:variable name="brdgInstance_" select="@INSTANCE"/> + <xsl:variable name="brdgPosition_" select="@POSITION"/> + + <xsl:variable name="busColor_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="@BUSSTD"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="min_bus_idx_" select="math:min(exsl:node-set($bridgeShapes_)/BRIDGECONN[(@POSITION = $brdgPosition_)]/@BUS_INDEX)"/> + <xsl:variable name="brdg_Y1_" select="($G_SharedBus_Y + ($min_bus_idx_ * $BLKD_SBS_LANE_H) + ceiling($BLKD_SBS_LANE_H div 2) - ceiling($BLKD_MOD_H div 2))"/> + <xsl:variable name="brdg_X_" select="($BLKD_INNER_X + $BLKD_BRIDGE_GAP + $BLKD_BUS_LANE_W + (@POSITION * ($BLKD_MOD_W + ($BLKD_BUS_LANE_W * 2))))"/> + + <xsl:variable name="bc_Y_" select="$brdg_Y1_ + $BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V + ceiling($BLKD_BIF_H div 2) - ceiling($BLKD_BIFC_H div 2)"/> + <xsl:variable name="bc_X_"> + <xsl:choose> + <xsl:when test="@ORIENTED='WEST'"> + <xsl:value-of select="($brdg_X_ - $BLKD_BIFC_W)"/> + </xsl:when> + <xsl:when test="@ORIENTED='EAST'"> + <xsl:value-of select="($brdg_X_ + $BLKD_MOD_W)"/> + </xsl:when> + </xsl:choose> + </xsl:variable> + + <!-- Layout the bus conn --> + <use x="{$bc_X_}" y="{$bc_Y_}" xlink:href="#{@BUSSTD}_busconn_{@TYPE}"/> + + <!-- Figure out the positions of the lines --> + +<!-- + <xsl:variable name="vert_line_x_" select="$bc_X_ + ceiling($BLKD_BIFC_W div 2)"/> + <xsl:message>vert line x <xsl:value-of select="$vert_line_x_"/></xsl:message> + <xsl:message>bus index <xsl:value-of select="@BUS_INDEX"/></xsl:message> +--> + + <xsl:variable name="vert_line_x_"> + <xsl:choose> + <xsl:when test="@ORIENTED='WEST'"> + <xsl:value-of select="($bc_X_ - ($BLKD_BUS_LANE_W - $BLKD_BIFC_W))"/> + </xsl:when> + <xsl:when test="@ORIENTED='EAST'"> + <xsl:value-of select="($bc_X_ + ($BLKD_BUS_LANE_W - $BLKD_P2P_BUS_W))"/> + </xsl:when> + </xsl:choose> + </xsl:variable> + + <!-- At least one of the points is going to be the bus --> +<!-- + <xsl:variable name="vert_line_y1_" select="($G_SharedBus_Y + $BLKD_PROC2SBS_GAP + (@BUS_INDEX * $BLKD_SBS_LANE_H))"/> +--> + <xsl:variable name="vert_line_y1_" select="($G_SharedBus_Y + (@BUS_INDEX * $BLKD_SBS_LANE_H))"/> + <xsl:variable name="vert_line_y2_" select="$bc_Y_ + ceiling($BLKD_BIFC_H div 2)"/> + + <xsl:variable name="v_bus_ul_y_"> + <xsl:choose> + <xsl:when test="$vert_line_y1_ > $vert_line_y2_"> + <xsl:value-of select="$vert_line_y2_"/> + </xsl:when> + <xsl:when test="$vert_line_y2_ > $vert_line_y1_"> + <xsl:value-of select="$vert_line_y1_"/> + </xsl:when> + </xsl:choose> + </xsl:variable> +<!-- + <xsl:variable name="v_bus_ul_x_" select="$vert_line_x_"/> +--> + <xsl:variable name="v_bus_ul_x_"> + <xsl:choose> + <xsl:when test="@ORIENTED='WEST'"> + <xsl:value-of select="($vert_line_x_ + $BLKD_MOD_BIF_GAP_H)"/> + </xsl:when> + <xsl:when test="@ORIENTED='EAST'"> + <xsl:value-of select="($vert_line_x_ - $BLKD_MOD_BIF_GAP_H)"/> + </xsl:when> + </xsl:choose> + </xsl:variable> + + + <xsl:variable name="v_bus_width_" select="$BLKD_P2P_BUS_W"/> + <xsl:variable name="v_bus_height_"> + <xsl:choose> + <xsl:when test="$vert_line_y1_ > $vert_line_y2_"> + <xsl:value-of select="($vert_line_y1_ - $vert_line_y2_)"/> + </xsl:when> + <xsl:when test="$vert_line_y2_ > $vert_line_y1_"> + <xsl:value-of select="($vert_line_y2_ - $vert_line_y1_)"/> + </xsl:when> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="h_bus_ul_x_"> + <xsl:choose> + <xsl:when test="@ORIENTED='WEST'"> + <xsl:value-of select="($bc_X_ - ($BLKD_BUS_LANE_W - $BLKD_BIFC_W) + $BLKD_MOD_BIF_GAP_H)"/> + </xsl:when> + <xsl:when test="@ORIENTED='EAST'"> + <xsl:value-of select="($bc_X_ + $BLKD_BIFC_W - ceiling(($BLKD_BIFC_W - $BLKD_BIFC_Wi) div 2))"/> + </xsl:when> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="h_bus_ul_y_" select="$bc_Y_ + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_P2P_BUS_W div 2)"/> + <xsl:variable name="h_bus_height_" select="$BLKD_P2P_BUS_W"/> + + <xsl:variable name="h_bus_width_"> + <xsl:choose> + <xsl:when test="@ORIENTED='WEST'"> + <xsl:value-of select="(($bc_X_ + ceiling(($BLKD_BIFC_W - $BLKD_BIFC_Wi) div 2)) - $h_bus_ul_x_ + 1)"/> + </xsl:when> + <xsl:when test="@ORIENTED='EAST'"> + <xsl:value-of select="(($v_bus_ul_x_ + $BLKD_P2P_BUS_W) - $h_bus_ul_x_)"/> + </xsl:when> + </xsl:choose> + </xsl:variable> + + +<!-- + <xsl:message>vert line y1 <xsl:value-of select="$vert_line_y1_"/></xsl:message> +--> + + <rect x="{$v_bus_ul_x_}" + y="{$v_bus_ul_y_ + 2}" + width= "{$v_bus_width_}" + height="{$v_bus_height_}" + style="stroke:none; fill:{$busColor_}"/> + + <rect x="{$h_bus_ul_x_}" + y="{$h_bus_ul_y_}" + width= "{$h_bus_width_}" + height="{$h_bus_height_}" + style="stroke:none; fill:{$busColor_}"/> + + </xsl:for-each> + +</xsl:template> + + + + +<!-- =========================================================================== --> +<!-- FUNCTION TEMPLATE --> +<!-- --> +<!-- Draw the IP Bucket --> +<!-- =========================================================================== --> +<xsl:template name="Draw_BlkDiagram_IPBucket"> + + <!-- Draw IP Bucket --> + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/IPBUCKET"> + + <xsl:variable name="bucket_w_" select="(($BLKD_MOD_BKTLANE_W * 2) + (($BLKD_MOD_W * @MODS_W) + ($BLKD_MOD_BUCKET_G * (@MODS_W - 1))))"/> + <xsl:variable name="bucket_h_" select="(($BLKD_MOD_BKTLANE_H * 2) + (($BLKD_MOD_H * @MODS_H) + ($BLKD_MOD_BUCKET_G * (@MODS_H - 1))))"/> + + <xsl:variable name="bucket_x_" select="(ceiling($G_Total_Blkd_W div 2) - ceiling($bucket_w_ div 2))"/> + <xsl:variable name="bucket_y_" select="($G_SharedBus_Y + $G_Total_SharedBus_H + $G_Max_Stack_BlwSbs_H + $BLKD_SBS2IP_GAP)"/> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="$bucket_x_"/> + <xsl:with-param name="iY" select="($bucket_y_ - 4)"/> + <xsl:with-param name="iText" select="'IP'"/> + <xsl:with-param name="iClass" select="'bkt_label'"/> + </xsl:call-template> + + <use x="{$bucket_x_}" y="{$bucket_y_}" xlink:href="#ipbucket"/> + + </xsl:for-each> + +</xsl:template> + + +<xsl:template name="Draw_BlkDiagram_Key"> + <use x="{ceiling($G_Total_Blkd_W div 2) - ceiling($BLKD_KEY_W div 2)}" y="0" xlink:href="#BlkDiagram_Key"/> +</xsl:template> + +<xsl:template name="Define_BlkDiagram_Key"> + + <xsl:variable name="key_col_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="'KEY'"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="key_lt_col_"> + <xsl:call-template name="F_BusStd2RGB_LT"> + <xsl:with-param name="iBusStd" select="'KEY'"/> + </xsl:call-template> + </xsl:variable> + + <g id="KEY_IntrCntrl"> + <rect + x="0" + y="0" + rx="3" + ry="3" + width= "{ceiling($BLKD_INTR_W div 2)}" + height="{$BLKD_INTR_H}" style="fill:{$key_lt_col_}; stroke:none; stroke-width:1"/> + + <line x1="0" + y1="{ceiling($BLKD_INTR_H div 4)}" + x2="{ceiling($BLKD_INTR_W div 2)}" + y2="{ceiling($BLKD_INTR_H div 4)}" + style="stroke:{$COL_BLACK};stroke-width:2"/> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="1.5"/> + <xsl:with-param name="iY" select="(7 + ceiling($BLKD_INTR_H div 2))"/> + <xsl:with-param name="iText" select="'x'"/> + <xsl:with-param name="iClass" select="'intr_symbol'"/> + </xsl:call-template> + + </g> + + <g id="KEY_IntrdProc"> + <rect + x="0" + y="0" + rx="3" + ry="3" + width= "{ceiling($BLKD_INTR_W div 2)}" + height="{$BLKD_INTR_H}" style="fill:{$key_lt_col_}; stroke:none; stroke-width:1"/> + + <line x1="0" + y1="{ceiling($BLKD_INTR_H div 4) - 2}" + x2="{ceiling($BLKD_INTR_W div 2)}" + y2="{ceiling($BLKD_INTR_H div 4) - 2}" + style="stroke:{$COL_BLACK};stroke-width:1"/> + + <line x1="0" + y1="{ceiling($BLKD_INTR_H div 4) + 2}" + x2="{ceiling($BLKD_INTR_W div 2)}" + y2="{ceiling($BLKD_INTR_H div 4) + 2}" + style="stroke:{$COL_BLACK};stroke-width:1"/> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="1.5"/> + <xsl:with-param name="iY" select="(7 + ceiling($BLKD_INTR_H div 2))"/> + <xsl:with-param name="iText" select="'x'"/> + <xsl:with-param name="iClass" select="'intr_symbol'"/> + </xsl:call-template> + </g> + + <g id="KEY_IntrSrc"> + <rect + x="0" + y="0" + rx="3" + ry="3" + width= "{$BLKD_INTR_W}" + height="{ceiling($BLKD_INTR_H div 2)}" style="fill:{$key_lt_col_}; stroke:none; stroke-width:1"/> + + <line x1="{ceiling($BLKD_INTR_W div 2)}" + y1="0" + x2="{ceiling($BLKD_INTR_W div 2)}" + y2="{ceiling($BLKD_INTR_H div 2)}" + style="stroke:{$COL_BLACK};stroke-width:1"/> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="'2'"/> + <xsl:with-param name="iY" select="'7'"/> + <xsl:with-param name="iText" select="'y'"/> + <xsl:with-param name="iClass" select="'intr_symbol'"/> + </xsl:call-template> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="(2 + ceiling($BLKD_INTR_W div 2))"/> + <xsl:with-param name="iY" select="'7'"/> + <xsl:with-param name="iText" select="'x'"/> + <xsl:with-param name="iClass" select="'intr_symbol'"/> + </xsl:call-template> + </g> + + + <g id="BlkDiagram_Key"> + <rect + x="0" + y="0" + width= "{$BLKD_KEY_W}" + height="{$BLKD_KEY_H}" + style="fill:{$COL_BG}; stroke:none;"/> + + <rect x="0" + y="0" + width= "{$BLKD_KEY_W}" + height="16" + style="fill:{$COL_BG}; stroke:none;"/> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="ceiling($BLKD_KEY_W div 2)"/> + <xsl:with-param name="iY" select="'14'"/> + <xsl:with-param name="iText" select="'KEY'"/> + <xsl:with-param name="iClass" select="'key_title'"/> + </xsl:call-template> + + <rect x="0" + y="16" + width= "{$BLKD_KEY_W}" + height="16" + style="fill:{$COL_BG_LT}; stroke:none;"/> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="ceiling($BLKD_KEY_W div 2)"/> + <xsl:with-param name="iY" select="'30'"/> + <xsl:with-param name="iText" select="'SYMBOLS'"/> + <xsl:with-param name="iClass" select="'key_header'"/> + </xsl:call-template> + + <use x="32" y="47" xlink:href="#KEY_BifLabel" transform="scale(0.75)"/> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="'12'"/> + <xsl:with-param name="iY" select="'60'"/> + <xsl:with-param name="iText" select="'bus interface'"/> + <xsl:with-param name="iClass" select="'key_label'"/> + </xsl:call-template> + + <use x="20" y="68" xlink:href="#KEY_SharedBus"/> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="'12'"/> + <xsl:with-param name="iY" select="'89'"/> + <xsl:with-param name="iText" select="'shared bus'"/> + <xsl:with-param name="iClass" select="'key_label'"/> + </xsl:call-template> + + +<!-- + ================================== + BUS CONNECTIONS + ================================== +--> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="'110'"/> + <xsl:with-param name="iY" select="'47'"/> + <xsl:with-param name="iText" select="'Bus connections'"/> + <xsl:with-param name="iClass" select="'key_label_ul'"/> + </xsl:call-template> + + <use x="110" y="58" xlink:href="#KEY_busconn_MASTER"/> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="'140'"/> + <xsl:with-param name="iY" select="'72'"/> + <xsl:with-param name="iText" select="'master or initiator'"/> + <xsl:with-param name="iClass" select="'key_label'"/> + </xsl:call-template> + + <use x="110" y="{58 + (($BLKD_BIFC_H + 4) * 1)}" xlink:href="#KEY_busconn_SLAVE"/> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="'140'"/> + <xsl:with-param name="iY" select="(72 + (($BLKD_BIFC_H + 4) * 1))"/> + <xsl:with-param name="iText" select="'slave or target'"/> + <xsl:with-param name="iClass" select="'key_label'"/> + </xsl:call-template> + + <use x="110" y="{58 + (($BLKD_BIFC_H + 4) * 2)}" xlink:href="#KEY_busconn_MASTER_SLAVE"/> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="'140'"/> + <xsl:with-param name="iY" select="(72 + (($BLKD_BIFC_H + 4) * 2))"/> + <xsl:with-param name="iText" select="'master slave'"/> + <xsl:with-param name="iClass" select="'key_label'"/> + </xsl:call-template> + + + <use x="110" y="{58 + (($BLKD_BIFC_H + 4) * 3)}" xlink:href="#KEY_busconn_MONITOR"/> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="'140'"/> + <xsl:with-param name="iY" select="(72 + (($BLKD_BIFC_H + 4) * 3))"/> + <xsl:with-param name="iText" select="'monitor'"/> + <xsl:with-param name="iClass" select="'key_label'"/> + </xsl:call-template> + +<!-- + ================================== + EXTERNAL PORTS + ================================== +--> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="'258'"/> + <xsl:with-param name="iY" select="'47'"/> + <xsl:with-param name="iText" select="'External Ports'"/> + <xsl:with-param name="iClass" select="'key_label_ul'"/> + </xsl:call-template> + + <use x="258" y="58" xlink:href="#KEY_INPort"/> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="'288'"/> + <xsl:with-param name="iY" select="'72'"/> + <xsl:with-param name="iText" select="'input'"/> + <xsl:with-param name="iClass" select="'key_label'"/> + </xsl:call-template> + + <use x="258" y="{58 + ($BLKD_IOP_H * 1) + 4}" xlink:href="#KEY_OUTPort"/> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="'288'"/> + <xsl:with-param name="iY" select="(72 + ($BLKD_IOP_H * 1) + 4)"/> + <xsl:with-param name="iText" select="'output'"/> + <xsl:with-param name="iClass" select="'key_label'"/> + </xsl:call-template> + + <use x="258" y="{58 + ($BLKD_IOP_H * 2) + 8}" xlink:href="#KEY_INOUTPort"/> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="'288'"/> + <xsl:with-param name="iY" select="(72 + ($BLKD_IOP_H * 2) + 8)"/> + <xsl:with-param name="iText" select="'inout'"/> + <xsl:with-param name="iClass" select="'key_label'"/> + </xsl:call-template> + + +<!-- + ================================== + INTERRUPTS + ================================== +--> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="'380'"/> + <xsl:with-param name="iY" select="'47'"/> + <xsl:with-param name="iText" select="'Interrupts'"/> + <xsl:with-param name="iClass" select="'key_label_ul'"/> + </xsl:call-template> + + <use x="380" y="58" xlink:href="#KEY_IntrCntrl"/> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="'396'"/> + <xsl:with-param name="iY" select="'64'"/> + <xsl:with-param name="iText" select="'Interrupt'"/> + <xsl:with-param name="iClass" select="'key_label_small'"/> + </xsl:call-template> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="'396'"/> + <xsl:with-param name="iY" select="'74'"/> + <xsl:with-param name="iText" select="'Controller'"/> + <xsl:with-param name="iClass" select="'key_label_small'"/> + </xsl:call-template> + + + <use x="380" y="88" xlink:href="#KEY_IntrdProc"/> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="'396'"/> + <xsl:with-param name="iY" select="'94'"/> + <xsl:with-param name="iText" select="'Interrupt'"/> + <xsl:with-param name="iClass" select="'key_label'"/> + </xsl:call-template> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="'396'"/> + <xsl:with-param name="iY" select="'104'"/> + <xsl:with-param name="iText" select="'Target'"/> + <xsl:with-param name="iClass" select="'key_label_small'"/> + </xsl:call-template> + + + <use x="380" y="118" xlink:href="#KEY_IntrSrc"/> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="'400'"/> + <xsl:with-param name="iY" select="'124'"/> + <xsl:with-param name="iText" select="'Interrupt'"/> + <xsl:with-param name="iClass" select="'key_label_small'"/> + </xsl:call-template> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="'400'"/> + <xsl:with-param name="iY" select="'134'"/> + <xsl:with-param name="iText" select="'Source'"/> + <xsl:with-param name="iClass" select="'key_label_small'"/> + </xsl:call-template> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="'360'"/> + <xsl:with-param name="iY" select="'146'"/> + <xsl:with-param name="iText" select="'X = Controller ID'"/> + <xsl:with-param name="iClass" select="'key_label_small'"/> + </xsl:call-template> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="'360'"/> + <xsl:with-param name="iY" select="'156'"/> + <xsl:with-param name="iText" select="'Y = Interrupt Priority'"/> + <xsl:with-param name="iClass" select="'key_label_small'"/> + </xsl:call-template> + +<!-- + ================================== + COLORS + ================================== +--> + <rect x="0" + y="160" + width= "{$BLKD_KEY_W}" + height="16" + style="fill:{$COL_BG_LT}; stroke:none;"/> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="ceiling($BLKD_KEY_W div 2)"/> + <xsl:with-param name="iY" select="'172'"/> + <xsl:with-param name="iText" select="'COLORS'"/> + <xsl:with-param name="iClass" select="'key_header'"/> + </xsl:call-template> + +<!-- + <text class="keylblul" + x="110" + y="190">Bus Standards</text> +--> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="'110'"/> + <xsl:with-param name="iY" select="'190'"/> + <xsl:with-param name="iText" select="'Bus Standard'"/> + <xsl:with-param name="iClass" select="'key_label'"/> + </xsl:call-template> + + <xsl:variable name="dcr_col_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="'DCR'"/> + </xsl:call-template> + </xsl:variable> + + <rect x="{12 + ((12 + $BLKD_BIFC_W + 36) * 0)}" + y="200" + width= "{$BLKD_BIFC_H}" + height="{$BLKD_BIFC_W}" + style="fill:{$dcr_col_}; stroke:none;"/> + +<!-- + <text class="keylabel" + x="{12 + $BLKD_BIFC_W + 4}" + y="{200 + (($BLKD_BIF_H + 4) * 1)}">DCR</text> +--> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="(12 + $BLKD_BIFC_W + 4)"/> + <xsl:with-param name="iY" select="(200 + (($BLKD_BIF_H + 4) * 1))"/> + <xsl:with-param name="iText" select="'DCR'"/> + <xsl:with-param name="iClass" select="'key_label'"/> + </xsl:call-template> + + <xsl:variable name="fcb_col_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="'FCB'"/> + </xsl:call-template> + </xsl:variable> + + <rect x="{12 + ((12 + $BLKD_BIFC_W + 36) * 0)}" + y="{200 + (($BLKD_BIFC_H + 4) * 1)}" + width= "{$BLKD_BIFC_H}" + height="{$BLKD_BIFC_W}" + style="fill:{$fcb_col_}; stroke:none;"/> + +<!-- + <text class="keylabel" + x="{12 + $BLKD_BIFC_W + 4}" + y="{200 + (($BLKD_BIF_H + 4) * 2)}">FCB</text> +--> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="(12 + $BLKD_BIFC_W + 4)"/> + <xsl:with-param name="iY" select="(200 + (($BLKD_BIF_H + 4) * 2))"/> + <xsl:with-param name="iText" select="'FCB'"/> + <xsl:with-param name="iClass" select="'key_label'"/> + </xsl:call-template> + + <xsl:variable name="fsl_col_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="'FSL'"/> + </xsl:call-template> + </xsl:variable> + + <rect x="{12 + ((12 + $BLKD_BIFC_W + 36) * 1)}" + y="200" + width= "{$BLKD_BIFC_H}" + height="{$BLKD_BIFC_W}" + style="fill:{$fsl_col_}; stroke:none;"/> +<!-- + <text class="keylabel" + x="{12 + ($BLKD_BIFC_W + 4) + ((12 + $BLKD_BIFC_W + 36) * 1)}" + y="{200 + (($BLKD_BIF_H + 4) * 1)}">FSL</text> +--> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="(12 + ($BLKD_BIFC_W + 4) + ((12 + $BLKD_BIFC_W + 36) * 1))"/> + <xsl:with-param name="iY" select="(200 + (($BLKD_BIF_H + 4) * 1))"/> + <xsl:with-param name="iText" select="'FSL'"/> + <xsl:with-param name="iClass" select="'key_label'"/> + </xsl:call-template> + + <xsl:variable name="col_lmb_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="'LMB'"/> + </xsl:call-template> + </xsl:variable> + + <rect x="{12 + ((12 + $BLKD_BIFC_W + 36) * 1)}" + y="{200 + (($BLKD_BIFC_H + 4) * 1)}" + width= "{$BLKD_BIFC_H}" + height="{$BLKD_BIFC_W}" + style="fill:{$col_lmb_}; stroke:none;"/> +<!-- + <text class="keylabel" + x="{12 + ($BLKD_BIFC_W + 4) + ((12 + $BLKD_BIFC_W + 36) * 1)}" + y="{200 + (($BLKD_BIF_H + 4) * 2)}">LMB</text> +--> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="(12 + ($BLKD_BIFC_W + 4) + ((12 + $BLKD_BIFC_W + 36) * 1))"/> + <xsl:with-param name="iY" select="(200 + (($BLKD_BIF_H + 4) * 2))"/> + <xsl:with-param name="iText" select="'LMB'"/> + <xsl:with-param name="iClass" select="'key_label'"/> + </xsl:call-template> + + <xsl:variable name="opb_col_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="'OPB'"/> + </xsl:call-template> + </xsl:variable> + + <rect + x="{12 + ((12 + $BLKD_BIFC_W + 36) * 2)}" + y="200" + width= "{$BLKD_BIFC_H}" + height="{$BLKD_BIFC_W}" + style="fill:{$opb_col_}; stroke:none;"/> +<!-- + <text class="keylabel" + x="{12 + ($BLKD_BIFC_W + 4) + ((12 + $BLKD_BIFC_W + 36) * 2)}" + y="{200 + (($BLKD_BIF_H + 4) * 1)}">OPB</text> +--> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="(12 + ($BLKD_BIFC_W + 4) + ((12 + $BLKD_BIFC_W + 36) * 2))"/> + <xsl:with-param name="iY" select="(200 + (($BLKD_BIF_H + 4) * 1))"/> + <xsl:with-param name="iText" select="'OPB'"/> + <xsl:with-param name="iClass" select="'key_label'"/> + </xsl:call-template> + + <xsl:variable name="plb_col_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="'PLB'"/> + </xsl:call-template> + </xsl:variable> + <rect + x="{12 + ((12 + $BLKD_BIFC_W + 36) * 2)}" + y="{200 + (($BLKD_BIFC_H + 4) * 1)}" + width= "{$BLKD_BIFC_H}" + height="{$BLKD_BIFC_W}" + style="fill:{$plb_col_}; stroke:none;"/> +<!-- + <text class="keylabel" + x="{12 + ($BLKD_BIFC_W + 4) + ((12 + $BLKD_BIFC_W + 36) * 2)}" + y="{200 + (($BLKD_BIF_H + 4) * 2)}">PLB</text> +--> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="(12 + ($BLKD_BIFC_W + 4) + ((12 + $BLKD_BIFC_W + 36) * 2))"/> + <xsl:with-param name="iY" select="(200 + (($BLKD_BIF_H + 4) * 2))"/> + <xsl:with-param name="iText" select="'PLB'"/> + <xsl:with-param name="iClass" select="'key_header'"/> + </xsl:call-template> + + + <xsl:variable name="ocm_col_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="'OCM'"/> + </xsl:call-template> + </xsl:variable> + + <rect + x="{12 + ((12 + $BLKD_BIFC_W + 36) * 3)}" + y="200" + width= "{$BLKD_BIFC_H}" + height="{$BLKD_BIFC_W}" + style="fill:{$ocm_col_}; stroke:none;"/> +<!-- + <text class="keylabel" + x="{12 + ($BLKD_BIFC_W + 4) + ((12 + $BLKD_BIFC_W + 36) * 3)}" + y="{200 + (($BLKD_BIF_H + 4) * 1)}">SOCM</text> + --> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="(12 + ($BLKD_BIFC_W + 4) + ((12 + $BLKD_BIFC_W + 36) * 3))"/> + <xsl:with-param name="iY" select="(200 + (($BLKD_BIF_H + 4) * 1))"/> + <xsl:with-param name="iText" select="'SOCM'"/> + <xsl:with-param name="iClass" select="'key_label'"/> + </xsl:call-template> + + + <xsl:variable name="xil_p2p_col_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="'XIL'"/> + </xsl:call-template> + </xsl:variable> + + <rect + x="{12 + ((12 + $BLKD_BIFC_W + 36) * 3)}" + y="{200 + (($BLKD_BIFC_H + 4) * 1)}" + width= "{$BLKD_BIFC_H}" + height="{$BLKD_BIFC_W}" + style="fill:{$xil_p2p_col_}; stroke:none;"/> +<!-- + <text class="keylabel" + x="{12 + ($BLKD_BIFC_W + 4) + ((12 + $BLKD_BIFC_W + 36) * 3)}" + y="{200 + (($BLKD_BIF_H + 4) * 2)}">Xilinx P2P</text> +--> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="(12 + ($BLKD_BIFC_W + 4) + ((12 + $BLKD_BIFC_W + 36) * 3))"/> + <xsl:with-param name="iY" select="(200 + (($BLKD_BIF_H + 4) * 2))"/> + <xsl:with-param name="iText" select="'Xilinx P2P'"/> + <xsl:with-param name="iClass" select="'key_label'"/> + </xsl:call-template> + + + <xsl:variable name="user_p2p_col_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="'USER'"/> + </xsl:call-template> + </xsl:variable> + + <rect x="{12 + ((12 + $BLKD_BIFC_W + 36) * 4)}" + y="200" + width= "{$BLKD_BIFC_H}" + height="{$BLKD_BIFC_W}" + style="fill:{$user_p2p_col_}; stroke:none;"/> +<!-- + <text class="keylabel" + x="{12 + ($BLKD_BIFC_W + 4) + ((12 + $BLKD_BIFC_W + 36) * 4)}" + y="{200 + (($BLKD_BIF_H + 4) * 1)}">USER P2P</text> +--> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="(12 + ($BLKD_BIFC_W + 4) + ((12 + $BLKD_BIFC_W + 36) * 4))"/> + <xsl:with-param name="iY" select="(200 + (($BLKD_BIF_H + 4) * 1))"/> + <xsl:with-param name="iText" select="'USER P2P'"/> + <xsl:with-param name="iClass" select="'key_label'"/> + </xsl:call-template> + + +</g> +</xsl:template> + +<xsl:template name="Define_BlkDiagram_Specs"> + + <xsl:param name="iArch" select="'NA'"/> + <xsl:param name="iPart" select="'NA'"/> + <xsl:param name="iTimeStamp" select="'NA'"/> + <xsl:param name="iEdkVersion" select="'NA'"/> + + <g id="BlkDiagram_Specs"> + <rect + x="0" + y="0" + width= "{$BLKD_SPECS_W}" + height="{$BLKD_SPECS_H}" + style="fill:{$COL_BG}; stroke:none;"/> + + <rect + x="0" + y="0" + width= "{$BLKD_SPECS_W}" + height="16" + style="fill:{$COL_BG}; stroke:none;"/> +<!-- + ================================== + SPEC HEADER + ================================== +--> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iClass" select="'key_title'"/> + <xsl:with-param name="iX" select="ceiling($BLKD_SPECS_W div 2)"/> + <xsl:with-param name="iY" select="'14'"/> + <xsl:with-param name="iText" select="'SPECS'"/> + </xsl:call-template> +<!-- + <text class="keytitle" + x="{ceiling($BLKD_SPECS_W div 2)} " + y="14">SPECS</text> +--> + +<!-- + ================================== + EDK VERSION + ================================== +--> + <rect x="0" + y="20" + width= "{$BLKD_SPECS_W}" + height="16" + style="fill:{$COL_BG_LT}; stroke:none;"/> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iClass" select="'blkd_spec_name'"/> + <xsl:with-param name="iX" select="'4'"/> + <xsl:with-param name="iY" select="'32'"/> + <xsl:with-param name="iText" select="'EDK VERSION'"/> + </xsl:call-template> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iClass" select="'blkd_spec_value_mid'"/> + <xsl:with-param name="iX" select="($BLKD_SPECS_W + 1) - ceiling($BLKD_SPECS_W div 5)"/> + <xsl:with-param name="iY" select="'32'"/> + <xsl:with-param name="iText" select="$iEdkVersion"/> + </xsl:call-template> + +<!-- + ================================== + ARCH + ================================== +--> + <rect x="0" + y="40" + width= "{$BLKD_SPECS_W}" + height="16" + style="fill:{$COL_BG_LT}; stroke:none;"/> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iClass" select="'blkd_spec_name'"/> + <xsl:with-param name="iX" select="'4'"/> + <xsl:with-param name="iY" select="'52'"/> + <xsl:with-param name="iText" select="'ARCH'"/> + </xsl:call-template> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iClass" select="'blkd_spec_value_mid'"/> + <xsl:with-param name="iX" select="($BLKD_SPECS_W + 1) - ceiling($BLKD_SPECS_W div 5)"/> + <xsl:with-param name="iY" select="'52'"/> + <xsl:with-param name="iText" select="$iArch"/> + </xsl:call-template> + +<!-- + <text class="specsvalue" + x="{($BLKD_SPECS_W + 1) - (string-length($blkd_arch) * 6.5)}" + y="52"><xsl:value-of select="$blkd_arch"/></text> + <text class="specsvaluemid" + x="{($BLKD_SPECS_W + 1) - ceiling($BLKD_SPECS_W div 5)}" + y="52"><xsl:value-of select="$iArch"/></text> +--> + +<!-- + ================================== + PART + ================================== +--> + <rect x="0" + y="60" + width= "{$BLKD_SPECS_W}" + height="16" + style="fill:{$COL_BG_LT}; stroke:none;"/> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iClass" select="'blkd_spec_name'"/> + <xsl:with-param name="iX" select="'4'"/> + <xsl:with-param name="iY" select="'72'"/> + <xsl:with-param name="iText" select="'PART'"/> + </xsl:call-template> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iClass" select="'blkd_spec_value_mid'"/> + <xsl:with-param name="iX" select="($BLKD_SPECS_W + 1) - ceiling($BLKD_SPECS_W div 5)"/> + <xsl:with-param name="iY" select="'72'"/> + <xsl:with-param name="iText" select="$iPart"/> + </xsl:call-template> + +<!-- + ================================== + TIMESTAMP + ================================== +--> + + <rect x="0" + y="80" + width= "{$BLKD_SPECS_W}" + height="16" + style="fill:{$COL_BG_LT}; stroke:none;"/> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iClass" select="'blkd_spec_name'"/> + <xsl:with-param name="iX" select="'4'"/> + <xsl:with-param name="iY" select="'92'"/> + <xsl:with-param name="iText" select="'GENERATED'"/> + </xsl:call-template> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iClass" select="'blkd_spec_value_mid'"/> + <xsl:with-param name="iX" select="($BLKD_SPECS_W + 1) - (string-length($iTimeStamp) * 3.5)"/> + <xsl:with-param name="iY" select="'92'"/> + <xsl:with-param name="iText" select="$iTimeStamp"/> + </xsl:call-template> + </g> +</xsl:template> + + +</xsl:stylesheet> + +<!-- =========================================================================== --> +<!-- FUNCTION TEMPLATE --> +<!-- --> +<!-- =========================================================================== -->
\ No newline at end of file diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtTinySvgBLKD_Peripherals.xsl b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtTinySvgBLKD_Peripherals.xsl new file mode 100644 index 000000000..d4c458d2e --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtTinySvgBLKD_Peripherals.xsl @@ -0,0 +1,1582 @@ +<?xml version="1.0" standalone="no"?> + +<xsl:stylesheet version="1.0" + xmlns:svg="http://www.w3.org/2000/svg" + xmlns:xsl="http://www.w3.org/1999/XSL/Transform" + xmlns:math="http://exslt.org/math" + xmlns:exsl="http://exslt.org/common" + xmlns:xlink="http://www.w3.org/1999/xlink" + extension-element-prefixes="math"> + +<xsl:output method="xml" version="1.0" encoding="UTF-8" indent="yes" + doctype-public="-//W3C//DTD SVG 1.0//EN" + doctype-system="http://www.w3.org/TR/SVG/DTD/svg10.dtd"/> + +<!-- +<xsl:variable name="INF_H" select="$BIF_H + ceiling($BIF_H div 2)"/> +<xsl:variable name="INF_W" select="($BIF_W * 2) + $BIF_GAP"/> +--> + + +<!-- ======================= DEF FUNCTIONS =================================== --> +<xsl:template name="Define_IPBucket"> + + <xsl:for-each select="BLKDIAGRAM/IPBUCKET"> + + <xsl:for-each select="MODULE"> + <xsl:sort data-type="text" select="@MODTYPE" order="ascending"/> + + <xsl:call-template name="Define_IPBucketModule"> + <xsl:with-param name="iIPType" select="@MODTYPE"/> + <xsl:with-param name="iIPName" select="@INSTANCE"/> + </xsl:call-template> + + </xsl:for-each> + + <g id="ipbucket"> + <xsl:variable name="bucket_w_" select="(($BLKD_MOD_BKTLANE_W * 2) + (($BLKD_MOD_W * @MODS_W) + ($BLKD_MOD_BUCKET_G * (@MODS_W - 1))))"/> + <xsl:variable name="bucket_h_" select="(($BLKD_MOD_BKTLANE_H * 2) + (($BLKD_MOD_H * @MODS_H) + ($BLKD_MOD_BUCKET_G * (@MODS_H - 1))))"/> + + <rect x="0" + y="0" + rx="4" + ry="4" + width= "{$bucket_w_}" + height="{$bucket_h_}" + style="stroke-width:2; stroke:{$COL_BLACK}; fill:{$COL_IORING_LT}"/> + + <xsl:variable name="bkt_mods_w_" select="@MODS_W"/> + + <xsl:for-each select="MODULE"> + + <xsl:variable name="clm_" select="(( position() - 1) mod $bkt_mods_w_)"/> + <xsl:variable name="row_" select="floor((position() - 1) div $bkt_mods_w_)"/> + + <xsl:variable name="bk_x_" select="$BLKD_MOD_BKTLANE_W + ($clm_ * ($BLKD_MOD_W + $BLKD_MOD_BUCKET_G))"/> + <xsl:variable name="bk_y_" select="$BLKD_MOD_BKTLANE_H + ($row_ * ($BLKD_MOD_H + $BLKD_MOD_BUCKET_G))"/> + + + <use x="{$bk_x_}" + y="{$bk_y_}" + xlink:href="#ipbktmodule_{@INSTANCE}"/> + + + </xsl:for-each> + + </g> + +</xsl:for-each> +</xsl:template> + + +<xsl:template name="Define_UNKBucket"> + + <xsl:for-each select="BLKDIAGRAM/UNKBUCKET"> + + <g id="unkbucket"> + <xsl:variable name="bucket_w_" select="(($BLKD_MOD_BKTLANE_W * 2) + (($BLKD_MOD_W * @MODS_W) + ($BLKD_MOD_BUCKET_G * (@MODS_W - 1))))"/> + <xsl:variable name="bucket_h_" select="(($BLKD_MOD_BKTLANE_H * 2) + (($BLKD_MOD_H * @MODS_H) + ($BLKD_MOD_BUCKET_G * (@MODS_H - 1))))"/> + + <rect x="0" + y="0" + rx="4" + ry="4" + width= "{$bucket_w_}" + height="{$bucket_h_}" + style="stroke-width:2; stroke:{$COL_BLACK}; fill:{$COL_BG_UNK}"/> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@IS_PROMOTED and @IS_PENALIZED)]"> + + <xsl:variable name="bkt_mods_w_" select="@MODS_W"/> + + <xsl:variable name="mod_row_" select="@BKTROW"/> + <xsl:variable name="row_mods_h_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/UNKBUCKET/BKTROW[(@INDEX = $mod_row_)]/@MODS_H"/> + +<!-- + <xsl:message>The row module is <xsl:value-of select="@BKTROW"/></xsl:message> + <xsl:message>The height of the module is <xsl:value-of select="$row_mods_h_"/></xsl:message> +--> + + <xsl:variable name="bk_x_" select="$BLKD_MOD_BKTLANE_W + (@MODS_X * ($BLKD_MOD_W + $BLKD_MOD_BUCKET_G))"/> + <xsl:variable name="bk_y_" select="$BLKD_MOD_BKTLANE_H + ($row_mods_h_ * ($BLKD_MOD_H + $BLKD_MOD_BUCKET_G))"/> + + <use x="{$bk_x_}" + y="{$bk_y_}" + xlink:href="#symbol_unkmodule_{@BKTROW}_{@MODS_X}"/> +<!-- +--> + + </xsl:for-each> + + + </g> + + </xsl:for-each> +</xsl:template> + + +<xsl:template name="Define_SBSBuckets"> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET"> + + <xsl:variable name="busStd_" select="@BUSSTD"/> + <xsl:variable name="busName_" select="@BUSNAME"/> +<!-- + <xsl:variable name="busStd_" select="BUSCONNS/BUSCONN/@BUSSTD"/> +--> + <xsl:variable name="bus_conn_w_" select="BUSCONNS/@BUSLANE_W"/> + + + <xsl:variable name="bktColor_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="$busStd_"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="bktBgColor_"> + <xsl:call-template name="F_BusStd2RGB_LT"> + <xsl:with-param name="iBusStd" select="$busStd_"/> + </xsl:call-template> + </xsl:variable> + + + <xsl:for-each select="MODULE"> + + <xsl:sort data-type="text" select="@MODTYPE" order="ascending"/> + + <xsl:call-template name="Define_SBSBucketModule"> + <xsl:with-param name="iBifType" select="$busStd_"/> + <xsl:with-param name="iIPType" select="@MODTYPE"/> + <xsl:with-param name="iIPName" select="@INSTANCE"/> + </xsl:call-template> + + </xsl:for-each> + + <g id="sbsbucket_{$busName_}"> + <xsl:variable name="bucket_w_" select="(($BLKD_MOD_BKTLANE_W * 2) + (($BLKD_MOD_W * @MODS_W) + ($BLKD_MOD_BUCKET_G * (@MODS_W - 1))))"/> + <xsl:variable name="bucket_h_" select="(($BLKD_MOD_BKTLANE_H * 2) + ((($BLKD_MOD_H + $BLKD_BIFC_H) * @MODS_H) + ($BLKD_MOD_BUCKET_G * (@MODS_H - 1))))"/> + + <rect x="0" + y="0" + rx="4" + ry="4" + width= "{$bucket_w_}" + height="{$bucket_h_}" + style="stroke-width:2; stroke:{$bktColor_}; fill:{$bktBgColor_}"/> + + <xsl:variable name="bkt_mods_w_" select="@MODS_W"/> + + <xsl:for-each select="MODULE"> + + <xsl:sort data-type="text" select="@MODTYPE" order="ascending"/> + + <xsl:variable name="clm_" select="(( position() - 1) mod $bkt_mods_w_)"/> + <xsl:variable name="row_" select="floor((position() - 1) div $bkt_mods_w_)"/> + + <xsl:variable name="bk_x_" select="$BLKD_MOD_BKTLANE_W + ($clm_ * ($BLKD_MOD_W + $BLKD_MOD_BUCKET_G))"/> + <xsl:variable name="bk_y_" select="$BLKD_MOD_BKTLANE_H + ($row_ * ($BLKD_MOD_H + $BLKD_BIFC_H + $BLKD_MOD_BUCKET_G))"/> + + <!-- Lay out the module in the bucket --> + <use x="{$bk_x_}" y="{$bk_y_}" xlink:href="#sbsbktmodule_{@INSTANCE}"/> + + <!-- Add its connection to the piece shared bus --> + <xsl:variable name="h_bus_y_" select="$bk_y_ + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_P2P_BUS_W div 2)"/> + +<!-- + <xsl:variable name="h_bus_x_" select="$bk_x_ - ($BLKD_MOD_BUCKET_G + ceiling($BLKD_MOD_W div 2))"/> +--> + <xsl:variable name="h_bus_x_"> + <xsl:choose> + <xsl:when test="($clm_ = '0')">0</xsl:when> + + <xsl:when test="not($clm_ = '0')"> + <xsl:value-of select="$bk_x_ - ($BLKD_MOD_BUCKET_G + ceiling($BLKD_MOD_W div 2))"/> + </xsl:when> + </xsl:choose> + </xsl:variable> + +<!-- + <xsl:variable name="h_bus_y_" select="$bk_y_ + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_P2P_BUS_W)"/> + <xsl:message>h bus x <xsl:value-of select="$h_bus_x_"/></xsl:message> + <xsl:message>h bus y <xsl:value-of select="$h_bus_y_"/></xsl:message> +--> + <xsl:variable name="h_bus_height_" select="$BLKD_P2P_BUS_W"/> + <xsl:variable name="h_bus_width_" select="($bk_x_ - $h_bus_x_ + ceiling($BLKD_MOD_W div 2))"/> + + <rect x="{$h_bus_x_}" + y="{$h_bus_y_}" + width= "{$h_bus_width_}" + height="{$BLKD_P2P_BUS_W}" + style="fill:{$bktColor_}"/> + + </xsl:for-each> + + <xsl:variable name="num_sbsbktmods_" select="count(MODULE)"/> + <xsl:variable name="num_sbsbktrows_" select="ceiling($num_sbsbktmods_ div $BLKD_BKT_MODS_PER_ROW)"/> + + <!-- If there is more than one row, connect the rows with a vertical bar --> + <xsl:if test="($num_sbsbktrows_ > 1)"> + + <xsl:variable name="v_bus_x_" select="$BLKD_MOD_BKTLANE_W + ($BLKD_MOD_W + $BLKD_MOD_BUCKET_G)"/> + + <xsl:variable name="bkt_top_" select="$BLKD_MOD_BKTLANE_H + (0 * ($BLKD_MOD_H + $BLKD_BIFC_H + $BLKD_MOD_BUCKET_G))"/> + <xsl:variable name="bkt_bot_" select="$BLKD_MOD_BKTLANE_H + (($num_sbsbktrows_ - 1) * ($BLKD_MOD_H + $BLKD_BIFC_H + $BLKD_MOD_BUCKET_G))"/> + + <xsl:variable name="v_bus_y_top_" select="$bkt_top_ + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_P2P_BUS_W div 2)"/> + <xsl:variable name="v_bus_y_bot_" select="$bkt_bot_ + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_P2P_BUS_W div 2)"/> + + <xsl:variable name="v_bus_width_" select="$BLKD_P2P_BUS_W"/> + <xsl:variable name="v_bus_height_" select="($v_bus_y_bot_ - $v_bus_y_top_)"/> + <rect x="0" + y="{$v_bus_y_top_}" + width= "{$v_bus_width_}" + height="{$v_bus_height_}" + style="fill:{$bktColor_}"/> + </xsl:if> + + </g> + + </xsl:for-each> + +</xsl:template> + + +<xsl:template name="Define_SBSBucketModule"> + + <xsl:param name="iBusStd" select="'PLB46'"/> + <xsl:param name="iIPName" select="'_ipType_'"/> + <xsl:param name="iIPType" select="'_ipName_'"/> + +<!-- + <xsl:message>The IPType is <xsl:value-of select="$iIPType"/> </xsl:message> +--> + <xsl:variable name="bif_y_"> + <xsl:value-of select="$BLKD_MOD_LANE_H + $BLKD_BIFC_H"/> + </xsl:variable> + + <xsl:variable name="label_y_"> + <xsl:value-of select="$BLKD_MOD_LANE_H + $BLKD_BIF_H + $BLKD_BIFC_H + $BLKD_MOD_BIF_GAP_V"/> + </xsl:variable> + + <xsl:variable name="modBgColor_"> + <xsl:choose> + <xsl:when test="$iIPType = 'mpmc'"><xsl:value-of select="$COL_MPMC_BG"/></xsl:when> + <xsl:otherwise><xsl:value-of select="$COL_BG"/></xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <g id="sbsbktmodule_{$iIPName}"> + + <rect x="0" + y="{$BLKD_BIFC_H}" + rx="6" + ry="6" + width = "{$BLKD_MOD_W}" + height= "{$BLKD_MOD_H}" + style="fill:{$modBgColor_}; stroke:{$COL_WHITE}; stroke-width:2"/> + + <rect x="{ceiling($BLKD_MOD_W div 2) - ceiling($BLKD_MOD_LABEL_W div 2)}" + y="{$label_y_}" + rx="3" + ry="3" + width= "{$BLKD_MOD_LABEL_W}" + height="{$BLKD_MOD_LABEL_H}" + style="fill:{$COL_WHITE}; stroke:none;"/> + + <xsl:if test="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE=$iIPName)]/@GROUP"> + + <rect x="{ceiling($BLKD_MOD_W div 2) - ceiling($BLKD_MOD_LABEL_W div 2)}" + y="{$label_y_ + $BLKD_BIF_H + ceiling($BLKD_BIF_H div 3) - 2}" + rx="3" + ry="3" + width= "{$BLKD_MOD_LABEL_W}" + height="{$BLKD_BIF_H}" + style="fill:{$COL_IORING_LT}; stroke:none;"/> + +<!-- + <text class="ioplblgrp" + x="{ceiling($BLKD_MOD_W div 2)}" + y="{$label_y_ + $BLKD_BIF_H + ceiling($BLKD_BIF_H div 3) + 12}"> + <xsl:value-of select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iIPName)]/@GROUP"/> + </text> +--> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="ceiling($BLKD_MOD_W div 2)"/> + <xsl:with-param name="iY" select="($label_y_ + $BLKD_BIF_H + ceiling($BLKD_BIF_H div 3) + 12)"/> + <xsl:with-param name="iText" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iIPName)]/@GROUP"/> + <xsl:with-param name="iClass" select="'iogrp_label'"/> + </xsl:call-template> + + </xsl:if> + +<!-- + <text class="bciptype" + x="{ceiling($BLKD_MOD_W div 2)}" + y="{$label_y_ + 8}"> + <xsl:value-of select="$iIPType"/> + </text> + + <text class="bciplabel" + x="{ceiling($BLKD_MOD_W div 2)}" + y="{$label_y_ + 16}"> + <xsl:value-of select="$iIPName"/> + </text> +--> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="ceiling($BLKD_MOD_W div 2)"/> + <xsl:with-param name="iY" select="($label_y_ + 8)"/> + <xsl:with-param name="iText" select="$iIPType"/> + <xsl:with-param name="iClass" select="'bc_iptype'"/> + </xsl:call-template> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="ceiling($BLKD_MOD_W div 2)"/> + <xsl:with-param name="iY" select="($label_y_ + 18)"/> + <xsl:with-param name="iText" select="$iIPName"/> + <xsl:with-param name="iClass" select="'bc_ipinst'"/> + </xsl:call-template> + + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iIPName)]/BUSINTERFACE[(@IS_INMHS = 'TRUE')]"> + + <xsl:variable name="bifBusStd_"> + <xsl:choose> + <xsl:when test="@BUSSTD"> + <xsl:value-of select="@BUSSTD"/> + </xsl:when> + <xsl:otherwise> + <xsl:value-of select="'USER'"/> + </xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="bifName_"> + <xsl:choose> + <xsl:when test="string-length(@NAME) <= 5"> + <xsl:value-of select="@NAME"/> + </xsl:when> + <xsl:otherwise> + <xsl:value-of select="substring(@NAME,0,5)"/> + </xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="bif_x_" select="ceiling($BLKD_MOD_W div 2) - ceiling($BLKD_BIF_W div 2)"/> + + <!-- Draw the BIF --> + <use x="{$bif_x_}" y="{$bif_y_}" xlink:href="#{$bifBusStd_}_BifLabel"/> + + + <!-- Draw the BIF connection --> + <use x="{$bif_x_ + ceiling($BLKD_BIF_W div 2) - ceiling($BLKD_BIFC_W div 2)}" y="{$bif_y_ - $BLKD_BIFC_H - $BLKD_MOD_LANE_H}" xlink:href="#{$bifBusStd_}_busconn_{@TYPE}"/> + +<!-- + <text class="bif_label" + x="{$bif_x_ + ceiling($BLKD_BIF_W div 2)}" + y="{$bif_y_ + ceiling($BLKD_BIF_H div 2) + 3}"> + <xsl:value-of select="$bifName_"/> + </text> +--> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="($bif_x_ + ceiling($BLKD_BIF_W div 2))"/> + <xsl:with-param name="iY" select="($bif_y_ + ceiling($BLKD_BIF_H div 2) + 3)"/> + <xsl:with-param name="iText" select="$bifName_"/> + <xsl:with-param name="iClass" select="'bif_label'"/> + </xsl:call-template> + + </xsl:for-each> + + <xsl:if test="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iIPName)]/INTERRUPTINFO[(@TYPE = 'CONTROLLER')]"> + + <xsl:variable name="intcIdx_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE=$iIPName)]/INTERRUPTINFO[(@TYPE = 'CONTROLLER')]/@INTC_INDEX"/> + + <xsl:variable name="intrColor_"> + <xsl:call-template name="F_IntcIdx2RGB"> + <xsl:with-param name="iIntcIdx" select="$intcIdx_"/> + </xsl:call-template> + </xsl:variable> + + <xsl:call-template name="F_draw_InterruptCntrl"> + <xsl:with-param name="iIntr_X" select="($BLKD_MOD_W - ceiling($BLKD_INTR_W div 2))"/> + <xsl:with-param name="iIntr_Y" select="3 + $BLKD_BIFC_H"/> + <xsl:with-param name="iIntr_COL" select="$intrColor_"/> + <xsl:with-param name="iIntr_IDX" select="$intcIdx_"/> + </xsl:call-template> + </xsl:if> + + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iIPName)]/INTERRUPTINFO[(@TYPE = 'SOURCE')]/TARGET"> +<!-- + <xsl:variable name="intcIdx_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE=$iIPName)]/INTERRUPTINFO[(@TYPE = 'SOURCE')]/@INTC_INDEX"/> +--> + <xsl:variable name="intrColor_"> + <xsl:call-template name="F_IntcIdx2RGB"> + <xsl:with-param name="iIntcIdx" select="@INTC_INDEX"/> + </xsl:call-template> + </xsl:variable> + + <xsl:call-template name="F_draw_InterruptSource"> + <xsl:with-param name="iIntr_X" select="($BLKD_MOD_W - $BLKD_INTR_W)"/> + <xsl:with-param name="iIntr_Y" select="((position() - 1) * (ceiling($BLKD_INTR_H div 2) + 3)) + $BLKD_BIFC_H"/> + <xsl:with-param name="iIntr_COL" select="$intrColor_"/> + <xsl:with-param name="iIntr_PRI" select="@PRIORITY"/> + <xsl:with-param name="iIntr_IDX" select="@INTC_INDEX"/> + </xsl:call-template> + + </xsl:for-each> + + </g> + +</xsl:template> + +<xsl:template name="Define_IPBucketModule"> + + <xsl:param name="iIPType" select="'_ip_type_'"/> + <xsl:param name="iIPName" select="'_ip_name_'"/> + + <xsl:variable name="bif_y_"> + <xsl:value-of select="$BLKD_MOD_LANE_H"/> + </xsl:variable> + + <xsl:variable name="label_y_"> + <xsl:value-of select="(ceiling($BLKD_MOD_H div 2) - ceiling($BLKD_MOD_LABEL_H div 2))"/> + </xsl:variable> + + <g id="ipbktmodule_{$iIPName}"> + + <rect x="0" + y="0" + rx="6" + ry="6" + width = "{$BLKD_MOD_W}" + height= "{$BLKD_MOD_H}" + style="fill:{$COL_BG}; stroke:{$COL_BLACK}; stroke-width:2"/> + + <rect x="{ceiling($BLKD_MOD_W div 2) - ceiling($BLKD_MOD_LABEL_W div 2)}" + y="{$label_y_}" + rx="3" + ry="3" + width= "{$BLKD_MOD_LABEL_W}" + height="{$BLKD_MOD_LABEL_H}" + style="fill:{$COL_WHITE}; stroke:none;"/> +<!-- + y="{$label_y_ + ceiling($BLKD_MOD_LABEL_H div 2) - 4}" + y="{$label_y_ + ceiling($BLKD_MOD_LABEL_H div 2) + 4}" +--> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="ceiling($BLKD_MOD_W div 2)"/> + <xsl:with-param name="iY" select="($label_y_ + 8)"/> + <xsl:with-param name="iText" select="$iIPType"/> + <xsl:with-param name="iClass" select="'bc_iptype'"/> + </xsl:call-template> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="ceiling($BLKD_MOD_W div 2)"/> + <xsl:with-param name="iY" select="($label_y_ + 20)"/> + <xsl:with-param name="iText" select="$iIPName"/> + <xsl:with-param name="iClass" select="'bc_ipinst'"/> + </xsl:call-template> + +<!-- + <text class="bc_iptype" + x="{ceiling($BLKD_MOD_W div 2)}" + y="{$label_y_ + 8}"> + <xsl:value-of select="$iIPType"/> + </text> + + <text class="bc_ipinst" + x="{ceiling($BLKD_MOD_W div 2)}" + y="{$label_y_ + 16}"> + <xsl:value-of select="$iIPName"/> + </text> +--> + + <xsl:if test="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iIPName)]/@GROUP"> + + <rect x="{ceiling($BLKD_MOD_W div 2) - ceiling($BLKD_MOD_LABEL_W div 2)}" + y="{$label_y_ + $BLKD_BIF_H + ceiling($BLKD_BIF_H div 3) - 2}" + rx="3" + ry="3" + width= "{$BLKD_MOD_LABEL_W}" + height="{$BLKD_BIF_H}" + style="fill:{$COL_IORING_LT}; stroke:none;"/> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="ceiling($BLKD_MOD_W div 2)"/> + <xsl:with-param name="iY" select="($label_y_ + $BLKD_BIF_H + ceiling($BLKD_BIF_H div 3) + 12)"/> + <xsl:with-param name="iText" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iIPName)]/@GROUP"/> + <xsl:with-param name="iClass" select="'iogrp_label'"/> + </xsl:call-template> + + <!-- + <text class="iogrp_label" + x="{ceiling($BLKD_MOD_W div 2)}" + y="{$label_y_ + $BLKD_BIF_H + ceiling($BLKD_BIF_H div 3) + 12}"> + <xsl:value-of select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iIPName)]/@GROUP"/> + </text> + --> + + </xsl:if> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iIPName)]/INTERRUPTINFO[(@TYPE = 'SOURCE')]"> + + <xsl:variable name="intrColor_"> + <xsl:call-template name="F_IntcIdx2RGB"> + <xsl:with-param name="iIntcIdx" select="@INTC_INDEX"/> + </xsl:call-template> + </xsl:variable> + + <xsl:call-template name="F_draw_InterruptSource"> + <xsl:with-param name="iIntr_X" select="($BLKD_MOD_W - $BLKD_INTR_W)"/> + <xsl:with-param name="iIntr_Y" select="((position() - 1) * (ceiling($BLKD_INTR_H div 2) + 3))"/> + <xsl:with-param name="iIntr_COL" select="$intrColor_"/> + <xsl:with-param name="iIntr_PRI" select="@PRIORITY"/> + <xsl:with-param name="iIntr_IDX" select="@INTC_INDEX"/> + </xsl:call-template> + + </xsl:for-each> + + </g> + +</xsl:template> + + +<xsl:template name="Define_Peripheral"> +<!-- + when the module is oriented normal its label goes above the bifs + when the module is oriented rot180, (part of a processor memory + controller for example) its label goes below the bifs +--> + + <xsl:param name="iModVori" select="'normal'"/> + <xsl:param name="iModInst" select="'_instance_'"/> + <xsl:param name="iModType" select="'_modtype_'"/> + <xsl:param name="iUnkInst" select="'_unknown_'"/> + <xsl:param name="iHorizIdx" select="'_unknown_'"/> + <xsl:param name="iVertiIdx" select="'_unknown_'"/> + +<!-- + <xsl:message>Stack Y <xsl:value-of select="$cstkMods_Y"/></xsl:message> + <xsl:message>Stack Index Y <xsl:value-of select="$cstkIndex"/></xsl:message> +--> + + <xsl:variable name="modName_"> + <xsl:choose> + <xsl:when test="$iUnkInst = '_unknown_'"> + <xsl:value-of select="$iModInst"/> + </xsl:when> + <xsl:otherwise> + <xsl:value-of select="$iUnkInst"/> + </xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="modSymbolName_"> + <xsl:choose> + <xsl:when test="(not($iHorizIdx = '_unknown_') and not($iVertiIdx = '_unknown_'))"> + <xsl:call-template name="F_generate_Stack_SymbolName"> + <xsl:with-param name="iHorizIdx" select="$iHorizIdx"/> + <xsl:with-param name="iVertiIdx" select="$iVertiIdx"/> + </xsl:call-template> + </xsl:when> + <xsl:otherwise>symbol_<xsl:value-of select="$modName_"/></xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="modTypeName_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iModInst)]/@MODTYPE"/> + +<!-- + <xsl:message>The symbol type of the module is <xsl:value-of select="$modTypeName_"/></xsl:message> + <xsl:message>The symbol name of the module is <xsl:value-of select="$modSymbolName_"/></xsl:message> +--> + + <xsl:variable name="bifs_h_"> + <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE/MODULE[(@INSTANCE = $iModInst)]/@BIFS_H) and not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/BRIDGESHAPES/MODULE[(@INSTANCE = $iModInst)]/@BIFS_H)">0</xsl:if> + + <xsl:if test="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE/MODULE[(@INSTANCE = $iModInst)]/@BIFS_H)"> + <xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE/MODULE[(@INSTANCE = $iModInst)]/@BIFS_H"/> + </xsl:if> + + <xsl:if test="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/BRIDGESHAPES/MODULE[(@INSTANCE = $iModInst)]/@BIFS_H)"> + <xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BRIDGESHAPES/MODULE[(@INSTANCE = $iModInst)]/@BIFS_H"/> + </xsl:if> + </xsl:variable> + + <xsl:variable name="label_y_"> + <xsl:choose> + <xsl:when test="$iModVori = 'rot180'"> + <xsl:value-of select="($BLKD_MOD_LANE_H + (($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * $bifs_h_))"/> + </xsl:when> + <xsl:otherwise> + <xsl:value-of select="$BLKD_MOD_LANE_H"/> + </xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="bif_dy_"> + <xsl:choose> + <xsl:when test="$iModVori = 'rot180'"> + <xsl:value-of select="$BLKD_MOD_LANE_H"/> + </xsl:when> + <xsl:otherwise> + <xsl:value-of select="($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V)"/> + </xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="peri_stroke_col_"> + <xsl:choose> + <xsl:when test="((@MODCLASS = 'MASTER_SLAVE') or (@MODCLASS = 'MONITOR')) and BUSCONNS/BUSCONN"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="BUSCONNS/BUSCONN/@BUSSTD"/> + </xsl:call-template> + </xsl:when> + + <xsl:otherwise> + <xsl:value-of select="$COL_WHITE"/> + </xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="modHeight_"> + <xsl:call-template name="F_Calc_PeriShape_Height"> + <xsl:with-param name="iShapeInst" select="$modName_"/> + </xsl:call-template> + </xsl:variable> + + <g id="{$modSymbolName_}"> + + <xsl:if test="$modTypeName_ = 'mpmc'"> + <rect x="0" + y="0" + rx="6" + ry="6" + width = "{$BLKD_MOD_W}" + height= "{$modHeight_}" + style="fill:{$COL_MPMC_BG}; stroke:{$peri_stroke_col_}; stroke-width:2"/> + </xsl:if> + + <xsl:if test="not($modTypeName_ = 'mpmc')"> + <rect x="0" + y="0" + rx="6" + ry="6" + width = "{$BLKD_MOD_W}" + height= "{$modHeight_}" + style="fill:{$COL_BG}; stroke:{$peri_stroke_col_}; stroke-width:2"/> + </xsl:if> + + + <rect x="{ceiling($BLKD_MOD_W div 2) - ceiling($BLKD_MOD_LABEL_W div 2)}" + y="{$label_y_}" + rx="3" + ry="3" + width= "{$BLKD_MOD_LABEL_W}" + height="{$BLKD_MOD_LABEL_H}" + style="fill:{$COL_WHITE}; stroke:none;"/> + +<!-- + y="{$label_y_ + ceiling($BLKD_MOD_LABEL_H div 2) - 4}"> + y="{$label_y_ + ceiling($BLKD_MOD_LABEL_H div 2) + 4}"> +--> +<!-- + <text class="bc_iptype" + x="{ceiling($BLKD_MOD_W div 2)}" + y="{$label_y_ + 8}"> + <xsl:value-of select="$iModType"/> + </text> + + <text class="bc_ipinst" + x="{ceiling($BLKD_MOD_W div 2)}" + y="{$label_y_ + 16}"> + <xsl:value-of select="$iModInst"/> + </text> +--> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="ceiling($BLKD_MOD_W div 2)"/> + <xsl:with-param name="iY" select="($label_y_ + 8)"/> + <xsl:with-param name="iText" select="$iModType"/> + <xsl:with-param name="iClass" select="'bc_iptype'"/> + </xsl:call-template> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="ceiling($BLKD_MOD_W div 2)"/> + <xsl:with-param name="iY" select="($label_y_ + 16)"/> + <xsl:with-param name="iText" select="$iModInst"/> + <xsl:with-param name="iClass" select="'bc_ipinst'"/> + </xsl:call-template> + + + <xsl:if test="$G_ROOT/EDKSYSTEM/MODULES/MODULE[@INSTANCE=$iModInst]/@GROUP"> + + <rect x="{ceiling($BLKD_MOD_W div 2) - ceiling($BLKD_MOD_LABEL_W div 2)}" + y="{$label_y_ + $BLKD_BIF_H + ceiling($BLKD_BIF_H div 3) - 2}" + rx="3" + ry="3" + width= "{$BLKD_MOD_LABEL_W}" + height="{$BLKD_BIF_H}" + style="fill:{$COL_IORING_LT}; stroke:none;"/> + +<!-- + <text class="iogrp_label" + x="{ceiling($BLKD_MOD_W div 2)}" + y="{$label_y_ + $BLKD_BIF_H + ceiling($BLKD_BIF_H div 3) + 12}"> + <xsl:value-of select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[@INSTANCE=$iModInst]/@GROUP"/> + </text> +--> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="ceiling($BLKD_MOD_W div 2)"/> + <xsl:with-param name="iY" select="($label_y_ + $BLKD_BIF_H + ceiling($BLKD_BIF_H div 3) + 12)"/> + <xsl:with-param name="iText" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iModInst)]/@GROUP"/> + <xsl:with-param name="iClass" select="'iogrp_label'"/> + </xsl:call-template> + + + </xsl:if> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iModInst)]/BUSINTERFACE[(@BIF_X and @BIF_Y and not(@BUSNAME = '__NOC__'))]"> + + <xsl:variable name="bifBusStd_"> + <xsl:choose> + <xsl:when test="@BUSSTD"> + <xsl:value-of select="@BUSSTD"/> + </xsl:when> + <xsl:otherwise> + <xsl:value-of select="'TRS'"/> + </xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="bif_y_"> + <xsl:value-of select="(($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * @BIF_Y)"/> + </xsl:variable> + + <xsl:variable name="bif_buscol_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="$bifBusStd_"/> + </xsl:call-template> + </xsl:variable> + + + <xsl:variable name="bifName_"> + <xsl:choose> + <xsl:when test="not(@NAME)">'UNK'</xsl:when> + <xsl:when test="string-length(@NAME) <= 5"> + <xsl:value-of select="@NAME"/> + </xsl:when> + <xsl:otherwise> + <xsl:value-of select="substring(@NAME,0,5)"/> + </xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="bif_x_" > + <xsl:if test="not(@ORIENTED='CENTER')"> + <xsl:value-of select="(($BLKD_BIF_W * @BIF_X) + ($BLKD_MOD_BIF_GAP_H * @BIF_X) + ($BLKD_MOD_LANE_W * 1))"/> + </xsl:if> + <xsl:if test="(@ORIENTED='CENTER')"> + <xsl:value-of select="ceiling($BLKD_MOD_W div 2) - ceiling($BLKD_BIF_W div 2)"/> + </xsl:if> + </xsl:variable> + + <xsl:if test="not(@IS_INTCONN)"> + <xsl:variable name="horz_line_y_" select="($bif_y_ + $bif_dy_ + ceiling($BLKD_BIFC_H div 2))"/> + + <xsl:variable name="horz_line_x1_"> + <xsl:choose> + <xsl:when test="@BIF_X = '0'">0</xsl:when> + <xsl:otherwise><xsl:value-of select="($BLKD_MOD_W - $BLKD_MOD_LANE_W)"/></xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="horz_line_x2_"> + <xsl:choose> + <xsl:when test="@BIF_X = '0'"><xsl:value-of select="$BLKD_MOD_LANE_W"/></xsl:when> + <xsl:otherwise><xsl:value-of select="$BLKD_MOD_W + 1"/></xsl:otherwise> + </xsl:choose> + </xsl:variable> + + + <line x1="{$horz_line_x1_}" + y1="{$horz_line_y_ - 2}" + x2="{$horz_line_x2_}" + y2="{$horz_line_y_ - 2}" + style="stroke:{$bif_buscol_};stroke-width:1"/> + + </xsl:if> + + <use x="{$bif_x_}" y="{$bif_y_ + $bif_dy_}" xlink:href="#{$bifBusStd_}_BifLabel"/> +<!-- + <text class="bif_label" + x="{$bif_x_ + ceiling($BLKD_BIF_W div 2)}" + y="{$bif_y_ + $bif_dy_ + ceiling($BLKD_BIF_H div 2) + 3}"> + <xsl:value-of select="$bifName_"/> + </text> +--> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="($bif_x_ + ceiling($BLKD_BIF_W div 2))"/> + <xsl:with-param name="iY" select="($bif_y_ + $bif_dy_ + ceiling($BLKD_BIF_H div 2) + 3)"/> + + <xsl:with-param name="iText" select="$bifName_"/> + <xsl:with-param name="iClass" select="'bif_label'"/> + </xsl:call-template> + + </xsl:for-each> + +<!-- + <xsl:if test="@INTC_INDEX"> + <xsl:variable name="intrColor_"> + <xsl:call-template name="F_IntcIdx2RGB"> + <xsl:with-param name="intcIdx" select="@INTC_INDEX"/> + </xsl:call-template> + </xsl:variable> + + <xsl:call-template name="F_draw_InterruptCntrl"> + <xsl:with-param name="intr_col" select="$intrColor_"/> + <xsl:with-param name="intr_x" select="($BLKD_MOD_W - ceiling($BLKD_INTR_W div 2))"/> + <xsl:with-param name="intr_y" select="3"/> + <xsl:with-param name="intr_idx" select="@INTC_INDEX"/> + </xsl:call-template> + </xsl:if> +--> + <xsl:if test="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iModInst)]/@INTC_INDEX"> + <xsl:variable name="intrColor_"> + <xsl:call-template name="F_IntcIdx2RGB"> + <xsl:with-param name="iIntcIdx" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iModInst)]/@INTC_INDEX"/> + </xsl:call-template> + </xsl:variable> + + <xsl:call-template name="F_draw_InterruptCntrl"> + <xsl:with-param name="iIntr_X" select="($BLKD_MOD_W - ceiling($BLKD_INTR_W div 2))"/> + <xsl:with-param name="iIntr_Y" select="3"/> + <xsl:with-param name="iIntr_COL" select="$intrColor_"/> + <xsl:with-param name="iIntr_IDX" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iModInst)]/@INTC_INDEX"/> + </xsl:call-template> + </xsl:if> + + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iModInst)]/INTERRUPTINFO[@TYPE ='TARGET']"> + + <xsl:variable name="intrColor_"> + <xsl:call-template name="F_IntcIdx2RGB"> + <xsl:with-param name="iIntcIdx" select="@INTC_INDEX"/> + </xsl:call-template> + </xsl:variable> + + <xsl:call-template name="F_draw_InterruptSource"> + <xsl:with-param name="iIntr_X" select="($BLKD_MOD_W - $BLKD_INTR_W)"/> + <xsl:with-param name="iIntr_Y" select="((position() - 1) * (ceiling($BLKD_INTR_H div 2) + 3))"/> + <xsl:with-param name="iIntr_COL" select="$intrColor_"/> + <xsl:with-param name="iIntr_PRI" select="@PRIORITY"/> + <xsl:with-param name="iIntr_IDX" select="@INTC_INDEX"/> + </xsl:call-template> + + </xsl:for-each> + </g> +</xsl:template> + +<xsl:template name="Define_MemoryUnit"> + <xsl:param name="iShapeId" select="1000"/> + + <xsl:variable name="horiz_idx_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/@STACK_HORIZ_INDEX"/> + <xsl:variable name="is_multistk_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/@IS_MULTISTK"/> + + <xsl:choose> + <xsl:when test="(($is_multistk_ = 'TRUE') or ($G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@STACK_HORIZ_INDEX = $horiz_idx_)]))"> + <xsl:call-template name="Define_Processor_MemoryUnit"> + <xsl:with-param name="iShapeId" select="$iShapeId"/> + </xsl:call-template> + </xsl:when> + + <xsl:otherwise> + <xsl:call-template name="Define_StandAlone_MemoryUnit"> + <xsl:with-param name="iShapeId" select="$iShapeId"/> + </xsl:call-template> + </xsl:otherwise> + + </xsl:choose> + +</xsl:template> + + +<xsl:template name="Define_Processor_MemoryUnit"> + <xsl:param name="iShapeId" select="1000"/> + +<!-- + <xsl:param name="cstkIndex" select="'_processor_'"/> +--> + + <xsl:variable name="mods_h_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/@MODS_H"/> + <xsl:variable name="mods_w_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/@MODS_W"/> + <xsl:variable name="memW_" select="($BLKD_MOD_W * $mods_w_)"/> + <xsl:variable name="memH_" select="($BLKD_MOD_H * $mods_h_)"/> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]"> + + <!-- first define its symbols as individual modules --> + <xsl:for-each select="MODULE[(@MODCLASS = 'MEMORY')]"> + + <xsl:variable name="modInst_" select="@INSTANCE"/> + <xsl:variable name="modType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $modInst_)]/@MODTYPE"/> + + <xsl:call-template name="Define_Peripheral"> + <xsl:with-param name="iModVori" select="'normal'"/> + <xsl:with-param name="iModInst" select="$modInst_"/> + <xsl:with-param name="iModType" select="$modType_"/> + </xsl:call-template> + </xsl:for-each> + + <xsl:for-each select="MODULE[@MODCLASS='MEMORY_CNTLR']"> + + <xsl:variable name="modInst_" select="@INSTANCE"/> + <xsl:variable name="modType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $modInst_)]/@MODTYPE"/> + + <xsl:call-template name="Define_Peripheral"> + <xsl:with-param name="iModVori" select="'rot180'"/> + <xsl:with-param name="iModInst" select="$modInst_"/> + <xsl:with-param name="iModType" select="$modType_"/> + </xsl:call-template> + </xsl:for-each> + </xsl:for-each> + +<!-- +--> + + <xsl:variable name="symbol_name_"> + <xsl:call-template name="F_generate_Stack_SymbolName"> + <xsl:with-param name="iHorizIdx" select="@STACK_HORIZ_INDEX"/> + <xsl:with-param name="iVertiIdx" select="@SHAPE_VERTI_INDEX"/> + </xsl:call-template> + </xsl:variable> + +<!-- + <xsl:message>The mp stack name is <xsl:value-of select="$mp_stack_name_"/></xsl:message> +--> + + <g id="{$symbol_name_}"> + + <rect x="0" + y="0" + rx="6" + ry="6" + width = "{$memW_}" + height= "{$memH_}" + style="fill:{$COL_BG}; stroke:{$COL_WHITE}; stroke-width:2"/> + + <!-- Draw the memory block--> + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/MODULE[(@MODCLASS = 'MEMORY')]"> + + <xsl:variable name="modInst_" select="@INSTANCE"/> + + <use x="{ceiling($memW_ div 2) - ($BLKD_MOD_W div 2)}" + y="0" + xlink:href="#symbol_{$modInst_}"/> + </xsl:for-each> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/MODULE[((@MODCLASS='MEMORY_CNTLR') and (@ORIENTED = 'WEST'))]"> + <xsl:variable name="modInst_" select="@INSTANCE"/> + + <use x="0" + y="{$BLKD_MOD_H}" + xlink:href="#symbol_{$modInst_}"/> + </xsl:for-each> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/MODULE[((@MODCLASS='MEMORY_CNTLR') and (@ORIENTED = 'EAST'))]"> + <xsl:variable name="modInst_" select="@INSTANCE"/> + + <use x="{$BLKD_MOD_W}" + y="{$BLKD_MOD_H}" + xlink:href="#symbol_{$modInst_}"/> + </xsl:for-each> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/MODULE[((@MODCLASS='MEMORY_CNTLR') and (@ORIENTED = 'CENTER'))]"> + <xsl:variable name="modInst_" select="@INSTANCE"/> + + <use x="{ceiling($memW_ div 2) - ($BLKD_MOD_W div 2)}" + y="{$BLKD_MOD_H}" + xlink:href="#symbol_{$modInst_}"/> + </xsl:for-each> + + </g> + +</xsl:template> + + +<xsl:template name="Define_StandAlone_MemoryUnit"> + + <xsl:param name="iShapeId" select="0"/> + + <xsl:variable name="mods_h_" select="@MODS_H"/> + <xsl:variable name="mods_w_" select="@MODS_W"/> + + <xsl:variable name="memcName_" select="MODULE[not(@MODCLASS = 'MEMORY')]/@INSTANCE"/> + <xsl:variable name="memcBusStd_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE/BUSCONNLANE[(BUSCONN[(@INSTANCE = $memcName_)])]/@BUSSTD"/> + +<!-- + <xsl:variable name="memcBusStd_" select="/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE/BUSCONNLANE/@BUSSTD"/> + <xsl:variable name="memcBusStd_" select="/EDKSYSTEM/BCLANESPACES/BCLANESPACE/BUSCONNLANE[(BUSCONN[(@INSTANCE)])]/@BUSSTD"/> + <xsl:message>Memory cntlr name <xsl:value-of select="$memcName_"/></xsl:message> + <xsl:message>Memory cntlr name <xsl:value-of select="$memcName_"/></xsl:message> + <xsl:message>Memory cntlr busstd <xsl:value-of select="$memcBusStd_"/></xsl:message> +--> + + <xsl:variable name="peri_col_"> + + <xsl:choose> + <xsl:when test="$mods_w_ > 1"> + <xsl:value-of select="$COL_BG"/> + </xsl:when> + + <xsl:when test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE/BUSCONNLANE[(BUSCONN[(@INSTANCE = $memcName_)])]/@BUSSTD"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="$memcBusStd_"/> + </xsl:call-template> + </xsl:when> + + <xsl:otherwise> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="'TRS'"/> + </xsl:call-template> + </xsl:otherwise> + </xsl:choose> + + </xsl:variable> + + <!-- first define its symbols as individual modules --> + <xsl:for-each select="MODULE[(@MODCLASS = 'MEMORY')]"> + + <xsl:variable name="modInst_" select="@INSTANCE"/> + <xsl:variable name="modType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $modInst_)]/@MODTYPE"/> + + <xsl:call-template name="Define_Peripheral"> + <xsl:with-param name="iModVori" select="'rot180'"/> + <xsl:with-param name="iModInst" select="$modInst_"/> + <xsl:with-param name="iModType" select="$modType_"/> + </xsl:call-template> + </xsl:for-each> + + <xsl:for-each select="MODULE[not(@MODCLASS='MEMORY')]"> + <xsl:variable name="modInst_" select="@INSTANCE"/> + <xsl:variable name="modType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $modInst_)]/@MODTYPE"/> + +<!-- + <xsl:message>Memory cntlr inst <xsl:value-of select="$modInst_"/></xsl:message> +--> + <xsl:call-template name="Define_Peripheral"> + <xsl:with-param name="iModVori" select="'normal'"/> + <xsl:with-param name="iModInst" select="$modInst_"/> + <xsl:with-param name="iModType" select="$modType_"/> + </xsl:call-template> + </xsl:for-each> + + <xsl:variable name="memW_" select="($BLKD_MOD_W * $mods_w_)"/> + <xsl:variable name="memH_" select="($BLKD_MOD_H * $mods_h_)"/> + + <xsl:variable name="symbol_name_"> + <xsl:call-template name="F_generate_Stack_SymbolName"> + <xsl:with-param name="iHorizIdx" select="@STACK_HORIZ_INDEX"/> + <xsl:with-param name="iVertiIdx" select="@SHAPE_VERTI_INDEX"/> + </xsl:call-template> + </xsl:variable> + + + <g id="{$symbol_name_}"> + + <rect x="0" + y="0" + rx="6" + ry="6" + width = "{$memW_ + 4}" + height= "{$memH_ + 4}" + style="fill:{$peri_col_}; stroke:{$peri_col_}; stroke-width:2"/> + + + <!-- Draw the memory block--> + <xsl:choose> + + <xsl:when test="$mods_w_ = 1"> + + <xsl:for-each select="MODULE[(@MODCLASS='MEMORY')]"> + <xsl:variable name="modInst_" select="@INSTANCE"/> + + <use x="2" + y="{$BLKD_MOD_H + 2}" + xlink:href="#symbol_{$modInst_}"/> + </xsl:for-each> + + + <!-- Draw the memory controllers--> + <xsl:for-each select="MODULE[not(@MODCLASS='MEMORY')]"> + <xsl:variable name="modInst_" select="@INSTANCE"/> + + <use x="2" + y="0" + xlink:href="#symbol_{$modInst_}"/> + </xsl:for-each> + </xsl:when> + + <xsl:when test="$mods_w_ > 1"> + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/MODULE[(@MODCLASS = 'MEMORY')]"> + + <xsl:variable name="modInst_" select="@INSTANCE"/> + + <use x="{ceiling($memW_ div 2) - ($BLKD_MOD_W div 2)}" + y="{$BLKD_MOD_H + 2}" + xlink:href="#symbol_{$modInst_}"/> + </xsl:for-each> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/MODULE[(not(@MODCLASS='MEMORY') and (@ORIENTED = 'WEST'))]"> + <xsl:variable name="modInst_" select="@INSTANCE"/> + + <use x="0" + y="0" + xlink:href="#symbol_{$modInst_}"/> + </xsl:for-each> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/MODULE[(not(@MODCLASS='MEMORY') and (@ORIENTED = 'EAST'))]"> + <xsl:variable name="modInst_" select="@INSTANCE"/> + + <use x="{$BLKD_MOD_W}" + y="0" + xlink:href="#symbol_{$modInst_}"/> + </xsl:for-each> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/MODULE[(not(@MODCLASS='MEMORY') and (@ORIENTED = 'CENTER'))]"> + <xsl:variable name="modInst_" select="@INSTANCE"/> + + <use x="{ceiling($memW_ div 2) - ($BLKD_MOD_W div 2)}" + y="0" + xlink:href="#symbol_{$modInst_}"/> + </xsl:for-each> + + </xsl:when> + </xsl:choose> + + </g> + +</xsl:template> + + +<xsl:template name="Define_StandAlone_MPMC"> + +<!-- + <xsl:param name="drawarea_w" select="500"/> + <xsl:param name="drawarea_h" select="500"/> +--> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/MPMCSHAPE"> + + <xsl:variable name="mpmcInst_" select="@INSTANCE"/> + <xsl:variable name="mpmcType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[@INSTANCE=$mpmcInst_]/@MODTYPE"/> +<!-- + <xsl:message>Drawing instance <xsl:value-of select="$mpmcInst_"/></xsl:message> +--> + + <xsl:variable name="mpmc_w_" select="($G_Total_DrawArea_W - ($BLKD_INNER_GAP * 2))"/> + <xsl:variable name="label_y_" select="ceiling($BLKD_MPMC_MOD_H div 2) - ceiling($BLKD_MOD_LABEL_H div 2)"/> + + <g id="mpmcmodule_{$mpmcInst_}"> + <rect x="0" + y="0" + width = "{$mpmc_w_}" + height= "{$BLKD_MPMC_MOD_H}" + style="fill:{$COL_MPMC_BG}; stroke:{$COL_BLACK}; stroke-width:2"/> + + <rect x="{$BLKD_MOD_LANE_H}" + y="{$label_y_}" + rx="3" + ry="3" + width= "{$BLKD_MOD_LABEL_W}" + height="{$BLKD_MOD_LABEL_H}" + style="fill:{$COL_WHITE}; stroke:none;"/> +<!-- + <text class="bc_iptype" + x="{ceiling(($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_W) div 2)}" + y="{$label_y_ + 8}"> + <xsl:value-of select="$mpmcType_"/> + </text> + + <text class="bc_ipinst" + x="{ceiling(($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_W) div 2)}" + y="{$label_y_ + 16}"> + <xsl:value-of select="$mpmcInst_"/> + </text> + + <text class="mpmc_title" + x="{ceiling($mpmc_w_ div 2)}" + y="{$label_y_ + 16}">MPMC Module Interface</text> +--> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="(ceiling(($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_W) div 2))"/> + <xsl:with-param name="iY" select="($label_y_ + 8)"/> + <xsl:with-param name="iText" select="$mpmcType_"/> + <xsl:with-param name="iClass" select="'bc_iptype'"/> + </xsl:call-template> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="(ceiling(($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_W) div 2))"/> + <xsl:with-param name="iY" select="($label_y_ + 16)"/> + <xsl:with-param name="iText" select="$mpmcInst_"/> + <xsl:with-param name="iClass" select="'bc_ipinst'"/> + </xsl:call-template> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="ceiling($mpmc_w_ div 2)"/> + <xsl:with-param name="iY" select="($label_y_ + 16)"/> + <xsl:with-param name="iText" select="'MPMC Module Interface'"/> + <xsl:with-param name="iClass" select="'mpmc_title'"/> + </xsl:call-template> + + + </g> + + </xsl:for-each> + +</xsl:template> + + +<!-- ======================= END DEF FUNCTIONS ============================ --> + +<!-- ======================= UTILITY FUNCTIONS ============================ --> + +<xsl:template name="F_draw_InterruptSource"> + + <xsl:param name="iIntr_X" select="0"/> + <xsl:param name="iIntr_Y" select="0"/> + <xsl:param name="iIntr_PRI" select="0"/> + <xsl:param name="iIntr_IDX" select="0"/> + <xsl:param name="iIntr_COL" select="$COL_INTR_0"/> + + <rect + x="{$iIntr_X}" + y="{$iIntr_Y}" + rx="3" + ry="3" + width= "{$BLKD_INTR_W}" + height="{ceiling($BLKD_INTR_H div 2)}" style="fill:{$iIntr_COL}; stroke:none; stroke-width:1"/> + + <line x1="{$iIntr_X + ceiling($BLKD_INTR_W div 2)}" + y1="{$iIntr_Y}" + x2="{$iIntr_X + ceiling($BLKD_INTR_W div 2)}" + y2="{$iIntr_Y + ceiling($BLKD_INTR_H div 2)}" + style="stroke:{$COL_BLACK};stroke-width:1"/> + + <xsl:variable name="txt_ofs_"> + <xsl:if test="($iIntr_PRI > 9)">4.5</xsl:if> + <xsl:if test="not($iIntr_PRI > 9)">0</xsl:if> + </xsl:variable> + +<!-- + <text class="intrsymbol" + x="{$iIntr_X + 2 - $txt_ofs_}" + y="{$iIntr_Y + 8}"> + <xsl:value-of select="$iIntr_PRI"/> + </text> + + <text class="intrsymbol" + x="{$iIntr_X + 2 + ceiling($BLKD_INTR_W div 2)}" + y="{$iIntr_Y + 8}"> + <xsl:value-of select="$iIntr_IDX"/> + </text> +--> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="($iIntr_X + 2 - $txt_ofs_)"/> + <xsl:with-param name="iY" select="($iIntr_Y + 8)"/> + <xsl:with-param name="iText" select="$iIntr_PRI"/> + <xsl:with-param name="iClass" select="'intr_symbol'"/> + </xsl:call-template> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="($iIntr_X + 2 + ceiling($BLKD_INTR_W div 2))"/> + <xsl:with-param name="iY" select="($iIntr_Y + 8)"/> + <xsl:with-param name="iText" select="$iIntr_IDX"/> + <xsl:with-param name="iClass" select="'intr_symbol'"/> + </xsl:call-template> + +</xsl:template> + +<xsl:template name="F_draw_InterruptCntrl"> + + <xsl:param name="iIntr_X" select="0"/> + <xsl:param name="iIntr_Y" select="0"/> + <xsl:param name="iIntr_IDX" select="0"/> + <xsl:param name="iIntr_COL" select="$COL_INTR_0"/> + + <rect + x="{$iIntr_X}" + y="{$iIntr_Y}" + rx="3" + ry="3" + width= "{ceiling($BLKD_INTR_W div 2)}" + height="{$BLKD_INTR_H}" style="fill:{$iIntr_COL}; stroke:none; stroke-width:1"/> + + <line x1="{$iIntr_X}" + y1="{$iIntr_Y + ceiling($BLKD_INTR_H div 4)}" + x2="{$iIntr_X + ceiling($BLKD_INTR_W div 2)}" + y2="{$iIntr_Y + ceiling($BLKD_INTR_H div 4)}" + style="stroke:{$COL_BLACK};stroke-width:2"/> +<!-- + <text class="intrsymbol" + x="{$iIntr_X + 2}" + y="{$iIntr_Y + 8 + ceiling($BLKD_INTR_H div 2)}"> + <xsl:value-of select="$iIntr_IDX"/> + </text> +--> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="($iIntr_X + 2)"/> + <xsl:with-param name="iY" select="($iIntr_Y + 8 + ceiling($BLKD_INTR_H div 2))"/> + <xsl:with-param name="iText" select="$iIntr_IDX"/> + <xsl:with-param name="iClass" select="'intr_symbol'"/> + </xsl:call-template> + +</xsl:template> + + +<xsl:template name="F_draw_InterruptedProc"> + + <xsl:param name="iIntr_X" select="0"/> + <xsl:param name="iIntr_Y" select="0"/> + <xsl:param name="iIntr_IDX" select="0"/> + <xsl:param name="iIntr_COL" select="$COL_INTR_0"/> + + <rect + x="{$iIntr_X}" + y="{$iIntr_Y}" + rx="3" + ry="3" + width= "{ceiling($BLKD_INTR_W div 2)}" + height="{$BLKD_INTR_H}" style="fill:{$iIntr_COL}; stroke:none; stroke-width:1"/> + + <line x1="{$iIntr_X}" + y1="{$iIntr_Y + ceiling($BLKD_INTR_H div 4) - 2}" + x2="{$iIntr_X + ceiling($BLKD_INTR_W div 2)}" + y2="{$iIntr_Y + ceiling($BLKD_INTR_H div 4) - 2}" + style="stroke:{$COL_BLACK};stroke-width:1"/> + + <line x1="{$iIntr_X}" + y1="{$iIntr_Y + ceiling($BLKD_INTR_H div 4) + 2}" + x2="{$iIntr_X + ceiling($BLKD_INTR_W div 2)}" + y2="{$iIntr_Y + ceiling($BLKD_INTR_H div 4) + 2}" + style="stroke:{$COL_BLACK};stroke-width:1"/> + +<!-- + <text class="intrsymbol" + x="{$iIntr_X + 2}" + y="{$iIntr_Y + 8 + ceiling($BLKD_INTR_H div 2)}"> + <xsl:value-of select="$iIntr_IDX"/> + </text> + --> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="($iIntr_X + 2)"/> + <xsl:with-param name="iY" select="($iIntr_Y + 8 + ceiling($BLKD_INTR_H div 2))"/> + <xsl:with-param name="iText" select="$iIntr_IDX"/> + <xsl:with-param name="iClass" select="'intr_symbol'"/> + </xsl:call-template> + +</xsl:template> + +<xsl:template name="F_Calc_CStackShapesAbv_Height"> + <xsl:param name="iCStackIndex" select="100"/> + <xsl:param name="iCStackMods_Y" select="1000"/> + +<!-- + <xsl:message>Stack Index <xsl:value-of select="$cstackIndex"/></xsl:message> + + <xsl:message>Stack Y <xsl:value-of select="$cstackModY"/></xsl:message> +--> + <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@CSTACK_INDEX = $iCStackIndex)])">0</xsl:if> + + <xsl:if test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@CSTACK_INDEX = $iCStackIndex)]"> + + <xsl:variable name="shapesAbv_Heights_"> + <CSTACK_MOD HEIGHT="0"/> + + <!-- Store the heights of all the peripherals above this one heights in a variable --> + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@CSTACK_INDEX = $iCStackIndex) and (@CSTACK_MODS_Y < $iCStackMods_Y))]"> + + <xsl:variable name="shapeHeight_"> + + <xsl:choose> + + <xsl:when test="@MODCLASS = 'PERIPHERAL'"> + <xsl:call-template name="F_Calc_PeriShape_Height"> + <xsl:with-param name="iShapeInst" select="MODULE/@INSTANCE"/> + </xsl:call-template> + </xsl:when> + + <xsl:when test="@MODCLASS = 'MEMORY_UNIT'"> + <xsl:call-template name="F_Calc_MemoryUnit_Height"> + <xsl:with-param name="iShapeId" select="@SHAPE_ID"/> + </xsl:call-template> + </xsl:when> + + <xsl:otherwise>0</xsl:otherwise> + </xsl:choose> + </xsl:variable> + +<!-- + <xsl:message>Calculated height of cstack shape of type <xsl:value-of select="@MODCLASS"/> as <xsl:value-of select="$shapeHeight_"/></xsl:message> +--> + + <CSTACK_MOD HEIGHT="{$shapeHeight_ + $BLKD_BIF_H}"/> + </xsl:for-each> + </xsl:variable> + +<!-- + <xsl:message>Calculated height of cstack as <xsl:value-of select="sum(exsl:node-set($shapesAbv_Heights_)/CSTACK_MOD/@HEIGHT)"/></xsl:message> +--> + + <xsl:value-of select="sum(exsl:node-set($shapesAbv_Heights_)/CSTACK_MOD/@HEIGHT)"/> + </xsl:if> + +</xsl:template> + + +<xsl:template name="F_Calc_PeriShape_Height"> + <xsl:param name="iShapeInst" select="'_shape_'"/> + +<!-- + <xsl:message>Calculating height of <xsl:value-of select="$iShapeInst"/></xsl:message> +--> + + <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE/MODULE[(@INSTANCE = $iShapeInst)]/@BIFS_H) and + not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $iShapeInst)]/@BIFS_H) and + not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/BRIDGESHAPES/MODULE[(@INSTANCE = $iShapeInst)]/@BIFS_H)">0</xsl:if> + + <xsl:if test="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE/MODULE[(@INSTANCE = $iShapeInst)]/@BIFS_H)"> + <xsl:variable name="bifs_h_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE/MODULE[(@INSTANCE = $iShapeInst)]/@BIFS_H"/> + + <xsl:value-of select="($BLKD_MOD_LABEL_H + ($BLKD_BIF_H * $bifs_h_) + ($BLKD_MOD_BIF_GAP_V * $bifs_h_) + ($BLKD_MOD_LANE_H * 2))"/> + </xsl:if> + + <xsl:if test="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/BRIDGESHAPES/MODULE[(@INSTANCE = $iShapeInst)]/@BIFS_H)"> + <xsl:variable name="bifs_h_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BRIDGESHAPES/MODULE[(@INSTANCE = $iShapeInst)]/@BIFS_H"/> + + <xsl:value-of select="($BLKD_MOD_LABEL_H + ($BLKD_BIF_H * $bifs_h_) + ($BLKD_MOD_BIF_GAP_V * $bifs_h_) + ($BLKD_MOD_LANE_H * 2))"/> + </xsl:if> + + <xsl:if test="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $iShapeInst)]/@BIFS_H)"> + <xsl:variable name="bifs_h_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@INSTANCE = $iShapeInst)]/@BIFS_H"/> + + <xsl:value-of select="($BLKD_MOD_LABEL_H + ($BLKD_BIF_H * $bifs_h_) + ($BLKD_MOD_BIF_GAP_V * $bifs_h_) + ($BLKD_MOD_LANE_H * 2))"/> + </xsl:if> + +</xsl:template> + +<xsl:template name="F_Calc_Shape_Height"> + <xsl:param name="iShapeId" select="_shape_"/> + +<!-- + <xsl:message>Calculating height of <xsl:value-of select="$shapeId"/></xsl:message> +--> + + <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)])">0</xsl:if> + + <xsl:if test="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/MODULE/@BIFS_H)"> + <xsl:variable name="bifs_h_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/MODULE/@BIFS_H"/> + + <xsl:value-of select="($BLKD_MOD_LABEL_H + ($BIF_H * $bifs_h_) + ($BLKD_MOD_BIF_GAP_V * $bifs_h_) + ($BLKD_MOD_LANE_H * 2))"/> + </xsl:if> + +</xsl:template> + + +<xsl:template name="F_Calc_MemoryUnit_Height"> + <xsl:param name="iShapeId" select="1000"/> + + <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)])">0</xsl:if> + + <xsl:if test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]"> + + <!-- Store the memory controller heights in a variable --> + <xsl:variable name="memC_heights_"> + <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/MODULE[(@MODCLASS = 'MEMORY_CNTLR')])"> + <MEM_CNTLR INSTANCE="{@INSTANCE}" HEIGHT="0"/> + </xsl:if> + + <xsl:if test="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/MODULE[(@MODCLASS = 'MEMORY_CNTLR')])"> + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/MODULE[(@MODCLASS = 'MEMORY_CNTLR')]"> + <xsl:variable name="memC_height_"> + <xsl:call-template name="F_Calc_PeriShape_Height"> + <xsl:with-param name="iShapeInst" select="@INSTANCE"/> + </xsl:call-template> + </xsl:variable> + <MEM_CNTLR INSTANCE="{@INSTANCE}" HEIGHT="{$memC_height_}"/> + </xsl:for-each> + </xsl:if> + </xsl:variable> + + <!-- Store the bram heights in a variable --> + <xsl:variable name="bram_heights_"> + <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/MODULE[not(@MODCLASS = 'MEMORY_CNTLR')])"> + <BRAM INSTANCE="{@INSTANCE}" HEIGHT="0"/> + </xsl:if> + <xsl:if test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/MODULE[not(@MODCLASS = 'MEMORY_CNTLR')]"> + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@SHAPE_ID = $iShapeId)]/MODULE[not(@MODCLASS = 'MEMORY_CNTLR')]"> + <xsl:variable name="bram_height_"> + <xsl:call-template name="F_Calc_PeriShape_Height"> + <xsl:with-param name="iShapeInst" select="@INSTANCE"/> + </xsl:call-template> + </xsl:variable> + <BRAM INSTANCE="{@INSTANCE}" HEIGHT="{$bram_height_}"/> + </xsl:for-each> + </xsl:if> + </xsl:variable> + + <!-- Select the maximum of them --> + <xsl:variable name="max_bram_height_" select="math:max(exsl:node-set($bram_heights_)/BRAM/@HEIGHT)"/> + <xsl:variable name="max_memC_height_" select="math:max(exsl:node-set($memC_heights_)/MEM_CNTLR/@HEIGHT)"/> + + <xsl:value-of select="$max_bram_height_ + $max_memC_height_"/> + </xsl:if> + +</xsl:template> + + +<xsl:template name="F_Calc_SbsBucket_Height"> + <xsl:param name="iBucketId" select="100"/> + +<!-- + <xsl:message>Looking of height of bucket <xsl:value-of select="$iBucketId"/></xsl:message> +--> + <xsl:variable name="bkt_gap_" select="$BLKD_BIF_H"/> + + <xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET[(@BUS_INDEX = $iBucketId)])">0</xsl:if> + + <xsl:if test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET[(@BUS_INDEX = $iBucketId)]"> + <xsl:variable name="mods_h_" select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET[(@BUS_INDEX = $iBucketId)]/@MODS_H"/> + <xsl:value-of select="((($BLKD_MOD_BKTLANE_H * 2) + ((($BLKD_MOD_H + $BLKD_BIFC_H) * $mods_h_) + ($BLKD_MOD_BUCKET_G * ($mods_h_ - 1)))) + $bkt_gap_)"/> + </xsl:if> +</xsl:template> + +<!-- + =============================================== + + Symbol Naming Functions + + =============================================== +--> + + +<xsl:template name="F_generate_Proc_StackName"> +<xsl:param name="iProcInst" select="'_unknown_'"/> +symbol_STACK_<xsl:value-of select="$iProcInst"/> +</xsl:template> + +<xsl:template name="F_generate_Proc_GroupName"> +<xsl:param name="iProcInst" select="'_unknown_'"/> +symbol_GROUP_<xsl:value-of select="$iProcInst"/> +</xsl:template> + + +<xsl:template name="F_generate_Space_Name"><xsl:param name="iStackToEast" select="'NONE'"/><xsl:param name="iStackToWest" select="'NONE'"/>symbol_SPACE_WEST_<xsl:value-of select="$iStackToWest"/>_EAST_<xsl:value-of select="$iStackToEast"/></xsl:template> +<xsl:template name="F_generate_Stack_Name"><xsl:param name="iHorizIdx" select="'_unknown_'"/>symbol_STACK_<xsl:value-of select="$iHorizIdx"/></xsl:template> +<xsl:template name="F_generate_Stack_SymbolName"><xsl:param name="iHorizIdx" select="'_unknown_'"/><xsl:param name="iVertiIdx" select="'_unknown_'"/>symbol_STACK_<xsl:value-of select="$iHorizIdx"/>_SHAPE_<xsl:value-of select="$iVertiIdx"/></xsl:template> + + +<!-- ======================= END UTILITY FUNCTIONS ======================= --> +</xsl:stylesheet> + diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtTinySvgBLKD_Processors.xsl b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtTinySvgBLKD_Processors.xsl new file mode 100644 index 000000000..9eb7a20bf --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtTinySvgBLKD_Processors.xsl @@ -0,0 +1,462 @@ +<?xml version="1.0" standalone="no"?> +<xsl:stylesheet version="1.0" + xmlns:svg="http://www.w3.org/2000/svg" + xmlns:xsl="http://www.w3.org/1999/XSL/Transform" + xmlns:math="http://exslt.org/math" + xmlns:exsl="http://exslt.org/common" + xmlns:xlink="http://www.w3.org/1999/xlink" + extension-element-prefixes="math"> + +<xsl:output method="xml" + version="1.0" + encoding="UTF-8" + indent="yes" + doctype-public="-//W3C//DTD SVG 1.0//EN" + doctype-system="http://www.w3.org/TR/SVG/DTD/svg10.dtd"/> + + +<!-- ======================= DEF BLOCK =================================== --> +<xsl:template name="Define_AllStacks"> + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE[(@EAST < $G_ROOT/EDKSYSTEM/BLKDIAGRAM/@STACK_HORIZ_WIDTH)]"> + + <xsl:call-template name="Define_Stack"> + <xsl:with-param name="iStackIdx" select="@EAST"/> + </xsl:call-template> + + </xsl:for-each> +</xsl:template> + + +<xsl:template name="Define_Stack"> + <xsl:param name="iStackIdx" select="100"/> + + <!-- Define the stack's peripheral shapes--> + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@STACK_HORIZ_INDEX = $iStackIdx) and not(@MODCLASS = 'MEMORY_UNIT'))]"> + + <xsl:for-each select="MODULE"> + <xsl:variable name="modInst_" select="@INSTANCE"/> + <xsl:variable name="modType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $modInst_)]/@MODTYPE"/> + <xsl:call-template name="Define_Peripheral"> + <xsl:with-param name="iModInst" select="$modInst_"/> + <xsl:with-param name="iModType" select="$modType_"/> + <xsl:with-param name="iShapeId" select="../@SHAPE_ID"/> + <xsl:with-param name="iHorizIdx" select="../@STACK_HORIZ_INDEX"/> + <xsl:with-param name="iVertiIdx" select="../@SHAPE_VERTI_INDEX"/> + </xsl:call-template> + </xsl:for-each> + + </xsl:for-each> + + <!-- Define the stack's memory shapes--> + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@STACK_HORIZ_INDEX = $iStackIdx) and (@MODCLASS='MEMORY_UNIT'))]"> + <xsl:call-template name="Define_MemoryUnit"> + <xsl:with-param name="iShapeId" select="@SHAPE_ID"/> + </xsl:call-template> + </xsl:for-each> + + + <!-- Define the stack's processors--> + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[@INSTANCE and @BIFS_W and @BIFS_H and (@STACK_HORIZ_INDEX = $iStackIdx)]"> + <xsl:call-template name="Define_Processor"/> + </xsl:for-each> + + <!-- Make an inventory of all the things in this processor's stack --> + <xsl:variable name="pstackW_"> + <xsl:call-template name="F_Calc_Stack_Width"> + <xsl:with-param name="iStackIdx" select="$iStackIdx"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="pstackH_"> + <xsl:call-template name="F_Calc_Stack_Height"> + <xsl:with-param name="iStackIdx" select="$iStackIdx"/> + </xsl:call-template> + </xsl:variable> + +<!-- + <xsl:message>Proc Stack Height <xsl:value-of select="$pstackH_"/></xsl:message> + <xsl:message>Proc Stack Height <xsl:value-of select="$pstackH_"/></xsl:message> +--> + + <xsl:variable name="procW_" select="$BLKD_MOD_W"/> + <xsl:variable name="procX_" select="(ceiling($pstackW_ div 2) - ceiling($procW_ div 2))"/> + + <xsl:variable name="sbsGap_" select="($BLKD_PROC2SBS_GAP + $G_Total_SharedBus_H)"/> + + <xsl:variable name="stack_name_"> + <xsl:call-template name="F_generate_Stack_Name"> + <xsl:with-param name="iHorizIdx" select="$iStackIdx"/> + </xsl:call-template> + </xsl:variable> + +<!-- + <xsl:message>Horiz index<xsl:value-of select="$stackIdx"/></xsl:message> + <xsl:message>Drawing stack <xsl:value-of select="$stack_name_"/></xsl:message> +--> + + <!-- Now use all this stuff to draw the stack--> + <g id="{$stack_name_}"> + <rect x="0" + y="0" + rx="6" + ry="6" + width = "{$pstackW_}" + height= "{$pstackH_}" + style="fill:{$COL_BG}; stroke:none;"/> + + + <!-- First draw the the processor's peripherals--> + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@STACK_HORIZ_INDEX = $iStackIdx)]"> + <xsl:sort select="@STACK_VERTI_INDEX" data-type="number"/> + + + <xsl:variable name="shapeW_" select="(@MODS_W * $BLKD_MOD_W)"/> + <xsl:variable name="shapeX_" select="(ceiling($pstackW_ div 2) - ceiling($shapeW_ div 2))"/> + + <xsl:variable name="stack_SymName_"> + <xsl:call-template name="F_generate_Stack_SymbolName"> + <xsl:with-param name="iHorizIdx" select="@STACK_HORIZ_INDEX"/> + <xsl:with-param name="iVertiIdx" select="@SHAPE_VERTI_INDEX"/> + </xsl:call-template> + </xsl:variable> + +<!-- + <xsl:message>Drawing stack peripheral <xsl:value-of select="$stack_SymName_"/></xsl:message> +--> + <xsl:variable name="shapeY_"> + <xsl:call-template name="F_Calc_Stack_Shape_Y"> + <xsl:with-param name="iHorizIdx" select="@STACK_HORIZ_INDEX"/> + <xsl:with-param name="iVertiIdx" select="@SHAPE_VERTI_INDEX"/> + </xsl:call-template> + </xsl:variable> + + <use x="{$shapeX_}" y="{$shapeY_}" xlink:href="#{$stack_SymName_}"/> + + </xsl:for-each> + + + <!-- Then draw the slave buckets for the shared busses that this processor is master to --> + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET[(@STACK_HORIZ_INDEX = $iStackIdx)]"> + <xsl:sort select="@SHAPE_VERTI_INDEX" data-type="number"/> + + <xsl:variable name="bucketW_" select="(($BLKD_MOD_BKTLANE_W * 2) + (($BLKD_MOD_W * @MODS_W) + ($BLKD_MOD_BUCKET_G * (@MODS_W - 1))))"/> + <xsl:variable name="bucketX_" select="(ceiling($pstackW_ div 2) - ceiling($bucketW_ div 2))"/> + + <xsl:variable name="bucketY_"> + <xsl:call-template name="F_Calc_Stack_Shape_Y"> + <xsl:with-param name="iHorizIdx" select="@STACK_HORIZ_INDEX"/> + <xsl:with-param name="iVertiIdx" select="@SHAPE_VERTI_INDEX"/> + </xsl:call-template> + </xsl:variable> + +<!-- + <xsl:message>SBS Bucket Y <xsl:value-of select="$bucketY_"/></xsl:message> +--> + + <use x="{$bucketX_}" y="{$bucketY_}" xlink:href="#sbsbucket_{@BUSNAME}"/> + + <xsl:variable name="slavesOfTxt_">SLAVES OF <xsl:value-of select="@BUSNAME"/></xsl:variable> +<!-- + <text class="bkt_label" + x="{$bucketX_}" + y="{$bucketY_ - 4}"><xsl:value-of select="$slavesOfTxt_"/></text> +--> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="$bucketX_"/> + <xsl:with-param name="iY" select="($bucketY_ - 4)"/> + <xsl:with-param name="iText" select="$slavesOfTxt_"/> + <xsl:with-param name="iClass" select="'bkt_label'"/> + </xsl:call-template> + + + </xsl:for-each> + + <!-- Then draw the the processor itself --> + <xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@STACK_HORIZ_INDEX = $iStackIdx)]"> + <xsl:sort select="@SHAPE_VERTI_INDEX" data-type="number"/> + + <xsl:variable name="procY_"> + <xsl:call-template name="F_Calc_Stack_Shape_Y"> + <xsl:with-param name="iHorizIdx" select="@STACK_HORIZ_INDEX"/> + <xsl:with-param name="iVertiIdx" select="@SHAPE_VERTI_INDEX"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="stack_SymName_"> + <xsl:call-template name="F_generate_Stack_SymbolName"> + <xsl:with-param name="iHorizIdx" select="@STACK_HORIZ_INDEX"/> + <xsl:with-param name="iVertiIdx" select="@SHAPE_VERTI_INDEX"/> + </xsl:call-template> + </xsl:variable> + + <use x="{$procX_}" y="{$procY_}" xlink:href="#{$stack_SymName_}"/> + + +<!-- + <xsl:if test = "not(@IS_LIKEPROC)"> + <text class="ipclass_label" + x="{$procX_}" + y="{$procY_ - 4}">PROCESSOR</text> + </xsl:if> + + <xsl:if test = "@IS_LIKEPROC = 'TRUE'"> + + <text class="ipclass_label" + x="{$procX_}" + y="{$procY_ - 4}">USER MODULE</text> + </xsl:if> + +--> + + <xsl:if test = "not(@IS_LIKEPROC)"> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="$procX_"/> + <xsl:with-param name="iY" select="($procY_ - 4)"/> + <xsl:with-param name="iText" select="'PROCESSOR'"/> + <xsl:with-param name="iClass" select="'ipclass_label'"/> + </xsl:call-template> + </xsl:if> + + <xsl:if test = "@IS_LIKEPROC = 'TRUE'"> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="$procX_"/> + <xsl:with-param name="iY" select="($procY_ - 4)"/> + <xsl:with-param name="iText" select="'USER MODULE'"/> + <xsl:with-param name="iClass" select="'ipclass_label'"/> + </xsl:call-template> + </xsl:if> + + </xsl:for-each> + </g> + +</xsl:template> + + +<xsl:template name="Define_Processor"> + <xsl:param name="iProcInst" select="@INSTANCE"/> + <xsl:param name="iModType" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iProcInst)]/@MODTYPE"/> + + <xsl:variable name="label_y_"> + <xsl:value-of select="$BLKD_MOD_LANE_H"/> + </xsl:variable> + +<!-- + <xsl:message>The proctype is <xsl:value-of select="$procType"/></xsl:message> +--> + + <xsl:variable name="procH_" select="(($BLKD_MOD_LANE_H * 2) + (($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * @BIFS_H) + ($BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V))"/> + <xsl:variable name="procW_" select="(($BLKD_MOD_LANE_W * 2) + (($BLKD_BIF_W * @BIFS_W) + $BLKD_MOD_BIF_GAP_H))"/> + + <xsl:variable name="procColor_"> + <xsl:choose> + <xsl:when test="contains($iModType,'microblaze')"><xsl:value-of select="$COL_PROC_BG_MB"/></xsl:when> + <xsl:when test="contains($iModType,'ppc')"><xsl:value-of select="$COL_PROC_BG_PP"/></xsl:when> + <xsl:otherwise> + <xsl:value-of select="$COL_PROC_BG_USR"/> + </xsl:otherwise> + </xsl:choose> + </xsl:variable> + +<!-- + <xsl:message>The proc color is <xsl:value-of select="$procColor"/></xsl:message> +--> + + <xsl:variable name="procName_"> + <xsl:call-template name="F_generate_Stack_SymbolName"> + <xsl:with-param name="iHorizIdx" select="@STACK_HORIZ_INDEX"/> + <xsl:with-param name="iVertiIdx" select="@SHAPE_VERTI_INDEX"/> + </xsl:call-template> + </xsl:variable> + +<!-- + <xsl:message>The proc name is <xsl:value-of select="$procName_"/></xsl:message> +--> + + <g id="{$procName_}"> + + <rect x="0" + y="0" + rx="6" + ry="6" + width = "{$procW_}" + height= "{$procH_}" + style="fill:{$procColor_}; stroke:{$COL_WHITE}; stroke-width:2"/> + + + <rect x="{ceiling($procW_ div 2) - ceiling($BLKD_MOD_LABEL_W div 2)}" + y="{$BLKD_MOD_LANE_H}" + rx="3" + ry="3" + width= "{$BLKD_MOD_LABEL_W}" + height="{$BLKD_MOD_LABEL_H}" + style="fill:{$COL_WHITE}; stroke:none;"/> +<!-- + <text class="bciptype" + x="{ceiling($procW_ div 2)}" + y="{$BLKD_MOD_LANE_H + 8}"> + <xsl:value-of select="$iModType"/> + </text> + + <text class="bciplabel" + x="{ceiling($procW_ div 2)}" + y="{$BLKD_MOD_LANE_H + 16}"> + <xsl:value-of select="$iProcInst"/> + </text> +--> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="ceiling($procW_ div 2)"/> + <xsl:with-param name="iY" select="($BLKD_MOD_LANE_H + 8)"/> + <xsl:with-param name="iText" select="$iModType"/> + <xsl:with-param name="iClass" select="'bc_iptype'"/> + </xsl:call-template> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="ceiling($procW_ div 2)"/> + <xsl:with-param name="iY" select="($BLKD_MOD_LANE_H + 16)"/> + <xsl:with-param name="iText" select="$iProcInst"/> + <xsl:with-param name="iClass" select="'bc_ipinst'"/> + </xsl:call-template> + + + + <xsl:if test="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iProcInst)]/@GROUP"> + + <rect x="{ceiling($BLKD_MOD_W div 2) - ceiling($BLKD_MOD_LABEL_W div 2)}" + y="{$BLKD_MOD_LANE_H + $BIF_H + ceiling($BLKD_BIF_H div 3) - 2}" + rx="3" + ry="3" + width= "{$BLKD_MOD_LABEL_W}" + height="{$BLKD_BIF_H}" + style="fill:{$COL_IORING_LT}; stroke:none;"/> +<!-- + <text class="ioplblgrp" + x="{ceiling($BLKD_MOD_W div 2)}" + y="{$BLKD_MOD_LANE_H + $BIF_H + ceiling($BIF_H div 3) + 12}"> + <xsl:value-of select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iProcInst)]/@GROUP"/> + </text> +--> + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="ceiling($BLKD_MOD_W div 2)"/> + <xsl:with-param name="iY" select="($BLKD_MOD_LANE_H + $BIF_H + ceiling($BIF_H div 3) + 12)"/> + <xsl:with-param name="iText" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iProcInst)]/@GROUP"/> + <xsl:with-param name="iClass" select="'iogrp_label'"/> + </xsl:call-template> + + </xsl:if> + + + <xsl:for-each select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iProcInst)]/BUSINTERFACE[(@BIF_X and @BIF_Y)]"> + + <xsl:variable name="bifBusStd_"> + <xsl:choose> + <xsl:when test="@BUSSTD"> + <xsl:value-of select="@BUSSTD"/> + </xsl:when> + <xsl:otherwise> + <xsl:value-of select="'TRS'"/> + </xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="bifBusColor_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="$bifBusStd_"/> + </xsl:call-template> + </xsl:variable> + + + <xsl:variable name="bifName_"> + <xsl:choose> + <xsl:when test="string-length(@NAME) <= 5"> + <xsl:value-of select="@NAME"/> + </xsl:when> + <xsl:otherwise> + <xsl:value-of select="substring(@NAME,0,5)"/> + </xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="bif_x_" select="(( $BLKD_BIF_W * @BIF_X) + ($BLKD_MOD_BIF_GAP_H * @BIF_X) + ($BLKD_MOD_LANE_W * 1))"/> + <xsl:variable name="bif_y_" select="((($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * @BIF_Y) + ($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V))"/> + + <xsl:variable name="horz_line_y_" select="($bif_y_ + ceiling($BLKD_BIFC_H div 2))"/> + + <xsl:variable name="horz_line_x1_"> + <xsl:choose> + <xsl:when test="@BIF_X = '0'">0</xsl:when> + <xsl:otherwise><xsl:value-of select="($BLKD_MOD_W - $BLKD_MOD_LANE_W)"/></xsl:otherwise> + </xsl:choose> + </xsl:variable> + + <xsl:variable name="horz_line_x2_"> + <xsl:choose> + <xsl:when test="@BIF_X = '0'"><xsl:value-of select="$BLKD_MOD_LANE_W"/></xsl:when> + <xsl:otherwise><xsl:value-of select="$BLKD_MOD_W + 1"/></xsl:otherwise> + </xsl:choose> + </xsl:variable> + + + <line x1="{$horz_line_x1_}" + y1="{$horz_line_y_ - 2}" + x2="{$horz_line_x2_}" + y2="{$horz_line_y_ - 2}" + style="stroke:{$bifBusColor_};stroke-width:1"/> + + <use x="{$bif_x_}" y="{$bif_y_}" xlink:href="#{$bifBusStd_}_BifLabel"/> + +<!-- + <text class="bif_label" + x="{$bif_x_ + ceiling($BIF_W div 2)}" + y="{$bif_y_ + ceiling($BIF_H div 2) + 3}"> + <xsl:value-of select="$bifName_"/> + </text> +--> + + <xsl:call-template name="F_WriteText"> + <xsl:with-param name="iX" select="($bif_x_ + ceiling($BIF_W div 2))"/> + <xsl:with-param name="iY" select="($bif_y_ + ceiling($BIF_H div 2) + 3)"/> + <xsl:with-param name="iText" select="$bifName_"/> + <xsl:with-param name="iClass" select="'bif_label'"/> + </xsl:call-template> + + </xsl:for-each> + + <xsl:variable name="intcIdx_"> + <xsl:choose> + <xsl:when test="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iProcInst)]/INTERRUPTINFO/@INTC_INDEX"> + <xsl:value-of select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iProcInst)]/INTERRUPTINFO/@INTC_INDEX"/> + </xsl:when> + <xsl:otherwise>"_no_interrupt_cntlr_"</xsl:otherwise> + </xsl:choose> + </xsl:variable> + +<!-- + <xsl:message> The intc index should <xsl:value-of select="$interrupt_cntlr_"/></xsl:message> + <xsl:message> The intc index is <xsl:value-of select="/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $interrupt_cntlr_)]/@INTC_INDEX"/></xsl:message> +--> + <xsl:if test="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(INTERRUPTINFO[(@INTC_INDEX = $intcIdx_)])]"> + + <xsl:variable name="intrColor_"> + <xsl:call-template name="F_IntcIdx2RGB"> + <xsl:with-param name="iIntcIdx" select="$intcIdx_"/> +<!-- + <xsl:with-param name="iIntcIdx" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $interrupt_cntlr_)]/INTERRUPTINFO/@INTC_INDEX"/> + --> + </xsl:call-template> + </xsl:variable> + + <xsl:call-template name="F_draw_InterruptedProc"> + <xsl:with-param name="iIntr_X" select="($BLKD_MOD_W - ceiling($BLKD_INTR_W div 2))"/> + <xsl:with-param name="iIntr_Y" select="3"/> + <xsl:with-param name="iIntr_COL" select="$intrColor_"/> + <xsl:with-param name="iIntr_IDX" select="$intcIdx_"/> + </xsl:call-template> + </xsl:if> + </g> + +</xsl:template> + +</xsl:stylesheet> diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtTinySvgDiag_BifShapes.xsl b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtTinySvgDiag_BifShapes.xsl new file mode 100644 index 000000000..7cbfab278 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtTinySvgDiag_BifShapes.xsl @@ -0,0 +1,241 @@ +<?xml version="1.0" standalone="no"?> +<xsl:stylesheet version="1.0" + xmlns:svg="http://www.w3.org/2000/svg" + xmlns:xsl="http://www.w3.org/1999/XSL/Transform" + xmlns:exsl="http://exslt.org/common" + xmlns:xlink="http://www.w3.org/1999/xlink"> + +<xsl:output method="xml" version="1.0" encoding="UTF-8" indent="yes" + doctype-public="-//W3C//DTD SVG 1.0//EN" + doctype-system="http://www.w3.org/TR/SVG/DTD/svg10.dtd"/> + +<!-- ======================= DEF BLOCK =================================== --> + +<xsl:template name="Define_ConnectedBifTypes"> + + <xsl:for-each select="exsl:node-set($COL_BUSSTDS)/BUSCOLOR"> + <xsl:variable name="busStd_" select="@BUSSTD"/> + + <xsl:for-each select="exsl:node-set($G_BIFTYPES)/BIFTYPE"> + <xsl:variable name="bifType_" select="@TYPE"/> + + <xsl:variable name="connectedBifs_cnt_" select="count($G_ROOT/EDKSYSTEM/MODULES/MODULE/BUSINTERFACE[((@IS_INMHS = 'TRUE') and (@TYPE = $bifType_) and (@BUSSTD = $busStd_))])"/> + + <xsl:if test="($connectedBifs_cnt_ > 0)"> +<!-- + <xsl:message>DEBUG : Connected BifType : <xsl:value-of select="$busStd_"/> : <xsl:value-of select="@TYPE"/> : <xsl:value-of select="$connectedBifs_cnt_"/> </xsl:message> +--> + <xsl:call-template name="Define_BifTypeConnector"> + <xsl:with-param name="iBusStd" select="$busStd_"/> + <xsl:with-param name="iBifType" select="$bifType_"/> + </xsl:call-template> + + <xsl:call-template name="Define_BifLabel"> + <xsl:with-param name="iBusStd" select="$busStd_"/> + </xsl:call-template> + + </xsl:if> + + </xsl:for-each> + + </xsl:for-each> + + <xsl:for-each select="exsl:node-set($G_BIFTYPES)/BIFTYPE"> + <xsl:variable name="bifType_" select="@TYPE"/> + + <xsl:call-template name="Define_BifTypeConnector"> + <xsl:with-param name="iBusStd" select="'KEY'"/> + <xsl:with-param name="iBifType" select="$bifType_"/> + </xsl:call-template> + + <xsl:call-template name="Define_BifLabel"> + <xsl:with-param name="iBusStd" select="'KEY'"/> + </xsl:call-template> + </xsl:for-each> + +</xsl:template> + +<xsl:template name="Define_BifLabel"> + + <xsl:param name="iBusStd" select="'OPB'"/> + + <xsl:variable name="busStdColor_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="$iBusStd"/> + </xsl:call-template> + </xsl:variable> + + <g id="{$iBusStd}_BifLabel"> + <rect x="0" + y="0" + rx="3" + ry="3" + width= "{$BIF_W}" + height="{$BIF_H}" + style="fill:{$busStdColor_}; stroke:black; stroke-width:1"/> + </g> + +</xsl:template> + + +<xsl:template name="Define_BifTypeConnector"> + + <xsl:param name="iBusStd" select="'OPB'"/> + <xsl:param name="iBifType" select="'USER'"/> + + <xsl:variable name="busStdColor_"> + <xsl:call-template name="F_BusStd2RGB"> + <xsl:with-param name="iBusStd" select="$iBusStd"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="busStdColor_lt_"> + <xsl:call-template name="F_BusStd2RGB_LT"> + <xsl:with-param name="iBusStd" select="$iBusStd"/> + </xsl:call-template> + </xsl:variable> + + <xsl:variable name="bifc_wi_" select="ceiling($BIFC_W div 3)"/> + <xsl:variable name="bifc_hi_" select="ceiling($BIFC_H div 3)"/> + + <xsl:choose> + + <xsl:when test="$iBifType = 'SLAVE'"> + <g id="{$iBusStd}_busconn_{$iBifType}"> + <circle + cx="{ceiling($BIFC_W div 2)}" + cy="{ceiling($BIFC_H div 2)}" + r="{ceiling($BIFC_W div 2)}" + style="fill:{$busStdColor_lt_}; stroke:{$busStdColor_}; stroke-width:1"/> + <circle + cx="{ceiling($BIFC_W div 2) + 0.5}" + cy="{ceiling($BIFC_H div 2)}" + r="{ceiling($BIFC_Wi div 2)}" + style="fill:{$busStdColor_}; stroke:none;"/> + </g> + </xsl:when> + + <xsl:when test="$iBifType = 'MASTER'"> + <g id="{$iBusStd}_busconn_{$iBifType}"> + <rect x="0" + y="0" + width= "{$BIFC_W}" + height="{$BIFC_H}" + style="fill:{$busStdColor_lt_}; stroke:{$busStdColor_}; stroke-width:1"/> + <rect x="{$BIFC_dx + 0.5}" + y="{$BIFC_dy}" + width= "{$BIFC_Wi}" + height="{$BIFC_Hi}" + style="fill:{$busStdColor_}; stroke:none;"/> + </g> + </xsl:when> + + <xsl:when test="$iBifType = 'INITIATOR'"> + <g id="{$iBusStd}_busconn_{$iBifType}"> + <rect x="0" + y="0" + width= "{$BIFC_W}" + height="{$BIFC_H}" + style="fill:{$busStdColor_lt_}; stroke:{$busStdColor_}; stroke-width:1"/> + <rect x="{$BIFC_dx + 0.5}" + y="{$BIFC_dy}" + width= "{$BIFC_Wi}" + height="{$BIFC_Hi}" + style="fill:{$busStdColor_}; stroke:none;"/> + </g> + </xsl:when> + + <xsl:when test="$iBifType = 'TARGET'"> + <g id="{$iBusStd}_busconn_{$iBifType}"> + <circle + cx="{ceiling($BIFC_W div 2)}" + cy="{ceiling($BIFC_H div 2)}" + r="{ceiling($BIFC_W div 2)}" + style="fill:{$busStdColor_lt_}; stroke:{$busStdColor_}; stroke-width:1"/> + <circle + cx="{ceiling($BIFC_W div 2) + 0.5}" + cy="{ceiling($BIFC_H div 2)}" + r="{ceiling($BIFC_Wi div 2)}" + style="fill:{$busStdColor_}; stroke:none;"/> + </g> + </xsl:when> + + <xsl:when test="$iBifType = 'MASTER_SLAVE'"> + <g id="{$iBusStd}_busconn_{$iBifType}"> + <circle + cx="{ceiling($BIFC_W div 2)}" + cy="{ceiling($BIFC_H div 2)}" + r="{ceiling($BIFC_W div 2)}" + style="fill:{$busStdColor_lt_}; stroke:{$busStdColor_}; stroke-width:1"/> + <circle + cx="{ceiling($BIFC_W div 2) + 0.5}" + cy="{ceiling($BIFC_H div 2)}" + r="{ceiling($BIFC_Wi div 2)}" + style="fill:{$busStdColor_}; stroke:none;"/> + <rect + x="0" + y="{ceiling($BIFC_H div 2)}" + width= "{$BIFC_W}" + height="{ceiling($BIFC_H div 2)}" + style="fill:{$busStdColor_lt_}; stroke:{$busStdColor_}; stroke-width:1"/> + <rect + x="{$BIFC_dx + 0.5}" + y="{ceiling($BIFC_H div 2)}" + width= "{$BIFC_Wi}" + height="{ceiling($BIFC_Hi div 2)}" + style="fill:{$busStdColor_}; stroke:none;"/> + </g> + </xsl:when> + + <xsl:when test="$iBifType = 'MONITOR'"> + <g id="{$iBusStd}_busconn_{$iBifType}"> + <rect + x="0" + y="0.5" + width= "{$BIFC_W}" + height="{ceiling($BIFC_Hi div 2)}" + style="fill:{$busStdColor_}; stroke:none;"/> + <rect + x="0" + y="{ceiling($BIFC_H div 2) + 4}" + width= "{$BIFC_W}" + height="{ceiling($BIFC_Hi div 2)}" + style="fill:{$busStdColor_}; stroke:none;"/> + </g> + </xsl:when> + + <xsl:when test="$iBifType = 'USER'"> + <g id="{$iBusStd}_busconn_USER"> + <circle + cx="{ceiling($BIFC_W div 2)}" + cy="{ceiling($BIFC_H div 2)}" + r="{ceiling($BIFC_W div 2)}" + style="fill:{$busStdColor_lt_}; stroke:{$busStdColor_}; stroke-width:1"/> + <circle + cx="{ceiling($BIFC_W div 2) + 0.5}" + cy="{ceiling($BIFC_H div 2)}" + r="{ceiling($BIFC_Wi div 2)}" + style="fill:{$busStdColor_}; stroke:none;"/> + </g> + </xsl:when> + + <xsl:otherwise> + <g id="{$iBusStd}_busconn_{$iBifType}"> + <circle + cx="{ceiling($BIFC_W div 2)}" + cy="{ceiling($BIFC_H div 2)}" + r="{ceiling($BIFC_W div 2)}" + style="fill:{$COL_WHITE}; stroke:{$busStdColor_}; stroke-width:1"/> + <circle + cx="{ceiling($BIFC_W div 2) + 0.5}" + cy="{ceiling($BIFC_H div 2)}" + r="{ceiling($BIFC_Wi div 2)}" + style="fill:{$COL_WHITE}; stroke:none;"/> + </g> + </xsl:otherwise> + </xsl:choose> + +</xsl:template> + + +</xsl:stylesheet> diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/svg10.dtd b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/svg10.dtd new file mode 100644 index 000000000..110f5ced5 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/svg10.dtd @@ -0,0 +1,1704 @@ +<!-- ===================================================================== + This is the DTD for SVG 1.0. + + The specification for SVG that corresponds to this DTD is available at: + + http://www.w3.org/TR/2001/REC-SVG-20010904/ + + Copyright (c) 2000 W3C (MIT, INRIA, Keio), All Rights Reserved. + + For SVG 1.0: + + Namespace: + http://www.w3.org/2000/svg + + Public identifier: + PUBLIC "-//W3C//DTD SVG 1.0//EN" + + URI for the DTD: + http://www.w3.org/TR/2001/REC-SVG-20010904/DTD/svg10.dtd +============================================================================= --> + + +<!-- ============================================================== + ENTITY DECLARATIONS: Data types + ============================================================== --> + +<!ENTITY % BaselineShiftValue "CDATA"> + <!-- 'baseline-shift' property/attribute value (e.g., 'baseline', 'sub', etc.) --> + +<!ENTITY % Boolean "(false | true)"> + <!-- feature specification --> + +<!ENTITY % ClassList "CDATA"> + <!-- list of classes --> + +<!ENTITY % ClipValue "CDATA"> + <!-- 'clip' property/attribute value (e.g., 'auto', rect(...)) --> + +<!ENTITY % ClipPathValue "CDATA"> + <!-- 'clip-path' property/attribute value (e.g., 'none', %URI;) --> + +<!ENTITY % ClipFillRule "(nonzero | evenodd | inherit)"> + <!-- 'clip-rule' or fill-rule property/attribute value --> + +<!ENTITY % ContentType "CDATA"> + <!-- media type, as per [RFC2045] --> + +<!ENTITY % Coordinate "CDATA"> + <!-- a <coordinate> --> + +<!ENTITY % Coordinates "CDATA"> + <!-- a list of <coordinate>s --> + +<!ENTITY % Color "CDATA"> + <!-- a <color> value --> + +<!ENTITY % CursorValue "CDATA"> + <!-- 'cursor' property/attribute value (e.g., 'crosshair', %URI;) --> + +<!ENTITY % EnableBackgroundValue "CDATA"> + <!-- 'enable-background' property/attribute value (e.g., 'new', 'accumulate') --> + +<!ENTITY % ExtensionList "CDATA"> + <!-- extension list specification --> + +<!ENTITY % FeatureList "CDATA"> + <!-- feature list specification --> + +<!ENTITY % FilterValue "CDATA"> + <!-- 'filter' property/attribute value (e.g., 'none', %URI;) --> + +<!ENTITY % FontFamilyValue "CDATA"> + <!-- 'font-family' property/attribute value (i.e., list of fonts) --> + +<!ENTITY % FontSizeValue "CDATA"> + <!-- 'font-size' property/attribute value --> + +<!ENTITY % FontSizeAdjustValue "CDATA"> + <!-- 'font-size-adjust' property/attribute value --> + +<!ENTITY % GlyphOrientationHorizontalValue "CDATA"> + <!-- 'glyph-orientation-horizontal' property/attribute value (e.g., <angle>) --> + +<!ENTITY % GlyphOrientationVerticalValue "CDATA"> + <!-- 'glyph-orientation-vertical' property/attribute value (e.g., 'auto', <angle>) --> + +<!ENTITY % Integer "CDATA"> + <!-- a <integer> --> + +<!ENTITY % KerningValue "CDATA"> + <!-- 'kerning' property/attribute value (e.g., auto | <length>) --> + +<!ENTITY % LanguageCode "NMTOKEN"> + <!-- a language code, as per [RFC3066] --> + +<!ENTITY % LanguageCodes "CDATA"> + <!-- comma-separated list of language codes, as per [RFC3066] --> + +<!ENTITY % Length "CDATA"> + <!-- a <length> --> + +<!ENTITY % Lengths "CDATA"> + <!-- a list of <length>s --> + +<!ENTITY % LinkTarget "NMTOKEN"> + <!-- link to this target --> + +<!ENTITY % MarkerValue "CDATA"> + <!-- 'marker' property/attribute value (e.g., 'none', %URI;) --> + +<!ENTITY % MaskValue "CDATA"> + <!-- 'mask' property/attribute value (e.g., 'none', %URI;) --> + +<!ENTITY % MediaDesc "CDATA"> + <!-- comma-separated list of media descriptors. --> + +<!ENTITY % Number "CDATA"> + <!-- a <number> --> + +<!ENTITY % NumberOptionalNumber "CDATA"> + <!-- list of <number>s, but at least one and at most two --> + +<!ENTITY % NumberOrPercentage "CDATA"> + <!-- a <number> or a <percentage> --> + +<!ENTITY % Numbers "CDATA"> + <!-- a list of <number>s --> + +<!ENTITY % OpacityValue "CDATA"> + <!-- opacity value (e.g., <number>) --> + +<!ENTITY % Paint "CDATA"> + <!-- a 'fill' or 'stroke' property/attribute value: <paint> --> + +<!ENTITY % PathData "CDATA"> + <!-- a path data specification --> + +<!ENTITY % Points "CDATA"> + <!-- a list of points --> + +<!ENTITY % PreserveAspectRatioSpec "CDATA"> + <!-- 'preserveAspectRatio' attribute specification --> + +<!ENTITY % Script "CDATA"> + <!-- script expression --> + +<!ENTITY % SpacingValue "CDATA"> + <!-- 'letter-spacing' or 'word-spacing' property/attribute value (e.g., normal | <length>) --> + +<!ENTITY % StrokeDashArrayValue "CDATA"> + <!-- 'stroke-dasharray' property/attribute value (e.g., 'none', list of <number>s) --> + +<!ENTITY % StrokeDashOffsetValue "CDATA"> + <!-- 'stroke-dashoffset' property/attribute value (e.g., 'none', <legnth>) --> + +<!ENTITY % StrokeMiterLimitValue "CDATA"> + <!-- 'stroke-miterlimit' property/attribute value (e.g., <number>) --> + +<!ENTITY % StrokeWidthValue "CDATA"> + <!-- 'stroke-width' property/attribute value (e.g., <length>) --> + +<!ENTITY % StructuredText + "content CDATA #FIXED 'structured text'" > + +<!ENTITY % StyleSheet "CDATA"> + <!-- style sheet data --> + +<!ENTITY % SVGColor "CDATA"> + <!-- An SVG color value (RGB plus optional ICC) --> + +<!ENTITY % Text "CDATA"> + <!-- arbitrary text string --> + +<!ENTITY % TextDecorationValue "CDATA"> + <!-- 'text-decoration' property/attribute value (e.g., 'none', 'underline') --> + +<!ENTITY % TransformList "CDATA"> + <!-- list of transforms --> + +<!ENTITY % URI "CDATA"> + <!-- a Uniform Resource Identifier, see [URI] --> + +<!ENTITY % ViewBoxSpec "CDATA"> + <!-- 'viewBox' attribute specification --> + + +<!-- ============================================================== + ENTITY DECLARATIONS: Collections of common attributes + ============================================================== --> + +<!-- All elements have an ID. --> +<!ENTITY % stdAttrs + "id ID #IMPLIED + xml:base %URI; #IMPLIED" > + +<!-- Common attributes for elements that might contain character data content. --> +<!ENTITY % langSpaceAttrs + "xml:lang %LanguageCode; #IMPLIED + xml:space (default|preserve) #IMPLIED" > + +<!-- Common attributes to check for system capabilities. --> +<!ENTITY % testAttrs + "requiredFeatures %FeatureList; #IMPLIED + requiredExtensions %ExtensionList; #IMPLIED + systemLanguage %LanguageCodes; #IMPLIED" > + +<!-- For most uses of URI referencing: + standard XLink attributes other than xlink:href. --> +<!ENTITY % xlinkRefAttrs + "xmlns:xlink CDATA #FIXED 'http://www.w3.org/1999/xlink' + xlink:type (simple) #FIXED 'simple' + xlink:role %URI; #IMPLIED + xlink:arcrole %URI; #IMPLIED + xlink:title CDATA #IMPLIED + xlink:show (other) 'other' + xlink:actuate (onLoad) #FIXED 'onLoad'" > + +<!-- Standard XLink attributes for uses of URI referencing where xlink:show is 'embed' --> +<!ENTITY % xlinkRefAttrsEmbed + "xmlns:xlink CDATA #FIXED 'http://www.w3.org/1999/xlink' + xlink:type (simple) #FIXED 'simple' + xlink:role %URI; #IMPLIED + xlink:arcrole %URI; #IMPLIED + xlink:title CDATA #IMPLIED + xlink:show (embed) 'embed' + xlink:actuate (onLoad) #FIXED 'onLoad'" > + +<!ENTITY % graphicsElementEvents + "onfocusin %Script; #IMPLIED + onfocusout %Script; #IMPLIED + onactivate %Script; #IMPLIED + onclick %Script; #IMPLIED + onmousedown %Script; #IMPLIED + onmouseup %Script; #IMPLIED + onmouseover %Script; #IMPLIED + onmousemove %Script; #IMPLIED + onmouseout %Script; #IMPLIED + onload %Script; #IMPLIED" > + +<!ENTITY % documentEvents + "onunload %Script; #IMPLIED + onabort %Script; #IMPLIED + onerror %Script; #IMPLIED + onresize %Script; #IMPLIED + onscroll %Script; #IMPLIED + onzoom %Script; #IMPLIED" > + +<!ENTITY % animationEvents + "onbegin %Script; #IMPLIED + onend %Script; #IMPLIED + onrepeat %Script; #IMPLIED" > + +<!-- This entity allows for at most one of desc, title and metadata, + supplied in any order --> +<!ENTITY % descTitleMetadata + "(((desc,((title,metadata?)|(metadata,title?))?)| + (title,((desc,metadata?)|(metadata,desc?))?)| + (metadata,((desc,title?)|(title,desc?))?))?)" > + + +<!-- ============================================================== + ENTITY DECLARATIONS: Collections of presentation attributes + ============================================================== --> + +<!-- The following presentation attributes have to do with specifying color. --> +<!ENTITY % PresentationAttributes-Color + "color %Color; #IMPLIED + color-interpolation (auto | sRGB | linearRGB | inherit) #IMPLIED + color-rendering (auto | optimizeSpeed | optimizeQuality | inherit) #IMPLIED " > + +<!-- The following presentation attributes apply to container elements. --> +<!ENTITY % PresentationAttributes-Containers + "enable-background %EnableBackgroundValue; #IMPLIED " > + +<!-- The following presentation attributes apply to 'feFlood' elements. --> +<!ENTITY % PresentationAttributes-feFlood + "flood-color %SVGColor; #IMPLIED + flood-opacity %OpacityValue; #IMPLIED " > + +<!-- The following presentation attributes apply to filling and stroking operations. --> +<!ENTITY % PresentationAttributes-FillStroke + "fill %Paint; #IMPLIED + fill-opacity %OpacityValue; #IMPLIED + fill-rule %ClipFillRule; #IMPLIED + stroke %Paint; #IMPLIED + stroke-dasharray %StrokeDashArrayValue; #IMPLIED + stroke-dashoffset %StrokeDashOffsetValue; #IMPLIED + stroke-linecap (butt | round | square | inherit) #IMPLIED + stroke-linejoin (miter | round | bevel | inherit) #IMPLIED + stroke-miterlimit %StrokeMiterLimitValue; #IMPLIED + stroke-opacity %OpacityValue; #IMPLIED + stroke-width %StrokeWidthValue; #IMPLIED " > + +<!-- The following presentation attributes apply to filter primitives. --> +<!ENTITY % PresentationAttributes-FilterPrimitives + "color-interpolation-filters (auto | sRGB | linearRGB | inherit) #IMPLIED " > + +<!-- The following presentation attributes have to do with selecting a font to use. --> +<!ENTITY % PresentationAttributes-FontSpecification + "font-family %FontFamilyValue; #IMPLIED + font-size %FontSizeValue; #IMPLIED + font-size-adjust %FontSizeAdjustValue; #IMPLIED + font-stretch (normal | wider | narrower | ultra-condensed | extra-condensed | + condensed | semi-condensed | semi-expanded | expanded | + extra-expanded | ultra-expanded | inherit) #IMPLIED + font-style (normal | italic | oblique | inherit) #IMPLIED + font-variant (normal | small-caps | inherit) #IMPLIED + font-weight (normal | bold | bolder | lighter | 100 | 200 | 300 | + 400 | 500 | 600 | 700 | 800 | 900 | inherit) #IMPLIED " > + +<!-- The following presentation attributes apply to gradient 'stop' elements. --> +<!ENTITY % PresentationAttributes-Gradients + "stop-color %SVGColor; #IMPLIED + stop-opacity %OpacityValue; #IMPLIED " > + +<!-- The following presentation attributes apply to graphics elements. --> +<!ENTITY % PresentationAttributes-Graphics + "clip-path %ClipPathValue; #IMPLIED + clip-rule %ClipFillRule; #IMPLIED + cursor %CursorValue; #IMPLIED + display (inline | block | list-item | run-in | compact | marker | + table | inline-table | table-row-group | table-header-group | + table-footer-group | table-row | table-column-group | table-column | + table-cell | table-caption | none | inherit) #IMPLIED + filter %FilterValue; #IMPLIED + image-rendering (auto | optimizeSpeed | optimizeQuality | inherit) #IMPLIED + mask %MaskValue; #IMPLIED + opacity %OpacityValue; #IMPLIED + pointer-events (visiblePainted | visibleFill | visibleStroke | visible | + painted | fill | stroke | all | none | inherit) #IMPLIED + shape-rendering (auto | optimizeSpeed | crispEdges | geometricPrecision | inherit) #IMPLIED + text-rendering (auto | optimizeSpeed | optimizeLegibility | geometricPrecision | inherit) #IMPLIED + visibility (visible | hidden | inherit) #IMPLIED " > + +<!-- The following presentation attributes apply to 'image' elements. --> +<!ENTITY % PresentationAttributes-Images + "color-profile CDATA #IMPLIED " > + +<!--The following presentation attributes apply to 'feDiffuseLighting' and 'feSpecularLighting' elements. --> +<!ENTITY % PresentationAttributes-LightingEffects + "lighting-color %SVGColor; #IMPLIED " > + +<!-- The following presentation attributes apply to marker operations. --> +<!ENTITY % PresentationAttributes-Markers + "marker-start %MarkerValue; #IMPLIED + marker-mid %MarkerValue; #IMPLIED + marker-end %MarkerValue; #IMPLIED " > + +<!-- The following presentation attributes apply to text content elements. --> +<!ENTITY % PresentationAttributes-TextContentElements + "alignment-baseline (baseline | top | before-edge | text-top | text-before-edge | + middle | bottom | after-edge | text-bottom | text-after-edge | + ideographic | lower | hanging | mathematical | inherit) #IMPLIED + baseline-shift %BaselineShiftValue; #IMPLIED + direction (ltr | rtl | inherit) #IMPLIED + dominant-baseline (auto | autosense-script | no-change | reset| + ideographic | lower | hanging | mathematical | inherit ) #IMPLIED + glyph-orientation-horizontal %GlyphOrientationHorizontalValue; #IMPLIED + glyph-orientation-vertical %GlyphOrientationVerticalValue; #IMPLIED + kerning %KerningValue; #IMPLIED + letter-spacing %SpacingValue; #IMPLIED + text-anchor (start | middle | end | inherit) #IMPLIED + text-decoration %TextDecorationValue; #IMPLIED + unicode-bidi (normal | embed | bidi-override | inherit) #IMPLIED + word-spacing %SpacingValue; #IMPLIED " > + +<!-- The following presentation attributes apply to 'text' elements. --> +<!ENTITY % PresentationAttributes-TextElements + "writing-mode (lr-tb | rl-tb | tb-rl | lr | rl | tb | inherit) #IMPLIED " > + +<!-- The following presentation attributes apply to elements that establish viewports. --> +<!ENTITY % PresentationAttributes-Viewports + "clip %ClipValue; #IMPLIED + overflow (visible | hidden | scroll | auto | inherit) #IMPLIED " > + +<!--The following represents the complete list of presentation attributes. --> +<!ENTITY % PresentationAttributes-All + "%PresentationAttributes-Color; + %PresentationAttributes-Containers; + %PresentationAttributes-feFlood; + %PresentationAttributes-FillStroke; + %PresentationAttributes-FilterPrimitives; + %PresentationAttributes-FontSpecification; + %PresentationAttributes-Gradients; + %PresentationAttributes-Graphics; + %PresentationAttributes-Images; + %PresentationAttributes-LightingEffects; + %PresentationAttributes-Markers; + %PresentationAttributes-TextContentElements; + %PresentationAttributes-TextElements; + %PresentationAttributes-Viewports;" > + + + +<!-- ============================================================== + ENTITY DECLARATIONS: DTD extensions + ============================================================== --> + +<!-- Allow for extending the DTD with internal subset for + container and graphics elements --> +<!ENTITY % ceExt "" > +<!ENTITY % geExt "" > + + +<!-- ============================================================== + DECLARATIONS CORRESPONDING TO: Document Structure + ============================================================== --> + +<!ENTITY % svgExt "" > +<!ELEMENT svg (desc|title|metadata|defs| + path|text|rect|circle|ellipse|line|polyline|polygon| + use|image|svg|g|view|switch|a|altGlyphDef| + script|style|symbol|marker|clipPath|mask| + linearGradient|radialGradient|pattern|filter|cursor|font| + animate|set|animateMotion|animateColor|animateTransform| + color-profile|font-face + %ceExt;%svgExt;)* > +<!ATTLIST svg + xmlns CDATA #FIXED "http://www.w3.org/2000/svg" + xmlns:xlink CDATA #FIXED "http://www.w3.org/1999/xlink" + %stdAttrs; + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-All; + viewBox %ViewBoxSpec; #IMPLIED + preserveAspectRatio %PreserveAspectRatioSpec; 'xMidYMid meet' + zoomAndPan (disable | magnify) 'magnify' + %graphicsElementEvents; + %documentEvents; + version %Number; #FIXED "1.0" + x %Coordinate; #IMPLIED + y %Coordinate; #IMPLIED + width %Length; #IMPLIED + height %Length; #IMPLIED + contentScriptType %ContentType; "text/ecmascript" + contentStyleType %ContentType; "text/css" > + +<!ENTITY % gExt "" > +<!ELEMENT g (desc|title|metadata|defs| + path|text|rect|circle|ellipse|line|polyline|polygon| + use|image|svg|g|view|switch|a|altGlyphDef| + script|style|symbol|marker|clipPath|mask| + linearGradient|radialGradient|pattern|filter|cursor|font| + animate|set|animateMotion|animateColor|animateTransform| + color-profile|font-face + %ceExt;%gExt;)* > +<!ATTLIST g + %stdAttrs; + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-All; + transform %TransformList; #IMPLIED + %graphicsElementEvents; > + +<!ENTITY % defsExt "" > +<!ELEMENT defs (desc|title|metadata|defs| + path|text|rect|circle|ellipse|line|polyline|polygon| + use|image|svg|g|view|switch|a|altGlyphDef| + script|style|symbol|marker|clipPath|mask| + linearGradient|radialGradient|pattern|filter|cursor|font| + animate|set|animateMotion|animateColor|animateTransform| + color-profile|font-face + %ceExt;%defsExt;)* > +<!ATTLIST defs + %stdAttrs; + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-All; + transform %TransformList; #IMPLIED + %graphicsElementEvents; > + +<!ENTITY % descExt "" > +<!ELEMENT desc (#PCDATA %descExt;)* > +<!ATTLIST desc + %stdAttrs; + %langSpaceAttrs; + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %StructuredText; > + +<!ENTITY % titleExt "" > +<!ELEMENT title (#PCDATA %titleExt;)* > +<!ATTLIST title + %stdAttrs; + %langSpaceAttrs; + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %StructuredText; > + +<!ENTITY % symbolExt "" > +<!ELEMENT symbol (desc|title|metadata|defs| + path|text|rect|circle|ellipse|line|polyline|polygon| + use|image|svg|g|view|switch|a|altGlyphDef| + script|style|symbol|marker|clipPath|mask| + linearGradient|radialGradient|pattern|filter|cursor|font| + animate|set|animateMotion|animateColor|animateTransform| + color-profile|font-face + %ceExt;%symbolExt;)* > +<!ATTLIST symbol + %stdAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-All; + viewBox %ViewBoxSpec; #IMPLIED + preserveAspectRatio %PreserveAspectRatioSpec; 'xMidYMid meet' + %graphicsElementEvents; > + +<!ENTITY % useExt "" > +<!ELEMENT use (%descTitleMetadata;,(animate|set|animateMotion|animateColor|animateTransform + %geExt;%useExt;)*) > +<!ATTLIST use + %stdAttrs; + %xlinkRefAttrsEmbed; + xlink:href %URI; #REQUIRED + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-All; + transform %TransformList; #IMPLIED + %graphicsElementEvents; + x %Coordinate; #IMPLIED + y %Coordinate; #IMPLIED + width %Length; #IMPLIED + height %Length; #IMPLIED > + +<!ENTITY % imageExt "" > +<!ELEMENT image (%descTitleMetadata;,(animate|set|animateMotion|animateColor|animateTransform + %geExt;%imageExt;)*) > +<!ATTLIST image + %stdAttrs; + %xlinkRefAttrsEmbed; + xlink:href %URI; #REQUIRED + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-Graphics; + %PresentationAttributes-Images; + %PresentationAttributes-Viewports; + transform %TransformList; #IMPLIED + preserveAspectRatio %PreserveAspectRatioSpec; 'xMidYMid meet' + %graphicsElementEvents; + x %Coordinate; #IMPLIED + y %Coordinate; #IMPLIED + width %Length; #REQUIRED + height %Length; #REQUIRED > + +<!ENTITY % switchExt "" > +<!ELEMENT switch (%descTitleMetadata;, + (path|text|rect|circle|ellipse|line|polyline|polygon| + use|image|svg|g|switch|a|foreignObject| + animate|set|animateMotion|animateColor|animateTransform + %ceExt;%switchExt;)*) > +<!ATTLIST switch + %stdAttrs; + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-All; + transform %TransformList; #IMPLIED + %graphicsElementEvents; > + + +<!-- ============================================================== + DECLARATIONS CORRESPONDING TO: Styling + ============================================================== --> + +<!ELEMENT style (#PCDATA) > +<!ATTLIST style + %stdAttrs; + xml:space (preserve) #FIXED "preserve" + type %ContentType; #REQUIRED + media %MediaDesc; #IMPLIED + title %Text; #IMPLIED > + + +<!-- ============================================================== + DECLARATIONS CORRESPONDING TO: Paths + ============================================================== --> + +<!ENTITY % pathExt "" > +<!ELEMENT path (%descTitleMetadata;,(animate|set|animateMotion|animateColor|animateTransform + %geExt;%pathExt;)*) > +<!ATTLIST path + %stdAttrs; + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-FillStroke; + %PresentationAttributes-Graphics; + %PresentationAttributes-Markers; + transform %TransformList; #IMPLIED + %graphicsElementEvents; + d %PathData; #REQUIRED + pathLength %Number; #IMPLIED > + + +<!-- ============================================================== + DECLARATIONS CORRESPONDING TO: Basic Shapes + ============================================================== --> + +<!ENTITY % rectExt "" > +<!ELEMENT rect (%descTitleMetadata;,(animate|set|animateMotion|animateColor|animateTransform + %geExt;%rectExt;)*) > +<!ATTLIST rect + %stdAttrs; + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-FillStroke; + %PresentationAttributes-Graphics; + transform %TransformList; #IMPLIED + %graphicsElementEvents; + x %Coordinate; #IMPLIED + y %Coordinate; #IMPLIED + width %Length; #REQUIRED + height %Length; #REQUIRED + rx %Length; #IMPLIED + ry %Length; #IMPLIED > + +<!ENTITY % circleExt "" > +<!ELEMENT circle (%descTitleMetadata;,(animate|set|animateMotion|animateColor|animateTransform + %geExt;%circleExt;)*) > +<!ATTLIST circle + %stdAttrs; + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-FillStroke; + %PresentationAttributes-Graphics; + transform %TransformList; #IMPLIED + %graphicsElementEvents; + cx %Coordinate; #IMPLIED + cy %Coordinate; #IMPLIED + r %Length; #REQUIRED > + +<!ENTITY % ellipseExt "" > +<!ELEMENT ellipse (%descTitleMetadata;,(animate|set|animateMotion|animateColor|animateTransform + %geExt;%ellipseExt;)*) > +<!ATTLIST ellipse + %stdAttrs; + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-FillStroke; + %PresentationAttributes-Graphics; + transform %TransformList; #IMPLIED + %graphicsElementEvents; + cx %Coordinate; #IMPLIED + cy %Coordinate; #IMPLIED + rx %Length; #REQUIRED + ry %Length; #REQUIRED > + +<!ENTITY % lineExt "" > +<!ELEMENT line (%descTitleMetadata;,(animate|set|animateMotion|animateColor|animateTransform + %geExt;%lineExt;)*) > +<!ATTLIST line + %stdAttrs; + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-FillStroke; + %PresentationAttributes-Graphics; + %PresentationAttributes-Markers; + transform %TransformList; #IMPLIED + %graphicsElementEvents; + x1 %Coordinate; #IMPLIED + y1 %Coordinate; #IMPLIED + x2 %Coordinate; #IMPLIED + y2 %Coordinate; #IMPLIED > + +<!ENTITY % polylineExt "" > +<!ELEMENT polyline (%descTitleMetadata;,(animate|set|animateMotion|animateColor|animateTransform + %geExt;%polylineExt;)*) > +<!ATTLIST polyline + %stdAttrs; + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-FillStroke; + %PresentationAttributes-Graphics; + %PresentationAttributes-Markers; + transform %TransformList; #IMPLIED + %graphicsElementEvents; + points %Points; #REQUIRED > + +<!ENTITY % polygonExt "" > +<!ELEMENT polygon (%descTitleMetadata;,(animate|set|animateMotion|animateColor|animateTransform + %geExt;%polygonExt;)*) > +<!ATTLIST polygon + %stdAttrs; + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-FillStroke; + %PresentationAttributes-Graphics; + %PresentationAttributes-Markers; + transform %TransformList; #IMPLIED + %graphicsElementEvents; + points %Points; #REQUIRED > + + +<!-- ============================================================== + DECLARATIONS CORRESPONDING TO: Text + ============================================================== --> + +<!ENTITY % textExt "" > +<!ELEMENT text (#PCDATA|desc|title|metadata| + tspan|tref|textPath|altGlyph|a|animate|set| + animateMotion|animateColor|animateTransform + %geExt;%textExt;)* > +<!ATTLIST text + %stdAttrs; + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-FillStroke; + %PresentationAttributes-FontSpecification; + %PresentationAttributes-Graphics; + %PresentationAttributes-TextContentElements; + %PresentationAttributes-TextElements; + transform %TransformList; #IMPLIED + %graphicsElementEvents; + x %Coordinates; #IMPLIED + y %Coordinates; #IMPLIED + dx %Lengths; #IMPLIED + dy %Lengths; #IMPLIED + rotate %Numbers; #IMPLIED + textLength %Length; #IMPLIED + lengthAdjust (spacing|spacingAndGlyphs) #IMPLIED > + +<!ENTITY % tspanExt "" > +<!ELEMENT tspan (#PCDATA|desc|title|metadata|tspan|tref|altGlyph|a|animate|set|animateColor + %tspanExt;)* > +<!ATTLIST tspan + %stdAttrs; + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-FillStroke; + %PresentationAttributes-FontSpecification; + %PresentationAttributes-Graphics; + %PresentationAttributes-TextContentElements; + %graphicsElementEvents; + x %Coordinates; #IMPLIED + y %Coordinates; #IMPLIED + dx %Lengths; #IMPLIED + dy %Lengths; #IMPLIED + rotate %Numbers; #IMPLIED + textLength %Length; #IMPLIED + lengthAdjust (spacing|spacingAndGlyphs) #IMPLIED > + +<!ENTITY % trefExt "" > +<!ELEMENT tref (desc|title|metadata|animate|set|animateColor + %trefExt;)* > +<!ATTLIST tref + %stdAttrs; + %xlinkRefAttrs; + xlink:href %URI; #REQUIRED + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-FillStroke; + %PresentationAttributes-FontSpecification; + %PresentationAttributes-Graphics; + %PresentationAttributes-TextContentElements; + %graphicsElementEvents; + x %Coordinates; #IMPLIED + y %Coordinates; #IMPLIED + dx %Lengths; #IMPLIED + dy %Lengths; #IMPLIED + rotate %Numbers; #IMPLIED + textLength %Length; #IMPLIED + lengthAdjust (spacing|spacingAndGlyphs) #IMPLIED > + +<!ENTITY % textPathExt "" > +<!ELEMENT textPath (#PCDATA|desc|title|metadata|tspan|tref|altGlyph|a|animate|set|animateColor + %textPathExt;)* > +<!ATTLIST textPath + %stdAttrs; + %xlinkRefAttrs; + xlink:href %URI; #REQUIRED + %langSpaceAttrs; + %testAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-FillStroke; + %PresentationAttributes-FontSpecification; + %PresentationAttributes-Graphics; + %PresentationAttributes-TextContentElements; + %graphicsElementEvents; + startOffset %Length; #IMPLIED + textLength %Length; #IMPLIED + lengthAdjust (spacing|spacingAndGlyphs) #IMPLIED + method (align|stretch) #IMPLIED + spacing (auto|exact) #IMPLIED > + +<!ENTITY % altGlyphExt "" > +<!ELEMENT altGlyph (#PCDATA %altGlyphExt;)* > +<!ATTLIST altGlyph + %stdAttrs; + %xlinkRefAttrs; + xlink:href %URI; #IMPLIED + glyphRef CDATA #IMPLIED + format CDATA #IMPLIED + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-FillStroke; + %PresentationAttributes-FontSpecification; + %PresentationAttributes-Graphics; + %PresentationAttributes-TextContentElements; + %graphicsElementEvents; + x %Coordinates; #IMPLIED + y %Coordinates; #IMPLIED + dx %Lengths; #IMPLIED + dy %Lengths; #IMPLIED + rotate %Numbers; #IMPLIED > + +<!ENTITY % altGlyphDefExt "" > +<!ELEMENT altGlyphDef ((glyphRef+|altGlyphItem+) %altGlyphDefExt;) > +<!ATTLIST altGlyphDef + %stdAttrs; > + +<!ENTITY % altGlyphItemExt "" > +<!ELEMENT altGlyphItem (glyphRef+ %altGlyphItemExt;) > +<!ATTLIST altGlyphItem + %stdAttrs; > + +<!ELEMENT glyphRef EMPTY > +<!ATTLIST glyphRef + %stdAttrs; + %xlinkRefAttrs; + xlink:href %URI; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-FontSpecification; + glyphRef CDATA #IMPLIED + format CDATA #IMPLIED + x %Number; #IMPLIED + y %Number; #IMPLIED + dx %Number; #IMPLIED + dy %Number; #IMPLIED > + + +<!-- ============================================================== + DECLARATIONS CORRESPONDING TO: Painting: Filling, Stroking and Marker Symbols + ============================================================== --> + +<!ENTITY % markerExt "" > +<!ELEMENT marker (desc|title|metadata|defs| + path|text|rect|circle|ellipse|line|polyline|polygon| + use|image|svg|g|view|switch|a|altGlyphDef| + script|style|symbol|marker|clipPath|mask| + linearGradient|radialGradient|pattern|filter|cursor|font| + animate|set|animateMotion|animateColor|animateTransform| + color-profile|font-face + %ceExt;%markerExt;)* > +<!ATTLIST marker + %stdAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-All; + viewBox %ViewBoxSpec; #IMPLIED + preserveAspectRatio %PreserveAspectRatioSpec; 'xMidYMid meet' + refX %Coordinate; #IMPLIED + refY %Coordinate; #IMPLIED + markerUnits (strokeWidth | userSpaceOnUse) #IMPLIED + markerWidth %Length; #IMPLIED + markerHeight %Length; #IMPLIED + orient CDATA #IMPLIED > + + +<!-- ============================================================== + DECLARATIONS CORRESPONDING TO: Color + ============================================================== --> + +<!ELEMENT color-profile (%descTitleMetadata;) > +<!ATTLIST color-profile + %stdAttrs; + %xlinkRefAttrs; + xlink:href %URI; #IMPLIED + local CDATA #IMPLIED + name CDATA #REQUIRED + rendering-intent (auto | perceptual | relative-colorimetric | saturation | absolute-colorimetric) "auto" > + + +<!-- ============================================================== + DECLARATIONS CORRESPONDING TO: Gradients and Patterns + ============================================================== --> + +<!ENTITY % linearGradientExt "" > +<!ELEMENT linearGradient (%descTitleMetadata;,(stop|animate|set|animateTransform + %linearGradientExt;)*) > +<!ATTLIST linearGradient + %stdAttrs; + %xlinkRefAttrs; + xlink:href %URI; #IMPLIED + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-Gradients; + gradientUnits (userSpaceOnUse | objectBoundingBox) #IMPLIED + gradientTransform %TransformList; #IMPLIED + x1 %Coordinate; #IMPLIED + y1 %Coordinate; #IMPLIED + x2 %Coordinate; #IMPLIED + y2 %Coordinate; #IMPLIED + spreadMethod (pad | reflect | repeat) #IMPLIED > + + +<!ENTITY % radialGradientExt "" > +<!ELEMENT radialGradient (%descTitleMetadata;,(stop|animate|set|animateTransform + %radialGradientExt;)*) > +<!ATTLIST radialGradient + %stdAttrs; + %xlinkRefAttrs; + xlink:href %URI; #IMPLIED + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-Gradients; + gradientUnits (userSpaceOnUse | objectBoundingBox) #IMPLIED + gradientTransform %TransformList; #IMPLIED + cx %Coordinate; #IMPLIED + cy %Coordinate; #IMPLIED + r %Length; #IMPLIED + fx %Coordinate; #IMPLIED + fy %Coordinate; #IMPLIED + spreadMethod (pad | reflect | repeat) #IMPLIED > + + +<!ENTITY % stopExt "" > +<!ELEMENT stop (animate|set|animateColor + %stopExt;)* > +<!ATTLIST stop + %stdAttrs; + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-Gradients; + offset %NumberOrPercentage; #REQUIRED > + +<!ENTITY % patternExt "" > +<!ELEMENT pattern (desc|title|metadata|defs| + path|text|rect|circle|ellipse|line|polyline|polygon| + use|image|svg|g|view|switch|a|altGlyphDef| + script|style|symbol|marker|clipPath|mask| + linearGradient|radialGradient|pattern|filter|cursor|font| + animate|set|animateMotion|animateColor|animateTransform| + color-profile|font-face + %ceExt;%patternExt;)* > +<!ATTLIST pattern + %stdAttrs; + %xlinkRefAttrs; + xlink:href %URI; #IMPLIED + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-All; + viewBox %ViewBoxSpec; #IMPLIED + preserveAspectRatio %PreserveAspectRatioSpec; 'xMidYMid meet' + patternUnits (userSpaceOnUse | objectBoundingBox) #IMPLIED + patternContentUnits (userSpaceOnUse | objectBoundingBox) #IMPLIED + patternTransform %TransformList; #IMPLIED + x %Coordinate; #IMPLIED + y %Coordinate; #IMPLIED + width %Length; #IMPLIED + height %Length; #IMPLIED > + + +<!-- ============================================================== + DECLARATIONS CORRESPONDING TO: Clipping, Masking and Compositing + ============================================================== --> + +<!ENTITY % clipPathExt "" > +<!ELEMENT clipPath (%descTitleMetadata;, + (path|text|rect|circle|ellipse|line|polyline|polygon| + use|animate|set|animateMotion|animateColor|animateTransform + %ceExt;%clipPathExt;)*) > +<!ATTLIST clipPath + %stdAttrs; + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-FillStroke; + %PresentationAttributes-FontSpecification; + %PresentationAttributes-Graphics; + %PresentationAttributes-TextContentElements; + %PresentationAttributes-TextElements; + transform %TransformList; #IMPLIED + clipPathUnits (userSpaceOnUse | objectBoundingBox) #IMPLIED > + +<!ENTITY % maskExt "" > +<!ELEMENT mask (desc|title|metadata|defs| + path|text|rect|circle|ellipse|line|polyline|polygon| + use|image|svg|g|view|switch|a|altGlyphDef| + script|style|symbol|marker|clipPath|mask| + linearGradient|radialGradient|pattern|filter|cursor|font| + animate|set|animateMotion|animateColor|animateTransform| + color-profile|font-face + %ceExt;%maskExt;)* > +<!ATTLIST mask + %stdAttrs; + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-All; + maskUnits (userSpaceOnUse | objectBoundingBox) #IMPLIED + maskContentUnits (userSpaceOnUse | objectBoundingBox) #IMPLIED + x %Coordinate; #IMPLIED + y %Coordinate; #IMPLIED + width %Length; #IMPLIED + height %Length; #IMPLIED > + + +<!-- ============================================================== + DECLARATIONS CORRESPONDING TO: Filter Effects + ============================================================== --> + +<!ENTITY % filterExt "" > +<!ELEMENT filter (%descTitleMetadata;,(feBlend|feFlood| + feColorMatrix|feComponentTransfer| + feComposite|feConvolveMatrix|feDiffuseLighting|feDisplacementMap| + feGaussianBlur|feImage|feMerge| + feMorphology|feOffset|feSpecularLighting| + feTile|feTurbulence| + animate|set + %filterExt;)*) > +<!ATTLIST filter + %stdAttrs; + %xlinkRefAttrs; + xlink:href %URI; #IMPLIED + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-All; + filterUnits (userSpaceOnUse | objectBoundingBox) #IMPLIED + primitiveUnits (userSpaceOnUse | objectBoundingBox) #IMPLIED + x %Coordinate; #IMPLIED + y %Coordinate; #IMPLIED + width %Length; #IMPLIED + height %Length; #IMPLIED + filterRes %NumberOptionalNumber; #IMPLIED > + +<!ENTITY % filter_primitive_attributes + "x %Coordinate; #IMPLIED + y %Coordinate; #IMPLIED + width %Length; #IMPLIED + height %Length; #IMPLIED + result CDATA #IMPLIED" > + +<!ENTITY % filter_primitive_attributes_with_in + "%filter_primitive_attributes; + in CDATA #IMPLIED"> + +<!ELEMENT feDistantLight (animate|set)* > +<!ATTLIST feDistantLight + %stdAttrs; + azimuth %Number; #IMPLIED + elevation %Number; #IMPLIED > + +<!ELEMENT fePointLight (animate|set)* > +<!ATTLIST fePointLight + %stdAttrs; + x %Number; #IMPLIED + y %Number; #IMPLIED + z %Number; #IMPLIED > + +<!ELEMENT feSpotLight (animate|set)* > +<!ATTLIST feSpotLight + %stdAttrs; + x %Number; #IMPLIED + y %Number; #IMPLIED + z %Number; #IMPLIED + pointsAtX %Number; #IMPLIED + pointsAtY %Number; #IMPLIED + pointsAtZ %Number; #IMPLIED + specularExponent %Number; #IMPLIED + limitingConeAngle %Number; #IMPLIED > + +<!ELEMENT feBlend (animate|set)* > +<!ATTLIST feBlend + %stdAttrs; + %PresentationAttributes-FilterPrimitives; + %filter_primitive_attributes_with_in; + in2 CDATA #REQUIRED + mode (normal | multiply | screen | darken | lighten) "normal" > + +<!ELEMENT feColorMatrix (animate|set)* > +<!ATTLIST feColorMatrix + %stdAttrs; + %PresentationAttributes-FilterPrimitives; + %filter_primitive_attributes_with_in; + type (matrix | saturate | hueRotate | luminanceToAlpha) "matrix" + values CDATA #IMPLIED > + +<!ELEMENT feComponentTransfer (feFuncR?,feFuncG?,feFuncB?,feFuncA?) > +<!ATTLIST feComponentTransfer + %stdAttrs; + %PresentationAttributes-FilterPrimitives; + %filter_primitive_attributes_with_in; > + +<!ENTITY % component_transfer_function_attributes + "type (identity | table | discrete | linear | gamma) #REQUIRED + tableValues CDATA #IMPLIED + slope %Number; #IMPLIED + intercept %Number; #IMPLIED + amplitude %Number; #IMPLIED + exponent %Number; #IMPLIED + offset %Number; #IMPLIED" > + +<!ELEMENT feFuncR (animate|set)* > +<!ATTLIST feFuncR + %stdAttrs; + %component_transfer_function_attributes; > + +<!ELEMENT feFuncG (animate|set)* > +<!ATTLIST feFuncG + %stdAttrs; + %component_transfer_function_attributes; > + +<!ELEMENT feFuncB (animate|set)* > +<!ATTLIST feFuncB + %stdAttrs; + %component_transfer_function_attributes; > + +<!ELEMENT feFuncA (animate|set)* > +<!ATTLIST feFuncA + %stdAttrs; + %component_transfer_function_attributes; > + +<!ELEMENT feComposite (animate|set)* > +<!ATTLIST feComposite + %stdAttrs; + %PresentationAttributes-FilterPrimitives; + %filter_primitive_attributes_with_in; + in2 CDATA #REQUIRED + operator (over | in | out | atop | xor | arithmetic) "over" + k1 %Number; #IMPLIED + k2 %Number; #IMPLIED + k3 %Number; #IMPLIED + k4 %Number; #IMPLIED > + +<!ELEMENT feConvolveMatrix (animate|set)* > +<!ATTLIST feConvolveMatrix + %stdAttrs; + %PresentationAttributes-FilterPrimitives; + %filter_primitive_attributes_with_in; + order %NumberOptionalNumber; #REQUIRED + kernelMatrix CDATA #REQUIRED + divisor %Number; #IMPLIED + bias %Number; #IMPLIED + targetX %Integer; #IMPLIED + targetY %Integer; #IMPLIED + edgeMode (duplicate|wrap|none) "duplicate" + kernelUnitLength %NumberOptionalNumber; #IMPLIED + preserveAlpha %Boolean; #IMPLIED > + +<!ELEMENT feDiffuseLighting ((feDistantLight|fePointLight|feSpotLight),(animate|set|animateColor)*) > +<!ATTLIST feDiffuseLighting + %stdAttrs; + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-FilterPrimitives; + %PresentationAttributes-LightingEffects; + %filter_primitive_attributes_with_in; + surfaceScale %Number; #IMPLIED + diffuseConstant %Number; #IMPLIED + kernelUnitLength %NumberOptionalNumber; #IMPLIED > + +<!ELEMENT feDisplacementMap (animate|set)* > +<!ATTLIST feDisplacementMap + %stdAttrs; + %PresentationAttributes-FilterPrimitives; + %filter_primitive_attributes_with_in; + in2 CDATA #REQUIRED + scale %Number; #IMPLIED + xChannelSelector (R | G | B | A) "A" + yChannelSelector (R | G | B | A) "A" > + +<!ELEMENT feFlood (animate|set|animateColor)* > +<!ATTLIST feFlood + %stdAttrs; + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-feFlood; + %PresentationAttributes-FilterPrimitives; + %filter_primitive_attributes_with_in; > + +<!ELEMENT feGaussianBlur (animate|set)* > +<!ATTLIST feGaussianBlur + %stdAttrs; + %PresentationAttributes-FilterPrimitives; + %filter_primitive_attributes_with_in; + stdDeviation %NumberOptionalNumber; #IMPLIED > + +<!ELEMENT feImage (animate|set|animateTransform)* > +<!ATTLIST feImage + %stdAttrs; + %xlinkRefAttrsEmbed; + xlink:href %URI; #REQUIRED + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-All; + %filter_primitive_attributes; + preserveAspectRatio %PreserveAspectRatioSpec; 'xMidYMid meet' > + +<!ELEMENT feMerge (feMergeNode)* > +<!ATTLIST feMerge + %stdAttrs; + %PresentationAttributes-FilterPrimitives; + %filter_primitive_attributes; > + +<!ELEMENT feMergeNode (animate|set)* > +<!ATTLIST feMergeNode + %stdAttrs; + in CDATA #IMPLIED > + +<!ELEMENT feMorphology (animate|set)* > +<!ATTLIST feMorphology + %stdAttrs; + %PresentationAttributes-FilterPrimitives; + %filter_primitive_attributes_with_in; + operator (erode | dilate) "erode" + radius %NumberOptionalNumber; #IMPLIED > + +<!ELEMENT feOffset (animate|set)* > +<!ATTLIST feOffset + %stdAttrs; + %PresentationAttributes-FilterPrimitives; + %filter_primitive_attributes_with_in; + dx %Number; #IMPLIED + dy %Number; #IMPLIED > + +<!ELEMENT feSpecularLighting ((feDistantLight|fePointLight|feSpotLight),(animate|set|animateColor)*) > +<!ATTLIST feSpecularLighting + %stdAttrs; + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-FilterPrimitives; + %PresentationAttributes-LightingEffects; + %filter_primitive_attributes_with_in; + surfaceScale %Number; #IMPLIED + specularConstant %Number; #IMPLIED + specularExponent %Number; #IMPLIED + kernelUnitLength %NumberOptionalNumber; #IMPLIED > + +<!ELEMENT feTile (animate|set)* > +<!ATTLIST feTile + %stdAttrs; + %PresentationAttributes-FilterPrimitives; + %filter_primitive_attributes_with_in; > + +<!ELEMENT feTurbulence (animate|set)* > +<!ATTLIST feTurbulence + %stdAttrs; + %PresentationAttributes-FilterPrimitives; + %filter_primitive_attributes; + baseFrequency %NumberOptionalNumber; #IMPLIED + numOctaves %Integer; #IMPLIED + seed %Number; #IMPLIED + stitchTiles (stitch | noStitch) "noStitch" + type (fractalNoise | turbulence) "turbulence" > + + +<!-- ============================================================== + DECLARATIONS CORRESPONDING TO: Interactivity + ============================================================== --> + +<!ELEMENT cursor (%descTitleMetadata;) > +<!ATTLIST cursor + %stdAttrs; + %xlinkRefAttrs; + xlink:href %URI; #REQUIRED + %testAttrs; + externalResourcesRequired %Boolean; #IMPLIED + x %Coordinate; #IMPLIED + y %Coordinate; #IMPLIED > + + +<!-- ============================================================== + DECLARATIONS CORRESPONDING TO: Linking + ============================================================== --> + +<!ENTITY % aExt "" > +<!ELEMENT a (#PCDATA|desc|title|metadata|defs| + path|text|rect|circle|ellipse|line|polyline|polygon| + use|image|svg|g|view|switch|a|altGlyphDef| + script|style|symbol|marker|clipPath|mask| + linearGradient|radialGradient|pattern|filter|cursor|font| + animate|set|animateMotion|animateColor|animateTransform| + color-profile|font-face + %ceExt;%aExt;)* > +<!ATTLIST a + %stdAttrs; + xmlns:xlink CDATA #FIXED "http://www.w3.org/1999/xlink" + xlink:type (simple) #FIXED "simple" + xlink:role %URI; #IMPLIED + xlink:arcrole %URI; #IMPLIED + xlink:title CDATA #IMPLIED + xlink:show (new|replace) 'replace' + xlink:actuate (onRequest) #FIXED 'onRequest' + xlink:href %URI; #REQUIRED + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-All; + transform %TransformList; #IMPLIED + %graphicsElementEvents; + target %LinkTarget; #IMPLIED > + +<!ENTITY % viewExt "" > +<!ELEMENT view (%descTitleMetadata;%viewExt;) > +<!ATTLIST view + %stdAttrs; + externalResourcesRequired %Boolean; #IMPLIED + viewBox %ViewBoxSpec; #IMPLIED + preserveAspectRatio %PreserveAspectRatioSpec; 'xMidYMid meet' + zoomAndPan (disable | magnify) 'magnify' + viewTarget CDATA #IMPLIED > + + +<!-- ============================================================== + DECLARATIONS CORRESPONDING TO: Scripting + ============================================================== --> + +<!ELEMENT script (#PCDATA) > +<!ATTLIST script + %stdAttrs; + %xlinkRefAttrs; + xlink:href %URI; #IMPLIED + externalResourcesRequired %Boolean; #IMPLIED + type %ContentType; #REQUIRED > + + +<!-- ============================================================== + DECLARATIONS CORRESPONDING TO: Animation + ============================================================== --> + +<!ENTITY % animElementAttrs + "%xlinkRefAttrs; + xlink:href %URI; #IMPLIED" > + +<!ENTITY % animAttributeAttrs + "attributeName CDATA #REQUIRED + attributeType CDATA #IMPLIED" > + +<!ENTITY % animTimingAttrs + "begin CDATA #IMPLIED + dur CDATA #IMPLIED + end CDATA #IMPLIED + min CDATA #IMPLIED + max CDATA #IMPLIED + restart (always | never | whenNotActive) 'always' + repeatCount CDATA #IMPLIED + repeatDur CDATA #IMPLIED + fill (remove | freeze) 'remove'" > + +<!ENTITY % animValueAttrs + "calcMode (discrete | linear | paced | spline) 'linear' + values CDATA #IMPLIED + keyTimes CDATA #IMPLIED + keySplines CDATA #IMPLIED + from CDATA #IMPLIED + to CDATA #IMPLIED + by CDATA #IMPLIED" > + +<!ENTITY % animAdditionAttrs + "additive (replace | sum) 'replace' + accumulate (none | sum) 'none'" > + +<!ENTITY % animateExt "" > +<!ELEMENT animate (%descTitleMetadata;%animateExt;) > +<!ATTLIST animate + %stdAttrs; + %testAttrs; + externalResourcesRequired %Boolean; #IMPLIED + %animationEvents; + %animElementAttrs; + %animAttributeAttrs; + %animTimingAttrs; + %animValueAttrs; + %animAdditionAttrs; > + +<!ENTITY % setExt "" > +<!ELEMENT set (%descTitleMetadata;%setExt;) > +<!ATTLIST set + %stdAttrs; + %testAttrs; + externalResourcesRequired %Boolean; #IMPLIED + %animationEvents; + %animElementAttrs; + %animAttributeAttrs; + %animTimingAttrs; + to CDATA #IMPLIED > + +<!ENTITY % animateMotionExt "" > +<!ELEMENT animateMotion (%descTitleMetadata;,mpath? %animateMotionExt;) > +<!ATTLIST animateMotion + %stdAttrs; + %testAttrs; + externalResourcesRequired %Boolean; #IMPLIED + %animationEvents; + %animElementAttrs; + %animTimingAttrs; + calcMode (discrete | linear | paced | spline) 'paced' + values CDATA #IMPLIED + keyTimes CDATA #IMPLIED + keySplines CDATA #IMPLIED + from CDATA #IMPLIED + to CDATA #IMPLIED + by CDATA #IMPLIED + %animAdditionAttrs; + path CDATA #IMPLIED + keyPoints CDATA #IMPLIED + rotate CDATA #IMPLIED + origin CDATA #IMPLIED > + +<!ENTITY % mpathExt "" > +<!ELEMENT mpath (%descTitleMetadata;%mpathExt;) > +<!ATTLIST mpath + %stdAttrs; + %xlinkRefAttrs; + xlink:href %URI; #REQUIRED + externalResourcesRequired %Boolean; #IMPLIED > + +<!ENTITY % animateColorExt "" > +<!ELEMENT animateColor (%descTitleMetadata;%animateColorExt;) > +<!ATTLIST animateColor + %stdAttrs; + %testAttrs; + externalResourcesRequired %Boolean; #IMPLIED + %animationEvents; + %animElementAttrs; + %animAttributeAttrs; + %animTimingAttrs; + %animValueAttrs; + %animAdditionAttrs; > + +<!ENTITY % animateTransformExt "" > +<!ELEMENT animateTransform (%descTitleMetadata;%animateTransformExt;) > +<!ATTLIST animateTransform + %stdAttrs; + %testAttrs; + externalResourcesRequired %Boolean; #IMPLIED + %animationEvents; + %animElementAttrs; + %animAttributeAttrs; + %animTimingAttrs; + %animValueAttrs; + %animAdditionAttrs; + type (translate | scale | rotate | skewX | skewY) "translate" > + + +<!-- ============================================================== + DECLARATIONS CORRESPONDING TO: Fonts + ============================================================== --> + +<!ENTITY % fontExt "" > +<!ELEMENT font (%descTitleMetadata;,font-face, + missing-glyph,(glyph|hkern|vkern %fontExt;)*) > +<!ATTLIST font + %stdAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-All; + horiz-origin-x %Number; #IMPLIED + horiz-origin-y %Number; #IMPLIED + horiz-adv-x %Number; #REQUIRED + vert-origin-x %Number; #IMPLIED + vert-origin-y %Number; #IMPLIED + vert-adv-y %Number; #IMPLIED > + +<!ENTITY % glyphExt "" > +<!ELEMENT glyph (desc|title|metadata|defs| + path|text|rect|circle|ellipse|line|polyline|polygon| + use|image|svg|g|view|switch|a|altGlyphDef| + script|style|symbol|marker|clipPath|mask| + linearGradient|radialGradient|pattern|filter|cursor|font| + animate|set|animateMotion|animateColor|animateTransform| + color-profile|font-face + %glyphExt;)* > +<!ATTLIST glyph + %stdAttrs; + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-All; + unicode CDATA #IMPLIED + glyph-name CDATA #IMPLIED + d %PathData; #IMPLIED + orientation CDATA #IMPLIED + arabic-form CDATA #IMPLIED + lang %LanguageCodes; #IMPLIED + horiz-adv-x %Number; #IMPLIED + vert-origin-x %Number; #IMPLIED + vert-origin-y %Number; #IMPLIED + vert-adv-y %Number; #IMPLIED > + +<!ENTITY % missing-glyphExt "" > +<!ELEMENT missing-glyph (desc|title|metadata|defs| + path|text|rect|circle|ellipse|line|polyline|polygon| + use|image|svg|g|view|switch|a|altGlyphDef| + script|style|symbol|marker|clipPath|mask| + linearGradient|radialGradient|pattern|filter|cursor|font| + animate|set|animateMotion|animateColor|animateTransform| + color-profile|font-face + %missing-glyphExt;)* > +<!ATTLIST missing-glyph + %stdAttrs; + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-All; + d %PathData; #IMPLIED + horiz-adv-x %Number; #IMPLIED + vert-origin-x %Number; #IMPLIED + vert-origin-y %Number; #IMPLIED + vert-adv-y %Number; #IMPLIED > + +<!ELEMENT hkern EMPTY > +<!ATTLIST hkern + %stdAttrs; + u1 CDATA #IMPLIED + g1 CDATA #IMPLIED + u2 CDATA #IMPLIED + g2 CDATA #IMPLIED + k %Number; #REQUIRED > + +<!ELEMENT vkern EMPTY > +<!ATTLIST vkern + %stdAttrs; + u1 CDATA #IMPLIED + g1 CDATA #IMPLIED + u2 CDATA #IMPLIED + g2 CDATA #IMPLIED + k %Number; #REQUIRED > + +<!ELEMENT font-face (%descTitleMetadata;,font-face-src?,definition-src?) > +<!ATTLIST font-face + %stdAttrs; + font-family CDATA #IMPLIED + font-style CDATA #IMPLIED + font-variant CDATA #IMPLIED + font-weight CDATA #IMPLIED + font-stretch CDATA #IMPLIED + font-size CDATA #IMPLIED + unicode-range CDATA #IMPLIED + units-per-em %Number; #IMPLIED + panose-1 CDATA #IMPLIED + stemv %Number; #IMPLIED + stemh %Number; #IMPLIED + slope %Number; #IMPLIED + cap-height %Number; #IMPLIED + x-height %Number; #IMPLIED + accent-height %Number; #IMPLIED + ascent %Number; #IMPLIED + descent %Number; #IMPLIED + widths CDATA #IMPLIED + bbox CDATA #IMPLIED + ideographic %Number; #IMPLIED + alphabetic %Number; #IMPLIED + mathematical %Number; #IMPLIED + hanging %Number; #IMPLIED + v-ideographic %Number; #IMPLIED + v-alphabetic %Number; #IMPLIED + v-mathematical %Number; #IMPLIED + v-hanging %Number; #IMPLIED + underline-position %Number; #IMPLIED + underline-thickness %Number; #IMPLIED + strikethrough-position %Number; #IMPLIED + strikethrough-thickness %Number; #IMPLIED + overline-position %Number; #IMPLIED + overline-thickness %Number; #IMPLIED > + +<!ELEMENT font-face-src (font-face-uri|font-face-name)+ > +<!ATTLIST font-face-src + %stdAttrs; > + +<!ELEMENT font-face-uri (font-face-format*) > +<!ATTLIST font-face-uri + %stdAttrs; + %xlinkRefAttrs; + xlink:href %URI; #REQUIRED > + +<!ELEMENT font-face-format EMPTY > +<!ATTLIST font-face-format + %stdAttrs; + string CDATA #IMPLIED > + +<!ELEMENT font-face-name EMPTY > +<!ATTLIST font-face-name + %stdAttrs; + name CDATA #IMPLIED > + +<!ELEMENT definition-src EMPTY > +<!ATTLIST definition-src + %stdAttrs; + %xlinkRefAttrs; + xlink:href %URI; #REQUIRED > + + +<!-- ============================================================== + DECLARATIONS CORRESPONDING TO: Metadata + ============================================================== --> + +<!ENTITY % metadataExt "" > +<!ELEMENT metadata (#PCDATA %metadataExt;)* > +<!ATTLIST metadata + %stdAttrs; > + + +<!-- ============================================================== + DECLARATIONS CORRESPONDING TO: Extensibility + ============================================================== --> + +<!ENTITY % foreignObjectExt "" > +<!ELEMENT foreignObject (#PCDATA %ceExt;%foreignObjectExt;)* > +<!ATTLIST foreignObject + %stdAttrs; + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-All; + transform %TransformList; #IMPLIED + %graphicsElementEvents; + x %Coordinate; #IMPLIED + y %Coordinate; #IMPLIED + width %Length; #REQUIRED + height %Length; #REQUIRED + %StructuredText; > diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/bitinit.opt b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/bitinit.opt new file mode 100644 index 000000000..a0575e42f --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/bitinit.opt @@ -0,0 +1 @@ + $(PPC440_0_BOOTLOOP)
diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/_xmsgs/map.xmsgs b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/_xmsgs/map.xmsgs new file mode 100644 index 000000000..054e8b25e --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/_xmsgs/map.xmsgs @@ -0,0 +1,254 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- IMPORTANT: This is an internal file that has been generated + by the Xilinx ISE software. Any direct editing or + changes made to this file may result in unpredictable + behavior or data corruption. It is strongly advised that + users do not edit the contents of this file. --> +<messages> +<msg type="info" file="Map" num="220" delta="old" >The command line option -timing is automatically supported for this architecture. Therefore, it is not necessary to specify this option. +</msg> + +<msg type="warning" file="LIT" num="243" delta="old" >Logical network <arg fmt="%s" index="1">N194</arg> has no load. +</msg> + +<msg type="warning" file="LIT" num="395" delta="new" >The above <arg fmt="%s" index="1">warning</arg> message is repeated <arg fmt="%d" index="2">1200</arg> more times for the following (max. 5 shown): +<arg fmt="%s" index="3">N195, +N196, +N197, +N198, +N199</arg> +To see the details of these <arg fmt="%s" index="4">warning</arg> messages, please use the -detail switch. +</msg> + +<msg type="info" file="MapLib" num="562" delta="old" >No environment variables are currently set. +</msg> + +<msg type="info" file="MapLib" num="159" delta="old" >Net Timing constraints on signal <arg fmt="%s" index="1">fpga_0_SysACE_CompactFlash_SysACE_CLK_pin</arg> are pushed forward through input buffer. +</msg> + +<msg type="info" file="MapLib" num="856" delta="old" >PLL_ADV <arg fmt="%s" index="1">clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst</arg> CLKIN2 pin was disconnected because a constant 1 is driving the CLKINSEL pin. +</msg> + +<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin</arg> connected to top level port <arg fmt="%s" index="2">fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin</arg> has been removed. +</msg> + +<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">fpga_0_Ethernet_MAC_PHY_col_pin</arg> connected to top level port <arg fmt="%s" index="2">fpga_0_Ethernet_MAC_PHY_col_pin</arg> has been removed. +</msg> + +<msg type="warning" file="MapLib" num="41" delta="old" >All members of TNM group "<arg fmt="%s" index="1">ppc440_0_PPCS0PLBMBUSY</arg>" have been optimized out of the design. +</msg> + +<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0</arg> +of frag <arg fmt="%s" index="2">REGCLKAU</arg> connected to power/ground net <arg fmt="%s" index="3">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAU_tiesig</arg> +</msg> + +<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0</arg> +of frag <arg fmt="%s" index="2">REGCLKAL</arg> connected to power/ground net <arg fmt="%s" index="3">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAL_tiesig</arg> +</msg> + +<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1</arg> +of frag <arg fmt="%s" index="2">REGCLKAU</arg> connected to power/ground net <arg fmt="%s" index="3">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAU_tiesig</arg> +</msg> + +<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1</arg> +of frag <arg fmt="%s" index="2">REGCLKAL</arg> connected to power/ground net <arg fmt="%s" index="3">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAL_tiesig</arg> +</msg> + +<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst</arg> +of frag <arg fmt="%s" index="2">REGCLKAU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAU_tiesig</arg> +</msg> + +<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst</arg> +of frag <arg fmt="%s" index="2">REGCLKAL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAL_tiesig</arg> +</msg> + +<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst</arg> +of frag <arg fmt="%s" index="2">REGCLKAU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAU_tiesig</arg> +</msg> + +<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst</arg> +of frag <arg fmt="%s" index="2">REGCLKAL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAL_tiesig</arg> +</msg> + +<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/oq_fifo/Mram_regBank</arg> +of frag <arg fmt="%s" index="2">RDRCLKU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKU_tiesig</arg> +</msg> + +<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/oq_fifo/Mram_regBank</arg> +of frag <arg fmt="%s" index="2">RDRCLKL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKL_tiesig</arg> +</msg> + +<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg> +of frag <arg fmt="%s" index="2">RDRCLKU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig</arg> +</msg> + +<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg> +of frag <arg fmt="%s" index="2">RDRCLKL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig</arg> +</msg> + +<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg> +of frag <arg fmt="%s" index="2">RDRCLKU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig</arg> +</msg> + +<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg> +of frag <arg fmt="%s" index="2">RDRCLKL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig</arg> +</msg> + +<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COMP_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg> +of frag <arg fmt="%s" index="2">RDRCLKU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COMP_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig</arg> +</msg> + +<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COMP_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg> +of frag <arg fmt="%s" index="2">RDRCLKL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COMP_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig</arg> +</msg> + +<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg> +of frag <arg fmt="%s" index="2">RDRCLKU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig</arg> +</msg> + +<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg> +of frag <arg fmt="%s" index="2">RDRCLKL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig</arg> +</msg> + +<msg type="info" file="Pack" num="1716" delta="old" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius) +</msg> + +<msg type="info" file="Pack" num="1720" delta="old" >Initializing voltage to <arg fmt="%0.3f" index="1">0.950</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">0.950</arg> to <arg fmt="%0.3f" index="3">1.050</arg> Volts) +</msg> + +<msg type="warning" file="Timing" num="3223" delta="old" >Timing constraint <arg fmt="%s" index="1">TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP "TNM_CLK0" TS_MC_CLK * 4</arg> ignored during timing analysis.</msg> + +<msg type="info" file="Timing" num="3386" delta="old" >Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</msg> + +<msg type="info" file="Map" num="215" delta="old" >The Interim Design Summary has been generated in the MAP Report (.mrp). +</msg> + +<msg type="warning" file="Place" num="838" delta="old" >An IO Bus with more than one IO standard is found. +<arg fmt="%s" index="1">Components associated with this bus are as follows: + Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<7> IOSTANDARD = LVCMOS25 + Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<6> IOSTANDARD = LVCMOS25 + Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<5> IOSTANDARD = LVCMOS25 + Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<4> IOSTANDARD = LVCMOS18 + Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25 + Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS18 + Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS18 + Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS18 + +</arg> +</msg> + +<msg type="warning" file="Place" num="838" delta="old" >An IO Bus with more than one IO standard is found. +<arg fmt="%s" index="1">Components associated with this bus are as follows: + Comp: fpga_0_SRAM_Mem_DQ_pin<31> IOSTANDARD = LVDCI_33 + Comp: fpga_0_SRAM_Mem_DQ_pin<30> IOSTANDARD = LVDCI_33 + Comp: fpga_0_SRAM_Mem_DQ_pin<29> IOSTANDARD = LVDCI_33 + Comp: fpga_0_SRAM_Mem_DQ_pin<28> IOSTANDARD = LVDCI_33 + Comp: fpga_0_SRAM_Mem_DQ_pin<27> IOSTANDARD = LVDCI_33 + Comp: fpga_0_SRAM_Mem_DQ_pin<26> IOSTANDARD = LVDCI_33 + Comp: fpga_0_SRAM_Mem_DQ_pin<25> IOSTANDARD = LVDCI_33 + Comp: fpga_0_SRAM_Mem_DQ_pin<24> IOSTANDARD = LVDCI_33 + Comp: fpga_0_SRAM_Mem_DQ_pin<23> IOSTANDARD = LVDCI_33 + Comp: fpga_0_SRAM_Mem_DQ_pin<22> IOSTANDARD = LVDCI_33 + Comp: fpga_0_SRAM_Mem_DQ_pin<21> IOSTANDARD = LVDCI_33 + Comp: fpga_0_SRAM_Mem_DQ_pin<20> IOSTANDARD = LVDCI_33 + Comp: fpga_0_SRAM_Mem_DQ_pin<19> IOSTANDARD = LVDCI_33 + Comp: fpga_0_SRAM_Mem_DQ_pin<18> IOSTANDARD = LVDCI_33 + Comp: fpga_0_SRAM_Mem_DQ_pin<17> IOSTANDARD = LVDCI_33 + Comp: fpga_0_SRAM_Mem_DQ_pin<16> IOSTANDARD = LVDCI_33 + Comp: fpga_0_SRAM_Mem_DQ_pin<15> IOSTANDARD = LVCMOS33 + Comp: fpga_0_SRAM_Mem_DQ_pin<14> IOSTANDARD = LVCMOS33 + Comp: fpga_0_SRAM_Mem_DQ_pin<13> IOSTANDARD = LVCMOS33 + Comp: fpga_0_SRAM_Mem_DQ_pin<12> IOSTANDARD = LVCMOS33 + Comp: fpga_0_SRAM_Mem_DQ_pin<11> IOSTANDARD = LVCMOS33 + Comp: fpga_0_SRAM_Mem_DQ_pin<10> IOSTANDARD = LVCMOS33 + Comp: fpga_0_SRAM_Mem_DQ_pin<9> IOSTANDARD = LVCMOS33 + Comp: fpga_0_SRAM_Mem_DQ_pin<8> IOSTANDARD = LVCMOS33 + Comp: fpga_0_SRAM_Mem_DQ_pin<7> IOSTANDARD = LVCMOS33 + Comp: fpga_0_SRAM_Mem_DQ_pin<6> IOSTANDARD = LVCMOS33 + Comp: fpga_0_SRAM_Mem_DQ_pin<5> IOSTANDARD = LVCMOS33 + Comp: fpga_0_SRAM_Mem_DQ_pin<4> IOSTANDARD = LVCMOS33 + Comp: fpga_0_SRAM_Mem_DQ_pin<3> IOSTANDARD = LVCMOS33 + Comp: fpga_0_SRAM_Mem_DQ_pin<2> IOSTANDARD = LVCMOS33 + Comp: fpga_0_SRAM_Mem_DQ_pin<1> IOSTANDARD = LVCMOS33 + Comp: fpga_0_SRAM_Mem_DQ_pin<0> IOSTANDARD = LVCMOS33 + +</arg> +</msg> + +<msg type="info" file="Pack" num="1650" delta="old" >Map created a placed design. +</msg> + +<msg type="warning" file="PhysDesignRules" num="1842" delta="new" >One or more GTXs are being used in this design. Evaluate the SelectIO-To-GTX Crosstalk section of the Virtex-5 RocketIO GTX Transceiver User Guide to ensure that the design SelectIO usage meets the guidelines to minimize the impact on GTX performance. +</msg> + +<msg type="warning" file="PhysDesignRules" num="372" delta="old" >Gated clock. Clock net <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/icdrreset<0></arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. +</msg> + +<msg type="warning" file="PhysDesignRules" num="372" delta="old" >Gated clock. Clock net <arg fmt="%s" index="1">Ethernet_MAC/Ethernet_MAC/phy_tx_clk_i</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. +</msg> + +<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal <<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/sig_sb_txrem_n<0></arg>> is incomplete. The signal does not drive any load pins in the design. +</msg> + +<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal <<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/sig_MB_TxREMn<0></arg>> is incomplete. The signal does not drive any load pins in the design. +</msg> + +<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal <<arg fmt="%s" index="1">xps_bram_if_cntlr_1_port_BRAM_Addr<30></arg>> is incomplete. The signal does not drive any load pins in the design. +</msg> + +<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal <<arg fmt="%s" index="1">xps_bram_if_cntlr_1_port_BRAM_Addr<31></arg>> is incomplete. The signal does not drive any load pins in the design. +</msg> + +<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal <<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/sig_MB_RxFull</arg>> is incomplete. The signal does not drive any load pins in the design. +</msg> + +<msg type="warning" file="PhysDesignRules" num="1269" delta="old" >Dangling pins on block:<<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce</arg>>:<<arg fmt="%s" index="2">ILOGIC_IFF</arg>>. The Q1 output pin of IFF is not used. +</msg> + +<msg type="warning" file="PhysDesignRules" num="1273" delta="old" >Dangling pins on block:<<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce</arg>>:<<arg fmt="%s" index="2">ILOGIC_IFF</arg>>. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured. +</msg> + +<msg type="warning" file="PhysDesignRules" num="1269" delta="old" >Dangling pins on block:<<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce</arg>>:<<arg fmt="%s" index="2">ILOGIC_IFF</arg>>. The Q1 output pin of IFF is not used. +</msg> + +<msg type="warning" file="PhysDesignRules" num="1273" delta="old" >Dangling pins on block:<<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce</arg>>:<<arg fmt="%s" index="2">ILOGIC_IFF</arg>>. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured. +</msg> + +<msg type="warning" file="PhysDesignRules" num="1269" delta="old" >Dangling pins on block:<<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce</arg>>:<<arg fmt="%s" index="2">ILOGIC_IFF</arg>>. The Q1 output pin of IFF is not used. +</msg> + +<msg type="warning" file="PhysDesignRules" num="1273" delta="old" >Dangling pins on block:<<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce</arg>>:<<arg fmt="%s" index="2">ILOGIC_IFF</arg>>. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured. +</msg> + +<msg type="warning" file="PhysDesignRules" num="1269" delta="old" >Dangling pins on block:<<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/u_iddr_dq_ce</arg>>:<<arg fmt="%s" index="2">ILOGIC_IFF</arg>>. The Q1 output pin of IFF is not used. +</msg> + +<msg type="warning" file="PhysDesignRules" num="1273" delta="old" >Dangling pins on block:<<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/u_iddr_dq_ce</arg>>:<<arg fmt="%s" index="2">ILOGIC_IFF</arg>>. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured. +</msg> + +<msg type="warning" file="PhysDesignRules" num="1269" delta="old" >Dangling pins on block:<<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce</arg>>:<<arg fmt="%s" index="2">ILOGIC_IFF</arg>>. The Q1 output pin of IFF is not used. +</msg> + +<msg type="warning" file="PhysDesignRules" num="1273" delta="old" >Dangling pins on block:<<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce</arg>>:<<arg fmt="%s" index="2">ILOGIC_IFF</arg>>. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured. +</msg> + +<msg type="warning" file="PhysDesignRules" num="1269" delta="old" >Dangling pins on block:<<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/u_iddr_dq_ce</arg>>:<<arg fmt="%s" index="2">ILOGIC_IFF</arg>>. The Q1 output pin of IFF is not used. +</msg> + +<msg type="warning" file="PhysDesignRules" num="1273" delta="old" >Dangling pins on block:<<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/u_iddr_dq_ce</arg>>:<<arg fmt="%s" index="2">ILOGIC_IFF</arg>>. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured. +</msg> + +<msg type="warning" file="PhysDesignRules" num="1269" delta="old" >Dangling pins on block:<<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[3].u_iob_dqs/u_iddr_dq_ce</arg>>:<<arg fmt="%s" index="2">ILOGIC_IFF</arg>>. The Q1 output pin of IFF is not used. +</msg> + +<msg type="warning" file="PhysDesignRules" num="1273" delta="old" >Dangling pins on block:<<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[3].u_iob_dqs/u_iddr_dq_ce</arg>>:<<arg fmt="%s" index="2">ILOGIC_IFF</arg>>. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured. +</msg> + +<msg type="warning" file="PhysDesignRules" num="1269" delta="old" >Dangling pins on block:<<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce</arg>>:<<arg fmt="%s" index="2">ILOGIC_IFF</arg>>. The Q1 output pin of IFF is not used. +</msg> + +<msg type="warning" file="PhysDesignRules" num="1273" delta="old" >Dangling pins on block:<<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce</arg>>:<<arg fmt="%s" index="2">ILOGIC_IFF</arg>>. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured. +</msg> + +</messages> + diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/_xmsgs/ngcbuild.xmsgs b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/_xmsgs/ngcbuild.xmsgs new file mode 100644 index 000000000..f84336aac --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/_xmsgs/ngcbuild.xmsgs @@ -0,0 +1,9 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- IMPORTANT: This is an internal file that has been generated + by the Xilinx ISE software. Any direct editing or + changes made to this file may result in unpredictable + behavior or data corruption. It is strongly advised that + users do not edit the contents of this file. --> +<messages> +</messages> + diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/_xmsgs/ngdbuild.xmsgs b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/_xmsgs/ngdbuild.xmsgs new file mode 100644 index 000000000..3372d0481 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/_xmsgs/ngdbuild.xmsgs @@ -0,0 +1,1073 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- IMPORTANT: This is an internal file that has been generated + by the Xilinx ISE software. Any direct editing or + changes made to this file may result in unpredictable + behavior or data corruption. It is strongly advised that + users do not edit the contents of this file. --> +<messages> +<msg type="warning" file="NgdBuild" num="931" delta="old" >The value of SIM_DEVICE on instance '<arg fmt="%s" index="1">clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST</arg>' of type <arg fmt="%s" index="2">DCM_ADV</arg> has been changed from '<arg fmt="%s" index="3">VIRTEX4</arg>' to '<arg fmt="%s" index="4">VIRTEX5</arg>' to correct post-ngdbuild and timing simulation for this primitive. In order for functional simulation to be correct, the value of SIM_DEVICE should be changed in this same manner in the source netlist or constraint file. +</msg> + +<msg type="warning" file="ConstraintSystem" num="3" delta="new" >Constraint <arg fmt="%s" index="1"><TIMESPEC "TS_MC_RD_DATA_SEL" = FROM "TNM_RD_DATA_SEL" TO "TNM_CLK0" "TS_clk_div_slow_0_clk_div_slow_0_DDR2_CLK_i" * 4;> [system.ucf(264)]</arg>: This constraint will be ignored because the relative clock constraint named '<arg fmt="%s" index="2">TS_clk_div_slow_0_clk_div_slow_0_DDR2_CLK_i</arg>' was not found. +</msg> + +<msg type="info" file="ConstraintSystem" num="178" delta="old" ><arg fmt="%s" index="1">TNM</arg> '<arg fmt="%s" index="2">sys_clk_pin</arg>', used in period specification '<arg fmt="%s" index="3">TS_sys_clk_pin</arg>', was traced into <arg fmt="%s" index="4">PLL_ADV</arg> instance <arg fmt="%s" index="5">clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst</arg>. The following new TNM groups and period specifications were generated at the <arg fmt="%s" index="6">PLL_ADV</arg> output(s): +<arg fmt="%s" index="7">CLKOUT0</arg>: <arg fmt="%s" index="8"><TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_0_ = PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_0_" TS_sys_clk_pin * 1.25 PHASE 2 ns HIGH 50%></arg> +</msg> + +<msg type="info" file="ConstraintSystem" num="178" delta="old" ><arg fmt="%s" index="1">TNM</arg> '<arg fmt="%s" index="2">sys_clk_pin</arg>', used in period specification '<arg fmt="%s" index="3">TS_sys_clk_pin</arg>', was traced into <arg fmt="%s" index="4">PLL_ADV</arg> instance <arg fmt="%s" index="5">clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst</arg>. The following new TNM groups and period specifications were generated at the <arg fmt="%s" index="6">PLL_ADV</arg> output(s): +<arg fmt="%s" index="7">CLKOUT1</arg>: <arg fmt="%s" index="8"><TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_1_ = PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_1_" TS_sys_clk_pin * 1.25 HIGH 50%></arg> +</msg> + +<msg type="info" file="ConstraintSystem" num="178" delta="old" ><arg fmt="%s" index="1">TNM</arg> '<arg fmt="%s" index="2">sys_clk_pin</arg>', used in period specification '<arg fmt="%s" index="3">TS_sys_clk_pin</arg>', was traced into <arg fmt="%s" index="4">PLL_ADV</arg> instance <arg fmt="%s" index="5">clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst</arg>. The following new TNM groups and period specifications were generated at the <arg fmt="%s" index="6">PLL_ADV</arg> output(s): +<arg fmt="%s" index="7">CLKOUT2</arg>: <arg fmt="%s" index="8"><TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_2_ = PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_2_" TS_sys_clk_pin * 1.25 HIGH 50%></arg> +</msg> + +<msg type="info" file="ConstraintSystem" num="178" delta="old" ><arg fmt="%s" index="1">TNM</arg> '<arg fmt="%s" index="2">sys_clk_pin</arg>', used in period specification '<arg fmt="%s" index="3">TS_sys_clk_pin</arg>', was traced into <arg fmt="%s" index="4">PLL_ADV</arg> instance <arg fmt="%s" index="5">clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst</arg>. The following new TNM groups and period specifications were generated at the <arg fmt="%s" index="6">PLL_ADV</arg> output(s): +<arg fmt="%s" index="7">CLKOUT3</arg>: <arg fmt="%s" index="8"><TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_3_ = PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_3_" TS_sys_clk_pin * 2 HIGH 50%></arg> +</msg> + +<msg type="info" file="ConstraintSystem" num="178" delta="old" ><arg fmt="%s" index="1">TNM</arg> '<arg fmt="%s" index="2">sys_clk_pin</arg>', used in period specification '<arg fmt="%s" index="3">TS_sys_clk_pin</arg>', was traced into <arg fmt="%s" index="4">PLL_ADV</arg> instance <arg fmt="%s" index="5">clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst</arg>. The following new TNM groups and period specifications were generated at the <arg fmt="%s" index="6">PLL_ADV</arg> output(s): +<arg fmt="%s" index="7">CLKOUT4</arg>: <arg fmt="%s" index="8"><TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_4_ = PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_4_" TS_sys_clk_pin * 0.625 HIGH 50%></arg> +</msg> + +<msg type="warning" file="NgdBuild" num="1212" delta="old" >User specified non-default attribute value (<arg fmt="%s" index="1">8.0000000000000000</arg>) was detected for the <arg fmt="%s" index="2">CLKIN_PERIOD</arg> attribute on <arg fmt="%s" index="3">DCM</arg> "<arg fmt="%s" index="4">clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST</arg>". This does not match the PERIOD constraint value (<arg fmt="%s" index="5">5 ns.</arg>). The uncertainty calculation will use the non-default attribute value. This could result in incorrect uncertainty calculated for <arg fmt="%s" index="6">DCM</arg> output clocks. +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">xps_bram_if_cntlr_1/xps_bram_if_cntlr_1/INCLUDE_BURST_SUPPORT.I_SLAVE_BURST_ATTACH/I_DBEAT_CONTROL/I_DBEAT_CNTR/STRUCTURAL_A_GEN.I_ADDSUB_GEN[4].FDRE_I</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">SRAM/SRAM/EMC_CTRL_I/MEM_STEER_I/SYNC_MEM_DQT.REG_DQT_GEN[2].DQT_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">SRAM/SRAM/EMC_CTRL_I/MEM_STEER_I/GSYNC_MEM_RDACK_GEN.ADDR_ALIGN_PIPE_GEN[3].ALIGN_PIPE</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_FOR_SHARED.GEN_BKEND_CE_REGISTERS[0].I_BKEND_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_FOR_SHARED.GEN_BKEND_CE_REGISTERS[0].I_BKEND_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BURST_SUPPORT/RESPONSE_DBEAT_CNTR_I/STRUCTURAL_A_GEN.I_ADDSUB_GEN[7].FDRE_I</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BURST_SUPPORT/CONTROL_DBEAT_CNTR_I/STRUCTURAL_A_GEN.I_ADDSUB_GEN[7].FDRE_I</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[0].I_FDRSE_BE0to3</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[1].I_FDRSE_BE0to3</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[2].I_FDRSE_BE0to3</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[3].I_FDRSE_BE0to3</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="486" delta="new" >Attribute "<arg fmt="%s" index="1">CLK_FEEDBACK</arg>" is not allowed on symbol "<arg fmt="%s" index="2">PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.pll_adv_i</arg>" of type "<arg fmt="%s" index="3">PLL_ADV</arg>". This attribute will be ignored. +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_STEER_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BUS_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE_4to7[7].I_FDRSE_BE4to7</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE_4to7[6].I_FDRSE_BE4to7</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE_4to7[5].I_FDRSE_BE4to7</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE_4to7[4].I_FDRSE_BE4to7</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[3].I_FDRSE_BE0to3</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[2].I_FDRSE_BE0to3</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[1].I_FDRSE_BE0to3</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[0].I_FDRSE_BE0to3</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_S_H_ADDR_REG[6].I_ADDR_S_H_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_S_H_ADDR_REG[7].I_ADDR_S_H_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[32].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[33].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[34].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[35].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[36].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[37].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[38].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[39].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[40].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[41].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[42].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[43].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[44].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[44].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[44].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[45].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[45].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[45].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[46].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[46].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[46].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[47].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[47].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[47].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[48].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[48].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[48].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[49].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[49].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[49].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[53].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[53].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[53].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[54].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[54].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[54].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[55].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[55].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[55].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[56].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[57].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[58].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[59].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[60].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[61].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[61].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[61].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[62].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[62].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[62].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[63].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[63].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[63].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[1].GEN_USER_CE.GEN_ALL_CEs[64].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[1].GEN_USER_CE.GEN_ALL_CEs[64].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[1].GEN_USER_CE.GEN_ALL_CEs[64].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[65].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[66].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[66].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[67].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[68].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[68].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[68].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[69].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[69].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[69].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[70].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[70].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[70].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[71].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[71].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[72].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[73].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[74].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[74].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[74].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[75].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[76].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[76].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[76].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[77].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[77].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[77].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[78].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[78].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[78].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[79].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[79].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[79].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[80].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[80].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[80].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[3].GEN_RESET_CE.I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[3].GEN_RESET_CE.I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[4].GEN_USER_CE.GEN_ALL_CEs[82].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[4].GEN_USER_CE.GEN_ALL_CEs[82].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[4].GEN_USER_CE.GEN_ALL_CEs[82].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[5].GEN_USER_CE.GEN_ALL_CEs[83].I_BKend_CE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[5].GEN_USER_CE.GEN_ALL_CEs[83].I_BKend_RDCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_CE_ASSIGNMENTS[5].GEN_USER_CE.GEN_ALL_CEs[83].I_BKend_WRCE_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_SIZE2_REG0</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_SIZE2_REG1</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_SIZE2_REG2</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_plbv46_master/I_RD_CONTROL/I_RD_ABORT_REG</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="443" delta="old" >SFF primitive '<arg fmt="%s" index="1">Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/COLLISION_SYNC</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="440" delta="old" >FF primitive '<arg fmt="%s" index="1">Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU10</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="440" delta="old" >FF primitive '<arg fmt="%s" index="1">Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU15</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="440" delta="old" >FF primitive '<arg fmt="%s" index="1">Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU20</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="440" delta="old" >FF primitive '<arg fmt="%s" index="1">Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU25</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="440" delta="old" >FF primitive '<arg fmt="%s" index="1">Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU30</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="440" delta="old" >FF primitive '<arg fmt="%s" index="1">Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU35</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="440" delta="old" >FF primitive '<arg fmt="%s" index="1">Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU130</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="440" delta="old" >FF primitive '<arg fmt="%s" index="1">Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU237</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="440" delta="old" >FF primitive '<arg fmt="%s" index="1">Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU10</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="440" delta="old" >FF primitive '<arg fmt="%s" index="1">Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU15</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="440" delta="old" >FF primitive '<arg fmt="%s" index="1">Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU20</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="440" delta="old" >FF primitive '<arg fmt="%s" index="1">Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU25</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="440" delta="old" >FF primitive '<arg fmt="%s" index="1">Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU30</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="440" delta="old" >FF primitive '<arg fmt="%s" index="1">Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU35</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="440" delta="old" >FF primitive '<arg fmt="%s" index="1">Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU130</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="440" delta="old" >FF primitive '<arg fmt="%s" index="1">Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU237</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="440" delta="old" >FF primitive '<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[1].u_calib_rden_r</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="440" delta="old" >FF primitive '<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[2].u_calib_rden_r</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="440" delta="old" >FF primitive '<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[3].u_calib_rden_r</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="440" delta="old" >FF primitive '<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[4].u_calib_rden_r</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="440" delta="old" >FF primitive '<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[5].u_calib_rden_r</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="440" delta="old" >FF primitive '<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[6].u_calib_rden_r</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="440" delta="old" >FF primitive '<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[7].u_calib_rden_r</arg>' has unconnected output pin +</msg> + +<msg type="warning" file="NgdBuild" num="486" delta="old" >Attribute "<arg fmt="%s" index="1">CLK_FEEDBACK</arg>" is not allowed on symbol "<arg fmt="%s" index="2">clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst</arg>" of type "<arg fmt="%s" index="3">PLL_ADV</arg>". This attribute will be ignored. +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N194</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N195</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N196</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N197</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N198</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N199</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N200</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N201</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N202</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N203</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N204</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N205</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N206</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N207</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N208</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N209</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N210</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N211</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N212</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N213</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N214</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N215</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N216</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N217</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N218</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N219</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N220</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N221</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N222</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N223</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N224</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N225</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N226</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N227</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N228</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N229</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N230</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N231</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N232</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N233</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N234</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N235</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N236</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N237</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N238</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N239</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N240</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N241</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N242</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N243</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N244</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N245</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N246</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N247</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N248</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N249</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N250</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N251</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N252</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N253</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N254</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N255</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N256</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N257</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N266</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N267</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N268</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N269</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N270</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N271</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N272</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N273</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N306</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N307</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N308</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N309</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N310</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N311</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N312</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">N313</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">PCIe_Bridge/PCIe_Bridge/sig_trn_terrfwd_n</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">PCIe_Bridge/PCIe_Bridge/sig_trn_rerrfwd_n</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">PCIe_Bridge/PCIe_Bridge/sig_trn_tsrc_dsc_n</arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">PCIe_Bridge/PCIe_Bridge/sig_trn_tbuf_av<3></arg>' has no driver +</msg> + +<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net '<arg fmt="%s" index="2">PCIe_Bridge/PCIe_Bridge/sig_trn_trem_n<4></arg>' has no driver +</msg> + +</messages> + diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/_xmsgs/par.xmsgs b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/_xmsgs/par.xmsgs new file mode 100644 index 000000000..a598a1796 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/_xmsgs/par.xmsgs @@ -0,0 +1,52 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- IMPORTANT: This is an internal file that has been generated + by the Xilinx ISE software. Any direct editing or + changes made to this file may result in unpredictable + behavior or data corruption. It is strongly advised that + users do not edit the contents of this file. --> +<messages> +<msg type="warning" file="ConstraintSystem" num="65" delta="new" >Constraint <arg fmt="%s" index="1"><NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(65973)]</arg> overrides constraint <arg fmt="%s" index="2"><NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(65972)]</arg>. +</msg> + +<msg type="warning" file="Timing" num="3223" delta="old" >Timing constraint <arg fmt="%s" index="1">TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP "TNM_CLK0" TS_MC_CLK * 4;</arg> ignored during timing analysis.</msg> + +<msg type="info" file="Timing" num="3386" delta="old" >Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</msg> + +<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/sig_sb_txrem_n<0></arg> has no load. PAR will not attempt to route this signal. +</msg> + +<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/sig_MB_TxREMn<0></arg> has no load. PAR will not attempt to route this signal. +</msg> + +<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">xps_bram_if_cntlr_1_port_BRAM_Addr<30></arg> has no load. PAR will not attempt to route this signal. +</msg> + +<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">xps_bram_if_cntlr_1_port_BRAM_Addr<31></arg> has no load. PAR will not attempt to route this signal. +</msg> + +<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/sig_MB_RxFull</arg> has no load. PAR will not attempt to route this signal. +</msg> + +<msg type="info" file="Route" num="501" delta="old" >One or more directed routing (DIRT) constraints generated for a specific device have been found. Note that DIRT strings are guaranteed to work only on the same device they were created for. If the DIRT constraints fail, verify that the same connectivity is available in the target device for this implementation. +</msg> + +<msg type="info" file="Timing" num="2761" delta="old" >N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value.</msg> + +<msg type="info" file="Timing" num="2761" delta="old" >N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value.</msg> + +<msg type="warning" file="ParHelpers" num="361" delta="old" >There are <arg fmt="%d" index="1">5</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings. + +</msg> + +<msg type="warning" file="Par" num="283" delta="old" >There are <arg fmt="%d" index="1">5</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings. + +</msg> + +<msg type="info" file="ParHelpers" num="197" delta="old" >Number of "Exact" mode Directed Routing Constraints: <arg fmt="%d" index="1">128</arg> +</msg> + +<msg type="info" file="ParHelpers" num="199" delta="old" >All "EXACT" mode Directed Routing constrained nets successfully routed. The number of constraints found: <arg fmt="%d" index="1">128</arg>, number successful: <arg fmt="%d" index="2">128</arg> +</msg> + +</messages> + diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/_xmsgs/trce.xmsgs b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/_xmsgs/trce.xmsgs new file mode 100644 index 000000000..5b58063e9 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/_xmsgs/trce.xmsgs @@ -0,0 +1,20 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- IMPORTANT: This is an internal file that has been generated + by the Xilinx ISE software. Any direct editing or + changes made to this file may result in unpredictable + behavior or data corruption. It is strongly advised that + users do not edit the contents of this file. --> +<messages> +<msg type="warning" file="ConstraintSystem" num="65" delta="new" >Constraint <arg fmt="%s" index="1"><NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(65973)]</arg> overrides constraint <arg fmt="%s" index="2"><NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(65972)]</arg>. +</msg> + +<msg type="warning" file="Timing" num="3223" delta="old" >Timing constraint <arg fmt="%s" index="1">TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP "TNM_CLK0" TS_MC_CLK * 4;</arg> ignored during timing analysis.</msg> + +<msg type="info" file="Timing" num="3386" delta="old" >Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</msg> + +<msg type="info" file="Timing" num="2752" delta="old" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg> + +<msg type="info" file="Timing" num="3339" delta="old" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg> + +</messages> + diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/_xmsgs/xst.xmsgs b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/_xmsgs/xst.xmsgs new file mode 100644 index 000000000..bea4a975e --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/_xmsgs/xst.xmsgs @@ -0,0 +1,1041 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- IMPORTANT: This is an internal file that has been generated + by the Xilinx ISE software. Any direct editing or + changes made to this file may result in unpredictable + behavior or data corruption. It is strongly advised that + users do not edit the contents of this file. --> +<messages> +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3111</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3119</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3127</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3135</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3143</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3151</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3159</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3167</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3175</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3183</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3191</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3199</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3207</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3215</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3223</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3231</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3239</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3247</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3255</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3263</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3271</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3279</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3287</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3295</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3303</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3311</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3319</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3327</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3335</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3343</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3351</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3359</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3367</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3375</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3383</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3391</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3399</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3407</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3415</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3423</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3431</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3439</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3447</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3455</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3463</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3471</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3479</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3487</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3495</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3503</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3511</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3519</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3527</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3535</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3543</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg 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num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3583</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3591</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3599</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg 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num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3639</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3647</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3655</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3663</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3671</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3679</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3687</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3695</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3703</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3711</arg>: Instantiating black box module <<arg fmt="%s" index="3">IOBUF</arg>>. +</msg> + +<msg type="warning" file="Xst" num="2211" delta="new" >"<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>" line <arg fmt="%d" index="2">3719</arg>: Instantiating black box module <<arg fmt="%s" index="3">IBUFGDS</arg>>. +</msg> + +<msg type="warning" file="Xst" num="646" delta="old" >Signal <<arg fmt="%s" index="1">pgassign9</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. +</msg> + +<msg type="warning" file="Xst" num="646" delta="old" >Signal <<arg fmt="%s" index="1">pgassign11<0:6></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. +</msg> + +<msg type="warning" file="Xst" num="646" delta="old" >Signal <<arg fmt="%s" index="1">pgassign11<31></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. +</msg> + +<msg type="warning" file="Xst" num="646" delta="old" >Signal <<arg fmt="%s" index="1">pgassign10<0></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">plb_v46_0/GEN_MPLB_RST[0].I_MPLB_RST</arg>> in Unit <<arg fmt="%s" index="2">plb_v46_0</arg>> is equivalent to the following <arg fmt="%s" index="3">13 FFs/Latches</arg> : <arg fmt="%s" index="4"><plb_v46_0/GEN_SPLB_RST[11].I_SPLB_RST> <plb_v46_0/GEN_SPLB_RST[10].I_SPLB_RST> <plb_v46_0/GEN_SPLB_RST[9].I_SPLB_RST> <plb_v46_0/GEN_SPLB_RST[8].I_SPLB_RST> <plb_v46_0/GEN_SPLB_RST[7].I_SPLB_RST> <plb_v46_0/GEN_SPLB_RST[6].I_SPLB_RST> <plb_v46_0/GEN_SPLB_RST[5].I_SPLB_RST> <plb_v46_0/GEN_SPLB_RST[4].I_SPLB_RST> <plb_v46_0/GEN_SPLB_RST[3].I_SPLB_RST> <plb_v46_0/GEN_SPLB_RST[2].I_SPLB_RST> <plb_v46_0/GEN_SPLB_RST[1].I_SPLB_RST> <plb_v46_0/GEN_SPLB_RST[0].I_SPLB_RST> <plb_v46_0/I_PLB_RST> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">xps_bram_if_cntlr_1/INCLUDE_BURST_SUPPORT.I_SLAVE_BURST_ATTACH/I_FLOP_ADDRACK</arg>> in Unit <<arg fmt="%s" index="2">xps_bram_if_cntlr_1</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><xps_bram_if_cntlr_1/INCLUDE_BURST_SUPPORT.I_SLAVE_BURST_ATTACH/I_FLOP_SET_SLBUSY> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">xps_bram_if_cntlr_1/INCLUDE_BURST_SUPPORT.I_SLAVE_BURST_ATTACH/I_FLOP_WRACK_2BUS</arg>> in Unit <<arg fmt="%s" index="2">xps_bram_if_cntlr_1</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><xps_bram_if_cntlr_1/INCLUDE_BURST_SUPPORT.I_SLAVE_BURST_ATTACH/I_FLOP_WRACK> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.I_BURST_S_H_REG</arg>> in Unit <<arg fmt="%s" index="2">SRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.I_BURST_S_H_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/sl_wrdack_i</arg>> in Unit <<arg fmt="%s" index="2">SRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/GEN_WRITE_BUFFER.GEN_WRBUF_WREN1> <SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/GEN_WRITE_BUFFER.GEN_WRBUF_WREN2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.I_SNGL_S_H_REG</arg>> in Unit <<arg fmt="%s" index="2">SRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.I_SNGL_S_H_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[1].I_SIZE_S_H_REG</arg>> in Unit <<arg fmt="%s" index="2">SRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[1].I_SIZE_S_H_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[2].I_SIZE_S_H_REG</arg>> in Unit <<arg fmt="%s" index="2">SRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[2].I_SIZE_S_H_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[3].I_SIZE_S_H_REG</arg>> in Unit <<arg fmt="%s" index="2">SRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[3].I_SIZE_S_H_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">SRAM/EMC_CTRL_I/IO_REGISTERS_I/mem_wen_reg</arg>> in Unit <<arg fmt="%s" index="2">SRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><SRAM/EMC_CTRL_I/MEM_STEER_I/SYNC_MEM_DQT.REG_DQT_GEN[0].DQT_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.I_CACHLN_S_H_REG</arg>> in Unit <<arg fmt="%s" index="2">SRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.I_CACHLN_S_H_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_STEER_ADDRESS_COUNTER/I_SNGL_S_H_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BUS_ADDRESS_COUNTER/I_SNGL_S_H_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_SIZE_REG1</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_SIZE_REG2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/flop[0].tx_power_down0</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/flop[0].rx_power_down0> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[29].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[29].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[28].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[28].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_STEER_ADDRESS_COUNTER/I_BURST_S_H_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BUS_ADDRESS_COUNTER/I_BURST_S_H_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[27].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[27].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[31].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[31].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[26].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[26].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_STEER_ADDRESS_COUNTER/I_CACHLN_S_H_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BUS_ADDRESS_COUNTER/I_CACHLN_S_H_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[30].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[30].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[25].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[25].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[19].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[19].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[24].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[24].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[23].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[23].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[18].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[18].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.GEN_FOR_64.DPHASE_REG2</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.GEN_FOR_64.DPHASE_REG1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[22].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[22].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[17].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[17].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[21].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[21].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[16].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[16].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[20].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[20].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[15].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[15].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[14].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[14].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[13].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[13].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[12].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[12].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[11].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[11].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[10].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[10].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[9].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[9].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/flop[0].tx_power_down1</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/flop[0].rx_power_down1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[8].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[8].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[7].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[7].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[6].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[6].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[5].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[5].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_STEER_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[3].I_SIZE_S_H_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BUS_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[3].I_SIZE_S_H_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[4].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[4].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_STEER_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[2].I_SIZE_S_H_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BUS_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[2].I_SIZE_S_H_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[3].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[3].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_STEER_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[1].I_SIZE_S_H_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BUS_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[1].I_SIZE_S_H_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[2].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[2].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[1].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[1].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[0].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[0].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BURST_SUPPORT/BTERM_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BURST_SUPPORT/BTERM_CLNUP> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.GEN_WRITE_BUFFER.GEN_WRBUF_WREN2</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.GEN_WRITE_BUFFER.GEN_WRBUF_WREN1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="new" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/plb_size_reg_3</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/plb_size_reg_3_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="new" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/plb_size_reg_2</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/plb_size_reg_2_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">U0/grf.rf/gl0.rd/grss.rsts/ram_empty_fb_i</arg>> in Unit <<arg fmt="%s" index="2">BU3</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><U0/grf.rf/gl0.rd/grss.rsts/ram_empty_i> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i</arg>> in Unit <<arg fmt="%s" index="2">BU3</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><U0/grf.rf/gl0.wr/gwss.wsts/ram_full_i> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">U0/grf.rf/gl0.rd/grss.rsts/ram_empty_fb_i</arg>> in Unit <<arg fmt="%s" index="2">BU3</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><U0/grf.rf/gl0.rd/grss.rsts/ram_empty_i> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i</arg>> in Unit <<arg fmt="%s" index="2">BU3</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><U0/grf.rf/gl0.wr/gwss.wsts/ram_full_i> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">U0/grf.rf/gl0.rd/gr1.rfwft/aempty_fwft_i</arg>> in Unit <<arg fmt="%s" index="2">BU2</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><U0/grf.rf/gl0.rd/gr1.rfwft/aempty_fwft_fb> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i</arg>> in Unit <<arg fmt="%s" index="2">BU2</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">U0/grf.rf/rstblk/wr_rst_reg_1</arg>> in Unit <<arg fmt="%s" index="2">BU2</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><U0/grf.rf/rstblk/wr_rst_reg_0> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i</arg>> in Unit <<arg fmt="%s" index="2">BU2</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">U0/grf.rf/rstblk/rd_rst_reg_2</arg>> in Unit <<arg fmt="%s" index="2">BU2</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><U0/grf.rf/rstblk/rd_rst_reg_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">ppc440_0_SPLB0/GEN_MPLB_RST[0].I_MPLB_RST</arg>> in Unit <<arg fmt="%s" index="2">ppc440_0_SPLB0</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><ppc440_0_SPLB0/GEN_SPLB_RST[0].I_SPLB_RST> <ppc440_0_SPLB0/I_PLB_RST> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_state_machine/state21a</arg>> in Unit <<arg fmt="%s" index="2">Ethernet_MAC</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_state_machine/state19a> <Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_state/state21a> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/clk_reset/rst0_sync_r_2</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/clk_reset/rst0_sync_r_2_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/clk_reset/rst90_sync_r_2</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">6 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/clk_reset/rst90_sync_r_2_1> <DDR2_SDRAM/u_ddr2_top/clk_reset/rst90_sync_r_2_2> <DDR2_SDRAM/u_ddr2_top/clk_reset/rst90_sync_r_2_3> <DDR2_SDRAM/u_ddr2_top/clk_reset/rst90_sync_r_2_4> <DDR2_SDRAM/u_ddr2_top/clk_reset/rst90_sync_r_2_5> <DDR2_SDRAM/u_ddr2_top/clk_reset/rst90_sync_r_2_6> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal2_rd_data_sel_r_0</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[0].u_ff_rd_data_sel> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal2_rd_data_sel_r_1</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[1].u_ff_rd_data_sel> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal2_rd_data_sel_r_2</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[2].u_ff_rd_data_sel> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal2_rd_data_sel_r_3</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[3].u_ff_rd_data_sel> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_usr_top/usr_rd/gen_rden_sel_mux[0].u_ff_rden_sel_mux</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_usr_top/usr_rd/rden_sel_r_0> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal2_rd_data_sel_r_4</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[4].u_ff_rd_data_sel> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_26</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_26_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_26_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_31</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_31_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_31_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal2_rd_data_sel_r_5</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[5].u_ff_rd_data_sel> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal2_rd_data_sel_r_6</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[6].u_ff_rd_data_sel> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal2_rd_data_sel_r_7</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[7].u_ff_rd_data_sel> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_6</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_6_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_11</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_11_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_18</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_18_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_18_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_23</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_23_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_23_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_5</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_5_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_10</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_10_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_35</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_35_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_35_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_40</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_40_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_40_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_39</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_39_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_39_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_44</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_44_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_44_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_25</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_25_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_25_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_30</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_30_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_30_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_1</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_1_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_hit_r_1</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_hit_r_1_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_13</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_13_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_17</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_17_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_17_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_22</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_22_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_22_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">40 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_1> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_2> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_3> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_4> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_5> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_6> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_7> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_8> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_9> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_10> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_11> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_12> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_13> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_14> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_15> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_16> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_17> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_18> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_19> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_20> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_21> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_22> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_23> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_24> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_25> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_26> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_27> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_28> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_29> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_30> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_31> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_32> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_33> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_34> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_35> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_36> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_37> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_38> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_39> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_40> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_0</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_0_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_12</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_12_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_29</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_29_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_29_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_34</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_34_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_34_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_38</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_38_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_38_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_43</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_43_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_43_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_59</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_59_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_16</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_16_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_16_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_21</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_21_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_21_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_2</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_2_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_7</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_7_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_28</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_28_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_28_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_33</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_33_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_33_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_14</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_14_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/dqs_rst_n_r</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">7 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/dqs_rst_n_r> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/dqs_rst_n_r> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[3].u_iob_dqs/dqs_rst_n_r> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/dqs_rst_n_r> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/dqs_rst_n_r> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/dqs_rst_n_r> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/dqs_rst_n_r> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_37</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_37_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_37_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_42</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_42_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_42_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_58</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_58_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_hit_r_2</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_hit_r_2_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_15</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_15_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_15_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_20</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_20_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_20_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_27</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_27_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_27_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_32</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_32_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_32_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_4</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_4_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_9</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_9_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_19</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_19_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_19_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_24</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_24_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_24_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dm[0].u_iob_dm/u_dm_ce</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">7 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dm[1].u_iob_dm/u_dm_ce> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dm[2].u_iob_dm/u_dm_ce> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dm[3].u_iob_dm/u_dm_ce> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dm[4].u_iob_dm/u_dm_ce> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dm[5].u_iob_dm/u_dm_ce> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dm[6].u_iob_dm/u_dm_ce> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dm[7].u_iob_dm/u_dm_ce> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_3</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_3_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_8</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_8_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_36</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_36_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_36_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_41</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_41_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_41_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">plb_v46_0/GEN_MPLB_RST[0].I_MPLB_RST</arg>> in Unit <<arg fmt="%s" index="2">plb_v46_0</arg>> is equivalent to the following <arg fmt="%s" index="3">13 FFs/Latches</arg> : <arg fmt="%s" index="4"><plb_v46_0/GEN_SPLB_RST[11].I_SPLB_RST> <plb_v46_0/GEN_SPLB_RST[10].I_SPLB_RST> <plb_v46_0/GEN_SPLB_RST[9].I_SPLB_RST> <plb_v46_0/GEN_SPLB_RST[8].I_SPLB_RST> <plb_v46_0/GEN_SPLB_RST[7].I_SPLB_RST> <plb_v46_0/GEN_SPLB_RST[6].I_SPLB_RST> <plb_v46_0/GEN_SPLB_RST[5].I_SPLB_RST> <plb_v46_0/GEN_SPLB_RST[4].I_SPLB_RST> <plb_v46_0/GEN_SPLB_RST[3].I_SPLB_RST> <plb_v46_0/GEN_SPLB_RST[2].I_SPLB_RST> <plb_v46_0/GEN_SPLB_RST[1].I_SPLB_RST> <plb_v46_0/GEN_SPLB_RST[0].I_SPLB_RST> <plb_v46_0/I_PLB_RST> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">xps_bram_if_cntlr_1/INCLUDE_BURST_SUPPORT.I_SLAVE_BURST_ATTACH/I_FLOP_ADDRACK</arg>> in Unit <<arg fmt="%s" index="2">xps_bram_if_cntlr_1</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><xps_bram_if_cntlr_1/INCLUDE_BURST_SUPPORT.I_SLAVE_BURST_ATTACH/I_FLOP_SET_SLBUSY> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">xps_bram_if_cntlr_1/INCLUDE_BURST_SUPPORT.I_SLAVE_BURST_ATTACH/I_FLOP_WRACK_2BUS</arg>> in Unit <<arg fmt="%s" index="2">xps_bram_if_cntlr_1</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><xps_bram_if_cntlr_1/INCLUDE_BURST_SUPPORT.I_SLAVE_BURST_ATTACH/I_FLOP_WRACK> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.I_BURST_S_H_REG</arg>> in Unit <<arg fmt="%s" index="2">SRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.I_BURST_S_H_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/sl_wrdack_i</arg>> in Unit <<arg fmt="%s" index="2">SRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/GEN_WRITE_BUFFER.GEN_WRBUF_WREN1> <SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/GEN_WRITE_BUFFER.GEN_WRBUF_WREN2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.I_SNGL_S_H_REG</arg>> in Unit <<arg fmt="%s" index="2">SRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.I_SNGL_S_H_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[1].I_SIZE_S_H_REG</arg>> in Unit <<arg fmt="%s" index="2">SRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[1].I_SIZE_S_H_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[2].I_SIZE_S_H_REG</arg>> in Unit <<arg fmt="%s" index="2">SRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[2].I_SIZE_S_H_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[3].I_SIZE_S_H_REG</arg>> in Unit <<arg fmt="%s" index="2">SRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[3].I_SIZE_S_H_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">SRAM/EMC_CTRL_I/IO_REGISTERS_I/mem_wen_reg</arg>> in Unit <<arg fmt="%s" index="2">SRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><SRAM/EMC_CTRL_I/MEM_STEER_I/SYNC_MEM_DQT.REG_DQT_GEN[0].DQT_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.I_CACHLN_S_H_REG</arg>> in Unit <<arg fmt="%s" index="2">SRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.I_CACHLN_S_H_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_STEER_ADDRESS_COUNTER/I_SNGL_S_H_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BUS_ADDRESS_COUNTER/I_SNGL_S_H_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_SIZE_REG1</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_SIZE_REG2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/flop[0].tx_power_down0</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/flop[0].rx_power_down0> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[29].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[29].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[28].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[28].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_STEER_ADDRESS_COUNTER/I_BURST_S_H_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BUS_ADDRESS_COUNTER/I_BURST_S_H_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[27].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[27].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[31].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[31].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[26].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[26].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_STEER_ADDRESS_COUNTER/I_CACHLN_S_H_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BUS_ADDRESS_COUNTER/I_CACHLN_S_H_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[30].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[30].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[25].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[25].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[19].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[19].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[24].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[24].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[23].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[23].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[18].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[18].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.GEN_FOR_64.DPHASE_REG2</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.GEN_FOR_64.DPHASE_REG1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[22].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[22].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[17].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[17].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[21].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[21].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[16].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[16].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[20].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[20].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[15].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[15].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[14].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[14].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[13].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[13].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[12].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[12].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[11].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[11].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[10].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[10].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[9].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[9].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/flop[0].tx_power_down1</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/flop[0].rx_power_down1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[8].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[8].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[7].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[7].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[6].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[6].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[5].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[5].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_STEER_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[3].I_SIZE_S_H_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BUS_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[3].I_SIZE_S_H_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[4].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[4].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_STEER_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[2].I_SIZE_S_H_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BUS_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[2].I_SIZE_S_H_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[3].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[3].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_STEER_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[1].I_SIZE_S_H_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BUS_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[1].I_SIZE_S_H_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[2].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[2].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[1].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[1].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[0].I_ADDR_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[0].I_ADDR_REG> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BURST_SUPPORT/BTERM_REG</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BURST_SUPPORT/BTERM_CLNUP> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.GEN_WRITE_BUFFER.GEN_WRBUF_WREN2</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.GEN_WRITE_BUFFER.GEN_WRBUF_WREN1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="new" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/plb_size_reg_3</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/plb_size_reg_3_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="new" >The FF/Latch <<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/plb_size_reg_2</arg>> in Unit <<arg fmt="%s" index="2">PCIe_Bridge</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/plb_size_reg_2_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">U0/grf.rf/gl0.rd/grss.rsts/ram_empty_fb_i</arg>> in Unit <<arg fmt="%s" index="2">BU3</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><U0/grf.rf/gl0.rd/grss.rsts/ram_empty_i> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i</arg>> in Unit <<arg fmt="%s" index="2">BU3</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><U0/grf.rf/gl0.wr/gwss.wsts/ram_full_i> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">U0/grf.rf/gl0.rd/grss.rsts/ram_empty_fb_i</arg>> in Unit <<arg fmt="%s" index="2">BU3</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><U0/grf.rf/gl0.rd/grss.rsts/ram_empty_i> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i</arg>> in Unit <<arg fmt="%s" index="2">BU3</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><U0/grf.rf/gl0.wr/gwss.wsts/ram_full_i> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">U0/grf.rf/gl0.rd/gr1.rfwft/aempty_fwft_i</arg>> in Unit <<arg fmt="%s" index="2">BU2</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><U0/grf.rf/gl0.rd/gr1.rfwft/aempty_fwft_fb> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i</arg>> in Unit <<arg fmt="%s" index="2">BU2</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">U0/grf.rf/rstblk/wr_rst_reg_1</arg>> in Unit <<arg fmt="%s" index="2">BU2</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><U0/grf.rf/rstblk/wr_rst_reg_0> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i</arg>> in Unit <<arg fmt="%s" index="2">BU2</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">U0/grf.rf/rstblk/rd_rst_reg_2</arg>> in Unit <<arg fmt="%s" index="2">BU2</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><U0/grf.rf/rstblk/rd_rst_reg_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">ppc440_0_SPLB0/GEN_MPLB_RST[0].I_MPLB_RST</arg>> in Unit <<arg fmt="%s" index="2">ppc440_0_SPLB0</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><ppc440_0_SPLB0/GEN_SPLB_RST[0].I_SPLB_RST> <ppc440_0_SPLB0/I_PLB_RST> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_state_machine/state21a</arg>> in Unit <<arg fmt="%s" index="2">Ethernet_MAC</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_state_machine/state19a> <Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_state/state21a> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/clk_reset/rst0_sync_r_2</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/clk_reset/rst0_sync_r_2_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/clk_reset/rst90_sync_r_2</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">6 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/clk_reset/rst90_sync_r_2_1> <DDR2_SDRAM/u_ddr2_top/clk_reset/rst90_sync_r_2_2> <DDR2_SDRAM/u_ddr2_top/clk_reset/rst90_sync_r_2_3> <DDR2_SDRAM/u_ddr2_top/clk_reset/rst90_sync_r_2_4> <DDR2_SDRAM/u_ddr2_top/clk_reset/rst90_sync_r_2_5> <DDR2_SDRAM/u_ddr2_top/clk_reset/rst90_sync_r_2_6> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal2_rd_data_sel_r_0</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[0].u_ff_rd_data_sel> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal2_rd_data_sel_r_1</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[1].u_ff_rd_data_sel> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal2_rd_data_sel_r_2</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[2].u_ff_rd_data_sel> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal2_rd_data_sel_r_3</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[3].u_ff_rd_data_sel> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_usr_top/usr_rd/gen_rden_sel_mux[0].u_ff_rden_sel_mux</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_usr_top/usr_rd/rden_sel_r_0> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal2_rd_data_sel_r_4</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[4].u_ff_rd_data_sel> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_26</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_26_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_26_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_31</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_31_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_31_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal2_rd_data_sel_r_5</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[5].u_ff_rd_data_sel> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal2_rd_data_sel_r_6</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[6].u_ff_rd_data_sel> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal2_rd_data_sel_r_7</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[7].u_ff_rd_data_sel> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_11</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_11_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_6</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_6_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_23</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_23_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_23_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_18</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_18_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_18_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_10</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_10_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_5</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_5_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_40</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_40_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_40_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_35</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_35_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_35_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_44</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_44_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_44_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_39</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_39_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_39_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_30</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_30_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_30_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_25</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_25_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_25_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_1</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_1_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_hit_r_1</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_hit_r_1_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_13</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_13_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_22</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_22_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_22_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_17</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_17_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_17_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">40 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_1> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_2> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_3> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_4> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_5> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_6> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_7> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_8> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_9> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_10> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_11> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_12> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_13> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_14> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_15> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_16> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_17> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_18> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_19> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_20> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_21> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_22> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_23> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_24> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_25> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_26> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_27> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_28> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_29> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_30> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_31> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_32> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_33> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_34> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_35> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_36> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_37> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_38> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_39> <DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_40> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_0</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_0_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_12</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_12_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_34</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_34_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_34_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_29</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_29_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_29_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_43</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_43_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_43_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_38</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_38_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_38_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_59</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_59_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_21</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_21_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_21_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_16</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_16_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_16_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_7</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_7_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_2</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_2_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_33</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_33_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_33_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_28</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_28_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_28_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_14</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_14_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/dqs_rst_n_r</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">7 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/dqs_rst_n_r> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/dqs_rst_n_r> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[3].u_iob_dqs/dqs_rst_n_r> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/dqs_rst_n_r> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/dqs_rst_n_r> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/dqs_rst_n_r> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/dqs_rst_n_r> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_42</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_42_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_42_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_37</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_37_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_37_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_58</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_58_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_hit_r_2</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_hit_r_2_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_15</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_15_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_15_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_20</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_20_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_20_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_32</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_32_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_32_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_27</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_27_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_27_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_9</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_9_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_4</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_4_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_24</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_24_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_24_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_19</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_19_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_19_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dm[0].u_iob_dm/u_dm_ce</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">7 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dm[1].u_iob_dm/u_dm_ce> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dm[2].u_iob_dm/u_dm_ce> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dm[3].u_iob_dm/u_dm_ce> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dm[4].u_iob_dm/u_dm_ce> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dm[5].u_iob_dm/u_dm_ce> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dm[6].u_iob_dm/u_dm_ce> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dm[7].u_iob_dm/u_dm_ce> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_8</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_8_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_3</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_3_1> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_41</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_41_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_41_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_36</arg>> in Unit <<arg fmt="%s" index="2">DDR2_SDRAM</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4"><DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_36_1> <DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_36_2> </arg> +</msg> + +<msg type="info" file="Xst" num="2169" delta="old" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. +</msg> + +</messages> + diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system.gise b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system.gise new file mode 100644 index 000000000..fb514ece4 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system.gise @@ -0,0 +1,26 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <!-- -->
+
+ <!-- For tool use only. Do not edit. -->
+
+ <!-- -->
+
+ <!-- ProjectNavigator created generated project file. -->
+
+ <!-- For use in tracking generated file and other information -->
+
+ <!-- allowing preservation of process status. -->
+
+ <!-- -->
+
+ <!-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. -->
+
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+ <files xmlns="http://www.xilinx.com/XMLSchema"/>
+
+ <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system.ise b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system.ise Binary files differnew file mode 100644 index 000000000..55ee07046 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system.ise diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system.ntrc_log b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system.ntrc_log new file mode 100644 index 000000000..0a8503fa5 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system.ntrc_log @@ -0,0 +1,8 @@ +--------------------
+Xst NTRC: "/" : OUT_OF_DATE
+--------------------
+Map NTRC: "/" : OUT_OF_DATE
+--------------------
+Xst NTRC: "/" : OUT_OF_DATE
+--------------------
+Map NTRC: "/" : OUT_OF_DATE
diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system.xise b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system.xise new file mode 100644 index 000000000..510ac7ebf --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system.xise @@ -0,0 +1,42 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> + + <header> + <!-- ISE source project file created by Project Navigator. --> + <!-- --> + <!-- This file contains project source information including a list of --> + <!-- project source files, project and process properties. This file, --> + <!-- along with the project source files, is sufficient to open and --> + <!-- implement in ISE Project Navigator. --> + <!-- --> + <!-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. --> + </header> + + <version xil_pn:ise_version="11.1" xil_pn:schema_version="2"/> + + <files/> + + <properties> + <property xil_pn:name="Device" xil_pn:value="xa2c*"/> + <property xil_pn:name="Device Family" xil_pn:value="Automotive CoolRunner2"/> + <property xil_pn:name="PROP_DesignName" xil_pn:value="system"/> + <property xil_pn:name="PROP_Enable_Incremental_Messaging" xil_pn:value="true"/> + <property xil_pn:name="PROP_Enable_Message_Filtering" xil_pn:value="true"/> + <property xil_pn:name="Package" xil_pn:value="*"/> + <property xil_pn:name="Preferred Language" xil_pn:value="Verilog"/> + <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)"/> + <property xil_pn:name="Speed Grade" xil_pn:value="-*"/> + <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)"/> + <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL"/> + <property xil_pn:name="Verbose Property Persistence" xil_pn:value="false"/> + </properties> + + <bindings/> + + <libraries/> + + <partitions> + <partition xil_pn:name="/"/> + </partitions> + +</project> diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/cst.xbcd b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/cst.xbcd Binary files differnew file mode 100644 index 000000000..4c6ff874e --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/cst.xbcd diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise.lock b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise.lock Binary files differnew file mode 100644 index 000000000..7f76861f9 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise.lock diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject Binary files differnew file mode 100644 index 000000000..61cf52f92 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject_StrTbl b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject_StrTbl Binary files differnew file mode 100644 index 000000000..1bc056b66 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject_StrTbl diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/__stored_object_table__ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/__stored_object_table__ Binary files differnew file mode 100644 index 000000000..0af2e0ddb --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/__stored_object_table__ diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl Binary files differnew file mode 100644 index 000000000..8947873d0 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl_StrTbl b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl_StrTbl Binary files differnew file mode 100644 index 000000000..bb5db76f3 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl_StrTbl diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main Binary files differnew file mode 100644 index 000000000..336370f80 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main_StrTbl b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main_StrTbl Binary files differnew file mode 100644 index 000000000..359501c5e --- /dev/null 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000000000..77989b78e --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Module-DataFactory-Default_StrTbl diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/Autonym/regkeys b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/Autonym/regkeys new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/Autonym/regkeys diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/HDProject/regkeys b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/HDProject/regkeys new file mode 100644 index 000000000..6b9df1847 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/HDProject/regkeys @@ -0,0 +1,24 @@ +CommandLine-Map + +s +CommandLine-Ngdbuild +ngdbuild -ise ../__xps/ise/system.ise -p xc5vfx70tff1136-1 -nt timestamp -bm system.bmm C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/system.ngc -uc system.ucf system.ngd +s +CommandLine-Par + +s +CommandLine-Xst + +s +Previous-NGD + +s +Previous-NGM + +s +Previous-Packed-NCD + +s +Previous-Routed-NCD + +s diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/regkeys b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/regkeys new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/regkeys diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/ProjectNavigator/regkeys b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/ProjectNavigator/regkeys new file mode 100644 index 000000000..4bd7af120 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/ProjectNavigator/regkeys @@ -0,0 +1,3 @@ +ISE_VERSION_LAST_SAVED_WITH +11.1 +s diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/ProjectNavigator11/regkeys b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/ProjectNavigator11/regkeys new file mode 100644 index 000000000..f90e0607f --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/ProjectNavigator11/regkeys @@ -0,0 +1,6 @@ +ISE_VERSION_LAST_SAVED_WITH +11.1 +s +XISE_FILE +system.xise +s diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/XSLTProcess/regkeys b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/XSLTProcess/regkeys new file mode 100644 index 000000000..87cda855f --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/XSLTProcess/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/XSLTProcess.xmsgs +s diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/_ProjRepoInternal_/regkeys b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/_ProjRepoInternal_/regkeys new file mode 100644 index 000000000..70eaf0b72 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/_ProjRepoInternal_/regkeys @@ -0,0 +1,21 @@ +ISE_VERSION_CREATED_WITH +11.1 +s +ISE_VERSION_LAST_SAVED_WITH +11.2 +s +LastRepoDir +E:\my_projects\Wittenstein\release\svn\main\FreeRTOS\Demo\PCC440_Xilinx_Virtex5_GCC\__xps\ise\ +s +OBJSTORE_VERSION +1.3 +s +PROJECT_CREATION_TIMESTAMP +2009-06-11T19:26:19 +s +REGISTRY_VERSION +1.1 +s +REPOSITORY_VERSION +1.1 +s diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/bitgen/regkeys b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/bitgen/regkeys new file mode 100644 index 000000000..949818c61 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/bitgen/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/bitgen.xmsgs +s diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/bitinit/regkeys b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/bitinit/regkeys new file mode 100644 index 000000000..dae1ec74d --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/bitinit/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/bitinit.xmsgs +s diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/common/regkeys b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/common/regkeys new file mode 100644 index 000000000..fac2f6efe --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/common/regkeys @@ -0,0 +1,12 @@ +IncrementalMessagingEnabled +true +s +MessageCaptureEnabled +true +s +MessageFilterFile +filter.filter +s +MessageFilteringEnabled +true +s diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/cpldfit/regkeys b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/cpldfit/regkeys new file mode 100644 index 000000000..f3969b3ea --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/cpldfit/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/cpldfit.xmsgs +s diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/dumpngdio/regkeys b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/dumpngdio/regkeys new file mode 100644 index 000000000..7e5b4bbcd --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/dumpngdio/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/dumpngdio.xmsgs +s diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/fuse/regkeys b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/fuse/regkeys new file mode 100644 index 000000000..77fa32d32 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/fuse/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/fuse.xmsgs +s diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/hprep6/regkeys b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/hprep6/regkeys new file mode 100644 index 000000000..e654ecd77 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/hprep6/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/hprep6.xmsgs +s diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/idem/regkeys b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/idem/regkeys new file mode 100644 index 000000000..7b9c3214a --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/idem/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/idem.xmsgs +s diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/libgen/regkeys b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/libgen/regkeys new file mode 100644 index 000000000..a2612daeb --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/libgen/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/libgen.xmsgs +s diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/map/regkeys b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/map/regkeys new file mode 100644 index 000000000..447e64cb9 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/map/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/map.xmsgs +s diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/netgen/regkeys b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/netgen/regkeys new file mode 100644 index 000000000..b15e57f97 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/netgen/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/netgen.xmsgs +s diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/ngc2edif/regkeys b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/ngc2edif/regkeys new file mode 100644 index 000000000..2cb66e467 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/ngc2edif/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/ngc2edif.xmsgs +s diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/ngcbuild/regkeys b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/ngcbuild/regkeys new file mode 100644 index 000000000..af67ad186 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/ngcbuild/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/ngcbuild.xmsgs +s diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/ngdbuild/regkeys b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/ngdbuild/regkeys new file mode 100644 index 000000000..47ac460f4 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/ngdbuild/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/ngdbuild.xmsgs +s diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/par/regkeys b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/par/regkeys new file mode 100644 index 000000000..17ae8fbf3 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/par/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/par.xmsgs +s diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/platgen/regkeys b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/platgen/regkeys new file mode 100644 index 000000000..d4497d267 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/platgen/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/platgen.xmsgs +s diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/runner/regkeys b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/runner/regkeys new file mode 100644 index 000000000..d5e13d0a7 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/runner/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/runner.xmsgs +s diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/simgen/regkeys b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/simgen/regkeys new file mode 100644 index 000000000..e12ea3860 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/simgen/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/simgen.xmsgs +s diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/taengine/regkeys b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/taengine/regkeys new file mode 100644 index 000000000..fc0b03832 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/taengine/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/taengine.xmsgs +s diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/trce/regkeys b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/trce/regkeys new file mode 100644 index 000000000..cffe0cfaa --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/trce/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/trce.xmsgs +s diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/tsim/regkeys b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/tsim/regkeys new file mode 100644 index 000000000..52a3e8bb0 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/tsim/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/tsim.xmsgs +s diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/vhpcomp/regkeys b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/vhpcomp/regkeys new file mode 100644 index 000000000..2d5cd6a1f --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/vhpcomp/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/vhpcomp.xmsgs +s diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/vlogcomp/regkeys b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/vlogcomp/regkeys new file mode 100644 index 000000000..9a5c2fab9 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/vlogcomp/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/vlogcomp.xmsgs +s diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/xpwr/regkeys b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/xpwr/regkeys new file mode 100644 index 000000000..c3f895c39 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/xpwr/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/xpwr.xmsgs +s diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/xreport/regkeys b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/xreport/regkeys new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/xreport/regkeys diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/xst/regkeys b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/xst/regkeys new file mode 100644 index 000000000..5b1ae90bb --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/xst/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/xst.xmsgs +s diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/version b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/version new file mode 100644 index 000000000..9ec2fe0a6 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/version @@ -0,0 +1,10 @@ +REPOSITORY_VERSION
+1.1
+REGISTRY_VERSION
+1.1
+OBJSTORE_VERSION
+1.3
+ISE_VERSION_CREATED_WITH
+11.1
+ISE_VERSION_LAST_SAVED_WITH
+11.2
diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/xmsgprops.lst b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/xmsgprops.lst new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/xmsgprops.lst diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/libgen.opt b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/libgen.opt new file mode 100644 index 000000000..55880074d --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/libgen.opt @@ -0,0 +1 @@ + -p virtex5 -msg __xps/ise/xmsgprops.lst
diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/platgen.opt b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/platgen.opt new file mode 100644 index 000000000..58d810347 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/platgen.opt @@ -0,0 +1,2 @@ + -p xc5vfx70tff1136-1 -lang vhdl -msg __xps/ise/xmsgprops.lst +
diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/rtosdemo_compiler.opt b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/rtosdemo_compiler.opt new file mode 100644 index 000000000..f61f00059 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/rtosdemo_compiler.opt @@ -0,0 +1,20 @@ +ppc440_0
+RTOSDEMO_SOURCES = /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/main.c
+RTOSDEMO_HEADERS =
+RTOSDEMO_CC = powerpc-eabi-gcc
+RTOSDEMO_CC_SIZE = powerpc-eabi-size
+RTOSDEMO_CC_OPT = -O0
+RTOSDEMO_CFLAGS = -D GCC_PPC440 -mregnames
+RTOSDEMO_CC_SEARCH = # -B
+RTOSDEMO_LIBPATH = -L./ppc440_0/lib/ # -L
+RTOSDEMO_INCLUDES = -I./ppc440_0/include/ -I../../Source/include -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop
+RTOSDEMO_LFLAGS = # -l
+RTOSDEMO_LINKER_SCRIPT = /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld
+RTOSDEMO_CC_DEBUG_FLAG = -g
+RTOSDEMO_CC_PROFILE_FLAG = # -pg
+RTOSDEMO_CC_GLOBPTR_FLAG= # -msdata=eabi
+RTOSDEMO_CC_INFERRED_FLAGS= -mcpu=440
+RTOSDEMO_CC_START_ADDR_FLAG= # # -Wl,-defsym -Wl,_START_ADDR=
+RTOSDEMO_CC_STACK_SIZE_FLAG= # # -Wl,-defsym -Wl,_STACK_SIZE=
+RTOSDEMO_CC_HEAP_SIZE_FLAG= # # -Wl,-defsym -Wl,_HEAP_SIZE=
+ $(RTOSDEMO_CC_INFERRED_FLAGS) \
diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/simgen.opt b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/simgen.opt new file mode 100644 index 000000000..953cc8cf8 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/simgen.opt @@ -0,0 +1 @@ + -p virtex5 -lang vhdl $(PPC440_0_BOOTLOOP) -msg __xps/ise/xmsgprops.lst -s mti -X C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/
diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/system.filters b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/system.filters new file mode 100644 index 000000000..327e64088 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/system.filters @@ -0,0 +1,121 @@ + +<FILTERS> + + <SET CLASS="PROJECT" VIEW_ID="BUSINTERFACE"> + <HEADERS HSCROLL="0" VSCROLL="0"> + <VARIABLE COL_INDEX="0" COL_WIDTH="217" IS_VISIBLE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="HEADER"/> + </HEADERS> + <SET CLASS="FILTER_GROUP" ID="By Connection" IS_EXPANDED="TRUE"> + <VARIABLE NAME="By Connection" VALUE="By Connection" VIEWDISP="Bus Interface Filters" VIEWTYPE="STATIC"/> + <SET CLASS="FILTER" ID="Connected" ROW_INDEX="0"> + <VARIABLE IS_LABELED="TRUE" NAME="Connected" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/> + </SET> + <SET CLASS="FILTER" ID="Unconnected" ROW_INDEX="1"> + <VARIABLE IS_LABELED="TRUE" NAME="Unconnected" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/> + </SET> + </SET> + <SET CLASS="FILTER_GROUP" ID="By Bus Standard" IS_EXPANDED="TRUE"> + <VARIABLE COLINDEX="0" NAME="By Bus Standard" VALUE="By Bus Standard" VIEWDISP="Bus Interface Filters" VIEWTYPE="STATIC"/> + <SET CLASS="FILTER" ID="OPB" IS_VISIBLE="FALSE" ROW_INDEX="0"> + <VARIABLE IS_LABELED="TRUE" NAME="OPB" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/> + </SET> + <SET CLASS="FILTER" ID="LMB" IS_VISIBLE="FALSE" ROW_INDEX="1"> + <VARIABLE IS_LABELED="TRUE" NAME="LMB" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/> + </SET> + <SET CLASS="FILTER" ID="PLBV34" IS_VISIBLE="FALSE" ROW_INDEX="2"> + <VARIABLE IS_LABELED="TRUE" NAME="PLBV34" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/> + </SET> + <SET CLASS="FILTER" ID="PLBV46" ROW_INDEX="3"> + <VARIABLE IS_LABELED="TRUE" NAME="PLBV46" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/> + </SET> + <SET CLASS="FILTER" ID="OCM" IS_VISIBLE="FALSE" ROW_INDEX="4"> + <VARIABLE IS_LABELED="TRUE" NAME="OCM" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/> + </SET> + <SET CLASS="FILTER" ID="FSL" IS_VISIBLE="FALSE" ROW_INDEX="5"> + <VARIABLE IS_LABELED="TRUE" NAME="FSL" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/> + </SET> + <SET CLASS="FILTER" ID="DCR" ROW_INDEX="6"> + <VARIABLE IS_LABELED="TRUE" NAME="DCR" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/> + </SET> + <SET CLASS="FILTER" ID="FCB" ROW_INDEX="7"> + <VARIABLE IS_LABELED="TRUE" NAME="FCB" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/> + </SET> + <SET CLASS="FILTER" ID="XIL" ROW_INDEX="8"> + <VARIABLE IS_LABELED="TRUE" NAME="Xilinx Point To Point" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/> + </SET> + <SET CLASS="FILTER" ID="USER" IS_VISIBLE="FALSE" ROW_INDEX="9"> + <VARIABLE IS_LABELED="TRUE" NAME="User Defined" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/> + </SET> + <SET CLASS="FILTER" ID="XCL" IS_VISIBLE="FALSE" ROW_INDEX="10"> + <VARIABLE IS_LABELED="TRUE" NAME="XCL" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/> + </SET> + </SET> + <SET CLASS="FILTER_GROUP" ID="By Interface Type" IS_EXPANDED="TRUE"> + <VARIABLE NAME="By Interface Type" VALUE="By Interface Type" VIEWDISP="Bus Interface Filters" VIEWTYPE="STATIC"/> + <SET CLASS="FILTER" ID="Slaves" ROW_INDEX="0"> + <VARIABLE IS_LABELED="TRUE" NAME="Slaves" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/> + </SET> + <SET CLASS="FILTER" ID="Masters" ROW_INDEX="1"> + <VARIABLE IS_LABELED="TRUE" NAME="Masters" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/> + </SET> + <SET CLASS="FILTER" ID="Master Slaves" ROW_INDEX="2"> + <VARIABLE IS_LABELED="TRUE" NAME="Master Slaves" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/> + </SET> + <SET CLASS="FILTER" ID="Monitors" ROW_INDEX="3"> + <VARIABLE IS_LABELED="TRUE" NAME="Monitors" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/> + </SET> + <SET CLASS="FILTER" ID="Targets" ROW_INDEX="4"> + <VARIABLE IS_LABELED="TRUE" NAME="Targets" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/> + </SET> + <SET CLASS="FILTER" ID="Initiators" ROW_INDEX="5"> + <VARIABLE IS_LABELED="TRUE" NAME="Initiators" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/> + </SET> + </SET> + </SET> + + <SET CLASS="PROJECT" VIEW_ID="PORT"> + <HEADERS> + <VARIABLE COL_WIDTH="50" IS_VISIBLE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="HEADER"/> + </HEADERS> + <SET CLASS="FILTER_GROUP" ID="By Connection" IS_EXPANDED="TRUE"> + <VARIABLE NAME="By Connection" VALUE="By Connection" VIEWDISP="Port Filters" VIEWTYPE="STATIC"/> + <SET CLASS="FILTER" ID="Defaults" ROW_INDEX="0"> + <VARIABLE IS_LABELED="TRUE" NAME="Defaults" VALUE="FALSE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/> + </SET> + <SET CLASS="FILTER" ID="Connected" ROW_INDEX="1"> + <VARIABLE IS_LABELED="TRUE" NAME="Connected" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/> + </SET> + <SET CLASS="FILTER" ID="Unconnected" ROW_INDEX="2"> + <VARIABLE IS_LABELED="TRUE" NAME="Unconnected" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/> + </SET> + </SET> + <SET CLASS="FILTER_GROUP" ID="By Class" IS_EXPANDED="TRUE"> + <VARIABLE COL_INDEX="0" NAME="By Class" VALUE="By Class" VIEWDISP="Port Filters" VIEWTYPE="STATIC"/> + <SET CLASS="FILTER" ID="Clocks" ROW_INDEX="0"> + <VARIABLE IS_LABELED="TRUE" NAME="Clocks" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/> + </SET> + <SET CLASS="FILTER" ID="Resets" ROW_INDEX="1"> + <VARIABLE IS_LABELED="TRUE" NAME="Resets" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/> + </SET> + <SET CLASS="FILTER" ID="Interrupts" ROW_INDEX="2"> + <VARIABLE IS_LABELED="TRUE" NAME="Interrupts" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/> + </SET> + <SET CLASS="FILTER" ID="Others" ROW_INDEX="3"> + <VARIABLE IS_LABELED="TRUE" NAME="Others" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/> + </SET> + </SET> + <SET CLASS="FILTER_GROUP" ID="By Direction" IS_EXPANDED="TRUE"> + <VARIABLE NAME="By Direction" VALUE="By Direction" VIEWDISP="Port Filters" VIEWTYPE="STATIC"/> + <SET CLASS="FILTER" ID="Inputs" ROW_INDEX="0"> + <VARIABLE IS_LABELED="TRUE" NAME="Inputs" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/> + </SET> + <SET CLASS="FILTER" ID="Outputs" ROW_INDEX="1"> + <VARIABLE IS_LABELED="TRUE" NAME="Outputs" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/> + </SET> + <SET CLASS="FILTER" ID="InOuts" ROW_INDEX="2"> + <VARIABLE IS_LABELED="TRUE" NAME="InOuts" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/> + </SET> + </SET> + </SET> + +</FILTERS>
\ No newline at end of file diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/system.gui b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/system.gui new file mode 100644 index 000000000..b115db307 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/system.gui @@ -0,0 +1,101 @@ + +<SETTINGS> + + <SET CLASS="PROJECT" DISPLAYMODE="TREE" VIEW_ID="BUSINTERFACE"> + <HEADERS HSCROLL="0" VSCROLL="0"> + <VARIABLE COL_INDEX="0" COL_WIDTH="189" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="1" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Bus Name" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="2" IS_VISIBLE="FALSE" VIEWDISP="Bus Standard" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="3" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="4" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="5" COL_WIDTH="227" IS_VISIBLE="TRUE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="6" IS_VISIBLE="FALSE" VIEWDISP="Type" VIEWTYPE="HEADER"/> + </HEADERS> + <SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="120,687,306" VERSION="0"/> + <STATUS> + <SELECTIONS/> + </STATUS> + </SET> + + <SET CLASS="PROJECT" DISPLAYMODE="FLAT" VIEW_ID="BUSINTERFACE"> + <HEADERS> + <VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Instance" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="1" IS_VISIBLE="TRUE" VIEWDISP="Bus Interface" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="2" IS_VISIBLE="TRUE" VIEWDISP="Bus Name" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="3" IS_VISIBLE="FALSE" VIEWDISP="Bus Standard" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="4" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="5" IS_VISIBLE="TRUE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="6" IS_VISIBLE="TRUE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="7" IS_VISIBLE="FALSE" VIEWDISP="Type" VIEWTYPE="HEADER"/> + </HEADERS> + <SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="180,450,180" VERSION="0"/> + </SET> + + <SET CLASS="PROJECT" DISPLAYMODE="TREE" VIEW_ID="PORT"> + <HEADERS HSCROLL="0" VSCROLL="0"> + <VARIABLE COL_INDEX="0" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="1" COL_WIDTH="231" IS_VISIBLE="TRUE" VIEWDISP="Net" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="2" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Direction" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="3" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Range" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="4" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Class" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="5" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Frequency" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="6" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Reset Polarity" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="7" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Sensitivity" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="8" COL_WIDTH="25" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="9" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="10" IS_VISIBLE="TRUE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/> + </HEADERS> + <SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="0,586,143" VERSION="0"/> + </SET> + + <SET CLASS="PROJECT" DISPLAYMODE="FLAT" VIEW_ID="PORT"> + <HEADERS> + <VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Instance" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="1" IS_VISIBLE="TRUE" VIEWDISP="Port Name" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="2" IS_VISIBLE="TRUE" VIEWDISP="Net" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="3" IS_VISIBLE="TRUE" VIEWDISP="Direction" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="4" IS_VISIBLE="TRUE" VIEWDISP="Range" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="5" IS_VISIBLE="TRUE" VIEWDISP="Class" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="6" IS_VISIBLE="TRUE" VIEWDISP="Frequency" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="7" IS_VISIBLE="TRUE" VIEWDISP="Reset Polarity" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="8" IS_VISIBLE="TRUE" VIEWDISP="Sensitivity" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="9" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="10" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="11" IS_VISIBLE="TRUE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/> + </HEADERS> + <SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="0,630,180" VERSION="0"/> + </SET> + + <SET CLASS="PROJECT" DISPLAYMODE="TREE" VIEW_ID="ADDRESS"> + <HEADERS> + <VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Instance" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="1" IS_VISIBLE="TRUE" VIEWDISP="Base Name" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="2" IS_VISIBLE="TRUE" VIEWDISP="Base Address" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="3" IS_VISIBLE="TRUE" VIEWDISP="High Address" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="4" IS_VISIBLE="TRUE" VIEWDISP="Size" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="5" IS_VISIBLE="TRUE" VIEWDISP="Bus Interface(s)" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="6" IS_VISIBLE="TRUE" VIEWDISP="Bus Name" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="7" IS_VISIBLE="TRUE" VIEWDISP="ICache" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="8" IS_VISIBLE="TRUE" VIEWDISP="DCache" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="9" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="10" IS_VISIBLE="TRUE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/> + </HEADERS> + </SET> + + <SET CLASS="PROJECT" DISPLAYMODE="FLAT" VIEW_ID="ADDRESS"> + <HEADERS> + <VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Instance" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="1" IS_VISIBLE="TRUE" VIEWDISP="Base Name" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="2" IS_VISIBLE="TRUE" VIEWDISP="Base Address" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="3" IS_VISIBLE="TRUE" VIEWDISP="High Address" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="4" IS_VISIBLE="TRUE" VIEWDISP="Size" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="5" IS_VISIBLE="TRUE" VIEWDISP="Bus Interface(s)" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="6" IS_VISIBLE="TRUE" VIEWDISP="Bus Name" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="7" IS_VISIBLE="TRUE" VIEWDISP="ICache" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="8" IS_VISIBLE="TRUE" VIEWDISP="DCache" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="9" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/> + <VARIABLE COL_INDEX="10" IS_VISIBLE="TRUE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/> + </HEADERS> + </SET> + +</SETTINGS>
\ No newline at end of file diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/system.xml b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/system.xml new file mode 100644 index 000000000..bcd8c1da0 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/system.xml @@ -0,0 +1,4197 @@ + +<EDKSYSTEM EDKVERSION="11.2" EDWVERSION="1.1" TIMESTAMP="Tue Jun 30 20:53:27 2009"> + + <SYSTEMINFO ARCH="virtex5" DEVICE="5vfx70t" PACKAGE="ff1136" PART="5vfx70tff1136-1" SOURCE="C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/" SPEEDGRADE="-1"/> + + <EXTERNALPORTS> + <PORT DIR="I" MHS_INDEX="0" NAME="fpga_0_RS232_Uart_1_RX_pin" SIGNAME="fpga_0_RS232_Uart_1_RX_pin"/> + <PORT DIR="O" MHS_INDEX="1" NAME="fpga_0_RS232_Uart_1_TX_pin" SIGNAME="fpga_0_RS232_Uart_1_TX_pin"/> + <PORT DIR="IO" ENDIAN="LITTLE" LSB="0" MHS_INDEX="2" MSB="7" NAME="fpga_0_LEDs_8Bit_GPIO_IO_pin" SIGNAME="fpga_0_LEDs_8Bit_GPIO_IO_pin"/> + <PORT DIR="IO" ENDIAN="LITTLE" LSB="0" MHS_INDEX="3" MSB="4" NAME="fpga_0_LEDs_Positions_GPIO_IO_pin" SIGNAME="fpga_0_LEDs_Positions_GPIO_IO_pin"/> + <PORT DIR="IO" ENDIAN="LITTLE" LSB="0" MHS_INDEX="4" MSB="4" NAME="fpga_0_Push_Buttons_5Bit_GPIO_IO_pin" SIGNAME="fpga_0_Push_Buttons_5Bit_GPIO_IO_pin"/> + <PORT DIR="IO" ENDIAN="LITTLE" LSB="0" MHS_INDEX="5" MSB="7" NAME="fpga_0_DIP_Switches_8Bit_GPIO_IO_pin" SIGNAME="fpga_0_DIP_Switches_8Bit_GPIO_IO_pin"/> + <PORT DIR="IO" MHS_INDEX="6" NAME="fpga_0_IIC_EEPROM_Sda_pin" SIGNAME="fpga_0_IIC_EEPROM_Sda_pin"/> + <PORT DIR="IO" MHS_INDEX="7" NAME="fpga_0_IIC_EEPROM_Scl_pin" SIGNAME="fpga_0_IIC_EEPROM_Scl_pin"/> + <PORT DIR="O" ENDIAN="LITTLE" LSB="7" MHS_INDEX="8" MSB="30" NAME="fpga_0_SRAM_Mem_A_pin" SIGNAME="fpga_0_SRAM_Mem_A_pin_vslice_7_30_concat"/> + <PORT DIR="O" MHS_INDEX="9" NAME="fpga_0_SRAM_Mem_CEN_pin" SIGNAME="fpga_0_SRAM_Mem_CEN_pin"/> + <PORT DIR="O" MHS_INDEX="10" NAME="fpga_0_SRAM_Mem_OEN_pin" SIGNAME="fpga_0_SRAM_Mem_OEN_pin"/> + <PORT DIR="O" MHS_INDEX="11" NAME="fpga_0_SRAM_Mem_WEN_pin" SIGNAME="fpga_0_SRAM_Mem_WEN_pin"/> + <PORT DIR="O" ENDIAN="LITTLE" LSB="0" MHS_INDEX="12" MSB="3" NAME="fpga_0_SRAM_Mem_BEN_pin" SIGNAME="fpga_0_SRAM_Mem_BEN_pin"/> + <PORT DIR="O" MHS_INDEX="13" NAME="fpga_0_SRAM_Mem_ADV_LDN_pin" SIGNAME="fpga_0_SRAM_Mem_ADV_LDN_pin"/> + <PORT DIR="IO" ENDIAN="LITTLE" LSB="0" MHS_INDEX="14" MSB="31" NAME="fpga_0_SRAM_Mem_DQ_pin" SIGNAME="fpga_0_SRAM_Mem_DQ_pin"/> + <PORT DIR="O" MHS_INDEX="15" NAME="fpga_0_SRAM_ZBT_CLK_OUT_pin" SIGIS="CLK" SIGNAME="SRAM_CLK_OUT_s"/> + <PORT CLKFREQUENCY="125000000" DIR="I" MHS_INDEX="16" NAME="fpga_0_SRAM_ZBT_CLK_FB_pin" SIGIS="CLK" SIGNAME="SRAM_CLK_FB_s"/> + <PORT DIR="I" MHS_INDEX="17" NAME="fpga_0_PCIe_Bridge_RXN_pin" SIGNAME="fpga_0_PCIe_Bridge_RXN_pin"/> + <PORT DIR="I" MHS_INDEX="18" NAME="fpga_0_PCIe_Bridge_RXP_pin" SIGNAME="fpga_0_PCIe_Bridge_RXP_pin"/> + <PORT DIR="O" MHS_INDEX="19" NAME="fpga_0_PCIe_Bridge_TXN_pin" SIGNAME="fpga_0_PCIe_Bridge_TXN_pin"/> + <PORT DIR="O" MHS_INDEX="20" NAME="fpga_0_PCIe_Bridge_TXP_pin" SIGNAME="fpga_0_PCIe_Bridge_TXP_pin"/> + <PORT DIR="I" MHS_INDEX="21" NAME="fpga_0_Ethernet_MAC_PHY_tx_clk_pin" SIGNAME="fpga_0_Ethernet_MAC_PHY_tx_clk_pin"/> + <PORT DIR="I" MHS_INDEX="22" NAME="fpga_0_Ethernet_MAC_PHY_rx_clk_pin" SIGNAME="fpga_0_Ethernet_MAC_PHY_rx_clk_pin"/> + <PORT DIR="I" MHS_INDEX="23" NAME="fpga_0_Ethernet_MAC_PHY_crs_pin" SIGNAME="fpga_0_Ethernet_MAC_PHY_crs_pin"/> + <PORT DIR="I" MHS_INDEX="24" NAME="fpga_0_Ethernet_MAC_PHY_dv_pin" SIGNAME="fpga_0_Ethernet_MAC_PHY_dv_pin"/> + <PORT DIR="I" ENDIAN="LITTLE" LSB="3" MHS_INDEX="25" MSB="0" NAME="fpga_0_Ethernet_MAC_PHY_rx_data_pin" SIGNAME="fpga_0_Ethernet_MAC_PHY_rx_data_pin"/> + <PORT DIR="I" MHS_INDEX="26" NAME="fpga_0_Ethernet_MAC_PHY_col_pin" SIGNAME="fpga_0_Ethernet_MAC_PHY_col_pin"/> + <PORT DIR="I" MHS_INDEX="27" NAME="fpga_0_Ethernet_MAC_PHY_rx_er_pin" SIGNAME="fpga_0_Ethernet_MAC_PHY_rx_er_pin"/> + <PORT DIR="O" MHS_INDEX="28" NAME="fpga_0_Ethernet_MAC_PHY_rst_n_pin" SIGNAME="fpga_0_Ethernet_MAC_PHY_rst_n_pin"/> + <PORT DIR="O" MHS_INDEX="29" NAME="fpga_0_Ethernet_MAC_PHY_tx_en_pin" SIGNAME="fpga_0_Ethernet_MAC_PHY_tx_en_pin"/> + <PORT DIR="O" ENDIAN="LITTLE" LSB="3" MHS_INDEX="30" MSB="0" NAME="fpga_0_Ethernet_MAC_PHY_tx_data_pin" SIGNAME="fpga_0_Ethernet_MAC_PHY_tx_data_pin"/> + <PORT DIR="I" MHS_INDEX="31" NAME="fpga_0_Ethernet_MAC_MDINT_pin" SENSITIVITY="LEVEL_LOW" SIGIS="INTERRUPT" SIGNAME="fpga_0_Ethernet_MAC_MDINT_pin"/> + <PORT DIR="IO" ENDIAN="BIG" LSB="63" MHS_INDEX="32" MSB="0" NAME="fpga_0_DDR2_SDRAM_DDR2_DQ_pin" SIGNAME="fpga_0_DDR2_SDRAM_DDR2_DQ_pin"/> + <PORT DIR="IO" ENDIAN="LITTLE" LSB="7" MHS_INDEX="33" MSB="0" NAME="fpga_0_DDR2_SDRAM_DDR2_DQS_pin" SIGNAME="fpga_0_DDR2_SDRAM_DDR2_DQS_pin"/> + <PORT DIR="IO" ENDIAN="BIG" LSB="7" MHS_INDEX="34" MSB="0" NAME="fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin" SIGNAME="fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin"/> + <PORT DIR="O" ENDIAN="LITTLE" LSB="12" MHS_INDEX="35" MSB="0" NAME="fpga_0_DDR2_SDRAM_DDR2_A_pin" SIGNAME="fpga_0_DDR2_SDRAM_DDR2_A_pin"/> + <PORT DIR="O" ENDIAN="BIG" LSB="1" MHS_INDEX="36" MSB="0" NAME="fpga_0_DDR2_SDRAM_DDR2_BA_pin" SIGNAME="fpga_0_DDR2_SDRAM_DDR2_BA_pin"/> + <PORT DIR="O" MHS_INDEX="37" NAME="fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin" SIGNAME="fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin"/> + <PORT DIR="O" MHS_INDEX="38" NAME="fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin" SIGNAME="fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin"/> + <PORT DIR="O" MHS_INDEX="39" NAME="fpga_0_DDR2_SDRAM_DDR2_WE_N_pin" SIGNAME="fpga_0_DDR2_SDRAM_DDR2_WE_N_pin"/> + <PORT DIR="O" MHS_INDEX="40" NAME="fpga_0_DDR2_SDRAM_DDR2_CS_N_pin" SIGNAME="fpga_0_DDR2_SDRAM_DDR2_CS_N_pin"/> + <PORT DIR="O" ENDIAN="LITTLE" LSB="1" MHS_INDEX="41" MSB="0" NAME="fpga_0_DDR2_SDRAM_DDR2_ODT_pin" SIGNAME="fpga_0_DDR2_SDRAM_DDR2_ODT_pin"/> + <PORT DIR="O" MHS_INDEX="42" NAME="fpga_0_DDR2_SDRAM_DDR2_CKE_pin" SIGNAME="fpga_0_DDR2_SDRAM_DDR2_CKE_pin"/> + <PORT DIR="O" ENDIAN="BIG" LSB="7" MHS_INDEX="43" MSB="0" NAME="fpga_0_DDR2_SDRAM_DDR2_DM_pin" SIGNAME="fpga_0_DDR2_SDRAM_DDR2_DM_pin"/> + <PORT DIR="O" ENDIAN="LITTLE" LSB="1" MHS_INDEX="44" MSB="0" NAME="fpga_0_DDR2_SDRAM_DDR2_CK_pin" SIGNAME="fpga_0_DDR2_SDRAM_DDR2_CK_pin"/> + <PORT DIR="O" ENDIAN="BIG" LSB="1" MHS_INDEX="45" MSB="0" NAME="fpga_0_DDR2_SDRAM_DDR2_CK_N_pin" SIGNAME="fpga_0_DDR2_SDRAM_DDR2_CK_N_pin"/> + <PORT DIR="O" ENDIAN="LITTLE" LSB="6" MHS_INDEX="46" MSB="0" NAME="fpga_0_SysACE_CompactFlash_SysACE_MPA_pin" SIGNAME="fpga_0_SysACE_CompactFlash_SysACE_MPA_pin"/> + <PORT DIR="I" MHS_INDEX="47" NAME="fpga_0_SysACE_CompactFlash_SysACE_CLK_pin" SIGNAME="fpga_0_SysACE_CompactFlash_SysACE_CLK_pin"/> + <PORT DIR="I" MHS_INDEX="48" NAME="fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin" SIGNAME="fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin"/> + <PORT DIR="O" MHS_INDEX="49" NAME="fpga_0_SysACE_CompactFlash_SysACE_CEN_pin" SIGNAME="fpga_0_SysACE_CompactFlash_SysACE_CEN_pin"/> + <PORT DIR="O" MHS_INDEX="50" NAME="fpga_0_SysACE_CompactFlash_SysACE_OEN_pin" SIGNAME="fpga_0_SysACE_CompactFlash_SysACE_OEN_pin"/> + <PORT DIR="O" MHS_INDEX="51" NAME="fpga_0_SysACE_CompactFlash_SysACE_WEN_pin" SIGNAME="fpga_0_SysACE_CompactFlash_SysACE_WEN_pin"/> + <PORT DIR="IO" ENDIAN="BIG" LSB="15" MHS_INDEX="52" MSB="0" NAME="fpga_0_SysACE_CompactFlash_SysACE_MPD_pin" SIGNAME="fpga_0_SysACE_CompactFlash_SysACE_MPD_pin"/> + <PORT CLKFREQUENCY="100000000" DIR="I" MHS_INDEX="53" NAME="fpga_0_clk_1_sys_clk_pin" SIGIS="CLK" SIGNAME="dcm_clk_s"/> + <PORT DIR="I" MHS_INDEX="54" NAME="fpga_0_rst_1_sys_rst_pin" RSTPOLARITY="0" SIGIS="RST" SIGNAME="sys_rst_s"/> + <PORT DIR="I" MHS_INDEX="55" NAME="fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin" SIGIS="CLK" SIGNAME="PCIe_Diff_Clk"/> + <PORT DIR="I" MHS_INDEX="56" NAME="fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin" SIGIS="CLK" SIGNAME="PCIe_Diff_Clk"/> + </EXTERNALPORTS> + + <MODULES> + <MODULE HWVERSION="1.01.a" INSTANCE="ppc440_0" IPTYPE="PROCESSOR" MHS_INDEX="0" MODCLASS="PROCESSOR" MODTYPE="ppc440_virtex5" PROCTYPE="PPC440"> + <DESCRIPTION TYPE="SHORT">PowerPC 440 Virtex-5</DESCRIPTION> + <DESCRIPTION TYPE="LONG">A wrapper to instantiate the PowerPC 440 Processor Block primitive</DESCRIPTION> + <DOCUMENTATION> + <DOCUMENT SOURCE="c:/devtools/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/ppc440_virtex5_v1_01_a/doc/ppc440_virtex5.pdf" TYPE="IP"/> + </DOCUMENTATION> + <LICENSEINFO ICON_NAME="ps_core_preferred"/> + <PARAMETER MPD_INDEX="0" NAME="C_PIR" TYPE="std_logic_vector(28 to 31)" VALUE="0b1111"> + <DESCRIPTION>Unique Processor ID</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="1" NAME="C_ENDIAN_RESET" TYPE="std_logic" VALUE="0"> + <DESCRIPTION>Reset Value for Endian Storage Byte Ordering</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="2" NAME="C_USER_RESET" TYPE="std_logic_vector(0 to 3)" VALUE="0b0000"> + <DESCRIPTION>Reset Value for User Defined Storage Attributes: Tattribute[4:7]</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="3" NAME="C_INTERCONNECT_IMASK" TYPE="BIT_VECTOR(0 to 31)" VALUE="0xffffffff"> + <DESCRIPTION>Interrupt Mask for Crossbar-related Interrupts</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="4" NAME="C_ICU_RD_FETCH_PLB_PRIO" TYPE="std_logic_vector(0 to 1)" VALUE="0b00"> + <DESCRIPTION>Arbitration Priority for all CPU Fetch Requests</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="5" NAME="C_ICU_RD_SPEC_PLB_PRIO" TYPE="std_logic_vector(0 to 1)" VALUE="0b00"> + <DESCRIPTION>Arbitration Priority for all Speculative CPU Fetch Requests</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="6" NAME="C_ICU_RD_TOUCH_PLB_PRIO" TYPE="std_logic_vector(0 to 1)" VALUE="0b00"> + <DESCRIPTION>Arbitration Priority for all CPU Fetch Requests Initiated by ICBT Instructions</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="7" NAME="C_DCU_RD_LD_CACHE_PLB_PRIO" TYPE="std_logic_vector(0 to 1)" VALUE="0b00"> + <DESCRIPTION>Arbitration Priority for all CPU Cacheable Load Requests</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="8" NAME="C_DCU_RD_NONCACHE_PLB_PRIO" TYPE="std_logic_vector(0 to 1)" VALUE="0b00"> + <DESCRIPTION>Arbitration Priority for CPU Non-cacheable Load Requests</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="9" NAME="C_DCU_RD_TOUCH_PLB_PRIO" TYPE="std_logic_vector(0 to 1)" VALUE="0b00"> + <DESCRIPTION>Arbitration Priority for all CPU Load Requests Initiated by DCBT Instructions</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="10" NAME="C_DCU_RD_URGENT_PLB_PRIO" TYPE="std_logic_vector(0 to 1)" VALUE="0b00"> + <DESCRIPTION>Arbitration Priority for an Urgent CPU Load Request</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="11" NAME="C_DCU_WR_FLUSH_PLB_PRIO" TYPE="std_logic_vector(0 to 1)" VALUE="0b00"> + <DESCRIPTION>Arbitration Priority for CPU Write Requests Initiated by flush Instruction</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="12" NAME="C_DCU_WR_STORE_PLB_PRIO" TYPE="std_logic_vector(0 to 1)" VALUE="0b00"> + <DESCRIPTION>Arbitration Priority for CPU Write Requests Initiated by store Instructions</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="13" NAME="C_DCU_WR_URGENT_PLB_PRIO" TYPE="std_logic_vector(0 to 1)" VALUE="0b00"> + <DESCRIPTION>Arbitration Priority for an Urgent CPU Write Request</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="14" NAME="C_DMA0_PLB_PRIO" TYPE="bit_vector(0 to 1)" VALUE="0b00"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="15" NAME="C_DMA1_PLB_PRIO" TYPE="bit_vector(0 to 1)" VALUE="0b00"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="16" NAME="C_DMA2_PLB_PRIO" TYPE="bit_vector(0 to 1)" VALUE="0b00"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="17" NAME="C_DMA3_PLB_PRIO" TYPE="bit_vector(0 to 1)" VALUE="0b00"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" MPD_INDEX="18" NAME="C_IDCR_BASEADDR" TYPE="std_logic_vector(0 to 9)" VALUE="0b0000000000"> + <DESCRIPTION>Internal DCR Register Base Address</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" MPD_INDEX="19" NAME="C_IDCR_HIGHADDR" TYPE="std_logic_vector(0 to 9)" VALUE="0b0011111111"> + <DESCRIPTION>Internal DCR Register High Address</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="20" NAME="C_APU_CONTROL" TYPE="BIT_VECTOR(0 to 16)" VALUE="0b00010000000000000"> + <DESCRIPTION>APU Controller Configuration Register Value</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="21" NAME="C_APU_UDI_0" TYPE="BIT_VECTOR(0 to 23)" VALUE="0b000000000000000000000000"> + <DESCRIPTION>UDI Configuration Register 0 Value</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="22" NAME="C_APU_UDI_1" TYPE="BIT_VECTOR(0 to 23)" VALUE="0b000000000000000000000000"> + <DESCRIPTION>UDI Configuration Register 1 Value</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="23" NAME="C_APU_UDI_2" TYPE="BIT_VECTOR(0 to 23)" VALUE="0b000000000000000000000000"> + <DESCRIPTION>UDI Configuration Register 2 Value</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="24" NAME="C_APU_UDI_3" TYPE="BIT_VECTOR(0 to 23)" VALUE="0b000000000000000000000000"> + <DESCRIPTION>UDI Configuration Register 3 Value</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="25" NAME="C_APU_UDI_4" TYPE="BIT_VECTOR(0 to 23)" VALUE="0b000000000000000000000000"> + <DESCRIPTION>UDI Configuration Register 4 Value</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="26" NAME="C_APU_UDI_5" TYPE="BIT_VECTOR(0 to 23)" VALUE="0b000000000000000000000000"> + <DESCRIPTION>UDI Configuration Register 5 Value</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="27" NAME="C_APU_UDI_6" TYPE="BIT_VECTOR(0 to 23)" VALUE="0b000000000000000000000000"> + <DESCRIPTION>UDI Configuration Register 6 Value</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="28" NAME="C_APU_UDI_7" TYPE="BIT_VECTOR(0 to 23)" VALUE="0b000000000000000000000000"> + <DESCRIPTION>UDI Configuration Register 7 Value</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="29" NAME="C_APU_UDI_8" TYPE="BIT_VECTOR(0 to 23)" VALUE="0b000000000000000000000000"> + <DESCRIPTION>UDI Configuration Register 8 Value</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="30" NAME="C_APU_UDI_9" TYPE="BIT_VECTOR(0 to 23)" VALUE="0b000000000000000000000000"> + <DESCRIPTION>UDI Configuration Register 9 Value</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="31" NAME="C_APU_UDI_10" TYPE="BIT_VECTOR(0 to 23)" VALUE="0b000000000000000000000000"> + <DESCRIPTION>UDI Configuration Register 10 Value</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="32" NAME="C_APU_UDI_11" TYPE="BIT_VECTOR(0 to 23)" VALUE="0b000000000000000000000000"> + <DESCRIPTION>UDI Configuration Register 11 Value</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="33" NAME="C_APU_UDI_12" TYPE="BIT_VECTOR(0 to 23)" VALUE="0b000000000000000000000000"> + <DESCRIPTION>UDI Configuration Register 12 Value</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="34" NAME="C_APU_UDI_13" TYPE="BIT_VECTOR(0 to 23)" VALUE="0b000000000000000000000000"> + <DESCRIPTION>UDI Configuration Register 13 Value</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="35" NAME="C_APU_UDI_14" TYPE="BIT_VECTOR(0 to 23)" VALUE="0b000000000000000000000000"> + <DESCRIPTION>UDI Configuration Register 14 Value</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="36" NAME="C_APU_UDI_15" TYPE="BIT_VECTOR(0 to 23)" VALUE="0b000000000000000000000000"> + <DESCRIPTION>UDI Configuration Register 15 Value</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="37" NAME="C_PPC440MC_ADDR_BASE" TYPE="std_logic_vector(0 to 31)" VALUE="0x00000000"> + <DESCRIPTION>Base Address of Memory</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="38" NAME="C_PPC440MC_ADDR_HIGH" TYPE="std_logic_vector(0 to 31)" VALUE="0x0fffffff"> + <DESCRIPTION>High Address of Memory </DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="39" NAME="C_PPC440MC_ROW_CONFLICT_MASK" TYPE="BIT_VECTOR(0 to 31)" VALUE="0x003FFE00"> + <DESCRIPTION>Mask Used to Determine a Row Conflict</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="40" NAME="C_PPC440MC_BANK_CONFLICT_MASK" TYPE="BIT_VECTOR(0 to 31)" VALUE="0x00C00000"> + <DESCRIPTION>Mask Used to Determine a Bank Conflict</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="41" NAME="C_PPC440MC_CONTROL" TYPE="BIT_VECTOR(0 to 31)" VALUE="0xF810008F"> + <DESCRIPTION>Control and Configuration for the MC Interface</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="42" NAME="C_PPC440MC_PRIO_ICU" TYPE="integer" VALUE="4"> + <DESCRIPTION>Secondary Arbitration Priority for all Instruction Fetches from CPU</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="43" NAME="C_PPC440MC_PRIO_DCUW" TYPE="integer" VALUE="3"> + <DESCRIPTION>Secondary Arbitration Priority for all Data Writes from CPU</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="44" NAME="C_PPC440MC_PRIO_DCUR" TYPE="integer" VALUE="2"> + <DESCRIPTION>Secondary Arbitration Priority for all Data Reads from CPU</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="45" NAME="C_PPC440MC_PRIO_SPLB1" TYPE="integer" VALUE="0"> + <DESCRIPTION>Secondary Arbitration Priority for SPLB1, DMA2 and DMA3</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="46" NAME="C_PPC440MC_PRIO_SPLB0" TYPE="integer" VALUE="1"> + <DESCRIPTION>Secondary Arbitration Priority for SPLB0, DMA0 and DMA1</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="47" NAME="C_PPC440MC_ARB_MODE" TYPE="integer" VALUE="0"> + <DESCRIPTION>Memory Control Interface Arbitration Mode</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="48" NAME="C_PPC440MC_MAX_BURST" TYPE="integer" VALUE="8"> + <DESCRIPTION>Max Number of Quad-words per Burst thru Xbar to MC Interface</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="49" NAME="C_MPLB_AWIDTH" TYPE="integer" VALUE="32"> + <DESCRIPTION>C_MPLB_AWIDTH</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="50" NAME="C_MPLB_DWIDTH" TYPE="integer" VALUE="128"> + <DESCRIPTION>C_MPLB_DWIDTH</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="51" NAME="C_MPLB_NATIVE_DWIDTH" TYPE="integer" VALUE="128"> + <DESCRIPTION>C_MPLB_NATIVE_DWIDTH</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="52" NAME="C_MPLB_COUNTER" TYPE="BIT_VECTOR(0 to 31)" VALUE="0x00000500"> + <DESCRIPTION>Watchdog Counter Threshold</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="53" NAME="C_MPLB_PRIO_ICU" TYPE="integer" VALUE="4"> + <DESCRIPTION>Secondary Arbitration Prio for Instr Fetches</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="54" NAME="C_MPLB_PRIO_DCUW" TYPE="integer" VALUE="3"> + <DESCRIPTION>Secondary Arbitration Prio for Data Writes</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="55" NAME="C_MPLB_PRIO_DCUR" TYPE="integer" VALUE="2"> + <DESCRIPTION>Secondary Arbitration Prio for Data Reads</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="56" NAME="C_MPLB_PRIO_SPLB1" TYPE="integer" VALUE="0"> + <DESCRIPTION>Secondary Arbitration Prio for SPLB1, DMA2, DMA3</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="57" NAME="C_MPLB_PRIO_SPLB0" TYPE="integer" VALUE="1"> + <DESCRIPTION>Secondary Arbitration Prio for SPLB0, DMA0, DMA1</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="58" NAME="C_MPLB_ARB_MODE" TYPE="integer" VALUE="0"> + <DESCRIPTION>MPLB Arbitration Mode</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="59" NAME="C_MPLB_SYNC_TATTRIBUTE" TYPE="integer" VALUE="0"> + <DESCRIPTION>Allow MBusy to Block MPLB</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="60" NAME="C_MPLB_MAX_BURST" TYPE="integer" VALUE="8"> + <DESCRIPTION>Max Num of Quad-words in Bursts</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="61" NAME="C_MPLB_ALLOW_LOCK_XFER" TYPE="integer" VALUE="1"> + <DESCRIPTION>Allow Locked Transfer</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="62" NAME="C_MPLB_READ_PIPE_ENABLE" TYPE="integer" VALUE="1"> + <DESCRIPTION>Allow Read Addr Pipelining</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="63" NAME="C_MPLB_WRITE_PIPE_ENABLE" TYPE="integer" VALUE="1"> + <DESCRIPTION>Allow Write Addr Pipelining</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="64" NAME="C_MPLB_WRITE_POST_ENABLE" TYPE="integer" VALUE="1"> + <DESCRIPTION>Allow Posted Writes</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="65" NAME="C_MPLB_P2P" TYPE="integer" VALUE="0"> + <DESCRIPTION>C_MPLB_P2P</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="66" NAME="C_MPLB_WDOG_ENABLE" TYPE="integer" VALUE="1"> + <DESCRIPTION>Enable Watchdog Timer</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="67" NAME="C_SPLB0_AWIDTH" TYPE="integer" VALUE="32"> + <DESCRIPTION>C_SPLB0_AWIDTH</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="68" NAME="C_SPLB0_DWIDTH" TYPE="integer" VALUE="128"> + <DESCRIPTION>C_SPLB0_DWIDTH</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="69" NAME="C_SPLB0_NATIVE_DWIDTH" TYPE="integer" VALUE="128"> + <DESCRIPTION>C_SPLB0_NATIVE_DWIDTH</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="70" NAME="C_SPLB0_SUPPORT_BURSTS" TYPE="integer" VALUE="1"> + <DESCRIPTION>SPLB Support Bursts</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="71" NAME="C_SPLB0_USE_MPLB_ADDR" TYPE="integer" VALUE="1"> + <DESCRIPTION>Allow SPLB0 to Access MPLB Addr</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="72" NAME="C_SPLB0_NUM_MPLB_ADDR_RNG" TYPE="integer" VALUE="1"> + <DESCRIPTION>Number of MPLB Addr Ranges</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" MPD_INDEX="73" NAME="C_SPLB0_RNG_MC_BASEADDR" TYPE="std_logic_vector(0 to 31)" VALUE="0x00000000"> + <DESCRIPTION>Base Addr </DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" MPD_INDEX="74" NAME="C_SPLB0_RNG_MC_HIGHADDR" TYPE="std_logic_vector(0 to 31)" VALUE="0x0fffffff"> + <DESCRIPTION>High Addr </DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="BRIDGE" CHANGEDBY="USER" MPD_INDEX="75" NAME="C_SPLB0_RNG0_MPLB_BASEADDR" TYPE="std_logic_vector(0 to 31)" VALUE="0x80000000"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="BRIDGE" CHANGEDBY="USER" MPD_INDEX="76" NAME="C_SPLB0_RNG0_MPLB_HIGHADDR" TYPE="std_logic_vector(0 to 31)" VALUE="0xffffffff"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="BRIDGE" MPD_INDEX="77" NAME="C_SPLB0_RNG1_MPLB_BASEADDR" TYPE="std_logic_vector(0 to 31)" VALUE="0xffffffff"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="BRIDGE" MPD_INDEX="78" NAME="C_SPLB0_RNG1_MPLB_HIGHADDR" TYPE="std_logic_vector(0 to 31)" VALUE="0x00000000"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="BRIDGE" MPD_INDEX="79" NAME="C_SPLB0_RNG2_MPLB_BASEADDR" TYPE="std_logic_vector(0 to 31)" VALUE="0xffffffff"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="BRIDGE" MPD_INDEX="80" NAME="C_SPLB0_RNG2_MPLB_HIGHADDR" TYPE="std_logic_vector(0 to 31)" VALUE="0x00000000"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="BRIDGE" MPD_INDEX="81" NAME="C_SPLB0_RNG3_MPLB_BASEADDR" TYPE="std_logic_vector(0 to 31)" VALUE="0xffffffff"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="BRIDGE" MPD_INDEX="82" NAME="C_SPLB0_RNG3_MPLB_HIGHADDR" TYPE="std_logic_vector(0 to 31)" VALUE="0x00000000"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="83" NAME="C_SPLB0_NUM_MASTERS" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Number of Masters</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="84" NAME="C_SPLB0_MID_WIDTH" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Mid Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="85" NAME="C_SPLB0_ALLOW_LOCK_XFER" TYPE="integer" VALUE="1"> + <DESCRIPTION>SPLB Allow Locked Transfer</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="86" NAME="C_SPLB0_READ_PIPE_ENABLE" TYPE="integer" VALUE="1"> + <DESCRIPTION>Enable SPLB Read Pipeline</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="87" NAME="C_SPLB0_PROPAGATE_MIRQ" TYPE="integer" VALUE="0"> + <DESCRIPTION>Propagate MIRQ Signals from Xbar onto SPLB </DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="88" NAME="C_SPLB0_P2P" TYPE="integer" VALUE="0"> + <DESCRIPTION>Use P2P</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="89" NAME="C_SPLB1_AWIDTH" TYPE="integer" VALUE="32"> + <DESCRIPTION>C_SPLB1_AWIDTH</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="90" NAME="C_SPLB1_DWIDTH" TYPE="integer" VALUE="128"> + <DESCRIPTION>C_SPLB1_DWIDTH</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="91" NAME="C_SPLB1_NATIVE_DWIDTH" TYPE="integer" VALUE="128"> + <DESCRIPTION>C_SPLB1_NATIVE_DWIDTH</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="92" NAME="C_SPLB1_SUPPORT_BURSTS" TYPE="integer" VALUE="1"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="93" NAME="C_SPLB1_USE_MPLB_ADDR" TYPE="integer" VALUE="0"> + <DESCRIPTION>Allow SPLB1 to Access MPLB Addr</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="94" NAME="C_SPLB1_NUM_MPLB_ADDR_RNG" TYPE="integer" VALUE="0"> + <DESCRIPTION>Number of MPLB Address Ranges</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="95" NAME="C_SPLB1_RNG_MC_BASEADDR" TYPE="std_logic_vector(0 to 31)" VALUE="0xffffffff"> + <DESCRIPTION>Base Addr </DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="96" NAME="C_SPLB1_RNG_MC_HIGHADDR" TYPE="std_logic_vector(0 to 31)" VALUE="0x00000000"> + <DESCRIPTION>High Addr</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="BRIDGE" MPD_INDEX="97" NAME="C_SPLB1_RNG0_MPLB_BASEADDR" TYPE="std_logic_vector(0 to 31)" VALUE="0xffffffff"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="BRIDGE" MPD_INDEX="98" NAME="C_SPLB1_RNG0_MPLB_HIGHADDR" TYPE="std_logic_vector(0 to 31)" VALUE="0x00000000"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="BRIDGE" MPD_INDEX="99" NAME="C_SPLB1_RNG1_MPLB_BASEADDR" TYPE="std_logic_vector(0 to 31)" VALUE="0xffffffff"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="BRIDGE" MPD_INDEX="100" NAME="C_SPLB1_RNG1_MPLB_HIGHADDR" TYPE="std_logic_vector(0 to 31)" VALUE="0x00000000"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="BRIDGE" MPD_INDEX="101" NAME="C_SPLB1_RNG2_MPLB_BASEADDR" TYPE="std_logic_vector(0 to 31)" VALUE="0xffffffff"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="BRIDGE" MPD_INDEX="102" NAME="C_SPLB1_RNG2_MPLB_HIGHADDR" TYPE="std_logic_vector(0 to 31)" VALUE="0x00000000"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="BRIDGE" MPD_INDEX="103" NAME="C_SPLB1_RNG3_MPLB_BASEADDR" TYPE="std_logic_vector(0 to 31)" VALUE="0xffffffff"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="BRIDGE" MPD_INDEX="104" NAME="C_SPLB1_RNG3_MPLB_HIGHADDR" TYPE="std_logic_vector(0 to 31)" VALUE="0x00000000"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="105" NAME="C_SPLB1_NUM_MASTERS" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Number of Masters</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="106" NAME="C_SPLB1_MID_WIDTH" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Mid Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="107" NAME="C_SPLB1_ALLOW_LOCK_XFER" TYPE="integer" VALUE="1"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="108" NAME="C_SPLB1_READ_PIPE_ENABLE" TYPE="integer" VALUE="1"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="109" NAME="C_SPLB1_PROPAGATE_MIRQ" TYPE="integer" VALUE="0"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="110" NAME="C_SPLB1_P2P" TYPE="integer" VALUE="-1"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="111" NAME="C_NUM_DMA" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Number of DMA Channel</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="112" NAME="C_DMA0_TXCHANNELCTRL" TYPE="BIT_VECTOR(0 to 31)" VALUE="0x01010000"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="113" NAME="C_DMA0_RXCHANNELCTRL" TYPE="BIT_VECTOR(0 to 31)" VALUE="0x01010000"> + <DESCRIPTION> DMA 0 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="114" NAME="C_DMA0_CONTROL" TYPE="BIT_VECTOR(0 to 7)" VALUE="0b00000000"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="115" NAME="C_DMA0_TXIRQTIMER" TYPE="BIT_VECTOR(0 to 9)" VALUE="0b1111111111"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="116" NAME="C_DMA0_RXIRQTIMER" TYPE="BIT_VECTOR(0 to 9)" VALUE="0b1111111111"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="117" NAME="C_DMA1_TXCHANNELCTRL" TYPE="BIT_VECTOR(0 to 31)" VALUE="0x01010000"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="118" NAME="C_DMA1_RXCHANNELCTRL" TYPE="BIT_VECTOR(0 to 31)" VALUE="0x01010000"> + <DESCRIPTION> DMA 1</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="119" NAME="C_DMA1_CONTROL" TYPE="BIT_VECTOR(0 to 7)" VALUE="0b00000000"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="120" NAME="C_DMA1_TXIRQTIMER" TYPE="BIT_VECTOR(0 to 9)" VALUE="0b1111111111"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="121" NAME="C_DMA1_RXIRQTIMER" TYPE="BIT_VECTOR(0 to 9)" VALUE="0b1111111111"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="122" NAME="C_DMA2_TXCHANNELCTRL" TYPE="BIT_VECTOR(0 to 31)" VALUE="0x01010000"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="123" NAME="C_DMA2_RXCHANNELCTRL" TYPE="BIT_VECTOR(0 to 31)" VALUE="0x01010000"> + <DESCRIPTION> DMA 2</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="124" NAME="C_DMA2_CONTROL" TYPE="BIT_VECTOR(0 to 7)" VALUE="0b00000000"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="125" NAME="C_DMA2_TXIRQTIMER" TYPE="BIT_VECTOR(0 to 9)" VALUE="0b1111111111"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="126" NAME="C_DMA2_RXIRQTIMER" TYPE="BIT_VECTOR(0 to 9)" VALUE="0b1111111111"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="127" NAME="C_DMA3_TXCHANNELCTRL" TYPE="BIT_VECTOR(0 to 31)" VALUE="0x01010000"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="128" NAME="C_DMA3_RXCHANNELCTRL" TYPE="BIT_VECTOR(0 to 31)" VALUE="0x01010000"> + <DESCRIPTION> DMA 3</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="129" NAME="C_DMA3_CONTROL" TYPE="BIT_VECTOR(0 to 7)" VALUE="0b00000000"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="130" NAME="C_DMA3_TXIRQTIMER" TYPE="BIT_VECTOR(0 to 9)" VALUE="0b1111111111"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="131" NAME="C_DMA3_RXIRQTIMER" TYPE="BIT_VECTOR(0 to 9)" VALUE="0b1111111111"> + <DESCRIPTION></DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="132" NAME="C_DCR_AUTOLOCK_ENABLE" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Enable the Auto-lock Feature for the DCR Indirect Mode</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="133" NAME="C_PPCDM_ASYNCMODE" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Synchronization Mode for the External MDCR Interface</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="134" NAME="C_PPCDS_ASYNCMODE" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Synchronization Mode for the External SDCR Interface</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="135" NAME="C_GENERATE_PLB_TIMESPECS" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Generate Timing Constraint to Resynchronize SPLB MBusy Outputs</DESCRIPTION> + </PARAMETER> + <MEMORYMAP> + <MEMRANGE BASEDECIMAL="0" BASENAME="C_IDCR_BASEADDR" BASEVALUE="0b0000000000" HIGHDECIMAL="255" HIGHNAME="C_IDCR_HIGHADDR" HIGHVALUE="0b0011111111" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="256" SIZEABRV="256"> + <SLVINTERFACES> + <BUSINTERFACE NAME="SDCR"/> + <BUSINTERFACE NAME="MDCR"/> + </SLVINTERFACES> + </MEMRANGE> + <MEMRANGE BASEDECIMAL="0" BASENAME="C_SPLB0_RNG_MC_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="268435455" HIGHNAME="C_SPLB0_RNG_MC_HIGHADDR" HIGHVALUE="0x0fffffff" MEMTYPE="REGISTER" MINSIZE="0x08000000" SIZE="268435456" SIZEABRV="256M"> + <SLVINTERFACES> + <BUSINTERFACE NAME="SPLB0"/> + </SLVINTERFACES> + </MEMRANGE> + <MEMRANGE BASEDECIMAL="2147483648" BASENAME="C_SPLB0_RNG0_MPLB_BASEADDR" BASEVALUE="0x80000000" HIGHDECIMAL="4294967295" HIGHNAME="C_SPLB0_RNG0_MPLB_HIGHADDR" HIGHVALUE="0xffffffff" MEMTYPE="BRIDGE" MINSIZE="0x08000000" SIZE="-2147483648" SIZEABRV="2G"> + <SLVINTERFACES> + <BUSINTERFACE NAME="SPLB0"/> + </SLVINTERFACES> + </MEMRANGE> + <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SPLB0_RNG1_MPLB_BASEADDR" BASEVALUE="0xffffffff" HIGHDECIMAL="0" HIGHNAME="C_SPLB0_RNG1_MPLB_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="BRIDGE" MINSIZE="0x08000000" SIZE="0" SIZEABRV="U"> + <SLVINTERFACES> + <BUSINTERFACE NAME="SPLB0"/> + </SLVINTERFACES> + </MEMRANGE> + <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SPLB0_RNG2_MPLB_BASEADDR" BASEVALUE="0xffffffff" HIGHDECIMAL="0" HIGHNAME="C_SPLB0_RNG2_MPLB_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="BRIDGE" MINSIZE="0x08000000" SIZE="0" SIZEABRV="U"> + <SLVINTERFACES> + <BUSINTERFACE NAME="SPLB0"/> + </SLVINTERFACES> + </MEMRANGE> + <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SPLB0_RNG3_MPLB_BASEADDR" BASEVALUE="0xffffffff" HIGHDECIMAL="0" HIGHNAME="C_SPLB0_RNG3_MPLB_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="BRIDGE" MINSIZE="0x08000000" SIZE="0" SIZEABRV="U"> + <SLVINTERFACES> + <BUSINTERFACE NAME="SPLB0"/> + </SLVINTERFACES> + </MEMRANGE> + <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SPLB1_RNG_MC_BASEADDR" BASEVALUE="0xffffffff" HIGHDECIMAL="0" HIGHNAME="C_SPLB1_RNG_MC_HIGHADDR" HIGHVALUE="0x00000000" MEMTYPE="REGISTER" MINSIZE="0x08000000" SIZE="0" SIZEABRV="U"> + <SLVINTERFACES> + <BUSINTERFACE NAME="SPLB1"/> + </SLVINTERFACES> + </MEMRANGE> + <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SPLB1_RNG0_MPLB_BASEADDR" BASEVALUE="0xffffffff" HIGHDECIMAL="0" HIGHNAME="C_SPLB1_RNG0_MPLB_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="BRIDGE" MINSIZE="0x08000000" SIZE="0" SIZEABRV="U"> + <SLVINTERFACES> + <BUSINTERFACE NAME="SPLB1"/> + </SLVINTERFACES> + </MEMRANGE> + <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SPLB1_RNG1_MPLB_BASEADDR" BASEVALUE="0xffffffff" HIGHDECIMAL="0" HIGHNAME="C_SPLB1_RNG1_MPLB_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="BRIDGE" MINSIZE="0x08000000" SIZE="0" SIZEABRV="U"> + <SLVINTERFACES> + <BUSINTERFACE NAME="SPLB1"/> + </SLVINTERFACES> + </MEMRANGE> + <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SPLB1_RNG2_MPLB_BASEADDR" BASEVALUE="0xffffffff" HIGHDECIMAL="0" HIGHNAME="C_SPLB1_RNG2_MPLB_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="BRIDGE" MINSIZE="0x08000000" SIZE="0" SIZEABRV="U"> + <SLVINTERFACES> + <BUSINTERFACE NAME="SPLB1"/> + </SLVINTERFACES> + </MEMRANGE> + <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SPLB1_RNG3_MPLB_BASEADDR" BASEVALUE="0xffffffff" HIGHDECIMAL="0" HIGHNAME="C_SPLB1_RNG3_MPLB_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="BRIDGE" MINSIZE="0x08000000" SIZE="0" SIZEABRV="U"> + <SLVINTERFACES> + <BUSINTERFACE NAME="SPLB1"/> + </SLVINTERFACES> + </MEMRANGE> + <MEMRANGE BASEDECIMAL="4294959104" BASENAME="C_BASEADDR" BASEVALUE="0xffffe000" HIGHDECIMAL="4294967295" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xffffffff" INSTANCE="xps_bram_if_cntlr_1" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="8192" SIZEABRV="8K"> + <ACCESSROUTE> + <ROUTEPNT INDEX="0" INSTANCE="plb_v46_0"/> + </ACCESSROUTE> + </MEMRANGE> + <MEMRANGE BASEDECIMAL="2214592512" BASENAME="C_BASEADDR" BASEVALUE="0x84000000" HIGHDECIMAL="2214658047" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8400ffff" INSTANCE="RS232_Uart_1" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K"> + <ACCESSROUTE> + <ROUTEPNT INDEX="0" INSTANCE="plb_v46_0"/> + </ACCESSROUTE> + </MEMRANGE> + <MEMRANGE BASEDECIMAL="2168717312" BASENAME="C_BASEADDR" BASEVALUE="0x81440000" HIGHDECIMAL="2168782847" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8144ffff" INSTANCE="LEDs_8Bit" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K"> + <ACCESSROUTE> + <ROUTEPNT INDEX="0" INSTANCE="plb_v46_0"/> + </ACCESSROUTE> + </MEMRANGE> + <MEMRANGE BASEDECIMAL="2168586240" BASENAME="C_BASEADDR" BASEVALUE="0x81420000" HIGHDECIMAL="2168651775" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8142ffff" INSTANCE="LEDs_Positions" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K"> + <ACCESSROUTE> + <ROUTEPNT INDEX="0" INSTANCE="plb_v46_0"/> + </ACCESSROUTE> + </MEMRANGE> + <MEMRANGE BASEDECIMAL="2168455168" BASENAME="C_BASEADDR" BASEVALUE="0x81400000" HIGHDECIMAL="2168520703" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8140ffff" INSTANCE="Push_Buttons_5Bit" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K"> + <ACCESSROUTE> + <ROUTEPNT INDEX="0" INSTANCE="plb_v46_0"/> + </ACCESSROUTE> + </MEMRANGE> + <MEMRANGE BASEDECIMAL="2168848384" BASENAME="C_BASEADDR" BASEVALUE="0x81460000" HIGHDECIMAL="2168913919" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8146ffff" INSTANCE="DIP_Switches_8Bit" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K"> + <ACCESSROUTE> + <ROUTEPNT INDEX="0" INSTANCE="plb_v46_0"/> + </ACCESSROUTE> + </MEMRANGE> + <MEMRANGE BASEDECIMAL="2170552320" BASENAME="C_BASEADDR" BASEVALUE="0x81600000" HIGHDECIMAL="2170617855" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8160ffff" INSTANCE="IIC_EEPROM" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K"> + <ACCESSROUTE> + <ROUTEPNT INDEX="0" INSTANCE="plb_v46_0"/> + </ACCESSROUTE> + </MEMRANGE> + <MEMRANGE BASEDECIMAL="4160749568" BASENAME="C_MEM0_BASEADDR" BASEVALUE="0xf8000000" HIGHDECIMAL="4161798143" HIGHNAME="C_MEM0_HIGHADDR" HIGHVALUE="0xf80fffff" INSTANCE="SRAM" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="1048576" SIZEABRV="1M"> + <ACCESSROUTE> + <ROUTEPNT INDEX="0" INSTANCE="plb_v46_0"/> + </ACCESSROUTE> + </MEMRANGE> + <MEMRANGE BASEDECIMAL="2243952640" BASENAME="C_BASEADDR" BASEVALUE="0x85c00000" HIGHDECIMAL="2244018175" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x85c0ffff" INSTANCE="PCIe_Bridge" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K"> + <ACCESSROUTE> + <ROUTEPNT INDEX="0" INSTANCE="plb_v46_0"/> + </ACCESSROUTE> + </MEMRANGE> + <MEMRANGE BASEDECIMAL="3221225472" BASENAME="C_IPIFBAR_0" BASEVALUE="0xc0000000" HIGHDECIMAL="3758096383" HIGHNAME="C_IPIFBAR_HIGHADDR_0" HIGHVALUE="0xdfffffff" INSTANCE="PCIe_Bridge" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="BRIDGE" SIZE="536870912" SIZEABRV="512M"> + <ACCESSROUTE> + <ROUTEPNT INDEX="0" INSTANCE="plb_v46_0"/> + </ACCESSROUTE> + </MEMRANGE> + <MEMRANGE BASEDECIMAL="3758096384" BASENAME="C_IPIFBAR_1" BASEVALUE="0xe0000000" HIGHDECIMAL="4026531839" HIGHNAME="C_IPIFBAR_HIGHADDR_1" HIGHVALUE="0xefffffff" INSTANCE="PCIe_Bridge" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="BRIDGE" SIZE="268435456" SIZEABRV="256M"> + <ACCESSROUTE> + <ROUTEPNT INDEX="0" INSTANCE="plb_v46_0"/> + </ACCESSROUTE> + </MEMRANGE> + <MEMRANGE BASEDECIMAL="2164260864" BASENAME="C_BASEADDR" BASEVALUE="0x81000000" HIGHDECIMAL="2164326399" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8100ffff" INSTANCE="Ethernet_MAC" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K"> + <ACCESSROUTE> + <ROUTEPNT INDEX="0" INSTANCE="plb_v46_0"/> + </ACCESSROUTE> + </MEMRANGE> + <MEMRANGE BASEDECIMAL="2204106752" BASENAME="C_BASEADDR" BASEVALUE="0x83600000" HIGHDECIMAL="2204172287" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8360ffff" INSTANCE="SysACE_CompactFlash" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K"> + <ACCESSROUTE> + <ROUTEPNT INDEX="0" INSTANCE="plb_v46_0"/> + </ACCESSROUTE> + </MEMRANGE> + <MEMRANGE BASEDECIMAL="2172649472" BASENAME="C_BASEADDR" BASEVALUE="0x81800000" HIGHDECIMAL="2172715007" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8180ffff" INSTANCE="xps_intc_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K"> + <ACCESSROUTE> + <ROUTEPNT INDEX="0" INSTANCE="plb_v46_0"/> + </ACCESSROUTE> + </MEMRANGE> + <MEMRANGE BASEDECIMAL="0" BASENAME="C_MEM_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="268435455" HIGHNAME="C_MEM_HIGHADDR" HIGHVALUE="0x0fffffff" INSTANCE="DDR2_SDRAM" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="268435456" SIZEABRV="256M"> + <ACCESSROUTE> + <ROUTEPNT INDEX="0" INSTANCE="ppc440_0_PPC440MC"/> + </ACCESSROUTE> + </MEMRANGE> + </MEMORYMAP> + <PORT CLKFREQUENCY="125000000" DIR="I" IS_INMHS="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="CPMC440CLK" SIGIS="CLK" SIGNAME="clk_125_0000MHzPLL0"/> + <PORT CLKFREQUENCY="125000000" DIR="I" IS_INMHS="TRUE" MHS_INDEX="1" MPD_INDEX="2" NAME="CPMINTERCONNECTCLK" SIGIS="CLK" SIGNAME="clk_125_0000MHzPLL0"/> + <PORT DIR="I" IS_INMHS="TRUE" MHS_INDEX="2" MPD_INDEX="4" NAME="CPMINTERCONNECTCLKNTO1" SIGNAME="net_vcc"/> + <PORT DIR="I" IS_INMHS="TRUE" MHS_INDEX="3" MPD_INDEX="24" NAME="EICC440EXTIRQ" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="ppc440_0_EICC440EXTIRQ"/> + <PORT CLKFREQUENCY="125000000" DIR="I" IS_INMHS="TRUE" MHS_INDEX="4" MPD_INDEX="78" NAME="CPMMCCLK" SIGIS="CLK" SIGNAME="clk_125_0000MHzPLL0_ADJUST"/> + <PORT BUS="MPLB" CLKFREQUENCY="125000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INMHS="TRUE" MHS_INDEX="5" MPD_INDEX="91" NAME="CPMPPCMPLBCLK" SIGIS="CLK" SIGNAME="clk_125_0000MHzPLL0_ADJUST"/> + <PORT BUS="SPLB0" CLKFREQUENCY="125000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INMHS="TRUE" MHS_INDEX="6" MPD_INDEX="127" NAME="CPMPPCS0PLBCLK" SIGIS="CLK" SIGNAME="clk_125_0000MHzPLL0_ADJUST"/> + <PORT DIR="I" MPD_INDEX="1" NAME="CPMC440CLKEN" SIGNAME="__NOC__"/> + <PORT DIR="I" MPD_INDEX="3" NAME="CPMINTERCONNECTCLKEN" SIGNAME="__NOC__"/> + <PORT DIR="I" MPD_INDEX="5" NAME="CPMC440CORECLOCKINACTIVE" SIGNAME="__NOC__"/> + <PORT DIR="I" MPD_INDEX="6" NAME="CPMC440TIMERCLOCK" SIGIS="CLK" SIGNAME="__NOC__"/> + <PORT DIR="O" MPD_INDEX="7" NAME="C440MACHINECHECK" SIGNAME="__NOC__"/> + <PORT DIR="O" MPD_INDEX="8" NAME="C440CPMCORESLEEPREQ" SIGNAME="__NOC__"/> + <PORT DIR="O" MPD_INDEX="9" NAME="C440CPMDECIRPTREQ" SIGNAME="__NOC__"/> + <PORT DIR="O" MPD_INDEX="10" NAME="C440CPMFITIRPTREQ" SIGNAME="__NOC__"/> + <PORT DIR="O" MPD_INDEX="11" NAME="C440CPMMSRCE" SIGNAME="__NOC__"/> + <PORT DIR="O" MPD_INDEX="12" NAME="C440CPMMSREE" SIGNAME="__NOC__"/> + <PORT DIR="O" MPD_INDEX="13" NAME="C440CPMTIMERRESETREQ" SIGNAME="__NOC__"/> + <PORT DIR="O" MPD_INDEX="14" NAME="C440CPMWDIRPTREQ" SIGNAME="__NOC__"/> + <PORT DIR="O" MPD_INDEX="15" NAME="PPCCPMINTERCONNECTBUSY" SIGNAME="__NOC__"/> + <PORT DIR="I" MPD_INDEX="16" NAME="DBGC440DEBUGHALT" SIGNAME="__NOC__"> + <DESCRIPTION>JTAG HALT</DESCRIPTION> + </PORT> + <PORT DIR="I" MPD_INDEX="17" NAME="DBGC440DEBUGHALTNEG" SIGNAME="__NOC__"> + <DESCRIPTION>JTAG HALT INV</DESCRIPTION> + </PORT> + <PORT DIR="I" MPD_INDEX="18" NAME="DBGC440SYSTEMSTATUS" SIGNAME="__NOC__" VECFORMULA="[0:4]"/> + <PORT DIR="I" MPD_INDEX="19" NAME="DBGC440UNCONDDEBUGEVENT" SIGNAME="__NOC__"/> + <PORT DIR="O" MPD_INDEX="20" NAME="C440DBGSYSTEMCONTROL" SIGNAME="__NOC__" VECFORMULA="[0:7]"/> + <PORT DIR="O" MPD_INDEX="21" NAME="SPLB0_Error" SIGNAME="__NOC__" VECFORMULA="[0:3]"/> + <PORT DIR="O" MPD_INDEX="22" NAME="SPLB1_Error" SIGNAME="__NOC__" VECFORMULA="[0:3]"/> + <PORT DIR="I" MPD_INDEX="23" NAME="EICC440CRITIRQ" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/> + <PORT DIR="O" MPD_INDEX="25" NAME="PPCEICINTERCONNECTIRQ" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/> + <PORT DIR="I" MPD_INDEX="26" NAME="CPMDCRCLK" SIGIS="CLK" SIGNAME="__NOC__"/> + <PORT BUS="MDCR" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="27" NAME="DCRPPCDMACK" SIGNAME="__NOC__"/> + <PORT BUS="MDCR" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="28" NAME="DCRPPCDMDBUSIN" SIGNAME="__NOC__" VECFORMULA="[0:31]"/> + <PORT BUS="MDCR" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="29" NAME="DCRPPCDMTIMEOUTWAIT" SIGNAME="__NOC__"/> + <PORT BUS="MDCR" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="30" NAME="PPCDMDCRREAD" SIGNAME="__NOC__"/> + <PORT BUS="MDCR" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="31" NAME="PPCDMDCRWRITE" SIGNAME="__NOC__"/> + <PORT BUS="MDCR" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="32" NAME="PPCDMDCRABUS" SIGNAME="__NOC__" VECFORMULA="[0:9]"/> + <PORT BUS="MDCR" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="33" NAME="PPCDMDCRDBUSOUT" SIGNAME="__NOC__" VECFORMULA="[0:31]"/> + <PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="34" NAME="DCRPPCDSREAD" SIGNAME="__NOC__"/> + <PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="35" NAME="DCRPPCDSWRITE" SIGNAME="__NOC__"/> + <PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="36" NAME="DCRPPCDSABUS" SIGNAME="__NOC__" VECFORMULA="[0:9]"/> + <PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="37" NAME="DCRPPCDSDBUSOUT" SIGNAME="__NOC__" VECFORMULA="[0:31]"/> + <PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="38" NAME="PPCDSDCRACK" SIGNAME="__NOC__"/> + <PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="39" NAME="PPCDSDCRDBUSIN" SIGNAME="__NOC__" VECFORMULA="[0:31]"/> + <PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="40" NAME="PPCDSDCRTIMEOUTWAIT" SIGNAME="__NOC__"/> + <PORT BUS="MFCB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="41" NAME="CPMFCMCLK" SIGIS="CLK" SIGNAME="__NOC__"/> + <PORT BUS="MFCM:MFCB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="42" NAME="FCMAPUCR" SIGNAME="__NOC__" VECFORMULA="[0:3]"/> + <PORT BUS="MFCM:MFCB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="43" NAME="FCMAPUDONE" SIGNAME="__NOC__"/> + <PORT BUS="MFCM:MFCB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="FCMAPUEXCEPTION" SIGNAME="__NOC__"/> + <PORT BUS="MFCM:MFCB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="45" NAME="FCMAPUFPSCRFEX" SIGNAME="__NOC__"/> + <PORT BUS="MFCM:MFCB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="46" NAME="FCMAPURESULT" SIGNAME="__NOC__" VECFORMULA="[0:31]"/> + <PORT BUS="MFCM:MFCB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="47" NAME="FCMAPURESULTVALID" SIGNAME="__NOC__"/> + <PORT BUS="MFCM:MFCB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="48" NAME="FCMAPUSLEEPNOTREADY" SIGNAME="__NOC__"/> + <PORT BUS="MFCM:MFCB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="49" NAME="FCMAPUCONFIRMINSTR" SIGNAME="__NOC__"/> + <PORT BUS="MFCM:MFCB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="50" NAME="FCMAPUSTOREDATA" SIGNAME="__NOC__" VECFORMULA="[0:127]"/> + <PORT BUS="MFCM:MFCB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="51" NAME="APUFCMDECNONAUTON" SIGNAME="__NOC__"/> + <PORT BUS="MFCM:MFCB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="52" NAME="APUFCMDECFPUOP" SIGNAME="__NOC__"/> + <PORT BUS="MFCM:MFCB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="53" NAME="APUFCMDECLDSTXFERSIZE" SIGNAME="__NOC__" VECFORMULA="[0:2]"/> + <PORT BUS="MFCM:MFCB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="54" NAME="APUFCMDECLOAD" SIGNAME="__NOC__"/> + <PORT BUS="MFCM:MFCB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="55" NAME="APUFCMNEXTINSTRREADY" SIGNAME="__NOC__"/> + <PORT BUS="MFCM:MFCB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="56" NAME="APUFCMDECSTORE" SIGNAME="__NOC__"/> + <PORT BUS="MFCM:MFCB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="57" NAME="APUFCMDECUDI" SIGNAME="__NOC__" VECFORMULA="[0:3]"/> + <PORT BUS="MFCM:MFCB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="58" NAME="APUFCMDECUDIVALID" SIGNAME="__NOC__"/> + <PORT BUS="MFCM:MFCB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="59" NAME="APUFCMENDIAN" SIGNAME="__NOC__"/> + <PORT BUS="MFCM:MFCB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="60" NAME="APUFCMFLUSH" SIGNAME="__NOC__"/> + <PORT BUS="MFCM:MFCB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="61" NAME="APUFCMINSTRUCTION" SIGNAME="__NOC__" VECFORMULA="[0:31]"/> + <PORT BUS="MFCM:MFCB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="62" NAME="APUFCMINSTRVALID" SIGNAME="__NOC__"/> + <PORT BUS="MFCM:MFCB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="63" NAME="APUFCMLOADBYTEADDR" SIGNAME="__NOC__" VECFORMULA="[0:3]"/> + <PORT BUS="MFCM:MFCB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="64" NAME="APUFCMLOADDATA" SIGNAME="__NOC__" VECFORMULA="[0:127]"/> + <PORT BUS="MFCM:MFCB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="65" NAME="APUFCMLOADDVALID" SIGNAME="__NOC__"/> + <PORT BUS="MFCM:MFCB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="66" NAME="APUFCMOPERANDVALID" SIGNAME="__NOC__"/> + <PORT BUS="MFCM:MFCB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="67" NAME="APUFCMRADATA" SIGNAME="__NOC__" VECFORMULA="[0:31]"/> + <PORT BUS="MFCM:MFCB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="68" NAME="APUFCMRBDATA" SIGNAME="__NOC__" VECFORMULA="[0:31]"/> + <PORT BUS="MFCM:MFCB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="69" NAME="APUFCMWRITEBACKOK" SIGNAME="__NOC__"/> + <PORT BUS="MFCM:MFCB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="70" NAME="APUFCMMSRFE0" SIGNAME="__NOC__"/> + <PORT BUS="MFCM:MFCB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="71" NAME="APUFCMMSRFE1" SIGNAME="__NOC__"/> + <PORT BUS="JTAGPPC" DEF_SIGNAME="ppc440_0_jtagppc_bus_JTGC405TCK" DIR="I" MPD_INDEX="72" NAME="JTGC440TCK" SIGNAME="ppc440_0_jtagppc_bus_JTGC405TCK"> + <DESCRIPTION>JTAG TCK</DESCRIPTION> + </PORT> + <PORT BUS="JTAGPPC" DEF_SIGNAME="ppc440_0_jtagppc_bus_JTGC405TDI" DIR="I" MPD_INDEX="73" NAME="JTGC440TDI" SIGNAME="ppc440_0_jtagppc_bus_JTGC405TDI"> + <DESCRIPTION>JTAG TDI</DESCRIPTION> + </PORT> + <PORT BUS="JTAGPPC" DEF_SIGNAME="ppc440_0_jtagppc_bus_JTGC405TMS" DIR="I" MPD_INDEX="74" NAME="JTGC440TMS" SIGNAME="ppc440_0_jtagppc_bus_JTGC405TMS"> + <DESCRIPTION>JTAG TMS</DESCRIPTION> + </PORT> + <PORT BUS="JTAGPPC" DEF_SIGNAME="ppc440_0_jtagppc_bus_JTGC405TRSTNEG" DIR="I" MPD_INDEX="75" NAME="JTGC440TRSTNEG" SIGNAME="ppc440_0_jtagppc_bus_JTGC405TRSTNEG"> + <DESCRIPTION>JTAG TRST</DESCRIPTION> + </PORT> + <PORT BUS="JTAGPPC" DEF_SIGNAME="ppc440_0_jtagppc_bus_C405JTGTDO" DIR="O" MPD_INDEX="76" NAME="C440JTGTDO" SIGNAME="ppc440_0_jtagppc_bus_C405JTGTDO"> + <DESCRIPTION>JTAG TDO</DESCRIPTION> + </PORT> + <PORT BUS="JTAGPPC" DEF_SIGNAME="ppc440_0_jtagppc_bus_C405JTGTDOEN" DIR="O" MPD_INDEX="77" NAME="C440JTGTDOEN" SIGNAME="ppc440_0_jtagppc_bus_C405JTGTDOEN"/> + <PORT BUS="PPC440MC" DEF_SIGNAME="ppc440_0_PPC440MC_MCMIREADDATA" DIR="I" MPD_INDEX="79" NAME="MCMIREADDATA" SIGNAME="ppc440_0_PPC440MC_MCMIREADDATA" VECFORMULA="[0:127]"/> + <PORT BUS="PPC440MC" DEF_SIGNAME="ppc440_0_PPC440MC_MCMIREADDATAVALID" DIR="I" MPD_INDEX="80" NAME="MCMIREADDATAVALID" SIGNAME="ppc440_0_PPC440MC_MCMIREADDATAVALID"/> + <PORT BUS="PPC440MC" DEF_SIGNAME="ppc440_0_PPC440MC_MCMIREADDATAERR" DIR="I" MPD_INDEX="81" NAME="MCMIREADDATAERR" SIGNAME="ppc440_0_PPC440MC_MCMIREADDATAERR"/> + <PORT BUS="PPC440MC" DEF_SIGNAME="ppc440_0_PPC440MC_MCMIADDRREADYTOACCEPT" DIR="I" MPD_INDEX="82" NAME="MCMIADDRREADYTOACCEPT" SIGNAME="ppc440_0_PPC440MC_MCMIADDRREADYTOACCEPT"/> + <PORT BUS="PPC440MC" DEF_SIGNAME="ppc440_0_PPC440MC_MIMCREADNOTWRITE" DIR="O" MPD_INDEX="83" NAME="MIMCREADNOTWRITE" SIGNAME="ppc440_0_PPC440MC_MIMCREADNOTWRITE"/> + <PORT BUS="PPC440MC" DEF_SIGNAME="ppc440_0_PPC440MC_MIMCADDRESS" DIR="O" MPD_INDEX="84" NAME="MIMCADDRESS" SIGNAME="ppc440_0_PPC440MC_MIMCADDRESS" VECFORMULA="[0:35]"/> + <PORT BUS="PPC440MC" DEF_SIGNAME="ppc440_0_PPC440MC_MIMCADDRESSVALID" DIR="O" MPD_INDEX="85" NAME="MIMCADDRESSVALID" SIGNAME="ppc440_0_PPC440MC_MIMCADDRESSVALID"/> + <PORT BUS="PPC440MC" DEF_SIGNAME="ppc440_0_PPC440MC_MIMCWRITEDATA" DIR="O" MPD_INDEX="86" NAME="MIMCWRITEDATA" SIGNAME="ppc440_0_PPC440MC_MIMCWRITEDATA" VECFORMULA="[0:127]"/> + <PORT BUS="PPC440MC" DEF_SIGNAME="ppc440_0_PPC440MC_MIMCWRITEDATAVALID" DIR="O" MPD_INDEX="87" NAME="MIMCWRITEDATAVALID" SIGNAME="ppc440_0_PPC440MC_MIMCWRITEDATAVALID"/> + <PORT BUS="PPC440MC" DEF_SIGNAME="ppc440_0_PPC440MC_MIMCBYTEENABLE" DIR="O" MPD_INDEX="88" NAME="MIMCBYTEENABLE" SIGNAME="ppc440_0_PPC440MC_MIMCBYTEENABLE" VECFORMULA="[0:15]"/> + <PORT BUS="PPC440MC" DEF_SIGNAME="ppc440_0_PPC440MC_MIMCBANKCONFLICT" DIR="O" MPD_INDEX="89" NAME="MIMCBANKCONFLICT" SIGNAME="ppc440_0_PPC440MC_MIMCBANKCONFLICT"/> + <PORT BUS="PPC440MC" DEF_SIGNAME="ppc440_0_PPC440MC_MIMCROWCONFLICT" DIR="O" MPD_INDEX="90" NAME="MIMCROWCONFLICT" SIGNAME="ppc440_0_PPC440MC_MIMCROWCONFLICT"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_PLB_MBusy" DIR="I" MPD_INDEX="92" NAME="PLBPPCMMBUSY" SIGNAME="plb_v46_0_PLB_MBusy"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_PLB_MIRQ" DIR="I" MPD_INDEX="93" NAME="PLBPPCMMIRQ" SIGNAME="plb_v46_0_PLB_MIRQ"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_PLB_MRdErr" DIR="I" MPD_INDEX="94" NAME="PLBPPCMMRDERR" SIGNAME="plb_v46_0_PLB_MRdErr"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_PLB_MWrErr" DIR="I" MPD_INDEX="95" NAME="PLBPPCMMWRERR" SIGNAME="plb_v46_0_PLB_MWrErr"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_PLB_MAddrAck" DIR="I" MPD_INDEX="96" NAME="PLBPPCMADDRACK" SIGNAME="plb_v46_0_PLB_MAddrAck"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_PLB_MRdBTerm" DIR="I" MPD_INDEX="97" NAME="PLBPPCMRDBTERM" SIGNAME="plb_v46_0_PLB_MRdBTerm"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_PLB_MRdDAck" DIR="I" MPD_INDEX="98" NAME="PLBPPCMRDDACK" SIGNAME="plb_v46_0_PLB_MRdDAck"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_PLB_MRdDBus" DIR="I" MPD_INDEX="99" NAME="PLBPPCMRDDBUS" SIGNAME="plb_v46_0_PLB_MRdDBus" VECFORMULA="[0:127]"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_PLB_MRdWdAddr" DIR="I" MPD_INDEX="100" NAME="PLBPPCMRDWDADDR" SIGNAME="plb_v46_0_PLB_MRdWdAddr" VECFORMULA="[0:3]"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_PLB_MRearbitrate" DIR="I" MPD_INDEX="101" NAME="PLBPPCMREARBITRATE" SIGNAME="plb_v46_0_PLB_MRearbitrate"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_PLB_MSSize" DIR="I" MPD_INDEX="102" NAME="PLBPPCMSSIZE" SIGNAME="plb_v46_0_PLB_MSSize" VECFORMULA="[0:1]"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_PLB_MTimeout" DIR="I" MPD_INDEX="103" NAME="PLBPPCMTIMEOUT" SIGNAME="plb_v46_0_PLB_MTimeout"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_PLB_MWrBTerm" DIR="I" MPD_INDEX="104" NAME="PLBPPCMWRBTERM" SIGNAME="plb_v46_0_PLB_MWrBTerm"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_PLB_MWrDAck" DIR="I" MPD_INDEX="105" NAME="PLBPPCMWRDACK" SIGNAME="plb_v46_0_PLB_MWrDAck"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPendPri" DIR="I" MPD_INDEX="106" NAME="PLBPPCMRDPENDPRI" SIGNAME="plb_v46_0_PLB_rdPendPri" VECFORMULA="[0:1]"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPendReq" DIR="I" MPD_INDEX="107" NAME="PLBPPCMRDPENDREQ" SIGNAME="plb_v46_0_PLB_rdPendReq"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_PLB_reqPri" DIR="I" MPD_INDEX="108" NAME="PLBPPCMREQPRI" SIGNAME="plb_v46_0_PLB_reqPri" VECFORMULA="[0:1]"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPendPri" DIR="I" MPD_INDEX="109" NAME="PLBPPCMWRPENDPRI" SIGNAME="plb_v46_0_PLB_wrPendPri" VECFORMULA="[0:1]"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPendReq" DIR="I" MPD_INDEX="110" NAME="PLBPPCMWRPENDREQ" SIGNAME="plb_v46_0_PLB_wrPendReq"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_M_abort" DIR="O" MPD_INDEX="111" NAME="PPCMPLBABORT" SIGNAME="plb_v46_0_M_abort"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_M_ABus" DIR="O" MPD_INDEX="112" NAME="PPCMPLBABUS" SIGNAME="plb_v46_0_M_ABus" VECFORMULA="[0:31]"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_M_BE" DIR="O" MPD_INDEX="113" NAME="PPCMPLBBE" SIGNAME="plb_v46_0_M_BE" VECFORMULA="[0:15]"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_M_busLock" DIR="O" MPD_INDEX="114" NAME="PPCMPLBBUSLOCK" SIGNAME="plb_v46_0_M_busLock"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_M_lockErr" DIR="O" MPD_INDEX="115" NAME="PPCMPLBLOCKERR" SIGNAME="plb_v46_0_M_lockErr"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_M_MSize" DIR="O" MPD_INDEX="116" NAME="PPCMPLBMSIZE" SIGNAME="plb_v46_0_M_MSize" VECFORMULA="[0:1]"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_M_priority" DIR="O" MPD_INDEX="117" NAME="PPCMPLBPRIORITY" SIGNAME="plb_v46_0_M_priority" VECFORMULA="[0:1]"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_M_rdBurst" DIR="O" MPD_INDEX="118" NAME="PPCMPLBRDBURST" SIGNAME="plb_v46_0_M_rdBurst"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_M_request" DIR="O" MPD_INDEX="119" NAME="PPCMPLBREQUEST" SIGNAME="plb_v46_0_M_request"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_M_RNW" DIR="O" MPD_INDEX="120" NAME="PPCMPLBRNW" SIGNAME="plb_v46_0_M_RNW"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_M_size" DIR="O" MPD_INDEX="121" NAME="PPCMPLBSIZE" SIGNAME="plb_v46_0_M_size" VECFORMULA="[0:3]"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_M_TAttribute" DIR="O" MPD_INDEX="122" NAME="PPCMPLBTATTRIBUTE" SIGNAME="plb_v46_0_M_TAttribute" VECFORMULA="[0:15]"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_M_type" DIR="O" MPD_INDEX="123" NAME="PPCMPLBTYPE" SIGNAME="plb_v46_0_M_type" VECFORMULA="[0:2]"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_M_UABus" DIR="O" MPD_INDEX="124" NAME="PPCMPLBUABUS" SIGNAME="plb_v46_0_M_UABus" VECFORMULA="[0:31]"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_M_wrBurst" DIR="O" MPD_INDEX="125" NAME="PPCMPLBWRBURST" SIGNAME="plb_v46_0_M_wrBurst"/> + <PORT BUS="MPLB" DEF_SIGNAME="plb_v46_0_M_wrDBus" DIR="O" MPD_INDEX="126" NAME="PPCMPLBWRDBUS" SIGNAME="plb_v46_0_M_wrDBus" VECFORMULA="[0:127]"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_PLB_masterID" DIR="I" MPD_INDEX="128" NAME="PLBPPCS0MASTERID" SIGNAME="ppc440_0_SPLB0_PLB_masterID" VECFORMULA="[0:(C_SPLB0_MID_WIDTH-1)]"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_PLB_PAValid" DIR="I" MPD_INDEX="129" NAME="PLBPPCS0PAVALID" SIGNAME="ppc440_0_SPLB0_PLB_PAValid"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_PLB_SAValid" DIR="I" MPD_INDEX="130" NAME="PLBPPCS0SAVALID" SIGNAME="ppc440_0_SPLB0_PLB_SAValid"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_PLB_rdPendReq" DIR="I" MPD_INDEX="131" NAME="PLBPPCS0RDPENDREQ" SIGNAME="ppc440_0_SPLB0_PLB_rdPendReq"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_PLB_wrPendReq" DIR="I" MPD_INDEX="132" NAME="PLBPPCS0WRPENDREQ" SIGNAME="ppc440_0_SPLB0_PLB_wrPendReq"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_PLB_rdPendPri" DIR="I" MPD_INDEX="133" NAME="PLBPPCS0RDPENDPRI" SIGNAME="ppc440_0_SPLB0_PLB_rdPendPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_PLB_wrPendPri" DIR="I" MPD_INDEX="134" NAME="PLBPPCS0WRPENDPRI" SIGNAME="ppc440_0_SPLB0_PLB_wrPendPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_PLB_reqPri" DIR="I" MPD_INDEX="135" NAME="PLBPPCS0REQPRI" SIGNAME="ppc440_0_SPLB0_PLB_reqPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_PLB_rdPrim" DIR="I" MPD_INDEX="136" NAME="PLBPPCS0RDPRIM" SIGNAME="ppc440_0_SPLB0_PLB_rdPrim"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_PLB_wrPrim" DIR="I" MPD_INDEX="137" NAME="PLBPPCS0WRPRIM" SIGNAME="ppc440_0_SPLB0_PLB_wrPrim"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_PLB_busLock" DIR="I" MPD_INDEX="138" NAME="PLBPPCS0BUSLOCK" SIGNAME="ppc440_0_SPLB0_PLB_busLock"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_PLB_abort" DIR="I" MPD_INDEX="139" NAME="PLBPPCS0ABORT" SIGNAME="ppc440_0_SPLB0_PLB_abort"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_PLB_RNW" DIR="I" MPD_INDEX="140" NAME="PLBPPCS0RNW" SIGNAME="ppc440_0_SPLB0_PLB_RNW"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_PLB_BE" DIR="I" MPD_INDEX="141" NAME="PLBPPCS0BE" SIGNAME="ppc440_0_SPLB0_PLB_BE" VECFORMULA="[0:15]"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_PLB_size" DIR="I" MPD_INDEX="142" NAME="PLBPPCS0SIZE" SIGNAME="ppc440_0_SPLB0_PLB_size" VECFORMULA="[0:3]"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_PLB_type" DIR="I" MPD_INDEX="143" NAME="PLBPPCS0TYPE" SIGNAME="ppc440_0_SPLB0_PLB_type" VECFORMULA="[0:2]"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_PLB_TAttribute" DIR="I" MPD_INDEX="144" NAME="PLBPPCS0TATTRIBUTE" SIGNAME="ppc440_0_SPLB0_PLB_TAttribute" VECFORMULA="[0:15]"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_PLB_lockErr" DIR="I" MPD_INDEX="145" NAME="PLBPPCS0LOCKERR" SIGNAME="ppc440_0_SPLB0_PLB_lockErr"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_PLB_MSize" DIR="I" MPD_INDEX="146" NAME="PLBPPCS0MSIZE" SIGNAME="ppc440_0_SPLB0_PLB_MSize" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_PLB_UABus" DIR="I" MPD_INDEX="147" NAME="PLBPPCS0UABUS" SIGNAME="ppc440_0_SPLB0_PLB_UABus" VECFORMULA="[0:31]"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_PLB_ABus" DIR="I" MPD_INDEX="148" NAME="PLBPPCS0ABUS" SIGNAME="ppc440_0_SPLB0_PLB_ABus" VECFORMULA="[0:31]"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_PLB_wrDBus" DIR="I" MPD_INDEX="149" NAME="PLBPPCS0WRDBUS" SIGNAME="ppc440_0_SPLB0_PLB_wrDBus" VECFORMULA="[0:127]"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_PLB_wrBurst" DIR="I" MPD_INDEX="150" NAME="PLBPPCS0WRBURST" SIGNAME="ppc440_0_SPLB0_PLB_wrBurst"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_PLB_rdBurst" DIR="I" MPD_INDEX="151" NAME="PLBPPCS0RDBURST" SIGNAME="ppc440_0_SPLB0_PLB_rdBurst"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_Sl_addrAck" DIR="O" MPD_INDEX="152" NAME="PPCS0PLBADDRACK" SIGNAME="ppc440_0_SPLB0_Sl_addrAck"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_Sl_wait" DIR="O" MPD_INDEX="153" NAME="PPCS0PLBWAIT" SIGNAME="ppc440_0_SPLB0_Sl_wait"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_Sl_rearbitrate" DIR="O" MPD_INDEX="154" NAME="PPCS0PLBREARBITRATE" SIGNAME="ppc440_0_SPLB0_Sl_rearbitrate"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_Sl_wrDAck" DIR="O" MPD_INDEX="155" NAME="PPCS0PLBWRDACK" SIGNAME="ppc440_0_SPLB0_Sl_wrDAck"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_Sl_wrComp" DIR="O" MPD_INDEX="156" NAME="PPCS0PLBWRCOMP" SIGNAME="ppc440_0_SPLB0_Sl_wrComp"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_Sl_rdDBus" DIR="O" MPD_INDEX="157" NAME="PPCS0PLBRDDBUS" SIGNAME="ppc440_0_SPLB0_Sl_rdDBus" VECFORMULA="[0:127]"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_Sl_rdWdAddr" DIR="O" MPD_INDEX="158" NAME="PPCS0PLBRDWDADDR" SIGNAME="ppc440_0_SPLB0_Sl_rdWdAddr" VECFORMULA="[0:3]"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_Sl_rdDAck" DIR="O" MPD_INDEX="159" NAME="PPCS0PLBRDDACK" SIGNAME="ppc440_0_SPLB0_Sl_rdDAck"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_Sl_rdComp" DIR="O" MPD_INDEX="160" NAME="PPCS0PLBRDCOMP" SIGNAME="ppc440_0_SPLB0_Sl_rdComp"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_Sl_rdBTerm" DIR="O" MPD_INDEX="161" NAME="PPCS0PLBRDBTERM" SIGNAME="ppc440_0_SPLB0_Sl_rdBTerm"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_Sl_wrBTerm" DIR="O" MPD_INDEX="162" NAME="PPCS0PLBWRBTERM" SIGNAME="ppc440_0_SPLB0_Sl_wrBTerm"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_Sl_MBusy" DIR="O" MPD_INDEX="163" NAME="PPCS0PLBMBUSY" SIGNAME="ppc440_0_SPLB0_Sl_MBusy" VECFORMULA="[0:(C_SPLB0_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_Sl_MRdErr" DIR="O" MPD_INDEX="164" NAME="PPCS0PLBMRDERR" SIGNAME="ppc440_0_SPLB0_Sl_MRdErr" VECFORMULA="[0:(C_SPLB0_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_Sl_MWrErr" DIR="O" MPD_INDEX="165" NAME="PPCS0PLBMWRERR" SIGNAME="ppc440_0_SPLB0_Sl_MWrErr" VECFORMULA="[0:(C_SPLB0_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_Sl_MIRQ" DIR="O" MPD_INDEX="166" NAME="PPCS0PLBMIRQ" SIGNAME="ppc440_0_SPLB0_Sl_MIRQ" VECFORMULA="[0:(C_SPLB0_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB0" DEF_SIGNAME="ppc440_0_SPLB0_Sl_SSize" DIR="O" MPD_INDEX="167" NAME="PPCS0PLBSSIZE" SIGNAME="ppc440_0_SPLB0_Sl_SSize" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="168" NAME="CPMPPCS1PLBCLK" SIGIS="CLK" SIGNAME="__NOC__"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="169" NAME="PLBPPCS1MASTERID" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB1_MID_WIDTH-1)]"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="170" NAME="PLBPPCS1PAVALID" SIGNAME="__NOC__"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="171" NAME="PLBPPCS1SAVALID" SIGNAME="__NOC__"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="172" NAME="PLBPPCS1RDPENDREQ" SIGNAME="__NOC__"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="173" NAME="PLBPPCS1WRPENDREQ" SIGNAME="__NOC__"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="174" NAME="PLBPPCS1RDPENDPRI" SIGNAME="__NOC__" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="175" NAME="PLBPPCS1WRPENDPRI" SIGNAME="__NOC__" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="176" NAME="PLBPPCS1REQPRI" SIGNAME="__NOC__" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="177" NAME="PLBPPCS1RDPRIM" SIGNAME="__NOC__"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="178" NAME="PLBPPCS1WRPRIM" SIGNAME="__NOC__"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="179" NAME="PLBPPCS1BUSLOCK" SIGNAME="__NOC__"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="180" NAME="PLBPPCS1ABORT" SIGNAME="__NOC__"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="181" NAME="PLBPPCS1RNW" SIGNAME="__NOC__"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="182" NAME="PLBPPCS1BE" SIGNAME="__NOC__" VECFORMULA="[0:15]"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="183" NAME="PLBPPCS1SIZE" SIGNAME="__NOC__" VECFORMULA="[0:3]"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="184" NAME="PLBPPCS1TYPE" SIGNAME="__NOC__" VECFORMULA="[0:2]"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="185" NAME="PLBPPCS1TATTRIBUTE" SIGNAME="__NOC__" VECFORMULA="[0:15]"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="186" NAME="PLBPPCS1LOCKERR" SIGNAME="__NOC__"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="187" NAME="PLBPPCS1MSIZE" SIGNAME="__NOC__" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="188" NAME="PLBPPCS1UABUS" SIGNAME="__NOC__" VECFORMULA="[0:31]"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="189" NAME="PLBPPCS1ABUS" SIGNAME="__NOC__" VECFORMULA="[0:31]"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="190" NAME="PLBPPCS1WRDBUS" SIGNAME="__NOC__" VECFORMULA="[0:127]"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="191" NAME="PLBPPCS1WRBURST" SIGNAME="__NOC__"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="192" NAME="PLBPPCS1RDBURST" SIGNAME="__NOC__"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="193" NAME="PPCS1PLBADDRACK" SIGNAME="__NOC__"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="194" NAME="PPCS1PLBWAIT" SIGNAME="__NOC__"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="195" NAME="PPCS1PLBREARBITRATE" SIGNAME="__NOC__"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="196" NAME="PPCS1PLBWRDACK" SIGNAME="__NOC__"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="197" NAME="PPCS1PLBWRCOMP" SIGNAME="__NOC__"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="198" NAME="PPCS1PLBRDDBUS" SIGNAME="__NOC__" VECFORMULA="[0:127]"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="199" NAME="PPCS1PLBRDWDADDR" SIGNAME="__NOC__" VECFORMULA="[0:3]"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="200" NAME="PPCS1PLBRDDACK" SIGNAME="__NOC__"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="201" NAME="PPCS1PLBRDCOMP" SIGNAME="__NOC__"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="202" NAME="PPCS1PLBRDBTERM" SIGNAME="__NOC__"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="203" NAME="PPCS1PLBWRBTERM" SIGNAME="__NOC__"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="204" NAME="PPCS1PLBMBUSY" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB1_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="205" NAME="PPCS1PLBMRDERR" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB1_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="206" NAME="PPCS1PLBMWRERR" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB1_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="207" NAME="PPCS1PLBMIRQ" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB1_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="208" NAME="PPCS1PLBSSIZE" SIGNAME="__NOC__" VECFORMULA="[0:1]"/> + <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="209" NAME="CPMDMA0LLCLK" SIGIS="CLK" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="210" NAME="LLDMA0TXDSTRDYN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="211" NAME="LLDMA0RXD" SIGNAME="__NOC__" VECFORMULA="[0:31]"/> + <PORT BUS="LLDMA0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="212" NAME="LLDMA0RXREM" SIGNAME="__NOC__" VECFORMULA="[0:3]"/> + <PORT BUS="LLDMA0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="213" NAME="LLDMA0RXSOFN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="214" NAME="LLDMA0RXEOFN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="215" NAME="LLDMA0RXSOPN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="216" NAME="LLDMA0RXEOPN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="217" NAME="LLDMA0RXSRCRDYN" SIGNAME="__NOC__"/> + <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="218" NAME="LLDMA0RSTENGINEREQ" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="219" NAME="DMA0LLTXD" SIGNAME="__NOC__" VECFORMULA="[0:31]"/> + <PORT BUS="LLDMA0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="220" NAME="DMA0LLTXREM" SIGNAME="__NOC__" VECFORMULA="[0:3]"/> + <PORT BUS="LLDMA0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="221" NAME="DMA0LLTXSOFN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="222" NAME="DMA0LLTXEOFN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="223" NAME="DMA0LLTXSOPN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="224" NAME="DMA0LLTXEOPN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="225" NAME="DMA0LLTXSRCRDYN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="226" NAME="DMA0LLRXDSTRDYN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA0" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="227" NAME="DMA0LLRSTENGINEACK" SIGNAME="__NOC__"/> + <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="228" NAME="DMA0TXIRQ" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/> + <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="229" NAME="DMA0RXIRQ" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/> + <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="230" NAME="CPMDMA1LLCLK" SIGIS="CLK" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="231" NAME="LLDMA1TXDSTRDYN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="232" NAME="LLDMA1RXD" SIGNAME="__NOC__" VECFORMULA="[0:31]"/> + <PORT BUS="LLDMA1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="233" NAME="LLDMA1RXREM" SIGNAME="__NOC__" VECFORMULA="[0:3]"/> + <PORT BUS="LLDMA1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="234" NAME="LLDMA1RXSOFN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="235" NAME="LLDMA1RXEOFN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="236" NAME="LLDMA1RXSOPN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="237" NAME="LLDMA1RXEOPN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="238" NAME="LLDMA1RXSRCRDYN" SIGNAME="__NOC__"/> + <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="239" NAME="LLDMA1RSTENGINEREQ" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="240" NAME="DMA1LLTXD" SIGNAME="__NOC__" VECFORMULA="[0:31]"/> + <PORT BUS="LLDMA1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="241" NAME="DMA1LLTXREM" SIGNAME="__NOC__" VECFORMULA="[0:3]"/> + <PORT BUS="LLDMA1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="242" NAME="DMA1LLTXSOFN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="243" NAME="DMA1LLTXEOFN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="244" NAME="DMA1LLTXSOPN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="245" NAME="DMA1LLTXEOPN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="246" NAME="DMA1LLTXSRCRDYN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="247" NAME="DMA1LLRXDSTRDYN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA1" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="248" NAME="DMA1LLRSTENGINEACK" SIGNAME="__NOC__"/> + <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="249" NAME="DMA1TXIRQ" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/> + <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="250" NAME="DMA1RXIRQ" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/> + <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="251" NAME="CPMDMA2LLCLK" SIGIS="CLK" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="252" NAME="LLDMA2TXDSTRDYN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="253" NAME="LLDMA2RXD" SIGNAME="__NOC__" VECFORMULA="[0:31]"/> + <PORT BUS="LLDMA2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="254" NAME="LLDMA2RXREM" SIGNAME="__NOC__" VECFORMULA="[0:3]"/> + <PORT BUS="LLDMA2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="255" NAME="LLDMA2RXSOFN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="256" NAME="LLDMA2RXEOFN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="257" NAME="LLDMA2RXSOPN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="258" NAME="LLDMA2RXEOPN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="259" NAME="LLDMA2RXSRCRDYN" SIGNAME="__NOC__"/> + <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="260" NAME="LLDMA2RSTENGINEREQ" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="261" NAME="DMA2LLTXD" SIGNAME="__NOC__" VECFORMULA="[0:31]"/> + <PORT BUS="LLDMA2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="262" NAME="DMA2LLTXREM" SIGNAME="__NOC__" VECFORMULA="[0:3]"/> + <PORT BUS="LLDMA2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="263" NAME="DMA2LLTXSOFN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="264" NAME="DMA2LLTXEOFN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="265" NAME="DMA2LLTXSOPN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="266" NAME="DMA2LLTXEOPN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="267" NAME="DMA2LLTXSRCRDYN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="268" NAME="DMA2LLRXDSTRDYN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA2" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="269" NAME="DMA2LLRSTENGINEACK" SIGNAME="__NOC__"/> + <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="270" NAME="DMA2TXIRQ" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/> + <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="271" NAME="DMA2RXIRQ" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/> + <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="272" NAME="CPMDMA3LLCLK" SIGIS="CLK" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="273" NAME="LLDMA3TXDSTRDYN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="274" NAME="LLDMA3RXD" SIGNAME="__NOC__" VECFORMULA="[0:31]"/> + <PORT BUS="LLDMA3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="275" NAME="LLDMA3RXREM" SIGNAME="__NOC__" VECFORMULA="[0:3]"/> + <PORT BUS="LLDMA3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="276" NAME="LLDMA3RXSOFN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="277" NAME="LLDMA3RXEOFN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="278" NAME="LLDMA3RXSOPN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="279" NAME="LLDMA3RXEOPN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="280" NAME="LLDMA3RXSRCRDYN" SIGNAME="__NOC__"/> + <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="281" NAME="LLDMA3RSTENGINEREQ" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="282" NAME="DMA3LLTXD" SIGNAME="__NOC__" VECFORMULA="[0:31]"/> + <PORT BUS="LLDMA3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="283" NAME="DMA3LLTXREM" SIGNAME="__NOC__" VECFORMULA="[0:3]"/> + <PORT BUS="LLDMA3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="284" NAME="DMA3LLTXSOFN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="285" NAME="DMA3LLTXEOFN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="286" NAME="DMA3LLTXSOPN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="287" NAME="DMA3LLTXEOPN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="288" NAME="DMA3LLTXSRCRDYN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="289" NAME="DMA3LLRXDSTRDYN" SIGNAME="__NOC__"/> + <PORT BUS="LLDMA3" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="290" NAME="DMA3LLRSTENGINEACK" SIGNAME="__NOC__"/> + <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="291" NAME="DMA3TXIRQ" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/> + <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="292" NAME="DMA3RXIRQ" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/> + <PORT BUS="RESETPPC" DEF_SIGNAME="ppc_reset_bus_RstcPPCresetcore" DIR="I" MPD_INDEX="293" NAME="RSTC440RESETCORE" SIGIS="RST" SIGNAME="ppc_reset_bus_RstcPPCresetcore"/> + <PORT BUS="RESETPPC" DEF_SIGNAME="ppc_reset_bus_RstsPPCresetchip" DIR="I" MPD_INDEX="294" NAME="RSTC440RESETCHIP" SIGIS="RST" SIGNAME="ppc_reset_bus_RstsPPCresetchip"/> + <PORT BUS="RESETPPC" DEF_SIGNAME="ppc_reset_bus_RstcPPCresetsys" DIR="I" MPD_INDEX="295" NAME="RSTC440RESETSYSTEM" SIGIS="RST" SIGNAME="ppc_reset_bus_RstcPPCresetsys"/> + <PORT BUS="RESETPPC" DEF_SIGNAME="ppc_reset_bus_Core_Reset_Req" DIR="O" MPD_INDEX="296" NAME="C440RSTCORERESETREQ" SIGIS="RST" SIGNAME="ppc_reset_bus_Core_Reset_Req"/> + <PORT BUS="RESETPPC" DEF_SIGNAME="ppc_reset_bus_Chip_Reset_Req" DIR="O" MPD_INDEX="297" NAME="C440RSTCHIPRESETREQ" SIGIS="RST" SIGNAME="ppc_reset_bus_Chip_Reset_Req"/> + <PORT BUS="RESETPPC" DEF_SIGNAME="ppc_reset_bus_System_Reset_Req" DIR="O" MPD_INDEX="298" NAME="C440RSTSYSTEMRESETREQ" SIGIS="RST" SIGNAME="ppc_reset_bus_System_Reset_Req"/> + <PORT DIR="I" MPD_INDEX="299" NAME="TRCC440TRACEDISABLE" SIGNAME="__NOC__"/> + <PORT DIR="I" MPD_INDEX="300" NAME="TRCC440TRIGGEREVENTIN" SIGNAME="__NOC__"> + <DESCRIPTION>Trace Trigger Event In</DESCRIPTION> + </PORT> + <PORT DIR="O" MPD_INDEX="301" NAME="C440TRCBRANCHSTATUS" SIGNAME="__NOC__" VECFORMULA="[0:2]"> + <DESCRIPTION>Trace Branch Status</DESCRIPTION> + </PORT> + <PORT DIR="O" MPD_INDEX="302" NAME="C440TRCCYCLE" SIGNAME="__NOC__"> + <DESCRIPTION>Trace Clock</DESCRIPTION> + </PORT> + <PORT DIR="O" MPD_INDEX="303" NAME="C440TRCEXECUTIONSTATUS" SIGNAME="__NOC__" VECFORMULA="[0:4]"> + <DESCRIPTION>Trace Execution Status</DESCRIPTION> + </PORT> + <PORT DIR="O" MPD_INDEX="304" NAME="C440TRCTRACESTATUS" SIGNAME="__NOC__" VECFORMULA="[0:6]"> + <DESCRIPTION>Trace Status</DESCRIPTION> + </PORT> + <PORT DIR="O" MPD_INDEX="305" NAME="C440TRCTRIGGEREVENTOUT" SIGNAME="__NOC__"> + <DESCRIPTION>Trace Trigger Event Out</DESCRIPTION> + </PORT> + <PORT DIR="O" MPD_INDEX="306" NAME="C440TRCTRIGGEREVENTTYPE" SIGNAME="__NOC__" VECFORMULA="[0:13]"/> + <BUSINTERFACE BUSNAME="plb_v46_0" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_DATA="TRUE" IS_INMHS="TRUE" IS_INSTRUCTION="TRUE" MPD_INDEX="0" NAME="MPLB" TYPE="MASTER"/> + <BUSINTERFACE BUSNAME="ppc440_0_SPLB0" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INMHS="TRUE" MPD_INDEX="1" NAME="SPLB0" TYPE="SLAVE"/> + <BUSINTERFACE BUSNAME="ppc440_0_PPC440MC" BUSSTD="XIL" BUSSTD_PSF="XIL_PPC440MC" IS_DATA="TRUE" IS_INMHS="TRUE" IS_INSTRUCTION="TRUE" MPD_INDEX="3" NAME="PPC440MC" TYPE="INITIATOR"/> + <BUSINTERFACE BUSNAME="ppc440_0_jtagppc_bus" BUSSTD="XIL" BUSSTD_PSF="XIL_JTAGPPC" IS_INMHS="TRUE" MPD_INDEX="12" NAME="JTAGPPC" TYPE="TARGET"/> + <BUSINTERFACE BUSNAME="ppc_reset_bus" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_INMHS="TRUE" MPD_INDEX="13" NAME="RESETPPC" TYPE="TARGET"/> + <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" MPD_INDEX="2" NAME="SPLB1" TYPE="SLAVE"/> + <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_LL_DMA" IS_VALID="FALSE" MPD_INDEX="4" NAME="LLDMA0" TYPE="TARGET"/> + <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_LL_DMA" IS_VALID="FALSE" MPD_INDEX="5" NAME="LLDMA1" TYPE="TARGET"/> + <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_LL_DMA" IS_VALID="FALSE" MPD_INDEX="6" NAME="LLDMA2" TYPE="TARGET"/> + <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_LL_DMA" IS_VALID="FALSE" MPD_INDEX="7" NAME="LLDMA3" TYPE="TARGET"/> + <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="DCR" BUSSTD_PSF="DCR" MPD_INDEX="8" NAME="MDCR" TYPE="MASTER"/> + <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="DCR" BUSSTD_PSF="DCR" MPD_INDEX="9" NAME="SDCR" TYPE="SLAVE"/> + <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FCB" BUSSTD_PSF="FCB2" MPD_INDEX="10" NAME="MFCB" TYPE="MASTER"/> + <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_FCM2" MPD_INDEX="11" NAME="MFCM" TYPE="INITIATOR"/> + <PERIPHERALS> + <MODULE INSTANCE="xps_bram_if_cntlr_1"/> + <MODULE INSTANCE="RS232_Uart_1"/> + <MODULE INSTANCE="LEDs_8Bit"/> + <MODULE INSTANCE="LEDs_Positions"/> + <MODULE INSTANCE="Push_Buttons_5Bit"/> + <MODULE INSTANCE="DIP_Switches_8Bit"/> + <MODULE INSTANCE="IIC_EEPROM"/> + <MODULE INSTANCE="SRAM"/> + <MODULE INSTANCE="PCIe_Bridge"/> + <MODULE INSTANCE="Ethernet_MAC"/> + <MODULE INSTANCE="SysACE_CompactFlash"/> + <MODULE INSTANCE="xps_intc_0"/> + <MODULE INSTANCE="DDR2_SDRAM"/> + </PERIPHERALS> + <INTERRUPTINFO INTC_INDEX="0" INTERRUPT_CNTLR="xps_intc_0" TYPE="TARGET"/> + </MODULE> + <MODULE BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" HWVERSION="1.04.a" INSTANCE="plb_v46_0" IPTYPE="BUS" MHS_INDEX="1" MODCLASS="BUS" MODTYPE="plb_v46"> + <DESCRIPTION TYPE="SHORT">Processor Local Bus (PLB) 4.6</DESCRIPTION> + <DESCRIPTION TYPE="LONG">'Xilinx 64-bit Processor Local Bus (PLB) consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units with a a three-cycle only arbitration feature'</DESCRIPTION> + <DOCUMENTATION> + <DOCUMENT SOURCE="c:/devtools/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/plb_v46_v1_04_a/doc/plb_v46.pdf" TYPE="IP"/> + </DOCUMENTATION> + <LICENSEINFO ICON_NAME="ps_core_preferred"/> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_PLBV46_NUM_MASTERS" TYPE="integer" VALUE="1"> + <DESCRIPTION>Number of PLB Masters</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_PLBV46_NUM_SLAVES" TYPE="integer" VALUE="12"> + <DESCRIPTION>Number of PLB Slaves</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_PLBV46_MID_WIDTH" TYPE="integer" VALUE="1"> + <DESCRIPTION>PLB Master ID Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="3" NAME="C_PLBV46_AWIDTH" TYPE="integer" VALUE="32"> + <DESCRIPTION>PLB Address Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_PLBV46_DWIDTH" TYPE="integer" VALUE="128"> + <DESCRIPTION>PLB Data Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="5" NAME="C_DCR_INTFCE" TYPE="integer" VALUE="0"> + <DESCRIPTION>Include DCR Interface and Error Registers</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="6" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0b1111111111"> + <DESCRIPTION>Base Address</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="7" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0b0000000000"> + <DESCRIPTION>High Address</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="8" NAME="C_DCR_AWIDTH" TYPE="integer" VALUE="10"> + <DESCRIPTION>DCR Address Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="9" NAME="C_DCR_DWIDTH" TYPE="integer" VALUE="32"> + <DESCRIPTION>DCR Data Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="10" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1"> + <DESCRIPTION>External Reset Active High </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="11" NAME="C_IRQ_ACTIVE" TYPE="std_logic" VALUE="1"> + <DESCRIPTION>IRQ Active State </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="12" NAME="C_NUM_CLK_PLB2OPB_REARB" TYPE="integer" VALUE="5"> + <DESCRIPTION><qt>Number of PLB Clock Periods a PLB Master that Received a Rearbitrate from an OPB2PLB Bridge on a Read Operation is Denied Grant on the PLB Bus</qt></DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="13" NAME="C_ADDR_PIPELINING_TYPE" TYPE="integer" VALUE="1"> + <DESCRIPTION>Enable Address Pipelining Type</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="14" NAME="C_FAMILY" TYPE="string" VALUE="virtex5"> + <DESCRIPTION>Device Family</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="15" NAME="C_P2P" TYPE="integer" VALUE="0"> + <DESCRIPTION>Optimize PLB for Point-to-point Topology</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="16" NAME="C_ARB_TYPE" TYPE="integer" VALUE="0"> + <DESCRIPTION>Selects the Arbitration Scheme</DESCRIPTION> + </PARAMETER> + <MEMORYMAP> + <MEMRANGE BASEDECIMAL="1023" BASENAME="C_BASEADDR" BASEVALUE="0b1111111111" HIGHDECIMAL="0" HIGHNAME="C_HIGHADDR" HIGHVALUE="0b0000000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x08" SIZE="0" SIZEABRV="U"> + <SLVINTERFACES> + <BUSINTERFACE NAME="SDCR"/> + </SLVINTERFACES> + </MEMRANGE> + </MEMORYMAP> + <PORT CLKFREQUENCY="125000000" DIR="I" IS_INMHS="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="PLB_Clk" SIGIS="CLK" SIGNAME="clk_125_0000MHzPLL0_ADJUST"/> + <PORT DIR="I" IS_INMHS="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="SYS_Rst" SIGIS="RST" SIGNAME="sys_bus_reset"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_Rst" DIR="O" MPD_INDEX="2" NAME="PLB_Rst" SIGIS="RST" SIGNAME="plb_v46_0_PLB_Rst"/> + <PORT DEF_SIGNAME="plb_v46_0_SPLB_Rst" DIR="O" MPD_INDEX="3" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="plb_v46_0_SPLB_Rst" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_MPLB_Rst" DIR="O" MPD_INDEX="4" NAME="MPLB_Rst" SIGIS="RST" SIGNAME="plb_v46_0_MPLB_Rst" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="5" NAME="PLB_dcrAck" SIGNAME="__NOC__"/> + <PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="6" NAME="PLB_dcrDBus" SIGNAME="__NOC__" VECFORMULA="[0:C_DCR_DWIDTH-1]"/> + <PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="7" NAME="DCR_ABus" SIGNAME="__NOC__" VECFORMULA="[0:C_DCR_AWIDTH-1]"/> + <PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="8" NAME="DCR_DBus" SIGNAME="__NOC__" VECFORMULA="[0:C_DCR_DWIDTH-1]"/> + <PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="9" NAME="DCR_Read" SIGNAME="__NOC__"/> + <PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="10" NAME="DCR_Write" SIGNAME="__NOC__"/> + <PORT DEF_SIGNAME="plb_v46_0_M_ABus" DIR="I" MPD_INDEX="11" NAME="M_ABus" SIGNAME="plb_v46_0_M_ABus" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*32)-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_M_UABus" DIR="I" MPD_INDEX="12" NAME="M_UABus" SIGNAME="plb_v46_0_M_UABus" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*32)-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_M_BE" DIR="I" MPD_INDEX="13" NAME="M_BE" SIGNAME="plb_v46_0_M_BE" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*(C_PLBV46_DWIDTH/8))-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_M_RNW" DIR="I" MPD_INDEX="14" NAME="M_RNW" SIGNAME="plb_v46_0_M_RNW" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_M_abort" DIR="I" MPD_INDEX="15" NAME="M_abort" SIGNAME="plb_v46_0_M_abort" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_M_busLock" DIR="I" MPD_INDEX="16" NAME="M_busLock" SIGNAME="plb_v46_0_M_busLock" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_M_TAttribute" DIR="I" MPD_INDEX="17" NAME="M_TAttribute" SIGNAME="plb_v46_0_M_TAttribute" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*16)-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_M_lockErr" DIR="I" MPD_INDEX="18" NAME="M_lockErr" SIGNAME="plb_v46_0_M_lockErr" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_M_MSize" DIR="I" MPD_INDEX="19" NAME="M_MSize" SIGNAME="plb_v46_0_M_MSize" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*2)-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_M_priority" DIR="I" MPD_INDEX="20" NAME="M_priority" SIGNAME="plb_v46_0_M_priority" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*2)-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_M_rdBurst" DIR="I" MPD_INDEX="21" NAME="M_rdBurst" SIGNAME="plb_v46_0_M_rdBurst" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_M_request" DIR="I" MPD_INDEX="22" NAME="M_request" SIGNAME="plb_v46_0_M_request" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_M_size" DIR="I" MPD_INDEX="23" NAME="M_size" SIGNAME="plb_v46_0_M_size" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*4)-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_M_type" DIR="I" MPD_INDEX="24" NAME="M_type" SIGNAME="plb_v46_0_M_type" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*3)-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_M_wrBurst" DIR="I" MPD_INDEX="25" NAME="M_wrBurst" SIGNAME="plb_v46_0_M_wrBurst" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_M_wrDBus" DIR="I" MPD_INDEX="26" NAME="M_wrDBus" SIGNAME="plb_v46_0_M_wrDBus" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_Sl_addrAck" DIR="I" MPD_INDEX="27" NAME="Sl_addrAck" SIGNAME="plb_v46_0_Sl_addrAck" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_Sl_MRdErr" DIR="I" MPD_INDEX="28" NAME="Sl_MRdErr" SIGNAME="plb_v46_0_Sl_MRdErr" VECFORMULA="[0:(C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_Sl_MWrErr" DIR="I" MPD_INDEX="29" NAME="Sl_MWrErr" SIGNAME="plb_v46_0_Sl_MWrErr" VECFORMULA="[0:(C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_Sl_MBusy" DIR="I" MPD_INDEX="30" NAME="Sl_MBusy" SIGNAME="plb_v46_0_Sl_MBusy" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS - 1 ]"/> + <PORT DEF_SIGNAME="plb_v46_0_Sl_rdBTerm" DIR="I" MPD_INDEX="31" NAME="Sl_rdBTerm" SIGNAME="plb_v46_0_Sl_rdBTerm" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_Sl_rdComp" DIR="I" MPD_INDEX="32" NAME="Sl_rdComp" SIGNAME="plb_v46_0_Sl_rdComp" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_Sl_rdDAck" DIR="I" MPD_INDEX="33" NAME="Sl_rdDAck" SIGNAME="plb_v46_0_Sl_rdDAck" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_Sl_rdDBus" DIR="I" MPD_INDEX="34" NAME="Sl_rdDBus" SIGNAME="plb_v46_0_Sl_rdDBus" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*C_PLBV46_DWIDTH-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_Sl_rdWdAddr" DIR="I" MPD_INDEX="35" NAME="Sl_rdWdAddr" SIGNAME="plb_v46_0_Sl_rdWdAddr" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*4-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_Sl_rearbitrate" DIR="I" MPD_INDEX="36" NAME="Sl_rearbitrate" SIGNAME="plb_v46_0_Sl_rearbitrate" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_Sl_SSize" DIR="I" MPD_INDEX="37" NAME="Sl_SSize" SIGNAME="plb_v46_0_Sl_SSize" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*2-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_Sl_wait" DIR="I" MPD_INDEX="38" NAME="Sl_wait" SIGNAME="plb_v46_0_Sl_wait" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_Sl_wrBTerm" DIR="I" MPD_INDEX="39" NAME="Sl_wrBTerm" SIGNAME="plb_v46_0_Sl_wrBTerm" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_Sl_wrComp" DIR="I" MPD_INDEX="40" NAME="Sl_wrComp" SIGNAME="plb_v46_0_Sl_wrComp" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_Sl_wrDAck" DIR="I" MPD_INDEX="41" NAME="Sl_wrDAck" SIGNAME="plb_v46_0_Sl_wrDAck" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_Sl_MIRQ" DIR="I" MPD_INDEX="42" NAME="Sl_MIRQ" SIGNAME="plb_v46_0_Sl_MIRQ" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_MIRQ" DIR="O" MPD_INDEX="43" NAME="PLB_MIRQ" SIGNAME="plb_v46_0_PLB_MIRQ" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_ABus" DIR="O" MPD_INDEX="44" NAME="PLB_ABus" SIGNAME="plb_v46_0_PLB_ABus" VECFORMULA="[0:31]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_UABus" DIR="O" MPD_INDEX="45" NAME="PLB_UABus" SIGNAME="plb_v46_0_PLB_UABus" VECFORMULA="[0:31]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_BE" DIR="O" MPD_INDEX="46" NAME="PLB_BE" SIGNAME="plb_v46_0_PLB_BE" VECFORMULA="[0:(C_PLBV46_DWIDTH/8)-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_MAddrAck" DIR="O" MPD_INDEX="47" NAME="PLB_MAddrAck" SIGNAME="plb_v46_0_PLB_MAddrAck" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_MTimeout" DIR="O" MPD_INDEX="48" NAME="PLB_MTimeout" SIGNAME="plb_v46_0_PLB_MTimeout" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_MBusy" DIR="O" MPD_INDEX="49" NAME="PLB_MBusy" SIGNAME="plb_v46_0_PLB_MBusy" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_MRdErr" DIR="O" MPD_INDEX="50" NAME="PLB_MRdErr" SIGNAME="plb_v46_0_PLB_MRdErr" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_MWrErr" DIR="O" MPD_INDEX="51" NAME="PLB_MWrErr" SIGNAME="plb_v46_0_PLB_MWrErr" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_MRdBTerm" DIR="O" MPD_INDEX="52" NAME="PLB_MRdBTerm" SIGNAME="plb_v46_0_PLB_MRdBTerm" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_MRdDAck" DIR="O" MPD_INDEX="53" NAME="PLB_MRdDAck" SIGNAME="plb_v46_0_PLB_MRdDAck" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_MRdDBus" DIR="O" MPD_INDEX="54" NAME="PLB_MRdDBus" SIGNAME="plb_v46_0_PLB_MRdDBus" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_MRdWdAddr" DIR="O" MPD_INDEX="55" NAME="PLB_MRdWdAddr" SIGNAME="plb_v46_0_PLB_MRdWdAddr" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*4)-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_MRearbitrate" DIR="O" MPD_INDEX="56" NAME="PLB_MRearbitrate" SIGNAME="plb_v46_0_PLB_MRearbitrate" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_MWrBTerm" DIR="O" MPD_INDEX="57" NAME="PLB_MWrBTerm" SIGNAME="plb_v46_0_PLB_MWrBTerm" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_MWrDAck" DIR="O" MPD_INDEX="58" NAME="PLB_MWrDAck" SIGNAME="plb_v46_0_PLB_MWrDAck" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_MSSize" DIR="O" MPD_INDEX="59" NAME="PLB_MSSize" SIGNAME="plb_v46_0_PLB_MSSize" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*2)-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_PAValid" DIR="O" MPD_INDEX="60" NAME="PLB_PAValid" SIGNAME="plb_v46_0_PLB_PAValid"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_RNW" DIR="O" MPD_INDEX="61" NAME="PLB_RNW" SIGNAME="plb_v46_0_PLB_RNW"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_SAValid" DIR="O" MPD_INDEX="62" NAME="PLB_SAValid" SIGNAME="plb_v46_0_PLB_SAValid"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_abort" DIR="O" MPD_INDEX="63" NAME="PLB_abort" SIGNAME="plb_v46_0_PLB_abort"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_busLock" DIR="O" MPD_INDEX="64" NAME="PLB_busLock" SIGNAME="plb_v46_0_PLB_busLock"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_TAttribute" DIR="O" MPD_INDEX="65" NAME="PLB_TAttribute" SIGNAME="plb_v46_0_PLB_TAttribute" VECFORMULA="[0:15]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_lockErr" DIR="O" MPD_INDEX="66" NAME="PLB_lockErr" SIGNAME="plb_v46_0_PLB_lockErr"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_masterID" DIR="O" MPD_INDEX="67" NAME="PLB_masterID" SIGNAME="plb_v46_0_PLB_masterID" VECFORMULA="[0:C_PLBV46_MID_WIDTH-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_MSize" DIR="O" MPD_INDEX="68" NAME="PLB_MSize" SIGNAME="plb_v46_0_PLB_MSize" VECFORMULA="[0:1]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_rdPendPri" DIR="O" MPD_INDEX="69" NAME="PLB_rdPendPri" SIGNAME="plb_v46_0_PLB_rdPendPri" VECFORMULA="[0:1]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_wrPendPri" DIR="O" MPD_INDEX="70" NAME="PLB_wrPendPri" SIGNAME="plb_v46_0_PLB_wrPendPri" VECFORMULA="[0:1]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_rdPendReq" DIR="O" MPD_INDEX="71" NAME="PLB_rdPendReq" SIGNAME="plb_v46_0_PLB_rdPendReq"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_wrPendReq" DIR="O" MPD_INDEX="72" NAME="PLB_wrPendReq" SIGNAME="plb_v46_0_PLB_wrPendReq"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_rdBurst" DIR="O" MPD_INDEX="73" NAME="PLB_rdBurst" SIGNAME="plb_v46_0_PLB_rdBurst"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_rdPrim" DIR="O" MPD_INDEX="74" NAME="PLB_rdPrim" SIGNAME="plb_v46_0_PLB_rdPrim" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_reqPri" DIR="O" MPD_INDEX="75" NAME="PLB_reqPri" SIGNAME="plb_v46_0_PLB_reqPri" VECFORMULA="[0:1]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_size" DIR="O" MPD_INDEX="76" NAME="PLB_size" SIGNAME="plb_v46_0_PLB_size" VECFORMULA="[0:3]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_type" DIR="O" MPD_INDEX="77" NAME="PLB_type" SIGNAME="plb_v46_0_PLB_type" VECFORMULA="[0:2]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_wrBurst" DIR="O" MPD_INDEX="78" NAME="PLB_wrBurst" SIGNAME="plb_v46_0_PLB_wrBurst"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_wrDBus" DIR="O" MPD_INDEX="79" NAME="PLB_wrDBus" SIGNAME="plb_v46_0_PLB_wrDBus" VECFORMULA="[0:C_PLBV46_DWIDTH-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_wrPrim" DIR="O" MPD_INDEX="80" NAME="PLB_wrPrim" SIGNAME="plb_v46_0_PLB_wrPrim" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_SaddrAck" DIR="O" MPD_INDEX="81" NAME="PLB_SaddrAck" SIGNAME="plb_v46_0_PLB_SaddrAck"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_SMRdErr" DIR="O" MPD_INDEX="82" NAME="PLB_SMRdErr" SIGNAME="plb_v46_0_PLB_SMRdErr" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_SMWrErr" DIR="O" MPD_INDEX="83" NAME="PLB_SMWrErr" SIGNAME="plb_v46_0_PLB_SMWrErr" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_SMBusy" DIR="O" MPD_INDEX="84" NAME="PLB_SMBusy" SIGNAME="plb_v46_0_PLB_SMBusy" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_SrdBTerm" DIR="O" MPD_INDEX="85" NAME="PLB_SrdBTerm" SIGNAME="plb_v46_0_PLB_SrdBTerm"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_SrdComp" DIR="O" MPD_INDEX="86" NAME="PLB_SrdComp" SIGNAME="plb_v46_0_PLB_SrdComp"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_SrdDAck" DIR="O" MPD_INDEX="87" NAME="PLB_SrdDAck" SIGNAME="plb_v46_0_PLB_SrdDAck"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_SrdDBus" DIR="O" MPD_INDEX="88" NAME="PLB_SrdDBus" SIGNAME="plb_v46_0_PLB_SrdDBus" VECFORMULA="[0:C_PLBV46_DWIDTH-1]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_SrdWdAddr" DIR="O" MPD_INDEX="89" NAME="PLB_SrdWdAddr" SIGNAME="plb_v46_0_PLB_SrdWdAddr" VECFORMULA="[0:3]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_Srearbitrate" DIR="O" MPD_INDEX="90" NAME="PLB_Srearbitrate" SIGNAME="plb_v46_0_PLB_Srearbitrate"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_Sssize" DIR="O" MPD_INDEX="91" NAME="PLB_Sssize" SIGNAME="plb_v46_0_PLB_Sssize" VECFORMULA="[0:1]"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_Swait" DIR="O" MPD_INDEX="92" NAME="PLB_Swait" SIGNAME="plb_v46_0_PLB_Swait"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_SwrBTerm" DIR="O" MPD_INDEX="93" NAME="PLB_SwrBTerm" SIGNAME="plb_v46_0_PLB_SwrBTerm"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_SwrComp" DIR="O" MPD_INDEX="94" NAME="PLB_SwrComp" SIGNAME="plb_v46_0_PLB_SwrComp"/> + <PORT DEF_SIGNAME="plb_v46_0_PLB_SwrDAck" DIR="O" MPD_INDEX="95" NAME="PLB_SwrDAck" SIGNAME="plb_v46_0_PLB_SwrDAck"/> + <PORT DIR="O" MPD_INDEX="96" NAME="Bus_Error_Det" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/> + <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="DCR" BUSSTD_PSF="DCR" IS_VALID="FALSE" MPD_INDEX="0" NAME="SDCR" TYPE="SLAVE"/> + </MODULE> + <MODULE HWVERSION="1.00.b" INSTANCE="xps_bram_if_cntlr_1" IPTYPE="PERIPHERAL" MHS_INDEX="2" MODCLASS="MEMORY_CNTLR" MODTYPE="xps_bram_if_cntlr"> + <DESCRIPTION TYPE="SHORT">XPS BRAM Controller</DESCRIPTION> + <DESCRIPTION TYPE="LONG">Attaches BRAM to the PLBV46</DESCRIPTION> + <DOCUMENTATION> + <DOCUMENT SOURCE="c:/devtools/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/xps_bram_if_cntlr_v1_00_b/doc/xps_bram_if_cntlr.pdf" TYPE="IP"/> + </DOCUMENTATION> + <LICENSEINFO ICON_NAME="ps_core_preferred"/> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" MPD_INDEX="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0xffffe000"> + <DESCRIPTION>Base Address</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" MPD_INDEX="1" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0xffffffff"> + <DESCRIPTION>High Address</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="2" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="integer" VALUE="64"> + <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="3" NAME="C_SPLB_AWIDTH" TYPE="integer" VALUE="32"> + <DESCRIPTION>PLB Address Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_SPLB_DWIDTH" TYPE="integer" VALUE="128"> + <DESCRIPTION>PLB Data Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_SPLB_NUM_MASTERS" TYPE="integer" VALUE="1"> + <DESCRIPTION>Number of PLB Masters</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="6" NAME="C_SPLB_MID_WIDTH" TYPE="integer" VALUE="1"> + <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="7" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="integer" VALUE="1"> + <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="8" NAME="C_SPLB_P2P" TYPE="integer" VALUE="0"> + <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_SPLB_SMALLEST_MASTER" TYPE="integer" VALUE="128"> + <DESCRIPTION>Smallest Master Data Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="10" NAME="C_FAMILY" TYPE="string" VALUE="virtex5"> + <DESCRIPTION>Device Family</DESCRIPTION> + </PARAMETER> + <MEMORYMAP> + <MEMRANGE BASEDECIMAL="4294959104" BASENAME="C_BASEADDR" BASEVALUE="0xffffe000" HIGHDECIMAL="4294967295" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xffffffff" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="8192" SIZEABRV="8K"> + <SLVINTERFACES> + <BUSINTERFACE NAME="SPLB"/> + </SLVINTERFACES> + </MEMRANGE> + </MEMORYMAP> + <PORT BUS="SPLB" CLKFREQUENCY="125000000" DEF_SIGNAME="clk_125_0000MHzPLL0_ADJUST" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_125_0000MHzPLL0_ADJUST"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="plb_v46_0_SPLB_Rst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_ABus" DIR="I" MPD_INDEX="2" NAME="PLB_ABus" SIGNAME="plb_v46_0_PLB_ABus" VECFORMULA="[0:31]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_UABus" DIR="I" MPD_INDEX="3" NAME="PLB_UABus" SIGNAME="plb_v46_0_PLB_UABus" VECFORMULA="[0:31]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_PAValid" DIR="I" MPD_INDEX="4" NAME="PLB_PAValid" SIGNAME="plb_v46_0_PLB_PAValid"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_SAValid" DIR="I" MPD_INDEX="5" NAME="PLB_SAValid" SIGNAME="plb_v46_0_PLB_SAValid"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPrim" DIR="I" MPD_INDEX="6" NAME="PLB_rdPrim" SIGNAME="plb_v46_0_PLB_rdPrim"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPrim" DIR="I" MPD_INDEX="7" NAME="PLB_wrPrim" SIGNAME="plb_v46_0_PLB_wrPrim"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_masterID" DIR="I" MPD_INDEX="8" NAME="PLB_masterID" SIGNAME="plb_v46_0_PLB_masterID" VECFORMULA="[0:C_SPLB_MID_WIDTH-1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_abort" DIR="I" MPD_INDEX="9" NAME="PLB_abort" SIGNAME="plb_v46_0_PLB_abort"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_busLock" DIR="I" MPD_INDEX="10" NAME="PLB_busLock" SIGNAME="plb_v46_0_PLB_busLock"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_RNW" DIR="I" MPD_INDEX="11" NAME="PLB_RNW" SIGNAME="plb_v46_0_PLB_RNW"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_BE" DIR="I" MPD_INDEX="12" NAME="PLB_BE" SIGNAME="plb_v46_0_PLB_BE" VECFORMULA="[0:(C_SPLB_DWIDTH/8)-1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_MSize" DIR="I" MPD_INDEX="13" NAME="PLB_MSize" SIGNAME="plb_v46_0_PLB_MSize" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_size" DIR="I" MPD_INDEX="14" NAME="PLB_size" SIGNAME="plb_v46_0_PLB_size" VECFORMULA="[0:3]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_type" DIR="I" MPD_INDEX="15" NAME="PLB_type" SIGNAME="plb_v46_0_PLB_type" VECFORMULA="[0:2]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_lockErr" DIR="I" MPD_INDEX="16" NAME="PLB_lockErr" SIGNAME="plb_v46_0_PLB_lockErr"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrDBus" DIR="I" MPD_INDEX="17" NAME="PLB_wrDBus" SIGNAME="plb_v46_0_PLB_wrDBus" VECFORMULA="[0:C_SPLB_DWIDTH-1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrBurst" DIR="I" MPD_INDEX="18" NAME="PLB_wrBurst" SIGNAME="plb_v46_0_PLB_wrBurst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdBurst" DIR="I" MPD_INDEX="19" NAME="PLB_rdBurst" SIGNAME="plb_v46_0_PLB_rdBurst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPendReq" DIR="I" MPD_INDEX="20" NAME="PLB_wrPendReq" SIGNAME="plb_v46_0_PLB_wrPendReq"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPendReq" DIR="I" MPD_INDEX="21" NAME="PLB_rdPendReq" SIGNAME="plb_v46_0_PLB_rdPendReq"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPendPri" DIR="I" MPD_INDEX="22" NAME="PLB_wrPendPri" SIGNAME="plb_v46_0_PLB_wrPendPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPendPri" DIR="I" MPD_INDEX="23" NAME="PLB_rdPendPri" SIGNAME="plb_v46_0_PLB_rdPendPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_reqPri" DIR="I" MPD_INDEX="24" NAME="PLB_reqPri" SIGNAME="plb_v46_0_PLB_reqPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_TAttribute" DIR="I" MPD_INDEX="25" NAME="PLB_TAttribute" SIGNAME="plb_v46_0_PLB_TAttribute" VECFORMULA="[0:15]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_addrAck" DIR="O" MPD_INDEX="26" NAME="Sl_addrAck" SIGNAME="plb_v46_0_Sl_addrAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_SSize" DIR="O" MPD_INDEX="27" NAME="Sl_SSize" SIGNAME="plb_v46_0_Sl_SSize" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wait" DIR="O" MPD_INDEX="28" NAME="Sl_wait" SIGNAME="plb_v46_0_Sl_wait"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rearbitrate" DIR="O" MPD_INDEX="29" NAME="Sl_rearbitrate" SIGNAME="plb_v46_0_Sl_rearbitrate"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrDAck" DIR="O" MPD_INDEX="30" NAME="Sl_wrDAck" SIGNAME="plb_v46_0_Sl_wrDAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrComp" DIR="O" MPD_INDEX="31" NAME="Sl_wrComp" SIGNAME="plb_v46_0_Sl_wrComp"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrBTerm" DIR="O" MPD_INDEX="32" NAME="Sl_wrBTerm" SIGNAME="plb_v46_0_Sl_wrBTerm"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdDBus" DIR="O" MPD_INDEX="33" NAME="Sl_rdDBus" SIGNAME="plb_v46_0_Sl_rdDBus" VECFORMULA="[0:C_SPLB_DWIDTH-1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdWdAddr" DIR="O" MPD_INDEX="34" NAME="Sl_rdWdAddr" SIGNAME="plb_v46_0_Sl_rdWdAddr" VECFORMULA="[0:3]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdDAck" DIR="O" MPD_INDEX="35" NAME="Sl_rdDAck" SIGNAME="plb_v46_0_Sl_rdDAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdComp" DIR="O" MPD_INDEX="36" NAME="Sl_rdComp" SIGNAME="plb_v46_0_Sl_rdComp"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdBTerm" DIR="O" MPD_INDEX="37" NAME="Sl_rdBTerm" SIGNAME="plb_v46_0_Sl_rdBTerm"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MBusy" DIR="O" MPD_INDEX="38" NAME="Sl_MBusy" SIGNAME="plb_v46_0_Sl_MBusy" VECFORMULA="[0:C_SPLB_NUM_MASTERS-1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MWrErr" DIR="O" MPD_INDEX="39" NAME="Sl_MWrErr" SIGNAME="plb_v46_0_Sl_MWrErr" VECFORMULA="[0:C_SPLB_NUM_MASTERS-1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MRdErr" DIR="O" MPD_INDEX="40" NAME="Sl_MRdErr" SIGNAME="plb_v46_0_Sl_MRdErr" VECFORMULA="[0:C_SPLB_NUM_MASTERS-1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MIRQ" DIR="O" MPD_INDEX="41" NAME="Sl_MIRQ" SIGNAME="plb_v46_0_Sl_MIRQ" VECFORMULA="[0:C_SPLB_NUM_MASTERS-1]"/> + <PORT BUS="PORTA" DEF_SIGNAME="xps_bram_if_cntlr_1_port_BRAM_Rst" DIR="O" MPD_INDEX="42" NAME="BRAM_Rst" SIGNAME="xps_bram_if_cntlr_1_port_BRAM_Rst"/> + <PORT BUS="PORTA" CLKFREQUENCY="125000000" DEF_SIGNAME="xps_bram_if_cntlr_1_port_BRAM_Clk" DIR="O" MPD_INDEX="43" NAME="BRAM_Clk" SIGNAME="xps_bram_if_cntlr_1_port_BRAM_Clk"/> + <PORT BUS="PORTA" DEF_SIGNAME="xps_bram_if_cntlr_1_port_BRAM_EN" DIR="O" MPD_INDEX="44" NAME="BRAM_EN" SIGNAME="xps_bram_if_cntlr_1_port_BRAM_EN"/> + <PORT BUS="PORTA" DEF_SIGNAME="xps_bram_if_cntlr_1_port_BRAM_WEN" DIR="O" MPD_INDEX="45" NAME="BRAM_WEN" SIGNAME="xps_bram_if_cntlr_1_port_BRAM_WEN" VECFORMULA="[0:(C_SPLB_NATIVE_DWIDTH/8)-1]"/> + <PORT BUS="PORTA" DEF_SIGNAME="xps_bram_if_cntlr_1_port_BRAM_Addr" DIR="O" MPD_INDEX="46" NAME="BRAM_Addr" SIGNAME="xps_bram_if_cntlr_1_port_BRAM_Addr" VECFORMULA="[0:C_SPLB_AWIDTH-1]"/> + <PORT BUS="PORTA" DEF_SIGNAME="xps_bram_if_cntlr_1_port_BRAM_Din" DIR="I" MPD_INDEX="47" NAME="BRAM_Din" SIGNAME="xps_bram_if_cntlr_1_port_BRAM_Din" VECFORMULA="[0:C_SPLB_NATIVE_DWIDTH-1]"/> + <PORT BUS="PORTA" DEF_SIGNAME="xps_bram_if_cntlr_1_port_BRAM_Dout" DIR="O" MPD_INDEX="48" NAME="BRAM_Dout" SIGNAME="xps_bram_if_cntlr_1_port_BRAM_Dout" VECFORMULA="[0:C_SPLB_NATIVE_DWIDTH-1]"/> + <BUSINTERFACE BUSNAME="plb_v46_0" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INMHS="TRUE" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE"/> + <BUSINTERFACE BUSNAME="xps_bram_if_cntlr_1_port" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INMHS="TRUE" MPD_INDEX="1" NAME="PORTA" TYPE="INITIATOR"/> + </MODULE> + <MODULE HWVERSION="1.00.a" INSTANCE="xps_bram_if_cntlr_1_bram" IPTYPE="PERIPHERAL" MHS_INDEX="3" MODCLASS="MEMORY" MODTYPE="bram_block"> + <DESCRIPTION TYPE="SHORT">Block RAM (BRAM) Block</DESCRIPTION> + <DESCRIPTION TYPE="LONG">The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.</DESCRIPTION> + <DOCUMENTATION> + <DOCUMENT SOURCE="c:/devtools/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/bram_block_v1_00_a/doc/bram_block.pdf" TYPE="IP"/> + </DOCUMENTATION> + <LICENSEINFO ICON_NAME="ps_core_preferred"/> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_MEMSIZE" TYPE="integer" VALUE="0x2000"> + <DESCRIPTION>Size of BRAM(s) in Bytes</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_PORT_DWIDTH" TYPE="integer" VALUE="64"> + <DESCRIPTION>Data Width of Port A and B</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="2" NAME="C_PORT_AWIDTH" TYPE="integer" VALUE="32"> + <DESCRIPTION>Address Width of Port A and B</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_NUM_WE" TYPE="integer" VALUE="8"> + <DESCRIPTION>Number of Byte Write Enables</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="4" NAME="C_FAMILY" TYPE="string" VALUE="virtex5"> + <DESCRIPTION>Device Family</DESCRIPTION> + </PARAMETER> + <PORT BUS="PORTA" DEF_SIGNAME="xps_bram_if_cntlr_1_port_BRAM_Rst" DIR="I" MPD_INDEX="0" NAME="BRAM_Rst_A" SIGNAME="xps_bram_if_cntlr_1_port_BRAM_Rst"/> + <PORT BUS="PORTA" CLKFREQUENCY="125000000" DEF_SIGNAME="xps_bram_if_cntlr_1_port_BRAM_Clk" DIR="I" MPD_INDEX="1" NAME="BRAM_Clk_A" SIGIS="CLK" SIGNAME="xps_bram_if_cntlr_1_port_BRAM_Clk"/> + <PORT BUS="PORTA" DEF_SIGNAME="xps_bram_if_cntlr_1_port_BRAM_EN" DIR="I" MPD_INDEX="2" NAME="BRAM_EN_A" SIGNAME="xps_bram_if_cntlr_1_port_BRAM_EN"/> + <PORT BUS="PORTA" DEF_SIGNAME="xps_bram_if_cntlr_1_port_BRAM_WEN" DIR="I" MPD_INDEX="3" NAME="BRAM_WEN_A" SIGNAME="xps_bram_if_cntlr_1_port_BRAM_WEN" VECFORMULA="[0:C_NUM_WE-1]"/> + <PORT BUS="PORTA" DEF_SIGNAME="xps_bram_if_cntlr_1_port_BRAM_Addr" DIR="I" MPD_INDEX="4" NAME="BRAM_Addr_A" SIGNAME="xps_bram_if_cntlr_1_port_BRAM_Addr" VECFORMULA="[0:C_PORT_AWIDTH-1]"/> + <PORT BUS="PORTA" DEF_SIGNAME="xps_bram_if_cntlr_1_port_BRAM_Din" DIR="O" MPD_INDEX="5" NAME="BRAM_Din_A" SIGNAME="xps_bram_if_cntlr_1_port_BRAM_Din" VECFORMULA="[0:C_PORT_DWIDTH-1]"/> + <PORT BUS="PORTA" DEF_SIGNAME="xps_bram_if_cntlr_1_port_BRAM_Dout" DIR="I" MPD_INDEX="6" NAME="BRAM_Dout_A" SIGNAME="xps_bram_if_cntlr_1_port_BRAM_Dout" VECFORMULA="[0:C_PORT_DWIDTH-1]"/> + <PORT BUS="PORTB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="7" NAME="BRAM_Rst_B" SIGNAME="__NOC__"/> + <PORT BUS="PORTB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="8" NAME="BRAM_Clk_B" SIGIS="CLK" SIGNAME="__NOC__"/> + <PORT BUS="PORTB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="9" NAME="BRAM_EN_B" SIGNAME="__NOC__"/> + <PORT BUS="PORTB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="10" NAME="BRAM_WEN_B" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_WE-1]"/> + <PORT BUS="PORTB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="11" NAME="BRAM_Addr_B" SIGNAME="__NOC__" VECFORMULA="[0:C_PORT_AWIDTH-1]"/> + <PORT BUS="PORTB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="12" NAME="BRAM_Din_B" SIGNAME="__NOC__" VECFORMULA="[0:C_PORT_DWIDTH-1]"/> + <PORT BUS="PORTB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="13" NAME="BRAM_Dout_B" SIGNAME="__NOC__" VECFORMULA="[0:C_PORT_DWIDTH-1]"/> + <BUSINTERFACE BUSNAME="xps_bram_if_cntlr_1_port" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INMHS="TRUE" MPD_INDEX="0" NAME="PORTA" TYPE="TARGET"/> + <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" MPD_INDEX="1" NAME="PORTB" TYPE="TARGET"/> + </MODULE> + <MODULE HWVERSION="1.01.a" INSTANCE="RS232_Uart_1" IPTYPE="PERIPHERAL" MHS_INDEX="4" MODCLASS="PERIPHERAL" MODTYPE="xps_uartlite"> + <DESCRIPTION TYPE="SHORT">XPS UART (Lite)</DESCRIPTION> + <DESCRIPTION TYPE="LONG">Generic UART (Universal Asynchronous Receiver/Transmitter) for PLBV46 bus.</DESCRIPTION> + <DOCUMENTATION> + <DOCUMENT SOURCE="c:/devtools/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/xps_uartlite_v1_01_a/doc/xps_uartlite.pdf" TYPE="IP"/> + </DOCUMENTATION> + <LICENSEINFO ICON_NAME="ps_core_preferred"/> + <PARAMETER MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex5"> + <DESCRIPTION>Device Family</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_SPLB_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="125000000"> + <DESCRIPTION>Clock Frequency of PLB Slave</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" MPD_INDEX="2" NAME="C_BASEADDR" TYPE="std_logic_vector(0 to 31)" VALUE="0x84000000"> + <DESCRIPTION>Base Address</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" MPD_INDEX="3" NAME="C_HIGHADDR" TYPE="std_logic_vector(0 to 31)" VALUE="0x8400ffff"> + <DESCRIPTION>High Address</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="4" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32"> + <DESCRIPTION>PLB Address Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="128"> + <DESCRIPTION>PLB Data Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="6" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="7" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="8" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Number of PLB Masters</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="9" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="10" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"> + <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="11" NAME="C_BAUDRATE" TYPE="INTEGER" VALUE="9600"> + <DESCRIPTION>UART Lite Baud Rate </DESCRIPTION> + <DESCRIPTION>Baud Rate</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="12" NAME="C_DATA_BITS" TYPE="INTEGER" VALUE="8"> + <DESCRIPTION>Number of Data Bits in a Serial Frame</DESCRIPTION> + <DESCRIPTION>Data Bits</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="13" NAME="C_USE_PARITY" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Use Parity </DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="14" NAME="C_ODD_PARITY" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Parity Type </DESCRIPTION> + </PARAMETER> + <MEMORYMAP> + <MEMRANGE BASEDECIMAL="2214592512" BASENAME="C_BASEADDR" BASEVALUE="0x84000000" HIGHDECIMAL="2214658047" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8400ffff" MEMTYPE="REGISTER" MINSIZE="0x10" SIZE="65536" SIZEABRV="64K"> + <SLVINTERFACES> + <BUSINTERFACE NAME="SPLB"/> + </SLVINTERFACES> + </MEMRANGE> + </MEMORYMAP> + <PORT DIR="I" IS_INMHS="TRUE" MHS_INDEX="0" MPD_INDEX="42" NAME="RX" SIGNAME="fpga_0_RS232_Uart_1_RX_pin"> + <DESCRIPTION>Serial Data In</DESCRIPTION> + </PORT> + <PORT DIR="O" IS_INMHS="TRUE" MHS_INDEX="1" MPD_INDEX="43" NAME="TX" SIGNAME="fpga_0_RS232_Uart_1_TX_pin"> + <DESCRIPTION>Serial Data Out</DESCRIPTION> + </PORT> + <PORT DIR="O" IS_INMHS="TRUE" MHS_INDEX="2" MPD_INDEX="44" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="RS232_Uart_1_Interrupt"/> + <PORT BUS="SPLB" CLKFREQUENCY="125000000" DEF_SIGNAME="clk_125_0000MHzPLL0_ADJUST" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_125_0000MHzPLL0_ADJUST"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="plb_v46_0_SPLB_Rst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_ABus" DIR="I" MPD_INDEX="2" NAME="PLB_ABus" SIGNAME="plb_v46_0_PLB_ABus" VECFORMULA="[0:31]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_PAValid" DIR="I" MPD_INDEX="3" NAME="PLB_PAValid" SIGNAME="plb_v46_0_PLB_PAValid"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_masterID" DIR="I" MPD_INDEX="4" NAME="PLB_masterID" SIGNAME="plb_v46_0_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_RNW" DIR="I" MPD_INDEX="5" NAME="PLB_RNW" SIGNAME="plb_v46_0_PLB_RNW"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_BE" DIR="I" MPD_INDEX="6" NAME="PLB_BE" SIGNAME="plb_v46_0_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_size" DIR="I" MPD_INDEX="7" NAME="PLB_size" SIGNAME="plb_v46_0_PLB_size" VECFORMULA="[0:3]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_type" DIR="I" MPD_INDEX="8" NAME="PLB_type" SIGNAME="plb_v46_0_PLB_type" VECFORMULA="[0:2]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrDBus" DIR="I" MPD_INDEX="9" NAME="PLB_wrDBus" SIGNAME="plb_v46_0_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_UABus" DIR="I" MPD_INDEX="10" NAME="PLB_UABus" SIGNAME="plb_v46_0_PLB_UABus" VECFORMULA="[0:31]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_SAValid" DIR="I" MPD_INDEX="11" NAME="PLB_SAValid" SIGNAME="plb_v46_0_PLB_SAValid"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPrim" DIR="I" MPD_INDEX="12" NAME="PLB_rdPrim" SIGNAME="plb_v46_0_PLB_rdPrim"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPrim" DIR="I" MPD_INDEX="13" NAME="PLB_wrPrim" SIGNAME="plb_v46_0_PLB_wrPrim"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_abort" DIR="I" MPD_INDEX="14" NAME="PLB_abort" SIGNAME="plb_v46_0_PLB_abort"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_busLock" DIR="I" MPD_INDEX="15" NAME="PLB_busLock" SIGNAME="plb_v46_0_PLB_busLock"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_MSize" DIR="I" MPD_INDEX="16" NAME="PLB_MSize" SIGNAME="plb_v46_0_PLB_MSize" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_lockErr" DIR="I" MPD_INDEX="17" NAME="PLB_lockErr" SIGNAME="plb_v46_0_PLB_lockErr"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrBurst" DIR="I" MPD_INDEX="18" NAME="PLB_wrBurst" SIGNAME="plb_v46_0_PLB_wrBurst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdBurst" DIR="I" MPD_INDEX="19" NAME="PLB_rdBurst" SIGNAME="plb_v46_0_PLB_rdBurst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPendReq" DIR="I" MPD_INDEX="20" NAME="PLB_wrPendReq" SIGNAME="plb_v46_0_PLB_wrPendReq"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPendReq" DIR="I" MPD_INDEX="21" NAME="PLB_rdPendReq" SIGNAME="plb_v46_0_PLB_rdPendReq"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPendPri" DIR="I" MPD_INDEX="22" NAME="PLB_wrPendPri" SIGNAME="plb_v46_0_PLB_wrPendPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPendPri" DIR="I" MPD_INDEX="23" NAME="PLB_rdPendPri" SIGNAME="plb_v46_0_PLB_rdPendPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_reqPri" DIR="I" MPD_INDEX="24" NAME="PLB_reqPri" SIGNAME="plb_v46_0_PLB_reqPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_TAttribute" DIR="I" MPD_INDEX="25" NAME="PLB_TAttribute" SIGNAME="plb_v46_0_PLB_TAttribute" VECFORMULA="[0:15]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_addrAck" DIR="O" MPD_INDEX="26" NAME="Sl_addrAck" SIGNAME="plb_v46_0_Sl_addrAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_SSize" DIR="O" MPD_INDEX="27" NAME="Sl_SSize" SIGNAME="plb_v46_0_Sl_SSize" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wait" DIR="O" MPD_INDEX="28" NAME="Sl_wait" SIGNAME="plb_v46_0_Sl_wait"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rearbitrate" DIR="O" MPD_INDEX="29" NAME="Sl_rearbitrate" SIGNAME="plb_v46_0_Sl_rearbitrate"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrDAck" DIR="O" MPD_INDEX="30" NAME="Sl_wrDAck" SIGNAME="plb_v46_0_Sl_wrDAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrComp" DIR="O" MPD_INDEX="31" NAME="Sl_wrComp" SIGNAME="plb_v46_0_Sl_wrComp"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdDBus" DIR="O" MPD_INDEX="32" NAME="Sl_rdDBus" SIGNAME="plb_v46_0_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdDAck" DIR="O" MPD_INDEX="33" NAME="Sl_rdDAck" SIGNAME="plb_v46_0_Sl_rdDAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdComp" DIR="O" MPD_INDEX="34" NAME="Sl_rdComp" SIGNAME="plb_v46_0_Sl_rdComp"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MBusy" DIR="O" MPD_INDEX="35" NAME="Sl_MBusy" SIGNAME="plb_v46_0_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MWrErr" DIR="O" MPD_INDEX="36" NAME="Sl_MWrErr" SIGNAME="plb_v46_0_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MRdErr" DIR="O" MPD_INDEX="37" NAME="Sl_MRdErr" SIGNAME="plb_v46_0_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrBTerm" DIR="O" MPD_INDEX="38" NAME="Sl_wrBTerm" SIGNAME="plb_v46_0_Sl_wrBTerm"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdWdAddr" DIR="O" MPD_INDEX="39" NAME="Sl_rdWdAddr" SIGNAME="plb_v46_0_Sl_rdWdAddr" VECFORMULA="[0:3]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdBTerm" DIR="O" MPD_INDEX="40" NAME="Sl_rdBTerm" SIGNAME="plb_v46_0_Sl_rdBTerm"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MIRQ" DIR="O" MPD_INDEX="41" NAME="Sl_MIRQ" SIGNAME="plb_v46_0_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <BUSINTERFACE BUSNAME="plb_v46_0" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INMHS="TRUE" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE"/> + <INTERRUPTINFO TYPE="SOURCE"> + <TARGET INTC_INDEX="0" PRIORITY="1"/> + </INTERRUPTINFO> + </MODULE> + <MODULE HWVERSION="2.00.a" INSTANCE="LEDs_8Bit" IPTYPE="PERIPHERAL" MHS_INDEX="5" MODCLASS="PERIPHERAL" MODTYPE="xps_gpio"> + <DESCRIPTION TYPE="SHORT">XPS General Purpose IO</DESCRIPTION> + <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the PLBV46 bus.</DESCRIPTION> + <DOCUMENTATION> + <DOCUMENT SOURCE="c:/devtools/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/xps_gpio_v2_00_a/doc/xps_gpio.pdf" TYPE="IP"/> + </DOCUMENTATION> + <LICENSEINFO ICON_NAME="ps_core_preferred"/> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" MPD_INDEX="0" NAME="C_BASEADDR" TYPE="std_logic_vector(0 to 31)" VALUE="0x81440000"> + <DESCRIPTION>Base Address</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" MPD_INDEX="1" NAME="C_HIGHADDR" TYPE="std_logic_vector(0 to 31)" VALUE="0x8144ffff"> + <DESCRIPTION>High Address</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="2" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32"> + <DESCRIPTION>PLB Address Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="128"> + <DESCRIPTION>PLB Data Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="4" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="5" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="6" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Number of PLB Masters</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="7" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"> + <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="8" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="9" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex5"> + <DESCRIPTION>Device Family</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="10" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Channel 1 is Input Only </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="11" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Channel 2 is Input Only </DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="12" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="8"> + <DESCRIPTION>GPIO Data Channel Width</DESCRIPTION> + <DESCRIPTION>GPIO Data Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="13" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32"> + <DESCRIPTION>GPIO2 Data Channel Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="14" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>GPIO Supports Interrupts</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="15" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000"> + <DESCRIPTION>Channel 1 Data Out Default Value </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="16" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff"> + <DESCRIPTION>Channel 1 Tri-state Default Value </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="17" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Enable Channel 2 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="18" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000"> + <DESCRIPTION>Channel 2 Data Out Default Value </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="19" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff"> + <DESCRIPTION>Channel 2 Tri-state Default Value </DESCRIPTION> + </PARAMETER> + <MEMORYMAP> + <MEMRANGE BASEDECIMAL="2168717312" BASENAME="C_BASEADDR" BASEVALUE="0x81440000" HIGHDECIMAL="2168782847" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8144ffff" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K"> + <SLVINTERFACES> + <BUSINTERFACE NAME="SPLB"/> + </SLVINTERFACES> + </MEMRANGE> + </MEMORYMAP> + <PORT DIR="IO" ENDIAN="BIG" IS_INMHS="TRUE" LSB="0" MHS_INDEX="0" MPD_INDEX="49" MSB="7" NAME="GPIO_IO" SIGNAME="fpga_0_LEDs_8Bit_GPIO_IO_pin" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"> + <DESCRIPTION>GPIO1 Data IO</DESCRIPTION> + </PORT> + <PORT BUS="SPLB" CLKFREQUENCY="125000000" DEF_SIGNAME="clk_125_0000MHzPLL0_ADJUST" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_125_0000MHzPLL0_ADJUST"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="plb_v46_0_SPLB_Rst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_ABus" DIR="I" MPD_INDEX="2" NAME="PLB_ABus" SIGNAME="plb_v46_0_PLB_ABus" VECFORMULA="[0:31]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_UABus" DIR="I" MPD_INDEX="3" NAME="PLB_UABus" SIGNAME="plb_v46_0_PLB_UABus" VECFORMULA="[0:31]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_PAValid" DIR="I" MPD_INDEX="4" NAME="PLB_PAValid" SIGNAME="plb_v46_0_PLB_PAValid"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_SAValid" DIR="I" MPD_INDEX="5" NAME="PLB_SAValid" SIGNAME="plb_v46_0_PLB_SAValid"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPrim" DIR="I" MPD_INDEX="6" NAME="PLB_rdPrim" SIGNAME="plb_v46_0_PLB_rdPrim"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPrim" DIR="I" MPD_INDEX="7" NAME="PLB_wrPrim" SIGNAME="plb_v46_0_PLB_wrPrim"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_masterID" DIR="I" MPD_INDEX="8" NAME="PLB_masterID" SIGNAME="plb_v46_0_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_abort" DIR="I" MPD_INDEX="9" NAME="PLB_abort" SIGNAME="plb_v46_0_PLB_abort"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_busLock" DIR="I" MPD_INDEX="10" NAME="PLB_busLock" SIGNAME="plb_v46_0_PLB_busLock"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_RNW" DIR="I" MPD_INDEX="11" NAME="PLB_RNW" SIGNAME="plb_v46_0_PLB_RNW"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_BE" DIR="I" MPD_INDEX="12" NAME="PLB_BE" SIGNAME="plb_v46_0_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_MSize" DIR="I" MPD_INDEX="13" NAME="PLB_MSize" SIGNAME="plb_v46_0_PLB_MSize" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_size" DIR="I" MPD_INDEX="14" NAME="PLB_size" SIGNAME="plb_v46_0_PLB_size" VECFORMULA="[0:3]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_type" DIR="I" MPD_INDEX="15" NAME="PLB_type" SIGNAME="plb_v46_0_PLB_type" VECFORMULA="[0:2]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_lockErr" DIR="I" MPD_INDEX="16" NAME="PLB_lockErr" SIGNAME="plb_v46_0_PLB_lockErr"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrDBus" DIR="I" MPD_INDEX="17" NAME="PLB_wrDBus" SIGNAME="plb_v46_0_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrBurst" DIR="I" MPD_INDEX="18" NAME="PLB_wrBurst" SIGNAME="plb_v46_0_PLB_wrBurst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdBurst" DIR="I" MPD_INDEX="19" NAME="PLB_rdBurst" SIGNAME="plb_v46_0_PLB_rdBurst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPendReq" DIR="I" MPD_INDEX="20" NAME="PLB_wrPendReq" SIGNAME="plb_v46_0_PLB_wrPendReq"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPendReq" DIR="I" MPD_INDEX="21" NAME="PLB_rdPendReq" SIGNAME="plb_v46_0_PLB_rdPendReq"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPendPri" DIR="I" MPD_INDEX="22" NAME="PLB_wrPendPri" SIGNAME="plb_v46_0_PLB_wrPendPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPendPri" DIR="I" MPD_INDEX="23" NAME="PLB_rdPendPri" SIGNAME="plb_v46_0_PLB_rdPendPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_reqPri" DIR="I" MPD_INDEX="24" NAME="PLB_reqPri" SIGNAME="plb_v46_0_PLB_reqPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_TAttribute" DIR="I" MPD_INDEX="25" NAME="PLB_TAttribute" SIGNAME="plb_v46_0_PLB_TAttribute" VECFORMULA="[0:15]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_addrAck" DIR="O" MPD_INDEX="26" NAME="Sl_addrAck" SIGNAME="plb_v46_0_Sl_addrAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_SSize" DIR="O" MPD_INDEX="27" NAME="Sl_SSize" SIGNAME="plb_v46_0_Sl_SSize" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wait" DIR="O" MPD_INDEX="28" NAME="Sl_wait" SIGNAME="plb_v46_0_Sl_wait"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rearbitrate" DIR="O" MPD_INDEX="29" NAME="Sl_rearbitrate" SIGNAME="plb_v46_0_Sl_rearbitrate"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrDAck" DIR="O" MPD_INDEX="30" NAME="Sl_wrDAck" SIGNAME="plb_v46_0_Sl_wrDAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrComp" DIR="O" MPD_INDEX="31" NAME="Sl_wrComp" SIGNAME="plb_v46_0_Sl_wrComp"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrBTerm" DIR="O" MPD_INDEX="32" NAME="Sl_wrBTerm" SIGNAME="plb_v46_0_Sl_wrBTerm"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdDBus" DIR="O" MPD_INDEX="33" NAME="Sl_rdDBus" SIGNAME="plb_v46_0_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdWdAddr" DIR="O" MPD_INDEX="34" NAME="Sl_rdWdAddr" SIGNAME="plb_v46_0_Sl_rdWdAddr" VECFORMULA="[0:3]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdDAck" DIR="O" MPD_INDEX="35" NAME="Sl_rdDAck" SIGNAME="plb_v46_0_Sl_rdDAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdComp" DIR="O" MPD_INDEX="36" NAME="Sl_rdComp" SIGNAME="plb_v46_0_Sl_rdComp"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdBTerm" DIR="O" MPD_INDEX="37" NAME="Sl_rdBTerm" SIGNAME="plb_v46_0_Sl_rdBTerm"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MBusy" DIR="O" MPD_INDEX="38" NAME="Sl_MBusy" SIGNAME="plb_v46_0_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MWrErr" DIR="O" MPD_INDEX="39" NAME="Sl_MWrErr" SIGNAME="plb_v46_0_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MRdErr" DIR="O" MPD_INDEX="40" NAME="Sl_MRdErr" SIGNAME="plb_v46_0_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MIRQ" DIR="O" MPD_INDEX="41" NAME="Sl_MIRQ" SIGNAME="plb_v46_0_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="42" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/> + <PORT DIR="I" MPD_INDEX="43" NAME="GPIO_IO_I" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/> + <PORT DIR="O" MPD_INDEX="44" NAME="GPIO_IO_O" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/> + <PORT DIR="O" MPD_INDEX="45" NAME="GPIO_IO_T" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/> + <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="46" NAME="GPIO2_IO_I" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/> + <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="47" NAME="GPIO2_IO_O" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/> + <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="48" NAME="GPIO2_IO_T" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/> + <PORT DIR="IO" IS_VALID="FALSE" MPD_INDEX="50" NAME="GPIO2_IO" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"> + <DESCRIPTION>GPIO2 Data IO</DESCRIPTION> + </PORT> + <BUSINTERFACE BUSNAME="plb_v46_0" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INMHS="TRUE" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE"/> + </MODULE> + <MODULE HWVERSION="2.00.a" INSTANCE="LEDs_Positions" IPTYPE="PERIPHERAL" MHS_INDEX="6" MODCLASS="PERIPHERAL" MODTYPE="xps_gpio"> + <DESCRIPTION TYPE="SHORT">XPS General Purpose IO</DESCRIPTION> + <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the PLBV46 bus.</DESCRIPTION> + <DOCUMENTATION> + <DOCUMENT SOURCE="c:/devtools/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/xps_gpio_v2_00_a/doc/xps_gpio.pdf" TYPE="IP"/> + </DOCUMENTATION> + <LICENSEINFO ICON_NAME="ps_core_preferred"/> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" MPD_INDEX="0" NAME="C_BASEADDR" TYPE="std_logic_vector(0 to 31)" VALUE="0x81420000"> + <DESCRIPTION>Base Address</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" MPD_INDEX="1" NAME="C_HIGHADDR" TYPE="std_logic_vector(0 to 31)" VALUE="0x8142ffff"> + <DESCRIPTION>High Address</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="2" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32"> + <DESCRIPTION>PLB Address Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="128"> + <DESCRIPTION>PLB Data Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="4" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="5" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="6" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Number of PLB Masters</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="7" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"> + <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="8" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="9" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex5"> + <DESCRIPTION>Device Family</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="10" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Channel 1 is Input Only </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="11" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Channel 2 is Input Only </DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="12" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="5"> + <DESCRIPTION>GPIO Data Channel Width</DESCRIPTION> + <DESCRIPTION>GPIO Data Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="13" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32"> + <DESCRIPTION>GPIO2 Data Channel Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="14" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>GPIO Supports Interrupts</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="15" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000"> + <DESCRIPTION>Channel 1 Data Out Default Value </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="16" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff"> + <DESCRIPTION>Channel 1 Tri-state Default Value </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="17" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Enable Channel 2 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="18" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000"> + <DESCRIPTION>Channel 2 Data Out Default Value </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="19" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff"> + <DESCRIPTION>Channel 2 Tri-state Default Value </DESCRIPTION> + </PARAMETER> + <MEMORYMAP> + <MEMRANGE BASEDECIMAL="2168586240" BASENAME="C_BASEADDR" BASEVALUE="0x81420000" HIGHDECIMAL="2168651775" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8142ffff" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K"> + <SLVINTERFACES> + <BUSINTERFACE NAME="SPLB"/> + </SLVINTERFACES> + </MEMRANGE> + </MEMORYMAP> + <PORT DIR="IO" ENDIAN="BIG" IS_INMHS="TRUE" LSB="0" MHS_INDEX="0" MPD_INDEX="49" MSB="4" NAME="GPIO_IO" SIGNAME="fpga_0_LEDs_Positions_GPIO_IO_pin" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"> + <DESCRIPTION>GPIO1 Data IO</DESCRIPTION> + </PORT> + <PORT BUS="SPLB" CLKFREQUENCY="125000000" DEF_SIGNAME="clk_125_0000MHzPLL0_ADJUST" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_125_0000MHzPLL0_ADJUST"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="plb_v46_0_SPLB_Rst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_ABus" DIR="I" MPD_INDEX="2" NAME="PLB_ABus" SIGNAME="plb_v46_0_PLB_ABus" VECFORMULA="[0:31]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_UABus" DIR="I" MPD_INDEX="3" NAME="PLB_UABus" SIGNAME="plb_v46_0_PLB_UABus" VECFORMULA="[0:31]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_PAValid" DIR="I" MPD_INDEX="4" NAME="PLB_PAValid" SIGNAME="plb_v46_0_PLB_PAValid"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_SAValid" DIR="I" MPD_INDEX="5" NAME="PLB_SAValid" SIGNAME="plb_v46_0_PLB_SAValid"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPrim" DIR="I" MPD_INDEX="6" NAME="PLB_rdPrim" SIGNAME="plb_v46_0_PLB_rdPrim"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPrim" DIR="I" MPD_INDEX="7" NAME="PLB_wrPrim" SIGNAME="plb_v46_0_PLB_wrPrim"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_masterID" DIR="I" MPD_INDEX="8" NAME="PLB_masterID" SIGNAME="plb_v46_0_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_abort" DIR="I" MPD_INDEX="9" NAME="PLB_abort" SIGNAME="plb_v46_0_PLB_abort"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_busLock" DIR="I" MPD_INDEX="10" NAME="PLB_busLock" SIGNAME="plb_v46_0_PLB_busLock"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_RNW" DIR="I" MPD_INDEX="11" NAME="PLB_RNW" SIGNAME="plb_v46_0_PLB_RNW"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_BE" DIR="I" MPD_INDEX="12" NAME="PLB_BE" SIGNAME="plb_v46_0_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_MSize" DIR="I" MPD_INDEX="13" NAME="PLB_MSize" SIGNAME="plb_v46_0_PLB_MSize" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_size" DIR="I" MPD_INDEX="14" NAME="PLB_size" SIGNAME="plb_v46_0_PLB_size" VECFORMULA="[0:3]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_type" DIR="I" MPD_INDEX="15" NAME="PLB_type" SIGNAME="plb_v46_0_PLB_type" VECFORMULA="[0:2]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_lockErr" DIR="I" MPD_INDEX="16" NAME="PLB_lockErr" SIGNAME="plb_v46_0_PLB_lockErr"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrDBus" DIR="I" MPD_INDEX="17" NAME="PLB_wrDBus" SIGNAME="plb_v46_0_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrBurst" DIR="I" MPD_INDEX="18" NAME="PLB_wrBurst" SIGNAME="plb_v46_0_PLB_wrBurst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdBurst" DIR="I" MPD_INDEX="19" NAME="PLB_rdBurst" SIGNAME="plb_v46_0_PLB_rdBurst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPendReq" DIR="I" MPD_INDEX="20" NAME="PLB_wrPendReq" SIGNAME="plb_v46_0_PLB_wrPendReq"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPendReq" DIR="I" MPD_INDEX="21" NAME="PLB_rdPendReq" SIGNAME="plb_v46_0_PLB_rdPendReq"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPendPri" DIR="I" MPD_INDEX="22" NAME="PLB_wrPendPri" SIGNAME="plb_v46_0_PLB_wrPendPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPendPri" DIR="I" MPD_INDEX="23" NAME="PLB_rdPendPri" SIGNAME="plb_v46_0_PLB_rdPendPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_reqPri" DIR="I" MPD_INDEX="24" NAME="PLB_reqPri" SIGNAME="plb_v46_0_PLB_reqPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_TAttribute" DIR="I" MPD_INDEX="25" NAME="PLB_TAttribute" SIGNAME="plb_v46_0_PLB_TAttribute" VECFORMULA="[0:15]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_addrAck" DIR="O" MPD_INDEX="26" NAME="Sl_addrAck" SIGNAME="plb_v46_0_Sl_addrAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_SSize" DIR="O" MPD_INDEX="27" NAME="Sl_SSize" SIGNAME="plb_v46_0_Sl_SSize" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wait" DIR="O" MPD_INDEX="28" NAME="Sl_wait" SIGNAME="plb_v46_0_Sl_wait"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rearbitrate" DIR="O" MPD_INDEX="29" NAME="Sl_rearbitrate" SIGNAME="plb_v46_0_Sl_rearbitrate"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrDAck" DIR="O" MPD_INDEX="30" NAME="Sl_wrDAck" SIGNAME="plb_v46_0_Sl_wrDAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrComp" DIR="O" MPD_INDEX="31" NAME="Sl_wrComp" SIGNAME="plb_v46_0_Sl_wrComp"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrBTerm" DIR="O" MPD_INDEX="32" NAME="Sl_wrBTerm" SIGNAME="plb_v46_0_Sl_wrBTerm"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdDBus" DIR="O" MPD_INDEX="33" NAME="Sl_rdDBus" SIGNAME="plb_v46_0_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdWdAddr" DIR="O" MPD_INDEX="34" NAME="Sl_rdWdAddr" SIGNAME="plb_v46_0_Sl_rdWdAddr" VECFORMULA="[0:3]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdDAck" DIR="O" MPD_INDEX="35" NAME="Sl_rdDAck" SIGNAME="plb_v46_0_Sl_rdDAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdComp" DIR="O" MPD_INDEX="36" NAME="Sl_rdComp" SIGNAME="plb_v46_0_Sl_rdComp"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdBTerm" DIR="O" MPD_INDEX="37" NAME="Sl_rdBTerm" SIGNAME="plb_v46_0_Sl_rdBTerm"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MBusy" DIR="O" MPD_INDEX="38" NAME="Sl_MBusy" SIGNAME="plb_v46_0_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MWrErr" DIR="O" MPD_INDEX="39" NAME="Sl_MWrErr" SIGNAME="plb_v46_0_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MRdErr" DIR="O" MPD_INDEX="40" NAME="Sl_MRdErr" SIGNAME="plb_v46_0_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MIRQ" DIR="O" MPD_INDEX="41" NAME="Sl_MIRQ" SIGNAME="plb_v46_0_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="42" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/> + <PORT DIR="I" MPD_INDEX="43" NAME="GPIO_IO_I" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/> + <PORT DIR="O" MPD_INDEX="44" NAME="GPIO_IO_O" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/> + <PORT DIR="O" MPD_INDEX="45" NAME="GPIO_IO_T" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/> + <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="46" NAME="GPIO2_IO_I" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/> + <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="47" NAME="GPIO2_IO_O" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/> + <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="48" NAME="GPIO2_IO_T" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/> + <PORT DIR="IO" IS_VALID="FALSE" MPD_INDEX="50" NAME="GPIO2_IO" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"> + <DESCRIPTION>GPIO2 Data IO</DESCRIPTION> + </PORT> + <BUSINTERFACE BUSNAME="plb_v46_0" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INMHS="TRUE" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE"/> + </MODULE> + <MODULE HWVERSION="2.00.a" INSTANCE="Push_Buttons_5Bit" IPTYPE="PERIPHERAL" MHS_INDEX="7" MODCLASS="PERIPHERAL" MODTYPE="xps_gpio"> + <DESCRIPTION TYPE="SHORT">XPS General Purpose IO</DESCRIPTION> + <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the PLBV46 bus.</DESCRIPTION> + <DOCUMENTATION> + <DOCUMENT SOURCE="c:/devtools/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/xps_gpio_v2_00_a/doc/xps_gpio.pdf" TYPE="IP"/> + </DOCUMENTATION> + <LICENSEINFO ICON_NAME="ps_core_preferred"/> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" MPD_INDEX="0" NAME="C_BASEADDR" TYPE="std_logic_vector(0 to 31)" VALUE="0x81400000"> + <DESCRIPTION>Base Address</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" MPD_INDEX="1" NAME="C_HIGHADDR" TYPE="std_logic_vector(0 to 31)" VALUE="0x8140ffff"> + <DESCRIPTION>High Address</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="2" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32"> + <DESCRIPTION>PLB Address Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="128"> + <DESCRIPTION>PLB Data Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="4" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="5" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="6" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Number of PLB Masters</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="7" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"> + <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="8" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="9" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex5"> + <DESCRIPTION>Device Family</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="10" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Channel 1 is Input Only </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="11" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Channel 2 is Input Only </DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="12" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="5"> + <DESCRIPTION>GPIO Data Channel Width</DESCRIPTION> + <DESCRIPTION>GPIO Data Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="13" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32"> + <DESCRIPTION>GPIO2 Data Channel Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="14" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>GPIO Supports Interrupts</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="15" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000"> + <DESCRIPTION>Channel 1 Data Out Default Value </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="16" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff"> + <DESCRIPTION>Channel 1 Tri-state Default Value </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="17" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Enable Channel 2 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="18" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000"> + <DESCRIPTION>Channel 2 Data Out Default Value </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="19" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff"> + <DESCRIPTION>Channel 2 Tri-state Default Value </DESCRIPTION> + </PARAMETER> + <MEMORYMAP> + <MEMRANGE BASEDECIMAL="2168455168" BASENAME="C_BASEADDR" BASEVALUE="0x81400000" HIGHDECIMAL="2168520703" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8140ffff" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K"> + <SLVINTERFACES> + <BUSINTERFACE NAME="SPLB"/> + </SLVINTERFACES> + </MEMRANGE> + </MEMORYMAP> + <PORT DIR="IO" ENDIAN="BIG" IS_INMHS="TRUE" LSB="0" MHS_INDEX="0" MPD_INDEX="49" MSB="4" NAME="GPIO_IO" SIGNAME="fpga_0_Push_Buttons_5Bit_GPIO_IO_pin" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"> + <DESCRIPTION>GPIO1 Data IO</DESCRIPTION> + </PORT> + <PORT BUS="SPLB" CLKFREQUENCY="125000000" DEF_SIGNAME="clk_125_0000MHzPLL0_ADJUST" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_125_0000MHzPLL0_ADJUST"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="plb_v46_0_SPLB_Rst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_ABus" DIR="I" MPD_INDEX="2" NAME="PLB_ABus" SIGNAME="plb_v46_0_PLB_ABus" VECFORMULA="[0:31]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_UABus" DIR="I" MPD_INDEX="3" NAME="PLB_UABus" SIGNAME="plb_v46_0_PLB_UABus" VECFORMULA="[0:31]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_PAValid" DIR="I" MPD_INDEX="4" NAME="PLB_PAValid" SIGNAME="plb_v46_0_PLB_PAValid"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_SAValid" DIR="I" MPD_INDEX="5" NAME="PLB_SAValid" SIGNAME="plb_v46_0_PLB_SAValid"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPrim" DIR="I" MPD_INDEX="6" NAME="PLB_rdPrim" SIGNAME="plb_v46_0_PLB_rdPrim"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPrim" DIR="I" MPD_INDEX="7" NAME="PLB_wrPrim" SIGNAME="plb_v46_0_PLB_wrPrim"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_masterID" DIR="I" MPD_INDEX="8" NAME="PLB_masterID" SIGNAME="plb_v46_0_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_abort" DIR="I" MPD_INDEX="9" NAME="PLB_abort" SIGNAME="plb_v46_0_PLB_abort"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_busLock" DIR="I" MPD_INDEX="10" NAME="PLB_busLock" SIGNAME="plb_v46_0_PLB_busLock"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_RNW" DIR="I" MPD_INDEX="11" NAME="PLB_RNW" SIGNAME="plb_v46_0_PLB_RNW"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_BE" DIR="I" MPD_INDEX="12" NAME="PLB_BE" SIGNAME="plb_v46_0_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_MSize" DIR="I" MPD_INDEX="13" NAME="PLB_MSize" SIGNAME="plb_v46_0_PLB_MSize" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_size" DIR="I" MPD_INDEX="14" NAME="PLB_size" SIGNAME="plb_v46_0_PLB_size" VECFORMULA="[0:3]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_type" DIR="I" MPD_INDEX="15" NAME="PLB_type" SIGNAME="plb_v46_0_PLB_type" VECFORMULA="[0:2]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_lockErr" DIR="I" MPD_INDEX="16" NAME="PLB_lockErr" SIGNAME="plb_v46_0_PLB_lockErr"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrDBus" DIR="I" MPD_INDEX="17" NAME="PLB_wrDBus" SIGNAME="plb_v46_0_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrBurst" DIR="I" MPD_INDEX="18" NAME="PLB_wrBurst" SIGNAME="plb_v46_0_PLB_wrBurst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdBurst" DIR="I" MPD_INDEX="19" NAME="PLB_rdBurst" SIGNAME="plb_v46_0_PLB_rdBurst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPendReq" DIR="I" MPD_INDEX="20" NAME="PLB_wrPendReq" SIGNAME="plb_v46_0_PLB_wrPendReq"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPendReq" DIR="I" MPD_INDEX="21" NAME="PLB_rdPendReq" SIGNAME="plb_v46_0_PLB_rdPendReq"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPendPri" DIR="I" MPD_INDEX="22" NAME="PLB_wrPendPri" SIGNAME="plb_v46_0_PLB_wrPendPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPendPri" DIR="I" MPD_INDEX="23" NAME="PLB_rdPendPri" SIGNAME="plb_v46_0_PLB_rdPendPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_reqPri" DIR="I" MPD_INDEX="24" NAME="PLB_reqPri" SIGNAME="plb_v46_0_PLB_reqPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_TAttribute" DIR="I" MPD_INDEX="25" NAME="PLB_TAttribute" SIGNAME="plb_v46_0_PLB_TAttribute" VECFORMULA="[0:15]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_addrAck" DIR="O" MPD_INDEX="26" NAME="Sl_addrAck" SIGNAME="plb_v46_0_Sl_addrAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_SSize" DIR="O" MPD_INDEX="27" NAME="Sl_SSize" SIGNAME="plb_v46_0_Sl_SSize" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wait" DIR="O" MPD_INDEX="28" NAME="Sl_wait" SIGNAME="plb_v46_0_Sl_wait"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rearbitrate" DIR="O" MPD_INDEX="29" NAME="Sl_rearbitrate" SIGNAME="plb_v46_0_Sl_rearbitrate"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrDAck" DIR="O" MPD_INDEX="30" NAME="Sl_wrDAck" SIGNAME="plb_v46_0_Sl_wrDAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrComp" DIR="O" MPD_INDEX="31" NAME="Sl_wrComp" SIGNAME="plb_v46_0_Sl_wrComp"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrBTerm" DIR="O" MPD_INDEX="32" NAME="Sl_wrBTerm" SIGNAME="plb_v46_0_Sl_wrBTerm"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdDBus" DIR="O" MPD_INDEX="33" NAME="Sl_rdDBus" SIGNAME="plb_v46_0_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdWdAddr" DIR="O" MPD_INDEX="34" NAME="Sl_rdWdAddr" SIGNAME="plb_v46_0_Sl_rdWdAddr" VECFORMULA="[0:3]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdDAck" DIR="O" MPD_INDEX="35" NAME="Sl_rdDAck" SIGNAME="plb_v46_0_Sl_rdDAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdComp" DIR="O" MPD_INDEX="36" NAME="Sl_rdComp" SIGNAME="plb_v46_0_Sl_rdComp"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdBTerm" DIR="O" MPD_INDEX="37" NAME="Sl_rdBTerm" SIGNAME="plb_v46_0_Sl_rdBTerm"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MBusy" DIR="O" MPD_INDEX="38" NAME="Sl_MBusy" SIGNAME="plb_v46_0_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MWrErr" DIR="O" MPD_INDEX="39" NAME="Sl_MWrErr" SIGNAME="plb_v46_0_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MRdErr" DIR="O" MPD_INDEX="40" NAME="Sl_MRdErr" SIGNAME="plb_v46_0_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MIRQ" DIR="O" MPD_INDEX="41" NAME="Sl_MIRQ" SIGNAME="plb_v46_0_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="42" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/> + <PORT DIR="I" MPD_INDEX="43" NAME="GPIO_IO_I" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/> + <PORT DIR="O" MPD_INDEX="44" NAME="GPIO_IO_O" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/> + <PORT DIR="O" MPD_INDEX="45" NAME="GPIO_IO_T" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/> + <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="46" NAME="GPIO2_IO_I" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/> + <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="47" NAME="GPIO2_IO_O" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/> + <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="48" NAME="GPIO2_IO_T" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/> + <PORT DIR="IO" IS_VALID="FALSE" MPD_INDEX="50" NAME="GPIO2_IO" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"> + <DESCRIPTION>GPIO2 Data IO</DESCRIPTION> + </PORT> + <BUSINTERFACE BUSNAME="plb_v46_0" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INMHS="TRUE" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE"/> + </MODULE> + <MODULE HWVERSION="2.00.a" INSTANCE="DIP_Switches_8Bit" IPTYPE="PERIPHERAL" MHS_INDEX="8" MODCLASS="PERIPHERAL" MODTYPE="xps_gpio"> + <DESCRIPTION TYPE="SHORT">XPS General Purpose IO</DESCRIPTION> + <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the PLBV46 bus.</DESCRIPTION> + <DOCUMENTATION> + <DOCUMENT SOURCE="c:/devtools/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/xps_gpio_v2_00_a/doc/xps_gpio.pdf" TYPE="IP"/> + </DOCUMENTATION> + <LICENSEINFO ICON_NAME="ps_core_preferred"/> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" MPD_INDEX="0" NAME="C_BASEADDR" TYPE="std_logic_vector(0 to 31)" VALUE="0x81460000"> + <DESCRIPTION>Base Address</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" MPD_INDEX="1" NAME="C_HIGHADDR" TYPE="std_logic_vector(0 to 31)" VALUE="0x8146ffff"> + <DESCRIPTION>High Address</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="2" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32"> + <DESCRIPTION>PLB Address Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="128"> + <DESCRIPTION>PLB Data Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="4" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="5" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="6" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Number of PLB Masters</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="7" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"> + <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="8" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="9" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex5"> + <DESCRIPTION>Device Family</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="10" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Channel 1 is Input Only </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="11" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Channel 2 is Input Only </DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="12" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="8"> + <DESCRIPTION>GPIO Data Channel Width</DESCRIPTION> + <DESCRIPTION>GPIO Data Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="13" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32"> + <DESCRIPTION>GPIO2 Data Channel Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="14" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>GPIO Supports Interrupts</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="15" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000"> + <DESCRIPTION>Channel 1 Data Out Default Value </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="16" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff"> + <DESCRIPTION>Channel 1 Tri-state Default Value </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="17" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Enable Channel 2 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="18" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000"> + <DESCRIPTION>Channel 2 Data Out Default Value </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="19" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff"> + <DESCRIPTION>Channel 2 Tri-state Default Value </DESCRIPTION> + </PARAMETER> + <MEMORYMAP> + <MEMRANGE BASEDECIMAL="2168848384" BASENAME="C_BASEADDR" BASEVALUE="0x81460000" HIGHDECIMAL="2168913919" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8146ffff" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K"> + <SLVINTERFACES> + <BUSINTERFACE NAME="SPLB"/> + </SLVINTERFACES> + </MEMRANGE> + </MEMORYMAP> + <PORT DIR="IO" ENDIAN="BIG" IS_INMHS="TRUE" LSB="0" MHS_INDEX="0" MPD_INDEX="49" MSB="7" NAME="GPIO_IO" SIGNAME="fpga_0_DIP_Switches_8Bit_GPIO_IO_pin" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"> + <DESCRIPTION>GPIO1 Data IO</DESCRIPTION> + </PORT> + <PORT BUS="SPLB" CLKFREQUENCY="125000000" DEF_SIGNAME="clk_125_0000MHzPLL0_ADJUST" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_125_0000MHzPLL0_ADJUST"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="plb_v46_0_SPLB_Rst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_ABus" DIR="I" MPD_INDEX="2" NAME="PLB_ABus" SIGNAME="plb_v46_0_PLB_ABus" VECFORMULA="[0:31]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_UABus" DIR="I" MPD_INDEX="3" NAME="PLB_UABus" SIGNAME="plb_v46_0_PLB_UABus" VECFORMULA="[0:31]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_PAValid" DIR="I" MPD_INDEX="4" NAME="PLB_PAValid" SIGNAME="plb_v46_0_PLB_PAValid"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_SAValid" DIR="I" MPD_INDEX="5" NAME="PLB_SAValid" SIGNAME="plb_v46_0_PLB_SAValid"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPrim" DIR="I" MPD_INDEX="6" NAME="PLB_rdPrim" SIGNAME="plb_v46_0_PLB_rdPrim"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPrim" DIR="I" MPD_INDEX="7" NAME="PLB_wrPrim" SIGNAME="plb_v46_0_PLB_wrPrim"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_masterID" DIR="I" MPD_INDEX="8" NAME="PLB_masterID" SIGNAME="plb_v46_0_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_abort" DIR="I" MPD_INDEX="9" NAME="PLB_abort" SIGNAME="plb_v46_0_PLB_abort"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_busLock" DIR="I" MPD_INDEX="10" NAME="PLB_busLock" SIGNAME="plb_v46_0_PLB_busLock"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_RNW" DIR="I" MPD_INDEX="11" NAME="PLB_RNW" SIGNAME="plb_v46_0_PLB_RNW"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_BE" DIR="I" MPD_INDEX="12" NAME="PLB_BE" SIGNAME="plb_v46_0_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_MSize" DIR="I" MPD_INDEX="13" NAME="PLB_MSize" SIGNAME="plb_v46_0_PLB_MSize" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_size" DIR="I" MPD_INDEX="14" NAME="PLB_size" SIGNAME="plb_v46_0_PLB_size" VECFORMULA="[0:3]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_type" DIR="I" MPD_INDEX="15" NAME="PLB_type" SIGNAME="plb_v46_0_PLB_type" VECFORMULA="[0:2]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_lockErr" DIR="I" MPD_INDEX="16" NAME="PLB_lockErr" SIGNAME="plb_v46_0_PLB_lockErr"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrDBus" DIR="I" MPD_INDEX="17" NAME="PLB_wrDBus" SIGNAME="plb_v46_0_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrBurst" DIR="I" MPD_INDEX="18" NAME="PLB_wrBurst" SIGNAME="plb_v46_0_PLB_wrBurst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdBurst" DIR="I" MPD_INDEX="19" NAME="PLB_rdBurst" SIGNAME="plb_v46_0_PLB_rdBurst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPendReq" DIR="I" MPD_INDEX="20" NAME="PLB_wrPendReq" SIGNAME="plb_v46_0_PLB_wrPendReq"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPendReq" DIR="I" MPD_INDEX="21" NAME="PLB_rdPendReq" SIGNAME="plb_v46_0_PLB_rdPendReq"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPendPri" DIR="I" MPD_INDEX="22" NAME="PLB_wrPendPri" SIGNAME="plb_v46_0_PLB_wrPendPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPendPri" DIR="I" MPD_INDEX="23" NAME="PLB_rdPendPri" SIGNAME="plb_v46_0_PLB_rdPendPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_reqPri" DIR="I" MPD_INDEX="24" NAME="PLB_reqPri" SIGNAME="plb_v46_0_PLB_reqPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_TAttribute" DIR="I" MPD_INDEX="25" NAME="PLB_TAttribute" SIGNAME="plb_v46_0_PLB_TAttribute" VECFORMULA="[0:15]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_addrAck" DIR="O" MPD_INDEX="26" NAME="Sl_addrAck" SIGNAME="plb_v46_0_Sl_addrAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_SSize" DIR="O" MPD_INDEX="27" NAME="Sl_SSize" SIGNAME="plb_v46_0_Sl_SSize" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wait" DIR="O" MPD_INDEX="28" NAME="Sl_wait" SIGNAME="plb_v46_0_Sl_wait"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rearbitrate" DIR="O" MPD_INDEX="29" NAME="Sl_rearbitrate" SIGNAME="plb_v46_0_Sl_rearbitrate"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrDAck" DIR="O" MPD_INDEX="30" NAME="Sl_wrDAck" SIGNAME="plb_v46_0_Sl_wrDAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrComp" DIR="O" MPD_INDEX="31" NAME="Sl_wrComp" SIGNAME="plb_v46_0_Sl_wrComp"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrBTerm" DIR="O" MPD_INDEX="32" NAME="Sl_wrBTerm" SIGNAME="plb_v46_0_Sl_wrBTerm"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdDBus" DIR="O" MPD_INDEX="33" NAME="Sl_rdDBus" SIGNAME="plb_v46_0_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdWdAddr" DIR="O" MPD_INDEX="34" NAME="Sl_rdWdAddr" SIGNAME="plb_v46_0_Sl_rdWdAddr" VECFORMULA="[0:3]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdDAck" DIR="O" MPD_INDEX="35" NAME="Sl_rdDAck" SIGNAME="plb_v46_0_Sl_rdDAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdComp" DIR="O" MPD_INDEX="36" NAME="Sl_rdComp" SIGNAME="plb_v46_0_Sl_rdComp"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdBTerm" DIR="O" MPD_INDEX="37" NAME="Sl_rdBTerm" SIGNAME="plb_v46_0_Sl_rdBTerm"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MBusy" DIR="O" MPD_INDEX="38" NAME="Sl_MBusy" SIGNAME="plb_v46_0_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MWrErr" DIR="O" MPD_INDEX="39" NAME="Sl_MWrErr" SIGNAME="plb_v46_0_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MRdErr" DIR="O" MPD_INDEX="40" NAME="Sl_MRdErr" SIGNAME="plb_v46_0_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MIRQ" DIR="O" MPD_INDEX="41" NAME="Sl_MIRQ" SIGNAME="plb_v46_0_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="42" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/> + <PORT DIR="I" MPD_INDEX="43" NAME="GPIO_IO_I" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/> + <PORT DIR="O" MPD_INDEX="44" NAME="GPIO_IO_O" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/> + <PORT DIR="O" MPD_INDEX="45" NAME="GPIO_IO_T" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/> + <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="46" NAME="GPIO2_IO_I" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/> + <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="47" NAME="GPIO2_IO_O" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/> + <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="48" NAME="GPIO2_IO_T" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/> + <PORT DIR="IO" IS_VALID="FALSE" MPD_INDEX="50" NAME="GPIO2_IO" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"> + <DESCRIPTION>GPIO2 Data IO</DESCRIPTION> + </PORT> + <BUSINTERFACE BUSNAME="plb_v46_0" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INMHS="TRUE" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE"/> + </MODULE> + <MODULE HWVERSION="2.01.a" INSTANCE="IIC_EEPROM" IPTYPE="PERIPHERAL" MHS_INDEX="9" MODCLASS="PERIPHERAL" MODTYPE="xps_iic"> + <DESCRIPTION TYPE="SHORT">XPS IIC Interface</DESCRIPTION> + <DESCRIPTION TYPE="LONG">PLBV46 interface to Philips I2C bus v2.1</DESCRIPTION> + <DOCUMENTATION> + <DOCUMENT SOURCE="c:/devtools/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/xps_iic_v2_01_a/doc/xps_iic.pdf" TYPE="IP"/> + </DOCUMENTATION> + <LICENSEINFO ICON_NAME="ps_core_preferred"/> + <PARAMETER MPD_INDEX="0" NAME="C_IIC_FREQ" TYPE="INTEGER" VALUE="100000"> + <DESCRIPTION>Output Frequency of SCL Signal</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="1" NAME="C_TEN_BIT_ADR" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Use 10-bit Address</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="2" NAME="C_GPO_WIDTH" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Width of GPIO</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_CLK_FREQ" TYPE="INTEGER" VALUE="125000000"> + <DESCRIPTION>PLBv46 Bus Clock Frequency</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="4" NAME="C_SCL_INERTIAL_DELAY" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Width of glitches removed on SCL input</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="5" NAME="C_SDA_INERTIAL_DELAY" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Width of glitches removed on SDA input</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" MPD_INDEX="6" NAME="C_BASEADDR" TYPE="std_logic_vector(0 to 31)" VALUE="0x81600000"> + <DESCRIPTION>Base Address</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" MPD_INDEX="7" NAME="C_HIGHADDR" TYPE="std_logic_vector(0 to 31)" VALUE="0x8160ffff"> + <DESCRIPTION>High Address</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="8" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="9" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Number of PLB Masters</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="10" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32"> + <DESCRIPTION>PLB Address Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="11" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="128"> + <DESCRIPTION>PLB Data Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="12" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"> + <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="13" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex5"> + <DESCRIPTION>Device Family</DESCRIPTION> + </PARAMETER> + <MEMORYMAP> + <MEMRANGE BASEDECIMAL="2170552320" BASENAME="C_BASEADDR" BASEVALUE="0x81600000" HIGHDECIMAL="2170617855" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8160ffff" MEMTYPE="REGISTER" MINSIZE="0x00200" SIZE="65536" SIZEABRV="64K"> + <SLVINTERFACES> + <BUSINTERFACE NAME="SPLB"/> + </SLVINTERFACES> + </MEMRANGE> + </MEMORYMAP> + <PORT DIR="IO" IS_INMHS="TRUE" MHS_INDEX="0" MPD_INDEX="50" NAME="Sda" SIGNAME="fpga_0_IIC_EEPROM_Sda_pin"> + <DESCRIPTION>IIC Serial Data</DESCRIPTION> + </PORT> + <PORT DIR="IO" IS_INMHS="TRUE" MHS_INDEX="1" MPD_INDEX="51" NAME="Scl" SIGNAME="fpga_0_IIC_EEPROM_Scl_pin"> + <DESCRIPTION>IIC Serial Clock</DESCRIPTION> + </PORT> + <PORT DIR="I" MPD_INDEX="0" NAME="Sda_I" SIGNAME="__NOC__"/> + <PORT DIR="O" MPD_INDEX="1" NAME="Sda_O" SIGNAME="__NOC__"/> + <PORT DIR="O" MPD_INDEX="2" NAME="Sda_T" SIGNAME="__NOC__"/> + <PORT DIR="I" MPD_INDEX="3" NAME="Scl_I" SIGNAME="__NOC__"/> + <PORT DIR="O" MPD_INDEX="4" NAME="Scl_O" SIGNAME="__NOC__"/> + <PORT DIR="O" MPD_INDEX="5" NAME="Scl_T" SIGNAME="__NOC__"/> + <PORT DIR="O" MPD_INDEX="6" NAME="Gpo" SIGNAME="__NOC__" VECFORMULA="[(32-C_GPO_WIDTH):(32-1)]"> + <DESCRIPTION>IIC General Purpose Output</DESCRIPTION> + </PORT> + <PORT DIR="O" MPD_INDEX="7" NAME="IIC2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/> + <PORT BUS="SPLB" CLKFREQUENCY="125000000" DEF_SIGNAME="clk_125_0000MHzPLL0_ADJUST" DIR="I" MPD_INDEX="8" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_125_0000MHzPLL0_ADJUST"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_SPLB_Rst" DIR="I" MPD_INDEX="9" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="plb_v46_0_SPLB_Rst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_ABus" DIR="I" MPD_INDEX="10" NAME="PLB_ABus" SIGNAME="plb_v46_0_PLB_ABus" VECFORMULA="[0:31]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_UABus" DIR="I" MPD_INDEX="11" NAME="PLB_UABus" SIGNAME="plb_v46_0_PLB_UABus" VECFORMULA="[0:31]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_PAValid" DIR="I" MPD_INDEX="12" NAME="PLB_PAValid" SIGNAME="plb_v46_0_PLB_PAValid"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_SAValid" DIR="I" MPD_INDEX="13" NAME="PLB_SAValid" SIGNAME="plb_v46_0_PLB_SAValid"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPrim" DIR="I" MPD_INDEX="14" NAME="PLB_rdPrim" SIGNAME="plb_v46_0_PLB_rdPrim"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPrim" DIR="I" MPD_INDEX="15" NAME="PLB_wrPrim" SIGNAME="plb_v46_0_PLB_wrPrim"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_masterID" DIR="I" MPD_INDEX="16" NAME="PLB_masterID" SIGNAME="plb_v46_0_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_abort" DIR="I" MPD_INDEX="17" NAME="PLB_abort" SIGNAME="plb_v46_0_PLB_abort"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_busLock" DIR="I" MPD_INDEX="18" NAME="PLB_busLock" SIGNAME="plb_v46_0_PLB_busLock"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_RNW" DIR="I" MPD_INDEX="19" NAME="PLB_RNW" SIGNAME="plb_v46_0_PLB_RNW"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_BE" DIR="I" MPD_INDEX="20" NAME="PLB_BE" SIGNAME="plb_v46_0_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_MSize" DIR="I" MPD_INDEX="21" NAME="PLB_MSize" SIGNAME="plb_v46_0_PLB_MSize" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_size" DIR="I" MPD_INDEX="22" NAME="PLB_size" SIGNAME="plb_v46_0_PLB_size" VECFORMULA="[0:3]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_type" DIR="I" MPD_INDEX="23" NAME="PLB_type" SIGNAME="plb_v46_0_PLB_type" VECFORMULA="[0:2]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_lockErr" DIR="I" MPD_INDEX="24" NAME="PLB_lockErr" SIGNAME="plb_v46_0_PLB_lockErr"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrDBus" DIR="I" MPD_INDEX="25" NAME="PLB_wrDBus" SIGNAME="plb_v46_0_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrBurst" DIR="I" MPD_INDEX="26" NAME="PLB_wrBurst" SIGNAME="plb_v46_0_PLB_wrBurst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdBurst" DIR="I" MPD_INDEX="27" NAME="PLB_rdBurst" SIGNAME="plb_v46_0_PLB_rdBurst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPendReq" DIR="I" MPD_INDEX="28" NAME="PLB_wrPendReq" SIGNAME="plb_v46_0_PLB_wrPendReq"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPendReq" DIR="I" MPD_INDEX="29" NAME="PLB_rdPendReq" SIGNAME="plb_v46_0_PLB_rdPendReq"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPendPri" DIR="I" MPD_INDEX="30" NAME="PLB_wrPendPri" SIGNAME="plb_v46_0_PLB_wrPendPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPendPri" DIR="I" MPD_INDEX="31" NAME="PLB_rdPendPri" SIGNAME="plb_v46_0_PLB_rdPendPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_reqPri" DIR="I" MPD_INDEX="32" NAME="PLB_reqPri" SIGNAME="plb_v46_0_PLB_reqPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_TAttribute" DIR="I" MPD_INDEX="33" NAME="PLB_TAttribute" SIGNAME="plb_v46_0_PLB_TAttribute" VECFORMULA="[0:15]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_addrAck" DIR="O" MPD_INDEX="34" NAME="Sl_addrAck" SIGNAME="plb_v46_0_Sl_addrAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_SSize" DIR="O" MPD_INDEX="35" NAME="Sl_SSize" SIGNAME="plb_v46_0_Sl_SSize" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wait" DIR="O" MPD_INDEX="36" NAME="Sl_wait" SIGNAME="plb_v46_0_Sl_wait"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rearbitrate" DIR="O" MPD_INDEX="37" NAME="Sl_rearbitrate" SIGNAME="plb_v46_0_Sl_rearbitrate"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrDAck" DIR="O" MPD_INDEX="38" NAME="Sl_wrDAck" SIGNAME="plb_v46_0_Sl_wrDAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrComp" DIR="O" MPD_INDEX="39" NAME="Sl_wrComp" SIGNAME="plb_v46_0_Sl_wrComp"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrBTerm" DIR="O" MPD_INDEX="40" NAME="Sl_wrBTerm" SIGNAME="plb_v46_0_Sl_wrBTerm"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdDBus" DIR="O" MPD_INDEX="41" NAME="Sl_rdDBus" SIGNAME="plb_v46_0_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdWdAddr" DIR="O" MPD_INDEX="42" NAME="Sl_rdWdAddr" SIGNAME="plb_v46_0_Sl_rdWdAddr" VECFORMULA="[0:3]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdDAck" DIR="O" MPD_INDEX="43" NAME="Sl_rdDAck" SIGNAME="plb_v46_0_Sl_rdDAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdComp" DIR="O" MPD_INDEX="44" NAME="Sl_rdComp" SIGNAME="plb_v46_0_Sl_rdComp"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdBTerm" DIR="O" MPD_INDEX="45" NAME="Sl_rdBTerm" SIGNAME="plb_v46_0_Sl_rdBTerm"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MBusy" DIR="O" MPD_INDEX="46" NAME="Sl_MBusy" SIGNAME="plb_v46_0_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MWrErr" DIR="O" MPD_INDEX="47" NAME="Sl_MWrErr" SIGNAME="plb_v46_0_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MRdErr" DIR="O" MPD_INDEX="48" NAME="Sl_MRdErr" SIGNAME="plb_v46_0_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MIRQ" DIR="O" MPD_INDEX="49" NAME="Sl_MIRQ" SIGNAME="plb_v46_0_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <BUSINTERFACE BUSNAME="plb_v46_0" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INMHS="TRUE" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE"/> + </MODULE> + <MODULE HWVERSION="3.00.a" INSTANCE="SRAM" IPTYPE="PERIPHERAL" MHS_INDEX="10" MODCLASS="MEMORY_CNTLR" MODTYPE="xps_mch_emc"> + <DESCRIPTION TYPE="SHORT">XPS Multi-Channel External Memory Controller(SRAM/Flash)</DESCRIPTION> + <DESCRIPTION TYPE="LONG">Xilinx Multi-CHannel (MCH) PLBV46 external memory controller</DESCRIPTION> + <DOCUMENTATION> + <DOCUMENT SOURCE="c:/devtools/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_00_a/doc/xps_mch_emc.pdf" TYPE="IP"/> + </DOCUMENTATION> + <LICENSEINFO ICON_NAME="ps_core_preferred"/> + <PARAMETER MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex5"> + <DESCRIPTION>Device Family</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="1" NAME="C_NUM_BANKS_MEM" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Number of Memory Banks </DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="2" NAME="C_NUM_CHANNELS" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Number of MCH Channels </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="3" NAME="C_PRIORITY_MODE" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Arbitration Mode Between PLB and MCH Interface </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="4" NAME="C_INCLUDE_PLB_IPIF" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Include PLB Slave Interface </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="5" NAME="C_INCLUDE_WRBUF" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Include Write Buffer</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="6" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="7" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Number of PLB Masters</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="8" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="128"> + <DESCRIPTION>PLB Data Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="10" NAME="C_MCH_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32"> + <DESCRIPTION>MCH and PLB Address Bus Width </DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="11" NAME="C_SPLB_SMALLEST_MASTER" TYPE="INTEGER" VALUE="128"> + <DESCRIPTION>Smallest Master Data Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="12" NAME="C_MCH_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"> + <DESCRIPTION>Data Bus Width of MCH</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_MCH_SPLB_CLK_PERIOD_PS" TYPE="INTEGER" VALUE="8000"> + <DESCRIPTION>MCH and PLB Clock Period </DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" MPD_INDEX="14" NAME="C_MEM0_BASEADDR" TYPE="std_logic_vector" VALUE="0xf8000000"> + <DESCRIPTION>Base Address of Bank 0 </DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" MPD_INDEX="15" NAME="C_MEM0_HIGHADDR" TYPE="std_logic_vector" VALUE="0xf80fffff"> + <DESCRIPTION>High Address of Bank 0 </DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="16" NAME="C_MEM1_BASEADDR" TYPE="std_logic_vector" VALUE="0xffffffff"> + <DESCRIPTION>Base Address of Bank 1 </DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="17" NAME="C_MEM1_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000"> + <DESCRIPTION>High Address of Bank 1 </DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="18" NAME="C_MEM2_BASEADDR" TYPE="std_logic_vector" VALUE="0xffffffff"> + <DESCRIPTION>Base Address of Bank 2 </DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="19" NAME="C_MEM2_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000"> + <DESCRIPTION>High Address of Bank 2 </DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="20" NAME="C_MEM3_BASEADDR" TYPE="std_logic_vector" VALUE="0xffffffff"> + <DESCRIPTION>Base Address of Bank 3 </DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="21" NAME="C_MEM3_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000"> + <DESCRIPTION>High Address of Bank 3 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="22" NAME="C_PAGEMODE_FLASH_0" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Page mode flash enable of Bank 0 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="23" NAME="C_PAGEMODE_FLASH_1" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Page mode flash enable of Bank 1 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="24" NAME="C_PAGEMODE_FLASH_2" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Page mode flash enable of Bank 2 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="25" NAME="C_PAGEMODE_FLASH_3" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Page mode flash enable of Bank 3 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="26" NAME="C_INCLUDE_NEGEDGE_IOREGS" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Use Falling Edge IO Register in Interface Signals </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="27" NAME="C_MEM0_WIDTH" TYPE="INTEGER" VALUE="32"> + <DESCRIPTION>Data Bus Width of Bank 0 </DESCRIPTION> + <DESCRIPTION>Data Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="28" NAME="C_MEM1_WIDTH" TYPE="INTEGER" VALUE="32"> + <DESCRIPTION>Data Bus Width of Bank 1 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="29" NAME="C_MEM2_WIDTH" TYPE="INTEGER" VALUE="32"> + <DESCRIPTION>Data Bus Width of Bank 2 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="30" NAME="C_MEM3_WIDTH" TYPE="INTEGER" VALUE="32"> + <DESCRIPTION>Data Bus Width of Bank 3 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="31" NAME="C_MAX_MEM_WIDTH" TYPE="INTEGER" VALUE="32"> + <DESCRIPTION>Maximum Data Bus Width </DESCRIPTION> + <DESCRIPTION>Maximum Data Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="32" NAME="C_INCLUDE_DATAWIDTH_MATCHING_0" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Execute Multiple Memory Accesses To Match Bank 0 Data Bus Width To PLB Data Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="33" NAME="C_INCLUDE_DATAWIDTH_MATCHING_1" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION> Execute Multiple Memory Accesses To Match Bank 1 Data Bus Width To PLB Data Bus Width </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="34" NAME="C_INCLUDE_DATAWIDTH_MATCHING_2" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION> Execute Multiple Memory Accesses To Match Bank 2 Data Bus Width To PLB Data Bus Width </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="35" NAME="C_INCLUDE_DATAWIDTH_MATCHING_3" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION> Execute Multiple Memory Accesses To Match Bank 3 Data Bus Width To PLB Data Bus Width </DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="36" NAME="C_SYNCH_MEM_0" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Bank 0 is Synchronous </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="37" NAME="C_SYNCH_PIPEDELAY_0" TYPE="INTEGER" VALUE="2"> + <DESCRIPTION>Pipeline Latency of Bank 0 </DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="38" NAME="C_TCEDV_PS_MEM_0" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>TCEDV of Bank 0 </DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="39" NAME="C_TAVDV_PS_MEM_0" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>TAVDV of Bank 0 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="40" NAME="C_TPACC_PS_FLASH_0" TYPE="INTEGER" VALUE="25000"> + <DESCRIPTION>TPACC of Bank 0 </DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="41" NAME="C_THZCE_PS_MEM_0" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>THZCE of Bank 0 </DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="42" NAME="C_THZOE_PS_MEM_0" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>THZOE of Bank 0 </DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="43" NAME="C_TWC_PS_MEM_0" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>TWC of Bank 0 </DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="44" NAME="C_TWP_PS_MEM_0" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>TWP of Bank 0 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="45" NAME="C_TLZWE_PS_MEM_0" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>TLZWE of Bank 0 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="46" NAME="C_SYNCH_MEM_1" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Bank 1 is Synchronous </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="47" NAME="C_SYNCH_PIPEDELAY_1" TYPE="INTEGER" VALUE="2"> + <DESCRIPTION>Pipeline Latency of Bank 1 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="48" NAME="C_TCEDV_PS_MEM_1" TYPE="INTEGER" VALUE="15000"> + <DESCRIPTION>TCEDV of Bank 1 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="49" NAME="C_TAVDV_PS_MEM_1" TYPE="INTEGER" VALUE="15000"> + <DESCRIPTION>TAVDV of Bank 1 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="50" NAME="C_TPACC_PS_FLASH_1" TYPE="INTEGER" VALUE="25000"> + <DESCRIPTION>TPACC of Bank 1 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="51" NAME="C_THZCE_PS_MEM_1" TYPE="INTEGER" VALUE="7000"> + <DESCRIPTION>THZCE of Bank 1 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="52" NAME="C_THZOE_PS_MEM_1" TYPE="INTEGER" VALUE="7000"> + <DESCRIPTION>THZOE of Bank 1 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="53" NAME="C_TWC_PS_MEM_1" TYPE="INTEGER" VALUE="15000"> + <DESCRIPTION>TWC of Bank 1 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="54" NAME="C_TWP_PS_MEM_1" TYPE="INTEGER" VALUE="12000"> + <DESCRIPTION>TWP of Bank 1 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="55" NAME="C_TLZWE_PS_MEM_1" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>TLZWE of Bank 1 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="56" NAME="C_SYNCH_MEM_2" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Bank 2 is Synchronous </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="57" NAME="C_SYNCH_PIPEDELAY_2" TYPE="INTEGER" VALUE="2"> + <DESCRIPTION>Pipeline Latency of Bank 2 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="58" NAME="C_TCEDV_PS_MEM_2" TYPE="INTEGER" VALUE="15000"> + <DESCRIPTION>TCEDV of Bank 2 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="59" NAME="C_TAVDV_PS_MEM_2" TYPE="INTEGER" VALUE="15000"> + <DESCRIPTION>TAVDV of Bank 2 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="60" NAME="C_TPACC_PS_FLASH_2" TYPE="INTEGER" VALUE="25000"> + <DESCRIPTION>TPACC of Bank 2 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="61" NAME="C_THZCE_PS_MEM_2" TYPE="INTEGER" VALUE="7000"> + <DESCRIPTION>THZCE of Bank 2 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="62" NAME="C_THZOE_PS_MEM_2" TYPE="INTEGER" VALUE="7000"> + <DESCRIPTION>THZOE of Bank 2 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="63" NAME="C_TWC_PS_MEM_2" TYPE="INTEGER" VALUE="15000"> + <DESCRIPTION>TWC of Bank 2 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="64" NAME="C_TWP_PS_MEM_2" TYPE="INTEGER" VALUE="12000"> + <DESCRIPTION>TWP of Bank 2 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="65" NAME="C_TLZWE_PS_MEM_2" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>TLZWE of Bank 2 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="66" NAME="C_SYNCH_MEM_3" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Bank 3 is Synchronous </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="67" NAME="C_SYNCH_PIPEDELAY_3" TYPE="INTEGER" VALUE="2"> + <DESCRIPTION>Pipeline Latency of Bank 3 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="68" NAME="C_TCEDV_PS_MEM_3" TYPE="INTEGER" VALUE="15000"> + <DESCRIPTION>TCEDV of Bank 3 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="69" NAME="C_TAVDV_PS_MEM_3" TYPE="INTEGER" VALUE="15000"> + <DESCRIPTION>TAVDV of Bank 3 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="70" NAME="C_TPACC_PS_FLASH_3" TYPE="INTEGER" VALUE="25000"> + <DESCRIPTION>TPACC of Bank 3 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="71" NAME="C_THZCE_PS_MEM_3" TYPE="INTEGER" VALUE="7000"> + <DESCRIPTION>THZCE of Bank 3 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="72" NAME="C_THZOE_PS_MEM_3" TYPE="INTEGER" VALUE="7000"> + <DESCRIPTION>THZOE of Bank 3 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="73" NAME="C_TWC_PS_MEM_3" TYPE="INTEGER" VALUE="15000"> + <DESCRIPTION>TWC of Bank 3 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="74" NAME="C_TWP_PS_MEM_3" TYPE="INTEGER" VALUE="12000"> + <DESCRIPTION>TWP of Bank 3 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="75" NAME="C_TLZWE_PS_MEM_3" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>TLZWE of Bank 3 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="76" NAME="C_MCH0_PROTOCOL" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Interface Protocol of Ch 0 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="77" NAME="C_MCH0_ACCESSBUF_DEPTH" TYPE="INTEGER" VALUE="16"> + <DESCRIPTION>Depth of Access Buffer of Ch 0 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="78" NAME="C_MCH0_RDDATABUF_DEPTH" TYPE="INTEGER" VALUE="16"> + <DESCRIPTION>Depth of Read Data Buffer Depath of Ch 0 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="79" NAME="C_MCH1_PROTOCOL" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Interface Protocol of Ch 1 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="80" NAME="C_MCH1_ACCESSBUF_DEPTH" TYPE="INTEGER" VALUE="16"> + <DESCRIPTION>Depth of Access Buffer of Ch 1 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="81" NAME="C_MCH1_RDDATABUF_DEPTH" TYPE="INTEGER" VALUE="16"> + <DESCRIPTION>Depth of Read Data Buffer of Ch 1 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="82" NAME="C_MCH2_PROTOCOL" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Interface Protocol of Ch 2 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="83" NAME="C_MCH2_ACCESSBUF_DEPTH" TYPE="INTEGER" VALUE="16"> + <DESCRIPTION>Depth of Access Buffer of Ch 2 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="84" NAME="C_MCH2_RDDATABUF_DEPTH" TYPE="INTEGER" VALUE="16"> + <DESCRIPTION>Depth of Read Data Buffer of Ch 2 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="85" NAME="C_MCH3_PROTOCOL" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Interface Protocol of Ch 3 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="86" NAME="C_MCH3_ACCESSBUF_DEPTH" TYPE="INTEGER" VALUE="16"> + <DESCRIPTION>Depth of Access Buffer of Ch 3 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="87" NAME="C_MCH3_RDDATABUF_DEPTH" TYPE="INTEGER" VALUE="16"> + <DESCRIPTION>Depth of Read Data Buffer of Ch 3 </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="88" NAME="C_XCL0_LINESIZE" TYPE="INTEGER" VALUE="4"> + <DESCRIPTION>Cacheline Size of Ch0</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="89" NAME="C_XCL0_WRITEXFER" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Write Transfer Type of Ch0</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="90" NAME="C_XCL1_LINESIZE" TYPE="INTEGER" VALUE="4"> + <DESCRIPTION>Cacheline Size of Ch1</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="91" NAME="C_XCL1_WRITEXFER" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Write Transfer Type of Ch1</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="92" NAME="C_XCL2_LINESIZE" TYPE="INTEGER" VALUE="4"> + <DESCRIPTION>Cacheline Size of Ch2</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="93" NAME="C_XCL2_WRITEXFER" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Write Transfer Type of Ch2</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="94" NAME="C_XCL3_LINESIZE" TYPE="INTEGER" VALUE="4"> + <DESCRIPTION>Cacheline Size of Ch3</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="95" NAME="C_XCL3_WRITEXFER" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Write Transfer Type of Ch3</DESCRIPTION> + </PARAMETER> + <MEMORYMAP> + <MEMRANGE BASEDECIMAL="4160749568" BASENAME="C_MEM0_BASEADDR" BASEVALUE="0xf8000000" HIGHDECIMAL="4161798143" HIGHNAME="C_MEM0_HIGHADDR" HIGHVALUE="0xf80fffff" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="1048576" SIZEABRV="1M"> + <SLVINTERFACES> + <BUSINTERFACE NAME="SPLB"/> + <BUSINTERFACE NAME="MCH0"/> + <BUSINTERFACE NAME="MCH1"/> + <BUSINTERFACE NAME="MCH2"/> + <BUSINTERFACE NAME="MCH3"/> + </SLVINTERFACES> + </MEMRANGE> + <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_MEM1_BASEADDR" BASEVALUE="0xffffffff" HIGHDECIMAL="0" HIGHNAME="C_MEM1_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" SIZE="0" SIZEABRV="U"> + <SLVINTERFACES> + <BUSINTERFACE NAME="SPLB"/> + <BUSINTERFACE NAME="MCH0"/> + <BUSINTERFACE NAME="MCH1"/> + <BUSINTERFACE NAME="MCH2"/> + <BUSINTERFACE NAME="MCH3"/> + </SLVINTERFACES> + </MEMRANGE> + <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_MEM2_BASEADDR" BASEVALUE="0xffffffff" HIGHDECIMAL="0" HIGHNAME="C_MEM2_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" SIZE="0" SIZEABRV="U"> + <SLVINTERFACES> + <BUSINTERFACE NAME="SPLB"/> + <BUSINTERFACE NAME="MCH0"/> + <BUSINTERFACE NAME="MCH1"/> + <BUSINTERFACE NAME="MCH2"/> + <BUSINTERFACE NAME="MCH3"/> + </SLVINTERFACES> + </MEMRANGE> + <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_MEM3_BASEADDR" BASEVALUE="0xffffffff" HIGHDECIMAL="0" HIGHNAME="C_MEM3_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" SIZE="0" SIZEABRV="U"> + <SLVINTERFACES> + <BUSINTERFACE NAME="SPLB"/> + <BUSINTERFACE NAME="MCH0"/> + <BUSINTERFACE NAME="MCH1"/> + <BUSINTERFACE NAME="MCH2"/> + <BUSINTERFACE NAME="MCH3"/> + </SLVINTERFACES> + </MEMRANGE> + </MEMORYMAP> + <PORT CLKFREQUENCY="125000000" DIR="I" IS_INMHS="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="RdClk" SIGIS="CLK" SIGNAME="clk_125_0000MHzPLL0_ADJUST"/> + <PORT DIR="O" ENDIAN="BIG" IS_INMHS="TRUE" LSB="0" MHS_INDEX="1" MPD_INDEX="78" MSB="31" NAME="Mem_A" SIGNAME="0b0000000 & fpga_0_SRAM_Mem_A_pin_vslice_7_30_concat & 0b0" VECFORMULA="[0:(C_MCH_SPLB_AWIDTH-1)]"> + <DESCRIPTION>Memory Address Bus</DESCRIPTION> + </PORT> + <PORT DIR="O" IS_INMHS="TRUE" MHS_INDEX="2" MPD_INDEX="80" NAME="Mem_CEN" SIGNAME="fpga_0_SRAM_Mem_CEN_pin" VECFORMULA="[0:(C_NUM_BANKS_MEM-1)]"> + <DESCRIPTION>Memory Chip Enable Active Low</DESCRIPTION> + </PORT> + <PORT DIR="O" IS_INMHS="TRUE" MHS_INDEX="3" MPD_INDEX="81" NAME="Mem_OEN" SIGNAME="fpga_0_SRAM_Mem_OEN_pin" VECFORMULA="[0:(C_NUM_BANKS_MEM-1)]"> + <DESCRIPTION>Memory Output Enable</DESCRIPTION> + </PORT> + <PORT DIR="O" IS_INMHS="TRUE" MHS_INDEX="4" MPD_INDEX="82" NAME="Mem_WEN" SIGNAME="fpga_0_SRAM_Mem_WEN_pin"> + <DESCRIPTION>Memory Write Enable</DESCRIPTION> + </PORT> + <PORT DIR="O" ENDIAN="BIG" IS_INMHS="TRUE" LSB="0" MHS_INDEX="5" MPD_INDEX="84" MSB="3" NAME="Mem_BEN" SIGNAME="fpga_0_SRAM_Mem_BEN_pin" VECFORMULA="[0:((C_MAX_MEM_WIDTH/8)-1)]"> + <DESCRIPTION>Memory Byte Enable</DESCRIPTION> + </PORT> + <PORT DIR="O" IS_INMHS="TRUE" MHS_INDEX="6" MPD_INDEX="86" NAME="Mem_ADV_LDN" SIGNAME="fpga_0_SRAM_Mem_ADV_LDN_pin"> + <DESCRIPTION>Memory Advanced Burst Address/Load New Address</DESCRIPTION> + </PORT> + <PORT DIR="IO" ENDIAN="BIG" IS_INMHS="TRUE" LSB="0" MHS_INDEX="7" MPD_INDEX="90" MSB="31" NAME="Mem_DQ" SIGNAME="fpga_0_SRAM_Mem_DQ_pin" VECFORMULA="[0:(C_MAX_MEM_WIDTH-1)]"> + <DESCRIPTION>Memory Data Bus</DESCRIPTION> + </PORT> + <PORT BUS="SPLB" CLKFREQUENCY="125000000" DEF_SIGNAME="clk_125_0000MHzPLL0_ADJUST" DIR="I" MPD_INDEX="0" NAME="MCH_SPLB_Clk" SIGIS="CLK" SIGNAME="clk_125_0000MHzPLL0_ADJUST"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_SPLB_Rst" DIR="I" MPD_INDEX="2" NAME="MCH_SPLB_Rst" SIGIS="RST" SIGNAME="plb_v46_0_SPLB_Rst"/> + <PORT BUS="MCH0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="3" NAME="MCH0_Access_Control" SIGNAME="__NOC__"/> + <PORT BUS="MCH0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="4" NAME="MCH0_Access_Data" SIGNAME="__NOC__" VECFORMULA="[0:(C_MCH_NATIVE_DWIDTH-1)]"/> + <PORT BUS="MCH0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="5" NAME="MCH0_Access_Write" SIGNAME="__NOC__"/> + <PORT BUS="MCH0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="6" NAME="MCH0_Access_Full" SIGNAME="__NOC__"/> + <PORT BUS="MCH0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="7" NAME="MCH0_ReadData_Control" SIGNAME="__NOC__"/> + <PORT BUS="MCH0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="8" NAME="MCH0_ReadData_Data" SIGNAME="__NOC__" VECFORMULA="[0:(C_MCH_NATIVE_DWIDTH-1)]"/> + <PORT BUS="MCH0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="9" NAME="MCH0_ReadData_Read" SIGNAME="__NOC__"/> + <PORT BUS="MCH0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="10" NAME="MCH0_ReadData_Exists" SIGNAME="__NOC__"/> + <PORT BUS="MCH1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="11" NAME="MCH1_Access_Control" SIGNAME="__NOC__"/> + <PORT BUS="MCH1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="12" NAME="MCH1_Access_Data" SIGNAME="__NOC__" VECFORMULA="[0:(C_MCH_NATIVE_DWIDTH-1)]"/> + <PORT BUS="MCH1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="13" NAME="MCH1_Access_Write" SIGNAME="__NOC__"/> + <PORT BUS="MCH1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="14" NAME="MCH1_Access_Full" SIGNAME="__NOC__"/> + <PORT BUS="MCH1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="15" NAME="MCH1_ReadData_Control" SIGNAME="__NOC__"/> + <PORT BUS="MCH1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="16" NAME="MCH1_ReadData_Data" SIGNAME="__NOC__" VECFORMULA="[0:(C_MCH_NATIVE_DWIDTH-1)]"/> + <PORT BUS="MCH1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="17" NAME="MCH1_ReadData_Read" SIGNAME="__NOC__"/> + <PORT BUS="MCH1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="18" NAME="MCH1_ReadData_Exists" SIGNAME="__NOC__"/> + <PORT BUS="MCH2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="19" NAME="MCH2_Access_Control" SIGNAME="__NOC__"/> + <PORT BUS="MCH2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="20" NAME="MCH2_Access_Data" SIGNAME="__NOC__" VECFORMULA="[0:(C_MCH_NATIVE_DWIDTH-1)]"/> + <PORT BUS="MCH2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="21" NAME="MCH2_Access_Write" SIGNAME="__NOC__"/> + <PORT BUS="MCH2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="22" NAME="MCH2_Access_Full" SIGNAME="__NOC__"/> + <PORT BUS="MCH2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="23" NAME="MCH2_ReadData_Control" SIGNAME="__NOC__"/> + <PORT BUS="MCH2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="24" NAME="MCH2_ReadData_Data" SIGNAME="__NOC__" VECFORMULA="[0:(C_MCH_NATIVE_DWIDTH-1)]"/> + <PORT BUS="MCH2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="25" NAME="MCH2_ReadData_Read" SIGNAME="__NOC__"/> + <PORT BUS="MCH2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="26" NAME="MCH2_ReadData_Exists" SIGNAME="__NOC__"/> + <PORT BUS="MCH3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="27" NAME="MCH3_Access_Control" SIGNAME="__NOC__"/> + <PORT BUS="MCH3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="28" NAME="MCH3_Access_Data" SIGNAME="__NOC__" VECFORMULA="[0:(C_MCH_NATIVE_DWIDTH-1)]"/> + <PORT BUS="MCH3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="29" NAME="MCH3_Access_Write" SIGNAME="__NOC__"/> + <PORT BUS="MCH3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="30" NAME="MCH3_Access_Full" SIGNAME="__NOC__"/> + <PORT BUS="MCH3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="31" NAME="MCH3_ReadData_Control" SIGNAME="__NOC__"/> + <PORT BUS="MCH3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="32" NAME="MCH3_ReadData_Data" SIGNAME="__NOC__" VECFORMULA="[0:(C_MCH_NATIVE_DWIDTH-1)]"/> + <PORT BUS="MCH3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="33" NAME="MCH3_ReadData_Read" SIGNAME="__NOC__"/> + <PORT BUS="MCH3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="34" NAME="MCH3_ReadData_Exists" SIGNAME="__NOC__"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_ABus" DIR="I" MPD_INDEX="35" NAME="PLB_ABus" SIGNAME="plb_v46_0_PLB_ABus" VECFORMULA="[0:31]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_UABus" DIR="I" MPD_INDEX="36" NAME="PLB_UABus" SIGNAME="plb_v46_0_PLB_UABus" VECFORMULA="[0:31]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_PAValid" DIR="I" MPD_INDEX="37" NAME="PLB_PAValid" SIGNAME="plb_v46_0_PLB_PAValid"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_SAValid" DIR="I" MPD_INDEX="38" NAME="PLB_SAValid" SIGNAME="plb_v46_0_PLB_SAValid"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPrim" DIR="I" MPD_INDEX="39" NAME="PLB_rdPrim" SIGNAME="plb_v46_0_PLB_rdPrim"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPrim" DIR="I" MPD_INDEX="40" NAME="PLB_wrPrim" SIGNAME="plb_v46_0_PLB_wrPrim"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_masterID" DIR="I" MPD_INDEX="41" NAME="PLB_masterID" SIGNAME="plb_v46_0_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_abort" DIR="I" MPD_INDEX="42" NAME="PLB_abort" SIGNAME="plb_v46_0_PLB_abort"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_busLock" DIR="I" MPD_INDEX="43" NAME="PLB_busLock" SIGNAME="plb_v46_0_PLB_busLock"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_RNW" DIR="I" MPD_INDEX="44" NAME="PLB_RNW" SIGNAME="plb_v46_0_PLB_RNW"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_BE" DIR="I" MPD_INDEX="45" NAME="PLB_BE" SIGNAME="plb_v46_0_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_MSize" DIR="I" MPD_INDEX="46" NAME="PLB_MSize" SIGNAME="plb_v46_0_PLB_MSize" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_size" DIR="I" MPD_INDEX="47" NAME="PLB_size" SIGNAME="plb_v46_0_PLB_size" VECFORMULA="[0:3]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_type" DIR="I" MPD_INDEX="48" NAME="PLB_type" SIGNAME="plb_v46_0_PLB_type" VECFORMULA="[0:2]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_lockErr" DIR="I" MPD_INDEX="49" NAME="PLB_lockErr" SIGNAME="plb_v46_0_PLB_lockErr"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrDBus" DIR="I" MPD_INDEX="50" NAME="PLB_wrDBus" SIGNAME="plb_v46_0_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrBurst" DIR="I" MPD_INDEX="51" NAME="PLB_wrBurst" SIGNAME="plb_v46_0_PLB_wrBurst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdBurst" DIR="I" MPD_INDEX="52" NAME="PLB_rdBurst" SIGNAME="plb_v46_0_PLB_rdBurst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPendReq" DIR="I" MPD_INDEX="53" NAME="PLB_wrPendReq" SIGNAME="plb_v46_0_PLB_wrPendReq"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPendReq" DIR="I" MPD_INDEX="54" NAME="PLB_rdPendReq" SIGNAME="plb_v46_0_PLB_rdPendReq"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPendPri" DIR="I" MPD_INDEX="55" NAME="PLB_wrPendPri" SIGNAME="plb_v46_0_PLB_wrPendPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPendPri" DIR="I" MPD_INDEX="56" NAME="PLB_rdPendPri" SIGNAME="plb_v46_0_PLB_rdPendPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_reqPri" DIR="I" MPD_INDEX="57" NAME="PLB_reqPri" SIGNAME="plb_v46_0_PLB_reqPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_TAttribute" DIR="I" MPD_INDEX="58" NAME="PLB_TAttribute" SIGNAME="plb_v46_0_PLB_TAttribute" VECFORMULA="[0:15]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_addrAck" DIR="O" MPD_INDEX="59" NAME="Sl_addrAck" SIGNAME="plb_v46_0_Sl_addrAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_SSize" DIR="O" MPD_INDEX="60" NAME="Sl_SSize" SIGNAME="plb_v46_0_Sl_SSize" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wait" DIR="O" MPD_INDEX="61" NAME="Sl_wait" SIGNAME="plb_v46_0_Sl_wait"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rearbitrate" DIR="O" MPD_INDEX="62" NAME="Sl_rearbitrate" SIGNAME="plb_v46_0_Sl_rearbitrate"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrDAck" DIR="O" MPD_INDEX="63" NAME="Sl_wrDAck" SIGNAME="plb_v46_0_Sl_wrDAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrComp" DIR="O" MPD_INDEX="64" NAME="Sl_wrComp" SIGNAME="plb_v46_0_Sl_wrComp"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrBTerm" DIR="O" MPD_INDEX="65" NAME="Sl_wrBTerm" SIGNAME="plb_v46_0_Sl_wrBTerm"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdDBus" DIR="O" MPD_INDEX="66" NAME="Sl_rdDBus" SIGNAME="plb_v46_0_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdWdAddr" DIR="O" MPD_INDEX="67" NAME="Sl_rdWdAddr" SIGNAME="plb_v46_0_Sl_rdWdAddr" VECFORMULA="[0:3]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdDAck" DIR="O" MPD_INDEX="68" NAME="Sl_rdDAck" SIGNAME="plb_v46_0_Sl_rdDAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdComp" DIR="O" MPD_INDEX="69" NAME="Sl_rdComp" SIGNAME="plb_v46_0_Sl_rdComp"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdBTerm" DIR="O" MPD_INDEX="70" NAME="Sl_rdBTerm" SIGNAME="plb_v46_0_Sl_rdBTerm"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MBusy" DIR="O" MPD_INDEX="71" NAME="Sl_MBusy" SIGNAME="plb_v46_0_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MWrErr" DIR="O" MPD_INDEX="72" NAME="Sl_MWrErr" SIGNAME="plb_v46_0_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MRdErr" DIR="O" MPD_INDEX="73" NAME="Sl_MRdErr" SIGNAME="plb_v46_0_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MIRQ" DIR="O" MPD_INDEX="74" NAME="Sl_MIRQ" SIGNAME="plb_v46_0_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT DIR="I" MPD_INDEX="75" NAME="Mem_DQ_I" SIGNAME="__NOC__" VECFORMULA="[0:(C_MAX_MEM_WIDTH-1)]"/> + <PORT DIR="O" MPD_INDEX="76" NAME="Mem_DQ_O" SIGNAME="__NOC__" VECFORMULA="[0:(C_MAX_MEM_WIDTH-1)]"/> + <PORT DIR="O" MPD_INDEX="77" NAME="Mem_DQ_T" SIGNAME="__NOC__" VECFORMULA="[0:(C_MAX_MEM_WIDTH-1)]"/> + <PORT DIR="O" MPD_INDEX="79" NAME="Mem_RPN" SIGNAME="__NOC__"> + <DESCRIPTION>Memory Reset/Power Down</DESCRIPTION> + </PORT> + <PORT DIR="O" MPD_INDEX="83" NAME="Mem_QWEN" SIGNAME="__NOC__" VECFORMULA="[0:((C_MAX_MEM_WIDTH/8)-1)]"> + <DESCRIPTION>Memory Qualified Write Enable</DESCRIPTION> + </PORT> + <PORT DIR="O" MPD_INDEX="85" NAME="Mem_CE" SIGNAME="__NOC__" VECFORMULA="[0:(C_NUM_BANKS_MEM-1)]"> + <DESCRIPTION>Memory Chip Enable Active High</DESCRIPTION> + </PORT> + <PORT DIR="O" MPD_INDEX="87" NAME="Mem_LBON" SIGNAME="__NOC__"> + <DESCRIPTION>Memory Linear/Interleaved Burst Order</DESCRIPTION> + </PORT> + <PORT DIR="O" MPD_INDEX="88" NAME="Mem_CKEN" SIGNAME="__NOC__"> + <DESCRIPTION>Memory Clock Enable</DESCRIPTION> + </PORT> + <PORT DIR="O" MPD_INDEX="89" NAME="Mem_RNW" SIGNAME="__NOC__"> + <DESCRIPTION>Memory Read Not Write</DESCRIPTION> + </PORT> + <BUSINTERFACE BUSNAME="plb_v46_0" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INMHS="TRUE" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE"/> + <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_VALID="FALSE" MPD_INDEX="1" NAME="MCH0" TYPE="TARGET"/> + <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_VALID="FALSE" MPD_INDEX="2" NAME="MCH1" TYPE="TARGET"/> + <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_VALID="FALSE" MPD_INDEX="3" NAME="MCH2" TYPE="TARGET"/> + <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_VALID="FALSE" MPD_INDEX="4" NAME="MCH3" TYPE="TARGET"/> + </MODULE> + <MODULE HWVERSION="3.00.b" INSTANCE="PCIe_Bridge" IPTYPE="PERIPHERAL" MHS_INDEX="11" MODCLASS="PERIPHERAL" MODTYPE="plbv46_pcie"> + <DESCRIPTION TYPE="SHORT">PLBv46 IP Interface (IPIF) to LogicCORE PCI Express Bridge</DESCRIPTION> + <DESCRIPTION TYPE="LONG">Bridge between the PLBv46 IPIF and the Xilinx LogiCORE PCI Express Interface core</DESCRIPTION> + <DOCUMENTATION> + <DOCUMENT SOURCE="c:/devtools/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_pcie_v3_00_b/doc/plbv46_pcie.pdf" TYPE="IP"/> + </DOCUMENTATION> + <LICENSEINFO ICON_NAME="ps_core_preferred"/> + <PARAMETER MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex5"> + <DESCRIPTION>Device Family</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="1" NAME="C_IPIFBAR_NUM" TYPE="INTEGER" VALUE="2"> + <DESCRIPTION>Number of IPIF devices</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="2" NAME="C_INCLUDE_BAROFFSET_REG" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Include Registers for Each IPIF BAR High-order Bits to be Substituted in Translation.</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="3" NAME="C_PCIBAR_NUM" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Number of PCI Devices</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="4" NAME="C_NO_OF_LANES" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Number of Lanes</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="5" NAME="C_DEVICE_ID" TYPE="std_logic_vector" VALUE="0x0505"> + <DESCRIPTION>PCI Configuration Space Header Device ID</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="6" NAME="C_VENDOR_ID" TYPE="std_logic_vector" VALUE="0x10EE"> + <DESCRIPTION>PCI Configuration Space Header Vendor ID</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="7" NAME="C_CLASS_CODE" TYPE="std_logic_vector" VALUE="0x058000"> + <DESCRIPTION>PCI Configuration Space Header Class Code</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="8" NAME="C_REV_ID" TYPE="std_logic_vector" VALUE="0x00"> + <DESCRIPTION>PCI Configuration Space Header Rev ID</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="9" NAME="C_SUBSYSTEM_ID" TYPE="std_logic_vector" VALUE="0x0000"> + <DESCRIPTION>PCI Configuration Space Header Subsystem ID</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="10" NAME="C_SUBSYSTEM_VENDOR_ID" TYPE="std_logic_vector" VALUE="0x0000"> + <DESCRIPTION>PCI Configuration Space Header Subsystem Vendor ID</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="11" NAME="C_COMP_TIMEOUT" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Completion Timeout</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_SUBFAMILY" TYPE="STRING" VALUE="fx"> + <DESCRIPTION>Device Sub Family</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="13" NAME="C_MPLB_AWIDTH" TYPE="INTEGER" VALUE="32"> + <DESCRIPTION>Master Address Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="14" NAME="C_MPLB_DWIDTH" TYPE="INTEGER" VALUE="128"> + <DESCRIPTION>Master Data Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="15" NAME="C_MPLB_SMALLEST_SLAVE" TYPE="INTEGER" VALUE="128"> + <DESCRIPTION>Smallest Master Data Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="16" NAME="C_MPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="64"> + <DESCRIPTION>Native Data Bus Width of PLB Master</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="17" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="18" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Number of PLB Masters</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="19" NAME="C_SPLB_SMALLEST_MASTER" TYPE="INTEGER" VALUE="128"> + <DESCRIPTION>Smallest Master Data Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="20" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32"> + <DESCRIPTION>PLB Address Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" MPD_INDEX="21" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x85c00000"> + <DESCRIPTION>Base Address</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" MPD_INDEX="22" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x85c0ffff"> + <DESCRIPTION>High Address</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="23" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="128"> + <DESCRIPTION>PLB Data Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="24" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="64"> + <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="25" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="BRIDGE" CHANGEDBY="USER" MPD_INDEX="26" NAME="C_IPIFBAR_0" TYPE="std_logic_vector" VALUE="0xc0000000"> + <DESCRIPTION>IPIF BAR0 Base Address</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="BRIDGE" CHANGEDBY="USER" MPD_INDEX="27" NAME="C_IPIFBAR_1" TYPE="std_logic_vector" VALUE="0xe0000000"> + <DESCRIPTION>IPIF BAR1 Base Address</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="BRIDGE" MPD_INDEX="28" NAME="C_IPIFBAR_2" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"> + <DESCRIPTION>IPIF BAR2 Base Address</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="BRIDGE" MPD_INDEX="29" NAME="C_IPIFBAR_3" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"> + <DESCRIPTION>IPIF BAR3 Base Address</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="BRIDGE" MPD_INDEX="30" NAME="C_IPIFBAR_4" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"> + <DESCRIPTION>IPIF BAR4 Base Address</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="BRIDGE" MPD_INDEX="31" NAME="C_IPIFBAR_5" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"> + <DESCRIPTION>IPIF BAR5 Base Address</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="BRIDGE" CHANGEDBY="USER" MPD_INDEX="32" NAME="C_IPIFBAR_HIGHADDR_0" TYPE="std_logic_vector" VALUE="0xdfffffff"> + <DESCRIPTION>IPIF BAR0 High Address</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="BRIDGE" CHANGEDBY="USER" MPD_INDEX="33" NAME="C_IPIFBAR_HIGHADDR_1" TYPE="std_logic_vector" VALUE="0xefffffff"> + <DESCRIPTION>IPIF BAR1 High Address</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="BRIDGE" MPD_INDEX="34" NAME="C_IPIFBAR_HIGHADDR_2" TYPE="std_logic_vector" VALUE="0x00000000"> + <DESCRIPTION>IPIF BAR2 High Address</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="BRIDGE" MPD_INDEX="35" NAME="C_IPIFBAR_HIGHADDR_3" TYPE="std_logic_vector" VALUE="0x00000000"> + <DESCRIPTION>IPIF BAR3 High Address</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="BRIDGE" MPD_INDEX="36" NAME="C_IPIFBAR_HIGHADDR_4" TYPE="std_logic_vector" VALUE="0x00000000"> + <DESCRIPTION>IPIF BAR4 High Address</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="BRIDGE" MPD_INDEX="37" NAME="C_IPIFBAR_HIGHADDR_5" TYPE="std_logic_vector" VALUE="0x00000000"> + <DESCRIPTION>IPIF BAR5 High Address</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="38" NAME="C_IPIFBAR2PCIBAR_0" TYPE="std_logic_vector" VALUE="0x00000000"> + <DESCRIPTION>Remote PCI device BAR to which IPIF BAR0 is translated when configured with FIFOs +</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="39" NAME="C_IPIFBAR2PCIBAR_1" TYPE="std_logic_vector" VALUE="0x00000000"> + <DESCRIPTION>Remote PCI device BAR to which IPIF BAR1 is translated when configured with FIFOs +</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="40" NAME="C_IPIFBAR2PCIBAR_2" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"> + <DESCRIPTION>Remote PCI device BAR to which IPIF BAR2 is translated when configured with FIFOs +</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="41" NAME="C_IPIFBAR2PCIBAR_3" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"> + <DESCRIPTION>Remote PCI device BAR to which IPIF BAR3 is translated when configured with FIFOs +</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="42" NAME="C_IPIFBAR2PCIBAR_4" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"> + <DESCRIPTION>Remote PCI device BAR to which IPIF BAR4 is translated when configured with FIFOs +</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="43" NAME="C_IPIFBAR2PCIBAR_5" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"> + <DESCRIPTION>Remote PCI device BAR to which IPIF BAR5 is translated when configured with FIFOs +</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="44" NAME="C_IPIFBAR_AS_0" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>IPIF BAR 0 Address Size</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="45" NAME="C_IPIFBAR_AS_1" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>IPIF BAR 1 Address Size</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="46" NAME="C_IPIFBAR_AS_2" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>IPIF BAR 2 Address Size</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="47" NAME="C_IPIFBAR_AS_3" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>IPIF BAR 3 Address Size</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="48" NAME="C_IPIFBAR_AS_4" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>IPIF BAR 4 Address Size</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="49" NAME="C_IPIFBAR_AS_5" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>IPIF BAR 5 Address Size</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="50" NAME="C_PCIBAR2IPIFBAR_0" TYPE="std_logic_vector" VALUE="0xf8000000"> + <DESCRIPTION>Remote PLB device BAR to which PCI BAR0 is translated when configured with FIFOs</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="51" NAME="C_PCIBAR2IPIFBAR_1" TYPE="std_logic_vector" VALUE="0x00000000"> + <DESCRIPTION>Remote PLB device BAR to which PCI BAR1 is translated when configured with FIFOs</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="52" NAME="C_PCIBAR2IPIFBAR_2" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"> + <DESCRIPTION>Remote PLB device BAR to which PCI BAR2 is translated when configured with FIFOs</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="53" NAME="C_PCIBAR_LEN_0" TYPE="INTEGER" VALUE="20"> + <DESCRIPTION>Power of 2 defining the Size in Bytes of PCI BAR0 Space</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="54" NAME="C_PCIBAR_LEN_1" TYPE="INTEGER" VALUE="28"> + <DESCRIPTION>Power of 2 defining the Size in Bytes of PCI BAR1 Space</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="55" NAME="C_PCIBAR_LEN_2" TYPE="INTEGER" VALUE="16"> + <DESCRIPTION>Power of 2 defining the Size in Bytes of PCI BAR2 Space</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="56" NAME="C_BOARD" TYPE="STRING" VALUE="ml507"> + <DESCRIPTION>Type of Board</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="57" NAME="C_DEVICE" TYPE="STRING" VALUE="5vfx70t"> + <DESCRIPTION>Device Name</DESCRIPTION> + </PARAMETER> + <MEMORYMAP> + <MEMRANGE BASEDECIMAL="2243952640" BASENAME="C_BASEADDR" BASEVALUE="0x85c00000" HIGHDECIMAL="2244018175" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x85c0ffff" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K"> + <SLVINTERFACES> + <BUSINTERFACE NAME="SPLB"/> + </SLVINTERFACES> + </MEMRANGE> + <MEMRANGE BASEDECIMAL="3221225472" BASENAME="C_IPIFBAR_0" BASEVALUE="0xc0000000" HIGHDECIMAL="3758096383" HIGHNAME="C_IPIFBAR_HIGHADDR_0" HIGHVALUE="0xdfffffff" MEMTYPE="BRIDGE" SIZE="536870912" SIZEABRV="512M"> + <SLVINTERFACES> + <BUSINTERFACE NAME="SPLB"/> + </SLVINTERFACES> + </MEMRANGE> + <MEMRANGE BASEDECIMAL="3758096384" BASENAME="C_IPIFBAR_1" BASEVALUE="0xe0000000" HIGHDECIMAL="4026531839" HIGHNAME="C_IPIFBAR_HIGHADDR_1" HIGHVALUE="0xefffffff" MEMTYPE="BRIDGE" SIZE="268435456" SIZEABRV="256M"> + <SLVINTERFACES> + <BUSINTERFACE NAME="SPLB"/> + </SLVINTERFACES> + </MEMRANGE> + <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_IPIFBAR_2" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_IPIFBAR_HIGHADDR_2" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="BRIDGE" SIZE="0" SIZEABRV="U"> + <SLVINTERFACES> + <BUSINTERFACE NAME="SPLB"/> + </SLVINTERFACES> + </MEMRANGE> + <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_IPIFBAR_3" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_IPIFBAR_HIGHADDR_3" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="BRIDGE" SIZE="0" SIZEABRV="U"> + <SLVINTERFACES> + <BUSINTERFACE NAME="SPLB"/> + </SLVINTERFACES> + </MEMRANGE> + <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_IPIFBAR_4" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_IPIFBAR_HIGHADDR_4" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="BRIDGE" SIZE="0" SIZEABRV="U"> + <SLVINTERFACES> + <BUSINTERFACE NAME="SPLB"/> + </SLVINTERFACES> + </MEMRANGE> + <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_IPIFBAR_5" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_IPIFBAR_HIGHADDR_5" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="BRIDGE" SIZE="0" SIZEABRV="U"> + <SLVINTERFACES> + <BUSINTERFACE NAME="SPLB"/> + </SLVINTERFACES> + </MEMRANGE> + </MEMORYMAP> + <PORT DIR="I" IS_INMHS="TRUE" MHS_INDEX="0" MPD_INDEX="74" NAME="PERSTN" SIGNAME="net_vcc"/> + <PORT DIR="I" IS_INMHS="TRUE" MHS_INDEX="1" MPD_INDEX="75" NAME="REFCLK" SIGNAME="PCIe_Diff_Clk"/> + <PORT DIR="I" IS_INMHS="TRUE" MHS_INDEX="2" MPD_INDEX="78" NAME="RXN" SIGNAME="fpga_0_PCIe_Bridge_RXN_pin" VECFORMULA="[(C_NO_OF_LANES-1):0]"/> + <PORT DIR="I" IS_INMHS="TRUE" MHS_INDEX="3" MPD_INDEX="79" NAME="RXP" SIGNAME="fpga_0_PCIe_Bridge_RXP_pin" VECFORMULA="[(C_NO_OF_LANES-1):0]"/> + <PORT DIR="O" IS_INMHS="TRUE" MHS_INDEX="4" MPD_INDEX="80" NAME="TXN" SIGNAME="fpga_0_PCIe_Bridge_TXN_pin" VECFORMULA="[(C_NO_OF_LANES-1):0]"/> + <PORT DIR="O" IS_INMHS="TRUE" MHS_INDEX="5" MPD_INDEX="81" NAME="TXP" SIGNAME="fpga_0_PCIe_Bridge_TXP_pin" VECFORMULA="[(C_NO_OF_LANES-1):0]"/> + <PORT DIR="I" IS_INMHS="TRUE" MHS_INDEX="6" MPD_INDEX="83" NAME="MSI_request" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="net_gnd"/> + <PORT BUS="MPLB" CLKFREQUENCY="125000000" DEF_SIGNAME="clk_125_0000MHzPLL0_ADJUST" DIR="I" MPD_INDEX="0" NAME="MPLB_Clk" SIGIS="CLK" SIGNAME="clk_125_0000MHzPLL0_ADJUST"/> + <PORT BUS="MPLB" DEF_SIGNAME="ppc440_0_SPLB0_MPLB_Rst" DIR="I" MPD_INDEX="1" NAME="MPLB_Rst" SIGIS="RST" SIGNAME="ppc440_0_SPLB0_MPLB_Rst"/> + <PORT BUS="MPLB" DEF_SIGNAME="ppc440_0_SPLB0_PLB_MTimeout" DIR="I" MPD_INDEX="2" NAME="PLB_MTimeout" SIGNAME="ppc440_0_SPLB0_PLB_MTimeout"/> + <PORT BUS="MPLB" DEF_SIGNAME="ppc440_0_SPLB0_PLB_MIRQ" DIR="I" MPD_INDEX="3" NAME="PLB_MIRQ" SIGNAME="ppc440_0_SPLB0_PLB_MIRQ"/> + <PORT BUS="MPLB" DEF_SIGNAME="ppc440_0_SPLB0_PLB_MAddrAck" DIR="I" MPD_INDEX="4" NAME="PLB_MAddrAck" SIGNAME="ppc440_0_SPLB0_PLB_MAddrAck"/> + <PORT BUS="MPLB" DEF_SIGNAME="ppc440_0_SPLB0_PLB_MSSize" DIR="I" MPD_INDEX="5" NAME="PLB_MSSize" SIGNAME="ppc440_0_SPLB0_PLB_MSSize" VECFORMULA="[0:1]"/> + <PORT BUS="MPLB" DEF_SIGNAME="ppc440_0_SPLB0_PLB_MRearbitrate" DIR="I" MPD_INDEX="6" NAME="PLB_MRearbitrate" SIGNAME="ppc440_0_SPLB0_PLB_MRearbitrate"/> + <PORT BUS="MPLB" DEF_SIGNAME="ppc440_0_SPLB0_PLB_MBusy" DIR="I" MPD_INDEX="7" NAME="PLB_MBusy" SIGNAME="ppc440_0_SPLB0_PLB_MBusy"/> + <PORT BUS="MPLB" DEF_SIGNAME="ppc440_0_SPLB0_PLB_MRdErr" DIR="I" MPD_INDEX="8" NAME="PLB_MRdErr" SIGNAME="ppc440_0_SPLB0_PLB_MRdErr"/> + <PORT BUS="MPLB" DEF_SIGNAME="ppc440_0_SPLB0_PLB_MWrErr" DIR="I" MPD_INDEX="9" NAME="PLB_MWrErr" SIGNAME="ppc440_0_SPLB0_PLB_MWrErr"/> + <PORT BUS="MPLB" DEF_SIGNAME="ppc440_0_SPLB0_PLB_MWrDAck" DIR="I" MPD_INDEX="10" NAME="PLB_MWrDAck" SIGNAME="ppc440_0_SPLB0_PLB_MWrDAck"/> + <PORT BUS="MPLB" DEF_SIGNAME="ppc440_0_SPLB0_PLB_MRdDBus" DIR="I" MPD_INDEX="11" NAME="PLB_MRdDBus" SIGNAME="ppc440_0_SPLB0_PLB_MRdDBus" VECFORMULA="[0:(C_MPLB_DWIDTH-1)]"/> + <PORT BUS="MPLB" DEF_SIGNAME="ppc440_0_SPLB0_PLB_MRdWdAddr" DIR="I" MPD_INDEX="12" NAME="PLB_MRdWdAddr" SIGNAME="ppc440_0_SPLB0_PLB_MRdWdAddr" VECFORMULA="[0:3]"/> + <PORT BUS="MPLB" DEF_SIGNAME="ppc440_0_SPLB0_PLB_MRdDAck" DIR="I" MPD_INDEX="13" NAME="PLB_MRdDAck" SIGNAME="ppc440_0_SPLB0_PLB_MRdDAck"/> + <PORT BUS="MPLB" DEF_SIGNAME="ppc440_0_SPLB0_PLB_MRdBTerm" DIR="I" MPD_INDEX="14" NAME="PLB_MRdBTerm" SIGNAME="ppc440_0_SPLB0_PLB_MRdBTerm"/> + <PORT BUS="MPLB" DEF_SIGNAME="ppc440_0_SPLB0_PLB_MWrBTerm" DIR="I" MPD_INDEX="15" NAME="PLB_MWrBTerm" SIGNAME="ppc440_0_SPLB0_PLB_MWrBTerm"/> + <PORT BUS="MPLB" DEF_SIGNAME="ppc440_0_SPLB0_M_request" DIR="O" MPD_INDEX="16" NAME="M_request" SIGNAME="ppc440_0_SPLB0_M_request"/> + <PORT BUS="MPLB" DEF_SIGNAME="ppc440_0_SPLB0_M_priority" DIR="O" MPD_INDEX="17" NAME="M_priority" SIGNAME="ppc440_0_SPLB0_M_priority" VECFORMULA="[0:1]"/> + <PORT BUS="MPLB" DEF_SIGNAME="ppc440_0_SPLB0_M_busLock" DIR="O" MPD_INDEX="18" NAME="M_buslock" SIGNAME="ppc440_0_SPLB0_M_busLock"/> + <PORT BUS="MPLB" DEF_SIGNAME="ppc440_0_SPLB0_M_RNW" DIR="O" MPD_INDEX="19" NAME="M_RNW" SIGNAME="ppc440_0_SPLB0_M_RNW"/> + <PORT BUS="MPLB" DEF_SIGNAME="ppc440_0_SPLB0_M_BE" DIR="O" MPD_INDEX="20" NAME="M_BE" SIGNAME="ppc440_0_SPLB0_M_BE" VECFORMULA="[0:((C_MPLB_DWIDTH/8)-1)]"/> + <PORT BUS="MPLB" DEF_SIGNAME="ppc440_0_SPLB0_M_MSize" DIR="O" MPD_INDEX="21" NAME="M_MSize" SIGNAME="ppc440_0_SPLB0_M_MSize" VECFORMULA="[0:1]"/> + <PORT BUS="MPLB" DEF_SIGNAME="ppc440_0_SPLB0_M_size" DIR="O" MPD_INDEX="22" NAME="M_size" SIGNAME="ppc440_0_SPLB0_M_size" VECFORMULA="[0:3]"/> + <PORT BUS="MPLB" DEF_SIGNAME="ppc440_0_SPLB0_M_type" DIR="O" MPD_INDEX="23" NAME="M_type" SIGNAME="ppc440_0_SPLB0_M_type" VECFORMULA="[0:2]"/> + <PORT BUS="MPLB" DEF_SIGNAME="ppc440_0_SPLB0_M_lockErr" DIR="O" MPD_INDEX="24" NAME="M_lockErr" SIGNAME="ppc440_0_SPLB0_M_lockErr"/> + <PORT BUS="MPLB" DEF_SIGNAME="ppc440_0_SPLB0_M_abort" DIR="O" MPD_INDEX="25" NAME="M_abort" SIGNAME="ppc440_0_SPLB0_M_abort"/> + <PORT BUS="MPLB" DEF_SIGNAME="ppc440_0_SPLB0_M_TAttribute" DIR="O" MPD_INDEX="26" NAME="M_TAttribute" SIGNAME="ppc440_0_SPLB0_M_TAttribute" VECFORMULA="[0:15]"/> + <PORT BUS="MPLB" DEF_SIGNAME="ppc440_0_SPLB0_M_UABus" DIR="O" MPD_INDEX="27" NAME="M_UABus" SIGNAME="ppc440_0_SPLB0_M_UABus" VECFORMULA="[0:31]"/> + <PORT BUS="MPLB" DEF_SIGNAME="ppc440_0_SPLB0_M_ABus" DIR="O" MPD_INDEX="28" NAME="M_ABus" SIGNAME="ppc440_0_SPLB0_M_ABus" VECFORMULA="[0:(C_MPLB_AWIDTH-1)]"/> + <PORT BUS="MPLB" DEF_SIGNAME="ppc440_0_SPLB0_M_wrDBus" DIR="O" MPD_INDEX="29" NAME="M_wrDBus" SIGNAME="ppc440_0_SPLB0_M_wrDBus" VECFORMULA="[0:(C_MPLB_DWIDTH-1)]"/> + <PORT BUS="MPLB" DEF_SIGNAME="ppc440_0_SPLB0_M_wrBurst" DIR="O" MPD_INDEX="30" NAME="M_wrBurst" SIGNAME="ppc440_0_SPLB0_M_wrBurst"/> + <PORT BUS="MPLB" DEF_SIGNAME="ppc440_0_SPLB0_M_rdBurst" DIR="O" MPD_INDEX="31" NAME="M_rdBurst" SIGNAME="ppc440_0_SPLB0_M_rdBurst"/> + <PORT BUS="SPLB" CLKFREQUENCY="125000000" DEF_SIGNAME="clk_125_0000MHzPLL0_ADJUST" DIR="I" MPD_INDEX="32" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_125_0000MHzPLL0_ADJUST"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_SPLB_Rst" DIR="I" MPD_INDEX="33" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="plb_v46_0_SPLB_Rst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_ABus" DIR="I" MPD_INDEX="34" NAME="PLB_ABus" SIGNAME="plb_v46_0_PLB_ABus" VECFORMULA="[0:31]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_UABus" DIR="I" MPD_INDEX="35" NAME="PLB_UABus" SIGNAME="plb_v46_0_PLB_UABus" VECFORMULA="[0:31]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_PAValid" DIR="I" MPD_INDEX="36" NAME="PLB_PAValid" SIGNAME="plb_v46_0_PLB_PAValid"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_SAValid" DIR="I" MPD_INDEX="37" NAME="PLB_SAValid" SIGNAME="plb_v46_0_PLB_SAValid"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPrim" DIR="I" MPD_INDEX="38" NAME="PLB_rdPrim" SIGNAME="plb_v46_0_PLB_rdPrim"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPrim" DIR="I" MPD_INDEX="39" NAME="PLB_wrPrim" SIGNAME="plb_v46_0_PLB_wrPrim"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_masterID" DIR="I" MPD_INDEX="40" NAME="PLB_masterID" SIGNAME="plb_v46_0_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_abort" DIR="I" MPD_INDEX="41" NAME="PLB_abort" SIGNAME="plb_v46_0_PLB_abort"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_busLock" DIR="I" MPD_INDEX="42" NAME="PLB_busLock" SIGNAME="plb_v46_0_PLB_busLock"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_RNW" DIR="I" MPD_INDEX="43" NAME="PLB_RNW" SIGNAME="plb_v46_0_PLB_RNW"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_BE" DIR="I" MPD_INDEX="44" NAME="PLB_BE" SIGNAME="plb_v46_0_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_MSize" DIR="I" MPD_INDEX="45" NAME="PLB_MSize" SIGNAME="plb_v46_0_PLB_MSize" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_size" DIR="I" MPD_INDEX="46" NAME="PLB_size" SIGNAME="plb_v46_0_PLB_size" VECFORMULA="[0:3]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_type" DIR="I" MPD_INDEX="47" NAME="PLB_type" SIGNAME="plb_v46_0_PLB_type" VECFORMULA="[0:2]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_lockErr" DIR="I" MPD_INDEX="48" NAME="PLB_lockErr" SIGNAME="plb_v46_0_PLB_lockErr"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrDBus" DIR="I" MPD_INDEX="49" NAME="PLB_wrDBus" SIGNAME="plb_v46_0_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrBurst" DIR="I" MPD_INDEX="50" NAME="PLB_wrBurst" SIGNAME="plb_v46_0_PLB_wrBurst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdBurst" DIR="I" MPD_INDEX="51" NAME="PLB_rdBurst" SIGNAME="plb_v46_0_PLB_rdBurst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPendReq" DIR="I" MPD_INDEX="52" NAME="PLB_wrPendReq" SIGNAME="plb_v46_0_PLB_wrPendReq"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPendReq" DIR="I" MPD_INDEX="53" NAME="PLB_rdPendReq" SIGNAME="plb_v46_0_PLB_rdPendReq"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPendPri" DIR="I" MPD_INDEX="54" NAME="PLB_wrPendPri" SIGNAME="plb_v46_0_PLB_wrPendPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPendPri" DIR="I" MPD_INDEX="55" NAME="PLB_rdPendPri" SIGNAME="plb_v46_0_PLB_rdPendPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_reqPri" DIR="I" MPD_INDEX="56" NAME="PLB_reqPri" SIGNAME="plb_v46_0_PLB_reqPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_TAttribute" DIR="I" MPD_INDEX="57" NAME="PLB_TAttribute" SIGNAME="plb_v46_0_PLB_TAttribute" VECFORMULA="[0:15]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_addrAck" DIR="O" MPD_INDEX="58" NAME="Sl_addrAck" SIGNAME="plb_v46_0_Sl_addrAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_SSize" DIR="O" MPD_INDEX="59" NAME="Sl_SSize" SIGNAME="plb_v46_0_Sl_SSize" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wait" DIR="O" MPD_INDEX="60" NAME="Sl_wait" SIGNAME="plb_v46_0_Sl_wait"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rearbitrate" DIR="O" MPD_INDEX="61" NAME="Sl_rearbitrate" SIGNAME="plb_v46_0_Sl_rearbitrate"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrDAck" DIR="O" MPD_INDEX="62" NAME="Sl_wrDAck" SIGNAME="plb_v46_0_Sl_wrDAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrComp" DIR="O" MPD_INDEX="63" NAME="Sl_wrComp" SIGNAME="plb_v46_0_Sl_wrComp"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrBTerm" DIR="O" MPD_INDEX="64" NAME="Sl_wrBTerm" SIGNAME="plb_v46_0_Sl_wrBTerm"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdDBus" DIR="O" MPD_INDEX="65" NAME="Sl_rdDBus" SIGNAME="plb_v46_0_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdWdAddr" DIR="O" MPD_INDEX="66" NAME="Sl_rdWdAddr" SIGNAME="plb_v46_0_Sl_rdWdAddr" VECFORMULA="[0:3]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdDAck" DIR="O" MPD_INDEX="67" NAME="Sl_rdDAck" SIGNAME="plb_v46_0_Sl_rdDAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdComp" DIR="O" MPD_INDEX="68" NAME="Sl_rdComp" SIGNAME="plb_v46_0_Sl_rdComp"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdBTerm" DIR="O" MPD_INDEX="69" NAME="Sl_rdBTerm" SIGNAME="plb_v46_0_Sl_rdBTerm"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MBusy" DIR="O" MPD_INDEX="70" NAME="Sl_MBusy" SIGNAME="plb_v46_0_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MWrErr" DIR="O" MPD_INDEX="71" NAME="Sl_MWrErr" SIGNAME="plb_v46_0_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MRdErr" DIR="O" MPD_INDEX="72" NAME="Sl_MRdErr" SIGNAME="plb_v46_0_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MIRQ" DIR="O" MPD_INDEX="73" NAME="Sl_MIRQ" SIGNAME="plb_v46_0_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT DIR="O" MPD_INDEX="76" NAME="Bridge_Clk" SIGNAME="__NOC__"/> + <PORT DIR="O" MPD_INDEX="77" NAME="LinkUp" SIGNAME="__NOC__"/> + <PORT DIR="O" MPD_INDEX="82" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/> + <BUSINTERFACE BUSNAME="plb_v46_0" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INMHS="TRUE" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE"/> + <BUSINTERFACE BUSNAME="ppc440_0_SPLB0" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INMHS="TRUE" MPD_INDEX="1" NAME="MPLB" TYPE="MASTER"/> + </MODULE> + <MODULE BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" HWVERSION="1.04.a" INSTANCE="ppc440_0_SPLB0" IPTYPE="BUS" MHS_INDEX="12" MODCLASS="BUS" MODTYPE="plb_v46"> + <DESCRIPTION TYPE="SHORT">Processor Local Bus (PLB) 4.6</DESCRIPTION> + <DESCRIPTION TYPE="LONG">'Xilinx 64-bit Processor Local Bus (PLB) consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units with a a three-cycle only arbitration feature'</DESCRIPTION> + <DOCUMENTATION> + <DOCUMENT SOURCE="c:/devtools/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/plb_v46_v1_04_a/doc/plb_v46.pdf" TYPE="IP"/> + </DOCUMENTATION> + <LICENSEINFO ICON_NAME="ps_core_preferred"/> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_PLBV46_NUM_MASTERS" TYPE="integer" VALUE="1"> + <DESCRIPTION>Number of PLB Masters</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_PLBV46_NUM_SLAVES" TYPE="integer" VALUE="1"> + <DESCRIPTION>Number of PLB Slaves</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_PLBV46_MID_WIDTH" TYPE="integer" VALUE="1"> + <DESCRIPTION>PLB Master ID Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="3" NAME="C_PLBV46_AWIDTH" TYPE="integer" VALUE="32"> + <DESCRIPTION>PLB Address Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_PLBV46_DWIDTH" TYPE="integer" VALUE="128"> + <DESCRIPTION>PLB Data Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="5" NAME="C_DCR_INTFCE" TYPE="integer" VALUE="0"> + <DESCRIPTION>Include DCR Interface and Error Registers</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="6" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0b1111111111"> + <DESCRIPTION>Base Address</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="7" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0b0000000000"> + <DESCRIPTION>High Address</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="8" NAME="C_DCR_AWIDTH" TYPE="integer" VALUE="10"> + <DESCRIPTION>DCR Address Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="9" NAME="C_DCR_DWIDTH" TYPE="integer" VALUE="32"> + <DESCRIPTION>DCR Data Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="10" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1"> + <DESCRIPTION>External Reset Active High </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="11" NAME="C_IRQ_ACTIVE" TYPE="std_logic" VALUE="1"> + <DESCRIPTION>IRQ Active State </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="12" NAME="C_NUM_CLK_PLB2OPB_REARB" TYPE="integer" VALUE="5"> + <DESCRIPTION><qt>Number of PLB Clock Periods a PLB Master that Received a Rearbitrate from an OPB2PLB Bridge on a Read Operation is Denied Grant on the PLB Bus</qt></DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="13" NAME="C_ADDR_PIPELINING_TYPE" TYPE="integer" VALUE="1"> + <DESCRIPTION>Enable Address Pipelining Type</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="14" NAME="C_FAMILY" TYPE="string" VALUE="virtex5"> + <DESCRIPTION>Device Family</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="15" NAME="C_P2P" TYPE="integer" VALUE="0"> + <DESCRIPTION>Optimize PLB for Point-to-point Topology</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="16" NAME="C_ARB_TYPE" TYPE="integer" VALUE="0"> + <DESCRIPTION>Selects the Arbitration Scheme</DESCRIPTION> + </PARAMETER> + <MEMORYMAP> + <MEMRANGE BASEDECIMAL="1023" BASENAME="C_BASEADDR" BASEVALUE="0b1111111111" HIGHDECIMAL="0" HIGHNAME="C_HIGHADDR" HIGHVALUE="0b0000000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x08" SIZE="0" SIZEABRV="U"> + <SLVINTERFACES> + <BUSINTERFACE NAME="SDCR"/> + </SLVINTERFACES> + </MEMRANGE> + </MEMORYMAP> + <PORT CLKFREQUENCY="125000000" DIR="I" IS_INMHS="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="PLB_Clk" SIGIS="CLK" SIGNAME="clk_125_0000MHzPLL0_ADJUST"/> + <PORT DIR="I" IS_INMHS="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="SYS_Rst" SIGIS="RST" SIGNAME="sys_bus_reset"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_Rst" DIR="O" MPD_INDEX="2" NAME="PLB_Rst" SIGIS="RST" SIGNAME="ppc440_0_splb0_PLB_Rst"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_SPLB_Rst" DIR="O" MPD_INDEX="3" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="ppc440_0_splb0_SPLB_Rst" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_MPLB_Rst" DIR="O" MPD_INDEX="4" NAME="MPLB_Rst" SIGIS="RST" SIGNAME="ppc440_0_splb0_MPLB_Rst" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="5" NAME="PLB_dcrAck" SIGNAME="__NOC__"/> + <PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="6" NAME="PLB_dcrDBus" SIGNAME="__NOC__" VECFORMULA="[0:C_DCR_DWIDTH-1]"/> + <PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="7" NAME="DCR_ABus" SIGNAME="__NOC__" VECFORMULA="[0:C_DCR_AWIDTH-1]"/> + <PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="8" NAME="DCR_DBus" SIGNAME="__NOC__" VECFORMULA="[0:C_DCR_DWIDTH-1]"/> + <PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="9" NAME="DCR_Read" SIGNAME="__NOC__"/> + <PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="10" NAME="DCR_Write" SIGNAME="__NOC__"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_M_ABus" DIR="I" MPD_INDEX="11" NAME="M_ABus" SIGNAME="ppc440_0_splb0_M_ABus" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*32)-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_M_UABus" DIR="I" MPD_INDEX="12" NAME="M_UABus" SIGNAME="ppc440_0_splb0_M_UABus" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*32)-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_M_BE" DIR="I" MPD_INDEX="13" NAME="M_BE" SIGNAME="ppc440_0_splb0_M_BE" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*(C_PLBV46_DWIDTH/8))-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_M_RNW" DIR="I" MPD_INDEX="14" NAME="M_RNW" SIGNAME="ppc440_0_splb0_M_RNW" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_M_abort" DIR="I" MPD_INDEX="15" NAME="M_abort" SIGNAME="ppc440_0_splb0_M_abort" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_M_busLock" DIR="I" MPD_INDEX="16" NAME="M_busLock" SIGNAME="ppc440_0_splb0_M_busLock" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_M_TAttribute" DIR="I" MPD_INDEX="17" NAME="M_TAttribute" SIGNAME="ppc440_0_splb0_M_TAttribute" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*16)-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_M_lockErr" DIR="I" MPD_INDEX="18" NAME="M_lockErr" SIGNAME="ppc440_0_splb0_M_lockErr" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_M_MSize" DIR="I" MPD_INDEX="19" NAME="M_MSize" SIGNAME="ppc440_0_splb0_M_MSize" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*2)-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_M_priority" DIR="I" MPD_INDEX="20" NAME="M_priority" SIGNAME="ppc440_0_splb0_M_priority" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*2)-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_M_rdBurst" DIR="I" MPD_INDEX="21" NAME="M_rdBurst" SIGNAME="ppc440_0_splb0_M_rdBurst" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_M_request" DIR="I" MPD_INDEX="22" NAME="M_request" SIGNAME="ppc440_0_splb0_M_request" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_M_size" DIR="I" MPD_INDEX="23" NAME="M_size" SIGNAME="ppc440_0_splb0_M_size" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*4)-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_M_type" DIR="I" MPD_INDEX="24" NAME="M_type" SIGNAME="ppc440_0_splb0_M_type" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*3)-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_M_wrBurst" DIR="I" MPD_INDEX="25" NAME="M_wrBurst" SIGNAME="ppc440_0_splb0_M_wrBurst" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_M_wrDBus" DIR="I" MPD_INDEX="26" NAME="M_wrDBus" SIGNAME="ppc440_0_splb0_M_wrDBus" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_Sl_addrAck" DIR="I" MPD_INDEX="27" NAME="Sl_addrAck" SIGNAME="ppc440_0_splb0_Sl_addrAck" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_Sl_MRdErr" DIR="I" MPD_INDEX="28" NAME="Sl_MRdErr" SIGNAME="ppc440_0_splb0_Sl_MRdErr" VECFORMULA="[0:(C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_Sl_MWrErr" DIR="I" MPD_INDEX="29" NAME="Sl_MWrErr" SIGNAME="ppc440_0_splb0_Sl_MWrErr" VECFORMULA="[0:(C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_Sl_MBusy" DIR="I" MPD_INDEX="30" NAME="Sl_MBusy" SIGNAME="ppc440_0_splb0_Sl_MBusy" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS - 1 ]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_Sl_rdBTerm" DIR="I" MPD_INDEX="31" NAME="Sl_rdBTerm" SIGNAME="ppc440_0_splb0_Sl_rdBTerm" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_Sl_rdComp" DIR="I" MPD_INDEX="32" NAME="Sl_rdComp" SIGNAME="ppc440_0_splb0_Sl_rdComp" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_Sl_rdDAck" DIR="I" MPD_INDEX="33" NAME="Sl_rdDAck" SIGNAME="ppc440_0_splb0_Sl_rdDAck" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_Sl_rdDBus" DIR="I" MPD_INDEX="34" NAME="Sl_rdDBus" SIGNAME="ppc440_0_splb0_Sl_rdDBus" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*C_PLBV46_DWIDTH-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_Sl_rdWdAddr" DIR="I" MPD_INDEX="35" NAME="Sl_rdWdAddr" SIGNAME="ppc440_0_splb0_Sl_rdWdAddr" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*4-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_Sl_rearbitrate" DIR="I" MPD_INDEX="36" NAME="Sl_rearbitrate" SIGNAME="ppc440_0_splb0_Sl_rearbitrate" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_Sl_SSize" DIR="I" MPD_INDEX="37" NAME="Sl_SSize" SIGNAME="ppc440_0_splb0_Sl_SSize" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*2-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_Sl_wait" DIR="I" MPD_INDEX="38" NAME="Sl_wait" SIGNAME="ppc440_0_splb0_Sl_wait" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_Sl_wrBTerm" DIR="I" MPD_INDEX="39" NAME="Sl_wrBTerm" SIGNAME="ppc440_0_splb0_Sl_wrBTerm" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_Sl_wrComp" DIR="I" MPD_INDEX="40" NAME="Sl_wrComp" SIGNAME="ppc440_0_splb0_Sl_wrComp" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_Sl_wrDAck" DIR="I" MPD_INDEX="41" NAME="Sl_wrDAck" SIGNAME="ppc440_0_splb0_Sl_wrDAck" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_Sl_MIRQ" DIR="I" MPD_INDEX="42" NAME="Sl_MIRQ" SIGNAME="ppc440_0_splb0_Sl_MIRQ" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_MIRQ" DIR="O" MPD_INDEX="43" NAME="PLB_MIRQ" SIGNAME="ppc440_0_splb0_PLB_MIRQ" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_ABus" DIR="O" MPD_INDEX="44" NAME="PLB_ABus" SIGNAME="ppc440_0_splb0_PLB_ABus" VECFORMULA="[0:31]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_UABus" DIR="O" MPD_INDEX="45" NAME="PLB_UABus" SIGNAME="ppc440_0_splb0_PLB_UABus" VECFORMULA="[0:31]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_BE" DIR="O" MPD_INDEX="46" NAME="PLB_BE" SIGNAME="ppc440_0_splb0_PLB_BE" VECFORMULA="[0:(C_PLBV46_DWIDTH/8)-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_MAddrAck" DIR="O" MPD_INDEX="47" NAME="PLB_MAddrAck" SIGNAME="ppc440_0_splb0_PLB_MAddrAck" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_MTimeout" DIR="O" MPD_INDEX="48" NAME="PLB_MTimeout" SIGNAME="ppc440_0_splb0_PLB_MTimeout" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_MBusy" DIR="O" MPD_INDEX="49" NAME="PLB_MBusy" SIGNAME="ppc440_0_splb0_PLB_MBusy" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_MRdErr" DIR="O" MPD_INDEX="50" NAME="PLB_MRdErr" SIGNAME="ppc440_0_splb0_PLB_MRdErr" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_MWrErr" DIR="O" MPD_INDEX="51" NAME="PLB_MWrErr" SIGNAME="ppc440_0_splb0_PLB_MWrErr" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_MRdBTerm" DIR="O" MPD_INDEX="52" NAME="PLB_MRdBTerm" SIGNAME="ppc440_0_splb0_PLB_MRdBTerm" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_MRdDAck" DIR="O" MPD_INDEX="53" NAME="PLB_MRdDAck" SIGNAME="ppc440_0_splb0_PLB_MRdDAck" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_MRdDBus" DIR="O" MPD_INDEX="54" NAME="PLB_MRdDBus" SIGNAME="ppc440_0_splb0_PLB_MRdDBus" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_MRdWdAddr" DIR="O" MPD_INDEX="55" NAME="PLB_MRdWdAddr" SIGNAME="ppc440_0_splb0_PLB_MRdWdAddr" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*4)-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_MRearbitrate" DIR="O" MPD_INDEX="56" NAME="PLB_MRearbitrate" SIGNAME="ppc440_0_splb0_PLB_MRearbitrate" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_MWrBTerm" DIR="O" MPD_INDEX="57" NAME="PLB_MWrBTerm" SIGNAME="ppc440_0_splb0_PLB_MWrBTerm" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_MWrDAck" DIR="O" MPD_INDEX="58" NAME="PLB_MWrDAck" SIGNAME="ppc440_0_splb0_PLB_MWrDAck" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_MSSize" DIR="O" MPD_INDEX="59" NAME="PLB_MSSize" SIGNAME="ppc440_0_splb0_PLB_MSSize" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*2)-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_PAValid" DIR="O" MPD_INDEX="60" NAME="PLB_PAValid" SIGNAME="ppc440_0_splb0_PLB_PAValid"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_RNW" DIR="O" MPD_INDEX="61" NAME="PLB_RNW" SIGNAME="ppc440_0_splb0_PLB_RNW"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_SAValid" DIR="O" MPD_INDEX="62" NAME="PLB_SAValid" SIGNAME="ppc440_0_splb0_PLB_SAValid"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_abort" DIR="O" MPD_INDEX="63" NAME="PLB_abort" SIGNAME="ppc440_0_splb0_PLB_abort"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_busLock" DIR="O" MPD_INDEX="64" NAME="PLB_busLock" SIGNAME="ppc440_0_splb0_PLB_busLock"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_TAttribute" DIR="O" MPD_INDEX="65" NAME="PLB_TAttribute" SIGNAME="ppc440_0_splb0_PLB_TAttribute" VECFORMULA="[0:15]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_lockErr" DIR="O" MPD_INDEX="66" NAME="PLB_lockErr" SIGNAME="ppc440_0_splb0_PLB_lockErr"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_masterID" DIR="O" MPD_INDEX="67" NAME="PLB_masterID" SIGNAME="ppc440_0_splb0_PLB_masterID" VECFORMULA="[0:C_PLBV46_MID_WIDTH-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_MSize" DIR="O" MPD_INDEX="68" NAME="PLB_MSize" SIGNAME="ppc440_0_splb0_PLB_MSize" VECFORMULA="[0:1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_rdPendPri" DIR="O" MPD_INDEX="69" NAME="PLB_rdPendPri" SIGNAME="ppc440_0_splb0_PLB_rdPendPri" VECFORMULA="[0:1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_wrPendPri" DIR="O" MPD_INDEX="70" NAME="PLB_wrPendPri" SIGNAME="ppc440_0_splb0_PLB_wrPendPri" VECFORMULA="[0:1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_rdPendReq" DIR="O" MPD_INDEX="71" NAME="PLB_rdPendReq" SIGNAME="ppc440_0_splb0_PLB_rdPendReq"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_wrPendReq" DIR="O" MPD_INDEX="72" NAME="PLB_wrPendReq" SIGNAME="ppc440_0_splb0_PLB_wrPendReq"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_rdBurst" DIR="O" MPD_INDEX="73" NAME="PLB_rdBurst" SIGNAME="ppc440_0_splb0_PLB_rdBurst"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_rdPrim" DIR="O" MPD_INDEX="74" NAME="PLB_rdPrim" SIGNAME="ppc440_0_splb0_PLB_rdPrim" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_reqPri" DIR="O" MPD_INDEX="75" NAME="PLB_reqPri" SIGNAME="ppc440_0_splb0_PLB_reqPri" VECFORMULA="[0:1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_size" DIR="O" MPD_INDEX="76" NAME="PLB_size" SIGNAME="ppc440_0_splb0_PLB_size" VECFORMULA="[0:3]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_type" DIR="O" MPD_INDEX="77" NAME="PLB_type" SIGNAME="ppc440_0_splb0_PLB_type" VECFORMULA="[0:2]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_wrBurst" DIR="O" MPD_INDEX="78" NAME="PLB_wrBurst" SIGNAME="ppc440_0_splb0_PLB_wrBurst"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_wrDBus" DIR="O" MPD_INDEX="79" NAME="PLB_wrDBus" SIGNAME="ppc440_0_splb0_PLB_wrDBus" VECFORMULA="[0:C_PLBV46_DWIDTH-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_wrPrim" DIR="O" MPD_INDEX="80" NAME="PLB_wrPrim" SIGNAME="ppc440_0_splb0_PLB_wrPrim" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_SaddrAck" DIR="O" MPD_INDEX="81" NAME="PLB_SaddrAck" SIGNAME="ppc440_0_splb0_PLB_SaddrAck"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_SMRdErr" DIR="O" MPD_INDEX="82" NAME="PLB_SMRdErr" SIGNAME="ppc440_0_splb0_PLB_SMRdErr" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_SMWrErr" DIR="O" MPD_INDEX="83" NAME="PLB_SMWrErr" SIGNAME="ppc440_0_splb0_PLB_SMWrErr" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_SMBusy" DIR="O" MPD_INDEX="84" NAME="PLB_SMBusy" SIGNAME="ppc440_0_splb0_PLB_SMBusy" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_SrdBTerm" DIR="O" MPD_INDEX="85" NAME="PLB_SrdBTerm" SIGNAME="ppc440_0_splb0_PLB_SrdBTerm"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_SrdComp" DIR="O" MPD_INDEX="86" NAME="PLB_SrdComp" SIGNAME="ppc440_0_splb0_PLB_SrdComp"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_SrdDAck" DIR="O" MPD_INDEX="87" NAME="PLB_SrdDAck" SIGNAME="ppc440_0_splb0_PLB_SrdDAck"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_SrdDBus" DIR="O" MPD_INDEX="88" NAME="PLB_SrdDBus" SIGNAME="ppc440_0_splb0_PLB_SrdDBus" VECFORMULA="[0:C_PLBV46_DWIDTH-1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_SrdWdAddr" DIR="O" MPD_INDEX="89" NAME="PLB_SrdWdAddr" SIGNAME="ppc440_0_splb0_PLB_SrdWdAddr" VECFORMULA="[0:3]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_Srearbitrate" DIR="O" MPD_INDEX="90" NAME="PLB_Srearbitrate" SIGNAME="ppc440_0_splb0_PLB_Srearbitrate"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_Sssize" DIR="O" MPD_INDEX="91" NAME="PLB_Sssize" SIGNAME="ppc440_0_splb0_PLB_Sssize" VECFORMULA="[0:1]"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_Swait" DIR="O" MPD_INDEX="92" NAME="PLB_Swait" SIGNAME="ppc440_0_splb0_PLB_Swait"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_SwrBTerm" DIR="O" MPD_INDEX="93" NAME="PLB_SwrBTerm" SIGNAME="ppc440_0_splb0_PLB_SwrBTerm"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_SwrComp" DIR="O" MPD_INDEX="94" NAME="PLB_SwrComp" SIGNAME="ppc440_0_splb0_PLB_SwrComp"/> + <PORT DEF_SIGNAME="ppc440_0_splb0_PLB_SwrDAck" DIR="O" MPD_INDEX="95" NAME="PLB_SwrDAck" SIGNAME="ppc440_0_splb0_PLB_SwrDAck"/> + <PORT DIR="O" MPD_INDEX="96" NAME="Bus_Error_Det" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/> + <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="DCR" BUSSTD_PSF="DCR" IS_VALID="FALSE" MPD_INDEX="0" NAME="SDCR" TYPE="SLAVE"/> + </MODULE> + <MODULE HWVERSION="2.01.a" INSTANCE="Ethernet_MAC" IPTYPE="PERIPHERAL" MHS_INDEX="13" MODCLASS="PERIPHERAL" MODTYPE="xps_ethernetlite"> + <DESCRIPTION TYPE="SHORT">XPS 10/100 Ethernet MAC Lite</DESCRIPTION> + <DESCRIPTION TYPE="LONG">'IEEE Std. 802.3 MII interface MAC with PLBV46 interface, lightweight implementation'</DESCRIPTION> + <DOCUMENTATION> + <DOCUMENT SOURCE="c:/devtools/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/xps_ethernetlite_v2_01_a/doc/xps_ethernetlite.pdf" TYPE="IP"/> + </DOCUMENTATION> + <LICENSEINFO ICON_NAME="ps_core_preferred"/> + <PARAMETER MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex5"> + <DESCRIPTION>Device Family</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x81000000"> + <DESCRIPTION>Base Address</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" MPD_INDEX="2" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x8100ffff"> + <DESCRIPTION>High Address</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPLB_CLK_PERIOD_PS" TYPE="INTEGER" VALUE="8000"> + <DESCRIPTION>Clock Period of PLB Slave</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="4" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32"> + <DESCRIPTION>PLB Address Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="128"> + <DESCRIPTION>PLB Data Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="6" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="7" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="8" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Number of PLB Masters</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="9" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"> + <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="10" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="11" NAME="C_DUPLEX" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Duplex Mode </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="12" NAME="C_TX_PING_PONG" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Include Second Transmitter Buffer </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="13" NAME="C_RX_PING_PONG" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>Include Second Receiver Buffer </DESCRIPTION> + </PARAMETER> + <MEMORYMAP> + <MEMRANGE BASEDECIMAL="2164260864" BASENAME="C_BASEADDR" BASEVALUE="0x81000000" HIGHDECIMAL="2164326399" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8100ffff" MEMTYPE="REGISTER" MINSIZE="0x02000" SIZE="65536" SIZEABRV="64K"> + <SLVINTERFACES> + <BUSINTERFACE NAME="SPLB"/> + </SLVINTERFACES> + </MEMRANGE> + </MEMORYMAP> + <PORT DIR="I" IS_INMHS="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="PHY_tx_clk" SIGNAME="fpga_0_Ethernet_MAC_PHY_tx_clk_pin"> + <DESCRIPTION>Ethernet Transmit Clock Input</DESCRIPTION> + </PORT> + <PORT DIR="I" IS_INMHS="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="PHY_rx_clk" SIGNAME="fpga_0_Ethernet_MAC_PHY_rx_clk_pin"> + <DESCRIPTION>Ethernet Receive Clock Input</DESCRIPTION> + </PORT> + <PORT DIR="I" IS_INMHS="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="PHY_crs" SIGNAME="fpga_0_Ethernet_MAC_PHY_crs_pin"> + <DESCRIPTION>Ethernet Carrier Sense Input</DESCRIPTION> + </PORT> + <PORT DIR="I" IS_INMHS="TRUE" MHS_INDEX="3" MPD_INDEX="3" NAME="PHY_dv" SIGNAME="fpga_0_Ethernet_MAC_PHY_dv_pin"> + <DESCRIPTION>Ethernet Receive Data Valid</DESCRIPTION> + </PORT> + <PORT DIR="I" ENDIAN="LITTLE" IS_INMHS="TRUE" LSB="0" MHS_INDEX="4" MPD_INDEX="4" MSB="3" NAME="PHY_rx_data" SIGNAME="fpga_0_Ethernet_MAC_PHY_rx_data_pin" VECFORMULA="[3:0]"> + <DESCRIPTION>Ethernet Receive Data Input</DESCRIPTION> + </PORT> + <PORT DIR="I" IS_INMHS="TRUE" MHS_INDEX="5" MPD_INDEX="5" NAME="PHY_col" SIGNAME="fpga_0_Ethernet_MAC_PHY_col_pin"> + <DESCRIPTION>Ethernet Collision Input</DESCRIPTION> + </PORT> + <PORT DIR="I" IS_INMHS="TRUE" MHS_INDEX="6" MPD_INDEX="6" NAME="PHY_rx_er" SIGNAME="fpga_0_Ethernet_MAC_PHY_rx_er_pin"> + <DESCRIPTION>Ethernet Receive Error Input</DESCRIPTION> + </PORT> + <PORT DIR="O" IS_INMHS="TRUE" MHS_INDEX="7" MPD_INDEX="7" NAME="PHY_rst_n" SIGNAME="fpga_0_Ethernet_MAC_PHY_rst_n_pin"> + <DESCRIPTION>Ethernet PHY Reset</DESCRIPTION> + </PORT> + <PORT DIR="O" IS_INMHS="TRUE" MHS_INDEX="8" MPD_INDEX="8" NAME="PHY_tx_en" SIGNAME="fpga_0_Ethernet_MAC_PHY_tx_en_pin"> + <DESCRIPTION>Ethernet Transmit Enable</DESCRIPTION> + </PORT> + <PORT DIR="O" ENDIAN="LITTLE" IS_INMHS="TRUE" LSB="0" MHS_INDEX="9" MPD_INDEX="9" MSB="3" NAME="PHY_tx_data" SIGNAME="fpga_0_Ethernet_MAC_PHY_tx_data_pin" VECFORMULA="[3:0]"> + <DESCRIPTION>Ethernet Transmit Data Output</DESCRIPTION> + </PORT> + <PORT DIR="O" MPD_INDEX="10" NAME="IP2INTC_Irpt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/> + <PORT BUS="SPLB" CLKFREQUENCY="125000000" DEF_SIGNAME="clk_125_0000MHzPLL0_ADJUST" DIR="I" MPD_INDEX="11" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_125_0000MHzPLL0_ADJUST"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_SPLB_Rst" DIR="I" MPD_INDEX="12" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="plb_v46_0_SPLB_Rst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_ABus" DIR="I" MPD_INDEX="13" NAME="PLB_ABus" SIGNAME="plb_v46_0_PLB_ABus" VECFORMULA="[0:(C_SPLB_AWIDTH-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_UABus" DIR="I" MPD_INDEX="14" NAME="PLB_UABus" SIGNAME="plb_v46_0_PLB_UABus" VECFORMULA="[0:31]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_PAValid" DIR="I" MPD_INDEX="15" NAME="PLB_PAValid" SIGNAME="plb_v46_0_PLB_PAValid"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_SAValid" DIR="I" MPD_INDEX="16" NAME="PLB_SAValid" SIGNAME="plb_v46_0_PLB_SAValid"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPrim" DIR="I" MPD_INDEX="17" NAME="PLB_rdPrim" SIGNAME="plb_v46_0_PLB_rdPrim"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPrim" DIR="I" MPD_INDEX="18" NAME="PLB_wrPrim" SIGNAME="plb_v46_0_PLB_wrPrim"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_masterID" DIR="I" MPD_INDEX="19" NAME="PLB_masterID" SIGNAME="plb_v46_0_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_abort" DIR="I" MPD_INDEX="20" NAME="PLB_abort" SIGNAME="plb_v46_0_PLB_abort"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_busLock" DIR="I" MPD_INDEX="21" NAME="PLB_busLock" SIGNAME="plb_v46_0_PLB_busLock"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_RNW" DIR="I" MPD_INDEX="22" NAME="PLB_RNW" SIGNAME="plb_v46_0_PLB_RNW"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_BE" DIR="I" MPD_INDEX="23" NAME="PLB_BE" SIGNAME="plb_v46_0_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_MSize" DIR="I" MPD_INDEX="24" NAME="PLB_MSize" SIGNAME="plb_v46_0_PLB_MSize" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_size" DIR="I" MPD_INDEX="25" NAME="PLB_size" SIGNAME="plb_v46_0_PLB_size" VECFORMULA="[0:3]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_type" DIR="I" MPD_INDEX="26" NAME="PLB_type" SIGNAME="plb_v46_0_PLB_type" VECFORMULA="[0:2]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_lockErr" DIR="I" MPD_INDEX="27" NAME="PLB_lockErr" SIGNAME="plb_v46_0_PLB_lockErr"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrDBus" DIR="I" MPD_INDEX="28" NAME="PLB_wrDBus" SIGNAME="plb_v46_0_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrBurst" DIR="I" MPD_INDEX="29" NAME="PLB_wrBurst" SIGNAME="plb_v46_0_PLB_wrBurst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdBurst" DIR="I" MPD_INDEX="30" NAME="PLB_rdBurst" SIGNAME="plb_v46_0_PLB_rdBurst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPendReq" DIR="I" MPD_INDEX="31" NAME="PLB_wrPendReq" SIGNAME="plb_v46_0_PLB_wrPendReq"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPendReq" DIR="I" MPD_INDEX="32" NAME="PLB_rdPendReq" SIGNAME="plb_v46_0_PLB_rdPendReq"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPendPri" DIR="I" MPD_INDEX="33" NAME="PLB_wrPendPri" SIGNAME="plb_v46_0_PLB_wrPendPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPendPri" DIR="I" MPD_INDEX="34" NAME="PLB_rdPendPri" SIGNAME="plb_v46_0_PLB_rdPendPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_reqPri" DIR="I" MPD_INDEX="35" NAME="PLB_reqPri" SIGNAME="plb_v46_0_PLB_reqPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_TAttribute" DIR="I" MPD_INDEX="36" NAME="PLB_TAttribute" SIGNAME="plb_v46_0_PLB_TAttribute" VECFORMULA="[0:15]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_addrAck" DIR="O" MPD_INDEX="37" NAME="Sl_addrAck" SIGNAME="plb_v46_0_Sl_addrAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_SSize" DIR="O" MPD_INDEX="38" NAME="Sl_SSize" SIGNAME="plb_v46_0_Sl_SSize" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wait" DIR="O" MPD_INDEX="39" NAME="Sl_wait" SIGNAME="plb_v46_0_Sl_wait"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rearbitrate" DIR="O" MPD_INDEX="40" NAME="Sl_rearbitrate" SIGNAME="plb_v46_0_Sl_rearbitrate"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrDAck" DIR="O" MPD_INDEX="41" NAME="Sl_wrDAck" SIGNAME="plb_v46_0_Sl_wrDAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrComp" DIR="O" MPD_INDEX="42" NAME="Sl_wrComp" SIGNAME="plb_v46_0_Sl_wrComp"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrBTerm" DIR="O" MPD_INDEX="43" NAME="Sl_wrBTerm" SIGNAME="plb_v46_0_Sl_wrBTerm"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdDBus" DIR="O" MPD_INDEX="44" NAME="Sl_rdDBus" SIGNAME="plb_v46_0_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdWdAddr" DIR="O" MPD_INDEX="45" NAME="Sl_rdWdAddr" SIGNAME="plb_v46_0_Sl_rdWdAddr" VECFORMULA="[0:3]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdDAck" DIR="O" MPD_INDEX="46" NAME="Sl_rdDAck" SIGNAME="plb_v46_0_Sl_rdDAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdComp" DIR="O" MPD_INDEX="47" NAME="Sl_rdComp" SIGNAME="plb_v46_0_Sl_rdComp"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdBTerm" DIR="O" MPD_INDEX="48" NAME="Sl_rdBTerm" SIGNAME="plb_v46_0_Sl_rdBTerm"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MBusy" DIR="O" MPD_INDEX="49" NAME="Sl_MBusy" SIGNAME="plb_v46_0_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MWrErr" DIR="O" MPD_INDEX="50" NAME="Sl_MWrErr" SIGNAME="plb_v46_0_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MRdErr" DIR="O" MPD_INDEX="51" NAME="Sl_MRdErr" SIGNAME="plb_v46_0_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MIRQ" DIR="O" MPD_INDEX="52" NAME="Sl_MIRQ" SIGNAME="plb_v46_0_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <BUSINTERFACE BUSNAME="plb_v46_0" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INMHS="TRUE" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE"/> + </MODULE> + <MODULE HWVERSION="2.00.b" INSTANCE="DDR2_SDRAM" IPTYPE="PERIPHERAL" MHS_INDEX="14" MODCLASS="MEMORY_CNTLR" MODTYPE="ppc440mc_ddr2"> + <DESCRIPTION TYPE="SHORT">PowerPC 440 DDR2 Memory Controller</DESCRIPTION> + <DESCRIPTION TYPE="LONG">A wrapper to instantiate the PowerPC 440 DDR2 Memory Controller</DESCRIPTION> + <DOCUMENTATION> + <DOCUMENT SOURCE="c:/devtools/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/ppc440mc_ddr2_v2_00_b/doc/ppc440mc_ddr2.pdf" TYPE="IP"/> + </DOCUMENTATION> + <LICENSEINFO ICON_NAME="ps_core_preferred"/> + <PARAMETER MPD_INDEX="0" NAME="C_DDR_BAWIDTH" TYPE="integer" VALUE="2"> + <DESCRIPTION>Bank Address Width of DDR Memory </DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="1" NAME="C_NUM_CLK_PAIRS" TYPE="integer" VALUE="2"> + <DESCRIPTION>Number of Generated DDR Clock Pairs.</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="2" NAME="C_DDR_DWIDTH" TYPE="integer" VALUE="64"> + <DESCRIPTION>Data Bus Width of DDR </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="3" NAME="C_DDR_CAWIDTH" TYPE="integer" VALUE="10"> + <DESCRIPTION>Column Address Width of DDR Memory </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="4" NAME="C_NUM_RANKS_MEM" TYPE="integer" VALUE="1"> + <DESCRIPTION>Number of DDR2 Memory Ranks</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="5" NAME="C_CS_BITS" TYPE="integer" VALUE="0"> + <DESCRIPTION>Number of Chip Select in DDR2 Memory Rank (a.k.a log2C_NUM_RANKS_MEM)</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="6" NAME="C_DDR_DM_WIDTH" TYPE="integer" VALUE="8"> + <DESCRIPTION>DDR2 Data Mask Width</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="7" NAME="C_DQ_BITS" TYPE="integer" VALUE="8"> + <DESCRIPTION>C_DQ_BITS</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="8" NAME="C_DDR2_ODT_WIDTH" TYPE="integer" VALUE="2"> + <DESCRIPTION>DDR2 On Die Termination Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="9" NAME="C_DDR2_ADDT_LAT" TYPE="integer" VALUE="0"> + <DESCRIPTION>Additive Latency of DDR2 Memory </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="10" NAME="C_INCLUDE_ECC_SUPPORT" TYPE="integer" VALUE="0"> + <DESCRIPTION>Support ECC Logic </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="11" NAME="C_DDR2_ODT_SETTING" TYPE="integer" VALUE="1"> + <DESCRIPTION>Setting for On Die Termination</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="12" NAME="C_DQS_BITS" TYPE="integer" VALUE="3"> + <DESCRIPTION>DQS Bit Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="13" NAME="C_DDR_DQS_WIDTH" TYPE="integer" VALUE="8"> + <DESCRIPTION>DDR2 Strobe Width</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="14" NAME="C_DDR_RAWIDTH" TYPE="integer" VALUE="13"> + <DESCRIPTION>Row Address Width of DDR Memory </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="15" NAME="C_DDR_BURST_LENGTH" TYPE="integer" VALUE="4"> + <DESCRIPTION>Burst Length of DDR Memory</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="16" NAME="C_DDR_CAS_LAT" TYPE="integer" VALUE="4"> + <DESCRIPTION>CAS Latency of DDR Memory </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="17" NAME="C_REG_DIMM" TYPE="integer" VALUE="0"> + <DESCRIPTION>Include Support for Registered DIMMs.</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="18" NAME="C_MIB_MC_CLOCK_RATIO" TYPE="integer" VALUE="1"> + <DESCRIPTION>Clock Ratio between CPMINTERCONNECTCLK to DDR2 Clock</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" MPD_INDEX="19" NAME="C_MEM_BASEADDR" VALUE="0x00000000"> + <DESCRIPTION>Memory Base Address </DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" MPD_INDEX="20" NAME="C_MEM_HIGHADDR" VALUE="0x0fffffff"> + <DESCRIPTION>Memory High Address </DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="21" NAME="C_DDR_TREFI" TYPE="integer" VALUE="3900"> + <DESCRIPTION>TREFI of DDR </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="22" NAME="C_DDR_TRAS" TYPE="integer" VALUE="40000"> + <DESCRIPTION>TRAS of DDR </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="23" NAME="C_DDR_TRCD" TYPE="integer" VALUE="15000"> + <DESCRIPTION>TRCD of DDR </DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="24" NAME="C_DDR_TRFC" TYPE="integer" VALUE="75000"> + <DESCRIPTION>TRFC of DDR </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="25" NAME="C_DDR_TRP" TYPE="integer" VALUE="15000"> + <DESCRIPTION>TRP of DDR </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="26" NAME="C_DDR_TRTP" TYPE="integer" VALUE="7500"> + <DESCRIPTION>TRTP of DDR </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="27" NAME="C_DDR_TWR" TYPE="integer" VALUE="15000"> + <DESCRIPTION>TWR of DDR </DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="28" NAME="C_DDR_TWTR" TYPE="integer" VALUE="7500"> + <DESCRIPTION>TWTR of DDR </DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="29" NAME="C_MC_MIBCLK_PERIOD_PS" TYPE="integer" VALUE="8000"> + <DESCRIPTION>Clock Period(ps) of MIB Clock</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="30" NAME="C_IDEL_HIGH_PERF" TYPE="string" VALUE="TRUE"> + <DESCRIPTION>IDELAY High Performance Mode</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="31" NAME="C_SIM_ONLY" TYPE="integer" VALUE="0"> + <DESCRIPTION>SKip 200us Power-up Time for Simulation</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="32" NAME="C_NUM_IDELAYCTRL" TYPE="integer" VALUE="3"> + <DESCRIPTION>Number of IDELAYCTRL Primitives (V4 only) that are explicitly instantiated</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="33" NAME="C_IDELAYCTRL_LOC" TYPE="string" VALUE="IDELAYCTRL_X0Y6-IDELAYCTRL_X0Y2-IDELAYCTRL_X0Y1"> + <DESCRIPTION>LOC Constraints of IDELAYCTRL Primitive</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="34" NAME="C_READ_DATA_PIPELINE" TYPE="integer" VALUE="0"> + <DESCRIPTION>Read Data Pipeline</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="35" NAME="C_DQS_IO_COL" VALUE="0b000000000000000000"> + <DESCRIPTION>IO Column Location of DQS Groups</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="36" NAME="C_DQ_IO_MS" VALUE="0b000000000111010100111101000011110001111000101110110000111100000110111100"> + <DESCRIPTION>Master Slave Location of DQ IO</DESCRIPTION> + </PARAMETER> + <MEMORYMAP> + <MEMRANGE BASEDECIMAL="0" BASENAME="C_MEM_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="268435455" HIGHNAME="C_MEM_HIGHADDR" HIGHVALUE="0x0fffffff" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="268435456" SIZEABRV="256M"> + <SLVINTERFACES> + <BUSINTERFACE NAME="PPC440MC"/> + </SLVINTERFACES> + </MEMRANGE> + </MEMORYMAP> + <PORT CLKFREQUENCY="125000000" DIR="I" IS_INMHS="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="mc_mibclk" SIGIS="CLK" SIGNAME="clk_125_0000MHzPLL0_ADJUST"/> + <PORT CLKFREQUENCY="125000000" DIR="I" IS_INMHS="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="mi_mcclk90" SIGIS="CLK" SIGNAME="clk_125_0000MHz90PLL0_ADJUST"/> + <PORT DIR="I" IS_INMHS="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="mi_mcreset" SIGIS="RST" SIGNAME="sys_bus_reset"/> + <PORT CLKFREQUENCY="62500000" DIR="I" IS_INMHS="TRUE" MHS_INDEX="3" MPD_INDEX="3" NAME="mi_mcclkdiv2" SIGIS="CLK" SIGNAME="clk_62_5000MHzPLL0_ADJUST"/> + <PORT CLKFREQUENCY="200000000" DIR="I" IS_INMHS="TRUE" MHS_INDEX="4" MPD_INDEX="4" NAME="mi_mcclk_200" SIGIS="CLK" SIGNAME="clk_200_0000MHz"/> + <PORT DIR="IO" ENDIAN="LITTLE" IS_INMHS="TRUE" LSB="0" MHS_INDEX="5" MPD_INDEX="17" MSB="63" NAME="DDR2_DQ" SIGNAME="fpga_0_DDR2_SDRAM_DDR2_DQ_pin" VECFORMULA="[(C_DDR_DWIDTH-1):0]"/> + <PORT DIR="IO" ENDIAN="LITTLE" IS_INMHS="TRUE" LSB="0" MHS_INDEX="6" MPD_INDEX="18" MSB="7" NAME="DDR2_DQS" SIGNAME="fpga_0_DDR2_SDRAM_DDR2_DQS_pin" VECFORMULA="[(C_DDR_DQS_WIDTH-1):0]"/> + <PORT DIR="IO" ENDIAN="LITTLE" IS_INMHS="TRUE" LSB="0" MHS_INDEX="7" MPD_INDEX="19" MSB="7" NAME="DDR2_DQS_N" SIGNAME="fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin" VECFORMULA="[(C_DDR_DQS_WIDTH-1):0]"/> + <PORT DIR="O" ENDIAN="LITTLE" IS_INMHS="TRUE" LSB="0" MHS_INDEX="8" MPD_INDEX="20" MSB="12" NAME="DDR2_A" SIGNAME="fpga_0_DDR2_SDRAM_DDR2_A_pin" VECFORMULA="[(C_DDR_RAWIDTH-1):0]"/> + <PORT DIR="O" ENDIAN="LITTLE" IS_INMHS="TRUE" LSB="0" MHS_INDEX="9" MPD_INDEX="21" MSB="1" NAME="DDR2_BA" SIGNAME="fpga_0_DDR2_SDRAM_DDR2_BA_pin" VECFORMULA="[(C_DDR_BAWIDTH-1):0]"/> + <PORT DIR="O" IS_INMHS="TRUE" MHS_INDEX="10" MPD_INDEX="22" NAME="DDR2_RAS_N" SIGNAME="fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin"/> + <PORT DIR="O" IS_INMHS="TRUE" MHS_INDEX="11" MPD_INDEX="23" NAME="DDR2_CAS_N" SIGNAME="fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin"/> + <PORT DIR="O" IS_INMHS="TRUE" MHS_INDEX="12" MPD_INDEX="24" NAME="DDR2_WE_N" SIGNAME="fpga_0_DDR2_SDRAM_DDR2_WE_N_pin"/> + <PORT DIR="O" IS_INMHS="TRUE" MHS_INDEX="13" MPD_INDEX="25" NAME="DDR2_CS_N" SIGNAME="fpga_0_DDR2_SDRAM_DDR2_CS_N_pin" VECFORMULA="[(C_NUM_RANKS_MEM-1):0]"/> + <PORT DIR="O" ENDIAN="LITTLE" IS_INMHS="TRUE" LSB="0" MHS_INDEX="14" MPD_INDEX="26" MSB="1" NAME="DDR2_ODT" SIGNAME="fpga_0_DDR2_SDRAM_DDR2_ODT_pin" VECFORMULA="[(C_DDR2_ODT_WIDTH-1):0]"/> + <PORT DIR="O" IS_INMHS="TRUE" MHS_INDEX="15" MPD_INDEX="27" NAME="DDR2_CKE" SIGNAME="fpga_0_DDR2_SDRAM_DDR2_CKE_pin" VECFORMULA="[(C_NUM_RANKS_MEM-1):0]"/> + <PORT DIR="O" ENDIAN="LITTLE" IS_INMHS="TRUE" LSB="0" MHS_INDEX="16" MPD_INDEX="28" MSB="7" NAME="DDR2_DM" SIGNAME="fpga_0_DDR2_SDRAM_DDR2_DM_pin" VECFORMULA="[(C_DDR_DM_WIDTH-1):0]"/> + <PORT DIR="O" ENDIAN="LITTLE" IS_INMHS="TRUE" LSB="0" MHS_INDEX="17" MPD_INDEX="29" MSB="1" NAME="DDR2_CK" SIGNAME="fpga_0_DDR2_SDRAM_DDR2_CK_pin" VECFORMULA="[(C_NUM_CLK_PAIRS-1):0]"/> + <PORT DIR="O" ENDIAN="LITTLE" IS_INMHS="TRUE" LSB="0" MHS_INDEX="18" MPD_INDEX="30" MSB="1" NAME="DDR2_CK_N" SIGNAME="fpga_0_DDR2_SDRAM_DDR2_CK_N_pin" VECFORMULA="[(C_NUM_CLK_PAIRS-1):0]"/> + <PORT BUS="PPC440MC" DEF_SIGNAME="ppc440_0_PPC440MC_mimcaddressvalid" DIR="I" MPD_INDEX="5" NAME="mi_mcaddressvalid" SIGNAME="ppc440_0_PPC440MC_mimcaddressvalid"/> + <PORT BUS="PPC440MC" DEF_SIGNAME="ppc440_0_PPC440MC_mimcaddress" DIR="I" MPD_INDEX="6" NAME="mi_mcaddress" SIGNAME="ppc440_0_PPC440MC_mimcaddress" VECFORMULA="[0:35]"/> + <PORT BUS="PPC440MC" DEF_SIGNAME="ppc440_0_PPC440MC_mimcbankconflict" DIR="I" MPD_INDEX="7" NAME="mi_mcbankconflict" SIGNAME="ppc440_0_PPC440MC_mimcbankconflict"/> + <PORT BUS="PPC440MC" DEF_SIGNAME="ppc440_0_PPC440MC_mimcrowconflict" DIR="I" MPD_INDEX="8" NAME="mi_mcrowconflict" SIGNAME="ppc440_0_PPC440MC_mimcrowconflict"/> + <PORT BUS="PPC440MC" DEF_SIGNAME="ppc440_0_PPC440MC_mimcbyteenable" DIR="I" MPD_INDEX="9" NAME="mi_mcbyteenable" SIGNAME="ppc440_0_PPC440MC_mimcbyteenable" VECFORMULA="[0:15]"/> + <PORT BUS="PPC440MC" DEF_SIGNAME="ppc440_0_PPC440MC_mimcwritedata" DIR="I" MPD_INDEX="10" NAME="mi_mcwritedata" SIGNAME="ppc440_0_PPC440MC_mimcwritedata" VECFORMULA="[0:127]"/> + <PORT BUS="PPC440MC" DEF_SIGNAME="ppc440_0_PPC440MC_mimcreadnotwrite" DIR="I" MPD_INDEX="11" NAME="mi_mcreadnotwrite" SIGNAME="ppc440_0_PPC440MC_mimcreadnotwrite"/> + <PORT BUS="PPC440MC" DEF_SIGNAME="ppc440_0_PPC440MC_mimcwritedatavalid" DIR="I" MPD_INDEX="12" NAME="mi_mcwritedatavalid" SIGNAME="ppc440_0_PPC440MC_mimcwritedatavalid"/> + <PORT BUS="PPC440MC" DEF_SIGNAME="ppc440_0_PPC440MC_mcmiaddrreadytoaccept" DIR="O" MPD_INDEX="13" NAME="mc_miaddrreadytoaccept" SIGNAME="ppc440_0_PPC440MC_mcmiaddrreadytoaccept"/> + <PORT BUS="PPC440MC" DEF_SIGNAME="ppc440_0_PPC440MC_mcmireaddata" DIR="O" MPD_INDEX="14" NAME="mc_mireaddata" SIGNAME="ppc440_0_PPC440MC_mcmireaddata" VECFORMULA="[0:127]"/> + <PORT BUS="PPC440MC" DEF_SIGNAME="ppc440_0_PPC440MC_mcmireaddataerr" DIR="O" MPD_INDEX="15" NAME="mc_mireaddataerr" SIGNAME="ppc440_0_PPC440MC_mcmireaddataerr"/> + <PORT BUS="PPC440MC" DEF_SIGNAME="ppc440_0_PPC440MC_mcmireaddatavalid" DIR="O" MPD_INDEX="16" NAME="mc_mireaddatavalid" SIGNAME="ppc440_0_PPC440MC_mcmireaddatavalid"/> + <BUSINTERFACE BUSNAME="ppc440_0_PPC440MC" BUSSTD="XIL" BUSSTD_PSF="XIL_PPC440MC" IS_INMHS="TRUE" MPD_INDEX="0" NAME="PPC440MC" TYPE="TARGET"/> + </MODULE> + <MODULE HWVERSION="1.01.a" INSTANCE="SysACE_CompactFlash" IPTYPE="PERIPHERAL" MHS_INDEX="15" MODCLASS="PERIPHERAL" MODTYPE="xps_sysace"> + <DESCRIPTION TYPE="SHORT">XPS System ACE Interface Controller(Compact Flash)</DESCRIPTION> + <DESCRIPTION TYPE="LONG">Interface between the PLBV46 and the Microprocessor Interface (MPU) of the System ACE Compact Flash solution peripheral</DESCRIPTION> + <DOCUMENTATION> + <DOCUMENT SOURCE="c:/devtools/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/xps_sysace_v1_01_a/doc/xps_sysace.pdf" TYPE="IP"/> + </DOCUMENTATION> + <LICENSEINFO ICON_NAME="ps_core_preferred"/> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" MPD_INDEX="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x83600000"> + <DESCRIPTION>Base Address</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" MPD_INDEX="1" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x8360ffff"> + <DESCRIPTION>High Address</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="2" NAME="C_MEM_WIDTH" TYPE="INTEGER" VALUE="16"> + <DESCRIPTION>Width of System ACE Data Bus </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="3" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32"> + <DESCRIPTION>PLB Address Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="128"> + <DESCRIPTION>PLB Data Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="5" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="6" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Number of PLB Masters</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="8" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"> + <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="9" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="10" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex5"> + <DESCRIPTION>Device Family</DESCRIPTION> + </PARAMETER> + <MEMORYMAP> + <MEMRANGE BASEDECIMAL="2204106752" BASENAME="C_BASEADDR" BASEVALUE="0x83600000" HIGHDECIMAL="2204172287" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8360ffff" MEMTYPE="REGISTER" MINSIZE="0x80" SIZE="65536" SIZEABRV="64K"> + <SLVINTERFACES> + <BUSINTERFACE NAME="SPLB"/> + </SLVINTERFACES> + </MEMRANGE> + </MEMORYMAP> + <PORT DIR="O" ENDIAN="LITTLE" IS_INMHS="TRUE" LSB="0" MHS_INDEX="0" MPD_INDEX="42" MSB="6" NAME="SysACE_MPA" SIGNAME="fpga_0_SysACE_CompactFlash_SysACE_MPA_pin" VECFORMULA="[6:0]"> + <DESCRIPTION>Address Input</DESCRIPTION> + </PORT> + <PORT DIR="I" IS_INMHS="TRUE" MHS_INDEX="1" MPD_INDEX="43" NAME="SysACE_CLK" SIGNAME="fpga_0_SysACE_CompactFlash_SysACE_CLK_pin"> + <DESCRIPTION>Clock Input</DESCRIPTION> + </PORT> + <PORT DIR="I" IS_INMHS="TRUE" MHS_INDEX="2" MPD_INDEX="44" NAME="SysACE_MPIRQ" SIGNAME="fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin"> + <DESCRIPTION>Active high Interrupt Output</DESCRIPTION> + </PORT> + <PORT DIR="O" IS_INMHS="TRUE" MHS_INDEX="3" MPD_INDEX="48" NAME="SysACE_CEN" SIGNAME="fpga_0_SysACE_CompactFlash_SysACE_CEN_pin"> + <DESCRIPTION>Active LOW Chip Enable</DESCRIPTION> + </PORT> + <PORT DIR="O" IS_INMHS="TRUE" MHS_INDEX="4" MPD_INDEX="49" NAME="SysACE_OEN" SIGNAME="fpga_0_SysACE_CompactFlash_SysACE_OEN_pin"> + <DESCRIPTION>Active LOW Output Enable</DESCRIPTION> + </PORT> + <PORT DIR="O" IS_INMHS="TRUE" MHS_INDEX="5" MPD_INDEX="50" NAME="SysACE_WEN" SIGNAME="fpga_0_SysACE_CompactFlash_SysACE_WEN_pin"> + <DESCRIPTION>Active LOW Write Enable</DESCRIPTION> + </PORT> + <PORT DIR="IO" ENDIAN="LITTLE" IS_INMHS="TRUE" LSB="0" MHS_INDEX="6" MPD_INDEX="52" MSB="15" NAME="SysACE_MPD" SIGNAME="fpga_0_SysACE_CompactFlash_SysACE_MPD_pin" VECFORMULA="[(C_MEM_WIDTH-1):0]"> + <DESCRIPTION>Data Input/Output</DESCRIPTION> + </PORT> + <PORT BUS="SPLB" CLKFREQUENCY="125000000" DEF_SIGNAME="clk_125_0000MHzPLL0_ADJUST" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_125_0000MHzPLL0_ADJUST"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="plb_v46_0_SPLB_Rst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_ABus" DIR="I" MPD_INDEX="2" NAME="PLB_ABus" SIGNAME="plb_v46_0_PLB_ABus" VECFORMULA="[0:31]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_UABus" DIR="I" MPD_INDEX="3" NAME="PLB_UABus" SIGNAME="plb_v46_0_PLB_UABus" VECFORMULA="[0:31]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_PAValid" DIR="I" MPD_INDEX="4" NAME="PLB_PAValid" SIGNAME="plb_v46_0_PLB_PAValid"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_SAValid" DIR="I" MPD_INDEX="5" NAME="PLB_SAValid" SIGNAME="plb_v46_0_PLB_SAValid"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPrim" DIR="I" MPD_INDEX="6" NAME="PLB_rdPrim" SIGNAME="plb_v46_0_PLB_rdPrim"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPrim" DIR="I" MPD_INDEX="7" NAME="PLB_wrPrim" SIGNAME="plb_v46_0_PLB_wrPrim"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_masterID" DIR="I" MPD_INDEX="8" NAME="PLB_masterID" SIGNAME="plb_v46_0_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_abort" DIR="I" MPD_INDEX="9" NAME="PLB_abort" SIGNAME="plb_v46_0_PLB_abort"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_busLock" DIR="I" MPD_INDEX="10" NAME="PLB_busLock" SIGNAME="plb_v46_0_PLB_busLock"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_RNW" DIR="I" MPD_INDEX="11" NAME="PLB_RNW" SIGNAME="plb_v46_0_PLB_RNW"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_BE" DIR="I" MPD_INDEX="12" NAME="PLB_BE" SIGNAME="plb_v46_0_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_MSize" DIR="I" MPD_INDEX="13" NAME="PLB_MSize" SIGNAME="plb_v46_0_PLB_MSize" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_size" DIR="I" MPD_INDEX="14" NAME="PLB_size" SIGNAME="plb_v46_0_PLB_size" VECFORMULA="[0:3]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_type" DIR="I" MPD_INDEX="15" NAME="PLB_type" SIGNAME="plb_v46_0_PLB_type" VECFORMULA="[0:2]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_lockErr" DIR="I" MPD_INDEX="16" NAME="PLB_lockErr" SIGNAME="plb_v46_0_PLB_lockErr"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrDBus" DIR="I" MPD_INDEX="17" NAME="PLB_wrDBus" SIGNAME="plb_v46_0_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrBurst" DIR="I" MPD_INDEX="18" NAME="PLB_wrBurst" SIGNAME="plb_v46_0_PLB_wrBurst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdBurst" DIR="I" MPD_INDEX="19" NAME="PLB_rdBurst" SIGNAME="plb_v46_0_PLB_rdBurst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPendReq" DIR="I" MPD_INDEX="20" NAME="PLB_wrPendReq" SIGNAME="plb_v46_0_PLB_wrPendReq"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPendReq" DIR="I" MPD_INDEX="21" NAME="PLB_rdPendReq" SIGNAME="plb_v46_0_PLB_rdPendReq"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPendPri" DIR="I" MPD_INDEX="22" NAME="PLB_wrPendPri" SIGNAME="plb_v46_0_PLB_wrPendPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPendPri" DIR="I" MPD_INDEX="23" NAME="PLB_rdPendPri" SIGNAME="plb_v46_0_PLB_rdPendPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_reqPri" DIR="I" MPD_INDEX="24" NAME="PLB_reqPri" SIGNAME="plb_v46_0_PLB_reqPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_TAttribute" DIR="I" MPD_INDEX="25" NAME="PLB_TAttribute" SIGNAME="plb_v46_0_PLB_TAttribute" VECFORMULA="[0:15]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_addrAck" DIR="O" MPD_INDEX="26" NAME="Sl_addrAck" SIGNAME="plb_v46_0_Sl_addrAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_SSize" DIR="O" MPD_INDEX="27" NAME="Sl_SSize" SIGNAME="plb_v46_0_Sl_SSize" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wait" DIR="O" MPD_INDEX="28" NAME="Sl_wait" SIGNAME="plb_v46_0_Sl_wait"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rearbitrate" DIR="O" MPD_INDEX="29" NAME="Sl_rearbitrate" SIGNAME="plb_v46_0_Sl_rearbitrate"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrDAck" DIR="O" MPD_INDEX="30" NAME="Sl_wrDAck" SIGNAME="plb_v46_0_Sl_wrDAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrComp" DIR="O" MPD_INDEX="31" NAME="Sl_wrComp" SIGNAME="plb_v46_0_Sl_wrComp"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrBTerm" DIR="O" MPD_INDEX="32" NAME="Sl_wrBTerm" SIGNAME="plb_v46_0_Sl_wrBTerm"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdDBus" DIR="O" MPD_INDEX="33" NAME="Sl_rdDBus" SIGNAME="plb_v46_0_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdWdAddr" DIR="O" MPD_INDEX="34" NAME="Sl_rdWdAddr" SIGNAME="plb_v46_0_Sl_rdWdAddr" VECFORMULA="[0:3]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdDAck" DIR="O" MPD_INDEX="35" NAME="Sl_rdDAck" SIGNAME="plb_v46_0_Sl_rdDAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdComp" DIR="O" MPD_INDEX="36" NAME="Sl_rdComp" SIGNAME="plb_v46_0_Sl_rdComp"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdBTerm" DIR="O" MPD_INDEX="37" NAME="Sl_rdBTerm" SIGNAME="plb_v46_0_Sl_rdBTerm"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MBusy" DIR="O" MPD_INDEX="38" NAME="Sl_MBusy" SIGNAME="plb_v46_0_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MWrErr" DIR="O" MPD_INDEX="39" NAME="Sl_MWrErr" SIGNAME="plb_v46_0_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MRdErr" DIR="O" MPD_INDEX="40" NAME="Sl_MRdErr" SIGNAME="plb_v46_0_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MIRQ" DIR="O" MPD_INDEX="41" NAME="Sl_MIRQ" SIGNAME="plb_v46_0_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT DIR="I" MPD_INDEX="45" NAME="SysACE_MPD_I" SIGNAME="__NOC__" VECFORMULA="[(C_MEM_WIDTH-1):0]"/> + <PORT DIR="O" MPD_INDEX="46" NAME="SysACE_MPD_O" SIGNAME="__NOC__" VECFORMULA="[(C_MEM_WIDTH-1):0]"/> + <PORT DIR="O" MPD_INDEX="47" NAME="SysACE_MPD_T" SIGNAME="__NOC__" VECFORMULA="[(C_MEM_WIDTH-1):0]"/> + <PORT DIR="O" MPD_INDEX="51" NAME="SysACE_IRQ" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/> + <BUSINTERFACE BUSNAME="plb_v46_0" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INMHS="TRUE" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE"/> + </MODULE> + <MODULE HWVERSION="3.01.a" INSTANCE="clock_generator_0" IPTYPE="PERIPHERAL" MHS_INDEX="16" MODCLASS="IP" MODTYPE="clock_generator"> + <DESCRIPTION TYPE="SHORT">Clock Generator</DESCRIPTION> + <DESCRIPTION TYPE="LONG">Clock generator for processor system.</DESCRIPTION> + <DOCUMENTATION> + <DOCUMENT SOURCE="c:/devtools/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/clock_generator_v3_01_a/doc/clock_generator.pdf" TYPE="IP"/> + </DOCUMENTATION> + <LICENSEINFO ICON_NAME="ps_core_preferred"/> + <PARAMETER MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex5"/> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_SPEEDGRADE" TYPE="STRING" VALUE="-1"/> + <PARAMETER MPD_INDEX="2" NAME="C_EXT_RESET_HIGH" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="3" NAME="C_CLK_GEN" TYPE="STRING" VALUE="update"/> + <PARAMETER MPD_INDEX="4" NAME="C_CLKOUT0_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="5" NAME="C_CLKOUT0_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="6" NAME="C_CLKOUT1_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="7" NAME="C_CLKOUT1_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="8" NAME="C_CLKOUT2_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="9" NAME="C_CLKOUT2_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="10" NAME="C_CLKOUT3_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="11" NAME="C_CLKOUT3_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="12" NAME="C_CLKOUT4_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="13" NAME="C_CLKOUT4_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="14" NAME="C_CLKOUT5_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="15" NAME="C_CLKOUT5_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="16" NAME="C_CLKOUT6_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="17" NAME="C_CLKOUT6_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="18" NAME="C_CLKOUT7_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="19" NAME="C_CLKOUT7_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="20" NAME="C_CLKOUT8_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="21" NAME="C_CLKOUT8_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="22" NAME="C_CLKOUT9_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="23" NAME="C_CLKOUT9_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="24" NAME="C_CLKOUT10_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="25" NAME="C_CLKOUT10_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="26" NAME="C_CLKOUT11_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="27" NAME="C_CLKOUT11_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="28" NAME="C_CLKOUT12_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="29" NAME="C_CLKOUT12_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="30" NAME="C_CLKOUT13_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="31" NAME="C_CLKOUT13_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="32" NAME="C_CLKOUT14_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="33" NAME="C_CLKOUT14_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="34" NAME="C_CLKOUT15_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="35" NAME="C_CLKOUT15_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="36" NAME="C_CLKFBOUT_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="37" NAME="C_CLKFBOUT_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="38" NAME="C_PSDONE_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="39" NAME="C_PLL0_DIVCLK_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="40" NAME="C_PLL0_CLKFBOUT_MULT" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="41" NAME="C_PLL0_CLKFBOUT_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="42" NAME="C_PLL0_CLKIN1_PERIOD" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="43" NAME="C_PLL0_CLKOUT0_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="44" NAME="C_PLL0_CLKOUT0_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="45" NAME="C_PLL0_CLKOUT0_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="46" NAME="C_PLL0_CLKOUT1_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="47" NAME="C_PLL0_CLKOUT1_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="48" NAME="C_PLL0_CLKOUT1_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="49" NAME="C_PLL0_CLKOUT2_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="50" NAME="C_PLL0_CLKOUT2_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="51" NAME="C_PLL0_CLKOUT2_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="52" NAME="C_PLL0_CLKOUT3_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="53" NAME="C_PLL0_CLKOUT3_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="54" NAME="C_PLL0_CLKOUT3_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="55" NAME="C_PLL0_CLKOUT4_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="56" NAME="C_PLL0_CLKOUT4_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="57" NAME="C_PLL0_CLKOUT4_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="58" NAME="C_PLL0_CLKOUT5_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="59" NAME="C_PLL0_CLKOUT5_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="60" NAME="C_PLL0_CLKOUT5_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="61" NAME="C_PLL0_BANDWIDTH" TYPE="STRING" VALUE="OPTIMIZED"/> + <PARAMETER MPD_INDEX="62" NAME="C_PLL0_COMPENSATION" TYPE="STRING" VALUE="SYSTEM_SYNCHRONOUS"/> + <PARAMETER MPD_INDEX="63" NAME="C_PLL0_REF_JITTER" TYPE="REAL" VALUE="0.100000"/> + <PARAMETER MPD_INDEX="64" NAME="C_PLL0_RESET_ON_LOSS_OF_LOCK" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="65" NAME="C_PLL0_RST_DEASSERT_CLK" TYPE="STRING" VALUE="CLKIN1"/> + <PARAMETER MPD_INDEX="66" NAME="C_PLL0_EXT_RESET_HIGH" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="67" NAME="C_PLL0_FAMILY" TYPE="STRING" VALUE="virtex5"/> + <PARAMETER MPD_INDEX="68" NAME="C_PLL0_CLKOUT0_DESKEW_ADJUST" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="69" NAME="C_PLL0_CLKOUT1_DESKEW_ADJUST" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="70" NAME="C_PLL0_CLKOUT2_DESKEW_ADJUST" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="71" NAME="C_PLL0_CLKOUT3_DESKEW_ADJUST" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="72" NAME="C_PLL0_CLKOUT4_DESKEW_ADJUST" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="73" NAME="C_PLL0_CLKOUT5_DESKEW_ADJUST" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="74" NAME="C_PLL0_CLKFBOUT_DESKEW_ADJUST" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="75" NAME="C_PLL0_CLKIN1_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="76" NAME="C_PLL0_CLKFBOUT_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="77" NAME="C_PLL0_CLKOUT0_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="78" NAME="C_PLL0_CLKOUT1_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="79" NAME="C_PLL0_CLKOUT2_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="80" NAME="C_PLL0_CLKOUT3_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="81" NAME="C_PLL0_CLKOUT4_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="82" NAME="C_PLL0_CLKOUT5_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="83" NAME="C_PLL0_CLKIN1_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="84" NAME="C_PLL0_CLKIN1_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="85" NAME="C_PLL0_CLKFBIN_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="86" NAME="C_PLL0_CLKFBIN_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="87" NAME="C_PLL0_RST_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="88" NAME="C_PLL1_DIVCLK_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="89" NAME="C_PLL1_CLKFBOUT_MULT" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="90" NAME="C_PLL1_CLKFBOUT_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="91" NAME="C_PLL1_CLKIN1_PERIOD" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="92" NAME="C_PLL1_CLKOUT0_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="93" NAME="C_PLL1_CLKOUT0_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="94" NAME="C_PLL1_CLKOUT0_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="95" NAME="C_PLL1_CLKOUT1_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="96" NAME="C_PLL1_CLKOUT1_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="97" NAME="C_PLL1_CLKOUT1_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="98" NAME="C_PLL1_CLKOUT2_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="99" NAME="C_PLL1_CLKOUT2_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="100" NAME="C_PLL1_CLKOUT2_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="101" NAME="C_PLL1_CLKOUT3_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="102" NAME="C_PLL1_CLKOUT3_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="103" NAME="C_PLL1_CLKOUT3_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="104" NAME="C_PLL1_CLKOUT4_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="105" NAME="C_PLL1_CLKOUT4_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="106" NAME="C_PLL1_CLKOUT4_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="107" NAME="C_PLL1_CLKOUT5_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="108" NAME="C_PLL1_CLKOUT5_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="109" NAME="C_PLL1_CLKOUT5_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="110" NAME="C_PLL1_BANDWIDTH" TYPE="STRING" VALUE="OPTIMIZED"/> + <PARAMETER MPD_INDEX="111" NAME="C_PLL1_COMPENSATION" TYPE="STRING" VALUE="SYSTEM_SYNCHRONOUS"/> + <PARAMETER MPD_INDEX="112" NAME="C_PLL1_REF_JITTER" TYPE="REAL" VALUE="0.100000"/> + <PARAMETER MPD_INDEX="113" NAME="C_PLL1_RESET_ON_LOSS_OF_LOCK" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="114" NAME="C_PLL1_RST_DEASSERT_CLK" TYPE="STRING" VALUE="CLKIN1"/> + <PARAMETER MPD_INDEX="115" NAME="C_PLL1_EXT_RESET_HIGH" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="116" NAME="C_PLL1_FAMILY" TYPE="STRING" VALUE="virtex5"/> + <PARAMETER MPD_INDEX="117" NAME="C_PLL1_CLKOUT0_DESKEW_ADJUST" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="118" NAME="C_PLL1_CLKOUT1_DESKEW_ADJUST" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="119" NAME="C_PLL1_CLKOUT2_DESKEW_ADJUST" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="120" NAME="C_PLL1_CLKOUT3_DESKEW_ADJUST" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="121" NAME="C_PLL1_CLKOUT4_DESKEW_ADJUST" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="122" NAME="C_PLL1_CLKOUT5_DESKEW_ADJUST" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="123" NAME="C_PLL1_CLKFBOUT_DESKEW_ADJUST" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="124" NAME="C_PLL1_CLKIN1_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="125" NAME="C_PLL1_CLKFBOUT_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="126" NAME="C_PLL1_CLKOUT0_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="127" NAME="C_PLL1_CLKOUT1_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="128" NAME="C_PLL1_CLKOUT2_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="129" NAME="C_PLL1_CLKOUT3_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="130" NAME="C_PLL1_CLKOUT4_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="131" NAME="C_PLL1_CLKOUT5_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="132" NAME="C_PLL1_CLKIN1_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="133" NAME="C_PLL1_CLKIN1_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="134" NAME="C_PLL1_CLKFBIN_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="135" NAME="C_PLL1_CLKFBIN_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="136" NAME="C_PLL1_RST_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="137" NAME="C_DCM0_DFS_FREQUENCY_MODE" TYPE="STRING" VALUE="LOW"/> + <PARAMETER MPD_INDEX="138" NAME="C_DCM0_DLL_FREQUENCY_MODE" TYPE="STRING" VALUE="LOW"/> + <PARAMETER MPD_INDEX="139" NAME="C_DCM0_DUTY_CYCLE_CORRECTION" TYPE="BOOLEAN" VALUE="true"/> + <PARAMETER MPD_INDEX="140" NAME="C_DCM0_CLKIN_DIVIDE_BY_2" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="141" NAME="C_DCM0_CLK_FEEDBACK" TYPE="STRING" VALUE="1X"/> + <PARAMETER MPD_INDEX="142" NAME="C_DCM0_CLKOUT_PHASE_SHIFT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="143" NAME="C_DCM0_DSS_MODE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="144" NAME="C_DCM0_STARTUP_WAIT" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="145" NAME="C_DCM0_PHASE_SHIFT" TYPE="INTEGER" VALUE="0"/> + <PARAMETER MPD_INDEX="146" NAME="C_DCM0_CLKFX_MULTIPLY" TYPE="INTEGER" VALUE="4"/> + <PARAMETER MPD_INDEX="147" NAME="C_DCM0_CLKFX_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="148" NAME="C_DCM0_CLKDV_DIVIDE" TYPE="REAL" VALUE="2.000000"/> + <PARAMETER MPD_INDEX="149" NAME="C_DCM0_CLKIN_PERIOD" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="150" NAME="C_DCM0_DESKEW_ADJUST" TYPE="STRING" VALUE="SYSTEM_SYNCHRONOUS"/> + <PARAMETER MPD_INDEX="151" NAME="C_DCM0_CLKIN_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="152" NAME="C_DCM0_CLKFB_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="153" NAME="C_DCM0_CLK0_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="154" NAME="C_DCM0_CLK90_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="155" NAME="C_DCM0_CLK180_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="156" NAME="C_DCM0_CLK270_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="157" NAME="C_DCM0_CLKDV_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="158" NAME="C_DCM0_CLKDV180_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="159" NAME="C_DCM0_CLK2X_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="160" NAME="C_DCM0_CLK2X180_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="161" NAME="C_DCM0_CLKFX_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="162" NAME="C_DCM0_CLKFX180_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="163" NAME="C_DCM0_EXT_RESET_HIGH" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="164" NAME="C_DCM0_FAMILY" TYPE="STRING" VALUE="virtex5"/> + <PARAMETER MPD_INDEX="165" NAME="C_DCM0_CLKIN_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="166" NAME="C_DCM0_CLKIN_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="167" NAME="C_DCM0_CLKFB_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="168" NAME="C_DCM0_CLKFB_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="169" NAME="C_DCM0_RST_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="170" NAME="C_DCM1_DFS_FREQUENCY_MODE" TYPE="STRING" VALUE="LOW"/> + <PARAMETER MPD_INDEX="171" NAME="C_DCM1_DLL_FREQUENCY_MODE" TYPE="STRING" VALUE="LOW"/> + <PARAMETER MPD_INDEX="172" NAME="C_DCM1_DUTY_CYCLE_CORRECTION" TYPE="BOOLEAN" VALUE="true"/> + <PARAMETER MPD_INDEX="173" NAME="C_DCM1_CLKIN_DIVIDE_BY_2" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="174" NAME="C_DCM1_CLK_FEEDBACK" TYPE="STRING" VALUE="1X"/> + <PARAMETER MPD_INDEX="175" NAME="C_DCM1_CLKOUT_PHASE_SHIFT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="176" NAME="C_DCM1_DSS_MODE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="177" NAME="C_DCM1_STARTUP_WAIT" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="178" NAME="C_DCM1_PHASE_SHIFT" TYPE="INTEGER" VALUE="0"/> + <PARAMETER MPD_INDEX="179" NAME="C_DCM1_CLKFX_MULTIPLY" TYPE="INTEGER" VALUE="4"/> + <PARAMETER MPD_INDEX="180" NAME="C_DCM1_CLKFX_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="181" NAME="C_DCM1_CLKDV_DIVIDE" TYPE="REAL" VALUE="2.000000"/> + <PARAMETER MPD_INDEX="182" NAME="C_DCM1_CLKIN_PERIOD" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="183" NAME="C_DCM1_DESKEW_ADJUST" TYPE="STRING" VALUE="SYSTEM_SYNCHRONOUS"/> + <PARAMETER MPD_INDEX="184" NAME="C_DCM1_CLKIN_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="185" NAME="C_DCM1_CLKFB_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="186" NAME="C_DCM1_CLK0_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="187" NAME="C_DCM1_CLK90_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="188" NAME="C_DCM1_CLK180_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="189" NAME="C_DCM1_CLK270_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="190" NAME="C_DCM1_CLKDV_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="191" NAME="C_DCM1_CLKDV180_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="192" NAME="C_DCM1_CLK2X_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="193" NAME="C_DCM1_CLK2X180_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="194" NAME="C_DCM1_CLKFX_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="195" NAME="C_DCM1_CLKFX180_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="196" NAME="C_DCM1_EXT_RESET_HIGH" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="197" NAME="C_DCM1_FAMILY" TYPE="STRING" VALUE="virtex5"/> + <PARAMETER MPD_INDEX="198" NAME="C_DCM1_CLKIN_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="199" NAME="C_DCM1_CLKIN_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="200" NAME="C_DCM1_CLKFB_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="201" NAME="C_DCM1_CLKFB_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="202" NAME="C_DCM1_RST_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="203" NAME="C_DCM2_DFS_FREQUENCY_MODE" TYPE="STRING" VALUE="LOW"/> + <PARAMETER MPD_INDEX="204" NAME="C_DCM2_DLL_FREQUENCY_MODE" TYPE="STRING" VALUE="LOW"/> + <PARAMETER MPD_INDEX="205" NAME="C_DCM2_DUTY_CYCLE_CORRECTION" TYPE="BOOLEAN" VALUE="true"/> + <PARAMETER MPD_INDEX="206" NAME="C_DCM2_CLKIN_DIVIDE_BY_2" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="207" NAME="C_DCM2_CLK_FEEDBACK" TYPE="STRING" VALUE="1X"/> + <PARAMETER MPD_INDEX="208" NAME="C_DCM2_CLKOUT_PHASE_SHIFT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="209" NAME="C_DCM2_DSS_MODE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="210" NAME="C_DCM2_STARTUP_WAIT" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="211" NAME="C_DCM2_PHASE_SHIFT" TYPE="INTEGER" VALUE="0"/> + <PARAMETER MPD_INDEX="212" NAME="C_DCM2_CLKFX_MULTIPLY" TYPE="INTEGER" VALUE="4"/> + <PARAMETER MPD_INDEX="213" NAME="C_DCM2_CLKFX_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="214" NAME="C_DCM2_CLKDV_DIVIDE" TYPE="REAL" VALUE="2.000000"/> + <PARAMETER MPD_INDEX="215" NAME="C_DCM2_CLKIN_PERIOD" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="216" NAME="C_DCM2_DESKEW_ADJUST" TYPE="STRING" VALUE="SYSTEM_SYNCHRONOUS"/> + <PARAMETER MPD_INDEX="217" NAME="C_DCM2_CLKIN_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="218" NAME="C_DCM2_CLKFB_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="219" NAME="C_DCM2_CLK0_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="220" NAME="C_DCM2_CLK90_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="221" NAME="C_DCM2_CLK180_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="222" NAME="C_DCM2_CLK270_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="223" NAME="C_DCM2_CLKDV_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="224" NAME="C_DCM2_CLKDV180_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="225" NAME="C_DCM2_CLK2X_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="226" NAME="C_DCM2_CLK2X180_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="227" NAME="C_DCM2_CLKFX_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="228" NAME="C_DCM2_CLKFX180_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="229" NAME="C_DCM2_EXT_RESET_HIGH" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="230" NAME="C_DCM2_FAMILY" TYPE="STRING" VALUE="virtex5"/> + <PARAMETER MPD_INDEX="231" NAME="C_DCM2_CLKIN_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="232" NAME="C_DCM2_CLKIN_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="233" NAME="C_DCM2_CLKFB_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="234" NAME="C_DCM2_CLKFB_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="235" NAME="C_DCM2_RST_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="236" NAME="C_DCM3_DFS_FREQUENCY_MODE" TYPE="STRING" VALUE="LOW"/> + <PARAMETER MPD_INDEX="237" NAME="C_DCM3_DLL_FREQUENCY_MODE" TYPE="STRING" VALUE="LOW"/> + <PARAMETER MPD_INDEX="238" NAME="C_DCM3_DUTY_CYCLE_CORRECTION" TYPE="BOOLEAN" VALUE="true"/> + <PARAMETER MPD_INDEX="239" NAME="C_DCM3_CLKIN_DIVIDE_BY_2" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="240" NAME="C_DCM3_CLK_FEEDBACK" TYPE="STRING" VALUE="1X"/> + <PARAMETER MPD_INDEX="241" NAME="C_DCM3_CLKOUT_PHASE_SHIFT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="242" NAME="C_DCM3_DSS_MODE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="243" NAME="C_DCM3_STARTUP_WAIT" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="244" NAME="C_DCM3_PHASE_SHIFT" TYPE="INTEGER" VALUE="0"/> + <PARAMETER MPD_INDEX="245" NAME="C_DCM3_CLKFX_MULTIPLY" TYPE="INTEGER" VALUE="4"/> + <PARAMETER MPD_INDEX="246" NAME="C_DCM3_CLKFX_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="247" NAME="C_DCM3_CLKDV_DIVIDE" TYPE="REAL" VALUE="2.000000"/> + <PARAMETER MPD_INDEX="248" NAME="C_DCM3_CLKIN_PERIOD" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="249" NAME="C_DCM3_DESKEW_ADJUST" TYPE="STRING" VALUE="SYSTEM_SYNCHRONOUS"/> + <PARAMETER MPD_INDEX="250" NAME="C_DCM3_CLKIN_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="251" NAME="C_DCM3_CLKFB_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="252" NAME="C_DCM3_CLK0_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="253" NAME="C_DCM3_CLK90_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="254" NAME="C_DCM3_CLK180_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="255" NAME="C_DCM3_CLK270_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="256" NAME="C_DCM3_CLKDV_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="257" NAME="C_DCM3_CLKDV180_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="258" NAME="C_DCM3_CLK2X_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="259" NAME="C_DCM3_CLK2X180_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="260" NAME="C_DCM3_CLKFX_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="261" NAME="C_DCM3_CLKFX180_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="262" NAME="C_DCM3_EXT_RESET_HIGH" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="263" NAME="C_DCM3_FAMILY" TYPE="STRING" VALUE="virtex5"/> + <PARAMETER MPD_INDEX="264" NAME="C_DCM3_CLKIN_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="265" NAME="C_DCM3_CLKIN_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="266" NAME="C_DCM3_CLKFB_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="267" NAME="C_DCM3_CLKFB_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="268" NAME="C_DCM3_RST_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="269" NAME="C_MMCM0_BANDWIDTH" TYPE="STRING" VALUE="OPTIMIZED"/> + <PARAMETER MPD_INDEX="270" NAME="C_MMCM0_CLKFBOUT_MULT_F" TYPE="REAL" VALUE="1.000000"/> + <PARAMETER MPD_INDEX="271" NAME="C_MMCM0_CLKFBOUT_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="272" NAME="C_MMCM0_CLKFBOUT_USE_FINE_PS" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="273" NAME="C_MMCM0_CLKIN1_PERIOD" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="274" NAME="C_MMCM0_CLKOUT0_DIVIDE_F" TYPE="REAL" VALUE="1.000000"/> + <PARAMETER MPD_INDEX="275" NAME="C_MMCM0_CLKOUT0_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="276" NAME="C_MMCM0_CLKOUT0_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="277" NAME="C_MMCM0_CLKOUT1_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="278" NAME="C_MMCM0_CLKOUT1_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="279" NAME="C_MMCM0_CLKOUT1_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="280" NAME="C_MMCM0_CLKOUT2_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="281" NAME="C_MMCM0_CLKOUT2_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="282" NAME="C_MMCM0_CLKOUT2_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="283" NAME="C_MMCM0_CLKOUT3_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="284" NAME="C_MMCM0_CLKOUT3_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="285" NAME="C_MMCM0_CLKOUT3_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="286" NAME="C_MMCM0_CLKOUT4_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="287" NAME="C_MMCM0_CLKOUT4_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="288" NAME="C_MMCM0_CLKOUT4_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="289" NAME="C_MMCM0_CLKOUT4_CASCADE" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="290" NAME="C_MMCM0_CLKOUT5_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="291" NAME="C_MMCM0_CLKOUT5_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="292" NAME="C_MMCM0_CLKOUT5_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="293" NAME="C_MMCM0_CLKOUT6_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="294" NAME="C_MMCM0_CLKOUT6_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="295" NAME="C_MMCM0_CLKOUT6_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="296" NAME="C_MMCM0_CLKOUT0_USE_FINE_PS" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="297" NAME="C_MMCM0_CLKOUT1_USE_FINE_PS" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="298" NAME="C_MMCM0_CLKOUT2_USE_FINE_PS" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="299" NAME="C_MMCM0_CLKOUT3_USE_FINE_PS" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="300" NAME="C_MMCM0_CLKOUT4_USE_FINE_PS" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="301" NAME="C_MMCM0_CLKOUT5_USE_FINE_PS" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="302" NAME="C_MMCM0_CLKOUT6_USE_FINE_PS" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="303" NAME="C_MMCM0_COMPENSATION" TYPE="STRING" VALUE="ZHOLD"/> + <PARAMETER MPD_INDEX="304" NAME="C_MMCM0_DIVCLK_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="305" NAME="C_MMCM0_REF_JITTER1" TYPE="REAL" VALUE="0.010000"/> + <PARAMETER MPD_INDEX="306" NAME="C_MMCM0_CLKIN1_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="307" NAME="C_MMCM0_CLKFBOUT_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="308" NAME="C_MMCM0_CLOCK_HOLD" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="309" NAME="C_MMCM0_STARTUP_WAIT" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="310" NAME="C_MMCM0_EXT_RESET_HIGH" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="311" NAME="C_MMCM0_FAMILY" TYPE="STRING" VALUE="virtex6"/> + <PARAMETER MPD_INDEX="312" NAME="C_MMCM0_CLKOUT0_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="313" NAME="C_MMCM0_CLKOUT1_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="314" NAME="C_MMCM0_CLKOUT2_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="315" NAME="C_MMCM0_CLKOUT3_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="316" NAME="C_MMCM0_CLKOUT4_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="317" NAME="C_MMCM0_CLKOUT5_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="318" NAME="C_MMCM0_CLKOUT6_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="319" NAME="C_MMCM0_CLKIN1_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="320" NAME="C_MMCM0_CLKIN1_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="321" NAME="C_MMCM0_CLKFBIN_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="322" NAME="C_MMCM0_CLKFBIN_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="323" NAME="C_MMCM0_RST_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="324" NAME="C_MMCM1_BANDWIDTH" TYPE="STRING" VALUE="OPTIMIZED"/> + <PARAMETER MPD_INDEX="325" NAME="C_MMCM1_CLKFBOUT_MULT_F" TYPE="REAL" VALUE="1.000000"/> + <PARAMETER MPD_INDEX="326" NAME="C_MMCM1_CLKFBOUT_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="327" NAME="C_MMCM1_CLKFBOUT_USE_FINE_PS" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="328" NAME="C_MMCM1_CLKIN1_PERIOD" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="329" NAME="C_MMCM1_CLKOUT0_DIVIDE_F" TYPE="REAL" VALUE="1.000000"/> + <PARAMETER MPD_INDEX="330" NAME="C_MMCM1_CLKOUT0_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="331" NAME="C_MMCM1_CLKOUT0_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="332" NAME="C_MMCM1_CLKOUT1_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="333" NAME="C_MMCM1_CLKOUT1_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="334" NAME="C_MMCM1_CLKOUT1_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="335" NAME="C_MMCM1_CLKOUT2_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="336" NAME="C_MMCM1_CLKOUT2_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="337" NAME="C_MMCM1_CLKOUT2_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="338" NAME="C_MMCM1_CLKOUT3_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="339" NAME="C_MMCM1_CLKOUT3_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="340" NAME="C_MMCM1_CLKOUT3_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="341" NAME="C_MMCM1_CLKOUT4_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="342" NAME="C_MMCM1_CLKOUT4_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="343" NAME="C_MMCM1_CLKOUT4_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="344" NAME="C_MMCM1_CLKOUT4_CASCADE" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="345" NAME="C_MMCM1_CLKOUT5_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="346" NAME="C_MMCM1_CLKOUT5_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="347" NAME="C_MMCM1_CLKOUT5_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="348" NAME="C_MMCM1_CLKOUT6_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="349" NAME="C_MMCM1_CLKOUT6_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="350" NAME="C_MMCM1_CLKOUT6_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="351" NAME="C_MMCM1_CLKOUT0_USE_FINE_PS" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="352" NAME="C_MMCM1_CLKOUT1_USE_FINE_PS" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="353" NAME="C_MMCM1_CLKOUT2_USE_FINE_PS" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="354" NAME="C_MMCM1_CLKOUT3_USE_FINE_PS" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="355" NAME="C_MMCM1_CLKOUT4_USE_FINE_PS" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="356" NAME="C_MMCM1_CLKOUT5_USE_FINE_PS" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="357" NAME="C_MMCM1_CLKOUT6_USE_FINE_PS" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="358" NAME="C_MMCM1_COMPENSATION" TYPE="STRING" VALUE="ZHOLD"/> + <PARAMETER MPD_INDEX="359" NAME="C_MMCM1_DIVCLK_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="360" NAME="C_MMCM1_REF_JITTER1" TYPE="REAL" VALUE="0.010000"/> + <PARAMETER MPD_INDEX="361" NAME="C_MMCM1_CLKIN1_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="362" NAME="C_MMCM1_CLKFBOUT_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="363" NAME="C_MMCM1_CLOCK_HOLD" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="364" NAME="C_MMCM1_STARTUP_WAIT" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="365" NAME="C_MMCM1_EXT_RESET_HIGH" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="366" NAME="C_MMCM1_FAMILY" TYPE="STRING" VALUE="virtex6"/> + <PARAMETER MPD_INDEX="367" NAME="C_MMCM1_CLKOUT0_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="368" NAME="C_MMCM1_CLKOUT1_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="369" NAME="C_MMCM1_CLKOUT2_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="370" NAME="C_MMCM1_CLKOUT3_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="371" NAME="C_MMCM1_CLKOUT4_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="372" NAME="C_MMCM1_CLKOUT5_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="373" NAME="C_MMCM1_CLKOUT6_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="374" NAME="C_MMCM1_CLKIN1_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="375" NAME="C_MMCM1_CLKIN1_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="376" NAME="C_MMCM1_CLKFBIN_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="377" NAME="C_MMCM1_CLKFBIN_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="378" NAME="C_MMCM1_RST_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="379" NAME="C_MMCM2_BANDWIDTH" TYPE="STRING" VALUE="OPTIMIZED"/> + <PARAMETER MPD_INDEX="380" NAME="C_MMCM2_CLKFBOUT_MULT_F" TYPE="REAL" VALUE="1.000000"/> + <PARAMETER MPD_INDEX="381" NAME="C_MMCM2_CLKFBOUT_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="382" NAME="C_MMCM2_CLKFBOUT_USE_FINE_PS" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="383" NAME="C_MMCM2_CLKIN1_PERIOD" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="384" NAME="C_MMCM2_CLKOUT0_DIVIDE_F" TYPE="REAL" VALUE="1.000000"/> + <PARAMETER MPD_INDEX="385" NAME="C_MMCM2_CLKOUT0_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="386" NAME="C_MMCM2_CLKOUT0_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="387" NAME="C_MMCM2_CLKOUT1_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="388" NAME="C_MMCM2_CLKOUT1_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="389" NAME="C_MMCM2_CLKOUT1_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="390" NAME="C_MMCM2_CLKOUT2_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="391" NAME="C_MMCM2_CLKOUT2_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="392" NAME="C_MMCM2_CLKOUT2_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="393" NAME="C_MMCM2_CLKOUT3_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="394" NAME="C_MMCM2_CLKOUT3_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="395" NAME="C_MMCM2_CLKOUT3_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="396" NAME="C_MMCM2_CLKOUT4_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="397" NAME="C_MMCM2_CLKOUT4_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="398" NAME="C_MMCM2_CLKOUT4_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="399" NAME="C_MMCM2_CLKOUT4_CASCADE" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="400" NAME="C_MMCM2_CLKOUT5_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="401" NAME="C_MMCM2_CLKOUT5_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="402" NAME="C_MMCM2_CLKOUT5_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="403" NAME="C_MMCM2_CLKOUT6_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="404" NAME="C_MMCM2_CLKOUT6_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="405" NAME="C_MMCM2_CLKOUT6_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="406" NAME="C_MMCM2_CLKOUT0_USE_FINE_PS" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="407" NAME="C_MMCM2_CLKOUT1_USE_FINE_PS" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="408" NAME="C_MMCM2_CLKOUT2_USE_FINE_PS" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="409" NAME="C_MMCM2_CLKOUT3_USE_FINE_PS" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="410" NAME="C_MMCM2_CLKOUT4_USE_FINE_PS" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="411" NAME="C_MMCM2_CLKOUT5_USE_FINE_PS" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="412" NAME="C_MMCM2_CLKOUT6_USE_FINE_PS" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="413" NAME="C_MMCM2_COMPENSATION" TYPE="STRING" VALUE="ZHOLD"/> + <PARAMETER MPD_INDEX="414" NAME="C_MMCM2_DIVCLK_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="415" NAME="C_MMCM2_REF_JITTER1" TYPE="REAL" VALUE="0.010000"/> + <PARAMETER MPD_INDEX="416" NAME="C_MMCM2_CLKIN1_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="417" NAME="C_MMCM2_CLKFBOUT_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="418" NAME="C_MMCM2_CLOCK_HOLD" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="419" NAME="C_MMCM2_STARTUP_WAIT" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="420" NAME="C_MMCM2_EXT_RESET_HIGH" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="421" NAME="C_MMCM2_FAMILY" TYPE="STRING" VALUE="virtex6"/> + <PARAMETER MPD_INDEX="422" NAME="C_MMCM2_CLKOUT0_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="423" NAME="C_MMCM2_CLKOUT1_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="424" NAME="C_MMCM2_CLKOUT2_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="425" NAME="C_MMCM2_CLKOUT3_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="426" NAME="C_MMCM2_CLKOUT4_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="427" NAME="C_MMCM2_CLKOUT5_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="428" NAME="C_MMCM2_CLKOUT6_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="429" NAME="C_MMCM2_CLKIN1_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="430" NAME="C_MMCM2_CLKIN1_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="431" NAME="C_MMCM2_CLKFBIN_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="432" NAME="C_MMCM2_CLKFBIN_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="433" NAME="C_MMCM2_RST_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="434" NAME="C_MMCM3_BANDWIDTH" TYPE="STRING" VALUE="OPTIMIZED"/> + <PARAMETER MPD_INDEX="435" NAME="C_MMCM3_CLKFBOUT_MULT_F" TYPE="REAL" VALUE="1.000000"/> + <PARAMETER MPD_INDEX="436" NAME="C_MMCM3_CLKFBOUT_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="437" NAME="C_MMCM3_CLKFBOUT_USE_FINE_PS" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="438" NAME="C_MMCM3_CLKIN1_PERIOD" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="439" NAME="C_MMCM3_CLKOUT0_DIVIDE_F" TYPE="REAL" VALUE="1.000000"/> + <PARAMETER MPD_INDEX="440" NAME="C_MMCM3_CLKOUT0_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="441" NAME="C_MMCM3_CLKOUT0_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="442" NAME="C_MMCM3_CLKOUT1_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="443" NAME="C_MMCM3_CLKOUT1_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="444" NAME="C_MMCM3_CLKOUT1_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="445" NAME="C_MMCM3_CLKOUT2_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="446" NAME="C_MMCM3_CLKOUT2_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="447" NAME="C_MMCM3_CLKOUT2_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="448" NAME="C_MMCM3_CLKOUT3_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="449" NAME="C_MMCM3_CLKOUT3_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="450" NAME="C_MMCM3_CLKOUT3_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="451" NAME="C_MMCM3_CLKOUT4_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="452" NAME="C_MMCM3_CLKOUT4_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="453" NAME="C_MMCM3_CLKOUT4_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="454" NAME="C_MMCM3_CLKOUT4_CASCADE" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="455" NAME="C_MMCM3_CLKOUT5_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="456" NAME="C_MMCM3_CLKOUT5_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="457" NAME="C_MMCM3_CLKOUT5_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="458" NAME="C_MMCM3_CLKOUT6_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="459" NAME="C_MMCM3_CLKOUT6_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/> + <PARAMETER MPD_INDEX="460" NAME="C_MMCM3_CLKOUT6_PHASE" TYPE="REAL" VALUE="0.000000"/> + <PARAMETER MPD_INDEX="461" NAME="C_MMCM3_CLKOUT0_USE_FINE_PS" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="462" NAME="C_MMCM3_CLKOUT1_USE_FINE_PS" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="463" NAME="C_MMCM3_CLKOUT2_USE_FINE_PS" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="464" NAME="C_MMCM3_CLKOUT3_USE_FINE_PS" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="465" NAME="C_MMCM3_CLKOUT4_USE_FINE_PS" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="466" NAME="C_MMCM3_CLKOUT5_USE_FINE_PS" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="467" NAME="C_MMCM3_CLKOUT6_USE_FINE_PS" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="468" NAME="C_MMCM3_COMPENSATION" TYPE="STRING" VALUE="ZHOLD"/> + <PARAMETER MPD_INDEX="469" NAME="C_MMCM3_DIVCLK_DIVIDE" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="470" NAME="C_MMCM3_REF_JITTER1" TYPE="REAL" VALUE="0.010000"/> + <PARAMETER MPD_INDEX="471" NAME="C_MMCM3_CLKIN1_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="472" NAME="C_MMCM3_CLKFBOUT_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="473" NAME="C_MMCM3_CLOCK_HOLD" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="474" NAME="C_MMCM3_STARTUP_WAIT" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="475" NAME="C_MMCM3_EXT_RESET_HIGH" TYPE="INTEGER" VALUE="1"/> + <PARAMETER MPD_INDEX="476" NAME="C_MMCM3_FAMILY" TYPE="STRING" VALUE="virtex6"/> + <PARAMETER MPD_INDEX="477" NAME="C_MMCM3_CLKOUT0_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="478" NAME="C_MMCM3_CLKOUT1_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="479" NAME="C_MMCM3_CLKOUT2_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="480" NAME="C_MMCM3_CLKOUT3_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="481" NAME="C_MMCM3_CLKOUT4_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="482" NAME="C_MMCM3_CLKOUT5_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="483" NAME="C_MMCM3_CLKOUT6_BUF" TYPE="BOOLEAN" VALUE="false"/> + <PARAMETER MPD_INDEX="484" NAME="C_MMCM3_CLKIN1_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="485" NAME="C_MMCM3_CLKIN1_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="486" NAME="C_MMCM3_CLKFBIN_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="487" NAME="C_MMCM3_CLKFBIN_PORT" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="488" NAME="C_MMCM3_RST_MODULE" TYPE="STRING" VALUE="NONE"/> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="489" NAME="C_CLKIN_FREQ" TYPE="INTEGER" VALUE="100000000"/> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="490" NAME="C_CLKFBIN_FREQ" TYPE="INTEGER" VALUE="125000000"/> + <PARAMETER MPD_INDEX="491" NAME="C_CLKFBIN_DESKEW" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="492" NAME="C_PSDONE_GROUP" TYPE="STRING" VALUE="NONE"/> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="493" NAME="C_CLKOUT0_FREQ" TYPE="INTEGER" VALUE="125000000"/> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="494" NAME="C_CLKOUT0_PHASE" TYPE="INTEGER" VALUE="90"/> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="495" NAME="C_CLKOUT0_GROUP" TYPE="STRING" VALUE="PLL0_ADJUST"/> + <PARAMETER MPD_INDEX="496" NAME="C_CLKOUT0_BUF" TYPE="BOOLEAN" VALUE="TRUE"/> + <PARAMETER MPD_INDEX="497" NAME="C_CLKOUT0_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="498" NAME="C_CLKOUT1_FREQ" TYPE="INTEGER" VALUE="125000000"/> + <PARAMETER MPD_INDEX="499" NAME="C_CLKOUT1_PHASE" TYPE="INTEGER" VALUE="0"/> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="500" NAME="C_CLKOUT1_GROUP" TYPE="STRING" VALUE="PLL0"/> + <PARAMETER MPD_INDEX="501" NAME="C_CLKOUT1_BUF" TYPE="BOOLEAN" VALUE="TRUE"/> + <PARAMETER MPD_INDEX="502" NAME="C_CLKOUT1_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="503" NAME="C_CLKOUT2_FREQ" TYPE="INTEGER" VALUE="125000000"/> + <PARAMETER MPD_INDEX="504" NAME="C_CLKOUT2_PHASE" TYPE="INTEGER" VALUE="0"/> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="505" NAME="C_CLKOUT2_GROUP" TYPE="STRING" VALUE="PLL0_ADJUST"/> + <PARAMETER MPD_INDEX="506" NAME="C_CLKOUT2_BUF" TYPE="BOOLEAN" VALUE="TRUE"/> + <PARAMETER MPD_INDEX="507" NAME="C_CLKOUT2_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="508" NAME="C_CLKOUT3_FREQ" TYPE="INTEGER" VALUE="200000000"/> + <PARAMETER MPD_INDEX="509" NAME="C_CLKOUT3_PHASE" TYPE="INTEGER" VALUE="0"/> + <PARAMETER MPD_INDEX="510" NAME="C_CLKOUT3_GROUP" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="511" NAME="C_CLKOUT3_BUF" TYPE="BOOLEAN" VALUE="TRUE"/> + <PARAMETER MPD_INDEX="512" NAME="C_CLKOUT3_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="513" NAME="C_CLKOUT4_FREQ" TYPE="INTEGER" VALUE="62500000"/> + <PARAMETER MPD_INDEX="514" NAME="C_CLKOUT4_PHASE" TYPE="INTEGER" VALUE="0"/> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="515" NAME="C_CLKOUT4_GROUP" TYPE="STRING" VALUE="PLL0_ADJUST"/> + <PARAMETER MPD_INDEX="516" NAME="C_CLKOUT4_BUF" TYPE="BOOLEAN" VALUE="TRUE"/> + <PARAMETER MPD_INDEX="517" NAME="C_CLKOUT4_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/> + <PARAMETER MPD_INDEX="518" NAME="C_CLKOUT5_FREQ" TYPE="INTEGER" VALUE="0"/> + <PARAMETER MPD_INDEX="519" NAME="C_CLKOUT5_PHASE" TYPE="INTEGER" VALUE="0"/> + <PARAMETER MPD_INDEX="520" NAME="C_CLKOUT5_GROUP" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="521" NAME="C_CLKOUT5_BUF" TYPE="BOOLEAN" VALUE="TRUE"/> + <PARAMETER MPD_INDEX="522" NAME="C_CLKOUT5_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/> + <PARAMETER MPD_INDEX="523" NAME="C_CLKOUT6_FREQ" TYPE="INTEGER" VALUE="0"/> + <PARAMETER MPD_INDEX="524" NAME="C_CLKOUT6_PHASE" TYPE="INTEGER" VALUE="0"/> + <PARAMETER MPD_INDEX="525" NAME="C_CLKOUT6_GROUP" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="526" NAME="C_CLKOUT6_BUF" TYPE="BOOLEAN" VALUE="TRUE"/> + <PARAMETER MPD_INDEX="527" NAME="C_CLKOUT6_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/> + <PARAMETER MPD_INDEX="528" NAME="C_CLKOUT7_FREQ" TYPE="INTEGER" VALUE="0"/> + <PARAMETER MPD_INDEX="529" NAME="C_CLKOUT7_PHASE" TYPE="INTEGER" VALUE="0"/> + <PARAMETER MPD_INDEX="530" NAME="C_CLKOUT7_GROUP" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="531" NAME="C_CLKOUT7_BUF" TYPE="BOOLEAN" VALUE="TRUE"/> + <PARAMETER MPD_INDEX="532" NAME="C_CLKOUT7_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/> + <PARAMETER MPD_INDEX="533" NAME="C_CLKOUT8_FREQ" TYPE="INTEGER" VALUE="0"/> + <PARAMETER MPD_INDEX="534" NAME="C_CLKOUT8_PHASE" TYPE="INTEGER" VALUE="0"/> + <PARAMETER MPD_INDEX="535" NAME="C_CLKOUT8_GROUP" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="536" NAME="C_CLKOUT8_BUF" TYPE="BOOLEAN" VALUE="TRUE"/> + <PARAMETER MPD_INDEX="537" NAME="C_CLKOUT8_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/> + <PARAMETER MPD_INDEX="538" NAME="C_CLKOUT9_FREQ" TYPE="INTEGER" VALUE="0"/> + <PARAMETER MPD_INDEX="539" NAME="C_CLKOUT9_PHASE" TYPE="INTEGER" VALUE="0"/> + <PARAMETER MPD_INDEX="540" NAME="C_CLKOUT9_GROUP" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="541" NAME="C_CLKOUT9_BUF" TYPE="BOOLEAN" VALUE="TRUE"/> + <PARAMETER MPD_INDEX="542" NAME="C_CLKOUT9_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/> + <PARAMETER MPD_INDEX="543" NAME="C_CLKOUT10_FREQ" TYPE="INTEGER" VALUE="0"/> + <PARAMETER MPD_INDEX="544" NAME="C_CLKOUT10_PHASE" TYPE="INTEGER" VALUE="0"/> + <PARAMETER MPD_INDEX="545" NAME="C_CLKOUT10_GROUP" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="546" NAME="C_CLKOUT10_BUF" TYPE="BOOLEAN" VALUE="TRUE"/> + <PARAMETER MPD_INDEX="547" NAME="C_CLKOUT10_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/> + <PARAMETER MPD_INDEX="548" NAME="C_CLKOUT11_FREQ" TYPE="INTEGER" VALUE="0"/> + <PARAMETER MPD_INDEX="549" NAME="C_CLKOUT11_PHASE" TYPE="INTEGER" VALUE="0"/> + <PARAMETER MPD_INDEX="550" NAME="C_CLKOUT11_GROUP" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="551" NAME="C_CLKOUT11_BUF" TYPE="BOOLEAN" VALUE="TRUE"/> + <PARAMETER MPD_INDEX="552" NAME="C_CLKOUT11_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/> + <PARAMETER MPD_INDEX="553" NAME="C_CLKOUT12_FREQ" TYPE="INTEGER" VALUE="0"/> + <PARAMETER MPD_INDEX="554" NAME="C_CLKOUT12_PHASE" TYPE="INTEGER" VALUE="0"/> + <PARAMETER MPD_INDEX="555" NAME="C_CLKOUT12_GROUP" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="556" NAME="C_CLKOUT12_BUF" TYPE="BOOLEAN" VALUE="TRUE"/> + <PARAMETER MPD_INDEX="557" NAME="C_CLKOUT12_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/> + <PARAMETER MPD_INDEX="558" NAME="C_CLKOUT13_FREQ" TYPE="INTEGER" VALUE="0"/> + <PARAMETER MPD_INDEX="559" NAME="C_CLKOUT13_PHASE" TYPE="INTEGER" VALUE="0"/> + <PARAMETER MPD_INDEX="560" NAME="C_CLKOUT13_GROUP" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="561" NAME="C_CLKOUT13_BUF" TYPE="BOOLEAN" VALUE="TRUE"/> + <PARAMETER MPD_INDEX="562" NAME="C_CLKOUT13_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/> + <PARAMETER MPD_INDEX="563" NAME="C_CLKOUT14_FREQ" TYPE="INTEGER" VALUE="0"/> + <PARAMETER MPD_INDEX="564" NAME="C_CLKOUT14_PHASE" TYPE="INTEGER" VALUE="0"/> + <PARAMETER MPD_INDEX="565" NAME="C_CLKOUT14_GROUP" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="566" NAME="C_CLKOUT14_BUF" TYPE="BOOLEAN" VALUE="TRUE"/> + <PARAMETER MPD_INDEX="567" NAME="C_CLKOUT14_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/> + <PARAMETER MPD_INDEX="568" NAME="C_CLKOUT15_FREQ" TYPE="INTEGER" VALUE="0"/> + <PARAMETER MPD_INDEX="569" NAME="C_CLKOUT15_PHASE" TYPE="INTEGER" VALUE="0"/> + <PARAMETER MPD_INDEX="570" NAME="C_CLKOUT15_GROUP" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="571" NAME="C_CLKOUT15_BUF" TYPE="BOOLEAN" VALUE="TRUE"/> + <PARAMETER MPD_INDEX="572" NAME="C_CLKOUT15_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="573" NAME="C_CLKFBOUT_FREQ" TYPE="INTEGER" VALUE="125000000"/> + <PARAMETER MPD_INDEX="574" NAME="C_CLKFBOUT_PHASE" TYPE="INTEGER" VALUE="0"/> + <PARAMETER MPD_INDEX="575" NAME="C_CLKFBOUT_GROUP" TYPE="STRING" VALUE="NONE"/> + <PARAMETER MPD_INDEX="576" NAME="C_CLKFBOUT_BUF" TYPE="BOOLEAN" VALUE="TRUE"/> + <PORT CLKFREQUENCY="100000000" DIR="I" IS_INMHS="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="CLKIN" SIGIS="CLK" SIGNAME="dcm_clk_s"/> + <PORT CLKFREQUENCY="125000000" DIR="I" IS_INMHS="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="CLKFBIN" SIGIS="CLK" SIGNAME="SRAM_CLK_FB_s"/> + <PORT CLKFREQUENCY="125000000" DIR="O" IS_INMHS="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="CLKOUT0" SIGIS="CLK" SIGNAME="clk_125_0000MHz90PLL0_ADJUST"/> + <PORT CLKFREQUENCY="125000000" DIR="O" IS_INMHS="TRUE" MHS_INDEX="3" MPD_INDEX="3" NAME="CLKOUT1" SIGIS="CLK" SIGNAME="clk_125_0000MHzPLL0"/> + <PORT CLKFREQUENCY="125000000" DIR="O" IS_INMHS="TRUE" MHS_INDEX="4" MPD_INDEX="4" NAME="CLKOUT2" SIGIS="CLK" SIGNAME="clk_125_0000MHzPLL0_ADJUST"/> + <PORT CLKFREQUENCY="200000000" DIR="O" IS_INMHS="TRUE" MHS_INDEX="5" MPD_INDEX="5" NAME="CLKOUT3" SIGIS="CLK" SIGNAME="clk_200_0000MHz"/> + <PORT CLKFREQUENCY="62500000" DIR="O" IS_INMHS="TRUE" MHS_INDEX="6" MPD_INDEX="6" NAME="CLKOUT4" SIGIS="CLK" SIGNAME="clk_62_5000MHzPLL0_ADJUST"/> + <PORT CLKFREQUENCY="125000000" DIR="O" IS_INMHS="TRUE" MHS_INDEX="7" MPD_INDEX="18" NAME="CLKFBOUT" SIGIS="CLK" SIGNAME="SRAM_CLK_OUT_s"/> + <PORT DIR="I" IS_INMHS="TRUE" MHS_INDEX="8" MPD_INDEX="23" NAME="RST" SIGIS="RST" SIGNAME="net_gnd"/> + <PORT DIR="O" IS_INMHS="TRUE" MHS_INDEX="9" MPD_INDEX="24" NAME="LOCKED" SIGNAME="Dcm_all_locked"/> + <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="7" NAME="CLKOUT5" SIGIS="CLK" SIGNAME="__NOC__"/> + <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="8" NAME="CLKOUT6" SIGIS="CLK" SIGNAME="__NOC__"/> + <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="9" NAME="CLKOUT7" SIGIS="CLK" SIGNAME="__NOC__"/> + <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="10" NAME="CLKOUT8" SIGIS="CLK" SIGNAME="__NOC__"/> + <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="11" NAME="CLKOUT9" SIGIS="CLK" SIGNAME="__NOC__"/> + <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="12" NAME="CLKOUT10" SIGIS="CLK" SIGNAME="__NOC__"/> + <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="13" NAME="CLKOUT11" SIGIS="CLK" SIGNAME="__NOC__"/> + <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="14" NAME="CLKOUT12" SIGIS="CLK" SIGNAME="__NOC__"/> + <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="15" NAME="CLKOUT13" SIGIS="CLK" SIGNAME="__NOC__"/> + <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="16" NAME="CLKOUT14" SIGIS="CLK" SIGNAME="__NOC__"/> + <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="17" NAME="CLKOUT15" SIGIS="CLK" SIGNAME="__NOC__"/> + <PORT DIR="I" MPD_INDEX="19" NAME="PSCLK" SIGIS="CLK" SIGNAME="__NOC__"/> + <PORT DIR="I" MPD_INDEX="20" NAME="PSEN" SIGNAME="__NOC__"/> + <PORT DIR="I" MPD_INDEX="21" NAME="PSINCDEC" SIGNAME="__NOC__"/> + <PORT DIR="O" MPD_INDEX="22" NAME="PSDONE" SIGNAME="__NOC__"/> + </MODULE> + <MODULE HWVERSION="2.01.c" INSTANCE="jtagppc_cntlr_inst" IPTYPE="PERIPHERAL" MHS_INDEX="17" MODCLASS="PERIPHERAL" MODTYPE="jtagppc_cntlr"> + <DESCRIPTION TYPE="SHORT">PowerPC JTAG Controller</DESCRIPTION> + <DESCRIPTION TYPE="LONG">JTAGPPC wrapper allows the PowerPC to connect to the JTAG chain of the FPGA.</DESCRIPTION> + <DOCUMENTATION> + <DOCUMENT SOURCE="c:/devtools/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/jtagppc_cntlr_v2_01_c/doc/jtagppc_cntlr.pdf" TYPE="IP"/> + </DOCUMENTATION> + <LICENSEINFO ICON_NAME="ps_core_preferred"/> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_DEVICE" TYPE="string" VALUE="5vfx70t"/> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_NUM_PPC_USED" TYPE="integer" VALUE="1"/> + <PORT DIR="I" MPD_INDEX="0" NAME="TRSTNEG" SIGNAME="__NOC__"/> + <PORT DIR="I" MPD_INDEX="1" NAME="HALTNEG0" SIGNAME="__NOC__"/> + <PORT DIR="O" MPD_INDEX="2" NAME="DBGC405DEBUGHALT0" SIGNAME="__NOC__"/> + <PORT DIR="I" MPD_INDEX="3" NAME="HALTNEG1" SIGNAME="__NOC__"/> + <PORT DIR="O" MPD_INDEX="4" NAME="DBGC405DEBUGHALT1" SIGNAME="__NOC__"/> + <PORT BUS="JTAGPPC0" DEF_SIGNAME="ppc440_0_jtagppc_bus_C405JTGTDO" DIR="I" MPD_INDEX="5" NAME="C405JTGTDO0" SIGNAME="ppc440_0_jtagppc_bus_C405JTGTDO"/> + <PORT BUS="JTAGPPC0" DEF_SIGNAME="ppc440_0_jtagppc_bus_C405JTGTDOEN" DIR="I" MPD_INDEX="6" NAME="C405JTGTDOEN0" SIGNAME="ppc440_0_jtagppc_bus_C405JTGTDOEN"/> + <PORT BUS="JTAGPPC0" DEF_SIGNAME="ppc440_0_jtagppc_bus_JTGC405TCK" DIR="O" MPD_INDEX="7" NAME="JTGC405TCK0" SIGNAME="ppc440_0_jtagppc_bus_JTGC405TCK"/> + <PORT BUS="JTAGPPC0" DEF_SIGNAME="ppc440_0_jtagppc_bus_JTGC405TDI" DIR="O" MPD_INDEX="8" NAME="JTGC405TDI0" SIGNAME="ppc440_0_jtagppc_bus_JTGC405TDI"/> + <PORT BUS="JTAGPPC0" DEF_SIGNAME="ppc440_0_jtagppc_bus_JTGC405TMS" DIR="O" MPD_INDEX="9" NAME="JTGC405TMS0" SIGNAME="ppc440_0_jtagppc_bus_JTGC405TMS"/> + <PORT BUS="JTAGPPC0" DEF_SIGNAME="ppc440_0_jtagppc_bus_JTGC405TRSTNEG" DIR="O" MPD_INDEX="10" NAME="JTGC405TRSTNEG0" SIGNAME="ppc440_0_jtagppc_bus_JTGC405TRSTNEG"/> + <PORT BUS="JTAGPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="11" NAME="C405JTGTDO1" SIGNAME="__NOC__"/> + <PORT BUS="JTAGPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="12" NAME="C405JTGTDOEN1" SIGNAME="__NOC__"/> + <PORT BUS="JTAGPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="13" NAME="JTGC405TCK1" SIGNAME="__NOC__"/> + <PORT BUS="JTAGPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="14" NAME="JTGC405TDI1" SIGNAME="__NOC__"/> + <PORT BUS="JTAGPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="15" NAME="JTGC405TMS1" SIGNAME="__NOC__"/> + <PORT BUS="JTAGPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="16" NAME="JTGC405TRSTNEG1" SIGNAME="__NOC__"/> + <BUSINTERFACE BUSNAME="ppc440_0_jtagppc_bus" BUSSTD="XIL" BUSSTD_PSF="XIL_JTAGPPC" IS_INMHS="TRUE" MPD_INDEX="0" NAME="JTAGPPC0" TYPE="INITIATOR"/> + <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_JTAGPPC" IS_VALID="FALSE" MPD_INDEX="1" NAME="JTAGPPC1" TYPE="INITIATOR"/> + </MODULE> + <MODULE HWVERSION="2.00.a" INSTANCE="proc_sys_reset_0" IPTYPE="PERIPHERAL" MHS_INDEX="18" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset"> + <DESCRIPTION TYPE="SHORT">Processor System Reset Module</DESCRIPTION> + <DESCRIPTION TYPE="LONG">Reset management module</DESCRIPTION> + <DOCUMENTATION> + <DOCUMENT SOURCE="c:/devtools/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_sys_reset_v2_00_a/doc/proc_sys_reset.pdf" TYPE="IP"/> + </DOCUMENTATION> + <LICENSEINFO ICON_NAME="ps_core_preferred"/> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_SUBFAMILY" TYPE="string" VALUE="fx"> + <DESCRIPTION>Device Subfamily</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="1" NAME="C_EXT_RST_WIDTH" TYPE="integer" VALUE="4"> + <DESCRIPTION>Number of Clocks Before Input Change is Recognized On The External Reset Input </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="2" NAME="C_AUX_RST_WIDTH" TYPE="integer" VALUE="4"> + <DESCRIPTION>Number of Clocks Before Input Change is Recognized On The Auxiliary Reset Input </DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="USER" MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="std_logic" VALUE="0"> + <DESCRIPTION>External Reset Active High </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="4" NAME="C_AUX_RESET_HIGH" TYPE="std_logic" VALUE="1"> + <DESCRIPTION>Auxiliary Reset Active High </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="5" NAME="C_NUM_BUS_RST" TYPE="integer" VALUE="1"> + <DESCRIPTION>Number of Bus Structure Reset Registered Outputs </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="6" NAME="C_NUM_PERP_RST" TYPE="integer" VALUE="1"> + <DESCRIPTION>Number of Peripheral Reset Registered Outputs </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="7" NAME="C_FAMILY" VALUE="virtex5"> + <DESCRIPTION>Device Family</DESCRIPTION> + </PARAMETER> + <PORT CLKFREQUENCY="125000000" DIR="I" IS_INMHS="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="Slowest_sync_clk" SIGIS="CLK" SIGNAME="clk_125_0000MHzPLL0_ADJUST"/> + <PORT DIR="I" IS_INMHS="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="Ext_Reset_In" SIGIS="RST" SIGNAME="sys_rst_s"/> + <PORT DIR="I" IS_INMHS="TRUE" MHS_INDEX="2" MPD_INDEX="10" NAME="Dcm_locked" SIGNAME="Dcm_all_locked"/> + <PORT DIR="O" IS_INMHS="TRUE" MHS_INDEX="3" MPD_INDEX="18" NAME="Bus_Struct_Reset" SIGIS="RST" SIGNAME="sys_bus_reset" VECFORMULA="[0:C_NUM_BUS_RST-1]"/> + <PORT DIR="O" IS_INMHS="TRUE" MHS_INDEX="4" MPD_INDEX="19" NAME="Peripheral_Reset" SIGIS="RST" SIGNAME="sys_periph_reset" VECFORMULA="[0:C_NUM_PERP_RST-1]"/> + <PORT DIR="I" MPD_INDEX="2" NAME="Aux_Reset_In" SIGIS="RST" SIGNAME="__NOC__"/> + <PORT DIR="I" MPD_INDEX="3" NAME="MB_Debug_Sys_Rst" SIGIS="RST" SIGNAME="__NOC__"/> + <PORT BUS="RESETPPC0" DEF_SIGNAME="ppc_reset_bus_Core_Reset_Req" DIR="I" MPD_INDEX="4" NAME="Core_Reset_Req_0" SIGIS="RST" SIGNAME="ppc_reset_bus_Core_Reset_Req"/> + <PORT BUS="RESETPPC0" DEF_SIGNAME="ppc_reset_bus_Chip_Reset_Req" DIR="I" MPD_INDEX="5" NAME="Chip_Reset_Req_0" SIGIS="RST" SIGNAME="ppc_reset_bus_Chip_Reset_Req"/> + <PORT BUS="RESETPPC0" DEF_SIGNAME="ppc_reset_bus_System_Reset_Req" DIR="I" MPD_INDEX="6" NAME="System_Reset_Req_0" SIGIS="RST" SIGNAME="ppc_reset_bus_System_Reset_Req"/> + <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="7" NAME="Core_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/> + <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="8" NAME="Chip_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/> + <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="9" NAME="System_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/> + <PORT BUS="RESETPPC0" DEF_SIGNAME="ppc_reset_bus_RstcPPCresetcore" DIR="O" MPD_INDEX="11" NAME="RstcPPCresetcore_0" SIGIS="RST" SIGNAME="ppc_reset_bus_RstcPPCresetcore"/> + <PORT BUS="RESETPPC0" DEF_SIGNAME="ppc_reset_bus_RstsPPCresetchip" DIR="O" MPD_INDEX="12" NAME="RstcPPCresetchip_0" SIGIS="RST" SIGNAME="ppc_reset_bus_RstsPPCresetchip"/> + <PORT BUS="RESETPPC0" DEF_SIGNAME="ppc_reset_bus_RstcPPCresetsys" DIR="O" MPD_INDEX="13" NAME="RstcPPCresetsys_0" SIGIS="RST" SIGNAME="ppc_reset_bus_RstcPPCresetsys"/> + <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="14" NAME="RstcPPCresetcore_1" SIGIS="RST" SIGNAME="__NOC__"/> + <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="15" NAME="RstcPPCresetchip_1" SIGIS="RST" SIGNAME="__NOC__"/> + <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="16" NAME="RstcPPCresetsys_1" SIGIS="RST" SIGNAME="__NOC__"/> + <PORT DIR="O" MPD_INDEX="17" NAME="MB_Reset" SIGIS="RST" SIGNAME="__NOC__"/> + <BUSINTERFACE BUSNAME="ppc_reset_bus" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_INMHS="TRUE" MPD_INDEX="0" NAME="RESETPPC0" TYPE="INITIATOR"/> + <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="1" NAME="RESETPPC1" TYPE="INITIATOR"/> + </MODULE> + <MODULE HWVERSION="2.00.a" INSTANCE="xps_intc_0" IPTYPE="PERIPHERAL" MHS_INDEX="19" MODCLASS="INTERRUPT_CNTLR" MODTYPE="xps_intc"> + <DESCRIPTION TYPE="SHORT">XPS Interrupt Controller</DESCRIPTION> + <DESCRIPTION TYPE="LONG">intc core attached to the PLBV46</DESCRIPTION> + <DOCUMENTATION> + <DOCUMENT SOURCE="c:/devtools/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/xps_intc_v2_00_a/doc/xps_intc.pdf" TYPE="IP"/> + </DOCUMENTATION> + <LICENSEINFO ICON_NAME="ps_core_preferred"/> + <PARAMETER MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex5"> + <DESCRIPTION>Device Family</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector(0 to 31)" VALUE="0x81800000"> + <DESCRIPTION>Base Address</DESCRIPTION> + </PARAMETER> + <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" MPD_INDEX="2" NAME="C_HIGHADDR" TYPE="std_logic_vector(0 to 31)" VALUE="0x8180ffff"> + <DESCRIPTION>High Address</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="3" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32"> + <DESCRIPTION>PLB Address Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="128"> + <DESCRIPTION>PLB Data Bus Width</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="5" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="6" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Number of PLB Masters</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="7" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="8" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"> + <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="9" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"> + <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="10" NAME="C_NUM_INTR_INPUTS" TYPE="INTEGER" VALUE="2"> + <DESCRIPTION>Number of Interrupt Inputs </DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="11" NAME="C_KIND_OF_INTR" TYPE="std_logic_vector(31 downto 0)" VALUE="0b00000000000000000000000000000001"> + <DESCRIPTION>Type of Interrupt for Each Input </DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_KIND_OF_EDGE" TYPE="std_logic_vector(31 downto 0)" VALUE="0b00000000000000000000000000000001"> + <DESCRIPTION>Type of Each Edge Senstive Interrupt </DESCRIPTION> + </PARAMETER> + <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_KIND_OF_LVL" TYPE="std_logic_vector(31 downto 0)" VALUE="0b00000000000000000000000000000000"> + <DESCRIPTION>Type of Each Level Sensitive Interrupt </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="14" NAME="C_HAS_IPR" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Support IPR </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="15" NAME="C_HAS_SIE" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Support SIE </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="16" NAME="C_HAS_CIE" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Support CIE </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="17" NAME="C_HAS_IVR" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>Support IVR </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="18" NAME="C_IRQ_IS_LEVEL" TYPE="INTEGER" VALUE="1"> + <DESCRIPTION>IRQ Output Use Level </DESCRIPTION> + </PARAMETER> + <PARAMETER MPD_INDEX="19" NAME="C_IRQ_ACTIVE" TYPE="std_logic" VALUE="1"> + <DESCRIPTION>The Sense of IRQ Output </DESCRIPTION> + </PARAMETER> + <MEMORYMAP> + <MEMRANGE BASEDECIMAL="2172649472" BASENAME="C_BASEADDR" BASEVALUE="0x81800000" HIGHDECIMAL="2172715007" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8180ffff" MEMTYPE="REGISTER" MINSIZE="0x20" SIZE="65536" SIZEABRV="64K"> + <SLVINTERFACES> + <BUSINTERFACE NAME="SPLB"/> + </SLVINTERFACES> + </MEMRANGE> + </MEMORYMAP> + <PORT DIR="I" ENDIAN="LITTLE" IS_INMHS="TRUE" LSB="0" MHS_INDEX="0" MPD_INDEX="42" MSB="1" NAME="Intr" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="fpga_0_Ethernet_MAC_MDINT_pin&RS232_Uart_1_Interrupt" VECFORMULA="[(C_NUM_INTR_INPUTS-1):0]"/> + <PORT DIR="O" IS_INMHS="TRUE" MHS_INDEX="1" MPD_INDEX="43" NAME="Irq" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="ppc440_0_EICC440EXTIRQ"/> + <PORT BUS="SPLB" CLKFREQUENCY="125000000" DEF_SIGNAME="clk_125_0000MHzPLL0_ADJUST" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_125_0000MHzPLL0_ADJUST"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="plb_v46_0_SPLB_Rst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_ABus" DIR="I" MPD_INDEX="2" NAME="PLB_ABus" SIGNAME="plb_v46_0_PLB_ABus" VECFORMULA="[0:31]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_PAValid" DIR="I" MPD_INDEX="3" NAME="PLB_PAValid" SIGNAME="plb_v46_0_PLB_PAValid"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_masterID" DIR="I" MPD_INDEX="4" NAME="PLB_masterID" SIGNAME="plb_v46_0_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_RNW" DIR="I" MPD_INDEX="5" NAME="PLB_RNW" SIGNAME="plb_v46_0_PLB_RNW"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_BE" DIR="I" MPD_INDEX="6" NAME="PLB_BE" SIGNAME="plb_v46_0_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_size" DIR="I" MPD_INDEX="7" NAME="PLB_size" SIGNAME="plb_v46_0_PLB_size" VECFORMULA="[0:3]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_type" DIR="I" MPD_INDEX="8" NAME="PLB_type" SIGNAME="plb_v46_0_PLB_type" VECFORMULA="[0:2]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrDBus" DIR="I" MPD_INDEX="9" NAME="PLB_wrDBus" SIGNAME="plb_v46_0_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_UABus" DIR="I" MPD_INDEX="10" NAME="PLB_UABus" SIGNAME="plb_v46_0_PLB_UABus" VECFORMULA="[0:31]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_SAValid" DIR="I" MPD_INDEX="11" NAME="PLB_SAValid" SIGNAME="plb_v46_0_PLB_SAValid"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPrim" DIR="I" MPD_INDEX="12" NAME="PLB_rdPrim" SIGNAME="plb_v46_0_PLB_rdPrim"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPrim" DIR="I" MPD_INDEX="13" NAME="PLB_wrPrim" SIGNAME="plb_v46_0_PLB_wrPrim"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_abort" DIR="I" MPD_INDEX="14" NAME="PLB_abort" SIGNAME="plb_v46_0_PLB_abort"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_busLock" DIR="I" MPD_INDEX="15" NAME="PLB_busLock" SIGNAME="plb_v46_0_PLB_busLock"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_MSize" DIR="I" MPD_INDEX="16" NAME="PLB_MSize" SIGNAME="plb_v46_0_PLB_MSize" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_lockErr" DIR="I" MPD_INDEX="17" NAME="PLB_lockErr" SIGNAME="plb_v46_0_PLB_lockErr"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrBurst" DIR="I" MPD_INDEX="18" NAME="PLB_wrBurst" SIGNAME="plb_v46_0_PLB_wrBurst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdBurst" DIR="I" MPD_INDEX="19" NAME="PLB_rdBurst" SIGNAME="plb_v46_0_PLB_rdBurst"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPendReq" DIR="I" MPD_INDEX="20" NAME="PLB_wrPendReq" SIGNAME="plb_v46_0_PLB_wrPendReq"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPendReq" DIR="I" MPD_INDEX="21" NAME="PLB_rdPendReq" SIGNAME="plb_v46_0_PLB_rdPendReq"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_wrPendPri" DIR="I" MPD_INDEX="22" NAME="PLB_wrPendPri" SIGNAME="plb_v46_0_PLB_wrPendPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_rdPendPri" DIR="I" MPD_INDEX="23" NAME="PLB_rdPendPri" SIGNAME="plb_v46_0_PLB_rdPendPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_reqPri" DIR="I" MPD_INDEX="24" NAME="PLB_reqPri" SIGNAME="plb_v46_0_PLB_reqPri" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_PLB_TAttribute" DIR="I" MPD_INDEX="25" NAME="PLB_TAttribute" SIGNAME="plb_v46_0_PLB_TAttribute" VECFORMULA="[0:15]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_addrAck" DIR="O" MPD_INDEX="26" NAME="Sl_addrAck" SIGNAME="plb_v46_0_Sl_addrAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_SSize" DIR="O" MPD_INDEX="27" NAME="Sl_SSize" SIGNAME="plb_v46_0_Sl_SSize" VECFORMULA="[0:1]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wait" DIR="O" MPD_INDEX="28" NAME="Sl_wait" SIGNAME="plb_v46_0_Sl_wait"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rearbitrate" DIR="O" MPD_INDEX="29" NAME="Sl_rearbitrate" SIGNAME="plb_v46_0_Sl_rearbitrate"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrDAck" DIR="O" MPD_INDEX="30" NAME="Sl_wrDAck" SIGNAME="plb_v46_0_Sl_wrDAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrComp" DIR="O" MPD_INDEX="31" NAME="Sl_wrComp" SIGNAME="plb_v46_0_Sl_wrComp"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdDBus" DIR="O" MPD_INDEX="32" NAME="Sl_rdDBus" SIGNAME="plb_v46_0_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdDAck" DIR="O" MPD_INDEX="33" NAME="Sl_rdDAck" SIGNAME="plb_v46_0_Sl_rdDAck"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdComp" DIR="O" MPD_INDEX="34" NAME="Sl_rdComp" SIGNAME="plb_v46_0_Sl_rdComp"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MBusy" DIR="O" MPD_INDEX="35" NAME="Sl_MBusy" SIGNAME="plb_v46_0_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MWrErr" DIR="O" MPD_INDEX="36" NAME="Sl_MWrErr" SIGNAME="plb_v46_0_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MRdErr" DIR="O" MPD_INDEX="37" NAME="Sl_MRdErr" SIGNAME="plb_v46_0_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_wrBTerm" DIR="O" MPD_INDEX="38" NAME="Sl_wrBTerm" SIGNAME="plb_v46_0_Sl_wrBTerm"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdWdAddr" DIR="O" MPD_INDEX="39" NAME="Sl_rdWdAddr" SIGNAME="plb_v46_0_Sl_rdWdAddr" VECFORMULA="[0:3]"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_rdBTerm" DIR="O" MPD_INDEX="40" NAME="Sl_rdBTerm" SIGNAME="plb_v46_0_Sl_rdBTerm"/> + <PORT BUS="SPLB" DEF_SIGNAME="plb_v46_0_Sl_MIRQ" DIR="O" MPD_INDEX="41" NAME="Sl_MIRQ" SIGNAME="plb_v46_0_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> + <BUSINTERFACE BUSNAME="plb_v46_0" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INMHS="TRUE" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE"/> + <INTERRUPTINFO INTC_INDEX="0" PROCESSOR="ppc440_0" TYPE="CONTROLLER"> + <SOURCE PRIORITY="0" SIGNAME="fpga_0_Ethernet_MAC_MDINT_pin"/> + <SOURCE INSTANCE="RS232_Uart_1" PRIORITY="1" SIGNAME="RS232_Uart_1_Interrupt"/> + </INTERRUPTINFO> + </MODULE> + </MODULES> + +</EDKSYSTEM>
\ No newline at end of file diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/xplorer.opt b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/xplorer.opt new file mode 100644 index 000000000..53ea0c72f --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/xplorer.opt @@ -0,0 +1 @@ + -device xc5vfx70tff1136-1 data/system.ucf 7 0
diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/xpsxflow.opt b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/xpsxflow.opt new file mode 100644 index 000000000..b8fbf7ab1 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/__xps/xpsxflow.opt @@ -0,0 +1 @@ + -device xc5vfx70tff1136-1 data/system.ucf 0
diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/blockdiagram/svg10.dtd b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/blockdiagram/svg10.dtd new file mode 100644 index 000000000..110f5ced5 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/blockdiagram/svg10.dtd @@ -0,0 +1,1704 @@ +<!-- ===================================================================== + This is the DTD for SVG 1.0. + + The specification for SVG that corresponds to this DTD is available at: + + http://www.w3.org/TR/2001/REC-SVG-20010904/ + + Copyright (c) 2000 W3C (MIT, INRIA, Keio), All Rights Reserved. + + For SVG 1.0: + + Namespace: + http://www.w3.org/2000/svg + + Public identifier: + PUBLIC "-//W3C//DTD SVG 1.0//EN" + + URI for the DTD: + http://www.w3.org/TR/2001/REC-SVG-20010904/DTD/svg10.dtd +============================================================================= --> + + +<!-- ============================================================== + ENTITY DECLARATIONS: Data types + ============================================================== --> + +<!ENTITY % BaselineShiftValue "CDATA"> + <!-- 'baseline-shift' property/attribute value (e.g., 'baseline', 'sub', etc.) --> + +<!ENTITY % Boolean "(false | true)"> + <!-- feature specification --> + +<!ENTITY % ClassList "CDATA"> + <!-- list of classes --> + +<!ENTITY % ClipValue "CDATA"> + <!-- 'clip' property/attribute value (e.g., 'auto', rect(...)) --> + +<!ENTITY % ClipPathValue "CDATA"> + <!-- 'clip-path' property/attribute value (e.g., 'none', %URI;) --> + +<!ENTITY % ClipFillRule "(nonzero | evenodd | inherit)"> + <!-- 'clip-rule' or fill-rule property/attribute value --> + +<!ENTITY % ContentType "CDATA"> + <!-- media type, as per [RFC2045] --> + +<!ENTITY % Coordinate "CDATA"> + <!-- a <coordinate> --> + +<!ENTITY % Coordinates "CDATA"> + <!-- a list of <coordinate>s --> + +<!ENTITY % Color "CDATA"> + <!-- a <color> value --> + +<!ENTITY % CursorValue "CDATA"> + <!-- 'cursor' property/attribute value (e.g., 'crosshair', %URI;) --> + +<!ENTITY % EnableBackgroundValue "CDATA"> + <!-- 'enable-background' property/attribute value (e.g., 'new', 'accumulate') --> + +<!ENTITY % ExtensionList "CDATA"> + <!-- extension list specification --> + +<!ENTITY % FeatureList "CDATA"> + <!-- feature list specification --> + +<!ENTITY % FilterValue "CDATA"> + <!-- 'filter' property/attribute value (e.g., 'none', %URI;) --> + +<!ENTITY % FontFamilyValue "CDATA"> + <!-- 'font-family' property/attribute value (i.e., list of fonts) --> + +<!ENTITY % FontSizeValue "CDATA"> + <!-- 'font-size' property/attribute value --> + +<!ENTITY % FontSizeAdjustValue "CDATA"> + <!-- 'font-size-adjust' property/attribute value --> + +<!ENTITY % GlyphOrientationHorizontalValue "CDATA"> + <!-- 'glyph-orientation-horizontal' property/attribute value (e.g., <angle>) --> + +<!ENTITY % GlyphOrientationVerticalValue "CDATA"> + <!-- 'glyph-orientation-vertical' property/attribute value (e.g., 'auto', <angle>) --> + +<!ENTITY % Integer "CDATA"> + <!-- a <integer> --> + +<!ENTITY % KerningValue "CDATA"> + <!-- 'kerning' property/attribute value (e.g., auto | <length>) --> + +<!ENTITY % LanguageCode "NMTOKEN"> + <!-- a language code, as per [RFC3066] --> + +<!ENTITY % LanguageCodes "CDATA"> + <!-- comma-separated list of language codes, as per [RFC3066] --> + +<!ENTITY % Length "CDATA"> + <!-- a <length> --> + +<!ENTITY % Lengths "CDATA"> + <!-- a list of <length>s --> + +<!ENTITY % LinkTarget "NMTOKEN"> + <!-- link to this target --> + +<!ENTITY % MarkerValue "CDATA"> + <!-- 'marker' property/attribute value (e.g., 'none', %URI;) --> + +<!ENTITY % MaskValue "CDATA"> + <!-- 'mask' property/attribute value (e.g., 'none', %URI;) --> + +<!ENTITY % MediaDesc "CDATA"> + <!-- comma-separated list of media descriptors. --> + +<!ENTITY % Number "CDATA"> + <!-- a <number> --> + +<!ENTITY % NumberOptionalNumber "CDATA"> + <!-- list of <number>s, but at least one and at most two --> + +<!ENTITY % NumberOrPercentage "CDATA"> + <!-- a <number> or a <percentage> --> + +<!ENTITY % Numbers "CDATA"> + <!-- a list of <number>s --> + +<!ENTITY % OpacityValue "CDATA"> + <!-- opacity value (e.g., <number>) --> + +<!ENTITY % Paint "CDATA"> + <!-- a 'fill' or 'stroke' property/attribute value: <paint> --> + +<!ENTITY % PathData "CDATA"> + <!-- a path data specification --> + +<!ENTITY % Points "CDATA"> + <!-- a list of points --> + +<!ENTITY % PreserveAspectRatioSpec "CDATA"> + <!-- 'preserveAspectRatio' attribute specification --> + +<!ENTITY % Script "CDATA"> + <!-- script expression --> + +<!ENTITY % SpacingValue "CDATA"> + <!-- 'letter-spacing' or 'word-spacing' property/attribute value (e.g., normal | <length>) --> + +<!ENTITY % StrokeDashArrayValue "CDATA"> + <!-- 'stroke-dasharray' property/attribute value (e.g., 'none', list of <number>s) --> + +<!ENTITY % StrokeDashOffsetValue "CDATA"> + <!-- 'stroke-dashoffset' property/attribute value (e.g., 'none', <legnth>) --> + +<!ENTITY % StrokeMiterLimitValue "CDATA"> + <!-- 'stroke-miterlimit' property/attribute value (e.g., <number>) --> + +<!ENTITY % StrokeWidthValue "CDATA"> + <!-- 'stroke-width' property/attribute value (e.g., <length>) --> + +<!ENTITY % StructuredText + "content CDATA #FIXED 'structured text'" > + +<!ENTITY % StyleSheet "CDATA"> + <!-- style sheet data --> + +<!ENTITY % SVGColor "CDATA"> + <!-- An SVG color value (RGB plus optional ICC) --> + +<!ENTITY % Text "CDATA"> + <!-- arbitrary text string --> + +<!ENTITY % TextDecorationValue "CDATA"> + <!-- 'text-decoration' property/attribute value (e.g., 'none', 'underline') --> + +<!ENTITY % TransformList "CDATA"> + <!-- list of transforms --> + +<!ENTITY % URI "CDATA"> + <!-- a Uniform Resource Identifier, see [URI] --> + +<!ENTITY % ViewBoxSpec "CDATA"> + <!-- 'viewBox' attribute specification --> + + +<!-- ============================================================== + ENTITY DECLARATIONS: Collections of common attributes + ============================================================== --> + +<!-- All elements have an ID. --> +<!ENTITY % stdAttrs + "id ID #IMPLIED + xml:base %URI; #IMPLIED" > + +<!-- Common attributes for elements that might contain character data content. --> +<!ENTITY % langSpaceAttrs + "xml:lang %LanguageCode; #IMPLIED + xml:space (default|preserve) #IMPLIED" > + +<!-- Common attributes to check for system capabilities. --> +<!ENTITY % testAttrs + "requiredFeatures %FeatureList; #IMPLIED + requiredExtensions %ExtensionList; #IMPLIED + systemLanguage %LanguageCodes; #IMPLIED" > + +<!-- For most uses of URI referencing: + standard XLink attributes other than xlink:href. --> +<!ENTITY % xlinkRefAttrs + "xmlns:xlink CDATA #FIXED 'http://www.w3.org/1999/xlink' + xlink:type (simple) #FIXED 'simple' + xlink:role %URI; #IMPLIED + xlink:arcrole %URI; #IMPLIED + xlink:title CDATA #IMPLIED + xlink:show (other) 'other' + xlink:actuate (onLoad) #FIXED 'onLoad'" > + +<!-- Standard XLink attributes for uses of URI referencing where xlink:show is 'embed' --> +<!ENTITY % xlinkRefAttrsEmbed + "xmlns:xlink CDATA #FIXED 'http://www.w3.org/1999/xlink' + xlink:type (simple) #FIXED 'simple' + xlink:role %URI; #IMPLIED + xlink:arcrole %URI; #IMPLIED + xlink:title CDATA #IMPLIED + xlink:show (embed) 'embed' + xlink:actuate (onLoad) #FIXED 'onLoad'" > + +<!ENTITY % graphicsElementEvents + "onfocusin %Script; #IMPLIED + onfocusout %Script; #IMPLIED + onactivate %Script; #IMPLIED + onclick %Script; #IMPLIED + onmousedown %Script; #IMPLIED + onmouseup %Script; #IMPLIED + onmouseover %Script; #IMPLIED + onmousemove %Script; #IMPLIED + onmouseout %Script; #IMPLIED + onload %Script; #IMPLIED" > + +<!ENTITY % documentEvents + "onunload %Script; #IMPLIED + onabort %Script; #IMPLIED + onerror %Script; #IMPLIED + onresize %Script; #IMPLIED + onscroll %Script; #IMPLIED + onzoom %Script; #IMPLIED" > + +<!ENTITY % animationEvents + "onbegin %Script; #IMPLIED + onend %Script; #IMPLIED + onrepeat %Script; #IMPLIED" > + +<!-- This entity allows for at most one of desc, title and metadata, + supplied in any order --> +<!ENTITY % descTitleMetadata + "(((desc,((title,metadata?)|(metadata,title?))?)| + (title,((desc,metadata?)|(metadata,desc?))?)| + (metadata,((desc,title?)|(title,desc?))?))?)" > + + +<!-- ============================================================== + ENTITY DECLARATIONS: Collections of presentation attributes + ============================================================== --> + +<!-- The following presentation attributes have to do with specifying color. --> +<!ENTITY % PresentationAttributes-Color + "color %Color; #IMPLIED + color-interpolation (auto | sRGB | linearRGB | inherit) #IMPLIED + color-rendering (auto | optimizeSpeed | optimizeQuality | inherit) #IMPLIED " > + +<!-- The following presentation attributes apply to container elements. --> +<!ENTITY % PresentationAttributes-Containers + "enable-background %EnableBackgroundValue; #IMPLIED " > + +<!-- The following presentation attributes apply to 'feFlood' elements. --> +<!ENTITY % PresentationAttributes-feFlood + "flood-color %SVGColor; #IMPLIED + flood-opacity %OpacityValue; #IMPLIED " > + +<!-- The following presentation attributes apply to filling and stroking operations. --> +<!ENTITY % PresentationAttributes-FillStroke + "fill %Paint; #IMPLIED + fill-opacity %OpacityValue; #IMPLIED + fill-rule %ClipFillRule; #IMPLIED + stroke %Paint; #IMPLIED + stroke-dasharray %StrokeDashArrayValue; #IMPLIED + stroke-dashoffset %StrokeDashOffsetValue; #IMPLIED + stroke-linecap (butt | round | square | inherit) #IMPLIED + stroke-linejoin (miter | round | bevel | inherit) #IMPLIED + stroke-miterlimit %StrokeMiterLimitValue; #IMPLIED + stroke-opacity %OpacityValue; #IMPLIED + stroke-width %StrokeWidthValue; #IMPLIED " > + +<!-- The following presentation attributes apply to filter primitives. --> +<!ENTITY % PresentationAttributes-FilterPrimitives + "color-interpolation-filters (auto | sRGB | linearRGB | inherit) #IMPLIED " > + +<!-- The following presentation attributes have to do with selecting a font to use. --> +<!ENTITY % PresentationAttributes-FontSpecification + "font-family %FontFamilyValue; #IMPLIED + font-size %FontSizeValue; #IMPLIED + font-size-adjust %FontSizeAdjustValue; #IMPLIED + font-stretch (normal | wider | narrower | ultra-condensed | extra-condensed | + condensed | semi-condensed | semi-expanded | expanded | + extra-expanded | ultra-expanded | inherit) #IMPLIED + font-style (normal | italic | oblique | inherit) #IMPLIED + font-variant (normal | small-caps | inherit) #IMPLIED + font-weight (normal | bold | bolder | lighter | 100 | 200 | 300 | + 400 | 500 | 600 | 700 | 800 | 900 | inherit) #IMPLIED " > + +<!-- The following presentation attributes apply to gradient 'stop' elements. --> +<!ENTITY % PresentationAttributes-Gradients + "stop-color %SVGColor; #IMPLIED + stop-opacity %OpacityValue; #IMPLIED " > + +<!-- The following presentation attributes apply to graphics elements. --> +<!ENTITY % PresentationAttributes-Graphics + "clip-path %ClipPathValue; #IMPLIED + clip-rule %ClipFillRule; #IMPLIED + cursor %CursorValue; #IMPLIED + display (inline | block | list-item | run-in | compact | marker | + table | inline-table | table-row-group | table-header-group | + table-footer-group | table-row | table-column-group | table-column | + table-cell | table-caption | none | inherit) #IMPLIED + filter %FilterValue; #IMPLIED + image-rendering (auto | optimizeSpeed | optimizeQuality | inherit) #IMPLIED + mask %MaskValue; #IMPLIED + opacity %OpacityValue; #IMPLIED + pointer-events (visiblePainted | visibleFill | visibleStroke | visible | + painted | fill | stroke | all | none | inherit) #IMPLIED + shape-rendering (auto | optimizeSpeed | crispEdges | geometricPrecision | inherit) #IMPLIED + text-rendering (auto | optimizeSpeed | optimizeLegibility | geometricPrecision | inherit) #IMPLIED + visibility (visible | hidden | inherit) #IMPLIED " > + +<!-- The following presentation attributes apply to 'image' elements. --> +<!ENTITY % PresentationAttributes-Images + "color-profile CDATA #IMPLIED " > + +<!--The following presentation attributes apply to 'feDiffuseLighting' and 'feSpecularLighting' elements. --> +<!ENTITY % PresentationAttributes-LightingEffects + "lighting-color %SVGColor; #IMPLIED " > + +<!-- The following presentation attributes apply to marker operations. --> +<!ENTITY % PresentationAttributes-Markers + "marker-start %MarkerValue; #IMPLIED + marker-mid %MarkerValue; #IMPLIED + marker-end %MarkerValue; #IMPLIED " > + +<!-- The following presentation attributes apply to text content elements. --> +<!ENTITY % PresentationAttributes-TextContentElements + "alignment-baseline (baseline | top | before-edge | text-top | text-before-edge | + middle | bottom | after-edge | text-bottom | text-after-edge | + ideographic | lower | hanging | mathematical | inherit) #IMPLIED + baseline-shift %BaselineShiftValue; #IMPLIED + direction (ltr | rtl | inherit) #IMPLIED + dominant-baseline (auto | autosense-script | no-change | reset| + ideographic | lower | hanging | mathematical | inherit ) #IMPLIED + glyph-orientation-horizontal %GlyphOrientationHorizontalValue; #IMPLIED + glyph-orientation-vertical %GlyphOrientationVerticalValue; #IMPLIED + kerning %KerningValue; #IMPLIED + letter-spacing %SpacingValue; #IMPLIED + text-anchor (start | middle | end | inherit) #IMPLIED + text-decoration %TextDecorationValue; #IMPLIED + unicode-bidi (normal | embed | bidi-override | inherit) #IMPLIED + word-spacing %SpacingValue; #IMPLIED " > + +<!-- The following presentation attributes apply to 'text' elements. --> +<!ENTITY % PresentationAttributes-TextElements + "writing-mode (lr-tb | rl-tb | tb-rl | lr | rl | tb | inherit) #IMPLIED " > + +<!-- The following presentation attributes apply to elements that establish viewports. --> +<!ENTITY % PresentationAttributes-Viewports + "clip %ClipValue; #IMPLIED + overflow (visible | hidden | scroll | auto | inherit) #IMPLIED " > + +<!--The following represents the complete list of presentation attributes. --> +<!ENTITY % PresentationAttributes-All + "%PresentationAttributes-Color; + %PresentationAttributes-Containers; + %PresentationAttributes-feFlood; + %PresentationAttributes-FillStroke; + %PresentationAttributes-FilterPrimitives; + %PresentationAttributes-FontSpecification; + %PresentationAttributes-Gradients; + %PresentationAttributes-Graphics; + %PresentationAttributes-Images; + %PresentationAttributes-LightingEffects; + %PresentationAttributes-Markers; + %PresentationAttributes-TextContentElements; + %PresentationAttributes-TextElements; + %PresentationAttributes-Viewports;" > + + + +<!-- ============================================================== + ENTITY DECLARATIONS: DTD extensions + ============================================================== --> + +<!-- Allow for extending the DTD with internal subset for + container and graphics elements --> +<!ENTITY % ceExt "" > +<!ENTITY % geExt "" > + + +<!-- ============================================================== + DECLARATIONS CORRESPONDING TO: Document Structure + ============================================================== --> + +<!ENTITY % svgExt "" > +<!ELEMENT svg (desc|title|metadata|defs| + path|text|rect|circle|ellipse|line|polyline|polygon| + use|image|svg|g|view|switch|a|altGlyphDef| + script|style|symbol|marker|clipPath|mask| + linearGradient|radialGradient|pattern|filter|cursor|font| + animate|set|animateMotion|animateColor|animateTransform| + color-profile|font-face + %ceExt;%svgExt;)* > +<!ATTLIST svg + xmlns CDATA #FIXED "http://www.w3.org/2000/svg" + xmlns:xlink CDATA #FIXED "http://www.w3.org/1999/xlink" + %stdAttrs; + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-All; + viewBox %ViewBoxSpec; #IMPLIED + preserveAspectRatio %PreserveAspectRatioSpec; 'xMidYMid meet' + zoomAndPan (disable | magnify) 'magnify' + %graphicsElementEvents; + %documentEvents; + version %Number; #FIXED "1.0" + x %Coordinate; #IMPLIED + y %Coordinate; #IMPLIED + width %Length; #IMPLIED + height %Length; #IMPLIED + contentScriptType %ContentType; "text/ecmascript" + contentStyleType %ContentType; "text/css" > + +<!ENTITY % gExt "" > +<!ELEMENT g (desc|title|metadata|defs| + path|text|rect|circle|ellipse|line|polyline|polygon| + use|image|svg|g|view|switch|a|altGlyphDef| + script|style|symbol|marker|clipPath|mask| + linearGradient|radialGradient|pattern|filter|cursor|font| + animate|set|animateMotion|animateColor|animateTransform| + color-profile|font-face + %ceExt;%gExt;)* > +<!ATTLIST g + %stdAttrs; + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-All; + transform %TransformList; #IMPLIED + %graphicsElementEvents; > + +<!ENTITY % defsExt "" > +<!ELEMENT defs (desc|title|metadata|defs| + path|text|rect|circle|ellipse|line|polyline|polygon| + use|image|svg|g|view|switch|a|altGlyphDef| + script|style|symbol|marker|clipPath|mask| + linearGradient|radialGradient|pattern|filter|cursor|font| + animate|set|animateMotion|animateColor|animateTransform| + color-profile|font-face + %ceExt;%defsExt;)* > +<!ATTLIST defs + %stdAttrs; + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-All; + transform %TransformList; #IMPLIED + %graphicsElementEvents; > + +<!ENTITY % descExt "" > +<!ELEMENT desc (#PCDATA %descExt;)* > +<!ATTLIST desc + %stdAttrs; + %langSpaceAttrs; + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %StructuredText; > + +<!ENTITY % titleExt "" > +<!ELEMENT title (#PCDATA %titleExt;)* > +<!ATTLIST title + %stdAttrs; + %langSpaceAttrs; + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %StructuredText; > + +<!ENTITY % symbolExt "" > +<!ELEMENT symbol (desc|title|metadata|defs| + path|text|rect|circle|ellipse|line|polyline|polygon| + use|image|svg|g|view|switch|a|altGlyphDef| + script|style|symbol|marker|clipPath|mask| + linearGradient|radialGradient|pattern|filter|cursor|font| + animate|set|animateMotion|animateColor|animateTransform| + color-profile|font-face + %ceExt;%symbolExt;)* > +<!ATTLIST symbol + %stdAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-All; + viewBox %ViewBoxSpec; #IMPLIED + preserveAspectRatio %PreserveAspectRatioSpec; 'xMidYMid meet' + %graphicsElementEvents; > + +<!ENTITY % useExt "" > +<!ELEMENT use (%descTitleMetadata;,(animate|set|animateMotion|animateColor|animateTransform + %geExt;%useExt;)*) > +<!ATTLIST use + %stdAttrs; + %xlinkRefAttrsEmbed; + xlink:href %URI; #REQUIRED + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-All; + transform %TransformList; #IMPLIED + %graphicsElementEvents; + x %Coordinate; #IMPLIED + y %Coordinate; #IMPLIED + width %Length; #IMPLIED + height %Length; #IMPLIED > + +<!ENTITY % imageExt "" > +<!ELEMENT image (%descTitleMetadata;,(animate|set|animateMotion|animateColor|animateTransform + %geExt;%imageExt;)*) > +<!ATTLIST image + %stdAttrs; + %xlinkRefAttrsEmbed; + xlink:href %URI; #REQUIRED + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-Graphics; + %PresentationAttributes-Images; + %PresentationAttributes-Viewports; + transform %TransformList; #IMPLIED + preserveAspectRatio %PreserveAspectRatioSpec; 'xMidYMid meet' + %graphicsElementEvents; + x %Coordinate; #IMPLIED + y %Coordinate; #IMPLIED + width %Length; #REQUIRED + height %Length; #REQUIRED > + +<!ENTITY % switchExt "" > +<!ELEMENT switch (%descTitleMetadata;, + (path|text|rect|circle|ellipse|line|polyline|polygon| + use|image|svg|g|switch|a|foreignObject| + animate|set|animateMotion|animateColor|animateTransform + %ceExt;%switchExt;)*) > +<!ATTLIST switch + %stdAttrs; + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-All; + transform %TransformList; #IMPLIED + %graphicsElementEvents; > + + +<!-- ============================================================== + DECLARATIONS CORRESPONDING TO: Styling + ============================================================== --> + +<!ELEMENT style (#PCDATA) > +<!ATTLIST style + %stdAttrs; + xml:space (preserve) #FIXED "preserve" + type %ContentType; #REQUIRED + media %MediaDesc; #IMPLIED + title %Text; #IMPLIED > + + +<!-- ============================================================== + DECLARATIONS CORRESPONDING TO: Paths + ============================================================== --> + +<!ENTITY % pathExt "" > +<!ELEMENT path (%descTitleMetadata;,(animate|set|animateMotion|animateColor|animateTransform + %geExt;%pathExt;)*) > +<!ATTLIST path + %stdAttrs; + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-FillStroke; + %PresentationAttributes-Graphics; + %PresentationAttributes-Markers; + transform %TransformList; #IMPLIED + %graphicsElementEvents; + d %PathData; #REQUIRED + pathLength %Number; #IMPLIED > + + +<!-- ============================================================== + DECLARATIONS CORRESPONDING TO: Basic Shapes + ============================================================== --> + +<!ENTITY % rectExt "" > +<!ELEMENT rect (%descTitleMetadata;,(animate|set|animateMotion|animateColor|animateTransform + %geExt;%rectExt;)*) > +<!ATTLIST rect + %stdAttrs; + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-FillStroke; + %PresentationAttributes-Graphics; + transform %TransformList; #IMPLIED + %graphicsElementEvents; + x %Coordinate; #IMPLIED + y %Coordinate; #IMPLIED + width %Length; #REQUIRED + height %Length; #REQUIRED + rx %Length; #IMPLIED + ry %Length; #IMPLIED > + +<!ENTITY % circleExt "" > +<!ELEMENT circle (%descTitleMetadata;,(animate|set|animateMotion|animateColor|animateTransform + %geExt;%circleExt;)*) > +<!ATTLIST circle + %stdAttrs; + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-FillStroke; + %PresentationAttributes-Graphics; + transform %TransformList; #IMPLIED + %graphicsElementEvents; + cx %Coordinate; #IMPLIED + cy %Coordinate; #IMPLIED + r %Length; #REQUIRED > + +<!ENTITY % ellipseExt "" > +<!ELEMENT ellipse (%descTitleMetadata;,(animate|set|animateMotion|animateColor|animateTransform + %geExt;%ellipseExt;)*) > +<!ATTLIST ellipse + %stdAttrs; + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-FillStroke; + %PresentationAttributes-Graphics; + transform %TransformList; #IMPLIED + %graphicsElementEvents; + cx %Coordinate; #IMPLIED + cy %Coordinate; #IMPLIED + rx %Length; #REQUIRED + ry %Length; #REQUIRED > + +<!ENTITY % lineExt "" > +<!ELEMENT line (%descTitleMetadata;,(animate|set|animateMotion|animateColor|animateTransform + %geExt;%lineExt;)*) > +<!ATTLIST line + %stdAttrs; + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-FillStroke; + %PresentationAttributes-Graphics; + %PresentationAttributes-Markers; + transform %TransformList; #IMPLIED + %graphicsElementEvents; + x1 %Coordinate; #IMPLIED + y1 %Coordinate; #IMPLIED + x2 %Coordinate; #IMPLIED + y2 %Coordinate; #IMPLIED > + +<!ENTITY % polylineExt "" > +<!ELEMENT polyline (%descTitleMetadata;,(animate|set|animateMotion|animateColor|animateTransform + %geExt;%polylineExt;)*) > +<!ATTLIST polyline + %stdAttrs; + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-FillStroke; + %PresentationAttributes-Graphics; + %PresentationAttributes-Markers; + transform %TransformList; #IMPLIED + %graphicsElementEvents; + points %Points; #REQUIRED > + +<!ENTITY % polygonExt "" > +<!ELEMENT polygon (%descTitleMetadata;,(animate|set|animateMotion|animateColor|animateTransform + %geExt;%polygonExt;)*) > +<!ATTLIST polygon + %stdAttrs; + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-FillStroke; + %PresentationAttributes-Graphics; + %PresentationAttributes-Markers; + transform %TransformList; #IMPLIED + %graphicsElementEvents; + points %Points; #REQUIRED > + + +<!-- ============================================================== + DECLARATIONS CORRESPONDING TO: Text + ============================================================== --> + +<!ENTITY % textExt "" > +<!ELEMENT text (#PCDATA|desc|title|metadata| + tspan|tref|textPath|altGlyph|a|animate|set| + animateMotion|animateColor|animateTransform + %geExt;%textExt;)* > +<!ATTLIST text + %stdAttrs; + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-FillStroke; + %PresentationAttributes-FontSpecification; + %PresentationAttributes-Graphics; + %PresentationAttributes-TextContentElements; + %PresentationAttributes-TextElements; + transform %TransformList; #IMPLIED + %graphicsElementEvents; + x %Coordinates; #IMPLIED + y %Coordinates; #IMPLIED + dx %Lengths; #IMPLIED + dy %Lengths; #IMPLIED + rotate %Numbers; #IMPLIED + textLength %Length; #IMPLIED + lengthAdjust (spacing|spacingAndGlyphs) #IMPLIED > + +<!ENTITY % tspanExt "" > +<!ELEMENT tspan (#PCDATA|desc|title|metadata|tspan|tref|altGlyph|a|animate|set|animateColor + %tspanExt;)* > +<!ATTLIST tspan + %stdAttrs; + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-FillStroke; + %PresentationAttributes-FontSpecification; + %PresentationAttributes-Graphics; + %PresentationAttributes-TextContentElements; + %graphicsElementEvents; + x %Coordinates; #IMPLIED + y %Coordinates; #IMPLIED + dx %Lengths; #IMPLIED + dy %Lengths; #IMPLIED + rotate %Numbers; #IMPLIED + textLength %Length; #IMPLIED + lengthAdjust (spacing|spacingAndGlyphs) #IMPLIED > + +<!ENTITY % trefExt "" > +<!ELEMENT tref (desc|title|metadata|animate|set|animateColor + %trefExt;)* > +<!ATTLIST tref + %stdAttrs; + %xlinkRefAttrs; + xlink:href %URI; #REQUIRED + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-FillStroke; + %PresentationAttributes-FontSpecification; + %PresentationAttributes-Graphics; + %PresentationAttributes-TextContentElements; + %graphicsElementEvents; + x %Coordinates; #IMPLIED + y %Coordinates; #IMPLIED + dx %Lengths; #IMPLIED + dy %Lengths; #IMPLIED + rotate %Numbers; #IMPLIED + textLength %Length; #IMPLIED + lengthAdjust (spacing|spacingAndGlyphs) #IMPLIED > + +<!ENTITY % textPathExt "" > +<!ELEMENT textPath (#PCDATA|desc|title|metadata|tspan|tref|altGlyph|a|animate|set|animateColor + %textPathExt;)* > +<!ATTLIST textPath + %stdAttrs; + %xlinkRefAttrs; + xlink:href %URI; #REQUIRED + %langSpaceAttrs; + %testAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-FillStroke; + %PresentationAttributes-FontSpecification; + %PresentationAttributes-Graphics; + %PresentationAttributes-TextContentElements; + %graphicsElementEvents; + startOffset %Length; #IMPLIED + textLength %Length; #IMPLIED + lengthAdjust (spacing|spacingAndGlyphs) #IMPLIED + method (align|stretch) #IMPLIED + spacing (auto|exact) #IMPLIED > + +<!ENTITY % altGlyphExt "" > +<!ELEMENT altGlyph (#PCDATA %altGlyphExt;)* > +<!ATTLIST altGlyph + %stdAttrs; + %xlinkRefAttrs; + xlink:href %URI; #IMPLIED + glyphRef CDATA #IMPLIED + format CDATA #IMPLIED + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-FillStroke; + %PresentationAttributes-FontSpecification; + %PresentationAttributes-Graphics; + %PresentationAttributes-TextContentElements; + %graphicsElementEvents; + x %Coordinates; #IMPLIED + y %Coordinates; #IMPLIED + dx %Lengths; #IMPLIED + dy %Lengths; #IMPLIED + rotate %Numbers; #IMPLIED > + +<!ENTITY % altGlyphDefExt "" > +<!ELEMENT altGlyphDef ((glyphRef+|altGlyphItem+) %altGlyphDefExt;) > +<!ATTLIST altGlyphDef + %stdAttrs; > + +<!ENTITY % altGlyphItemExt "" > +<!ELEMENT altGlyphItem (glyphRef+ %altGlyphItemExt;) > +<!ATTLIST altGlyphItem + %stdAttrs; > + +<!ELEMENT glyphRef EMPTY > +<!ATTLIST glyphRef + %stdAttrs; + %xlinkRefAttrs; + xlink:href %URI; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-FontSpecification; + glyphRef CDATA #IMPLIED + format CDATA #IMPLIED + x %Number; #IMPLIED + y %Number; #IMPLIED + dx %Number; #IMPLIED + dy %Number; #IMPLIED > + + +<!-- ============================================================== + DECLARATIONS CORRESPONDING TO: Painting: Filling, Stroking and Marker Symbols + ============================================================== --> + +<!ENTITY % markerExt "" > +<!ELEMENT marker (desc|title|metadata|defs| + path|text|rect|circle|ellipse|line|polyline|polygon| + use|image|svg|g|view|switch|a|altGlyphDef| + script|style|symbol|marker|clipPath|mask| + linearGradient|radialGradient|pattern|filter|cursor|font| + animate|set|animateMotion|animateColor|animateTransform| + color-profile|font-face + %ceExt;%markerExt;)* > +<!ATTLIST marker + %stdAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-All; + viewBox %ViewBoxSpec; #IMPLIED + preserveAspectRatio %PreserveAspectRatioSpec; 'xMidYMid meet' + refX %Coordinate; #IMPLIED + refY %Coordinate; #IMPLIED + markerUnits (strokeWidth | userSpaceOnUse) #IMPLIED + markerWidth %Length; #IMPLIED + markerHeight %Length; #IMPLIED + orient CDATA #IMPLIED > + + +<!-- ============================================================== + DECLARATIONS CORRESPONDING TO: Color + ============================================================== --> + +<!ELEMENT color-profile (%descTitleMetadata;) > +<!ATTLIST color-profile + %stdAttrs; + %xlinkRefAttrs; + xlink:href %URI; #IMPLIED + local CDATA #IMPLIED + name CDATA #REQUIRED + rendering-intent (auto | perceptual | relative-colorimetric | saturation | absolute-colorimetric) "auto" > + + +<!-- ============================================================== + DECLARATIONS CORRESPONDING TO: Gradients and Patterns + ============================================================== --> + +<!ENTITY % linearGradientExt "" > +<!ELEMENT linearGradient (%descTitleMetadata;,(stop|animate|set|animateTransform + %linearGradientExt;)*) > +<!ATTLIST linearGradient + %stdAttrs; + %xlinkRefAttrs; + xlink:href %URI; #IMPLIED + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-Gradients; + gradientUnits (userSpaceOnUse | objectBoundingBox) #IMPLIED + gradientTransform %TransformList; #IMPLIED + x1 %Coordinate; #IMPLIED + y1 %Coordinate; #IMPLIED + x2 %Coordinate; #IMPLIED + y2 %Coordinate; #IMPLIED + spreadMethod (pad | reflect | repeat) #IMPLIED > + + +<!ENTITY % radialGradientExt "" > +<!ELEMENT radialGradient (%descTitleMetadata;,(stop|animate|set|animateTransform + %radialGradientExt;)*) > +<!ATTLIST radialGradient + %stdAttrs; + %xlinkRefAttrs; + xlink:href %URI; #IMPLIED + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-Gradients; + gradientUnits (userSpaceOnUse | objectBoundingBox) #IMPLIED + gradientTransform %TransformList; #IMPLIED + cx %Coordinate; #IMPLIED + cy %Coordinate; #IMPLIED + r %Length; #IMPLIED + fx %Coordinate; #IMPLIED + fy %Coordinate; #IMPLIED + spreadMethod (pad | reflect | repeat) #IMPLIED > + + +<!ENTITY % stopExt "" > +<!ELEMENT stop (animate|set|animateColor + %stopExt;)* > +<!ATTLIST stop + %stdAttrs; + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-Gradients; + offset %NumberOrPercentage; #REQUIRED > + +<!ENTITY % patternExt "" > +<!ELEMENT pattern (desc|title|metadata|defs| + path|text|rect|circle|ellipse|line|polyline|polygon| + use|image|svg|g|view|switch|a|altGlyphDef| + script|style|symbol|marker|clipPath|mask| + linearGradient|radialGradient|pattern|filter|cursor|font| + animate|set|animateMotion|animateColor|animateTransform| + color-profile|font-face + %ceExt;%patternExt;)* > +<!ATTLIST pattern + %stdAttrs; + %xlinkRefAttrs; + xlink:href %URI; #IMPLIED + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-All; + viewBox %ViewBoxSpec; #IMPLIED + preserveAspectRatio %PreserveAspectRatioSpec; 'xMidYMid meet' + patternUnits (userSpaceOnUse | objectBoundingBox) #IMPLIED + patternContentUnits (userSpaceOnUse | objectBoundingBox) #IMPLIED + patternTransform %TransformList; #IMPLIED + x %Coordinate; #IMPLIED + y %Coordinate; #IMPLIED + width %Length; #IMPLIED + height %Length; #IMPLIED > + + +<!-- ============================================================== + DECLARATIONS CORRESPONDING TO: Clipping, Masking and Compositing + ============================================================== --> + +<!ENTITY % clipPathExt "" > +<!ELEMENT clipPath (%descTitleMetadata;, + (path|text|rect|circle|ellipse|line|polyline|polygon| + use|animate|set|animateMotion|animateColor|animateTransform + %ceExt;%clipPathExt;)*) > +<!ATTLIST clipPath + %stdAttrs; + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-FillStroke; + %PresentationAttributes-FontSpecification; + %PresentationAttributes-Graphics; + %PresentationAttributes-TextContentElements; + %PresentationAttributes-TextElements; + transform %TransformList; #IMPLIED + clipPathUnits (userSpaceOnUse | objectBoundingBox) #IMPLIED > + +<!ENTITY % maskExt "" > +<!ELEMENT mask (desc|title|metadata|defs| + path|text|rect|circle|ellipse|line|polyline|polygon| + use|image|svg|g|view|switch|a|altGlyphDef| + script|style|symbol|marker|clipPath|mask| + linearGradient|radialGradient|pattern|filter|cursor|font| + animate|set|animateMotion|animateColor|animateTransform| + color-profile|font-face + %ceExt;%maskExt;)* > +<!ATTLIST mask + %stdAttrs; + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-All; + maskUnits (userSpaceOnUse | objectBoundingBox) #IMPLIED + maskContentUnits (userSpaceOnUse | objectBoundingBox) #IMPLIED + x %Coordinate; #IMPLIED + y %Coordinate; #IMPLIED + width %Length; #IMPLIED + height %Length; #IMPLIED > + + +<!-- ============================================================== + DECLARATIONS CORRESPONDING TO: Filter Effects + ============================================================== --> + +<!ENTITY % filterExt "" > +<!ELEMENT filter (%descTitleMetadata;,(feBlend|feFlood| + feColorMatrix|feComponentTransfer| + feComposite|feConvolveMatrix|feDiffuseLighting|feDisplacementMap| + feGaussianBlur|feImage|feMerge| + feMorphology|feOffset|feSpecularLighting| + feTile|feTurbulence| + animate|set + %filterExt;)*) > +<!ATTLIST filter + %stdAttrs; + %xlinkRefAttrs; + xlink:href %URI; #IMPLIED + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-All; + filterUnits (userSpaceOnUse | objectBoundingBox) #IMPLIED + primitiveUnits (userSpaceOnUse | objectBoundingBox) #IMPLIED + x %Coordinate; #IMPLIED + y %Coordinate; #IMPLIED + width %Length; #IMPLIED + height %Length; #IMPLIED + filterRes %NumberOptionalNumber; #IMPLIED > + +<!ENTITY % filter_primitive_attributes + "x %Coordinate; #IMPLIED + y %Coordinate; #IMPLIED + width %Length; #IMPLIED + height %Length; #IMPLIED + result CDATA #IMPLIED" > + +<!ENTITY % filter_primitive_attributes_with_in + "%filter_primitive_attributes; + in CDATA #IMPLIED"> + +<!ELEMENT feDistantLight (animate|set)* > +<!ATTLIST feDistantLight + %stdAttrs; + azimuth %Number; #IMPLIED + elevation %Number; #IMPLIED > + +<!ELEMENT fePointLight (animate|set)* > +<!ATTLIST fePointLight + %stdAttrs; + x %Number; #IMPLIED + y %Number; #IMPLIED + z %Number; #IMPLIED > + +<!ELEMENT feSpotLight (animate|set)* > +<!ATTLIST feSpotLight + %stdAttrs; + x %Number; #IMPLIED + y %Number; #IMPLIED + z %Number; #IMPLIED + pointsAtX %Number; #IMPLIED + pointsAtY %Number; #IMPLIED + pointsAtZ %Number; #IMPLIED + specularExponent %Number; #IMPLIED + limitingConeAngle %Number; #IMPLIED > + +<!ELEMENT feBlend (animate|set)* > +<!ATTLIST feBlend + %stdAttrs; + %PresentationAttributes-FilterPrimitives; + %filter_primitive_attributes_with_in; + in2 CDATA #REQUIRED + mode (normal | multiply | screen | darken | lighten) "normal" > + +<!ELEMENT feColorMatrix (animate|set)* > +<!ATTLIST feColorMatrix + %stdAttrs; + %PresentationAttributes-FilterPrimitives; + %filter_primitive_attributes_with_in; + type (matrix | saturate | hueRotate | luminanceToAlpha) "matrix" + values CDATA #IMPLIED > + +<!ELEMENT feComponentTransfer (feFuncR?,feFuncG?,feFuncB?,feFuncA?) > +<!ATTLIST feComponentTransfer + %stdAttrs; + %PresentationAttributes-FilterPrimitives; + %filter_primitive_attributes_with_in; > + +<!ENTITY % component_transfer_function_attributes + "type (identity | table | discrete | linear | gamma) #REQUIRED + tableValues CDATA #IMPLIED + slope %Number; #IMPLIED + intercept %Number; #IMPLIED + amplitude %Number; #IMPLIED + exponent %Number; #IMPLIED + offset %Number; #IMPLIED" > + +<!ELEMENT feFuncR (animate|set)* > +<!ATTLIST feFuncR + %stdAttrs; + %component_transfer_function_attributes; > + +<!ELEMENT feFuncG (animate|set)* > +<!ATTLIST feFuncG + %stdAttrs; + %component_transfer_function_attributes; > + +<!ELEMENT feFuncB (animate|set)* > +<!ATTLIST feFuncB + %stdAttrs; + %component_transfer_function_attributes; > + +<!ELEMENT feFuncA (animate|set)* > +<!ATTLIST feFuncA + %stdAttrs; + %component_transfer_function_attributes; > + +<!ELEMENT feComposite (animate|set)* > +<!ATTLIST feComposite + %stdAttrs; + %PresentationAttributes-FilterPrimitives; + %filter_primitive_attributes_with_in; + in2 CDATA #REQUIRED + operator (over | in | out | atop | xor | arithmetic) "over" + k1 %Number; #IMPLIED + k2 %Number; #IMPLIED + k3 %Number; #IMPLIED + k4 %Number; #IMPLIED > + +<!ELEMENT feConvolveMatrix (animate|set)* > +<!ATTLIST feConvolveMatrix + %stdAttrs; + %PresentationAttributes-FilterPrimitives; + %filter_primitive_attributes_with_in; + order %NumberOptionalNumber; #REQUIRED + kernelMatrix CDATA #REQUIRED + divisor %Number; #IMPLIED + bias %Number; #IMPLIED + targetX %Integer; #IMPLIED + targetY %Integer; #IMPLIED + edgeMode (duplicate|wrap|none) "duplicate" + kernelUnitLength %NumberOptionalNumber; #IMPLIED + preserveAlpha %Boolean; #IMPLIED > + +<!ELEMENT feDiffuseLighting ((feDistantLight|fePointLight|feSpotLight),(animate|set|animateColor)*) > +<!ATTLIST feDiffuseLighting + %stdAttrs; + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-FilterPrimitives; + %PresentationAttributes-LightingEffects; + %filter_primitive_attributes_with_in; + surfaceScale %Number; #IMPLIED + diffuseConstant %Number; #IMPLIED + kernelUnitLength %NumberOptionalNumber; #IMPLIED > + +<!ELEMENT feDisplacementMap (animate|set)* > +<!ATTLIST feDisplacementMap + %stdAttrs; + %PresentationAttributes-FilterPrimitives; + %filter_primitive_attributes_with_in; + in2 CDATA #REQUIRED + scale %Number; #IMPLIED + xChannelSelector (R | G | B | A) "A" + yChannelSelector (R | G | B | A) "A" > + +<!ELEMENT feFlood (animate|set|animateColor)* > +<!ATTLIST feFlood + %stdAttrs; + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-feFlood; + %PresentationAttributes-FilterPrimitives; + %filter_primitive_attributes_with_in; > + +<!ELEMENT feGaussianBlur (animate|set)* > +<!ATTLIST feGaussianBlur + %stdAttrs; + %PresentationAttributes-FilterPrimitives; + %filter_primitive_attributes_with_in; + stdDeviation %NumberOptionalNumber; #IMPLIED > + +<!ELEMENT feImage (animate|set|animateTransform)* > +<!ATTLIST feImage + %stdAttrs; + %xlinkRefAttrsEmbed; + xlink:href %URI; #REQUIRED + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-All; + %filter_primitive_attributes; + preserveAspectRatio %PreserveAspectRatioSpec; 'xMidYMid meet' > + +<!ELEMENT feMerge (feMergeNode)* > +<!ATTLIST feMerge + %stdAttrs; + %PresentationAttributes-FilterPrimitives; + %filter_primitive_attributes; > + +<!ELEMENT feMergeNode (animate|set)* > +<!ATTLIST feMergeNode + %stdAttrs; + in CDATA #IMPLIED > + +<!ELEMENT feMorphology (animate|set)* > +<!ATTLIST feMorphology + %stdAttrs; + %PresentationAttributes-FilterPrimitives; + %filter_primitive_attributes_with_in; + operator (erode | dilate) "erode" + radius %NumberOptionalNumber; #IMPLIED > + +<!ELEMENT feOffset (animate|set)* > +<!ATTLIST feOffset + %stdAttrs; + %PresentationAttributes-FilterPrimitives; + %filter_primitive_attributes_with_in; + dx %Number; #IMPLIED + dy %Number; #IMPLIED > + +<!ELEMENT feSpecularLighting ((feDistantLight|fePointLight|feSpotLight),(animate|set|animateColor)*) > +<!ATTLIST feSpecularLighting + %stdAttrs; + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-Color; + %PresentationAttributes-FilterPrimitives; + %PresentationAttributes-LightingEffects; + %filter_primitive_attributes_with_in; + surfaceScale %Number; #IMPLIED + specularConstant %Number; #IMPLIED + specularExponent %Number; #IMPLIED + kernelUnitLength %NumberOptionalNumber; #IMPLIED > + +<!ELEMENT feTile (animate|set)* > +<!ATTLIST feTile + %stdAttrs; + %PresentationAttributes-FilterPrimitives; + %filter_primitive_attributes_with_in; > + +<!ELEMENT feTurbulence (animate|set)* > +<!ATTLIST feTurbulence + %stdAttrs; + %PresentationAttributes-FilterPrimitives; + %filter_primitive_attributes; + baseFrequency %NumberOptionalNumber; #IMPLIED + numOctaves %Integer; #IMPLIED + seed %Number; #IMPLIED + stitchTiles (stitch | noStitch) "noStitch" + type (fractalNoise | turbulence) "turbulence" > + + +<!-- ============================================================== + DECLARATIONS CORRESPONDING TO: Interactivity + ============================================================== --> + +<!ELEMENT cursor (%descTitleMetadata;) > +<!ATTLIST cursor + %stdAttrs; + %xlinkRefAttrs; + xlink:href %URI; #REQUIRED + %testAttrs; + externalResourcesRequired %Boolean; #IMPLIED + x %Coordinate; #IMPLIED + y %Coordinate; #IMPLIED > + + +<!-- ============================================================== + DECLARATIONS CORRESPONDING TO: Linking + ============================================================== --> + +<!ENTITY % aExt "" > +<!ELEMENT a (#PCDATA|desc|title|metadata|defs| + path|text|rect|circle|ellipse|line|polyline|polygon| + use|image|svg|g|view|switch|a|altGlyphDef| + script|style|symbol|marker|clipPath|mask| + linearGradient|radialGradient|pattern|filter|cursor|font| + animate|set|animateMotion|animateColor|animateTransform| + color-profile|font-face + %ceExt;%aExt;)* > +<!ATTLIST a + %stdAttrs; + xmlns:xlink CDATA #FIXED "http://www.w3.org/1999/xlink" + xlink:type (simple) #FIXED "simple" + xlink:role %URI; #IMPLIED + xlink:arcrole %URI; #IMPLIED + xlink:title CDATA #IMPLIED + xlink:show (new|replace) 'replace' + xlink:actuate (onRequest) #FIXED 'onRequest' + xlink:href %URI; #REQUIRED + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-All; + transform %TransformList; #IMPLIED + %graphicsElementEvents; + target %LinkTarget; #IMPLIED > + +<!ENTITY % viewExt "" > +<!ELEMENT view (%descTitleMetadata;%viewExt;) > +<!ATTLIST view + %stdAttrs; + externalResourcesRequired %Boolean; #IMPLIED + viewBox %ViewBoxSpec; #IMPLIED + preserveAspectRatio %PreserveAspectRatioSpec; 'xMidYMid meet' + zoomAndPan (disable | magnify) 'magnify' + viewTarget CDATA #IMPLIED > + + +<!-- ============================================================== + DECLARATIONS CORRESPONDING TO: Scripting + ============================================================== --> + +<!ELEMENT script (#PCDATA) > +<!ATTLIST script + %stdAttrs; + %xlinkRefAttrs; + xlink:href %URI; #IMPLIED + externalResourcesRequired %Boolean; #IMPLIED + type %ContentType; #REQUIRED > + + +<!-- ============================================================== + DECLARATIONS CORRESPONDING TO: Animation + ============================================================== --> + +<!ENTITY % animElementAttrs + "%xlinkRefAttrs; + xlink:href %URI; #IMPLIED" > + +<!ENTITY % animAttributeAttrs + "attributeName CDATA #REQUIRED + attributeType CDATA #IMPLIED" > + +<!ENTITY % animTimingAttrs + "begin CDATA #IMPLIED + dur CDATA #IMPLIED + end CDATA #IMPLIED + min CDATA #IMPLIED + max CDATA #IMPLIED + restart (always | never | whenNotActive) 'always' + repeatCount CDATA #IMPLIED + repeatDur CDATA #IMPLIED + fill (remove | freeze) 'remove'" > + +<!ENTITY % animValueAttrs + "calcMode (discrete | linear | paced | spline) 'linear' + values CDATA #IMPLIED + keyTimes CDATA #IMPLIED + keySplines CDATA #IMPLIED + from CDATA #IMPLIED + to CDATA #IMPLIED + by CDATA #IMPLIED" > + +<!ENTITY % animAdditionAttrs + "additive (replace | sum) 'replace' + accumulate (none | sum) 'none'" > + +<!ENTITY % animateExt "" > +<!ELEMENT animate (%descTitleMetadata;%animateExt;) > +<!ATTLIST animate + %stdAttrs; + %testAttrs; + externalResourcesRequired %Boolean; #IMPLIED + %animationEvents; + %animElementAttrs; + %animAttributeAttrs; + %animTimingAttrs; + %animValueAttrs; + %animAdditionAttrs; > + +<!ENTITY % setExt "" > +<!ELEMENT set (%descTitleMetadata;%setExt;) > +<!ATTLIST set + %stdAttrs; + %testAttrs; + externalResourcesRequired %Boolean; #IMPLIED + %animationEvents; + %animElementAttrs; + %animAttributeAttrs; + %animTimingAttrs; + to CDATA #IMPLIED > + +<!ENTITY % animateMotionExt "" > +<!ELEMENT animateMotion (%descTitleMetadata;,mpath? %animateMotionExt;) > +<!ATTLIST animateMotion + %stdAttrs; + %testAttrs; + externalResourcesRequired %Boolean; #IMPLIED + %animationEvents; + %animElementAttrs; + %animTimingAttrs; + calcMode (discrete | linear | paced | spline) 'paced' + values CDATA #IMPLIED + keyTimes CDATA #IMPLIED + keySplines CDATA #IMPLIED + from CDATA #IMPLIED + to CDATA #IMPLIED + by CDATA #IMPLIED + %animAdditionAttrs; + path CDATA #IMPLIED + keyPoints CDATA #IMPLIED + rotate CDATA #IMPLIED + origin CDATA #IMPLIED > + +<!ENTITY % mpathExt "" > +<!ELEMENT mpath (%descTitleMetadata;%mpathExt;) > +<!ATTLIST mpath + %stdAttrs; + %xlinkRefAttrs; + xlink:href %URI; #REQUIRED + externalResourcesRequired %Boolean; #IMPLIED > + +<!ENTITY % animateColorExt "" > +<!ELEMENT animateColor (%descTitleMetadata;%animateColorExt;) > +<!ATTLIST animateColor + %stdAttrs; + %testAttrs; + externalResourcesRequired %Boolean; #IMPLIED + %animationEvents; + %animElementAttrs; + %animAttributeAttrs; + %animTimingAttrs; + %animValueAttrs; + %animAdditionAttrs; > + +<!ENTITY % animateTransformExt "" > +<!ELEMENT animateTransform (%descTitleMetadata;%animateTransformExt;) > +<!ATTLIST animateTransform + %stdAttrs; + %testAttrs; + externalResourcesRequired %Boolean; #IMPLIED + %animationEvents; + %animElementAttrs; + %animAttributeAttrs; + %animTimingAttrs; + %animValueAttrs; + %animAdditionAttrs; + type (translate | scale | rotate | skewX | skewY) "translate" > + + +<!-- ============================================================== + DECLARATIONS CORRESPONDING TO: Fonts + ============================================================== --> + +<!ENTITY % fontExt "" > +<!ELEMENT font (%descTitleMetadata;,font-face, + missing-glyph,(glyph|hkern|vkern %fontExt;)*) > +<!ATTLIST font + %stdAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-All; + horiz-origin-x %Number; #IMPLIED + horiz-origin-y %Number; #IMPLIED + horiz-adv-x %Number; #REQUIRED + vert-origin-x %Number; #IMPLIED + vert-origin-y %Number; #IMPLIED + vert-adv-y %Number; #IMPLIED > + +<!ENTITY % glyphExt "" > +<!ELEMENT glyph (desc|title|metadata|defs| + path|text|rect|circle|ellipse|line|polyline|polygon| + use|image|svg|g|view|switch|a|altGlyphDef| + script|style|symbol|marker|clipPath|mask| + linearGradient|radialGradient|pattern|filter|cursor|font| + animate|set|animateMotion|animateColor|animateTransform| + color-profile|font-face + %glyphExt;)* > +<!ATTLIST glyph + %stdAttrs; + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-All; + unicode CDATA #IMPLIED + glyph-name CDATA #IMPLIED + d %PathData; #IMPLIED + orientation CDATA #IMPLIED + arabic-form CDATA #IMPLIED + lang %LanguageCodes; #IMPLIED + horiz-adv-x %Number; #IMPLIED + vert-origin-x %Number; #IMPLIED + vert-origin-y %Number; #IMPLIED + vert-adv-y %Number; #IMPLIED > + +<!ENTITY % missing-glyphExt "" > +<!ELEMENT missing-glyph (desc|title|metadata|defs| + path|text|rect|circle|ellipse|line|polyline|polygon| + use|image|svg|g|view|switch|a|altGlyphDef| + script|style|symbol|marker|clipPath|mask| + linearGradient|radialGradient|pattern|filter|cursor|font| + animate|set|animateMotion|animateColor|animateTransform| + color-profile|font-face + %missing-glyphExt;)* > +<!ATTLIST missing-glyph + %stdAttrs; + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-All; + d %PathData; #IMPLIED + horiz-adv-x %Number; #IMPLIED + vert-origin-x %Number; #IMPLIED + vert-origin-y %Number; #IMPLIED + vert-adv-y %Number; #IMPLIED > + +<!ELEMENT hkern EMPTY > +<!ATTLIST hkern + %stdAttrs; + u1 CDATA #IMPLIED + g1 CDATA #IMPLIED + u2 CDATA #IMPLIED + g2 CDATA #IMPLIED + k %Number; #REQUIRED > + +<!ELEMENT vkern EMPTY > +<!ATTLIST vkern + %stdAttrs; + u1 CDATA #IMPLIED + g1 CDATA #IMPLIED + u2 CDATA #IMPLIED + g2 CDATA #IMPLIED + k %Number; #REQUIRED > + +<!ELEMENT font-face (%descTitleMetadata;,font-face-src?,definition-src?) > +<!ATTLIST font-face + %stdAttrs; + font-family CDATA #IMPLIED + font-style CDATA #IMPLIED + font-variant CDATA #IMPLIED + font-weight CDATA #IMPLIED + font-stretch CDATA #IMPLIED + font-size CDATA #IMPLIED + unicode-range CDATA #IMPLIED + units-per-em %Number; #IMPLIED + panose-1 CDATA #IMPLIED + stemv %Number; #IMPLIED + stemh %Number; #IMPLIED + slope %Number; #IMPLIED + cap-height %Number; #IMPLIED + x-height %Number; #IMPLIED + accent-height %Number; #IMPLIED + ascent %Number; #IMPLIED + descent %Number; #IMPLIED + widths CDATA #IMPLIED + bbox CDATA #IMPLIED + ideographic %Number; #IMPLIED + alphabetic %Number; #IMPLIED + mathematical %Number; #IMPLIED + hanging %Number; #IMPLIED + v-ideographic %Number; #IMPLIED + v-alphabetic %Number; #IMPLIED + v-mathematical %Number; #IMPLIED + v-hanging %Number; #IMPLIED + underline-position %Number; #IMPLIED + underline-thickness %Number; #IMPLIED + strikethrough-position %Number; #IMPLIED + strikethrough-thickness %Number; #IMPLIED + overline-position %Number; #IMPLIED + overline-thickness %Number; #IMPLIED > + +<!ELEMENT font-face-src (font-face-uri|font-face-name)+ > +<!ATTLIST font-face-src + %stdAttrs; > + +<!ELEMENT font-face-uri (font-face-format*) > +<!ATTLIST font-face-uri + %stdAttrs; + %xlinkRefAttrs; + xlink:href %URI; #REQUIRED > + +<!ELEMENT font-face-format EMPTY > +<!ATTLIST font-face-format + %stdAttrs; + string CDATA #IMPLIED > + +<!ELEMENT font-face-name EMPTY > +<!ATTLIST font-face-name + %stdAttrs; + name CDATA #IMPLIED > + +<!ELEMENT definition-src EMPTY > +<!ATTLIST definition-src + %stdAttrs; + %xlinkRefAttrs; + xlink:href %URI; #REQUIRED > + + +<!-- ============================================================== + DECLARATIONS CORRESPONDING TO: Metadata + ============================================================== --> + +<!ENTITY % metadataExt "" > +<!ELEMENT metadata (#PCDATA %metadataExt;)* > +<!ATTLIST metadata + %stdAttrs; > + + +<!-- ============================================================== + DECLARATIONS CORRESPONDING TO: Extensibility + ============================================================== --> + +<!ENTITY % foreignObjectExt "" > +<!ELEMENT foreignObject (#PCDATA %ceExt;%foreignObjectExt;)* > +<!ATTLIST foreignObject + %stdAttrs; + %testAttrs; + %langSpaceAttrs; + externalResourcesRequired %Boolean; #IMPLIED + class %ClassList; #IMPLIED + style %StyleSheet; #IMPLIED + %PresentationAttributes-All; + transform %TransformList; #IMPLIED + %graphicsElementEvents; + x %Coordinate; #IMPLIED + y %Coordinate; #IMPLIED + width %Length; #REQUIRED + height %Length; #REQUIRED + %StructuredText; > diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/blockdiagram/system.css b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/blockdiagram/system.css new file mode 100644 index 000000000..0d7b46bd6 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/blockdiagram/system.css @@ -0,0 +1,446 @@ + + text.bif_label { + fill: #000000; + stroke: none; + font-size: 6pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.debug_label { + fill: #555555; + stroke: none; + font-size: 8pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + font-family: Times Arial Helvetica sans-serif; + } + + text.ionum_label { + fill: #555555; + stroke: none; + font-size: 10pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.iogrp_label { + fill: #000088; + stroke: none; + font-size: 10pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + tspan.iogrp_label_super { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + baseline-shift:super; + font-family: Arial Courier san-serif; + } + + text.p2pbus_label { + fill: #000000; + stroke: none; + font-size: 10pt; + font-style: italic; + font-weight: bold; + text-anchor: start; + writing-mode: tb; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.multip_label { + fill: #000000; + stroke: none; + font-size: 6pt; + font-style: italic; + font-weight: bold; + text-anchor: start; + writing-mode: tb; + font-family: Verdana Arial Helvetica sans-serif; + } + + + + text.bc_iplabel { + fill: #000000; + stroke: none; + font-size: 6pt; + font-style: italic; + font-weight: bold; + text-anchor: middle; + font-family: Courier Arial Helvetica sans-serif; + } + + text.bc_iptype { + fill: #AA0017; + stroke: none; + font-size: 6pt; + font-style: italic; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.splitbus_label { + fill: #000000; + stroke: none; + font-size: 6pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: sans-serif; + } + + text.sharedbus_label { + fill: #000000; + stroke: none; + font-size: 10pt; + font-style: italic; + font-weight: bold; + text-anchor: start; + font-family: Verdana Arial Helvetica sans-serif; + } + + + text.p2pbus_label_horiz { + fill: #000000; + stroke: none; + font-size: 6pt; + font-style: italic; + font-weight: bold; + text-anchor: start; + font-family: Verdana Arial Helvetica sans-serif; + } + + + + text.key_title { + fill: #AA0017; + stroke: none; + font-size: 12pt; + font-weight: bold; + text-anchor: middle; + font-family: Arial Helvetica sans-serif; + } + + text.key_header { + fill: #000000; + stroke: none; + font-size: 10pt; + font-weight: bold; + text-anchor: middle; + font-family: Arial Helvetica sans-serif; + } + + text.key_label { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: start; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.key_label_ul { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: start; + text-decoration: underline; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.specs_header { + fill: #000000; + stroke: none; + font-size: 10pt; + font-weight: bold; + text-anchor: start; + font-family: Arial Helvetica sans-serif; + } + + text.specs_start { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: start; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.specs_middle { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.intr_symbol { + fill: #000000; + stroke: none; + font-size: 8pt; + font-weight: bold; + text-anchor: start; + font-family: Arial Helvetica sans-serif; + } + + text.busintlabel { + fill: #810017; + stroke: none; + font-size: 7pt; + font-style: italic; + font-weight: 900; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.mpmctitle { + fill: #FFFFFF; + stroke: none; + font-size: 16pt; + font-weight: bold; + text-anchor: middle; + font-family: Arial Verdana Helvetica sans-serif; + } + + text.mpmcbiflabel { + fill: #FFFFFF; + stroke: none; + font-size: 6pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + + } + + text.buslabel { + fill: #CC3333; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.iplabel { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: 800; + text-anchor: middle; + font-family: Courier Arial Helvetica sans-serif; + } + + text.iptype { + fill: #AA0017; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.ipclass { + fill: #000000; + stroke: none; + font-size: 7pt; + font-style: normal; + font-weight: bold; + text-anchor: start; + font-family: Times Arial Helvetica sans-serif; + } + + text.procclass { + fill: #000000; + stroke: none; + font-size: 7pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: Times Arial Helvetica sans-serif; + } + + + text.portlabel { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.ipdbiflbl { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: normal; + font-weight: bold; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.mmMHeader { + fill: #FFFFFF; + stroke: none; + font-size: 10pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.mmSHeader { + fill: #810017; + stroke: none; + font-size: 10pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.busintlabel { + fill: #810017; + stroke: none; + font-size: 7pt; + font-style: italic; + font-weight: 900; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.mpmctitle { + fill: #FFFFFF; + stroke: none; + font-size: 16pt; + font-weight: bold; + text-anchor: middle; + font-family: Arial Verdana Helvetica sans-serif; + } + + text.mpmcbiflabel { + fill: #FFFFFF; + stroke: none; + font-size: 6pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + + } + + text.buslabel { + fill: #CC3333; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.iplabel { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: 800; + text-anchor: middle; + font-family: Courier Arial Helvetica sans-serif; + } + + text.iptype { + fill: #AA0017; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.ipclass { + fill: #000000; + stroke: none; + font-size: 7pt; + font-style: normal; + font-weight: bold; + text-anchor: start; + font-family: Times Arial Helvetica sans-serif; + } + + text.procclass { + fill: #000000; + stroke: none; + font-size: 7pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: Times Arial Helvetica sans-serif; + } + + + text.portlabel { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.ipdbiflbl { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: normal; + font-weight: bold; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.mmMHeader { + fill: #FFFFFF; + stroke: none; + font-size: 10pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.mmSHeader { + fill: #810017; + stroke: none; + font-size: 10pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/blockdiagram/system.svg b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/blockdiagram/system.svg new file mode 100644 index 000000000..c7e3fcaec --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/blockdiagram/system.svg @@ -0,0 +1,1078 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.0//EN" "svg10.dtd"> +<?xml-stylesheet href="system.css" type="text/css"?> +<svg xmlns:svg="http://www.w3.org/2000/svg" xmlns:exsl="http://exslt.org/common" xmlns:xlink="http://www.w3.org/1999/xlink" width="1322" height="1833"> + <defs> + <g id="G_IOPort"> + <rect x="0" y="0" width="16" height="16" style="fill:#CCCCFF; stroke:#000088; stroke-width:1"/> + <path class="ioport" d="M 0,0 L 16,8 L 0,16 Z" style="stroke:none; fill:#0000BB"/> + </g> + <g id="G_BIPort"> + <rect x="0" y="0" width="16" height="16" style="fill:#CCCCFF; stroke:#000088; stroke-width:1"/> + <path class="btop" d="M 0,8 8,0 16,8 Z" style="stroke:none; fill:#0000BB"/> + <path class="bbot" d="M 0,8 8,16 16,8 Z" style="stroke:none; fill:#0000BB"/> + </g> + <g id="KEY_IOPort"> + <rect x="0" y="0" width="16" height="16" style="fill:#888888; stroke:none;"/> + <path class="ioport" d="M 0,0 L 16,8 L 0,16 Z" style="stroke:none; fill:#444444"/> + </g> + <g id="KEY_BIPort"> + <rect x="0" y="0" width="16" height="16" style="fill:#888888; stroke:none;"/> + <path class="btop" d="M 0,8 8,0 16,8 Z" style="stroke:none; fill:#444444"/> + <path class="bbot" d="M 0,8 8,16 16,8 Z" style="stroke:none; fill:#444444"/> + </g> + <g id="KEY_INPort"> + <use x="0" y="0" xlink:href="#KEY_IOPort"/> + <rect x="16" y="0" width="8" height="16" style="fill:#0000BB; stroke:none;"/> + </g> + <g id="KEY_OUTPort"> + <use x="0" y="0" xlink:href="#KEY_IOPort" transform="scale(-1,1) translate(-16,0)"/> + <rect x="16" y="0" width="8" height="16" style="fill:#0000BB; stroke:none;"/> + </g> + <g id="KEY_INOUTPort"> + <use x="0" y="0" xlink:href="#KEY_BIPort"/> + <rect x="16" y="0" width="8" height="16" style="fill:#0000BB; stroke:none;"/> + </g> + <g id="XIL_busconn_TARGET"> + <circle cx="12" cy="12" r="12" style="fill:#CC3399; stroke:#990066; stroke-width:1"/> + <circle cx="12.5" cy="12" r="7" style="fill:#990066; stroke:none;"/> + </g> + <g id="XIL_BifLabel"> + <rect x="0" y="0" rx="3" ry="3" width="32" height="16" style="fill:#990066; stroke:black; stroke-width:1"/> + </g> + <g id="XIL_busconn_INITIATOR"> + <rect x="0" y="0" width="24" height="24" style="fill:#CC3399; stroke:#990066; stroke-width:1"/> + <rect x="5.5" y="5" width="14" height="14" style="fill:#990066; stroke:none;"/> + </g> + <g id="XIL_BifLabel"> + <rect x="0" y="0" rx="3" ry="3" width="32" height="16" style="fill:#990066; stroke:black; stroke-width:1"/> + </g> + <g id="PLBV46_busconn_SLAVE"> + <circle cx="12" cy="12" r="12" style="fill:#FFFFDD; stroke:#BB9955; stroke-width:1"/> + <circle cx="12.5" cy="12" r="7" style="fill:#BB9955; stroke:none;"/> + </g> + <g id="PLBV46_BifLabel"> + <rect x="0" y="0" rx="3" ry="3" width="32" height="16" style="fill:#BB9955; stroke:black; stroke-width:1"/> + </g> + <g id="PLBV46_busconn_MASTER"> + <rect x="0" y="0" width="24" height="24" style="fill:#FFFFDD; stroke:#BB9955; stroke-width:1"/> + <rect x="5.5" y="5" width="14" height="14" style="fill:#BB9955; stroke:none;"/> + </g> + <g id="PLBV46_BifLabel"> + <rect x="0" y="0" rx="3" ry="3" width="32" height="16" style="fill:#BB9955; stroke:black; stroke-width:1"/> + </g> + <g id="PLBV46_P2P_busconn_SLAVE"> + <circle cx="12" cy="12" r="12" style="fill:#FFFFDD; stroke:#BB9955; stroke-width:1"/> + <circle cx="12.5" cy="12" r="7" style="fill:#BB9955; stroke:none;"/> + </g> + <g id="PLBV46_P2P_BifLabel"> + <rect x="0" y="0" rx="3" ry="3" width="32" height="16" style="fill:#BB9955; stroke:black; stroke-width:1"/> + </g> + <g id="PLBV46_P2P_busconn_MASTER"> + <rect x="0" y="0" width="24" height="24" style="fill:#FFFFDD; stroke:#BB9955; stroke-width:1"/> + <rect x="5.5" y="5" width="14" height="14" style="fill:#BB9955; stroke:none;"/> + </g> + <g id="PLBV46_P2P_BifLabel"> + <rect x="0" y="0" rx="3" ry="3" width="32" height="16" style="fill:#BB9955; stroke:black; stroke-width:1"/> + </g> + <g id="KEY_busconn_SLAVE"> + <circle cx="12" cy="12" r="12" style="fill:#888888; stroke:#444444; stroke-width:1"/> + <circle cx="12.5" cy="12" r="7" style="fill:#444444; stroke:none;"/> + </g> + <g id="KEY_BifLabel"> + <rect x="0" y="0" rx="3" ry="3" width="32" height="16" style="fill:#444444; stroke:black; stroke-width:1"/> + </g> + <g id="KEY_busconn_MASTER"> + <rect x="0" y="0" width="24" height="24" style="fill:#888888; stroke:#444444; stroke-width:1"/> + <rect x="5.5" y="5" width="14" height="14" style="fill:#444444; stroke:none;"/> + </g> + <g id="KEY_BifLabel"> + <rect x="0" y="0" rx="3" ry="3" width="32" height="16" style="fill:#444444; stroke:black; stroke-width:1"/> + </g> + <g id="KEY_busconn_MASTER_SLAVE"> + <circle cx="12" cy="12" r="12" style="fill:#888888; stroke:#444444; stroke-width:1"/> + <circle cx="12.5" cy="12" r="7" style="fill:#444444; stroke:none;"/> + <rect x="0" y="12" width="24" height="12" style="fill:#888888; stroke:#444444; stroke-width:1"/> + <rect x="5.5" y="12" width="14" height="7" style="fill:#444444; stroke:none;"/> + </g> + <g id="KEY_BifLabel"> + <rect x="0" y="0" rx="3" ry="3" width="32" height="16" style="fill:#444444; stroke:black; stroke-width:1"/> + </g> + <g id="KEY_busconn_TARGET"> + <circle cx="12" cy="12" r="12" style="fill:#888888; stroke:#444444; stroke-width:1"/> + <circle cx="12.5" cy="12" r="7" style="fill:#444444; stroke:none;"/> + </g> + <g id="KEY_BifLabel"> + <rect x="0" y="0" rx="3" ry="3" width="32" height="16" style="fill:#444444; stroke:black; stroke-width:1"/> + </g> + <g id="KEY_busconn_INITIATOR"> + <rect x="0" y="0" width="24" height="24" style="fill:#888888; stroke:#444444; stroke-width:1"/> + <rect x="5.5" y="5" width="14" height="14" style="fill:#444444; stroke:none;"/> + </g> + <g id="KEY_BifLabel"> + <rect x="0" y="0" rx="3" ry="3" width="32" height="16" style="fill:#444444; stroke:black; stroke-width:1"/> + </g> + <g id="KEY_busconn_MONITOR"> + <rect x="0" y="0.5" width="24" height="7" style="fill:#444444; stroke:none;"/> + <rect x="0" y="16" width="24" height="7" style="fill:#444444; stroke:none;"/> + </g> + <g id="KEY_BifLabel"> + <rect x="0" y="0" rx="3" ry="3" width="32" height="16" style="fill:#444444; stroke:black; stroke-width:1"/> + </g> + <g id="KEY_busconn_USER"> + <circle cx="12" cy="12" r="12" style="fill:#888888; stroke:#444444; stroke-width:1"/> + <circle cx="12.5" cy="12" r="7" style="fill:#444444; stroke:none;"/> + </g> + <g id="KEY_BifLabel"> + <rect x="0" y="0" rx="3" ry="3" width="32" height="16" style="fill:#444444; stroke:black; stroke-width:1"/> + </g> + <g id="XIL_BusArrowEast"> + <path class="bus" d="M 0,0 L 8, 6 L 0,12, Z" style="stroke:none; fill:#990066"/> + </g> + <g id="XIL_BusArrowWest"> + <use x="0" y="0" xlink:href="#XIL_BusArrowEast" transform="scale(-1,1) translate(-8,0)"/> + </g> + <g id="XIL_BusArrowHInitiator"> + <rect x="0" y="2" width="8" height="8" style="stroke:none; fill:#990066"/> + </g> + <g id="XIL_BusArrowSouth"> + <path class="bus" d="M 0,0 L 12,0 L 6, 8 Z" style="stroke:none; fill:#990066"/> + </g> + <g id="XIL_BusArrowNorth"> + <use x="0" y="0" xlink:href="#XIL_BusArrowSouth" transform="scale(1,-1) translate(0,-12)"/> + </g> + <g id="XIL_BusArrowInitiator"> + <rect x="2" y="0" width="4" height="12" style="stroke:none; fill:#990066"/> + </g> + <g id="XIL_SplitBus_EAST"> + <use x="0" y="0" xlink:href="#XIL_BusArrowWest"/> + <rect x="8" y="2" width="24" height="8" style="stroke:none; fill:#990066"/> + </g> + <g id="XIL_SplitBus_WEST"> + <use x="0" y="0" xlink:href="#XIL_SplitBus_EAST" transform="scale(-1,1) translate(-46,0)"/> + </g> + <g id="XIL_SplitBus_OneWay"> + <rect x="0" y="2" width="16" height="8" style="stroke:none; fill:#990066"/> + <rect x="16" y="0" width="12" height="12" style="stroke:none; fill:#990066"/> + </g> + <g id="OCM_BusArrowEast"> + <path class="bus" d="M 0,0 L 8, 6 L 0,12, Z" style="stroke:none; fill:#0000DD"/> + </g> + <g id="OCM_BusArrowWest"> + <use x="0" y="0" xlink:href="#OCM_BusArrowEast" transform="scale(-1,1) translate(-8,0)"/> + </g> + <g id="OCM_BusArrowHInitiator"> + <rect x="0" y="2" width="8" height="8" style="stroke:none; fill:#0000DD"/> + </g> + <g id="OCM_BusArrowSouth"> + <path class="bus" d="M 0,0 L 12,0 L 6, 8 Z" style="stroke:none; fill:#0000DD"/> + </g> + <g id="OCM_BusArrowNorth"> + <use x="0" y="0" xlink:href="#OCM_BusArrowSouth" transform="scale(1,-1) translate(0,-12)"/> + </g> + <g id="OCM_BusArrowInitiator"> + <rect x="2" y="0" width="4" height="12" style="stroke:none; fill:#0000DD"/> + </g> + <g id="OCM_SplitBus_EAST"> + <use x="0" y="0" xlink:href="#OCM_BusArrowWest"/> + <rect x="8" y="2" width="24" height="8" style="stroke:none; fill:#0000DD"/> + </g> + <g id="OCM_SplitBus_WEST"> + <use x="0" y="0" xlink:href="#OCM_SplitBus_EAST" transform="scale(-1,1) translate(-46,0)"/> + </g> + <g id="OCM_SplitBus_OneWay"> + <rect x="0" y="2" width="16" height="8" style="stroke:none; fill:#0000DD"/> + <rect x="16" y="0" width="12" height="12" style="stroke:none; fill:#0000DD"/> + </g> + <g id="OPB_BusArrowEast"> + <path class="bus" d="M 0,0 L 8, 6 L 0,12, Z" style="stroke:none; fill:#339900"/> + </g> + <g id="OPB_BusArrowWest"> + <use x="0" y="0" xlink:href="#OPB_BusArrowEast" transform="scale(-1,1) translate(-8,0)"/> + </g> + <g id="OPB_BusArrowHInitiator"> + <rect x="0" y="2" width="8" height="8" style="stroke:none; fill:#339900"/> + </g> + <g id="OPB_BusArrowSouth"> + <path class="bus" d="M 0,0 L 12,0 L 6, 8 Z" style="stroke:none; fill:#339900"/> + </g> + <g id="OPB_BusArrowNorth"> + <use x="0" y="0" xlink:href="#OPB_BusArrowSouth" transform="scale(1,-1) translate(0,-12)"/> + </g> + <g id="OPB_BusArrowInitiator"> + <rect x="2" y="0" width="4" height="12" style="stroke:none; fill:#339900"/> + </g> + <g id="OPB_SplitBus_EAST"> + <use x="0" y="0" xlink:href="#OPB_BusArrowWest"/> + <rect x="8" y="2" width="24" height="8" style="stroke:none; fill:#339900"/> + </g> + <g id="OPB_SplitBus_WEST"> + <use x="0" y="0" xlink:href="#OPB_SplitBus_EAST" transform="scale(-1,1) translate(-46,0)"/> + </g> + <g id="OPB_SplitBus_OneWay"> + <rect x="0" y="2" width="16" height="8" style="stroke:none; fill:#339900"/> + <rect x="16" y="0" width="12" height="12" style="stroke:none; fill:#339900"/> + </g> + <g id="LMB_BusArrowEast"> + <path class="bus" d="M 0,0 L 8, 6 L 0,12, Z" style="stroke:none; fill:#7777FF"/> + </g> + <g id="LMB_BusArrowWest"> + <use x="0" y="0" xlink:href="#LMB_BusArrowEast" transform="scale(-1,1) translate(-8,0)"/> + </g> + <g id="LMB_BusArrowHInitiator"> + <rect x="0" y="2" width="8" height="8" style="stroke:none; fill:#7777FF"/> + </g> + <g id="LMB_BusArrowSouth"> + <path class="bus" d="M 0,0 L 12,0 L 6, 8 Z" style="stroke:none; fill:#7777FF"/> + </g> + <g id="LMB_BusArrowNorth"> + <use x="0" y="0" xlink:href="#LMB_BusArrowSouth" transform="scale(1,-1) translate(0,-12)"/> + </g> + <g id="LMB_BusArrowInitiator"> + <rect x="2" y="0" width="4" height="12" style="stroke:none; fill:#7777FF"/> + </g> + <g id="LMB_SplitBus_EAST"> + <use x="0" y="0" xlink:href="#LMB_BusArrowWest"/> + <rect x="8" y="2" width="24" height="8" style="stroke:none; fill:#7777FF"/> + </g> + <g id="LMB_SplitBus_WEST"> + <use x="0" y="0" xlink:href="#LMB_SplitBus_EAST" transform="scale(-1,1) translate(-46,0)"/> + </g> + <g id="LMB_SplitBus_OneWay"> + <rect x="0" y="2" width="16" height="8" style="stroke:none; fill:#7777FF"/> + <rect x="16" y="0" width="12" height="12" style="stroke:none; fill:#7777FF"/> + </g> + <g id="FSL_BusArrowEast"> + <path class="bus" d="M 0,0 L 8, 6 L 0,12, Z" style="stroke:none; fill:#CC00CC"/> + </g> + <g id="FSL_BusArrowWest"> + <use x="0" y="0" xlink:href="#FSL_BusArrowEast" transform="scale(-1,1) translate(-8,0)"/> + </g> + <g id="FSL_BusArrowHInitiator"> + <rect x="0" y="2" width="8" height="8" style="stroke:none; fill:#CC00CC"/> + </g> + <g id="FSL_BusArrowSouth"> + <path class="bus" d="M 0,0 L 12,0 L 6, 8 Z" style="stroke:none; fill:#CC00CC"/> + </g> + <g id="FSL_BusArrowNorth"> + <use x="0" y="0" xlink:href="#FSL_BusArrowSouth" transform="scale(1,-1) translate(0,-12)"/> + </g> + <g id="FSL_BusArrowInitiator"> + <rect x="2" y="0" width="4" height="12" style="stroke:none; fill:#CC00CC"/> + </g> + <g id="FSL_SplitBus_EAST"> + <use x="0" y="0" xlink:href="#FSL_BusArrowWest"/> + <rect x="8" y="2" width="24" height="8" style="stroke:none; fill:#CC00CC"/> + </g> + <g id="FSL_SplitBus_WEST"> + <use x="0" y="0" xlink:href="#FSL_SplitBus_EAST" transform="scale(-1,1) translate(-46,0)"/> + </g> + <g id="FSL_SplitBus_OneWay"> + <rect x="0" y="2" width="16" height="8" style="stroke:none; fill:#CC00CC"/> + <rect x="16" y="0" width="12" height="12" style="stroke:none; fill:#CC00CC"/> + </g> + <g id="DCR_BusArrowEast"> + <path class="bus" d="M 0,0 L 8, 6 L 0,12, Z" style="stroke:none; fill:#6699FF"/> + </g> + <g id="DCR_BusArrowWest"> + <use x="0" y="0" xlink:href="#DCR_BusArrowEast" transform="scale(-1,1) translate(-8,0)"/> + </g> + <g id="DCR_BusArrowHInitiator"> + <rect x="0" y="2" width="8" height="8" style="stroke:none; fill:#6699FF"/> + </g> + <g id="DCR_BusArrowSouth"> + <path class="bus" d="M 0,0 L 12,0 L 6, 8 Z" style="stroke:none; fill:#6699FF"/> + </g> + <g id="DCR_BusArrowNorth"> + <use x="0" y="0" xlink:href="#DCR_BusArrowSouth" transform="scale(1,-1) translate(0,-12)"/> + </g> + <g id="DCR_BusArrowInitiator"> + <rect x="2" y="0" width="4" height="12" style="stroke:none; fill:#6699FF"/> + </g> + <g id="DCR_SplitBus_EAST"> + <use x="0" y="0" xlink:href="#DCR_BusArrowWest"/> + <rect x="8" y="2" width="24" height="8" style="stroke:none; fill:#6699FF"/> + </g> + <g id="DCR_SplitBus_WEST"> + <use x="0" y="0" xlink:href="#DCR_SplitBus_EAST" transform="scale(-1,1) translate(-46,0)"/> + </g> + <g id="DCR_SplitBus_OneWay"> + <rect x="0" y="2" width="16" height="8" style="stroke:none; fill:#6699FF"/> + <rect x="16" y="0" width="12" height="12" style="stroke:none; fill:#6699FF"/> + </g> + <g id="FCB_BusArrowEast"> + <path class="bus" d="M 0,0 L 8, 6 L 0,12, Z" style="stroke:none; fill:#8C00FF"/> + </g> + <g id="FCB_BusArrowWest"> + <use x="0" y="0" xlink:href="#FCB_BusArrowEast" transform="scale(-1,1) translate(-8,0)"/> + </g> + <g id="FCB_BusArrowHInitiator"> + <rect x="0" y="2" width="8" height="8" style="stroke:none; fill:#8C00FF"/> + </g> + <g id="FCB_BusArrowSouth"> + <path class="bus" d="M 0,0 L 12,0 L 6, 8 Z" style="stroke:none; fill:#8C00FF"/> + </g> + <g id="FCB_BusArrowNorth"> + <use x="0" y="0" xlink:href="#FCB_BusArrowSouth" transform="scale(1,-1) translate(0,-12)"/> + </g> + <g id="FCB_BusArrowInitiator"> + <rect x="2" y="0" width="4" height="12" style="stroke:none; fill:#8C00FF"/> + </g> + <g id="FCB_SplitBus_EAST"> + <use x="0" y="0" xlink:href="#FCB_BusArrowWest"/> + <rect x="8" y="2" width="24" height="8" style="stroke:none; fill:#8C00FF"/> + </g> + <g id="FCB_SplitBus_WEST"> + <use x="0" y="0" xlink:href="#FCB_SplitBus_EAST" transform="scale(-1,1) translate(-46,0)"/> + </g> + <g id="FCB_SplitBus_OneWay"> + <rect x="0" y="2" width="16" height="8" style="stroke:none; fill:#8C00FF"/> + <rect x="16" y="0" width="12" height="12" style="stroke:none; fill:#8C00FF"/> + </g> + <g id="PLB_BusArrowEast"> + <path class="bus" d="M 0,0 L 8, 6 L 0,12, Z" style="stroke:none; fill:#FF5500"/> + </g> + <g id="PLB_BusArrowWest"> + <use x="0" y="0" xlink:href="#PLB_BusArrowEast" transform="scale(-1,1) translate(-8,0)"/> + </g> + <g id="PLB_BusArrowHInitiator"> + <rect x="0" y="2" width="8" height="8" style="stroke:none; fill:#FF5500"/> + </g> + <g id="PLB_BusArrowSouth"> + <path class="bus" d="M 0,0 L 12,0 L 6, 8 Z" style="stroke:none; fill:#FF5500"/> + </g> + <g id="PLB_BusArrowNorth"> + <use x="0" y="0" xlink:href="#PLB_BusArrowSouth" transform="scale(1,-1) translate(0,-12)"/> + </g> + <g id="PLB_BusArrowInitiator"> + <rect x="2" y="0" width="4" height="12" style="stroke:none; fill:#FF5500"/> + </g> + <g id="PLB_SplitBus_EAST"> + <use x="0" y="0" xlink:href="#PLB_BusArrowWest"/> + <rect x="8" y="2" width="24" height="8" style="stroke:none; fill:#FF5500"/> + </g> + <g id="PLB_SplitBus_WEST"> + <use x="0" y="0" xlink:href="#PLB_SplitBus_EAST" transform="scale(-1,1) translate(-46,0)"/> + </g> + <g id="PLB_SplitBus_OneWay"> + <rect x="0" y="2" width="16" height="8" style="stroke:none; fill:#FF5500"/> + <rect x="16" y="0" width="12" height="12" style="stroke:none; fill:#FF5500"/> + </g> + <g id="PLBV46_BusArrowEast"> + <path class="bus" d="M 0,0 L 8, 6 L 0,12, Z" style="stroke:none; fill:#BB9955"/> + </g> + <g id="PLBV46_BusArrowWest"> + <use x="0" y="0" xlink:href="#PLBV46_BusArrowEast" transform="scale(-1,1) translate(-8,0)"/> + </g> + <g id="PLBV46_BusArrowHInitiator"> + <rect x="0" y="2" width="8" height="8" style="stroke:none; fill:#BB9955"/> + </g> + <g id="PLBV46_BusArrowSouth"> + <path class="bus" d="M 0,0 L 12,0 L 6, 8 Z" style="stroke:none; fill:#BB9955"/> + </g> + <g id="PLBV46_BusArrowNorth"> + <use x="0" y="0" xlink:href="#PLBV46_BusArrowSouth" transform="scale(1,-1) translate(0,-12)"/> + </g> + <g id="PLBV46_BusArrowInitiator"> + <rect x="2" y="0" width="4" height="12" style="stroke:none; fill:#BB9955"/> + </g> + <g id="PLBV46_SplitBus_EAST"> + <use x="0" y="0" xlink:href="#PLBV46_BusArrowWest"/> + <rect x="8" y="2" width="24" height="8" style="stroke:none; fill:#BB9955"/> + </g> + <g id="PLBV46_SplitBus_WEST"> + <use x="0" y="0" xlink:href="#PLBV46_SplitBus_EAST" transform="scale(-1,1) translate(-46,0)"/> + </g> + <g id="PLBV46_SplitBus_OneWay"> + <rect x="0" y="2" width="16" height="8" style="stroke:none; fill:#BB9955"/> + <rect x="16" y="0" width="12" height="12" style="stroke:none; fill:#BB9955"/> + </g> + <g id="PLBV46_P2P_BusArrowEast"> + <path class="bus" d="M 0,0 L 8, 6 L 0,12, Z" style="stroke:none; fill:#BB9955"/> + </g> + <g id="PLBV46_P2P_BusArrowWest"> + <use x="0" y="0" xlink:href="#PLBV46_P2P_BusArrowEast" transform="scale(-1,1) translate(-8,0)"/> + </g> + <g id="PLBV46_P2P_BusArrowHInitiator"> + <rect x="0" y="2" width="8" height="8" style="stroke:none; fill:#BB9955"/> + </g> + <g id="PLBV46_P2P_BusArrowSouth"> + <path class="bus" d="M 0,0 L 12,0 L 6, 8 Z" style="stroke:none; fill:#BB9955"/> + </g> + <g id="PLBV46_P2P_BusArrowNorth"> + <use x="0" y="0" xlink:href="#PLBV46_P2P_BusArrowSouth" transform="scale(1,-1) translate(0,-12)"/> + </g> + <g id="PLBV46_P2P_BusArrowInitiator"> + <rect x="2" y="0" width="4" height="12" style="stroke:none; fill:#BB9955"/> + </g> + <g id="PLBV46_P2P_SplitBus_EAST"> + <use x="0" y="0" xlink:href="#PLBV46_P2P_BusArrowWest"/> + <rect x="8" y="2" width="24" height="8" style="stroke:none; fill:#BB9955"/> + </g> + <g id="PLBV46_P2P_SplitBus_WEST"> + <use x="0" y="0" xlink:href="#PLBV46_P2P_SplitBus_EAST" transform="scale(-1,1) translate(-46,0)"/> + </g> + <g id="PLBV46_P2P_SplitBus_OneWay"> + <rect x="0" y="2" width="16" height="8" style="stroke:none; fill:#BB9955"/> + <rect x="16" y="0" width="12" height="12" style="stroke:none; fill:#BB9955"/> + </g> + <g id="TARGET_BusArrowEast"> + <path class="bus" d="M 0,0 L 8, 6 L 0,12, Z" style="stroke:none; fill:#009999"/> + </g> + <g id="TARGET_BusArrowWest"> + <use x="0" y="0" xlink:href="#TARGET_BusArrowEast" transform="scale(-1,1) translate(-8,0)"/> + </g> + <g id="TARGET_BusArrowHInitiator"> + <rect x="0" y="2" width="8" height="8" style="stroke:none; fill:#009999"/> + </g> + <g id="TARGET_BusArrowSouth"> + <path class="bus" d="M 0,0 L 12,0 L 6, 8 Z" style="stroke:none; fill:#009999"/> + </g> + <g id="TARGET_BusArrowNorth"> + <use x="0" y="0" xlink:href="#TARGET_BusArrowSouth" transform="scale(1,-1) translate(0,-12)"/> + </g> + <g id="TARGET_BusArrowInitiator"> + <rect x="2" y="0" width="4" height="12" style="stroke:none; fill:#009999"/> + </g> + <g id="TARGET_SplitBus_EAST"> + <use x="0" y="0" xlink:href="#TARGET_BusArrowWest"/> + <rect x="8" y="2" width="24" height="8" style="stroke:none; fill:#009999"/> + </g> + <g id="TARGET_SplitBus_WEST"> + <use x="0" y="0" xlink:href="#TARGET_SplitBus_EAST" transform="scale(-1,1) translate(-46,0)"/> + </g> + <g id="TARGET_SplitBus_OneWay"> + <rect x="0" y="2" width="16" height="8" style="stroke:none; fill:#009999"/> + <rect x="16" y="0" width="12" height="12" style="stroke:none; fill:#009999"/> + </g> + <g id="INITIATOR_BusArrowEast"> + <path class="bus" d="M 0,0 L 8, 6 L 0,12, Z" style="stroke:none; fill:#009999"/> + </g> + <g id="INITIATOR_BusArrowWest"> + <use x="0" y="0" xlink:href="#INITIATOR_BusArrowEast" transform="scale(-1,1) translate(-8,0)"/> + </g> + <g id="INITIATOR_BusArrowHInitiator"> + <rect x="0" y="2" width="8" height="8" style="stroke:none; fill:#009999"/> + </g> + <g id="INITIATOR_BusArrowSouth"> + <path class="bus" d="M 0,0 L 12,0 L 6, 8 Z" style="stroke:none; fill:#009999"/> + </g> + <g id="INITIATOR_BusArrowNorth"> + <use x="0" y="0" xlink:href="#INITIATOR_BusArrowSouth" transform="scale(1,-1) translate(0,-12)"/> + </g> + <g id="INITIATOR_BusArrowInitiator"> + <rect x="2" y="0" width="4" height="12" style="stroke:none; fill:#009999"/> + </g> + <g id="INITIATOR_SplitBus_EAST"> + <use x="0" y="0" xlink:href="#INITIATOR_BusArrowWest"/> + <rect x="8" y="2" width="24" height="8" style="stroke:none; fill:#009999"/> + </g> + <g id="INITIATOR_SplitBus_WEST"> + <use x="0" y="0" xlink:href="#INITIATOR_SplitBus_EAST" transform="scale(-1,1) translate(-46,0)"/> + </g> + <g id="INITIATOR_SplitBus_OneWay"> + <rect x="0" y="2" width="16" height="8" style="stroke:none; fill:#009999"/> + <rect x="16" y="0" width="12" height="12" style="stroke:none; fill:#009999"/> + </g> + <g id="USER_BusArrowEast"> + <path class="bus" d="M 0,0 L 8, 6 L 0,12, Z" style="stroke:none; fill:#009999"/> + </g> + <g id="USER_BusArrowWest"> + <use x="0" y="0" xlink:href="#USER_BusArrowEast" transform="scale(-1,1) translate(-8,0)"/> + </g> + <g id="USER_BusArrowHInitiator"> + <rect x="0" y="2" width="8" height="8" style="stroke:none; fill:#009999"/> + </g> + <g id="USER_BusArrowSouth"> + <path class="bus" d="M 0,0 L 12,0 L 6, 8 Z" style="stroke:none; fill:#009999"/> + </g> + <g id="USER_BusArrowNorth"> + <use x="0" y="0" xlink:href="#USER_BusArrowSouth" transform="scale(1,-1) translate(0,-12)"/> + </g> + <g id="USER_BusArrowInitiator"> + <rect x="2" y="0" width="4" height="12" style="stroke:none; fill:#009999"/> + </g> + <g id="USER_SplitBus_EAST"> + <use x="0" y="0" xlink:href="#USER_BusArrowWest"/> + <rect x="8" y="2" width="24" height="8" style="stroke:none; fill:#009999"/> + </g> + <g id="USER_SplitBus_WEST"> + <use x="0" y="0" xlink:href="#USER_SplitBus_EAST" transform="scale(-1,1) translate(-46,0)"/> + </g> + <g id="USER_SplitBus_OneWay"> + <rect x="0" y="2" width="16" height="8" style="stroke:none; fill:#009999"/> + <rect x="16" y="0" width="12" height="12" style="stroke:none; fill:#009999"/> + </g> + <g id="KEY_BusArrowEast"> + <path class="bus" d="M 0,0 L 8, 6 L 0,12, Z" style="stroke:none; fill:#444444"/> + </g> + <g id="KEY_BusArrowWest"> + <use x="0" y="0" xlink:href="#KEY_BusArrowEast" transform="scale(-1,1) translate(-8,0)"/> + </g> + <g id="KEY_BusArrowHInitiator"> + <rect x="0" y="2" width="8" height="8" style="stroke:none; fill:#444444"/> + </g> + <g id="KEY_BusArrowSouth"> + <path class="bus" d="M 0,0 L 12,0 L 6, 8 Z" style="stroke:none; fill:#444444"/> + </g> + <g id="KEY_BusArrowNorth"> + <use x="0" y="0" xlink:href="#KEY_BusArrowSouth" transform="scale(1,-1) translate(0,-12)"/> + </g> + <g id="KEY_BusArrowInitiator"> + <rect x="2" y="0" width="4" height="12" style="stroke:none; fill:#444444"/> + </g> + <g id="KEY_SplitBus_EAST"> + <use x="0" y="0" xlink:href="#KEY_BusArrowWest"/> + <rect x="8" y="2" width="24" height="8" style="stroke:none; fill:#444444"/> + </g> + <g id="KEY_SplitBus_WEST"> + <use x="0" y="0" xlink:href="#KEY_SplitBus_EAST" transform="scale(-1,1) translate(-46,0)"/> + </g> + <g id="KEY_SplitBus_OneWay"> + <rect x="0" y="2" width="16" height="8" style="stroke:none; fill:#444444"/> + <rect x="16" y="0" width="12" height="12" style="stroke:none; fill:#444444"/> + </g> + <g id="PLB_SharedBus"> + <use x="0" y="0" xlink:href="#PLB_BusArrowWest"/> + <use x="1096" y="0" xlink:href="#PLB_BusArrowEast"/> + <rect x="8" y="2" width="1088" height="8" style="stroke:none; fill:#FF5500"/> + </g> + <g id="PLBV46_SharedBus"> + <use x="0" y="0" xlink:href="#PLBV46_BusArrowWest"/> + <use x="1096" y="0" xlink:href="#PLBV46_BusArrowEast"/> + <rect x="8" y="2" width="1088" height="8" style="stroke:none; fill:#BB9955"/> + </g> + <g id="OPB_SharedBus"> + <use x="0" y="0" xlink:href="#OPB_BusArrowWest"/> + <use x="1096" y="0" xlink:href="#OPB_BusArrowEast"/> + <rect x="8" y="2" width="1088" height="8" style="stroke:none; fill:#339900"/> + </g> + <g id="group_sharedBusses"> + <use x="0" y="0" xlink:href="#PLBV46_SharedBus"/> + <text x="8" y="22" fill="#000000" stroke="none" font-size="12pt" font-style="italic" font-weight="900" text-anchor="start" font-family="Verdana Courier Arial Helvetica san-serif">plb_v46_0</text> + </g> + <g id="KEY_SharedBus"> + <use x="0" y="0" xlink:href="#KEY_BusArrowWest"/> + <use x="30" y="0" xlink:href="#KEY_BusArrowEast"/> + <rect x="8" y="2" width="22" height="8" style="stroke:none; fill:#444444"/> + </g> + <g id="sbsbktmodule_Ethernet_MAC"> + <rect x="0" y="24" rx="6" ry="6" width="90" height="74" style="fill:#CCCCCC; stroke:#FFFFFF; stroke-width:2"/> + <rect x="11" y="56" rx="3" ry="3" width="68" height="38" style="fill:#FFFFFF; stroke:none;"/> + <text x="45" y="64" fill="#AA0017" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Arial Helvetica san-serif">xps_ethernetlite</text> + <text x="45" y="74" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Courier Arial Helvetica san-serif">Ethernet_MAC</text> + <use x="29" y="28" xlink:href="#PLBV46_BifLabel"/> + <use x="33" y="0" xlink:href="#PLBV46_busconn_SLAVE"/> + <text x="45" y="39" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Courier Arial Helvetica san-serif">SPLB</text> + </g> + <g id="sbsbktmodule_LEDs_8Bit"> + <rect x="0" y="24" rx="6" ry="6" width="90" height="74" style="fill:#CCCCCC; stroke:#FFFFFF; stroke-width:2"/> + <rect x="11" y="56" rx="3" ry="3" width="68" height="38" style="fill:#FFFFFF; stroke:none;"/> + <text x="45" y="64" fill="#AA0017" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Arial Helvetica san-serif">xps_gpio</text> + <text x="45" y="74" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Courier Arial Helvetica san-serif">LEDs_8Bit</text> + <use x="29" y="28" xlink:href="#PLBV46_BifLabel"/> + <use x="33" y="0" xlink:href="#PLBV46_busconn_SLAVE"/> + <text x="45" y="39" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Courier Arial Helvetica san-serif">SPLB</text> + </g> + <g id="sbsbktmodule_LEDs_Positions"> + <rect x="0" y="24" rx="6" ry="6" width="90" height="74" style="fill:#CCCCCC; stroke:#FFFFFF; stroke-width:2"/> + <rect x="11" y="56" rx="3" ry="3" width="68" height="38" style="fill:#FFFFFF; stroke:none;"/> + <text x="45" y="64" fill="#AA0017" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Arial Helvetica san-serif">xps_gpio</text> + <text x="45" y="74" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Courier Arial Helvetica san-serif">LEDs_Positions</text> + <use x="29" y="28" xlink:href="#PLBV46_BifLabel"/> + <use x="33" y="0" xlink:href="#PLBV46_busconn_SLAVE"/> + <text x="45" y="39" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Courier Arial Helvetica san-serif">SPLB</text> + </g> + <g id="sbsbktmodule_Push_Buttons_5Bit"> + <rect x="0" y="24" rx="6" ry="6" width="90" height="74" style="fill:#CCCCCC; stroke:#FFFFFF; stroke-width:2"/> + <rect x="11" y="56" rx="3" ry="3" width="68" height="38" style="fill:#FFFFFF; stroke:none;"/> + <text x="45" y="64" fill="#AA0017" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Arial Helvetica san-serif">xps_gpio</text> + <text x="45" y="74" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Courier Arial Helvetica san-serif">Push_Buttons_5Bit</text> + <use x="29" y="28" xlink:href="#PLBV46_BifLabel"/> + <use x="33" y="0" xlink:href="#PLBV46_busconn_SLAVE"/> + <text x="45" y="39" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Courier Arial Helvetica san-serif">SPLB</text> + </g> + <g id="sbsbktmodule_DIP_Switches_8Bit"> + <rect x="0" y="24" rx="6" ry="6" width="90" height="74" style="fill:#CCCCCC; stroke:#FFFFFF; stroke-width:2"/> + <rect x="11" y="56" rx="3" ry="3" width="68" height="38" style="fill:#FFFFFF; stroke:none;"/> + <text x="45" y="64" fill="#AA0017" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Arial Helvetica san-serif">xps_gpio</text> + <text x="45" y="74" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Courier Arial Helvetica san-serif">DIP_Switches_8Bit</text> + <use x="29" y="28" xlink:href="#PLBV46_BifLabel"/> + <use x="33" y="0" xlink:href="#PLBV46_busconn_SLAVE"/> + <text x="45" y="39" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Courier Arial Helvetica san-serif">SPLB</text> + </g> + <g id="sbsbktmodule_IIC_EEPROM"> + <rect x="0" y="24" rx="6" ry="6" width="90" height="74" style="fill:#CCCCCC; stroke:#FFFFFF; stroke-width:2"/> + <rect x="11" y="56" rx="3" ry="3" width="68" height="38" style="fill:#FFFFFF; stroke:none;"/> + <text x="45" y="64" fill="#AA0017" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Arial Helvetica san-serif">xps_iic</text> + <text x="45" y="74" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Courier Arial Helvetica san-serif">IIC_EEPROM</text> + <use x="29" y="28" xlink:href="#PLBV46_BifLabel"/> + <use x="33" y="0" xlink:href="#PLBV46_busconn_SLAVE"/> + <text x="45" y="39" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Courier Arial Helvetica san-serif">SPLB</text> + </g> + <g id="sbsbktmodule_xps_intc_0"> + <rect x="0" y="24" rx="6" ry="6" width="90" height="74" style="fill:#CCCCCC; stroke:#FFFFFF; stroke-width:2"/> + <rect x="11" y="56" rx="3" ry="3" width="68" height="38" style="fill:#FFFFFF; stroke:none;"/> + <text x="45" y="64" fill="#AA0017" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Arial Helvetica san-serif">xps_intc</text> + <text x="45" y="74" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Courier Arial Helvetica san-serif">xps_intc_0</text> + <use x="29" y="28" xlink:href="#PLBV46_BifLabel"/> + <use x="33" y="0" xlink:href="#PLBV46_busconn_SLAVE"/> + <text x="45" y="39" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Courier Arial Helvetica san-serif">SPLB</text> + <rect x="81" y="27" rx="3" ry="3" width="9" height="18" style="fill:#FF9900; stroke:none; stroke-width:1"/> + <line x1="81" y1="32" x2="90" y2="32" style="stroke:#000000;stroke-width:2"/> + <text x="83" y="44" fill="#000000" stroke="none" font-size="10pt" font-weight="900" text-anchor="start" font-family="Arial Helvetica san-serif">0</text> + </g> + <g id="sbsbktmodule_SRAM"> + <rect x="0" y="24" rx="6" ry="6" width="90" height="74" style="fill:#CCCCCC; stroke:#FFFFFF; stroke-width:2"/> + <rect x="11" y="56" rx="3" ry="3" width="68" height="38" style="fill:#FFFFFF; stroke:none;"/> + <text x="45" y="64" fill="#AA0017" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Arial Helvetica san-serif">xps_mch_emc</text> + <text x="45" y="74" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Courier Arial Helvetica san-serif">SRAM</text> + <use x="29" y="28" xlink:href="#PLBV46_BifLabel"/> + <use x="33" y="0" xlink:href="#PLBV46_busconn_SLAVE"/> + <text x="45" y="39" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Courier Arial Helvetica san-serif">SPLB</text> + </g> + <g id="sbsbktmodule_SysACE_CompactFlash"> + <rect x="0" y="24" rx="6" ry="6" width="90" height="74" style="fill:#CCCCCC; stroke:#FFFFFF; stroke-width:2"/> + <rect x="11" y="56" rx="3" ry="3" width="68" height="38" style="fill:#FFFFFF; stroke:none;"/> + <text x="45" y="64" fill="#AA0017" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Arial Helvetica san-serif">xps_sysace</text> + <text x="45" y="74" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Courier Arial Helvetica san-serif">SysACE_CompactFlash</text> + <use x="29" y="28" xlink:href="#PLBV46_BifLabel"/> + <use x="33" y="0" xlink:href="#PLBV46_busconn_SLAVE"/> + <text x="45" y="39" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Courier Arial Helvetica san-serif">SPLB</text> + </g> + <g id="sbsbktmodule_RS232_Uart_1"> + <rect x="0" y="24" rx="6" ry="6" width="90" height="74" style="fill:#CCCCCC; stroke:#FFFFFF; stroke-width:2"/> + <rect x="11" y="56" rx="3" ry="3" width="68" height="38" style="fill:#FFFFFF; stroke:none;"/> + <text x="45" y="64" fill="#AA0017" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Arial Helvetica san-serif">xps_uartlite</text> + <text x="45" y="74" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Courier Arial Helvetica san-serif">RS232_Uart_1</text> + <use x="29" y="28" xlink:href="#PLBV46_BifLabel"/> + <use x="33" y="0" xlink:href="#PLBV46_busconn_SLAVE"/> + <text x="45" y="39" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Courier Arial Helvetica san-serif">SPLB</text> + <rect x="72" y="24" rx="3" ry="3" width="18" height="9" style="fill:#FF9900; stroke:none; stroke-width:1"/> + <line x1="81" y1="24" x2="81" y2="33" style="stroke:#000000;stroke-width:1"/> + <text x="74" y="32" fill="#000000" stroke="none" font-size="10pt" font-weight="900" text-anchor="start" font-family="Arial Helvetica san-serif">1</text> + <text x="83" y="32" fill="#000000" stroke="none" font-size="10pt" font-weight="900" text-anchor="start" font-family="Arial Helvetica san-serif">0</text> + </g> + <g id="sbsbucket_plb_v46_0"> + <rect x="0" y="0" rx="4" ry="4" width="334" height="472" style="stroke-width:2; stroke:#BB9955; fill:#FFFFDD"/> + <use x="16" y="16" xlink:href="#sbsbktmodule_Ethernet_MAC"/> + <rect x="0" y="24" width="61" height="8" style="fill:#BB9955"/> + <use x="122" y="16" xlink:href="#sbsbktmodule_LEDs_8Bit"/> + <rect x="61" y="24" width="106" height="8" style="fill:#BB9955"/> + <use x="228" y="16" xlink:href="#sbsbktmodule_LEDs_Positions"/> + <rect x="167" y="24" width="106" height="8" style="fill:#BB9955"/> + <use x="16" y="130" xlink:href="#sbsbktmodule_Push_Buttons_5Bit"/> + <rect x="0" y="138" width="61" height="8" style="fill:#BB9955"/> + <use x="122" y="130" xlink:href="#sbsbktmodule_DIP_Switches_8Bit"/> + <rect x="61" y="138" width="106" height="8" style="fill:#BB9955"/> + <use x="228" y="130" xlink:href="#sbsbktmodule_IIC_EEPROM"/> + <rect x="167" y="138" width="106" height="8" style="fill:#BB9955"/> + <use x="16" y="244" xlink:href="#sbsbktmodule_xps_intc_0"/> + <rect x="0" y="252" width="61" height="8" style="fill:#BB9955"/> + <use x="122" y="244" xlink:href="#sbsbktmodule_SRAM"/> + <rect x="61" y="252" width="106" height="8" style="fill:#BB9955"/> + <use x="228" y="244" xlink:href="#sbsbktmodule_SysACE_CompactFlash"/> + <rect x="167" y="252" width="106" height="8" style="fill:#BB9955"/> + <use x="16" y="358" xlink:href="#sbsbktmodule_RS232_Uart_1"/> + <rect x="0" y="366" width="61" height="8" style="fill:#BB9955"/> + <rect x="0" y="24" width="8" height="342" style="fill:#BB9955"/> + </g> + <g id="ipbktmodule_clock_generator_0"> + <rect x="0" y="0" rx="6" ry="6" width="90" height="74" style="fill:#CCCCCC; stroke:#000000; stroke-width:2"/> + <rect x="11" y="18" rx="3" ry="3" width="68" height="38" style="fill:#FFFFFF; stroke:none;"/> + <text x="45" y="26" fill="#AA0017" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Arial Helvetica san-serif">clock_generator</text> + <text x="45" y="38" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Courier Arial Helvetica san-serif">clock_generator_0</text> + </g> + <g id="ipbucket"> + <rect x="0" y="0" rx="4" ry="4" width="122" height="106" style="stroke-width:2; stroke:#000000; fill:#CCCCFF"/> + <use x="16" y="16" xlink:href="#ipbktmodule_clock_generator_0"/> + </g> + <g id="symbol_STACK_0_SHAPE_4"> + <rect x="0" y="0" rx="6" ry="6" width="90" height="74" style="fill:#CCCCCC; stroke:#FFFFFF; stroke-width:2"/> + <rect x="11" y="4" rx="3" ry="3" width="68" height="38" style="fill:#FFFFFF; stroke:none;"/> + <text x="45" y="12" fill="#AA0017" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Arial Helvetica san-serif">plbv46_pcie</text> + <text x="45" y="20" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Courier Arial Helvetica san-serif">PCIe_Bridge</text> + <line x1="79" y1="64" x2="91" y2="64" style="stroke:#BB9955;stroke-width:1"/> + <use x="47" y="54" xlink:href="#PLBV46_BifLabel"/> + <text x="63" y="65" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Courier Arial Helvetica san-serif">SPLB</text> + <line x1="0" y1="64" x2="11" y2="64" style="stroke:#BB9955;stroke-width:1"/> + <use x="11" y="54" xlink:href="#PLBV46_P2P_BifLabel"/> + <text x="27" y="65" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Courier Arial Helvetica san-serif">MPLB</text> + </g> + <g id="symbol_STACK_0_SHAPE_1"> + <rect x="0" y="0" rx="6" ry="6" width="90" height="74" style="fill:#CCCCCC; stroke:#FFFFFF; stroke-width:2"/> + <rect x="11" y="4" rx="3" ry="3" width="68" height="38" style="fill:#FFFFFF; stroke:none;"/> + <text x="45" y="12" fill="#AA0017" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Arial Helvetica san-serif">ppc440mc_ddr2</text> + <text x="45" y="20" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Courier Arial Helvetica san-serif">DDR2_SDRAM</text> + <line x1="0" y1="64" x2="11" y2="64" style="stroke:#990066;stroke-width:1"/> + <use x="11" y="54" xlink:href="#XIL_BifLabel"/> + <text x="27" y="65" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Courier Arial Helvetica san-serif">PPC4</text> + </g> + <g id="symbol_STACK_0_SHAPE_2"> + <rect x="0" y="0" rx="6" ry="6" width="90" height="74" style="fill:#CCCCCC; stroke:#FFFFFF; stroke-width:2"/> + <rect x="11" y="4" rx="3" ry="3" width="68" height="38" style="fill:#FFFFFF; stroke:none;"/> + <text x="45" y="12" fill="#AA0017" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Arial Helvetica san-serif">jtagppc_cntlr</text> + <text x="45" y="20" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Courier Arial Helvetica san-serif">jtagppc_cntlr_inst</text> + <line x1="79" y1="64" x2="91" y2="64" style="stroke:#990066;stroke-width:1"/> + <use x="47" y="54" xlink:href="#XIL_BifLabel"/> + <text x="63" y="65" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Courier Arial Helvetica san-serif">JTAG</text> + </g> + <g id="symbol_STACK_0_SHAPE_0"> + <rect x="0" y="0" rx="6" ry="6" width="90" height="74" style="fill:#CCCCCC; stroke:#FFFFFF; stroke-width:2"/> + <rect x="11" y="4" rx="3" ry="3" width="68" height="38" style="fill:#FFFFFF; stroke:none;"/> + <text x="45" y="12" fill="#AA0017" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Arial Helvetica san-serif">proc_sys_reset</text> + <text x="45" y="20" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Courier Arial Helvetica san-serif">proc_sys_reset_0</text> + <line x1="0" y1="64" x2="11" y2="64" style="stroke:#990066;stroke-width:1"/> + <use x="11" y="54" xlink:href="#XIL_BifLabel"/> + <text x="27" y="65" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Courier Arial Helvetica san-serif">RESE</text> + </g> + <g id="symbol_STACK_0_SHAPE_3"> + <rect x="0" y="0" rx="6" ry="6" width="90" height="142" style="fill:#90001C; stroke:#FFFFFF; stroke-width:2"/> + <rect x="11" y="4" rx="3" ry="3" width="68" height="38" style="fill:#FFFFFF; stroke:none;"/> + <text x="45" y="12" fill="#AA0017" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Arial Helvetica san-serif">ppc440_virtex5</text> + <text x="45" y="20" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Courier Arial Helvetica san-serif">ppc440_0</text> + <line x1="79" y1="92" x2="91" y2="92" style="stroke:#BB9955;stroke-width:1"/> + <use x="47" y="82" xlink:href="#PLBV46_BifLabel"/> + <text x="63" y="93" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Courier Arial Helvetica san-serif">MPLB</text> + <line x1="0" y1="92" x2="11" y2="92" style="stroke:#BB9955;stroke-width:1"/> + <use x="11" y="82" xlink:href="#PLBV46_P2P_BifLabel"/> + <text x="27" y="93" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Courier Arial Helvetica san-serif">SPLB0</text> + <line x1="0" y1="64" x2="11" y2="64" style="stroke:#990066;stroke-width:1"/> + <use x="11" y="54" xlink:href="#XIL_BifLabel"/> + <text x="27" y="65" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Courier Arial Helvetica san-serif">PPC4</text> + <line x1="79" y1="64" x2="91" y2="64" style="stroke:#990066;stroke-width:1"/> + <use x="47" y="54" xlink:href="#XIL_BifLabel"/> + <text x="63" y="65" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Courier Arial Helvetica san-serif">JTAG</text> + <line x1="0" y1="120" x2="11" y2="120" style="stroke:#990066;stroke-width:1"/> + <use x="11" y="110" xlink:href="#XIL_BifLabel"/> + <text x="27" y="121" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Courier Arial Helvetica san-serif">RESE</text> + <rect x="81" y="3" rx="3" ry="3" width="9" height="18" style="fill:#FF9900; stroke:none; stroke-width:1"/> + <line x1="81" y1="6" x2="90" y2="6" style="stroke:#000000;stroke-width:1"/> + <line x1="81" y1="10" x2="90" y2="10" style="stroke:#000000;stroke-width:1"/> + <text x="83" y="20" fill="#000000" stroke="none" font-size="10pt" font-weight="900" text-anchor="start" font-family="Arial Helvetica san-serif">0</text> + </g> + <g id="symbol_STACK_0"> + <rect x="0" y="0" rx="6" ry="6" width="334" height="1010" style="fill:#CCCCCC; stroke:none;"/> + <use x="122" y="554" xlink:href="#symbol_STACK_0_SHAPE_4"/> + <use x="122" y="90" xlink:href="#symbol_STACK_0_SHAPE_1"/> + <use x="122" y="180" xlink:href="#symbol_STACK_0_SHAPE_2"/> + <use x="122" y="0" xlink:href="#symbol_STACK_0_SHAPE_0"/> + <use x="0" y="644" xlink:href="#sbsbucket_plb_v46_0"/> + <text x="0" y="640" fill="#000000" stroke="none" font-size="9pt" font-style="normal" font-weight="900" text-anchor="start" font-family="Arial Helvetica san-serif">SLAVES OF plb_v46_0</text> + <use x="122" y="270" xlink:href="#symbol_STACK_0_SHAPE_3"/> + <text x="122" y="266" fill="#000000" stroke="none" font-size="9pt" font-style="normal" font-weight="900" text-anchor="start" font-family="Arial Helvetica san-serif">PROCESSOR</text> + </g> + <g id="symbol_xps_bram_if_cntlr_1_bram"> + <rect x="0" y="0" rx="6" ry="6" width="90" height="74" style="fill:#CCCCCC; stroke:#FFFFFF; stroke-width:2"/> + <rect x="11" y="32" rx="3" ry="3" width="68" height="38" style="fill:#FFFFFF; stroke:none;"/> + <text x="45" y="40" fill="#AA0017" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Arial Helvetica san-serif">bram_block</text> + <text x="45" y="48" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Courier Arial Helvetica san-serif">xps_bram_if_cntlr_1_bram</text> + <use x="47" y="4" xlink:href="#XIL_BifLabel"/> + <text x="63" y="15" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Courier Arial Helvetica san-serif">PORTA</text> + </g> + <g id="symbol_xps_bram_if_cntlr_1"> + <rect x="0" y="0" rx="6" ry="6" width="90" height="74" style="fill:#CCCCCC; stroke:#FFFFFF; stroke-width:2"/> + <rect x="11" y="4" rx="3" ry="3" width="68" height="38" style="fill:#FFFFFF; stroke:none;"/> + <text x="45" y="12" fill="#AA0017" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Arial Helvetica san-serif">xps_bram_if_cntlr</text> + <text x="45" y="20" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Courier Arial Helvetica san-serif">xps_bram_if_cntlr_1</text> + <line x1="0" y1="64" x2="11" y2="64" style="stroke:#BB9955;stroke-width:1"/> + <use x="11" y="54" xlink:href="#PLBV46_BifLabel"/> + <text x="27" y="65" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Courier Arial Helvetica san-serif">SPLB</text> + <use x="47" y="54" xlink:href="#XIL_BifLabel"/> + <text x="63" y="65" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="middle" font-family="Verdana Courier Arial Helvetica san-serif">PORTA</text> + </g> + <g id="symbol_STACK_1_SHAPE_0"> + <rect x="0" y="0" rx="6" ry="6" width="94" height="152" style="fill:#BB9955; stroke:#BB9955; stroke-width:2"/> + <use x="2" y="76" xlink:href="#symbol_xps_bram_if_cntlr_1_bram"/> + <use x="2" y="0" xlink:href="#symbol_xps_bram_if_cntlr_1"/> + </g> + <g id="symbol_STACK_1"> + <rect x="0" y="0" rx="6" ry="6" width="90" height="164" style="fill:#CCCCCC; stroke:none;"/> + <use x="0" y="138" xlink:href="#symbol_STACK_1_SHAPE_0"/> + </g> + <g id="symbol_SPACE_WEST_NONE_EAST_0"> + <rect x="40" y="356" width="8" height="264" style="stroke:#FFFFFF;stroke-width:1.5;fill:#BB9955"/> + <text x="52" y="384" fill="#000000" stroke="none" font-size="8pt" font-style="italic" font-weight="900" text-anchor="start" font-family="Verdana Courier Arial Helvetica san-serif">ppc440_0_SPLB0</text> + <use x="298" y="348" xlink:href="#PLBV46_P2P_busconn_SLAVE"/> + <use x="290" y="354" xlink:href="#PLBV46_P2P_BusArrowEast"/> + <rect x="44" y="356" width="246" height="8" style="stroke:none; fill:#BB9955"/> + <use x="298" y="604" xlink:href="#PLBV46_P2P_busconn_MASTER"/> + <use x="290" y="610" xlink:href="#PLBV46_P2P_BusArrowEast"/> + <rect x="44" y="612" width="246" height="8" style="stroke:none; fill:#BB9955"/> + <rect x="40" y="148" width="8" height="188" style="stroke:none;fill:#990066"/> + <text x="52" y="176" fill="#000000" stroke="none" font-size="8pt" font-style="italic" font-weight="900" text-anchor="start" font-family="Verdana Courier Arial Helvetica san-serif">ppc440_0_PPC440MC</text> + <use x="298" y="320" xlink:href="#XIL_busconn_INITIATOR"/> + <use x="290" y="326" xlink:href="#XIL_BusArrowEast"/> + <rect x="44" y="328" width="246" height="8" style="stroke:none; fill:#990066"/> + <use x="298" y="140" xlink:href="#XIL_busconn_TARGET"/> + <use x="290" y="146" xlink:href="#XIL_BusArrowEast"/> + <rect x="44" y="148" width="246" height="8" style="stroke:none; fill:#990066"/> + <rect x="0" y="58" width="8" height="334" style="stroke:none;fill:#990066"/> + <text x="12" y="86" fill="#000000" stroke="none" font-size="8pt" font-style="italic" font-weight="900" text-anchor="start" font-family="Verdana Courier Arial Helvetica san-serif">ppc_reset_bus</text> + <use x="298" y="376" xlink:href="#XIL_busconn_TARGET"/> + <use x="290" y="382" xlink:href="#XIL_BusArrowEast"/> + <rect x="4" y="384" width="286" height="8" style="stroke:none; fill:#990066"/> + <use x="298" y="50" xlink:href="#XIL_busconn_INITIATOR"/> + <use x="290" y="56" xlink:href="#XIL_BusArrowEast"/> + <rect x="4" y="58" width="286" height="8" style="stroke:none; fill:#990066"/> + <rect x="-4" y="458" width="8" height="217" style="stroke:none; fill:#BB9955"/> + <rect x="-4" y="668" width="267" height="8" style="stroke:none; fill:#BB9955"/> + </g> + <g id="symbol_SPACE_WEST_0_EAST_1"> + <use x="45" y="348" xlink:href="#PLBV46_busconn_MASTER"/> + <rect x="223" y="362" width="8" height="92" style="stroke:none; fill:#BB9955"/> + <rect x="64" y="356" width="167" height="8" style="stroke:none; fill:#BB9955"/> + <rect x="303" y="238" width="8" height="98" style="stroke:none;fill:#990066"/> + <text x="315" y="266" fill="#000000" stroke="none" font-size="8pt" font-style="italic" font-weight="900" text-anchor="start" font-family="Verdana Courier Arial Helvetica san-serif">ppc440_0_jtagppc_bus</text> + <use x="45" y="320" xlink:href="#XIL_busconn_TARGET"/> + <use x="69" y="326" xlink:href="#XIL_BusArrowWest"/> + <rect x="76" y="328" width="232" height="8" style="stroke:none; fill:#990066"/> + <use x="45" y="230" xlink:href="#XIL_busconn_INITIATOR"/> + <use x="69" y="236" xlink:href="#XIL_BusArrowWest"/> + <rect x="76" y="238" width="232" height="8" style="stroke:none; fill:#990066"/> + <use x="45" y="604" xlink:href="#PLBV46_busconn_SLAVE"/> + <rect x="263" y="458" width="8" height="156" style="stroke:none; fill:#BB9955"/> + <rect x="64" y="612" width="207" height="8" style="stroke:none; fill:#BB9955"/> + <use x="383" y="572" xlink:href="#PLBV46_busconn_SLAVE"/> + <rect x="239" y="458" width="8" height="124" style="stroke:none; fill:#BB9955"/> + <rect x="239" y="580" width="150" height="8" style="stroke:none; fill:#BB9955"/> + </g> + <g id="symbol_SPACE_WEST_1_EAST_NONE"/> + <g id="KEY_IntrCntrl"> + <rect x="0" y="0" rx="3" ry="3" width="9" height="18" style="fill:#888888; stroke:none; stroke-width:1"/> + <line x1="0" y1="5" x2="9" y2="5" style="stroke:#000000;stroke-width:2"/> + <text x="1.5" y="16" fill="#000000" stroke="none" font-size="10pt" font-weight="900" text-anchor="start" font-family="Arial Helvetica san-serif">x</text> + </g> + <g id="KEY_IntrdProc"> + <rect x="0" y="0" rx="3" ry="3" width="9" height="18" style="fill:#888888; stroke:none; stroke-width:1"/> + <line x1="0" y1="3" x2="9" y2="3" style="stroke:#000000;stroke-width:1"/> + <line x1="0" y1="7" x2="9" y2="7" style="stroke:#000000;stroke-width:1"/> + <text x="1.5" y="16" fill="#000000" stroke="none" font-size="10pt" font-weight="900" text-anchor="start" font-family="Arial Helvetica san-serif">x</text> + </g> + <g id="KEY_IntrSrc"> + <rect x="0" y="0" rx="3" ry="3" width="18" height="9" style="fill:#888888; stroke:none; stroke-width:1"/> + <line x1="9" y1="0" x2="9" y2="9" style="stroke:#000000;stroke-width:1"/> + <text x="2" y="7" fill="#000000" stroke="none" font-size="10pt" font-weight="900" text-anchor="start" font-family="Arial Helvetica san-serif">y</text> + <text x="11" y="7" fill="#000000" stroke="none" font-size="10pt" font-weight="900" text-anchor="start" font-family="Arial Helvetica san-serif">x</text> + </g> + <g id="BlkDiagram_Key"> + <rect x="0" y="0" width="468" height="250" style="fill:#CCCCCC; stroke:none;"/> + <rect x="0" y="0" width="468" height="16" style="fill:#CCCCCC; stroke:none;"/> + <text x="234" y="14" fill="#AA0017" stroke="none" font-size="14pt" font-weight="900" text-anchor="middle" font-family="Arial Helvetica san-serif">KEY</text> + <rect x="0" y="16" width="468" height="16" style="fill:#EEEEEE; stroke:none;"/> + <text x="234" y="30" fill="#000000" stroke="none" font-size="10pt" font-weight="900" text-anchor="middle" font-family="Arial Helvetica san-serif">SYMBOLS</text> + <use x="32" y="47" xlink:href="#KEY_BifLabel" transform="scale(0.75)"/> + <text x="12" y="60" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="start" font-family="Verdana Arial Helvetica san-serif">bus interface</text> + <use x="20" y="68" xlink:href="#KEY_SharedBus"/> + <text x="12" y="85" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="start" font-family="Verdana Arial Helvetica san-serif">shared bus</text> + <text class="keylblul" x="110" y="47">Bus connections</text> + <use x="110" y="58" xlink:href="#KEY_busconn_MASTER"/> + <text x="140" y="72" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="start" font-family="Verdana Arial Helvetica san-serif">master or initiator</text> + <use x="110" y="86" xlink:href="#KEY_busconn_SLAVE"/> + <text x="140" y="100" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="start" font-family="Verdana Arial Helvetica san-serif">slave or target</text> + <use x="110" y="114" xlink:href="#KEY_busconn_MASTER_SLAVE"/> + <text x="140" y="128" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="start" font-family="Verdana Arial Helvetica san-serif">master slave</text> + <use x="110" y="142" xlink:href="#KEY_busconn_MONITOR"/> + <text x="140" y="156" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="start" font-family="Verdana Arial Helvetica san-serif">monitor</text> + <text class="keylblul" x="258" y="47">External Ports</text> + <use x="258" y="58" xlink:href="#KEY_INPort"/> + <text x="288" y="72" fill="#000000" stroke="none" font-size="10pt" font-style="italic" font-weight="900" text-anchor="start" font-family="Verdana Arial Helvetica san-serif">monitor</text> + <use x="258" y="78" xlink:href="#KEY_OUTPort"/> + <text class="keylabel" x="288" y="92">output</text> + <use x="258" y="98" xlink:href="#KEY_INOUTPort"/> + <text class="keylabel" x="288" y="112">inout</text> + <text class="keylblul" x="380" y="47">Interrupts</text> + <use x="380" y="58" xlink:href="#KEY_IntrCntrl"/> + <text class="keylabel" x="396" y="64">interrupt</text> + <text class="keylabel" x="396" y="74">controller</text> + <use x="380" y="88" xlink:href="#KEY_IntrdProc"/> + <text class="keylabel" x="396" y="94">interrupted</text> + <text class="keylabel" x="396" y="104">processor</text> + <use x="380" y="118" xlink:href="#KEY_IntrSrc"/> + <text class="keylabel" x="400" y="124">interrupt</text> + <text class="keylabel" x="400" y="134">source</text> + <text class="keylabel" x="360" y="146">x = controller ID</text> + <text class="keylabel" x="360" y="156">y = priority</text> + <rect x="0" y="160" width="468" height="16" style="fill:#EEEEEE; stroke:none;"/> + <text class="keyheader" x="234 " y="172">COLORS</text> + <text class="keylblul" x="110" y="190">Bus Standards</text> + <rect x="12" y="200" width="24" height="24" style="fill:#6699FF; stroke:none;"/> + <text class="keylabel" x="40" y="220">DCR</text> + <rect x="12" y="228" width="24" height="24" style="fill:#8C00FF; stroke:none;"/> + <text class="keylabel" x="40" y="240">FCB</text> + <rect x="84" y="200" width="24" height="24" style="fill:#CC00CC; stroke:none;"/> + <text class="keylabel" x="112" y="220">FSL</text> + <rect x="84" y="228" width="24" height="24" style="fill:#7777FF; stroke:none;"/> + <text class="keylabel" x="112" y="240">LMB</text> + <rect x="156" y="200" width="24" height="24" style="fill:#339900; stroke:none;"/> + <text class="keylabel" x="184" y="220">OPB</text> + <rect x="156" y="228" width="24" height="24" style="fill:#FF5500; stroke:none;"/> + <text class="keylabel" x="184" y="240">PLB</text> + <rect x="228" y="200" width="24" height="24" style="fill:#0000DD; stroke:none;"/> + <text class="keylabel" x="256" y="220">SOCM</text> + <rect x="228" y="228" width="24" height="24" style="fill:#990066; stroke:none;"/> + <text class="keylabel" x="256" y="240">Xilinx P2P</text> + <rect x="300" y="200" width="24" height="24" style="fill:#009999; stroke:none;"/> + <text class="keylabel" x="328" y="220">USER P2P</text> + </g> + <g id="BlkDiagram_Specs"> + <rect x="0" y="0" width="300" height="100" style="fill:#CCCCCC; stroke:none;"/> + <rect x="0" y="0" width="300" height="16" style="fill:#CCCCCC; stroke:none;"/> + <text class="keytitle" x="150 " y="14">SPECS</text> + <rect x="0" y="20" width="300" height="16" style="fill:#EEEEEE; stroke:none;"/> + <text class="specsheader" x="4" y="32">EDK VERSION</text> + <text class="specsvaluemid" x="241" y="32">11.1</text> + <rect x="0" y="40" width="300" height="16" style="fill:#EEEEEE; stroke:none;"/> + <text class="specsheader" x="4" y="52">ARCH</text> + <text class="specsvaluemid" x="241" y="52">virtex5</text> + <rect x="0" y="60" width="300" height="16" style="fill:#EEEEEE; stroke:none;"/> + <text class="specsheader" x="4" y="72">PART</text> + <text class="specsvaluemid" x="241" y="72">xc5vfx70tff1136-1</text> + <rect x="0" y="80" width="300" height="16" style="fill:#EEEEEE; stroke:none;"/> + <text class="specsheader" x="4" y="92">GENERATED</text> + <text class="specsvalue" x="145" y="92">Fri Jun 12 17:10:55 2009</text> + </g> + </defs> + <rect x="0" y="0" width="1322" height="1833" style="fill:#FFFFFF; stroke:#000000;stroke-width:4"/> + <rect x="48" y="40" width="1226" height="1492" style="fill:#000088"/> + <rect x="64" y="56" width="1194" height="1460" rx="8" ry="8" style="fill:#CCCCCC"/> + <use x="32" y="566" id="fpga_0_RS232_Uart_1_RX_pin" xlink:href="#G_IOPort" transform="rotate(0,40,574)"/> + <text class="iopnumb" x="18" y="580"><tspan class="iopgrp"></tspan></text> + <use x="32" y="594" id="fpga_0_RS232_Uart_1_TX_pin" xlink:href="#G_IOPort" transform="rotate(180,40,602)"/> + <text class="iopnumb" x="18" y="608"><tspan class="iopgrp"></tspan></text> + <use x="32" y="622" id="fpga_0_LEDs_8Bit_GPIO_IO_pin" xlink:href="#G_BIPort" transform="rotate(0,40,630)"/> + <text class="iopnumb" x="18" y="636"><tspan class="iopgrp"></tspan></text> + <use x="32" y="650" id="fpga_0_LEDs_Positions_GPIO_IO_pin" xlink:href="#G_BIPort" transform="rotate(0,40,658)"/> + <text class="iopnumb" x="18" y="664"><tspan class="iopgrp"></tspan></text> + <use x="32" y="678" id="fpga_0_Push_Buttons_5Bit_GPIO_IO_pin" xlink:href="#G_BIPort" transform="rotate(0,40,686)"/> + <text class="iopnumb" x="18" y="692"><tspan class="iopgrp"></tspan></text> + <use x="32" y="706" id="fpga_0_DIP_Switches_8Bit_GPIO_IO_pin" xlink:href="#G_BIPort" transform="rotate(0,40,714)"/> + <text class="iopnumb" x="18" y="720"><tspan class="iopgrp"></tspan></text> + <use x="32" y="734" id="fpga_0_IIC_EEPROM_Sda_pin" xlink:href="#G_BIPort" transform="rotate(0,40,742)"/> + <text class="iopnumb" x="18" y="748"><tspan class="iopgrp"></tspan></text> + <use x="32" y="762" id="fpga_0_IIC_EEPROM_Scl_pin" xlink:href="#G_BIPort" transform="rotate(0,40,770)"/> + <text class="iopnumb" x="18" y="776"><tspan class="iopgrp"></tspan></text> + <use x="32" y="790" id="fpga_0_SRAM_Mem_A_pin" xlink:href="#G_IOPort" transform="rotate(180,40,798)"/> + <text class="iopnumb" x="18" y="804"><tspan class="iopgrp"></tspan></text> + <use x="32" y="818" id="fpga_0_SRAM_Mem_CEN_pin" xlink:href="#G_IOPort" transform="rotate(180,40,826)"/> + <text class="iopnumb" x="18" y="832"><tspan class="iopgrp"></tspan></text> + <use x="32" y="846" id="fpga_0_SRAM_Mem_OEN_pin" xlink:href="#G_IOPort" transform="rotate(180,40,854)"/> + <text class="iopnumb" x="18" y="860"><tspan class="iopgrp"></tspan></text> + <use x="32" y="874" id="fpga_0_SRAM_Mem_WEN_pin" xlink:href="#G_IOPort" transform="rotate(180,40,882)"/> + <text class="iopnumb" x="18" y="888"><tspan class="iopgrp"></tspan></text> + <use x="32" y="902" id="fpga_0_SRAM_Mem_BEN_pin" xlink:href="#G_IOPort" transform="rotate(180,40,910)"/> + <text class="iopnumb" x="18" y="916"><tspan class="iopgrp"></tspan></text> + <use x="32" y="930" id="fpga_0_SRAM_Mem_ADV_LDN_pin" xlink:href="#G_IOPort" transform="rotate(180,40,938)"/> + <text class="iopnumb" x="18" y="944"><tspan class="iopgrp"></tspan></text> + <use x="32" y="958" id="fpga_0_SRAM_Mem_DQ_pin" xlink:href="#G_BIPort" transform="rotate(0,40,966)"/> + <text class="iopnumb" x="18" y="972"><tspan class="iopgrp"></tspan></text> + <rect x="439" y="1532" width="16" height="16" style="stroke:#000088; stroke-width:1"/> + <use x="439" y="1532" id="fpga_0_SRAM_ZBT_CLK_OUT_pin" xlink:href="#G_IOPort" transform="rotate(90,447,1540)"/> + <text class="iopnumb" x="447" y="1568"><tspan class="iopgrp"></tspan></text> + <rect x="467" y="1532" width="16" height="16" style="stroke:#000088; stroke-width:1"/> + <use x="467" y="1532" id="fpga_0_SRAM_ZBT_CLK_FB_pin" xlink:href="#G_IOPort" transform="rotate(-90,475,1540)"/> + <text class="iopnumb" x="475" y="1568"><tspan class="iopgrp"></tspan></text> + <rect x="495" y="1532" width="16" height="16" style="stroke:#000088; stroke-width:1"/> + <use x="495" y="1532" id="fpga_0_PCIe_Bridge_RXN_pin" xlink:href="#G_IOPort" transform="rotate(-90,503,1540)"/> + <text class="iopnumb" x="503" y="1568"><tspan class="iopgrp"></tspan></text> + <rect x="523" y="1532" width="16" height="16" style="stroke:#000088; stroke-width:1"/> + <use x="523" y="1532" id="fpga_0_PCIe_Bridge_RXP_pin" xlink:href="#G_IOPort" transform="rotate(-90,531,1540)"/> + <text class="iopnumb" x="531" y="1568"><tspan class="iopgrp"></tspan></text> + <rect x="551" y="1532" width="16" height="16" style="stroke:#000088; stroke-width:1"/> + <use x="551" y="1532" id="fpga_0_PCIe_Bridge_TXN_pin" xlink:href="#G_IOPort" transform="rotate(90,559,1540)"/> + <text class="iopnumb" x="559" y="1568"><tspan class="iopgrp"></tspan></text> + <rect x="579" y="1532" width="16" height="16" style="stroke:#000088; stroke-width:1"/> + <use x="579" y="1532" id="fpga_0_PCIe_Bridge_TXP_pin" xlink:href="#G_IOPort" transform="rotate(90,587,1540)"/> + <text class="iopnumb" x="587" y="1568"><tspan class="iopgrp"></tspan></text> + <rect x="607" y="1532" width="16" height="16" style="stroke:#000088; stroke-width:1"/> + <use x="607" y="1532" id="fpga_0_Ethernet_MAC_PHY_tx_clk_pin" xlink:href="#G_IOPort" transform="rotate(-90,615,1540)"/> + <text class="iopnumb" x="615" y="1568"><tspan class="iopgrp"></tspan></text> + <rect x="635" y="1532" width="16" height="16" style="stroke:#000088; stroke-width:1"/> + <use x="635" y="1532" id="fpga_0_Ethernet_MAC_PHY_rx_clk_pin" xlink:href="#G_IOPort" transform="rotate(-90,643,1540)"/> + <text class="iopnumb" x="643" y="1568"><tspan class="iopgrp"></tspan></text> + <rect x="663" y="1532" width="16" height="16" style="stroke:#000088; stroke-width:1"/> + <use x="663" y="1532" id="fpga_0_Ethernet_MAC_PHY_crs_pin" xlink:href="#G_IOPort" transform="rotate(-90,671,1540)"/> + <text class="iopnumb" x="671" y="1568"><tspan class="iopgrp"></tspan></text> + <rect x="691" y="1532" width="16" height="16" style="stroke:#000088; stroke-width:1"/> + <use x="691" y="1532" id="fpga_0_Ethernet_MAC_PHY_dv_pin" xlink:href="#G_IOPort" transform="rotate(-90,699,1540)"/> + <text class="iopnumb" x="699" y="1568"><tspan class="iopgrp"></tspan></text> + <rect x="719" y="1532" width="16" height="16" style="stroke:#000088; stroke-width:1"/> + <use x="719" y="1532" id="fpga_0_Ethernet_MAC_PHY_rx_data_pin" xlink:href="#G_IOPort" transform="rotate(-90,727,1540)"/> + <text class="iopnumb" x="727" y="1568"><tspan class="iopgrp"></tspan></text> + <rect x="747" y="1532" width="16" height="16" style="stroke:#000088; stroke-width:1"/> + <use x="747" y="1532" id="fpga_0_Ethernet_MAC_PHY_col_pin" xlink:href="#G_IOPort" transform="rotate(-90,755,1540)"/> + <text class="iopnumb" x="755" y="1568"><tspan class="iopgrp"></tspan></text> + <rect x="775" y="1532" width="16" height="16" style="stroke:#000088; stroke-width:1"/> + <use x="775" y="1532" id="fpga_0_Ethernet_MAC_PHY_rx_er_pin" xlink:href="#G_IOPort" transform="rotate(-90,783,1540)"/> + <text class="iopnumb" x="783" y="1568"><tspan class="iopgrp"></tspan></text> + <rect x="803" y="1532" width="16" height="16" style="stroke:#000088; stroke-width:1"/> + <use x="803" y="1532" id="fpga_0_Ethernet_MAC_PHY_rst_n_pin" xlink:href="#G_IOPort" transform="rotate(90,811,1540)"/> + <text class="iopnumb" x="811" y="1568"><tspan class="iopgrp"></tspan></text> + <rect x="831" y="1532" width="16" height="16" style="stroke:#000088; stroke-width:1"/> + <use x="831" y="1532" id="fpga_0_Ethernet_MAC_PHY_tx_en_pin" xlink:href="#G_IOPort" transform="rotate(90,839,1540)"/> + <text class="iopnumb" x="839" y="1568"><tspan class="iopgrp"></tspan></text> + <use x="1274" y="566" id="fpga_0_Ethernet_MAC_PHY_tx_data_pin" xlink:href="#G_IOPort" transform="rotate(0,1282,574)"/> + <text class="iopnumb" x="1302" y="580"><tspan class="iopgrp"></tspan></text> + <use x="1274" y="594" id="fpga_0_Ethernet_MAC_MDINT_pin" xlink:href="#G_IOPort" transform="rotate(180,1282,602)"/> + <text class="iopnumb" x="1302" y="608"><tspan class="iopgrp"></tspan></text> + <use x="1274" y="622" id="fpga_0_DDR2_SDRAM_DDR2_DQ_pin" xlink:href="#G_BIPort" transform="rotate(0,1282,630)"/> + <text class="iopnumb" x="1302" y="636"><tspan class="iopgrp"></tspan></text> + <use x="1274" y="650" id="fpga_0_DDR2_SDRAM_DDR2_DQS_pin" xlink:href="#G_BIPort" transform="rotate(0,1282,658)"/> + <text class="iopnumb" x="1302" y="664"><tspan class="iopgrp"></tspan></text> + <use x="1274" y="678" id="fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin" xlink:href="#G_BIPort" transform="rotate(0,1282,686)"/> + <text class="iopnumb" x="1302" y="692"><tspan class="iopgrp"></tspan></text> + <use x="1274" y="706" id="fpga_0_DDR2_SDRAM_DDR2_A_pin" xlink:href="#G_IOPort" transform="rotate(0,1282,714)"/> + <text class="iopnumb" x="1302" y="720"><tspan class="iopgrp"></tspan></text> + <use x="1274" y="734" id="fpga_0_DDR2_SDRAM_DDR2_BA_pin" xlink:href="#G_IOPort" transform="rotate(0,1282,742)"/> + <text class="iopnumb" x="1302" y="748"><tspan class="iopgrp"></tspan></text> + <use x="1274" y="762" id="fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin" xlink:href="#G_IOPort" transform="rotate(0,1282,770)"/> + <text class="iopnumb" x="1302" y="776"><tspan class="iopgrp"></tspan></text> + <use x="1274" y="790" id="fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin" xlink:href="#G_IOPort" transform="rotate(0,1282,798)"/> + <text class="iopnumb" x="1302" y="804"><tspan class="iopgrp"></tspan></text> + <use x="1274" y="818" id="fpga_0_DDR2_SDRAM_DDR2_WE_N_pin" xlink:href="#G_IOPort" transform="rotate(0,1282,826)"/> + <text class="iopnumb" x="1302" y="832"><tspan class="iopgrp"></tspan></text> + <use x="1274" y="846" id="fpga_0_DDR2_SDRAM_DDR2_CS_N_pin" xlink:href="#G_IOPort" transform="rotate(0,1282,854)"/> + <text class="iopnumb" x="1302" y="860"><tspan class="iopgrp"></tspan></text> + <use x="1274" y="874" id="fpga_0_DDR2_SDRAM_DDR2_ODT_pin" xlink:href="#G_IOPort" transform="rotate(0,1282,882)"/> + <text class="iopnumb" x="1302" y="888"><tspan class="iopgrp"></tspan></text> + <use x="1274" y="902" id="fpga_0_DDR2_SDRAM_DDR2_CKE_pin" xlink:href="#G_IOPort" transform="rotate(0,1282,910)"/> + <text class="iopnumb" x="1302" y="916"><tspan class="iopgrp"></tspan></text> + <use x="1274" y="930" id="fpga_0_DDR2_SDRAM_DDR2_DM_pin" xlink:href="#G_IOPort" transform="rotate(0,1282,938)"/> + <text class="iopnumb" x="1302" y="944"><tspan class="iopgrp"></tspan></text> + <use x="1274" y="958" id="fpga_0_DDR2_SDRAM_DDR2_CK_pin" xlink:href="#G_IOPort" transform="rotate(0,1282,966)"/> + <text class="iopnumb" x="1302" y="972"><tspan class="iopgrp"></tspan></text> + <use x="441" y="24" id="fpga_0_DDR2_SDRAM_DDR2_CK_N_pin" xlink:href="#G_IOPort" transform="rotate(-90,449,32)"/> + <text class="iopnumb" x="449" y="22"><tspan class="iopgrp"></tspan></text> + <use x="469" y="24" id="fpga_0_SysACE_CompactFlash_SysACE_MPA_pin" xlink:href="#G_IOPort" transform="rotate(-90,477,32)"/> + <text class="iopnumb" x="477" y="22"><tspan class="iopgrp"></tspan></text> + <use x="497" y="24" id="fpga_0_SysACE_CompactFlash_SysACE_CLK_pin" xlink:href="#G_IOPort" transform="rotate(90,505,32)"/> + <text class="iopnumb" x="505" y="22"><tspan class="iopgrp"></tspan></text> + <use x="525" y="24" id="fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin" xlink:href="#G_IOPort" transform="rotate(90,533,32)"/> + <text class="iopnumb" x="533" y="22"><tspan class="iopgrp"></tspan></text> + <use x="553" y="24" id="fpga_0_SysACE_CompactFlash_SysACE_CEN_pin" xlink:href="#G_IOPort" transform="rotate(-90,561,32)"/> + <text class="iopnumb" x="561" y="22"><tspan class="iopgrp"></tspan></text> + <use x="581" y="24" id="fpga_0_SysACE_CompactFlash_SysACE_OEN_pin" xlink:href="#G_IOPort" transform="rotate(-90,589,32)"/> + <text class="iopnumb" x="589" y="22"><tspan class="iopgrp"></tspan></text> + <use x="609" y="24" id="fpga_0_SysACE_CompactFlash_SysACE_WEN_pin" xlink:href="#G_IOPort" transform="rotate(-90,617,32)"/> + <text class="iopnumb" x="617" y="22"><tspan class="iopgrp"></tspan></text> + <use x="637" y="24" id="fpga_0_SysACE_CompactFlash_SysACE_MPD_pin" xlink:href="#G_BIPort" transform="rotate(0,645,32)"/> + <text class="iopnumb" x="645" y="22"><tspan class="iopgrp"></tspan></text> + <use x="665" y="24" id="fpga_0_clk_1_sys_clk_pin" xlink:href="#G_IOPort" transform="rotate(90,673,32)"/> + <text class="iopnumb" x="673" y="22"><tspan class="iopgrp"></tspan></text> + <use x="693" y="24" id="fpga_0_rst_1_sys_rst_pin" xlink:href="#G_IOPort" transform="rotate(90,701,32)"/> + <text class="iopnumb" x="701" y="22"><tspan class="iopgrp"></tspan></text> + <use x="721" y="24" id="fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin" xlink:href="#G_IOPort" transform="rotate(90,729,32)"/> + <text class="iopnumb" x="729" y="22"><tspan class="iopgrp"></tspan></text> + <use x="749" y="24" id="fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin" xlink:href="#G_IOPort" transform="rotate(90,757,32)"/> + <text class="iopnumb" x="757" y="22"><tspan class="iopgrp"></tspan></text> + <use x="469" y="101" xlink:href="#symbol_STACK_0"/> + <use x="1043" y="485" xlink:href="#symbol_STACK_1"/> + <use x="269" y="101" xlink:href="#symbol_SPACE_WEST_NONE_EAST_0"/> + <use x="636" y="101" xlink:href="#symbol_SPACE_WEST_0_EAST_1"/> + <use x="1088" y="485" xlink:href="#symbol_SPACE_WEST_1_EAST_NONE"/> + <use x="109" y="549" xlink:href="#group_sharedBusses"/> + <text x="600" y="1303" fill="#000000" stroke="none" font-size="9pt" font-style="normal" font-weight="900" text-anchor="start" font-family="Arial Helvetica san-serif">IP</text> + <use x="600" y="1307" xlink:href="#ipbucket"/> + <use x="806" y="1575" xlink:href="#BlkDiagram_Key"/> + <use x="48" y="1575" xlink:href="#BlkDiagram_Specs"/> +</svg> diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/data/system.ucf b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/data/system.ucf new file mode 100644 index 000000000..fd1b9bdd6 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/data/system.ucf @@ -0,0 +1,495 @@ +Net fpga_0_RS232_Uart_1_RX_pin LOC = AG15 | IOSTANDARD=LVCMOS33; +Net fpga_0_RS232_Uart_1_TX_pin LOC = AG20 | IOSTANDARD=LVCMOS33; +Net fpga_0_LEDs_8Bit_GPIO_IO_pin<0> LOC = AE24 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_LEDs_8Bit_GPIO_IO_pin<1> LOC = AD24 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_LEDs_8Bit_GPIO_IO_pin<2> LOC = AD25 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_LEDs_8Bit_GPIO_IO_pin<3> LOC = G16 | IOSTANDARD=LVCMOS25 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_LEDs_8Bit_GPIO_IO_pin<4> LOC = AD26 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_LEDs_8Bit_GPIO_IO_pin<5> LOC = G15 | IOSTANDARD=LVCMOS25 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_LEDs_8Bit_GPIO_IO_pin<6> LOC = L18 | IOSTANDARD=LVCMOS25 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_LEDs_8Bit_GPIO_IO_pin<7> LOC = H18 | IOSTANDARD=LVCMOS25 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> LOC=E8 | IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> LOC=AF23 | IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> LOC=AG12 | IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> LOC=AG23 | IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> LOC=AF13 | IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<0> LOC = AJ6 | IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<1> LOC = AJ7 | IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<2> LOC = V8 | IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<3> LOC = AK7 | IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<4> LOC = U8 | IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<0> LOC=U25 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<1> LOC=AG27 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<2> LOC=AF25 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<3> LOC=AF26 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<4> LOC=AE27 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<5> LOC=AE26 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<6> LOC=AC25 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<7> LOC=AC24 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_IIC_EEPROM_Sda_pin LOC=F8 | SLEW = SLOW | DRIVE = 6 | IOSTANDARD=LVCMOS33; +Net fpga_0_IIC_EEPROM_Scl_pin LOC=F9 | SLEW = SLOW | DRIVE = 6 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<30> LOC=K12 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<29> LOC=K13 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<28> LOC=H23 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<27> LOC=G23 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<26> LOC=H12 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<25> LOC=J12 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<24> LOC=K22 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<23> LOC=K23 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<22> LOC=K14 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<21> LOC=L14 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<20> LOC=H22 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<19> LOC=G22 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<18> LOC=J15 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<17> LOC=K16 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<16> LOC=K21 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<15> LOC=J22 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<14> LOC=L16 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<13> LOC=L15 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<12> LOC=L20 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<11> LOC=L21 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<10> LOC=AE23 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<9> LOC=AE22 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<8> LOC=AE12 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<7> LOC=AE13 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_CEN_pin LOC=J10 | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_OEN_pin LOC=B12 | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_WEN_pin LOC=AF20 | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_BEN_pin<3> LOC=J11 | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_BEN_pin<2> LOC=K11 | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_BEN_pin<1> LOC=D10 | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_BEN_pin<0> LOC=D11 | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_ADV_LDN_pin LOC=H8 | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_DQ_pin<0> LOC=AG22 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<1> LOC=AH22 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<2> LOC=AH12 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<3> LOC=AG13 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<4> LOC=AH20 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<5> LOC=AH19 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<6> LOC=AH14 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<7> LOC=AH13 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<8> LOC=AF15 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<9> LOC=AE16 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<10> LOC=AE21 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<11> LOC=AD20 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<12> LOC=AF16 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<13> LOC=AE17 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<14> LOC=AE19 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<15> LOC=AD19 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<16> LOC=J9 | PULLDOWN | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_DQ_pin<17> LOC=K8 | PULLDOWN | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_DQ_pin<18> LOC=K9 | PULLDOWN | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_DQ_pin<19> LOC=B13 | PULLDOWN | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_DQ_pin<20> LOC=C13 | PULLDOWN | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_DQ_pin<21> LOC=G11 | PULLDOWN | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_DQ_pin<22> LOC=G12 | PULLDOWN | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_DQ_pin<23> LOC=M8 | PULLDOWN | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_DQ_pin<24> LOC=L8 | PULLDOWN | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_DQ_pin<25> LOC=F11 | PULLDOWN | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_DQ_pin<26> LOC=E11 | PULLDOWN | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_DQ_pin<27> LOC=M10 | PULLDOWN | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_DQ_pin<28> LOC=L9 | PULLDOWN | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_DQ_pin<29> LOC=E12 | PULLDOWN | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_DQ_pin<30> LOC=E13 | PULLDOWN | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_DQ_pin<31> LOC=N10 | PULLDOWN | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_ZBT_CLK_OUT_pin LOC=G8 | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_ZBT_CLK_FB_pin LOC=AG21 | IOSTANDARD=LVCMOS33; +Net fpga_0_PCIe_Bridge_RXN_pin LOC=AF1 | IOSTANDARD = LVDS_25; +Net fpga_0_PCIe_Bridge_RXP_pin LOC=AE1 | IOSTANDARD = LVDS_25; +Net fpga_0_PCIe_Bridge_TXN_pin LOC=AE2 | IOSTANDARD = LVDS_25; +Net fpga_0_PCIe_Bridge_TXP_pin LOC=AD2 | IOSTANDARD = LVDS_25; +Net "pcie_bridge/*SPLB_Clk" TNM_NET = "SPLB_Clk"; +Net "pcie_bridge/*Bridge_Clk" TNM_NET = "Bridge_Clk"; + +## Timing constraints between clock-domain boundaries +# +TIMESPEC "TS_PLB_PCIe" = FROM "SPLB_Clk" TO "Bridge_Clk" 8 ns datapathonly; +TIMESPEC "TS_PCIe_PLB" = FROM "Bridge_Clk" TO "SPLB_Clk" 8 ns datapathonly; + +Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin LOC=K17 | IOSTANDARD = LVCMOS25; +Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin LOC=H17 | IOSTANDARD = LVCMOS25; +Net fpga_0_Ethernet_MAC_PHY_crs_pin LOC=E34 | IOSTANDARD = LVCMOS25; +Net fpga_0_Ethernet_MAC_PHY_dv_pin LOC=E32 | IOSTANDARD = LVCMOS25; +Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<0> LOC=A33 | IOSTANDARD = LVCMOS25; +Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<1> LOC=B33 | IOSTANDARD = LVCMOS25; +Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<2> LOC=C33 | IOSTANDARD = LVCMOS25; +Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<3> LOC=C32 | IOSTANDARD = LVCMOS25; +Net fpga_0_Ethernet_MAC_PHY_col_pin LOC=B32 | IOSTANDARD = LVCMOS25; +Net fpga_0_Ethernet_MAC_PHY_rx_er_pin LOC=E33 | IOSTANDARD = LVCMOS25; +Net fpga_0_Ethernet_MAC_PHY_rst_n_pin LOC=J14 | IOSTANDARD = LVCMOS25 | TIG; +Net fpga_0_Ethernet_MAC_PHY_tx_en_pin LOC=AJ10 | IOSTANDARD = LVDCI_33; +Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> LOC=AH10 | IOSTANDARD = LVDCI_33; +Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> LOC=AH9 | IOSTANDARD = LVDCI_33; +Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> LOC=AE11 | IOSTANDARD = LVDCI_33; +Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> LOC=AF11 | IOSTANDARD = LVDCI_33; +Net fpga_0_Ethernet_MAC_MDINT_pin LOC=H20 | IOSTANDARD = LVCMOS25 | TIG; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<0> LOC=AF30 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<1> LOC=AK31 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<2> LOC=AF31 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<3> LOC=AD30 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<4> LOC=AJ30 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<5> LOC=AF29 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<6> LOC=AD29 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<7> LOC=AE29 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<8> LOC=AH27 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<9> LOC=AF28 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<10> LOC=AH28 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<11> LOC=AA28 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<12> LOC=AG25 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<13> LOC=AJ26 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<14> LOC=AG28 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<15> LOC=AB28 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<16> LOC=AC28 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<17> LOC=AB25 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<18> LOC=AC27 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<19> LOC=AA26 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<20> LOC=AB26 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<21> LOC=AA24 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<22> LOC=AB27 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<23> LOC=AA25 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<24> LOC=AC29 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<25> LOC=AB30 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<26> LOC=W31 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<27> LOC=V30 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<28> LOC=AC30 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<29> LOC=W29 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<30> LOC=V27 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<31> LOC=W27 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<32> LOC=V29 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<33> LOC=Y27 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<34> LOC=Y26 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<35> LOC=W24 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<36> LOC=V28 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<37> LOC=W25 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<38> LOC=W26 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<39> LOC=V24 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<40> LOC=R24 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<41> LOC=P25 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<42> LOC=N24 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<43> LOC=P26 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<44> LOC=T24 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<45> LOC=N25 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<46> LOC=P27 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<47> LOC=N28 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<48> LOC=M28 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<49> LOC=L28 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<50> LOC=F25 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<51> LOC=H25 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<52> LOC=K27 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<53> LOC=K28 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<54> LOC=H24 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<55> LOC=G26 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<56> LOC=G25 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<57> LOC=M26 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<58> LOC=J24 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<59> LOC=L26 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<60> LOC=J27 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<61> LOC=M25 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<62> LOC=L25 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<63> LOC=L24 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<0> LOC=AA29 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<1> LOC=AK28 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<2> LOC=AK26 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<3> LOC=AB31 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<4> LOC=Y28 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<5> LOC=E26 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<6> LOC=H28 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<7> LOC=G27 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<0> LOC=AA30 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<1> LOC=AK27 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<2> LOC=AJ27 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<3> LOC=AA31 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<4> LOC=Y29 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<5> LOC=E27 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<6> LOC=G28 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<7> LOC=H27 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_A_pin<0> LOC=L30 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_A_pin<1> LOC=M30 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_A_pin<2> LOC=N29 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_A_pin<3> LOC=P29 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_A_pin<4> LOC=K31 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_A_pin<5> LOC=L31 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_A_pin<6> LOC=P31 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_A_pin<7> LOC=P30 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_A_pin<8> LOC=M31 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_A_pin<9> LOC=R28 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_A_pin<10> LOC=J31 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_A_pin<11> LOC=R29 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_A_pin<12> LOC=T31 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_BA_pin<0> LOC=G31 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_BA_pin<1> LOC=J30 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin LOC=H30 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin LOC=E31 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_WE_N_pin LOC=K29 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_CS_N_pin LOC=L29 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_ODT_pin<0> LOC=F31 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_ODT_pin<1> LOC=F30 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_CKE_pin LOC=T28 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<0> LOC=AJ31 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<1> LOC=AE28 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<2> LOC=Y24 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<3> LOC=Y31 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<4> LOC=V25 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<5> LOC=P24 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<6> LOC=F26 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<7> LOC=J25 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_CK_pin<0> LOC=AK29 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_CK_pin<1> LOC=E28 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_CK_N_pin<0> LOC=AJ29 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_CK_N_pin<1> LOC=F28 | IOSTANDARD = DIFF_SSTL18_II; +############################################################################ +# +# PPC440MC_DDR2 BRAM Location Constraints +# +############################################################################ + +##------------------------------------------------------------------------------ +## MIG 2.0 Constraints +##------------------------------------------------------------------------------ +########################################################################### +## Define multicycle paths - these paths may take longer because additional +## time allowed for logic to settle in calibration/initialization FSM +########################################################################### + +NET "DDR2_SDRAM*/mc_mibclk" TNM = FFS "TNM_CLK0"; +NET "DDR2_SDRAM*/mi_mcclk90" TNM = FFS "TNM_CLK90"; + +NET "DDR2_SDRAM*/mc_mibclk" TNM_NET = "mc_clk"; +TIMESPEC "TS_MC_CLK" = PERIOD "mc_clk" 5.000 ns; + + +## MUX Select for either rising/falling CLK0 for 2nd stage read capture +INST "*/u_phy_calib/gen_rd_data_sel*.u_ff_rd_data_sel" TNM = "TNM_RD_DATA_SEL"; +TIMESPEC "TS_MC_RD_DATA_SEL" = FROM "TNM_RD_DATA_SEL" TO "TNM_CLK0" +"TS_clk_div_slow_0_clk_div_slow_0_DDR2_CLK_i" * 4; + +## Calibration/Initialization complete status flag (for PHY logic only) +INST "*/u_phy_init/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_DATA_SEL"; +TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_0" = FROM "TNM_PHY_INIT_DATA_SEL" TO + "TNM_CLK0" +"TS_MC_CLK" * 4; + +TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_90" = FROM "TNM_PHY_INIT_DATA_SEL" TO + "TNM_CLK90" "TS_MC_CLK" * 4; + +## Select (address) bits for SRL32 shift registers used in stage3/stage4 +## calibration +INST "*/u_phy_calib/gen_gate_dly*.u_ff_gate_dly" TNM = "TNM_GATE_DLY"; +TIMESPEC "TS_MC_GATE_DLY" = FROM "TNM_GATE_DLY" TO "TNM_CLK0" +"TS_MC_CLK" * 4; + +INST "*/u_phy_calib/gen_rden_dly*.u_ff_rden_dly" TNM = "TNM_RDEN_DLY"; +TIMESPEC "TS_MC_RDEN_DLY" = FROM "TNM_RDEN_DLY" TO "TNM_CLK0" +"TS_MC_CLK" * 4; + +INST "*/u_phy_calib/gen_cal_rden_dly*.u_ff_cal_rden_dly" + TNM = "TNM_CAL_RDEN_DLY"; +TIMESPEC "TS_MC_CAL_RDEN_DLY" = FROM "TNM_CAL_RDEN_DLY" TO "TNM_CLK0" +"TS_MC_CLK" * 4; + +## MUX select for read data - optional delay on data to account for byte skews +INST "*/usr_rd/gen_rden_sel_mux*.u_ff_rden_sel_mux" TNM = "TNM_RDEN_SEL_MUX"; +TIMESPEC "TS_MC_RDEN_SEL_MUX" = FROM "TNM_RDEN_SEL_MUX" TO "TNM_CLK0" +"TS_MC_CLK" * 4; + +########################################################################### +## LOC placment of DQS-squelch related IDDR and IDELAY elements +## Each circuit can be located at any of the following locations: +## 1. Ununsed "N"-side of DQS diff pair I/O +## 2. DM data mask (output only, input side is free for use) +## 3. Any output-only site +########################################################################### + +INST "*/gen_dqs[0].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y96"; +INST "*/gen_dqs[0].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y96"; +INST "*/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y58"; +INST "*/gen_dqs[1].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y58"; +INST "*/gen_dqs[2].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y62"; +INST "*/gen_dqs[2].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y62"; +INST "*/gen_dqs[3].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y100"; +INST "*/gen_dqs[3].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y100"; +INST "*/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y102"; +INST "*/gen_dqs[4].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y102"; +INST "*/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y256"; +INST "*/gen_dqs[5].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y256"; +INST "*/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y260"; +INST "*/gen_dqs[6].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y260"; +INST "*/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y262"; +INST "*/gen_dqs[7].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y262"; + +########################################################################### +## DQS Squelch-related timing constraints +########################################################################### + +########################################################################### +## Half-cycle path constraint from IDDR to CE pin for all DQ IDDRs +## for DQS Read Postamble Glitch Squelch circuit +########################################################################### +## Max delay from output of IDDR to CE input of DQ IDDRs = tRPST + some slack +## where slack account for rise-time of DQS on board. For now assume slack = +## 0.400ns (based on initial SPICE simulations, assumes use of ODT), so +## time = 0.4*Tcyc + 0.40ns = 1.6ns @333MHz +INST "*/gen_dqs[*].u_iob_dqs/u_iddr_dq_ce" TNM = "TNM_DQ_CE_IDDR"; +INST "*/gen_dq[*].u_iob_dq/gen_stg2_*.u_iddr_dq" TNM = "TNM_DQS_FLOPS"; +TIMESPEC "TS_DQ_CE" = FROM "TNM_DQ_CE_IDDR" TO "TNM_DQS_FLOPS" 1.9 ns; + +########################################################################### +## LOC and timing constraints for flop driving DQS CE enable signal +## from fabric logic. Even though the absolute delay on this path is +## calibrated out (when synchronizing this output to DQS), the delay +## should still be kept as low as possible to reduce post-calibration +## voltage/temp variations - these are roughly proportional to the +## absolute delay of the path +########################################################################### + +INST "*/u_phy_calib/gen_gate[0].u_en_dqs_ff" LOC = SLICE_X0Y48; +INST "*/u_phy_calib/gen_gate[1].u_en_dqs_ff" LOC = SLICE_X0Y29; +INST "*/u_phy_calib/gen_gate[2].u_en_dqs_ff" LOC = SLICE_X0Y31; +INST "*/u_phy_calib/gen_gate[3].u_en_dqs_ff" LOC = SLICE_X0Y50; +INST "*/u_phy_calib/gen_gate[4].u_en_dqs_ff" LOC = SLICE_X0Y51; +INST "*/u_phy_calib/gen_gate[5].u_en_dqs_ff" LOC = SLICE_X0Y128; +INST "*/u_phy_calib/gen_gate[6].u_en_dqs_ff" LOC = SLICE_X0Y130; +INST "*/u_phy_calib/gen_gate[7].u_en_dqs_ff" LOC = SLICE_X0Y131; + +########################################################################### +## Control for DQS gate - from fabric flop. Prevent runaway delay - +## two parts to this path: (1) from fabric flop to IDELAY, (2) from +## IDELAY to asynchronous reset of IDDR that drives the DQ CEs +## A single number is used for all speed grades - value based on 333MHz. +## This can be relaxed for lower frequencies. +########################################################################### + +NET "*/u_phy_io/en_dqs*" MAXDELAY = 600 ps; +NET "*/u_phy_io/gen_dqs*.u_iob_dqs/en_dqs_sync" MAXDELAY = 850 ps; + +########################################################################### + +INST "*/gen_dq[0].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y42; +INST "*/gen_dq[1].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y43; +INST "*/gen_dq[2].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y45; +INST "*/gen_dq[3].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y46; +INST "*/gen_dq[4].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y41; +INST "*/gen_dq[5].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y42; +INST "*/gen_dq[6].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y44; +INST "*/gen_dq[7].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y44; +INST "*/gen_dq[8].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y28; +INST "*/gen_dq[9].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y32; +INST "*/gen_dq[10].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y33; +INST "*/gen_dq[11].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y34; +INST "*/gen_dq[12].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y26; +INST "*/gen_dq[13].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y28; +INST "*/gen_dq[14].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y33; +INST "*/gen_dq[15].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y34; +INST "*/gen_dq[16].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y35; +INST "*/gen_dq[17].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y36; +INST "*/gen_dq[18].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y38; +INST "*/gen_dq[19].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y39; +INST "*/gen_dq[20].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y36; +INST "*/gen_dq[21].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y37; +INST "*/gen_dq[22].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y38; +INST "*/gen_dq[23].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y39; +INST "*/gen_dq[24].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y46; +INST "*/gen_dq[25].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y49; +INST "*/gen_dq[26].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y53; +INST "*/gen_dq[27].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y55; +INST "*/gen_dq[28].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y49; +INST "*/gen_dq[29].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y52; +INST "*/gen_dq[30].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y54; +INST "*/gen_dq[31].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y56; +INST "*/gen_dq[32].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y52; +INST "*/gen_dq[33].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y56; +INST "*/gen_dq[34].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y58; +INST "*/gen_dq[35].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y59; +INST "*/gen_dq[36].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y54; +INST "*/gen_dq[37].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y57; +INST "*/gen_dq[38].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y58; +INST "*/gen_dq[39].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y59; +INST "*/gen_dq[40].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y120; +INST "*/gen_dq[41].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y121; +INST "*/gen_dq[42].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y122; +INST "*/gen_dq[43].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y123; +INST "*/gen_dq[44].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y120; +INST "*/gen_dq[45].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y121; +INST "*/gen_dq[46].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y123; +INST "*/gen_dq[47].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y124; +INST "*/gen_dq[48].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y124; +INST "*/gen_dq[49].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y126; +INST "*/gen_dq[50].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y132; +INST "*/gen_dq[51].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y133; +INST "*/gen_dq[52].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y125; +INST "*/gen_dq[53].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y126; +INST "*/gen_dq[54].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y133; +INST "*/gen_dq[55].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y134; +INST "*/gen_dq[56].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y134; +INST "*/gen_dq[57].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y136; +INST "*/gen_dq[58].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y137; +INST "*/gen_dq[59].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y138; +INST "*/gen_dq[60].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y135; +INST "*/gen_dq[61].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y136; +INST "*/gen_dq[62].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y138; +INST "*/gen_dq[63].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y139; + + +INST "DDR2_SDRAM/*/*u_rdf" LOC = RAMB36_X0Y19; +INST "DDR2_SDRAM/*/*u_rdf1" LOC = RAMB36_X0Y18; +INST "DDR2_SDRAM/*/*gen_wdf[0]*u_wdf" LOC = RAMB36_X0Y17; +INST "DDR2_SDRAM/*/*gen_wdf[1]*u_wdf" LOC = RAMB36_X0Y16; + + +############################################################################### + +# Prevent unrelated logic from being packed into any slices used + +# by read data capture RPM's - if unrelated logic gets packed into + +# these slices, it could cause the DIRT strings that define the + +# IDDR -> fabric flop routing to become unroutable during PAR stage + +# (unrelated logic may require routing resources required by the + +# DIRT strings - MAP does not currently take into account DIRT + +# strings when placing logic + +############################################################################### + +AREA_GROUP "DDR_CAPTURE_FFS" GROUP = CLOSED; + + + +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> LOC=G5 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> LOC=N7 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> LOC=N5 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> LOC=P5 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> LOC=R6 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> LOC=M6 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> LOC=L6 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin LOC=AH17 | IOSTANDARD = LVCMOS33 | PERIOD = 30000 ps; +Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin LOC=M7 | IOSTANDARD = LVCMOS33 | TIG; +Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin LOC=M5 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin LOC=N8 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin LOC=R9 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> LOC=P9 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> LOC=T8 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> LOC=J7 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> LOC=H7 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> LOC=R7 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> LOC=U7 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> LOC=P7 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> LOC=P6 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> LOC=R8 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> LOC=L5 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> LOC=L4 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> LOC=K6 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> LOC=J5 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> LOC=T6 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> LOC=K7 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> LOC=J6 | IOSTANDARD = LVCMOS33; +Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin; +TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz; +Net fpga_0_clk_1_sys_clk_pin LOC = AH15 | IOSTANDARD=LVCMOS33; +Net fpga_0_rst_1_sys_rst_pin TIG; +Net fpga_0_rst_1_sys_rst_pin LOC = E9 | IOSTANDARD=LVCMOS33 | PULLUP; +Net fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin LOC=AF4 | IOSTANDARD = LVDS_25; +Net fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin LOC=AF3 | IOSTANDARD = LVDS_25; diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/etc/bitgen.ut b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/etc/bitgen.ut new file mode 100644 index 000000000..9bdebfcf7 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/etc/bitgen.ut @@ -0,0 +1,14 @@ +-g TdoPin:PULLNONE +-g DriveDone:No +-g StartUpClk:JTAGCLK +-g DONE_cycle:4 +-g GTS_cycle:5 +-g TckPin:PULLUP +-g TdiPin:PULLUP +-g TmsPin:PULLUP +-g DonePipe:No +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:NONE +-g Persist:No + diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/etc/download.cmd b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/etc/download.cmd new file mode 100644 index 000000000..f46037346 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/etc/download.cmd @@ -0,0 +1,6 @@ +setMode -bscan
+setCable -p auto
+identify
+assignfile -p 5 -file implementation/download.bit
+program -p 5
+quit
diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/etc/fast_runtime.opt b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/etc/fast_runtime.opt new file mode 100644 index 000000000..52396f17f --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/etc/fast_runtime.opt @@ -0,0 +1,83 @@ +FLOWTYPE = FPGA; +############################################################### +## Filename: fast_runtime.opt +## +## Option File For Xilinx FPGA Implementation Flow for Fast +## Runtime. +## +## Version: 4.1.1 +############################################################### +# +# Options for Translator +# +# Type "ngdbuild -h" for a detailed list of ngdbuild command line options +# +Program ngdbuild +-p <partname>; # Partname to use - picked from xflow commandline +-nt timestamp; # NGO File generation. Regenerate only when + # source netlist is newer than existing + # NGO file (default) +-bm <design>.bmm # Block RAM memory map file +<userdesign>; # User design - pick from xflow command line +-uc <design>.ucf; # ucf constraints +<design>.ngd; # Name of NGD file. Filebase same as design filebase +End Program ngdbuild + +# +# Options for Mapper +# +# Type "map -h <arch>" for a detailed list of map command line options +# +Program map +-o <design>_map.ncd; # Output Mapped ncd file +-w; # Overwrite output files. +-pr b; # Pack internal FF/latches into IOBs +#-fp <design>.mfp; # Floorplan file +-ol high; +-timing; +<inputdir><design>.ngd; # Input NGD file +<inputdir><design>.pcf; # Physical constraints file +END Program map + +# +# Options for Post Map Trace +# +# Type "trce -h" for a detailed list of trce command line options +# +Program post_map_trce +-e 3; # Produce error report limited to 3 items per constraint +#-o <design>_map.twr; # Output trace report file +-xml <design>_map.twx; # Output XML version of the timing report +#-tsi <design>_map.tsi; # Produce Timing Specification Interaction report +<inputdir><design>_map.ncd; # Input mapped ncd +<inputdir><design>.pcf; # Physical constraints file +END Program post_map_trce + +# +# Options for Place and Route +# +# Type "par -h" for a detailed list of par command line options +# +Program par +-w; # Overwrite existing placed and routed ncd +-ol high; # Overall effort level +<inputdir><design>_map.ncd; # Input mapped NCD file +<design>.ncd; # Output placed and routed NCD +<inputdir><design>.pcf; # Input physical constraints file +END Program par + +# +# Options for Post Par Trace +# +# Type "trce -h" for a detailed list of trce command line options +# +Program post_par_trce +-e 3; # Produce error report limited to 3 items per constraint +#-o <design>.twr; # Output trace report file +-xml <design>.twx; # Output XML version of the timing report +#-tsi <design>.tsi; # Produce Timing Specification Interaction report +<inputdir><design>.ncd; # Input placed and routed ncd +<inputdir><design>.pcf; # Physical constraints file +END Program post_par_trce + + diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/etc/xmd_ppc440_0.opt b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/etc/xmd_ppc440_0.opt new file mode 100644 index 000000000..65076f3a8 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/etc/xmd_ppc440_0.opt @@ -0,0 +1 @@ +connect ppc hw -debugdevice cpunr 1
diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/platgen.opt b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/platgen.opt new file mode 100644 index 000000000..d8575bc54 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/platgen.opt @@ -0,0 +1,7 @@ +-p
+xc5vfx70tff1136-1
+-lang
+vhdl
+-msg
+__xps/ise/xmsgprops.lst
+system.mhs
diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/psf2Edward.log b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/psf2Edward.log new file mode 100644 index 000000000..276d7d645 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/psf2Edward.log @@ -0,0 +1,41 @@ +WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
+ C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+ 251 - deprecated core for architecture 'virtex5fx'! +WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
+ C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+ 296 - deprecated core for architecture 'virtex5fx'! +WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
+ C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+ 251 - deprecated core for architecture 'virtex5fx'! +WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
+ C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+ 296 - deprecated core for architecture 'virtex5fx'! + +Checking platform configuration ... +IPNAME:plb_v46 INSTANCE:plb_v46_0 -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+107 - 1 master(s) : 12 slave(s) +IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+288 - 1 master(s) : 1 slave(s) + +Checking port drivers... +WARNING:EDK:2099 - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -
+ C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+ 446 - floating connection! + +Performing Clock DRCs... + +Performing Reset DRCs... + +Overriding system level properties... + +Running system level update procedures... + +Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC... + +Running system level DRCs... + +Performing System level DRCs on properties... + +Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC... diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/revup/system_mhs.11.1 b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/revup/system_mhs.11.1 new file mode 100644 index 000000000..886583480 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/revup/system_mhs.11.1 @@ -0,0 +1,458 @@ +
+# ##############################################################################
+# Created by Base System Builder Wizard for Xilinx EDK 11.1 Build EDK_L.29.1
+# Thu Jun 11 19:28:07 2009
+# Target Board: Xilinx Virtex 5 ML507 Evaluation Platform Rev A
+# Family: virtex5
+# Device: xc5vfx70t
+# Package: ff1136
+# Speed Grade: -1
+# Processor number: 1
+# Processor 1: ppc440_0
+# Processor clock frequency: 125.0
+# Bus clock frequency: 125.0
+# Debug Interface: FPGA JTAG
+# ##############################################################################
+ PARAMETER VERSION = 2.1.0
+
+
+ PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX_pin, DIR = I
+ PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX_pin, DIR = O
+ PORT fpga_0_LEDs_8Bit_GPIO_IO_pin = fpga_0_LEDs_8Bit_GPIO_IO_pin, DIR = IO, VEC = [0:7]
+ PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO_pin, DIR = IO, VEC = [0:4]
+ PORT fpga_0_Push_Buttons_5Bit_GPIO_IO_pin = fpga_0_Push_Buttons_5Bit_GPIO_IO_pin, DIR = IO, VEC = [0:4]
+ PORT fpga_0_DIP_Switches_8Bit_GPIO_IO_pin = fpga_0_DIP_Switches_8Bit_GPIO_IO_pin, DIR = IO, VEC = [0:7]
+ PORT fpga_0_IIC_EEPROM_Sda_pin = fpga_0_IIC_EEPROM_Sda_pin, DIR = IO
+ PORT fpga_0_IIC_EEPROM_Scl_pin = fpga_0_IIC_EEPROM_Scl_pin, DIR = IO
+ PORT fpga_0_SRAM_Mem_A_pin = fpga_0_SRAM_Mem_A_pin_vslice_7_30_concat, DIR = O, VEC = [7:30]
+ PORT fpga_0_SRAM_Mem_CEN_pin = fpga_0_SRAM_Mem_CEN_pin, DIR = O
+ PORT fpga_0_SRAM_Mem_OEN_pin = fpga_0_SRAM_Mem_OEN_pin, DIR = O
+ PORT fpga_0_SRAM_Mem_WEN_pin = fpga_0_SRAM_Mem_WEN_pin, DIR = O
+ PORT fpga_0_SRAM_Mem_BEN_pin = fpga_0_SRAM_Mem_BEN_pin, DIR = O, VEC = [0:3]
+ PORT fpga_0_SRAM_Mem_ADV_LDN_pin = fpga_0_SRAM_Mem_ADV_LDN_pin, DIR = O
+ PORT fpga_0_SRAM_Mem_DQ_pin = fpga_0_SRAM_Mem_DQ_pin, DIR = IO, VEC = [0:31]
+ PORT fpga_0_SRAM_ZBT_CLK_OUT_pin = SRAM_CLK_OUT_s, DIR = O
+ PORT fpga_0_SRAM_ZBT_CLK_FB_pin = SRAM_CLK_FB_s, DIR = I, SIGIS = CLK, CLK_FREQ = 125000000
+ PORT fpga_0_PCIe_Bridge_RXN_pin = fpga_0_PCIe_Bridge_RXN_pin, DIR = I
+ PORT fpga_0_PCIe_Bridge_RXP_pin = fpga_0_PCIe_Bridge_RXP_pin, DIR = I
+ PORT fpga_0_PCIe_Bridge_TXN_pin = fpga_0_PCIe_Bridge_TXN_pin, DIR = O
+ PORT fpga_0_PCIe_Bridge_TXP_pin = fpga_0_PCIe_Bridge_TXP_pin, DIR = O
+ PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = fpga_0_Ethernet_MAC_PHY_tx_clk_pin, DIR = I
+ PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = fpga_0_Ethernet_MAC_PHY_rx_clk_pin, DIR = I
+ PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs_pin, DIR = I
+ PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv_pin, DIR = I
+ PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin = fpga_0_Ethernet_MAC_PHY_rx_data_pin, DIR = I, VEC = [3:0]
+ PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col_pin, DIR = I
+ PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er_pin, DIR = I
+ PORT fpga_0_Ethernet_MAC_PHY_rst_n_pin = fpga_0_Ethernet_MAC_PHY_rst_n_pin, DIR = O
+ PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en_pin, DIR = O
+ PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin = fpga_0_Ethernet_MAC_PHY_tx_data_pin, DIR = O, VEC = [3:0]
+ PORT fpga_0_Ethernet_MAC_MDINT_pin = fpga_0_Ethernet_MAC_MDINT_pin, DIR = I, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_LOW, INTERRUPT_PRIORITY = MEDIUM
+ PORT fpga_0_DDR2_SDRAM_DDR2_DQ_pin = fpga_0_DDR2_SDRAM_DDR2_DQ_pin, DIR = IO, VEC = [63:0]
+ PORT fpga_0_DDR2_SDRAM_DDR2_DQS_pin = fpga_0_DDR2_SDRAM_DDR2_DQS_pin, DIR = IO, VEC = [7:0]
+ PORT fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin = fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin, DIR = IO, VEC = [7:0]
+ PORT fpga_0_DDR2_SDRAM_DDR2_A_pin = fpga_0_DDR2_SDRAM_DDR2_A_pin, DIR = O, VEC = [12:0]
+ PORT fpga_0_DDR2_SDRAM_DDR2_BA_pin = fpga_0_DDR2_SDRAM_DDR2_BA_pin, DIR = O, VEC = [1:0]
+ PORT fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin = fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin, DIR = O
+ PORT fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin = fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin, DIR = O
+ PORT fpga_0_DDR2_SDRAM_DDR2_WE_N_pin = fpga_0_DDR2_SDRAM_DDR2_WE_N_pin, DIR = O
+ PORT fpga_0_DDR2_SDRAM_DDR2_CS_N_pin = fpga_0_DDR2_SDRAM_DDR2_CS_N_pin, DIR = O
+ PORT fpga_0_DDR2_SDRAM_DDR2_ODT_pin = fpga_0_DDR2_SDRAM_DDR2_ODT_pin, DIR = O, VEC = [1:0]
+ PORT fpga_0_DDR2_SDRAM_DDR2_CKE_pin = fpga_0_DDR2_SDRAM_DDR2_CKE_pin, DIR = O
+ PORT fpga_0_DDR2_SDRAM_DDR2_DM_pin = fpga_0_DDR2_SDRAM_DDR2_DM_pin, DIR = O, VEC = [7:0]
+ PORT fpga_0_DDR2_SDRAM_DDR2_CK_pin = fpga_0_DDR2_SDRAM_DDR2_CK_pin, DIR = O, VEC = [1:0]
+ PORT fpga_0_DDR2_SDRAM_DDR2_CK_N_pin = fpga_0_DDR2_SDRAM_DDR2_CK_N_pin, DIR = O, VEC = [1:0]
+ PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA_pin, DIR = O, VEC = [6:0]
+ PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK_pin, DIR = I
+ PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin, DIR = I
+ PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN_pin, DIR = O
+ PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN_pin, DIR = O
+ PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN_pin, DIR = O
+ PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD_pin, DIR = IO, VEC = [15:0]
+ PORT fpga_0_clk_1_sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
+ PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 0
+ PORT fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin = PCIe_Diff_Clk, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK
+ PORT fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin = PCIe_Diff_Clk, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK
+
+
+BEGIN ppc440_virtex5
+ PARAMETER INSTANCE = ppc440_0
+ PARAMETER C_IDCR_BASEADDR = 0b0000000000
+ PARAMETER C_IDCR_HIGHADDR = 0b0011111111
+ PARAMETER C_PPC440MC_ROW_CONFLICT_MASK = 0x003FFE00
+ PARAMETER C_PPC440MC_BANK_CONFLICT_MASK = 0x00C00000
+ PARAMETER C_PPC440MC_CONTROL = 0xF810008F
+ PARAMETER C_SPLB0_USE_MPLB_ADDR = 1
+ PARAMETER C_SPLB0_NUM_MPLB_ADDR_RNG = 1
+ PARAMETER C_SPLB1_NUM_MPLB_ADDR_RNG = 0
+ PARAMETER HW_VER = 1.01.a
+ PARAMETER C_SPLB0_RNG0_MPLB_BASEADDR = 0x80000000
+ PARAMETER C_SPLB0_RNG0_MPLB_HIGHADDR = 0xffffffff
+ PARAMETER C_SPLB0_RNG_MC_BASEADDR = 0x00000000
+ PARAMETER C_SPLB0_RNG_MC_HIGHADDR = 0x0fffffff
+ BUS_INTERFACE MPLB = plb_v46_0
+ BUS_INTERFACE SPLB0 = ppc440_0_SPLB0
+ BUS_INTERFACE PPC440MC = ppc440_0_PPC440MC
+ BUS_INTERFACE JTAGPPC = ppc440_0_jtagppc_bus
+ BUS_INTERFACE RESETPPC = ppc_reset_bus
+ PORT CPMC440CLK = clk_125_0000MHzPLL0
+ PORT CPMINTERCONNECTCLK = clk_125_0000MHzPLL0
+ PORT CPMINTERCONNECTCLKNTO1 = net_vcc
+ PORT EICC440EXTIRQ = ppc440_0_EICC440EXTIRQ
+ PORT CPMMCCLK = clk_125_0000MHzPLL0_ADJUST
+ PORT CPMPPCMPLBCLK = clk_125_0000MHzPLL0_ADJUST
+ PORT CPMPPCS0PLBCLK = clk_125_0000MHzPLL0_ADJUST
+END
+
+BEGIN plb_v46
+ PARAMETER INSTANCE = plb_v46_0
+ PARAMETER C_DCR_INTFCE = 0
+ PARAMETER C_FAMILY = virtex5
+ PARAMETER HW_VER = 1.04.a
+ PORT PLB_Clk = clk_125_0000MHzPLL0_ADJUST
+ PORT SYS_Rst = sys_bus_reset
+END
+
+BEGIN xps_bram_if_cntlr
+ PARAMETER INSTANCE = xps_bram_if_cntlr_1
+ PARAMETER C_SPLB_NATIVE_DWIDTH = 64
+ PARAMETER C_SPLB_SUPPORT_BURSTS = 1
+ PARAMETER C_SPLB_P2P = 0
+ PARAMETER C_FAMILY = virtex5
+ PARAMETER HW_VER = 1.00.b
+ PARAMETER C_BASEADDR = 0xffffe000
+ PARAMETER C_HIGHADDR = 0xffffffff
+ BUS_INTERFACE SPLB = plb_v46_0
+ BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
+END
+
+BEGIN bram_block
+ PARAMETER INSTANCE = xps_bram_if_cntlr_1_bram
+ PARAMETER C_FAMILY = virtex5
+ PARAMETER HW_VER = 1.00.a
+ BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
+END
+
+BEGIN xps_uartlite
+ PARAMETER INSTANCE = RS232_Uart_1
+ PARAMETER C_FAMILY = virtex5
+ PARAMETER C_BAUDRATE = 9600
+ PARAMETER C_DATA_BITS = 8
+ PARAMETER C_USE_PARITY = 0
+ PARAMETER C_ODD_PARITY = 0
+ PARAMETER HW_VER = 1.01.a
+ PARAMETER C_BASEADDR = 0x84000000
+ PARAMETER C_HIGHADDR = 0x8400ffff
+ BUS_INTERFACE SPLB = plb_v46_0
+ PORT RX = fpga_0_RS232_Uart_1_RX_pin
+ PORT TX = fpga_0_RS232_Uart_1_TX_pin
+ PORT Interrupt = RS232_Uart_1_Interrupt
+END
+
+BEGIN xps_gpio
+ PARAMETER INSTANCE = LEDs_8Bit
+ PARAMETER C_FAMILY = virtex5
+ PARAMETER C_ALL_INPUTS = 0
+ PARAMETER C_GPIO_WIDTH = 8
+ PARAMETER C_INTERRUPT_PRESENT = 0
+ PARAMETER C_IS_DUAL = 0
+ PARAMETER HW_VER = 2.00.a
+ PARAMETER C_BASEADDR = 0x81440000
+ PARAMETER C_HIGHADDR = 0x8144ffff
+ BUS_INTERFACE SPLB = plb_v46_0
+ PORT GPIO_IO = fpga_0_LEDs_8Bit_GPIO_IO_pin
+END
+
+BEGIN xps_gpio
+ PARAMETER INSTANCE = LEDs_Positions
+ PARAMETER C_FAMILY = virtex5
+ PARAMETER C_ALL_INPUTS = 0
+ PARAMETER C_GPIO_WIDTH = 5
+ PARAMETER C_INTERRUPT_PRESENT = 0
+ PARAMETER C_IS_DUAL = 0
+ PARAMETER HW_VER = 2.00.a
+ PARAMETER C_BASEADDR = 0x81420000
+ PARAMETER C_HIGHADDR = 0x8142ffff
+ BUS_INTERFACE SPLB = plb_v46_0
+ PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO_pin
+END
+
+BEGIN xps_gpio
+ PARAMETER INSTANCE = Push_Buttons_5Bit
+ PARAMETER C_FAMILY = virtex5
+ PARAMETER C_ALL_INPUTS = 1
+ PARAMETER C_GPIO_WIDTH = 5
+ PARAMETER C_INTERRUPT_PRESENT = 0
+ PARAMETER C_IS_DUAL = 0
+ PARAMETER HW_VER = 2.00.a
+ PARAMETER C_BASEADDR = 0x81400000
+ PARAMETER C_HIGHADDR = 0x8140ffff
+ BUS_INTERFACE SPLB = plb_v46_0
+ PORT GPIO_IO = fpga_0_Push_Buttons_5Bit_GPIO_IO_pin
+END
+
+BEGIN xps_gpio
+ PARAMETER INSTANCE = DIP_Switches_8Bit
+ PARAMETER C_FAMILY = virtex5
+ PARAMETER C_ALL_INPUTS = 1
+ PARAMETER C_GPIO_WIDTH = 8
+ PARAMETER C_INTERRUPT_PRESENT = 0
+ PARAMETER C_IS_DUAL = 0
+ PARAMETER HW_VER = 2.00.a
+ PARAMETER C_BASEADDR = 0x81460000
+ PARAMETER C_HIGHADDR = 0x8146ffff
+ BUS_INTERFACE SPLB = plb_v46_0
+ PORT GPIO_IO = fpga_0_DIP_Switches_8Bit_GPIO_IO_pin
+END
+
+BEGIN xps_iic
+ PARAMETER INSTANCE = IIC_EEPROM
+ PARAMETER C_IIC_FREQ = 100000
+ PARAMETER C_TEN_BIT_ADR = 0
+ PARAMETER C_FAMILY = virtex5
+ PARAMETER HW_VER = 2.01.a
+ PARAMETER C_BASEADDR = 0x81600000
+ PARAMETER C_HIGHADDR = 0x8160ffff
+ BUS_INTERFACE SPLB = plb_v46_0
+ PORT Sda = fpga_0_IIC_EEPROM_Sda_pin
+ PORT Scl = fpga_0_IIC_EEPROM_Scl_pin
+END
+
+BEGIN xps_mch_emc
+ PARAMETER INSTANCE = SRAM
+ PARAMETER C_FAMILY = virtex5
+ PARAMETER C_NUM_BANKS_MEM = 1
+ PARAMETER C_NUM_CHANNELS = 0
+ PARAMETER C_MEM0_WIDTH = 32
+ PARAMETER C_MAX_MEM_WIDTH = 32
+ PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 0
+ PARAMETER C_SYNCH_MEM_0 = 1
+ PARAMETER C_TCEDV_PS_MEM_0 = 0
+ PARAMETER C_TAVDV_PS_MEM_0 = 0
+ PARAMETER C_THZCE_PS_MEM_0 = 0
+ PARAMETER C_THZOE_PS_MEM_0 = 0
+ PARAMETER C_TWC_PS_MEM_0 = 0
+ PARAMETER C_TWP_PS_MEM_0 = 0
+ PARAMETER C_TLZWE_PS_MEM_0 = 0
+ PARAMETER HW_VER = 3.00.a
+ PARAMETER C_MEM0_BASEADDR = 0xf8000000
+ PARAMETER C_MEM0_HIGHADDR = 0xf80fffff
+ BUS_INTERFACE SPLB = plb_v46_0
+ PORT RdClk = clk_125_0000MHzPLL0_ADJUST
+ PORT Mem_A = 0b0000000 & fpga_0_SRAM_Mem_A_pin_vslice_7_30_concat & 0b0
+ PORT Mem_CEN = fpga_0_SRAM_Mem_CEN_pin
+ PORT Mem_OEN = fpga_0_SRAM_Mem_OEN_pin
+ PORT Mem_WEN = fpga_0_SRAM_Mem_WEN_pin
+ PORT Mem_BEN = fpga_0_SRAM_Mem_BEN_pin
+ PORT Mem_ADV_LDN = fpga_0_SRAM_Mem_ADV_LDN_pin
+ PORT Mem_DQ = fpga_0_SRAM_Mem_DQ_pin
+END
+
+BEGIN plbv46_pcie
+ PARAMETER INSTANCE = PCIe_Bridge
+ PARAMETER C_FAMILY = virtex5
+ PARAMETER C_IPIFBAR_NUM = 2
+ PARAMETER C_PCIBAR_NUM = 1
+ PARAMETER C_DEVICE_ID = 0x0505
+ PARAMETER C_VENDOR_ID = 0x10EE
+ PARAMETER C_CLASS_CODE = 0x058000
+ PARAMETER C_REV_ID = 0x00
+ PARAMETER C_SUBSYSTEM_ID = 0x0000
+ PARAMETER C_SUBSYSTEM_VENDOR_ID = 0x0000
+ PARAMETER C_COMP_TIMEOUT = 1
+ PARAMETER C_IPIFBAR2PCIBAR_0 = 0x00000000
+ PARAMETER C_IPIFBAR2PCIBAR_1 = 0x00000000
+ PARAMETER C_PCIBAR2IPIFBAR_0 = 0xf8000000
+ PARAMETER C_PCIBAR2IPIFBAR_1 = 0x00000000
+ PARAMETER C_PCIBAR_LEN_0 = 20
+ PARAMETER C_PCIBAR_LEN_1 = 28
+ PARAMETER C_BOARD = ml507
+ PARAMETER HW_VER = 3.00.b
+ PARAMETER C_BASEADDR = 0x85c00000
+ PARAMETER C_HIGHADDR = 0x85c0ffff
+ PARAMETER C_IPIFBAR_0 = 0xc0000000
+ PARAMETER C_IPIFBAR_HIGHADDR_0 = 0xdfffffff
+ PARAMETER C_IPIFBAR_1 = 0xe0000000
+ PARAMETER C_IPIFBAR_HIGHADDR_1 = 0xefffffff
+ BUS_INTERFACE SPLB = plb_v46_0
+ BUS_INTERFACE MPLB = ppc440_0_SPLB0
+ PORT PERSTN = net_vcc
+ PORT REFCLK = PCIe_Diff_Clk
+ PORT RXN = fpga_0_PCIe_Bridge_RXN_pin
+ PORT RXP = fpga_0_PCIe_Bridge_RXP_pin
+ PORT TXN = fpga_0_PCIe_Bridge_TXN_pin
+ PORT TXP = fpga_0_PCIe_Bridge_TXP_pin
+ PORT MSI_request = net_gnd
+END
+
+BEGIN plb_v46
+ PARAMETER INSTANCE = ppc440_0_SPLB0
+ PARAMETER C_FAMILY = virtex5
+ PARAMETER HW_VER = 1.04.a
+ PORT PLB_Clk = clk_125_0000MHzPLL0_ADJUST
+ PORT SYS_Rst = sys_bus_reset
+END
+
+BEGIN xps_ethernetlite
+ PARAMETER INSTANCE = Ethernet_MAC
+ PARAMETER C_FAMILY = virtex5
+ PARAMETER HW_VER = 2.01.a
+ PARAMETER C_BASEADDR = 0x81000000
+ PARAMETER C_HIGHADDR = 0x8100ffff
+ BUS_INTERFACE SPLB = plb_v46_0
+ PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk_pin
+ PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk_pin
+ PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs_pin
+ PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv_pin
+ PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data_pin
+ PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col_pin
+ PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er_pin
+ PORT PHY_rst_n = fpga_0_Ethernet_MAC_PHY_rst_n_pin
+ PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en_pin
+ PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data_pin
+END
+
+BEGIN ppc440mc_ddr2
+ PARAMETER INSTANCE = DDR2_SDRAM
+ PARAMETER C_DDR_BAWIDTH = 2
+ PARAMETER C_NUM_CLK_PAIRS = 2
+ PARAMETER C_DDR_DWIDTH = 64
+ PARAMETER C_DDR_CAWIDTH = 10
+ PARAMETER C_NUM_RANKS_MEM = 1
+ PARAMETER C_CS_BITS = 0
+ PARAMETER C_DDR_DM_WIDTH = 8
+ PARAMETER C_DQ_BITS = 8
+ PARAMETER C_DDR2_ODT_WIDTH = 2
+ PARAMETER C_DDR2_ADDT_LAT = 0
+ PARAMETER C_INCLUDE_ECC_SUPPORT = 0
+ PARAMETER C_DDR2_ODT_SETTING = 1
+ PARAMETER C_DQS_BITS = 3
+ PARAMETER C_DDR_DQS_WIDTH = 8
+ PARAMETER C_DDR_RAWIDTH = 13
+ PARAMETER C_DDR_BURST_LENGTH = 4
+ PARAMETER C_DDR_CAS_LAT = 4
+ PARAMETER C_REG_DIMM = 0
+ PARAMETER C_MIB_MC_CLOCK_RATIO = 1
+ PARAMETER C_DDR_TREFI = 3900
+ PARAMETER C_DDR_TRAS = 40000
+ PARAMETER C_DDR_TRCD = 15000
+ PARAMETER C_DDR_TRFC = 75000
+ PARAMETER C_DDR_TRP = 15000
+ PARAMETER C_DDR_TRTP = 7500
+ PARAMETER C_DDR_TWR = 15000
+ PARAMETER C_DDR_TWTR = 7500
+ PARAMETER C_MC_MIBCLK_PERIOD_PS = 8000
+ PARAMETER C_IDEL_HIGH_PERF = TRUE
+ PARAMETER C_NUM_IDELAYCTRL = 3
+ PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y6-IDELAYCTRL_X0Y2-IDELAYCTRL_X0Y1
+ PARAMETER C_DQS_IO_COL = 0b000000000000000000
+ PARAMETER C_DQ_IO_MS = 0b000000000111010100111101000011110001111000101110110000111100000110111100
+ PARAMETER HW_VER = 2.00.a
+ PARAMETER C_MEM_BASEADDR = 0x00000000
+ PARAMETER C_MEM_HIGHADDR = 0x0fffffff
+ BUS_INTERFACE PPC440MC = ppc440_0_PPC440MC
+ PORT mc_mibclk = clk_125_0000MHzPLL0_ADJUST
+ PORT mi_mcclk90 = clk_125_0000MHz90PLL0_ADJUST
+ PORT mi_mcreset = sys_bus_reset
+ PORT mi_mcclkdiv2 = clk_62_5000MHzPLL0_ADJUST
+ PORT mi_mcclk_200 = clk_200_0000MHz
+ PORT DDR2_DQ = fpga_0_DDR2_SDRAM_DDR2_DQ_pin
+ PORT DDR2_DQS = fpga_0_DDR2_SDRAM_DDR2_DQS_pin
+ PORT DDR2_DQS_N = fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin
+ PORT DDR2_A = fpga_0_DDR2_SDRAM_DDR2_A_pin
+ PORT DDR2_BA = fpga_0_DDR2_SDRAM_DDR2_BA_pin
+ PORT DDR2_RAS_N = fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin
+ PORT DDR2_CAS_N = fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin
+ PORT DDR2_WE_N = fpga_0_DDR2_SDRAM_DDR2_WE_N_pin
+ PORT DDR2_CS_N = fpga_0_DDR2_SDRAM_DDR2_CS_N_pin
+ PORT DDR2_ODT = fpga_0_DDR2_SDRAM_DDR2_ODT_pin
+ PORT DDR2_CKE = fpga_0_DDR2_SDRAM_DDR2_CKE_pin
+ PORT DDR2_DM = fpga_0_DDR2_SDRAM_DDR2_DM_pin
+ PORT DDR2_CK = fpga_0_DDR2_SDRAM_DDR2_CK_pin
+ PORT DDR2_CK_N = fpga_0_DDR2_SDRAM_DDR2_CK_N_pin
+END
+
+BEGIN xps_sysace
+ PARAMETER INSTANCE = SysACE_CompactFlash
+ PARAMETER C_MEM_WIDTH = 16
+ PARAMETER C_FAMILY = virtex5
+ PARAMETER HW_VER = 1.01.a
+ PARAMETER C_BASEADDR = 0x83600000
+ PARAMETER C_HIGHADDR = 0x8360ffff
+ BUS_INTERFACE SPLB = plb_v46_0
+ PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA_pin
+ PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK_pin
+ PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin
+ PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN_pin
+ PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN_pin
+ PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN_pin
+ PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD_pin
+END
+
+BEGIN clock_generator
+ PARAMETER INSTANCE = clock_generator_0
+ PARAMETER C_CLKIN_FREQ = 100000000
+ PARAMETER C_CLKFBIN_FREQ = 125000000
+ PARAMETER C_CLKOUT0_FREQ = 125000000
+ PARAMETER C_CLKOUT0_PHASE = 90
+ PARAMETER C_CLKOUT0_GROUP = PLL0_ADJUST
+ PARAMETER C_CLKOUT0_BUF = TRUE
+ PARAMETER C_CLKOUT1_FREQ = 125000000
+ PARAMETER C_CLKOUT1_PHASE = 0
+ PARAMETER C_CLKOUT1_GROUP = PLL0
+ PARAMETER C_CLKOUT1_BUF = TRUE
+ PARAMETER C_CLKOUT2_FREQ = 125000000
+ PARAMETER C_CLKOUT2_PHASE = 0
+ PARAMETER C_CLKOUT2_GROUP = PLL0_ADJUST
+ PARAMETER C_CLKOUT2_BUF = TRUE
+ PARAMETER C_CLKOUT3_FREQ = 200000000
+ PARAMETER C_CLKOUT3_PHASE = 0
+ PARAMETER C_CLKOUT3_GROUP = NONE
+ PARAMETER C_CLKOUT3_BUF = TRUE
+ PARAMETER C_CLKOUT4_FREQ = 62500000
+ PARAMETER C_CLKOUT4_PHASE = 0
+ PARAMETER C_CLKOUT4_GROUP = PLL0_ADJUST
+ PARAMETER C_CLKOUT4_BUF = TRUE
+ PARAMETER C_CLKFBOUT_FREQ = 125000000
+ PARAMETER C_CLKFBOUT_BUF = TRUE
+ PARAMETER HW_VER = 3.00.a
+ PORT CLKIN = dcm_clk_s
+ PORT CLKFBIN = SRAM_CLK_FB_s
+ PORT CLKOUT0 = clk_125_0000MHz90PLL0_ADJUST
+ PORT CLKOUT1 = clk_125_0000MHzPLL0
+ PORT CLKOUT2 = clk_125_0000MHzPLL0_ADJUST
+ PORT CLKOUT3 = clk_200_0000MHz
+ PORT CLKOUT4 = clk_62_5000MHzPLL0_ADJUST
+ PORT CLKFBOUT = SRAM_CLK_OUT_s
+ PORT RST = net_gnd
+ PORT LOCKED = Dcm_all_locked
+END
+
+BEGIN jtagppc_cntlr
+ PARAMETER INSTANCE = jtagppc_cntlr_inst
+ PARAMETER HW_VER = 2.01.c
+ BUS_INTERFACE JTAGPPC0 = ppc440_0_jtagppc_bus
+END
+
+BEGIN proc_sys_reset
+ PARAMETER INSTANCE = proc_sys_reset_0
+ PARAMETER C_EXT_RESET_HIGH = 0
+ PARAMETER HW_VER = 2.00.a
+ BUS_INTERFACE RESETPPC0 = ppc_reset_bus
+ PORT Slowest_sync_clk = clk_125_0000MHzPLL0_ADJUST
+ PORT Ext_Reset_In = sys_rst_s
+ PORT Dcm_locked = Dcm_all_locked
+ PORT Bus_Struct_Reset = sys_bus_reset
+ PORT Peripheral_Reset = sys_periph_reset
+END
+
+BEGIN xps_intc
+ PARAMETER INSTANCE = xps_intc_0
+ PARAMETER HW_VER = 2.00.a
+ PARAMETER C_BASEADDR = 0x81800000
+ PARAMETER C_HIGHADDR = 0x8180ffff
+ BUS_INTERFACE SPLB = plb_v46_0
+ PORT Intr = fpga_0_Ethernet_MAC_MDINT_pin&RS232_Uart_1_Interrupt
+ PORT Irq = ppc440_0_EICC440EXTIRQ
+END
+
diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/revup/system_mss.11.1 b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/revup/system_mss.11.1 new file mode 100644 index 000000000..188abc721 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/revup/system_mss.11.1 @@ -0,0 +1,125 @@ +
+ PARAMETER VERSION = 2.2.0
+
+
+BEGIN OS
+ PARAMETER OS_NAME = standalone
+ PARAMETER OS_VER = 2.00.a
+ PARAMETER PROC_INSTANCE = ppc440_0
+ PARAMETER STDIN = RS232_Uart_1
+ PARAMETER STDOUT = RS232_Uart_1
+END
+
+
+BEGIN PROCESSOR
+ PARAMETER DRIVER_NAME = cpu_ppc440
+ PARAMETER DRIVER_VER = 1.00.b
+ PARAMETER HW_INSTANCE = ppc440_0
+ PARAMETER COMPILER = powerpc-eabi-gcc
+ PARAMETER ARCHIVER = powerpc-eabi-ar
+END
+
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = bram
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = xps_bram_if_cntlr_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = xps_bram_if_cntlr_1_bram
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = uartlite
+ PARAMETER DRIVER_VER = 1.14.a
+ PARAMETER HW_INSTANCE = RS232_Uart_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = gpio
+ PARAMETER DRIVER_VER = 2.13.a
+ PARAMETER HW_INSTANCE = LEDs_8Bit
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = gpio
+ PARAMETER DRIVER_VER = 2.13.a
+ PARAMETER HW_INSTANCE = LEDs_Positions
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = gpio
+ PARAMETER DRIVER_VER = 2.13.a
+ PARAMETER HW_INSTANCE = Push_Buttons_5Bit
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = gpio
+ PARAMETER DRIVER_VER = 2.13.a
+ PARAMETER HW_INSTANCE = DIP_Switches_8Bit
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = iic
+ PARAMETER DRIVER_VER = 1.14.a
+ PARAMETER HW_INSTANCE = IIC_EEPROM
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = emc
+ PARAMETER DRIVER_VER = 2.00.a
+ PARAMETER HW_INSTANCE = SRAM
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = pcie
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = PCIe_Bridge
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = emaclite
+ PARAMETER DRIVER_VER = 1.14.a
+ PARAMETER HW_INSTANCE = Ethernet_MAC
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = memcon
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = DDR2_SDRAM
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = sysace
+ PARAMETER DRIVER_VER = 1.12.a
+ PARAMETER HW_INSTANCE = SysACE_CompactFlash
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = clock_generator_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = jtagppc_cntlr_inst
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = proc_sys_reset_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = intc
+ PARAMETER DRIVER_VER = 1.11.a
+ PARAMETER HW_INSTANCE = xps_intc_0
+END
+
+
diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/revup/system_xmp.11.1 b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/revup/system_xmp.11.1 new file mode 100644 index 000000000..406959b34 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/revup/system_xmp.11.1 @@ -0,0 +1,69 @@ +#Please do not modify this file by hand
+XmpVersion: 11.1
+VerMgmt: 11.1
+IntStyle: default
+MHS File: system.mhs
+MSS File: system.mss
+Architecture: virtex5
+Device: xc5vfx70t
+Package: ff1136
+SpeedGrade: -1
+UserCmd1:
+UserCmd1Type: 0
+UserCmd2:
+UserCmd2Type: 0
+GenSimTB: 0
+SdkExportBmmBit: 1
+SdkExportDir: SDK/SDK_Export
+InsertNoPads: 0
+WarnForEAArch: 1
+HdlLang: VHDL
+SimModel: BEHAVIORAL
+UcfFile: data/system.ucf
+EnableParTimingError: 1
+ShowLicenseDialog: 1
+Processor: ppc440_0
+BootLoop: 1
+XmdStub: 0
+SwProj: RTOSDemo
+Processor: ppc440_0
+Executable: RTOSDemo/executable.elf
+Source: RTOSDemo/../../Common/Minimal/BlockQ.c
+Source: RTOSDemo/../../Common/Minimal/blocktim.c
+Source: RTOSDemo/../../Common/Minimal/comtest.c
+Source: RTOSDemo/../../Common/Minimal/countsem.c
+Source: RTOSDemo/../../Common/Minimal/death.c
+Source: RTOSDemo/../../Common/Minimal/dynamic.c
+Source: RTOSDemo/../../Common/Minimal/flash.c
+Source: RTOSDemo/../../Common/Minimal/GenQTest.c
+Source: RTOSDemo/../../Common/Minimal/integer.c
+Source: RTOSDemo/../../Common/Minimal/QPeek.c
+Source: RTOSDemo/../../Common/Minimal/recmutex.c
+Source: RTOSDemo/../../Common/Minimal/semtest.c
+Source: RTOSDemo/../../../Source/tasks.c
+Source: RTOSDemo/../../../Source/list.c
+Source: RTOSDemo/../../../Source/queue.c
+Source: RTOSDemo/../../../Source/croutine.c
+Source: RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S
+Source: RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c
+Source: RTOSDemo/../../../Source/portable/MemMang/heap_2.c
+Source: RTOSDemo/flop/flop-reg-test.c
+Source: RTOSDemo/flop/flop.c
+Source: RTOSDemo/partest/partest.c
+Source: RTOSDemo/serial/serial.c
+Source: RTOSDemo/main.c
+DefaultInit: EXECUTABLE
+InitBram: 0
+Active: 1
+CompilerOptLevel: 0
+GlobPtrOpt: 0
+DebugSym: 1
+ProfileFlag: 0
+SearchIncl: ../../Source/include ../Common/include ./RTOSDemo ./RTOSDemo/flop
+ProgStart:
+StackSize:
+HeapSize:
+LinkerScript: RTOSDemo/RTOSDemo_linker_script.ld
+ProgCCFlags: -D GCC_PPC440 -mregnames
+CompileInXps: 1
+NonXpsApp: 0
diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/system.bsb b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/system.bsb new file mode 100644 index 000000000..8ebdf68ef --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/system.bsb @@ -0,0 +1 @@ + „æÄ®Òôtt¦Êè¬ÊäæÒÞÜ@Dbb\b\`bDvC„æÄ®Òôtt¦Êè„ÞÂäÈ@D°ÒØÒÜðD@D¬ÒäèÊð@j@š˜j`n@ŠìÂØêÂèÒÞÜ@ ØÂèÌÞäÚD@D‚Dv-„æÄ®ÒôttªàÈÂèÊ„ÞÂäÈ@D‚¤†’¨Š†¨ª¤ŠD@DìÒäèÊðjDv.„æÄ®ÒôttªàÈÂèÊ„ÞÂäÈ@DˆŠ¬’†Š¾¦’´ŠD@DðÆjìÌðn`èDv'„æÄ®ÒôttªàÈÂèÊ„ÞÂäÈ@D ‚†–‚ŽŠD@DÌÌbbflDv'„æÄ®ÒôttªàÈÂèÊ„ÞÂäÈ@D¤¦¨¾ ž˜‚¤’¨²D@D`Dv&„æÄ®ÒôttªàÈÂèÊ„ÞÂäÈ@D¦ ŠŠˆŽ¤‚ˆŠD@DZbDv$„æÄ®Òôtt¦Êè¦òæèÊÚ@DààÆhh`D@Db\``\ÂDv8„æÄ®ÒôttªàÈÂèʦòæèÊÚ@D„ª¦¾Œ¤Š¢D@Dbdj\``````D@DààÆhh`¾`Dv8„æÄ®ÒôttªàÈÂèʦòæèÊÚ@D†˜–¾Œ¤Š¢D@Db``\``````D@DààÆhh`¾`Dv9„æÄ®ÒôttªàÈÂèʦòæèÊÚ@D ¤ž†¾Œ¤Š¢D@Dbdj\``````D@DààÆhh`¾`Dv4„æÄ®Òôtt‚ÈÈ äÞÆÊææÞä@DààÆhh`¾`D@D †hh`D@DààÆhh`¾`Dv6„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DààÆhh`¾`D@D†‚†ŠD@Dœž@†‚†ŠDv3„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DààÆhh`¾`D@D†¾ª¦Š¾Œ ªD@D`Dv6„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DààÆhh`¾`D@Dˆž†š@¦’´ŠD@DœÞÜÊDv6„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DààÆhh`¾`D@D’ž†š@¦’´ŠD@DœÞÜÊDv>„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@Dˆˆ¤d¾¦ˆ¤‚šD@DààÆhh`ÚƾÈÈädD@DààÆhh`¾`Dv@„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@Dˆ’ ¾¦îÒèÆÐÊæ¾p„ÒèD@Dðàæ¾ÎàÒÞD@DààÆhh`¾`DvF„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@Dˆ’ ¾¦îÒèÆÐÊæ¾p„ÒèD@DŽ¾ª¦Š¾’œ¨Š¤¤ª ¨D@DŒ‚˜¦ŠDvC„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@DŠèÐÊäÜÊ辚‚†D@Dðàæ¾ÊèÐÊäÜÊèØÒèÊD@DààÆhh`¾`DvA„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DŠèÐÊäÜÊ辚‚†D@DŽ¾ª¦Š¾’œ¨Š¤¤ª ¨D@DŒ‚˜¦ŠDv8„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@D’’†¾ŠŠ ¤žšD@Dðàæ¾ÒÒÆD@DààÆhh`¾`Dv?„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D’’†¾ŠŠ ¤žšD@DŽ¾ª¦Š¾’œ¨Š¤¤ª ¨D@DŒ‚˜¦ŠDv8„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@D˜Šˆæ¾p„ÒèD@Dðàæ¾ÎàÒÞD@DààÆhh`¾`Dv>„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D˜Šˆæ¾p„ÒèD@DŽ¾ª¦Š¾’œ¨Š¤¤ª ¨D@DŒ‚˜¦ŠDv=„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@D˜Šˆæ¾ ÞæÒèÒÞÜæD@Dðàæ¾ÎàÒÞD@DààÆhh`¾`DvC„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D˜Šˆæ¾ ÞæÒèÒÞÜæD@DŽ¾ª¦Š¾’œ¨Š¤¤ª ¨D@DŒ‚˜¦ŠDv=„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@D †’ʾ„äÒÈÎÊD@DàØÄìhl¾àÆÒÊD@DààÆhh`¾`Dv:„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D †’ʾ„äÒÈÎÊD@DŽ¾ª¦Š¾ˆš‚D@DŒ‚˜¦ŠDv@„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D †’ʾ„äÒÈÎÊD@DŽ¾ª¦Š¾’œ¨Š¤¤ª ¨D@DŒ‚˜¦ŠDv@„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@D êæо„êèèÞÜæ¾j„ÒèD@Dðàæ¾ÎàÒÞD@DààÆhh`¾`DvF„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D êæо„êèèÞÜæ¾j„ÒèD@DŽ¾ª¦Š¾’œ¨Š¤¤ª ¨D@DŒ‚˜¦ŠDv?„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@D¤¦dfd¾ªÂäè¾bD@Dðàæ¾êÂäèØÒèÊD@DààÆhh`¾`Dv;„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäè¾bD@D†¾„‚ªˆ¤‚¨ŠD@Drl``Dv9„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäè¾bD@D†¾ˆ‚¨‚¾„’¨¦D@DpDv9„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäè¾bD@DŽ¾ ‚¤’¨²D@DœÞÜÊDvA„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäè¾bD@DŽ¾ª¦Š¾’œ¨Š¤¤ª ¨D@DŒ‚˜¦ŠDv6„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@D¦¤‚šD@Dðàæ¾ÚÆоÊÚÆD@DààÆhh`¾`DvD„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@D¦ò悆Š¾†ÞÚàÂÆèŒØÂæÐD@Dðàæ¾æòæÂÆÊD@DààÆhh`¾`DvH„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¦ò悆Š¾†ÞÚàÂÆèŒØÂæÐD@DŽ¾ª¦Š¾’œ¨Š¤¤ª ¨D@DŒ‚˜¦ŠDvK„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@Dðàæ¾ÄäÂÚ¾Ò̾ÆÜèØä¾bD@Dðàæ¾ÄäÂÚ¾Ò̾ÆÜèØäD@DààÆhh`¾`DvB„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@Dðàæ¾ÄäÂÚ¾Ò̾ÆÜèØä¾bD@DŽ¾šŠš¾¦’´ŠD@Dp@–„DvS„æÄ®ÒôttªàÈÂèʦ®@D¦®¾ŽŠœŠ¤‚¨Š¾šŠš¨Š¦¨D@D¨¤ªŠD@D¨Êæè‚àྚÊÚÞäò¾ààÆhh`¾`D@DààÆhh`¾`DvS„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྚÊÚÞäò¾ààÆhh`¾`D@D¦®¾„žž¨šŠšD@Dðàæ¾ÄäÂÚ¾Ò̾ÆÜèØä¾bDvK„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྚÊÚÞäò¾ààÆhh`¾`D@D¦®¾„žž¨¾ ‚¤D@D†¾„‚¦Š‚ˆˆ¤DvT„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྚÊÚÞäò¾ààÆhh`¾`D@D¦®¾ˆ‚¨‚¾’œ¦D@Dðàæ¾ÄäÂÚ¾Ò̾ÆÜèØä¾bDvK„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྚÊÚÞäò¾ààÆhh`¾`D@D¦®¾ˆ‚¨‚¾ ‚¤D@D†¾„‚¦Š‚ˆˆ¤DvT„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྚÊÚÞäò¾ààÆhh`¾`D@D¦®¾Š‚ ¾’œ¦D@Dðàæ¾ÄäÂÚ¾Ò̾ÆÜèØä¾bDvK„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྚÊÚÞäò¾ààÆhh`¾`D@D¦®¾Š‚ ¾ ‚¤D@D†¾„‚¦Š‚ˆˆ¤DvW„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྚÊÚÞäò¾ààÆhh`¾`D@D¦®¾ ¤žŽ¤‚š¾’œ¦D@Dðàæ¾ÄäÂÚ¾Ò̾ÆÜèØä¾bDvN„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྚÊÚÞäò¾ààÆhh`¾`D@D¦®¾ ¤žŽ¤‚š¾ ‚¤D@D†¾„‚¦Š‚ˆˆ¤DvU„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྚÊÚÞäò¾ààÆhh`¾`D@D¦®¾¦¨‚†–¾’œ¦D@Dðàæ¾ÄäÂÚ¾Ò̾ÆÜèØä¾bDvL„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྚÊÚÞäò¾ààÆhh`¾`D@D¦®¾¦¨‚†–¾ ‚¤D@D†¾„‚¦Š‚ˆˆ¤DvJ„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྚÊÚÞäò¾ààÆhh`¾`D@D¦®¾¦¨ˆ’œD@D¤¦dfd¾ªÂäè¾bDvK„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྚÊÚÞäò¾ààÆhh`¾`D@D¦®¾¦¨ˆžª¨D@D¤¦dfd¾ªÂäè¾bDvH„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྚÊÚÞäò¾ààÆhh`¾`D@D¦®¾¬Š†¨ž¤¦¾’œ¦D@D¦¤‚šDvS„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྚÊÚÞäò¾ààÆhh`¾`D@D¦®¾¬Š†¨ž¤¦¾ ‚¤D@D†¾šŠš`¾„‚¦Š‚ˆˆ¤DvZ„æÄ®ÒôttªàÈÂèʦ®@D¦®¾ŽŠœŠ¤‚¨Š¾ Š¤’ ¨Š¦¨D@D¨¤ªŠD@D¨Êæè‚àྠÊäÒàÐÊäÂؾààÆhh`¾`D@DààÆhh`¾`DvW„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂؾààÆhh`¾`D@D¦®¾„žž¨šŠšD@Dðàæ¾ÄäÂÚ¾Ò̾ÆÜèØä¾bDvO„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂؾààÆhh`¾`D@D¦®¾„žž¨¾ ‚¤D@D†¾„‚¦Š‚ˆˆ¤DvI„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂؾààÆhh`¾`D@D¦®¾ˆ‚¨‚¾’œ¦D@D¦¤‚šDvT„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂؾààÆhh`¾`D@D¦®¾ˆ‚¨‚¾ ‚¤D@D†¾šŠš`¾„‚¦Š‚ˆˆ¤DvI„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂؾààÆhh`¾`D@D¦®¾Š‚ ¾’œ¦D@D¦¤‚šDvT„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂؾààÆhh`¾`D@D¦®¾Š‚ ¾ ‚¤D@D†¾šŠš`¾„‚¦Š‚ˆˆ¤DvL„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂؾààÆhh`¾`D@D¦®¾ ¤žŽ¤‚š¾’œ¦D@D¦¤‚šDvW„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂؾààÆhh`¾`D@D¦®¾ ¤žŽ¤‚š¾ ‚¤D@D†¾šŠš`¾„‚¦Š‚ˆˆ¤DvJ„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂؾààÆhh`¾`D@D¦®¾¦¨‚†–¾’œ¦D@D¦¤‚šDvU„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂؾààÆhh`¾`D@D¦®¾¦¨‚†–¾ ‚¤D@D†¾šŠš`¾„‚¦Š‚ˆˆ¤DvN„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂؾààÆhh`¾`D@D¦®¾¦¨ˆ’œD@D¤¦dfd¾ªÂäè¾bDvO„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂؾààÆhh`¾`D@D¦®¾¦¨ˆžª¨D@D¤¦dfd¾ªÂäè¾bDvL„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂؾààÆhh`¾`D@D¦®¾¬Š†¨ž¤¦¾’œ¦D@D¦¤‚šDvW„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂؾààÆhh`¾`D@D¦®¾¬Š†¨ž¤¦¾ ‚¤D@D†¾šŠš`¾„‚¦Š‚ˆˆ¤Dv
\ No newline at end of file diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/system.log b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/system.log new file mode 100644 index 000000000..179be9a5f --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/system.log @@ -0,0 +1,4571 @@ +No logfile was found.
+
+Xilinx Platform Studio (XPS)
+Xilinx EDK 11.2 Build EDK_LS3.47 +
+Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. +
+WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line 251 - deprecated core for architecture 'virtex5fx'! +
+WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line 296 - deprecated core for architecture 'virtex5fx'! +
+Generating Block Diagram to Buffer +
+Generated Block Diagram SVG +
+At Local date and time: Mon Jun 29 21:01:23 2009 + make -f system.make program started... +
+*********************************************
+Creating software libraries...
+*********************************************
+libgen -mhs system.mhs -p xc5vfx70tff1136-1 -msg __xps/ise/xmsgprops.lst system.mss
+libgen
+Xilinx EDK 11.2 Build EDK_LS3.47
+Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
+
+Command Line: libgen -mhs system.mhs -p xc5vfx70tff1136-1 -msg
+__xps/ise/xmsgprops.lst system.mss
+
+Release 11.2 - psf2Edward EDK_LS3.47 (nt)
+Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
+WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
+ C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste
+ m.mhs line 251 - deprecated core for architecture 'virtex5fx'!
+WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
+ C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste
+ m.mhs line 296 - deprecated core for architecture 'virtex5fx'!
+WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
+ C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste
+ m.mhs line 251 - deprecated core for architecture 'virtex5fx'!
+WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
+ C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste
+ m.mhs line 296 - deprecated core for architecture 'virtex5fx'!
+
+Checking platform configuration ...
+IPNAME:plb_v46 INSTANCE:plb_v46_0 -
+C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\system.m
+hs line 107 - 1 master(s) : 12 slave(s)
+IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
+C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\system.m
+hs line 288 - 1 master(s) : 1 slave(s)
+
+Checking port drivers...
+WARNING:EDK:2099 - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -
+ C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste
+ m.mhs line 446 - floating connection!
+
+Performing Clock DRCs...
+
+Performing Reset DRCs...
+
+Overriding system level properties...
+
+Running system level update procedures...
+
+Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...
+
+Running system level DRCs...
+
+Performing System level DRCs on properties...
+
+Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
+WARNING:EDK:494 -
+ C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\synth
+ esis\ not found.
+WARNING:EDK:2530 - Timing and Resource utilization information not added
+WARNING:EDK:411 - pcie -
+ C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste
+ m.mss line 77 - deprecated driver!
+WARNING:EDK:411 - emaclite -
+ C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste
+ m.mss line 83 - deprecated driver!
+INFO:EDK:1740 - List of peripherals connected to processor instance ppc440_0:
+ - DDR2_SDRAM
+ - DIP_Switches_8Bit
+ - Ethernet_MAC
+ - IIC_EEPROM
+ - LEDs_8Bit
+ - LEDs_Positions
+ - PCIe_Bridge
+ - Push_Buttons_5Bit
+ - RS232_Uart_1
+ - SRAM
+ - SysACE_CompactFlash
+ - xps_bram_if_cntlr_1
+ - xps_intc_0
+
+-- Generating libraries for processor: ppc440_0 --
+
+
+Staging source files.
+Running DRCs.
+Running generate.
+Running post_generate.
+Running include - 'make -s include "COMPILER=powerpc-eabi-gcc"
+"ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mcpu=440 -O2 -c"
+"EXTRA_COMPILER_FLAGS=-g"'.
+
+Running libs - 'make -s libs "COMPILER=powerpc-eabi-gcc"
+"ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mcpu=440 -O2 -c"
+"EXTRA_COMPILER_FLAGS=-g"'.
+Compiling common
+powerpc-eabi-ar: creating ../../../lib/libxil.a +
+Compiling lldma
+Compiling standalone
+Compiling gpio
+Compiling emaclite
+Compiling iic
+Compiling pci
+Compiling uartlite
+Compiling sysace
+Compiling intc
+Compiling cpu_ppc440
+Running execs_generate.
+powerpc-eabi-gcc -O0 /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \
+ -mcpu=440 -Wl,-T -Wl,/cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \
+-D GCC_PPC440 -mregnames
+powerpc-eabi-size RTOSDemo/executable.elf
+ text data bss dec hex filename
+ 53754 372 86524 140650 2256a RTOSDemo/executable.elf
+
+
+Done! +
+Writing filter settings.... +
+Done writing filter settings to: + C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters +
+Done writing Tab View settings to: + C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.gui +
+Xilinx Platform Studio (XPS)
+Xilinx EDK 11.2 Build EDK_LS3.47 +
+Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. +
+WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 237 - deprecated core for architecture 'virtex5fx'! +
+WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 282 - deprecated core for architecture 'virtex5fx'! +
+Generating Block Diagram to Buffer +
+Generated Block Diagram SVG +
+At Local date and time: Tue Jun 30 18:32:58 2009 + make -f system.make hwclean started... +
+rm -f implementation/system.ngc
+rm -f platgen.log
+rm -f __xps/ise/_xmsgs/platgen.xmsgs
+rm -f implementation/system.bmm
+rm -f implementation/system.bit
+rm -f implementation/system.ncd
+rm -f implementation/system_bd.bmm
+rm -f implementation/system_map.ncd
+rm -f __xps/system_routed
+rm -rf implementation synthesis xst hdl
+rm -rf xst.srp system.srp
+rm -f __xps/ise/_xmsgs/bitinit.xmsgs
+
+
+Done! +
+At Local date and time: Tue Jun 30 18:33:07 2009 + make -f system.make netlistclean started... +
+rm -f implementation/system.ngc
+rm -f platgen.log
+rm -f __xps/ise/_xmsgs/platgen.xmsgs
+rm -f implementation/system.bmm
+
+
+Done! +
+At Local date and time: Tue Jun 30 18:33:13 2009 + make -f system.make bitsclean started... +
+rm -f implementation/system.bit
+rm -f implementation/system.ncd
+rm -f implementation/system_bd.bmm
+rm -f implementation/system_map.ncd
+rm -f __xps/system_routed
+
+
+Done! +
+At Local date and time: Tue Jun 30 18:33:24 2009 + make -f system.make libsclean started... +
+rm -rf ppc440_0/
+rm -f libgen.log
+rm -f __xps/ise/_xmsgs/libgen.xmsgs
+
+
+Done! +
+At Local date and time: Tue Jun 30 18:33:31 2009 + make -f system.make programclean started... +
+rm -f RTOSDemo/executable.elf
+
+
+Done! +
+At Local date and time: Tue Jun 30 18:33:37 2009 + make -f system.make swclean started... +
+rm -rf ppc440_0/
+rm -f libgen.log
+rm -f __xps/ise/_xmsgs/libgen.xmsgs
+rm -f RTOSDemo/executable.elf
+
+
+Done! +
+Writing filter settings.... +
+Done writing filter settings to: + C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters +
+Done writing Tab View settings to: + C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.gui +
+Xilinx Platform Studio (XPS)
+Xilinx EDK 11.2 Build EDK_LS3.47 +
+Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. +
+WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 237 - deprecated core for architecture 'virtex5fx'! +
+WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 282 - deprecated core for architecture 'virtex5fx'! +
+Generating Block Diagram to Buffer +
+Generated Block Diagram SVG +
+At Local date and time: Tue Jun 30 20:53:14 2009 + make -f system.make program started... +
+*********************************************
+Creating software libraries...
+*********************************************
+libgen -mhs system.mhs -p xc5vfx70tff1136-1 -msg __xps/ise/xmsgprops.lst system.mss
+libgen
+Xilinx EDK 11.2 Build EDK_LS3.47
+Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
+
+Command Line: libgen -mhs system.mhs -p xc5vfx70tff1136-1 -msg
+__xps/ise/xmsgprops.lst system.mss
+
+Release 11.2 - psf2Edward EDK_LS3.47 (nt)
+Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
+WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
+ C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+ 251 - deprecated core for architecture 'virtex5fx'!
+WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
+ C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+ 296 - deprecated core for architecture 'virtex5fx'!
+WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
+ C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+ 251 - deprecated core for architecture 'virtex5fx'!
+WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
+ C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+ 296 - deprecated core for architecture 'virtex5fx'!
+
+Checking platform configuration ...
+IPNAME:plb_v46 INSTANCE:plb_v46_0 -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+107 - 1 master(s) : 12 slave(s)
+IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+288 - 1 master(s) : 1 slave(s)
+
+Checking port drivers...
+WARNING:EDK:2099 - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -
+ C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+ 446 - floating connection!
+
+Performing Clock DRCs...
+
+Performing Reset DRCs...
+
+Overriding system level properties...
+
+Running system level update procedures...
+
+Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...
+
+Running system level DRCs...
+
+Performing System level DRCs on properties...
+
+Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
+WARNING:EDK:494 -
+ C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\synthesis\ not
+ found.
+WARNING:EDK:2530 - Timing and Resource utilization information not added
+WARNING:EDK:411 - pcie -
+ C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mss line
+ 77 - deprecated driver!
+WARNING:EDK:411 - emaclite -
+ C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mss line
+ 83 - deprecated driver!
+INFO:EDK:1740 - List of peripherals connected to processor instance ppc440_0:
+ - DDR2_SDRAM
+ - DIP_Switches_8Bit
+ - Ethernet_MAC
+ - IIC_EEPROM
+ - LEDs_8Bit
+ - LEDs_Positions
+ - PCIe_Bridge
+ - Push_Buttons_5Bit
+ - RS232_Uart_1
+ - SRAM
+ - SysACE_CompactFlash
+ - xps_bram_if_cntlr_1
+ - xps_intc_0
+
+-- Generating libraries for processor: ppc440_0 --
+
+
+Staging source files.
+Running DRCs.
+Running generate.
+Running post_generate.
+Running include - 'make -s include "COMPILER=powerpc-eabi-gcc"
+"ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mcpu=440 -O2 -c"
+"EXTRA_COMPILER_FLAGS=-g"'.
+
+Running libs - 'make -s libs "COMPILER=powerpc-eabi-gcc"
+"ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mcpu=440 -O2 -c"
+"EXTRA_COMPILER_FLAGS=-g"'.
+Compiling common
+powerpc-eabi-ar: creating ../../../lib/libxil.a +
+Compiling lldma
+Compiling standalone
+Compiling gpio
+Compiling emaclite
+Compiling iic
+Compiling pci
+Compiling uartlite
+Compiling sysace
+Compiling intc
+Compiling cpu_ppc440
+Running execs_generate.
+powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \
+ -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \
+-D GCC_PPC440 -mregnames
+powerpc-eabi-size RTOSDemo/executable.elf
+ text data bss dec hex filename
+ 53754 372 86524 140650 2256a RTOSDemo/executable.elf
+
+
+Done! +
+Writing filter settings.... +
+Done writing filter settings to: + C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters +
+Done writing Tab View settings to: + C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.gui +
+Xilinx Platform Studio (XPS)
+Xilinx EDK 11.2 Build EDK_LS3.47 +
+Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. +
+WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 237 - deprecated core for architecture 'virtex5fx'! +
+WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 282 - deprecated core for architecture 'virtex5fx'! +
+Generating Block Diagram to Buffer +
+Generated Block Diagram SVG +
+At Local date and time: Tue Jun 30 21:05:40 2009 + make -f system.make bits started... +
+****************************************************
+Creating system netlist for hardware specification..
+****************************************************
+platgen -p xc5vfx70tff1136-1 -lang vhdl -msg __xps/ise/xmsgprops.lst system.mhs
+
+Release 11.2 - platgen Xilinx EDK 11.2 Build EDK_LS3.47
+ (nt)
+Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
+
+
+Command Line: platgen -p xc5vfx70tff1136-1 -lang vhdl -msg
+__xps/ise/xmsgprops.lst system.mhs
+
+Parse C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/system.mhs
+...
+
+Read MPD definitions ...
+WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
+ C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+ 251 - deprecated core for architecture 'virtex5fx'!
+WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
+ C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+ 296 - deprecated core for architecture 'virtex5fx'!
+WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
+ C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+ 251 - deprecated core for architecture 'virtex5fx'!
+WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
+ C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+ 296 - deprecated core for architecture 'virtex5fx'!
+
+Overriding IP level properties ...
+
+Performing IP level DRCs on properties...
+
+Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
+Address Map for Processor ppc440_0
+ (0b0000000000-0b0011111111) ppc440_0
+ (0000000000-0x0fffffff) DDR2_SDRAM ppc440_0_PPC440MC
+ (0x81000000-0x8100ffff) Ethernet_MAC plb_v46_0
+ (0x81400000-0x8140ffff) Push_Buttons_5Bit plb_v46_0
+ (0x81420000-0x8142ffff) LEDs_Positions plb_v46_0
+ (0x81440000-0x8144ffff) LEDs_8Bit plb_v46_0
+ (0x81460000-0x8146ffff) DIP_Switches_8Bit plb_v46_0
+ (0x81600000-0x8160ffff) IIC_EEPROM plb_v46_0
+ (0x81800000-0x8180ffff) xps_intc_0 plb_v46_0
+ (0x83600000-0x8360ffff) SysACE_CompactFlash plb_v46_0
+ (0x84000000-0x8400ffff) RS232_Uart_1 plb_v46_0
+ (0x85c00000-0x85c0ffff) PCIe_Bridge plb_v46_0
+ (0xc0000000-0xdfffffff) PCIe_Bridge plb_v46_0
+ (0xe0000000-0xefffffff) PCIe_Bridge plb_v46_0
+ (0xf8000000-0xf80fffff) SRAM plb_v46_0
+ (0xffffe000-0xffffffff) xps_bram_if_cntlr_1 plb_v46_0
+INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_
+ 01_a\data\ppc440_virtex5_v2_1_0.mpd line 175 - tool is overriding PARAMETER
+ C_SPLB0_P2P value to 0
+
+Computing clock values...
+INFO:EDK:1432 - Frequency for Top-Level Input Clock
+ 'fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin' is not specified. Clock DRCs will not be
+ performed for IPs connected to that clock port, unless they are connected
+ through the clock generator IP.
+
+INFO:EDK:1432 - Frequency for Top-Level Input Clock
+ 'fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin' is not specified. Clock DRCs will not be
+ performed for IPs connected to that clock port, unless they are connected
+ through the clock generator IP.
+
+INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
+ ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER
+ C_PLBV46_NUM_MASTERS value to 1
+INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
+ ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER
+ C_PLBV46_NUM_SLAVES value to 12
+INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
+ ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER
+ C_PLBV46_MID_WIDTH value to 1
+INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
+ ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH
+ value to 128
+INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
+ v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 75 - tool is overriding
+ PARAMETER C_SPLB_DWIDTH value to 128
+INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
+ v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 76 - tool is overriding
+ PARAMETER C_SPLB_NUM_MASTERS value to 1
+INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
+ v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 80 - tool is overriding
+ PARAMETER C_SPLB_SMALLEST_MASTER value to 128
+INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
+ \data\bram_block_v2_1_0.mpd line 69 - tool is overriding PARAMETER C_MEMSIZE
+ value to 0x2000
+INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
+ \data\bram_block_v2_1_0.mpd line 70 - tool is overriding PARAMETER
+ C_PORT_DWIDTH value to 64
+INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
+ \data\bram_block_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_NUM_WE
+ value to 8
+INFO:EDK:1560 - IPNAME:xps_uartlite INSTANCE:RS232_Uart_1 -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_uartlite_v1_01
+ _a\data\xps_uartlite_v2_1_0.mpd line 73 - tool is overriding PARAMETER
+ C_SPLB_DWIDTH value to 128
+INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_8Bit -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
+ ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH
+ value to 128
+INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_Positions -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
+ ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH
+ value to 128
+INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:Push_Buttons_5Bit -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
+ ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH
+ value to 128
+INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:DIP_Switches_8Bit -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
+ ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH
+ value to 128
+INFO:EDK:1560 - IPNAME:xps_iic INSTANCE:IIC_EEPROM -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_iic_v2_01_a\da
+ ta\xps_iic_v2_1_0.mpd line 79 - tool is overriding PARAMETER C_SPLB_DWIDTH
+ value to 128
+INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_
+ a\data\xps_mch_emc_v2_1_0.mpd line 82 - tool is overriding PARAMETER
+ C_SPLB_DWIDTH value to 128
+INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_
+ a\data\xps_mch_emc_v2_1_0.mpd line 84 - tool is overriding PARAMETER
+ C_SPLB_SMALLEST_MASTER value to 128
+INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
+ b\data\plbv46_pcie_v2_1_0.mpd line 86 - tool is overriding PARAMETER
+ C_MPLB_DWIDTH value to 128
+INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
+ b\data\plbv46_pcie_v2_1_0.mpd line 87 - tool is overriding PARAMETER
+ C_MPLB_SMALLEST_SLAVE value to 128
+INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
+ b\data\plbv46_pcie_v2_1_0.mpd line 89 - tool is overriding PARAMETER
+ C_SPLB_MID_WIDTH value to 1
+INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
+ b\data\plbv46_pcie_v2_1_0.mpd line 90 - tool is overriding PARAMETER
+ C_SPLB_NUM_MASTERS value to 1
+INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
+ b\data\plbv46_pcie_v2_1_0.mpd line 91 - tool is overriding PARAMETER
+ C_SPLB_SMALLEST_MASTER value to 128
+INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
+ b\data\plbv46_pcie_v2_1_0.mpd line 95 - tool is overriding PARAMETER
+ C_SPLB_DWIDTH value to 128
+INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
+ ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER
+ C_PLBV46_NUM_MASTERS value to 1
+INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
+ ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER
+ C_PLBV46_NUM_SLAVES value to 1
+INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
+ ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER
+ C_PLBV46_MID_WIDTH value to 1
+INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
+ ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH
+ value to 128
+INFO:EDK:1560 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_ethernetlite_v
+ 2_01_a\data\xps_ethernetlite_v2_1_0.mpd line 75 - tool is overriding
+ PARAMETER C_SPLB_DWIDTH value to 128
+INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
+ \data\xps_sysace_v2_1_0.mpd line 72 - tool is overriding PARAMETER
+ C_SPLB_DWIDTH value to 128
+INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
+ \data\xps_sysace_v2_1_0.mpd line 74 - tool is overriding PARAMETER
+ C_SPLB_MID_WIDTH value to 1
+INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
+ \data\xps_sysace_v2_1_0.mpd line 75 - tool is overriding PARAMETER
+ C_SPLB_NUM_MASTERS value to 1
+INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d
+ ata\xps_intc_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_SPLB_DWIDTH
+ value to 128
+
+Checking platform address map ...
+
+Checking platform configuration ...
+INFO:EDK:1563 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
+ C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+ 296 - This design requires design constraints to guarantee performance.
+ Please refer to the xps_ethernetlite_v2_00_a data sheet for details.
+ The PLB clock frequency must be greater than or equal to 50 MHz for 100 Mbs
+ Ethernet operation and greater than or equal to 5.0 MHz for 10 Mbs Ethernet
+ operation.
+IPNAME:plb_v46 INSTANCE:plb_v46_0 -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+107 - 1 master(s) : 12 slave(s)
+IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+288 - 1 master(s) : 1 slave(s)
+
+Checking port drivers...
+WARNING:EDK:2099 - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -
+ C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+ 446 - floating connection!
+
+Performing Clock DRCs...
+
+Performing Reset DRCs...
+
+Overriding system level properties...
+INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_
+ 01_a\data\ppc440_virtex5_v2_1_0.mpd line 124 - tcl is overriding PARAMETER
+ C_PPC440MC_ADDR_BASE value to 0x00000000
+INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_
+ 01_a\data\ppc440_virtex5_v2_1_0.mpd line 125 - tcl is overriding PARAMETER
+ C_PPC440MC_ADDR_HIGH value to 0x0fffffff
+INFO:EDK:1560 - IPNAME:jtagppc_cntlr INSTANCE:jtagppc_cntlr_inst -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\jtagppc_cntlr_v2_0
+ 1_c\data\jtagppc_cntlr_v2_1_0.mpd line 70 - tcl is overriding PARAMETER
+ C_NUM_PPC_USED value to 1
+INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d
+ ata\xps_intc_v2_1_0.mpd line 79 - tcl is overriding PARAMETER C_KIND_OF_INTR
+ value to 0b00000000000000000000000000000001
+INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d
+ ata\xps_intc_v2_1_0.mpd line 80 - tcl is overriding PARAMETER C_KIND_OF_EDGE
+ value to 0b00000000000000000000000000000001
+INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d
+ ata\xps_intc_v2_1_0.mpd line 81 - tcl is overriding PARAMETER C_KIND_OF_LVL
+ value to 0b00000000000000000000000000000000
+
+Running system level update procedures...
+
+Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...
+
+Running system level DRCs...
+
+Performing System level DRCs on properties...
+
+Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
+
+Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...
+INFO: The PCIe_Bridge core has constraints automatically generated by XPS in
+implementation/pcie_bridge_wrapper/pcie_bridge_wrapper.ucf.
+It can be overridden by constraints placed in the system.ucf file.
+
+
+
+INFO: The Ethernet_MAC core has constraints automatically generated by XPS in
+implementation/ethernet_mac_wrapper/ethernet_mac_wrapper.ucf.
+It can be overridden by constraints placed in the system.ucf file.
+
+
+
+INFO: The DDR2_SDRAM core has constraints automatically generated by XPS in
+implementation/ddr2_sdram_wrapper/ddr2_sdram_wrapper.ucf.
+It can be overridden by constraints placed in the system.ucf file.
+
+
+
+
+Modify defaults ...
+
+Creating stub ...
+
+Processing licensed instances ...
+Completion time: 0.00 seconds
+
+Creating hardware output directories ...
+
+Managing hardware (BBD-specified) netlist files ...
+IPNAME:plbv46_pcie INSTANCE:pcie_bridge -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+251 - Copying (BBD-specified) netlist files.
+IPNAME:xps_ethernetlite INSTANCE:ethernet_mac -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+296 - Copying (BBD-specified) netlist files.
+
+Managing cache ...
+
+Elaborating instances ...
+IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+129 - elaborating IP
+
+Writing HDL for elaborated instances ...
+
+Inserting wrapper level ...
+Completion time: 1.00 seconds
+
+Constructing platform-level connectivity ...
+Completion time: 1.00 seconds
+
+Writing (top-level) BMM ...
+
+Writing (top-level and wrappers) HDL ...
+
+Generating synthesis project file ...
+
+Running XST synthesis ...
+
+INFO:EDK:2502 - The following instances are synthesized with XST. The MPD option
+ IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
+ synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.
+INSTANCE:ppc440_0 -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line 78
+- Running XST synthesis
+INSTANCE:plb_v46_0 -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+107 - Running XST synthesis
+INSTANCE:xps_bram_if_cntlr_1 -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+116 - Running XST synthesis
+INSTANCE:xps_bram_if_cntlr_1_bram -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+129 - Running XST synthesis
+INSTANCE:rs232_uart_1 -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+136 - Running XST synthesis
+INSTANCE:leds_8bit -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+152 - Running XST synthesis
+INSTANCE:leds_positions -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+166 - Running XST synthesis
+INSTANCE:push_buttons_5bit -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+180 - Running XST synthesis
+INSTANCE:dip_switches_8bit -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+194 - Running XST synthesis
+INSTANCE:iic_eeprom -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+208 - Running XST synthesis
+INSTANCE:sram -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+221 - Running XST synthesis
+INSTANCE:pcie_bridge -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+251 - Running XST synthesis
+INSTANCE:ppc440_0_splb0 -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+288 - Running XST synthesis
+INSTANCE:ethernet_mac -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+296 - Running XST synthesis
+INSTANCE:ddr2_sdram -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+315 - Running XST synthesis
+INSTANCE:sysace_compactflash -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+375 - Running XST synthesis
+INSTANCE:clock_generator_0 -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+392 - Running XST synthesis
+INSTANCE:jtagppc_cntlr_inst -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+431 - Running XST synthesis
+INSTANCE:proc_sys_reset_0 -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+437 - Running XST synthesis
+INSTANCE:xps_intc_0 -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+449 - Running XST synthesis
+
+Running NGCBUILD ...
+IPNAME:ppc440_0_wrapper INSTANCE:ppc440_0 -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line 78
+- Running NGCBUILD
+PMSPEC -- Overriding Xilinx file
+<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file
+<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>
+
+Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p
+xc5vfx70tff1136-1 -intstyle silent -uc ppc440_0_wrapper.ucf -sd ..
+ppc440_0_wrapper.ngc ../ppc440_0_wrapper.ngc
+
+Reading NGO file
+"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/pp
+c440_0_wrapper/ppc440_0_wrapper.ngc" ...
+
+Applying constraints in "ppc440_0_wrapper.ucf" to the design...
+
+Partition Implementation Status
+-------------------------------
+
+ No Partitions were found in this design.
+
+-------------------------------
+
+NGCBUILD Design Results Summary:
+ Number of errors: 0
+ Number of warnings: 0
+
+Writing NGC file "../ppc440_0_wrapper.ngc" ...
+Total REAL time to NGCBUILD completion: 7 sec
+Total CPU time to NGCBUILD completion: 6 sec
+
+Writing NGCBUILD log file "../ppc440_0_wrapper.blc"...
+
+NGCBUILD done.
+IPNAME:rs232_uart_1_wrapper INSTANCE:rs232_uart_1 -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+136 - Running NGCBUILD
+PMSPEC -- Overriding Xilinx file
+<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file
+<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>
+
+Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p
+xc5vfx70tff1136-1 -intstyle silent -sd .. rs232_uart_1_wrapper.ngc
+../rs232_uart_1_wrapper.ngc
+
+Reading NGO file
+"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/rs
+232_uart_1_wrapper/rs232_uart_1_wrapper.ngc" ...
+
+Partition Implementation Status
+-------------------------------
+
+ No Partitions were found in this design.
+
+-------------------------------
+
+NGCBUILD Design Results Summary:
+ Number of errors: 0
+ Number of warnings: 0
+
+Writing NGC file "../rs232_uart_1_wrapper.ngc" ...
+Total REAL time to NGCBUILD completion: 8 sec
+Total CPU time to NGCBUILD completion: 2 sec
+
+Writing NGCBUILD log file "../rs232_uart_1_wrapper.blc"...
+
+NGCBUILD done.
+IPNAME:pcie_bridge_wrapper INSTANCE:pcie_bridge -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+251 - Running NGCBUILD
+PMSPEC -- Overriding Xilinx file
+<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file
+<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>
+
+Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p
+xc5vfx70tff1136-1 -intstyle silent -uc pcie_bridge_wrapper.ucf -sd ..
+pcie_bridge_wrapper.ngc ../pcie_bridge_wrapper.ngc
+
+Reading NGO file
+"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/pc
+ie_bridge_wrapper/pcie_bridge_wrapper.ngc" ...
+Executing edif2ngd -noa
+"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\implementation\pc
+ie_bridge_wrapper_fifo_generator_v4_3.edn"
+"pcie_bridge_wrapper_fifo_generator_v4_3.ngo"
+Release 11.2 - edif2ngd L.46 (nt)
+Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
+INFO:NgdBuild - Release 11.2 edif2ngd L.46 (nt)
+INFO:NgdBuild - Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
+PMSPEC -- Overriding Xilinx file <C:/devtools/Xilinx/11.1/EDK/data/edif2ngd.pfd>
+with local file <C:/devtools/Xilinx/11.1/ISE/data/edif2ngd.pfd>
+Writing module to "pcie_bridge_wrapper_fifo_generator_v4_3.ngo"...
+Loading design module
+"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\implementation\pc
+ie_bridge_wrapper\pcie_bridge_wrapper_fifo_generator_v4_3.ngo"...
+Loading design module
+"../pcie_bridge_wrapper_fifo_generator_v4_3_fifo_generator_v4_3_xst_1.ngc"...
+Loading design module
+"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\implementation\pc
+ie_bridge_wrapper/dpram_70_512.ngc"...
+Loading design module
+"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\implementation\pc
+ie_bridge_wrapper/fifo_71x512.ngc"...
+
+Applying constraints in "pcie_bridge_wrapper.ucf" to the design...
+
+Partition Implementation Status
+-------------------------------
+
+ No Partitions were found in this design.
+
+-------------------------------
+
+NGCBUILD Design Results Summary:
+ Number of errors: 0
+ Number of warnings: 0
+
+Writing NGC file "../pcie_bridge_wrapper.ngc" ...
+Total REAL time to NGCBUILD completion: 13 sec
+Total CPU time to NGCBUILD completion: 9 sec
+
+Writing NGCBUILD log file "../pcie_bridge_wrapper.blc"...
+
+NGCBUILD done.
+IPNAME:ethernet_mac_wrapper INSTANCE:ethernet_mac -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+296 - Running NGCBUILD
+PMSPEC -- Overriding Xilinx file
+<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file
+<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>
+
+Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p
+xc5vfx70tff1136-1 -intstyle silent -uc ethernet_mac_wrapper.ucf -sd ..
+ethernet_mac_wrapper.ngc ../ethernet_mac_wrapper.ngc
+
+Reading NGO file
+"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/et
+hernet_mac_wrapper/ethernet_mac_wrapper.ngc" ...
+Executing edif2ngd -noa "ethernetlite_v1_01_b_dmem_v2.edn"
+"ethernetlite_v1_01_b_dmem_v2.ngo"
+Release 11.2 - edif2ngd L.46 (nt)
+Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
+INFO:NgdBuild - Release 11.2 edif2ngd L.46 (nt)
+INFO:NgdBuild - Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
+PMSPEC -- Overriding Xilinx file <C:/devtools/Xilinx/11.1/EDK/data/edif2ngd.pfd>
+with local file <C:/devtools/Xilinx/11.1/ISE/data/edif2ngd.pfd>
+Writing module to "ethernetlite_v1_01_b_dmem_v2.ngo"...
+Loading design module
+"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\implementation\et
+hernet_mac_wrapper\ethernetlite_v1_01_b_dmem_v2.ngo"...
+
+Applying constraints in "ethernet_mac_wrapper.ucf" to the design...
+
+Partition Implementation Status
+-------------------------------
+
+ No Partitions were found in this design.
+
+-------------------------------
+
+NGCBUILD Design Results Summary:
+ Number of errors: 0
+ Number of warnings: 0
+
+Writing NGC file "../ethernet_mac_wrapper.ngc" ...
+Total REAL time to NGCBUILD completion: 9 sec
+Total CPU time to NGCBUILD completion: 6 sec
+
+Writing NGCBUILD log file "../ethernet_mac_wrapper.blc"...
+
+NGCBUILD done.
+IPNAME:ddr2_sdram_wrapper INSTANCE:ddr2_sdram -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+315 - Running NGCBUILD
+PMSPEC -- Overriding Xilinx file
+<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file
+<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>
+
+Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p
+xc5vfx70tff1136-1 -intstyle silent -uc ddr2_sdram_wrapper.ucf -sd ..
+ddr2_sdram_wrapper.ngc ../ddr2_sdram_wrapper.ngc
+
+Reading NGO file
+"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/dd
+r2_sdram_wrapper/ddr2_sdram_wrapper.ngc" ...
+
+Applying constraints in "ddr2_sdram_wrapper.ucf" to the design...
+
+Partition Implementation Status
+-------------------------------
+
+ No Partitions were found in this design.
+
+-------------------------------
+
+NGCBUILD Design Results Summary:
+ Number of errors: 0
+ Number of warnings: 0
+
+Writing NGC file "../ddr2_sdram_wrapper.ngc" ...
+Total REAL time to NGCBUILD completion: 7 sec
+Total CPU time to NGCBUILD completion: 7 sec
+
+Writing NGCBUILD log file "../ddr2_sdram_wrapper.blc"...
+
+NGCBUILD done.
+IPNAME:xps_intc_0_wrapper INSTANCE:xps_intc_0 -
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+449 - Running NGCBUILD
+PMSPEC -- Overriding Xilinx file
+<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file
+<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>
+
+Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p
+xc5vfx70tff1136-1 -intstyle silent -sd .. xps_intc_0_wrapper.ngc
+../xps_intc_0_wrapper.ngc
+
+Reading NGO file
+"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/xp
+s_intc_0_wrapper/xps_intc_0_wrapper.ngc" ...
+
+Partition Implementation Status
+-------------------------------
+
+ No Partitions were found in this design.
+
+-------------------------------
+
+NGCBUILD Design Results Summary:
+ Number of errors: 0
+ Number of warnings: 0
+
+Writing NGC file "../xps_intc_0_wrapper.ngc" ...
+Total REAL time to NGCBUILD completion: 1 sec
+Total CPU time to NGCBUILD completion: 1 sec
+
+Writing NGCBUILD log file "../xps_intc_0_wrapper.blc"...
+
+NGCBUILD done.
+
+Rebuilding cache ...
+
+Total run time: 1039.00 seconds
+Running synthesis...
+bash -c "cd synthesis; ./synthesis.sh"
+xst -ifn system_xst.scr -intstyle silent
+Running XST synthesis ...
+XST completed
+Release 11.2 - ngcbuild L.46 (nt)
+Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
+Overriding Xilinx file <ngcflow.csf> with local file
+<c:/devtools/Xilinx/11.1/ISE/data/ngcflow.csf>
+
+Command Line: c:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe
+./system.ngc ../implementation/system.ngc -sd ../implementation -i -ise
+../__xps/ise/system.ise
+
+Reading NGO file
+"c:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/synthesis/system.
+ngc" ...
+Loading design module "../implementation/ppc440_0_wrapper.ngc"...
+Loading design module "../implementation/plb_v46_0_wrapper.ngc"...
+Loading design module "../implementation/xps_bram_if_cntlr_1_wrapper.ngc"...
+Loading design module
+"../implementation/xps_bram_if_cntlr_1_bram_wrapper.ngc"...
+Loading design module "../implementation/rs232_uart_1_wrapper.ngc"...
+Loading design module "../implementation/leds_8bit_wrapper.ngc"...
+Loading design module "../implementation/leds_positions_wrapper.ngc"...
+Loading design module "../implementation/push_buttons_5bit_wrapper.ngc"...
+Loading design module "../implementation/dip_switches_8bit_wrapper.ngc"...
+Loading design module "../implementation/iic_eeprom_wrapper.ngc"...
+Loading design module "../implementation/sram_wrapper.ngc"...
+Loading design module "../implementation/pcie_bridge_wrapper.ngc"...
+Loading design module "../implementation/ppc440_0_splb0_wrapper.ngc"...
+Loading design module "../implementation/ethernet_mac_wrapper.ngc"...
+Loading design module "../implementation/ddr2_sdram_wrapper.ngc"...
+Loading design module "../implementation/sysace_compactflash_wrapper.ngc"...
+Loading design module "../implementation/clock_generator_0_wrapper.ngc"...
+Loading design module "../implementation/jtagppc_cntlr_inst_wrapper.ngc"...
+Loading design module "../implementation/proc_sys_reset_0_wrapper.ngc"...
+Loading design module "../implementation/xps_intc_0_wrapper.ngc"...
+
+Partition Implementation Status
+-------------------------------
+
+ No Partitions were found in this design.
+
+-------------------------------
+
+NGCBUILD Design Results Summary:
+ Number of errors: 0
+ Number of warnings: 0
+
+Writing NGC file "../implementation/system.ngc" ...
+Total REAL time to NGCBUILD completion: 10 sec
+Total CPU time to NGCBUILD completion: 9 sec
+
+Writing NGCBUILD log file "../implementation/system.blc"...
+
+NGCBUILD done.
+*********************************************
+Running Xilinx Implementation tools..
+*********************************************
+xflow -wd implementation -p xc5vfx70tff1136-1 -implement xflow.opt -ise ../__xps/ise/system.ise system.ngc
+Release 11.2 - Xflow L.46 (nt)
+Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
+xflow.exe -wd implementation -p xc5vfx70tff1136-1 -implement xflow.opt -ise
+../__xps/ise/system.ise system.ngc
+PMSPEC -- Overriding Xilinx file
+<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file
+<c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>
+.... Copying flowfile c:/devtools/Xilinx/11.1/ISE/xilinx/data/fpga.flw into
+working directory
+C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation
+
+Using Flow File:
+C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/fpg
+a.flw
+Using Option File(s):
+ C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/xf
+low.opt
+
+Creating Script File ...
+
+#----------------------------------------------#
+# Starting program ngdbuild
+# ngdbuild -ise ../__xps/ise/system.ise -p xc5vfx70tff1136-1 -nt timestamp -bm
+system.bmm
+"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/sy
+stem.ngc" -uc system.ucf system.ngd
+#----------------------------------------------#
+Release 11.2 - ngdbuild L.46 (nt)
+Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
+PMSPEC -- Overriding Xilinx file
+<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file
+<c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>
+
+Command Line: ngdbuild -ise ../__xps/ise/system.ise -p xc5vfx70tff1136-1 -nt
+timestamp -bm system.bmm
+C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/sys
+tem.ngc -uc system.ucf system.ngd
+
+Reading NGO file
+"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/sy
+stem.ngc" ...
+Gathering constraint information from source properties...
+Done.
+
+Applying constraints in "system.ucf" to the design...
+WARNING:NgdBuild:931 - The value of SIM_DEVICE on instance
+ 'clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_
+ ADV.DCM_ADV_INST' of type DCM_ADV has been changed from 'VIRTEX4' to
+ 'VIRTEX5' to correct post-ngdbuild and timing simulation for this primitive.
+ In order for functional simulation to be correct, the value of SIM_DEVICE
+ should be changed in this same manner in the source netlist or constraint
+ file.
+Resolving constraint associations...
+Checking Constraint Associations...
+WARNING:ConstraintSystem:3 - Constraint <TIMESPEC "TS_MC_RD_DATA_SEL" = FROM
+ "TNM_RD_DATA_SEL" TO "TNM_CLK0" "TS_clk_div_slow_0_clk_div_slow_0_DDR2_CLK_i"
+ * 4;> [system.ucf(264)]: This constraint will be ignored because the relative
+ clock constraint named 'TS_clk_div_slow_0_clk_div_slow_0_DDR2_CLK_i' was not
+ found.
+
+INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification
+ 'TS_sys_clk_pin', was traced into PLL_ADV instance
+ clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.
+ The following new TNM groups and period specifications were generated at the
+ PLL_ADV output(s):
+ CLKOUT0: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_0_ =
+ PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_0_" TS_sys_clk_pin *
+ 1.25 PHASE 2 ns HIGH 50%>
+
+INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification
+ 'TS_sys_clk_pin', was traced into PLL_ADV instance
+ clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.
+ The following new TNM groups and period specifications were generated at the
+ PLL_ADV output(s):
+ CLKOUT1: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_1_ =
+ PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_1_" TS_sys_clk_pin *
+ 1.25 HIGH 50%>
+
+INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification
+ 'TS_sys_clk_pin', was traced into PLL_ADV instance
+ clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.
+ The following new TNM groups and period specifications were generated at the
+ PLL_ADV output(s):
+ CLKOUT2: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_2_ =
+ PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_2_" TS_sys_clk_pin *
+ 1.25 HIGH 50%>
+
+INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification
+ 'TS_sys_clk_pin', was traced into PLL_ADV instance
+ clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.
+ The following new TNM groups and period specifications were generated at the
+ PLL_ADV output(s):
+ CLKOUT3: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_3_ =
+ PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_3_" TS_sys_clk_pin *
+ 2 HIGH 50%>
+
+INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification
+ 'TS_sys_clk_pin', was traced into PLL_ADV instance
+ clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.
+ The following new TNM groups and period specifications were generated at the
+ PLL_ADV output(s):
+ CLKOUT4: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_4_ =
+ PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_4_" TS_sys_clk_pin *
+ 0.625 HIGH 50%>
+
+Done...
+Checking Partitions ...
+
+Processing BMM file ...
+
+WARNING:NgdBuild:1212 - User specified non-default attribute value
+ (8.0000000000000000) was detected for the CLKIN_PERIOD attribute on DCM
+ "clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST".
+ This does not match the PERIOD constraint value (5 ns.). The uncertainty
+ calculation will use the non-default attribute value. This could result in
+ incorrect uncertainty calculated for DCM output clocks.
+Checking expanded design ...
+WARNING:NgdBuild:443 - SFF primitive
+ 'xps_bram_if_cntlr_1/xps_bram_if_cntlr_1/INCLUDE_BURST_SUPPORT.I_SLAVE_BURST_
+ ATTACH/I_DBEAT_CONTROL/I_DBEAT_CNTR/STRUCTURAL_A_GEN.I_ADDSUB_GEN[4].FDRE_I'
+ has unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'SRAM/SRAM/EMC_CTRL_I/MEM_STEER_I/SYNC_MEM_DQT.REG_DQT_GEN[2].DQT_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'SRAM/SRAM/EMC_CTRL_I/MEM_STEER_I/GSYNC_MEM_RDACK_GEN.ADDR_ALIGN_PIPE_GEN[3].
+ ALIGN_PIPE' has unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
+ ENT/I_DECODER/GEN_CE_FOR_SHARED.GEN_BKEND_CE_REGISTERS[0].I_BKEND_WRCE_REG'
+ has unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
+ ENT/I_DECODER/GEN_CE_FOR_SHARED.GEN_BKEND_CE_REGISTERS[0].I_BKEND_RDCE_REG'
+ has unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
+ ENT/I_BURST_SUPPORT/RESPONSE_DBEAT_CNTR_I/STRUCTURAL_A_GEN.I_ADDSUB_GEN[7].FD
+ RE_I' has unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
+ ENT/I_BURST_SUPPORT/CONTROL_DBEAT_CNTR_I/STRUCTURAL_A_GEN.I_ADDSUB_GEN[7].FDR
+ E_I' has unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
+ ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[0].I_FDRSE_BE0to3
+ ' has unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
+ ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[1].I_FDRSE_BE0to3
+ ' has unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
+ ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[2].I_FDRSE_BE0to3
+ ' has unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
+ ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[3].I_FDRSE_BE0to3
+ ' has unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
+ ENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG'
+ has unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
+ ENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG
+ ' has unconnected output pin
+WARNING:NgdBuild:486 - Attribute "CLK_FEEDBACK" is not allowed on symbol
+ "PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.pll_ad
+ v_i" of type "PLL_ADV". This attribute will be ignored.
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B
+ URSTXFER.I_STEER_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B
+ URSTXFER.I_BUS_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B
+ URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE
+ _4to7[7].I_FDRSE_BE4to7' has unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B
+ URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE
+ _4to7[6].I_FDRSE_BE4to7' has unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B
+ URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE
+ _4to7[5].I_FDRSE_BE4to7' has unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B
+ URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE
+ _4to7[4].I_FDRSE_BE4to7' has unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B
+ URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[3].I_FDRSE_B
+ E0to3' has unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B
+ URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[2].I_FDRSE_B
+ E0to3' has unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B
+ URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[1].I_FDRSE_B
+ E0to3' has unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B
+ URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[0].I_FDRSE_B
+ E0to3' has unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_S
+ _H_ADDR_REG[6].I_ADDR_S_H_REG' has unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_S
+ _H_ADDR_REG[7].I_ADDR_S_H_REG' has unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_RDCE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_WRCE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_RDCE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_WRCE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_RDCE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_WRCE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_RDCE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_WRCE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_RDCE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_WRCE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_RDCE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_WRCE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_RDCE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_WRCE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_RDCE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_WRCE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_RDCE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_WRCE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_RDCE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_WRCE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[32].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[33].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[34].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[35].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[36].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[37].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[38].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[39].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[40].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[41].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[42].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[43].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[44].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[44].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[44].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[45].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[45].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[45].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[46].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[46].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[46].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[47].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[47].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[47].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[48].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[48].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[48].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[49].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[49].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[49].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[53].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[53].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[53].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[54].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[54].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[54].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[55].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[55].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[55].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[56].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[57].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[58].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[59].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[60].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[61].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[61].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[61].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[62].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[62].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[62].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[63].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[63].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[63].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[1].GEN_USER_CE.GEN_ALL_CEs[64].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[1].GEN_USER_CE.GEN_ALL_CEs[64].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[1].GEN_USER_CE.GEN_ALL_CEs[64].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[65].I_BKend_CE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[66].I_BKend_CE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[66].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[67].I_BKend_CE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[68].I_BKend_CE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[68].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[68].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[69].I_BKend_CE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[69].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[69].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[70].I_BKend_CE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[70].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[70].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[71].I_BKend_CE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[71].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[72].I_BKend_CE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[73].I_BKend_CE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[74].I_BKend_CE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[74].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[74].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[75].I_BKend_CE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[76].I_BKend_CE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[76].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[76].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[77].I_BKend_CE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[77].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[77].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[78].I_BKend_CE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[78].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[78].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[79].I_BKend_CE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[79].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[79].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[80].I_BKend_CE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[80].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[80].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[3].GEN_RESET_CE.I_BKend_CE_REG' has unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[3].GEN_RESET_CE.I_BKend_RDCE_REG' has unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[4].GEN_USER_CE.GEN_ALL_CEs[82].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[4].GEN_USER_CE.GEN_ALL_CEs[82].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[4].GEN_USER_CE.GEN_ALL_CEs[82].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[5].GEN_USER_CE.GEN_ALL_CEs[83].I_BKend_CE_REG' has unconnected
+ output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[5].GEN_USER_CE.GEN_ALL_CEs[83].I_BKend_RDCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
+ E_ASSIGNMENTS[5].GEN_USER_CE.GEN_ALL_CEs[83].I_BKend_WRCE_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_
+ SIZE2_REG0' has unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_
+ SIZE2_REG1' has unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_
+ SIZE2_REG2' has unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'PCIe_Bridge/PCIe_Bridge/comp_plbv46_master/I_RD_CONTROL/I_RD_ABORT_REG' has
+ unconnected output pin
+WARNING:NgdBuild:443 - SFF primitive
+ 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/COLLISION_SYNC' has unconnected
+ output pin
+WARNING:NgdBuild:440 - FF primitive
+ 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU10'
+ has unconnected output pin
+WARNING:NgdBuild:440 - FF primitive
+ 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU15'
+ has unconnected output pin
+WARNING:NgdBuild:440 - FF primitive
+ 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU20'
+ has unconnected output pin
+WARNING:NgdBuild:440 - FF primitive
+ 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU25'
+ has unconnected output pin
+WARNING:NgdBuild:440 - FF primitive
+ 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU30'
+ has unconnected output pin
+WARNING:NgdBuild:440 - FF primitive
+ 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU35'
+ has unconnected output pin
+WARNING:NgdBuild:440 - FF primitive
+ 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU130'
+ has unconnected output pin
+WARNING:NgdBuild:440 - FF primitive
+ 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU237'
+ has unconnected output pin
+WARNING:NgdBuild:440 - FF primitive
+ 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU10'
+ has unconnected output pin
+WARNING:NgdBuild:440 - FF primitive
+ 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU15'
+ has unconnected output pin
+WARNING:NgdBuild:440 - FF primitive
+ 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU20'
+ has unconnected output pin
+WARNING:NgdBuild:440 - FF primitive
+ 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU25'
+ has unconnected output pin
+WARNING:NgdBuild:440 - FF primitive
+ 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU30'
+ has unconnected output pin
+WARNING:NgdBuild:440 - FF primitive
+ 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU35'
+ has unconnected output pin
+WARNING:NgdBuild:440 - FF primitive
+ 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU130'
+ has unconnected output pin
+WARNING:NgdBuild:440 - FF primitive
+ 'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU237'
+ has unconnected output pin
+WARNING:NgdBuild:440 - FF primitive
+ 'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib
+ /gen_rden[1].u_calib_rden_r' has unconnected output pin
+WARNING:NgdBuild:440 - FF primitive
+ 'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib
+ /gen_rden[2].u_calib_rden_r' has unconnected output pin
+WARNING:NgdBuild:440 - FF primitive
+ 'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib
+ /gen_rden[3].u_calib_rden_r' has unconnected output pin
+WARNING:NgdBuild:440 - FF primitive
+ 'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib
+ /gen_rden[4].u_calib_rden_r' has unconnected output pin
+WARNING:NgdBuild:440 - FF primitive
+ 'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib
+ /gen_rden[5].u_calib_rden_r' has unconnected output pin
+WARNING:NgdBuild:440 - FF primitive
+ 'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib
+ /gen_rden[6].u_calib_rden_r' has unconnected output pin
+WARNING:NgdBuild:440 - FF primitive
+ 'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib
+ /gen_rden[7].u_calib_rden_r' has unconnected output pin
+WARNING:NgdBuild:486 - Attribute "CLK_FEEDBACK" is not allowed on symbol
+ "clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst"
+ of type "PLL_ADV". This attribute will be ignored.
+WARNING:NgdBuild:452 - logical net 'N194' has no driver
+WARNING:NgdBuild:452 - logical net 'N195' has no driver
+WARNING:NgdBuild:452 - logical net 'N196' has no driver
+WARNING:NgdBuild:452 - logical net 'N197' has no driver
+WARNING:NgdBuild:452 - logical net 'N198' has no driver
+WARNING:NgdBuild:452 - logical net 'N199' has no driver
+WARNING:NgdBuild:452 - logical net 'N200' has no driver
+WARNING:NgdBuild:452 - logical net 'N201' has no driver
+WARNING:NgdBuild:452 - logical net 'N202' has no driver
+WARNING:NgdBuild:452 - logical net 'N203' has no driver
+WARNING:NgdBuild:452 - logical net 'N204' has no driver
+WARNING:NgdBuild:452 - logical net 'N205' has no driver
+WARNING:NgdBuild:452 - logical net 'N206' has no driver
+WARNING:NgdBuild:452 - logical net 'N207' has no driver
+WARNING:NgdBuild:452 - logical net 'N208' has no driver
+WARNING:NgdBuild:452 - logical net 'N209' has no driver
+WARNING:NgdBuild:452 - logical net 'N210' has no driver
+WARNING:NgdBuild:452 - logical net 'N211' has no driver
+WARNING:NgdBuild:452 - logical net 'N212' has no driver
+WARNING:NgdBuild:452 - logical net 'N213' has no driver
+WARNING:NgdBuild:452 - logical net 'N214' has no driver
+WARNING:NgdBuild:452 - logical net 'N215' has no driver
+WARNING:NgdBuild:452 - logical net 'N216' has no driver
+WARNING:NgdBuild:452 - logical net 'N217' has no driver
+WARNING:NgdBuild:452 - logical net 'N218' has no driver
+WARNING:NgdBuild:452 - logical net 'N219' has no driver
+WARNING:NgdBuild:452 - logical net 'N220' has no driver
+WARNING:NgdBuild:452 - logical net 'N221' has no driver
+WARNING:NgdBuild:452 - logical net 'N222' has no driver
+WARNING:NgdBuild:452 - logical net 'N223' has no driver
+WARNING:NgdBuild:452 - logical net 'N224' has no driver
+WARNING:NgdBuild:452 - logical net 'N225' has no driver
+WARNING:NgdBuild:452 - logical net 'N226' has no driver
+WARNING:NgdBuild:452 - logical net 'N227' has no driver
+WARNING:NgdBuild:452 - logical net 'N228' has no driver
+WARNING:NgdBuild:452 - logical net 'N229' has no driver
+WARNING:NgdBuild:452 - logical net 'N230' has no driver
+WARNING:NgdBuild:452 - logical net 'N231' has no driver
+WARNING:NgdBuild:452 - logical net 'N232' has no driver
+WARNING:NgdBuild:452 - logical net 'N233' has no driver
+WARNING:NgdBuild:452 - logical net 'N234' has no driver
+WARNING:NgdBuild:452 - logical net 'N235' has no driver
+WARNING:NgdBuild:452 - logical net 'N236' has no driver
+WARNING:NgdBuild:452 - logical net 'N237' has no driver
+WARNING:NgdBuild:452 - logical net 'N238' has no driver
+WARNING:NgdBuild:452 - logical net 'N239' has no driver
+WARNING:NgdBuild:452 - logical net 'N240' has no driver
+WARNING:NgdBuild:452 - logical net 'N241' has no driver
+WARNING:NgdBuild:452 - logical net 'N242' has no driver
+WARNING:NgdBuild:452 - logical net 'N243' has no driver
+WARNING:NgdBuild:452 - logical net 'N244' has no driver
+WARNING:NgdBuild:452 - logical net 'N245' has no driver
+WARNING:NgdBuild:452 - logical net 'N246' has no driver
+WARNING:NgdBuild:452 - logical net 'N247' has no driver
+WARNING:NgdBuild:452 - logical net 'N248' has no driver
+WARNING:NgdBuild:452 - logical net 'N249' has no driver
+WARNING:NgdBuild:452 - logical net 'N250' has no driver
+WARNING:NgdBuild:452 - logical net 'N251' has no driver
+WARNING:NgdBuild:452 - logical net 'N252' has no driver
+WARNING:NgdBuild:452 - logical net 'N253' has no driver
+WARNING:NgdBuild:452 - logical net 'N254' has no driver
+WARNING:NgdBuild:452 - logical net 'N255' has no driver
+WARNING:NgdBuild:452 - logical net 'N256' has no driver
+WARNING:NgdBuild:452 - logical net 'N257' has no driver
+WARNING:NgdBuild:452 - logical net 'N266' has no driver
+WARNING:NgdBuild:452 - logical net 'N267' has no driver
+WARNING:NgdBuild:452 - logical net 'N268' has no driver
+WARNING:NgdBuild:452 - logical net 'N269' has no driver
+WARNING:NgdBuild:452 - logical net 'N270' has no driver
+WARNING:NgdBuild:452 - logical net 'N271' has no driver
+WARNING:NgdBuild:452 - logical net 'N272' has no driver
+WARNING:NgdBuild:452 - logical net 'N273' has no driver
+WARNING:NgdBuild:452 - logical net 'N306' has no driver
+WARNING:NgdBuild:452 - logical net 'N307' has no driver
+WARNING:NgdBuild:452 - logical net 'N308' has no driver
+WARNING:NgdBuild:452 - logical net 'N309' has no driver
+WARNING:NgdBuild:452 - logical net 'N310' has no driver
+WARNING:NgdBuild:452 - logical net 'N311' has no driver
+WARNING:NgdBuild:452 - logical net 'N312' has no driver
+WARNING:NgdBuild:452 - logical net 'N313' has no driver
+WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_terrfwd_n'
+ has no driver
+WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_rerrfwd_n'
+ has no driver
+WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_tsrc_dsc_n'
+ has no driver
+WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_tbuf_av<3>'
+ has no driver
+WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_trem_n<4>'
+ has no driver
+
+Partition Implementation Status
+-------------------------------
+
+ No Partitions were found in this design.
+
+-------------------------------
+
+NGDBUILD Design Results Summary:
+ Number of errors: 0
+ Number of warnings: 348
+
+Writing NGD file "system.ngd" ...
+Total REAL time to NGDBUILD completion: 1 min 58 sec
+Total CPU time to NGDBUILD completion: 1 min 28 sec
+
+Writing NGDBUILD log file "system.bld"...
+
+NGDBUILD done.
+
+
+
+#----------------------------------------------#
+# Starting program map
+# map -ise ../__xps/ise/system.ise -o system_map.ncd -w -pr b -ol high -timing
+system.ngd system.pcf
+#----------------------------------------------#
+Release 11.2 - Map L.46 (nt)
+Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
+PMSPEC -- Overriding Xilinx file
+<C:/devtools/Xilinx/11.1/EDK/data/Xdh_PrimTypeLib.xda> with local file
+<c:/devtools/Xilinx/11.1/ISE/data/Xdh_PrimTypeLib.xda>
+Using target part "5vfx70tff1136-1".
+WARNING:LIT:243 - Logical network N194 has no load.
+WARNING:LIT:395 - The above warning message is repeated 1200 more times for the
+ following (max. 5 shown):
+ N195,
+ N196,
+ N197,
+ N198,
+ N199
+ To see the details of these warning messages, please use the -detail switch.
+Mapping design into LUTs...
+WARNING:MapLib:701 - Signal fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin
+ connected to top level port fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin has
+ been removed.
+WARNING:MapLib:701 - Signal fpga_0_Ethernet_MAC_PHY_col_pin connected to top
+ level port fpga_0_Ethernet_MAC_PHY_col_pin has been removed.
+WARNING:MapLib:41 - All members of TNM group "ppc440_0_PPCS0PLBMBUSY" have been
+ optimized out of the design.
+Writing file system_map.ngm...
+WARNING:Pack:2874 - Trimming timing constraints from pin
+ xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0
+ of frag REGCLKAU connected to power/ground net
+ xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAU_tiesig
+WARNING:Pack:2874 - Trimming timing constraints from pin
+ xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0
+ of frag REGCLKAL connected to power/ground net
+ xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAL_tiesig
+WARNING:Pack:2874 - Trimming timing constraints from pin
+ xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1
+ of frag REGCLKAU connected to power/ground net
+ xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAU_tiesig
+WARNING:Pack:2874 - Trimming timing constraints from pin
+ xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1
+ of frag REGCLKAL connected to power/ground net
+ xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAL_tiesig
+WARNING:Pack:2874 - Trimming timing constraints from pin
+ PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
+ er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst
+ of frag REGCLKAU connected to power/ground net
+ PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
+ er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAU_tiesig
+WARNING:Pack:2874 - Trimming timing constraints from pin
+ PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
+ er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst
+ of frag REGCLKAL connected to power/ground net
+ PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
+ er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAL_tiesig
+WARNING:Pack:2874 - Trimming timing constraints from pin
+ PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
+ er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst
+ of frag REGCLKAU connected to power/ground net
+ PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
+ er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAU_tiesig
+WARNING:Pack:2874 - Trimming timing constraints from pin
+ PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
+ er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst
+ of frag REGCLKAL connected to power/ground net
+ PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
+ er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAL_tiesig
+WARNING:Pack:2874 - Trimming timing constraints from pin
+ PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r
+ x_bridge/fifo_inst/oq_fifo/Mram_regBank
+ of frag RDRCLKU connected to power/ground net
+ PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r
+ x_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKU_tiesig
+WARNING:Pack:2874 - Trimming timing constraints from pin
+ PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r
+ x_bridge/fifo_inst/oq_fifo/Mram_regBank
+ of frag RDRCLKL connected to power/ground net
+ PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r
+ x_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKL_tiesig
+WARNING:Pack:2874 - Trimming timing constraints from pin
+ PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0
+ /blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.
+ noeccerr.SDP
+ of frag RDRCLKU connected to power/ground net
+ PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0
+ /blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.
+ noeccerr.SDP_RDRCLKU_tiesig
+WARNING:Pack:2874 - Trimming timing constraints from pin
+ PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0
+ /blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.
+ noeccerr.SDP
+ of frag RDRCLKL connected to power/ground net
+ PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0
+ /blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.
+ noeccerr.SDP_RDRCLKL_tiesig
+WARNING:Pack:2874 - Trimming timing constraints from pin
+ PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m
+ em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.
+ ram/SDP.WIDE_PRIM36.noeccerr.SDP
+ of frag RDRCLKU connected to power/ground net
+ PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m
+ em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.
+ ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig
+WARNING:Pack:2874 - Trimming timing constraints from pin
+ PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m
+ em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.
+ ram/SDP.WIDE_PRIM36.noeccerr.SDP
+ of frag RDRCLKL connected to power/ground net
+ PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m
+ em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.
+ ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig
+WARNING:Pack:2874 - Trimming timing constraints from pin
+ PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM
+ P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi
+ nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP
+ of frag RDRCLKU connected to power/ground net
+ PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM
+ P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi
+ nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig
+WARNING:Pack:2874 - Trimming timing constraints from pin
+ PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM
+ P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi
+ nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP
+ of frag RDRCLKL connected to power/ground net
+ PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM
+ P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi
+ nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig
+WARNING:Pack:2874 - Trimming timing constraints from pin
+ PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2
+ /U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM
+ 36.noeccerr.SDP
+ of frag RDRCLKU connected to power/ground net
+ PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2
+ /U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM
+ 36.noeccerr.SDP_RDRCLKU_tiesig
+WARNING:Pack:2874 - Trimming timing constraints from pin
+ PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2
+ /U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM
+ 36.noeccerr.SDP
+ of frag RDRCLKL connected to power/ground net
+ PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2
+ /U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM
+ 36.noeccerr.SDP_RDRCLKL_tiesig
+Running directed packing...
+Running delay-based LUT packing...
+Updating timing models...
+WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM
+ TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP "TNM_CLK0" TS_MC_CLK * 4 ignored during
+ timing analysis.
+INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
+ (.mrp).
+Running timing-driven placement...
+Total REAL time at the beginning of Placer: 1 mins 55 secs
+Total CPU time at the beginning of Placer: 1 mins 43 secs
+
+Phase 1.1 Initial Placement Analysis
+Phase 1.1 Initial Placement Analysis (Checksum:150b88e2) REAL time: 2 mins 13 secs
+
+Phase 2.7 Design Feasibility Check
+WARNING:Place:838 - An IO Bus with more than one IO standard is found.
+ Components associated with this bus are as follows:
+ Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<7> IOSTANDARD = LVCMOS25
+ Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<6> IOSTANDARD = LVCMOS25
+ Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<5> IOSTANDARD = LVCMOS25
+ Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<4> IOSTANDARD = LVCMOS18
+ Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25
+ Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS18
+ Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS18
+ Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS18
+
+
+WARNING:Place:838 - An IO Bus with more than one IO standard is found.
+ Components associated with this bus are as follows:
+ Comp: fpga_0_SRAM_Mem_DQ_pin<31> IOSTANDARD = LVDCI_33
+ Comp: fpga_0_SRAM_Mem_DQ_pin<30> IOSTANDARD = LVDCI_33
+ Comp: fpga_0_SRAM_Mem_DQ_pin<29> IOSTANDARD = LVDCI_33
+ Comp: fpga_0_SRAM_Mem_DQ_pin<28> IOSTANDARD = LVDCI_33
+ Comp: fpga_0_SRAM_Mem_DQ_pin<27> IOSTANDARD = LVDCI_33
+ Comp: fpga_0_SRAM_Mem_DQ_pin<26> IOSTANDARD = LVDCI_33
+ Comp: fpga_0_SRAM_Mem_DQ_pin<25> IOSTANDARD = LVDCI_33
+ Comp: fpga_0_SRAM_Mem_DQ_pin<24> IOSTANDARD = LVDCI_33
+ Comp: fpga_0_SRAM_Mem_DQ_pin<23> IOSTANDARD = LVDCI_33
+ Comp: fpga_0_SRAM_Mem_DQ_pin<22> IOSTANDARD = LVDCI_33
+ Comp: fpga_0_SRAM_Mem_DQ_pin<21> IOSTANDARD = LVDCI_33
+ Comp: fpga_0_SRAM_Mem_DQ_pin<20> IOSTANDARD = LVDCI_33
+ Comp: fpga_0_SRAM_Mem_DQ_pin<19> IOSTANDARD = LVDCI_33
+ Comp: fpga_0_SRAM_Mem_DQ_pin<18> IOSTANDARD = LVDCI_33
+ Comp: fpga_0_SRAM_Mem_DQ_pin<17> IOSTANDARD = LVDCI_33
+ Comp: fpga_0_SRAM_Mem_DQ_pin<16> IOSTANDARD = LVDCI_33
+ Comp: fpga_0_SRAM_Mem_DQ_pin<15> IOSTANDARD = LVCMOS33
+ Comp: fpga_0_SRAM_Mem_DQ_pin<14> IOSTANDARD = LVCMOS33
+ Comp: fpga_0_SRAM_Mem_DQ_pin<13> IOSTANDARD = LVCMOS33
+ Comp: fpga_0_SRAM_Mem_DQ_pin<12> IOSTANDARD = LVCMOS33
+ Comp: fpga_0_SRAM_Mem_DQ_pin<11> IOSTANDARD = LVCMOS33
+ Comp: fpga_0_SRAM_Mem_DQ_pin<10> IOSTANDARD = LVCMOS33
+ Comp: fpga_0_SRAM_Mem_DQ_pin<9> IOSTANDARD = LVCMOS33
+ Comp: fpga_0_SRAM_Mem_DQ_pin<8> IOSTANDARD = LVCMOS33
+ Comp: fpga_0_SRAM_Mem_DQ_pin<7> IOSTANDARD = LVCMOS33
+ Comp: fpga_0_SRAM_Mem_DQ_pin<6> IOSTANDARD = LVCMOS33
+ Comp: fpga_0_SRAM_Mem_DQ_pin<5> IOSTANDARD = LVCMOS33
+ Comp: fpga_0_SRAM_Mem_DQ_pin<4> IOSTANDARD = LVCMOS33
+ Comp: fpga_0_SRAM_Mem_DQ_pin<3> IOSTANDARD = LVCMOS33
+ Comp: fpga_0_SRAM_Mem_DQ_pin<2> IOSTANDARD = LVCMOS33
+ Comp: fpga_0_SRAM_Mem_DQ_pin<1> IOSTANDARD = LVCMOS33
+ Comp: fpga_0_SRAM_Mem_DQ_pin<0> IOSTANDARD = LVCMOS33
+
+
+Phase 2.7 Design Feasibility Check (Checksum:150b88e2) REAL time: 2 mins 14 secs
+
+Phase 3.31 Local Placement Optimization
+Phase 3.31 Local Placement Optimization (Checksum:f23945c2) REAL time: 2 mins 14 secs
+
+Phase 4.37 Local Placement Optimization
+Phase 4.37 Local Placement Optimization (Checksum:f23945c2) REAL time: 2 mins 14 secs
+
+Phase 5.33 Local Placement Optimization
+Phase 5.33 Local Placement Optimization (Checksum:f23945c2) REAL time: 8 mins 58 secs
+
+Phase 6.32 Local Placement Optimization
+Phase 6.32 Local Placement Optimization (Checksum:f23945c2) REAL time: 9 mins 1 secs
+
+Phase 7.2 Initial Clock and IO Placement
+
+
+
+There are 16 clock regions on the target FPGA device:
+|------------------------------------------|------------------------------------------|
+| CLOCKREGION_X0Y7: | CLOCKREGION_X1Y7: |
+| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |
+| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |
+| 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use |
+| 4 center BUFIOs available, 0 in use | |
+| | |
+|------------------------------------------|------------------------------------------|
+| CLOCKREGION_X0Y6: | CLOCKREGION_X1Y6: |
+| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |
+| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |
+| 4 edge BUFIOs available, 3 in use | 4 edge BUFIOs available, 0 in use |
+| 0 center BUFIOs available, 0 in use | |
+| | |
+|------------------------------------------|------------------------------------------|
+| CLOCKREGION_X0Y5: | CLOCKREGION_X1Y5: |
+| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |
+| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |
+| 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use |
+| 2 center BUFIOs available, 0 in use | |
+| | |
+|------------------------------------------|------------------------------------------|
+| CLOCKREGION_X0Y4: | CLOCKREGION_X1Y4: |
+| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |
+| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |
+| 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use |
+| 2 center BUFIOs available, 0 in use | |
+| | |
+|------------------------------------------|------------------------------------------|
+| CLOCKREGION_X0Y3: | CLOCKREGION_X1Y3: |
+| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |
+| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |
+| 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use |
+| 2 center BUFIOs available, 0 in use | |
+| | |
+|------------------------------------------|------------------------------------------|
+| CLOCKREGION_X0Y2: | CLOCKREGION_X1Y2: |
+| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |
+| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |
+| 4 edge BUFIOs available, 3 in use | 4 edge BUFIOs available, 0 in use |
+| 2 center BUFIOs available, 0 in use | |
+| | |
+|------------------------------------------|------------------------------------------|
+| CLOCKREGION_X0Y1: | CLOCKREGION_X1Y1: |
+| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |
+| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use
+ |
+| 4 edge BUFIOs available, 2 in use | 4 edge BUFIOs available, 0 in use |
+| 0 center BUFIOs available, 0 in use | |
+| | |
+|------------------------------------------|------------------------------------------|
+| CLOCKREGION_X0Y0: | CLOCKREGION_X1Y0: |
+| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |
+| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |
+| 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use |
+| 4 center BUFIOs available, 0 in use | |
+| | |
+|------------------------------------------|------------------------------------------|
+
+
+Clock-Region: <CLOCKREGION_X0Y1>
+ key resource utilizations (used/available): edge-bufios - 2/4; bufrs - 0/2; regional-clock-spines - 0/4
+|-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| | clock | BRAM | | | | | | | | | | | |
+| | region | FIFO | DCM | GT | ILOGIC | OLOGIC | FF | LUTM | LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
+| | Upper Region| 24 | 2 | 0 | 60 | 60 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the upper region
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
+| |CurrentRegion| 24 | 4 | 0 | 40 | 40 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the current region
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
+| | Lower Region| 24 | 0 | 0 | 80 | 80 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the lower region
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
+| clock | region | -----------------------------------------------
+| type | expansion | | <IO/Regional clock Net Name>
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
+| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>"
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
+| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>"
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
+
+
+Clock-Region: <CLOCKREGION_X0Y2>
+ key resource utilizations (used/available): edge-bufios - 3/4; center-bufios - 0/2; bufrs - 0/2; regional-clock-spines - 0/4
+|-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| | clock | BRAM | | | | | | | | | | | |
+| | region | FIFO | DCM | GT | ILOGIC | OLOGIC | FF | LUTM | LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
+| | Upper Region| 8 | 0 | 0 | 60 | 60 | 1280 | 640 | 1920 | 0 | 0 | 1 | 0 | <- Available resources in the upper region
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
+| |CurrentRegion| 24 | 2 | 0 | 60 | 60 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the current region
+|-------|-------------|------|-----|----|--------|-------
+-|-------|-------|-------|------|------|-----|------|----------------------------------------------
+| | Lower Region| 24 | 4 | 0 | 40 | 40 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the lower region
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
+| clock | region | -----------------------------------------------
+| type | expansion | | <IO/Regional clock Net Name>
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
+| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>"
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
+| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>"
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
+| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>"
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
+
+
+Clock-Region: <CLOCKREGION_X0Y6>
+ key resource utilizations (used/available): edge-bufios - 3/4; bufrs - 0/2; regional-clock-spines - 0/4
+|-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| | clock | BRAM | | | | | | | | | | | |
+| | region | FIFO | DCM | GT | ILOGIC | OLOGIC | FF | LUTM | LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
+| | Upper Region| 24 | 0 | 0 | 80 | 80 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the upper region
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
+| |CurrentRegion| 24 | 4 | 0 | 40 | 40 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the current region
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
+| | Lower Region| 24 | 2 | 0 | 60 | 60 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the lower region
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
+| clock | region | -----------------------------------------------
+| type | expansion | | <IO/Regional clock Net Name>
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
+| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 |
+ 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>"
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
+| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>"
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
+| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>"
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
+
+
+
+
+######################################################################################
+# REGIONAL CLOCKING RESOURCE DISTRIBUTION UCF REPORT:
+#
+# Number of Regional Clocking Regions in the device: 16 (4 clock spines in each)
+# Number of Regional Clock Networks used in this design: 8 (each network can be
+# composed of up to 3 clock spines and cover up to 3 regional clock regions)
+#
+######################################################################################
+
+# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" driven by "BUFIO_X0Y27"
+INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_bufio_dqs" LOC =
+"BUFIO_X0Y27" ;
+NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" TNM_NET =
+"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" ;
+TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" AREA_GROUP =
+"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" ;
+AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" RANGE =
+CLOCKREGION_X0Y6;
+
+
+# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" driven by "BUFIO_X0Y9"
+INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/u_bufio_dqs" LOC =
+"BUFIO_X0Y9" ;
+NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" TNM_NET =
+"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" ;
+TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" AREA_GROUP =
+"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" ;
+AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" RANGE =
+CLOCKREGION_X0Y2;
+
+
+# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" driven by "BUFIO_X0Y11"
+INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_bufio_dqs" LOC =
+"BUFIO_X0Y11" ;
+NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" TNM_NET =
+"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" ;
+TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" AREA_GROUP =
+"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" ;
+AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" RANGE =
+CLOCKREGION_X0Y2;
+
+
+# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" driven by "BUFIO_X0Y4"
+INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_bufio_dqs" LOC =
+"BUFIO_X0Y4" ;
+NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" TNM_NET =
+"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" ;
+TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" AREA_GROUP =
+"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" ;
+AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" RANGE =
+CLOCKREGION_X0Y1;
+
+
+# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" driven by "BUFIO_X0Y25"
+INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_bufio_dqs" LOC =
+"BUFIO_X0Y25" ;
+NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" TNM_NET =
+"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" ;
+TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" AREA_GROUP =
+"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" ;
+AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" RANGE =
+CLOCKREGION_X0Y6;
+
+
+# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" driven by "BUFIO_X0Y7"
+INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/u_bufio_dqs" LOC =
+"BUFIO_X0Y7" ;
+NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" TNM_NET =
+"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" ;
+TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" AREA_GROUP =
+"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" ;
+AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" RANGE =
+CLOCKREGION_X0Y1;
+
+
+# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" driven by "BUFIO_X0Y26"
+INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_bufio_dqs" LOC =
+"BUFIO_X0Y26" ;
+NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" TNM_NET =
+"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" ;
+TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" AREA_GROUP =
+"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" ;
+AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" RANGE =
+CLOCKREGION_X0Y6;
+
+
+# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" driven by "BUFIO_X0Y10"
+INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[3].u_iob_dqs/u_bufio_dqs" LOC =
+"BUFIO_X0Y10" ;
+NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" TNM_NET =
+"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" ;
+TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" AREA_GROUP =
+"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" ;
+AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" RANGE =
+CLOCKREGION_X0Y2;
+
+
+Phase 7.2 Initial Clock and IO Placement (Checksum:7e049af9) REAL time: 9 mins 19 secs
+
+Phase 8.36 Local Placement Optimization
+Phase 8.36 Local Placement Optimization (Checksum:7e049af9) REAL time: 9 mins 19 secs
+
+....................
+.................
+.....
+......
+.....
+......
+.....
+.....
+......
+......
+.......
+......
+.......
+.......
+.......
+..
+Phase 9.30 Global Clock Region Assignment
+
+
+######################################################################################
+# GLOBAL CLOCK NET DISTRIBUTION UCF REPORT:
+#
+# Number of Global Clock Regions : 16
+# Number of Global Clock Networks: 15
+#
+# Clock Region Assignment: SUCCESSFUL
+
+# Location of Clock Components
+INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT1.CLKOUT1_BUFG_INST" LOC = "BUFGCTRL_X0Y1" ;
+INST "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP/BUFG" LOC = "BUFGCTRL_X0Y30" ;
+INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.gtxclk_pll_bufg" LOC = "BUFGCTRL_X0Y29" ;
+INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.coreclk_pll_bufg" LOC = "BUFGCTRL_X0Y27" ;
+INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT2.CLKOUT2_BUFG_INST" LOC = "BUFGCTRL_X0Y2" ;
+INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_BUFG_for_CLKFBOUT.CLKFB_BUFG_INST" LOC = "BUFGCTRL_X0Y3" ;
+INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/notsame.usrclk_pll_bufg" LOC = "BUFGCTRL_X0Y28" ;
+INST "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP/BUFG" LOC = "BUFGCTRL_X0Y8" ;
+INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.clkfbin_pll_bufg" LOC = "BUFGCTRL_X0Y26" ;
+INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT3.CLKOUT3_BUFG_INST" LOC = "BUFGCTRL_X0Y4" ;
+INST "clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/Using_BUFG_for_CLK0.CLK0_BUFG_INST" LOC = "BUFGCTRL_X0Y7" ;
+INST "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP/BUFG" LOC = "BUFGCTRL_X0Y31" ;
+INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT0.CLKOUT0_BUFG_INST" LOC = "BUFGCTRL_X0Y5" ;
+INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT4.CLKOUT4_BUFG_INST" LOC = "BUFGCTRL_X0Y6" ;
+INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/bufg2" LOC = "BUFGCTRL_X0Y0" ;
+INST "clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST" LOC = "DCM_ADV_X0Y0" ;
+INST "fpga_0_SRAM_ZBT_CLK_FB_pin" LOC = "IOB_X1Y111" ;
+INST "fpga_0_clk_1_sys_clk_pin" LOC = "IOB_X1Y109" ;
+INST "fpga_0_Ethernet_MAC_PHY_rx_clk_pin" LOC = "IOB_X1Y219" ;
+INST "fpga_0_Ethernet_MAC_PHY_tx_clk_pin" LOC = "IOB_X1Y217" ;
+INST "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin" LOC = "IOB_X1Y105" ;
+INST "fpga_0_PCIe_Bridge_RXN_pin" LOC = "IPAD_X1Y12" ;
+INST "fpga_0_PCIe_Bridge_RXP_pin" LOC = "IPAD_X1Y13" ;
+INST "fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin" LOC = "IPAD_X1Y16" ;
+INST "fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin" LOC = "IPAD_X1Y17" ;
+INST "fpga_0_PCIe_Bridge_TXN_pin" LOC = "OPAD_X0Y8" ;
+INST "fpga_0_PCIe_Bridge_TXP_pin" LOC = "OPAD_X0Y9" ;
+INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.pll_adv_i" LOC = "PLL_ADV_X0Y5" ;
+INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst" LOC = "PLL_ADV_X0Y0" ;
+INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" LOC = "GTX_DUAL_X0Y2" ;
+INST "ibufgds_76" LOC = "BUFDS_X0Y2" ;
+
+# clk_125_0000MHzPLL0 driven by BUFGCTRL_X0Y1
+NET "clk_125_0000MHzPLL0" TNM_NET = "TN_clk_125_0000MHzPLL0" ;
+TIMEGRP "TN_clk_125_0000MHzPLL0" AREA_GROUP = "CLKAG_clk_125_0000MHzPLL0" ;
+AREA_GROUP "CLKAG_clk_125_0000MHzPLL0" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
+
+# fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP driven by BUFGCTRL_X0Y30
+NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" TNM_NET = "TN_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" ;
+TIMEGRP "TN_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" AREA_GROUP = "CLKAG_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" ;
+AREA_GROUP "CLKAG_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" RANGE = CLOCKREGION_X0Y2, CLOCKREGION_X0Y3, CLOCKREGION_X0Y4, CLOCKREGION_X0Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
+
+# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk driven by BUFGCTRL_X0Y29
+NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" ;
+TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" ;
+AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ;
+
+# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk driven by BUFGCTRL_X0Y27
+NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" ;
+TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" ;
+AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
+
+# clk_125_0000MHzPLL0_ADJUST driven by BUFGCTRL_X0Y2
+NET "clk_125_0000MHzPLL0_ADJUST" TNM_NET = "TN_clk_125_0000MHzPLL0_ADJUST" ;
+TIMEGRP "TN_clk_125_0000MHzPLL0_ADJUST" AREA_GROUP = "CLKAG_clk_125_0000MHzPLL0_ADJUST" ;
+AREA_GROUP "CLKAG_clk_125_0000MHzPLL0_ADJUST" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
+
+# clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6> driven by BUFGCTRL_X0Y3
+NET "clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" TNM_NET = "TN_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" ;
+TIMEGRP "TN_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" AREA_GROUP = "CLKAG_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" ;
+AREA_GROUP "CLKAG_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X0Y1 ;
+
+# PCIe_Bridge/Bridge_Clk driven by BUFGCTRL_X0Y28
+NET "PCIe_Bridge/Bridge_Clk" TNM_NET = "TN_PCIe_Bridge/Bridge_Clk" ;
+TIMEGRP "TN_PCIe_Bridge/Bridge_Clk" AREA_GROUP = "CLKAG_PCIe_Bridge/Bridge_Clk" ;
+AREA_GROUP "CLKAG_PCIe_Bridge/Bridge_Clk" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
+
+# fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP driven by BUFGCTRL_X0Y8
+NET "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" TNM_NET = "TN_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" ;
+TIMEGRP "TN_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" AREA_GROUP = "CLKAG_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" ;
+AREA_GROUP "CLKAG_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" RANGE = CLOCKREGION_X1Y0, CLOCKREGION_X1Y1, CLOCKREGION_X1Y2, CLOCKREGION_X1Y3, CLOCKREGION_X1Y4, CLOCKREGION_X1Y5, CLOCKREGION_X1Y6, CLOCKREGION_X1Y7 ;
+
+# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin driven by BUFGCTRL_X0Y26
+NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" ;
+TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" ;
+AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" RANGE = CLOCKREGION_X0Y6, CLOCKREGION_X0Y7 ;
+
+# clk_200_0000MHz driven by BUFGCTRL_X0Y4
+NET "clk_200_0000MHz" TNM_NET = "TN_clk_200_0000MHz" ;
+TIMEGRP "TN_clk_200_0000MHz" AREA_GROUP = "CLKAG_clk_200_0000MHz" ;
+AREA_GROUP "CLKAG_clk_200_0000MHz" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
+
+# fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF driven by BUFGCTRL_X0Y7
+NET "fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" TNM_NET = "TN_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" ;
+TIMEGRP "TN_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" AREA_GROUP = "CLKAG_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" ;
+AREA_GROUP "CLKAG_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" RANGE = CLOCKREGION_X1Y6, CLOCKREGION_X1Y7 ;
+
+# fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP driven by BUFGCTRL_X0Y31
+NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" TNM_NET = "TN_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" ;
+TIMEGRP "TN_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" AREA_GROUP = "CLKAG_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" ;
+AREA_GROUP "CLKAG_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ;
+
+# clk_125_0000MHz90PLL0_ADJUST driven by BUFGCTRL_X0Y5
+NET "clk_125_0000MHz90PLL0_ADJUST" TNM_NET = "TN_clk_125_0000MHz90PLL0_ADJUST" ;
+TIMEGRP "TN_clk_125_0000MHz90PLL0_ADJUST" AREA_GROUP = "CLKAG_clk_125_0000MHz90PLL0_ADJUST" ;
+AREA_GROUP "CLKAG_clk_125_0000MHz90PLL0_ADJUST" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
+
+# clk_62_5000MHzPLL0_ADJUST driven by BUFGCTRL_X0Y6
+NET "clk_62_5000MHzPLL0_ADJUST" TNM_NET = "TN_clk_62_5000MHzPLL0_ADJUST" ;
+TIMEGRP "TN_clk_62_5000MHzPLL0_ADJUST" AREA_GROUP = "CLKAG_clk_62_5000MHzPLL0_ADJUST" ;
+AREA_GROUP "CLKAG_clk_62_5000MHzPLL0_ADJUST" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
+
+# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg driven by BUFGCTRL_X0Y0
+NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" ;
+TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" ;
+AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" RANGE = CLOCKREGION_X0Y6, CLOCKREGION_X0Y7 ;
+
+# NOTE:
+# This report is provided to help reproduce successful clock-region
+# assignments. The report provides range constraints for all global
+# clock networks, in a format that is directly usable in ucf files.
+#
+#END of Global Clock Net Distribution UCF Constraints
+######################################################################################
+
+
+######################################################################################
+GLOBAL CLOCK NET LOADS DISTRIBUTION REPORT:
+
+Number of Global Clock Regions : 16
+Number of Global Clock Networks: 15
+
+Clock Region Assignment: SUCCESSFUL
+
+Clock-Region: <CLOCKREGION_X0Y0>
+ key resource utilizations (used/available): global-clocks - 2/10 ;
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)
+ FIFO | | | | | | | | | | | | | |
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 12 | 0 | 0 | 0 | 80 | 80 | 0 | 0 | 0 | 0 | 2 | 0 | 1600 | 3200 | <- (Available Resources in this Region)
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ | | | | | | | | | | | | | | <Global clock Net Name>
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 44 | 548 |PCIe_Bridge/Bridge_Clk
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 202 |clk_125_0000MHzPLL0_ADJUST
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 46 | 750 | Total
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+
+
+Clock-Region: <CLOCKREGION_X1Y0>
+ key resource utilizations (used/available): global-clocks - 2/10 ;
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)
+ FIFO | | | | | | | | | | | | | |
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 8 | 0 | 0 | 0 | 40 | 40 | 16 | 0 | 0 | 1 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ | | | | | | | | | | | | | | <Global clock Net Name>
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 38 | 934 |PCIe_Bridge/Bridge_Clk
+ 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 24 | 52 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 62 | 986 | Total
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+
+
+Clock-Region: <CLOCKREGION_X0Y1>
+ key resource utilizations (used/available): global-clocks - 6/10 ;
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)
+ FIFO | | | | | | | | | | | | | |
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 12 | 4 | 2 | 0 | 40 | 40 | 0 | 0 | 0 | 0 | 1 | 0 | 1600 | 3200 | <- (Available Resources in this Region)
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ | | | | | | | | | | | | | | <Global clock Net Name>
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13 | 195 |PCIe_Bridge/Bridge_Clk
+ 0 | 0 | 0 | 0 | 0 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |clk_125_0000MHz90PLL0_ADJUST
+ 0 | 1 | 0 | 0 | 0 | 17 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 719 |clk_125_0000MHzPLL0_ADJUST
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |clk_200_0000MHz
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 |clk_62_5000MHzPLL0_ADJUST
+ 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 0 | 1 | 1 | 0 | 0 | 35 | 0 | 0 | 0 | 0 | 1 | 0 | 17 | 918 | Total
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+
+
+Clock-Region: <CLOCKREGION_X1Y1>
+ key resource utilizations (used/available): global-clocks - 4/10 ;
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)
+ FIFO | | | | | | | | | | | | | |
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 8 | 0 | 0 | 0 | 40 | 40 | 16 | 0 | 0 | 0 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ | | | | | | | | | | | | | | <Global clock Net Name>
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 6 | 500 |PCIe_Bridge/Bridge_Clk
+ 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 20 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11 | 364 |clk_125_0000MHzPLL0_ADJUST
+ 0 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 1 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 17 | 884 | Total
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+
+
+Clock-Region: <CLOCKREGION_X0Y2>
+ key resource utilizations (used/available): global-clocks - 5/10 ;
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)
+ FIFO | | | | | | | | | | | | | |
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 12 | 2 | 1 | 0 | 60 | 60 | 0 | 0 | 0 | 0 | 2 | 0 | 1600 | 3200 | <- (Available Resources in this Region)
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ | | | | | | | | | | | | | | <Global clock Net Name>
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |PCIe_Bridge/Bridge_Clk
+ 0 | 0 | 0 | 0 | 0 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 17 |clk_125_0000MHz90PLL0_ADJUST
+ 5 | 0 | 0 | 0 | 9 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 58 | 913 |clk_125_0000MHzPLL0_ADJUST
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |clk_200_0000MHz
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 142 |clk_62_5000MHzPLL0_ADJUST
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 7 | 0 | 0 | 0 | 9 | 42 | 0 | 0 | 0 | 0 | 1 | 0 | 58 | 1072 | Total
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+
+
+Clock-Region: <CLOCKREGION_X1Y2>
+ key resource utilizations (used/available): global-clocks - 4/10 ;
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)
+ FIFO | | | | | | | | | | | | | |
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 8 | 0 | 0 | 0 | 40 | 40 | 16 | 0 | 0 | 1 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ | | | | | | | | | | | | | | <Global clock Net Name>
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 94 | 387 |PCIe_Bridge/Bridge_Clk
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 81 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk
+ 0 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 36 | 500 |clk_125_0000MHzPLL0_ADJUST
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 0 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 130 | 970 | Total
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+
+
+Clock-Region: <CLOCKREGION_X0Y3>
+ key resource utilizations (used/available): global-clocks - 4/10 ;
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)
+ FIFO | | | | | | | | | | | | | |
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 4 | 0 | 0 | 0 | 60 | 60 | 0 | 0 | 1 | 0 | 2 | 16 | 640 | 1280 | <- (Available Resources in this Region)
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ | | | | | | | | | | | | | | <Global clock Net Name>
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 83 |clk_125_0000MHz90PLL0_ADJUST
+ 0 | 0 | 0 | 0 | 8 | 17 | 0 | 0 | 1 | 0 | 0 | 0 | 36 | 272 |clk_125_0000MHzPLL0_ADJUST
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 |clk_200_0000MHz
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 154 |clk_62_5000MHzPLL0_ADJUST
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 0 | 0 | 0 | 0 | 8 | 17 | 0 | 0 | 1 | 0 | 0 | 0 | 36 | 512 | Total
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+
+
+Clock-Region: <CLOCKREGION_X1Y3>
+ key resource utilizations (used/available): global-clocks - 3/10 ;
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)
+ FIFO | | | | | | | | | | | | | |
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 8 | 0 | 0 | 0 | 40 | 40 | 16 | 0 | 0 | 0 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ | | | | | | | | | | | | | | <Global clock Net Name>
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 44 | 290 |PCIe_Bridge/Bridge_Clk
+ 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 22 | 659 |clk_125_0000MHzPLL0_ADJUST
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 66 | 950 | Total
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+
+
+Clock-Region: <CLOCKREGION_X0Y4>
+ key resource utilizations (used/available): global-clocks - 5/10 ;
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)
+ FIFO | | | | | | | | | | | | | |
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 4 | 0 | 0 | 0 | 60 | 60 | 0 | 0 | 1 | 0 | 2 | 16 | 640 | 1280 | <- (Available Resources in this Region)
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ | | | | | | | | | | | | | | <Global clock Net Name>
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |PCIe_Bridge/Bridge_Clk
+ 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 34 |clk_125_0000MHz90PLL0_ADJUST
+ 4 | 0 | 0 | 0 | 1 | 20 | 0 | 0 | 0 | 0 | 0 | 0 | 16 | 231 |clk_125_0000MHzPLL0_ADJUST
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 200 |clk_62_5000MHzPLL0_ADJUST
+ 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 6 | 0 | 0 | 0 | 7 | 20 | 0 | 0 | 0 | 0 | 0 | 0 | 18 | 466 | Total
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+
+
+Clock-Region: <CLOCKREGION_X1Y4>
+ key resource utilizations (used/available): global-clocks - 3/10 ;
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)
+ FIFO | | | | | | | | | | | | | |
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 10 | 0 | 0 | 0 | 40 | 40 | 16 | 1 | 0 | 0 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ | | | | | | | | | | | | | | <Global clock Net Name>
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 54 | 367 |PCIe_Bridge/Bridge_Clk
+ 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 20 | 602 |clk_125_0000MHzPLL0_ADJUST
+ 0 | 0 | 0 | 0 | 16 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 16 |fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 3 | 0 | 0 | 0 | 16 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 74 | 985 | Total
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+
+
+Clock-Region: <CLOCKREGION_X0Y5>
+ key resource utilizations (used/available): global-clocks - 4/10 ;
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)
+ FIFO | | | | | | | | | | | | | |
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 12 | 2 | 1 | 0 | 60 | 60 | 0 | 0 | 0 | 0 | 2 | 0 | 1600 | 3200 | <- (Available Resources in this Region)
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ | | | | | | | | | | | | | | <Global clock Net Name>
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 2 |PCIe_Bridge/Bridge_Clk
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 48 |clk_125_0000MHz90PLL0_ADJUST
+ 0 | 0 | 0 | 0 | 0 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | 16 | 517 |clk_125_0000MHzPLL0_ADJUST
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 206 |clk_62_5000MHzPLL0_ADJUST
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 0 | 0 | 0 | 0 | 0 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | 28 | 773 | Total
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+
+
+Clock-Region: <CLOCKREGION_X1Y5>
+ key resource utilizations (used/available): global-clocks - 3/10 ;
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)
+ FIFO | | | | | | | | | | | | | |
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 10 | 0 | 0 | 0 | 40 | 40 | 16 | 1 | 0 | 0 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ | | | | | | | | | | | | | | <Global clock Net Name>
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 68 | 285 |PCIe_Bridge/Bridge_Clk
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 50 | 333 |clk_125_0000MHzPLL0_ADJUST
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 21 |fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 118 | 639 | Total
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+
+
+Clock-Region: <CLOCKREGION_X0Y6>
+ key resource utilizations (used/available): global-clocks - 7/10 ;
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)
+ FIFO | | | | | | | | | | | | | |
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 12 | 4 | 2 | 0 | 40 | 40 | 0 | 0 | 0 | 0 | 1 | 0 | 1600 | 3200 | <- (Available Resources in this Region)
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ | | | | | | | | | | | | | | <Global clock Net Name>
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg
+ 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin
+ 0 | 0 | 0 | 0 | 0 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 |clk_125_0000MHz90PLL0_ADJUST
+ 0 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 10 | 605 |clk_125_0000MHzPLL0_ADJUST
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |clk_200_0000MHz
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 158 |clk_62_5000MHzPLL0_ADJUST
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 12 |fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 0 | 0 | 2 | 0 | 0 | 35 | 0 | 0 | 0 | 0 | 1 | 0 | 27 | 777 | Total
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+
+
+Clock-Region: <CLOCKREGION_X1Y6>
+ key resource utilizations (used/available): global-clocks - 2/10 ;
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)
+ FIFO | | | | | | | | | | | | | |
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 8 | 0 | 0 | 0 | 40 | 40 | 16 | 0 | 0 | 1 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ | | | | | | | | | | | | | | <Global clock Net Name>
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 103 |PCIe_Bridge/Bridge_Clk
+ 0 | 0 | 0 | 0 | 19 | 23 | 0 | 0 | 0 | 0 | 0 | 0 | 22 | 413 |clk_125_0000MHzPLL0_ADJUST
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 0 | 0 | 0 | 0 | 19 | 23 | 0 | 0 | 0 | 0 | 0 | 0 | 26 | 516 | Total
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+
+
+Clock-Region: <CLOCKREGION_X0Y7>
+ key resource utilizations (used/available): global-clocks - 2/10 ;
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)
+ FIFO | | | | | | | | | | | | | |
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 12 | 0 | 0 | 0 | 80 | 80 | 0 | 0 | 0 | 0 | 2 | 0 | 1600 | 3200 | <- (Available Resources in this Region)
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ | | | | | | | | | | | | | | <Global clock Net Name>
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 16 | 495 |clk_125_0000MHzPLL0_ADJUST
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 19 |clk_62_5000MHzPLL0_ADJUST
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 16 | 514 | Total
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+
+
+Clock-Region: <CLOCKREGION_X1Y7>
+ key resource utilizations (used/available): global-clocks - 1/10 ;
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)
+ FIFO | | | | | | | | | | | | | |
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 8 | 0 | 0 | 0 | 40 | 40 | 16 | 0 | 0 | 0 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ | | | | | | | | | | | | | | <Global clock Net Name>
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 46 | 327 |clk_125_0000MHzPLL0_ADJUST
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 46 | 327 | Total
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
+
+NOTE:
+The above detailed report is the initial placement of the logic after the clock region assignment. The final placement
+may be significantly different because of the various optimization steps which will follow. Specifically, logic blocks
+maybe moved to adjacent clock-regions as long as the "number of clocks per region" constraint is not violated.
+
+
+# END of Global Clock Net Loads Distribution Report:
+######################################################################################
+
+
+Phase 9.30 Global Clock Region Assignment (Checksum:7e049af9) REAL time: 10 mins 42 secs
+
+Phase 10.3 Local Placement Optimization
+Phase 10.3 Local Placement Optimization (Checksum:7e049af9) REAL time: 10 mins 43 secs
+
+Phase 11.5 Local Placement Optimization
+Phase 11.5 Local Placement Optimization (Checksum:7e049af9) REAL time: 10 mins 45 secs
+
+Phase 12.8 Global Placement
+.............................
+....
+.
+.......
+.....
+.......
+.......
+.......
+......
+........
+........
+........
+.........
+.........
+.........
+.
+.......
+......
+........
+.......
+.........
+........
+.........
+.......
+.
+.......
+.....
+.......
+.
+....
+...
+...
+......
+......
+......
+....
+.......
+......
+....
+.
+......
+......
+......
+....
+......
+.
+....
+...
+....
+.......
+......
+....
+...
+.......
+.........
+..
+.
+.....
+..
+...
+.......
+......
+.....
+......
+.....
+......
+......
+......
+.....
+.
+.....
+..
+.....
+...
+..
+......
+.......
+.......
+........
+...
+Phase 12.8 Global Placement (Checksum:4ba01660) REAL time: 15 mins 18 secs
+
+Phase 13.29 Local Placement Optimization
+Phase 13.29 Local Placement Optimization (Checksum:4ba01660) REAL time: 15 mins 18 secs
+
+Phase 14.5 Local Placement Optimization
+Phase 14.5 Local Placement Optimization (Checksum:4ba01660) REAL time: 15 mins 22 secs
+
+Phase 15.18 Placement Optimization
+Phase 15.18 Placement Optimization (Checksum:f81b02a1) REAL time: 18 mins 1 secs
+
+Phase 16.5 Local Placement Optimization
+Phase 16.5 Local Placement Optimization (Checksum:f81b02a1) REAL time: 18 mins 3 secs
+
+Phase 17.34 Placement Validation
+Phase 17.34 Placement Validation (Checksum:f81b02a1) REAL time: 18 mins 5 secs
+
+Total REAL time to Placer completion: 18 mins 7 secs
+Total CPU time to Placer completion: 17 mins 4 secs
+Running post-placement packing...
+Writing output files...
+
+Design Summary:
+Number of errors: 0
+Number of warnings: 50
+Slice Logic Utilization:
+ Number of Slice Registers: 12,128 out of 44,800 27%
+ Number used as Flip Flops: 12,127
+ Number used as Latches: 1
+ Number of Slice LUTs: 12,266 out of 44,800 27%
+ Number used as logic: 11,767 out of 44,800 26%
+ Number using O6 output only: 10,791
+ Number using O5 output only: 282
+ Number using O5 and O6: 694
+ Number used as Memory: 392 out of 13,120 2%
+ Number used as Dual Port RAM: 56
+ Number using O6 output only: 12
+ Number using O5 and O6: 44
+ Number used as Single Port RAM: 4
+ Number using O6 output only: 4
+ Number used as Shift Register: 332
+ Number using O6 output only: 332
+ Number used as exclusive route-thru: 107
+ Number of route-thrus: 438
+ Number using O6 output only: 382
+ Number using O5 output only: 51
+ Number using O5 and O6: 5
+
+Slice Logic Distribution:
+ Number of occupied Slices: 6,488 out of 11,200 57%
+ Number of LUT Flip Flop pairs used: 17,046
+ Number with an unused Flip Flop: 4,918 out of 17,046 28%
+ Number with an unused LUT: 4,780 out of 17,046 28%
+ Number of fully used LUT-FF pairs: 7,348 out of 17,046 43%
+ Number of unique control sets: 1,288
+ Number of slice register sites lost
+ to control set restrictions: 3,000 out of 44,800 6%
+
+ A LUT Flip Flop pair for this architecture represents one LUT paired with
+ one Flip Flop within a slice. A control set is a unique combination of
+ clock, reset, set, and enable signals for a registered element.
+ The Slice Logic Distribution report is not meaningful if the design is
+ over-mapped for a non-slice resource or if Placement fails.
+ OVERMAPPING of BRAM resources should be ignored if the design is
+ over-mapped for a non-BRAM resource or if placement fails.
+
+IO Utilization:
+ Number of bonded IOBs: 255 out of 640 39%
+ Number of LOCed IOBs: 255 out of 255 100%
+ IOB Flip Flops: 494
+ Number of bonded IPADs: 4 out of 50 8%
+ Number of bonded OPADs: 2 out of 32 6%
+
+Specific Feature Utilization:
+ Number of BlockRAM/FIFO: 23 out of 148 15%
+ Number using BlockRAM only: 21
+ Number using FIFO only: 2
+ Total primitives used:
+ Number of 36k BlockRAM used: 16
+ Number of 18k BlockRAM used: 6
+ Number of 36k FIFO used: 2
+ Total Memory used (KB): 756 out of 5,328 14%
+ Number of BUFG/BUFGCTRLs: 15 out of 32 46%
+ Number used as BUFGs: 15
+ Number of IDELAYCTRLs: 3 out of 22 13%
+ Number of BUFDSs: 1 out of 8 12%
+ Number of BUFIOs: 8 out of 80 10%
+ Number of DCM_ADVs: 1 out of 12 8%
+ Number of GTX_DUALs: 1 out of 8 12%
+ Number of PCIEs: 1 out of 3 33%
+ Number of LOCed PCIEs: 1 out of 1 100%
+ Number of PLL_ADVs: 2 out of 6 33%
+ Number of PPC440s: 1 out of 1 100%
+
+ Number of RPM macros: 64
+Average Fanout of Non-Clock Nets: 3.76
+
+Peak Memory Usage: 701 MB
+Total REAL time to MAP completion: 18 mins 45 secs
+Total CPU time to MAP completion: 17 mins 40 secs
+
+Mapping completed.
+See MAP report file "system_map.mrp" for details.
+
+
+
+#----------------------------------------------#
+# Starting program par
+# par -ise ../__xps/ise/system.ise -w -ol high system_map.ncd system.ncd
+system.pcf
+#----------------------------------------------#
+Release 11.2 - par L.46 (nt)
+Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
+PMSPEC -- Overriding Xilinx file <C:/devtools/Xilinx/11.1/EDK/data/parBmgr.acd> with local file
+<c:/devtools/Xilinx/11.1/ISE/data/parBmgr.acd>
+
+
+Loading device for application Rf_Device from file '5vfx70t.nph' in environment
+c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.
+ "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1
+
+Constraints file: system.pcf.
+ "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1
+WARNING:ConstraintSystem:65 - Constraint <NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(65973)]
+ overrides constraint <NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(65972)].
+
+
+Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
+Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)
+
+WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP
+ "TNM_CLK0" TS_MC_CLK * 4; ignored during timing analysis.
+INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please
+ consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.
+
+Device speed data version: "PRODUCTION 1.65 2009-06-01".
+
+
+
+Device Utilization Summary:
+
+ Number of BUFDSs 1 out of 8 12%
+ Number of BUFGs 15 out of 32 46%
+ Number of BUFIOs 8 out of 80 10%
+ Number of DCM_ADVs 1 out of 12 8%
+ Number of FIFO36_72_EXPs 2 out of 148 1%
+ Number of LOCed FIFO36_72_EXPs 2 out of 2 100%
+
+ Number of GTX_DUALs 1 out of 8 12%
+ Number of IDELAYCTRLs 3 out of 22 13%
+ Number of LOCed IDELAYCTRLs 3 out of 3 100%
+
+ Number of ILOGICs 131 out of 800 16%
+ Number of LOCed ILOGICs 8 out of 131 6%
+
+ Number of External IOBs 255 out of 640 39%
+ Number of LOCed IOBs 255 out of 255 100%
+
+ Number of IODELAYs 80 out of 800 10%
+ Number of LOCed IODELAYs 8 out of 80 10%
+
+ Number of External IPADs 4 out of 690 1%
+ Number of LOCed IPADs 4 out of 4 100%
+
+ Number of JTAGPPCs 1 out of 1 100%
+ Number of OLOGICs 236 out of 800 29%
+ Number of External OPADs 2 out of 32 6%
+ Number of LOCed OPADs 2 out of 2 100%
+
+ Number of PCIEs 1 out of 3 33%
+ Number of LOCed PCIEs 1 out of 1 100%
+
+ Number of PLL_ADVs 2 out of 6 33%
+ Number of PPC440s 1 out of 1 100%
+ Number of RAMB18X2SDPs 5 out of 148 3%
+ Number of RAMB36SDP_EXPs 6 out of 148 4%
+ Number of LOCed RAMB36SDP_EXPs 1 out of 6 16%
+
+ Number of RAMB36_EXPs 10 out of 148 6%
+ Number of LOCed RAMB36_EXPs 6 out of 10 60%
+
+ Number of Slice Registers 12128 out of 44800 27%
+ Number used as Flip Flops 12127
+ Number used as Latches 1
+ Number used as LatchThrus 0
+
+ Number of Slice LUTS 12266 out of 44800 27%
+ Number of Slice LUT-Flip Flop pairs 17046 out of 44800 38%
+
+
+Overall effort level (-ol): High
+Router effort level (-rl): High
+
+Starting initial Timing Analysis. REAL time: 51 secs
+Finished initial Timing Analysis. REAL time: 52 secs
+
+WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_sb_txrem_n<0> has no load. PAR will not attempt to route this
+ signal.
+WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_MB_TxREMn<0> has no load. PAR will not attempt to route this
+ signal.
+WARNING:Par:288 - The signal xps_bram_if_cntlr_1_port_BRAM_Addr<30> has no load. PAR will not attempt to route this
+ signal.
+WARNING:Par:288 - The signal xps_bram_if_cntlr_1_port_BRAM_Addr<31> has no load. PAR will not attempt to route this
+ signal.
+WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_MB_RxFull has no load. PAR will not attempt to route this
+ signal.
+Starting Router
+
+INFO:Route:501 - One or more directed routing (DIRT) constraints generated for a specific device have been found. Note
+ that DIRT strings are guaranteed to work only on the same device they were created for. If the DIRT constraints fail,
+ verify that the same connectivity is available in the target device for this implementation.
+
+Phase 1 : 82160 unrouted; REAL time: 1 mins 9 secs
+
+Phase 2 : 72970 unrouted; REAL time: 1 mins 22 secs
+
+Phase 3 : 28783 unrouted; REAL time: 3 mins 31 secs
+
+Phase 4 : 28815 unrouted; (Setup:0, Hold:103206, Component Switching Limit:0) REAL time: 3 mins 57 secs
+
+Updating file: system.ncd with current fully routed design.
+
+Phase 5 : 0 unrouted; (Setup:0, Hold:103693, Component Switching Limit:0) REAL time: 5 mins 9 secs
+
+Phase 6 : 0 unrouted; (Setup:0, Hold:103693, Component Switching Limit:0) REAL time: 5 mins 9 secs
+
+Phase 7 : 0 unrouted; (Setup:0, Hold:103693, Component Switching Limit:0) REAL time: 5 mins 9 secs
+
+Phase 8 : 0 unrouted; (Setup:0, Hold:103693, Component Switching Limit:0) REAL time: 5 mins 9 secs
+
+Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 7 mins 25 secs
+
+Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 7 mins 57 secs
+Total REAL time to Router completion: 7 mins 57 secs
+Total CPU time to Router completion: 7 mins 31 secs
+
+Partition Implementation Status
+-------------------------------
+
+ No Partitions were found in this design.
+
+-------------------------------
+
+Generating "PAR" statistics.
+
+**************************
+Generating Clock Report
+**************************
+
++---------------------+--------------+------+------+------------+-------------+
+| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
++---------------------+--------------+------+------+------------+-------------+
+|clk_125_0000MHzPLL0_ | | | | | |
+| ADJUST | BUFGCTRL_X0Y2| No | 3176 | 0.533 | 2.076 |
++---------------------+--------------+------+------+------------+-------------+
+|PCIe_Bridge/Bridge_C | | | | | |
+| lk |BUFGCTRL_X0Y28| No | 1481 | 0.519 | 2.085 |
++---------------------+--------------+------+------+------------+-------------+
+|clk_62_5000MHzPLL0_A | | | | | |
+| DJUST | BUFGCTRL_X0Y6| No | 501 | 0.313 | 2.062 |
++---------------------+--------------+------+------+------------+-------------+
+|clk_125_0000MHz90PLL | | | | | |
+| 0_ADJUST | BUFGCTRL_X0Y5| No | 165 | 0.262 | 2.028 |
++---------------------+--------------+------+------+------------+-------------+
+|PCIe_Bridge/PCIe_Bri | | | | | |
+|dge/comp_block_plus/ | | | | | |
+|comp_endpoint/core_c | | | | | |
+| lk |BUFGCTRL_X0Y27| No | 92 | 0.338 | 2.085 |
++---------------------+--------------+------+------+------------+-------------+
+|fpga_0_SysACE_Compac | | | | | |
+|tFlash_SysACE_CLK_pi | | | | | |
+| n_BUFGP | BUFGCTRL_X0Y8| No | 55 | 0.171 | 1.797 |
++---------------------+--------------+------+------+------------+-------------+
+|PCIe_Bridge/PCIe_Bri | | | | | |
+|dge/comp_block_plus/ | | | | | |
+|comp_endpoint/pcie_b | | | | | |
+| lk/gt_usrclk |BUFGCTRL_X0Y29| No | 6 | 0.065 | 1.886 |
++---------------------+--------------+------+------+------------+-------------+
+|fpga_0_Ethernet_MAC_ | | | | | |
+|PHY_rx_clk_pin_BUFGP | | | | | |
+| |BUFGCTRL_X0Y30| No | 12 | 0.086 | 1.874 |
++---------------------+--------------+------+------+------------+-------------+
+|fpga_0_Ethernet_MAC_ | | | | | |
+|PHY_tx_clk_pin_BUFGP | | | | | |
+| |BUFGCTRL_X0Y31| No | 6 | 0.004 | 1.941 |
++---------------------+--------------+------+------+------------+-------------+
+|DDR2_SDRAM/DDR2_SDRA | | | | | |
+|M/u_ddr2_top/u_mem_i | | | | | |
+|f_top/u_phy_top/u_ph | | | | | |
+| y_io/delayed_dqs<0> | IO Clk| No | 18 | 0.095 | 0.419 |
++---------------------+--------------+------+------+------------+-------------+
+|DDR2_SDRAM/DDR2_SDRA | | | | | |
+|M/u_ddr2_top/u_mem_i | | | | | |
+|f_top/u_phy_top/u_ph | | | | | |
+| y_io/delayed_dqs<1> | IO Clk| No | 18 | 0.083 | 0.380 |
++---------------------+--------------+------+------+------------+-------------+
+|DDR2_SDRAM/DDR2_SDRA | | | | | |
+|M/u_ddr2_top/u_mem_i | | | | | |
+|f_top/u_phy_top/u_ph | | |
+ | | |
+| y_io/delayed_dqs<2> | IO Clk| No | 18 | 0.101 | 0.425 |
++---------------------+--------------+------+------+------------+-------------+
+|DDR2_SDRAM/DDR2_SDRA | | | | | |
+|M/u_ddr2_top/u_mem_i | | | | | |
+|f_top/u_phy_top/u_ph | | | | | |
+| y_io/delayed_dqs<3> | IO Clk| No | 18 | 0.107 | 0.404 |
++---------------------+--------------+------+------+------------+-------------+
+|DDR2_SDRAM/DDR2_SDRA | | | | | |
+|M/u_ddr2_top/u_mem_i | | | | | |
+|f_top/u_phy_top/u_ph | | | | | |
+| y_io/delayed_dqs<5> | IO Clk| No | 18 | 0.101 | 0.425 |
++---------------------+--------------+------+------+------------+-------------+
+|DDR2_SDRAM/DDR2_SDRA | | | | | |
+|M/u_ddr2_top/u_mem_i | | | | | |
+|f_top/u_phy_top/u_ph | | | | | |
+| y_io/delayed_dqs<4> | IO Clk| No | 18 | 0.101 | 0.425 |
++---------------------+--------------+------+------+------------+-------------+
+|DDR2_SDRAM/DDR2_SDRA | | | | | |
+|M/u_ddr2_top/u_mem_i | | | | | |
+|f_top/u_phy_top/u_ph | | | | | |
+| y_io/delayed_dqs<6> | IO Clk| No | 18 | 0.096 | 0.393 |
++---------------------+--------------+------+------+------------+-------------+
+|DDR2_SDRAM/DDR2_SDRA | | | | | |
+|M/u_ddr2_top/u_mem_i | | | | | |
+|f_top/u_phy_top/u_ph | | | | | |
+| y_io/delayed_dqs<7> | IO Clk| No | 18 | 0.101 | 0.425 |
++---------------------+--------------+------+------+------------+-------------+
+| clk_125_0000MHzPLL0 | BUFGCTRL_X0Y1| No | 2 | 0.000 | 1.739 |
++---------------------+--------------+------+------+------------+-------------+
+| clk_200_0000MHz | BUFGCTRL_X0Y4| No | 4 | 0.100 | 1.879 |
++---------------------+--------------+------+------+------------+-------------+
+|RS232_Uart_1_Interru | | | | | |
+| pt | Local| | 1 | 0.000 | 0.625 |
++---------------------+--------------+------+------+------------+-------------+
+|PCIe_Bridge/PCIe_Bri | | | | | |
+|dge/comp_block_plus/ | | | | | |
+|comp_endpoint/pcie_b | | | | | |
+|lk/SIO/.pcie_gt_wrap | | | | | |
+| per_i/icdrreset<0> | Local| | 1 | 0.000 | 0.590 |
++---------------------+--------------+------+------+------------+-------------+
+|Ethernet_MAC/Etherne | | | | | |
+| t_MAC/phy_tx_clk_i | Local| | 9 | 3.273 | 3.994 |
++---------------------+--------------+------+------+------------+-------------+
+|ppc440_0_jtagppc_bus | | | | | |
+| _JTGC405TCK | Local| | 1 | 0.000 | 1.699 |
++---------------------+--------------+------+------+------------+-------------+
+
+* Net Skew is the difference between the minimum and maximum routing
+only delays for the net. Note this is different from Clock Skew which
+is reported in TRCE timing report. Clock Skew is the difference between
+the minimum and maximum path delays which includes logic delays.
+
+Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
+
+Number of Timing Constraints that were not applied: 5
+
+Asterisk (*) preceding a constraint indicates it was not met.
+ This may be due to a setup or hold violation.
+
+----------------------------------------------------------------------------------------------------------
+ Constraint | Check | Worst Case | Best Case | Timing | Timing
+ | | Slack | Achievable | Errors | Score
+----------------------------------------------------------------------------------------------------------
+ NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 n | SETUP | 0.026ns| 7.974ns| 0| 0
+ s HIGH 50% | HOLD | 0.030ns| | 0| 0
+ | MINPERIOD | 0.000ns| 8.000ns| 0| 0
+------------------------------------------------------------------------------------------------------
+ NET "PCIe_Bridge/PCIe_Bridge/comp_block_p | SETUP | 0.026ns| 3.974ns| 0| 0
+ lus/comp_endpoint/core_clk" PERIOD = | HOLD | 0.315ns| | 0| 0
+ 4 ns HIGH 50% | MINPERIOD | 0.000ns| 4.000ns| 0| 0
+------------------------------------------------------------------------------------------------------
+ NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.012ns| 0.838ns| 0| 0
+ _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | |
+ dqs[7].u_iob_dqs/en_dqs_sync" MAX | | | | |
+ DELAY = 0.85 ns | | | | |
+------------------------------------------------------------------------------------------------------
+ NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.015ns| 0.835ns| 0| 0
+ _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | |
+ dqs[0].u_iob_dqs/en_dqs_sync" MAX | | | | |
+ DELAY = 0.85 ns | | | | |
+------------------------------------------------------------------------------------------------------
+ TS_DQ_CE = MAXDELAY FROM TIMEGRP "TNM_DQ_ | SETUP | 0.021ns| 1.879ns| 0| 0
+ CE_IDDR" TO TIMEGRP "TNM_DQS_FLOPS" | HOLD | 1.026ns| | 0| 0
+ 1.9 ns | | | | |
+------------------------------------------------------------------------------------------------------
+ TS_clock_generator_0_clock_generator_0_PL | SETUP | 0.027ns| 7.973ns| 0| 0
+ L0_CLK_OUT_2_ = PERIOD TIMEGRP "c | HOLD | 0.021ns| | 0| 0
+ lock_generator_0_clock_generator_0_PLL0_C | | | | |
+ LK_OUT_2_" TS_sys_clk_pin * 1.25 | | | | |
+ HIGH 50% | | | | |
+------------------------------------------------------------------------------------------------------
+ NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.045ns| 0.805ns| 0| 0
+ _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | |
+ dqs[1].u_iob_dqs/en_dqs_sync" MAX | | | | |
+ DELAY = 0.85 ns | | | | |
+------------------------------------------------------------------------------------------------------
+ NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.045ns| 0.805ns| 0| 0
+ _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | |
+ dqs[5].u_iob_dqs/en_dqs_sync" MAX | | | | |
+ DELAY = 0.85 ns | | | | |
+------------------------------------------------------------------------------------------------------
+ NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.047ns| 0.803ns| 0| 0
+ _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | |
+ dqs[2].u_iob_dqs/en_dqs_sync" MAX | | | | |
+ DELAY = 0.85 ns | | | | |
+------------------------------------------------------------------------------------------------------
+ NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.047ns| 0.803ns| 0| 0
+ _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | |
+ dqs[3].u_iob_dqs/en_dqs_sync" MAX | | | | |
+ DELAY = 0.85 ns | | | | |
+------------------------------------------------------------------------------------------------------
+ NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.047ns| 0.803ns| 0| 0
+ _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | |
+ dqs[4].u_iob_dqs/en_dqs_sync" MAX | | | | |
+ DELAY = 0.85 ns | | | | |
+------------------------------------------------------------------------------------------------------
+ NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.047ns| 0.803ns| 0| 0
+ _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | |
+ dqs[6].u_iob_dqs/en_dqs_sync" MAX | | | | |
+ DELAY = 0.85 ns | | | | |
+------------------------------------------------------------------------------------------------------
+ NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.068ns| 0.532ns| 0| 0
+ _top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | |
+ qs<1>" MAXDELAY = 0.6 ns | | | | |
+------------------------------------------------------------------------------------------------------
+ NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0
+ _top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | |
+ qs<0>" MAXDELAY = 0.6 ns | | | | |
+------------------------------------------------------------------------------------------------------
+ NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0
+ _top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | |
+ qs<2>" MAXDELAY = 0.6 ns | | | | |
+------------------------------------------------------------------------------------------------------
+ NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0
+ _top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | |
+ qs<3>" MAXDELAY = 0.6 ns | | | | |
+------------------------------------------------------------------------------------------------------
+ NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0
+ _top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | |
+ qs<4>" MAXDELAY = 0.6 ns | | | | |
+------------------------------------------------------------------------------------------------------
+ NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0
+ _top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | |
+ qs<5>" MAXDELAY = 0.6 ns | | | | |
+------------------------------------------------------------------------------------------------------
+ NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0
+ _top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | |
+ qs<6>" MAXDELAY = 0.6 ns | | | | |
+------------------------------------------------------------------------------------------------------
+ NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0
+ _top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | |
+ qs<7>" MAXDELAY = 0.6 ns | | | | |
+------------------------------------------------------------------------------------------------------
+ TS_PCIe_PLB = MAXDELAY FROM TIMEGRP "Brid | SETUP | 0.188ns| 7.812ns| 0| 0
+ ge_Clk" TO TIMEGRP "SPLB_Clk" 8 ns | HOLD | 0.516ns| | 0| 0
+ DATAPATHONLY | | | | |
+------------------------------------------------------------------------------------------------------
+ TS_MC_CLK = PERIOD TIMEGRP "mc_clk" 5 ns | MINPERIOD | 1.010ns| 3.990ns| 0| 0
+ HIGH 50% | | | | |
+------------------------------------------------------------------------------------------------------
+ TS_PLB_PCIe = MAXDELAY FROM TIMEGRP "SPLB | SETUP | 1.252ns| 6.748ns| 0| 0
+ _Clk" TO TIMEGRP "Bridge_Clk" 8 ns | HOLD | 0.451ns| | 0| 0
+ DATAPATHONLY | | | | |
+------------------------------------------------------------------------------------------------------
+ TSRXIN_Ethernet_MAC = MAXDELAY FROM TIMEG | MAXDELAY | 1.700ns| 4.300ns| 0| 0
+ RP "PADS" TO TIMEGRP "RXCLK_GRP_E | HOLD | 1.060ns| | 0| 0
+ thernet_MAC" 6 ns | | | | |
+------------------------------------------------------------------------------------------------------
+ TS_clock_generator_0_clock_generator_0_PL | SETUP | 2.073ns| 5.466ns| 0| 0
+ L0_CLK_OUT_0_ = PERIOD TIMEGRP "c | HOLD | 0.307ns| | 0| 0
+ lock_generator_0_clock_generator_0_PLL0_C | | | | |
+ LK_OUT_0_" TS_sys_clk_pin * 1.25 | | | | |
+ PHASE 2 ns HIGH 50% | | | | |
+------------------------------------------------------------------------------------------------------
+ TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | MINLOWPULSE | 6.000ns| 4.000ns| 0| 0
+ pin" 100 MHz HIGH 50% | | | | |
+------------------------------------------------------------------------------------------------------
+ TS_clock_generator_0_clock_generator_0_PL | SETUP | 3.700ns| 8.600ns| 0| 0
+ L0_CLK_OUT_4_ = PERIOD TIMEGRP "c | HOLD | 0.153ns| | 0| 0
+ lock_generator_0_clock_generator_0_PLL0_C | | | | |
+ LK_OUT_4_" TS_sys_clk_pin * 0.625 | | | | |
+ HIGH 50% | | | | |
+------------------------------------------------------------------------------------------------------
+ TS_clock_generator_0_clock_generator_0_PL | SETUP | 3.950ns| 1.050ns| 0| 0
+ L0_CLK_OUT_3_ = PERIOD TIMEGRP "c | HOLD | 0.465ns| | 0| 0
+ lock_generator_0_clock_generator_0_PLL0_C | MINLOWPULSE | 3.946ns| 1.054ns| 0| 0
+ LK_OUT_3_" TS_sys_clk_pin * 2 HIG | | | | |
+ H 50% | | | | |
+------------------------------------------------------------------------------------------------------
+ NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_B | NETSKEW | 4.392ns| 0.608ns| 0| 0
+ UFGP" MAXSKEW = 5 ns | | | | |
+------------------------------------------------------------------------------------------------------
+ NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_B | NETSKEW | 4.789ns| 0.211ns| 0| 0
+ UFGP" MAXSKEW = 5 ns | | | | |
+------------------------------------------------------------------------------------------------------
+ TS_clock_generator_0_clock_generator_0_PL | MINPERIOD | 4.900ns| 3.100ns| 0| 0
+ L0_CLK_OUT_1_ = PERIOD TIMEGRP "c | | | | |
+ lock_generator_0_clock_generator_0_PLL0_C | | | | |
+ LK_OUT_1_" TS_sys_clk_pin * 1.25 | | | | |
+ HIGH 50% | | | | |
+------------------------------------------------------------------------------------------------------
+ TSTXOUT_Ethernet_MAC = MAXDELAY FROM TIME | MAXDELAY | 7.423ns| 2.577ns| 0| 0
+ GRP "TXCLK_GRP_Ethernet_MAC" TO T | | | | |
+ IMEGRP "PADS" 10 ns | | | | |
+------------------------------------------------------------------------------------------------------
+ NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_B | SETUP | 10.092ns| 11.165ns| 0| 0
+ UFGP" PERIOD = 40 ns HIGH 14 ns | HOLD | 0.473ns| | 0| 0
+------------------------------------------------------------------------------------------------------
+ TS_MC_PHY_INIT_DATA_SEL_90 = MAXDELAY FRO | SETUP | 13.832ns| 6.168ns| 0| 0
+ M TIMEGRP "TNM_PHY_INIT_DATA_SEL" TO | HOLD | 0.471ns| | 0| 0
+ TIMEGRP "TNM_CLK90" TS_MC_CLK * 4 | | | | |
+------------------------------------------------------------------------------------------------------
+ TS_MC_PHY_INIT_DATA_SEL_0 = MAXDELAY FROM | SETUP | 16.202ns| 3.798ns| 0| 0
+ TIMEGRP "TNM_PHY_INIT_DATA_SEL" TO | HOLD | 0.049ns| | 0| 0
+ TIMEGRP "TNM_CLK0" TS_MC_CLK * 4 | | | | |
+------------------------------------------------------------------------------------------------------
+ TS_MC_RDEN_DLY = MAXDELAY FROM TIMEGRP "T | SETUP | 17.943ns| 2.057ns| 0| 0
+ NM_RDEN_DLY" TO TIMEGRP "TNM_CLK0" | HOLD | 0.295ns| | 0| 0
+ TS_MC_CLK * 4 | | | | |
+------------------------------------------------------------------------------------------------------
+ TS_MC_GATE_DLY = MAXDELAY FROM TIMEGRP "T | SETUP | 17.975ns| 2.025ns| 0| 0
+ NM_GATE_DLY" TO TIMEGRP "TNM_CLK0" | HOLD | 0.030ns| | 0| 0
+ TS_MC_CLK * 4 | | | | |
+------------------------------------------------------------------------------------------------------
+ TS_MC_CAL_RDEN_DLY = MAXDELAY FROM TIMEGR | SETUP | 18.085ns| 1.915ns| 0| 0
+ P "TNM_CAL_RDEN_DLY" TO TIMEGRP " | HOLD | 0.096ns| | 0| 0
+ TNM_CLK0" TS_MC_CLK * 4 | | | | |
+------------------------------------------------------------------------------------------------------
+ NET "fpga_0_SysACE_CompactFlash_SysACE_CL | SETUP | 26.710ns| 3.290ns| 0| 0
+ K_pin_BUFGP/IBUFG" PERIOD = 30 ns | HOLD | 0.465ns| | 0| 0
+ HIGH 50% | | | | |
+------------------------------------------------------------------------------------------------------
+ NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_B | SETUP | 32.431ns| 7.569ns| 0| 0
+ UFGP" PERIOD = 40 ns HIGH 14 ns | HOLD | 0.351ns| | 0| 0
+------------------------------------------------------------------------------------------------------
+ Pin to Pin Skew Constraint | MAXDELAY | 2106523.523ns| 2106523.837ns| 0| 0
+------------------------------------------------------------------------------------------------------
+ TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGR | N/A | N/A| N/A| N/A| N/A
+ P "TNM_RDEN_SEL_MUX" TO TIMEGRP " | | | | |
+ TNM_CLK0" TS_MC_CLK * 4 | | | | |
+------------------------------------------------------------------------------------------------------
+ NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 n | N/A | N/A| N/A| N/A| N/A
+ s HIGH 50% | | | | |
+------------------------------------------------------------------------------------------------------
+
+
+Derived Constraint Report
+Derived Constraints for TS_MC_CLK
++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+| | Period | Actual Period | Timing Errors | Paths Analyzed |
+| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
+| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+|TS_MC_CLK | 5.000ns| 3.990ns| 1.542ns| 0| 0| 0| 345|
+| TS_MC_PHY_INIT_DATA_SEL_0 | 20.000ns| 3.798ns| N/A| 0| 0| 21| 0|
+| TS_MC_PHY_INIT_DATA_SEL_90 | 20.000ns| 6.168ns| N/A| 0| 0| 274| 0|
+| TS_MC_GATE_DLY | 20.000ns| 2.025ns| N/A| 0| 0| 40| 0|
+| TS_MC_RDEN_DLY | 20.000ns| 2.057ns| N/A| 0| 0| 5| 0|
+| TS_MC_CAL_RDEN_DLY | 20.000ns| 1.915ns| N/A| 0| 0| 5| 0|
+| TS_MC_RDEN_SEL_MUX | 20.000ns| N/A| N/A| 0| 0| 0| 0|
++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+
+Derived Constraints for TS_sys_clk_pin
++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+| | Period | Actual Period | Timing Errors | Paths Analyzed |
+| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
+| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+|TS_sys_clk_pin | 10.000ns| 4.000ns| 9.966ns| 0| 0| 0| 636358|
+| TS_clock_generator_0_clock_gen| 8.000ns| 5.466ns| N/A| 0| 0| 626| 0|
+| erator_0_PLL0_CLK_OUT_0_ | | | | | | | |
+| TS_clock_generator_0_clock_gen| 8.000ns| 3.100ns| N/A| 0| 0| 0| 0|
+| erator_0_PLL0_CLK_OUT_1_ | | | | | | | |
+| TS_clock_generator_0_clock_gen| 8.000ns| 7.973ns| N/A| 0| 0| 624688| 0|
+| erator_0_PLL0_CLK_OUT_2_ | | | | | | | |
+| TS_clock_generator_0_clock_gen| 5.000ns| 1.054ns| N/A| 0| 0| 2| 0|
+| erator_0_PLL0_CLK_OUT_3_ | | | | | | | |
+| TS_clock_generator_0_clock_gen| 16.000ns| 8.600ns| N/A| 0| 0| 11042| 0|
+| erator_0_PLL0_CLK_OUT_4_ | | | | | | | |
++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+
+All constraints were met.
+INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
+ constraint does not cover any paths or that it has no requested value.
+
+
+Generating Pad Report.
+
+All signals are completely routed.
+
+WARNING:Par:283 - There are 5 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
+
+Loading device for application Rf_Device from file '5vlx50t.nph' in environment
+c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.
+INFO:ParHelpers:197 - Number of "Exact" mode Directed Routing Constraints: 128
+INFO:ParHelpers:199 - All "EXACT" mode Directed Routing constrained nets successfully routed. The number of constraints
+ found: 128, number successful: 128
+Total REAL time to PAR completion: 9 mins 1 secs
+Total CPU time to PAR completion: 8 mins 19 secs
+
+Peak Memory Usage: 653 MB
+
+Placer: Placement generated during map.
+Routing: Completed - No errors found.
+Timing: Completed - No errors found.
+
+Number of error messages: 0
+Number of warning messages: 9
+Number of info messages: 4
+
+Writing design to file system.ncd
+
+
+
+PAR done!
+
+
+
+#----------------------------------------------#
+# Starting program post_par_trce
+# trce -ise ../__xps/ise/system.ise -e 3 -xml system.twx system.ncd system.pcf
+#----------------------------------------------#
+Release 11.2 - Trace (nt)
+Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
+
+
+PMSPEC -- Overriding Xilinx file
+<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file
+<c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>
+Loading device for application Rf_Device from file '5vfx70t.nph' in environment
+c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.
+ "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1
+WARNING:ConstraintSystem:65 - Constraint <NET "PCIe_Bridge/Bridge_Clk" PERIOD =
+ 8 ns HIGH 50%;> [system.pcf(65973)] overrides constraint <NET
+ "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(65972)].
+
+WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM
+ TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP "TNM_CLK0" TS_MC_CLK * 4;
+ ignored during timing analysis.
+INFO:Timing:3386 - Intersecting Constraints found and resolved. For more
+ information, see the TSI report. Please consult the Xilinx Command Line
+ Tools User Guide for information on generating a TSI report.
+--------------------------------------------------------------------------------
+Release 11.2 Trace (nt)
+Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
+
+trce -ise ../__xps/ise/system.ise -e 3 -xml system.twx system.ncd system.pcf
+
+
+Design file: system.ncd
+Physical constraint file: system.pcf
+Device,speed: xc5vfx70t,-1 (PRODUCTION 1.65 2009-06-01, STEPPING
+level 0)
+Report level: error report
+--------------------------------------------------------------------------------
+
+INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
+ option. All paths that are not constrained will be reported in the
+ unconstrained paths section(s) of the report.
+INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a
+ 50 Ohm transmission line loading model. For the details of this model, and
+ for more information on accounting for different loading conditions, please
+ see the device datasheet.
+
+
+Timing summary:
+---------------
+
+Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
+
+Constraints cover 826342 paths, 18 nets, and 74598 connections
+
+Design statistics:
+ Minimum period: 11.165ns (Maximum frequency: 89.566MHz)
+ Maximum path delay from/to any node: 7.812ns
+ Maximum net delay: 0.838ns
+ Maximum net skew: 0.608ns
+
+
+Analysis completed Tue Jun 30 21:57:31 2009
+--------------------------------------------------------------------------------
+
+Generating Report ...
+
+Number of warnings: 2
+Number of info messages: 3
+Total time: 1 mins 36 secs
+
+
+xflow done!
+touch __xps/system_routed
+xilperl C:/devtools/Xilinx/11.1/EDK/data/fpga_impl/observe_par.pl -error yes implementation/system.par
+Analyzing implementation/system.par
+*********************************************
+Running Bitgen..
+*********************************************
+cd implementation; bitgen -w -f bitgen.ut system; cd ..
+Release 11.2 - Bitgen L.46 (nt)
+Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
+PMSPEC -- Overriding Xilinx file
+<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file
+<c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>
+Loading device for application Rf_Device from file '5vfx70t.nph' in environment
+c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.
+ "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1
+Opened constraints file system.pcf.
+
+Tue Jun 30 21:58:01 2009
+
+Running DRC.
+WARNING:PhysDesignRules:1842 - One or more GTXs are being used in this design.
+ Evaluate the SelectIO-To-GTX Crosstalk section of the Virtex-5 RocketIO GTX
+ Transceiver User Guide to ensure that the design SelectIO usage meets the
+ guidelines to minimize the impact on GTX performance.
+WARNING:PhysDesignRules:372 - Gated clock. Clock net
+ PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_w
+ rapper_i/icdrreset<0> is sourced by a combinatorial pin. This is not good
+ design practice. Use the CE pin to control the loading of data into the
+ flip-flop.
+WARNING:PhysDesignRules:372 - Gated clock. Clock net
+ Ethernet_MAC/Ethernet_MAC/phy_tx_clk_i is sourced by a combinatorial pin.
+ This is not good design practice. Use the CE pin to control the loading of
+ data into the flip-flop.
+WARNING:PhysDesignRules:367 - The signal
+ <PCIe_Bridge/PCIe_Bridge/sig_sb_txrem_n<0>> is incomplete. The signal does
+ not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal
+ <PCIe_Bridge/PCIe_Bridge/sig_MB_TxREMn<0>> is incomplete. The signal does not
+ drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal
+ <xps_bram_if_cntlr_1_port_BRAM_Addr<30>> is incomplete. The signal does not
+ drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal
+ <xps_bram_if_cntlr_1_port_BRAM_Addr<31>> is incomplete. The signal does not
+ drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <PCIe_Bridge/PCIe_Bridge/sig_MB_RxFull>
+ is incomplete. The signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:1269 - Dangling pins on
+ block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d
+ qs[1].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not
+ used.
+WARNING:PhysDesignRules:1273 - Dangling pins on
+ block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d
+ qs[1].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF
+ Flip-flop but the SRVAL_Q1 set/reset value is not configured.
+WARNING:PhysDesignRules:1269 - Dangling pins on
+ block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d
+ qs[4].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not
+ used.
+WARNING:PhysDesignRules:1273 - Dangling pins on
+ block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d
+ qs[4].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF
+ Flip-flop but the SRVAL_Q1 set/reset value is not configured.
+WARNING:PhysDesignRules:1269 - Dangling pins on
+ block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d
+ qs[7].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not
+ used.
+WARNING:PhysDesignRules:1273 - Dangling pins on
+ block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d
+ qs[7].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF
+ Flip-flop but the SRVAL_Q1 set/reset value is not configured.
+WARNING:PhysDesignRules:1269 - Dangling pins on
+ block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d
+ qs[2].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not
+ used.
+WARNING:PhysDesignRules:1273 - Dangling pins on
+ block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d
+ qs[2].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF
+ Flip-flop but the SRVAL_Q1 set/reset value is not configured.
+WARNING:PhysDesignRules:1269 - Dangling pins on
+ block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d
+ qs[5].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not
+ used.
+WARNING:PhysDesignRules:1273 - Dangling pins on
+ block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d
+ qs[5].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF
+ Flip-flop but the SRVAL_Q1 set/reset value is not configured.
+WARNING:PhysDesignRules:1269 - Dangling pins on
+ block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d
+ qs[0].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not
+ used.
+WARNING:PhysDesignRules:1273 - Dangling pins on
+ block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d
+ qs[0].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF
+ Flip-flop but the SRVAL_Q1 set/reset value is not configured.
+WARNING:PhysDesignRules:1269 - Dangling pins on
+ block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d
+ qs[3].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not
+ used.
+WARNING:PhysDesignRules:1273 - Dangling pins on
+ block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d
+ qs[3].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF
+ Flip-flop but the SRVAL_Q1 set/reset value is not configured.
+WARNING:PhysDesignRules:1269 - Dangling pins on
+ block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d
+ qs[6].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not
+ used.
+WARNING:PhysDesignRules:1273 - Dangling pins on
+ block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d
+ qs[6].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF
+ Flip-flop but the SRVAL_Q1 set/reset value is not configured.
+DRC detected 0 errors and 24 warnings. Please see the previously displayed
+individual error or warning messages for more details.
+Creating bit map...
+Saving bit stream in "system.bit".
+Bitstream generation is complete.
+
+
+Done! +
+Writing filter settings.... +
+Done writing filter settings to: + C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters +
+Done writing Tab View settings to: + C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.gui +
+WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 237 - deprecated core for architecture 'virtex5fx'! +
+WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 282 - deprecated core for architecture 'virtex5fx'! +
+Generating Block Diagram to Buffer +
+Generated Block Diagram SVG +
+At Local date and time: Sat Jul 04 20:43:06 2009 + make -f system.make download started... +
+cp -f /cygdrive/c/devtools/Xilinx/11.1/EDK/sw/lib/ppc440/ppc440_bootloop.elf bootloops/ppc440_0.elf
+*********************************************
+Initializing BRAM contents of the bitstream
+*********************************************
+bitinit -p xc5vfx70tff1136-1 system.mhs -pe ppc440_0 bootloops/ppc440_0.elf \
+-bt implementation/system.bit -o implementation/download.bit
+
+bitinit version Xilinx EDK 11.2 Build EDK_LS3.47
+Copyright (c) Xilinx Inc. 2002.
+
+Parsing MHS File system.mhs...
+WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
+ C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+ 251 - deprecated core for architecture 'virtex5fx'!
+WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
+ C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
+ 296 - deprecated core for architecture 'virtex5fx'!
+
+Overriding IP level properties ...
+
+Performing IP level DRCs on properties...
+
+Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
+Address Map for Processor ppc440_0
+ (0b0000000000-0b0011111111) ppc440_0
+ (0000000000-0x0fffffff) DDR2_SDRAM ppc440_0_PPC440MC
+ (0x81000000-0x8100ffff) Ethernet_MAC plb_v46_0
+ (0x81400000-0x8140ffff) Push_Buttons_5Bit plb_v46_0
+ (0x81420000-0x8142ffff) LEDs_Positions plb_v46_0
+ (0x81440000-0x8144ffff) LEDs_8Bit plb_v46_0
+ (0x81460000-0x8146ffff) DIP_Switches_8Bit plb_v46_0
+ (0x81600000-0x8160ffff) IIC_EEPROM plb_v46_0
+ (0x81800000-0x8180ffff) xps_intc_0 plb_v46_0
+ (0x83600000-0x8360ffff) SysACE_CompactFlash plb_v46_0
+ (0x84000000-0x8400ffff) RS232_Uart_1 plb_v46_0
+ (0x85c00000-0x85c0ffff) PCIe_Bridge plb_v46_0
+ (0xc0000000-0xdfffffff) PCIe_Bridge plb_v46_0
+ (0xe0000000-0xefffffff) PCIe_Bridge plb_v46_0
+ (0xf8000000-0xf80fffff) SRAM plb_v46_0
+ (0xffffe000-0xffffffff) xps_bram_if_cntlr_1 plb_v46_0
+INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_
+ 01_a\data\ppc440_virtex5_v2_1_0.mpd line 175 - tool is overriding PARAMETER
+ C_SPLB0_P2P value to 0
+
+Computing clock values...
+INFO:EDK:1432 - Frequency for Top-Level Input Clock
+ 'fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin' is not specified. Clock DRCs will not be
+ performed for IPs connected to that clock port, unless they are connected
+ through the clock generator IP.
+
+INFO:EDK:1432 - Frequency for Top-Level Input Clock
+ 'fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin' is not specified. Clock DRCs will not be
+ performed for IPs connected to that clock port, unless they are connected
+ through the clock generator IP.
+
+INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
+ ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER
+ C_PLBV46_NUM_MASTERS value to 1
+INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
+ ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER
+ C_PLBV46_NUM_SLAVES value to 12
+INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
+ ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER
+ C_PLBV46_MID_WIDTH value to 1
+INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
+ ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH
+ value to 128
+INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
+ v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 75 - tool is overriding
+ PARAMETER C_SPLB_DWIDTH value to 128
+INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
+ v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 76 - tool is overriding
+ PARAMETER C_SPLB_NUM_MASTERS value to 1
+INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
+ v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 80 - tool is overriding
+ PARAMETER C_SPLB_SMALLEST_MASTER value to 128
+INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
+ \data\bram_block_v2_1_0.mpd line 69 - tool is overriding PARAMETER C_MEMSIZE
+ value to 0x2000
+INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
+ \data\bram_block_v2_1_0.mpd line 70 - tool is overriding PARAMETER
+ C_PORT_DWIDTH value to 64
+INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
+ \data\bram_block_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_NUM_WE
+ value to 8
+INFO:EDK:1560 - IPNAME:xps_uartlite INSTANCE:RS232_Uart_1 -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_uartlite_v1_01
+ _a\data\xps_uartlite_v2_1_0.mpd line 73 - tool is overriding PARAMETER
+ C_SPLB_DWIDTH value to 128
+INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_8Bit -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
+ ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH
+ value to 128
+INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_Positions -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
+ ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH
+ value to 128
+INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:Push_Buttons_5Bit -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
+ ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH
+ value to 128
+INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:DIP_Switches_8Bit -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
+ ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH
+ value to 128
+INFO:EDK:1560 - IPNAME:xps_iic INSTANCE:IIC_EEPROM -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_iic_v2_01_a\da
+ ta\xps_iic_v2_1_0.mpd line 79 - tool is overriding PARAMETER C_SPLB_DWIDTH
+ value to 128
+INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_
+ a\data\xps_mch_emc_v2_1_0.mpd line 82 - tool is overriding PARAMETER
+ C_SPLB_DWIDTH value to 128
+INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_
+ a\data\xps_mch_emc_v2_1_0.mpd line 84 - tool is overriding PARAMETER
+ C_SPLB_SMALLEST_MASTER value to 128
+INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
+ b\data\plbv46_pcie_v2_1_0.mpd line 86 - tool is overriding PARAMETER
+ C_MPLB_DWIDTH value to 128
+INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
+ b\data\plbv46_pcie_v2_1_0.mpd line 87 - tool is overriding PARAMETER
+ C_MPLB_SMALLEST_SLAVE value to 128
+INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
+ b\data\plbv46_pcie_v2_1_0.mpd line 89 - tool is overriding PARAMETER
+ C_SPLB_MID_WIDTH value to 1
+INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
+ b\data\plbv46_pcie_v2_1_0.mpd line 90 - tool is overriding PARAMETER
+ C_SPLB_NUM_MASTERS value to 1
+INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
+ b\data\plbv46_pcie_v2_1_0.mpd line 91 - tool is overriding PARAMETER
+ C_SPLB_SMALLEST_MASTER value to 128
+INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
+ b\data\plbv46_pcie_v2_1_0.mpd line 95 - tool is overriding PARAMETER
+ C_SPLB_DWIDTH value to 128
+INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
+ ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER
+ C_PLBV46_NUM_MASTERS value to 1
+INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
+ ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER
+ C_PLBV46_NUM_SLAVES value to 1
+INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
+ ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER
+ C_PLBV46_MID_WIDTH value to 1
+INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
+ ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH
+ value to 128
+INFO:EDK:1560 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_ethernetlite_v
+ 2_01_a\data\xps_ethernetlite_v2_1_0.mpd line 75 - tool is overriding
+ PARAMETER C_SPLB_DWIDTH value to 128
+INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
+ \data\xps_sysace_v2_1_0.mpd line 72 - tool is overriding PARAMETER
+ C_SPLB_DWIDTH value to 128
+INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
+ \data\xps_sysace_v2_1_0.mpd line 74 - tool is overriding PARAMETER
+ C_SPLB_MID_WIDTH value to 1
+INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
+ \data\xps_sysace_v2_1_0.mpd line 75 - tool is overriding PARAMETER
+ C_SPLB_NUM_MASTERS value to 1
+INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -
+ C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d
+ ata\xps_intc_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_SPLB_DWIDTH
+ value to 128
+
+Checking platform address map ...
+
+Initializing Memory...
+Running Data2Mem with the following command:
+data2mem -bm "implementation/system_bd" -bt "implementation/system.bit" -bd
+"bootloops/ppc440_0.elf" tag ppc440_0 -o b implementation/download.bit
+Memory Initialization completed successfully.
+
+*********************************************
+Downloading Bitstream onto the target board
+*********************************************
+impact -batch etc/download.cmd
+Release 11.2 - iMPACT L.46 (nt)
+Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
+Preference Table
+Name Setting
+StartupClock Auto_Correction
+AutoSignature False
+KeepSVF False
+ConcurrentMode False
+UseHighz False
+ConfigOnFailure Stop
+UserLevel Novice
+MessageLevel Detailed
+svfUseTime false
+SpiByteSwap Auto_Correction
+AutoDetecting cable. Please wait.
+Connecting to cable (Usb Port - USB21).
+Checking cable driver.
+ Driver file xusb_xp2.sys found.
+ Driver version: src=2301, dest=2301.
+ Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS
+13:58:07, version = 900.
+ Cable PID = 0008.
+ Max current requested during enumeration is 300 mA.
+Type = 0x0005.
+ Cable Type = 3, Revision = 0.
+ Setting cable speed to 6 MHz.
+Cable connection established.
+Firmware version = 2401.
+File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.
+Firmware hex file version = 2401.
+PLD file version = 200Dh.
+ PLD version = 200Dh.
+Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6
+INFO:iMPACT:1777 -
+ Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...
+
+----------------------------------------------------------------------
+----------------------------------------------------------------------
+'1': : Manufacturer's ID = Xilinx xccace, Version : 0
+----------------------------------------------------------------------
+----------------------------------------------------------------------
+'2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5
+INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.
+INFO:iMPACT:1777 -
+ Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...
+INFO:iMPACT:501 - '1': Added Device xccace successfully.
+
+----------------------------------------------------------------------
+----------------------------------------------------------------------
+'3': : Manufacturer's ID = Xilinx xcf32p, Version : 15
+INFO:iMPACT:1777 -
+ Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...
+INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.
+
+----------------------------------------------------------------------
+----------------------------------------------------------------------
+'4': : Manufacturer's ID = Xilinx xcf32p, Version : 15
+----------------------------------------------------------------------
+----------------------------------------------------------------------
+done.
+Elapsed time = 0 sec.
+Elapsed time = 0 sec.
+'5': Loading file 'implementation/download.bit' ...
+INFO:iMPACT:1777 -
+ Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...
+INFO:iMPACT:501 - '1': Added Device xcf32p successfully.
+INFO:iMPACT:501 - '1': Added Device xcf32p successfully.
+
+done.
+UserID read from the bitstream file = 0xFFFFFFFF.
+----------------------------------------------------------------------
+----------------------------------------------------------------------
+----------------------------------------------------------------------
+Maximum TCK operating frequency for this device chain: 10000000.
+Validating chain...
+Boundary-scan chain validated successfully.
+5: Device Temperature: Current Reading: 72.52 C, Min. Reading: 30.69 C, Max.
+Reading: 74.49 C
+5: VCCINT Supply: Current Reading: 0.993 V, Min. Reading: 0.993 V, Max.
+Reading: 1.002 V
+5: VCCAUX Supply: Current Reading: 2.496 V, Min. Reading: 2.493 V, Max.
+Reading: 2.508 V
+INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.
+
+'5': Programming device...
+ Match_cycle = 2.
+done.
+'5': Reading status register contents...
+CRC error : 0
+Decryptor security set : 0
+DCM locked : 1
+DCI matched : 1
+End of startup signal from Startup block : 1
+status of GTS_CFG_B : 1
+status of GWE : 1
+status of GHIGH : 1
+value of MODE pin M0 : 1
+value of MODE pin M1 : 0
+Value of MODE pin M2 : 1
+Internal signal indicates when housecleaning is completed: 1
+Value driver in from INIT pad : 1
+Internal signal indicates that chip is configured : 1
+Value of DONE pin : 1
+Indicates when ID value written does not match chip ID: 0
+Decryptor error Signal : 0
+System Monitor Over-Temperature Alarm : 0
+startup_state[18] CFG startup state machine : 0
+startup_state[19] CFG startup state machine : 0
+startup_state[20] CFG startup state machine : 1
+E-fuse program voltage available : 0
+SPI Flash Type[22] Select : 1
+SPI Flash Type[23] Select : 1
+SPI Flash Type[24] Select : 1
+CFG bus width auto detection result : 0
+CFG bus width auto detection result : 0
+Reserved : 0
+BPI address wrap around error : 0
+IPROG pulsed : 0
+read back crc error : 0
+Indicates that efuse logic is busy : 0
+ Match_cycle = 2.
+'5': Programmed successfully.
+Elapsed time = 11 sec.
+----------------------------------------------------------------------
+----------------------------------------------------------------------
+----------------------------------------------------------------------
+----------------------------------------------------------------------
+----------------------------------------------------------------------
+----------------------------------------------------------------------
+----------------------------------------------------------------------
+----------------------------------------------------------------------
+INFO:iMPACT:2219 - Status register values:
+INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000
+INFO:iMPACT:579 - '5': Completed downloading bit file to device.
+INFO:iMPACT - '5': Programing completed successfully.
+INFO:iMPACT - '5': Checking done pin....done.
+
+
+
+Done! +
+At Local date and time: Sat Jul 04 20:43:42 2009 + make -f system.make program started... +
+powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \
+ -mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \
+-D GCC_PPC440 -mregnames
+powerpc-eabi-size RTOSDemo/executable.elf
+ text data bss dec hex filename
+ 53174 372 86528 140074 2232a RTOSDemo/executable.elf
+
+
+Done! +
+start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/; exit;" +
+Writing filter settings.... +
+Done writing filter settings to: + C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters +
+Done writing Tab View settings to: + C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.gui +
+Xilinx Platform Studio (XPS)
+Xilinx EDK 11.2 Build EDK_LS3.47 +
+Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. +
+WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 237 - deprecated core for architecture 'virtex5fx'! +
+WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 282 - deprecated core for architecture 'virtex5fx'! +
+Generating Block Diagram to Buffer +
+Generated Block Diagram SVG +
+At Local date and time: Sun Jul 05 09:35:22 2009 + make -f system.make hwclean started... +
+rm -f implementation/system.ngc
+rm -f platgen.log
+rm -f __xps/ise/_xmsgs/platgen.xmsgs
+rm -f implementation/system.bmm
+rm -f implementation/system.bit
+rm -f implementation/system.ncd
+rm -f implementation/system_bd.bmm
+rm -f implementation/system_map.ncd
+rm -f __xps/system_routed
+rm -rf implementation synthesis xst hdl
+rm -rf xst.srp system.srp
+rm -f __xps/ise/_xmsgs/bitinit.xmsgs
+
+
+Done! +
+At Local date and time: Sun Jul 05 09:35:36 2009 + make -f system.make swclean started... +
+rm -rf ppc440_0/
+rm -f libgen.log
+rm -f __xps/ise/_xmsgs/libgen.xmsgs
+rm -f RTOSDemo/executable.elf
+
+
+Done! +
+Writing filter settings.... +
+Done writing filter settings to: + C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters +
+Done writing Tab View settings to: + C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.gui +
diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/system.make b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/system.make new file mode 100644 index 000000000..5cb4f0093 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/system.make @@ -0,0 +1,278 @@ +#################################################################
+# Makefile generated by Xilinx Platform Studio
+# Project:C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.xmp
+#
+# WARNING : This file will be re-generated every time a command
+# to run a make target is invoked. So, any changes made to this
+# file manually, will be lost when make is invoked next.
+#################################################################
+
+# Name of the Microprocessor system
+# The hardware specification of the system is in file :
+# C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs
+# The software specification of the system is in file :
+# C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mss
+
+include system_incl.make
+
+#################################################################
+# PHONY TARGETS
+#################################################################
+.PHONY: dummy
+.PHONY: netlistclean
+.PHONY: bitsclean
+.PHONY: simclean
+.PHONY: exporttosdk
+
+#################################################################
+# EXTERNAL TARGETS
+#################################################################
+all:
+ @echo "Makefile to build a Microprocessor system :"
+ @echo "Run make with any of the following targets"
+ @echo " "
+ @echo " netlist : Generates the netlist for the given MHS "
+ @echo " bits : Runs Implementation tools to generate the bitstream"
+ @echo " exporttosdk: Export files to SDK"
+ @echo " "
+ @echo " libs : Configures the sw libraries for this system"
+ @echo " program : Compiles the program sources for all the processor instances"
+ @echo " "
+ @echo " init_bram: Initializes bitstream with BRAM data"
+ @echo " ace : Generate ace file from bitstream and elf"
+ @echo " download : Downloads the bitstream onto the board"
+ @echo " "
+ @echo " sim : Generates HDL simulation models and runs simulator for chosen simulation mode"
+ @echo " simmodel : Generates HDL simulation models for chosen simulation mode"
+ @echo " behavioral_model : Generates behavioral HDL models with BRAM initialization"
+ @echo " structural_model : Generates structural simulation HDL models with BRAM initialization"
+ @echo " timing : Generates timing simulation HDL models with BRAM initialization"
+ @echo " "
+ @echo " netlistclean: Deletes netlist"
+ @echo " bitsclean: Deletes bit, ncd, bmm files"
+ @echo " hwclean : Deletes implementation dir"
+ @echo " libsclean: Deletes sw libraries"
+ @echo " programclean: Deletes compiled ELF files"
+ @echo " swclean : Deletes sw libraries and ELF files"
+ @echo " simclean : Deletes simulation dir"
+ @echo " clean : Deletes all generated files/directories"
+ @echo " "
+ @echo " make <target> : (Default)"
+ @echo " Creates a Microprocessor system using default initializations"
+ @echo " specified for each processor in MSS file"
+
+
+bits: $(SYSTEM_BIT)
+
+ace: $(SYSTEM_ACE)
+
+exporttosdk: $(SYSTEM_HW_HANDOFF_DEP)
+
+netlist: $(POSTSYN_NETLIST)
+
+libs: $(LIBRARIES)
+
+program: $(ALL_USER_ELF_FILES)
+
+download: $(DOWNLOAD_BIT) dummy
+ @echo "*********************************************"
+ @echo "Downloading Bitstream onto the target board"
+ @echo "*********************************************"
+ impact -batch etc/download.cmd
+
+init_bram: $(DOWNLOAD_BIT)
+
+sim: $(DEFAULT_SIM_SCRIPT)
+ cd simulation/behavioral; \
+ $(SIM_CMD) &
+
+simmodel: $(DEFAULT_SIM_SCRIPT)
+
+behavioral_model: $(BEHAVIORAL_SIM_SCRIPT)
+
+structural_model: $(STRUCTURAL_SIM_SCRIPT)
+
+clean: hwclean libsclean programclean simclean
+ rm -f _impact.cmd
+
+hwclean: netlistclean bitsclean
+ rm -rf implementation synthesis xst hdl
+ rm -rf xst.srp $(SYSTEM).srp
+ rm -f __xps/ise/_xmsgs/bitinit.xmsgs
+
+netlistclean:
+ rm -f $(POSTSYN_NETLIST)
+ rm -f platgen.log
+ rm -f __xps/ise/_xmsgs/platgen.xmsgs
+ rm -f $(BMM_FILE)
+
+bitsclean:
+ rm -f $(SYSTEM_BIT)
+ rm -f implementation/$(SYSTEM).ncd
+ rm -f implementation/$(SYSTEM)_bd.bmm
+ rm -f implementation/$(SYSTEM)_map.ncd
+ rm -f __xps/$(SYSTEM)_routed
+
+simclean:
+ rm -rf simulation/behavioral
+ rm -f simgen.log
+ rm -f __xps/ise/_xmsgs/simgen.xmsgs
+
+swclean: libsclean programclean
+ @echo ""
+
+libsclean: $(LIBSCLEAN_TARGETS)
+ rm -f libgen.log
+ rm -f __xps/ise/_xmsgs/libgen.xmsgs
+
+programclean: $(PROGRAMCLEAN_TARGETS)
+
+#################################################################
+# SOFTWARE PLATFORM FLOW
+#################################################################
+
+
+$(LIBRARIES): $(MHSFILE) $(MSSFILE) __xps/libgen.opt
+ @echo "*********************************************"
+ @echo "Creating software libraries..."
+ @echo "*********************************************"
+ libgen $(LIBGEN_OPTIONS) $(MSSFILE)
+
+
+ppc440_0_libsclean:
+ rm -rf ppc440_0/
+
+#################################################################
+# SOFTWARE APPLICATION RTOSDEMO
+#################################################################
+
+RTOSDemo_program: $(RTOSDEMO_OUTPUT)
+
+$(RTOSDEMO_OUTPUT) : $(RTOSDEMO_SOURCES) $(RTOSDEMO_HEADERS) $(RTOSDEMO_LINKER_SCRIPT) \
+ $(LIBRARIES) __xps/rtosdemo_compiler.opt
+ @mkdir -p $(RTOSDEMO_OUTPUT_DIR)
+ $(RTOSDEMO_CC) $(RTOSDEMO_CC_OPT) $(RTOSDEMO_SOURCES) -o $(RTOSDEMO_OUTPUT) \
+ $(RTOSDEMO_OTHER_CC_FLAGS) $(RTOSDEMO_INCLUDES) $(RTOSDEMO_LIBPATH) \
+ $(RTOSDEMO_CFLAGS) $(RTOSDEMO_LFLAGS)
+ $(RTOSDEMO_CC_SIZE) $(RTOSDEMO_OUTPUT)
+ @echo ""
+
+RTOSDemo_programclean:
+ rm -f $(RTOSDEMO_OUTPUT)
+
+#################################################################
+# BOOTLOOP ELF FILES
+#################################################################
+
+
+
+$(PPC440_0_BOOTLOOP): $(PPC440_BOOTLOOP)
+ @mkdir -p $(BOOTLOOP_DIR)
+ cp -f $(PPC440_BOOTLOOP) $(PPC440_0_BOOTLOOP)
+
+#################################################################
+# HARDWARE IMPLEMENTATION FLOW
+#################################################################
+
+
+$(BMM_FILE) \
+$(WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \
+ $(CORE_STATE_DEVELOPMENT_FILES)
+ @echo "****************************************************"
+ @echo "Creating system netlist for hardware specification.."
+ @echo "****************************************************"
+ platgen $(PLATGEN_OPTIONS) $(MHSFILE)
+
+$(POSTSYN_NETLIST): $(WRAPPER_NGC_FILES)
+ @echo "Running synthesis..."
+ bash -c "cd synthesis; ./synthesis.sh"
+
+__xps/$(SYSTEM)_routed: $(FPGA_IMP_DEPENDENCY)
+ @echo "*********************************************"
+ @echo "Running Xilinx Implementation tools.."
+ @echo "*********************************************"
+ @cp -f $(UCF_FILE) implementation/$(SYSTEM).ucf
+ @cp -f etc/fast_runtime.opt implementation/xflow.opt
+ xflow -wd implementation -p $(DEVICE) -implement xflow.opt -ise ../__xps/ise/$(SYSTEM).ise $(SYSTEM).ngc
+ touch __xps/$(SYSTEM)_routed
+
+$(SYSTEM_BIT): __xps/$(SYSTEM)_routed $(BITGEN_UT_FILE)
+ xilperl $(NON_CYG_XILINX_EDK_DIR)/data/fpga_impl/observe_par.pl $(OBSERVE_PAR_OPTIONS) implementation/$(SYSTEM).par
+ @echo "*********************************************"
+ @echo "Running Bitgen.."
+ @echo "*********************************************"
+ @cp -f $(BITGEN_UT_FILE) implementation/bitgen.ut
+ cd implementation; bitgen -w -f bitgen.ut $(SYSTEM); cd ..
+
+$(DOWNLOAD_BIT): $(SYSTEM_BIT) $(BRAMINIT_ELF_FILES) __xps/bitinit.opt
+ @cp -f implementation/$(SYSTEM)_bd.bmm .
+ @echo "*********************************************"
+ @echo "Initializing BRAM contents of the bitstream"
+ @echo "*********************************************"
+ bitinit -p $(DEVICE) $(MHSFILE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) \
+ -bt $(SYSTEM_BIT) -o $(DOWNLOAD_BIT)
+ @rm -f $(SYSTEM)_bd.bmm
+
+$(SYSTEM_ACE): $(DOWNLOAD_BIT) $(RTOSDEMO_OUTPUT)
+ @echo "*********************************************"
+ @echo "Creating system ace file"
+ @echo "*********************************************"
+ xmd -tcl genace.tcl -jprog -hw $(DOWNLOAD_BIT) -elf $(RTOSDEMO_OUTPUT) -target ppc_hw -ace $(SYSTEM_ACE)
+
+#################################################################
+# EXPORT_TO_SDK FLOW
+#################################################################
+
+
+$(SYSTEM_HW_HANDOFF): $(MHSFILE) __xps/platgen.opt
+ mkdir -p $(SDK_EXPORT_DIR)
+ psf2Edward.exe -inp $(SYSTEM).xmp -xml $(SDK_EXPORT_DIR)/$(SYSTEM).xml $(SEARCHPATHOPT)
+ xdsgen.exe -inp $(SYSTEM).xmp -report $(SDK_EXPORT_DIR)/$(SYSTEM).html $(SEARCHPATHOPT) -make_docs_local
+
+$(SYSTEM_HW_HANDOFF_BIT): $(SYSTEM_BIT)
+ @rm -rf $(SYSTEM_HW_HANDOFF_BIT)
+ @cp -f $(SYSTEM_BIT) $(SDK_EXPORT_DIR)/
+
+$(SYSTEM_HW_HANDOFF_BMM): implementation/$(SYSTEM)_bd.bmm
+ @rm -rf $(SYSTEM_HW_HANDOFF_BMM)
+ @cp -f implementation/$(SYSTEM)_bd.bmm $(SDK_EXPORT_DIR)/
+
+#################################################################
+# SIMULATION FLOW
+#################################################################
+
+
+################## BEHAVIORAL SIMULATION ##################
+
+$(BEHAVIORAL_SIM_SCRIPT): $(MHSFILE) __xps/simgen.opt \
+ $(WRAPPER_NGC_FILES) \
+ $(BRAMINIT_ELF_FILES)
+ @echo "*********************************************"
+ @echo "Creating behavioral simulation models..."
+ @echo "*********************************************"
+ simgen $(SIMGEN_OPTIONS) -m behavioral $(MHSFILE)
+
+################## STRUCTURAL SIMULATION ##################
+
+$(STRUCTURAL_SIM_SCRIPT): $(WRAPPER_NGC_FILES) __xps/simgen.opt \
+ $(BRAMINIT_ELF_FILES)
+ @echo "*********************************************"
+ @echo "Creating structural simulation models..."
+ @echo "*********************************************"
+ simgen $(SIMGEN_OPTIONS) -sd implementation -m structural $(MHSFILE)
+
+
+################## TIMING SIMULATION ##################
+
+implementation/$(SYSTEM).ncd: __xps/$(SYSTEM)_routed
+
+$(TIMING_SIM_SCRIPT): implementation/$(SYSTEM).ncd __xps/simgen.opt \
+ $(BRAMINIT_ELF_FILES)
+ @echo "*********************************************"
+ @echo "Creating timing simulation models..."
+ @echo "*********************************************"
+ simgen $(SIMGEN_OPTIONS) -sd implementation -m timing $(MHSFILE)
+
+dummy:
+ @echo ""
+
diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/system.mhs b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/system.mhs new file mode 100644 index 000000000..3581b1400 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/system.mhs @@ -0,0 +1,458 @@ +
+# ##############################################################################
+# Created by Base System Builder Wizard for Xilinx EDK 11.1 Build EDK_L.29.1
+# Thu Jun 11 19:28:07 2009
+# Target Board: Xilinx Virtex 5 ML507 Evaluation Platform Rev A
+# Family: virtex5
+# Device: xc5vfx70t
+# Package: ff1136
+# Speed Grade: -1
+# Processor number: 1
+# Processor 1: ppc440_0
+# Processor clock frequency: 125.0
+# Bus clock frequency: 125.0
+# Debug Interface: FPGA JTAG
+# ##############################################################################
+ PARAMETER VERSION = 2.1.0
+
+
+ PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX_pin, DIR = I
+ PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX_pin, DIR = O
+ PORT fpga_0_LEDs_8Bit_GPIO_IO_pin = fpga_0_LEDs_8Bit_GPIO_IO_pin, DIR = IO, VEC = [0:7]
+ PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO_pin, DIR = IO, VEC = [0:4]
+ PORT fpga_0_Push_Buttons_5Bit_GPIO_IO_pin = fpga_0_Push_Buttons_5Bit_GPIO_IO_pin, DIR = IO, VEC = [0:4]
+ PORT fpga_0_DIP_Switches_8Bit_GPIO_IO_pin = fpga_0_DIP_Switches_8Bit_GPIO_IO_pin, DIR = IO, VEC = [0:7]
+ PORT fpga_0_IIC_EEPROM_Sda_pin = fpga_0_IIC_EEPROM_Sda_pin, DIR = IO
+ PORT fpga_0_IIC_EEPROM_Scl_pin = fpga_0_IIC_EEPROM_Scl_pin, DIR = IO
+ PORT fpga_0_SRAM_Mem_A_pin = fpga_0_SRAM_Mem_A_pin_vslice_7_30_concat, DIR = O, VEC = [7:30]
+ PORT fpga_0_SRAM_Mem_CEN_pin = fpga_0_SRAM_Mem_CEN_pin, DIR = O
+ PORT fpga_0_SRAM_Mem_OEN_pin = fpga_0_SRAM_Mem_OEN_pin, DIR = O
+ PORT fpga_0_SRAM_Mem_WEN_pin = fpga_0_SRAM_Mem_WEN_pin, DIR = O
+ PORT fpga_0_SRAM_Mem_BEN_pin = fpga_0_SRAM_Mem_BEN_pin, DIR = O, VEC = [0:3]
+ PORT fpga_0_SRAM_Mem_ADV_LDN_pin = fpga_0_SRAM_Mem_ADV_LDN_pin, DIR = O
+ PORT fpga_0_SRAM_Mem_DQ_pin = fpga_0_SRAM_Mem_DQ_pin, DIR = IO, VEC = [0:31]
+ PORT fpga_0_SRAM_ZBT_CLK_OUT_pin = SRAM_CLK_OUT_s, DIR = O
+ PORT fpga_0_SRAM_ZBT_CLK_FB_pin = SRAM_CLK_FB_s, DIR = I, SIGIS = CLK, CLK_FREQ = 125000000
+ PORT fpga_0_PCIe_Bridge_RXN_pin = fpga_0_PCIe_Bridge_RXN_pin, DIR = I
+ PORT fpga_0_PCIe_Bridge_RXP_pin = fpga_0_PCIe_Bridge_RXP_pin, DIR = I
+ PORT fpga_0_PCIe_Bridge_TXN_pin = fpga_0_PCIe_Bridge_TXN_pin, DIR = O
+ PORT fpga_0_PCIe_Bridge_TXP_pin = fpga_0_PCIe_Bridge_TXP_pin, DIR = O
+ PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = fpga_0_Ethernet_MAC_PHY_tx_clk_pin, DIR = I
+ PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = fpga_0_Ethernet_MAC_PHY_rx_clk_pin, DIR = I
+ PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs_pin, DIR = I
+ PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv_pin, DIR = I
+ PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin = fpga_0_Ethernet_MAC_PHY_rx_data_pin, DIR = I, VEC = [3:0]
+ PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col_pin, DIR = I
+ PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er_pin, DIR = I
+ PORT fpga_0_Ethernet_MAC_PHY_rst_n_pin = fpga_0_Ethernet_MAC_PHY_rst_n_pin, DIR = O
+ PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en_pin, DIR = O
+ PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin = fpga_0_Ethernet_MAC_PHY_tx_data_pin, DIR = O, VEC = [3:0]
+ PORT fpga_0_Ethernet_MAC_MDINT_pin = fpga_0_Ethernet_MAC_MDINT_pin, DIR = I, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_LOW, INTERRUPT_PRIORITY = MEDIUM
+ PORT fpga_0_DDR2_SDRAM_DDR2_DQ_pin = fpga_0_DDR2_SDRAM_DDR2_DQ_pin, DIR = IO, VEC = [63:0]
+ PORT fpga_0_DDR2_SDRAM_DDR2_DQS_pin = fpga_0_DDR2_SDRAM_DDR2_DQS_pin, DIR = IO, VEC = [7:0]
+ PORT fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin = fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin, DIR = IO, VEC = [7:0]
+ PORT fpga_0_DDR2_SDRAM_DDR2_A_pin = fpga_0_DDR2_SDRAM_DDR2_A_pin, DIR = O, VEC = [12:0]
+ PORT fpga_0_DDR2_SDRAM_DDR2_BA_pin = fpga_0_DDR2_SDRAM_DDR2_BA_pin, DIR = O, VEC = [1:0]
+ PORT fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin = fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin, DIR = O
+ PORT fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin = fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin, DIR = O
+ PORT fpga_0_DDR2_SDRAM_DDR2_WE_N_pin = fpga_0_DDR2_SDRAM_DDR2_WE_N_pin, DIR = O
+ PORT fpga_0_DDR2_SDRAM_DDR2_CS_N_pin = fpga_0_DDR2_SDRAM_DDR2_CS_N_pin, DIR = O
+ PORT fpga_0_DDR2_SDRAM_DDR2_ODT_pin = fpga_0_DDR2_SDRAM_DDR2_ODT_pin, DIR = O, VEC = [1:0]
+ PORT fpga_0_DDR2_SDRAM_DDR2_CKE_pin = fpga_0_DDR2_SDRAM_DDR2_CKE_pin, DIR = O
+ PORT fpga_0_DDR2_SDRAM_DDR2_DM_pin = fpga_0_DDR2_SDRAM_DDR2_DM_pin, DIR = O, VEC = [7:0]
+ PORT fpga_0_DDR2_SDRAM_DDR2_CK_pin = fpga_0_DDR2_SDRAM_DDR2_CK_pin, DIR = O, VEC = [1:0]
+ PORT fpga_0_DDR2_SDRAM_DDR2_CK_N_pin = fpga_0_DDR2_SDRAM_DDR2_CK_N_pin, DIR = O, VEC = [1:0]
+ PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA_pin, DIR = O, VEC = [6:0]
+ PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK_pin, DIR = I
+ PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin, DIR = I
+ PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN_pin, DIR = O
+ PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN_pin, DIR = O
+ PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN_pin, DIR = O
+ PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD_pin, DIR = IO, VEC = [15:0]
+ PORT fpga_0_clk_1_sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
+ PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 0
+ PORT fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin = PCIe_Diff_Clk, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK
+ PORT fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin = PCIe_Diff_Clk, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK
+
+
+BEGIN ppc440_virtex5
+ PARAMETER INSTANCE = ppc440_0
+ PARAMETER C_IDCR_BASEADDR = 0b0000000000
+ PARAMETER C_IDCR_HIGHADDR = 0b0011111111
+ PARAMETER C_PPC440MC_ROW_CONFLICT_MASK = 0x003FFE00
+ PARAMETER C_PPC440MC_BANK_CONFLICT_MASK = 0x00C00000
+ PARAMETER C_PPC440MC_CONTROL = 0xF810008F
+ PARAMETER C_SPLB0_USE_MPLB_ADDR = 1
+ PARAMETER C_SPLB0_NUM_MPLB_ADDR_RNG = 1
+ PARAMETER C_SPLB1_NUM_MPLB_ADDR_RNG = 0
+ PARAMETER HW_VER = 1.01.a
+ PARAMETER C_SPLB0_RNG0_MPLB_BASEADDR = 0x80000000
+ PARAMETER C_SPLB0_RNG0_MPLB_HIGHADDR = 0xffffffff
+ PARAMETER C_SPLB0_RNG_MC_BASEADDR = 0x00000000
+ PARAMETER C_SPLB0_RNG_MC_HIGHADDR = 0x0fffffff
+ BUS_INTERFACE MPLB = plb_v46_0
+ BUS_INTERFACE SPLB0 = ppc440_0_SPLB0
+ BUS_INTERFACE PPC440MC = ppc440_0_PPC440MC
+ BUS_INTERFACE JTAGPPC = ppc440_0_jtagppc_bus
+ BUS_INTERFACE RESETPPC = ppc_reset_bus
+ PORT CPMC440CLK = clk_125_0000MHzPLL0
+ PORT CPMINTERCONNECTCLK = clk_125_0000MHzPLL0
+ PORT CPMINTERCONNECTCLKNTO1 = net_vcc
+ PORT EICC440EXTIRQ = ppc440_0_EICC440EXTIRQ
+ PORT CPMMCCLK = clk_125_0000MHzPLL0_ADJUST
+ PORT CPMPPCMPLBCLK = clk_125_0000MHzPLL0_ADJUST
+ PORT CPMPPCS0PLBCLK = clk_125_0000MHzPLL0_ADJUST
+END
+
+BEGIN plb_v46
+ PARAMETER INSTANCE = plb_v46_0
+ PARAMETER C_DCR_INTFCE = 0
+ PARAMETER C_FAMILY = virtex5
+ PARAMETER HW_VER = 1.04.a
+ PORT PLB_Clk = clk_125_0000MHzPLL0_ADJUST
+ PORT SYS_Rst = sys_bus_reset
+END
+
+BEGIN xps_bram_if_cntlr
+ PARAMETER INSTANCE = xps_bram_if_cntlr_1
+ PARAMETER C_SPLB_NATIVE_DWIDTH = 64
+ PARAMETER C_SPLB_SUPPORT_BURSTS = 1
+ PARAMETER C_SPLB_P2P = 0
+ PARAMETER C_FAMILY = virtex5
+ PARAMETER HW_VER = 1.00.b
+ PARAMETER C_BASEADDR = 0xffffe000
+ PARAMETER C_HIGHADDR = 0xffffffff
+ BUS_INTERFACE SPLB = plb_v46_0
+ BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
+END
+
+BEGIN bram_block
+ PARAMETER INSTANCE = xps_bram_if_cntlr_1_bram
+ PARAMETER C_FAMILY = virtex5
+ PARAMETER HW_VER = 1.00.a
+ BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
+END
+
+BEGIN xps_uartlite
+ PARAMETER INSTANCE = RS232_Uart_1
+ PARAMETER C_FAMILY = virtex5
+ PARAMETER C_BAUDRATE = 9600
+ PARAMETER C_DATA_BITS = 8
+ PARAMETER C_USE_PARITY = 0
+ PARAMETER C_ODD_PARITY = 0
+ PARAMETER HW_VER = 1.01.a
+ PARAMETER C_BASEADDR = 0x84000000
+ PARAMETER C_HIGHADDR = 0x8400ffff
+ BUS_INTERFACE SPLB = plb_v46_0
+ PORT RX = fpga_0_RS232_Uart_1_RX_pin
+ PORT TX = fpga_0_RS232_Uart_1_TX_pin
+ PORT Interrupt = RS232_Uart_1_Interrupt
+END
+
+BEGIN xps_gpio
+ PARAMETER INSTANCE = LEDs_8Bit
+ PARAMETER C_FAMILY = virtex5
+ PARAMETER C_ALL_INPUTS = 0
+ PARAMETER C_GPIO_WIDTH = 8
+ PARAMETER C_INTERRUPT_PRESENT = 0
+ PARAMETER C_IS_DUAL = 0
+ PARAMETER HW_VER = 2.00.a
+ PARAMETER C_BASEADDR = 0x81440000
+ PARAMETER C_HIGHADDR = 0x8144ffff
+ BUS_INTERFACE SPLB = plb_v46_0
+ PORT GPIO_IO = fpga_0_LEDs_8Bit_GPIO_IO_pin
+END
+
+BEGIN xps_gpio
+ PARAMETER INSTANCE = LEDs_Positions
+ PARAMETER C_FAMILY = virtex5
+ PARAMETER C_ALL_INPUTS = 0
+ PARAMETER C_GPIO_WIDTH = 5
+ PARAMETER C_INTERRUPT_PRESENT = 0
+ PARAMETER C_IS_DUAL = 0
+ PARAMETER HW_VER = 2.00.a
+ PARAMETER C_BASEADDR = 0x81420000
+ PARAMETER C_HIGHADDR = 0x8142ffff
+ BUS_INTERFACE SPLB = plb_v46_0
+ PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO_pin
+END
+
+BEGIN xps_gpio
+ PARAMETER INSTANCE = Push_Buttons_5Bit
+ PARAMETER C_FAMILY = virtex5
+ PARAMETER C_ALL_INPUTS = 1
+ PARAMETER C_GPIO_WIDTH = 5
+ PARAMETER C_INTERRUPT_PRESENT = 0
+ PARAMETER C_IS_DUAL = 0
+ PARAMETER HW_VER = 2.00.a
+ PARAMETER C_BASEADDR = 0x81400000
+ PARAMETER C_HIGHADDR = 0x8140ffff
+ BUS_INTERFACE SPLB = plb_v46_0
+ PORT GPIO_IO = fpga_0_Push_Buttons_5Bit_GPIO_IO_pin
+END
+
+BEGIN xps_gpio
+ PARAMETER INSTANCE = DIP_Switches_8Bit
+ PARAMETER C_FAMILY = virtex5
+ PARAMETER C_ALL_INPUTS = 1
+ PARAMETER C_GPIO_WIDTH = 8
+ PARAMETER C_INTERRUPT_PRESENT = 0
+ PARAMETER C_IS_DUAL = 0
+ PARAMETER HW_VER = 2.00.a
+ PARAMETER C_BASEADDR = 0x81460000
+ PARAMETER C_HIGHADDR = 0x8146ffff
+ BUS_INTERFACE SPLB = plb_v46_0
+ PORT GPIO_IO = fpga_0_DIP_Switches_8Bit_GPIO_IO_pin
+END
+
+BEGIN xps_iic
+ PARAMETER INSTANCE = IIC_EEPROM
+ PARAMETER C_IIC_FREQ = 100000
+ PARAMETER C_TEN_BIT_ADR = 0
+ PARAMETER C_FAMILY = virtex5
+ PARAMETER HW_VER = 2.01.a
+ PARAMETER C_BASEADDR = 0x81600000
+ PARAMETER C_HIGHADDR = 0x8160ffff
+ BUS_INTERFACE SPLB = plb_v46_0
+ PORT Sda = fpga_0_IIC_EEPROM_Sda_pin
+ PORT Scl = fpga_0_IIC_EEPROM_Scl_pin
+END
+
+BEGIN xps_mch_emc
+ PARAMETER INSTANCE = SRAM
+ PARAMETER C_FAMILY = virtex5
+ PARAMETER C_NUM_BANKS_MEM = 1
+ PARAMETER C_NUM_CHANNELS = 0
+ PARAMETER C_MEM0_WIDTH = 32
+ PARAMETER C_MAX_MEM_WIDTH = 32
+ PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 0
+ PARAMETER C_SYNCH_MEM_0 = 1
+ PARAMETER C_TCEDV_PS_MEM_0 = 0
+ PARAMETER C_TAVDV_PS_MEM_0 = 0
+ PARAMETER C_THZCE_PS_MEM_0 = 0
+ PARAMETER C_THZOE_PS_MEM_0 = 0
+ PARAMETER C_TWC_PS_MEM_0 = 0
+ PARAMETER C_TWP_PS_MEM_0 = 0
+ PARAMETER C_TLZWE_PS_MEM_0 = 0
+ PARAMETER HW_VER = 3.00.a
+ PARAMETER C_MEM0_BASEADDR = 0xf8000000
+ PARAMETER C_MEM0_HIGHADDR = 0xf80fffff
+ BUS_INTERFACE SPLB = plb_v46_0
+ PORT RdClk = clk_125_0000MHzPLL0_ADJUST
+ PORT Mem_A = 0b0000000 & fpga_0_SRAM_Mem_A_pin_vslice_7_30_concat & 0b0
+ PORT Mem_CEN = fpga_0_SRAM_Mem_CEN_pin
+ PORT Mem_OEN = fpga_0_SRAM_Mem_OEN_pin
+ PORT Mem_WEN = fpga_0_SRAM_Mem_WEN_pin
+ PORT Mem_BEN = fpga_0_SRAM_Mem_BEN_pin
+ PORT Mem_ADV_LDN = fpga_0_SRAM_Mem_ADV_LDN_pin
+ PORT Mem_DQ = fpga_0_SRAM_Mem_DQ_pin
+END
+
+BEGIN plbv46_pcie
+ PARAMETER INSTANCE = PCIe_Bridge
+ PARAMETER C_FAMILY = virtex5
+ PARAMETER C_IPIFBAR_NUM = 2
+ PARAMETER C_PCIBAR_NUM = 1
+ PARAMETER C_DEVICE_ID = 0x0505
+ PARAMETER C_VENDOR_ID = 0x10EE
+ PARAMETER C_CLASS_CODE = 0x058000
+ PARAMETER C_REV_ID = 0x00
+ PARAMETER C_SUBSYSTEM_ID = 0x0000
+ PARAMETER C_SUBSYSTEM_VENDOR_ID = 0x0000
+ PARAMETER C_COMP_TIMEOUT = 1
+ PARAMETER C_IPIFBAR2PCIBAR_0 = 0x00000000
+ PARAMETER C_IPIFBAR2PCIBAR_1 = 0x00000000
+ PARAMETER C_PCIBAR2IPIFBAR_0 = 0xf8000000
+ PARAMETER C_PCIBAR2IPIFBAR_1 = 0x00000000
+ PARAMETER C_PCIBAR_LEN_0 = 20
+ PARAMETER C_PCIBAR_LEN_1 = 28
+ PARAMETER C_BOARD = ml507
+ PARAMETER HW_VER = 3.00.b
+ PARAMETER C_BASEADDR = 0x85c00000
+ PARAMETER C_HIGHADDR = 0x85c0ffff
+ PARAMETER C_IPIFBAR_0 = 0xc0000000
+ PARAMETER C_IPIFBAR_HIGHADDR_0 = 0xdfffffff
+ PARAMETER C_IPIFBAR_1 = 0xe0000000
+ PARAMETER C_IPIFBAR_HIGHADDR_1 = 0xefffffff
+ BUS_INTERFACE SPLB = plb_v46_0
+ BUS_INTERFACE MPLB = ppc440_0_SPLB0
+ PORT PERSTN = net_vcc
+ PORT REFCLK = PCIe_Diff_Clk
+ PORT RXN = fpga_0_PCIe_Bridge_RXN_pin
+ PORT RXP = fpga_0_PCIe_Bridge_RXP_pin
+ PORT TXN = fpga_0_PCIe_Bridge_TXN_pin
+ PORT TXP = fpga_0_PCIe_Bridge_TXP_pin
+ PORT MSI_request = net_gnd
+END
+
+BEGIN plb_v46
+ PARAMETER INSTANCE = ppc440_0_SPLB0
+ PARAMETER C_FAMILY = virtex5
+ PARAMETER HW_VER = 1.04.a
+ PORT PLB_Clk = clk_125_0000MHzPLL0_ADJUST
+ PORT SYS_Rst = sys_bus_reset
+END
+
+BEGIN xps_ethernetlite
+ PARAMETER INSTANCE = Ethernet_MAC
+ PARAMETER C_FAMILY = virtex5
+ PARAMETER HW_VER = 2.01.a
+ PARAMETER C_BASEADDR = 0x81000000
+ PARAMETER C_HIGHADDR = 0x8100ffff
+ BUS_INTERFACE SPLB = plb_v46_0
+ PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk_pin
+ PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk_pin
+ PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs_pin
+ PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv_pin
+ PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data_pin
+ PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col_pin
+ PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er_pin
+ PORT PHY_rst_n = fpga_0_Ethernet_MAC_PHY_rst_n_pin
+ PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en_pin
+ PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data_pin
+END
+
+BEGIN ppc440mc_ddr2
+ PARAMETER INSTANCE = DDR2_SDRAM
+ PARAMETER C_DDR_BAWIDTH = 2
+ PARAMETER C_NUM_CLK_PAIRS = 2
+ PARAMETER C_DDR_DWIDTH = 64
+ PARAMETER C_DDR_CAWIDTH = 10
+ PARAMETER C_NUM_RANKS_MEM = 1
+ PARAMETER C_CS_BITS = 0
+ PARAMETER C_DDR_DM_WIDTH = 8
+ PARAMETER C_DQ_BITS = 8
+ PARAMETER C_DDR2_ODT_WIDTH = 2
+ PARAMETER C_DDR2_ADDT_LAT = 0
+ PARAMETER C_INCLUDE_ECC_SUPPORT = 0
+ PARAMETER C_DDR2_ODT_SETTING = 1
+ PARAMETER C_DQS_BITS = 3
+ PARAMETER C_DDR_DQS_WIDTH = 8
+ PARAMETER C_DDR_RAWIDTH = 13
+ PARAMETER C_DDR_BURST_LENGTH = 4
+ PARAMETER C_DDR_CAS_LAT = 4
+ PARAMETER C_REG_DIMM = 0
+ PARAMETER C_MIB_MC_CLOCK_RATIO = 1
+ PARAMETER C_DDR_TREFI = 3900
+ PARAMETER C_DDR_TRAS = 40000
+ PARAMETER C_DDR_TRCD = 15000
+ PARAMETER C_DDR_TRFC = 75000
+ PARAMETER C_DDR_TRP = 15000
+ PARAMETER C_DDR_TRTP = 7500
+ PARAMETER C_DDR_TWR = 15000
+ PARAMETER C_DDR_TWTR = 7500
+ PARAMETER C_MC_MIBCLK_PERIOD_PS = 8000
+ PARAMETER C_IDEL_HIGH_PERF = TRUE
+ PARAMETER C_NUM_IDELAYCTRL = 3
+ PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y6-IDELAYCTRL_X0Y2-IDELAYCTRL_X0Y1
+ PARAMETER C_DQS_IO_COL = 0b000000000000000000
+ PARAMETER C_DQ_IO_MS = 0b000000000111010100111101000011110001111000101110110000111100000110111100
+ PARAMETER HW_VER = 2.00.b
+ PARAMETER C_MEM_BASEADDR = 0x00000000
+ PARAMETER C_MEM_HIGHADDR = 0x0fffffff
+ BUS_INTERFACE PPC440MC = ppc440_0_PPC440MC
+ PORT mc_mibclk = clk_125_0000MHzPLL0_ADJUST
+ PORT mi_mcclk90 = clk_125_0000MHz90PLL0_ADJUST
+ PORT mi_mcreset = sys_bus_reset
+ PORT mi_mcclkdiv2 = clk_62_5000MHzPLL0_ADJUST
+ PORT mi_mcclk_200 = clk_200_0000MHz
+ PORT DDR2_DQ = fpga_0_DDR2_SDRAM_DDR2_DQ_pin
+ PORT DDR2_DQS = fpga_0_DDR2_SDRAM_DDR2_DQS_pin
+ PORT DDR2_DQS_N = fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin
+ PORT DDR2_A = fpga_0_DDR2_SDRAM_DDR2_A_pin
+ PORT DDR2_BA = fpga_0_DDR2_SDRAM_DDR2_BA_pin
+ PORT DDR2_RAS_N = fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin
+ PORT DDR2_CAS_N = fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin
+ PORT DDR2_WE_N = fpga_0_DDR2_SDRAM_DDR2_WE_N_pin
+ PORT DDR2_CS_N = fpga_0_DDR2_SDRAM_DDR2_CS_N_pin
+ PORT DDR2_ODT = fpga_0_DDR2_SDRAM_DDR2_ODT_pin
+ PORT DDR2_CKE = fpga_0_DDR2_SDRAM_DDR2_CKE_pin
+ PORT DDR2_DM = fpga_0_DDR2_SDRAM_DDR2_DM_pin
+ PORT DDR2_CK = fpga_0_DDR2_SDRAM_DDR2_CK_pin
+ PORT DDR2_CK_N = fpga_0_DDR2_SDRAM_DDR2_CK_N_pin
+END
+
+BEGIN xps_sysace
+ PARAMETER INSTANCE = SysACE_CompactFlash
+ PARAMETER C_MEM_WIDTH = 16
+ PARAMETER C_FAMILY = virtex5
+ PARAMETER HW_VER = 1.01.a
+ PARAMETER C_BASEADDR = 0x83600000
+ PARAMETER C_HIGHADDR = 0x8360ffff
+ BUS_INTERFACE SPLB = plb_v46_0
+ PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA_pin
+ PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK_pin
+ PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin
+ PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN_pin
+ PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN_pin
+ PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN_pin
+ PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD_pin
+END
+
+BEGIN clock_generator
+ PARAMETER INSTANCE = clock_generator_0
+ PARAMETER C_CLKIN_FREQ = 100000000
+ PARAMETER C_CLKFBIN_FREQ = 125000000
+ PARAMETER C_CLKOUT0_FREQ = 125000000
+ PARAMETER C_CLKOUT0_PHASE = 90
+ PARAMETER C_CLKOUT0_GROUP = PLL0_ADJUST
+ PARAMETER C_CLKOUT0_BUF = TRUE
+ PARAMETER C_CLKOUT1_FREQ = 125000000
+ PARAMETER C_CLKOUT1_PHASE = 0
+ PARAMETER C_CLKOUT1_GROUP = PLL0
+ PARAMETER C_CLKOUT1_BUF = TRUE
+ PARAMETER C_CLKOUT2_FREQ = 125000000
+ PARAMETER C_CLKOUT2_PHASE = 0
+ PARAMETER C_CLKOUT2_GROUP = PLL0_ADJUST
+ PARAMETER C_CLKOUT2_BUF = TRUE
+ PARAMETER C_CLKOUT3_FREQ = 200000000
+ PARAMETER C_CLKOUT3_PHASE = 0
+ PARAMETER C_CLKOUT3_GROUP = NONE
+ PARAMETER C_CLKOUT3_BUF = TRUE
+ PARAMETER C_CLKOUT4_FREQ = 62500000
+ PARAMETER C_CLKOUT4_PHASE = 0
+ PARAMETER C_CLKOUT4_GROUP = PLL0_ADJUST
+ PARAMETER C_CLKOUT4_BUF = TRUE
+ PARAMETER C_CLKFBOUT_FREQ = 125000000
+ PARAMETER C_CLKFBOUT_BUF = TRUE
+ PARAMETER HW_VER = 3.01.a
+ PORT CLKIN = dcm_clk_s
+ PORT CLKFBIN = SRAM_CLK_FB_s
+ PORT CLKOUT0 = clk_125_0000MHz90PLL0_ADJUST
+ PORT CLKOUT1 = clk_125_0000MHzPLL0
+ PORT CLKOUT2 = clk_125_0000MHzPLL0_ADJUST
+ PORT CLKOUT3 = clk_200_0000MHz
+ PORT CLKOUT4 = clk_62_5000MHzPLL0_ADJUST
+ PORT CLKFBOUT = SRAM_CLK_OUT_s
+ PORT RST = net_gnd
+ PORT LOCKED = Dcm_all_locked
+END
+
+BEGIN jtagppc_cntlr
+ PARAMETER INSTANCE = jtagppc_cntlr_inst
+ PARAMETER HW_VER = 2.01.c
+ BUS_INTERFACE JTAGPPC0 = ppc440_0_jtagppc_bus
+END
+
+BEGIN proc_sys_reset
+ PARAMETER INSTANCE = proc_sys_reset_0
+ PARAMETER C_EXT_RESET_HIGH = 0
+ PARAMETER HW_VER = 2.00.a
+ BUS_INTERFACE RESETPPC0 = ppc_reset_bus
+ PORT Slowest_sync_clk = clk_125_0000MHzPLL0_ADJUST
+ PORT Ext_Reset_In = sys_rst_s
+ PORT Dcm_locked = Dcm_all_locked
+ PORT Bus_Struct_Reset = sys_bus_reset
+ PORT Peripheral_Reset = sys_periph_reset
+END
+
+BEGIN xps_intc
+ PARAMETER INSTANCE = xps_intc_0
+ PARAMETER HW_VER = 2.00.a
+ PARAMETER C_BASEADDR = 0x81800000
+ PARAMETER C_HIGHADDR = 0x8180ffff
+ BUS_INTERFACE SPLB = plb_v46_0
+ PORT Intr = fpga_0_Ethernet_MAC_MDINT_pin&RS232_Uart_1_Interrupt
+ PORT Irq = ppc440_0_EICC440EXTIRQ
+END
+
diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/system.mss b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/system.mss new file mode 100644 index 000000000..36bd0f5fe --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/system.mss @@ -0,0 +1,125 @@ +
+ PARAMETER VERSION = 2.2.0
+
+
+BEGIN OS
+ PARAMETER OS_NAME = standalone
+ PARAMETER OS_VER = 2.00.a
+ PARAMETER PROC_INSTANCE = ppc440_0
+ PARAMETER STDIN = RS232_Uart_1
+ PARAMETER STDOUT = RS232_Uart_1
+END
+
+
+BEGIN PROCESSOR
+ PARAMETER DRIVER_NAME = cpu_ppc440
+ PARAMETER DRIVER_VER = 1.01.a
+ PARAMETER HW_INSTANCE = ppc440_0
+ PARAMETER COMPILER = powerpc-eabi-gcc
+ PARAMETER ARCHIVER = powerpc-eabi-ar
+END
+
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = bram
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = xps_bram_if_cntlr_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = xps_bram_if_cntlr_1_bram
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = uartlite
+ PARAMETER DRIVER_VER = 1.14.a
+ PARAMETER HW_INSTANCE = RS232_Uart_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = gpio
+ PARAMETER DRIVER_VER = 2.13.a
+ PARAMETER HW_INSTANCE = LEDs_8Bit
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = gpio
+ PARAMETER DRIVER_VER = 2.13.a
+ PARAMETER HW_INSTANCE = LEDs_Positions
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = gpio
+ PARAMETER DRIVER_VER = 2.13.a
+ PARAMETER HW_INSTANCE = Push_Buttons_5Bit
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = gpio
+ PARAMETER DRIVER_VER = 2.13.a
+ PARAMETER HW_INSTANCE = DIP_Switches_8Bit
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = iic
+ PARAMETER DRIVER_VER = 1.15.a
+ PARAMETER HW_INSTANCE = IIC_EEPROM
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = emc
+ PARAMETER DRIVER_VER = 2.00.a
+ PARAMETER HW_INSTANCE = SRAM
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = pcie
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = PCIe_Bridge
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = emaclite
+ PARAMETER DRIVER_VER = 1.14.a
+ PARAMETER HW_INSTANCE = Ethernet_MAC
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = memcon
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = DDR2_SDRAM
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = sysace
+ PARAMETER DRIVER_VER = 1.12.a
+ PARAMETER HW_INSTANCE = SysACE_CompactFlash
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = clock_generator_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = jtagppc_cntlr_inst
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 1.00.a
+ PARAMETER HW_INSTANCE = proc_sys_reset_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = intc
+ PARAMETER DRIVER_VER = 1.11.a
+ PARAMETER HW_INSTANCE = xps_intc_0
+END
+
+
diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/system.xmp b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/system.xmp new file mode 100644 index 000000000..d44417a73 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/system.xmp @@ -0,0 +1,69 @@ +#Please do not modify this file by hand
+XmpVersion: 11.2
+VerMgmt: 11.2
+IntStyle: default
+MHS File: system.mhs
+MSS File: system.mss
+Architecture: virtex5
+Device: xc5vfx70t
+Package: ff1136
+SpeedGrade: -1
+UserCmd1:
+UserCmd1Type: 0
+UserCmd2:
+UserCmd2Type: 0
+GenSimTB: 0
+SdkExportBmmBit: 1
+SdkExportDir: SDK/SDK_Export
+InsertNoPads: 0
+WarnForEAArch: 1
+HdlLang: VHDL
+SimModel: BEHAVIORAL
+UcfFile: data/system.ucf
+EnableParTimingError: 1
+ShowLicenseDialog: 1
+Processor: ppc440_0
+BootLoop: 1
+XmdStub: 0
+SwProj: RTOSDemo
+Processor: ppc440_0
+Executable: RTOSDemo/executable.elf
+Source: RTOSDemo/../../Common/Minimal/BlockQ.c
+Source: RTOSDemo/../../Common/Minimal/blocktim.c
+Source: RTOSDemo/../../Common/Minimal/comtest.c
+Source: RTOSDemo/../../Common/Minimal/countsem.c
+Source: RTOSDemo/../../Common/Minimal/death.c
+Source: RTOSDemo/../../Common/Minimal/dynamic.c
+Source: RTOSDemo/../../Common/Minimal/flash.c
+Source: RTOSDemo/../../Common/Minimal/GenQTest.c
+Source: RTOSDemo/../../Common/Minimal/integer.c
+Source: RTOSDemo/../../Common/Minimal/QPeek.c
+Source: RTOSDemo/../../Common/Minimal/recmutex.c
+Source: RTOSDemo/../../Common/Minimal/semtest.c
+Source: RTOSDemo/../../../Source/tasks.c
+Source: RTOSDemo/../../../Source/list.c
+Source: RTOSDemo/../../../Source/queue.c
+Source: RTOSDemo/../../../Source/croutine.c
+Source: RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S
+Source: RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c
+Source: RTOSDemo/../../../Source/portable/MemMang/heap_2.c
+Source: RTOSDemo/flop/flop-reg-test.c
+Source: RTOSDemo/flop/flop.c
+Source: RTOSDemo/partest/partest.c
+Source: RTOSDemo/serial/serial.c
+Source: RTOSDemo/main.c
+DefaultInit: EXECUTABLE
+InitBram: 0
+Active: 1
+CompilerOptLevel: 0
+GlobPtrOpt: 0
+DebugSym: 1
+ProfileFlag: 0
+SearchIncl: ../../Source/include ../Common/include ./RTOSDemo ./RTOSDemo/flop
+ProgStart:
+StackSize:
+HeapSize:
+LinkerScript: RTOSDemo/RTOSDemo_linker_script.ld
+ProgCCFlags: -D GCC_PPC440 -mregnames
+CompileInXps: 1
+NonXpsApp: 0
diff --git a/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/system_incl.make b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/system_incl.make new file mode 100644 index 000000000..78aad3208 --- /dev/null +++ b/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/system_incl.make @@ -0,0 +1,151 @@ +#################################################################
+# Makefile generated by Xilinx Platform Studio
+# Project:C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.xmp
+#
+# WARNING : This file will be re-generated every time a command
+# to run a make target is invoked. So, any changes made to this
+# file manually, will be lost when make is invoked next.
+#################################################################
+
+XILINX_EDK_DIR = /cygdrive/c/devtools/Xilinx/11.1/EDK
+NON_CYG_XILINX_EDK_DIR = C:/devtools/Xilinx/11.1/EDK
+
+SYSTEM = system
+
+MHSFILE = system.mhs
+
+MSSFILE = system.mss
+
+FPGA_ARCH = virtex5
+
+DEVICE = xc5vfx70tff1136-1
+
+LANGUAGE = vhdl
+
+SEARCHPATHOPT =
+
+SUBMODULE_OPT =
+
+PLATGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(SUBMODULE_OPT) -msg __xps/ise/xmsgprops.lst
+
+LIBGEN_OPTIONS = -mhs $(MHSFILE) -p $(DEVICE) $(SEARCHPATHOPT) -msg __xps/ise/xmsgprops.lst
+
+OBSERVE_PAR_OPTIONS = -error yes
+
+RTOSDEMO_OUTPUT_DIR = RTOSDemo
+RTOSDEMO_OUTPUT = $(RTOSDEMO_OUTPUT_DIR)/executable.elf
+
+MICROBLAZE_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop.elf
+PPC405_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc405/ppc_bootloop.elf
+PPC440_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc440/ppc440_bootloop.elf
+BOOTLOOP_DIR = bootloops
+
+PPC440_0_BOOTLOOP = $(BOOTLOOP_DIR)/ppc440_0.elf
+
+BRAMINIT_ELF_FILES = $(PPC440_0_BOOTLOOP)
+BRAMINIT_ELF_FILE_ARGS = -pe ppc440_0 $(PPC440_0_BOOTLOOP)
+
+ALL_USER_ELF_FILES = $(RTOSDEMO_OUTPUT)
+
+SIM_CMD = vsim
+
+BEHAVIORAL_SIM_SCRIPT = simulation/behavioral/$(SYSTEM)_setup.do
+
+STRUCTURAL_SIM_SCRIPT = simulation/structural/$(SYSTEM)_setup.do
+
+TIMING_SIM_SCRIPT = simulation/timing/$(SYSTEM)_setup.do
+
+DEFAULT_SIM_SCRIPT = $(BEHAVIORAL_SIM_SCRIPT)
+
+MIX_LANG_SIM_OPT = -mixed no
+
+SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) $(MIX_LANG_SIM_OPT) -msg __xps/ise/xmsgprops.lst -sd implementation/ -s mti -X C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/
+
+
+LIBRARIES = \
+ ppc440_0/lib/libxil.a
+
+LIBSCLEAN_TARGETS = ppc440_0_libsclean
+
+PROGRAMCLEAN_TARGETS = RTOSDemo_programclean
+
+CORE_STATE_DEVELOPMENT_FILES =
+
+WRAPPER_NGC_FILES = implementation/ppc440_0_wrapper.ngc \ +implementation/plb_v46_0_wrapper.ngc \ +implementation/xps_bram_if_cntlr_1_wrapper.ngc \ +implementation/xps_bram_if_cntlr_1_bram_wrapper.ngc \ +implementation/rs232_uart_1_wrapper.ngc \ +implementation/leds_8bit_wrapper.ngc \ +implementation/leds_positions_wrapper.ngc \ +implementation/push_buttons_5bit_wrapper.ngc \ +implementation/dip_switches_8bit_wrapper.ngc \ +implementation/iic_eeprom_wrapper.ngc \ +implementation/sram_wrapper.ngc \ +implementation/pcie_bridge_wrapper.ngc \ +implementation/ppc440_0_splb0_wrapper.ngc \ +implementation/ethernet_mac_wrapper.ngc \ +implementation/ddr2_sdram_wrapper.ngc \ +implementation/sysace_compactflash_wrapper.ngc \ +implementation/clock_generator_0_wrapper.ngc \ +implementation/jtagppc_cntlr_inst_wrapper.ngc \ +implementation/proc_sys_reset_0_wrapper.ngc \ +implementation/xps_intc_0_wrapper.ngc
+
+POSTSYN_NETLIST = implementation/$(SYSTEM).ngc
+
+SYSTEM_BIT = implementation/$(SYSTEM).bit
+
+DOWNLOAD_BIT = implementation/download.bit
+
+SYSTEM_ACE = implementation/$(SYSTEM).ace
+
+UCF_FILE = data/system.ucf
+
+BMM_FILE = implementation/$(SYSTEM).bmm
+
+BITGEN_UT_FILE = etc/bitgen.ut
+
+XFLOW_OPT_FILE = etc/fast_runtime.opt
+XFLOW_DEPENDENCY = __xps/xpsxflow.opt $(XFLOW_OPT_FILE)
+
+XPLORER_DEPENDENCY = __xps/xplorer.opt
+XPLORER_OPTIONS = -p $(DEVICE) -uc $(SYSTEM).ucf -bm $(SYSTEM).bmm -max_runs 7
+
+FPGA_IMP_DEPENDENCY = $(BMM_FILE) $(POSTSYN_NETLIST) $(UCF_FILE) $(XFLOW_DEPENDENCY)
+
+SDK_EXPORT_DIR = SDK/SDK_Export/hw
+SYSTEM_HW_HANDOFF = $(SDK_EXPORT_DIR)/$(SYSTEM).xml
+SYSTEM_HW_HANDOFF_BIT = $(SDK_EXPORT_DIR)/$(SYSTEM).bit
+SYSTEM_HW_HANDOFF_BMM = $(SDK_EXPORT_DIR)/$(SYSTEM)_bd.bmm
+SYSTEM_HW_HANDOFF_DEP = $(SYSTEM_HW_HANDOFF) $(SYSTEM_HW_HANDOFF_BIT) $(SYSTEM_HW_HANDOFF_BMM)
+
+#################################################################
+# SOFTWARE APPLICATION RTOSDEMO
+#################################################################
+
+RTOSDEMO_SOURCES = /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/main.c
+
+RTOSDEMO_HEADERS =
+
+RTOSDEMO_CC = powerpc-eabi-gcc
+RTOSDEMO_CC_SIZE = powerpc-eabi-size
+RTOSDEMO_CC_OPT = -O0
+RTOSDEMO_CFLAGS = -D GCC_PPC440 -mregnames
+RTOSDEMO_CC_SEARCH = # -B
+RTOSDEMO_LIBPATH = -L./ppc440_0/lib/ # -L
+RTOSDEMO_INCLUDES = -I./ppc440_0/include/ -I../../Source/include -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop
+RTOSDEMO_LFLAGS = # -l
+RTOSDEMO_LINKER_SCRIPT = /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld
+RTOSDEMO_LINKER_SCRIPT_FLAG = -Wl,-T -Wl,$(RTOSDEMO_LINKER_SCRIPT)
+RTOSDEMO_CC_DEBUG_FLAG = -g
+RTOSDEMO_CC_PROFILE_FLAG = # -pg
+RTOSDEMO_CC_GLOBPTR_FLAG= # -msdata=eabi
+RTOSDEMO_CC_INFERRED_FLAGS= -mcpu=440
+RTOSDEMO_CC_START_ADDR_FLAG= # # -Wl,-defsym -Wl,_START_ADDR=
+RTOSDEMO_CC_STACK_SIZE_FLAG= # # -Wl,-defsym -Wl,_STACK_SIZE=
+RTOSDEMO_CC_HEAP_SIZE_FLAG= # # -Wl,-defsym -Wl,_HEAP_SIZE=
+RTOSDEMO_OTHER_CC_FLAGS= $(RTOSDEMO_CC_GLOBPTR_FLAG) \
+ $(RTOSDEMO_CC_START_ADDR_FLAG) $(RTOSDEMO_CC_STACK_SIZE_FLAG) $(RTOSDEMO_CC_HEAP_SIZE_FLAG) \
+ $(RTOSDEMO_CC_INFERRED_FLAGS) \
+ $(RTOSDEMO_LINKER_SCRIPT_FLAG) $(RTOSDEMO_CC_DEBUG_FLAG) $(RTOSDEMO_CC_PROFILE_FLAG)
|
