diff options
| author | rtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2> | 2019-10-16 04:31:57 +0000 |
|---|---|---|
| committer | rtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2> | 2019-10-16 04:31:57 +0000 |
| commit | 25c08ac6fa20bd9da9cd6f791e24031c8bae82eb (patch) | |
| tree | 907452600449199c7b076e8fd76cf979bfd4ddce /FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC | |
| parent | 250429ced71c2b004c47db733203a38180abe8ba (diff) | |
| download | freertos-25c08ac6fa20bd9da9cd6f791e24031c8bae82eb.tar.gz | |
Rename RISC-V-Qemu-sive_e_Freedom_Studio directory to RISC-V-Qemu-sifive_e-Eclipse-GCC as it is now using Vanilla Eclipse and vanilla GCC in place of Freedom Studio.
git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2743 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
Diffstat (limited to 'FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC')
58 files changed, 7196 insertions, 0 deletions
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/.cproject b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/.cproject new file mode 100644 index 000000000..debca76bc --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/.cproject @@ -0,0 +1,93 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
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+ <externalSettings/>
+ <extensions>
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+ <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/full_demo/standard_demo_tasks/include}""/>
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/freedom-e-sdk/env}""/>
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/freedom-e-sdk/include}""/>
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/freedom-e-sdk/env/freedom-e300-hifive1}""/>
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/freertos_source/include}""/>
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/freertos_source/portable/GCC/RISC-V}""/>
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+ </folderInfo>
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+</cproject>
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/.project b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/.project new file mode 100644 index 000000000..c1f63311d --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/.project @@ -0,0 +1,155 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>RTOSDemo</name>
+ <comment></comment>
+ <projects>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <triggers>clean,full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+ <triggers>full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+ </natures>
+ <linkedResources>
+ <link>
+ <name>freertos_source</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>freertos_source/event_groups.c</name>
+ <type>1</type>
+ <locationURI>FREERTOS_ROOT/FreeRTOS/Source/event_groups.c</locationURI>
+ </link>
+ <link>
+ <name>freertos_source/include</name>
+ <type>2</type>
+ <locationURI>FREERTOS_ROOT/FreeRTOS/Source/include</locationURI>
+ </link>
+ <link>
+ <name>freertos_source/list.c</name>
+ <type>1</type>
+ <locationURI>FREERTOS_ROOT/FreeRTOS/Source/list.c</locationURI>
+ </link>
+ <link>
+ <name>freertos_source/portable</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>freertos_source/queue.c</name>
+ <type>1</type>
+ <locationURI>FREERTOS_ROOT/FreeRTOS/Source/queue.c</locationURI>
+ </link>
+ <link>
+ <name>freertos_source/stream_buffer.c</name>
+ <type>1</type>
+ <locationURI>FREERTOS_ROOT/FreeRTOS/Source/stream_buffer.c</locationURI>
+ </link>
+ <link>
+ <name>freertos_source/tasks.c</name>
+ <type>1</type>
+ <locationURI>FREERTOS_ROOT/FreeRTOS/Source/tasks.c</locationURI>
+ </link>
+ <link>
+ <name>freertos_source/timers.c</name>
+ <type>1</type>
+ <locationURI>FREERTOS_ROOT/FreeRTOS/Source/timers.c</locationURI>
+ </link>
+ <link>
+ <name>full_demo/standard_demo_tasks</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>freertos_source/portable/GCC</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>freertos_source/portable/MemMang</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>full_demo/standard_demo_tasks/EventGroupsDemo.c</name>
+ <type>1</type>
+ <locationURI>FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/EventGroupsDemo.c</locationURI>
+ </link>
+ <link>
+ <name>full_demo/standard_demo_tasks/GenQTest.c</name>
+ <type>1</type>
+ <locationURI>FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/GenQTest.c</locationURI>
+ </link>
+ <link>
+ <name>full_demo/standard_demo_tasks/TaskNotify.c</name>
+ <type>1</type>
+ <locationURI>FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/TaskNotify.c</locationURI>
+ </link>
+ <link>
+ <name>full_demo/standard_demo_tasks/TimerDemo.c</name>
+ <type>1</type>
+ <locationURI>FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/TimerDemo.c</locationURI>
+ </link>
+ <link>
+ <name>full_demo/standard_demo_tasks/blocktim.c</name>
+ <type>1</type>
+ <locationURI>FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/blocktim.c</locationURI>
+ </link>
+ <link>
+ <name>full_demo/standard_demo_tasks/dynamic.c</name>
+ <type>1</type>
+ <locationURI>FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/dynamic.c</locationURI>
+ </link>
+ <link>
+ <name>full_demo/standard_demo_tasks/include</name>
+ <type>2</type>
+ <locationURI>FREERTOS_ROOT/FreeRTOS/Demo/Common/include</locationURI>
+ </link>
+ <link>
+ <name>full_demo/standard_demo_tasks/recmutex.c</name>
+ <type>1</type>
+ <locationURI>FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/recmutex.c</locationURI>
+ </link>
+ <link>
+ <name>freertos_source/portable/GCC/RISC-V</name>
+ <type>2</type>
+ <locationURI>FREERTOS_ROOT/FreeRTOS/Source/portable/GCC/RISC-V</locationURI>
+ </link>
+ <link>
+ <name>freertos_source/portable/MemMang/heap_4.c</name>
+ <type>1</type>
+ <locationURI>FREERTOS_ROOT/FreeRTOS/Source/portable/MemMang/heap_4.c</locationURI>
+ </link>
+ </linkedResources>
+ <filteredResources>
+ <filter>
+ <id>1571146760235</id>
+ <name>freertos_source/portable/GCC/RISC-V/chip_specific_extensions</name>
+ <type>9</type>
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+ </matcher>
+ </filter>
+ </filteredResources>
+ <variableList>
+ <variable>
+ <name>FREERTOS_ROOT</name>
+ <value>$%7BPARENT-3-PROJECT_LOC%7D</value>
+ </variable>
+ </variableList>
+</projectDescription>
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/.settings/language.settings.xml b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/.settings/language.settings.xml new file mode 100644 index 000000000..97f9f0d9f --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/.settings/language.settings.xml @@ -0,0 +1,14 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+ <configuration id="cdt.managedbuild.config.gnu.cross.exe.debug.244253252" name="Debug">
+ <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+ <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+ <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ <provider class="org.eclipse.cdt.internal.build.crossgcc.CrossGCCBuiltinSpecsDetector" console="false" env-hash="-564276645149001" id="org.eclipse.cdt.build.crossgcc.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <language-scope id="org.eclipse.cdt.core.gcc"/>
+ <language-scope id="org.eclipse.cdt.core.g++"/>
+ </provider>
+ </extension>
+ </configuration>
+</project>
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/Demo Documentation.url b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/Demo Documentation.url new file mode 100644 index 000000000..e2478fbef --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/Demo Documentation.url @@ -0,0 +1,5 @@ +[{000214A0-0000-0000-C000-000000000046}]
+Prop3=19,11
+[InternetShortcut]
+IDList=
+URL=https://freertos.org/RTOS-RISC-V-FreedomStudio-QMEU.html
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/FreeRTOSConfig.h b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/FreeRTOSConfig.h new file mode 100644 index 000000000..c48a10b3a --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/FreeRTOSConfig.h @@ -0,0 +1,168 @@ +/*
+ FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+ ***************************************************************************
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+ ***************************************************************************
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following
+ link: http://www.freertos.org/a00114.html
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that is more than just the market leader, it *
+ * is the industry's de facto standard. *
+ * *
+ * Help yourself get started quickly while simultaneously helping *
+ * to support the FreeRTOS project by purchasing a FreeRTOS *
+ * tutorial book, reference manual, or both: *
+ * http://www.FreeRTOS.org/Documentation *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
+ the FAQ page "My application does not run, what could be wrong?". Have you
+ defined configASSERT()?
+
+ http://www.FreeRTOS.org/support - In return for receiving this top quality
+ embedded software for free we request you assist our global community by
+ participating in the support forum.
+
+ http://www.FreeRTOS.org/training - Investing in training allows your team to
+ be as productive as possible as early as possible. Now you can receive
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+ Ltd, and the world's leading authority on the world's leading RTOS.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and commercial middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+#include "platform.h"
+
+/*
+ * For some reason the standard demo timer demo/test tasks fail when executing
+ * in QEMU, although they pass on other RISC-V platforms. This requires
+ * further investigation, but for now, defining _WINDOWS_ has the effect of
+ * using the wider timer test thresholds that are normally only used when the
+ * tests are used with the FreeRTOS Windows port (which is not deterministic
+ * and therefore requires wider margins).
+ */
+#define _WINDOWS_
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+#define configCLINT_BASE_ADDRESS CLINT_CTRL_ADDR
+#define configUSE_PREEMPTION 1
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 1
+#define configCPU_CLOCK_HZ ( 10000000 ) /*QEMU*/
+#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )
+#define configMAX_PRIORITIES ( 7 )
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 70 )
+#define configTOTAL_HEAP_SIZE ( ( size_t ) 14500 )
+#define configMAX_TASK_NAME_LEN ( 16 )
+#define configUSE_TRACE_FACILITY 0
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 0
+#define configUSE_MUTEXES 1
+#define configQUEUE_REGISTRY_SIZE 8
+#define configCHECK_FOR_STACK_OVERFLOW 2
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_MALLOC_FAILED_HOOK 1
+#define configUSE_APPLICATION_TASK_TAG 0
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configGENERATE_RUN_TIME_STATS 0
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Software timer definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
+#define configTIMER_QUEUE_LENGTH 4
+#define configTIMER_TASK_STACK_DEPTH ( 120 )
+
+/* Task priorities. Allow these to be overridden. */
+#ifndef uartPRIMARY_PRIORITY
+ #define uartPRIMARY_PRIORITY ( configMAX_PRIORITIES - 3 )
+#endif
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskCleanUpResources 1
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_eTaskGetState 1
+#define INCLUDE_xTimerPendFunctionCall 1
+#define INCLUDE_xTaskAbortDelay 1
+#define INCLUDE_xTaskGetHandle 1
+#define INCLUDE_xSemaphoreGetMutexHolder 1
+
+/* Normal assert() semantics without relying on the provision of an assert.h
+header file. */
+void vAssertCalled( void );
+#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled()
+
+/* Overwrite some of the stack sizes allocated to various test and demo tasks.
+Like all task stack sizes, the value is the number of words, not bytes. */
+#define bktBLOCK_TIME_TASK_STACK_SIZE 100
+#define notifyNOTIFIED_TASK_STACK_SIZE 120
+#define priSUSPENDED_RX_TASK_STACK_SIZE 90
+#define tmrTIMER_TEST_TASK_STACK_SIZE 100
+#define ebRENDESVOUS_TEST_TASK_STACK_SIZE 100
+#define ebEVENT_GROUP_SET_BITS_TEST_TASK_STACK_SIZE 115
+#define genqMUTEX_TEST_TASK_STACK_SIZE 90
+#define genqGENERIC_QUEUE_TEST_TASK_STACK_SIZE 100
+#define recmuRECURSIVE_MUTEX_TEST_TASK_STACK_SIZE 90
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/Hardware_Qemu.launch b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/Hardware_Qemu.launch new file mode 100644 index 000000000..c95af4eb0 --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/Hardware_Qemu.launch @@ -0,0 +1,47 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="org.eclipse.cdt.debug.gdbjtag.launchConfigurationType">
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="3"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="Generic TCP/IP"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDeviceId" value="org.eclipse.cdt.debug.gdbjtag.core.jtagdevice.genericDevice"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="1234"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="riscv64-unknown-elf-gdb.exe -iex "set mem inaccessible-by-default off" -iex "set arch riscv:rv32" -iex "set riscv use_compressed_breakpoint off""/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.REMOTE_TIMEOUT_ENABLED" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.REMOTE_TIMEOUT_VALUE" value=""/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug\RTOSDemo.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="RTOSDemo"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/RTOSDemo"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"> <gdbmemoryBlockExpression address="2147486760" label="0x80000c28"/> </memoryBlockExpressionList> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/blinky_demo/main_blinky.c b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/blinky_demo/main_blinky.c new file mode 100644 index 000000000..96b9f9110 --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/blinky_demo/main_blinky.c @@ -0,0 +1,204 @@ +/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/******************************************************************************
+ * NOTE 1: This project provides two demo applications. A simple blinky
+ * style project, and a more comprehensive test and demo application. The
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
+ * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
+ * in main.c. This file implements the simply blinky style version.
+ *
+ * NOTE 2: This file only contains the source code that is specific to the
+ * basic demo. Generic functions, such FreeRTOS hook functions, and functions
+ * required to configure the hardware are defined in main.c.
+ ******************************************************************************
+ *
+ * main_blinky() creates one queue, and two tasks. It then starts the
+ * scheduler.
+ *
+ * The Queue Send Task:
+ * The queue send task is implemented by the prvQueueSendTask() function in
+ * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly
+ * block for 1000 milliseconds, before sending the value 100 to the queue that
+ * was created within main_blinky(). Once the value is sent, the task loops
+ * back around to block for another 1000 milliseconds...and so on.
+ *
+ * The Queue Receive Task:
+ * The queue receive task is implemented by the prvQueueReceiveTask() function
+ * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly
+ * blocks on attempts to read data from the queue that was created within
+ * main_blinky(). When data is received, the task checks the value of the
+ * data, and if the value equals the expected 100, writes 'Blink' to the UART
+ * (the UART is used in place of the LED to allow easy execution in QEMU). The
+ * 'block time' parameter passed to the queue receive function specifies that
+ * the task should be held in the Blocked state indefinitely to wait for data to
+ * be available on the queue. The queue receive task will only leave the
+ * Blocked state when the queue send task writes to the queue. As the queue
+ * send task writes to the queue every 1000 milliseconds, the queue receive
+ * task leaves the Blocked state every 1000 milliseconds, and therefore toggles
+ * the LED every 200 milliseconds.
+ */
+
+/* Standard includes. */
+#include <stdio.h>
+#include <string.h>
+#include <unistd.h>
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+/* Priorities used by the tasks. */
+#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
+#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
+
+/* The rate at which data is sent to the queue. The 200ms value is converted
+to ticks using the pdMS_TO_TICKS() macro. */
+#define mainQUEUE_SEND_FREQUENCY_MS pdMS_TO_TICKS( 1000 )
+
+/* The maximum number items the queue can hold. The priority of the receiving
+task is above the priority of the sending task, so the receiving task will
+preempt the sending task and remove the queue items each time the sending task
+writes to the queue. Therefore the queue will never have more than one item in
+it at any time, and even with a queue length of 1, the sending task will never
+find the queue full. */
+#define mainQUEUE_LENGTH ( 1 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in
+ * main.c.
+ */
+void main_blinky( void );
+
+/*
+ * The tasks as described in the comments at the top of this file.
+ */
+static void prvQueueReceiveTask( void *pvParameters );
+static void prvQueueSendTask( void *pvParameters );
+
+/*-----------------------------------------------------------*/
+
+/* The queue used by both tasks. */
+static QueueHandle_t xQueue = NULL;
+
+/*-----------------------------------------------------------*/
+
+void main_blinky( void )
+{
+ /* Create the queue. */
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) );
+
+ if( xQueue != NULL )
+ {
+ /* Start the two tasks as described in the comments at the top of this
+ file. */
+ xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */
+ "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */
+ configMINIMAL_STACK_SIZE * 2U, /* The size of the stack to allocate to the task. */
+ NULL, /* The parameter passed to the task - not used in this case. */
+ mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */
+ NULL ); /* The task handle is not required, so NULL is passed. */
+
+ xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE * 2U, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );
+
+ /* Start the tasks and timer running. */
+ vTaskStartScheduler();
+ }
+
+ /* If all is well, the scheduler will now be running, and the following
+ line will never be reached. If the following line does execute, then
+ there was insufficient FreeRTOS heap memory available for the Idle and/or
+ timer tasks to be created. See the memory management section on the
+ FreeRTOS web site for more details on the FreeRTOS heap
+ http://www.freertos.org/a00111.html. */
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+static void prvQueueSendTask( void *pvParameters )
+{
+TickType_t xNextWakeTime;
+const unsigned long ulValueToSend = 100UL;
+BaseType_t xReturned;
+
+ /* Remove compiler warning about unused parameter. */
+ ( void ) pvParameters;
+
+ /* Initialise xNextWakeTime - this only needs to be done once. */
+ xNextWakeTime = xTaskGetTickCount();
+
+ for( ;; )
+ {
+ /* Place this task in the blocked state until it is time to run again. */
+ vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );
+
+ /* Send to the queue - causing the queue receive task to unblock and
+ toggle the LED. 0 is used as the block time so the sending operation
+ will not block - it shouldn't need to block as the queue should always
+ be empty at this point in the code. */
+ xReturned = xQueueSend( xQueue, &ulValueToSend, 0U );
+ configASSERT( xReturned == pdPASS );
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvQueueReceiveTask( void *pvParameters )
+{
+unsigned long ulReceivedValue;
+const unsigned long ulExpectedValue = 100UL;
+const char * const pcPassMessage = "Blink\r\n";
+const char * const pcFailMessage = "Unexpected value received\r\n";
+extern void vSendString( const char * pcString );
+
+ /* Remove compiler warning about unused parameter. */
+ ( void ) pvParameters;
+
+ for( ;; )
+ {
+ /* Wait until something arrives in the queue - this task will block
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
+ FreeRTOSConfig.h. */
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
+
+ /* To get here something must have been received from the queue, but
+ is it the expected value? If it is, toggle the LED. */
+ if( ulReceivedValue == ulExpectedValue )
+ {
+ vSendString( pcPassMessage );
+ ulReceivedValue = 0U;
+ }
+ else
+ {
+ vSendString( pcFailMessage );
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/fe310-xsvd.json b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/fe310-xsvd.json new file mode 100644 index 000000000..d1767faf8 --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/fe310-xsvd.json @@ -0,0 +1,2325 @@ +{
+ "schemaVersion": "0.2.4",
+ "contentVersion": "0.2.0",
+ "headerVersion": "0.2.0",
+ "device": {
+ "fe310": {
+ "displayName": "Freedom E310-G000",
+ "description": "The FE310-G000 is the first Freedom E300 SoC, and is the industry's first commercially available RISC-V SoC. The FE310-G000 is built around the E31 Core Complex instantiated in the Freedom E300 platform.",
+ "supplier": {
+ "name": "sifive",
+ "id": "1",
+ "displayName": "SiFive",
+ "fullName": "SiFive, Inc.",
+ "contact": "info@sifive.com"
+ },
+ "busWidth": "32",
+ "resetMask": "all",
+ "resetValue": "0x00000000",
+ "access": "rw",
+ "headerGuardPrefix": "SIFIVE_DEVICES_FE310_",
+ "headerTypePrefix": "sifive_fe310_",
+ "headerInterruptPrefix": "sifive_fe310_interrupt_global_",
+ "headerInterruptEnumPrefix": "riscv_interrupts_global_",
+ "revision": "r0p0",
+ "numInterrupts": "51",
+ "priorityBits": "3",
+ "regWidth": "32",
+ "cores": {
+ "e31": {
+ "harts": "1",
+ "isa": "RV32IMAC",
+ "isaVersion": "2.2",
+ "mpu": "pmp",
+ "mmu": "none",
+ "localInterrupts": {
+ "machine_software": {
+ "description": "Machine Software Interrupt",
+ "value": "3"
+ },
+ "machine_timer": {
+ "description": "Machine Timer Interrupt",
+ "value": "7"
+ },
+ "machine_ext": {
+ "description": "Machine External Interrupt",
+ "value": "11"
+ }
+ },
+ "numLocalInterrupts": "0"
+ }
+ },
+ "peripherals": {
+ "clint": {
+ "description": "Core Complex Local Interruptor (CLINT) Peripheral",
+ "baseAddress": "0x02000000",
+ "size": "0x10000",
+ "registers": {
+ "msip": {
+ "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
+ "addressOffset": "0x0000",
+ "arraySize": "1"
+ }
+ },
+ "clusters": {
+ "mtimecmp": {
+ "description": "Machine Time Compare Registers per Hart",
+ "addressOffset": "0x4000",
+ "arraySize": "1",
+ "registers": {
+ "low": {
+ "description": "Machine Compare Register Low",
+ "addressOffset": "0x0000"
+ },
+ "high": {
+ "description": "Machine Compare Register High",
+ "addressOffset": "0x0004"
+ }
+ }
+ },
+ "mtime": {
+ "description": "Machine Time Register",
+ "addressOffset": "0xBFF8",
+ "access": "r",
+ "registers": {
+ "low": {
+ "description": "Machine Time Register Low",
+ "addressOffset": "0x0000"
+ },
+ "high": {
+ "description": "Machine Time Register High",
+ "addressOffset": "0x0004"
+ }
+ }
+ }
+ }
+ },
+ "plic": {
+ "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
+ "baseAddress": "0x0C000000",
+ "size": "0x4000000",
+ "registers": {
+ "priorities": {
+ "arraySize": "52",
+ "description": "Interrupt Priorities Registers; 0 is reserved.",
+ "addressOffset": "0x0000",
+ "fields": {
+ "value": {
+ "description": "The priority for a given global interrupt",
+ "bitOffset": "0",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "pendings": {
+ "arraySize": "2",
+ "description": "Interrupt Pending Bits Registers",
+ "addressOffset": "0x1000",
+ "access": "r"
+ }
+ },
+ "clusters": {
+ "enablestarget0": {
+ "description": "Hart 0 Interrupt Enable Bits",
+ "addressOffset": "0x00002000",
+ "clusters": {
+ "m": {
+ "addressOffset": "0x0000",
+ "description": "Hart 0 M-mode Interrupt Enable Bits",
+ "registers": {
+ "enables": {
+ "arraySize": "2",
+ "description": "Interrupt Enable Bits Registers",
+ "addressOffset": "0x0000"
+ }
+ }
+ }
+ }
+ },
+ "target0": {
+ "description": "Hart 0 Interrupt Thresholds",
+ "addressOffset": "0x00200000",
+ "clusters": {
+ "m": {
+ "addressOffset": "0x0000",
+ "description": "Hart 0 M-Mode Interrupt Threshold",
+ "registers": {
+ "threshold": {
+ "description": "The Priority Threshold Register",
+ "addressOffset": "0x0000",
+ "fields": {
+ "value": {
+ "description": "The priority threshold value",
+ "bitOffset": "0",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "claimcomplete": {
+ "description": "The Interrupt Claim/Completion Register",
+ "addressOffset": "0x0004"
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "wdog": {
+ "description": "Watchdog Timer (WDT), part of Always-On Domain",
+ "baseAddress": "0x10000000",
+ "size": "0x0040",
+ "resetMask": "none",
+ "registers": {
+ "cfg": {
+ "description": "Watchdog Configuration Register",
+ "addressOffset": "0x0000",
+ "fields": {
+ "scale": {
+ "description": "Watchdog counter scale",
+ "bitOffset": "0",
+ "bitWidth": "4"
+ },
+ "rsten": {
+ "description": "Watchdog full reset enable",
+ "bitOffset": "8",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "zerocmp": {
+ "description": "Watchdog zero on comparator",
+ "bitOffset": "9",
+ "bitWidth": "1"
+ },
+ "enalways": {
+ "description": "Watchdog enable counter always",
+ "bitOffset": "12",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "encoreawake": {
+ "description": "Watchdog counter only when awake",
+ "bitOffset": "13",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "cmpip": {
+ "description": "Watchdog interrupt pending",
+ "bitOffset": "28",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "count": {
+ "description": "Watchdog Count Register",
+ "addressOffset": "0x0008"
+ },
+ "scale": {
+ "description": "Watchdog Scale Register",
+ "addressOffset": "0x0010",
+ "fields": {
+ "value": {
+ "description": "Watchdog scale value",
+ "bitOffset": "0",
+ "bitWidth": "16"
+ }
+ }
+ },
+ "feed": {
+ "description": "Watchdog Feed Address Register",
+ "addressOffset": "0x0018"
+ },
+ "key": {
+ "description": "Watchdog Key Register",
+ "addressOffset": "0x001C"
+ },
+ "cmp": {
+ "description": "Watchdog Compare Register",
+ "addressOffset": "0x0020",
+ "fields": {
+ "value": {
+ "description": "Watchdog compare value",
+ "bitOffset": "0",
+ "bitWidth": "16"
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "wdogcmp": {
+ "description": "Watchdog Compare Interrupt",
+ "value": "1"
+ }
+ }
+ },
+ "rtc": {
+ "description": "Real-Time Clock (RTC), part of Always-On Domain",
+ "baseAddress": "0x10000040",
+ "size": "0x0030",
+ "resetMask": "none",
+ "registers": {
+ "cfg": {
+ "description": "RTC Configuration Register",
+ "addressOffset": "0x0000",
+ "fields": {
+ "scale": {
+ "description": "RTC clock rate scale",
+ "bitOffset": "0",
+ "bitWidth": "4"
+ },
+ "enalways": {
+ "description": "RTC counter enable",
+ "bitOffset": "12",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "cmpip": {
+ "description": "RTC comparator interrupt pending",
+ "bitOffset": "28",
+ "bitWidth": "1",
+ "access": "r"
+ }
+ }
+ },
+ "low": {
+ "description": "RTC Counter Register Low",
+ "addressOffset": "0x0008"
+ },
+ "high": {
+ "description": "RTC Counter Register High",
+ "addressOffset": "0x000C",
+ "fields": {
+ "value": {
+ "description": "RTC counter register, high bits",
+ "bitOffset": "0",
+ "bitWidth": "16"
+ }
+ }
+ },
+ "scale": {
+ "description": "RTC Scale Register",
+ "addressOffset": "0x0010"
+ },
+ "cmp": {
+ "description": "RTC Compare Register",
+ "addressOffset": "0x0020"
+ }
+ },
+ "interrupts": {
+ "rtccmp": {
+ "description": "RTC Compare Interrupt",
+ "value": "2"
+ }
+ }
+ },
+ "pmu": {
+ "description": "Power-Management Unit (PMU), part of Always-On Domain",
+ "baseAddress": "0x10000100",
+ "size": "0x0050",
+ "resetMask": "none",
+ "registers": {
+ "wakeupi": {
+ "description": "Wakeup program instruction Registers",
+ "addressOffset": "0x0000",
+ "arraySize": "8"
+ },
+ "sleepi": {
+ "description": "Sleep Program Instruction Registers",
+ "addressOffset": "0x0020",
+ "arraySize": "8"
+ },
+ "ie": {
+ "description": "PMU Interrupt Enables Register",
+ "addressOffset": "0x0040",
+ "fields": {
+ "rtc": {
+ "description": "RTC Comparator active",
+ "bitOffset": "1",
+ "bitWidth": "1"
+ },
+ "dwakeup": {
+ "description": "dwakeup_n pin active",
+ "bitOffset": "2",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "cause": {
+ "description": "PMU Wakeup Cause Register",
+ "addressOffset": "0x0044",
+ "fields": {
+ "wakeupcause": {
+ "description": "Wakeup cause",
+ "bitOffset": "0",
+ "bitWidth": "2",
+ "access": "r",
+ "enumerations": {
+ "wakeupcause-enum": {
+ "description": "Wakeup Cause Values Enumeration",
+ "values": {
+ "0": {
+ "displayName": "reset",
+ "description": "Reset Wakeup"
+ },
+ "1": {
+ "displayName": "rtc",
+ "description": "RTC Wakeup"
+ },
+ "2": {
+ "displayName": "dwakeup",
+ "description": "Digital input Wakeup"
+ },
+ "*": {
+ "displayName": "undefined"
+ }
+ }
+ }
+ }
+ },
+ "resetcause": {
+ "description": "Reset cause",
+ "bitOffset": "8",
+ "bitWidth": "2",
+ "access": "r",
+ "enumerations": {
+ "resetcause-enum": {
+ "description": "Reset Cause Values Enumeration",
+ "values": {
+ "1": {
+ "displayName": "external",
+ "description": "External reset"
+ },
+ "2": {
+ "displayName": "watchdog",
+ "description": "Watchdog timer reset"
+ },
+ "*": {
+ "displayName": "undefined"
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "sleep": {
+ "description": "PMU Initiate Sleep Sequence Register",
+ "addressOffset": "0x0048"
+ },
+ "key": {
+ "description": "PMU Key Register",
+ "addressOffset": "0x004C"
+ }
+ }
+ },
+ "aon": {
+ "description": "Always-On (AON) Domain",
+ "baseAddress": "0x10000070",
+ "size": "0x0090",
+ "resetMask": "none",
+ "registers": {
+ "lfrosccfg": {
+ "description": "Internal Programmable Low-Frequency Ring Oscillator Register",
+ "addressOffset": "0x0000",
+ "fields": {
+ "div": {
+ "description": "LFROSC divider",
+ "bitOffset": "0",
+ "bitWidth": "6",
+ "resetMask": "all",
+ "resetValue": "0x04"
+ },
+ "trim": {
+ "description": "LFROSC trim value",
+ "bitOffset": "16",
+ "bitWidth": "5",
+ "resetMask": "all",
+ "resetValue": "0x10"
+ },
+ "en": {
+ "description": "LFROSC enable",
+ "bitOffset": "30",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x1"
+ },
+ "rdy": {
+ "description": "LFROSC ready",
+ "bitOffset": "31",
+ "bitWidth": "1",
+ "access": "r"
+ }
+ }
+ },
+ "backup": {
+ "description": "Backup Registers",
+ "addressOffset": "0x0010",
+ "arraySize": "32"
+ }
+ }
+ },
+ "prci": {
+ "description": "Power, Reset, Clock, Interrupt (PRCI) Peripheral",
+ "baseAddress": "0x10008000",
+ "size": "0x8000",
+ "registers": {
+ "hfrosccfg": {
+ "description": "Internal Trimmable Programmable 72 MHz Oscillator Register",
+ "addressOffset": "0x0000",
+ "fields": {
+ "div": {
+ "description": "HFROSC divider",
+ "bitOffset": "0",
+ "bitWidth": "6",
+ "resetMask": "all",
+ "resetValue": "0x04"
+ },
+ "trim": {
+ "description": "HFROSC trim value",
+ "bitOffset": "16",
+ "bitWidth": "5",
+ "resetMask": "all",
+ "resetValue": "0x10"
+ },
+ "en": {
+ "description": "HFROSC enable",
+ "bitOffset": "30",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x1"
+ },
+ "rdy": {
+ "description": "HFROSC ready",
+ "bitOffset": "31",
+ "bitWidth": "1",
+ "access": "r"
+ }
+ }
+ },
+ "hfxosccfg": {
+ "description": "External 16 MHz Crystal Oscillator Register",
+ "addressOffset": "0x0004",
+ "fields": {
+ "en": {
+ "description": "HFXOSC enable",
+ "bitOffset": "30",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x1"
+ },
+ "rdy": {
+ "description": "HFXOSC ready",
+ "bitOffset": "31",
+ "bitWidth": "1",
+ "access": "r"
+ }
+ }
+ },
+ "pllcfg": {
+ "description": "Internal High-Frequency PLL (HFPLL) Register",
+ "addressOffset": "0x0008",
+ "fields": {
+ "r": {
+ "description": "PLL R input divider value",
+ "bitOffset": "0",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x1",
+ "enumerations": {
+ "pllr-enum": {
+ "description": "Reference Clock R Divide Ratio Enumeration",
+ "values": {
+ "0": {
+ "displayName": "/1",
+ "headerName": "div1",
+ "description": "Unchanged"
+ },
+ "1": {
+ "displayName": "/2",
+ "headerName": "div2",
+ "description": "Divided by 2"
+ },
+ "2": {
+ "displayName": "/3",
+ "headerName": "div3",
+ "description": "Divided by 3"
+ },
+ "3": {
+ "displayName": "/4",
+ "headerName": "div4",
+ "description": "Divided by 4"
+ }
+ }
+ }
+ }
+ },
+ "f": {
+ "description": "PLL F multiplier value",
+ "bitOffset": "4",
+ "bitWidth": "6",
+ "resetMask": "all",
+ "resetValue": "0x1F",
+ "enumerations": {
+ "pllf-enum": {
+ "description": "Reference Clock F Multiplier Ratio Enumeration",
+ "values": {
+ "0": {
+ "displayName": "*2",
+ "headerName": "mul2",
+ "description": "Multiplied by 2"
+ },
+ "1": {
+ "displayName": "*4",
+ "headerName": "mul4",
+ "description": "Multiplied by 4"
+ },
+ "2": {
+ "displayName": "*6",
+ "headerName": "mul6",
+ "description": "Multiplied by 6"
+ },
+ "3": {
+ "displayName": "*8",
+ "headerName": "mul8",
+ "description": "Multiplied by 8"
+ },
+ "4": {
+ "displayName": "*10",
+ "headerName": "mul10",
+ "description": "Multiplied by 10"
+ },
+ "5": {
+ "displayName": "*12",
+ "headerName": "mul12",
+ "description": "Multiplied by 12"
+ },
+ "6": {
+ "displayName": "*14",
+ "headerName": "mul14",
+ "description": "Multiplied by 14"
+ },
+ "7": {
+ "displayName": "*16",
+ "headerName": "mul16",
+ "description": "Multiplied by 16"
+ },
+ "8": {
+ "displayName": "*18",
+ "headerName": "mul18",
+ "description": "Multiplied by 18"
+ },
+ "9": {
+ "displayName": "*20",
+ "headerName": "mul20",
+ "description": "Multiplied by 20"
+ },
+ "10": {
+ "displayName": "*22",
+ "headerName": "mul22",
+ "description": "Multiplied by 22"
+ },
+ "11": {
+ "displayName": "*24",
+ "headerName": "mul24",
+ "description": "Multiplied by 24"
+ },
+ "12": {
+ "displayName": "*26",
+ "headerName": "mul26",
+ "description": "Multiplied by 26"
+ },
+ "13": {
+ "displayName": "*28",
+ "headerName": "mul28",
+ "description": "Multiplied by 28"
+ },
+ "14": {
+ "displayName": "*30",
+ "headerName": "mul30",
+ "description": "Multiplied by 30"
+ },
+ "15": {
+ "displayName": "*32",
+ "headerName": "mul32",
+ "description": "Multiplied by 32"
+ },
+ "16": {
+ "displayName": "*34",
+ "headerName": "mul34",
+ "description": "Multiplied by 34"
+ },
+ "17": {
+ "displayName": "*36",
+ "headerName": "mul36",
+ "description": "Multiplied by 36"
+ },
+ "18": {
+ "displayName": "*38",
+ "headerName": "mul38",
+ "description": "Multiplied by 38"
+ },
+ "19": {
+ "displayName": "*40",
+ "headerName": "mul40",
+ "description": "Multiplied by 40"
+ },
+ "20": {
+ "displayName": "*42",
+ "headerName": "mul42",
+ "description": "Multiplied by 42"
+ },
+ "21": {
+ "displayName": "*44",
+ "headerName": "mul44",
+ "description": "Multiplied by 44"
+ },
+ "22": {
+ "displayName": "*46",
+ "headerName": "mul46",
+ "description": "Multiplied by 46"
+ },
+ "23": {
+ "displayName": "*48",
+ "headerName": "mul48",
+ "description": "Multiplied by 48"
+ },
+ "24": {
+ "displayName": "*50",
+ "headerName": "mul50",
+ "description": "Multiplied by 50"
+ },
+ "25": {
+ "displayName": "*52",
+ "headerName": "mul52",
+ "description": "Multiplied by 52"
+ },
+ "26": {
+ "displayName": "*54",
+ "headerName": "mul54",
+ "description": "Multiplied by 54"
+ },
+ "27": {
+ "displayName": "*56",
+ "headerName": "mul56",
+ "description": "Multiplied by 56"
+ },
+ "28": {
+ "displayName": "*58",
+ "headerName": "mul58",
+ "description": "Multiplied by 58"
+ },
+ "29": {
+ "displayName": "*60",
+ "headerName": "mul60",
+ "description": "Multiplied by 60"
+ },
+ "30": {
+ "displayName": "*62",
+ "headerName": "mul62",
+ "description": "Multiplied by 62"
+ },
+ "31": {
+ "displayName": "*64",
+ "headerName": "mul64",
+ "description": "Multiplied by 64"
+ },
+ "32": {
+ "displayName": "*66",
+ "headerName": "mul66",
+ "description": "Multiplied by 66"
+ },
+ "33": {
+ "displayName": "*68",
+ "headerName": "mul68",
+ "description": "Multiplied by 68"
+ },
+ "34": {
+ "displayName": "*70",
+ "headerName": "mul70",
+ "description": "Multiplied by 70"
+ },
+ "35": {
+ "displayName": "*72",
+ "headerName": "mul72",
+ "description": "Multiplied by 72"
+ },
+ "36": {
+ "displayName": "*74",
+ "headerName": "mul74",
+ "description": "Multiplied by 74"
+ },
+ "37": {
+ "displayName": "*76",
+ "headerName": "mul76",
+ "description": "Multiplied by 76"
+ },
+ "38": {
+ "displayName": "*78",
+ "headerName": "mul78",
+ "description": "Multiplied by 78"
+ },
+ "39": {
+ "displayName": "*80",
+ "headerName": "mul80",
+ "description": "Multiplied by 80"
+ },
+ "40": {
+ "displayName": "*82",
+ "headerName": "mul82",
+ "description": "Multiplied by 82"
+ },
+ "41": {
+ "displayName": "*84",
+ "headerName": "mul84",
+ "description": "Multiplied by 84"
+ },
+ "42": {
+ "displayName": "*86",
+ "headerName": "mul86",
+ "description": "Multiplied by 86"
+ },
+ "43": {
+ "displayName": "*88",
+ "headerName": "mul88",
+ "description": "Multiplied by 88"
+ },
+ "44": {
+ "displayName": "*90",
+ "headerName": "mul90",
+ "description": "Multiplied by 90"
+ },
+ "45": {
+ "displayName": "*92",
+ "headerName": "mul92",
+ "description": "Multiplied by 92"
+ },
+ "46": {
+ "displayName": "*94",
+ "headerName": "mul94",
+ "description": "Multiplied by 94"
+ },
+ "47": {
+ "displayName": "*96",
+ "headerName": "mul96",
+ "description": "Multiplied by 96"
+ },
+ "48": {
+ "displayName": "*98",
+ "headerName": "mul98",
+ "description": "Multiplied by 98"
+ },
+ "49": {
+ "displayName": "*100",
+ "headerName": "mul100",
+ "description": "Multiplied by 100"
+ },
+ "50": {
+ "displayName": "*102",
+ "headerName": "mul102",
+ "description": "Multiplied by 102"
+ },
+ "51": {
+ "displayName": "*104",
+ "headerName": "mul104",
+ "description": "Multiplied by 104"
+ },
+ "52": {
+ "displayName": "*106",
+ "headerName": "mul106",
+ "description": "Multiplied by 106"
+ },
+ "53": {
+ "displayName": "*108",
+ "headerName": "mul108",
+ "description": "Multiplied by 108"
+ },
+ "54": {
+ "displayName": "*110",
+ "headerName": "mul110",
+ "description": "Multiplied by 110"
+ },
+ "55": {
+ "displayName": "*112",
+ "headerName": "mul112",
+ "description": "Multiplied by 112"
+ },
+ "56": {
+ "displayName": "*114",
+ "headerName": "mul114",
+ "description": "Multiplied by 114"
+ },
+ "57": {
+ "displayName": "*116",
+ "headerName": "mul116",
+ "description": "Multiplied by 116"
+ },
+ "58": {
+ "displayName": "*118",
+ "headerName": "mul118",
+ "description": "Multiplied by 118"
+ },
+ "59": {
+ "displayName": "*120",
+ "headerName": "mul120",
+ "description": "Multiplied by 120"
+ },
+ "60": {
+ "displayName": "*122",
+ "headerName": "mul122",
+ "description": "Multiplied by 122"
+ },
+ "61": {
+ "displayName": "*124",
+ "headerName": "mul124",
+ "description": "Multiplied by 124"
+ },
+ "62": {
+ "displayName": "*126",
+ "headerName": "mul126",
+ "description": "Multiplied by 126"
+ },
+ "63": {
+ "displayName": "*128",
+ "headerName": "mul128",
+ "description": "Multiplied by 128"
+ }
+ }
+ }
+ }
+ },
+ "q": {
+ "description": "PLL Q output divider value",
+ "bitOffset": "10",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x3",
+ "enumerations": {
+ "pllq-enum": {
+ "description": "Reference Clock Q Divide Ratio Enumeration",
+ "values": {
+ "*": {
+ "displayName": "n/a",
+ "description": "Not supported"
+ },
+ "1": {
+ "displayName": "/2",
+ "headerName": "div2",
+ "description": "Divided by 2"
+ },
+ "2": {
+ "displayName": "/4",
+ "headerName": "div4",
+ "description": "Divided by 4"
+ },
+ "3": {
+ "displayName": "/8",
+ "headerName": "div8",
+ "description": "Divided by 8"
+ }
+ }
+ }
+ }
+ },
+ "sel": {
+ "description": "PLL select",
+ "bitOffset": "16",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "refsel": {
+ "description": "PLL reference select",
+ "bitOffset": "17",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x1"
+ },
+ "bypass": {
+ "description": "PLL bypass",
+ "bitOffset": "18",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x1"
+ },
+ "lock": {
+ "description": "PLL lock indicator",
+ "bitOffset": "31",
+ "bitWidth": "1",
+ "access": "r"
+ }
+ }
+ },
+ "plloutdiv": {
+ "description": "PLL Output Divider",
+ "addressOffset": "0x000C"
+ }
+ }
+ },
+ "otp": {
+ "description": "One-Time Programmable Memory (OTP) Peripheral",
+ "baseAddress": "0x10010000",
+ "size": "0x1000",
+ "registers": {
+ "lock": {
+ "description": "Programmed-I/O Lock Register",
+ "addressOffset": "0x0000"
+ },
+ "ck": {
+ "description": "Device Clock Signal Register",
+ "addressOffset": "0x0004"
+ },
+ "oe": {
+ "description": "Device Output-Enable Signal Register",
+ "addressOffset": "0x0008"
+ },
+ "sel": {
+ "description": "Device Chip-Select Signal Register",
+ "addressOffset": "0x000C"
+ },
+ "we": {
+ "description": "Device Write-Enable Signal Register",
+ "addressOffset": "0x0010"
+ },
+ "mr": {
+ "description": "Device Mode Register",
+ "addressOffset": "0x0014"
+ },
+ "mrr": {
+ "description": "Read-Voltage Regulator Control Register",
+ "addressOffset": "0x0018"
+ },
+ "mpp": {
+ "description": "Write-Voltage Charge Pump Control Register",
+ "addressOffset": "0x001C"
+ },
+ "vrren": {
+ "description": "Read-Voltage Enable Register",
+ "addressOffset": "0x0020"
+ },
+ "vppen": {
+ "description": "Write-Voltage Enable Register",
+ "addressOffset": "0x0024"
+ },
+ "a": {
+ "description": "Device Address Register",
+ "addressOffset": "0x0028"
+ },
+ "d": {
+ "description": "Device Data Input Register",
+ "addressOffset": "0x002C"
+ },
+ "q": {
+ "description": "Device Data Output Register",
+ "addressOffset": "0x0030"
+ },
+ "rsctrl": {
+ "description": "Read Sequencer Control Register",
+ "addressOffset": "0x0034",
+ "fields": {
+ "scale": {
+ "description": "OTP timescale",
+ "bitOffset": "0",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x1"
+ },
+ "tas": {
+ "description": "Address setup time",
+ "bitOffset": "3",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "trp": {
+ "description": "Read pulse time",
+ "bitOffset": "4",
+ "bitWidth": "1"
+ },
+ "tracc": {
+ "description": "Read access time",
+ "bitOffset": "5",
+ "bitWidth": "1"
+ }
+ }
+ }
+ }
+ },
+ "gpio": {
+ "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
+ "baseAddress": "0x10012000",
+ "size": "0x1000",
+ "registers": {
+ "value": {
+ "description": "Pin Value Register",
+ "addressOffset": "0x000",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Value Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "inputen": {
+ "description": "Pin Input Enable Register",
+ "addressOffset": "0x004",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Pin Input Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "outputen": {
+ "description": "Pin Output Enable Register",
+ "addressOffset": "0x008",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Pin Output Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "port": {
+ "description": "Output Port Value Register",
+ "addressOffset": "0x00C",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Output Port Value Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "pue": {
+ "description": "Internal Pull-up Enable Register",
+ "addressOffset": "0x010",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Internal Pull-up Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "ds": {
+ "description": "Pin Drive Strength Register",
+ "addressOffset": "0x014",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Pin Drive Strength Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "riseie": {
+ "description": "Rise Interrupt Enable Register",
+ "addressOffset": "0x018",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Rise Interrupt Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "riseip": {
+ "description": "Rise Interrupt Pending Register",
+ "addressOffset": "0x01C",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Rise Interrupt Pending Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "fallie": {
+ "description": "Fall Interrupt Enable Register",
+ "addressOffset": "0x020",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Fall Interrupt Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "fallip": {
+ "description": "Fall Interrupt Pending Register",
+ "addressOffset": "0x024",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Fall Interrupt Pending Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "highie": {
+ "description": "High Interrupt Enable Register",
+ "addressOffset": "0x028",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "High Interrupt Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "highip": {
+ "description": "High Interrupt Pending Register",
+ "addressOffset": "0x02C",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "High Interrupt Pending Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "lowie": {
+ "description": "Low Interrupt Enable Register",
+ "addressOffset": "0x030",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Low Interrupt Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "lowip": {
+ "description": "Low Interrupt Pending Register",
+ "addressOffset": "0x034",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Low Interrupt Pending Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "iofen": {
+ "description": "HW I/O Function Enable Register",
+ "addressOffset": "0x038",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "HW I/O Function Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "iofsel": {
+ "description": "HW I/O Function Select Register",
+ "addressOffset": "0x03C",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "HW I/O Function Select Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "outxor": {
+ "description": "Output XOR (invert) Register",
+ "addressOffset": "0x040",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Output XOR Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "gpio0": {
+ "description": "GPIO0 Interrupt",
+ "value": "8"
+ },
+ "gpio1": {
+ "description": "GPIO1 Interrupt",
+ "value": "9"
+ },
+ "gpio2": {
+ "description": "GPIO2 Interrupt",
+ "value": "10"
+ },
+ "gpio3": {
+ "description": "GPIO3 Interrupt",
+ "value": "11"
+ },
+ "gpio4": {
+ "description": "GPIO4 Interrupt",
+ "value": "12"
+ },
+ "gpio5": {
+ "description": "GPIO5 Interrupt",
+ "value": "13"
+ },
+ "gpio6": {
+ "description": "GPIO6 Interrupt",
+ "value": "14"
+ },
+ "gpio7": {
+ "description": "GPIO7 Interrupt",
+ "value": "15"
+ },
+ "gpio8": {
+ "description": "GPIO8 Interrupt",
+ "value": "16"
+ },
+ "gpio9": {
+ "description": "GPIO9 Interrupt",
+ "value": "17"
+ },
+ "gpio10": {
+ "description": "GPIO10 Interrupt",
+ "value": "18"
+ },
+ "gpio11": {
+ "description": "GPIO11 Interrupt",
+ "value": "19"
+ },
+ "gpio12": {
+ "description": "GPIO12 Interrupt",
+ "value": "20"
+ },
+ "gpio13": {
+ "description": "GPIO13 Interrupt",
+ "value": "21"
+ },
+ "gpio14": {
+ "description": "GPIO14 Interrupt",
+ "value": "22"
+ },
+ "gpio15": {
+ "description": "GPIO15 Interrupt",
+ "value": "23"
+ },
+ "gpio16": {
+ "description": "GPIO16 Interrupt",
+ "value": "24"
+ },
+ "gpio17": {
+ "description": "GPIO17 Interrupt",
+ "value": "25"
+ },
+ "gpio18": {
+ "description": "GPIO18 Interrupt",
+ "value": "26"
+ },
+ "gpio19": {
+ "description": "GPIO19 Interrupt",
+ "value": "27"
+ },
+ "gpio20": {
+ "description": "GPIO20 Interrupt",
+ "value": "28"
+ },
+ "gpio21": {
+ "description": "GPIO21 Interrupt",
+ "value": "29"
+ },
+ "gpio22": {
+ "description": "GPIO22 Interrupt",
+ "value": "30"
+ },
+ "gpio23": {
+ "description": "GPIO23 Interrupt",
+ "value": "31"
+ },
+ "gpio24": {
+ "description": "GPIO24 Interrupt",
+ "value": "32"
+ },
+ "gpio25": {
+ "description": "GPIO25 Interrupt",
+ "value": "33"
+ },
+ "gpio26": {
+ "description": "GPIO26 Interrupt",
+ "value": "34"
+ },
+ "gpio27": {
+ "description": "GPIO27 Interrupt",
+ "value": "35"
+ },
+ "gpio28": {
+ "description": "GPIO28 Interrupt",
+ "value": "36"
+ },
+ "gpio29": {
+ "description": "GPIO29 Interrupt",
+ "value": "37"
+ },
+ "gpio30": {
+ "description": "GPIO30 Interrupt",
+ "value": "38"
+ },
+ "gpio31": {
+ "description": "GPIO31 Interrupt",
+ "value": "39"
+ }
+ }
+ },
+ "uart0": {
+ "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
+ "baseAddress": "0x10013000",
+ "size": "0x1000",
+ "resetMask": "none",
+ "groupName": "uart",
+ "registers": {
+ "txdata": {
+ "description": "Transmit Data Register",
+ "addressOffset": "0x000",
+ "fields": {
+ "data": {
+ "description": "Transmit data",
+ "bitOffset": "0",
+ "bitWidth": "8"
+ },
+ "full": {
+ "description": "Transmit FIFO full",
+ "bitOffset": "31",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "rxdata": {
+ "description": "Receive Data Register",
+ "addressOffset": "0x004",
+ "resetMask": "none",
+ "fields": {
+ "data": {
+ "description": "Received data",
+ "bitOffset": "0",
+ "bitWidth": "8",
+ "access": "r"
+ },
+ "empty": {
+ "description": "Receive FIFO empty",
+ "bitOffset": "31",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "txctrl": {
+ "description": "Transmit Control Register ",
+ "addressOffset": "0x008",
+ "fields": {
+ "txen": {
+ "description": "Transmit enable",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "nstop": {
+ "description": "Number of stop bits",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "txcnt": {
+ "description": "Transmit watermark level",
+ "bitOffset": "16",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "rxctrl": {
+ "description": "Receive Control Register",
+ "addressOffset": "0x00C",
+ "fields": {
+ "rxen": {
+ "description": "Receive enable",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "rxcnt": {
+ "description": "Receive watermark level",
+ "bitOffset": "16",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "ie": {
+ "description": "Interrupt Enable Register",
+ "addressOffset": "0x010",
+ "fields": {
+ "txwm": {
+ "description": "Transmit watermark interrupt enable",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "rxwm": {
+ "description": "Receive watermark interrupt enable",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "ip": {
+ "description": "Interrupt Pending Register",
+ "addressOffset": "0x014",
+ "access": "r",
+ "fields": {
+ "txwm": {
+ "description": "Transmit watermark interrupt pending",
+ "bitOffset": "0",
+ "bitWidth": "1"
+ },
+ "rxwm": {
+ "description": "Receive watermark interrupt pending",
+ "bitOffset": "1",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "div": {
+ "description": "Baud Rate Divisor Register",
+ "addressOffset": "0x018",
+ "fields": {
+ "value": {
+ "description": "Baud rate divisor",
+ "bitOffset": "0",
+ "bitWidth": "16",
+ "resetMask": "all",
+ "resetValue": "0x0000FFFF"
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "uart0": {
+ "description": "UART0 Interrupt",
+ "value": "3"
+ }
+ }
+ },
+ "spi0": {
+ "description": "Serial Peripheral Interface (SPI) Peripheral",
+ "baseAddress": "0x10014000",
+ "size": "0x1000",
+ "resetMask": "none",
+ "groupName": "spi",
+ "registers": {
+ "sckdiv": {
+ "description": "Serial clock divisor Register",
+ "addressOffset": "0x000",
+ "fields": {
+ "scale": {
+ "description": "Divisor for serial clock",
+ "bitOffset": "0",
+ "bitWidth": "12",
+ "resetMask": "all",
+ "resetValue": "0x003"
+ }
+ }
+ },
+ "sckmode": {
+ "description": "Serial Clock Mode Register",
+ "addressOffset": "0x004",
+ "fields": {
+ "pha": {
+ "description": "Serial clock phase",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "pol": {
+ "description": "Serial clock polarity",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "csid": {
+ "description": "Chip Select ID Register",
+ "addressOffset": "0x010",
+ "resetMask": "all",
+ "resetValue": "0x00000000"
+ },
+ "csdef": {
+ "description": "Chip Select Default Register",
+ "addressOffset": "0x014",
+ "resetMask": "all",
+ "resetValue": "0x00000001"
+ },
+ "csmode": {
+ "description": "Chip Select Mode Register",
+ "addressOffset": "0x018",
+ "fields": {
+ "mode": {
+ "description": "Chip select mode",
+ "bitOffset": "0",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0",
+ "enumerations": {
+ "csmode-enum": {
+ "description": "Chip Select Modes Enumeration",
+ "values": {
+ "0": {
+ "displayName": "auto",
+ "description": "Assert/de-assert CS at the beginning/end of each frame"
+ },
+ "*": {
+ "displayName": "reserved"
+ },
+ "2": {
+ "displayName": "hold",
+ "description": "Keep CS continuously asserted after the initial frame"
+ },
+ "3": {
+ "displayName": "off",
+ "description": "Disable hardware control of the CS pin"
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "delay0": {
+ "description": "Delay Control 0 Register",
+ "addressOffset": "0x028",
+ "fields": {
+ "cssck": {
+ "description": "CS to SCK Delay",
+ "bitOffset": "0",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x01"
+ },
+ "sckcs": {
+ "description": "SCK to CS Delay",
+ "bitOffset": "16",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x01"
+ }
+ }
+ },
+ "delay1": {
+ "description": "Delay Control 1 Register",
+ "addressOffset": "0x02C",
+ "fields": {
+ "intercs": {
+ "description": "Minimum CS inactive time",
+ "bitOffset": "0",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x01"
+ },
+ "interxfr": {
+ "description": "Maximum interframe delay",
+ "bitOffset": "16",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x01"
+ }
+ }
+ },
+ "fmt": {
+ "description": "Frame Format Register",
+ "addressOffset": "0x040",
+ "fields": {
+ "proto": {
+ "description": "SPI Protocol",
+ "bitOffset": "0",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0",
+ "enumerations": {
+ "proto-enum": {
+ "description": "SPI Protocol Enumeration",
+ "values": {
+ "0": {
+ "displayName": "single",
+ "description": "DQ0 (MOSI), DQ1 (MISO)"
+ },
+ "1": {
+ "displayName": "dual",
+ "description": "DQ0, DQ1"
+ },
+ "2": {
+ "displayName": "quad",
+ "description": "DQ0, DQ1, DQ2, DQ3"
+ },
+ "*": {
+ "displayName": "reserved"
+ }
+ }
+ }
+ }
+ },
+ "endian": {
+ "description": "SPI endianness",
+ "bitOffset": "2",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0",
+ "enumerations": {
+ "endian-enum": {
+ "description": "SPI Endianness Enumeration",
+ "values": {
+ "0": {
+ "displayName": "msb",
+ "description": "Transmit most-significant bit (MSB) first"
+ },
+ "1": {
+ "displayName": "lsb",
+ "description": "Transmit least-significant bit (LSB) first"
+ }
+ }
+ }
+ }
+ },
+ "dir": {
+ "description": "SPI I/O Direction",
+ "bitOffset": "3",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x1",
+ "enumerations": {
+ "dir-enum": {
+ "description": "SPI I/O Direction Enumeration",
+ "values": {
+ "0": {
+ "displayName": "rx",
+ "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
+ },
+ "1": {
+ "displayName": "tx",
+ "description": "The receive FIFO is not populated."
+ }
+ }
+ }
+ }
+ },
+ "len": {
+ "description": "Number of bits per frame",
+ "bitOffset": "16",
+ "bitWidth": "4",
+ "resetMask": "all",
+ "resetValue": "0x8"
+ }
+ }
+ },
+ "txdata": {
+ "description": "Tx FIFO Data Register",
+ "addressOffset": "0x048",
+ "fields": {
+ "data": {
+ "description": "Transmit data",
+ "bitOffset": "0",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x00"
+ },
+ "full": {
+ "description": "FIFO full flag",
+ "bitOffset": "31",
+ "bitWidth": "1",
+ "access": "r"
+ }
+ }
+ },
+ "rxdata": {
+ "description": "Rx FIFO Data Register",
+ "addressOffset": "0x04C",
+ "resetMask": "none",
+ "access": "r",
+ "fields": {
+ "data": {
+ "description": "Received data",
+ "bitOffset": "0",
+ "bitWidth": "8"
+ },
+ "empty": {
+ "description": "FIFO empty flag",
+ "bitOffset": "31",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "txmark": {
+ "description": "Tx FIFO Watermark Register",
+ "addressOffset": "0x050",
+ "fields": {
+ "value": {
+ "description": "Transmit watermark",
+ "bitOffset": "0",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x1"
+ }
+ }
+ },
+ "rxmark": {
+ "description": "Rx FIFO Watermark Register",
+ "addressOffset": "0x054",
+ "fields": {
+ "value": {
+ "description": "Receive watermark",
+ "bitOffset": "0",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "fctrl": {
+ "description": "Flash Interface Control Register",
+ "addressOffset": "0x060",
+ "fields": {
+ "en": {
+ "description": "SPI Flash Mode Select",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x1"
+ }
+ }
+ },
+ "ffmt": {
+ "description": "Flash Instruction Format Register",
+ "addressOffset": "0x064",
+ "fields": {
+ "cmden": {
+ "description": "Enable sending of command",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x1"
+ },
+ "addrlen": {
+ "description": "Number of address bytes(0 to 4)",
+ "bitOffset": "1",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x3"
+ },
+ "padcnt": {
+ "description": "Number of dummy cycles",
+ "bitOffset": "4",
+ "bitWidth": "4",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "cmdproto": {
+ "description": "Protocol for transmitting command",
+ "bitOffset": "8",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "addrproto": {
+ "description": "Protocol for transmitting address and padding",
+ "bitOffset": "10",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "dataproto": {
+ "description": "Protocol for receiving data bytes",
+ "bitOffset": "12",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "cmdcode": {
+ "description": "Value of command byte",
+ "bitOffset": "16",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x03"
+ },
+ "padcode": {
+ "description": "First 8 bits to transmit during dummy cycles",
+ "bitOffset": "24",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "ie": {
+ "description": "Interrupt Enable Register",
+ "addressOffset": "0x070",
+ "fields": {
+ "txwm": {
+ "description": "Transmit watermark enable",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "access": "r",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "rxwm": {
+ "description": "Receive watermark enable",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "access": "r",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "ip": {
+ "description": "Interrupt Pending Register",
+ "addressOffset": "0x074",
+ "fields": {
+ "txwm": {
+ "description": "Transmit watermark pending",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "access": "r"
+ },
+ "rxwm": {
+ "description": "Receive watermark pending",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "access": "r"
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "spi0": {
+ "description": "SPI0 Interrupt",
+ "value": "5"
+ }
+ }
+ },
+ "pwm0": {
+ "description": "Pulse-Width Modulation (PWM) Peripheral",
+ "baseAddress": "0x10015000",
+ "size": "0x1000",
+ "resetMask": "none",
+ "registers": {
+ "cfg": {
+ "description": "Configuration Register",
+ "addressOffset": "0x000",
+ "fields": {
+ "scale": {
+ "description": "Counter scale",
+ "bitOffset": "0",
+ "bitWidth": "4"
+ },
+ "sticky": {
+ "description": "Sticky - disallow clearing pwmcmpXip bits",
+ "bitOffset": "8",
+ "bitWidth": "1"
+ },
+ "zerocmp": {
+ "description": "Zero - counter resets to zero after match",
+ "bitOffset": "9",
+ "bitWidth": "1"
+ },
+ "deglitch": {
+ "description": "Deglitch - latch pwmcmpXip within same cycle",
+ "bitOffset": "10",
+ "bitWidth": "1"
+ },
+ "enalways": {
+ "description": "Enable always - run continuously",
+ "bitOffset": "12",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "enoneshot": {
+ "description": "enable one shot - run one cycle",
+ "bitOffset": "13",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "cmp0center": {
+ "description": "PWM0 Compare Center",
+ "bitOffset": "16",
+ "bitWidth": "1"
+ },
+ "cmp1center": {
+ "description": "PWM1 Compare Center",
+ "bitOffset": "17",
+ "bitWidth": "1"
+ },
+ "cmp2center": {
+ "description": "PWM2 Compare Center",
+ "bitOffset": "18",
+ "bitWidth": "1"
+ },
+ "cmp3center": {
+ "description": "PWM3 Compare Center",
+ "bitOffset": "19",
+ "bitWidth": "1"
+ },
+ "cmp0gang": {
+ "description": "PWM0/PWM1 Compare Gang",
+ "bitOffset": "24",
+ "bitWidth": "1"
+ },
+ "cmp1gang": {
+ "description": "PWM1/PWM2 Compare Gang",
+ "bitOffset": "25",
+ "bitWidth": "1"
+ },
+ "cmp2gang": {
+ "description": "PWM2/PWM3 Compare Gang",
+ "bitOffset": "26",
+ "bitWidth": "1"
+ },
+ "cmp3gang": {
+ "description": "PWM3/PWM0 Compare Gang",
+ "bitOffset": "27",
+ "bitWidth": "1"
+ },
+ "cmp0ip": {
+ "description": "PWM0 Interrupt Pending",
+ "bitOffset": "28",
+ "bitWidth": "1"
+ },
+ "cmp1ip": {
+ "description": "PWM1 Interrupt Pending",
+ "bitOffset": "29",
+ "bitWidth": "1"
+ },
+ "cmp2ip": {
+ "description": "PWM2 Interrupt Pending",
+ "bitOffset": "30",
+ "bitWidth": "1"
+ },
+ "cmp3ip": {
+ "description": "PWM3 Interrupt Pending",
+ "bitOffset": "31",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "count": {
+ "description": "Configuration Register",
+ "addressOffset": "0x008"
+ },
+ "scale": {
+ "description": "Scale Register",
+ "addressOffset": "0x010",
+ "fields": {
+ "value": {
+ "description": "Compare value",
+ "bitOffset": "0",
+ "bitWidth": "8"
+ }
+ }
+ },
+ "cmp": {
+ "arraySize": "4",
+ "description": "Compare Registers",
+ "addressOffset": "0x020",
+ "fields": {
+ "value": {
+ "description": "Compare value",
+ "bitOffset": "0",
+ "bitWidth": "8"
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "pwm0cmp0": {
+ "description": "PWM0 Compare 0 Interrupt",
+ "value": "40"
+ },
+ "pwm0cmp1": {
+ "description": "PWM0 Compare 1 Interrupt",
+ "value": "41"
+ },
+ "pwm0cmp2": {
+ "description": "PWM0 Compare 2 Interrupt",
+ "value": "42"
+ },
+ "pwm0cmp3": {
+ "description": "PWM0 Compare 3 Interrupt",
+ "value": "43"
+ }
+ }
+ },
+ "uart1": {
+ "baseAddress": "0x10023000",
+ "derivedFrom": "uart0",
+ "groupName": "uart",
+ "interrupts": {
+ "uart1": {
+ "description": "UART1 Interrupt",
+ "value": "4"
+ }
+ }
+ },
+ "spi1": {
+ "baseAddress": "0x10024000",
+ "derivedFrom": "spi0",
+ "groupName": "spi",
+ "interrupts": {
+ "spi1": {
+ "description": "SPI1 Interrupt",
+ "value": "6"
+ }
+ }
+ },
+ "pwm1": {
+ "description": "Pulse-Width Modulation (PWM) Peripheral",
+ "baseAddress": "0x10025000",
+ "groupName": "pwm",
+ "size": "0x1000",
+ "resetMask": "none",
+ "groupName": "pwm",
+ "registers": {
+ "cfg": {
+ "description": "Configuration Register",
+ "addressOffset": "0x000",
+ "fields": {
+ "scale": {
+ "description": "Counter scale",
+ "bitOffset": "0",
+ "bitWidth": "4"
+ },
+ "sticky": {
+ "description": "Sticky - disallow clearing pwmcmpXip bits",
+ "bitOffset": "8",
+ "bitWidth": "1"
+ },
+ "zerocmp": {
+ "description": "Zero - counter resets to zero after match",
+ "bitOffset": "9",
+ "bitWidth": "1"
+ },
+ "deglitch": {
+ "description": "Deglitch - latch pwmcmpXip within same cycle",
+ "bitOffset": "10",
+ "bitWidth": "1"
+ },
+ "enalways": {
+ "description": "Enable always - run continuously",
+ "bitOffset": "12",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "enoneshot": {
+ "description": "enable one shot - run one cycle",
+ "bitOffset": "13",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "cmp0center": {
+ "description": "PWM0 Compare Center",
+ "bitOffset": "16",
+ "bitWidth": "1"
+ },
+ "cmp1center": {
+ "description": "PWM1 Compare Center",
+ "bitOffset": "17",
+ "bitWidth": "1"
+ },
+ "cmp2center": {
+ "description": "PWM2 Compare Center",
+ "bitOffset": "18",
+ "bitWidth": "1"
+ },
+ "cmp3center": {
+ "description": "PWM3 Compare Center",
+ "bitOffset": "19",
+ "bitWidth": "1"
+ },
+ "cmp0gang": {
+ "description": "PWM0/PWM1 Compare Gang",
+ "bitOffset": "24",
+ "bitWidth": "1"
+ },
+ "cmp1gang": {
+ "description": "PWM1/PWM2 Compare Gang",
+ "bitOffset": "25",
+ "bitWidth": "1"
+ },
+ "cmp2gang": {
+ "description": "PWM2/PWM3 Compare Gang",
+ "bitOffset": "26",
+ "bitWidth": "1"
+ },
+ "cmp3gang": {
+ "description": "PWM3/PWM0 Compare Gang",
+ "bitOffset": "27",
+ "bitWidth": "1"
+ },
+ "cmp0ip": {
+ "description": "PWM0 Interrupt Pending",
+ "bitOffset": "28",
+ "bitWidth": "1"
+ },
+ "cmp1ip": {
+ "description": "PWM1 Interrupt Pending",
+ "bitOffset": "29",
+ "bitWidth": "1"
+ },
+ "cmp2ip": {
+ "description": "PWM2 Interrupt Pending",
+ "bitOffset": "30",
+ "bitWidth": "1"
+ },
+ "cmp3ip": {
+ "description": "PWM3 Interrupt Pending",
+ "bitOffset": "31",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "count": {
+ "description": "Configuration Register",
+ "addressOffset": "0x008"
+ },
+ "scale": {
+ "description": "Scale Register",
+ "addressOffset": "0x010",
+ "fields": {
+ "value": {
+ "description": "Compare value",
+ "bitOffset": "0",
+ "bitWidth": "16"
+ }
+ }
+ },
+ "cmp": {
+ "arraySize": "4",
+ "description": "Compare Registers",
+ "addressOffset": "0x020",
+ "fields": {
+ "value": {
+ "description": "Compare value",
+ "bitOffset": "0",
+ "bitWidth": "16"
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "pwm1cmp0": {
+ "description": "PWM1 Compare 0 Interrupt",
+ "value": "44"
+ },
+ "pwm1cmp1": {
+ "description": "PWM1 Compare 1 Interrupt",
+ "value": "45"
+ },
+ "pwm1cmp2": {
+ "description": "PWM1 Compare 2 Interrupt",
+ "value": "46"
+ },
+ "pwm1cmp3": {
+ "description": "PWM1 Compare 3 Interrupt",
+ "value": "47"
+ }
+ }
+ },
+ "spi2": {
+ "baseAddress": "0x10034000",
+ "derivedFrom": "spi0",
+ "groupName": "spi",
+ "interrupts": {
+ "spi2": {
+ "description": "SPI2 Interrupt",
+ "value": "7"
+ }
+ }
+ },
+ "pwm2": {
+ "baseAddress": "0x10035000",
+ "derivedFrom": "pwm1",
+ "groupName": "pwm",
+ "interrupts": {
+ "pwm2cmp0": {
+ "description": "PWM2 Compare 0 Interrupt",
+ "value": "48"
+ },
+ "pwm2cmp1": {
+ "description": "PWM2 Compare 1 Interrupt",
+ "value": "49"
+ },
+ "pwm2cmp2": {
+ "description": "PWM2 Compare 2 Interrupt",
+ "value": "50"
+ },
+ "pwm2cmp3": {
+ "description": "PWM2 Compare 3 Interrupt",
+ "value": "51"
+ }
+ }
+ }
+ }
+ }
+ }
+}
\ No newline at end of file diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/LICENSE(Freedom-e-SDK) b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/LICENSE(Freedom-e-SDK) new file mode 100644 index 000000000..0b0b6c8fc --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/LICENSE(Freedom-e-SDK) @@ -0,0 +1,206 @@ + +This software, except as otherwise noted in subrepositories, +is licensed under the Apache 2 license, quoted below. + + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright 2016 SiFive, Inc. + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/env/encoding.h b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/env/encoding.h new file mode 100644 index 000000000..417e75169 --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/env/encoding.h @@ -0,0 +1,1313 @@ +// See LICENSE for license details.
+
+#ifndef RISCV_CSR_ENCODING_H
+#define RISCV_CSR_ENCODING_H
+
+#define MSTATUS_UIE 0x00000001
+#define MSTATUS_SIE 0x00000002
+#define MSTATUS_HIE 0x00000004
+#define MSTATUS_MIE 0x00000008
+#define MSTATUS_UPIE 0x00000010
+#define MSTATUS_SPIE 0x00000020
+#define MSTATUS_HPIE 0x00000040
+#define MSTATUS_MPIE 0x00000080
+#define MSTATUS_SPP 0x00000100
+#define MSTATUS_HPP 0x00000600
+#define MSTATUS_MPP 0x00001800
+#define MSTATUS_FS 0x00006000
+#define MSTATUS_XS 0x00018000
+#define MSTATUS_MPRV 0x00020000
+#define MSTATUS_PUM 0x00040000
+#define MSTATUS_MXR 0x00080000
+#define MSTATUS_VM 0x1F000000
+#define MSTATUS32_SD 0x80000000
+#define MSTATUS64_SD 0x8000000000000000
+
+#define SSTATUS_UIE 0x00000001
+#define SSTATUS_SIE 0x00000002
+#define SSTATUS_UPIE 0x00000010
+#define SSTATUS_SPIE 0x00000020
+#define SSTATUS_SPP 0x00000100
+#define SSTATUS_FS 0x00006000
+#define SSTATUS_XS 0x00018000
+#define SSTATUS_PUM 0x00040000
+#define SSTATUS32_SD 0x80000000
+#define SSTATUS64_SD 0x8000000000000000
+
+#define DCSR_XDEBUGVER (3U<<30)
+#define DCSR_NDRESET (1<<29)
+#define DCSR_FULLRESET (1<<28)
+#define DCSR_EBREAKM (1<<15)
+#define DCSR_EBREAKH (1<<14)
+#define DCSR_EBREAKS (1<<13)
+#define DCSR_EBREAKU (1<<12)
+#define DCSR_STOPCYCLE (1<<10)
+#define DCSR_STOPTIME (1<<9)
+#define DCSR_CAUSE (7<<6)
+#define DCSR_DEBUGINT (1<<5)
+#define DCSR_HALT (1<<3)
+#define DCSR_STEP (1<<2)
+#define DCSR_PRV (3<<0)
+
+#define DCSR_CAUSE_NONE 0
+#define DCSR_CAUSE_SWBP 1
+#define DCSR_CAUSE_HWBP 2
+#define DCSR_CAUSE_DEBUGINT 3
+#define DCSR_CAUSE_STEP 4
+#define DCSR_CAUSE_HALT 5
+
+#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4))
+#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5))
+#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))
+
+#define MCONTROL_SELECT (1<<19)
+#define MCONTROL_TIMING (1<<18)
+#define MCONTROL_ACTION (0x3f<<12)
+#define MCONTROL_CHAIN (1<<11)
+#define MCONTROL_MATCH (0xf<<7)
+#define MCONTROL_M (1<<6)
+#define MCONTROL_H (1<<5)
+#define MCONTROL_S (1<<4)
+#define MCONTROL_U (1<<3)
+#define MCONTROL_EXECUTE (1<<2)
+#define MCONTROL_STORE (1<<1)
+#define MCONTROL_LOAD (1<<0)
+
+#define MCONTROL_TYPE_NONE 0
+#define MCONTROL_TYPE_MATCH 2
+
+#define MCONTROL_ACTION_DEBUG_EXCEPTION 0
+#define MCONTROL_ACTION_DEBUG_MODE 1
+#define MCONTROL_ACTION_TRACE_START 2
+#define MCONTROL_ACTION_TRACE_STOP 3
+#define MCONTROL_ACTION_TRACE_EMIT 4
+
+#define MCONTROL_MATCH_EQUAL 0
+#define MCONTROL_MATCH_NAPOT 1
+#define MCONTROL_MATCH_GE 2
+#define MCONTROL_MATCH_LT 3
+#define MCONTROL_MATCH_MASK_LOW 4
+#define MCONTROL_MATCH_MASK_HIGH 5
+
+#define MIP_SSIP (1 << IRQ_S_SOFT)
+#define MIP_HSIP (1 << IRQ_H_SOFT)
+#define MIP_MSIP (1 << IRQ_M_SOFT)
+#define MIP_STIP (1 << IRQ_S_TIMER)
+#define MIP_HTIP (1 << IRQ_H_TIMER)
+#define MIP_MTIP (1 << IRQ_M_TIMER)
+#define MIP_SEIP (1 << IRQ_S_EXT)
+#define MIP_HEIP (1 << IRQ_H_EXT)
+#define MIP_MEIP (1 << IRQ_M_EXT)
+
+#define SIP_SSIP MIP_SSIP
+#define SIP_STIP MIP_STIP
+
+#define PRV_U 0
+#define PRV_S 1
+#define PRV_H 2
+#define PRV_M 3
+
+#define VM_MBARE 0
+#define VM_MBB 1
+#define VM_MBBID 2
+#define VM_SV32 8
+#define VM_SV39 9
+#define VM_SV48 10
+
+#define IRQ_S_SOFT 1
+#define IRQ_H_SOFT 2
+#define IRQ_M_SOFT 3
+#define IRQ_S_TIMER 5
+#define IRQ_H_TIMER 6
+#define IRQ_M_TIMER 7
+#define IRQ_S_EXT 9
+#define IRQ_H_EXT 10
+#define IRQ_M_EXT 11
+#define IRQ_COP 12
+#define IRQ_HOST 13
+
+#define DEFAULT_RSTVEC 0x00001000
+#define DEFAULT_NMIVEC 0x00001004
+#define DEFAULT_MTVEC 0x00001010
+#define CONFIG_STRING_ADDR 0x0000100C
+#define EXT_IO_BASE 0x40000000
+#define DRAM_BASE 0x80000000
+
+// page table entry (PTE) fields
+#define PTE_V 0x001 // Valid
+#define PTE_R 0x002 // Read
+#define PTE_W 0x004 // Write
+#define PTE_X 0x008 // Execute
+#define PTE_U 0x010 // User
+#define PTE_G 0x020 // Global
+#define PTE_A 0x040 // Accessed
+#define PTE_D 0x080 // Dirty
+#define PTE_SOFT 0x300 // Reserved for Software
+
+#define PTE_PPN_SHIFT 10
+
+#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
+
+#ifdef __riscv
+
+#ifdef __riscv64
+# define MSTATUS_SD MSTATUS64_SD
+# define SSTATUS_SD SSTATUS64_SD
+# define RISCV_PGLEVEL_BITS 9
+#else
+# define MSTATUS_SD MSTATUS32_SD
+# define SSTATUS_SD SSTATUS32_SD
+# define RISCV_PGLEVEL_BITS 10
+#endif
+#define RISCV_PGSHIFT 12
+#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
+
+#ifndef __ASSEMBLER__
+
+#ifdef __GNUC__
+
+#define read_csr(reg) ({ unsigned long __tmp; \
+ asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
+ __tmp; })
+
+#define write_csr(reg, val) ({ \
+ if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+ asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
+ else \
+ asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
+
+#define swap_csr(reg, val) ({ unsigned long __tmp; \
+ if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+ asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
+ else \
+ asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
+ __tmp; })
+
+#define set_csr(reg, bit) ({ unsigned long __tmp; \
+ if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
+ else \
+ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
+ __tmp; })
+
+#define clear_csr(reg, bit) ({ unsigned long __tmp; \
+ if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+ asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
+ else \
+ asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
+ __tmp; })
+
+#define rdtime() read_csr(time)
+#define rdcycle() read_csr(cycle)
+#define rdinstret() read_csr(instret)
+
+#endif
+
+#endif
+
+#endif
+
+#endif
+/* Automatically generated by parse-opcodes */
+#ifndef RISCV_ENCODING_H
+#define RISCV_ENCODING_H
+#define MATCH_BEQ 0x63
+#define MASK_BEQ 0x707f
+#define MATCH_BNE 0x1063
+#define MASK_BNE 0x707f
+#define MATCH_BLT 0x4063
+#define MASK_BLT 0x707f
+#define MATCH_BGE 0x5063
+#define MASK_BGE 0x707f
+#define MATCH_BLTU 0x6063
+#define MASK_BLTU 0x707f
+#define MATCH_BGEU 0x7063
+#define MASK_BGEU 0x707f
+#define MATCH_JALR 0x67
+#define MASK_JALR 0x707f
+#define MATCH_JAL 0x6f
+#define MASK_JAL 0x7f
+#define MATCH_LUI 0x37
+#define MASK_LUI 0x7f
+#define MATCH_AUIPC 0x17
+#define MASK_AUIPC 0x7f
+#define MATCH_ADDI 0x13
+#define MASK_ADDI 0x707f
+#define MATCH_SLLI 0x1013
+#define MASK_SLLI 0xfc00707f
+#define MATCH_SLTI 0x2013
+#define MASK_SLTI 0x707f
+#define MATCH_SLTIU 0x3013
+#define MASK_SLTIU 0x707f
+#define MATCH_XORI 0x4013
+#define MASK_XORI 0x707f
+#define MATCH_SRLI 0x5013
+#define MASK_SRLI 0xfc00707f
+#define MATCH_SRAI 0x40005013
+#define MASK_SRAI 0xfc00707f
+#define MATCH_ORI 0x6013
+#define MASK_ORI 0x707f
+#define MATCH_ANDI 0x7013
+#define MASK_ANDI 0x707f
+#define MATCH_ADD 0x33
+#define MASK_ADD 0xfe00707f
+#define MATCH_SUB 0x40000033
+#define MASK_SUB 0xfe00707f
+#define MATCH_SLL 0x1033
+#define MASK_SLL 0xfe00707f
+#define MATCH_SLT 0x2033
+#define MASK_SLT 0xfe00707f
+#define MATCH_SLTU 0x3033
+#define MASK_SLTU 0xfe00707f
+#define MATCH_XOR 0x4033
+#define MASK_XOR 0xfe00707f
+#define MATCH_SRL 0x5033
+#define MASK_SRL 0xfe00707f
+#define MATCH_SRA 0x40005033
+#define MASK_SRA 0xfe00707f
+#define MATCH_OR 0x6033
+#define MASK_OR 0xfe00707f
+#define MATCH_AND 0x7033
+#define MASK_AND 0xfe00707f
+#define MATCH_ADDIW 0x1b
+#define MASK_ADDIW 0x707f
+#define MATCH_SLLIW 0x101b
+#define MASK_SLLIW 0xfe00707f
+#define MATCH_SRLIW 0x501b
+#define MASK_SRLIW 0xfe00707f
+#define MATCH_SRAIW 0x4000501b
+#define MASK_SRAIW 0xfe00707f
+#define MATCH_ADDW 0x3b
+#define MASK_ADDW 0xfe00707f
+#define MATCH_SUBW 0x4000003b
+#define MASK_SUBW 0xfe00707f
+#define MATCH_SLLW 0x103b
+#define MASK_SLLW 0xfe00707f
+#define MATCH_SRLW 0x503b
+#define MASK_SRLW 0xfe00707f
+#define MATCH_SRAW 0x4000503b
+#define MASK_SRAW 0xfe00707f
+#define MATCH_LB 0x3
+#define MASK_LB 0x707f
+#define MATCH_LH 0x1003
+#define MASK_LH 0x707f
+#define MATCH_LW 0x2003
+#define MASK_LW 0x707f
+#define MATCH_LD 0x3003
+#define MASK_LD 0x707f
+#define MATCH_LBU 0x4003
+#define MASK_LBU 0x707f
+#define MATCH_LHU 0x5003
+#define MASK_LHU 0x707f
+#define MATCH_LWU 0x6003
+#define MASK_LWU 0x707f
+#define MATCH_SB 0x23
+#define MASK_SB 0x707f
+#define MATCH_SH 0x1023
+#define MASK_SH 0x707f
+#define MATCH_SW 0x2023
+#define MASK_SW 0x707f
+#define MATCH_SD 0x3023
+#define MASK_SD 0x707f
+#define MATCH_FENCE 0xf
+#define MASK_FENCE 0x707f
+#define MATCH_FENCE_I 0x100f
+#define MASK_FENCE_I 0x707f
+#define MATCH_MUL 0x2000033
+#define MASK_MUL 0xfe00707f
+#define MATCH_MULH 0x2001033
+#define MASK_MULH 0xfe00707f
+#define MATCH_MULHSU 0x2002033
+#define MASK_MULHSU 0xfe00707f
+#define MATCH_MULHU 0x2003033
+#define MASK_MULHU 0xfe00707f
+#define MATCH_DIV 0x2004033
+#define MASK_DIV 0xfe00707f
+#define MATCH_DIVU 0x2005033
+#define MASK_DIVU 0xfe00707f
+#define MATCH_REM 0x2006033
+#define MASK_REM 0xfe00707f
+#define MATCH_REMU 0x2007033
+#define MASK_REMU 0xfe00707f
+#define MATCH_MULW 0x200003b
+#define MASK_MULW 0xfe00707f
+#define MATCH_DIVW 0x200403b
+#define MASK_DIVW 0xfe00707f
+#define MATCH_DIVUW 0x200503b
+#define MASK_DIVUW 0xfe00707f
+#define MATCH_REMW 0x200603b
+#define MASK_REMW 0xfe00707f
+#define MATCH_REMUW 0x200703b
+#define MASK_REMUW 0xfe00707f
+#define MATCH_AMOADD_W 0x202f
+#define MASK_AMOADD_W 0xf800707f
+#define MATCH_AMOXOR_W 0x2000202f
+#define MASK_AMOXOR_W 0xf800707f
+#define MATCH_AMOOR_W 0x4000202f
+#define MASK_AMOOR_W 0xf800707f
+#define MATCH_AMOAND_W 0x6000202f
+#define MASK_AMOAND_W 0xf800707f
+#define MATCH_AMOMIN_W 0x8000202f
+#define MASK_AMOMIN_W 0xf800707f
+#define MATCH_AMOMAX_W 0xa000202f
+#define MASK_AMOMAX_W 0xf800707f
+#define MATCH_AMOMINU_W 0xc000202f
+#define MASK_AMOMINU_W 0xf800707f
+#define MATCH_AMOMAXU_W 0xe000202f
+#define MASK_AMOMAXU_W 0xf800707f
+#define MATCH_AMOSWAP_W 0x800202f
+#define MASK_AMOSWAP_W 0xf800707f
+#define MATCH_LR_W 0x1000202f
+#define MASK_LR_W 0xf9f0707f
+#define MATCH_SC_W 0x1800202f
+#define MASK_SC_W 0xf800707f
+#define MATCH_AMOADD_D 0x302f
+#define MASK_AMOADD_D 0xf800707f
+#define MATCH_AMOXOR_D 0x2000302f
+#define MASK_AMOXOR_D 0xf800707f
+#define MATCH_AMOOR_D 0x4000302f
+#define MASK_AMOOR_D 0xf800707f
+#define MATCH_AMOAND_D 0x6000302f
+#define MASK_AMOAND_D 0xf800707f
+#define MATCH_AMOMIN_D 0x8000302f
+#define MASK_AMOMIN_D 0xf800707f
+#define MATCH_AMOMAX_D 0xa000302f
+#define MASK_AMOMAX_D 0xf800707f
+#define MATCH_AMOMINU_D 0xc000302f
+#define MASK_AMOMINU_D 0xf800707f
+#define MATCH_AMOMAXU_D 0xe000302f
+#define MASK_AMOMAXU_D 0xf800707f
+#define MATCH_AMOSWAP_D 0x800302f
+#define MASK_AMOSWAP_D 0xf800707f
+#define MATCH_LR_D 0x1000302f
+#define MASK_LR_D 0xf9f0707f
+#define MATCH_SC_D 0x1800302f
+#define MASK_SC_D 0xf800707f
+#define MATCH_ECALL 0x73
+#define MASK_ECALL 0xffffffff
+#define MATCH_EBREAK 0x100073
+#define MASK_EBREAK 0xffffffff
+#define MATCH_URET 0x200073
+#define MASK_URET 0xffffffff
+#define MATCH_SRET 0x10200073
+#define MASK_SRET 0xffffffff
+#define MATCH_HRET 0x20200073
+#define MASK_HRET 0xffffffff
+#define MATCH_MRET 0x30200073
+#define MASK_MRET 0xffffffff
+#define MATCH_DRET 0x7b200073
+#define MASK_DRET 0xffffffff
+#define MATCH_SFENCE_VM 0x10400073
+#define MASK_SFENCE_VM 0xfff07fff
+#define MATCH_WFI 0x10500073
+#define MASK_WFI 0xffffffff
+#define MATCH_CSRRW 0x1073
+#define MASK_CSRRW 0x707f
+#define MATCH_CSRRS 0x2073
+#define MASK_CSRRS 0x707f
+#define MATCH_CSRRC 0x3073
+#define MASK_CSRRC 0x707f
+#define MATCH_CSRRWI 0x5073
+#define MASK_CSRRWI 0x707f
+#define MATCH_CSRRSI 0x6073
+#define MASK_CSRRSI 0x707f
+#define MATCH_CSRRCI 0x7073
+#define MASK_CSRRCI 0x707f
+#define MATCH_FADD_S 0x53
+#define MASK_FADD_S 0xfe00007f
+#define MATCH_FSUB_S 0x8000053
+#define MASK_FSUB_S 0xfe00007f
+#define MATCH_FMUL_S 0x10000053
+#define MASK_FMUL_S 0xfe00007f
+#define MATCH_FDIV_S 0x18000053
+#define MASK_FDIV_S 0xfe00007f
+#define MATCH_FSGNJ_S 0x20000053
+#define MASK_FSGNJ_S 0xfe00707f
+#define MATCH_FSGNJN_S 0x20001053
+#define MASK_FSGNJN_S 0xfe00707f
+#define MATCH_FSGNJX_S 0x20002053
+#define MASK_FSGNJX_S 0xfe00707f
+#define MATCH_FMIN_S 0x28000053
+#define MASK_FMIN_S 0xfe00707f
+#define MATCH_FMAX_S 0x28001053
+#define MASK_FMAX_S 0xfe00707f
+#define MATCH_FSQRT_S 0x58000053
+#define MASK_FSQRT_S 0xfff0007f
+#define MATCH_FADD_D 0x2000053
+#define MASK_FADD_D 0xfe00007f
+#define MATCH_FSUB_D 0xa000053
+#define MASK_FSUB_D 0xfe00007f
+#define MATCH_FMUL_D 0x12000053
+#define MASK_FMUL_D 0xfe00007f
+#define MATCH_FDIV_D 0x1a000053
+#define MASK_FDIV_D 0xfe00007f
+#define MATCH_FSGNJ_D 0x22000053
+#define MASK_FSGNJ_D 0xfe00707f
+#define MATCH_FSGNJN_D 0x22001053
+#define MASK_FSGNJN_D 0xfe00707f
+#define MATCH_FSGNJX_D 0x22002053
+#define MASK_FSGNJX_D 0xfe00707f
+#define MATCH_FMIN_D 0x2a000053
+#define MASK_FMIN_D 0xfe00707f
+#define MATCH_FMAX_D 0x2a001053
+#define MASK_FMAX_D 0xfe00707f
+#define MATCH_FCVT_S_D 0x40100053
+#define MASK_FCVT_S_D 0xfff0007f
+#define MATCH_FCVT_D_S 0x42000053
+#define MASK_FCVT_D_S 0xfff0007f
+#define MATCH_FSQRT_D 0x5a000053
+#define MASK_FSQRT_D 0xfff0007f
+#define MATCH_FLE_S 0xa0000053
+#define MASK_FLE_S 0xfe00707f
+#define MATCH_FLT_S 0xa0001053
+#define MASK_FLT_S 0xfe00707f
+#define MATCH_FEQ_S 0xa0002053
+#define MASK_FEQ_S 0xfe00707f
+#define MATCH_FLE_D 0xa2000053
+#define MASK_FLE_D 0xfe00707f
+#define MATCH_FLT_D 0xa2001053
+#define MASK_FLT_D 0xfe00707f
+#define MATCH_FEQ_D 0xa2002053
+#define MASK_FEQ_D 0xfe00707f
+#define MATCH_FCVT_W_S 0xc0000053
+#define MASK_FCVT_W_S 0xfff0007f
+#define MATCH_FCVT_WU_S 0xc0100053
+#define MASK_FCVT_WU_S 0xfff0007f
+#define MATCH_FCVT_L_S 0xc0200053
+#define MASK_FCVT_L_S 0xfff0007f
+#define MATCH_FCVT_LU_S 0xc0300053
+#define MASK_FCVT_LU_S 0xfff0007f
+#define MATCH_FMV_X_S 0xe0000053
+#define MASK_FMV_X_S 0xfff0707f
+#define MATCH_FCLASS_S 0xe0001053
+#define MASK_FCLASS_S 0xfff0707f
+#define MATCH_FCVT_W_D 0xc2000053
+#define MASK_FCVT_W_D 0xfff0007f
+#define MATCH_FCVT_WU_D 0xc2100053
+#define MASK_FCVT_WU_D 0xfff0007f
+#define MATCH_FCVT_L_D 0xc2200053
+#define MASK_FCVT_L_D 0xfff0007f
+#define MATCH_FCVT_LU_D 0xc2300053
+#define MASK_FCVT_LU_D 0xfff0007f
+#define MATCH_FMV_X_D 0xe2000053
+#define MASK_FMV_X_D 0xfff0707f
+#define MATCH_FCLASS_D 0xe2001053
+#define MASK_FCLASS_D 0xfff0707f
+#define MATCH_FCVT_S_W 0xd0000053
+#define MASK_FCVT_S_W 0xfff0007f
+#define MATCH_FCVT_S_WU 0xd0100053
+#define MASK_FCVT_S_WU 0xfff0007f
+#define MATCH_FCVT_S_L 0xd0200053
+#define MASK_FCVT_S_L 0xfff0007f
+#define MATCH_FCVT_S_LU 0xd0300053
+#define MASK_FCVT_S_LU 0xfff0007f
+#define MATCH_FMV_S_X 0xf0000053
+#define MASK_FMV_S_X 0xfff0707f
+#define MATCH_FCVT_D_W 0xd2000053
+#define MASK_FCVT_D_W 0xfff0007f
+#define MATCH_FCVT_D_WU 0xd2100053
+#define MASK_FCVT_D_WU 0xfff0007f
+#define MATCH_FCVT_D_L 0xd2200053
+#define MASK_FCVT_D_L 0xfff0007f
+#define MATCH_FCVT_D_LU 0xd2300053
+#define MASK_FCVT_D_LU 0xfff0007f
+#define MATCH_FMV_D_X 0xf2000053
+#define MASK_FMV_D_X 0xfff0707f
+#define MATCH_FLW 0x2007
+#define MASK_FLW 0x707f
+#define MATCH_FLD 0x3007
+#define MASK_FLD 0x707f
+#define MATCH_FSW 0x2027
+#define MASK_FSW 0x707f
+#define MATCH_FSD 0x3027
+#define MASK_FSD 0x707f
+#define MATCH_FMADD_S 0x43
+#define MASK_FMADD_S 0x600007f
+#define MATCH_FMSUB_S 0x47
+#define MASK_FMSUB_S 0x600007f
+#define MATCH_FNMSUB_S 0x4b
+#define MASK_FNMSUB_S 0x600007f
+#define MATCH_FNMADD_S 0x4f
+#define MASK_FNMADD_S 0x600007f
+#define MATCH_FMADD_D 0x2000043
+#define MASK_FMADD_D 0x600007f
+#define MATCH_FMSUB_D 0x2000047
+#define MASK_FMSUB_D 0x600007f
+#define MATCH_FNMSUB_D 0x200004b
+#define MASK_FNMSUB_D 0x600007f
+#define MATCH_FNMADD_D 0x200004f
+#define MASK_FNMADD_D 0x600007f
+#define MATCH_C_NOP 0x1
+#define MASK_C_NOP 0xffff
+#define MATCH_C_ADDI16SP 0x6101
+#define MASK_C_ADDI16SP 0xef83
+#define MATCH_C_JR 0x8002
+#define MASK_C_JR 0xf07f
+#define MATCH_C_JALR 0x9002
+#define MASK_C_JALR 0xf07f
+#define MATCH_C_EBREAK 0x9002
+#define MASK_C_EBREAK 0xffff
+#define MATCH_C_LD 0x6000
+#define MASK_C_LD 0xe003
+#define MATCH_C_SD 0xe000
+#define MASK_C_SD 0xe003
+#define MATCH_C_ADDIW 0x2001
+#define MASK_C_ADDIW 0xe003
+#define MATCH_C_LDSP 0x6002
+#define MASK_C_LDSP 0xe003
+#define MATCH_C_SDSP 0xe002
+#define MASK_C_SDSP 0xe003
+#define MATCH_C_ADDI4SPN 0x0
+#define MASK_C_ADDI4SPN 0xe003
+#define MATCH_C_FLD 0x2000
+#define MASK_C_FLD 0xe003
+#define MATCH_C_LW 0x4000
+#define MASK_C_LW 0xe003
+#define MATCH_C_FLW 0x6000
+#define MASK_C_FLW 0xe003
+#define MATCH_C_FSD 0xa000
+#define MASK_C_FSD 0xe003
+#define MATCH_C_SW 0xc000
+#define MASK_C_SW 0xe003
+#define MATCH_C_FSW 0xe000
+#define MASK_C_FSW 0xe003
+#define MATCH_C_ADDI 0x1
+#define MASK_C_ADDI 0xe003
+#define MATCH_C_JAL 0x2001
+#define MASK_C_JAL 0xe003
+#define MATCH_C_LI 0x4001
+#define MASK_C_LI 0xe003
+#define MATCH_C_LUI 0x6001
+#define MASK_C_LUI 0xe003
+#define MATCH_C_SRLI 0x8001
+#define MASK_C_SRLI 0xec03
+#define MATCH_C_SRAI 0x8401
+#define MASK_C_SRAI 0xec03
+#define MATCH_C_ANDI 0x8801
+#define MASK_C_ANDI 0xec03
+#define MATCH_C_SUB 0x8c01
+#define MASK_C_SUB 0xfc63
+#define MATCH_C_XOR 0x8c21
+#define MASK_C_XOR 0xfc63
+#define MATCH_C_OR 0x8c41
+#define MASK_C_OR 0xfc63
+#define MATCH_C_AND 0x8c61
+#define MASK_C_AND 0xfc63
+#define MATCH_C_SUBW 0x9c01
+#define MASK_C_SUBW 0xfc63
+#define MATCH_C_ADDW 0x9c21
+#define MASK_C_ADDW 0xfc63
+#define MATCH_C_J 0xa001
+#define MASK_C_J 0xe003
+#define MATCH_C_BEQZ 0xc001
+#define MASK_C_BEQZ 0xe003
+#define MATCH_C_BNEZ 0xe001
+#define MASK_C_BNEZ 0xe003
+#define MATCH_C_SLLI 0x2
+#define MASK_C_SLLI 0xe003
+#define MATCH_C_FLDSP 0x2002
+#define MASK_C_FLDSP 0xe003
+#define MATCH_C_LWSP 0x4002
+#define MASK_C_LWSP 0xe003
+#define MATCH_C_FLWSP 0x6002
+#define MASK_C_FLWSP 0xe003
+#define MATCH_C_MV 0x8002
+#define MASK_C_MV 0xf003
+#define MATCH_C_ADD 0x9002
+#define MASK_C_ADD 0xf003
+#define MATCH_C_FSDSP 0xa002
+#define MASK_C_FSDSP 0xe003
+#define MATCH_C_SWSP 0xc002
+#define MASK_C_SWSP 0xe003
+#define MATCH_C_FSWSP 0xe002
+#define MASK_C_FSWSP 0xe003
+#define MATCH_CUSTOM0 0xb
+#define MASK_CUSTOM0 0x707f
+#define MATCH_CUSTOM0_RS1 0x200b
+#define MASK_CUSTOM0_RS1 0x707f
+#define MATCH_CUSTOM0_RS1_RS2 0x300b
+#define MASK_CUSTOM0_RS1_RS2 0x707f
+#define MATCH_CUSTOM0_RD 0x400b
+#define MASK_CUSTOM0_RD 0x707f
+#define MATCH_CUSTOM0_RD_RS1 0x600b
+#define MASK_CUSTOM0_RD_RS1 0x707f
+#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
+#define MASK_CUSTOM0_RD_RS1_RS2 0x707f
+#define MATCH_CUSTOM1 0x2b
+#define MASK_CUSTOM1 0x707f
+#define MATCH_CUSTOM1_RS1 0x202b
+#define MASK_CUSTOM1_RS1 0x707f
+#define MATCH_CUSTOM1_RS1_RS2 0x302b
+#define MASK_CUSTOM1_RS1_RS2 0x707f
+#define MATCH_CUSTOM1_RD 0x402b
+#define MASK_CUSTOM1_RD 0x707f
+#define MATCH_CUSTOM1_RD_RS1 0x602b
+#define MASK_CUSTOM1_RD_RS1 0x707f
+#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
+#define MASK_CUSTOM1_RD_RS1_RS2 0x707f
+#define MATCH_CUSTOM2 0x5b
+#define MASK_CUSTOM2 0x707f
+#define MATCH_CUSTOM2_RS1 0x205b
+#define MASK_CUSTOM2_RS1 0x707f
+#define MATCH_CUSTOM2_RS1_RS2 0x305b
+#define MASK_CUSTOM2_RS1_RS2 0x707f
+#define MATCH_CUSTOM2_RD 0x405b
+#define MASK_CUSTOM2_RD 0x707f
+#define MATCH_CUSTOM2_RD_RS1 0x605b
+#define MASK_CUSTOM2_RD_RS1 0x707f
+#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
+#define MASK_CUSTOM2_RD_RS1_RS2 0x707f
+#define MATCH_CUSTOM3 0x7b
+#define MASK_CUSTOM3 0x707f
+#define MATCH_CUSTOM3_RS1 0x207b
+#define MASK_CUSTOM3_RS1 0x707f
+#define MATCH_CUSTOM3_RS1_RS2 0x307b
+#define MASK_CUSTOM3_RS1_RS2 0x707f
+#define MATCH_CUSTOM3_RD 0x407b
+#define MASK_CUSTOM3_RD 0x707f
+#define MATCH_CUSTOM3_RD_RS1 0x607b
+#define MASK_CUSTOM3_RD_RS1 0x707f
+#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
+#define MASK_CUSTOM3_RD_RS1_RS2 0x707f
+#define CSR_FFLAGS 0x1
+#define CSR_FRM 0x2
+#define CSR_FCSR 0x3
+#define CSR_CYCLE 0xc00
+#define CSR_TIME 0xc01
+#define CSR_INSTRET 0xc02
+#define CSR_HPMCOUNTER3 0xc03
+#define CSR_HPMCOUNTER4 0xc04
+#define CSR_HPMCOUNTER5 0xc05
+#define CSR_HPMCOUNTER6 0xc06
+#define CSR_HPMCOUNTER7 0xc07
+#define CSR_HPMCOUNTER8 0xc08
+#define CSR_HPMCOUNTER9 0xc09
+#define CSR_HPMCOUNTER10 0xc0a
+#define CSR_HPMCOUNTER11 0xc0b
+#define CSR_HPMCOUNTER12 0xc0c
+#define CSR_HPMCOUNTER13 0xc0d
+#define CSR_HPMCOUNTER14 0xc0e
+#define CSR_HPMCOUNTER15 0xc0f
+#define CSR_HPMCOUNTER16 0xc10
+#define CSR_HPMCOUNTER17 0xc11
+#define CSR_HPMCOUNTER18 0xc12
+#define CSR_HPMCOUNTER19 0xc13
+#define CSR_HPMCOUNTER20 0xc14
+#define CSR_HPMCOUNTER21 0xc15
+#define CSR_HPMCOUNTER22 0xc16
+#define CSR_HPMCOUNTER23 0xc17
+#define CSR_HPMCOUNTER24 0xc18
+#define CSR_HPMCOUNTER25 0xc19
+#define CSR_HPMCOUNTER26 0xc1a
+#define CSR_HPMCOUNTER27 0xc1b
+#define CSR_HPMCOUNTER28 0xc1c
+#define CSR_HPMCOUNTER29 0xc1d
+#define CSR_HPMCOUNTER30 0xc1e
+#define CSR_HPMCOUNTER31 0xc1f
+#define CSR_SSTATUS 0x100
+#define CSR_SIE 0x104
+#define CSR_STVEC 0x105
+#define CSR_SSCRATCH 0x140
+#define CSR_SEPC 0x141
+#define CSR_SCAUSE 0x142
+#define CSR_SBADADDR 0x143
+#define CSR_SIP 0x144
+#define CSR_SPTBR 0x180
+#define CSR_MSTATUS 0x300
+#define CSR_MISA 0x301
+#define CSR_MEDELEG 0x302
+#define CSR_MIDELEG 0x303
+#define CSR_MIE 0x304
+#define CSR_MTVEC 0x305
+#define CSR_MSCRATCH 0x340
+#define CSR_MEPC 0x341
+#define CSR_MCAUSE 0x342
+#define CSR_MBADADDR 0x343
+#define CSR_MIP 0x344
+#define CSR_TSELECT 0x7a0
+#define CSR_TDATA1 0x7a1
+#define CSR_TDATA2 0x7a2
+#define CSR_TDATA3 0x7a3
+#define CSR_DCSR 0x7b0
+#define CSR_DPC 0x7b1
+#define CSR_DSCRATCH 0x7b2
+#define CSR_MCYCLE 0xb00
+#define CSR_MINSTRET 0xb02
+#define CSR_MHPMCOUNTER3 0xb03
+#define CSR_MHPMCOUNTER4 0xb04
+#define CSR_MHPMCOUNTER5 0xb05
+#define CSR_MHPMCOUNTER6 0xb06
+#define CSR_MHPMCOUNTER7 0xb07
+#define CSR_MHPMCOUNTER8 0xb08
+#define CSR_MHPMCOUNTER9 0xb09
+#define CSR_MHPMCOUNTER10 0xb0a
+#define CSR_MHPMCOUNTER11 0xb0b
+#define CSR_MHPMCOUNTER12 0xb0c
+#define CSR_MHPMCOUNTER13 0xb0d
+#define CSR_MHPMCOUNTER14 0xb0e
+#define CSR_MHPMCOUNTER15 0xb0f
+#define CSR_MHPMCOUNTER16 0xb10
+#define CSR_MHPMCOUNTER17 0xb11
+#define CSR_MHPMCOUNTER18 0xb12
+#define CSR_MHPMCOUNTER19 0xb13
+#define CSR_MHPMCOUNTER20 0xb14
+#define CSR_MHPMCOUNTER21 0xb15
+#define CSR_MHPMCOUNTER22 0xb16
+#define CSR_MHPMCOUNTER23 0xb17
+#define CSR_MHPMCOUNTER24 0xb18
+#define CSR_MHPMCOUNTER25 0xb19
+#define CSR_MHPMCOUNTER26 0xb1a
+#define CSR_MHPMCOUNTER27 0xb1b
+#define CSR_MHPMCOUNTER28 0xb1c
+#define CSR_MHPMCOUNTER29 0xb1d
+#define CSR_MHPMCOUNTER30 0xb1e
+#define CSR_MHPMCOUNTER31 0xb1f
+#define CSR_MUCOUNTEREN 0x320
+#define CSR_MSCOUNTEREN 0x321
+#define CSR_MHPMEVENT3 0x323
+#define CSR_MHPMEVENT4 0x324
+#define CSR_MHPMEVENT5 0x325
+#define CSR_MHPMEVENT6 0x326
+#define CSR_MHPMEVENT7 0x327
+#define CSR_MHPMEVENT8 0x328
+#define CSR_MHPMEVENT9 0x329
+#define CSR_MHPMEVENT10 0x32a
+#define CSR_MHPMEVENT11 0x32b
+#define CSR_MHPMEVENT12 0x32c
+#define CSR_MHPMEVENT13 0x32d
+#define CSR_MHPMEVENT14 0x32e
+#define CSR_MHPMEVENT15 0x32f
+#define CSR_MHPMEVENT16 0x330
+#define CSR_MHPMEVENT17 0x331
+#define CSR_MHPMEVENT18 0x332
+#define CSR_MHPMEVENT19 0x333
+#define CSR_MHPMEVENT20 0x334
+#define CSR_MHPMEVENT21 0x335
+#define CSR_MHPMEVENT22 0x336
+#define CSR_MHPMEVENT23 0x337
+#define CSR_MHPMEVENT24 0x338
+#define CSR_MHPMEVENT25 0x339
+#define CSR_MHPMEVENT26 0x33a
+#define CSR_MHPMEVENT27 0x33b
+#define CSR_MHPMEVENT28 0x33c
+#define CSR_MHPMEVENT29 0x33d
+#define CSR_MHPMEVENT30 0x33e
+#define CSR_MHPMEVENT31 0x33f
+#define CSR_MVENDORID 0xf11
+#define CSR_MARCHID 0xf12
+#define CSR_MIMPID 0xf13
+#define CSR_MHARTID 0xf14
+#define CSR_CYCLEH 0xc80
+#define CSR_TIMEH 0xc81
+#define CSR_INSTRETH 0xc82
+#define CSR_HPMCOUNTER3H 0xc83
+#define CSR_HPMCOUNTER4H 0xc84
+#define CSR_HPMCOUNTER5H 0xc85
+#define CSR_HPMCOUNTER6H 0xc86
+#define CSR_HPMCOUNTER7H 0xc87
+#define CSR_HPMCOUNTER8H 0xc88
+#define CSR_HPMCOUNTER9H 0xc89
+#define CSR_HPMCOUNTER10H 0xc8a
+#define CSR_HPMCOUNTER11H 0xc8b
+#define CSR_HPMCOUNTER12H 0xc8c
+#define CSR_HPMCOUNTER13H 0xc8d
+#define CSR_HPMCOUNTER14H 0xc8e
+#define CSR_HPMCOUNTER15H 0xc8f
+#define CSR_HPMCOUNTER16H 0xc90
+#define CSR_HPMCOUNTER17H 0xc91
+#define CSR_HPMCOUNTER18H 0xc92
+#define CSR_HPMCOUNTER19H 0xc93
+#define CSR_HPMCOUNTER20H 0xc94
+#define CSR_HPMCOUNTER21H 0xc95
+#define CSR_HPMCOUNTER22H 0xc96
+#define CSR_HPMCOUNTER23H 0xc97
+#define CSR_HPMCOUNTER24H 0xc98
+#define CSR_HPMCOUNTER25H 0xc99
+#define CSR_HPMCOUNTER26H 0xc9a
+#define CSR_HPMCOUNTER27H 0xc9b
+#define CSR_HPMCOUNTER28H 0xc9c
+#define CSR_HPMCOUNTER29H 0xc9d
+#define CSR_HPMCOUNTER30H 0xc9e
+#define CSR_HPMCOUNTER31H 0xc9f
+#define CSR_MCYCLEH 0xb80
+#define CSR_MINSTRETH 0xb82
+#define CSR_MHPMCOUNTER3H 0xb83
+#define CSR_MHPMCOUNTER4H 0xb84
+#define CSR_MHPMCOUNTER5H 0xb85
+#define CSR_MHPMCOUNTER6H 0xb86
+#define CSR_MHPMCOUNTER7H 0xb87
+#define CSR_MHPMCOUNTER8H 0xb88
+#define CSR_MHPMCOUNTER9H 0xb89
+#define CSR_MHPMCOUNTER10H 0xb8a
+#define CSR_MHPMCOUNTER11H 0xb8b
+#define CSR_MHPMCOUNTER12H 0xb8c
+#define CSR_MHPMCOUNTER13H 0xb8d
+#define CSR_MHPMCOUNTER14H 0xb8e
+#define CSR_MHPMCOUNTER15H 0xb8f
+#define CSR_MHPMCOUNTER16H 0xb90
+#define CSR_MHPMCOUNTER17H 0xb91
+#define CSR_MHPMCOUNTER18H 0xb92
+#define CSR_MHPMCOUNTER19H 0xb93
+#define CSR_MHPMCOUNTER20H 0xb94
+#define CSR_MHPMCOUNTER21H 0xb95
+#define CSR_MHPMCOUNTER22H 0xb96
+#define CSR_MHPMCOUNTER23H 0xb97
+#define CSR_MHPMCOUNTER24H 0xb98
+#define CSR_MHPMCOUNTER25H 0xb99
+#define CSR_MHPMCOUNTER26H 0xb9a
+#define CSR_MHPMCOUNTER27H 0xb9b
+#define CSR_MHPMCOUNTER28H 0xb9c
+#define CSR_MHPMCOUNTER29H 0xb9d
+#define CSR_MHPMCOUNTER30H 0xb9e
+#define CSR_MHPMCOUNTER31H 0xb9f
+#define CAUSE_MISALIGNED_FETCH 0x0
+#define CAUSE_FAULT_FETCH 0x1
+#define CAUSE_ILLEGAL_INSTRUCTION 0x2
+#define CAUSE_BREAKPOINT 0x3
+#define CAUSE_MISALIGNED_LOAD 0x4
+#define CAUSE_FAULT_LOAD 0x5
+#define CAUSE_MISALIGNED_STORE 0x6
+#define CAUSE_FAULT_STORE 0x7
+#define CAUSE_USER_ECALL 0x8
+#define CAUSE_SUPERVISOR_ECALL 0x9
+#define CAUSE_HYPERVISOR_ECALL 0xa
+#define CAUSE_MACHINE_ECALL 0xb
+#endif
+#ifdef DECLARE_INSN
+DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
+DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
+DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
+DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
+DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
+DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
+DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
+DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
+DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
+DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
+DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
+DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
+DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
+DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
+DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
+DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
+DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
+DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
+DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
+DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
+DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
+DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
+DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
+DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
+DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
+DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
+DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
+DECLARE_INSN(or, MATCH_OR, MASK_OR)
+DECLARE_INSN(and, MATCH_AND, MASK_AND)
+DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
+DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
+DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
+DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
+DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
+DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
+DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
+DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
+DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
+DECLARE_INSN(lb, MATCH_LB, MASK_LB)
+DECLARE_INSN(lh, MATCH_LH, MASK_LH)
+DECLARE_INSN(lw, MATCH_LW, MASK_LW)
+DECLARE_INSN(ld, MATCH_LD, MASK_LD)
+DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
+DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
+DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
+DECLARE_INSN(sb, MATCH_SB, MASK_SB)
+DECLARE_INSN(sh, MATCH_SH, MASK_SH)
+DECLARE_INSN(sw, MATCH_SW, MASK_SW)
+DECLARE_INSN(sd, MATCH_SD, MASK_SD)
+DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
+DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
+DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
+DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
+DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
+DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
+DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
+DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
+DECLARE_INSN(rem, MATCH_REM, MASK_REM)
+DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
+DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
+DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
+DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
+DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
+DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
+DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
+DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
+DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
+DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
+DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
+DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
+DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
+DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
+DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
+DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
+DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
+DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
+DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
+DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
+DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
+DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
+DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
+DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
+DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
+DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
+DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
+DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
+DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
+DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
+DECLARE_INSN(uret, MATCH_URET, MASK_URET)
+DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
+DECLARE_INSN(hret, MATCH_HRET, MASK_HRET)
+DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
+DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
+DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
+DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
+DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
+DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
+DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
+DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
+DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
+DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
+DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
+DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
+DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
+DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
+DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
+DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
+DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
+DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
+DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
+DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
+DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
+DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
+DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
+DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
+DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
+DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
+DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
+DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
+DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
+DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
+DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
+DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
+DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
+DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
+DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
+DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
+DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
+DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
+DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
+DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
+DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
+DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
+DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
+DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
+DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
+DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
+DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
+DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
+DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
+DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
+DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
+DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
+DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
+DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
+DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
+DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
+DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
+DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
+DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
+DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
+DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
+DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
+DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
+DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
+DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
+DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
+DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
+DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
+DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
+DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
+DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
+DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
+DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP)
+DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)
+DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
+DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)
+DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK)
+DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
+DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
+DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
+DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
+DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
+DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
+DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)
+DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
+DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW)
+DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD)
+DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
+DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW)
+DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
+DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL)
+DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
+DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)
+DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
+DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
+DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI)
+DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
+DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR)
+DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR)
+DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND)
+DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW)
+DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
+DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
+DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
+DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)
+DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
+DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP)
+DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
+DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP)
+DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV)
+DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
+DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP)
+DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
+DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP)
+DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
+DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
+DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
+DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
+DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
+DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2)
+DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
+DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
+DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
+DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
+DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
+DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2)
+DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
+DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
+DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
+DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
+DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
+DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2)
+DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
+DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
+DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
+DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
+DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
+DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
+#endif
+#ifdef DECLARE_CSR
+DECLARE_CSR(fflags, CSR_FFLAGS)
+DECLARE_CSR(frm, CSR_FRM)
+DECLARE_CSR(fcsr, CSR_FCSR)
+DECLARE_CSR(cycle, CSR_CYCLE)
+DECLARE_CSR(time, CSR_TIME)
+DECLARE_CSR(instret, CSR_INSTRET)
+DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3)
+DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4)
+DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5)
+DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6)
+DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7)
+DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8)
+DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9)
+DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10)
+DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11)
+DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12)
+DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13)
+DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14)
+DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15)
+DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16)
+DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17)
+DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18)
+DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19)
+DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20)
+DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21)
+DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22)
+DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23)
+DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24)
+DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25)
+DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26)
+DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27)
+DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28)
+DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29)
+DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30)
+DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31)
+DECLARE_CSR(sstatus, CSR_SSTATUS)
+DECLARE_CSR(sie, CSR_SIE)
+DECLARE_CSR(stvec, CSR_STVEC)
+DECLARE_CSR(sscratch, CSR_SSCRATCH)
+DECLARE_CSR(sepc, CSR_SEPC)
+DECLARE_CSR(scause, CSR_SCAUSE)
+DECLARE_CSR(sbadaddr, CSR_SBADADDR)
+DECLARE_CSR(sip, CSR_SIP)
+DECLARE_CSR(sptbr, CSR_SPTBR)
+DECLARE_CSR(mstatus, CSR_MSTATUS)
+DECLARE_CSR(misa, CSR_MISA)
+DECLARE_CSR(medeleg, CSR_MEDELEG)
+DECLARE_CSR(mideleg, CSR_MIDELEG)
+DECLARE_CSR(mie, CSR_MIE)
+DECLARE_CSR(mtvec, CSR_MTVEC)
+DECLARE_CSR(mscratch, CSR_MSCRATCH)
+DECLARE_CSR(mepc, CSR_MEPC)
+DECLARE_CSR(mcause, CSR_MCAUSE)
+DECLARE_CSR(mbadaddr, CSR_MBADADDR)
+DECLARE_CSR(mip, CSR_MIP)
+DECLARE_CSR(tselect, CSR_TSELECT)
+DECLARE_CSR(tdata1, CSR_TDATA1)
+DECLARE_CSR(tdata2, CSR_TDATA2)
+DECLARE_CSR(tdata3, CSR_TDATA3)
+DECLARE_CSR(dcsr, CSR_DCSR)
+DECLARE_CSR(dpc, CSR_DPC)
+DECLARE_CSR(dscratch, CSR_DSCRATCH)
+DECLARE_CSR(mcycle, CSR_MCYCLE)
+DECLARE_CSR(minstret, CSR_MINSTRET)
+DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3)
+DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4)
+DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5)
+DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6)
+DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7)
+DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8)
+DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9)
+DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10)
+DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11)
+DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12)
+DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13)
+DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14)
+DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15)
+DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16)
+DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17)
+DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18)
+DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19)
+DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20)
+DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21)
+DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22)
+DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23)
+DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24)
+DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25)
+DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26)
+DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27)
+DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28)
+DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29)
+DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30)
+DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31)
+DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN)
+DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN)
+DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3)
+DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4)
+DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5)
+DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6)
+DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7)
+DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8)
+DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9)
+DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10)
+DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11)
+DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12)
+DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13)
+DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14)
+DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15)
+DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16)
+DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17)
+DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18)
+DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19)
+DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20)
+DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21)
+DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22)
+DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23)
+DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24)
+DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25)
+DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26)
+DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27)
+DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28)
+DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29)
+DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30)
+DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31)
+DECLARE_CSR(mvendorid, CSR_MVENDORID)
+DECLARE_CSR(marchid, CSR_MARCHID)
+DECLARE_CSR(mimpid, CSR_MIMPID)
+DECLARE_CSR(mhartid, CSR_MHARTID)
+DECLARE_CSR(cycleh, CSR_CYCLEH)
+DECLARE_CSR(timeh, CSR_TIMEH)
+DECLARE_CSR(instreth, CSR_INSTRETH)
+DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H)
+DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H)
+DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H)
+DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H)
+DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H)
+DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H)
+DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H)
+DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H)
+DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H)
+DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H)
+DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H)
+DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H)
+DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H)
+DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H)
+DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H)
+DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H)
+DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H)
+DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H)
+DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H)
+DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H)
+DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H)
+DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H)
+DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H)
+DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H)
+DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H)
+DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H)
+DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H)
+DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H)
+DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H)
+DECLARE_CSR(mcycleh, CSR_MCYCLEH)
+DECLARE_CSR(minstreth, CSR_MINSTRETH)
+DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H)
+DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H)
+DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H)
+DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H)
+DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H)
+DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H)
+DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H)
+DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H)
+DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H)
+DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H)
+DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H)
+DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H)
+DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H)
+DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H)
+DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H)
+DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H)
+DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H)
+DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H)
+DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H)
+DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H)
+DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H)
+DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H)
+DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H)
+DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H)
+DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H)
+DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H)
+DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H)
+DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H)
+DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H)
+#endif
+#ifdef DECLARE_CAUSE
+DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
+DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH)
+DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION)
+DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT)
+DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD)
+DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD)
+DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE)
+DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE)
+DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL)
+DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL)
+DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL)
+DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL)
+#endif
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/env/entry.S b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/env/entry.S new file mode 100644 index 000000000..ce44f48de --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/env/entry.S @@ -0,0 +1,98 @@ +// See LICENSE for license details
+
+#ifndef ENTRY_S
+#define ENTRY_S
+
+#include "encoding.h"
+#include "sifive/bits.h"
+
+ .section .text.entry
+ .align 2
+ .weak trap_entry
+ .global trap_entry
+trap_entry:
+ addi sp, sp, -32*REGBYTES
+
+ STORE x1, 1*REGBYTES(sp)
+ STORE x2, 2*REGBYTES(sp)
+ STORE x3, 3*REGBYTES(sp)
+ STORE x4, 4*REGBYTES(sp)
+ STORE x5, 5*REGBYTES(sp)
+ STORE x6, 6*REGBYTES(sp)
+ STORE x7, 7*REGBYTES(sp)
+ STORE x8, 8*REGBYTES(sp)
+ STORE x9, 9*REGBYTES(sp)
+ STORE x10, 10*REGBYTES(sp)
+ STORE x11, 11*REGBYTES(sp)
+ STORE x12, 12*REGBYTES(sp)
+ STORE x13, 13*REGBYTES(sp)
+ STORE x14, 14*REGBYTES(sp)
+ STORE x15, 15*REGBYTES(sp)
+ STORE x16, 16*REGBYTES(sp)
+ STORE x17, 17*REGBYTES(sp)
+ STORE x18, 18*REGBYTES(sp)
+ STORE x19, 19*REGBYTES(sp)
+ STORE x20, 20*REGBYTES(sp)
+ STORE x21, 21*REGBYTES(sp)
+ STORE x22, 22*REGBYTES(sp)
+ STORE x23, 23*REGBYTES(sp)
+ STORE x24, 24*REGBYTES(sp)
+ STORE x25, 25*REGBYTES(sp)
+ STORE x26, 26*REGBYTES(sp)
+ STORE x27, 27*REGBYTES(sp)
+ STORE x28, 28*REGBYTES(sp)
+ STORE x29, 29*REGBYTES(sp)
+ STORE x30, 30*REGBYTES(sp)
+ STORE x31, 31*REGBYTES(sp)
+
+ csrr a0, mcause
+ csrr a1, mepc
+ mv a2, sp
+ call handle_trap
+ csrw mepc, a0
+
+ # Remain in M-mode after mret
+ li t0, MSTATUS_MPP
+ csrs mstatus, t0
+
+ LOAD x1, 1*REGBYTES(sp)
+ LOAD x2, 2*REGBYTES(sp)
+ LOAD x3, 3*REGBYTES(sp)
+ LOAD x4, 4*REGBYTES(sp)
+ LOAD x5, 5*REGBYTES(sp)
+ LOAD x6, 6*REGBYTES(sp)
+ LOAD x7, 7*REGBYTES(sp)
+ LOAD x8, 8*REGBYTES(sp)
+ LOAD x9, 9*REGBYTES(sp)
+ LOAD x10, 10*REGBYTES(sp)
+ LOAD x11, 11*REGBYTES(sp)
+ LOAD x12, 12*REGBYTES(sp)
+ LOAD x13, 13*REGBYTES(sp)
+ LOAD x14, 14*REGBYTES(sp)
+ LOAD x15, 15*REGBYTES(sp)
+ LOAD x16, 16*REGBYTES(sp)
+ LOAD x17, 17*REGBYTES(sp)
+ LOAD x18, 18*REGBYTES(sp)
+ LOAD x19, 19*REGBYTES(sp)
+ LOAD x20, 20*REGBYTES(sp)
+ LOAD x21, 21*REGBYTES(sp)
+ LOAD x22, 22*REGBYTES(sp)
+ LOAD x23, 23*REGBYTES(sp)
+ LOAD x24, 24*REGBYTES(sp)
+ LOAD x25, 25*REGBYTES(sp)
+ LOAD x26, 26*REGBYTES(sp)
+ LOAD x27, 27*REGBYTES(sp)
+ LOAD x28, 28*REGBYTES(sp)
+ LOAD x29, 29*REGBYTES(sp)
+ LOAD x30, 30*REGBYTES(sp)
+ LOAD x31, 31*REGBYTES(sp)
+
+ addi sp, sp, 32*REGBYTES
+ mret
+
+.weak handle_trap
+handle_trap:
+1:
+ j 1b
+
+#endif
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/env/freedom-e300-hifive1/dhrystone.lds b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/env/freedom-e300-hifive1/dhrystone.lds new file mode 100644 index 000000000..302bf743b --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/env/freedom-e300-hifive1/dhrystone.lds @@ -0,0 +1,157 @@ +OUTPUT_ARCH( "riscv" )
+
+ENTRY( _start )
+
+MEMORY
+{
+ flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M
+ ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
+}
+
+PHDRS
+{
+ flash PT_LOAD;
+ ram_init PT_LOAD;
+ ram PT_NULL;
+}
+
+SECTIONS
+{
+ __stack_size = DEFINED(__stack_size) ? __stack_size : 1K;
+
+ .init :
+ {
+ KEEP (*(SORT_NONE(.init)))
+ } >flash AT>flash :flash
+
+ .text :
+ {
+ *(.text.unlikely .text.unlikely.*)
+ *(.text.startup .text.startup.*)
+ *(.text .text.*)
+ *(.gnu.linkonce.t.*)
+ } >flash AT>flash :flash
+
+ .fini :
+ {
+ KEEP (*(SORT_NONE(.fini)))
+ } >flash AT>flash :flash
+
+ PROVIDE (__etext = .);
+ PROVIDE (_etext = .);
+ PROVIDE (etext = .);
+
+ . = ALIGN(4);
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >flash AT>flash :flash
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+ KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >flash AT>flash :flash
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+ KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >flash AT>flash :flash
+
+ .ctors :
+ {
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ } >flash AT>flash :flash
+
+ .dtors :
+ {
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ } >flash AT>flash :flash
+
+ .lalign :
+ {
+ . = ALIGN(4);
+ PROVIDE( _data_lma = . );
+ } >flash AT>flash :flash
+
+ .dalign :
+ {
+ . = ALIGN(4);
+ PROVIDE( _data = . );
+ } >ram AT>flash :ram_init
+
+ .data :
+ {
+ *(.rdata)
+ *(.rodata .rodata.*)
+ *(.gnu.linkonce.r.*)
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+ . = ALIGN(8);
+ PROVIDE( __global_pointer$ = . + 0x800 );
+ *(.sdata .sdata.*)
+ *(.gnu.linkonce.s.*)
+ . = ALIGN(8);
+ *(.srodata.cst16)
+ *(.srodata.cst8)
+ *(.srodata.cst4)
+ *(.srodata.cst2)
+ *(.srodata .srodata.*)
+ } >ram AT>flash :ram_init
+
+ . = ALIGN(4);
+ PROVIDE( _edata = . );
+ PROVIDE( edata = . );
+
+ PROVIDE( _fbss = . );
+ PROVIDE( __bss_start = . );
+ .bss :
+ {
+ *(.sbss*)
+ *(.gnu.linkonce.sb.*)
+ *(.bss .bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN(4);
+ } >ram AT>ram :ram
+
+ . = ALIGN(8);
+ PROVIDE( _end = . );
+ PROVIDE( end = . );
+
+ .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
+ {
+ PROVIDE( _heap_end = . );
+ . = __stack_size;
+ PROVIDE( _sp = . );
+ } >ram AT>ram :ram
+}
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/env/freedom-e300-hifive1/flash.lds b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/env/freedom-e300-hifive1/flash.lds new file mode 100644 index 000000000..44639ee71 --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/env/freedom-e300-hifive1/flash.lds @@ -0,0 +1,162 @@ +OUTPUT_ARCH( "riscv" )
+
+ENTRY( _start )
+
+MEMORY
+{
+ flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M
+ ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
+}
+
+PHDRS
+{
+ flash PT_LOAD;
+ ram_init PT_LOAD;
+ ram PT_NULL;
+}
+
+SECTIONS
+{
+ __stack_size = DEFINED(__stack_size) ? __stack_size : 400;
+
+ .init :
+ {
+ KEEP (*(SORT_NONE(.init)))
+ } >flash AT>flash :flash
+
+ .text :
+ {
+ *(.text.unlikely .text.unlikely.*)
+ *(.text.startup .text.startup.*)
+ *(.text .text.*)
+ *(.gnu.linkonce.t.*)
+ } >flash AT>flash :flash
+
+ .fini :
+ {
+ KEEP (*(SORT_NONE(.fini)))
+ } >flash AT>flash :flash
+
+ PROVIDE (__etext = .);
+ PROVIDE (_etext = .);
+ PROVIDE (etext = .);
+
+ .rodata :
+ {
+ *(.rdata)
+ *(.rodata .rodata.*)
+ *(.gnu.linkonce.r.*)
+ } >flash AT>flash :flash
+
+ . = ALIGN(4);
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >flash AT>flash :flash
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+ KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >flash AT>flash :flash
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+ KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >flash AT>flash :flash
+
+ .ctors :
+ {
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ } >flash AT>flash :flash
+
+ .dtors :
+ {
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ } >flash AT>flash :flash
+
+ .lalign :
+ {
+ . = ALIGN(4);
+ PROVIDE( _data_lma = . );
+ } >flash AT>flash :flash
+
+ .dalign :
+ {
+ . = ALIGN(4);
+ PROVIDE( _data = . );
+ } >ram AT>flash :ram_init
+
+ .data :
+ {
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+ . = ALIGN(8);
+ PROVIDE( __global_pointer$ = . + 0x800 );
+ *(.sdata .sdata.*)
+ *(.gnu.linkonce.s.*)
+ . = ALIGN(8);
+ *(.srodata.cst16)
+ *(.srodata.cst8)
+ *(.srodata.cst4)
+ *(.srodata.cst2)
+ *(.srodata .srodata.*)
+ } >ram AT>flash :ram_init
+
+ . = ALIGN(4);
+ PROVIDE( _edata = . );
+ PROVIDE( edata = . );
+
+ PROVIDE( _fbss = . );
+ PROVIDE( __bss_start = . );
+ .bss :
+ {
+ *(.sbss*)
+ *(.gnu.linkonce.sb.*)
+ *(.bss .bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN(4);
+ } >ram AT>ram :ram
+
+ . = ALIGN(8);
+ PROVIDE( _end = . );
+ PROVIDE( end = . );
+
+ .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
+ {
+ PROVIDE( _heap_end = . );
+ . = __stack_size;
+ PROVIDE( _sp = . );
+ __freertos_irq_stack_top = .;
+ } >ram AT>ram :ram
+}
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/env/freedom-e300-hifive1/init.c b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/env/freedom-e300-hifive1/init.c new file mode 100644 index 000000000..64fa6ef10 --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/env/freedom-e300-hifive1/init.c @@ -0,0 +1,236 @@ +#include <stdint.h>
+#include <stdio.h>
+#include <unistd.h>
+
+#include "platform.h"
+#include "encoding.h"
+
+extern int main(int argc, char** argv);
+extern void trap_entry();
+
+static unsigned long mtime_lo(void)
+{
+ return *(volatile unsigned long *)(CLINT_CTRL_ADDR + CLINT_MTIME);
+}
+
+#ifdef __riscv32
+
+static uint32_t mtime_hi(void)
+{
+ return *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIME + 4);
+}
+
+uint64_t get_timer_value()
+{
+ while (1) {
+ uint32_t hi = mtime_hi();
+ uint32_t lo = mtime_lo();
+ if (hi == mtime_hi())
+ return ((uint64_t)hi << 32) | lo;
+ }
+}
+
+#else /* __riscv32 */
+
+uint64_t get_timer_value()
+{
+ return mtime_lo();
+}
+
+#endif
+
+unsigned long get_timer_freq()
+{
+ return 32768;
+}
+
+static void use_hfrosc(int div, int trim)
+{
+ // Make sure the HFROSC is running at its default setting
+ PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1));
+ while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0) ;
+ PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1);
+}
+
+static void use_pll(int refsel, int bypass, int r, int f, int q)
+{
+ // Ensure that we aren't running off the PLL before we mess with it.
+ if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) {
+ // Make sure the HFROSC is running at its default setting
+ use_hfrosc(4, 16);
+ }
+
+ // Set PLL Source to be HFXOSC if available.
+ uint32_t config_value = 0;
+
+ config_value |= PLL_REFSEL(refsel);
+
+ if (bypass) {
+ // Bypass
+ config_value |= PLL_BYPASS(1);
+
+ PRCI_REG(PRCI_PLLCFG) = config_value;
+
+ // If we don't have an HFXTAL, this doesn't really matter.
+ // Set our Final output divide to divide-by-1:
+ PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
+ } else {
+ // In case we are executing from QSPI,
+ // (which is quite likely) we need to
+ // set the QSPI clock divider appropriately
+ // before boosting the clock frequency.
+
+ // Div = f_sck/2
+ SPI0_REG(SPI_REG_SCKDIV) = 8;
+
+ // Set DIV Settings for PLL
+ // Both HFROSC and HFXOSC are modeled as ideal
+ // 16MHz sources (assuming dividers are set properly for
+ // HFROSC).
+ // (Legal values of f_REF are 6-48MHz)
+
+ // Set DIVR to divide-by-2 to get 8MHz frequency
+ // (legal values of f_R are 6-12 MHz)
+
+ config_value |= PLL_BYPASS(1);
+ config_value |= PLL_R(r);
+
+ // Set DIVF to get 512Mhz frequncy
+ // There is an implied multiply-by-2, 16Mhz.
+ // So need to write 32-1
+ // (legal values of f_F are 384-768 MHz)
+ config_value |= PLL_F(f);
+
+ // Set DIVQ to divide-by-2 to get 256 MHz frequency
+ // (legal values of f_Q are 50-400Mhz)
+ config_value |= PLL_Q(q);
+
+ // Set our Final output divide to divide-by-1:
+ PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
+
+ PRCI_REG(PRCI_PLLCFG) = config_value;
+
+ // Un-Bypass the PLL.
+ PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1);
+
+ // Wait for PLL Lock
+ // Note that the Lock signal can be glitchy.
+ // Need to wait 100 us
+ // RTC is running at 32kHz.
+ // So wait 4 ticks of RTC.
+ uint32_t now = mtime_lo();
+ while (mtime_lo() - now < 4) ;
+
+ // Now it is safe to check for PLL Lock
+ while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0) ;
+ }
+
+ // Switch over to PLL Clock source
+ PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1);
+}
+
+static void use_default_clocks()
+{
+ // Turn off the LFROSC
+ AON_REG(AON_LFROSC) &= ~ROSC_EN(1);
+
+ // Use HFROSC
+ use_hfrosc(4, 16);
+}
+
+static unsigned long __attribute__((noinline)) measure_cpu_freq(size_t n)
+{
+ unsigned long start_mtime, delta_mtime;
+ unsigned long mtime_freq = get_timer_freq();
+
+ // Don't start measuruing until we see an mtime tick
+ unsigned long tmp = mtime_lo();
+ do {
+ start_mtime = mtime_lo();
+ } while (start_mtime == tmp);
+
+ unsigned long start_mcycle = read_csr(mcycle);
+
+ do {
+ delta_mtime = mtime_lo() - start_mtime;
+ } while (delta_mtime < n);
+
+ unsigned long delta_mcycle = read_csr(mcycle) - start_mcycle;
+
+ return (delta_mcycle / delta_mtime) * mtime_freq
+ + ((delta_mcycle % delta_mtime) * mtime_freq) / delta_mtime;
+}
+
+unsigned long get_cpu_freq()
+{
+ static uint32_t cpu_freq;
+
+ if (!cpu_freq) {
+ // warm up I$
+ measure_cpu_freq(1);
+ // measure for real
+ cpu_freq = measure_cpu_freq(10);
+ }
+
+ return cpu_freq;
+}
+
+static void uart_init(size_t baud_rate)
+{
+ GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK;
+ GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK;
+ UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1;
+ UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
+}
+
+
+
+#ifdef USE_PLIC
+extern void handle_m_ext_interrupt();
+#endif
+
+#ifdef USE_M_TIME
+extern void handle_m_time_interrupt();
+#endif
+
+uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)
+{
+ if (0){
+#ifdef USE_PLIC
+ // External Machine-Level interrupt from PLIC
+ } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) {
+ handle_m_ext_interrupt();
+#endif
+#ifdef USE_M_TIME
+ // External Machine-Level interrupt from PLIC
+ } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){
+ handle_m_time_interrupt();
+#endif
+ }
+ else {
+ write(1, "trap\n", 5);
+ _exit(1 + mcause);
+ }
+ return epc;
+}
+
+void _init()
+{
+
+ #ifndef NO_INIT
+ use_default_clocks();
+ use_pll(0, 0, 1, 31, 1);
+ uart_init(115200);
+
+ write_csr(mtvec, &trap_entry);
+ if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present
+ write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping
+ write_csr(fcsr, 0); // initialize rounding mode, undefined at reset
+ }
+ #endif
+
+}
+
+void _fini()
+{
+}
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/env/freedom-e300-hifive1/openocd.cfg b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/env/freedom-e300-hifive1/openocd.cfg new file mode 100644 index 000000000..08b7611d3 --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/env/freedom-e300-hifive1/openocd.cfg @@ -0,0 +1,34 @@ +adapter_khz 10000
+
+interface ftdi
+ftdi_device_desc "Dual RS232-HS"
+ftdi_vid_pid 0x0403 0x6010
+
+ftdi_layout_init 0x0008 0x001b
+ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
+
+#Reset Stretcher logic on FE310 is ~1 second long
+#This doesn't apply if you use
+# ftdi_set_signal, but still good to document
+#adapter_nsrst_delay 1500
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+
+flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME
+init
+#reset -- This type of reset is not implemented yet
+if {[ info exists pulse_srst]} {
+ ftdi_set_signal nSRST 0
+ ftdi_set_signal nSRST z
+ #Wait for the reset stretcher
+ #It will work without this, but
+ #will incur lots of delays for later commands.
+ sleep 1500
+}
+halt
+#flash protect 0 64 last off
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/env/freedom-e300-hifive1/platform.h b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/env/freedom-e300-hifive1/platform.h new file mode 100644 index 000000000..75d31e0f5 --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/env/freedom-e300-hifive1/platform.h @@ -0,0 +1,133 @@ +// See LICENSE for license details.
+
+#ifndef _SIFIVE_PLATFORM_H
+#define _SIFIVE_PLATFORM_H
+
+// Some things missing from the official encoding.h
+#define MCAUSE_INT 0x80000000
+#define MCAUSE_CAUSE 0x7FFFFFFF
+
+#include "sifive/const.h"
+#include "sifive/devices/aon.h"
+#include "sifive/devices/clint.h"
+#include "sifive/devices/gpio.h"
+#include "sifive/devices/otp.h"
+#include "sifive/devices/plic.h"
+#include "sifive/devices/prci.h"
+#include "sifive/devices/pwm.h"
+#include "sifive/devices/spi.h"
+#include "sifive/devices/uart.h"
+
+/****************************************************************************
+ * Platform definitions
+ *****************************************************************************/
+
+// Memory map
+#define MASKROM_MEM_ADDR _AC(0x00001000,UL)
+#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL)
+#define OTP_MEM_ADDR _AC(0x00020000,UL)
+#define CLINT_CTRL_ADDR _AC(0x02000000,UL)
+#define PLIC_CTRL_ADDR _AC(0x0C000000,UL)
+#define AON_CTRL_ADDR _AC(0x10000000,UL)
+#define PRCI_CTRL_ADDR _AC(0x10008000,UL)
+#define OTP_CTRL_ADDR _AC(0x10010000,UL)
+#define GPIO_CTRL_ADDR _AC(0x10012000,UL)
+#define UART0_CTRL_ADDR _AC(0x10013000,UL)
+#define SPI0_CTRL_ADDR _AC(0x10014000,UL)
+#define PWM0_CTRL_ADDR _AC(0x10015000,UL)
+#define UART1_CTRL_ADDR _AC(0x10023000,UL)
+#define SPI1_CTRL_ADDR _AC(0x10024000,UL)
+#define PWM1_CTRL_ADDR _AC(0x10025000,UL)
+#define SPI2_CTRL_ADDR _AC(0x10034000,UL)
+#define PWM2_CTRL_ADDR _AC(0x10035000,UL)
+#define SPI0_MEM_ADDR _AC(0x20000000,UL)
+#define MEM_CTRL_ADDR _AC(0x80000000,UL)
+
+// IOF masks
+#define IOF0_SPI1_MASK _AC(0x000007FC,UL)
+#define SPI11_NUM_SS (4)
+#define IOF_SPI1_SS0 (2u)
+#define IOF_SPI1_SS1 (8u)
+#define IOF_SPI1_SS2 (9u)
+#define IOF_SPI1_SS3 (10u)
+#define IOF_SPI1_MOSI (3u)
+#define IOF_SPI1_MISO (4u)
+#define IOF_SPI1_SCK (5u)
+#define IOF_SPI1_DQ0 (3u)
+#define IOF_SPI1_DQ1 (4u)
+#define IOF_SPI1_DQ2 (6u)
+#define IOF_SPI1_DQ3 (7u)
+
+#define IOF0_SPI2_MASK _AC(0xFC000000,UL)
+#define SPI2_NUM_SS (1)
+#define IOF_SPI2_SS0 (26u)
+#define IOF_SPI2_MOSI (27u)
+#define IOF_SPI2_MISO (28u)
+#define IOF_SPI2_SCK (29u)
+#define IOF_SPI2_DQ0 (27u)
+#define IOF_SPI2_DQ1 (28u)
+#define IOF_SPI2_DQ2 (30u)
+#define IOF_SPI2_DQ3 (31u)
+
+//#define IOF0_I2C_MASK _AC(0x00003000,UL)
+
+#define IOF0_UART0_MASK _AC(0x00030000, UL)
+#define IOF_UART0_RX (16u)
+#define IOF_UART0_TX (17u)
+
+#define IOF0_UART1_MASK _AC(0x03000000, UL)
+#define IOF_UART1_RX (24u)
+#define IOF_UART1_TX (25u)
+
+#define IOF1_PWM0_MASK _AC(0x0000000F, UL)
+#define IOF1_PWM1_MASK _AC(0x00780000, UL)
+#define IOF1_PWM2_MASK _AC(0x00003C00, UL)
+
+// Interrupt numbers
+#define INT_RESERVED 0
+#define INT_WDOGCMP 1
+#define INT_RTCCMP 2
+#define INT_UART0_BASE 3
+#define INT_UART1_BASE 4
+#define INT_SPI0_BASE 5
+#define INT_SPI1_BASE 6
+#define INT_SPI2_BASE 7
+#define INT_GPIO_BASE 8
+#define INT_PWM0_BASE 40
+#define INT_PWM1_BASE 44
+#define INT_PWM2_BASE 48
+
+// Helper functions
+#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
+#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i)))
+#define AON_REG(offset) _REG32(AON_CTRL_ADDR, offset)
+#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
+#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
+#define OTP_REG(offset) _REG32(OTP_CTRL_ADDR, offset)
+#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset)
+#define PRCI_REG(offset) _REG32(PRCI_CTRL_ADDR, offset)
+#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset)
+#define PWM1_REG(offset) _REG32(PWM1_CTRL_ADDR, offset)
+#define PWM2_REG(offset) _REG32(PWM2_CTRL_ADDR, offset)
+#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset)
+#define SPI1_REG(offset) _REG32(SPI1_CTRL_ADDR, offset)
+#define SPI2_REG(offset) _REG32(SPI2_CTRL_ADDR, offset)
+#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset)
+#define UART1_REG(offset) _REG32(UART1_CTRL_ADDR, offset)
+
+// Misc
+
+#include <stdint.h>
+
+#define NUM_GPIO 32
+
+#define PLIC_NUM_INTERRUPTS 52
+#define PLIC_NUM_PRIORITIES 7
+
+#include "hifive1.h"
+
+unsigned long get_cpu_freq(void);
+unsigned long get_timer_freq(void);
+uint64_t get_timer_value(void);
+
+#endif /* _SIFIVE_PLATFORM_H */
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/env/hifive1.h b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/env/hifive1.h new file mode 100644 index 000000000..d8fa4c981 --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/env/hifive1.h @@ -0,0 +1,81 @@ +// See LICENSE for license details.
+
+#ifndef _SIFIVE_HIFIVE1_H
+#define _SIFIVE_HIFIVE1_H
+
+#include <stdint.h>
+
+/****************************************************************************
+ * GPIO Connections
+ *****************************************************************************/
+
+// These are the GPIO bit offsets for the RGB LED on HiFive1 Board.
+// These are also mapped to RGB LEDs on the Freedom E300 Arty
+// FPGA
+// Dev Kit.
+
+#define RED_LED_OFFSET 22
+#define GREEN_LED_OFFSET 19
+#define BLUE_LED_OFFSET 21
+
+// These are the GPIO bit offsets for the differen digital pins
+// on the headers for both the HiFive1 Board and the Freedom E300 Arty FPGA Dev Kit.
+#define PIN_0_OFFSET 16
+#define PIN_1_OFFSET 17
+#define PIN_2_OFFSET 18
+#define PIN_3_OFFSET 19
+#define PIN_4_OFFSET 20
+#define PIN_5_OFFSET 21
+#define PIN_6_OFFSET 22
+#define PIN_7_OFFSET 23
+#define PIN_8_OFFSET 0
+#define PIN_9_OFFSET 1
+#define PIN_10_OFFSET 2
+#define PIN_11_OFFSET 3
+#define PIN_12_OFFSET 4
+#define PIN_13_OFFSET 5
+//#define PIN_14_OFFSET 8 //This pin is not connected on either board.
+#define PIN_15_OFFSET 9
+#define PIN_16_OFFSET 10
+#define PIN_17_OFFSET 11
+#define PIN_18_OFFSET 12
+#define PIN_19_OFFSET 13
+
+// These are *PIN* numbers, not
+// GPIO Offset Numbers.
+#define PIN_SPI1_SCK (13u)
+#define PIN_SPI1_MISO (12u)
+#define PIN_SPI1_MOSI (11u)
+#define PIN_SPI1_SS0 (10u)
+#define PIN_SPI1_SS1 (14u)
+#define PIN_SPI1_SS2 (15u)
+#define PIN_SPI1_SS3 (16u)
+
+#define SS_PIN_TO_CS_ID(x) \
+ ((x==PIN_SPI1_SS0 ? 0 : \
+ (x==PIN_SPI1_SS1 ? 1 : \
+ (x==PIN_SPI1_SS2 ? 2 : \
+ (x==PIN_SPI1_SS3 ? 3 : \
+ -1)))))
+
+
+// These buttons are present only on the Freedom E300 Arty Dev Kit.
+#ifdef HAS_BOARD_BUTTONS
+#define BUTTON_0_OFFSET 15
+#define BUTTON_1_OFFSET 30
+#define BUTTON_2_OFFSET 31
+
+#define INT_DEVICE_BUTTON_0 (INT_GPIO_BASE + BUTTON_0_OFFSET)
+#define INT_DEVICE_BUTTON_1 (INT_GPIO_BASE + BUTTON_1_OFFSET)
+#define INT_DEVICE_BUTTON_2 (INT_GPIO_BASE + BUTTON_2_OFFSET)
+
+#endif
+
+#define HAS_HFXOSC 1
+#define HAS_LFROSC_BYPASS 1
+
+#define RTC_FREQ 32768
+
+void write_hex(int fd, unsigned long int hex);
+
+#endif /* _SIFIVE_HIFIVE1_H */
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/env/start.S b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/env/start.S new file mode 100644 index 000000000..ac24d5125 --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/env/start.S @@ -0,0 +1,110 @@ +// See LICENSE for license details.
+
+/* This is defined in sifive/platform.h, but that can't be included from
+ * assembly. */
+#define CLINT_CTRL_ADDR 0x02000000
+
+ .section .init
+ .globl _start
+ .type _start,@function
+
+_start:
+ .cfi_startproc
+ .cfi_undefined ra
+.option push
+.option norelax
+ la gp, __global_pointer$
+.option pop
+ la sp, _sp
+
+#if defined(ENABLE_SMP)
+ smp_pause(t0, t1)
+#endif
+
+ /* Load data section */
+ la a0, _data_lma
+ la a1, _data
+ la a2, _edata
+ bgeu a1, a2, 2f
+1:
+ lw t0, (a0)
+ sw t0, (a1)
+ addi a0, a0, 4
+ addi a1, a1, 4
+ bltu a1, a2, 1b
+2:
+
+ /* Clear bss section */
+ la a0, __bss_start
+ la a1, _end
+ bgeu a0, a1, 2f
+1:
+ sw zero, (a0)
+ addi a0, a0, 4
+ bltu a0, a1, 1b
+2:
+
+ /* Call global constructors */
+ la a0, __libc_fini_array
+ call atexit
+ call __libc_init_array
+
+#ifndef __riscv_float_abi_soft
+ /* Enable FPU */
+ li t0, MSTATUS_FS
+ csrs mstatus, t0
+ csrr t1, mstatus
+ and t1, t1, t0
+ beqz t1, 1f
+ fssr x0
+1:
+#endif
+
+#if defined(ENABLE_SMP)
+ smp_resume(t0, t1)
+
+ csrr a0, mhartid
+ bnez a0, 2f
+#endif
+
+ auipc ra, 0
+ addi sp, sp, -16
+#if __riscv_xlen == 32
+ sw ra, 8(sp)
+#else
+ sd ra, 8(sp)
+#endif
+
+ /* argc = argv = 0 */
+ li a0, 0
+ li a1, 0
+ call main
+ tail exit
+1:
+ j 1b
+
+#if defined(ENABLE_SMP)
+2:
+ la t0, trap_entry
+ csrw mtvec, t0
+
+ csrr a0, mhartid
+ la t1, _sp
+ slli t0, a0, 10
+ sub sp, t1, t0
+
+ auipc ra, 0
+ addi sp, sp, -16
+#if __riscv_xlen == 32
+ sw ra, 8(sp)
+#else
+ sd ra, 8(sp)
+#endif
+
+ call secondary_main
+ tail exit
+
+1:
+ j 1b
+#endif
+ .cfi_endproc
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/bits.h b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/bits.h new file mode 100644 index 000000000..54ea8a4a3 --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/bits.h @@ -0,0 +1,36 @@ +// See LICENSE for license details.
+#ifndef _RISCV_BITS_H
+#define _RISCV_BITS_H
+
+#define likely(x) __builtin_expect((x), 1)
+#define unlikely(x) __builtin_expect((x), 0)
+
+#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b))
+#define ROUNDDOWN(a, b) ((a)/(b)*(b))
+
+#define MAX(a, b) ((a) > (b) ? (a) : (b))
+#define MIN(a, b) ((a) < (b) ? (a) : (b))
+#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)
+
+#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1)))
+#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
+
+#define STR(x) XSTR(x)
+#define XSTR(x) #x
+
+#if __riscv_xlen == 64
+# define SLL32 sllw
+# define STORE sd
+# define LOAD ld
+# define LWU lwu
+# define LOG_REGBYTES 3
+#else
+# define SLL32 sll
+# define STORE sw
+# define LOAD lw
+# define LWU lw
+# define LOG_REGBYTES 2
+#endif
+#define REGBYTES (1 << LOG_REGBYTES)
+
+#endif
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/const.h b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/const.h new file mode 100644 index 000000000..fdd6fcae2 --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/const.h @@ -0,0 +1,18 @@ +// See LICENSE for license details.
+/* Derived from <linux/const.h> */
+
+#ifndef _SIFIVE_CONST_H
+#define _SIFIVE_CONST_H
+
+#ifdef __ASSEMBLER__
+#define _AC(X,Y) X
+#define _AT(T,X) X
+#else
+#define _AC(X,Y) (X##Y)
+#define _AT(T,X) ((T)(X))
+#endif /* !__ASSEMBLER__*/
+
+#define _BITUL(x) (_AC(1,UL) << (x))
+#define _BITULL(x) (_AC(1,ULL) << (x))
+
+#endif /* _SIFIVE_CONST_H */
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/devices/aon.h b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/devices/aon.h new file mode 100644 index 000000000..784153702 --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/devices/aon.h @@ -0,0 +1,88 @@ +// See LICENSE for license details.
+
+#ifndef _SIFIVE_AON_H
+#define _SIFIVE_AON_H
+
+/* Register offsets */
+
+#define AON_WDOGCFG 0x000
+#define AON_WDOGCOUNT 0x008
+#define AON_WDOGS 0x010
+#define AON_WDOGFEED 0x018
+#define AON_WDOGKEY 0x01C
+#define AON_WDOGCMP 0x020
+
+#define AON_RTCCFG 0x040
+#define AON_RTCLO 0x048
+#define AON_RTCHI 0x04C
+#define AON_RTCS 0x050
+#define AON_RTCCMP 0x060
+
+#define AON_BACKUP0 0x080
+#define AON_BACKUP1 0x084
+#define AON_BACKUP2 0x088
+#define AON_BACKUP3 0x08C
+#define AON_BACKUP4 0x090
+#define AON_BACKUP5 0x094
+#define AON_BACKUP6 0x098
+#define AON_BACKUP7 0x09C
+#define AON_BACKUP8 0x0A0
+#define AON_BACKUP9 0x0A4
+#define AON_BACKUP10 0x0A8
+#define AON_BACKUP11 0x0AC
+#define AON_BACKUP12 0x0B0
+#define AON_BACKUP13 0x0B4
+#define AON_BACKUP14 0x0B8
+#define AON_BACKUP15 0x0BC
+
+#define AON_PMUWAKEUPI0 0x100
+#define AON_PMUWAKEUPI1 0x104
+#define AON_PMUWAKEUPI2 0x108
+#define AON_PMUWAKEUPI3 0x10C
+#define AON_PMUWAKEUPI4 0x110
+#define AON_PMUWAKEUPI5 0x114
+#define AON_PMUWAKEUPI6 0x118
+#define AON_PMUWAKEUPI7 0x11C
+#define AON_PMUSLEEPI0 0x120
+#define AON_PMUSLEEPI1 0x124
+#define AON_PMUSLEEPI2 0x128
+#define AON_PMUSLEEPI3 0x12C
+#define AON_PMUSLEEPI4 0x130
+#define AON_PMUSLEEPI5 0x134
+#define AON_PMUSLEEPI6 0x138
+#define AON_PMUSLEEPI7 0x13C
+#define AON_PMUIE 0x140
+#define AON_PMUCAUSE 0x144
+#define AON_PMUSLEEP 0x148
+#define AON_PMUKEY 0x14C
+
+#define AON_LFROSC 0x070
+/* Constants */
+
+#define AON_WDOGKEY_VALUE 0x51F15E
+#define AON_WDOGFEED_VALUE 0xD09F00D
+
+#define AON_WDOGCFG_SCALE 0x0000000F
+#define AON_WDOGCFG_RSTEN 0x00000100
+#define AON_WDOGCFG_ZEROCMP 0x00000200
+#define AON_WDOGCFG_ENALWAYS 0x00001000
+#define AON_WDOGCFG_ENCOREAWAKE 0x00002000
+#define AON_WDOGCFG_CMPIP 0x10000000
+
+#define AON_RTCCFG_SCALE 0x0000000F
+#define AON_RTCCFG_ENALWAYS 0x00001000
+#define AON_RTCCFG_CMPIP 0x10000000
+
+#define AON_WAKEUPCAUSE_RESET 0x00
+#define AON_WAKEUPCAUSE_RTC 0x01
+#define AON_WAKEUPCAUSE_DWAKEUP 0x02
+#define AON_WAKEUPCAUSE_AWAKEUP 0x03
+
+#define AON_RESETCAUSE_POWERON 0x0000
+#define AON_RESETCAUSE_EXTERNAL 0x0100
+#define AON_RESETCAUSE_WATCHDOG 0x0200
+
+#define AON_PMUCAUSE_WAKEUPCAUSE 0x00FF
+#define AON_PMUCAUSE_RESETCAUSE 0xFF00
+
+#endif /* _SIFIVE_AON_H */
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/devices/clint.h b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/devices/clint.h new file mode 100644 index 000000000..057ba0205 --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/devices/clint.h @@ -0,0 +1,14 @@ +// See LICENSE for license details
+
+#ifndef _SIFIVE_CLINT_H
+#define _SIFIVE_CLINT_H
+
+
+#define CLINT_MSIP 0x0000
+#define CLINT_MSIP_size 0x4
+#define CLINT_MTIMECMP 0x4000
+#define CLINT_MTIMECMP_size 0x8
+#define CLINT_MTIME 0xBFF8
+#define CLINT_MTIME_size 0x8
+
+#endif /* _SIFIVE_CLINT_H */
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/devices/gpio.h b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/devices/gpio.h new file mode 100644 index 000000000..69239de9b --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/devices/gpio.h @@ -0,0 +1,24 @@ +// See LICENSE for license details.
+
+#ifndef _SIFIVE_GPIO_H
+#define _SIFIVE_GPIO_H
+
+#define GPIO_INPUT_VAL (0x00)
+#define GPIO_INPUT_EN (0x04)
+#define GPIO_OUTPUT_EN (0x08)
+#define GPIO_OUTPUT_VAL (0x0C)
+#define GPIO_PULLUP_EN (0x10)
+#define GPIO_DRIVE (0x14)
+#define GPIO_RISE_IE (0x18)
+#define GPIO_RISE_IP (0x1C)
+#define GPIO_FALL_IE (0x20)
+#define GPIO_FALL_IP (0x24)
+#define GPIO_HIGH_IE (0x28)
+#define GPIO_HIGH_IP (0x2C)
+#define GPIO_LOW_IE (0x30)
+#define GPIO_LOW_IP (0x34)
+#define GPIO_IOF_EN (0x38)
+#define GPIO_IOF_SEL (0x3C)
+#define GPIO_OUTPUT_XOR (0x40)
+
+#endif /* _SIFIVE_GPIO_H */
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/devices/otp.h b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/devices/otp.h new file mode 100644 index 000000000..2482518f1 --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/devices/otp.h @@ -0,0 +1,23 @@ +// See LICENSE for license details.
+
+#ifndef _SIFIVE_OTP_H
+#define _SIFIVE_OTP_H
+
+/* Register offsets */
+
+#define OTP_LOCK 0x00
+#define OTP_CK 0x04
+#define OTP_OE 0x08
+#define OTP_SEL 0x0C
+#define OTP_WE 0x10
+#define OTP_MR 0x14
+#define OTP_MRR 0x18
+#define OTP_MPP 0x1C
+#define OTP_VRREN 0x20
+#define OTP_VPPEN 0x24
+#define OTP_A 0x28
+#define OTP_D 0x2C
+#define OTP_Q 0x30
+#define OTP_READ_TIMINGS 0x34
+
+#endif
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/devices/plic.h b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/devices/plic.h new file mode 100644 index 000000000..494e04e01 --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/devices/plic.h @@ -0,0 +1,31 @@ +// See LICENSE for license details.
+
+#ifndef PLIC_H
+#define PLIC_H
+
+#include <sifive/const.h>
+
+// 32 bits per source
+#define PLIC_PRIORITY_OFFSET _AC(0x0000,UL)
+#define PLIC_PRIORITY_SHIFT_PER_SOURCE 2
+// 1 bit per source (1 address)
+#define PLIC_PENDING_OFFSET _AC(0x1000,UL)
+#define PLIC_PENDING_SHIFT_PER_SOURCE 0
+
+//0x80 per target
+#define PLIC_ENABLE_OFFSET _AC(0x2000,UL)
+#define PLIC_ENABLE_SHIFT_PER_TARGET 7
+
+
+#define PLIC_THRESHOLD_OFFSET _AC(0x200000,UL)
+#define PLIC_CLAIM_OFFSET _AC(0x200004,UL)
+#define PLIC_THRESHOLD_SHIFT_PER_TARGET 12
+#define PLIC_CLAIM_SHIFT_PER_TARGET 12
+
+#define PLIC_MAX_SOURCE 1023
+#define PLIC_SOURCE_MASK 0x3FF
+
+#define PLIC_MAX_TARGET 15871
+#define PLIC_TARGET_MASK 0x3FFF
+
+#endif /* PLIC_H */
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/devices/prci.h b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/devices/prci.h new file mode 100644 index 000000000..582863cdc --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/devices/prci.h @@ -0,0 +1,56 @@ +// See LICENSE for license details.
+
+#ifndef _SIFIVE_PRCI_H
+#define _SIFIVE_PRCI_H
+
+/* Register offsets */
+
+#define PRCI_HFROSCCFG (0x0000)
+#define PRCI_HFXOSCCFG (0x0004)
+#define PRCI_PLLCFG (0x0008)
+#define PRCI_PLLDIV (0x000C)
+#define PRCI_PROCMONCFG (0x00F0)
+
+/* Fields */
+#define ROSC_DIV(x) (((x) & 0x2F) << 0 )
+#define ROSC_TRIM(x) (((x) & 0x1F) << 16)
+#define ROSC_EN(x) (((x) & 0x1 ) << 30)
+#define ROSC_RDY(x) (((x) & 0x1 ) << 31)
+
+#define XOSC_EN(x) (((x) & 0x1) << 30)
+#define XOSC_RDY(x) (((x) & 0x1) << 31)
+
+#define PLL_R(x) (((x) & 0x7) << 0)
+// single reserved bit for F LSB.
+#define PLL_F(x) (((x) & 0x3F) << 4)
+#define PLL_Q(x) (((x) & 0x3) << 10)
+#define PLL_SEL(x) (((x) & 0x1) << 16)
+#define PLL_REFSEL(x) (((x) & 0x1) << 17)
+#define PLL_BYPASS(x) (((x) & 0x1) << 18)
+#define PLL_LOCK(x) (((x) & 0x1) << 31)
+
+#define PLL_R_default 0x1
+#define PLL_F_default 0x1F
+#define PLL_Q_default 0x3
+
+#define PLL_REFSEL_HFROSC 0x0
+#define PLL_REFSEL_HFXOSC 0x1
+
+#define PLL_SEL_HFROSC 0x0
+#define PLL_SEL_PLL 0x1
+
+#define PLL_FINAL_DIV(x) (((x) & 0x3F) << 0)
+#define PLL_FINAL_DIV_BY_1(x) (((x) & 0x1 ) << 8)
+
+#define PROCMON_DIV(x) (((x) & 0x1F) << 0)
+#define PROCMON_TRIM(x) (((x) & 0x1F) << 8)
+#define PROCMON_EN(x) (((x) & 0x1) << 16)
+#define PROCMON_SEL(x) (((x) & 0x3) << 24)
+#define PROCMON_NT_EN(x) (((x) & 0x1) << 28)
+
+#define PROCMON_SEL_HFCLK 0
+#define PROCMON_SEL_HFXOSCIN 1
+#define PROCMON_SEL_PLLOUTDIV 2
+#define PROCMON_SEL_PROCMON 3
+
+#endif // _SIFIVE_PRCI_H
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/devices/pwm.h b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/devices/pwm.h new file mode 100644 index 000000000..3c5f704fa --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/devices/pwm.h @@ -0,0 +1,37 @@ +// See LICENSE for license details.
+
+#ifndef _SIFIVE_PWM_H
+#define _SIFIVE_PWM_H
+
+/* Register offsets */
+
+#define PWM_CFG 0x00
+#define PWM_COUNT 0x08
+#define PWM_S 0x10
+#define PWM_CMP0 0x20
+#define PWM_CMP1 0x24
+#define PWM_CMP2 0x28
+#define PWM_CMP3 0x2C
+
+/* Constants */
+
+#define PWM_CFG_SCALE 0x0000000F
+#define PWM_CFG_STICKY 0x00000100
+#define PWM_CFG_ZEROCMP 0x00000200
+#define PWM_CFG_DEGLITCH 0x00000400
+#define PWM_CFG_ENALWAYS 0x00001000
+#define PWM_CFG_ONESHOT 0x00002000
+#define PWM_CFG_CMP0CENTER 0x00010000
+#define PWM_CFG_CMP1CENTER 0x00020000
+#define PWM_CFG_CMP2CENTER 0x00040000
+#define PWM_CFG_CMP3CENTER 0x00080000
+#define PWM_CFG_CMP0GANG 0x01000000
+#define PWM_CFG_CMP1GANG 0x02000000
+#define PWM_CFG_CMP2GANG 0x04000000
+#define PWM_CFG_CMP3GANG 0x08000000
+#define PWM_CFG_CMP0IP 0x10000000
+#define PWM_CFG_CMP1IP 0x20000000
+#define PWM_CFG_CMP2IP 0x40000000
+#define PWM_CFG_CMP3IP 0x80000000
+
+#endif /* _SIFIVE_PWM_H */
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/devices/spi.h b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/devices/spi.h new file mode 100644 index 000000000..e3c1d35af --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/devices/spi.h @@ -0,0 +1,80 @@ +// See LICENSE for license details.
+
+#ifndef _SIFIVE_SPI_H
+#define _SIFIVE_SPI_H
+
+/* Register offsets */
+
+#define SPI_REG_SCKDIV 0x00
+#define SPI_REG_SCKMODE 0x04
+#define SPI_REG_CSID 0x10
+#define SPI_REG_CSDEF 0x14
+#define SPI_REG_CSMODE 0x18
+
+#define SPI_REG_DCSSCK 0x28
+#define SPI_REG_DSCKCS 0x2a
+#define SPI_REG_DINTERCS 0x2c
+#define SPI_REG_DINTERXFR 0x2e
+
+#define SPI_REG_FMT 0x40
+#define SPI_REG_TXFIFO 0x48
+#define SPI_REG_RXFIFO 0x4c
+#define SPI_REG_TXCTRL 0x50
+#define SPI_REG_RXCTRL 0x54
+
+#define SPI_REG_FCTRL 0x60
+#define SPI_REG_FFMT 0x64
+
+#define SPI_REG_IE 0x70
+#define SPI_REG_IP 0x74
+
+/* Fields */
+
+#define SPI_SCK_PHA 0x1
+#define SPI_SCK_POL 0x2
+
+#define SPI_FMT_PROTO(x) ((x) & 0x3)
+#define SPI_FMT_ENDIAN(x) (((x) & 0x1) << 2)
+#define SPI_FMT_DIR(x) (((x) & 0x1) << 3)
+#define SPI_FMT_LEN(x) (((x) & 0xf) << 16)
+
+/* TXCTRL register */
+#define SPI_TXWM(x) ((x) & 0xffff)
+/* RXCTRL register */
+#define SPI_RXWM(x) ((x) & 0xffff)
+
+#define SPI_IP_TXWM 0x1
+#define SPI_IP_RXWM 0x2
+
+#define SPI_FCTRL_EN 0x1
+
+#define SPI_INSN_CMD_EN 0x1
+#define SPI_INSN_ADDR_LEN(x) (((x) & 0x7) << 1)
+#define SPI_INSN_PAD_CNT(x) (((x) & 0xf) << 4)
+#define SPI_INSN_CMD_PROTO(x) (((x) & 0x3) << 8)
+#define SPI_INSN_ADDR_PROTO(x) (((x) & 0x3) << 10)
+#define SPI_INSN_DATA_PROTO(x) (((x) & 0x3) << 12)
+#define SPI_INSN_CMD_CODE(x) (((x) & 0xff) << 16)
+#define SPI_INSN_PAD_CODE(x) (((x) & 0xff) << 24)
+
+#define SPI_TXFIFO_FULL (1 << 31)
+#define SPI_RXFIFO_EMPTY (1 << 31)
+
+/* Values */
+
+#define SPI_CSMODE_AUTO 0
+#define SPI_CSMODE_HOLD 2
+#define SPI_CSMODE_OFF 3
+
+#define SPI_DIR_RX 0
+#define SPI_DIR_TX 1
+
+#define SPI_PROTO_S 0
+#define SPI_PROTO_D 1
+#define SPI_PROTO_Q 2
+
+#define SPI_ENDIAN_MSB 0
+#define SPI_ENDIAN_LSB 1
+
+
+#endif /* _SIFIVE_SPI_H */
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/devices/uart.h b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/devices/uart.h new file mode 100644 index 000000000..ce9fd01ca --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/devices/uart.h @@ -0,0 +1,27 @@ +// See LICENSE for license details.
+
+#ifndef _SIFIVE_UART_H
+#define _SIFIVE_UART_H
+
+/* Register offsets */
+#define UART_REG_TXFIFO 0x00
+#define UART_REG_RXFIFO 0x04
+#define UART_REG_TXCTRL 0x08
+#define UART_REG_RXCTRL 0x0c
+#define UART_REG_IE 0x10
+#define UART_REG_IP 0x14
+#define UART_REG_DIV 0x18
+
+/* TXCTRL register */
+#define UART_TXEN 0x1
+#define UART_TXWM(x) (((x) & 0xffff) << 16)
+
+/* RXCTRL register */
+#define UART_RXEN 0x1
+#define UART_RXWM(x) (((x) & 0xffff) << 16)
+
+/* IP register */
+#define UART_IP_TXWM 0x1
+#define UART_IP_RXWM 0x2
+
+#endif /* _SIFIVE_UART_H */
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/sections.h b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/sections.h new file mode 100644 index 000000000..bcbf9f820 --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/sections.h @@ -0,0 +1,17 @@ +// See LICENSE for license details.
+#ifndef _SECTIONS_H
+#define _SECTIONS_H
+
+extern unsigned char _rom[];
+extern unsigned char _rom_end[];
+
+extern unsigned char _ram[];
+extern unsigned char _ram_end[];
+
+extern unsigned char _ftext[];
+extern unsigned char _etext[];
+extern unsigned char _fbss[];
+extern unsigned char _ebss[];
+extern unsigned char _end[];
+
+#endif /* _SECTIONS_H */
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/smp.h b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/smp.h new file mode 100644 index 000000000..8e7d4857a --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/include/sifive/smp.h @@ -0,0 +1,65 @@ +#ifndef SIFIVE_SMP
+#define SIFIVE_SMP
+
+// The maximum number of HARTs this code supports
+#ifndef MAX_HARTS
+#define MAX_HARTS 32
+#endif
+#define CLINT_END_HART_IPI CLINT_CTRL_ADDR + (MAX_HARTS*4)
+
+// The hart that non-SMP tests should run on
+#ifndef NONSMP_HART
+#define NONSMP_HART 0
+#endif
+
+/* If your test cannot handle multiple-threads, use this:
+ * smp_disable(reg1)
+ */
+#define smp_disable(reg1, reg2) \
+ csrr reg1, mhartid ;\
+ li reg2, NONSMP_HART ;\
+ beq reg1, reg2, hart0_entry ;\
+42: ;\
+ wfi ;\
+ j 42b ;\
+hart0_entry:
+
+/* If your test needs to temporarily block multiple-threads, do this:
+ * smp_pause(reg1, reg2)
+ * ... single-threaded work ...
+ * smp_resume(reg1, reg2)
+ * ... multi-threaded work ...
+ */
+
+#define smp_pause(reg1, reg2) \
+ li reg2, 0x8 ;\
+ csrw mie, reg2 ;\
+ csrr reg2, mhartid ;\
+ bnez reg2, 42f
+
+#define smp_resume(reg1, reg2) \
+ li reg1, CLINT_CTRL_ADDR ;\
+41: ;\
+ li reg2, 1 ;\
+ sw reg2, 0(reg1) ;\
+ addi reg1, reg1, 4 ;\
+ li reg2, CLINT_END_HART_IPI ;\
+ blt reg1, reg2, 41b ;\
+42: ;\
+ wfi ;\
+ csrr reg2, mip ;\
+ andi reg2, reg2, 0x8 ;\
+ beqz reg2, 42b ;\
+ li reg1, CLINT_CTRL_ADDR ;\
+ csrr reg2, mhartid ;\
+ slli reg2, reg2, 2 ;\
+ add reg2, reg2, reg1 ;\
+ sw zero, 0(reg2) ;\
+41: ;\
+ lw reg2, 0(reg1) ;\
+ bnez reg2, 41b ;\
+ addi reg1, reg1, 4 ;\
+ li reg2, CLINT_END_HART_IPI ;\
+ blt reg1, reg2, 41b
+
+#endif
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/misc/write_hex.c b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/misc/write_hex.c new file mode 100644 index 000000000..4d25241f8 --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/misc/write_hex.c @@ -0,0 +1,19 @@ +/* See LICENSE of license details. */
+
+#include <stdint.h>
+#include <unistd.h>
+#include "platform.h"
+
+void write_hex(int fd, unsigned long int hex)
+{
+ uint8_t ii;
+ uint8_t jj;
+ char towrite;
+ write(fd , "0x", 2);
+ for (ii = sizeof(unsigned long int) * 2 ; ii > 0; ii--) {
+ jj = ii - 1;
+ uint8_t digit = ((hex & (0xF << (jj*4))) >> (jj*4));
+ towrite = digit < 0xA ? ('0' + digit) : ('A' + (digit - 0xA));
+ write(fd, &towrite, 1);
+ }
+}
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/stdlib/malloc.c b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/stdlib/malloc.c new file mode 100644 index 000000000..871766fb7 --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/stdlib/malloc.c @@ -0,0 +1,17 @@ +/* See LICENSE for license details. */
+
+/* These functions are intended for embedded RV32 systems and are
+ obviously incorrect in general. */
+
+void* __wrap_malloc(unsigned long sz)
+{
+ extern void* sbrk(long);
+ void* res = sbrk(sz);
+ if ((long)res == -1)
+ return 0;
+ return res;
+}
+
+void __wrap_free(void* ptr)
+{
+}
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/_exit.c b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/_exit.c new file mode 100644 index 000000000..89b0b3d62 --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/_exit.c @@ -0,0 +1,17 @@ +/* See LICENSE of license details. */
+
+#include <unistd.h>
+#include "platform.h"
+#include "weak_under_alias.h"
+
+void __wrap_exit(int code)
+{
+ const char message[] = "\nProgam has exited with code:";
+
+ write(STDERR_FILENO, message, sizeof(message) - 1);
+ write_hex(STDERR_FILENO, code);
+ write(STDERR_FILENO, "\n", 1);
+
+ for (;;);
+}
+weak_under_alias(exit);
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/close.c b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/close.c new file mode 100644 index 000000000..fe2dd779e --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/close.c @@ -0,0 +1,11 @@ +/* See LICENSE of license details. */
+
+#include <errno.h>
+#include "stub.h"
+#include "weak_under_alias.h"
+
+int __wrap_close(int fd)
+{
+ return _stub(EBADF);
+}
+weak_under_alias(close);
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/execve.c b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/execve.c new file mode 100644 index 000000000..508ae21be --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/execve.c @@ -0,0 +1,11 @@ +/* See LICENSE of license details. */
+
+#include <errno.h>
+#include "stub.h"
+#include "weak_under_alias.h"
+
+int __wrap_execve(const char* name, char* const argv[], char* const env[])
+{
+ return _stub(ENOMEM);
+}
+weak_under_alias(execve);
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/fork.c b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/fork.c new file mode 100644 index 000000000..3f05a67fc --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/fork.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */
+
+#include <errno.h>
+#include "stub.h"
+
+int fork(void)
+{
+ return _stub(EAGAIN);
+}
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/fstat.c b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/fstat.c new file mode 100644 index 000000000..8de6b8c2c --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/fstat.c @@ -0,0 +1,18 @@ +/* See LICENSE of license details. */
+
+#include <errno.h>
+#include <unistd.h>
+#include <sys/stat.h>
+#include "stub.h"
+#include "weak_under_alias.h"
+
+int __wrap_fstat(int fd, struct stat* st)
+{
+ if (isatty(fd)) {
+ st->st_mode = S_IFCHR;
+ return 0;
+ }
+
+ return _stub(EBADF);
+}
+weak_under_alias(fstat);
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/getpid.c b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/getpid.c new file mode 100644 index 000000000..8b2a7c729 --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/getpid.c @@ -0,0 +1,8 @@ +/* See LICENSE of license details. */
+#include "weak_under_alias.h"
+
+int __wrap_getpid(void)
+{
+ return 1;
+}
+weak_under_alias(getpid);
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/isatty.c b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/isatty.c new file mode 100644 index 000000000..d65f932ff --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/isatty.c @@ -0,0 +1,13 @@ +/* See LICENSE of license details. */
+
+#include <unistd.h>
+#include "weak_under_alias.h"
+
+int __wrap_isatty(int fd)
+{
+ if (fd == STDOUT_FILENO || fd == STDERR_FILENO)
+ return 1;
+
+ return 0;
+}
+weak_under_alias(isatty);
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/kill.c b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/kill.c new file mode 100644 index 000000000..fe1fa620c --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/kill.c @@ -0,0 +1,11 @@ +/* See LICENSE of license details. */
+
+#include <errno.h>
+#include "stub.h"
+#include "weak_under_alias.h"
+
+int __wrap_kill(int pid, int sig)
+{
+ return _stub(EINVAL);
+}
+weak_under_alias(kill);
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/link.c b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/link.c new file mode 100644 index 000000000..eeac5b91e --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/link.c @@ -0,0 +1,11 @@ +/* See LICENSE of license details. */
+
+#include <errno.h>
+#include "stub.h"
+#include "weak_under_alias.h"
+
+int __wrap_link(const char *old_name, const char *new_name)
+{
+ return _stub(EMLINK);
+}
+weak_under_alias(link);
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/lseek.c b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/lseek.c new file mode 100644 index 000000000..81b2b78af --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/lseek.c @@ -0,0 +1,16 @@ +/* See LICENSE of license details. */
+
+#include <errno.h>
+#include <unistd.h>
+#include <sys/types.h>
+#include "stub.h"
+#include "weak_under_alias.h"
+
+off_t __wrap_lseek(int fd, off_t ptr, int dir)
+{
+ if (isatty(fd))
+ return 0;
+
+ return _stub(EBADF);
+}
+weak_under_alias(lseek);
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/open.c b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/open.c new file mode 100644 index 000000000..8b74f2a21 --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/open.c @@ -0,0 +1,11 @@ +/* See LICENSE of license details. */
+
+#include <errno.h>
+#include "stub.h"
+#include "weak_under_alias.h"
+
+int __wrap_open(const char* name, int flags, int mode)
+{
+ return _stub(ENOENT);
+}
+weak_under_alias(open);
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/openat.c b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/openat.c new file mode 100644 index 000000000..687e0e2b7 --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/openat.c @@ -0,0 +1,11 @@ +/* See LICENSE of license details. */
+
+#include <errno.h>
+#include "stub.h"
+#include "weak_under_alias.h"
+
+int __wrap_openat(int dirfd, const char* name, int flags, int mode)
+{
+ return _stub(ENOENT);
+}
+weak_under_alias(openat);
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/puts.c b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/puts.c new file mode 100644 index 000000000..45c05c0ad --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/puts.c @@ -0,0 +1,28 @@ +/* See LICENSE of license details. */
+
+#include <stdint.h>
+#include <errno.h>
+#include <unistd.h>
+#include <sys/types.h>
+
+#include "platform.h"
+#include "stub.h"
+#include "weak_under_alias.h"
+
+int __wrap_puts(const char *s)
+{
+ while (*s != '\0') {
+ while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
+ UART0_REG(UART_REG_TXFIFO) = *s;
+
+ if (*s == '\n') {
+ while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
+ UART0_REG(UART_REG_TXFIFO) = '\r';
+ }
+
+ ++s;
+ }
+
+ return 0;
+}
+weak_under_alias(puts);
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/read.c b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/read.c new file mode 100644 index 000000000..08d0ab55d --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/read.c @@ -0,0 +1,32 @@ +/* See LICENSE of license details. */
+
+#include <stdint.h>
+#include <errno.h>
+#include <unistd.h>
+#include <sys/types.h>
+
+#include "platform.h"
+#include "stub.h"
+#include "weak_under_alias.h"
+
+ssize_t __wrap_read(int fd, void* ptr, size_t len)
+{
+ uint8_t * current = (uint8_t *)ptr;
+ volatile uint32_t * uart_rx = (uint32_t *)(UART0_CTRL_ADDR + UART_REG_RXFIFO);
+ volatile uint8_t * uart_rx_cnt = (uint8_t *)(UART0_CTRL_ADDR + UART_REG_RXCTRL + 2);
+
+ ssize_t result = 0;
+
+ if (isatty(fd)) {
+ for (current = (uint8_t *)ptr;
+ (current < ((uint8_t *)ptr) + len) && (*uart_rx_cnt > 0);
+ current ++) {
+ *current = *uart_rx;
+ result++;
+ }
+ return result;
+ }
+
+ return _stub(EBADF);
+}
+weak_under_alias(read);
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/sbrk.c b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/sbrk.c new file mode 100644 index 000000000..451bc27c7 --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/sbrk.c @@ -0,0 +1,18 @@ +/* See LICENSE of license details. */
+
+#include <stddef.h>
+#include "weak_under_alias.h"
+
+void *__wrap_sbrk(ptrdiff_t incr)
+{
+ extern char _end[];
+ extern char _heap_end[];
+ static char *curbrk = _end;
+
+ if ((curbrk + incr < _end) || (curbrk + incr > _heap_end))
+ return NULL - 1;
+
+ curbrk += incr;
+ return curbrk - incr;
+}
+weak_under_alias(sbrk);
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/stat.c b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/stat.c new file mode 100644 index 000000000..b950590a2 --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/stat.c @@ -0,0 +1,12 @@ +/* See LICENSE of license details. */
+
+#include <errno.h>
+#include <sys/stat.h>
+#include "stub.h"
+#include "weak_under_alias.h"
+
+int __wrap_stat(const char* file, struct stat* st)
+{
+ return _stub(EACCES);
+}
+weak_under_alias(stat);
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/stub.h b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/stub.h new file mode 100644 index 000000000..cebdddae2 --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/stub.h @@ -0,0 +1,10 @@ +/* See LICENSE of license details. */
+#ifndef _SIFIVE_SYS_STUB_H
+#define _SIFIVE_SYS_STUB_H
+
+static inline int _stub(int err)
+{
+ return -1;
+}
+
+#endif /* _SIFIVE_SYS_STUB_H */
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/times.c b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/times.c new file mode 100644 index 000000000..26e173775 --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/times.c @@ -0,0 +1,12 @@ +/* See LICENSE of license details. */
+
+#include <errno.h>
+#include <sys/times.h>
+#include "stub.h"
+#include "weak_under_alias.h"
+
+clock_t __wrap_times(struct tms* buf)
+{
+ return _stub(EACCES);
+}
+weak_under_alias(times);
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/unlink.c b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/unlink.c new file mode 100644 index 000000000..8e23464f7 --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/unlink.c @@ -0,0 +1,11 @@ +/* See LICENSE of license details. */
+
+#include <errno.h>
+#include "stub.h"
+#include "weak_under_alias.h"
+
+int __wrap_unlink(const char* name)
+{
+ return _stub(ENOENT);
+}
+weak_under_alias(unlink);
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/wait.c b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/wait.c new file mode 100644 index 000000000..bb566e600 --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/wait.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */
+
+#include <errno.h>
+#include "stub.h"
+
+int wait(int* status)
+{
+ return _stub(ECHILD);
+}
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/weak_under_alias.h b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/weak_under_alias.h new file mode 100644 index 000000000..402a223e3 --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/weak_under_alias.h @@ -0,0 +1,7 @@ +#ifndef _BSP_LIBWRAP_WEAK_UNDER_ALIAS_H
+#define _BSP_LIBWRAP_WEAK_UNDER_ALIAS_H
+
+#define weak_under_alias(name) \
+ extern __typeof (__wrap_##name) __wrap__##name __attribute__ ((weak, alias ("__wrap_"#name)))
+
+#endif
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/write.c b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/write.c new file mode 100644 index 000000000..c6ec5b42e --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/freedom-e-sdk/libwrap/sys/write.c @@ -0,0 +1,31 @@ +/* See LICENSE of license details. */
+
+#include <stdint.h>
+#include <errno.h>
+#include <unistd.h>
+#include <sys/types.h>
+
+#include "platform.h"
+#include "stub.h"
+#include "weak_under_alias.h"
+
+ssize_t __wrap_write(int fd, const void* ptr, size_t len)
+{
+ const uint8_t * current = (const uint8_t *)ptr;
+
+ if (isatty(fd)) {
+ for (size_t jj = 0; jj < len; jj++) {
+ while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
+ UART0_REG(UART_REG_TXFIFO) = current[jj];
+
+ if (current[jj] == '\n') {
+ while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
+ UART0_REG(UART_REG_TXFIFO) = '\r';
+ }
+ }
+ return len;
+ }
+
+ return _stub(EBADF);
+}
+weak_under_alias(write);
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/full_demo/RegTest.S b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/full_demo/RegTest.S new file mode 100644 index 000000000..8eef086e6 --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/full_demo/RegTest.S @@ -0,0 +1,266 @@ +/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+ .extern ulRegTest1LoopCounter
+ .extern ulRegTest2LoopCounter
+
+ .global vRegTest1Implementation
+ .global vRegTest2Implementation
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The register check tasks are described in the comments at the top of
+ * main_full.c.
+ */
+
+.align( 8 )
+vRegTest1Implementation:
+
+ /* Fill the core registers with known values. */
+ li x5, 0x5
+ li x6, 0x6
+ li x7, 0x7
+ li x8, 0x8
+ li x9, 0x9
+ li x10, 0xa
+ li x11, 0xb
+ li x12, 0xc
+ li x13, 0xd
+ li x14, 0xe
+ li x15, 0xf
+ li x16, 0x10
+ li x17, 0x11
+ li x18, 0x12
+ li x19, 0x13
+ li x20, 0x14
+ li x21, 0x15
+ li x22, 0x16
+ li x23, 0x17
+ li x24, 0x18
+ li x25, 0x19
+ li x26, 0x1a
+ li x27, 0x1b
+ li x28, 0x1c
+ li x29, 0x1d
+ li x30, 0x1e
+
+reg1_loop:
+
+ /* Check each register still contains the expected known value.
+ vRegTest1Implementation uses x31 as the temporary, vRegTest2Implementation
+ uses x5 as the temporary. */
+ li x31, 0x5
+ bne x31, x5, reg1_error_loop
+ li x31, 0x6
+ bne x31, x6, reg1_error_loop
+ li x31, 0x7
+ bne x31, x7, reg1_error_loop
+ li x31, 0x8
+ bne x31, x8, reg1_error_loop
+ li x31, 0x9
+ bne x31, x9, reg1_error_loop
+ li x31, 0xa
+ bne x31, x10, reg1_error_loop
+ li x31, 0xb
+ bne x31, x11, reg1_error_loop
+ li x31, 0xc
+ bne x31, x12, reg1_error_loop
+ li x31, 0xd
+ bne x31, x13, reg1_error_loop
+ li x31, 0xe
+ bne x31, x14, reg1_error_loop
+ li x31, 0xf
+ bne x31, x15, reg1_error_loop
+ li x31, 0x10
+ bne x31, x16, reg1_error_loop
+ li x31, 0x11
+ bne x31, x17, reg1_error_loop
+ li x31, 0x12
+ bne x31, x18, reg1_error_loop
+ li x31, 0x13
+ bne x31, x19, reg1_error_loop
+ li x31, 0x14
+ bne x31, x20, reg1_error_loop
+ li x31, 0x15
+ bne x31, x21, reg1_error_loop
+ li x31, 0x16
+ bne x31, x22, reg1_error_loop
+ li x31, 0x17
+ bne x31, x23, reg1_error_loop
+ li x31, 0x18
+ bne x31, x24, reg1_error_loop
+ li x31, 0x19
+ bne x31, x25, reg1_error_loop
+ li x31, 0x1a
+ bne x31, x26, reg1_error_loop
+ li x31, 0x1b
+ bne x31, x27, reg1_error_loop
+ li x31, 0x1c
+ bne x31, x28, reg1_error_loop
+ li x31, 0x1d
+ bne x31, x29, reg1_error_loop
+ li x31, 0x1e
+ bne x31, x30, reg1_error_loop
+
+ /* Everything passed, increment the loop counter. */
+ lw x31, ulRegTest1LoopCounterConst
+ lw x30, 0(x31)
+ addi x30, x30, 1
+ sw x30, 0(x31)
+
+ /* Restore clobbered register reading for next loop. */
+ li x30, 0x1e
+
+ /* Yield to increase code coverage. */
+ ecall
+
+ /* Start again. */
+ jal reg1_loop
+
+reg1_error_loop:
+ /* Jump here if a register contains an uxpected value. This stops the loop
+ counter being incremented so the check task knows an error was found. */
+ ebreak
+ jal reg1_error_loop
+
+.align( 16 )
+ulRegTest1LoopCounterConst: .word ulRegTest1LoopCounter
+
+/*-----------------------------------------------------------*/
+
+.align( 8 )
+vRegTest2Implementation:
+
+ /* Fill the core registers with known values. */
+ li x6, 0x61
+ li x7, 0x71
+ li x8, 0x81
+ li x9, 0x91
+ li x10, 0xa1
+ li x11, 0xb1
+ li x12, 0xc1
+ li x13, 0xd1
+ li x14, 0xe1
+ li x15, 0xf1
+ li x16, 0x20
+ li x17, 0x21
+ li x18, 0x22
+ li x19, 0x23
+ li x20, 0x24
+ li x21, 0x25
+ li x22, 0x26
+ li x23, 0x27
+ li x24, 0x28
+ li x25, 0x29
+ li x26, 0x2a
+ li x27, 0x2b
+ li x28, 0x2c
+ li x29, 0x2d
+ li x30, 0x2e
+ li x31, 0x2f
+
+Reg2_loop:
+
+ /* Check each register still contains the expected known value.
+ vRegTest2Implementation uses x5 as the temporary, vRegTest1Implementation
+ uses x31 as the temporary. */
+ li x5, 0x61
+ bne x5, x6, reg2_error_loop
+ li x5, 0x71
+ bne x5, x7, reg2_error_loop
+ li x5, 0x81
+ bne x5, x8, reg2_error_loop
+ li x5, 0x91
+ bne x5, x9, reg2_error_loop
+ li x5, 0xa1
+ bne x5, x10, reg2_error_loop
+ li x5, 0xb1
+ bne x5, x11, reg2_error_loop
+ li x5, 0xc1
+ bne x5, x12, reg2_error_loop
+ li x5, 0xd1
+ bne x5, x13, reg2_error_loop
+ li x5, 0xe1
+ bne x5, x14, reg2_error_loop
+ li x5, 0xf1
+ bne x5, x15, reg2_error_loop
+ li x5, 0x20
+ bne x5, x16, reg2_error_loop
+ li x5, 0x21
+ bne x5, x17, reg2_error_loop
+ li x5, 0x22
+ bne x5, x18, reg2_error_loop
+ li x5, 0x23
+ bne x5, x19, reg2_error_loop
+ li x5, 0x24
+ bne x5, x20, reg2_error_loop
+ li x5, 0x25
+ bne x5, x21, reg2_error_loop
+ li x5, 0x26
+ bne x5, x22, reg2_error_loop
+ li x5, 0x27
+ bne x5, x23, reg2_error_loop
+ li x5, 0x28
+ bne x5, x24, reg2_error_loop
+ li x5, 0x29
+ bne x5, x25, reg2_error_loop
+ li x5, 0x2a
+ bne x5, x26, reg2_error_loop
+ li x5, 0x2b
+ bne x5, x27, reg2_error_loop
+ li x5, 0x2c
+ bne x5, x28, reg2_error_loop
+ li x5, 0x2d
+ bne x5, x29, reg2_error_loop
+ li x5, 0x2e
+ bne x5, x30, reg2_error_loop
+ li x5, 0x2f
+ bne x5, x31, reg2_error_loop
+
+ /* Everything passed, increment the loop counter. */
+ lw x5, ulRegTest2LoopCounterConst
+ lw x6, 0(x5)
+ addi x6, x6, 1
+ sw x6, 0(x5)
+
+ /* Restore clobbered register reading for next loop. */
+ li x6, 0x61
+
+ /* Start again. */
+ jal Reg2_loop
+
+reg2_error_loop:
+ /* Jump here if a register contains an uxpected value. This stops the loop
+ counter being incremented so the check task knows an error was found. */
+ ebreak
+ jal reg2_error_loop
+
+.align( 16 )
+ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter
+
+
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/full_demo/main_full.c b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/full_demo/main_full.c new file mode 100644 index 000000000..6c053a7ff --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/full_demo/main_full.c @@ -0,0 +1,319 @@ +/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/******************************************************************************
+ * NOTE 1: This project provides two demo applications. A simple blinky style
+ * project, and a more comprehensive test and demo application. The
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
+ * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
+ * in main.c. This file implements the comprehensive test and demo version.
+ *
+ * NOTE 2: This file only contains the source code that is specific to the
+ * full demo. Generic functions, such FreeRTOS hook functions, and functions
+ * required to configure the hardware, are defined in main.c.
+ *
+ ******************************************************************************
+ *
+ * main_full() creates all the demo application tasks and software timers, then
+ * starts the scheduler. The web documentation provides more details of the
+ * standard demo application tasks, which provide no particular functionality,
+ * but do provide a good example of how to use the FreeRTOS API.
+ *
+ * In addition to the standard demo tasks, the following tasks and tests are
+ * defined and/or created within this file:
+ *
+ * "Reg test" tasks - These fill both the core registers with known values, then
+ * check that each register maintains its expected value for the lifetime of the
+ * task. Each task uses a different set of values. The reg test tasks execute
+ * with a very low priority, so get preempted very frequently. A register
+ * containing an unexpected value is indicative of an error in the context
+ * switching mechanism.
+ *
+ * "Check" task - The check executes every five seconds. It checks that all
+ * the standard demo tasks, and the register check tasks, are not only still
+ * executing, but are executing without reporting any errors. If the check task
+ * discovers that a task has either stalled, or reported an error, then it
+ * prints an error message to the UART, otherwise it prints "Pass" followed
+ * by an additional period (".") after each successful loop of its implementing
+ * function.
+ */
+
+/* Standard includes. */
+#include <stdio.h>
+#include <string.h>
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "semphr.h"
+
+/* Standard demo application includes. */
+#include "dynamic.h"
+#include "blocktim.h"
+#include "GenQTest.h"
+#include "recmutex.h"
+#include "TimerDemo.h"
+#include "EventGroupsDemo.h"
+#include "TaskNotify.h"
+
+/* SiFive includes. */
+#include "platform.h"
+#include "encoding.h"
+#include "unistd.h"
+
+/* Priorities for the demo application tasks. */
+#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
+
+/* The period of the check task, in ms, converted to ticks using the
+pdMS_TO_TICKS() macro. */
+#define mainNO_ERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( 5000UL )
+
+/* Parameters that are passed into the register check tasks solely for the
+purpose of ensuring parameters are passed into tasks correctl5. */
+#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 )
+#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 )
+
+/* The base period used by the timer test tasks. */
+#define mainTIMER_TEST_PERIOD ( 50 )
+
+/* The size of the stack allocated to the check task (as described in the
+comments at the top of this file. */
+#define mainCHECK_TASK_STACK_SIZE_WORDS 85
+
+/* Size of the stacks to allocated for the register check tasks. */
+#define mainREG_TEST_STACK_SIZE_WORDS 50
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Called by main() to run the full demo (as opposed to the blinky demo) when
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.
+ */
+void main_full( void );
+
+/*
+ * The check task, as described at the top of this file.
+ */
+static void prvCheckTask( void *pvParameters );
+
+/*
+ * Register check tasks as described at the top of this file. The nature of
+ * these files necessitates that they are written in an assembly file, but the
+ * entry points are kept in the C file for the convenience of checking the task
+ * parameter.
+ */
+static void prvRegTestTaskEntry1( void *pvParameters );
+extern void vRegTest1Implementation( void );
+static void prvRegTestTaskEntry2( void *pvParameters );
+extern void vRegTest2Implementation( void );
+
+/*
+ * Tick hook used by the full demo, which includes code that interacts with
+ * some of the tests.
+ */
+void vFullDemoTickHook( void );
+
+/*-----------------------------------------------------------*/
+
+/* The following two variables are used to communicate the status of the
+register check tasks to the check task. If the variables keep incrementing,
+then the register check tasks have not discovered any errors. If a variable
+stops incrementing, then an error has been found. */
+volatile uint32_t ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;
+
+/*-----------------------------------------------------------*/
+
+void main_full( void )
+{
+ /* Create the register check tasks, as described at the top of this file.
+ Use xTaskCreateStatic() to create a task using only statically allocated
+ memory. */
+ xTaskCreate( prvRegTestTaskEntry1, /* The function that implements the task. */
+ "Reg1", /* The name of the task. */
+ mainREG_TEST_STACK_SIZE_WORDS, /* Size of stack to allocate for the task - in words not bytes!. */
+ mainREG_TEST_TASK_1_PARAMETER, /* Parameter passed into the task. */
+ tskIDLE_PRIORITY, /* Priority of the task. */
+ NULL ); /* Can be used to pass out a handle to the created task. */
+ xTaskCreate( prvRegTestTaskEntry2, "Reg2", mainREG_TEST_STACK_SIZE_WORDS, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL );
+
+ /* Start all the other standard demo/test tasks. They have no particular
+ functionality, but do demonstrate how to use the FreeRTOS API and test the
+ kernel port. */
+ vStartDynamicPriorityTasks();
+ vCreateBlockTimeTasks();
+ vStartGenericQueueTasks( tskIDLE_PRIORITY );
+ vStartRecursiveMutexTasks();
+ vStartTimerDemoTask( mainTIMER_TEST_PERIOD );
+ vStartEventGroupTasks();
+ vStartTaskNotifyTask();
+
+ /* Create the task that performs the 'check' functionality, as described at
+ the top of this file. */
+ xTaskCreate( prvCheckTask, "Check", mainCHECK_TASK_STACK_SIZE_WORDS, NULL, mainCHECK_TASK_PRIORITY, NULL );
+
+ /* Start the scheduler. */
+ vTaskStartScheduler();
+
+ /* If all is well, the scheduler will now be running, and the following
+ line will never be reached. If the following line does execute, then
+ there was insufficient FreeRTOS heap memory available for the Idle and/or
+ timer tasks to be created. See the memory management section on the
+ FreeRTOS web site for more details on the FreeRTOS heap
+ http://www.freertos.org/a00111.html. */
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckTask( void *pvParameters )
+{
+const TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD;
+TickType_t xLastExecutionTime;
+static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;
+const char * const pcPassMessage = "Pass";
+const char * pcStatusMessage = ".";
+extern void vSendString( const char * pcString );
+
+ /* Just to stop compiler warnings. */
+ ( void ) pvParameters;
+
+ /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()
+ works correctly. */
+ xLastExecutionTime = xTaskGetTickCount();
+
+ /* Cycle for ever, delaying then checking all the other tasks are still
+ operating without error. The onboard LED is toggled on each iteration.
+ If an error is detected then the delay period is decreased from
+ mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the
+ effect of increasing the rate at which the onboard LED toggles, and in so
+ doing gives visual feedback of the system status. */
+ for( ;; )
+ {
+ /* Delay until it is time to execute again. */
+ vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod );
+
+ /* Check all the demo tasks (other than the flash tasks) to ensure
+ that they are all still running, and that none have detected an error. */
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
+ {
+ pcStatusMessage = "ERROR: Dynamic priority demo/tests.\r\n";
+ }
+
+ if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
+ {
+ pcStatusMessage = "ERROR: Block time demo/tests.\r\n";
+ }
+
+ if ( xAreGenericQueueTasksStillRunning() != pdTRUE )
+ {
+ pcStatusMessage = "ERROR: Generic queue demo/tests.\r\n";
+ }
+
+ if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
+ {
+ pcStatusMessage = "ERROR: Recursive mutex demo/tests.\r\n";
+ }
+
+ if( xAreTimerDemoTasksStillRunning( ( TickType_t ) xDelayPeriod ) != pdPASS )
+ {
+ pcStatusMessage = "ERROR: Timer demo/tests.\r\n";
+ }
+
+ if( xAreEventGroupTasksStillRunning() != pdPASS )
+ {
+ pcStatusMessage = "ERROR: Event group demo/tests.\r\n";
+ }
+
+ if( xAreTaskNotificationTasksStillRunning() != pdPASS )
+ {
+ pcStatusMessage = "ERROR: Task notification demo/tests.\r\n";
+ }
+
+ /* Check that the register test 1 task is still running. */
+ if( ulLastRegTest1Value == ulRegTest1LoopCounter )
+ {
+ pcStatusMessage = "ERROR: Register test 1.\r\n";
+ }
+ ulLastRegTest1Value = ulRegTest1LoopCounter;
+
+ /* Check that the register test 2 task is still running. */
+ if( ulLastRegTest2Value == ulRegTest2LoopCounter )
+ {
+ pcStatusMessage = "ERROR: Register test 2.\r\n";
+ }
+ ulLastRegTest2Value = ulRegTest2LoopCounter;
+
+ /* Write the status message to the UART. */
+ vSendString( pcStatusMessage );
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvRegTestTaskEntry1( void *pvParameters )
+{
+ /* Although the regtest task is written in assembler, its entry point is
+ written in C for convenience of checking the task parameter is being passed
+ in correctly. */
+ if( pvParameters == mainREG_TEST_TASK_1_PARAMETER )
+ {
+ /* Start the part of the test that is written in assembler. */
+ vRegTest1Implementation();
+ }
+
+ /* The following line will only execute if the task parameter is found to
+ be incorrect. The check task will detect that the regtest loop counter is
+ not being incremented and flag an error. */
+ vTaskDelete( NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvRegTestTaskEntry2( void *pvParameters )
+{
+ /* Although the regtest task is written in assembler, its entry point is
+ written in C for convenience of checking the task parameter is being passed
+ in correctly. */
+ if( pvParameters == mainREG_TEST_TASK_2_PARAMETER )
+ {
+ /* Start the part of the test that is written in assembler. */
+ vRegTest2Implementation();
+ }
+
+ /* The following line will only execute if the task parameter is found to
+ be incorrect. The check task will detect that the regtest loop counter is
+ not being incremented and flag an error. */
+ vTaskDelete( NULL );
+}
+/*-----------------------------------------------------------*/
+
+void vFullDemoTickHook( void )
+{
+ /* Called from vApplicationTickHook() when the project is configured to
+ build the full demo. */
+ vTimerPeriodicISRTests();
+ vPeriodicEventGroupsProcessing();
+ xNotifyTaskFromISR();
+}
diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/main.c b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/main.c new file mode 100644 index 000000000..07912293e --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/main.c @@ -0,0 +1,201 @@ +/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* FreeRTOS kernel includes. */
+#include <FreeRTOS.h>
+#include <task.h>
+
+/******************************************************************************
+ * This project provides two demo applications. A simple blinky style project,
+ * and a more comprehensive test and demo application. The
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to
+ * select between the two. The simply blinky demo is implemented and described
+ * in main_blinky.c. The more comprehensive test and demo application is
+ * implemented and described in main_full.c.
+ *
+ * This file implements the code that is not demo specific, including the
+ * hardware setup and standard FreeRTOS hook functions.
+ *
+ * ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON
+ * THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO
+ * APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT!
+ *
+ *
+ * NOTE 1:
+ *
+ * This project has only been tested in the QEMU emulation of the HiFive board
+ * from SiFive.
+ *
+ * Start QEMU using the following command line:
+ *
+ * [your_path_1]\qemu-system-riscv32 -kernel [your_path_2]\FreeRTOS\Demo\RISC-V-Qemu-sifive_e-FreedomStudio\Debug\RTOSDemo.elf -S -s -machine sifive_e
+ *
+ * Where [your_path_1] must be replaced with the correct path to your QEMU
+ * installation and the elf file generated by this project respectively.
+ *
+ *
+ * NOTE 2:
+ *
+ * Start GDB using the following command line (this can be entered in the
+ * Eclipse Debug Launch Configuration dialogue):
+ *
+ * riscv64-unknown-elf-gdb.exe -iex "set mem inaccessible-by-default off" -iex "set arch riscv:rv32" -iex "set riscv use_compressed_breakpoint off"
+ *
+ *
+ * Note 3:
+ *
+ * Status information is sent to the QEMU serial console.
+ */
+
+/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,
+or 0 to run the more comprehensive test and demo application. */
+#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0
+
+/*
+ * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.
+ * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.
+ */
+#if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1
+ extern void main_blinky( void );
+#else
+ extern void main_full( void );
+#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */
+
+/*
+ * Prototypes for the standard FreeRTOS callback/hook functions implemented
+ * within this file. See https://www.freertos.org/a00016.html
+ */
+void vApplicationMallocFailedHook( void );
+void vApplicationIdleHook( void );
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName );
+void vApplicationTickHook( void );
+
+/*
+ * Very simply polling write to the UART. The full demo only writes single
+ * characters at a time so as not to disrupt the timing of the test and demo
+ * tasks.
+ */
+void vSendString( const char * pcString );
+
+/*-----------------------------------------------------------*/
+
+int main( void )
+{
+ vSendString( "Starting" );
+
+ /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top
+ of this file. */
+ #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 )
+ {
+ main_blinky();
+ }
+ #else
+ {
+ main_full();
+ }
+ #endif
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationMallocFailedHook( void )
+{
+ /* vApplicationMallocFailedHook() will only be called if
+ configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook
+ function that will get called if a call to pvPortMalloc() fails.
+ pvPortMalloc() is called internally by the kernel whenever a task, queue,
+ timer or semaphore is created. It is also called by various parts of the
+ demo application. If heap_1.c or heap_2.c are used, then the size of the
+ heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
+ FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
+ to query the size of free heap space that remains (although it does not
+ provide information on how the remaining heap might be fragmented). */
+ taskDISABLE_INTERRUPTS();
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationIdleHook( void )
+{
+ /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set
+ to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle
+ task. It is essential that code added to this hook function never attempts
+ to block in any way (for example, call xQueueReceive() with a block time
+ specified, or call vTaskDelay()). If the application makes use of the
+ vTaskDelete() API function (as this demo application does) then it is also
+ important that vApplicationIdleHook() is permitted to return to its calling
+ function, because it is the responsibility of the idle task to clean up
+ memory allocated by the kernel to any task that has since been deleted. */
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )
+{
+ ( void ) pcTaskName;
+ ( void ) pxTask;
+
+ /* Run time stack overflow checking is performed if
+ configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
+ function is called if a stack overflow is detected. */
+ taskDISABLE_INTERRUPTS();
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationTickHook( void )
+{
+ /* The tests in the full demo expect some interaction with interrupts. */
+ #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY != 1 )
+ {
+ extern void vFullDemoTickHook( void );
+ vFullDemoTickHook();
+ }
+ #endif
+}
+/*-----------------------------------------------------------*/
+
+void vAssertCalled( void )
+{
+volatile uint32_t ulSetTo1ToExitFunction = 0;
+
+ taskDISABLE_INTERRUPTS();
+ while( ulSetTo1ToExitFunction != 1 )
+ {
+ __asm volatile( "NOP" );
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vSendString( const char * pcString )
+{
+ while( *pcString != 0x00 )
+ {
+ while( UART0_REG( UART_REG_TXFIFO ) & 0x80000000 );
+ UART0_REG( UART_REG_TXFIFO ) = *pcString;
+ *pcString++;
+ }
+}
+
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