Update CEC1302 peripheral library version.

git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2445 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
author: rtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2> 2016-04-18 15:52:19 +0000
committer: rtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2> 2016-04-18 15:52:19 +0000
commit: ddcf4846caece581db4a9398c8f04909a9bad637 (patch)
tree: 4725de7dddb41e0cb32788334f1fd21f61002bc1 /FreeRTOS/Demo
parent: 3639e3a4bb1177bb09d790fb3a1260f57eaf6759 (diff)
download: freertos-ddcf4846caece581db4a9398c8f04909a9bad637.tar.gz
27 files changed, 4035 insertions, 7221 deletions
diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/RTOSDemo.uvguix.barryri b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/RTOSDemo.uvguix.barryri
index 332cfb365..0ae28cff8 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/RTOSDemo.uvguix.barryri
+++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/RTOSDemo.uvguix.barryri
@@ -83,17 +83,17 @@
         <yPos>-1</yPos>
       </MaxPosition>
       <NormalPosition>
-        <Top>0</Top>
-        <Left>0</Left>
-        <Right>1238</Right>
-        <Bottom>872</Bottom>
+        <Top>104</Top>
+        <Left>399</Left>
+        <Right>1341</Right>
+        <Bottom>976</Bottom>
       </NormalPosition>
     </WindowPosition>
     <MDIClientArea>
       <RegID>0</RegID>
       <MDITabState>
         <Len>274</Len>
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       </MDITabState>
     </MDIClientArea>
     <ViewEx>
@@ -1288,7 +1288,7 @@
         <Name>File</Name>
         <Buttons>
           <Len>2098</Len>
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         <OriginalItems>
           <Len>1423</Len>
@@ -1320,7 +1320,7 @@
         <Name>Debug</Name>
         <Buttons>
           <Len>2247</Len>
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@@ -1343,7 +1343,7 @@
       <Window>
         <RegID>-1</RegID>
         <PaneID>-1</PaneID>
-        <IsVisible>0</IsVisible>
+        <IsVisible>1</IsVisible>
         <IsFloating>0</IsFloating>
         <IsTabbed>0</IsTabbed>
         <IsActivated>0</IsActivated>
@@ -1763,7 +1763,7 @@
       <Window>
         <RegID>203</RegID>
         <PaneID>203</PaneID>
-        <IsVisible>0</IsVisible>
+        <IsVisible>1</IsVisible>
         <IsFloating>0</IsFloating>
         <IsTabbed>0</IsTabbed>
         <IsActivated>0</IsActivated>
@@ -1773,7 +1773,7 @@
         <RecentRowIndex>0</RecentRowIndex>
         <RectRecentDocked>
           <Len>16</Len>
-          <Data>6F010000620000007D07000072010000</Data>
+          <Data>6C0100005F000000800700008B010000</Data>
         </RectRecentDocked>
         <RectRecentFloat>
           <Len>16</Len>
@@ -2522,14 +2522,14 @@
       </Window>
       <DockMan>
         <Len>2694</Len>
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       </DockMan>
       <ToolBar>
         <RegID>59392</RegID>
         <Name>File</Name>
         <Buttons>
-          <Len>2071</Len>
-          <Data>00200000010000002800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000000004000000000000000000000000000000000100000001000000018022E100000000000005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000004000700000000000000000000000000000000010000000100000001802CE10000000004000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000000000900000000000000000000000000000000010000000100000001807B8A0000000004000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000004000C0000000000000000000000000000000001000000010000000180F4B00000000004000D000000000000000000000000000000000100000001000000018036B10000000004000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF88000000000000460000000000000000000000000000000001000000010000000180FE880000000000004500000000000000000000000000000000010000000100000001800B810000000000001300000000000000000000000000000000010000000100000001800C810000000000001400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F0880000020000000F000000000000000000000000000000000100000001000000FFFF0100120043555646696E64436F6D626F427574746F6EE80300000000000000000000000000000000000000000000000100000001000000960000000200205000000000204D4D43525F5043525F50524F434553534F525F434C4F434B5F434F4E54524F4C96000000000000000100204D4D43525F5043525F50524F434553534F525F434C4F434B5F434F4E54524F4C00000000018024E10000000000001100000000000000000000000000000000010000000100000001800A810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018022800000020003001500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000160000000000000000000000000000000001000000010000000180C988000000000400180000000000000000000000000000000001000000010000000180C788000000000000190000000000000000000000000000000001000000010000000180C8880000000000001700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E4C010000020001001A0000000F2650726F6A6563742057696E646F77000000000000000000000000010000000100000000000000000000000100000008002880DD880000000000001A0000000750726F6A656374000000000000000000000000010000000100000000000000000000000100000000002880DC8B0000000000003A00000005426F6F6B73000000000000000000000000010000000100000000000000000000000100000000002880E18B0000000000003B0000000946756E6374696F6E73000000000000000000000000010000000100000000000000000000000100000000002880E28B000000000000400000000954656D706C6174657300000000000000000000000001000000010000000000000000000000010000000000288018890000000000003D0000000E536F757263652042726F777365720000000000000000000000000100000001000000000000000000000001000000000028800000000000000400FFFFFFFF00000000000000000001000000000000000100000000000000000000000100000000002880D988000000000000390000000C4275696C64204F7574707574000000000000000000000000010000000100000000000000000000000100000000002880E38B000000000000410000000B46696E64204F75747075740000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001B000000000000000000000000000000000100000001000000000000000446696C6572030000</Data>
+          <Len>2098</Len>
+          <Data>00200000010000002800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000040004000000000000000000000000000000000100000001000000018022E100000000040005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000004000700000000000000000000000000000000010000000100000001802CE10000000004000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000000000900000000000000000000000000000000010000000100000001807B8A0000000004000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000004000C0000000000000000000000000000000001000000010000000180F4B00000000004000D000000000000000000000000000000000100000001000000018036B10000000004000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF88000000000400460000000000000000000000000000000001000000010000000180FE880000000004004500000000000000000000000000000000010000000100000001800B810000000004001300000000000000000000000000000000010000000100000001800C810000000004001400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F0880000020000000F000000000000000000000000000000000100000001000000FFFF0100120043555646696E64436F6D626F427574746F6EE80300000000000000000000000000000000000000000000000100000001000000960000000200205000000000086D61696E56544F5296000000000000000500086D61696E56544F520015707276506F7274537461727446697273745461736B0E73746172747363686564756C6572146C70494E434C5544455F544553545F54494D45520000000000000000000000000000000000000000018024E10000000000001100000000000000000000000000000000010000000100000001800A810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018022800000020001001500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000160000000000000000000000000000000001000000010000000180C988000000000400180000000000000000000000000000000001000000010000000180C788000000000000190000000000000000000000000000000001000000010000000180C8880000000000001700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E4C010000020001001A0000000F2650726F6A6563742057696E646F77000000000000000000000000010000000100000000000000000000000100000008002880DD880000000000001A0000000750726F6A656374000000000000000000000000010000000100000000000000000000000100000000002880DC8B0000000000003A00000005426F6F6B73000000000000000000000000010000000100000000000000000000000100000000002880E18B0000000000003B0000000946756E6374696F6E73000000000000000000000000010000000100000000000000000000000100000000002880E28B000000000000400000000954656D706C6174657300000000000000000000000001000000010000000000000000000000010000000000288018890000000000003D0000000E536F757263652042726F777365720000000000000000000000000100000001000000000000000000000001000000000028800000000000000400FFFFFFFF00000000000000000001000000000000000100000000000000000000000100000000002880D988000000000000390000000C4275696C64204F7574707574000000000000000000000000010000000100000000000000000000000100000000002880E38B000000000000410000000B46696E64204F75747075740000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001B000000000000000000000000000000000100000001000000000000000446696C6572030000</Data>
         </Buttons>
         <OriginalItems>
           <Len>1423</Len>
@@ -2561,7 +2561,7 @@
         <Name>Debug</Name>
         <Buttons>
           <Len>2236</Len>
-          <Data>00200000010000001900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000002500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000002600000000000000000000000000000000010000000100000001801D800000000004002700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000002800000000000000000000000000000000010000000100000001801B80000000000000290000000000000000000000000000000001000000010000000180E57F0000000000002A00000000000000000000000000000000010000000100000001801C800000000000002B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000002C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B0000020001002D0000000000000000000000000000000001000000010000000180F07F0000020000002E0000000000000000000000000000000001000000010000000180E8880000020000003700000000000000000000000000000000010000000100000001803B010000020001002F0000000000000000000000000000000001000000010000000180BB8A00000200010030000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E0E01000002000100310000000D57617463682057696E646F7773000000000000000000000000010000000100000000000000000000000100000002001380D88B00000000000031000000085761746368202631000000000000000000000000010000000100000000000000000000000100000000001380D98B000000000000310000000857617463682026320000000000000000000000000100000001000000000000000000000001000000000013800F0100000200010032000000094D656D6F7279202631000000000000000000000000010000000100000000000000000000000100000004001380D28B00000000000032000000094D656D6F7279202631000000000000000000000000010000000100000000000000000000000100000000001380D38B00000000000032000000094D656D6F7279202632000000000000000000000000010000000100000000000000000000000100000000001380D48B00000000000032000000094D656D6F7279202633000000000000000000000000010000000100000000000000000000000100000000001380D58B00000000000032000000094D656D6F727920263400000000000000000000000001000000010000000000000000000000010000000000138010010000020000003300000008554152542023263100000000000000000000000001000000010000000000000000000000010000000400138093070000000000003300000008554152542023263100000000000000000000000001000000010000000000000000000000010000000000138094070000000000003300000008554152542023263200000000000000000000000001000000010000000000000000000000010000000000138095070000000000003300000008554152542023263300000000000000000000000001000000010000000000000000000000010000000000138096070000000000003300000015446562756720287072696E746629205669657765720000000000000000000000000100000001000000000000000000000001000000000013803C010000020000003400000010416E616C797369732057696E646F7773000000000000000000000000010000000100000000000000000000000100000003001380658A000000000000340000000F264C6F67696320416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380DC7F0000000000003E0000001526506572666F726D616E636520416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380E788000000000000380000000E26436F646520436F76657261676500000000000000000000000001000000010000000000000000000000010000000000138053010000000000003F0000000D54726163652057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013805401000000000000FFFFFFFF115472616365204D656E7520416E63686F720100000000000000010000000000000001000000000000000000000001000000000013802901000000000000350000001553797374656D205669657765722057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013804B01000000000000FFFFFFFF1453797374656D2056696577657220416E63686F720100000000000000010000000000000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000013800189000002000000360000000F26546F6F6C626F782057696E646F7700000000000000000000000001000000010000000000000000000000010000000300138044C5000000000000FFFFFFFF0E5570646174652057696E646F77730100000000000000010000000000000001000000000000000000000001000000000013800000000000000400FFFFFFFF000000000000000000010000000000000001000000000000000000000001000000000013805B01000000000000FFFFFFFF12546F6F6C626F78204D656E75416E63686F7201000000000000000100000000000000010000000000000000000000010000000000000000000544656275673C020000</Data>
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         </Buttons>
         <OriginalItems>
           <Len>898</Len>
@@ -2588,9 +2588,9 @@
       <ActiveTab>0</ActiveTab>
       <Doc>
         <Name>..\main.c</Name>
-        <ColumnNumber>0</ColumnNumber>
-        <TopLine>67</TopLine>
-        <CurrentLine>142</CurrentLine>
+        <ColumnNumber>47</ColumnNumber>
+        <TopLine>65</TopLine>
+        <CurrentLine>180</CurrentLine>
         <Folding>1</Folding>
         <ContractedFolders></ContractedFolders>
         <PaneID>0</PaneID>
diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/RTOSDemo.uvoptx b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/RTOSDemo.uvoptx
index f4ca31c1b..b168790da 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/RTOSDemo.uvoptx
+++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/RTOSDemo.uvoptx
@@ -89,7 +89,7 @@
         <sRfunc>1</sRfunc>
         <sRbox>1</sRbox>
         <tLdApp>1</tLdApp>
-        <tGomain>1</tGomain>
+        <tGomain>0</tGomain>
         <tRbreak>1</tRbreak>
         <tRwatch>1</tRwatch>
         <tRmem>1</tRmem>
@@ -179,7 +179,7 @@
       <DebugFlag>
         <trace>0</trace>
         <periodic>1</periodic>
-        <aLwin>0</aLwin>
+        <aLwin>1</aLwin>
         <aCover>0</aCover>
         <aSer1>0</aSer1>
         <aSer2>0</aSer2>
@@ -245,7 +245,7 @@
 
   <Group>
     <GroupName>main_and_config</GroupName>
-    <tvExp>1</tvExp>
+    <tvExp>0</tvExp>
     <tvExpOptDlg>0</tvExpOptDlg>
     <cbSel>0</cbSel>
     <RteFlg>0</RteFlg>
@@ -369,7 +369,7 @@
 
   <Group>
     <GroupName>main_low_power</GroupName>
-    <tvExp>1</tvExp>
+    <tvExp>0</tvExp>
     <tvExpOptDlg>0</tvExpOptDlg>
     <cbSel>0</cbSel>
     <RteFlg>0</RteFlg>
@@ -401,7 +401,7 @@
 
   <Group>
     <GroupName>main_full</GroupName>
-    <tvExp>1</tvExp>
+    <tvExp>0</tvExp>
     <tvExpOptDlg>0</tvExpOptDlg>
     <cbSel>0</cbSel>
     <RteFlg>0</RteFlg>
diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/sections.ld b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/sections.ld
index 95e1da65d..516ce0032 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/sections.ld
+++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/sections.ld
@@ -1,9 +1,10 @@
 /*
- * Default linker script for GCC MEC1322
+ * Default linker script for GCC CEC1302
  * Based upon linker scripts from GNU ARM Eclipse plug-in
  */
 
 INCLUDE mem.ld
+__SRAM_segment_end__ = ORIGIN( RAM ) + LENGTH( RAM );
 
 /*
  * The '__stack' definition is required by crt0, do not remove it.
@@ -58,7 +59,7 @@ SECTIONS
      * For Cortex-M devices, the beginning of the startup code is stored in
      * the .isr_vector section, which goes to ROM
      */
-	 
+
 	.isr_vector :
 	{
 		. = ALIGN(4);
@@ -66,8 +67,8 @@ SECTIONS
 		KEEP(*(.isr_vector))
 		. = ALIGN(4);
 	} >ROM
- 
-	 
+
+
     .text :
     {
         . = ALIGN(4);
diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/startup_ARMCM4.S b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/startup_ARMCM4.S
index 5178bec41..5c3185dee 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/startup_ARMCM4.S
+++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/startup_ARMCM4.S
@@ -33,43 +33,16 @@
 	.syntax	unified
 	.arch	armv7e-m
 
-	.section .stack
-	.align	3
-
-	.equ	ulMainStackSize, 200 * 4
-	.equ	Stack_Size, 0x004
-	.globl	__StackTop
-	.globl	__StackLimit
-	.extern ulMainStack
-__StackLimit:
-	.space	Stack_Size
-	.size	__StackLimit, . - __StackLimit
-__StackTop:
-	.size	__StackTop, . - __StackTop
-
-	.section .heap
-	.align	3
-#ifdef __HEAP_SIZE
-	.equ	Heap_Size, __HEAP_SIZE
-#else
-	.equ	Heap_Size, 0
-#endif
-	.globl	__HeapBase
-	.globl	__HeapLimit
-__HeapBase:
-	.if	Heap_Size
-	.space	Heap_Size
-	.endif
-	.size	__HeapBase, . - __HeapBase
-__HeapLimit:
-	.size	__HeapLimit, . - __HeapLimit
+	.extern __SRAM_segment_end__
 
 	.section .isr_vector,"a",%progbits
+	.align	4
+	.globl	__isr_vector
 	.global __Vectors
-	.type	__Vectors, %object
-	.size	__Vectors, .-__Vectors
+
 __Vectors:
-	.long	ulMainStack + ulMainStackSize           /* Top of Stack */
+__isr_vector:
+	.long	__SRAM_segment_end__ - 4  /* Top of Stack at top of RAM*/
 	.long	Reset_Handler         /* Reset Handler */
 	.long	NMI_Handler           /* NMI Handler */
 	.long	HardFault_Handler     /* Hard Fault Handler */
@@ -207,9 +180,6 @@ Reset_Handler:
  *
  *  All addresses must be aligned to 4 bytes boundary.
  */
-	ldr sp, =ulMainStack + ulMainStackSize
-	sub sp, sp, #4
-	
 	ldr	r1, =__etext
 	ldr	r2, =__data_start__
 	ldr	r3, =__data_end__
@@ -280,10 +250,10 @@ Default_Handler:
 	def_irq_handler	MemManage_Handler
 	def_irq_handler	BusFault_Handler
 	def_irq_handler	UsageFault_Handler
-/*	def_irq_handler	SVC_Handler */
+	def_irq_handler	SVC_Handler
 	def_irq_handler	DebugMon_Handler
-/*	def_irq_handler	PendSV_Handler */
-/*	def_irq_handler	SysTick_Handler */
+	def_irq_handler	PendSV_Handler
+	def_irq_handler	SysTick_Handler
 	def_irq_handler	DEF_IRQHandler
 
 	def_irq_handler     NVIC_Handler_I2C0
diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/system.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/system.c
index 9ecd3201d..0126388ba 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/system.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/system.c
@@ -22,12 +22,12 @@
  *  @{
  */
 /** @file pwm_c_wrapper.cpp
- \brief the pwm component C wrapper   
+ \brief the pwm component C wrapper
  This program is designed to allow the other C programs to be able to use this component
 
  There are entry points for all C wrapper API implementation
 
-<b>Platform:</b> This is ARC-based component 
+<b>Platform:</b> This is ARC-based component
 
 <b>Toolset:</b> Metaware IDE(8.5.1)
 <b>Reference:</b> smsc_reusable_fw_requirement.doc */
@@ -41,7 +41,7 @@
  *  AUTHOR:   $Author: akrishnan $
  *
  *  Revision history (latest first):
- *      #3  2011/05/09  martin_y    update to Metaware IDE(8.5.1) 
+ *      #3  2011/05/09  martin_y    update to Metaware IDE(8.5.1)
  *      #2  2011/03/25  martin_y    support FPGA build 058 apps
  *      #1  2011/03/23  martin_y    branch from MEC1618 sample code: MEC1618_evb_sample_code_build_0200
  ***********************************************************************************
@@ -55,12 +55,6 @@
 #define MMCR_PCR_PROCESSOR_CLOCK_CONTROL    (*(uint32_t *)(ADDR_PCR_PROCESSOR_CLOCK_CONTROL))
 #define CPU_CLOCK_DIVIDER					1
 
-/* The start up code is configured to use the following array as the stack used
-by main(), which will then also get used by FreeRTOS interrupt handlers after 
-the scheduler has been started. */
-#warning If the array size is modified here then ulMainStackSize must also be modified in startup_ARMCM4.S.
-volatile uint32_t ulMainStack[ 200 ];
-
 /******************************************************************************/
 /** system_set_ec_clock
 * Set CPU speed
diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/RTOSDemo.uvoptx b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/RTOSDemo.uvoptx
index f4f0cce03..2792135dc 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/RTOSDemo.uvoptx
+++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/RTOSDemo.uvoptx
@@ -397,7 +397,7 @@
       <GroupNumber>5</GroupNumber>
       <FileNumber>14</FileNumber>
       <FileType>1</FileType>
-      <tvExp>1</tvExp>
+      <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
       <PathWithFileName>..\main_full\main_full.c</PathWithFileName>
@@ -573,7 +573,7 @@
       <GroupNumber>6</GroupNumber>
       <FileNumber>28</FileNumber>
       <FileType>1</FileType>
-      <tvExp>0</tvExp>
+      <tvExp>1</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
       <PathWithFileName>..\peripheral_library\basic_timer\btimer_api.c</PathWithFileName>
diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/startup_CEC1302.s b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/startup_CEC1302.s
index 17984f30e..aa1fe659c 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/startup_CEC1302.s
+++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/startup_CEC1302.s
@@ -19,10 +19,10 @@
 ;* OF THESE TERMS.
 ;******************************************************************************
 ; */
-;/** @file startup_MEC1322.s
-; *MEC1322 API Test: startup and vector table
+;/** @file startup_CEC1302.s
+; *CEC1302 API Test: startup and vector table
 ; */
-;/** @defgroup startup_MEC1322
+;/** @defgroup startup_CEC1302
 ; *  @{
 ; */
 
@@ -55,7 +55,7 @@ __initial_sp
 ;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
 ; </h>
 
-Heap_Size       EQU     0x00000000 
+Heap_Size       EQU     0x00000000
 
                 AREA    HEAP, NOINIT, READWRITE, ALIGN=3
 __heap_base
@@ -88,7 +88,7 @@ __Vectors       DCD     __initial_sp              ; Top of Stack
                 DCD     PendSV_Handler            ; PendSV Handler
                 DCD     SysTick_Handler           ; SysTick Handler
 
-                ; MEC1322 External Interrupts
+                ; CEC1302 External Interrupts
                 DCD     NVIC_Handler_I2C0           ; 40h: 0, I2C/SMBus 0
                 DCD     NVIC_Handler_I2C1           ; 44h: 1, I2C/SMBus 1
                 DCD     NVIC_Handler_I2C2           ; 48h: 2, I2C/SMBus 2
@@ -152,7 +152,7 @@ __Vectors       DCD     __initial_sp              ; Top of Stack
                 DCD     NVIC_Handler_GIRQ11         ; 130h: 60, GIRQ11
                 DCD     NVIC_Handler_GIRQ12        ; 134h: 61, GIRQ12
                 DCD     NVIC_Handler_GIRQ13         ; 138h: 62, GIRQ13
-				DCD     NVIC_Handler_GIRQ14         ; 13Ch: 63, GIRQ14
+                DCD     NVIC_Handler_GIRQ14         ; 13Ch: 63, GIRQ14
                 DCD     NVIC_Handler_GIRQ15         ; 140h: 64, GIRQ15
                 DCD     NVIC_Handler_GIRQ16         ; 144h: 65, GIRQ16
                 DCD     NVIC_Handler_GIRQ17         ; 148h: 66, GIRQ17
@@ -178,9 +178,9 @@ __Vectors       DCD     __initial_sp              ; Top of Stack
                 DCD     NVIC_Handler_PKE_ERR        ; 198h: 86, PKE Error
                 DCD     NVIC_Handler_PKE_END        ; 19Ch: 87, PKE End
                 DCD     NVIC_Handler_TRNG           ; 1A0h: 88, TRandom Num Gen
-                DCD     NVIC_Handler_AES            ; 1A4h: 89, AES 
+                DCD     NVIC_Handler_AES            ; 1A4h: 89, AES
                 DCD     NVIC_Handler_HASH           ; 1A8h: 90, HASH
-                
+
 
                 AREA    ROMTABLE, CODE, READONLY
                 THUMB
@@ -198,16 +198,16 @@ Reset_Handler   PROC
                 EXPORT  Reset_Handler             [WEAK]
 
                 CPSID    i
-                
- 				; support code is loaded from ROM loader
-        		LDR 	SP, =__initial_sp
-				; configure CPU speed 
+
+                ; support code is loaded from ROM loader
+                LDR     SP, =__initial_sp
+                ; configure CPU speed
                 LDR     R0, =system_set_ec_clock
                 BLX     R0
 
                 LDR     SP, =__initial_sp
 
- 				; support FPU
+                ; support FPU
                 IF      {CPU} = "Cortex-M4.fp"
                 LDR     R0, =0xE000ED88           ; Enable CP10,CP11
                 LDR     R1,[R0]
@@ -275,7 +275,7 @@ SysTick_Handler PROC
 
 Default_Handler PROC
 
-        ; External MEC1322 NVIC Interrupt Inputs
+        ; External CEC1302 NVIC Interrupt Inputs
         EXPORT  NVIC_Handler_I2C0               [WEAK]
         EXPORT  NVIC_Handler_I2C1               [WEAK]
         EXPORT  NVIC_Handler_I2C2               [WEAK]
@@ -468,14 +468,14 @@ NVIC_Handler_HASH
 ; User Initial Stack & Heap
 
                 IF      :DEF:__MICROLIB
-                
+
                 EXPORT  __initial_sp
                 EXPORT  __heap_base
                 EXPORT  __heap_limit
                 EXPORT  __stack_bottom
 
                 ELSE
-                
+
                 IMPORT  __use_two_region_memory
                 EXPORT  __user_initial_stackheap
 __user_initial_stackheap
diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main.c
index 4c843fa18..feb080b87 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main.c
@@ -165,7 +165,7 @@ static void prvSetupHardware( void )
 extern void system_set_ec_clock( void );
 extern unsigned long __Vectors[];
 
-	/* Disable M4 write buffer: fix MEC1322 hardware bug. */
+	/* Disable M4 write buffer: fix CEC1302 hardware bug. */
 	mainNVIC_AUX_ACTLR |= 0x07;
 
 	/* Enable alternative NVIC vectors. */
diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_full/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_full/IntQueueTimer.c
index 6ff34e743..50c9bff50 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_full/IntQueueTimer.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_full/IntQueueTimer.c
@@ -117,8 +117,13 @@ timers must still be above the tick interrupt priority. */
 #define tmrMEDIUM_PRIORITY		( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 0 )
 #define tmrHIGHER_PRIORITY		( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY - 1 )
 
-/* Hardware register locations. */
-#define tmrGIRQ23_ENABLE_SET			( * ( volatile uint32_t * ) 0x4000C130 )
+/* Hardware register locations and bit definitions to enable the btimer 
+interrupts. */
+#define tmrGIRQ23_ENABLE_SET	( * ( volatile uint32_t * ) 0x4000C130 )
+#define tmrGIRQ23_BIT_TIMER0	( 1UL << 0UL )
+#define tmrGIRQ23_BIT_TIMER1	( 1UL << 1UL )
+#define tmrGIRQ23_BIT_TIMER2	( 1UL << 2UL )
+#define tmrGIRQ23_TIMER_BITS	( tmrGIRQ23_BIT_TIMER0 | tmrGIRQ23_BIT_TIMER1 | tmrGIRQ23_BIT_TIMER2 )
 
 #define tmrRECORD_NESTING_DEPTH()						\
 	ulNestingDepth++;									\
@@ -138,13 +143,12 @@ const uint32_t ulTimer0Count = configCPU_CLOCK_HZ / tmrTIMER_0_FREQUENCY;
 const uint32_t ulTimer1Count = configCPU_CLOCK_HZ / tmrTIMER_1_FREQUENCY;
 const uint32_t ulTimer2Count = configCPU_CLOCK_HZ / tmrTIMER_2_FREQUENCY;
 
-	tmrGIRQ23_ENABLE_SET = 0x03;
+	tmrGIRQ23_ENABLE_SET = tmrGIRQ23_TIMER_BITS;
 
 	/* Initialise the three timers as described at the top of this file, and
 	enable their interrupts in the NVIC. */
 	btimer_init( tmrTIMER_CHANNEL_0, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer0Count, ulTimer0Count );
 	btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_0 );
-	enable_timer0_irq();
 	NVIC_SetPriority( TIMER0_IRQn, tmrLOWER_PRIORITY ); //0xc0 into 0xe000e431
 	NVIC_ClearPendingIRQ( TIMER0_IRQn );
 	NVIC_EnableIRQ( TIMER0_IRQn );
@@ -152,7 +156,6 @@ const uint32_t ulTimer2Count = configCPU_CLOCK_HZ / tmrTIMER_2_FREQUENCY;
 
 	btimer_init( tmrTIMER_CHANNEL_1, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer1Count, ulTimer1Count );
 	btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_1 );
-	enable_timer1_irq();
 	NVIC_SetPriority( TIMER1_IRQn, tmrMEDIUM_PRIORITY ); //0xa0 into 0xe000e432
 	NVIC_ClearPendingIRQ( TIMER1_IRQn );
 	NVIC_EnableIRQ( TIMER1_IRQn );
@@ -160,7 +163,6 @@ const uint32_t ulTimer2Count = configCPU_CLOCK_HZ / tmrTIMER_2_FREQUENCY;
 
 	btimer_init( tmrTIMER_CHANNEL_2, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer2Count, ulTimer2Count );
 	btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_2 );
-	enable_timer2_irq();
 	NVIC_SetPriority( TIMER2_IRQn, tmrHIGHER_PRIORITY );
 	NVIC_ClearPendingIRQ( TIMER2_IRQn );
 	NVIC_EnableIRQ( TIMER2_IRQn );
diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_low_power/low_power_tick_config.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_low_power/low_power_tick_config.c
index 1d509e7cf..d88c15c5e 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_low_power/low_power_tick_config.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_low_power/low_power_tick_config.c
@@ -76,6 +76,8 @@
 
 /* Library includes. */
 #include "common_lib.h"
+#include "peripheral_library/interrupt/interrupt.h"
+#include "peripheral_library/basic_timer/btimer.h"
 
 /* This file contains functions that will override the default implementations
 in the RTOS port layer.  Therefore only build this file if the low power demo
@@ -170,13 +172,14 @@ void NVIC_Handler_HIB_TMR( void )
 #if( lpINCLUDE_TEST_TIMER == 1 )
 
 	#define lpGIRQ23_ENABLE_SET		( * ( uint32_t * ) 0x4000C130 )
+	#define tmrGIRQ23_BIT_TIMER0	( 1UL << 0UL )
 
 	static void prvSetupBasicTimer( void )
 	{
 	const uint8_t ucTimerChannel = 0;
 	const uint32_t ulTimer0Count = configCPU_CLOCK_HZ / 10;
 
-		lpGIRQ23_ENABLE_SET = 0x03;
+		lpGIRQ23_ENABLE_SET = tmrGIRQ23_BIT_TIMER0;
 
 		/* To fully test the low power tick processing it is necessary to sometimes
 		bring the MCU out of its sleep state by a method other than the tick
@@ -184,7 +187,6 @@ void NVIC_Handler_HIB_TMR( void )
 		purpose. */
 		btimer_init( ucTimerChannel, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer0Count, ulTimer0Count );
 		btimer_interrupt_status_get_clr( ucTimerChannel );
-		enable_timer0_irq();
 		NVIC_SetPriority( TIMER0_IRQn, ucTimerChannel );
 		NVIC_ClearPendingIRQ( TIMER0_IRQn );
 		NVIC_EnableIRQ( TIMER0_IRQn );
diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/ARM_REG.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/ARM_REG.h
index 035a10875..a836c6e42 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/ARM_REG.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/ARM_REG.h
@@ -1,194 +1,194 @@
-/*
- **********************************************************************************
-* � 2013 Microchip Technology Inc. and its subsidiaries.
-* You may use this software and any derivatives exclusively with
-* Microchip products.
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
-* OF THESE TERMS.
- **********************************************************************************
- *  ARM_REG.h
- *      This is the header to define Cortex-M3 system control & status registers
- **********************************************************************************
- *  SMSC version control information (Perforce):
- *
- *  FILE:     $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/ARM_REG.h $
- *  REVISION: $Revision: #1 $
- *  DATETIME: $DateTime: 2015/12/23 15:37:58 $
- *  AUTHOR:   $Author: akrishnan $
- *
- *  Revision history (latest first):
- *      #xx
- ***********************************************************************************
- */
-
-/******************************************************************************/
-/** @defgroup ARM_REG ARM_REG
- *  @{
- */
-
-/** @file ARM_REG.h
-* \brief ARM Cortex-M3 registers header file
-* \author KBCEC Team
-* 
-* This file contains ARM Cortex-M3 system control & status registers.
-******************************************************************************/   
-#ifndef ARM_REG_H_
-#define ARM_REG_H_
-
-#define REG8(x)  (*((volatile unsigned char  *)(x)))
-#define REG16(x) (*((volatile unsigned short *)(x)))
-#define REG32(x) (*((volatile unsigned long  *)(x)))
-
-/* NVIC Registers */
-#define NVIC_INT_TYPE           REG32(0xE000E004)
-#define NVIC_AUX_ACTLR          REG32(0xE000E008)
-    #define WR_BUF_DISABLE      (1 << 1)
-#define NVIC_ST_CTRL            REG32(0xE000E010)
-    #define ST_ENABLE           (1 << 0)
-    #define ST_TICKINT          (1 << 1)
-    #define ST_CLKSOURCE        (1 << 2)
-    #define ST_COUNTFLAG        (1 << 3)
-#define NVIC_ST_RELOAD          REG32(0xE000E014)
-#define NVIC_ST_CURRENT         REG32(0xE000E018)
-#define NVIC_ST_CALIB           REG32(0xE000E01C)
-#define NVIC_ENABLE0            REG32(0xE000E100)
-#define NVIC_ENABLE1            REG32(0xE000E104)
-#define NVIC_ENABLE2            REG32(0xE000E108)
-#define NVIC_ENABLE3            REG32(0xE000E10C)
-#define NVIC_ENABLE4            REG32(0xE000E110)
-#define NVIC_ENABLE5            REG32(0xE000E114)
-#define NVIC_ENABLE6            REG32(0xE000E118)
-#define NVIC_ENABLE7            REG32(0xE000E11C)
-#define NVIC_DISABLE0           REG32(0xE000E180)
-#define NVIC_DISABLE1           REG32(0xE000E184)
-#define NVIC_DISABLE2           REG32(0xE000E188)
-#define NVIC_DISABLE3           REG32(0xE000E18C)
-#define NVIC_DISABLE4           REG32(0xE000E190)
-#define NVIC_DISABLE5           REG32(0xE000E194)
-#define NVIC_DISABLE6           REG32(0xE000E198)
-#define NVIC_DISABLE7           REG32(0xE000E19C)
-#define NVIC_PEND0              REG32(0xE000E200)
-#define NVIC_PEND1              REG32(0xE000E204)
-#define NVIC_PEND2              REG32(0xE000E208)
-#define NVIC_PEND3              REG32(0xE000E20C)
-#define NVIC_PEND4              REG32(0xE000E210)
-#define NVIC_PEND5              REG32(0xE000E214)
-#define NVIC_PEND6              REG32(0xE000E218)
-#define NVIC_PEND7              REG32(0xE000E21C)
-#define NVIC_UNPEND0            REG32(0xE000E280)
-#define NVIC_UNPEND1            REG32(0xE000E284)
-#define NVIC_UNPEND2            REG32(0xE000E288)
-#define NVIC_UNPEND3            REG32(0xE000E28C)
-#define NVIC_UNPEND4            REG32(0xE000E290)
-#define NVIC_UNPEND5            REG32(0xE000E294)
-#define NVIC_UNPEND6            REG32(0xE000E298)
-#define NVIC_UNPEND7            REG32(0xE000E29C)
-#define NVIC_ACTIVE0            REG32(0xE000E300)
-#define NVIC_ACTIVE1            REG32(0xE000E304)
-#define NVIC_ACTIVE2            REG32(0xE000E308)
-#define NVIC_ACTIVE3            REG32(0xE000E30C)
-#define NVIC_ACTIVE4            REG32(0xE000E310)
-#define NVIC_ACTIVE5            REG32(0xE000E314)
-#define NVIC_ACTIVE6            REG32(0xE000E318)
-#define NVIC_ACTIVE7            REG32(0xE000E31C)
-#define NVIC_PRI0               REG32(0xE000E400)
-#define NVIC_PRI1               REG32(0xE000E404)
-#define NVIC_PRI2               REG32(0xE000E408)
-#define NVIC_PRI3               REG32(0xE000E40C)
-#define NVIC_PRI4               REG32(0xE000E410)
-#define NVIC_PRI5               REG32(0xE000E414)
-#define NVIC_PRI6               REG32(0xE000E418)
-#define NVIC_PRI7               REG32(0xE000E41C)
-#define NVIC_PRI8               REG32(0xE000E420)
-#define NVIC_PRI9               REG32(0xE000E424)
-#define NVIC_PRI10              REG32(0xE000E428)
-#define NVIC_PRI11              REG32(0xE000E42C)
-#define NVIC_PRI12              REG32(0xE000E430)
-#define NVIC_PRI13              REG32(0xE000E434)
-#define NVIC_PRI14              REG32(0xE000E438)
-#define NVIC_PRI15              REG32(0xE000E43C)
-#define NVIC_PRI16              REG32(0xE000E440)
-#define NVIC_PRI17              REG32(0xE000E444)
-#define NVIC_PRI18              REG32(0xE000E448)
-#define NVIC_PRI19              REG32(0xE000E44C)
-#define NVIC_PRI20              REG32(0xE000E450)
-#define NVIC_PRI21              REG32(0xE000E454)
-#define NVIC_PRI22              REG32(0xE000E458)
-#define NVIC_PRI23              REG32(0xE000E45C)
-#define NVIC_PRI24              REG32(0xE000E460)
-#define NVIC_PRI25              REG32(0xE000E464)
-#define NVIC_PRI26              REG32(0xE000E468)
-#define NVIC_PRI27              REG32(0xE000E46C)
-#define NVIC_PRI28              REG32(0xE000E470)
-#define NVIC_PRI29              REG32(0xE000E474)
-#define NVIC_PRI30              REG32(0xE000E478)
-#define NVIC_PRI31              REG32(0xE000E47C)
-#define NVIC_PRI32              REG32(0xE000E480)
-#define NVIC_PRI33              REG32(0xE000E484)
-#define NVIC_PRI34              REG32(0xE000E488)
-#define NVIC_PRI35              REG32(0xE000E48C)
-#define NVIC_PRI36              REG32(0xE000E490)
-#define NVIC_PRI37              REG32(0xE000E494)
-#define NVIC_PRI38              REG32(0xE000E498)
-#define NVIC_PRI39              REG32(0xE000E49C)
-#define NVIC_PRI40              REG32(0xE000E4A0)
-#define NVIC_PRI41              REG32(0xE000E4A4)
-#define NVIC_PRI42              REG32(0xE000E4A8)
-#define NVIC_PRI43              REG32(0xE000E4AC)
-#define NVIC_PRI44              REG32(0xE000E4B0)
-#define NVIC_PRI45              REG32(0xE000E4B4)
-#define NVIC_PRI46              REG32(0xE000E4B8)
-#define NVIC_PRI47              REG32(0xE000E4BC)
-#define NVIC_PRI48              REG32(0xE000E4C0)
-#define NVIC_PRI49              REG32(0xE000E4C4)
-#define NVIC_PRI50              REG32(0xE000E4C8)
-#define NVIC_PRI51              REG32(0xE000E4CC)
-#define NVIC_PRI52              REG32(0xE000E4D0)
-#define NVIC_PRI53              REG32(0xE000E4D4)
-#define NVIC_PRI54              REG32(0xE000E4D8)
-#define NVIC_PRI55              REG32(0xE000E4DC)
-#define NVIC_PRI56              REG32(0xE000E4E0)
-#define NVIC_PRI57              REG32(0xE000E4E4)
-#define NVIC_PRI58              REG32(0xE000E4E8)
-#define NVIC_PRI59              REG32(0xE000E4EC)
-#define NVIC_CPUID              REG32(0xE000ED00)
-#define NVIC_INT_CTRL           REG32(0xE000ED04)
-#define NVIC_VECT_TABLE         REG32(0xE000ED08)
-#define NVIC_AP_INT_RST         REG32(0xE000ED0C)
-#define NVIC_SYS_CTRL           REG32(0xE000ED10)
-#define NVIC_CFG_CTRL           REG32(0xE000ED14)
-#define NVIC_SYS_H_PRI1         REG32(0xE000ED18)
-#define NVIC_SYS_H_PRI2         REG32(0xE000ED1C)
-#define NVIC_SYS_H_PRI3         REG32(0xE000ED20)
-#define NVIC_SYS_H_CTRL         REG32(0xE000ED24)
-#define NVIC_FAULT_STA          REG32(0xE000ED28)
-#define NVIC_HARD_F_STA         REG32(0xE000ED2C)
-#define NVIC_DBG_F_STA          REG32(0xE000ED30)
-#define NVIC_MM_F_ADR           REG32(0xE000ED34)
-#define NVIC_BUS_F_ADR          REG32(0xE000ED38)
-#define NVIC_SW_TRIG            REG32(0xE000EF00)
-
-/* MPU Registers */
-#define MPU_TYPE                REG32(0xE000ED90)
-#define MPU_CTRL                REG32(0xE000ED94)
-#define MPU_RG_NUM              REG32(0xE000ED98)
-#define MPU_RG_ADDR             REG32(0xE000ED9C)
-#define MPU_RG_AT_SZ            REG32(0xE000EDA0)
-
-
-#endif /* #ifndef ARM_REG_H_ */
-
-/**   @}
- */
+/*
+ **********************************************************************************
+* � 2013 Microchip Technology Inc. and its subsidiaries.
+* You may use this software and any derivatives exclusively with
+* Microchip products.
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
+* OF THESE TERMS.
+ **********************************************************************************
+ *  ARM_REG.h
+ *      This is the header to define Cortex-M3 system control & status registers
+ **********************************************************************************
+ *  SMSC version control information (Perforce):
+ *
+ *  FILE:     $File: //depot_pcs/FWEng/Release/projects/CEC1302_PLIB_CLIB/release5/Source/hw_blks/common/include/ARM_REG.h $
+ *  REVISION: $Revision: #1 $
+ *  DATETIME: $DateTime: 2016/04/08 10:18:28 $
+ *  AUTHOR:   $Author: pramans $
+ *
+ *  Revision history (latest first):
+ *      #xx
+ ***********************************************************************************
+ */
+
+/******************************************************************************/
+/** @defgroup ARM_REG ARM_REG
+ *  @{
+ */
+
+/** @file ARM_REG.h
+* \brief ARM Cortex-M3 registers header file
+* \author KBCEC Team
+* 
+* This file contains ARM Cortex-M3 system control & status registers.
+******************************************************************************/   
+#ifndef ARM_REG_H_
+#define ARM_REG_H_
+
+#define REG8(x)  (*((volatile unsigned char  *)(x)))
+#define REG16(x) (*((volatile unsigned short *)(x)))
+#define REG32(x) (*((volatile unsigned long  *)(x)))
+
+/* NVIC Registers */
+#define NVIC_INT_TYPE           REG32(0xE000E004)
+#define NVIC_AUX_ACTLR          REG32(0xE000E008)
+    #define WR_BUF_DISABLE      (1 << 1)
+#define NVIC_ST_CTRL            REG32(0xE000E010)
+    #define ST_ENABLE           (1 << 0)
+    #define ST_TICKINT          (1 << 1)
+    #define ST_CLKSOURCE        (1 << 2)
+    #define ST_COUNTFLAG        (1 << 3)
+#define NVIC_ST_RELOAD          REG32(0xE000E014)
+#define NVIC_ST_CURRENT         REG32(0xE000E018)
+#define NVIC_ST_CALIB           REG32(0xE000E01C)
+#define NVIC_ENABLE0            REG32(0xE000E100)
+#define NVIC_ENABLE1            REG32(0xE000E104)
+#define NVIC_ENABLE2            REG32(0xE000E108)
+#define NVIC_ENABLE3            REG32(0xE000E10C)
+#define NVIC_ENABLE4            REG32(0xE000E110)
+#define NVIC_ENABLE5            REG32(0xE000E114)
+#define NVIC_ENABLE6            REG32(0xE000E118)
+#define NVIC_ENABLE7            REG32(0xE000E11C)
+#define NVIC_DISABLE0           REG32(0xE000E180)
+#define NVIC_DISABLE1           REG32(0xE000E184)
+#define NVIC_DISABLE2           REG32(0xE000E188)
+#define NVIC_DISABLE3           REG32(0xE000E18C)
+#define NVIC_DISABLE4           REG32(0xE000E190)
+#define NVIC_DISABLE5           REG32(0xE000E194)
+#define NVIC_DISABLE6           REG32(0xE000E198)
+#define NVIC_DISABLE7           REG32(0xE000E19C)
+#define NVIC_PEND0              REG32(0xE000E200)
+#define NVIC_PEND1              REG32(0xE000E204)
+#define NVIC_PEND2              REG32(0xE000E208)
+#define NVIC_PEND3              REG32(0xE000E20C)
+#define NVIC_PEND4              REG32(0xE000E210)
+#define NVIC_PEND5              REG32(0xE000E214)
+#define NVIC_PEND6              REG32(0xE000E218)
+#define NVIC_PEND7              REG32(0xE000E21C)
+#define NVIC_UNPEND0            REG32(0xE000E280)
+#define NVIC_UNPEND1            REG32(0xE000E284)
+#define NVIC_UNPEND2            REG32(0xE000E288)
+#define NVIC_UNPEND3            REG32(0xE000E28C)
+#define NVIC_UNPEND4            REG32(0xE000E290)
+#define NVIC_UNPEND5            REG32(0xE000E294)
+#define NVIC_UNPEND6            REG32(0xE000E298)
+#define NVIC_UNPEND7            REG32(0xE000E29C)
+#define NVIC_ACTIVE0            REG32(0xE000E300)
+#define NVIC_ACTIVE1            REG32(0xE000E304)
+#define NVIC_ACTIVE2            REG32(0xE000E308)
+#define NVIC_ACTIVE3            REG32(0xE000E30C)
+#define NVIC_ACTIVE4            REG32(0xE000E310)
+#define NVIC_ACTIVE5            REG32(0xE000E314)
+#define NVIC_ACTIVE6            REG32(0xE000E318)
+#define NVIC_ACTIVE7            REG32(0xE000E31C)
+#define NVIC_PRI0               REG32(0xE000E400)
+#define NVIC_PRI1               REG32(0xE000E404)
+#define NVIC_PRI2               REG32(0xE000E408)
+#define NVIC_PRI3               REG32(0xE000E40C)
+#define NVIC_PRI4               REG32(0xE000E410)
+#define NVIC_PRI5               REG32(0xE000E414)
+#define NVIC_PRI6               REG32(0xE000E418)
+#define NVIC_PRI7               REG32(0xE000E41C)
+#define NVIC_PRI8               REG32(0xE000E420)
+#define NVIC_PRI9               REG32(0xE000E424)
+#define NVIC_PRI10              REG32(0xE000E428)
+#define NVIC_PRI11              REG32(0xE000E42C)
+#define NVIC_PRI12              REG32(0xE000E430)
+#define NVIC_PRI13              REG32(0xE000E434)
+#define NVIC_PRI14              REG32(0xE000E438)
+#define NVIC_PRI15              REG32(0xE000E43C)
+#define NVIC_PRI16              REG32(0xE000E440)
+#define NVIC_PRI17              REG32(0xE000E444)
+#define NVIC_PRI18              REG32(0xE000E448)
+#define NVIC_PRI19              REG32(0xE000E44C)
+#define NVIC_PRI20              REG32(0xE000E450)
+#define NVIC_PRI21              REG32(0xE000E454)
+#define NVIC_PRI22              REG32(0xE000E458)
+#define NVIC_PRI23              REG32(0xE000E45C)
+#define NVIC_PRI24              REG32(0xE000E460)
+#define NVIC_PRI25              REG32(0xE000E464)
+#define NVIC_PRI26              REG32(0xE000E468)
+#define NVIC_PRI27              REG32(0xE000E46C)
+#define NVIC_PRI28              REG32(0xE000E470)
+#define NVIC_PRI29              REG32(0xE000E474)
+#define NVIC_PRI30              REG32(0xE000E478)
+#define NVIC_PRI31              REG32(0xE000E47C)
+#define NVIC_PRI32              REG32(0xE000E480)
+#define NVIC_PRI33              REG32(0xE000E484)
+#define NVIC_PRI34              REG32(0xE000E488)
+#define NVIC_PRI35              REG32(0xE000E48C)
+#define NVIC_PRI36              REG32(0xE000E490)
+#define NVIC_PRI37              REG32(0xE000E494)
+#define NVIC_PRI38              REG32(0xE000E498)
+#define NVIC_PRI39              REG32(0xE000E49C)
+#define NVIC_PRI40              REG32(0xE000E4A0)
+#define NVIC_PRI41              REG32(0xE000E4A4)
+#define NVIC_PRI42              REG32(0xE000E4A8)
+#define NVIC_PRI43              REG32(0xE000E4AC)
+#define NVIC_PRI44              REG32(0xE000E4B0)
+#define NVIC_PRI45              REG32(0xE000E4B4)
+#define NVIC_PRI46              REG32(0xE000E4B8)
+#define NVIC_PRI47              REG32(0xE000E4BC)
+#define NVIC_PRI48              REG32(0xE000E4C0)
+#define NVIC_PRI49              REG32(0xE000E4C4)
+#define NVIC_PRI50              REG32(0xE000E4C8)
+#define NVIC_PRI51              REG32(0xE000E4CC)
+#define NVIC_PRI52              REG32(0xE000E4D0)
+#define NVIC_PRI53              REG32(0xE000E4D4)
+#define NVIC_PRI54              REG32(0xE000E4D8)
+#define NVIC_PRI55              REG32(0xE000E4DC)
+#define NVIC_PRI56              REG32(0xE000E4E0)
+#define NVIC_PRI57              REG32(0xE000E4E4)
+#define NVIC_PRI58              REG32(0xE000E4E8)
+#define NVIC_PRI59              REG32(0xE000E4EC)
+#define NVIC_CPUID              REG32(0xE000ED00)
+#define NVIC_INT_CTRL           REG32(0xE000ED04)
+#define NVIC_VECT_TABLE         REG32(0xE000ED08)
+#define NVIC_AP_INT_RST         REG32(0xE000ED0C)
+#define NVIC_SYS_CTRL           REG32(0xE000ED10)
+#define NVIC_CFG_CTRL           REG32(0xE000ED14)
+#define NVIC_SYS_H_PRI1         REG32(0xE000ED18)
+#define NVIC_SYS_H_PRI2         REG32(0xE000ED1C)
+#define NVIC_SYS_H_PRI3         REG32(0xE000ED20)
+#define NVIC_SYS_H_CTRL         REG32(0xE000ED24)
+#define NVIC_FAULT_STA          REG32(0xE000ED28)
+#define NVIC_HARD_F_STA         REG32(0xE000ED2C)
+#define NVIC_DBG_F_STA          REG32(0xE000ED30)
+#define NVIC_MM_F_ADR           REG32(0xE000ED34)
+#define NVIC_BUS_F_ADR          REG32(0xE000ED38)
+#define NVIC_SW_TRIG            REG32(0xE000EF00)
+
+/* MPU Registers */
+#define MPU_TYPE                REG32(0xE000ED90)
+#define MPU_CTRL                REG32(0xE000ED94)
+#define MPU_RG_NUM              REG32(0xE000ED98)
+#define MPU_RG_ADDR             REG32(0xE000ED9C)
+#define MPU_RG_AT_SZ            REG32(0xE000EDA0)
+
+
+#endif /* #ifndef ARM_REG_H_ */
+
+/**   @}
+ */
diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/MCHP_CEC1302.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/MCHP_CEC1302.h
index b451de0f6..ffa6281f9 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/MCHP_CEC1302.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/MCHP_CEC1302.h
@@ -963,7 +963,7 @@ typedef struct {                                    /*!< ACPI_EC0 Structure
     struct {
       __I  uint8_t   OBF        :  1;               /*!< Output Buffer Full bit                                                */
       __I  uint8_t   IBF        :  1;               /*!< Input Buffer Full bit                                                 */
-      __I  uint8_t   UD1A       :  1;               /*!< User Defined                                                          */
+      __IO uint8_t   UD1A       :  1;               /*!< User Defined                                                          */
       __I  uint8_t   CMD        :  1;               /*!< OS2EC Data contains a command byte                                    */
       __IO uint8_t   BURST      :  1;               /*!< set when the ACPI_EC is in Burst Mode                                 */
       __IO uint8_t   SCI_EVT    :  1;               /*!< set when an SCI event is pending                                      */
@@ -975,8 +975,8 @@ typedef struct {                                    /*!< ACPI_EC0 Structure
   __I  uint16_t  RESERVED1;
   
   union {
-    __IO uint32_t  OS2EC_DATA;                      /*!< OS2EC Data EC-Register                                                */
-    __IO uint8_t   OS2EC_DATA_BYTE[4];              /*!< OS2EC Data Bytes                                                      */
+    __I uint32_t  OS2EC_DATA;                       /*!< OS2EC Data EC-Register                                                */
+    __I uint8_t   OS2EC_DATA_BYTE[4];               /*!< OS2EC Data Bytes                                                      */
   };
 } ACPI_EC0_Type;
 
@@ -1034,7 +1034,7 @@ typedef struct {                                    /*!< KBC Structure
       __IO uint8_t   UD0        :  1;               /*!< User-defined data.                                                    */
       __I  uint8_t   CMDnDATA   :  1;               /*!< data register contains data(0) or command(1)                          */
       __IO uint8_t   UD1        :  1;               /*!< User-defined data.                                                    */
-      __IO uint8_t   AUXOBF     :  1;               /*!< Auxiliary Output Buffer Full.                                         */
+      __I  uint8_t   AUXOBF     :  1;               /*!< Auxiliary Output Buffer Full.                                         */
       __IO uint8_t   UD2        :  2;               /*!< User-defined data.                                                    */
     } STATUS_b;                                     /*!< BitSize                                                               */
   };
@@ -1087,7 +1087,7 @@ typedef struct {                                    /*!< PORT92 Structure
   __I  uint8_t   RESERVED1[7];
   __O  uint8_t   SETGA20L;                          /*!< write to set GATEA20 in GATEA20 Control Reg                           */
   __I  uint8_t   RESERVED2[3];
-  __IO uint8_t   RSTGA20L;                          /*!< write to set GATEA20 in GATEA20 Control Reg                           */
+  __O  uint8_t   RSTGA20L;                          /*!< write to set GATEA20 in GATEA20 Control Reg                           */
   __I  uint8_t   RESERVED3[547];
   __IO uint8_t   PORT92_ENABLE;                     /*!< [0:0] 1= Port92h Register is enabled.                                 */
 } PORT92_Type;
@@ -2110,8 +2110,7 @@ typedef struct {                                    /*!< RPM_FAN Structure
   __IO uint8_t   VALID_TACH_COUNT;                  /*!< max value to indicate fan spin properly                               */
   __IO uint16_t  DRIVE_FAIL_BAND;                   /*!< [15:3]counts for Drive Fail circuitry                                 */
   __IO uint16_t  TACH_TARGET;                       /*!< [12:0] The target tachometer value.                                   */
-  __IO uint8_t   TACH_READING;                      /*!< [15:3]current tachometer reading value.                               */
-  __I  uint8_t   RESERVED1;
+  __IO uint16_t  TACH_READING;                      /*!< [15:3]current tachometer reading value.                               */
   __IO uint8_t   DRIVER_BASE_FREQUENCY;             /*!< [1:0]frequency range of the PWM fan driver                            */
   
   union {
@@ -2513,7 +2512,7 @@ typedef struct {                                    /*!< JTAG Structure
 
 
 /*------------- Public Key Encryption Subsystem (PKE) -----------------------------*/
-/** @addtogroup MEC1322_PKE Public Key Encryption (PKE)
+/** @addtogroup CEC1302_PKE Public Key Encryption (PKE)
   @{
 */
 typedef struct
@@ -2525,10 +2524,10 @@ typedef struct
     __I     uint32_t VERSION;               /*!< Offset: 0x0010  Version */
     __IO    uint32_t LOAD_MICRO_CODE;       /*!< Offset: 0x0014  Load Micro Code */
 } PKE_TypeDef;
-/*@}*/ /* end of group MEC1322_PKE */
+/*@}*/ /* end of group CEC1302_PKE */
 
 /*------------- Random Number Generator Subsystem (TRNG) -----------------------------*/
-/** @addtogroup MEC1322_TRNG Random Number Generator (TRNG)
+/** @addtogroup CEC1302_TRNG Random Number Generator (TRNG)
   @{
 */
 typedef struct
@@ -2537,10 +2536,10 @@ typedef struct
     __I     uint32_t FIFO_LEVEL;            /*!< Offset: 0x0004  FIFO Level */
     __I     uint32_t VERSION;               /*!< Offset: 0x0008  Version */
 } TRNG_TypeDef;
-/*@}*/ /* end of group MEC1322_TRNG */
+/*@}*/ /* end of group CEC1302_TRNG */
 
 /*------------- Hash Subsystem (HASH) -----------------------------*/
-/** @addtogroup MEC1322_HASH Hash Security (HASH)
+/** @addtogroup CEC1302_HASH Hash Security (HASH)
   @{
 */
 typedef struct
@@ -2555,12 +2554,12 @@ typedef struct
     __IO    uint32_t DATA_SOURCE_ADDR;      /*!< Offset: 0x001C  Data to hash Address */
     __IO    uint32_t HASH_RESULT_ADDR;      /*!< Offset: 0x0020  Hash result address */
 } HASH_TypeDef;
-/*@}*/ /* end of group MEC1322_HASH */
+/*@}*/ /* end of group CEC1302_HASH */
 
 
 
 /*------------- Advanced Encryption Subsystem (AES) -----------------------------*/
-/** @addtogroup MEC1322_AES Advanced Encryption Subsys (AES)
+/** @addtogroup CEC1302_AES Advanced Encryption Subsys (AES)
   @{
 */
 
@@ -2603,7 +2602,7 @@ typedef struct
                                               !< Offset: 0x0158  KeyIn1[95:64] 
                                               !< Offset: 0x015C  KeyIn1[127:96] */
 } AES_TypeDef;
-/*@}*/ /* end of group MEC1322_AES */
+/*@}*/ /* end of group CEC1302_AES */
 
 /* --------------------  End of section using anonymous unions  ------------------- */
 #if defined(__CC_ARM)
@@ -3281,114 +3280,6 @@ typedef struct
 
 
 /* ================================================================================ */
-/* ================        struct 'ACPI_EC1' Position & Mask       ================ */
-/* ================================================================================ */
-
-
-/* -----------------------------  ACPI_EC1_OS_STATUS  ----------------------------- */
-#define ACPI_EC1_OS_STATUS_OBF_Pos            (0UL)                     /*!< ACPI_EC1 OS_STATUS: OBF (Bit 0)                             */
-#define ACPI_EC1_OS_STATUS_OBF_Msk            (0x1UL)                   /*!< ACPI_EC1 OS_STATUS: OBF (Bitfield-Mask: 0x01)               */
-#define ACPI_EC1_OS_STATUS_IBF_Pos            (1UL)                     /*!< ACPI_EC1 OS_STATUS: IBF (Bit 1)                             */
-#define ACPI_EC1_OS_STATUS_IBF_Msk            (0x2UL)                   /*!< ACPI_EC1 OS_STATUS: IBF (Bitfield-Mask: 0x01)               */
-#define ACPI_EC1_OS_STATUS_UD1B_Pos           (2UL)                     /*!< ACPI_EC1 OS_STATUS: UD1B (Bit 2)                            */
-#define ACPI_EC1_OS_STATUS_UD1B_Msk           (0x4UL)                   /*!< ACPI_EC1 OS_STATUS: UD1B (Bitfield-Mask: 0x01)              */
-#define ACPI_EC1_OS_STATUS_CMD_Pos            (3UL)                     /*!< ACPI_EC1 OS_STATUS: CMD (Bit 3)                             */
-#define ACPI_EC1_OS_STATUS_CMD_Msk            (0x8UL)                   /*!< ACPI_EC1 OS_STATUS: CMD (Bitfield-Mask: 0x01)               */
-#define ACPI_EC1_OS_STATUS_BURST_Pos          (4UL)                     /*!< ACPI_EC1 OS_STATUS: BURST (Bit 4)                           */
-#define ACPI_EC1_OS_STATUS_BURST_Msk          (0x10UL)                  /*!< ACPI_EC1 OS_STATUS: BURST (Bitfield-Mask: 0x01)             */
-#define ACPI_EC1_OS_STATUS_SCI_EVT_Pos        (5UL)                     /*!< ACPI_EC1 OS_STATUS: SCI_EVT (Bit 5)                         */
-#define ACPI_EC1_OS_STATUS_SCI_EVT_Msk        (0x20UL)                  /*!< ACPI_EC1 OS_STATUS: SCI_EVT (Bitfield-Mask: 0x01)           */
-#define ACPI_EC1_OS_STATUS_SMI_EVT_Pos        (6UL)                     /*!< ACPI_EC1 OS_STATUS: SMI_EVT (Bit 6)                         */
-#define ACPI_EC1_OS_STATUS_SMI_EVT_Msk        (0x40UL)                  /*!< ACPI_EC1 OS_STATUS: SMI_EVT (Bitfield-Mask: 0x01)           */
-#define ACPI_EC1_OS_STATUS_UD0B_Pos           (7UL)                     /*!< ACPI_EC1 OS_STATUS: UD0B (Bit 7)                            */
-#define ACPI_EC1_OS_STATUS_UD0B_Msk           (0x80UL)                  /*!< ACPI_EC1 OS_STATUS: UD0B (Bitfield-Mask: 0x01)              */
-
-/* -----------------------------  ACPI_EC1_EC_STATUS  ----------------------------- */
-#define ACPI_EC1_EC_STATUS_OBF_Pos            (0UL)                     /*!< ACPI_EC1 EC_STATUS: OBF (Bit 0)                             */
-#define ACPI_EC1_EC_STATUS_OBF_Msk            (0x1UL)                   /*!< ACPI_EC1 EC_STATUS: OBF (Bitfield-Mask: 0x01)               */
-#define ACPI_EC1_EC_STATUS_IBF_Pos            (1UL)                     /*!< ACPI_EC1 EC_STATUS: IBF (Bit 1)                             */
-#define ACPI_EC1_EC_STATUS_IBF_Msk            (0x2UL)                   /*!< ACPI_EC1 EC_STATUS: IBF (Bitfield-Mask: 0x01)               */
-#define ACPI_EC1_EC_STATUS_UD1A_Pos           (2UL)                     /*!< ACPI_EC1 EC_STATUS: UD1A (Bit 2)                            */
-#define ACPI_EC1_EC_STATUS_UD1A_Msk           (0x4UL)                   /*!< ACPI_EC1 EC_STATUS: UD1A (Bitfield-Mask: 0x01)              */
-#define ACPI_EC1_EC_STATUS_CMD_Pos            (3UL)                     /*!< ACPI_EC1 EC_STATUS: CMD (Bit 3)                             */
-#define ACPI_EC1_EC_STATUS_CMD_Msk            (0x8UL)                   /*!< ACPI_EC1 EC_STATUS: CMD (Bitfield-Mask: 0x01)               */
-#define ACPI_EC1_EC_STATUS_BURST_Pos          (4UL)                     /*!< ACPI_EC1 EC_STATUS: BURST (Bit 4)                           */
-#define ACPI_EC1_EC_STATUS_BURST_Msk          (0x10UL)                  /*!< ACPI_EC1 EC_STATUS: BURST (Bitfield-Mask: 0x01)             */
-#define ACPI_EC1_EC_STATUS_SCI_EVT_Pos        (5UL)                     /*!< ACPI_EC1 EC_STATUS: SCI_EVT (Bit 5)                         */
-#define ACPI_EC1_EC_STATUS_SCI_EVT_Msk        (0x20UL)                  /*!< ACPI_EC1 EC_STATUS: SCI_EVT (Bitfield-Mask: 0x01)           */
-#define ACPI_EC1_EC_STATUS_SMI_EVT_Pos        (6UL)                     /*!< ACPI_EC1 EC_STATUS: SMI_EVT (Bit 6)                         */
-#define ACPI_EC1_EC_STATUS_SMI_EVT_Msk        (0x40UL)                  /*!< ACPI_EC1 EC_STATUS: SMI_EVT (Bitfield-Mask: 0x01)           */
-#define ACPI_EC1_EC_STATUS_UD0A_Pos           (7UL)                     /*!< ACPI_EC1 EC_STATUS: UD0A (Bit 7)                            */
-#define ACPI_EC1_EC_STATUS_UD0A_Msk           (0x80UL)                  /*!< ACPI_EC1 EC_STATUS: UD0A (Bitfield-Mask: 0x01)              */
-
-
-/* ================================================================================ */
-/* ================          struct 'KBC' Position & Mask          ================ */
-/* ================================================================================ */
-
-
-/* ----------------------------  KBC_RD_PORT64_STATUS  ---------------------------- */
-#define KBC_RD_PORT64_STATUS_OBF_Pos          (0UL)                     /*!< KBC RD_PORT64_STATUS: OBF (Bit 0)                           */
-#define KBC_RD_PORT64_STATUS_OBF_Msk          (0x1UL)                   /*!< KBC RD_PORT64_STATUS: OBF (Bitfield-Mask: 0x01)             */
-#define KBC_RD_PORT64_STATUS_IBF_Pos          (1UL)                     /*!< KBC RD_PORT64_STATUS: IBF (Bit 1)                           */
-#define KBC_RD_PORT64_STATUS_IBF_Msk          (0x2UL)                   /*!< KBC RD_PORT64_STATUS: IBF (Bitfield-Mask: 0x01)             */
-#define KBC_RD_PORT64_STATUS_UD0_Pos          (2UL)                     /*!< KBC RD_PORT64_STATUS: UD0 (Bit 2)                           */
-#define KBC_RD_PORT64_STATUS_UD0_Msk          (0x4UL)                   /*!< KBC RD_PORT64_STATUS: UD0 (Bitfield-Mask: 0x01)             */
-#define KBC_RD_PORT64_STATUS_CMDnDATA_Pos     (3UL)                     /*!< KBC RD_PORT64_STATUS: CMDnDATA (Bit 3)                      */
-#define KBC_RD_PORT64_STATUS_CMDnDATA_Msk     (0x8UL)                   /*!< KBC RD_PORT64_STATUS: CMDnDATA (Bitfield-Mask: 0x01)        */
-#define KBC_RD_PORT64_STATUS_UD1_Pos          (4UL)                     /*!< KBC RD_PORT64_STATUS: UD1 (Bit 4)                           */
-#define KBC_RD_PORT64_STATUS_UD1_Msk          (0x10UL)                  /*!< KBC RD_PORT64_STATUS: UD1 (Bitfield-Mask: 0x01)             */
-#define KBC_RD_PORT64_STATUS_AUXOBF_Pos       (5UL)                     /*!< KBC RD_PORT64_STATUS: AUXOBF (Bit 5)                        */
-#define KBC_RD_PORT64_STATUS_AUXOBF_Msk       (0x20UL)                  /*!< KBC RD_PORT64_STATUS: AUXOBF (Bitfield-Mask: 0x01)          */
-#define KBC_RD_PORT64_STATUS_UD2_Pos          (6UL)                     /*!< KBC RD_PORT64_STATUS: UD2 (Bit 6)                           */
-#define KBC_RD_PORT64_STATUS_UD2_Msk          (0xc0UL)                  /*!< KBC RD_PORT64_STATUS: UD2 (Bitfield-Mask: 0x03)             */
-
-/* ---------------------------------  KBC_STATUS  --------------------------------- */
-#define KBC_STATUS_OBF_Pos                    (0UL)                     /*!< KBC STATUS: OBF (Bit 0)                                     */
-#define KBC_STATUS_OBF_Msk                    (0x1UL)                   /*!< KBC STATUS: OBF (Bitfield-Mask: 0x01)                       */
-#define KBC_STATUS_IBF_Pos                    (1UL)                     /*!< KBC STATUS: IBF (Bit 1)                                     */
-#define KBC_STATUS_IBF_Msk                    (0x2UL)                   /*!< KBC STATUS: IBF (Bitfield-Mask: 0x01)                       */
-#define KBC_STATUS_UD0_Pos                    (2UL)                     /*!< KBC STATUS: UD0 (Bit 2)                                     */
-#define KBC_STATUS_UD0_Msk                    (0x4UL)                   /*!< KBC STATUS: UD0 (Bitfield-Mask: 0x01)                       */
-#define KBC_STATUS_CMDnDATA_Pos               (3UL)                     /*!< KBC STATUS: CMDnDATA (Bit 3)                                */
-#define KBC_STATUS_CMDnDATA_Msk               (0x8UL)                   /*!< KBC STATUS: CMDnDATA (Bitfield-Mask: 0x01)                  */
-#define KBC_STATUS_UD1_Pos                    (4UL)                     /*!< KBC STATUS: UD1 (Bit 4)                                     */
-#define KBC_STATUS_UD1_Msk                    (0x10UL)                  /*!< KBC STATUS: UD1 (Bitfield-Mask: 0x01)                       */
-#define KBC_STATUS_AUXOBF_Pos                 (5UL)                     /*!< KBC STATUS: AUXOBF (Bit 5)                                  */
-#define KBC_STATUS_AUXOBF_Msk                 (0x20UL)                  /*!< KBC STATUS: AUXOBF (Bitfield-Mask: 0x01)                    */
-#define KBC_STATUS_UD2_Pos                    (6UL)                     /*!< KBC STATUS: UD2 (Bit 6)                                     */
-#define KBC_STATUS_UD2_Msk                    (0xc0UL)                  /*!< KBC STATUS: UD2 (Bitfield-Mask: 0x03)                       */
-
-/* ---------------------------------  KBC_CONTROL  -------------------------------- */
-#define KBC_CONTROL_UD3_Pos                   (0UL)                     /*!< KBC CONTROL: UD3 (Bit 0)                                    */
-#define KBC_CONTROL_UD3_Msk                   (0x1UL)                   /*!< KBC CONTROL: UD3 (Bitfield-Mask: 0x01)                      */
-#define KBC_CONTROL_SAEN_Pos                  (1UL)                     /*!< KBC CONTROL: SAEN (Bit 1)                                   */
-#define KBC_CONTROL_SAEN_Msk                  (0x2UL)                   /*!< KBC CONTROL: SAEN (Bitfield-Mask: 0x01)                     */
-#define KBC_CONTROL_PCOBFEN_Pos               (2UL)                     /*!< KBC CONTROL: PCOBFEN (Bit 2)                                */
-#define KBC_CONTROL_PCOBFEN_Msk               (0x4UL)                   /*!< KBC CONTROL: PCOBFEN (Bitfield-Mask: 0x01)                  */
-#define KBC_CONTROL_UD4_Pos                   (3UL)                     /*!< KBC CONTROL: UD4 (Bit 3)                                    */
-#define KBC_CONTROL_UD4_Msk                   (0x18UL)                  /*!< KBC CONTROL: UD4 (Bitfield-Mask: 0x03)                      */
-#define KBC_CONTROL_OBFEN_Pos                 (5UL)                     /*!< KBC CONTROL: OBFEN (Bit 5)                                  */
-#define KBC_CONTROL_OBFEN_Msk                 (0x20UL)                  /*!< KBC CONTROL: OBFEN (Bitfield-Mask: 0x01)                    */
-#define KBC_CONTROL_UD5_Pos                   (6UL)                     /*!< KBC CONTROL: UD5 (Bit 6)                                    */
-#define KBC_CONTROL_UD5_Msk                   (0x40UL)                  /*!< KBC CONTROL: UD5 (Bitfield-Mask: 0x01)                      */
-#define KBC_CONTROL_AUXH_Pos                  (7UL)                     /*!< KBC CONTROL: AUXH (Bit 7)                                   */
-#define KBC_CONTROL_AUXH_Msk                  (0x80UL)                  /*!< KBC CONTROL: AUXH (Bitfield-Mask: 0x01)                     */
-
-
-/* ================================================================================ */
-/* ================         struct 'PORT92' Position & Mask        ================ */
-/* ================================================================================ */
-
-
-/* --------------------------------  PORT92_PORT92  ------------------------------- */
-#define PORT92_PORT92_ALT_CPU_RESET_Pos       (0UL)                     /*!< PORT92 PORT92: ALT_CPU_RESET (Bit 0)                        */
-#define PORT92_PORT92_ALT_CPU_RESET_Msk       (0x1UL)                   /*!< PORT92 PORT92: ALT_CPU_RESET (Bitfield-Mask: 0x01)          */
-#define PORT92_PORT92_ALT_GATE_A20_Pos        (1UL)                     /*!< PORT92 PORT92: ALT_GATE_A20 (Bit 1)                         */
-#define PORT92_PORT92_ALT_GATE_A20_Msk        (0x2UL)                   /*!< PORT92 PORT92: ALT_GATE_A20 (Bitfield-Mask: 0x01)           */
-
-
-/* ================================================================================ */
 /* ================          struct 'MBX' Position & Mask          ================ */
 /* ================================================================================ */
 
diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/MEC1322.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/MEC1322.h
deleted file mode 100644
index 91f3c8ead..000000000
--- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/MEC1322.h
+++ /dev/null
@@ -1,2862 +0,0 @@
-/*******************************************************************************
-* © 2013 Microchip Technology Inc. and its subsidiaries.
-* You may use this software and any derivatives exclusively with
-* Microchip products.
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
-* OF THESE TERMS.
-********************************************************************************
-
-Version Control Information (Perforce)
-$File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/MEC1322.h $
-********************************************************************************
-$Revision: #1 $
-$DateTime: 2015/12/23 15:37:58 $
-$Author: akrishnan $
- Change Description:  Initial revision for MEC1322
-******************************************************************************/
-/** @file smscmmcr.h
-*  brief the mmcr definitions
-* 
-******************************************************************************/
-#ifndef SMSCMMCR_H_
-#define SMSCMMCR_H_
-
-//NOTE: Please Don't edit this File, this is extrated from the Spread sheet 
-//    : //depotAE/projects/MEC1322/docs/MMCRs/MEC1322_FPGA1_Query_All_Addressing_ResultSet.csv
-typedef volatile unsigned char      VUINT8;
-typedef volatile unsigned short int VUINT16;
-typedef volatile unsigned long int  VUINT32;
-
-/***************************************************************
-*                            PWM
-***************************************************************/
-#define ADDR_PWM_0_COUNTER_ON_TIME                               0x40005800
-#define MMCR_PWM_0_COUNTER_ON_TIME                               (*(VUINT32 *)(ADDR_PWM_0_COUNTER_ON_TIME))
-
-#define ADDR_PWM_0_COUNTER_OFF_TIME                              0x40005804
-#define MMCR_PWM_0_COUNTER_OFF_TIME                              (*(VUINT32 *)(ADDR_PWM_0_COUNTER_OFF_TIME))
-
-#define ADDR_PWM_0_CONFIGURATION                                 0x40005808
-#define MMCR_PWM_0_CONFIGURATION                                 (*(VUINT32 *)(ADDR_PWM_0_CONFIGURATION))
-
-#define ADDR_PWM_1_COUNTER_ON_TIME                               0x40005810
-#define MMCR_PWM_1_COUNTER_ON_TIME                               (*(VUINT32 *)(ADDR_PWM_1_COUNTER_ON_TIME))
-
-#define ADDR_PWM_1_COUNTER_OFF_TIME                              0x40005814
-#define MMCR_PWM_1_COUNTER_OFF_TIME                              (*(VUINT32 *)(ADDR_PWM_1_COUNTER_OFF_TIME))
-
-#define ADDR_PWM_1_CONFIGURATION                                 0x40005818
-#define MMCR_PWM_1_CONFIGURATION                                 (*(VUINT32 *)(ADDR_PWM_1_CONFIGURATION))
-
-#define ADDR_PWM_2_COUNTER_ON_TIME                               0x40005820
-#define MMCR_PWM_2_COUNTER_ON_TIME                               (*(VUINT32 *)(ADDR_PWM_2_COUNTER_ON_TIME))
-
-#define ADDR_PWM_2_COUNTER_OFF_TIME                              0x40005824
-#define MMCR_PWM_2_COUNTER_OFF_TIME                              (*(VUINT32 *)(ADDR_PWM_2_COUNTER_OFF_TIME))
-
-#define ADDR_PWM_2_CONFIGURATION                                 0x40005828
-#define MMCR_PWM_2_CONFIGURATION                                 (*(VUINT32 *)(ADDR_PWM_2_CONFIGURATION))
-
-#define ADDR_PWM_3_COUNTER_ON_TIME                               0x40005830
-#define MMCR_PWM_3_COUNTER_ON_TIME                               (*(VUINT32 *)(ADDR_PWM_3_COUNTER_ON_TIME))
-
-#define ADDR_PWM_3_COUNTER_OFF_TIME                              0x40005834
-#define MMCR_PWM_3_COUNTER_OFF_TIME                              (*(VUINT32 *)(ADDR_PWM_3_COUNTER_OFF_TIME))
-
-#define ADDR_PWM_3_CONFIGURATION                                 0x40005838
-#define MMCR_PWM_3_CONFIGURATION                                 (*(VUINT32 *)(ADDR_PWM_3_CONFIGURATION))
-
-/***************************************************************
-*                            PECI
-***************************************************************/
-#define ADDR_PECI_WRITE_DATA                                     0x40006400
-#define MMCR_PECI_WRITE_DATA                                     (*(VUINT32 *)(ADDR_PECI_WRITE_DATA))
-
-#define ADDR_PECI_READ_DATA                                      0x40006404
-#define MMCR_PECI_READ_DATA                                      (*(VUINT32 *)(ADDR_PECI_READ_DATA))
-
-#define ADDR_PECI_CONTROL                                        0x40006408
-#define MMCR_PECI_CONTROL                                        (*(VUINT32 *)(ADDR_PECI_CONTROL))
-
-#define ADDR_PECI_STATUS_1                                       0x4000640C
-#define MMCR_PECI_STATUS_1                                       (*(VUINT32 *)(ADDR_PECI_STATUS_1))
-
-#define ADDR_PECI_STATUS_2                                       0x40006410
-#define MMCR_PECI_STATUS_2                                       (*(VUINT32 *)(ADDR_PECI_STATUS_2))
-
-#define ADDR_PECI_ERROR                                          0x40006414
-#define MMCR_PECI_ERROR                                          (*(VUINT32 *)(ADDR_PECI_ERROR))
-
-#define ADDR_PECI_INTERRUPT_ENABLE_1                             0x40006418
-#define MMCR_PECI_INTERRUPT_ENABLE_1                             (*(VUINT32 *)(ADDR_PECI_INTERRUPT_ENABLE_1))
-
-#define ADDR_PECI_INTERRUPT_ENABLE_2                             0x4000641C
-#define MMCR_PECI_INTERRUPT_ENABLE_2                             (*(VUINT32 *)(ADDR_PECI_INTERRUPT_ENABLE_2))
-
-#define ADDR_PECI_OPTIMAL_BIT_TIME_LOW_BYTE                      0x40006420
-#define MMCR_PECI_OPTIMAL_BIT_TIME_LOW_BYTE                      (*(VUINT32 *)(ADDR_PECI_OPTIMAL_BIT_TIME_LOW_BYTE))
-
-#define ADDR_PECI_OPTIMAL_BIT_TIME_HIGH_BYTE                     0x40006424
-#define MMCR_PECI_OPTIMAL_BIT_TIME_HIGH_BYTE                     (*(VUINT32 *)(ADDR_PECI_OPTIMAL_BIT_TIME_HIGH_BYTE))
-
-#define ADDR_PECI_REQUEST_TIMER_LOW_BYTE                         0x40006428
-#define MMCR_PECI_REQUEST_TIMER_LOW_BYTE                         (*(VUINT32 *)(ADDR_PECI_REQUEST_TIMER_LOW_BYTE))
-
-#define ADDR_PECI_REQUEST_TIMER_HIGH_BYTE                        0x4000642C
-#define MMCR_PECI_REQUEST_TIMER_HIGH_BYTE                        (*(VUINT32 *)(ADDR_PECI_REQUEST_TIMER_HIGH_BYTE))
-
-#define ADDR_PECI_BLOCK_ID                                       0x40006440
-#define MMCR_PECI_BLOCK_ID                                       (*(VUINT32 *)(ADDR_PECI_BLOCK_ID))
-
-#define ADDR_PECI_BLOCK_REVISION                                 0x40006444
-#define MMCR_PECI_BLOCK_REVISION                                 (*(VUINT32 *)(ADDR_PECI_BLOCK_REVISION))
-
-/***************************************************************
-*                            ACPI EC Interface 
-***************************************************************/
-#define ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_0                         0x400F0D00
-#define MMCR_ACPI_0_EC2OS_DATA_EC_BYTE_0                         (*(VUINT8 *)(ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_0))
-
-#define ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_1                         0x400F0D01
-#define MMCR_ACPI_0_EC2OS_DATA_EC_BYTE_1                         (*(VUINT8 *)(ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_1))
-
-#define ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_2                         0x400F0D02
-#define MMCR_ACPI_0_EC2OS_DATA_EC_BYTE_2                         (*(VUINT8 *)(ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_2))
-
-#define ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_3                         0x400F0D03
-#define MMCR_ACPI_0_EC2OS_DATA_EC_BYTE_3                         (*(VUINT8 *)(ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_3))
-
-#define ADDR_ACPI_0_STATUS_EC                                    0x400F0D04
-#define MMCR_ACPI_0_STATUS_EC                                    (*(VUINT8 *)(ADDR_ACPI_0_STATUS_EC))
-
-#define ADDR_ACPI_0_BYTE_CONTROL_EC                              0x400F0D05
-#define MMCR_ACPI_0_BYTE_CONTROL_EC                              (*(VUINT8 *)(ADDR_ACPI_0_BYTE_CONTROL_EC))
-
-#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_0                         0x400F0D08
-#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_0                         (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_0))
-
-#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_0                         0x400F0D08
-#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_0                         (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_0))
-
-#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_1                         0x400F0D09
-#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_1                         (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_1))
-
-#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_2                         0x400F0D0A
-#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_2                         (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_2))
-
-#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_3                         0x400F0D0B
-#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_3                         (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_3))
-
-#define ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_0                         0x400F1100
-#define MMCR_ACPI_1_EC2OS_DATA_EC_BYTE_0                         (*(VUINT8 *)(ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_0))
-
-#define ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_1                         0x400F1101
-#define MMCR_ACPI_1_EC2OS_DATA_EC_BYTE_1                         (*(VUINT8 *)(ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_1))
-
-#define ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_2                         0x400F1102
-#define MMCR_ACPI_1_EC2OS_DATA_EC_BYTE_2                         (*(VUINT8 *)(ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_2))
-
-#define ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_3                         0x400F1103
-#define MMCR_ACPI_1_EC2OS_DATA_EC_BYTE_3                         (*(VUINT8 *)(ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_3))
-
-#define ADDR_ACPI_1_STATUS_EC                                    0x400F1104
-#define MMCR_ACPI_1_STATUS_EC                                    (*(VUINT8 *)(ADDR_ACPI_1_STATUS_EC))
-
-#define ADDR_ACPI_1_BYTE_CONTROL_EC                              0x400F1105
-#define MMCR_ACPI_1_BYTE_CONTROL_EC                              (*(VUINT8 *)(ADDR_ACPI_1_BYTE_CONTROL_EC))
-
-#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_0                         0x400F1108
-#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_0                         (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_0))
-
-#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_0                         0x400F1108
-#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_0                         (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_0))
-
-#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_1                         0x400F1109
-#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_1                         (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_1))
-
-#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_2                         0x400F110A
-#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_2                         (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_2))
-
-#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_3                         0x400F110B
-#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_3                         (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_3))
-
-/***************************************************************
-*                            Keyboard Matrix Scan Support
-***************************************************************/
-#define ADDR_KEYBOARD_KSO_SELECT                                 0x40009C04
-#define MMCR_KEYBOARD_KSO_SELECT                                 (*(VUINT32 *)(ADDR_KEYBOARD_KSO_SELECT))
-
-#define ADDR_KEYBOARD_KSI_INPUT                                  0x40009C08
-#define MMCR_KEYBOARD_KSI_INPUT                                  (*(VUINT32 *)(ADDR_KEYBOARD_KSI_INPUT))
-
-#define ADDR_KEYBOARD_KSI_STATUS                                 0x40009C0C
-#define MMCR_KEYBOARD_KSI_STATUS                                 (*(VUINT32 *)(ADDR_KEYBOARD_KSI_STATUS))
-
-#define ADDR_KEYBOARD_KSI_INTERRUPT_ENABLE                       0x40009C10
-#define MMCR_KEYBOARD_KSI_INTERRUPT_ENABLE                       (*(VUINT32 *)(ADDR_KEYBOARD_KSI_INTERRUPT_ENABLE))
-
-#define ADDR_KEYBOARD_KEYSCAN_EXTENDED_CONTROL                   0x40009C14
-#define MMCR_KEYBOARD_KEYSCAN_EXTENDED_CONTROL                   (*(VUINT32 *)(ADDR_KEYBOARD_KEYSCAN_EXTENDED_CONTROL))
-
-/***************************************************************
-*                            PS/2 Device Interface
-***************************************************************/
-#define ADDR_PS2_3_STATUS                                        0x400090C8
-#define MMCR_PS2_3_STATUS                                        (*(VUINT8 *)(ADDR_PS2_3_STATUS))
-
-#define ADDR_PS2_3_CONTROL                                       0x400090C4
-#define MMCR_PS2_3_CONTROL                                       (*(VUINT8 *)(ADDR_PS2_3_CONTROL))
-
-#define ADDR_PS2_3_RECEIVE_BUFFER                                0x400090C0
-#define MMCR_PS2_3_RECEIVE_BUFFER                                (*(VUINT8 *)(ADDR_PS2_3_RECEIVE_BUFFER))
-
-#define ADDR_PS2_3_TRANSMIT_BUFFER                               0x400090C0
-#define MMCR_PS2_3_TRANSMIT_BUFFER                               (*(VUINT8 *)(ADDR_PS2_3_TRANSMIT_BUFFER))
-
-#define ADDR_PS2_0_TRANSMIT_BUFFER                               0x40009000
-#define MMCR_PS2_0_TRANSMIT_BUFFER                               (*(VUINT8 *)(ADDR_PS2_0_TRANSMIT_BUFFER))
-
-#define ADDR_PS2_0_RECEIVE_BUFFER                                0x40009000
-#define MMCR_PS2_0_RECEIVE_BUFFER                                (*(VUINT8 *)(ADDR_PS2_0_RECEIVE_BUFFER))
-
-#define ADDR_PS2_0_CONTROL                                       0x40009004
-#define MMCR_PS2_0_CONTROL                                       (*(VUINT8 *)(ADDR_PS2_0_CONTROL))
-
-#define ADDR_PS2_0_STATUS                                        0x40009008
-#define MMCR_PS2_0_STATUS                                        (*(VUINT8 *)(ADDR_PS2_0_STATUS))
-
-#define ADDR_PS2_1_TRANSMIT_BUFFER                               0x40009040
-#define MMCR_PS2_1_TRANSMIT_BUFFER                               (*(VUINT8 *)(ADDR_PS2_1_TRANSMIT_BUFFER))
-
-#define ADDR_PS2_1_RECEIVE_BUFFER                                0x40009040
-#define MMCR_PS2_1_RECEIVE_BUFFER                                (*(VUINT8 *)(ADDR_PS2_1_RECEIVE_BUFFER))
-
-#define ADDR_PS2_1_CONTROL                                       0x40009044
-#define MMCR_PS2_1_CONTROL                                       (*(VUINT8 *)(ADDR_PS2_1_CONTROL))
-
-#define ADDR_PS2_1_STATUS                                        0x40009048
-#define MMCR_PS2_1_STATUS                                        (*(VUINT8 *)(ADDR_PS2_1_STATUS))
-
-#define ADDR_PS2_2_RECEIVE_BUFFER                                0x40009080
-#define MMCR_PS2_2_RECEIVE_BUFFER                                (*(VUINT8 *)(ADDR_PS2_2_RECEIVE_BUFFER))
-
-#define ADDR_PS2_2_TRANSMIT_BUFFER                               0x40009080
-#define MMCR_PS2_2_TRANSMIT_BUFFER                               (*(VUINT8 *)(ADDR_PS2_2_TRANSMIT_BUFFER))
-
-#define ADDR_PS2_2_CONTROL                                       0x40009084
-#define MMCR_PS2_2_CONTROL                                       (*(VUINT8 *)(ADDR_PS2_2_CONTROL))
-
-#define ADDR_PS2_2_STATUS                                        0x40009088
-#define MMCR_PS2_2_STATUS                                        (*(VUINT8 *)(ADDR_PS2_2_STATUS))
-
-/***************************************************************
-*                            8042 Host Interface
-***************************************************************/
-#define ADDR_8042_ACTIVATE                                       0x400F0730
-#define MMCR_8042_ACTIVATE                                       (*(VUINT8 *)(ADDR_8042_ACTIVATE))
-
-#define ADDR_8042_HOST_EC_DATACMD                                0x400F0500
-#define MMCR_8042_HOST_EC_DATACMD                                (*(VUINT8 *)(ADDR_8042_HOST_EC_DATACMD))
-
-#define ADDR_8042_EC_HOST_DATA                                   0x400F0500
-#define MMCR_8042_EC_HOST_DATA                                   (*(VUINT8 *)(ADDR_8042_EC_HOST_DATA))
-
-#define ADDR_8042_KEYBOARD_STATUS_READ                           0x400F0504
-#define MMCR_8042_KEYBOARD_STATUS_READ                           (*(VUINT8 *)(ADDR_8042_KEYBOARD_STATUS_READ))
-
-#define ADDR_8042_KEYBOARD_CONTROL                               0x400F0508
-#define MMCR_8042_KEYBOARD_CONTROL                               (*(VUINT8 *)(ADDR_8042_KEYBOARD_CONTROL))
-
-#define ADDR_8042_EC_HOST_AUX                                    0x400F050C
-#define MMCR_8042_EC_HOST_AUX                                    (*(VUINT8 *)(ADDR_8042_EC_HOST_AUX))
-
-#define ADDR_8042_PCOBF                                          0x400F0514
-#define MMCR_8042_PCOBF                                          (*(VUINT8 *)(ADDR_8042_PCOBF))
-
-#define ADDR_8042_PORT92_ENABLE                                  0x400F1B30
-#define MMCR_8042_PORT92_ENABLE                                  (*(VUINT8 *)(ADDR_8042_PORT92_ENABLE))
-
-#define ADDR_8042_GATEA20_CONTROL                                0x400F1900
-#define MMCR_8042_GATEA20_CONTROL                                (*(VUINT8 *)(ADDR_8042_GATEA20_CONTROL))
-
-#define ADDR_8042_SETGA20L                                       0x400F1908
-#define MMCR_8042_SETGA20L                                       (*(VUINT8 *)(ADDR_8042_SETGA20L))
-
-#define ADDR_8042_RSTGA20L                                       0x400F190C
-#define MMCR_8042_RSTGA20L                                       (*(VUINT8 *)(ADDR_8042_RSTGA20L))
-
-/***************************************************************
-*                            SMBus
-***************************************************************/
-#define ADDR_SMB_3_DEBUG_FSM_SMB                                 0x4000B45C
-#define MMCR_SMB_3_DEBUG_FSM_SMB                                 (*(VUINT32 *)(ADDR_SMB_3_DEBUG_FSM_SMB))
-
-#define ADDR_SMB_3_DEBUG_FSM_I2C                                 0x4000B458
-#define MMCR_SMB_3_DEBUG_FSM_I2C                                 (*(VUINT32 *)(ADDR_SMB_3_DEBUG_FSM_I2C))
-
-#define ADDR_SMBUS_3_MASTER_RECEIVE_BUFFER                       0x4000B454
-#define MMCR_SMBUS_3_MASTER_RECEIVE_BUFFER                       (*(VUINT8 *)(ADDR_SMBUS_3_MASTER_RECEIVE_BUFFER))
-
-#define ADDR_SMBUS_3_MASTER_TRANSMIT_BUFER                       0x4000B450
-#define MMCR_SMBUS_3_MASTER_TRANSMIT_BUFER                       (*(VUINT8 *)(ADDR_SMBUS_3_MASTER_TRANSMIT_BUFER))
-
-#define ADDR_SMBUS_3_SLAVE_RECEIVE_BUFFER                        0x4000B44C
-#define MMCR_SMBUS_3_SLAVE_RECEIVE_BUFFER                        (*(VUINT8 *)(ADDR_SMBUS_3_SLAVE_RECEIVE_BUFFER))
-
-#define ADDR_SMBUS_3_SLAVE_TRANSMIT_BUFFER                       0x4000B448
-#define MMCR_SMBUS_3_SLAVE_TRANSMIT_BUFFER                       (*(VUINT8 *)(ADDR_SMBUS_3_SLAVE_TRANSMIT_BUFFER))
-
-#define ADDR_SMB_3_TIME_OUT_SCALING                              0x4000B444
-#define MMCR_SMB_3_TIME_OUT_SCALING                              (*(VUINT32 *)(ADDR_SMB_3_TIME_OUT_SCALING))
-
-#define ADDR_SMB_3_DATA_TIMING                                   0x4000B440
-#define MMCR_SMB_3_DATA_TIMING                                   (*(VUINT32 *)(ADDR_SMB_3_DATA_TIMING))
-
-#define ADDR_SMB_3_CLOCK_SYNC                                    0x4000B43C
-#define MMCR_SMB_3_CLOCK_SYNC                                    (*(VUINT32 *)(ADDR_SMB_3_CLOCK_SYNC))
-
-#define ADDR_SMB_3_BIT_BANG_CONTROL                              0x4000B438
-#define MMCR_SMB_3_BIT_BANG_CONTROL                              (*(VUINT8 *)(ADDR_SMB_3_BIT_BANG_CONTROL))
-
-#define ADDR_SMB_3_REVISION                                      0x4000B434
-#define MMCR_SMB_3_REVISION                                      (*(VUINT8 *)(ADDR_SMB_3_REVISION))
-
-#define ADDR_SMB_3_BLOCK_ID                                      0x4000B430
-#define MMCR_SMB_3_BLOCK_ID                                      (*(VUINT8 *)(ADDR_SMB_3_BLOCK_ID))
-
-#define ADDR_SMB_3_BUS_CLOCK                                     0x4000B42C
-#define MMCR_SMB_3_BUS_CLOCK                                     (*(VUINT16 *)(ADDR_SMB_3_BUS_CLOCK))
-
-#define ADDR_SMB_3_CONFIGURATION                                 0x4000B428
-#define MMCR_SMB_3_CONFIGURATION                                 (*(VUINT32 *)(ADDR_SMB_3_CONFIGURATION))
-
-#define ADDR_SMB_3_IDLE_SCALING                                  0x4000B424
-#define MMCR_SMB_3_IDLE_SCALING                                  (*(VUINT32 *)(ADDR_SMB_3_IDLE_SCALING))
-
-#define ADDR_SMB_3_COMPLETION                                    0x4000B420
-#define MMCR_SMB_3_COMPLETION                                    (*(VUINT32 *)(ADDR_SMB_3_COMPLETION))
-
-#define ADDR_SMB_3_DATA_TIMING2                                  0x4000B418
-#define MMCR_SMB_3_DATA_TIMING2                                  (*(VUINT8 *)(ADDR_SMB_3_DATA_TIMING2))
-
-#define ADDR_SMB_3_PEC                                           0x4000B414
-#define MMCR_SMB_3_PEC                                           (*(VUINT8 *)(ADDR_SMB_3_PEC))
-
-#define ADDR_SMBUS_3_SLAVE_COMMAND                               0x4000B410
-#define MMCR_SMBUS_3_SLAVE_COMMAND                               (*(VUINT32 *)(ADDR_SMBUS_3_SLAVE_COMMAND))
-
-#define ADDR_SMBUS_3_MASTER_COMMAND                              0x4000B40C
-#define MMCR_SMBUS_3_MASTER_COMMAND                              (*(VUINT32 *)(ADDR_SMBUS_3_MASTER_COMMAND))
-
-#define ADDR_SMB_3_DATA                                          0x4000B408
-#define MMCR_SMB_3_DATA                                          (*(VUINT8 *)(ADDR_SMB_3_DATA))
-
-#define ADDR_SMB_3_OWN_ADDRESS                                   0x4000B404
-#define MMCR_SMB_3_OWN_ADDRESS                                   (*(VUINT16 *)(ADDR_SMB_3_OWN_ADDRESS))
-
-#define ADDR_SMB_3_STATUS                                        0x4000B400
-#define MMCR_SMB_3_STATUS                                        (*(VUINT8 *)(ADDR_SMB_3_STATUS))
-
-#define ADDR_SMB_3_CONTROL                                       0x4000B400
-#define MMCR_SMB_3_CONTROL                                       (*(VUINT8 *)(ADDR_SMB_3_CONTROL))
-
-#define ADDR_SMB_2_CONTROL                                       0x4000B000
-#define MMCR_SMB_2_CONTROL                                       (*(VUINT8 *)(ADDR_SMB_2_CONTROL))
-
-#define ADDR_SMB_2_STATUS                                        0x4000B000
-#define MMCR_SMB_2_STATUS                                        (*(VUINT8 *)(ADDR_SMB_2_STATUS))
-
-#define ADDR_SMB_2_OWN_ADDRESS                                   0x4000B004
-#define MMCR_SMB_2_OWN_ADDRESS                                   (*(VUINT16 *)(ADDR_SMB_2_OWN_ADDRESS))
-
-#define ADDR_SMB_2_DATA                                          0x4000B008
-#define MMCR_SMB_2_DATA                                          (*(VUINT8 *)(ADDR_SMB_2_DATA))
-
-#define ADDR_SMBUS_2_MASTER_COMMAND                              0x4000B00C
-#define MMCR_SMBUS_2_MASTER_COMMAND                              (*(VUINT32 *)(ADDR_SMBUS_2_MASTER_COMMAND))
-
-#define ADDR_SMBUS_2_SLAVE_COMMAND                               0x4000B010
-#define MMCR_SMBUS_2_SLAVE_COMMAND                               (*(VUINT32 *)(ADDR_SMBUS_2_SLAVE_COMMAND))
-
-#define ADDR_SMB_2_PEC                                           0x4000B014
-#define MMCR_SMB_2_PEC                                           (*(VUINT8 *)(ADDR_SMB_2_PEC))
-
-#define ADDR_SMB_2_DATA_TIMING2                                  0x4000B018
-#define MMCR_SMB_2_DATA_TIMING2                                  (*(VUINT8 *)(ADDR_SMB_2_DATA_TIMING2))
-
-#define ADDR_SMB_2_COMPLETION                                    0x4000B020
-#define MMCR_SMB_2_COMPLETION                                    (*(VUINT32 *)(ADDR_SMB_2_COMPLETION))
-
-#define ADDR_SMB_2_IDLE_SCALING                                  0x4000B024
-#define MMCR_SMB_2_IDLE_SCALING                                  (*(VUINT32 *)(ADDR_SMB_2_IDLE_SCALING))
-
-#define ADDR_SMB_2_CONFIGURATION                                 0x4000B028
-#define MMCR_SMB_2_CONFIGURATION                                 (*(VUINT32 *)(ADDR_SMB_2_CONFIGURATION))
-
-#define ADDR_SMB_2_BUS_CLOCK                                     0x4000B02C
-#define MMCR_SMB_2_BUS_CLOCK                                     (*(VUINT16 *)(ADDR_SMB_2_BUS_CLOCK))
-
-#define ADDR_SMB_2_BLOCK_ID                                      0x4000B030
-#define MMCR_SMB_2_BLOCK_ID                                      (*(VUINT8 *)(ADDR_SMB_2_BLOCK_ID))
-
-#define ADDR_SMB_2_REVISION                                      0x4000B034
-#define MMCR_SMB_2_REVISION                                      (*(VUINT8 *)(ADDR_SMB_2_REVISION))
-
-#define ADDR_SMB_2_BIT_BANG_CONTROL                              0x4000B038
-#define MMCR_SMB_2_BIT_BANG_CONTROL                              (*(VUINT8 *)(ADDR_SMB_2_BIT_BANG_CONTROL))
-
-#define ADDR_SMB_2_CLOCK_SYNC                                    0x4000B03C
-#define MMCR_SMB_2_CLOCK_SYNC                                    (*(VUINT32 *)(ADDR_SMB_2_CLOCK_SYNC))
-
-#define ADDR_SMB_2_DATA_TIMING                                   0x4000B040
-#define MMCR_SMB_2_DATA_TIMING                                   (*(VUINT32 *)(ADDR_SMB_2_DATA_TIMING))
-
-#define ADDR_SMB_2_TIME_OUT_SCALING                              0x4000B044
-#define MMCR_SMB_2_TIME_OUT_SCALING                              (*(VUINT32 *)(ADDR_SMB_2_TIME_OUT_SCALING))
-
-#define ADDR_SMBUS_2_SLAVE_TRANSMIT_BUFFER                       0x4000B048
-#define MMCR_SMBUS_2_SLAVE_TRANSMIT_BUFFER                       (*(VUINT8 *)(ADDR_SMBUS_2_SLAVE_TRANSMIT_BUFFER))
-
-#define ADDR_SMBUS_2_SLAVE_RECEIVE_BUFFER                        0x4000B04C
-#define MMCR_SMBUS_2_SLAVE_RECEIVE_BUFFER                        (*(VUINT8 *)(ADDR_SMBUS_2_SLAVE_RECEIVE_BUFFER))
-
-#define ADDR_SMBUS_2_MASTER_TRANSMIT_BUFER                       0x4000B050
-#define MMCR_SMBUS_2_MASTER_TRANSMIT_BUFER                       (*(VUINT8 *)(ADDR_SMBUS_2_MASTER_TRANSMIT_BUFER))
-
-#define ADDR_SMBUS_2_MASTER_RECEIVE_BUFFER                       0x4000B054
-#define MMCR_SMBUS_2_MASTER_RECEIVE_BUFFER                       (*(VUINT8 *)(ADDR_SMBUS_2_MASTER_RECEIVE_BUFFER))
-
-#define ADDR_SMB_2_DEBUG_FSM_I2C                                 0x4000B058
-#define MMCR_SMB_2_DEBUG_FSM_I2C                                 (*(VUINT32 *)(ADDR_SMB_2_DEBUG_FSM_I2C))
-
-#define ADDR_SMB_2_DEBUG_FSM_SMB                                 0x4000B05C
-#define MMCR_SMB_2_DEBUG_FSM_SMB                                 (*(VUINT32 *)(ADDR_SMB_2_DEBUG_FSM_SMB))
-
-#define ADDR_SMB_1_CONTROL                                       0x4000AC00
-#define MMCR_SMB_1_CONTROL                                       (*(VUINT8 *)(ADDR_SMB_1_CONTROL))
-
-#define ADDR_SMB_1_STATUS                                        0x4000AC00
-#define MMCR_SMB_1_STATUS                                        (*(VUINT8 *)(ADDR_SMB_1_STATUS))
-
-#define ADDR_SMB_1_OWN_ADDRESS                                   0x4000AC04
-#define MMCR_SMB_1_OWN_ADDRESS                                   (*(VUINT16 *)(ADDR_SMB_1_OWN_ADDRESS))
-
-#define ADDR_SMB_1_DATA                                          0x4000AC08
-#define MMCR_SMB_1_DATA                                          (*(VUINT8 *)(ADDR_SMB_1_DATA))
-
-#define ADDR_SMBUS_1_MASTER_COMMAND                              0x4000AC0C
-#define MMCR_SMBUS_1_MASTER_COMMAND                              (*(VUINT32 *)(ADDR_SMBUS_1_MASTER_COMMAND))
-
-#define ADDR_SMBUS_1_SLAVE_COMMAND                               0x4000AC10
-#define MMCR_SMBUS_1_SLAVE_COMMAND                               (*(VUINT32 *)(ADDR_SMBUS_1_SLAVE_COMMAND))
-
-#define ADDR_SMB_1_PEC                                           0x4000AC14
-#define MMCR_SMB_1_PEC                                           (*(VUINT8 *)(ADDR_SMB_1_PEC))
-
-#define ADDR_SMB_1_DATA_TIMING2                                  0x4000AC18
-#define MMCR_SMB_1_DATA_TIMING2                                  (*(VUINT8 *)(ADDR_SMB_1_DATA_TIMING2))
-
-#define ADDR_SMB_1_COMPLETION                                    0x4000AC20
-#define MMCR_SMB_1_COMPLETION                                    (*(VUINT32 *)(ADDR_SMB_1_COMPLETION))
-
-#define ADDR_SMB_1_IDLE_SCALING                                  0x4000AC24
-#define MMCR_SMB_1_IDLE_SCALING                                  (*(VUINT32 *)(ADDR_SMB_1_IDLE_SCALING))
-
-#define ADDR_SMB_1_CONFIGURATION                                 0x4000AC28
-#define MMCR_SMB_1_CONFIGURATION                                 (*(VUINT32 *)(ADDR_SMB_1_CONFIGURATION))
-
-#define ADDR_SMB_1_BUS_CLOCK                                     0x4000AC2C
-#define MMCR_SMB_1_BUS_CLOCK                                     (*(VUINT16 *)(ADDR_SMB_1_BUS_CLOCK))
-
-#define ADDR_SMB_1_BLOCK_ID                                      0x4000AC30
-#define MMCR_SMB_1_BLOCK_ID                                      (*(VUINT8 *)(ADDR_SMB_1_BLOCK_ID))
-
-#define ADDR_SMB_1_REVISION                                      0x4000AC34
-#define MMCR_SMB_1_REVISION                                      (*(VUINT8 *)(ADDR_SMB_1_REVISION))
-
-#define ADDR_SMB_1_BIT_BANG_CONTROL                              0x4000AC38
-#define MMCR_SMB_1_BIT_BANG_CONTROL                              (*(VUINT8 *)(ADDR_SMB_1_BIT_BANG_CONTROL))
-
-#define ADDR_SMB_1_CLOCK_SYNC                                    0x4000AC3C
-#define MMCR_SMB_1_CLOCK_SYNC                                    (*(VUINT32 *)(ADDR_SMB_1_CLOCK_SYNC))
-
-#define ADDR_SMB_1_DATA_TIMING                                   0x4000AC40
-#define MMCR_SMB_1_DATA_TIMING                                   (*(VUINT32 *)(ADDR_SMB_1_DATA_TIMING))
-
-#define ADDR_SMB_1_TIME_OUT_SCALING                              0x4000AC44
-#define MMCR_SMB_1_TIME_OUT_SCALING                              (*(VUINT32 *)(ADDR_SMB_1_TIME_OUT_SCALING))
-
-#define ADDR_SMBUS_1_SLAVE_TRANSMIT_BUFFER                       0x4000AC48
-#define MMCR_SMBUS_1_SLAVE_TRANSMIT_BUFFER                       (*(VUINT8 *)(ADDR_SMBUS_1_SLAVE_TRANSMIT_BUFFER))
-
-#define ADDR_SMBUS_1_SLAVE_RECEIVE_BUFFER                        0x4000AC4C
-#define MMCR_SMBUS_1_SLAVE_RECEIVE_BUFFER                        (*(VUINT8 *)(ADDR_SMBUS_1_SLAVE_RECEIVE_BUFFER))
-
-#define ADDR_SMBUS_1_MASTER_TRANSMIT_BUFER                       0x4000AC50
-#define MMCR_SMBUS_1_MASTER_TRANSMIT_BUFER                       (*(VUINT8 *)(ADDR_SMBUS_1_MASTER_TRANSMIT_BUFER))
-
-#define ADDR_SMBUS_1_MASTER_RECEIVE_BUFFER                       0x4000AC54
-#define MMCR_SMBUS_1_MASTER_RECEIVE_BUFFER                       (*(VUINT8 *)(ADDR_SMBUS_1_MASTER_RECEIVE_BUFFER))
-
-#define ADDR_SMB_1_DEBUG_FSM_I2C                                 0x4000AC58
-#define MMCR_SMB_1_DEBUG_FSM_I2C                                 (*(VUINT32 *)(ADDR_SMB_1_DEBUG_FSM_I2C))
-
-#define ADDR_SMB_1_DEBUG_FSM_SMB                                 0x4000AC5C
-#define MMCR_SMB_1_DEBUG_FSM_SMB                                 (*(VUINT32 *)(ADDR_SMB_1_DEBUG_FSM_SMB))
-
-#define ADDR_SMB_0_STATUS                                        0x40001800
-#define MMCR_SMB_0_STATUS                                        (*(VUINT8 *)(ADDR_SMB_0_STATUS))
-
-#define ADDR_SMB_0_CONTROL                                       0x40001800
-#define MMCR_SMB_0_CONTROL                                       (*(VUINT8 *)(ADDR_SMB_0_CONTROL))
-
-#define ADDR_SMB_0_OWN_ADDRESS                                   0x40001804
-#define MMCR_SMB_0_OWN_ADDRESS                                   (*(VUINT16 *)(ADDR_SMB_0_OWN_ADDRESS))
-
-#define ADDR_SMB_0_DATA                                          0x40001808
-#define MMCR_SMB_0_DATA                                          (*(VUINT8 *)(ADDR_SMB_0_DATA))
-
-#define ADDR_SMBUS_0_MASTER_COMMAND                              0x4000180C
-#define MMCR_SMBUS_0_MASTER_COMMAND                              (*(VUINT32 *)(ADDR_SMBUS_0_MASTER_COMMAND))
-
-#define ADDR_SMBUS_0_SLAVE_COMMAND                               0x40001810
-#define MMCR_SMBUS_0_SLAVE_COMMAND                               (*(VUINT32 *)(ADDR_SMBUS_0_SLAVE_COMMAND))
-
-#define ADDR_SMB_0_PEC                                           0x40001814
-#define MMCR_SMB_0_PEC                                           (*(VUINT8 *)(ADDR_SMB_0_PEC))
-
-#define ADDR_SMB_0_DATA_TIMING2                                  0x40001818
-#define MMCR_SMB_0_DATA_TIMING2                                  (*(VUINT8 *)(ADDR_SMB_0_DATA_TIMING2))
-
-#define ADDR_SMB_0_COMPLETION                                    0x40001820
-#define MMCR_SMB_0_COMPLETION                                    (*(VUINT32 *)(ADDR_SMB_0_COMPLETION))
-
-#define ADDR_SMB_0_IDLE_SCALING                                  0x40001824
-#define MMCR_SMB_0_IDLE_SCALING                                  (*(VUINT32 *)(ADDR_SMB_0_IDLE_SCALING))
-
-#define ADDR_SMB_0_CONFIGURATION                                 0x40001828
-#define MMCR_SMB_0_CONFIGURATION                                 (*(VUINT32 *)(ADDR_SMB_0_CONFIGURATION))
-
-#define ADDR_SMB_0_BUS_CLOCK                                     0x4000182C
-#define MMCR_SMB_0_BUS_CLOCK                                     (*(VUINT16 *)(ADDR_SMB_0_BUS_CLOCK))
-
-#define ADDR_SMB_0_BLOCK_ID                                      0x40001830
-#define MMCR_SMB_0_BLOCK_ID                                      (*(VUINT8 *)(ADDR_SMB_0_BLOCK_ID))
-
-#define ADDR_SMB_0_REVISION                                      0x40001834
-#define MMCR_SMB_0_REVISION                                      (*(VUINT8 *)(ADDR_SMB_0_REVISION))
-
-#define ADDR_SMB_0_BIT_BANG_CONTROL                              0x40001838
-#define MMCR_SMB_0_BIT_BANG_CONTROL                              (*(VUINT8 *)(ADDR_SMB_0_BIT_BANG_CONTROL))
-
-#define ADDR_SMB_0_CLOCK_SYNC                                    0x4000183C
-#define MMCR_SMB_0_CLOCK_SYNC                                    (*(VUINT32 *)(ADDR_SMB_0_CLOCK_SYNC))
-
-#define ADDR_SMB_0_DATA_TIMING                                   0x40001840
-#define MMCR_SMB_0_DATA_TIMING                                   (*(VUINT32 *)(ADDR_SMB_0_DATA_TIMING))
-
-#define ADDR_SMB_0_TIME_OUT_SCALING                              0x40001844
-#define MMCR_SMB_0_TIME_OUT_SCALING                              (*(VUINT32 *)(ADDR_SMB_0_TIME_OUT_SCALING))
-
-#define ADDR_SMBUS_0_SLAVE_TRANSMIT_BUFFER                       0x40001848
-#define MMCR_SMBUS_0_SLAVE_TRANSMIT_BUFFER                       (*(VUINT8 *)(ADDR_SMBUS_0_SLAVE_TRANSMIT_BUFFER))
-
-#define ADDR_SMBUS_0_SLAVE_RECEIVE_BUFFER                        0x4000184C
-#define MMCR_SMBUS_0_SLAVE_RECEIVE_BUFFER                        (*(VUINT8 *)(ADDR_SMBUS_0_SLAVE_RECEIVE_BUFFER))
-
-#define ADDR_SMBUS_0_MASTER_TRANSMIT_BUFER                       0x40001850
-#define MMCR_SMBUS_0_MASTER_TRANSMIT_BUFER                       (*(VUINT8 *)(ADDR_SMBUS_0_MASTER_TRANSMIT_BUFER))
-
-#define ADDR_SMBUS_0_MASTER_RECEIVE_BUFFER                       0x40001854
-#define MMCR_SMBUS_0_MASTER_RECEIVE_BUFFER                       (*(VUINT8 *)(ADDR_SMBUS_0_MASTER_RECEIVE_BUFFER))
-
-#define ADDR_SMB_0_DEBUG_FSM_I2C                                 0x40001858
-#define MMCR_SMB_0_DEBUG_FSM_I2C                                 (*(VUINT32 *)(ADDR_SMB_0_DEBUG_FSM_I2C))
-
-#define ADDR_SMB_0_DEBUG_FSM_SMB                                 0x4000185C
-#define MMCR_SMB_0_DEBUG_FSM_SMB                                 (*(VUINT32 *)(ADDR_SMB_0_DEBUG_FSM_SMB))
-
-/***************************************************************
-*                            Watchdog Timer Interface
-***************************************************************/
-#define ADDR_WATCHDOG_WDT_LOAD                                   0x40000400
-#define MMCR_WATCHDOG_WDT_LOAD                                   (*(VUINT16 *)(ADDR_WATCHDOG_WDT_LOAD))
-
-#define ADDR_WATCHDOG_WDT_CONTROL                                0x40000404
-#define MMCR_WATCHDOG_WDT_CONTROL                                (*(VUINT8 *)(ADDR_WATCHDOG_WDT_CONTROL))
-
-#define ADDR_WATCHDOG_WDT_KICK                                   0x40000408
-#define MMCR_WATCHDOG_WDT_KICK                                   (*(VUINT8 *)(ADDR_WATCHDOG_WDT_KICK))
-
-#define ADDR_WATCHDOG_WDT_COUNT                                  0x4000040C
-#define MMCR_WATCHDOG_WDT_COUNT                                  (*(VUINT16 *)(ADDR_WATCHDOG_WDT_COUNT))
-
-/***************************************************************
-*                            ACPI PM1
-***************************************************************/
-#define ADDR_ACPI_0_PM1_STATUS_1                                 0x400F1500
-#define MMCR_ACPI_0_PM1_STATUS_1                                 (*(VUINT8 *)(ADDR_ACPI_0_PM1_STATUS_1))
-
-#define ADDR_ACPI_0_PM1_STATUS_2                                 0x400F1501
-#define MMCR_ACPI_0_PM1_STATUS_2                                 (*(VUINT8 *)(ADDR_ACPI_0_PM1_STATUS_2))
-
-#define ADDR_ACPI_0_PM1_ENABLE_1                                 0x400F1502
-#define MMCR_ACPI_0_PM1_ENABLE_1                                 (*(VUINT8 *)(ADDR_ACPI_0_PM1_ENABLE_1))
-
-#define ADDR_ACPI_0_PM1_ENABLE_2                                 0x400F1503
-#define MMCR_ACPI_0_PM1_ENABLE_2                                 (*(VUINT8 *)(ADDR_ACPI_0_PM1_ENABLE_2))
-
-#define ADDR_ACPI_0_PM1_CONTROL_1                                0x400F1504
-#define MMCR_ACPI_0_PM1_CONTROL_1                                (*(VUINT8 *)(ADDR_ACPI_0_PM1_CONTROL_1))
-
-#define ADDR_ACPI_0_PM1_CONTROL_2                                0x400F1505
-#define MMCR_ACPI_0_PM1_CONTROL_2                                (*(VUINT8 *)(ADDR_ACPI_0_PM1_CONTROL_2))
-
-#define ADDR_ACPI_0_PM2_CONTROL_1                                0x400F1506
-#define MMCR_ACPI_0_PM2_CONTROL_1                                (*(VUINT8 *)(ADDR_ACPI_0_PM2_CONTROL_1))
-
-#define ADDR_ACPI_0_PM2_CONTROL_2                                0x400F1507
-#define MMCR_ACPI_0_PM2_CONTROL_2                                (*(VUINT8 *)(ADDR_ACPI_0_PM2_CONTROL_2))
-
-#define ADDR_ACPI_0_PM1_EC_PM_STATUS                             0x400F1510
-#define MMCR_ACPI_0_PM1_EC_PM_STATUS                             (*(VUINT8 *)(ADDR_ACPI_0_PM1_EC_PM_STATUS))
-
-/***************************************************************
-*                            EC GP-SPI
-***************************************************************/
-#define ADDR_EC_1_SPI_CLOCK_GENERATOR                            0x40009498
-#define MMCR_EC_1_SPI_CLOCK_GENERATOR                            (*(VUINT32 *)(ADDR_EC_1_SPI_CLOCK_GENERATOR))
-
-#define ADDR_EC_1_SPI_CLOCK_CONTROL                              0x40009494
-#define MMCR_EC_1_SPI_CLOCK_CONTROL                              (*(VUINT32 *)(ADDR_EC_1_SPI_CLOCK_CONTROL))
-
-#define ADDR_EC_1_SPI_RX_DATA                                    0x40009490
-#define MMCR_EC_1_SPI_RX_DATA                                    (*(VUINT32 *)(ADDR_EC_1_SPI_RX_DATA))
-
-#define ADDR_EC_1_SPI_TX_DATA                                    0x4000948C
-#define MMCR_EC_1_SPI_TX_DATA                                    (*(VUINT32 *)(ADDR_EC_1_SPI_TX_DATA))
-
-#define ADDR_EC_1_SPI_STATUS                                     0x40009488
-#define MMCR_EC_1_SPI_STATUS                                     (*(VUINT32 *)(ADDR_EC_1_SPI_STATUS))
-
-#define ADDR_EC_1_SPI_CONTROL                                    0x40009484
-#define MMCR_EC_1_SPI_CONTROL                                    (*(VUINT32 *)(ADDR_EC_1_SPI_CONTROL))
-
-#define ADDR_EC_1_SPI_ENABLE                                     0x40009480
-#define MMCR_EC_1_SPI_ENABLE                                     (*(VUINT32 *)(ADDR_EC_1_SPI_ENABLE))
-
-#define ADDR_EC_0_SPI_ENABLE                                     0x40009400
-#define MMCR_EC_0_SPI_ENABLE                                     (*(VUINT32 *)(ADDR_EC_0_SPI_ENABLE))
-
-#define ADDR_EC_0_SPI_CONTROL                                    0x40009404
-#define MMCR_EC_0_SPI_CONTROL                                    (*(VUINT32 *)(ADDR_EC_0_SPI_CONTROL))
-
-#define ADDR_EC_0_SPI_STATUS                                     0x40009408
-#define MMCR_EC_0_SPI_STATUS                                     (*(VUINT32 *)(ADDR_EC_0_SPI_STATUS))
-
-#define ADDR_EC_0_SPI_TX_DATA                                    0x4000940C
-#define MMCR_EC_0_SPI_TX_DATA                                    (*(VUINT32 *)(ADDR_EC_0_SPI_TX_DATA))
-
-#define ADDR_EC_0_SPI_RX_DATA                                    0x40009410
-#define MMCR_EC_0_SPI_RX_DATA                                    (*(VUINT32 *)(ADDR_EC_0_SPI_RX_DATA))
-
-#define ADDR_EC_0_SPI_CLOCK_CONTROL                              0x40009414
-#define MMCR_EC_0_SPI_CLOCK_CONTROL                              (*(VUINT32 *)(ADDR_EC_0_SPI_CLOCK_CONTROL))
-
-#define ADDR_EC_0_SPI_CLOCK_GENERATOR                            0x40009418
-#define MMCR_EC_0_SPI_CLOCK_GENERATOR                            (*(VUINT32 *)(ADDR_EC_0_SPI_CLOCK_GENERATOR))
-
-/***************************************************************
-*                            Mailbox Registers Interface
-***************************************************************/
-#define ADDR_MAILBOX_HOST_TO_EC_MAILBOX                          0x400F2500
-#define MMCR_MAILBOX_HOST_TO_EC_MAILBOX                          (*(VUINT32 *)(ADDR_MAILBOX_HOST_TO_EC_MAILBOX))
-
-#define ADDR_MAILBOX_EC_TO_HOST_MAILBOX                          0x400F2504
-#define MMCR_MAILBOX_EC_TO_HOST_MAILBOX                          (*(VUINT32 *)(ADDR_MAILBOX_EC_TO_HOST_MAILBOX))
-
-#define ADDR_MAILBOX_SMI_INTERRUPT_SOURCE                        0x400F2508
-#define MMCR_MAILBOX_SMI_INTERRUPT_SOURCE                        (*(VUINT32 *)(ADDR_MAILBOX_SMI_INTERRUPT_SOURCE))
-
-#define ADDR_MAILBOX_SMI_INTERRUPT_MASK                          0x400F250C
-#define MMCR_MAILBOX_SMI_INTERRUPT_MASK                          (*(VUINT32 *)(ADDR_MAILBOX_SMI_INTERRUPT_MASK))
-
-#define ADDR_MAILBOX_3_0                                         0x400F2510
-#define MMCR_MAILBOX_3_0                                         (*(VUINT32 *)(ADDR_MAILBOX_3_0))
-
-#define ADDR_MAILBOX_7_4                                         0x400F2514
-#define MMCR_MAILBOX_7_4                                         (*(VUINT32 *)(ADDR_MAILBOX_7_4))
-
-#define ADDR_MAILBOX_BH_8                                        0x400F2518
-#define MMCR_MAILBOX_BH_8                                        (*(VUINT32 *)(ADDR_MAILBOX_BH_8))
-
-#define ADDR_MAILBOX_FH_CH                                       0x400F251C
-#define MMCR_MAILBOX_FH_CH                                       (*(VUINT32 *)(ADDR_MAILBOX_FH_CH))
-
-#define ADDR_MAILBOX_13H_10H                                     0x400F2520
-#define MMCR_MAILBOX_13H_10H                                     (*(VUINT32 *)(ADDR_MAILBOX_13H_10H))
-
-#define ADDR_MAILBOX_17H_14H                                     0x400F2524
-#define MMCR_MAILBOX_17H_14H                                     (*(VUINT32 *)(ADDR_MAILBOX_17H_14H))
-
-#define ADDR_MAILBOX_1BH_18H                                     0x400F2528
-#define MMCR_MAILBOX_1BH_18H                                     (*(VUINT32 *)(ADDR_MAILBOX_1BH_18H))
-
-#define ADDR_MAILBOX_1FH_1CH                                     0x400F252C
-#define MMCR_MAILBOX_1FH_1CH                                     (*(VUINT32 *)(ADDR_MAILBOX_1FH_1CH))
-
-/***************************************************************
-*                            Hibernation Timer
-***************************************************************/
-#define ADDR_HIBERNATION_0_HTIMER_X_PRELOAD                      0x40009800
-#define MMCR_HIBERNATION_0_HTIMER_X_PRELOAD                      (*(VUINT16 *)(ADDR_HIBERNATION_0_HTIMER_X_PRELOAD))
-
-#define ADDR_HIBERNATION_0_TIMER_X_CONTROL                       0x40009804
-#define MMCR_HIBERNATION_0_TIMER_X_CONTROL                       (*(VUINT16 *)(ADDR_HIBERNATION_0_TIMER_X_CONTROL))
-
-#define ADDR_HIBERNATION_0_TIMER_X_COUNT                         0x40009808
-#define MMCR_HIBERNATION_0_TIMER_X_COUNT                         (*(VUINT16 *)(ADDR_HIBERNATION_0_TIMER_X_COUNT))
-
-/***************************************************************
-*                            UART
-***************************************************************/
-#define ADDR_M16C550A_UART_ACTIVATE                              0x400F1F30
-#define MMCR_M16C550A_UART_ACTIVATE                              (*(VUINT8 *)(ADDR_M16C550A_UART_ACTIVATE))
-
-#define ADDR_M16C550A_UART_CONFIG_SELECT                         0x400F1FF0
-#define MMCR_M16C550A_UART_CONFIG_SELECT                         (*(VUINT8 *)(ADDR_M16C550A_UART_CONFIG_SELECT))
-
-#define ADDR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_LSB  0x400F1D00
-#define MMCR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_LSB  (*(VUINT8 *)(ADDR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_LSB))
-
-#define ADDR_M16C550A_UART_RECEIVE_BUFFER                        0x400F1D00
-#define MMCR_M16C550A_UART_RECEIVE_BUFFER                        (*(VUINT8 *)(ADDR_M16C550A_UART_RECEIVE_BUFFER))
-
-#define ADDR_M16C550A_UART_TRANSMIT_BUFFER                       0x400F1D00
-#define MMCR_M16C550A_UART_TRANSMIT_BUFFER                       (*(VUINT8 *)(ADDR_M16C550A_UART_TRANSMIT_BUFFER))
-
-#define ADDR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_MSB  0x400F1D01
-#define MMCR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_MSB  (*(VUINT8 *)(ADDR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_MSB))
-
-#define ADDR_M16C550A_UART_INTERRUPT_ENABLE                      0x400F1D01
-#define MMCR_M16C550A_UART_INTERRUPT_ENABLE                      (*(VUINT8 *)(ADDR_M16C550A_UART_INTERRUPT_ENABLE))
-
-#define ADDR_M16C550A_UART_FIFO_CONTROL                          0x400F1D02
-#define MMCR_M16C550A_UART_FIFO_CONTROL                          (*(VUINT8 *)(ADDR_M16C550A_UART_FIFO_CONTROL))
-
-#define ADDR_M16C550A_UART_INTERRUPT_IDENTIFICATION              0x400F1D02
-#define MMCR_M16C550A_UART_INTERRUPT_IDENTIFICATION              (*(VUINT8 *)(ADDR_M16C550A_UART_INTERRUPT_IDENTIFICATION))
-
-#define ADDR_M16C550A_UART_LINE_CONTROL                          0x400F1D03
-#define MMCR_M16C550A_UART_LINE_CONTROL                          (*(VUINT8 *)(ADDR_M16C550A_UART_LINE_CONTROL))
-
-#define ADDR_M16C550A_UART_MODEM_CONTROL                         0x400F1D04
-#define MMCR_M16C550A_UART_MODEM_CONTROL                         (*(VUINT8 *)(ADDR_M16C550A_UART_MODEM_CONTROL))
-
-#define ADDR_M16C550A_UART_LINE_STATUS                           0x400F1D05
-#define MMCR_M16C550A_UART_LINE_STATUS                           (*(VUINT8 *)(ADDR_M16C550A_UART_LINE_STATUS))
-
-#define ADDR_M16C550A_UART_MODEM_STATUS                          0x400F1D06
-#define MMCR_M16C550A_UART_MODEM_STATUS                          (*(VUINT8 *)(ADDR_M16C550A_UART_MODEM_STATUS))
-
-#define ADDR_M16C550A_UART_SCRATCHPAD                            0x400F1D07
-#define MMCR_M16C550A_UART_SCRATCHPAD                            (*(VUINT8 *)(ADDR_M16C550A_UART_SCRATCHPAD))
-
-/***************************************************************
-*                            TACH
-***************************************************************/
-#define ADDR_TACH_0_CONTROL                                      0x40006000
-#define MMCR_TACH_0_CONTROL                                      (*(VUINT32 *)(ADDR_TACH_0_CONTROL))
-
-#define ADDR_TACH_0_STATUS                                       0x40006004
-#define MMCR_TACH_0_STATUS                                       (*(VUINT32 *)(ADDR_TACH_0_STATUS))
-
-#define ADDR_TACH_0_HIGH_LIMIT                                   0x40006008
-#define MMCR_TACH_0_HIGH_LIMIT                                   (*(VUINT32 *)(ADDR_TACH_0_HIGH_LIMIT))
-
-#define ADDR_TACH_0_LOW_LIMIT                                    0x4000600C
-#define MMCR_TACH_0_LOW_LIMIT                                    (*(VUINT32 *)(ADDR_TACH_0_LOW_LIMIT))
-
-#define ADDR_TACH_1_CONTROL                                      0x40006010
-#define MMCR_TACH_1_CONTROL                                      (*(VUINT32 *)(ADDR_TACH_1_CONTROL))
-
-#define ADDR_TACH_1_STATUS                                       0x40006014
-#define MMCR_TACH_1_STATUS                                       (*(VUINT32 *)(ADDR_TACH_1_STATUS))
-
-#define ADDR_TACH_1_HIGH_LIMIT                                   0x40006018
-#define MMCR_TACH_1_HIGH_LIMIT                                   (*(VUINT32 *)(ADDR_TACH_1_HIGH_LIMIT))
-
-#define ADDR_TACH_1_LOW_LIMIT                                    0x4000601C
-#define MMCR_TACH_1_LOW_LIMIT                                    (*(VUINT32 *)(ADDR_TACH_1_LOW_LIMIT))
-
-/***************************************************************
-*                            Global Config Regs Basic
-***************************************************************/
-#define ADDR_GLOBAL_LOGICAL_DEVICE_NUMBER                        0x400FFF07
-#define MMCR_GLOBAL_LOGICAL_DEVICE_NUMBER                        (*(VUINT8 *)(ADDR_GLOBAL_LOGICAL_DEVICE_NUMBER))
-
-#define ADDR_GLOBAL_DEVICE_ID                                    0x400FFF20
-#define MMCR_GLOBAL_DEVICE_ID                                    (*(VUINT8 *)(ADDR_GLOBAL_DEVICE_ID))
-
-#define ADDR_GLOBAL_DEVICE_REVISION_HARD_WIRED                   0x400FFF21
-#define MMCR_GLOBAL_DEVICE_REVISION_HARD_WIRED                   (*(VUINT8 *)(ADDR_GLOBAL_DEVICE_REVISION_HARD_WIRED))
-
-#define ADDR_GLOBAL_GCR_BUILD                                    0x400FFF28
-#define MMCR_GLOBAL_GCR_BUILD                                    (*(VUINT16 *)(ADDR_GLOBAL_GCR_BUILD))
-
-#define ADDR_GLOBAL_GCR_SCRATCH                                  0x400FFF2C
-#define MMCR_GLOBAL_GCR_SCRATCH                                  (*(VUINT32 *)(ADDR_GLOBAL_GCR_SCRATCH))
-
-/***************************************************************
-*                            Trace FIFO Debug Port
-***************************************************************/
-#define ADDR_TRACE_DATA                                          0x40008C00
-#define MMCR_TRACE_DATA                                          (*(VUINT32 *)(ADDR_TRACE_DATA))
-
-#define ADDR_TRACE_CONTROL                                       0x40008C04
-#define MMCR_TRACE_CONTROL                                       (*(VUINT32 *)(ADDR_TRACE_CONTROL))
-
-/***************************************************************
-*                            STAP
-***************************************************************/
-#define ADDR_STAP_MESSAGE_OBF                                    0x40080000
-#define MMCR_STAP_MESSAGE_OBF                                    (*(VUINT32 *)(ADDR_STAP_MESSAGE_OBF))
-
-#define ADDR_STAP_MESSAGE_IBF                                    0x40080004
-#define MMCR_STAP_MESSAGE_IBF                                    (*(VUINT32 *)(ADDR_STAP_MESSAGE_IBF))
-
-#define ADDR_STAP_OBF_STATUS                                     0x40080008
-#define MMCR_STAP_OBF_STATUS                                     (*(VUINT8 *)(ADDR_STAP_OBF_STATUS))
-
-#define ADDR_STAP_IBF_STATUS                                     0x40080009
-#define MMCR_STAP_IBF_STATUS                                     (*(VUINT8 *)(ADDR_STAP_IBF_STATUS))
-
-#define ADDR_STAP_DBG_CTRL                                       0x4008000C
-#define MMCR_STAP_DBG_CTRL                                       (*(VUINT8 *)(ADDR_STAP_DBG_CTRL))
-
-/***************************************************************
-*                            EMI
-***************************************************************/
-#define ADDR_IMAP_EMI_HOST_TO_EC_MAILBOX                         0x400F0100
-#define MMCR_IMAP_EMI_HOST_TO_EC_MAILBOX                         (*(VUINT8 *)(ADDR_IMAP_EMI_HOST_TO_EC_MAILBOX))
-
-#define ADDR_IMAP_EC_TO_HOST_MAILBOX                             0x400F0101
-#define MMCR_IMAP_EC_TO_HOST_MAILBOX                             (*(VUINT8 *)(ADDR_IMAP_EC_TO_HOST_MAILBOX))
-
-#define ADDR_IMAP_MEMORY_BASE_ADDRESS_0                          0x400F0104
-#define MMCR_IMAP_MEMORY_BASE_ADDRESS_0                          (*(VUINT32 *)(ADDR_IMAP_MEMORY_BASE_ADDRESS_0))
-
-#define ADDR_IMAP_MEMORY_READ_LIMIT_0                            0x400F0108
-#define MMCR_IMAP_MEMORY_READ_LIMIT_0                            (*(VUINT16 *)(ADDR_IMAP_MEMORY_READ_LIMIT_0))
-
-#define ADDR_IMAP_MEMORY_WRITE_LIMIT_0                           0x400F010A
-#define MMCR_IMAP_MEMORY_WRITE_LIMIT_0                           (*(VUINT16 *)(ADDR_IMAP_MEMORY_WRITE_LIMIT_0))
-
-#define ADDR_IMAP_MEMORY_BASE_ADDRESS_1                          0x400F010C
-#define MMCR_IMAP_MEMORY_BASE_ADDRESS_1                          (*(VUINT32 *)(ADDR_IMAP_MEMORY_BASE_ADDRESS_1))
-
-#define ADDR_IMAP_MEMORY_READ_LIMIT_1                            0x400F0110
-#define MMCR_IMAP_MEMORY_READ_LIMIT_1                            (*(VUINT16 *)(ADDR_IMAP_MEMORY_READ_LIMIT_1))
-
-#define ADDR_IMAP_MEMORY_WRITE_LIMIT_1                           0x400F0112
-#define MMCR_IMAP_MEMORY_WRITE_LIMIT_1                           (*(VUINT16 *)(ADDR_IMAP_MEMORY_WRITE_LIMIT_1))
-
-#define ADDR_IMAP_INTERRUPT_SET                                  0x400F0114
-#define MMCR_IMAP_INTERRUPT_SET                                  (*(VUINT16 *)(ADDR_IMAP_INTERRUPT_SET))
-
-#define ADDR_IMAP_HOST_CLEAR_ENABLE                              0x400F0116
-#define MMCR_IMAP_HOST_CLEAR_ENABLE                              (*(VUINT16 *)(ADDR_IMAP_HOST_CLEAR_ENABLE))
-
-/***************************************************************
-*                            Blinking/Breathing PWM
-***************************************************************/
-#define ADDR_LED_3_UPDATE_INTERVAL                               0x4000BB10
-#define MMCR_LED_3_UPDATE_INTERVAL                               (*(VUINT32 *)(ADDR_LED_3_UPDATE_INTERVAL))
-
-#define ADDR_LED_3_UPDATE_STEPSIZE                               0x4000BB0C
-#define MMCR_LED_3_UPDATE_STEPSIZE                               (*(VUINT32 *)(ADDR_LED_3_UPDATE_STEPSIZE))
-
-#define ADDR_LED_3_DELAY                                         0x4000BB08
-#define MMCR_LED_3_DELAY                                         (*(VUINT32 *)(ADDR_LED_3_DELAY))
-
-#define ADDR_LED_3_LIMITS                                        0x4000BB04
-#define MMCR_LED_3_LIMITS                                        (*(VUINT32 *)(ADDR_LED_3_LIMITS))
-
-#define ADDR_LED_3_CONFIGURATION                                 0x4000BB00
-#define MMCR_LED_3_CONFIGURATION                                 (*(VUINT32 *)(ADDR_LED_3_CONFIGURATION))
-
-#define ADDR_LED_2_UPDATE_INTERVAL                               0x4000BA10
-#define MMCR_LED_2_UPDATE_INTERVAL                               (*(VUINT32 *)(ADDR_LED_2_UPDATE_INTERVAL))
-
-#define ADDR_LED_2_UPDATE_STEPSIZE                               0x4000BA0C
-#define MMCR_LED_2_UPDATE_STEPSIZE                               (*(VUINT32 *)(ADDR_LED_2_UPDATE_STEPSIZE))
-
-#define ADDR_LED_2_DELAY                                         0x4000BA08
-#define MMCR_LED_2_DELAY                                         (*(VUINT32 *)(ADDR_LED_2_DELAY))
-
-#define ADDR_LED_2_LIMITS                                        0x4000BA04
-#define MMCR_LED_2_LIMITS                                        (*(VUINT32 *)(ADDR_LED_2_LIMITS))
-
-#define ADDR_LED_2_CONFIGURATION                                 0x4000BA00
-#define MMCR_LED_2_CONFIGURATION                                 (*(VUINT32 *)(ADDR_LED_2_CONFIGURATION))
-
-#define ADDR_LED_1_CONFIGURATION                                 0x4000B900
-#define MMCR_LED_1_CONFIGURATION                                 (*(VUINT32 *)(ADDR_LED_1_CONFIGURATION))
-
-#define ADDR_LED_1_LIMITS                                        0x4000B904
-#define MMCR_LED_1_LIMITS                                        (*(VUINT32 *)(ADDR_LED_1_LIMITS))
-
-#define ADDR_LED_1_DELAY                                         0x4000B908
-#define MMCR_LED_1_DELAY                                         (*(VUINT32 *)(ADDR_LED_1_DELAY))
-
-#define ADDR_LED_1_UPDATE_STEPSIZE                               0x4000B90C
-#define MMCR_LED_1_UPDATE_STEPSIZE                               (*(VUINT32 *)(ADDR_LED_1_UPDATE_STEPSIZE))
-
-#define ADDR_LED_1_UPDATE_INTERVAL                               0x4000B910
-#define MMCR_LED_1_UPDATE_INTERVAL                               (*(VUINT32 *)(ADDR_LED_1_UPDATE_INTERVAL))
-
-#define ADDR_LED_0_CONFIGURATION                                 0x4000B800
-#define MMCR_LED_0_CONFIGURATION                                 (*(VUINT32 *)(ADDR_LED_0_CONFIGURATION))
-
-#define ADDR_LED_0_LIMITS                                        0x4000B804
-#define MMCR_LED_0_LIMITS                                        (*(VUINT32 *)(ADDR_LED_0_LIMITS))
-
-#define ADDR_LED_0_DELAY                                         0x4000B808
-#define MMCR_LED_0_DELAY                                         (*(VUINT32 *)(ADDR_LED_0_DELAY))
-
-#define ADDR_LED_0_UPDATE_STEPSIZE                               0x4000B80C
-#define MMCR_LED_0_UPDATE_STEPSIZE                               (*(VUINT32 *)(ADDR_LED_0_UPDATE_STEPSIZE))
-
-#define ADDR_LED_0_UPDATE_INTERVAL                               0x4000B810
-#define MMCR_LED_0_UPDATE_INTERVAL                               (*(VUINT32 *)(ADDR_LED_0_UPDATE_INTERVAL))
-
-/***************************************************************
-*                            SMSC BC-Link Master
-***************************************************************/
-#define ADDR_BC_LINK_STATUS                                      0x4000BC00
-#define MMCR_BC_LINK_STATUS                                      (*(VUINT8 *)(ADDR_BC_LINK_STATUS))
-
-#define ADDR_BC_LINK_ADDRESS                                     0x4000BC04
-#define MMCR_BC_LINK_ADDRESS                                     (*(VUINT8 *)(ADDR_BC_LINK_ADDRESS))
-
-#define ADDR_BC_LINK_DATA                                        0x4000BC08
-#define MMCR_BC_LINK_DATA                                        (*(VUINT8 *)(ADDR_BC_LINK_DATA))
-
-#define ADDR_BC_LINK_CLOCK_SELECT                                0x4000BC0C
-#define MMCR_BC_LINK_CLOCK_SELECT                                (*(VUINT8 *)(ADDR_BC_LINK_CLOCK_SELECT))
-
-/***************************************************************
-*                            Basic Timer
-***************************************************************/
-#define ADDR_BASIC_0_TIMER_COUNT                                 0x40000C00
-#define MMCR_BASIC_0_TIMER_COUNT                                 (*(VUINT32 *)(ADDR_BASIC_0_TIMER_COUNT))
-
-#define ADDR_BASIC_0_TIMER_PRELOAD                               0x40000C04
-#define MMCR_BASIC_0_TIMER_PRELOAD                               (*(VUINT32 *)(ADDR_BASIC_0_TIMER_PRELOAD))
-
-#define ADDR_BASIC_0_TIMER_STATUS                                0x40000C08
-#define MMCR_BASIC_0_TIMER_STATUS                                (*(VUINT32 *)(ADDR_BASIC_0_TIMER_STATUS))
-
-#define ADDR_BASIC_0_TIMER_INTERRUPT_ENABLE                      0x40000C0C
-#define MMCR_BASIC_0_TIMER_INTERRUPT_ENABLE                      (*(VUINT32 *)(ADDR_BASIC_0_TIMER_INTERRUPT_ENABLE))
-
-#define ADDR_BASIC_0_TIMER_CONTROL                               0x40000C10
-#define MMCR_BASIC_0_TIMER_CONTROL                               (*(VUINT32 *)(ADDR_BASIC_0_TIMER_CONTROL))
-
-#define ADDR_BASIC_1_TIMER_COUNT                                 0x40000C20
-#define MMCR_BASIC_1_TIMER_COUNT                                 (*(VUINT32 *)(ADDR_BASIC_1_TIMER_COUNT))
-
-#define ADDR_BASIC_1_TIMER_PRELOAD                               0x40000C24
-#define MMCR_BASIC_1_TIMER_PRELOAD                               (*(VUINT32 *)(ADDR_BASIC_1_TIMER_PRELOAD))
-
-#define ADDR_BASIC_1_TIMER_STATUS                                0x40000C28
-#define MMCR_BASIC_1_TIMER_STATUS                                (*(VUINT32 *)(ADDR_BASIC_1_TIMER_STATUS))
-
-#define ADDR_BASIC_1_TIMER_INTERRUPT_ENABLE                      0x40000C2C
-#define MMCR_BASIC_1_TIMER_INTERRUPT_ENABLE                      (*(VUINT32 *)(ADDR_BASIC_1_TIMER_INTERRUPT_ENABLE))
-
-#define ADDR_BASIC_1_TIMER_CONTROL                               0x40000C30
-#define MMCR_BASIC_1_TIMER_CONTROL                               (*(VUINT32 *)(ADDR_BASIC_1_TIMER_CONTROL))
-
-#define ADDR_BASIC_2_TIMER_COUNT                                 0x40000C40
-#define MMCR_BASIC_2_TIMER_COUNT                                 (*(VUINT32 *)(ADDR_BASIC_2_TIMER_COUNT))
-
-#define ADDR_BASIC_2_TIMER_PRELOAD                               0x40000C44
-#define MMCR_BASIC_2_TIMER_PRELOAD                               (*(VUINT32 *)(ADDR_BASIC_2_TIMER_PRELOAD))
-
-#define ADDR_BASIC_2_TIMER_STATUS                                0x40000C48
-#define MMCR_BASIC_2_TIMER_STATUS                                (*(VUINT32 *)(ADDR_BASIC_2_TIMER_STATUS))
-
-#define ADDR_BASIC_2_TIMER_INTERRUPT_ENABLE                      0x40000C4C
-#define MMCR_BASIC_2_TIMER_INTERRUPT_ENABLE                      (*(VUINT32 *)(ADDR_BASIC_2_TIMER_INTERRUPT_ENABLE))
-
-#define ADDR_BASIC_2_TIMER_CONTROL                               0x40000C50
-#define MMCR_BASIC_2_TIMER_CONTROL                               (*(VUINT32 *)(ADDR_BASIC_2_TIMER_CONTROL))
-
-#define ADDR_BASIC_3_TIMER_COUNT                                 0x40000C60
-#define MMCR_BASIC_3_TIMER_COUNT                                 (*(VUINT32 *)(ADDR_BASIC_3_TIMER_COUNT))
-
-#define ADDR_BASIC_3_TIMER_PRELOAD                               0x40000C64
-#define MMCR_BASIC_3_TIMER_PRELOAD                               (*(VUINT32 *)(ADDR_BASIC_3_TIMER_PRELOAD))
-
-#define ADDR_BASIC_3_TIMER_STATUS                                0x40000C68
-#define MMCR_BASIC_3_TIMER_STATUS                                (*(VUINT32 *)(ADDR_BASIC_3_TIMER_STATUS))
-
-#define ADDR_BASIC_3_TIMER_INTERRUPT_ENABLE                      0x40000C6C
-#define MMCR_BASIC_3_TIMER_INTERRUPT_ENABLE                      (*(VUINT32 *)(ADDR_BASIC_3_TIMER_INTERRUPT_ENABLE))
-
-#define ADDR_BASIC_3_TIMER_CONTROL                               0x40000C70
-#define MMCR_BASIC_3_TIMER_CONTROL                               (*(VUINT32 *)(ADDR_BASIC_3_TIMER_CONTROL))
-
-#define ADDR_BASIC_4_TIMER_COUNT                                 0x40000C80
-#define MMCR_BASIC_4_TIMER_COUNT                                 (*(VUINT32 *)(ADDR_BASIC_4_TIMER_COUNT))
-
-#define ADDR_BASIC_4_TIMER_PRELOAD                               0x40000C84
-#define MMCR_BASIC_4_TIMER_PRELOAD                               (*(VUINT32 *)(ADDR_BASIC_4_TIMER_PRELOAD))
-
-#define ADDR_BASIC_4_TIMER_STATUS                                0x40000C88
-#define MMCR_BASIC_4_TIMER_STATUS                                (*(VUINT32 *)(ADDR_BASIC_4_TIMER_STATUS))
-
-#define ADDR_BASIC_4_TIMER_INTERRUPT_ENABLE                      0x40000C8C
-#define MMCR_BASIC_4_TIMER_INTERRUPT_ENABLE                      (*(VUINT32 *)(ADDR_BASIC_4_TIMER_INTERRUPT_ENABLE))
-
-#define ADDR_BASIC_4_TIMER_CONTROL                               0x40000C90
-#define MMCR_BASIC_4_TIMER_CONTROL                               (*(VUINT32 *)(ADDR_BASIC_4_TIMER_CONTROL))
-
-#define ADDR_BASIC_5_TIMER_COUNT                                 0x40000CA0
-#define MMCR_BASIC_5_TIMER_COUNT                                 (*(VUINT32 *)(ADDR_BASIC_5_TIMER_COUNT))
-
-#define ADDR_BASIC_5_TIMER_PRELOAD                               0x40000CA4
-#define MMCR_BASIC_5_TIMER_PRELOAD                               (*(VUINT32 *)(ADDR_BASIC_5_TIMER_PRELOAD))
-
-#define ADDR_BASIC_5_TIMER_STATUS                                0x40000CA8
-#define MMCR_BASIC_5_TIMER_STATUS                                (*(VUINT32 *)(ADDR_BASIC_5_TIMER_STATUS))
-
-#define ADDR_BASIC_5_TIMER_INTERRUPT_ENABLE                      0x40000CAC
-#define MMCR_BASIC_5_TIMER_INTERRUPT_ENABLE                      (*(VUINT32 *)(ADDR_BASIC_5_TIMER_INTERRUPT_ENABLE))
-
-#define ADDR_BASIC_5_TIMER_CONTROL                               0x40000CB0
-#define MMCR_BASIC_5_TIMER_CONTROL                               (*(VUINT32 *)(ADDR_BASIC_5_TIMER_CONTROL))
-
-/***************************************************************
-*                            INTS
-***************************************************************/
-#define ADDR_EC_GIRQ8_SOURCE                                     0x4000C000
-#define MMCR_EC_GIRQ8_SOURCE                                     (*(VUINT32 *)(ADDR_EC_GIRQ8_SOURCE))
-
-#define ADDR_EC_GIRQ8_ENABLE_SET                                 0x4000C004
-#define MMCR_EC_GIRQ8_ENABLE_SET                                 (*(VUINT32 *)(ADDR_EC_GIRQ8_ENABLE_SET))
-
-#define ADDR_EC_GIRQ8_RESULT                                     0x4000C008
-#define MMCR_EC_GIRQ8_RESULT                                     (*(VUINT32 *)(ADDR_EC_GIRQ8_RESULT))
-
-#define ADDR_EC_GIRQ8_ENABLE_CLEAR                               0x4000C00C
-#define MMCR_EC_GIRQ8_ENABLE_CLEAR                               (*(VUINT32 *)(ADDR_EC_GIRQ8_ENABLE_CLEAR))
-
-#define ADDR_EC_GIRQ9_SOURCE                                     0x4000C014
-#define MMCR_EC_GIRQ9_SOURCE                                     (*(VUINT32 *)(ADDR_EC_GIRQ9_SOURCE))
-
-#define ADDR_EC_GIRQ9_ENABLE_SET                                 0x4000C018
-#define MMCR_EC_GIRQ9_ENABLE_SET                                 (*(VUINT32 *)(ADDR_EC_GIRQ9_ENABLE_SET))
-
-#define ADDR_EC_GIRQ9_RESULT                                     0x4000C01C
-#define MMCR_EC_GIRQ9_RESULT                                     (*(VUINT32 *)(ADDR_EC_GIRQ9_RESULT))
-
-#define ADDR_EC_GIRQ9_ENABLE_CLEAR                               0x4000C020
-#define MMCR_EC_GIRQ9_ENABLE_CLEAR                               (*(VUINT32 *)(ADDR_EC_GIRQ9_ENABLE_CLEAR))
-
-#define ADDR_EC_GIRQ10_SOURCE                                    0x4000C028
-#define MMCR_EC_GIRQ10_SOURCE                                    (*(VUINT32 *)(ADDR_EC_GIRQ10_SOURCE))
-
-#define ADDR_EC_GIRQ10_ENABLE_SET                                0x4000C02C
-#define MMCR_EC_GIRQ10_ENABLE_SET                                (*(VUINT32 *)(ADDR_EC_GIRQ10_ENABLE_SET))
-
-#define ADDR_EC_GIRQ10_RESULT                                    0x4000C030
-#define MMCR_EC_GIRQ10_RESULT                                    (*(VUINT32 *)(ADDR_EC_GIRQ10_RESULT))
-
-#define ADDR_EC_GIRQ10_ENABLE_CLEAR                              0x4000C034
-#define MMCR_EC_GIRQ10_ENABLE_CLEAR                              (*(VUINT32 *)(ADDR_EC_GIRQ10_ENABLE_CLEAR))
-
-#define ADDR_EC_GIRQ11_SOURCE                                    0x4000C03C
-#define MMCR_EC_GIRQ11_SOURCE                                    (*(VUINT32 *)(ADDR_EC_GIRQ11_SOURCE))
-
-#define ADDR_EC_GIRQ11_ENABLE_SET                                0x4000C040
-#define MMCR_EC_GIRQ11_ENABLE_SET                                (*(VUINT32 *)(ADDR_EC_GIRQ11_ENABLE_SET))
-
-#define ADDR_EC_GIRQ11_RESULT                                    0x4000C044
-#define MMCR_EC_GIRQ11_RESULT                                    (*(VUINT32 *)(ADDR_EC_GIRQ11_RESULT))
-
-#define ADDR_EC_GIRQ11_ENABLE_CLEAR                              0x4000C048
-#define MMCR_EC_GIRQ11_ENABLE_CLEAR                              (*(VUINT32 *)(ADDR_EC_GIRQ11_ENABLE_CLEAR))
-
-#define ADDR_EC_GIRQ12_SOURCE                                    0x4000C050
-#define MMCR_EC_GIRQ12_SOURCE                                    (*(VUINT32 *)(ADDR_EC_GIRQ12_SOURCE))
-
-#define ADDR_EC_GIRQ12_ENABLE_SET                                0x4000C054
-#define MMCR_EC_GIRQ12_ENABLE_SET                                (*(VUINT32 *)(ADDR_EC_GIRQ12_ENABLE_SET))
-
-#define ADDR_EC_GIRQ12_RESULT                                    0x4000C058
-#define MMCR_EC_GIRQ12_RESULT                                    (*(VUINT32 *)(ADDR_EC_GIRQ12_RESULT))
-
-#define ADDR_EC_GIRQ12_ENABLE_CLEAR                              0x4000C05C
-#define MMCR_EC_GIRQ12_ENABLE_CLEAR                              (*(VUINT32 *)(ADDR_EC_GIRQ12_ENABLE_CLEAR))
-
-#define ADDR_EC_GIRQ13_SOURCE                                    0x4000C064
-#define MMCR_EC_GIRQ13_SOURCE                                    (*(VUINT32 *)(ADDR_EC_GIRQ13_SOURCE))
-
-#define ADDR_EC_GIRQ13_ENABLE_SET                                0x4000C068
-#define MMCR_EC_GIRQ13_ENABLE_SET                                (*(VUINT32 *)(ADDR_EC_GIRQ13_ENABLE_SET))
-
-#define ADDR_EC_GIRQ13_RESULT                                    0x4000C06C
-#define MMCR_EC_GIRQ13_RESULT                                    (*(VUINT32 *)(ADDR_EC_GIRQ13_RESULT))
-
-#define ADDR_EC_GIRQ13_ENABLE_CLEAR                              0x4000C070
-#define MMCR_EC_GIRQ13_ENABLE_CLEAR                              (*(VUINT32 *)(ADDR_EC_GIRQ13_ENABLE_CLEAR))
-
-#define ADDR_EC_GIRQ14_SOURCE                                    0x4000C078
-#define MMCR_EC_GIRQ14_SOURCE                                    (*(VUINT32 *)(ADDR_EC_GIRQ14_SOURCE))
-
-#define ADDR_EC_GIRQ14_ENABLE_SET                                0x4000C07C
-#define MMCR_EC_GIRQ14_ENABLE_SET                                (*(VUINT32 *)(ADDR_EC_GIRQ14_ENABLE_SET))
-
-#define ADDR_EC_GIRQ14_RESULT                                    0x4000C080
-#define MMCR_EC_GIRQ14_RESULT                                    (*(VUINT32 *)(ADDR_EC_GIRQ14_RESULT))
-
-#define ADDR_EC_GIRQ14_ENABLE_CLEAR                              0x4000C084
-#define MMCR_EC_GIRQ14_ENABLE_CLEAR                              (*(VUINT32 *)(ADDR_EC_GIRQ14_ENABLE_CLEAR))
-
-#define ADDR_EC_GIRQ15_SOURCE                                    0x4000C08C
-#define MMCR_EC_GIRQ15_SOURCE                                    (*(VUINT32 *)(ADDR_EC_GIRQ15_SOURCE))
-
-#define ADDR_EC_GIRQ15_ENABLE_SET                                0x4000C090
-#define MMCR_EC_GIRQ15_ENABLE_SET                                (*(VUINT32 *)(ADDR_EC_GIRQ15_ENABLE_SET))
-
-#define ADDR_EC_GIRQ15_RESULT                                    0x4000C094
-#define MMCR_EC_GIRQ15_RESULT                                    (*(VUINT32 *)(ADDR_EC_GIRQ15_RESULT))
-
-#define ADDR_EC_GIRQ15_ENABLE_CLEAR                              0x4000C098
-#define MMCR_EC_GIRQ15_ENABLE_CLEAR                              (*(VUINT32 *)(ADDR_EC_GIRQ15_ENABLE_CLEAR))
-
-#define ADDR_EC_GIRQ16_SOURCE                                    0x4000C0A0
-#define MMCR_EC_GIRQ16_SOURCE                                    (*(VUINT32 *)(ADDR_EC_GIRQ16_SOURCE))
-
-#define ADDR_EC_GIRQ16_ENABLE_SET                                0x4000C0A4
-#define MMCR_EC_GIRQ16_ENABLE_SET                                (*(VUINT32 *)(ADDR_EC_GIRQ16_ENABLE_SET))
-
-#define ADDR_EC_GIRQ16_RESULT                                    0x4000C0A8
-#define MMCR_EC_GIRQ16_RESULT                                    (*(VUINT32 *)(ADDR_EC_GIRQ16_RESULT))
-
-#define ADDR_EC_GIRQ16_ENABLE_CLEAR                              0x4000C0AC
-#define MMCR_EC_GIRQ16_ENABLE_CLEAR                              (*(VUINT32 *)(ADDR_EC_GIRQ16_ENABLE_CLEAR))
-
-#define ADDR_EC_GIRQ17_SOURCE                                    0x4000C0B4
-#define MMCR_EC_GIRQ17_SOURCE                                    (*(VUINT32 *)(ADDR_EC_GIRQ17_SOURCE))
-
-#define ADDR_EC_GIRQ17_ENABLE_SET                                0x4000C0B8
-#define MMCR_EC_GIRQ17_ENABLE_SET                                (*(VUINT32 *)(ADDR_EC_GIRQ17_ENABLE_SET))
-
-#define ADDR_EC_GIRQ17_RESULT                                    0x4000C0BC
-#define MMCR_EC_GIRQ17_RESULT                                    (*(VUINT32 *)(ADDR_EC_GIRQ17_RESULT))
-
-#define ADDR_EC_GIRQ17_ENABLE_CLEAR                              0x4000C0C0
-#define MMCR_EC_GIRQ17_ENABLE_CLEAR                              (*(VUINT32 *)(ADDR_EC_GIRQ17_ENABLE_CLEAR))
-
-#define ADDR_EC_GIRQ18_SOURCE                                    0x4000C0C8
-#define MMCR_EC_GIRQ18_SOURCE                                    (*(VUINT32 *)(ADDR_EC_GIRQ18_SOURCE))
-
-#define ADDR_EC_GIRQ18_ENABLE_SET                                0x4000C0CC
-#define MMCR_EC_GIRQ18_ENABLE_SET                                (*(VUINT32 *)(ADDR_EC_GIRQ18_ENABLE_SET))
-
-#define ADDR_EC_GIRQ18_RESULT                                    0x4000C0D0
-#define MMCR_EC_GIRQ18_RESULT                                    (*(VUINT32 *)(ADDR_EC_GIRQ18_RESULT))
-
-#define ADDR_EC_GIRQ18_ENABLE_CLEAR                              0x4000C0D4
-#define MMCR_EC_GIRQ18_ENABLE_CLEAR                              (*(VUINT32 *)(ADDR_EC_GIRQ18_ENABLE_CLEAR))
-
-#define ADDR_EC_GIRQ19_SOURCE                                    0x4000C0DC
-#define MMCR_EC_GIRQ19_SOURCE                                    (*(VUINT32 *)(ADDR_EC_GIRQ19_SOURCE))
-
-#define ADDR_EC_GIRQ19_ENABLE_SET                                0x4000C0E0
-#define MMCR_EC_GIRQ19_ENABLE_SET                                (*(VUINT32 *)(ADDR_EC_GIRQ19_ENABLE_SET))
-
-#define ADDR_EC_GIRQ19_RESULT                                    0x4000C0E4
-#define MMCR_EC_GIRQ19_RESULT                                    (*(VUINT32 *)(ADDR_EC_GIRQ19_RESULT))
-
-#define ADDR_EC_GIRQ19_ENABLE_CLEAR                              0x4000C0E8
-#define MMCR_EC_GIRQ19_ENABLE_CLEAR                              (*(VUINT32 *)(ADDR_EC_GIRQ19_ENABLE_CLEAR))
-
-#define ADDR_EC_GIRQ20_SOURCE                                    0x4000C0F0
-#define MMCR_EC_GIRQ20_SOURCE                                    (*(VUINT32 *)(ADDR_EC_GIRQ20_SOURCE))
-
-#define ADDR_EC_GIRQ20_ENABLE_SET                                0x4000C0F4
-#define MMCR_EC_GIRQ20_ENABLE_SET                                (*(VUINT32 *)(ADDR_EC_GIRQ20_ENABLE_SET))
-
-#define ADDR_EC_GIRQ20_RESULT                                    0x4000C0F8
-#define MMCR_EC_GIRQ20_RESULT                                    (*(VUINT32 *)(ADDR_EC_GIRQ20_RESULT))
-
-#define ADDR_EC_GIRQ20_ENABLE_CLEAR                              0x4000C0FC
-#define MMCR_EC_GIRQ20_ENABLE_CLEAR                              (*(VUINT32 *)(ADDR_EC_GIRQ20_ENABLE_CLEAR))
-
-#define ADDR_EC_GIRQ21_SOURCE                                    0x4000C104
-#define MMCR_EC_GIRQ21_SOURCE                                    (*(VUINT32 *)(ADDR_EC_GIRQ21_SOURCE))
-
-#define ADDR_EC_GIRQ21_ENABLE_SET                                0x4000C108
-#define MMCR_EC_GIRQ21_ENABLE_SET                                (*(VUINT32 *)(ADDR_EC_GIRQ21_ENABLE_SET))
-
-#define ADDR_EC_GIRQ21_RESULT                                    0x4000C10C
-#define MMCR_EC_GIRQ21_RESULT                                    (*(VUINT32 *)(ADDR_EC_GIRQ21_RESULT))
-
-#define ADDR_EC_GIRQ21_ENABLE_CLEAR                              0x4000C110
-#define MMCR_EC_GIRQ21_ENABLE_CLEAR                              (*(VUINT32 *)(ADDR_EC_GIRQ21_ENABLE_CLEAR))
-
-#define ADDR_EC_GIRQ22_SOURCE                                    0x4000C118
-#define MMCR_EC_GIRQ22_SOURCE                                    (*(VUINT32 *)(ADDR_EC_GIRQ22_SOURCE))
-
-#define ADDR_EC_GIRQ22_ENABLE_SET                                0x4000C11C
-#define MMCR_EC_GIRQ22_ENABLE_SET                                (*(VUINT32 *)(ADDR_EC_GIRQ22_ENABLE_SET))
-
-#define ADDR_EC_GIRQ22_RESULT                                    0x4000C120
-#define MMCR_EC_GIRQ22_RESULT                                    (*(VUINT32 *)(ADDR_EC_GIRQ22_RESULT))
-
-#define ADDR_EC_GIRQ22_ENABLE_CLEAR                              0x4000C124
-#define MMCR_EC_GIRQ22_ENABLE_CLEAR                              (*(VUINT32 *)(ADDR_EC_GIRQ22_ENABLE_CLEAR))
-
-#define ADDR_EC_GIRQ23_SOURCE                                    0x4000C12C
-#define MMCR_EC_GIRQ23_SOURCE                                    (*(VUINT32 *)(ADDR_EC_GIRQ23_SOURCE))
-
-#define ADDR_EC_GIRQ23_ENABLE_SET                                0x4000C130
-#define MMCR_EC_GIRQ23_ENABLE_SET                                (*(VUINT32 *)(ADDR_EC_GIRQ23_ENABLE_SET))
-
-#define ADDR_EC_GIRQ23_RESULT                                    0x4000C134
-#define MMCR_EC_GIRQ23_RESULT                                    (*(VUINT32 *)(ADDR_EC_GIRQ23_RESULT))
-
-#define ADDR_EC_GIRQ23_ENABLE_CLEAR                              0x4000C138
-#define MMCR_EC_GIRQ23_ENABLE_CLEAR                              (*(VUINT32 *)(ADDR_EC_GIRQ23_ENABLE_CLEAR))
-
-#define ADDR_EC_BLOCK_ENABLE_SET                                 0x4000C200
-#define MMCR_EC_BLOCK_ENABLE_SET                                 (*(VUINT32 *)(ADDR_EC_BLOCK_ENABLE_SET))
-
-#define ADDR_EC_BLOCK_ENABLE_CLEAR                               0x4000C204
-#define MMCR_EC_BLOCK_ENABLE_CLEAR                               (*(VUINT32 *)(ADDR_EC_BLOCK_ENABLE_CLEAR))
-
-#define ADDR_EC_BLOCK_IRQ_VECTOR                                 0x4000C208
-#define MMCR_EC_BLOCK_IRQ_VECTOR                                 (*(VUINT32 *)(ADDR_EC_BLOCK_IRQ_VECTOR))
-
-/***************************************************************
-*                            RPM Fan Control
-***************************************************************/
-#define ADDR_RPM_FAN_SETTING                                     0x4000A000
-#define MMCR_RPM_FAN_SETTING                                     (*(VUINT8 *)(ADDR_RPM_FAN_SETTING))
-
-#define ADDR_RPM_PWM_DIVIDE                                      0x4000A001
-#define MMCR_RPM_PWM_DIVIDE                                      (*(VUINT8 *)(ADDR_RPM_PWM_DIVIDE))
-
-#define ADDR_RPM_FAN_CONFIGURATION_1                             0x4000A002
-#define MMCR_RPM_FAN_CONFIGURATION_1                             (*(VUINT8 *)(ADDR_RPM_FAN_CONFIGURATION_1))
-
-#define ADDR_RPM_FAN_CONFIGURATION_2                             0x4000A003
-#define MMCR_RPM_FAN_CONFIGURATION_2                             (*(VUINT8 *)(ADDR_RPM_FAN_CONFIGURATION_2))
-
-#define ADDR_RPM_GAIN                                            0x4000A005
-#define MMCR_RPM_GAIN                                            (*(VUINT8 *)(ADDR_RPM_GAIN))
-
-#define ADDR_RPM_FAN_SPIN_UP_CONFIGURATION                       0x4000A006
-#define MMCR_RPM_FAN_SPIN_UP_CONFIGURATION                       (*(VUINT8 *)(ADDR_RPM_FAN_SPIN_UP_CONFIGURATION))
-
-#define ADDR_RPM_FAN_STEP                                        0x4000A007
-#define MMCR_RPM_FAN_STEP                                        (*(VUINT8 *)(ADDR_RPM_FAN_STEP))
-
-#define ADDR_RPM_FAN_MINIMUM_DRIVE                               0x4000A008
-#define MMCR_RPM_FAN_MINIMUM_DRIVE                               (*(VUINT8 *)(ADDR_RPM_FAN_MINIMUM_DRIVE))
-
-#define ADDR_RPM_VALID_TACH_COUNT                                0x4000A009
-#define MMCR_RPM_VALID_TACH_COUNT                                (*(VUINT8 *)(ADDR_RPM_VALID_TACH_COUNT))
-
-#define ADDR_RPM_FAN_DRIVE_FAIL_BAND_LOW_BYTE                    0x4000A00A
-#define MMCR_RPM_FAN_DRIVE_FAIL_BAND_LOW_BYTE                    (*(VUINT8 *)(ADDR_RPM_FAN_DRIVE_FAIL_BAND_LOW_BYTE))
-
-#define ADDR_RPM_FAN_DRIVE_FAIL_BAND_HIGH_BYTE                   0x4000A00B
-#define MMCR_RPM_FAN_DRIVE_FAIL_BAND_HIGH_BYTE                   (*(VUINT8 *)(ADDR_RPM_FAN_DRIVE_FAIL_BAND_HIGH_BYTE))
-
-#define ADDR_RPM_TACH_TARGET_LOW_BYTE                            0x4000A00C
-#define MMCR_RPM_TACH_TARGET_LOW_BYTE                            (*(VUINT8 *)(ADDR_RPM_TACH_TARGET_LOW_BYTE))
-
-#define ADDR_RPM_TACH_TARGET_HIGH_BYTE                           0x4000A00D
-#define MMCR_RPM_TACH_TARGET_HIGH_BYTE                           (*(VUINT8 *)(ADDR_RPM_TACH_TARGET_HIGH_BYTE))
-
-#define ADDR_RPM_TACH_READING_LOW_BYTE                           0x4000A00E
-#define MMCR_RPM_TACH_READING_LOW_BYTE                           (*(VUINT8 *)(ADDR_RPM_TACH_READING_LOW_BYTE))
-
-#define ADDR_RPM_TACH_READING_HIGH_BYTE                          0x4000A00F
-#define MMCR_RPM_TACH_READING_HIGH_BYTE                          (*(VUINT8 *)(ADDR_RPM_TACH_READING_HIGH_BYTE))
-
-#define ADDR_RPM_PWM_DRIVER_BASE_FREQUENCY                       0x4000A010
-#define MMCR_RPM_PWM_DRIVER_BASE_FREQUENCY                       (*(VUINT8 *)(ADDR_RPM_PWM_DRIVER_BASE_FREQUENCY))
-
-#define ADDR_RPM_FAN_STATUS                                      0x4000A011
-#define MMCR_RPM_FAN_STATUS                                      (*(VUINT8 *)(ADDR_RPM_FAN_STATUS))
-
-#define ADDR_RPM_FAN_TEST                                        0x4000A014
-#define MMCR_RPM_FAN_TEST                                        (*(VUINT8 *)(ADDR_RPM_FAN_TEST))
-
-#define ADDR_RPM_FAN_TEST1                                       0x4000A015
-#define MMCR_RPM_FAN_TEST1                                       (*(VUINT8 *)(ADDR_RPM_FAN_TEST1))
-
-#define ADDR_RPM_FAN_TEST2                                       0x4000A016
-#define MMCR_RPM_FAN_TEST2                                       (*(VUINT8 *)(ADDR_RPM_FAN_TEST2))
-
-#define ADDR_RPM_FAN_TEST3                                       0x4000A017
-#define MMCR_RPM_FAN_TEST3                                       (*(VUINT8 *)(ADDR_RPM_FAN_TEST3))
-
-/***************************************************************
-*                            V2P (HP ckt#1) 32bit_aligned
-***************************************************************/
-#define ADDR_V2P_ADC2PWM_OUTPUT_FREQUENCY                        0x40007C80
-#define MMCR_V2P_ADC2PWM_OUTPUT_FREQUENCY                        (*(VUINT32 *)(ADDR_V2P_ADC2PWM_OUTPUT_FREQUENCY))
-
-#define ADDR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_LOW                   0x40007C84
-#define MMCR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_LOW                   (*(VUINT32 *)(ADDR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_LOW))
-
-#define ADDR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_HIGH                  0x40007C88
-#define MMCR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_HIGH                  (*(VUINT32 *)(ADDR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_HIGH))
-
-#define ADDR_V2P_ADC2PWM_DUTY_CYCLE_QUANTA                       0x40007C8C
-#define MMCR_V2P_ADC2PWM_DUTY_CYCLE_QUANTA                       (*(VUINT32 *)(ADDR_V2P_ADC2PWM_DUTY_CYCLE_QUANTA))
-
-#define ADDR_V2P_ADC2PWM_DUTY_CYCLE_STATUS                       0x40007C90
-#define MMCR_V2P_ADC2PWM_DUTY_CYCLE_STATUS                       (*(VUINT32 *)(ADDR_V2P_ADC2PWM_DUTY_CYCLE_STATUS))
-
-#define ADDR_V2P_ADC2PWM_NOTIFICATION_LIMIT_1                    0x40007C94
-#define MMCR_V2P_ADC2PWM_NOTIFICATION_LIMIT_1                    (*(VUINT32 *)(ADDR_V2P_ADC2PWM_NOTIFICATION_LIMIT_1))
-
-#define ADDR_V2P_ADC2PWM_NOTIFICATION_LIMIT_2                    0x40007C98
-#define MMCR_V2P_ADC2PWM_NOTIFICATION_LIMIT_2                    (*(VUINT32 *)(ADDR_V2P_ADC2PWM_NOTIFICATION_LIMIT_2))
-
-#define ADDR_V2P_ADC2PWM_CONTROL                                 0x40007C9C
-#define MMCR_V2P_ADC2PWM_CONTROL                                 (*(VUINT32 *)(ADDR_V2P_ADC2PWM_CONTROL))
-
-#define ADDR_V2P_LPF_CUT_OFF_FREQUENCY                           0x40007CA0
-#define MMCR_V2P_LPF_CUT_OFF_FREQUENCY                           (*(VUINT32 *)(ADDR_V2P_LPF_CUT_OFF_FREQUENCY))
-
-#define ADDR_V2P_TEST                                            0x40007CA4
-#define MMCR_V2P_TEST                                            (*(VUINT32 *)(ADDR_V2P_TEST))
-
-#define ADDR_V2P_NOTICE_DATA                                     0x40007CA8
-#define MMCR_V2P_NOTICE_DATA                                     (*(VUINT32 *)(ADDR_V2P_NOTICE_DATA))
-
-#define ADDR_V2P_TEST_DATA                                       0x40007CAC
-#define MMCR_V2P_TEST_DATA                                       (*(VUINT32 *)(ADDR_V2P_TEST_DATA))
-
-#define ADDR_V2P_COUNTER_START                                   0x40007CB0
-#define MMCR_V2P_COUNTER_START                                   (*(VUINT32 *)(ADDR_V2P_COUNTER_START))
-
-#define ADDR_V2P_HYSTERESIS                                      0x40007CB4
-#define MMCR_V2P_HYSTERESIS                                      (*(VUINT32 *)(ADDR_V2P_HYSTERESIS))
-
-#define ADDR_V2P_BIAS                                            0x40007CB8
-#define MMCR_V2P_BIAS                                            (*(VUINT32 *)(ADDR_V2P_BIAS))
-
-#define ADDR_V2P_INTERRUPT_CONTROL                               0x40007CBC
-#define MMCR_V2P_INTERRUPT_CONTROL                               (*(VUINT32 *)(ADDR_V2P_INTERRUPT_CONTROL))
-
-/***************************************************************
-*                            VBAT_REGS (1322)
-***************************************************************/
-#define ADDR_VBAT_POWER_FAIL_AND_RESET_STATUS                    0x4000A400
-#define MMCR_VBAT_POWER_FAIL_AND_RESET_STATUS                    (*(VUINT8 *)(ADDR_VBAT_POWER_FAIL_AND_RESET_STATUS))
-
-#define ADDR_VBAT_CONTROL                                        0x4000A404
-#define MMCR_VBAT_CONTROL                                        (*(VUINT8 *)(ADDR_VBAT_CONTROL))
-
-#define ADDR_VBAT_CLOCK_ENABLE                                   0x4000A408
-#define MMCR_VBAT_CLOCK_ENABLE                                   (*(VUINT8 *)(ADDR_VBAT_CLOCK_ENABLE))
-
-/***************************************************************
-*                            EC_REG_BANK (1322)
-***************************************************************/
-#define ADDR_EC_REG_BANK_AHB_ERROR_ADDRESS                       0x4000FC04
-#define MMCR_EC_REG_BANK_AHB_ERROR_ADDRESS                       (*(VUINT32 *)(ADDR_EC_REG_BANK_AHB_ERROR_ADDRESS))
-
-#define ADDR_EC_REG_BANK_INPUT_MUX0                              0x4000FC08
-#define MMCR_EC_REG_BANK_INPUT_MUX0                              (*(VUINT32 *)(ADDR_EC_REG_BANK_INPUT_MUX0))
-
-#define ADDR_EC_REG_BANK_INPUT_MUX1                              0x4000FC0C
-#define MMCR_EC_REG_BANK_INPUT_MUX1                              (*(VUINT32 *)(ADDR_EC_REG_BANK_INPUT_MUX1))
-
-#define ADDR_EC_REG_BANK_ID                                      0x4000FC10
-#define MMCR_EC_REG_BANK_ID                                      (*(VUINT8 *)(ADDR_EC_REG_BANK_ID))
-
-#define ADDR_EC_REG_BANK_AHB_ERROR_CONTROL                       0x4000FC14
-#define MMCR_EC_REG_BANK_AHB_ERROR_CONTROL                       (*(VUINT8 *)(ADDR_EC_REG_BANK_AHB_ERROR_CONTROL))
-
-#define ADDR_EC_REG_BANK_INTERRUPT_CONTROL                       0x4000FC18
-#define MMCR_EC_REG_BANK_INTERRUPT_CONTROL                       (*(VUINT32 *)(ADDR_EC_REG_BANK_INTERRUPT_CONTROL))
-
-#define ADDR_EC_REG_BANK_ETM_TRACE                               0x4000FC1C
-#define MMCR_EC_REG_BANK_ETM_TRACE                               (*(VUINT32 *)(ADDR_EC_REG_BANK_ETM_TRACE))
-
-#define ADDR_EC_REG_BANK_JTAG_ENABLE                             0x4000FC20
-#define MMCR_EC_REG_BANK_JTAG_ENABLE                             (*(VUINT32 *)(ADDR_EC_REG_BANK_JTAG_ENABLE))
-
-#define ADDR_EC_REG_BANK_PRIVATE_KEY_LOCK                        0x4000FC24
-#define MMCR_EC_REG_BANK_PRIVATE_KEY_LOCK                        (*(VUINT32 *)(ADDR_EC_REG_BANK_PRIVATE_KEY_LOCK))
-
-#define ADDR_EC_REG_BANK_WDT_COUNT                               0x4000FC28
-#define MMCR_EC_REG_BANK_WDT_COUNT                               (*(VUINT32 *)(ADDR_EC_REG_BANK_WDT_COUNT))
-
-#define ADDR_EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL              0x4000FC2C
-#define MMCR_EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL              (*(VUINT32 *)(ADDR_EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL))
-
-#define ADDR_EC_REG_BANK_ADC_VREF_TRIM                           0x4000FC30
-#define MMCR_EC_REG_BANK_ADC_VREF_TRIM                           (*(VUINT32 *)(ADDR_EC_REG_BANK_ADC_VREF_TRIM))
-
-#define ADDR_EC_REG_BANK_REGULATOR_TRIM                          0x4000FC34
-#define MMCR_EC_REG_BANK_REGULATOR_TRIM                          (*(VUINT32 *)(ADDR_EC_REG_BANK_REGULATOR_TRIM))
-
-#define ADDR_EC_REG_BANK_ADC_VREF_PD                             0x4000FC38
-#define MMCR_EC_REG_BANK_ADC_VREF_PD                             (*(VUINT32 *)(ADDR_EC_REG_BANK_ADC_VREF_PD))
-
-#define ADDR_EC_REG_BANK_ADC_COMP_BIAS_CURRENT_ADJUST            0x4000FC3C
-#define MMCR_EC_REG_BANK_ADC_COMP_BIAS_CURRENT_ADJUST            (*(VUINT32 *)(ADDR_EC_REG_BANK_ADC_COMP_BIAS_CURRENT_ADJUST))
-
-#define ADDR_EC_REG_BANK_MISC_TRIM                               0x4000FC40
-#define MMCR_EC_REG_BANK_MISC_TRIM                               (*(VUINT8 *)(ADDR_EC_REG_BANK_MISC_TRIM))
-
-/***************************************************************
-*                            PCR
-***************************************************************/
-#define ADDR_PCR_CHIP_SLEEP_ENABLE                               0x40080100
-#define MMCR_PCR_CHIP_SLEEP_ENABLE                               (*(VUINT32 *)(ADDR_PCR_CHIP_SLEEP_ENABLE))
-
-#define ADDR_PCR_CHIP_CLOCK_REQUIRED                             0x40080104
-#define MMCR_PCR_CHIP_CLOCK_REQUIRED                             (*(VUINT32 *)(ADDR_PCR_CHIP_CLOCK_REQUIRED))
-
-#define ADDR_PCR_EC_SLEEP_ENABLES                                0x40080108
-#define MMCR_PCR_EC_SLEEP_ENABLES                                (*(VUINT32 *)(ADDR_PCR_EC_SLEEP_ENABLES))
-
-#define ADDR_PCR_EC_CLOCK_REQUIRED_STATUS                        0x4008010C
-#define MMCR_PCR_EC_CLOCK_REQUIRED_STATUS                        (*(VUINT32 *)(ADDR_PCR_EC_CLOCK_REQUIRED_STATUS))
-
-#define ADDR_PCR_HOST_SLEEP_ENABLES                              0x40080110
-#define MMCR_PCR_HOST_SLEEP_ENABLES                              (*(VUINT32 *)(ADDR_PCR_HOST_SLEEP_ENABLES))
-
-#define ADDR_PCR_HOST_CLOCK_REQUIRED_STATUS                      0x40080114
-#define MMCR_PCR_HOST_CLOCK_REQUIRED_STATUS                      (*(VUINT32 *)(ADDR_PCR_HOST_CLOCK_REQUIRED_STATUS))
-
-#define ADDR_PCR_CHIP_PCR_ADDR_SYS_SLEEP_CTRL_0                  0x40080118
-#define MMCR_PCR_CHIP_PCR_ADDR_SYS_SLEEP_CTRL_0                  (*(VUINT32 *)(ADDR_PCR_CHIP_PCR_ADDR_SYS_SLEEP_CTRL_0))
-
-#define ADDR_PCR_PROCESSOR_CLOCK_CONTROL                         0x40080120
-#define MMCR_PCR_PROCESSOR_CLOCK_CONTROL                         (*(VUINT32 *)(ADDR_PCR_PROCESSOR_CLOCK_CONTROL))
-
-#define ADDR_PCR_EC_SLEEP_ENABLE_2                               0x40080124
-#define MMCR_PCR_EC_SLEEP_ENABLE_2                               (*(VUINT32 *)(ADDR_PCR_EC_SLEEP_ENABLE_2))
-
-#define ADDR_PCR_EC_CLOCK_REQUIRED_2_STATUS                      0x40080128
-#define MMCR_PCR_EC_CLOCK_REQUIRED_2_STATUS                      (*(VUINT32 *)(ADDR_PCR_EC_CLOCK_REQUIRED_2_STATUS))
-
-#define ADDR_PCR_SLOW_CLOCK_CONTROL                              0x4008012C
-#define MMCR_PCR_SLOW_CLOCK_CONTROL                              (*(VUINT32 *)(ADDR_PCR_SLOW_CLOCK_CONTROL))
-
-#define ADDR_PCR_OSCILLATOR_ID                                   0x40080130
-#define MMCR_PCR_OSCILLATOR_ID                                   (*(VUINT32 *)(ADDR_PCR_OSCILLATOR_ID))
-
-#define ADDR_PCR_CHIP_RESET_ENABLE                               0x40080138
-#define MMCR_PCR_CHIP_RESET_ENABLE                               (*(VUINT32 *)(ADDR_PCR_CHIP_RESET_ENABLE))
-
-#define ADDR_PCR_HOST_RESET_ENABLE                               0x4008013C
-#define MMCR_PCR_HOST_RESET_ENABLE                               (*(VUINT32 *)(ADDR_PCR_HOST_RESET_ENABLE))
-
-#define ADDR_PCR_EC_RESET_ENABLE                                 0x40080140
-#define MMCR_PCR_EC_RESET_ENABLE                                 (*(VUINT32 *)(ADDR_PCR_EC_RESET_ENABLE))
-
-#define ADDR_PCR_EC_RESET_ENABLE_2                               0x40080144
-#define MMCR_PCR_EC_RESET_ENABLE_2                               (*(VUINT32 *)(ADDR_PCR_EC_RESET_ENABLE_2))
-
-#define ADDR_PCR_CLOCK_RESET_CONTROL                             0x40080148
-#define MMCR_PCR_CLOCK_RESET_CONTROL                             (*(VUINT32 *)(ADDR_PCR_CLOCK_RESET_CONTROL))
-
-/***************************************************************
-*                            Public Key Crypto Engine
-***************************************************************/
-#define ADDR_PUBLIC_PK_CONFIGREG                                 0x4000BD00
-#define MMCR_PUBLIC_PK_CONFIGREG                                 (*(VUINT32 *)(ADDR_PUBLIC_PK_CONFIGREG))
-
-#define ADDR_PUBLIC_PK_COMMANDREG                                0x4000BD04
-#define MMCR_PUBLIC_PK_COMMANDREG                                (*(VUINT32 *)(ADDR_PUBLIC_PK_COMMANDREG))
-
-#define ADDR_PUBLIC_PK_CONTROLREG                                0x4000BD08
-#define MMCR_PUBLIC_PK_CONTROLREG                                (*(VUINT32 *)(ADDR_PUBLIC_PK_CONTROLREG))
-
-#define ADDR_PUBLIC_PK_STATUSREG                                 0x4000BD0C
-#define MMCR_PUBLIC_PK_STATUSREG                                 (*(VUINT32 *)(ADDR_PUBLIC_PK_STATUSREG))
-
-#define ADDR_PUBLIC_PK_VERSIONREG                                0x4000BD10
-#define MMCR_PUBLIC_PK_VERSIONREG                                (*(VUINT32 *)(ADDR_PUBLIC_PK_VERSIONREG))
-
-#define ADDR_PUBLIC_PK_LOADMICROCODEREG                          0x4000BD14
-#define MMCR_PUBLIC_PK_LOADMICROCODEREG                          (*(VUINT32 *)(ADDR_PUBLIC_PK_LOADMICROCODEREG))
-
-/***************************************************************
-*                            Non Deterministic Random Number Generator
-***************************************************************/
-#define ADDR_NON_CONTROLREG                                      0x4000BE00
-#define MMCR_NON_CONTROLREG                                      (*(VUINT32 *)(ADDR_NON_CONTROLREG))
-
-#define ADDR_NON_FIFOLEVELREG                                    0x4000BE04
-#define MMCR_NON_FIFOLEVELREG                                    (*(VUINT32 *)(ADDR_NON_FIFOLEVELREG))
-
-#define ADDR_NON_VERSIONREG                                      0x4000BE08
-#define MMCR_NON_VERSIONREG                                      (*(VUINT32 *)(ADDR_NON_VERSIONREG))
-
-/***************************************************************
-*                            RTC
-***************************************************************/
-#define ADDR_RTC_SECONDS                                         0x400F2800
-#define MMCR_RTC_SECONDS                                         (*(VUINT8 *)(ADDR_RTC_SECONDS))
-
-#define ADDR_RTC_SECONDS_ALARM                                   0x400F2801
-#define MMCR_RTC_SECONDS_ALARM                                   (*(VUINT8 *)(ADDR_RTC_SECONDS_ALARM))
-
-#define ADDR_RTC_MINUTES                                         0x400F2802
-#define MMCR_RTC_MINUTES                                         (*(VUINT8 *)(ADDR_RTC_MINUTES))
-
-#define ADDR_RTC_MINUTES_ALARM                                   0x400F2803
-#define MMCR_RTC_MINUTES_ALARM                                   (*(VUINT8 *)(ADDR_RTC_MINUTES_ALARM))
-
-#define ADDR_RTC_HOURS                                           0x400F2804
-#define MMCR_RTC_HOURS                                           (*(VUINT8 *)(ADDR_RTC_HOURS))
-
-#define ADDR_RTC_HOURS_ALARM                                     0x400F2805
-#define MMCR_RTC_HOURS_ALARM                                     (*(VUINT8 *)(ADDR_RTC_HOURS_ALARM))
-
-#define ADDR_RTC_DAY_OF_WEEK                                     0x400F2806
-#define MMCR_RTC_DAY_OF_WEEK                                     (*(VUINT8 *)(ADDR_RTC_DAY_OF_WEEK))
-
-#define ADDR_RTC_DAY_OF_MONTH                                    0x400F2807
-#define MMCR_RTC_DAY_OF_MONTH                                    (*(VUINT8 *)(ADDR_RTC_DAY_OF_MONTH))
-
-#define ADDR_RTC_MONTH                                           0x400F2808
-#define MMCR_RTC_MONTH                                           (*(VUINT8 *)(ADDR_RTC_MONTH))
-
-#define ADDR_RTC_YEAR                                            0x400F2809
-#define MMCR_RTC_YEAR                                            (*(VUINT8 *)(ADDR_RTC_YEAR))
-
-#define ADDR_RTC_A                                               0x400F280A
-#define MMCR_RTC_A                                               (*(VUINT8 *)(ADDR_RTC_A))
-
-#define ADDR_RTC_B                                               0x400F280B
-#define MMCR_RTC_B                                               (*(VUINT8 *)(ADDR_RTC_B))
-
-#define ADDR_RTC_C                                               0x400F280C
-#define MMCR_RTC_C                                               (*(VUINT8 *)(ADDR_RTC_C))
-
-#define ADDR_RTC_D                                               0x400F280D
-#define MMCR_RTC_D                                               (*(VUINT8 *)(ADDR_RTC_D))
-
-#define ADDR_RTC_CONTROL                                         0x400F2810
-#define MMCR_RTC_CONTROL                                         (*(VUINT8 *)(ADDR_RTC_CONTROL))
-
-#define ADDR_RTC_WEEK_ALARM                                      0x400F2814
-#define MMCR_RTC_WEEK_ALARM                                      (*(VUINT8 *)(ADDR_RTC_WEEK_ALARM))
-
-#define ADDR_RTC_DAYLIGHT_SAVINGS_FORWARD                        0x400F2818
-#define MMCR_RTC_DAYLIGHT_SAVINGS_FORWARD                        (*(VUINT32 *)(ADDR_RTC_DAYLIGHT_SAVINGS_FORWARD))
-
-#define ADDR_RTC_DAYLIGHT_SAVINGS_BACKWARD                       0x400F281C
-#define MMCR_RTC_DAYLIGHT_SAVINGS_BACKWARD                       (*(VUINT32 *)(ADDR_RTC_DAYLIGHT_SAVINGS_BACKWARD))
-
-#define ADDR_RTC_TEST_MODE                                       0x400F2820
-#define MMCR_RTC_TEST_MODE                                       (*(VUINT8 *)(ADDR_RTC_TEST_MODE))
-
-/***************************************************************
-*                            Analog to Digital Converter (ADC)
-***************************************************************/
-#define ADDR_ADC_CONTROL                                         0x40007C00
-#define MMCR_ADC_CONTROL                                         (*(VUINT32 *)(ADDR_ADC_CONTROL))
-
-#define ADDR_ADC_DELAY                                           0x40007C04
-#define MMCR_ADC_DELAY                                           (*(VUINT32 *)(ADDR_ADC_DELAY))
-
-#define ADDR_ADC_STATUS                                          0x40007C08
-#define MMCR_ADC_STATUS                                          (*(VUINT32 *)(ADDR_ADC_STATUS))
-
-#define ADDR_ADC_SINGLE                                          0x40007C0C
-#define MMCR_ADC_SINGLE                                          (*(VUINT32 *)(ADDR_ADC_SINGLE))
-
-#define ADDR_ADC_REPEAT                                          0x40007C10
-#define MMCR_ADC_REPEAT                                          (*(VUINT32 *)(ADDR_ADC_REPEAT))
-
-#define ADDR_ADC_CHANNEL_0_READINGS                              0x40007C14
-#define MMCR_ADC_CHANNEL_0_READINGS                              (*(VUINT32 *)(ADDR_ADC_CHANNEL_0_READINGS))
-
-#define ADDR_ADC_CHANNEL_1_READINGS                              0x40007C18
-#define MMCR_ADC_CHANNEL_1_READINGS                              (*(VUINT32 *)(ADDR_ADC_CHANNEL_1_READINGS))
-
-#define ADDR_ADC_CHANNEL_2_READINGS                              0x40007C1C
-#define MMCR_ADC_CHANNEL_2_READINGS                              (*(VUINT32 *)(ADDR_ADC_CHANNEL_2_READINGS))
-
-#define ADDR_ADC_CHANNEL_3_READINGS                              0x40007C20
-#define MMCR_ADC_CHANNEL_3_READINGS                              (*(VUINT32 *)(ADDR_ADC_CHANNEL_3_READINGS))
-
-#define ADDR_ADC_CHANNEL_4_READINGS                              0x40007C24
-#define MMCR_ADC_CHANNEL_4_READINGS                              (*(VUINT32 *)(ADDR_ADC_CHANNEL_4_READINGS))
-
-#define ADDR_ADC_DEBUG_FPGA_TEST_MODE                            0x40007C54
-#define MMCR_ADC_DEBUG_FPGA_TEST_MODE                            (*(VUINT32 *)(ADDR_ADC_DEBUG_FPGA_TEST_MODE))
-
-#define ADDR_ADC_TEST                                            0x40007C78
-#define MMCR_ADC_TEST                                            (*(VUINT32 *)(ADDR_ADC_TEST))
-
-#define ADDR_ADC_CONFIGURATION                                   0x40007C7C
-#define MMCR_ADC_CONFIGURATION                                   (*(VUINT32 *)(ADDR_ADC_CONFIGURATION))
-
-/***************************************************************
-*                            eFUSE
-***************************************************************/
-#define ADDR_EFUSE_CONTROL                                       0x40082000
-#define MMCR_EFUSE_CONTROL                                       (*(VUINT8 *)(ADDR_EFUSE_CONTROL))
-
-#define ADDR_EFUSE_MANUAL_CONTROL                                0x40082004
-#define MMCR_EFUSE_MANUAL_CONTROL                                (*(VUINT8 *)(ADDR_EFUSE_MANUAL_CONTROL))
-
-#define ADDR_EFUSE_MANUAL_MODE_ADDRESS                           0x40082006
-#define MMCR_EFUSE_MANUAL_MODE_ADDRESS                           (*(VUINT16 *)(ADDR_EFUSE_MANUAL_MODE_ADDRESS))
-
-#define ADDR_EFUSE_MANUAL_MODE_DATA                              0x4008200C
-#define MMCR_EFUSE_MANUAL_MODE_DATA                              (*(VUINT16 *)(ADDR_EFUSE_MANUAL_MODE_DATA))
-
-/***************************************************************
-*                            AES Crypto Engine & Hash Function
-***************************************************************/
-#define ADDR_AES_CONFIGREG                                       0x4000D200
-#define MMCR_AES_CONFIGREG                                       (*(VUINT32 *)(ADDR_AES_CONFIGREG))
-
-#define ADDR_AES_COMMANDREG                                      0x4000D204
-#define MMCR_AES_COMMANDREG                                      (*(VUINT32 *)(ADDR_AES_COMMANDREG))
-
-#define ADDR_AES_CONTROLREG                                      0x4000D208
-#define MMCR_AES_CONTROLREG                                      (*(VUINT32 *)(ADDR_AES_CONTROLREG))
-
-#define ADDR_AES_STATUSREG                                       0x4000D20C
-#define MMCR_AES_STATUSREG                                       (*(VUINT32 *)(ADDR_AES_STATUSREG))
-
-#define ADDR_AES_VERSIONREG                                      0x4000D210
-#define MMCR_AES_VERSIONREG                                      (*(VUINT32 *)(ADDR_AES_VERSIONREG))
-
-#define ADDR_AES_NBHEADERREG                                     0x4000D214
-#define MMCR_AES_NBHEADERREG                                     (*(VUINT32 *)(ADDR_AES_NBHEADERREG))
-
-#define ADDR_AES_LASTHEADERREG                                   0x4000D218
-#define MMCR_AES_LASTHEADERREG                                   (*(VUINT32 *)(ADDR_AES_LASTHEADERREG))
-
-#define ADDR_AES_NBBLOCKREG                                      0x4000D21C
-#define MMCR_AES_NBBLOCKREG                                      (*(VUINT32 *)(ADDR_AES_NBBLOCKREG))
-
-#define ADDR_AES_LASTBLOCKREG                                    0x4000D220
-#define MMCR_AES_LASTBLOCKREG                                    (*(VUINT32 *)(ADDR_AES_LASTBLOCKREG))
-
-#define ADDR_AES_DMAINREG                                        0x4000D224
-#define MMCR_AES_DMAINREG                                        (*(VUINT32 *)(ADDR_AES_DMAINREG))
-
-#define ADDR_AES_DMAOUTREG                                       0x4000D228
-#define MMCR_AES_DMAOUTREG                                       (*(VUINT32 *)(ADDR_AES_DMAOUTREG))
-
-#define ADDR_AES_SHAMODE_REGISTER                                0x4000D000
-#define MMCR_AES_SHAMODE_REGISTER                                (*(VUINT32 *)(ADDR_AES_SHAMODE_REGISTER))
-
-#define ADDR_AES_NBBLOCK_REGISTER                                0x4000D004
-#define MMCR_AES_NBBLOCK_REGISTER                                (*(VUINT32 *)(ADDR_AES_NBBLOCK_REGISTER))
-
-#define ADDR_AES_CONTROL                                         0x4000D008
-#define MMCR_AES_CONTROL                                         (*(VUINT32 *)(ADDR_AES_CONTROL))
-
-#define ADDR_AES_STATUS                                          0x4000D00C
-#define MMCR_AES_STATUS                                          (*(VUINT32 *)(ADDR_AES_STATUS))
-
-#define ADDR_AES_VERSION                                         0x4000D010
-#define MMCR_AES_VERSION                                         (*(VUINT32 *)(ADDR_AES_VERSION))
-
-#define ADDR_AES_GENERICVALUE_REGISTER                           0x4000D014
-#define MMCR_AES_GENERICVALUE_REGISTER                           (*(VUINT32 *)(ADDR_AES_GENERICVALUE_REGISTER))
-
-#define ADDR_AES_INITIAL_HASH_SOURCE_ADDRESS                     0x4000D018
-#define MMCR_AES_INITIAL_HASH_SOURCE_ADDRESS                     (*(VUINT32 *)(ADDR_AES_INITIAL_HASH_SOURCE_ADDRESS))
-
-#define ADDR_AES_DATA_SOURCE_ADDRESS                             0x4000D01C
-#define MMCR_AES_DATA_SOURCE_ADDRESS                             (*(VUINT32 *)(ADDR_AES_DATA_SOURCE_ADDRESS))
-
-#define ADDR_AES_HASH_RESULT_DESTINATION_ADDRESS                 0x4000D020
-#define MMCR_AES_HASH_RESULT_DESTINATION_ADDRESS                 (*(VUINT32 *)(ADDR_AES_HASH_RESULT_DESTINATION_ADDRESS))
-
-/***************************************************************
-*                            LPC
-***************************************************************/
-#define ADDR_LPC_ACTIVATE                                        0x400F3330
-#define MMCR_LPC_ACTIVATE                                        (*(VUINT8 *)(ADDR_LPC_ACTIVATE))
-
-#define ADDR_LPC_SIRQ0_INTERRUPT_CONFIGURATION                   0x400F3340
-#define MMCR_LPC_SIRQ0_INTERRUPT_CONFIGURATION                   (*(VUINT8 *)(ADDR_LPC_SIRQ0_INTERRUPT_CONFIGURATION))
-
-#define ADDR_LPC_SIRQ1_INTERRUPT_CONFIGURATION                   0x400F3341
-#define MMCR_LPC_SIRQ1_INTERRUPT_CONFIGURATION                   (*(VUINT8 *)(ADDR_LPC_SIRQ1_INTERRUPT_CONFIGURATION))
-
-#define ADDR_LPC_SIRQ2_INTERRUPT_CONFIGURATION                   0x400F3342
-#define MMCR_LPC_SIRQ2_INTERRUPT_CONFIGURATION                   (*(VUINT8 *)(ADDR_LPC_SIRQ2_INTERRUPT_CONFIGURATION))
-
-#define ADDR_LPC_SIRQ3_INTERRUPT_CONFIGURATION                   0x400F3343
-#define MMCR_LPC_SIRQ3_INTERRUPT_CONFIGURATION                   (*(VUINT8 *)(ADDR_LPC_SIRQ3_INTERRUPT_CONFIGURATION))
-
-#define ADDR_LPC_SIRQ4_INTERRUPT_CONFIGURATION                   0x400F3344
-#define MMCR_LPC_SIRQ4_INTERRUPT_CONFIGURATION                   (*(VUINT8 *)(ADDR_LPC_SIRQ4_INTERRUPT_CONFIGURATION))
-
-#define ADDR_LPC_SIRQ5_INTERRUPT_CONFIGURATION                   0x400F3345
-#define MMCR_LPC_SIRQ5_INTERRUPT_CONFIGURATION                   (*(VUINT8 *)(ADDR_LPC_SIRQ5_INTERRUPT_CONFIGURATION))
-
-#define ADDR_LPC_SIRQ6_INTERRUPT_CONFIGURATION                   0x400F3346
-#define MMCR_LPC_SIRQ6_INTERRUPT_CONFIGURATION                   (*(VUINT8 *)(ADDR_LPC_SIRQ6_INTERRUPT_CONFIGURATION))
-
-#define ADDR_LPC_SIRQ7_INTERRUPT_CONFIGURATION                   0x400F3347
-#define MMCR_LPC_SIRQ7_INTERRUPT_CONFIGURATION                   (*(VUINT8 *)(ADDR_LPC_SIRQ7_INTERRUPT_CONFIGURATION))
-
-#define ADDR_LPC_SIRQ8_INTERRUPT_CONFIGURATION                   0x400F3348
-#define MMCR_LPC_SIRQ8_INTERRUPT_CONFIGURATION                   (*(VUINT8 *)(ADDR_LPC_SIRQ8_INTERRUPT_CONFIGURATION))
-
-#define ADDR_LPC_SIRQ9_INTERRUPT_CONFIGURATION                   0x400F3349
-#define MMCR_LPC_SIRQ9_INTERRUPT_CONFIGURATION                   (*(VUINT8 *)(ADDR_LPC_SIRQ9_INTERRUPT_CONFIGURATION))
-
-#define ADDR_LPC_SIRQ10_INTERRUPT_CONFIGURATION                  0x400F334A
-#define MMCR_LPC_SIRQ10_INTERRUPT_CONFIGURATION                  (*(VUINT8 *)(ADDR_LPC_SIRQ10_INTERRUPT_CONFIGURATION))
-
-#define ADDR_LPC_SIRQ11_INTERRUPT_CONFIGURATION                  0x400F334B
-#define MMCR_LPC_SIRQ11_INTERRUPT_CONFIGURATION                  (*(VUINT8 *)(ADDR_LPC_SIRQ11_INTERRUPT_CONFIGURATION))
-
-#define ADDR_LPC_SIRQ12_INTERRUPT_CONFIGURATION                  0x400F334C
-#define MMCR_LPC_SIRQ12_INTERRUPT_CONFIGURATION                  (*(VUINT8 *)(ADDR_LPC_SIRQ12_INTERRUPT_CONFIGURATION))
-
-#define ADDR_LPC_SIRQ13_INTERRUPT_CONFIGURATION                  0x400F334D
-#define MMCR_LPC_SIRQ13_INTERRUPT_CONFIGURATION                  (*(VUINT8 *)(ADDR_LPC_SIRQ13_INTERRUPT_CONFIGURATION))
-
-#define ADDR_LPC_SIRQ14_INTERRUPT_CONFIGURATION                  0x400F334E
-#define MMCR_LPC_SIRQ14_INTERRUPT_CONFIGURATION                  (*(VUINT8 *)(ADDR_LPC_SIRQ14_INTERRUPT_CONFIGURATION))
-
-#define ADDR_LPC_SIRQ15_INTERRUPT_CONFIGURATION                  0x400F334F
-#define MMCR_LPC_SIRQ15_INTERRUPT_CONFIGURATION                  (*(VUINT8 *)(ADDR_LPC_SIRQ15_INTERRUPT_CONFIGURATION))
-
-#define ADDR_LPC_INTERFACE_BAR                                   0x400F3360
-#define MMCR_LPC_INTERFACE_BAR                                   (*(VUINT32 *)(ADDR_LPC_INTERFACE_BAR))
-
-#define ADDR_LPC_EM_INTERFACE_0_BAR                              0x400F3364
-#define MMCR_LPC_EM_INTERFACE_0_BAR                              (*(VUINT32 *)(ADDR_LPC_EM_INTERFACE_0_BAR))
-
-#define ADDR_LPC_UART_0_BAR                                      0x400F3368
-#define MMCR_LPC_UART_0_BAR                                      (*(VUINT32 *)(ADDR_LPC_UART_0_BAR))
-
-#define ADDR_LPC_KEYBOARD_CONTROLLER_BAR                         0x400F3378
-#define MMCR_LPC_KEYBOARD_CONTROLLER_BAR                         (*(VUINT32 *)(ADDR_LPC_KEYBOARD_CONTROLLER_BAR))
-
-#define ADDR_LPC_ACPI_EC_INTERFACE_0_BAR                         0x400F3388
-#define MMCR_LPC_ACPI_EC_INTERFACE_0_BAR                         (*(VUINT32 *)(ADDR_LPC_ACPI_EC_INTERFACE_0_BAR))
-
-#define ADDR_LPC_ACPI_EC_INTERFACE_1_BAR                         0x400F338C
-#define MMCR_LPC_ACPI_EC_INTERFACE_1_BAR                         (*(VUINT32 *)(ADDR_LPC_ACPI_EC_INTERFACE_1_BAR))
-
-#define ADDR_LPC_ACPI_PM1_INTERFACE_BAR                          0x400F3390
-#define MMCR_LPC_ACPI_PM1_INTERFACE_BAR                          (*(VUINT32 *)(ADDR_LPC_ACPI_PM1_INTERFACE_BAR))
-
-#define ADDR_LPC_LEGACY_GATEA20_INTERFACE_BAR                    0x400F3394
-#define MMCR_LPC_LEGACY_GATEA20_INTERFACE_BAR                    (*(VUINT32 *)(ADDR_LPC_LEGACY_GATEA20_INTERFACE_BAR))
-
-#define ADDR_LPC_MAILBOXS_INTERFACE_BAR                          0x400F3398
-#define MMCR_LPC_MAILBOXS_INTERFACE_BAR                          (*(VUINT32 *)(ADDR_LPC_MAILBOXS_INTERFACE_BAR))
-
-#define ADDR_LPC_BUS_MONITOR                                     0x400F3104
-#define MMCR_LPC_BUS_MONITOR                                     (*(VUINT32 *)(ADDR_LPC_BUS_MONITOR))
-
-#define ADDR_LPC_HOST_BUS_ERROR                                  0x400F3108
-#define MMCR_LPC_HOST_BUS_ERROR                                  (*(VUINT32 *)(ADDR_LPC_HOST_BUS_ERROR))
-
-#define ADDR_LPC_EC_SERIRQ                                       0x400F310C
-#define MMCR_LPC_EC_SERIRQ                                       (*(VUINT32 *)(ADDR_LPC_EC_SERIRQ))
-
-#define ADDR_LPC_EC_CLOCK_CONTROL                                0x400F3110
-#define MMCR_LPC_EC_CLOCK_CONTROL                                (*(VUINT32 *)(ADDR_LPC_EC_CLOCK_CONTROL))
-
-#define ADDR_LPC_BAR_INHIBIT                                     0x400F3120
-#define MMCR_LPC_BAR_INHIBIT                                     (*(VUINT32 *)(ADDR_LPC_BAR_INHIBIT))
-
-#define ADDR_LPC_BAR_INIT                                        0x400F3130
-#define MMCR_LPC_BAR_INIT                                        (*(VUINT16 *)(ADDR_LPC_BAR_INIT))
-
-#define ADDR_LPC_MEMORY_HOST_CONFIGURATION                       0x400F31FC
-#define MMCR_LPC_MEMORY_HOST_CONFIGURATION                       (*(VUINT32 *)(ADDR_LPC_MEMORY_HOST_CONFIGURATION))
-
-/***************************************************************
-*                            GPIO
-***************************************************************/
-#define ADDR_GPIO000_PIN_CONTROL                                 0x40081000
-#define MMCR_GPIO000_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO000_PIN_CONTROL))
-
-#define ADDR_GPIO001_PIN_CONTROL                                 0x40081004
-#define MMCR_GPIO001_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO001_PIN_CONTROL))
-
-#define ADDR_GPIO002_PIN_CONTROL                                 0x40081008
-#define MMCR_GPIO002_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO002_PIN_CONTROL))
-
-#define ADDR_GPIO003_PIN_CONTROL                                 0x4008100C
-#define MMCR_GPIO003_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO003_PIN_CONTROL))
-
-#define ADDR_GPIO004_PIN_CONTROL                                 0x40081010
-#define MMCR_GPIO004_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO004_PIN_CONTROL))
-
-#define ADDR_GPIO005_PIN_CONTROL                                 0x40081014
-#define MMCR_GPIO005_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO005_PIN_CONTROL))
-
-#define ADDR_GPIO006_PIN_CONTROL                                 0x40081018
-#define MMCR_GPIO006_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO006_PIN_CONTROL))
-
-#define ADDR_GPIO007_PIN_CONTROL                                 0x4008101C
-#define MMCR_GPIO007_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO007_PIN_CONTROL))
-
-#define ADDR_GPIO010_PIN_CONTROL                                 0x40081020
-#define MMCR_GPIO010_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO010_PIN_CONTROL))
-
-#define ADDR_GPIO011_PIN_CONTROL                                 0x40081024
-#define MMCR_GPIO011_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO011_PIN_CONTROL))
-
-#define ADDR_GPIO012_PIN_CONTROL                                 0x40081028
-#define MMCR_GPIO012_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO012_PIN_CONTROL))
-
-#define ADDR_GPIO013_PIN_CONTROL                                 0x4008102C
-#define MMCR_GPIO013_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO013_PIN_CONTROL))
-
-#define ADDR_GPIO014_PIN_CONTROL                                 0x40081030
-#define MMCR_GPIO014_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO014_PIN_CONTROL))
-
-#define ADDR_GPIO015_PIN_CONTROL                                 0x40081034
-#define MMCR_GPIO015_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO015_PIN_CONTROL))
-
-#define ADDR_GPIO016_PIN_CONTROL                                 0x40081038
-#define MMCR_GPIO016_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO016_PIN_CONTROL))
-
-#define ADDR_GPIO017_PIN_CONTROL                                 0x4008103C
-#define MMCR_GPIO017_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO017_PIN_CONTROL))
-
-#define ADDR_GPIO020_PIN_CONTROL                                 0x40081040
-#define MMCR_GPIO020_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO020_PIN_CONTROL))
-
-#define ADDR_GPIO021_PIN_CONTROL                                 0x40081044
-#define MMCR_GPIO021_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO021_PIN_CONTROL))
-
-#define ADDR_GPIO022_PIN_CONTROL                                 0x40081048
-#define MMCR_GPIO022_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO022_PIN_CONTROL))
-
-#define ADDR_GPIO023_PIN_CONTROL                                 0x4008104C
-#define MMCR_GPIO023_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO023_PIN_CONTROL))
-
-#define ADDR_GPIO024_PIN_CONTROL                                 0x40081050
-#define MMCR_GPIO024_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO024_PIN_CONTROL))
-
-#define ADDR_GPIO025_PIN_CONTROL                                 0x40081054
-#define MMCR_GPIO025_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO025_PIN_CONTROL))
-
-#define ADDR_GPIO026_PIN_CONTROL                                 0x40081058
-#define MMCR_GPIO026_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO026_PIN_CONTROL))
-
-#define ADDR_GPIO027_PIN_CONTROL                                 0x4008105C
-#define MMCR_GPIO027_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO027_PIN_CONTROL))
-
-#define ADDR_GPIO030_PIN_CONTROL                                 0x40081060
-#define MMCR_GPIO030_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO030_PIN_CONTROL))
-
-#define ADDR_GPIO031_PIN_CONTROL                                 0x40081064
-#define MMCR_GPIO031_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO031_PIN_CONTROL))
-
-#define ADDR_GPIO032_PIN_CONTROL                                 0x40081068
-#define MMCR_GPIO032_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO032_PIN_CONTROL))
-
-#define ADDR_GPIO033_PIN_CONTROL                                 0x4008106C
-#define MMCR_GPIO033_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO033_PIN_CONTROL))
-
-#define ADDR_GPIO034_PIN_CONTROL                                 0x40081070
-#define MMCR_GPIO034_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO034_PIN_CONTROL))
-
-#define ADDR_GPIO035_PIN_CONTROL                                 0x40081074
-#define MMCR_GPIO035_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO035_PIN_CONTROL))
-
-#define ADDR_GPIO036_PIN_CONTROL                                 0x40081078
-#define MMCR_GPIO036_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO036_PIN_CONTROL))
-
-#define ADDR_GPIO040_PIN_CONTROL                                 0x40081080
-#define MMCR_GPIO040_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO040_PIN_CONTROL))
-
-#define ADDR_GPIO041_PIN_CONTROL                                 0x40081084
-#define MMCR_GPIO041_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO041_PIN_CONTROL))
-
-#define ADDR_GPIO042_PIN_CONTROL                                 0x40081088
-#define MMCR_GPIO042_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO042_PIN_CONTROL))
-
-#define ADDR_GPIO043_PIN_CONTROL                                 0x4008108C
-#define MMCR_GPIO043_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO043_PIN_CONTROL))
-
-#define ADDR_GPIO044_PIN_CONTROL                                 0x40081090
-#define MMCR_GPIO044_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO044_PIN_CONTROL))
-
-#define ADDR_GPIO045_PIN_CONTROL                                 0x40081094
-#define MMCR_GPIO045_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO045_PIN_CONTROL))
-
-#define ADDR_GPIO046_PIN_CONTROL                                 0x40081098
-#define MMCR_GPIO046_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO046_PIN_CONTROL))
-
-#define ADDR_GPIO047_PIN_CONTROL                                 0x4008109C
-#define MMCR_GPIO047_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO047_PIN_CONTROL))
-
-#define ADDR_GPIO050_PIN_CONTROL                                 0x400810A0
-#define MMCR_GPIO050_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO050_PIN_CONTROL))
-
-#define ADDR_GPIO051_PIN_CONTROL                                 0x400810A4
-#define MMCR_GPIO051_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO051_PIN_CONTROL))
-
-#define ADDR_GPIO052_PIN_CONTROL                                 0x400810A8
-#define MMCR_GPIO052_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO052_PIN_CONTROL))
-
-#define ADDR_GPIO053_PIN_CONTROL                                 0x400810AC
-#define MMCR_GPIO053_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO053_PIN_CONTROL))
-
-#define ADDR_GPIO054_PIN_CONTROL                                 0x400810B0
-#define MMCR_GPIO054_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO054_PIN_CONTROL))
-
-#define ADDR_GPIO055_PIN_CONTROL                                 0x400810B4
-#define MMCR_GPIO055_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO055_PIN_CONTROL))
-
-#define ADDR_GPIO056_PIN_CONTROL                                 0x400810B8
-#define MMCR_GPIO056_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO056_PIN_CONTROL))
-
-#define ADDR_GPIO057_PIN_CONTROL                                 0x400810BC
-#define MMCR_GPIO057_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO057_PIN_CONTROL))
-
-#define ADDR_GPIO060_PIN_CONTROL                                 0x400810C0
-#define MMCR_GPIO060_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO060_PIN_CONTROL))
-
-#define ADDR_GPIO061_PIN_CONTROL                                 0x400810C4
-#define MMCR_GPIO061_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO061_PIN_CONTROL))
-
-#define ADDR_GPIO062_PIN_CONTROL                                 0x400810C8
-#define MMCR_GPIO062_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO062_PIN_CONTROL))
-
-#define ADDR_GPIO063_PIN_CONTROL                                 0x400810CC
-#define MMCR_GPIO063_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO063_PIN_CONTROL))
-
-#define ADDR_GPIO064_PIN_CONTROL                                 0x400810D0
-#define MMCR_GPIO064_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO064_PIN_CONTROL))
-
-#define ADDR_GPIO065_PIN_CONTROL                                 0x400810D4
-#define MMCR_GPIO065_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO065_PIN_CONTROL))
-
-#define ADDR_GPIO066_PIN_CONTROL                                 0x400810D8
-#define MMCR_GPIO066_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO066_PIN_CONTROL))
-
-#define ADDR_GPIO067_PIN_CONTROL                                 0x400810DC
-#define MMCR_GPIO067_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO067_PIN_CONTROL))
-
-#define ADDR_GPIO100_PIN_CONTROL                                 0x40081100
-#define MMCR_GPIO100_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO100_PIN_CONTROL))
-
-#define ADDR_GPIO101_PIN_CONTROL                                 0x40081104
-#define MMCR_GPIO101_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO101_PIN_CONTROL))
-
-#define ADDR_GPIO102_PIN_CONTROL                                 0x40081108
-#define MMCR_GPIO102_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO102_PIN_CONTROL))
-
-#define ADDR_GPIO103_PIN_CONTROL                                 0x4008110C
-#define MMCR_GPIO103_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO103_PIN_CONTROL))
-
-#define ADDR_GPIO104_PIN_CONTROL                                 0x40081110
-#define MMCR_GPIO104_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO104_PIN_CONTROL))
-
-#define ADDR_GPIO105_PIN_CONTROL                                 0x40081114
-#define MMCR_GPIO105_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO105_PIN_CONTROL))
-
-#define ADDR_GPIO106_PIN_CONTROL                                 0x40081118
-#define MMCR_GPIO106_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO106_PIN_CONTROL))
-
-#define ADDR_GPIO107_PIN_CONTROL                                 0x4008111C
-#define MMCR_GPIO107_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO107_PIN_CONTROL))
-
-#define ADDR_GPIO110_PIN_CONTROL                                 0x40081120
-#define MMCR_GPIO110_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO110_PIN_CONTROL))
-
-#define ADDR_GPIO111_PIN_CONTROL                                 0x40081124
-#define MMCR_GPIO111_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO111_PIN_CONTROL))
-
-#define ADDR_GPIO112_PIN_CONTROL                                 0x40081128
-#define MMCR_GPIO112_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO112_PIN_CONTROL))
-
-#define ADDR_GPIO113_PIN_CONTROL                                 0x4008112C
-#define MMCR_GPIO113_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO113_PIN_CONTROL))
-
-#define ADDR_GPIO114_PIN_CONTROL                                 0x40081130
-#define MMCR_GPIO114_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO114_PIN_CONTROL))
-
-#define ADDR_GPIO115_PIN_CONTROL                                 0x40081134
-#define MMCR_GPIO115_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO115_PIN_CONTROL))
-
-#define ADDR_GPIO116_PIN_CONTROL                                 0x40081138
-#define MMCR_GPIO116_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO116_PIN_CONTROL))
-
-#define ADDR_GPIO117_PIN_CONTROL                                 0x4008113C
-#define MMCR_GPIO117_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO117_PIN_CONTROL))
-
-#define ADDR_GPIO120_PIN_CONTROL                                 0x40081140
-#define MMCR_GPIO120_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO120_PIN_CONTROL))
-
-#define ADDR_GPIO121_PIN_CONTROL                                 0x40081144
-#define MMCR_GPIO121_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO121_PIN_CONTROL))
-
-#define ADDR_GPIO122_PIN_CONTROL                                 0x40081148
-#define MMCR_GPIO122_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO122_PIN_CONTROL))
-
-#define ADDR_GPIO123_PIN_CONTROL                                 0x4008114C
-#define MMCR_GPIO123_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO123_PIN_CONTROL))
-
-#define ADDR_GPIO124_PIN_CONTROL                                 0x40081150
-#define MMCR_GPIO124_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO124_PIN_CONTROL))
-
-#define ADDR_GPIO125_PIN_CONTROL                                 0x40081154
-#define MMCR_GPIO125_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO125_PIN_CONTROL))
-
-#define ADDR_GPIO126_PIN_CONTROL                                 0x40081158
-#define MMCR_GPIO126_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO126_PIN_CONTROL))
-
-#define ADDR_GPIO127_PIN_CONTROL                                 0x4008115C
-#define MMCR_GPIO127_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO127_PIN_CONTROL))
-
-#define ADDR_GPIO130_PIN_CONTROL                                 0x40081160
-#define MMCR_GPIO130_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO130_PIN_CONTROL))
-
-#define ADDR_GPIO131_PIN_CONTROL                                 0x40081164
-#define MMCR_GPIO131_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO131_PIN_CONTROL))
-
-#define ADDR_GPIO132_PIN_CONTROL                                 0x40081168
-#define MMCR_GPIO132_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO132_PIN_CONTROL))
-
-#define ADDR_GPIO133_PIN_CONTROL                                 0x4008116C
-#define MMCR_GPIO133_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO133_PIN_CONTROL))
-
-#define ADDR_GPIO134_PIN_CONTROL                                 0x40081170
-#define MMCR_GPIO134_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO134_PIN_CONTROL))
-
-#define ADDR_GPIO135_PIN_CONTROL                                 0x40081174
-#define MMCR_GPIO135_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO135_PIN_CONTROL))
-
-#define ADDR_GPIO136_PIN_CONTROL                                 0x40081178
-#define MMCR_GPIO136_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO136_PIN_CONTROL))
-
-#define ADDR_GPIO140_PIN_CONTROL                                 0x40081180
-#define MMCR_GPIO140_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO140_PIN_CONTROL))
-
-#define ADDR_GPIO141_PIN_CONTROL                                 0x40081184
-#define MMCR_GPIO141_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO141_PIN_CONTROL))
-
-#define ADDR_GPIO142_PIN_CONTROL                                 0x40081188
-#define MMCR_GPIO142_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO142_PIN_CONTROL))
-
-#define ADDR_GPIO143_PIN_CONTROL                                 0x4008118C
-#define MMCR_GPIO143_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO143_PIN_CONTROL))
-
-#define ADDR_GPIO144_PIN_CONTROL                                 0x40081190
-#define MMCR_GPIO144_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO144_PIN_CONTROL))
-
-#define ADDR_GPIO145_PIN_CONTROL                                 0x40081194
-#define MMCR_GPIO145_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO145_PIN_CONTROL))
-
-#define ADDR_GPIO146_PIN_CONTROL                                 0x40081198
-#define MMCR_GPIO146_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO146_PIN_CONTROL))
-
-#define ADDR_GPIO147_PIN_CONTROL                                 0x4008119C
-#define MMCR_GPIO147_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO147_PIN_CONTROL))
-
-#define ADDR_GPIO150_PIN_CONTROL                                 0x400811A0
-#define MMCR_GPIO150_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO150_PIN_CONTROL))
-
-#define ADDR_GPIO151_PIN_CONTROL                                 0x400811A4
-#define MMCR_GPIO151_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO151_PIN_CONTROL))
-
-#define ADDR_GPIO152_PIN_CONTROL                                 0x400811A8
-#define MMCR_GPIO152_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO152_PIN_CONTROL))
-
-#define ADDR_GPIO153_PIN_CONTROL                                 0x400811AC
-#define MMCR_GPIO153_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO153_PIN_CONTROL))
-
-#define ADDR_GPIO154_PIN_CONTROL                                 0x400811B0
-#define MMCR_GPIO154_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO154_PIN_CONTROL))
-
-#define ADDR_GPIO155_PIN_CONTROL                                 0x400811B4
-#define MMCR_GPIO155_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO155_PIN_CONTROL))
-
-#define ADDR_GPIO156_PIN_CONTROL                                 0x400811B8
-#define MMCR_GPIO156_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO156_PIN_CONTROL))
-
-#define ADDR_GPIO157_PIN_CONTROL                                 0x400811BC
-#define MMCR_GPIO157_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO157_PIN_CONTROL))
-
-#define ADDR_GPIO160_PIN_CONTROL                                 0x400811C0
-#define MMCR_GPIO160_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO160_PIN_CONTROL))
-
-#define ADDR_GPIO161_PIN_CONTROL                                 0x400811C4
-#define MMCR_GPIO161_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO161_PIN_CONTROL))
-
-#define ADDR_GPIO162_PIN_CONTROL                                 0x400811C8
-#define MMCR_GPIO162_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO162_PIN_CONTROL))
-
-#define ADDR_GPIO163_PIN_CONTROL                                 0x400811CC
-#define MMCR_GPIO163_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO163_PIN_CONTROL))
-
-#define ADDR_GPIO164_PIN_CONTROL                                 0x400811D0
-#define MMCR_GPIO164_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO164_PIN_CONTROL))
-
-#define ADDR_GPIO165_PIN_CONTROL                                 0x400811D4
-#define MMCR_GPIO165_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO165_PIN_CONTROL))
-
-#define ADDR_GPIO200_PIN_CONTROL                                 0x40081200
-#define MMCR_GPIO200_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO200_PIN_CONTROL))
-
-#define ADDR_GPIO201_PIN_CONTROL                                 0x40081204
-#define MMCR_GPIO201_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO201_PIN_CONTROL))
-
-#define ADDR_GPIO202_PIN_CONTROL                                 0x40081208
-#define MMCR_GPIO202_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO202_PIN_CONTROL))
-
-#define ADDR_GPIO203_PIN_CONTROL                                 0x4008120C
-#define MMCR_GPIO203_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO203_PIN_CONTROL))
-
-#define ADDR_GPIO204_PIN_CONTROL                                 0x40081210
-#define MMCR_GPIO204_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO204_PIN_CONTROL))
-
-#define ADDR_GPIO206_PIN_CONTROL                                 0x40081218
-#define MMCR_GPIO206_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO206_PIN_CONTROL))
-
-#define ADDR_GPIO210_PIN_CONTROL                                 0x40081220
-#define MMCR_GPIO210_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO210_PIN_CONTROL))
-
-#define ADDR_GPIO211_PIN_CONTROL                                 0x40081224
-#define MMCR_GPIO211_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO211_PIN_CONTROL))
-
-#define ADDR_GPIO212_PIN_CONTROL                                 0x40081228
-#define MMCR_GPIO212_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO212_PIN_CONTROL))
-
-#define ADDR_GPIO213_PIN_CONTROL                                 0x4008122C
-#define MMCR_GPIO213_PIN_CONTROL                                 (*(VUINT32 *)(ADDR_GPIO213_PIN_CONTROL))
-
-#define ADDR_GPIO_OUTPUT_GPIO_000_036                            0x40081280
-#define MMCR_GPIO_OUTPUT_GPIO_000_036                            (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_000_036))
-
-#define ADDR_GPIO_OUTPUT_GPIO_040_076                            0x40081284
-#define MMCR_GPIO_OUTPUT_GPIO_040_076                            (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_040_076))
-
-#define ADDR_GPIO_OUTPUT_GPIO_100_136                            0x40081288
-#define MMCR_GPIO_OUTPUT_GPIO_100_136                            (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_100_136))
-
-#define ADDR_GPIO_OUTPUT_GPIO_140_176                            0x4008128C
-#define MMCR_GPIO_OUTPUT_GPIO_140_176                            (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_140_176))
-
-#define ADDR_GPIO_OUTPUT_GPIO_200_236                            0x40081290
-#define MMCR_GPIO_OUTPUT_GPIO_200_236                            (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_200_236))
-
-#define ADDR_GPIO_INPUT_GPIO_000_036                             0x40081300
-#define MMCR_GPIO_INPUT_GPIO_000_036                             (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_000_036))
-
-#define ADDR_GPIO_INPUT_GPIO_040_076                             0x40081304
-#define MMCR_GPIO_INPUT_GPIO_040_076                             (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_040_076))
-
-#define ADDR_GPIO_INPUT_GPIO_100_136                             0x40081308
-#define MMCR_GPIO_INPUT_GPIO_100_136                             (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_100_136))
-
-#define ADDR_GPIO_INPUT_GPIO_140_176                             0x4008130C
-#define MMCR_GPIO_INPUT_GPIO_140_176                             (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_140_176))
-
-#define ADDR_GPIO_INPUT_GPIO_200_236                             0x40081310
-#define MMCR_GPIO_INPUT_GPIO_200_236                             (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_200_236))
-
-#define ADDR_GPIO_LOCK_4                                         0x400813EC
-#define MMCR_GPIO_LOCK_4                                         (*(VUINT32 *)(ADDR_GPIO_LOCK_4))
-
-#define ADDR_GPIO_LOCK_3                                         0x400813F0
-#define MMCR_GPIO_LOCK_3                                         (*(VUINT32 *)(ADDR_GPIO_LOCK_3))
-
-#define ADDR_GPIO_LOCK_2                                         0x400813F4
-#define MMCR_GPIO_LOCK_2                                         (*(VUINT32 *)(ADDR_GPIO_LOCK_2))
-
-#define ADDR_GPIO_LOCK_1                                         0x400813F8
-#define MMCR_GPIO_LOCK_1                                         (*(VUINT32 *)(ADDR_GPIO_LOCK_1))
-
-#define ADDR_GPIO_LOCK_0                                         0x400813FC
-#define MMCR_GPIO_LOCK_0                                         (*(VUINT32 *)(ADDR_GPIO_LOCK_0))
-
-#define ADDR_GPIO000_PIN_CONTROL_2                               0x40081500
-#define MMCR_GPIO000_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO000_PIN_CONTROL_2))
-
-#define ADDR_GPIO001_PIN_CONTROL_2                               0x40081504
-#define MMCR_GPIO001_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO001_PIN_CONTROL_2))
-
-#define ADDR_GPIO002_PIN_CONTROL_2                               0x40081508
-#define MMCR_GPIO002_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO002_PIN_CONTROL_2))
-
-#define ADDR_GPIO003_PIN_CONTROL_2                               0x4008150C
-#define MMCR_GPIO003_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO003_PIN_CONTROL_2))
-
-#define ADDR_GPIO004_PIN_CONTROL_2                               0x40081510
-#define MMCR_GPIO004_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO004_PIN_CONTROL_2))
-
-#define ADDR_GPIO005_PIN_CONTROL_2                               0x40081514
-#define MMCR_GPIO005_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO005_PIN_CONTROL_2))
-
-#define ADDR_GPIO006_PIN_CONTROL_2                               0x40081518
-#define MMCR_GPIO006_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO006_PIN_CONTROL_2))
-
-#define ADDR_GPIO007_PIN_CONTROL_2                               0x4008151C
-#define MMCR_GPIO007_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO007_PIN_CONTROL_2))
-
-#define ADDR_GPIO010_PIN_CONTROL_2                               0x40081520
-#define MMCR_GPIO010_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO010_PIN_CONTROL_2))
-
-#define ADDR_GPIO011_PIN_CONTROL_2                               0x40081524
-#define MMCR_GPIO011_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO011_PIN_CONTROL_2))
-
-#define ADDR_GPIO012_PIN_CONTROL_2                               0x40081528
-#define MMCR_GPIO012_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO012_PIN_CONTROL_2))
-
-#define ADDR_GPIO013_PIN_CONTROL_2                               0x4008152C
-#define MMCR_GPIO013_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO013_PIN_CONTROL_2))
-
-#define ADDR_GPIO014_PIN_CONTROL_2                               0x40081530
-#define MMCR_GPIO014_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO014_PIN_CONTROL_2))
-
-#define ADDR_GPIO015_PIN_CONTROL_2                               0x40081534
-#define MMCR_GPIO015_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO015_PIN_CONTROL_2))
-
-#define ADDR_GPIO016_PIN_CONTROL_2                               0x40081538
-#define MMCR_GPIO016_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO016_PIN_CONTROL_2))
-
-#define ADDR_GPIO017_PIN_CONTROL_2                               0x4008153C
-#define MMCR_GPIO017_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO017_PIN_CONTROL_2))
-
-#define ADDR_GPIO020_PIN_CONTROL_2                               0x40081540
-#define MMCR_GPIO020_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO020_PIN_CONTROL_2))
-
-#define ADDR_GPIO021_PIN_CONTROL_2                               0x40081544
-#define MMCR_GPIO021_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO021_PIN_CONTROL_2))
-
-#define ADDR_GPIO022_PIN_CONTROL_2                               0x40081548
-#define MMCR_GPIO022_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO022_PIN_CONTROL_2))
-
-#define ADDR_GPIO023_PIN_CONTROL_2                               0x4008154C
-#define MMCR_GPIO023_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO023_PIN_CONTROL_2))
-
-#define ADDR_GPIO024_PIN_CONTROL_2                               0x40081550
-#define MMCR_GPIO024_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO024_PIN_CONTROL_2))
-
-#define ADDR_GPIO025_PIN_CONTROL_2                               0x40081554
-#define MMCR_GPIO025_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO025_PIN_CONTROL_2))
-
-#define ADDR_GPIO026_PIN_CONTROL_2                               0x40081558
-#define MMCR_GPIO026_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO026_PIN_CONTROL_2))
-
-#define ADDR_GPIO027_PIN_CONTROL_2                               0x4008155C
-#define MMCR_GPIO027_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO027_PIN_CONTROL_2))
-
-#define ADDR_GPIO030_PIN_CONTROL_2                               0x40081560
-#define MMCR_GPIO030_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO030_PIN_CONTROL_2))
-
-#define ADDR_GPIO031_PIN_CONTROL_2                               0x40081564
-#define MMCR_GPIO031_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO031_PIN_CONTROL_2))
-
-#define ADDR_GPIO032_PIN_CONTROL_2                               0x40081568
-#define MMCR_GPIO032_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO032_PIN_CONTROL_2))
-
-#define ADDR_GPIO033_PIN_CONTROL_2                               0x4008156C
-#define MMCR_GPIO033_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO033_PIN_CONTROL_2))
-
-#define ADDR_GPIO034_PIN_CONTROL_2                               0x40081570
-#define MMCR_GPIO034_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO034_PIN_CONTROL_2))
-
-#define ADDR_GPIO035_PIN_CONTROL_2                               0x40081574
-#define MMCR_GPIO035_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO035_PIN_CONTROL_2))
-
-#define ADDR_GPIO036_PIN_CONTROL_2                               0x40081578
-#define MMCR_GPIO036_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO036_PIN_CONTROL_2))
-
-#define ADDR_GPIO040_PIN_CONTROL_2                               0x40081580
-#define MMCR_GPIO040_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO040_PIN_CONTROL_2))
-
-#define ADDR_GPIO041_PIN_CONTROL_2                               0x40081584
-#define MMCR_GPIO041_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO041_PIN_CONTROL_2))
-
-#define ADDR_GPIO042_PIN_CONTROL_2                               0x40081588
-#define MMCR_GPIO042_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO042_PIN_CONTROL_2))
-
-#define ADDR_GPIO043_PIN_CONTROL_2                               0x4008158C
-#define MMCR_GPIO043_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO043_PIN_CONTROL_2))
-
-#define ADDR_GPIO044_PIN_CONTROL_2                               0x40081590
-#define MMCR_GPIO044_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO044_PIN_CONTROL_2))
-
-#define ADDR_GPIO045_PIN_CONTROL_2                               0x40081594
-#define MMCR_GPIO045_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO045_PIN_CONTROL_2))
-
-#define ADDR_GPIO046_PIN_CONTROL_2                               0x40081598
-#define MMCR_GPIO046_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO046_PIN_CONTROL_2))
-
-#define ADDR_GPIO047_PIN_CONTROL_2                               0x4008159C
-#define MMCR_GPIO047_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO047_PIN_CONTROL_2))
-
-#define ADDR_GPIO050_PIN_CONTROL_2                               0x400815A0
-#define MMCR_GPIO050_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO050_PIN_CONTROL_2))
-
-#define ADDR_GPIO051_PIN_CONTROL_2                               0x400815A4
-#define MMCR_GPIO051_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO051_PIN_CONTROL_2))
-
-#define ADDR_GPIO052_PIN_CONTROL_2                               0x400815A8
-#define MMCR_GPIO052_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO052_PIN_CONTROL_2))
-
-#define ADDR_GPIO053_PIN_CONTROL_2                               0x400815AC
-#define MMCR_GPIO053_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO053_PIN_CONTROL_2))
-
-#define ADDR_GPIO054_PIN_CONTROL_2                               0x400815B0
-#define MMCR_GPIO054_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO054_PIN_CONTROL_2))
-
-#define ADDR_GPIO055_PIN_CONTROL_2                               0x400815B4
-#define MMCR_GPIO055_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO055_PIN_CONTROL_2))
-
-#define ADDR_GPIO056_PIN_CONTROL_2                               0x400815B8
-#define MMCR_GPIO056_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO056_PIN_CONTROL_2))
-
-#define ADDR_GPIO057_PIN_CONTROL_2                               0x400815BC
-#define MMCR_GPIO057_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO057_PIN_CONTROL_2))
-
-#define ADDR_GPIO060_PIN_CONTROL_2                               0x400815C0
-#define MMCR_GPIO060_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO060_PIN_CONTROL_2))
-
-#define ADDR_GPIO061_PIN_CONTROL_2                               0x400815C4
-#define MMCR_GPIO061_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO061_PIN_CONTROL_2))
-
-#define ADDR_GPIO062_PIN_CONTROL_2                               0x400815C8
-#define MMCR_GPIO062_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO062_PIN_CONTROL_2))
-
-#define ADDR_GPIO063_PIN_CONTROL_2                               0x400815CC
-#define MMCR_GPIO063_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO063_PIN_CONTROL_2))
-
-#define ADDR_GPIO064_PIN_CONTROL_2                               0x400815D0
-#define MMCR_GPIO064_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO064_PIN_CONTROL_2))
-
-#define ADDR_GPIO065_PIN_CONTROL_2                               0x400815D4
-#define MMCR_GPIO065_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO065_PIN_CONTROL_2))
-
-#define ADDR_GPIO066_PIN_CONTROL_2                               0x400815D8
-#define MMCR_GPIO066_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO066_PIN_CONTROL_2))
-
-#define ADDR_GPIO067_PIN_CONTROL_2                               0x400815DC
-#define MMCR_GPIO067_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO067_PIN_CONTROL_2))
-
-#define ADDR_GPIO100_PIN_CONTROL_2                               0x400815E0
-#define MMCR_GPIO100_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO100_PIN_CONTROL_2))
-
-#define ADDR_GPIO101_PIN_CONTROL_2                               0x400815E4
-#define MMCR_GPIO101_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO101_PIN_CONTROL_2))
-
-#define ADDR_GPIO102_PIN_CONTROL_2                               0x400815E8
-#define MMCR_GPIO102_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO102_PIN_CONTROL_2))
-
-#define ADDR_GPIO103_PIN_CONTROL_2                               0x400815EC
-#define MMCR_GPIO103_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO103_PIN_CONTROL_2))
-
-#define ADDR_GPIO104_PIN_CONTROL_2                               0x400815F0
-#define MMCR_GPIO104_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO104_PIN_CONTROL_2))
-
-#define ADDR_GPIO105_PIN_CONTROL_2                               0x400815F4
-#define MMCR_GPIO105_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO105_PIN_CONTROL_2))
-
-#define ADDR_GPIO106_PIN_CONTROL_2                               0x400815F8
-#define MMCR_GPIO106_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO106_PIN_CONTROL_2))
-
-#define ADDR_GPIO107_PIN_CONTROL_2                               0x400815FC
-#define MMCR_GPIO107_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO107_PIN_CONTROL_2))
-
-#define ADDR_GPIO110_PIN_CONTROL_2                               0x40081600
-#define MMCR_GPIO110_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO110_PIN_CONTROL_2))
-
-#define ADDR_GPIO111_PIN_CONTROL_2                               0x40081604
-#define MMCR_GPIO111_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO111_PIN_CONTROL_2))
-
-#define ADDR_GPIO112_PIN_CONTROL_2                               0x40081608
-#define MMCR_GPIO112_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO112_PIN_CONTROL_2))
-
-#define ADDR_GPIO113_PIN_CONTROL_2                               0x4008160C
-#define MMCR_GPIO113_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO113_PIN_CONTROL_2))
-
-#define ADDR_GPIO114_PIN_CONTROL_2                               0x40081610
-#define MMCR_GPIO114_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO114_PIN_CONTROL_2))
-
-#define ADDR_GPIO115_PIN_CONTROL_2                               0x40081614
-#define MMCR_GPIO115_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO115_PIN_CONTROL_2))
-
-#define ADDR_GPIO116_PIN_CONTROL_2                               0x40081618
-#define MMCR_GPIO116_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO116_PIN_CONTROL_2))
-
-#define ADDR_GPIO117_PIN_CONTROL_2                               0x4008161C
-#define MMCR_GPIO117_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO117_PIN_CONTROL_2))
-
-#define ADDR_GPIO120_PIN_CONTROL_2                               0x40081620
-#define MMCR_GPIO120_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO120_PIN_CONTROL_2))
-
-#define ADDR_GPIO121_PIN_CONTROL_2                               0x40081624
-#define MMCR_GPIO121_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO121_PIN_CONTROL_2))
-
-#define ADDR_GPIO122_PIN_CONTROL_2                               0x40081628
-#define MMCR_GPIO122_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO122_PIN_CONTROL_2))
-
-#define ADDR_GPIO123_PIN_CONTROL_2                               0x4008162C
-#define MMCR_GPIO123_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO123_PIN_CONTROL_2))
-
-#define ADDR_GPIO124_PIN_CONTROL_2                               0x40081630
-#define MMCR_GPIO124_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO124_PIN_CONTROL_2))
-
-#define ADDR_GPIO125_PIN_CONTROL_2                               0x40081634
-#define MMCR_GPIO125_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO125_PIN_CONTROL_2))
-
-#define ADDR_GPIO126_PIN_CONTROL_2                               0x40081638
-#define MMCR_GPIO126_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO126_PIN_CONTROL_2))
-
-#define ADDR_GPIO127_PIN_CONTROL_2                               0x4008163C
-#define MMCR_GPIO127_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO127_PIN_CONTROL_2))
-
-#define ADDR_GPIO130_PIN_CONTROL_2                               0x40081640
-#define MMCR_GPIO130_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO130_PIN_CONTROL_2))
-
-#define ADDR_GPIO131_PIN_CONTROL_2                               0x40081644
-#define MMCR_GPIO131_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO131_PIN_CONTROL_2))
-
-#define ADDR_GPIO132_PIN_CONTROL_2                               0x40081648
-#define MMCR_GPIO132_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO132_PIN_CONTROL_2))
-
-#define ADDR_GPIO133_PIN_CONTROL_2                               0x4008164C
-#define MMCR_GPIO133_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO133_PIN_CONTROL_2))
-
-#define ADDR_GPIO134_PIN_CONTROL_2                               0x40081650
-#define MMCR_GPIO134_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO134_PIN_CONTROL_2))
-
-#define ADDR_GPIO135_PIN_CONTROL_2                               0x40081654
-#define MMCR_GPIO135_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO135_PIN_CONTROL_2))
-
-#define ADDR_GPIO136_PIN_CONTROL_2                               0x40081658
-#define MMCR_GPIO136_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO136_PIN_CONTROL_2))
-
-#define ADDR_GPIO140_PIN_CONTROL_2                               0x40081660
-#define MMCR_GPIO140_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO140_PIN_CONTROL_2))
-
-#define ADDR_GPIO141_PIN_CONTROL_2                               0x40081664
-#define MMCR_GPIO141_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO141_PIN_CONTROL_2))
-
-#define ADDR_GPIO142_PIN_CONTROL_2                               0x40081668
-#define MMCR_GPIO142_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO142_PIN_CONTROL_2))
-
-#define ADDR_GPIO143_PIN_CONTROL_2                               0x4008166C
-#define MMCR_GPIO143_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO143_PIN_CONTROL_2))
-
-#define ADDR_GPIO144_PIN_CONTROL_2                               0x40081670
-#define MMCR_GPIO144_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO144_PIN_CONTROL_2))
-
-#define ADDR_GPIO145_PIN_CONTROL_2                               0x40081674
-#define MMCR_GPIO145_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO145_PIN_CONTROL_2))
-
-#define ADDR_GPIO146_PIN_CONTROL_2                               0x40081678
-#define MMCR_GPIO146_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO146_PIN_CONTROL_2))
-
-#define ADDR_GPIO147_PIN_CONTROL_2                               0x4008167C
-#define MMCR_GPIO147_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO147_PIN_CONTROL_2))
-
-#define ADDR_GPIO150_PIN_CONTROL_2                               0x40081680
-#define MMCR_GPIO150_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO150_PIN_CONTROL_2))
-
-#define ADDR_GPIO151_PIN_CONTROL_2                               0x40081684
-#define MMCR_GPIO151_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO151_PIN_CONTROL_2))
-
-#define ADDR_GPIO152_PIN_CONTROL_2                               0x40081688
-#define MMCR_GPIO152_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO152_PIN_CONTROL_2))
-
-#define ADDR_GPIO153_PIN_CONTROL_2                               0x4008168C
-#define MMCR_GPIO153_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO153_PIN_CONTROL_2))
-
-#define ADDR_GPIO154_PIN_CONTROL_2                               0x40081690
-#define MMCR_GPIO154_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO154_PIN_CONTROL_2))
-
-#define ADDR_GPIO155_PIN_CONTROL_2                               0x40081694
-#define MMCR_GPIO155_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO155_PIN_CONTROL_2))
-
-#define ADDR_GPIO156_PIN_CONTROL_2                               0x40081698
-#define MMCR_GPIO156_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO156_PIN_CONTROL_2))
-
-#define ADDR_GPIO157_PIN_CONTROL_2                               0x4008169C
-#define MMCR_GPIO157_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO157_PIN_CONTROL_2))
-
-#define ADDR_GPIO160_PIN_CONTROL_2                               0x400816A0
-#define MMCR_GPIO160_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO160_PIN_CONTROL_2))
-
-#define ADDR_GPIO161_PIN_CONTROL_2                               0x400816A4
-#define MMCR_GPIO161_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO161_PIN_CONTROL_2))
-
-#define ADDR_GPIO162_PIN_CONTROL_2                               0x400816A8
-#define MMCR_GPIO162_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO162_PIN_CONTROL_2))
-
-#define ADDR_GPIO163_PIN_CONTROL_2                               0x400816AC
-#define MMCR_GPIO163_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO163_PIN_CONTROL_2))
-
-#define ADDR_GPIO164_PIN_CONTROL_2                               0x400816B0
-#define MMCR_GPIO164_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO164_PIN_CONTROL_2))
-
-#define ADDR_GPIO165_PIN_CONTROL_2                               0x400816B4
-#define MMCR_GPIO165_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO165_PIN_CONTROL_2))
-
-#define ADDR_GPIO200_PIN_CONTROL_2                               0x40081720
-#define MMCR_GPIO200_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO200_PIN_CONTROL_2))
-
-#define ADDR_GPIO201_PIN_CONTROL_2                               0x40081724
-#define MMCR_GPIO201_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO201_PIN_CONTROL_2))
-
-#define ADDR_GPIO202_PIN_CONTROL_2                               0x40081728
-#define MMCR_GPIO202_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO202_PIN_CONTROL_2))
-
-#define ADDR_GPIO203_PIN_CONTROL_2                               0x4008172C
-#define MMCR_GPIO203_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO203_PIN_CONTROL_2))
-
-#define ADDR_GPIO204_PIN_CONTROL_2                               0x40081730
-#define MMCR_GPIO204_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO204_PIN_CONTROL_2))
-
-#define ADDR_GPIO206_PIN_CONTROL_2                               0x40081738
-#define MMCR_GPIO206_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO206_PIN_CONTROL_2))
-
-#define ADDR_GPIO210_PIN_CONTROL_2                               0x40081740
-#define MMCR_GPIO210_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO210_PIN_CONTROL_2))
-
-#define ADDR_GPIO211_PIN_CONTROL_2                               0x40081744
-#define MMCR_GPIO211_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO211_PIN_CONTROL_2))
-
-#define ADDR_GPIO212_PIN_CONTROL_2                               0x40081748
-#define MMCR_GPIO212_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO212_PIN_CONTROL_2))
-
-#define ADDR_GPIO213_PIN_CONTROL_2                               0x4008174C
-#define MMCR_GPIO213_PIN_CONTROL_2                               (*(VUINT32 *)(ADDR_GPIO213_PIN_CONTROL_2))
-
-/***************************************************************
-*                            DMA
-***************************************************************/
-#define ADDR_DMA_MAIN_CONTROL                                    0x40002400
-#define MMCR_DMA_MAIN_CONTROL                                    (*(VUINT8 *)(ADDR_DMA_MAIN_CONTROL))
-
-#define ADDR_DMA_AFIFO_DATA                                      0x40002404
-#define MMCR_DMA_AFIFO_DATA                                      (*(VUINT32 *)(ADDR_DMA_AFIFO_DATA))
-
-#define ADDR_DMA_MAIN_DEBUG                                      0x40002408
-#define MMCR_DMA_MAIN_DEBUG                                      (*(VUINT8 *)(ADDR_DMA_MAIN_DEBUG))
-
-#define ADDR_DMA_CH0_ACTIVATE                                    0x40002410
-#define MMCR_DMA_CH0_ACTIVATE                                    (*(VUINT32 *)(ADDR_DMA_CH0_ACTIVATE))
-
-#define ADDR_DMA_CH0_MEMORY_START_ADDRESS                        0x40002414
-#define MMCR_DMA_CH0_MEMORY_START_ADDRESS                        (*(VUINT32 *)(ADDR_DMA_CH0_MEMORY_START_ADDRESS))
-
-#define ADDR_DMA_CH0_MEMORY_END_ADDRESS                          0x40002418
-#define MMCR_DMA_CH0_MEMORY_END_ADDRESS                          (*(VUINT32 *)(ADDR_DMA_CH0_MEMORY_END_ADDRESS))
-
-#define ADDR_DMA_CH0_AHB_ADDRESS                                 0x4000241C
-#define MMCR_DMA_CH0_AHB_ADDRESS                                 (*(VUINT32 *)(ADDR_DMA_CH0_AHB_ADDRESS))
-
-#define ADDR_DMA_CH0_CONTROL                                     0x40002420
-#define MMCR_DMA_CH0_CONTROL                                     (*(VUINT32 *)(ADDR_DMA_CH0_CONTROL))
-
-#define ADDR_DMA_CH0_CHANNEL_INTERRUPT_STATUS                    0x40002424
-#define MMCR_DMA_CH0_CHANNEL_INTERRUPT_STATUS                    (*(VUINT32 *)(ADDR_DMA_CH0_CHANNEL_INTERRUPT_STATUS))
-
-#define ADDR_DMA_CH0_CHANNEL_INTERRUPT_ENABLE                    0x40002428
-#define MMCR_DMA_CH0_CHANNEL_INTERRUPT_ENABLE                    (*(VUINT32 *)(ADDR_DMA_CH0_CHANNEL_INTERRUPT_ENABLE))
-
-#define ADDR_DMA_CH0_TEST                                        0x4000242C
-#define MMCR_DMA_CH0_TEST                                        (*(VUINT32 *)(ADDR_DMA_CH0_TEST))
-
-#define ADDR_DMA_CH1_ACTIVATE                                    0x40002430
-#define MMCR_DMA_CH1_ACTIVATE                                    (*(VUINT32 *)(ADDR_DMA_CH1_ACTIVATE))
-
-#define ADDR_DMA_CH1_MEMORY_START_ADDRESS                        0x40002434
-#define MMCR_DMA_CH1_MEMORY_START_ADDRESS                        (*(VUINT32 *)(ADDR_DMA_CH1_MEMORY_START_ADDRESS))
-
-#define ADDR_DMA_CH1_MEMORY_END_ADDRESS                          0x40002438
-#define MMCR_DMA_CH1_MEMORY_END_ADDRESS                          (*(VUINT32 *)(ADDR_DMA_CH1_MEMORY_END_ADDRESS))
-
-#define ADDR_DMA_CH1_AHB_ADDRESS                                 0x4000243C
-#define MMCR_DMA_CH1_AHB_ADDRESS                                 (*(VUINT32 *)(ADDR_DMA_CH1_AHB_ADDRESS))
-
-#define ADDR_DMA_CH1_CONTROL                                     0x40002440
-#define MMCR_DMA_CH1_CONTROL                                     (*(VUINT32 *)(ADDR_DMA_CH1_CONTROL))
-
-#define ADDR_DMA_CH1_CHANNEL_INTERRUPT_STATUS                    0x40002444
-#define MMCR_DMA_CH1_CHANNEL_INTERRUPT_STATUS                    (*(VUINT32 *)(ADDR_DMA_CH1_CHANNEL_INTERRUPT_STATUS))
-
-#define ADDR_DMA_CH1_CHANNEL_INTERRUPT_ENABLE                    0x40002448
-#define MMCR_DMA_CH1_CHANNEL_INTERRUPT_ENABLE                    (*(VUINT32 *)(ADDR_DMA_CH1_CHANNEL_INTERRUPT_ENABLE))
-
-#define ADDR_DMA_CH1_TEST                                        0x4000244C
-#define MMCR_DMA_CH1_TEST                                        (*(VUINT32 *)(ADDR_DMA_CH1_TEST))
-
-#define ADDR_DMA_CH10_ACTIVATE                                   0x40002550
-#define MMCR_DMA_CH10_ACTIVATE                                   (*(VUINT32 *)(ADDR_DMA_CH10_ACTIVATE))
-
-#define ADDR_DMA_CH10_MEMORY_START_ADDRESS                       0x40002554
-#define MMCR_DMA_CH10_MEMORY_START_ADDRESS                       (*(VUINT32 *)(ADDR_DMA_CH10_MEMORY_START_ADDRESS))
-
-#define ADDR_DMA_CH10_MEMORY_END_ADDRESS                         0x40002558
-#define MMCR_DMA_CH10_MEMORY_END_ADDRESS                         (*(VUINT32 *)(ADDR_DMA_CH10_MEMORY_END_ADDRESS))
-
-#define ADDR_DMA_CH10_AHB_ADDRESS                                0x4000255C
-#define MMCR_DMA_CH10_AHB_ADDRESS                                (*(VUINT32 *)(ADDR_DMA_CH10_AHB_ADDRESS))
-
-#define ADDR_DMA_CH10_CONTROL                                    0x40002560
-#define MMCR_DMA_CH10_CONTROL                                    (*(VUINT32 *)(ADDR_DMA_CH10_CONTROL))
-
-#define ADDR_DMA_CH10_CHANNEL_INTERRUPT_STATUS                   0x40002564
-#define MMCR_DMA_CH10_CHANNEL_INTERRUPT_STATUS                   (*(VUINT32 *)(ADDR_DMA_CH10_CHANNEL_INTERRUPT_STATUS))
-
-#define ADDR_DMA_CH10_CHANNEL_INTERRUPT_ENABLE                   0x40002568
-#define MMCR_DMA_CH10_CHANNEL_INTERRUPT_ENABLE                   (*(VUINT32 *)(ADDR_DMA_CH10_CHANNEL_INTERRUPT_ENABLE))
-
-#define ADDR_DMA_CH10_TEST                                       0x4000256C
-#define MMCR_DMA_CH10_TEST                                       (*(VUINT32 *)(ADDR_DMA_CH10_TEST))
-
-#define ADDR_DMA_CH11_ACTIVATE                                   0x40002570
-#define MMCR_DMA_CH11_ACTIVATE                                   (*(VUINT32 *)(ADDR_DMA_CH11_ACTIVATE))
-
-#define ADDR_DMA_CH11_MEMORY_START_ADDRESS                       0x40002574
-#define MMCR_DMA_CH11_MEMORY_START_ADDRESS                       (*(VUINT32 *)(ADDR_DMA_CH11_MEMORY_START_ADDRESS))
-
-#define ADDR_DMA_CH11_MEMORY_END_ADDRESS                         0x40002578
-#define MMCR_DMA_CH11_MEMORY_END_ADDRESS                         (*(VUINT32 *)(ADDR_DMA_CH11_MEMORY_END_ADDRESS))
-
-#define ADDR_DMA_CH11_AHB_ADDRESS                                0x4000257C
-#define MMCR_DMA_CH11_AHB_ADDRESS                                (*(VUINT32 *)(ADDR_DMA_CH11_AHB_ADDRESS))
-
-#define ADDR_DMA_CH11_CONTROL                                    0x40002580
-#define MMCR_DMA_CH11_CONTROL                                    (*(VUINT32 *)(ADDR_DMA_CH11_CONTROL))
-
-#define ADDR_DMA_CH11_CHANNEL_INTERRUPT_STATUS                   0x40002584
-#define MMCR_DMA_CH11_CHANNEL_INTERRUPT_STATUS                   (*(VUINT32 *)(ADDR_DMA_CH11_CHANNEL_INTERRUPT_STATUS))
-
-#define ADDR_DMA_CH11_CHANNEL_INTERRUPT_ENABLE                   0x40002588
-#define MMCR_DMA_CH11_CHANNEL_INTERRUPT_ENABLE                   (*(VUINT32 *)(ADDR_DMA_CH11_CHANNEL_INTERRUPT_ENABLE))
-
-#define ADDR_DMA_CH11_TEST                                       0x4000258C
-#define MMCR_DMA_CH11_TEST                                       (*(VUINT32 *)(ADDR_DMA_CH11_TEST))
-
-#define ADDR_DMA_CH2_ACTIVATE                                    0x40002450
-#define MMCR_DMA_CH2_ACTIVATE                                    (*(VUINT32 *)(ADDR_DMA_CH2_ACTIVATE))
-
-#define ADDR_DMA_CH2_MEMORY_START_ADDRESS                        0x40002454
-#define MMCR_DMA_CH2_MEMORY_START_ADDRESS                        (*(VUINT32 *)(ADDR_DMA_CH2_MEMORY_START_ADDRESS))
-
-#define ADDR_DMA_CH2_MEMORY_END_ADDRESS                          0x40002458
-#define MMCR_DMA_CH2_MEMORY_END_ADDRESS                          (*(VUINT32 *)(ADDR_DMA_CH2_MEMORY_END_ADDRESS))
-
-#define ADDR_DMA_CH2_AHB_ADDRESS                                 0x4000245C
-#define MMCR_DMA_CH2_AHB_ADDRESS                                 (*(VUINT32 *)(ADDR_DMA_CH2_AHB_ADDRESS))
-
-#define ADDR_DMA_CH2_CONTROL                                     0x40002460
-#define MMCR_DMA_CH2_CONTROL                                     (*(VUINT32 *)(ADDR_DMA_CH2_CONTROL))
-
-#define ADDR_DMA_CH2_CHANNEL_INTERRUPT_STATUS                    0x40002464
-#define MMCR_DMA_CH2_CHANNEL_INTERRUPT_STATUS                    (*(VUINT32 *)(ADDR_DMA_CH2_CHANNEL_INTERRUPT_STATUS))
-
-#define ADDR_DMA_CH2_CHANNEL_INTERRUPT_ENABLE                    0x40002468
-#define MMCR_DMA_CH2_CHANNEL_INTERRUPT_ENABLE                    (*(VUINT32 *)(ADDR_DMA_CH2_CHANNEL_INTERRUPT_ENABLE))
-
-#define ADDR_DMA_CH2_TEST                                        0x4000246C
-#define MMCR_DMA_CH2_TEST                                        (*(VUINT32 *)(ADDR_DMA_CH2_TEST))
-
-#define ADDR_DMA_CH3_ACTIVATE                                    0x40002470
-#define MMCR_DMA_CH3_ACTIVATE                                    (*(VUINT32 *)(ADDR_DMA_CH3_ACTIVATE))
-
-#define ADDR_DMA_CH3_MEMORY_START_ADDRESS                        0x40002474
-#define MMCR_DMA_CH3_MEMORY_START_ADDRESS                        (*(VUINT32 *)(ADDR_DMA_CH3_MEMORY_START_ADDRESS))
-
-#define ADDR_DMA_CH3_MEMORY_END_ADDRESS                          0x40002478
-#define MMCR_DMA_CH3_MEMORY_END_ADDRESS                          (*(VUINT32 *)(ADDR_DMA_CH3_MEMORY_END_ADDRESS))
-
-#define ADDR_DMA_CH3_AHB_ADDRESS                                 0x4000247C
-#define MMCR_DMA_CH3_AHB_ADDRESS                                 (*(VUINT32 *)(ADDR_DMA_CH3_AHB_ADDRESS))
-
-#define ADDR_DMA_CH3_CONTROL                                     0x40002480
-#define MMCR_DMA_CH3_CONTROL                                     (*(VUINT32 *)(ADDR_DMA_CH3_CONTROL))
-
-#define ADDR_DMA_CH3_CHANNEL_INTERRUPT_STATUS                    0x40002484
-#define MMCR_DMA_CH3_CHANNEL_INTERRUPT_STATUS                    (*(VUINT32 *)(ADDR_DMA_CH3_CHANNEL_INTERRUPT_STATUS))
-
-#define ADDR_DMA_CH3_CHANNEL_INTERRUPT_ENABLE                    0x40002488
-#define MMCR_DMA_CH3_CHANNEL_INTERRUPT_ENABLE                    (*(VUINT32 *)(ADDR_DMA_CH3_CHANNEL_INTERRUPT_ENABLE))
-
-#define ADDR_DMA_CH3_TEST                                        0x4000248C
-#define MMCR_DMA_CH3_TEST                                        (*(VUINT32 *)(ADDR_DMA_CH3_TEST))
-
-#define ADDR_DMA_CH4_ACTIVATE                                    0x40002490
-#define MMCR_DMA_CH4_ACTIVATE                                    (*(VUINT32 *)(ADDR_DMA_CH4_ACTIVATE))
-
-#define ADDR_DMA_CH4_MEMORY_START_ADDRESS                        0x40002494
-#define MMCR_DMA_CH4_MEMORY_START_ADDRESS                        (*(VUINT32 *)(ADDR_DMA_CH4_MEMORY_START_ADDRESS))
-
-#define ADDR_DMA_CH4_MEMORY_END_ADDRESS                          0x40002498
-#define MMCR_DMA_CH4_MEMORY_END_ADDRESS                          (*(VUINT32 *)(ADDR_DMA_CH4_MEMORY_END_ADDRESS))
-
-#define ADDR_DMA_CH4_AHB_ADDRESS                                 0x4000249C
-#define MMCR_DMA_CH4_AHB_ADDRESS                                 (*(VUINT32 *)(ADDR_DMA_CH4_AHB_ADDRESS))
-
-#define ADDR_DMA_CH4_CONTROL                                     0x400024A0
-#define MMCR_DMA_CH4_CONTROL                                     (*(VUINT32 *)(ADDR_DMA_CH4_CONTROL))
-
-#define ADDR_DMA_CH4_CHANNEL_INTERRUPT_STATUS                    0x400024A4
-#define MMCR_DMA_CH4_CHANNEL_INTERRUPT_STATUS                    (*(VUINT32 *)(ADDR_DMA_CH4_CHANNEL_INTERRUPT_STATUS))
-
-#define ADDR_DMA_CH4_CHANNEL_INTERRUPT_ENABLE                    0x400024A8
-#define MMCR_DMA_CH4_CHANNEL_INTERRUPT_ENABLE                    (*(VUINT32 *)(ADDR_DMA_CH4_CHANNEL_INTERRUPT_ENABLE))
-
-#define ADDR_DMA_CH4_TEST                                        0x400024AC
-#define MMCR_DMA_CH4_TEST                                        (*(VUINT32 *)(ADDR_DMA_CH4_TEST))
-
-#define ADDR_DMA_CH5_ACTIVATE                                    0x400024B0
-#define MMCR_DMA_CH5_ACTIVATE                                    (*(VUINT32 *)(ADDR_DMA_CH5_ACTIVATE))
-
-#define ADDR_DMA_CH5_MEMORY_START_ADDRESS                        0x400024B4
-#define MMCR_DMA_CH5_MEMORY_START_ADDRESS                        (*(VUINT32 *)(ADDR_DMA_CH5_MEMORY_START_ADDRESS))
-
-#define ADDR_DMA_CH5_MEMORY_END_ADDRESS                          0x400024B8
-#define MMCR_DMA_CH5_MEMORY_END_ADDRESS                          (*(VUINT32 *)(ADDR_DMA_CH5_MEMORY_END_ADDRESS))
-
-#define ADDR_DMA_CH5_AHB_ADDRESS                                 0x400024BC
-#define MMCR_DMA_CH5_AHB_ADDRESS                                 (*(VUINT32 *)(ADDR_DMA_CH5_AHB_ADDRESS))
-
-#define ADDR_DMA_CH5_CONTROL                                     0x400024C0
-#define MMCR_DMA_CH5_CONTROL                                     (*(VUINT32 *)(ADDR_DMA_CH5_CONTROL))
-
-#define ADDR_DMA_CH5_CHANNEL_INTERRUPT_STATUS                    0x400024C4
-#define MMCR_DMA_CH5_CHANNEL_INTERRUPT_STATUS                    (*(VUINT32 *)(ADDR_DMA_CH5_CHANNEL_INTERRUPT_STATUS))
-
-#define ADDR_DMA_CH5_CHANNEL_INTERRUPT_ENABLE                    0x400024C8
-#define MMCR_DMA_CH5_CHANNEL_INTERRUPT_ENABLE                    (*(VUINT32 *)(ADDR_DMA_CH5_CHANNEL_INTERRUPT_ENABLE))
-
-#define ADDR_DMA_CH5_TEST                                        0x400024CC
-#define MMCR_DMA_CH5_TEST                                        (*(VUINT32 *)(ADDR_DMA_CH5_TEST))
-
-#define ADDR_DMA_CH6_ACTIVATE                                    0x400024D0
-#define MMCR_DMA_CH6_ACTIVATE                                    (*(VUINT32 *)(ADDR_DMA_CH6_ACTIVATE))
-
-#define ADDR_DMA_CH6_MEMORY_START_ADDRESS                        0x400024D4
-#define MMCR_DMA_CH6_MEMORY_START_ADDRESS                        (*(VUINT32 *)(ADDR_DMA_CH6_MEMORY_START_ADDRESS))
-
-#define ADDR_DMA_CH6_MEMORY_END_ADDRESS                          0x400024D8
-#define MMCR_DMA_CH6_MEMORY_END_ADDRESS                          (*(VUINT32 *)(ADDR_DMA_CH6_MEMORY_END_ADDRESS))
-
-#define ADDR_DMA_CH6_AHB_ADDRESS                                 0x400024DC
-#define MMCR_DMA_CH6_AHB_ADDRESS                                 (*(VUINT32 *)(ADDR_DMA_CH6_AHB_ADDRESS))
-
-#define ADDR_DMA_CH6_CONTROL                                     0x4.00E+05
-#define MMCR_DMA_CH6_CONTROL                                     (*(VUINT32 *)(ADDR_DMA_CH6_CONTROL))
-
-#define ADDR_DMA_CH6_CHANNEL_INTERRUPT_STATUS                    0x4.00E+09
-#define MMCR_DMA_CH6_CHANNEL_INTERRUPT_STATUS                    (*(VUINT32 *)(ADDR_DMA_CH6_CHANNEL_INTERRUPT_STATUS))
-
-#define ADDR_DMA_CH6_CHANNEL_INTERRUPT_ENABLE                    0x4.00E+13
-#define MMCR_DMA_CH6_CHANNEL_INTERRUPT_ENABLE                    (*(VUINT32 *)(ADDR_DMA_CH6_CHANNEL_INTERRUPT_ENABLE))
-
-#define ADDR_DMA_CH6_TEST                                        0x400024EC
-#define MMCR_DMA_CH6_TEST                                        (*(VUINT32 *)(ADDR_DMA_CH6_TEST))
-
-#define ADDR_DMA_CH7_ACTIVATE                                    0x400024F0
-#define MMCR_DMA_CH7_ACTIVATE                                    (*(VUINT32 *)(ADDR_DMA_CH7_ACTIVATE))
-
-#define ADDR_DMA_CH7_MEMORY_START_ADDRESS                        0x400024F4
-#define MMCR_DMA_CH7_MEMORY_START_ADDRESS                        (*(VUINT32 *)(ADDR_DMA_CH7_MEMORY_START_ADDRESS))
-
-#define ADDR_DMA_CH7_MEMORY_END_ADDRESS                          0x400024F8
-#define MMCR_DMA_CH7_MEMORY_END_ADDRESS                          (*(VUINT32 *)(ADDR_DMA_CH7_MEMORY_END_ADDRESS))
-
-#define ADDR_DMA_CH7_AHB_ADDRESS                                 0x400024FC
-#define MMCR_DMA_CH7_AHB_ADDRESS                                 (*(VUINT32 *)(ADDR_DMA_CH7_AHB_ADDRESS))
-
-#define ADDR_DMA_CH7_CONTROL                                     0x40002500
-#define MMCR_DMA_CH7_CONTROL                                     (*(VUINT32 *)(ADDR_DMA_CH7_CONTROL))
-
-#define ADDR_DMA_CH7_CHANNEL_INTERRUPT_STATUS                    0x40002504
-#define MMCR_DMA_CH7_CHANNEL_INTERRUPT_STATUS                    (*(VUINT32 *)(ADDR_DMA_CH7_CHANNEL_INTERRUPT_STATUS))
-
-#define ADDR_DMA_CH7_CHANNEL_INTERRUPT_ENABLE                    0x40002508
-#define MMCR_DMA_CH7_CHANNEL_INTERRUPT_ENABLE                    (*(VUINT32 *)(ADDR_DMA_CH7_CHANNEL_INTERRUPT_ENABLE))
-
-#define ADDR_DMA_CH7_TEST                                        0x4000250C
-#define MMCR_DMA_CH7_TEST                                        (*(VUINT32 *)(ADDR_DMA_CH7_TEST))
-
-#define ADDR_DMA_CH8_ACTIVATE                                    0x40002510
-#define MMCR_DMA_CH8_ACTIVATE                                    (*(VUINT32 *)(ADDR_DMA_CH8_ACTIVATE))
-
-#define ADDR_DMA_CH8_MEMORY_START_ADDRESS                        0x40002514
-#define MMCR_DMA_CH8_MEMORY_START_ADDRESS                        (*(VUINT32 *)(ADDR_DMA_CH8_MEMORY_START_ADDRESS))
-
-#define ADDR_DMA_CH8_MEMORY_END_ADDRESS                          0x40002518
-#define MMCR_DMA_CH8_MEMORY_END_ADDRESS                          (*(VUINT32 *)(ADDR_DMA_CH8_MEMORY_END_ADDRESS))
-
-#define ADDR_DMA_CH8_AHB_ADDRESS                                 0x4000251C
-#define MMCR_DMA_CH8_AHB_ADDRESS                                 (*(VUINT32 *)(ADDR_DMA_CH8_AHB_ADDRESS))
-
-#define ADDR_DMA_CH8_CONTROL                                     0x40002520
-#define MMCR_DMA_CH8_CONTROL                                     (*(VUINT32 *)(ADDR_DMA_CH8_CONTROL))
-
-#define ADDR_DMA_CH8_CHANNEL_INTERRUPT_STATUS                    0x40002524
-#define MMCR_DMA_CH8_CHANNEL_INTERRUPT_STATUS                    (*(VUINT32 *)(ADDR_DMA_CH8_CHANNEL_INTERRUPT_STATUS))
-
-#define ADDR_DMA_CH8_CHANNEL_INTERRUPT_ENABLE                    0x40002528
-#define MMCR_DMA_CH8_CHANNEL_INTERRUPT_ENABLE                    (*(VUINT32 *)(ADDR_DMA_CH8_CHANNEL_INTERRUPT_ENABLE))
-
-#define ADDR_DMA_CH8_TEST                                        0x4000252C
-#define MMCR_DMA_CH8_TEST                                        (*(VUINT32 *)(ADDR_DMA_CH8_TEST))
-
-#define ADDR_DMA_CH9_ACTIVATE                                    0x40002530
-#define MMCR_DMA_CH9_ACTIVATE                                    (*(VUINT32 *)(ADDR_DMA_CH9_ACTIVATE))
-
-#define ADDR_DMA_CH9_MEMORY_START_ADDRESS                        0x40002534
-#define MMCR_DMA_CH9_MEMORY_START_ADDRESS                        (*(VUINT32 *)(ADDR_DMA_CH9_MEMORY_START_ADDRESS))
-
-#define ADDR_DMA_CH9_MEMORY_END_ADDRESS                          0x40002538
-#define MMCR_DMA_CH9_MEMORY_END_ADDRESS                          (*(VUINT32 *)(ADDR_DMA_CH9_MEMORY_END_ADDRESS))
-
-#define ADDR_DMA_CH9_AHB_ADDRESS                                 0x4000253C
-#define MMCR_DMA_CH9_AHB_ADDRESS                                 (*(VUINT32 *)(ADDR_DMA_CH9_AHB_ADDRESS))
-
-#define ADDR_DMA_CH9_CONTROL                                     0x40002540
-#define MMCR_DMA_CH9_CONTROL                                     (*(VUINT32 *)(ADDR_DMA_CH9_CONTROL))
-
-#define ADDR_DMA_CH9_CHANNEL_INTERRUPT_STATUS                    0x40002544
-#define MMCR_DMA_CH9_CHANNEL_INTERRUPT_STATUS                    (*(VUINT32 *)(ADDR_DMA_CH9_CHANNEL_INTERRUPT_STATUS))
-
-#define ADDR_DMA_CH9_CHANNEL_INTERRUPT_ENABLE                    0x40002548
-#define MMCR_DMA_CH9_CHANNEL_INTERRUPT_ENABLE                    (*(VUINT32 *)(ADDR_DMA_CH9_CHANNEL_INTERRUPT_ENABLE))
-
-#define ADDR_DMA_CH9_TEST                                        0x4000254C
-#define MMCR_DMA_CH9_TEST                                        (*(VUINT32 *)(ADDR_DMA_CH9_TEST))
-
-#endif /*SMSCMMCR_H_*/
diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/basic_timer/btimer.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/basic_timer/btimer.h
index 129f5f2f5..d2b6cdf80 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/basic_timer/btimer.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/basic_timer/btimer.h
@@ -1,409 +1,409 @@
-/*****************************************************************************
-* � 2015 Microchip Technology Inc. and its subsidiaries.
-* You may use this software and any derivatives exclusively with
-* Microchip products.
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
-* OF THESE TERMS.
-******************************************************************************
-
-Version Control Information (Perforce)
-******************************************************************************
-$Revision: #1 $ 
-$DateTime: 2015/11/22 06:01:28 $ 
-$Author: amohandas $
-Last Change:	Updated with unit testing feedbacks
-******************************************************************************/
-/** @file btimer.h
-* \brief Basic Timer Peripheral Header file
-* \author jvasanth
-* 
-* This file is the header file for Basic Timer Peripheral 
-******************************************************************************/
-
-/** @defgroup Basic_Timer
- *  @{
- */
-
-#ifndef _BTIMER_H
-#define _BTIMER_H
-
-/******************************************************************************/
-/**  Logical Timer ID for APIs.
- * This is the timer IDs passed to Basic Timer API function calls 
- *******************************************************************************/
-enum _PID_BTIMER_
-{
-	PID_BTIMER_0,
-	PID_BTIMER_1,
-	PID_BTIMER_2,
-	PID_BTIMER_3,
-	PID_BTIMER_4,
-	PID_BTIMER_5,
-	PID_BTIMER_MAX	
-};
-
-/* ---------------------------------------------------------------------- */
-/*                    Logical flags for Timer Control                     */
-/* ---------------------------------------------------------------------- */
-//This is for tmr_cntl parameter in btimer_init function
-#define BTIMER_AUTO_RESTART     			     (0x08u)
-#define BTIMER_ONE_SHOT         			     (0u)
-#define BTIMER_COUNT_UP         			     (0x04u)
-#define BTIMER_COUNT_DOWN       			     (0u)
-#define BTIMER_INT_EN           			     (0x01u)
-#define BTIMER_NO_INT           			     (0u)
-/* ---------------------------------------------------------------------- */
-
-
-//Timer Block Hardware Bits and Masks
-#define BTIMER_CNTL_HALT                   (0x80UL)
-#define BTIMER_CNTL_RELOAD                 (0x40UL)
-#define BTIMER_CNTL_START                  (0x20UL)
-#define BTIMER_CNTL_SOFT_RESET             (0x10UL)
-#define BTIMER_CNTL_AUTO_RESTART           (0x08UL)
-#define BTIMER_CNTL_COUNT_UP               (0x04UL)
-#define BTIMER_CNTL_ENABLE                 (0x01UL)
-
-#define BTIMER_CNTL_HALT_BIT               (7U)
-#define BTIMER_CNTL_RELOAD_BIT             (6U)
-#define BTIMER_CNTL_START_BIT              (5U)
-#define BTIMER_CNTRL_SOFT_RESET_BIT        (4U)
-#define BTIMER_CNTL_AUTO_RESTART_BIT       (3U)
-#define BTIMER_CNTL_COUNT_DIR_BIT          (2U)
-#define BTIMER_CNTL_ENABLE_BIT             (0U)
-
-#define BTIMER_GIRQ													MEC_GIRQ23_ID
-#define BTIMER_MAX_INSTANCE									PID_BTIMER_MAX
-
-
-/* ---------------------------------------------------------------------- */
-/*            API - Basic Timer Intitialization function                  */
-/* ---------------------------------------------------------------------- */
-
-/** Initialize specified timer
- * @param btimer_id Basic Timer ID
- * @param tmr_cntl Logical flags for Timer Control
- * @param initial_count Initial Count
- * @param preload_count Preload Count
- * @note Performs a soft reset of the timer before configuration 
- */
-void btimer_init(uint8_t btimer_id, 
-               uint16_t tmr_cntl,
-               uint16_t prescaler,
-               uint32_t initial_count,
-               uint32_t preload_count);
-
-/* ---------------------------------------------------------------------- */
-/*  API -   Functions to program and read the Basic Timer Counter         */
-/* ---------------------------------------------------------------------- */
-/** Program timer's counter register.
- * @param btimer_id Basic Timer ID
- * @param count new counter value 
- * @note Timer hardware may implement a 16-bit or 32-bit 
- *       hardware counter. If the timer is 16-bit only the lower
- *       16-bits of the count paramter are used.
- */
-void btimer_count_set(uint8_t btimer_id, uint32_t count);
-
-/** Return current value of timer's count register.
- * @param btimer_id Basic Timer ID. 
- * @return uint32_t timer count may be 32 or 16 bits depending 
- *         upon the hardware.  Timers 0-3 are 16-bit
- *         and Timers 4-5 are 32-bit.
- */
-uint32_t btimer_count_get(uint8_t btimer_id);
-
-/* ---------------------------------------------------------------------- */
-/*  API -   Function to reload counter from Preload Register              */
-/* ---------------------------------------------------------------------- */
-/** Force timer to reload counter from preload 
- * register.  
- * @param btimer_id Basic Timer ID. 
- * @note Hardware will only reload counter if timer is running. 
- */
-void btimer_reload(uint8_t btimer_id);
-
-/* ---------------------------------------------------------------------- */
-/*  API -    Functions for stopping and starting the basic Timer          */
-/* ---------------------------------------------------------------------- */
-/** Start timer counting.
- * @param btimer_id Basic Timer ID.
- */
-void btimer_start(uint8_t btimer_id);
-
-/** Stop timer. 
- * @param btimer_id Basic Timer ID. 
- * @note When a stopped timer is started again it will reload 
- *       the count register from preload value.
- */
-void btimer_stop(uint8_t btimer_id);
-
-/** Return state of timer's START bit. 
- * @param btimer_id Basic Timer ID. 
- * @return uint8_t 0(timer not started), 1 (timer started)
- */
-uint8_t btimer_is_started(uint8_t btimer_id);
-
-/* ---------------------------------------------------------------------- */
-/*  API -         Function to perform basic timer soft reset              */
-/* ---------------------------------------------------------------------- */
-/** Peform soft reset of specified timer. 
- * @param btimer_id Basic Timer ID 
- * @note Soft reset set all registers to POR values.
- * Spins 256 times waiting on hardware to clear reset bit. 
- */
-void btimer_reset(uint8_t btimer_id);
-
-/* ---------------------------------------------------------------------- */
-/*   API -        Functions to halt/unhalt the timer counting             */
-/* ---------------------------------------------------------------------- */
-/** Halt timer counting with no reload on unhalt.   
- * @param btimer_id Basic Timer ID. 
- * @note A halted timer will not reload the count register when 
- *       unhalted, it will continue counting from the current
- *       count value.
- */
-void btimer_halt(uint8_t btimer_id);
-
-/** Unhalt timer counting. 
- * @param btimer_id Basic Timer ID.
- */
-void btimer_unhalt(uint8_t btimer_id);
-
-/* ---------------------------------------------------------------------- */
-/*   API -        Functions for Basic Timer interrupt                     */
-/* ---------------------------------------------------------------------- */
-/** Enable specified timer's interrupt from the block. 
- * @param btimer_id Basic Timer ID.
- * @param ien Non-zero enable interrupt in timer block, 0 
- *            disable.
- */
-void btimer_interrupt_enable(uint8_t btimer_id, uint8_t ien);
-
-/** Read Timer interrupt status and clear if set 
- * @param btimer_id Basic Timer ID. 
- * @return uint8_t 1 (Timer interrupt status set) else 0. 
- * @note If timer interrupt status is set then clear it before 
- *       returning.
- */
-uint8_t btimer_interrupt_status_get_clr(uint8_t btimer_id);
-
-/* ---------------------------------------------------------------------- */
-/*  API -         Functions for Basic Timer GIRQ                          */
-/* ---------------------------------------------------------------------- */
-/** Enables GIRQ enable bit for the timer 
- * @param btimer_id Basic Timer ID.
- */
-void btimer_girq_enable_set(uint8_t btimer_id);
-
-/** Clears GIRQ enable bit for the timer 
- * @param btimer_id Basic Timer ID.
- */
-void btimer_girq_enable_clr(uint8_t btimer_id);
-
-/** Returns GIRQ source bit for the timer 
- * @param btimer_id Basic Timer ID.
- * @return uint8_t 0(src bit not set), Non-zero (src bit set)
- */
-uint8_t btimer_girq_src_get(uint8_t btimer_id);
-
-/** Clears GIRQ source bit for the timer 
- * @param btimer_id Basic Timer ID.
- */
-void btimer_girq_src_clr(uint8_t btimer_id);
-
-/** Returns GIRQ result bit for the timer 
- * @param btimer_id Basic Timer ID.
- * @return uint8_t 0(result bit not set), Non-zero (result bit set)
- */
-uint8_t btimer_girq_result_get(uint8_t btimer_id);
-
-/* ---------------------------------------------------------------------- */
-/*  API -         Functions for Basic Timer Sleep                         */
-/* ---------------------------------------------------------------------- */
-/** Enable/Disable clock gating on idle of a timer  
- * @param btimer_id Basic Timer ID.
- * @param sleep_en 1 = Sleep enable, 0 = Sleep disable
- */
-void btimer_sleep(uint8_t btimer_id, uint8_t sleep_en);
-
-/** Returns clk required status for the timer block
- * @param btimer_id Basic Timer ID.
- * @return Non-zero if clk required, else 0
- */
-uint32_t btimer_clk_reqd_sts_get(uint8_t btimer_id);
-
-/** Enable/Disable reset on sleep for the timer block 
- * @param btimer_id Basic Timer ID.
- * @param reset_en 1 to enable, 0 to disable
- */
-void btimer_reset_on_sleep(uint8_t btimer_id, uint8_t reset_en);
-
-/* ---------------------------------------------------------------------- */
-/* Peripheral Function - Functions to set and read Timer Counter Register */
-/* ---------------------------------------------------------------------- */
-/** Sets timer counter
- * @param btimer_id Basic Timer ID
- * @param count	- 32-bit counter  
- */
-void p_btimer_count_set(uint8_t btimer_id, uint32_t count);
-
-/** Read the timer counter
- * @param btimer_id Basic Timer ID
- * @return count	- 32-bit counter  
- */
-uint32_t p_btimer_count_get(uint8_t btimer_id);
-
-
-/* ---------------------------------------------------------------------- */
-/* Peripheral Function - Function to program the Preload                  */
-/* ---------------------------------------------------------------------- */
-/** Sets preload for the counter
- * @param btimer_id Basic Timer ID
- * @param preload_count	- 32-bit pre-load value 
- */
-void p_btimer_preload_set(uint8_t btimer_id, uint32_t preload_count);
-
-/* ---------------------------------------------------------------------- */
-/* Peripheral Functions - Functions for basic timer interrupts            */
-/* ---------------------------------------------------------------------- */
-/** Reads the interrupt status bit in the timer block
- * @param btimer_id Basic Timer ID 
- * @return status - 1 if interrupt status set, else 0
- */
-uint8_t p_btimer_int_status_get(uint8_t btimer_id);
-
-/** Clears interrupt status bit in the timer block
- * @param btimer_id Basic Timer ID 
- */
-void p_btimer_int_status_clr(uint8_t btimer_id);
-
-/** Sets interrupt enable bit in the timer block
- * @param btimer_id Basic Timer ID  
- */
-void p_btimer_int_enable_set(uint8_t btimer_id);
-
-/** Clears interrupt enable bit for the timer block
- * @param btimer_id Basic Timer ID  
- */
-void p_btimer_int_enable_clr(uint8_t btimer_id);
-
-/* ---------------------------------------------------------------------- */
-/* Peripheral Functions - Functions for Control Register                  */
-/* ---------------------------------------------------------------------- */
-/** Writes the control register 32-bits
- * @param btimer_id Basic Timer ID
- * @param value	- 32-bit value to program
- */
-void p_btimer_ctrl_write(uint8_t btimer_id, uint32_t value);
-
-/** Reads the control register 
- * @param btimer_id Basic Timer ID
- * @return uint32_t	- 32-bit value
- */
-uint32_t p_btimer_ctrl_read(uint8_t btimer_id);
-
-/** Clears enable bit in the control register
- * @param btimer_id Basic Timer ID
- */
-void p_btimer_ctrl_enable_set(uint8_t btimer_id);
-
-/** Clears enable bit in the control register
- * @param btimer_id Basic Timer ID
- */
-void p_btimer_ctrl_enable_clr(uint8_t btimer_id);
-
-/** Sets counter direction bit in the control register
- * @param btimer_id Basic Timer ID
- */
-void p_btimer_ctrl_counter_dir_set(uint8_t btimer_id);
-
-/** Clears counter direction bit in the control register
- * @param btimer_id Basic Timer ID
- */
-void p_btimer_ctrl_counter_dir_clr(uint8_t btimer_id);
-
-/** Sets auto restart bit in the control register
- * @param btimer_id Basic Timer ID
- */
-void p_btimer_ctrl_auto_restart_set(uint8_t btimer_id);
-
-/** Clears auto resetart bit in the control register
- * @param btimer_id Basic Timer ID
- */
-void p_btimer_ctrl_auto_restart_clr(uint8_t btimer_id);
-
-/** Sets soft reset bit in the control register
- * @param btimer_id Basic Timer ID 
- */
-void p_btimer_ctrl_soft_reset_set(uint8_t btimer_id);
-
-/** Read Soft Reset bit 
- * @param btimer_id Basic Timer ID
- * @return 0 if soft reset status bit cleared; else non-zero value
- */
-uint8_t p_btimer_ctrl_soft_reset_sts_get(uint8_t btimer_id);
-
-/** Sets start bit in the control register
- * @param btimer_id Basic Timer ID 
- */
-void p_btimer_ctrl_start_set(uint8_t btimer_id);
-
-/** Read start bit in the control register
- * @param btimer_id Basic Timer ID 
- * @return 0 if start bit not set; else non-zero value
- */
-uint8_t p_btimer_ctrl_start_get(uint8_t btimer_id);
-
-/** Clears start bit in the control register
- * @param btimer_id Basic Timer ID 
- */
-void p_btimer_ctrl_start_clr(uint8_t btimer_id);
-
-/** Sets reload bit in the control register
- * @param btimer_id Basic Timer ID 
- */
-void p_btimer_ctrl_reload_set(uint8_t btimer_id);
-
-/** Clears reload bit in the control register
- * @param btimer_id Basic Timer ID 
- */
-void p_btimer_ctrl_reload_clr(uint8_t btimer_id);
-
-/** Sets halt bit in the control register
- * @param btimer_id Basic Timer ID 
- */
-void p_btimer_ctrl_halt_set(uint8_t btimer_id);
-
-/** Clears halt bit in the control register
- * @param btimer_id Basic Timer ID 
- */
-
-void p_btimer_ctrl_halt_clr(uint8_t btimer_id);
-
-/** Sets prescale value
- * @param btimer_id Basic Timer ID
- * @param prescaler	- 16-bit pre-scale value 
- */
-void p_btimer_ctrl_prescale_set(uint8_t btimer_id, uint16_t prescaler);
-
-
-#endif // #ifndef _BTIMER_H
-
-/* end btimer_perphl.c */
-
-/**   @} //Peripherals Basic_Timer
- */
-
+/*****************************************************************************
+* � 2015 Microchip Technology Inc. and its subsidiaries.
+* You may use this software and any derivatives exclusively with
+* Microchip products.
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
+* OF THESE TERMS.
+******************************************************************************
+
+Version Control Information (Perforce)
+******************************************************************************
+$Revision: #1 $ 
+$DateTime: 2016/04/08 10:18:28 $ 
+$Author: pramans $
+Last Change:	Updated with unit testing feedbacks
+******************************************************************************/
+/** @file btimer.h
+* \brief Basic Timer Peripheral Header file
+* \author jvasanth
+* 
+* This file is the header file for Basic Timer Peripheral 
+******************************************************************************/
+
+/** @defgroup Basic_Timer
+ *  @{
+ */
+
+#ifndef _BTIMER_H
+#define _BTIMER_H
+
+/******************************************************************************/
+/**  Logical Timer ID for APIs.
+ * This is the timer IDs passed to Basic Timer API function calls 
+ *******************************************************************************/
+enum _PID_BTIMER_
+{
+	PID_BTIMER_0,
+	PID_BTIMER_1,
+	PID_BTIMER_2,
+	PID_BTIMER_3,
+	PID_BTIMER_4,
+	PID_BTIMER_5,
+	PID_BTIMER_MAX	
+};
+
+/* ---------------------------------------------------------------------- */
+/*                    Logical flags for Timer Control                     */
+/* ---------------------------------------------------------------------- */
+//This is for tmr_cntl parameter in btimer_init function
+#define BTIMER_AUTO_RESTART     			     (0x08u)
+#define BTIMER_ONE_SHOT         			     (0u)
+#define BTIMER_COUNT_UP         			     (0x04u)
+#define BTIMER_COUNT_DOWN       			     (0u)
+#define BTIMER_INT_EN           			     (0x01u)
+#define BTIMER_NO_INT           			     (0u)
+/* ---------------------------------------------------------------------- */
+
+
+//Timer Block Hardware Bits and Masks
+#define BTIMER_CNTL_HALT                   (0x80UL)
+#define BTIMER_CNTL_RELOAD                 (0x40UL)
+#define BTIMER_CNTL_START                  (0x20UL)
+#define BTIMER_CNTL_SOFT_RESET             (0x10UL)
+#define BTIMER_CNTL_AUTO_RESTART           (0x08UL)
+#define BTIMER_CNTL_COUNT_UP               (0x04UL)
+#define BTIMER_CNTL_ENABLE                 (0x01UL)
+
+#define BTIMER_CNTL_HALT_BIT               (7U)
+#define BTIMER_CNTL_RELOAD_BIT             (6U)
+#define BTIMER_CNTL_START_BIT              (5U)
+#define BTIMER_CNTRL_SOFT_RESET_BIT        (4U)
+#define BTIMER_CNTL_AUTO_RESTART_BIT       (3U)
+#define BTIMER_CNTL_COUNT_DIR_BIT          (2U)
+#define BTIMER_CNTL_ENABLE_BIT             (0U)
+
+#define BTIMER_GIRQ													MEC_GIRQ23_ID
+#define BTIMER_MAX_INSTANCE									PID_BTIMER_MAX
+
+
+/* ---------------------------------------------------------------------- */
+/*            API - Basic Timer Intitialization function                  */
+/* ---------------------------------------------------------------------- */
+
+/** Initialize specified timer
+ * @param btimer_id Basic Timer ID
+ * @param tmr_cntl Logical flags for Timer Control
+ * @param initial_count Initial Count
+ * @param preload_count Preload Count
+ * @note Performs a soft reset of the timer before configuration 
+ */
+void btimer_init(uint8_t btimer_id, 
+               uint16_t tmr_cntl,
+               uint16_t prescaler,
+               uint32_t initial_count,
+               uint32_t preload_count);
+
+/* ---------------------------------------------------------------------- */
+/*  API -   Functions to program and read the Basic Timer Counter         */
+/* ---------------------------------------------------------------------- */
+/** Program timer's counter register.
+ * @param btimer_id Basic Timer ID
+ * @param count new counter value 
+ * @note Timer hardware may implement a 16-bit or 32-bit 
+ *       hardware counter. If the timer is 16-bit only the lower
+ *       16-bits of the count paramter are used.
+ */
+void btimer_count_set(uint8_t btimer_id, uint32_t count);
+
+/** Return current value of timer's count register.
+ * @param btimer_id Basic Timer ID. 
+ * @return uint32_t timer count may be 32 or 16 bits depending 
+ *         upon the hardware.  Timers 0-3 are 16-bit
+ *         and Timers 4-5 are 32-bit.
+ */
+uint32_t btimer_count_get(uint8_t btimer_id);
+
+/* ---------------------------------------------------------------------- */
+/*  API -   Function to reload counter from Preload Register              */
+/* ---------------------------------------------------------------------- */
+/** Force timer to reload counter from preload 
+ * register.  
+ * @param btimer_id Basic Timer ID. 
+ * @note Hardware will only reload counter if timer is running. 
+ */
+void btimer_reload(uint8_t btimer_id);
+
+/* ---------------------------------------------------------------------- */
+/*  API -    Functions for stopping and starting the basic Timer          */
+/* ---------------------------------------------------------------------- */
+/** Start timer counting.
+ * @param btimer_id Basic Timer ID.
+ */
+void btimer_start(uint8_t btimer_id);
+
+/** Stop timer. 
+ * @param btimer_id Basic Timer ID. 
+ * @note When a stopped timer is started again it will reload 
+ *       the count register from preload value.
+ */
+void btimer_stop(uint8_t btimer_id);
+
+/** Return state of timer's START bit. 
+ * @param btimer_id Basic Timer ID. 
+ * @return uint8_t 0(timer not started), 1 (timer started)
+ */
+uint8_t btimer_is_started(uint8_t btimer_id);
+
+/* ---------------------------------------------------------------------- */
+/*  API -         Function to perform basic timer soft reset              */
+/* ---------------------------------------------------------------------- */
+/** Peform soft reset of specified timer. 
+ * @param btimer_id Basic Timer ID 
+ * @note Soft reset set all registers to POR values.
+ * Spins 256 times waiting on hardware to clear reset bit. 
+ */
+void btimer_reset(uint8_t btimer_id);
+
+/* ---------------------------------------------------------------------- */
+/*   API -        Functions to halt/unhalt the timer counting             */
+/* ---------------------------------------------------------------------- */
+/** Halt timer counting with no reload on unhalt.   
+ * @param btimer_id Basic Timer ID. 
+ * @note A halted timer will not reload the count register when 
+ *       unhalted, it will continue counting from the current
+ *       count value.
+ */
+void btimer_halt(uint8_t btimer_id);
+
+/** Unhalt timer counting. 
+ * @param btimer_id Basic Timer ID.
+ */
+void btimer_unhalt(uint8_t btimer_id);
+
+/* ---------------------------------------------------------------------- */
+/*   API -        Functions for Basic Timer interrupt                     */
+/* ---------------------------------------------------------------------- */
+/** Enable specified timer's interrupt from the block. 
+ * @param btimer_id Basic Timer ID.
+ * @param ien Non-zero enable interrupt in timer block, 0 
+ *            disable.
+ */
+void btimer_interrupt_enable(uint8_t btimer_id, uint8_t ien);
+
+/** Read Timer interrupt status and clear if set 
+ * @param btimer_id Basic Timer ID. 
+ * @return uint8_t 1 (Timer interrupt status set) else 0. 
+ * @note If timer interrupt status is set then clear it before 
+ *       returning.
+ */
+uint8_t btimer_interrupt_status_get_clr(uint8_t btimer_id);
+
+/* ---------------------------------------------------------------------- */
+/*  API -         Functions for Basic Timer GIRQ                          */
+/* ---------------------------------------------------------------------- */
+/** Enables GIRQ enable bit for the timer 
+ * @param btimer_id Basic Timer ID.
+ */
+void btimer_girq_enable_set(uint8_t btimer_id);
+
+/** Clears GIRQ enable bit for the timer 
+ * @param btimer_id Basic Timer ID.
+ */
+void btimer_girq_enable_clr(uint8_t btimer_id);
+
+/** Returns GIRQ source bit for the timer 
+ * @param btimer_id Basic Timer ID.
+ * @return uint8_t 0(src bit not set), Non-zero (src bit set)
+ */
+uint8_t btimer_girq_src_get(uint8_t btimer_id);
+
+/** Clears GIRQ source bit for the timer 
+ * @param btimer_id Basic Timer ID.
+ */
+void btimer_girq_src_clr(uint8_t btimer_id);
+
+/** Returns GIRQ result bit for the timer 
+ * @param btimer_id Basic Timer ID.
+ * @return uint8_t 0(result bit not set), Non-zero (result bit set)
+ */
+uint8_t btimer_girq_result_get(uint8_t btimer_id);
+
+/* ---------------------------------------------------------------------- */
+/*  API -         Functions for Basic Timer Sleep                         */
+/* ---------------------------------------------------------------------- */
+/** Enable/Disable clock gating on idle of a timer  
+ * @param btimer_id Basic Timer ID.
+ * @param sleep_en 1 = Sleep enable, 0 = Sleep disable
+ */
+void btimer_sleep(uint8_t btimer_id, uint8_t sleep_en);
+
+/** Returns clk required status for the timer block
+ * @param btimer_id Basic Timer ID.
+ * @return Non-zero if clk required, else 0
+ */
+uint32_t btimer_clk_reqd_sts_get(uint8_t btimer_id);
+
+/** Enable/Disable reset on sleep for the timer block 
+ * @param btimer_id Basic Timer ID.
+ * @param reset_en 1 to enable, 0 to disable
+ */
+void btimer_reset_on_sleep(uint8_t btimer_id, uint8_t reset_en);
+
+/* ---------------------------------------------------------------------- */
+/* Peripheral Function - Functions to set and read Timer Counter Register */
+/* ---------------------------------------------------------------------- */
+/** Sets timer counter
+ * @param btimer_id Basic Timer ID
+ * @param count	- 32-bit counter  
+ */
+void p_btimer_count_set(uint8_t btimer_id, uint32_t count);
+
+/** Read the timer counter
+ * @param btimer_id Basic Timer ID
+ * @return count	- 32-bit counter  
+ */
+uint32_t p_btimer_count_get(uint8_t btimer_id);
+
+
+/* ---------------------------------------------------------------------- */
+/* Peripheral Function - Function to program the Preload                  */
+/* ---------------------------------------------------------------------- */
+/** Sets preload for the counter
+ * @param btimer_id Basic Timer ID
+ * @param preload_count	- 32-bit pre-load value 
+ */
+void p_btimer_preload_set(uint8_t btimer_id, uint32_t preload_count);
+
+/* ---------------------------------------------------------------------- */
+/* Peripheral Functions - Functions for basic timer interrupts            */
+/* ---------------------------------------------------------------------- */
+/** Reads the interrupt status bit in the timer block
+ * @param btimer_id Basic Timer ID 
+ * @return status - 1 if interrupt status set, else 0
+ */
+uint8_t p_btimer_int_status_get(uint8_t btimer_id);
+
+/** Clears interrupt status bit in the timer block
+ * @param btimer_id Basic Timer ID 
+ */
+void p_btimer_int_status_clr(uint8_t btimer_id);
+
+/** Sets interrupt enable bit in the timer block
+ * @param btimer_id Basic Timer ID  
+ */
+void p_btimer_int_enable_set(uint8_t btimer_id);
+
+/** Clears interrupt enable bit for the timer block
+ * @param btimer_id Basic Timer ID  
+ */
+void p_btimer_int_enable_clr(uint8_t btimer_id);
+
+/* ---------------------------------------------------------------------- */
+/* Peripheral Functions - Functions for Control Register                  */
+/* ---------------------------------------------------------------------- */
+/** Writes the control register 32-bits
+ * @param btimer_id Basic Timer ID
+ * @param value	- 32-bit value to program
+ */
+void p_btimer_ctrl_write(uint8_t btimer_id, uint32_t value);
+
+/** Reads the control register 
+ * @param btimer_id Basic Timer ID
+ * @return uint32_t	- 32-bit value
+ */
+uint32_t p_btimer_ctrl_read(uint8_t btimer_id);
+
+/** Clears enable bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_enable_set(uint8_t btimer_id);
+
+/** Clears enable bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_enable_clr(uint8_t btimer_id);
+
+/** Sets counter direction bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_counter_dir_set(uint8_t btimer_id);
+
+/** Clears counter direction bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_counter_dir_clr(uint8_t btimer_id);
+
+/** Sets auto restart bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_auto_restart_set(uint8_t btimer_id);
+
+/** Clears auto resetart bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_auto_restart_clr(uint8_t btimer_id);
+
+/** Sets soft reset bit in the control register
+ * @param btimer_id Basic Timer ID 
+ */
+void p_btimer_ctrl_soft_reset_set(uint8_t btimer_id);
+
+/** Read Soft Reset bit 
+ * @param btimer_id Basic Timer ID
+ * @return 0 if soft reset status bit cleared; else non-zero value
+ */
+uint8_t p_btimer_ctrl_soft_reset_sts_get(uint8_t btimer_id);
+
+/** Sets start bit in the control register
+ * @param btimer_id Basic Timer ID 
+ */
+void p_btimer_ctrl_start_set(uint8_t btimer_id);
+
+/** Read start bit in the control register
+ * @param btimer_id Basic Timer ID 
+ * @return 0 if start bit not set; else non-zero value
+ */
+uint8_t p_btimer_ctrl_start_get(uint8_t btimer_id);
+
+/** Clears start bit in the control register
+ * @param btimer_id Basic Timer ID 
+ */
+void p_btimer_ctrl_start_clr(uint8_t btimer_id);
+
+/** Sets reload bit in the control register
+ * @param btimer_id Basic Timer ID 
+ */
+void p_btimer_ctrl_reload_set(uint8_t btimer_id);
+
+/** Clears reload bit in the control register
+ * @param btimer_id Basic Timer ID 
+ */
+void p_btimer_ctrl_reload_clr(uint8_t btimer_id);
+
+/** Sets halt bit in the control register
+ * @param btimer_id Basic Timer ID 
+ */
+void p_btimer_ctrl_halt_set(uint8_t btimer_id);
+
+/** Clears halt bit in the control register
+ * @param btimer_id Basic Timer ID 
+ */
+
+void p_btimer_ctrl_halt_clr(uint8_t btimer_id);
+
+/** Sets prescale value
+ * @param btimer_id Basic Timer ID
+ * @param prescaler	- 16-bit pre-scale value 
+ */
+void p_btimer_ctrl_prescale_set(uint8_t btimer_id, uint16_t prescaler);
+
+
+#endif // #ifndef _BTIMER_H
+
+/* end btimer_perphl.c */
+
+/**   @} //Peripherals Basic_Timer
+ */
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/basic_timer/btimer_api.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/basic_timer/btimer_api.c
index d4cfea3e2..d865ecc8e 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/basic_timer/btimer_api.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/basic_timer/btimer_api.c
@@ -1,473 +1,474 @@
-/*****************************************************************************
-* � 2015 Microchip Technology Inc. and its subsidiaries.
-* You may use this software and any derivatives exclusively with
-* Microchip products.
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
-* OF THESE TERMS.
-******************************************************************************
-
-Version Control Information (Perforce)
-******************************************************************************
-$Revision: #2 $ 
-$DateTime: 2015/11/24 06:27:00 $ 
-$Author: amohandas $
-Last Change:	Updated for tabs
-******************************************************************************/
-/** @file btimer_api.c
-* \brief Basic Timer APIs Source file
-* \author jvasanth
-* 
-* This file implements the Basic Timer API functions  
-******************************************************************************/
-
-/** @defgroup Basic_Timer
- *  @{
- */
-
-#include "common_lib.h"
-#include "btimer.h"
-#include "..\pcr\pcr.h"
-
-/** Basic Timer Sleep Registers & Bit Positions */
-static const uint32_t btmr_pcr_id[BTIMER_MAX_INSTANCE] = {
-    PCR_BTIMER0,
-    PCR_BTIMER1,
-    PCR_BTIMER2,
-    PCR_BTIMER3,
-    PCR_BTIMER4,
-    PCR_BTIMER5
-};
-
-#ifdef PLIB_BTIMER_CHECK_ID
-
-/** Local helper that checks if logical Timer ID is valid.  
- * @param btimer_id Basic Timer ID 
- * @return uint8_t Non-zero(VALID), 0(Invalid)
- */
-static uint8_t btmr_valid(uint8_t btimer_id)
-{
-    if ( btimer_id < (PID_BTIMER_MAX ) ) {
-        return true;
-    }
-    return false;
-}
-
-#else
-
-
-/** This version of tmr_valid skips checking always returning 1.  
- *  Compiler may optimize it out.
- * @param btimer_id Basic Timer ID 
- * @return uint8_t 1(VALID) 
- */
-static uint8_t btmr_valid(uint8_t btimer_id) { return 1; }
-
-#endif
-
-
-/* ---------------------------------------------------------------------- */
-/*                 Basic Timer Intitialization function                   */
-/* ---------------------------------------------------------------------- */
-
-/** Initialize specified timer
- * @param btimer_id Basic Timer ID
- * @param tmr_cntl Logical flags for Timer Control
- * @param initial_count Initial Count
- * @param preload_count Preload Count
- * @note Performs a soft reset of the timer before configuration 
- */
-void btimer_init(uint8_t btimer_id, 
-               uint16_t tmr_cntl,
-               uint16_t prescaler,
-               uint32_t initial_count,
-               uint32_t preload_count)
-{    
-	 uint32_t value;    
-
-    if (btmr_valid(btimer_id)) {
-			
-        btimer_reset(btimer_id); 
-        
-        // Ungate timer clocks and program prescale
-        value = ((uint32_t)prescaler << 16) + (BTIMER_CNTL_ENABLE);			  
-        p_btimer_ctrl_write(btimer_id, value);
-    
-        // Program Preload & initial counter value
-        p_btimer_preload_set(btimer_id, preload_count);
-        p_btimer_count_set(btimer_id, initial_count);			
-        
-        // Program control register, interrupt enable, and clear status
-        if (tmr_cntl & BTIMER_COUNT_UP) {					
-            p_btimer_ctrl_counter_dir_set(btimer_id);            
-        }
-        if (tmr_cntl & BTIMER_AUTO_RESTART) {
-            p_btimer_ctrl_auto_restart_set(btimer_id);             
-        }        
-        if (tmr_cntl & BTIMER_INT_EN) {					
-            p_btimer_int_enable_set(btimer_id); // enable first
-            p_btimer_int_status_clr(btimer_id); // clear status          
-        }
-    }
-}
-
-/* ---------------------------------------------------------------------- */
-/*          Functions to program and read the Basic Timer Counter         */
-/* ---------------------------------------------------------------------- */
-
-/** Program timer's counter register.
- * @param btimer_id Basic Timer ID
- * @param count new counter value 
- * @note Timer hardware may implement a 16-bit or 32-bit 
- *       hardware counter. If the timer is 16-bit only the lower
- *       16-bits of the count paramter are used.
- */
-void btimer_count_set(uint8_t btimer_id, uint32_t count)
-{
-    if ( btmr_valid(btimer_id) ) {       
-			
-        p_btimer_count_set(btimer_id, count);        
-    }
-}
-
-/** Return current value of timer's count register.
- * @param btimer_id Basic Timer ID. 
- * @return uint32_t timer count may be 32 or 16 bits depending 
- *         upon the hardware.  Timers 0-3 are 16-bit
- *         and Timers 4-5 are 32-bit.
- */
-uint32_t btimer_count_get(uint8_t btimer_id)
-{    
-    uint32_t cnt;
-    
-    cnt = 0ul;
-    if ( btmr_valid(btimer_id) ) {        
-			
-        cnt = p_btimer_count_get(btimer_id);        
-    }
-    
-    return cnt;
-}
-
-/* ---------------------------------------------------------------------- */
-/*          Function to reload counter from Preload Register              */
-/* ---------------------------------------------------------------------- */
-
-/** Force timer to reload counter from preload 
- * register.  
- * @param btimer_id Basic Timer ID. 
- * @note Hardware will only reload counter if timer is running. 
- */
-void btimer_reload(uint8_t btimer_id)
-{
-    if ( btmr_valid(btimer_id) ) {        
-			
-        if (p_btimer_ctrl_start_get(btimer_id)) //Check if timer is running
-        {
-                p_btimer_ctrl_reload_set(btimer_id);
-        }
-    }
-}
-
-/* ---------------------------------------------------------------------- */
-/*           Functions for stopping and starting the basic Timer          */
-/* ---------------------------------------------------------------------- */
-
-/** Start timer counting.
- * @param btimer_id Basic Timer ID.
- */
-void btimer_start(uint8_t btimer_id)
-{
-    if ( btmr_valid(btimer_id) ) {
-            
-        p_btimer_ctrl_start_set(btimer_id);
-    }
-}
-
-/** Stop timer. 
- * @param btimer_id Basic Timer ID. 
- * @note When a stopped timer is started again it will reload 
- *       the count register from preload value.
- */
-void btimer_stop(uint8_t btimer_id)
-{
-    if ( btmr_valid(btimer_id) ) {        
-			
-        p_btimer_ctrl_start_clr(btimer_id);			
-        
-    }
-}
-
-/** Return state of timer's START bit. 
- * @param btimer_id Basic Timer ID. 
- * @return uint8_t 0(timer not started), 1 (timer started)
- */
-uint8_t btimer_is_started(uint8_t btimer_id)
-{ 
-    uint8_t sts;
-    
-    sts = 0;
-    if ( btmr_valid(btimer_id) ) {	  
- 			
-        if (p_btimer_ctrl_start_get(btimer_id))	
-        {
-            sts = 1;
-        }					
-    }
-    return sts;
-}
-
-/* ---------------------------------------------------------------------- */
-/*                Function to perform basic timer soft reset              */
-/* ---------------------------------------------------------------------- */
-
-/** Peform soft reset of specified timer. 
- * @param btimer_id Basic Timer ID 
- * @note Soft reset set all registers to POR values.
- * Spins 256 times waiting on hardware to clear reset bit. 
- */
-void btimer_reset(uint8_t btimer_id)
-{   
-    uint32_t wait_cnt;
-    uint8_t soft_reset_sts;
-
-    if (btmr_valid(btimer_id)) {      
-		 
-        p_btimer_ctrl_soft_reset_set(btimer_id);    
-
-        wait_cnt = 256ul;
-        do {
-            soft_reset_sts = p_btimer_ctrl_soft_reset_sts_get(btimer_id);
-            
-            if (0 == soft_reset_sts){          
-                break;
-            }
-        } 
-        while ( wait_cnt-- ); 
-    }      
-}
-
-/* ---------------------------------------------------------------------- */
-/*                Functions to halt/unhalt the timer counting             */
-/* ---------------------------------------------------------------------- */
-
-/** Halt timer counting with no reload on unhalt.   
- * @param btimer_id Basic Timer ID. 
- * @note A halted timer will not reload the count register when 
- *       unhalted, it will continue counting from the current
- *       count value.
- */
-void btimer_halt(uint8_t btimer_id)
-{
-    if ( btmr_valid(btimer_id) ) {
- 			
-        p_btimer_ctrl_halt_set(btimer_id);        
-    }
-}
-
-/** Unhalt timer counting. 
- * @param btimer_id Basic Timer ID.
- */
-void btimer_unhalt(uint8_t btimer_id)
-{
-    if ( btmr_valid(btimer_id) ) { 
-			
-        p_btimer_ctrl_halt_clr(btimer_id);
-    }
-}
-
-/* ---------------------------------------------------------------------- */
-/*                Functions for Basic Timer interrupt                     */
-/* ---------------------------------------------------------------------- */
-
-/** Enable specified timer's interrupt from the block. 
- * @param btimer_id Basic Timer ID.
- * @param ien Non-zero enable interrupt in timer block, 0 
- *            disable.
- */
-void btimer_interrupt_enable(uint8_t btimer_id, uint8_t ien)
-{    
-    if (btmr_valid(btimer_id)) {      
-			
-        p_btimer_int_enable_set(btimer_id);
-
-        if (ien) {
-             p_btimer_int_enable_set(btimer_id);
-        } else {
-             p_btimer_int_enable_clr(btimer_id);
-        }
-    }
-}
-
-/** Read Timer interrupt status and clear if set 
- * @param btimer_id Basic Timer ID. 
- * @return uint8_t 1 (Timer interrupt status set) else 0. 
- * @note If timer interrupt status is set then clear it before 
- *       returning.
- */
-uint8_t btimer_interrupt_status_get_clr(uint8_t btimer_id)
-{    
-    uint8_t sts;
-
-    sts = 0;
-    if (btmr_valid(btimer_id)) {        
-				
-				sts = p_btimer_int_status_get(btimer_id);
-        if (sts) {
-					p_btimer_int_status_clr(btimer_id);            
-        }
-    }
-    return sts;
-}
-
-#if 0 //Temporary disable until interrupt module
-
-/* ---------------------------------------------------------------------- */
-/*                Functions for Basic Timer GIRQ                          */
-/* ---------------------------------------------------------------------- */
-
-/** Enables GIRQ enable bit for the timer 
- * @param btimer_id Basic Timer ID.
- */
-void btimer_girq_enable_set(uint8_t btimer_id)
-{
-    if (btmr_valid(btimer_id))
-    {
-        //Note: Bit Position is same as Timer ID			
-        p_ecia_girq_enable_set(BTIMER_GIRQ, btimer_id);
-    }		
-}
-
-/** Clears GIRQ enable bit for the timer 
- * @param btimer_id Basic Timer ID.
- */
-void btimer_girq_enable_clr(uint8_t btimer_id)
-{	
-    if (btmr_valid(btimer_id))
-    {			
-        //Note: Bit Position is same as Timer ID			
-        p_ecia_girq_enable_clr(BTIMER_GIRQ, btimer_id);
-    }	
-		
-}
-
-/** Returns GIRQ source bit for the timer 
- * @param btimer_id Basic Timer ID.
- * @return uint8_t 0(src bit not set), Non-zero (src bit set)
- */
-uint8_t btimer_girq_src_get(uint8_t btimer_id)
-{
-    uint8_t retVal;
-
-    retVal = 0;
-    if (btmr_valid(btimer_id))
-    {
-        //Note: Bit Position is same as Timer ID			
-        retVal = p_ecia_girq_source_get(BTIMER_GIRQ, btimer_id);			
-    }
-
-    return retVal;
-}
-
-/** Clears GIRQ source bit for the timer 
- * @param btimer_id Basic Timer ID.
- */
-void btimer_girq_src_clr(uint8_t btimer_id)
-{
-    if (btmr_valid(btimer_id))
-    {
-        //Note: Bit Position is same as Timer ID			
-        p_ecia_girq_source_clr(BTIMER_GIRQ, btimer_id);				
-    }			
-}
-
-/** Returns GIRQ result bit for the timer 
- * @param btimer_id Basic Timer ID.
- * @return uint8_t 0(result bit not set), Non-zero (result bit set)
- */
-uint8_t btimer_girq_result_get(uint8_t btimer_id)
-{
-    uint8_t retVal;
-
-    retVal = 0;
-    if (btmr_valid(btimer_id))
-    {
-        //Note: Bit Position is same as Timer ID			
-        retVal = p_ecia_girq_result_get(BTIMER_GIRQ, btimer_id);			
-    }
-
-    return retVal;			
-}
-#endif
-
-/* ---------------------------------------------------------------------- */
-/*                Functions for Basic Timer Sleep                         */
-/* ---------------------------------------------------------------------- */
-
-/** Enable/Disable clock gating on idle of a timer  
- * @param btimer_id Basic Timer ID.
- * @param sleep_en 1 = Sleep enable, 0 = Sleep disable
- */
-void btimer_sleep(uint8_t btimer_id, uint8_t sleep_en)
-{
-    uint32_t pcr_blk_id;
-		
-    if ( btmr_valid(btimer_id) ) 
-    {				
-        pcr_blk_id = btmr_pcr_id[btimer_id];			
-			
-        pcr_sleep_enable(pcr_blk_id, sleep_en);        
-    }
-}
-
-/** Returns clk required status for the timer block
- * @param btimer_id Basic Timer ID.
- * @return Non-zero if clk required, else 0
- */
-uint32_t btimer_clk_reqd_sts_get(uint8_t btimer_id)
-{
-    uint32_t retVal;
-    uint32_t pcr_blk_id;
-    	
-    retVal = 0ul;   
-    if ( btmr_valid(btimer_id) ) 
-    {			
-        pcr_blk_id = btmr_pcr_id[btimer_id];
-        
-        retVal = pcr_clock_reqd_status_get(pcr_blk_id);			       
-    }
-		
-    return retVal;
-}
-
-/** Enable/Disable reset on sleep for the timer block 
- * @param btimer_id Basic Timer ID.
- * @param reset_en 1 to enable, 0 to disable
- */
-void btimer_reset_on_sleep(uint8_t btimer_id, uint8_t reset_en)
-{
-    uint32_t pcr_blk_id;   
-    
-    if ( btmr_valid(btimer_id) ) 
-    {			
-        pcr_blk_id = btmr_pcr_id[btimer_id];
-    
-        pcr_reset_enable(pcr_blk_id, reset_en);			
-    }
-}
-
-/* end btimer_api.c */
-
-/**   @} //Peripheral Basic_Timer
- */
+/*****************************************************************************
+* � 2015 Microchip Technology Inc. and its subsidiaries.
+* You may use this software and any derivatives exclusively with
+* Microchip products.
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
+* OF THESE TERMS.
+******************************************************************************
+
+Version Control Information (Perforce)
+******************************************************************************
+$Revision: #1 $ 
+$DateTime: 2016/04/08 10:18:28 $ 
+$Author: pramans $
+Last Change:	Updated for tabs
+******************************************************************************/
+/** @file btimer_api.c
+* \brief Basic Timer APIs Source file
+* \author jvasanth
+* 
+* This file implements the Basic Timer API functions  
+******************************************************************************/
+
+/** @defgroup Basic_Timer
+ *  @{
+ */
+
+#include "common_lib.h"
+#include "btimer.h"
+#include "..\pcr\pcr.h"
+//#include "..\interrupt\ecia.h"
+
+/** Basic Timer Sleep Registers & Bit Positions */
+static const uint32_t btmr_pcr_id[BTIMER_MAX_INSTANCE] = {
+    PCR_BTIMER0,
+    PCR_BTIMER1,
+    PCR_BTIMER2,
+    PCR_BTIMER3,
+    PCR_BTIMER4,
+    PCR_BTIMER5
+};
+
+#ifdef PLIB_BTIMER_CHECK_ID
+
+/** Local helper that checks if logical Timer ID is valid.  
+ * @param btimer_id Basic Timer ID 
+ * @return uint8_t Non-zero(VALID), 0(Invalid)
+ */
+static uint8_t btmr_valid(uint8_t btimer_id)
+{
+    if ( btimer_id < (PID_BTIMER_MAX ) ) {
+        return true;
+    }
+    return false;
+}
+
+#else
+
+
+/** This version of tmr_valid skips checking always returning 1.  
+ *  Compiler may optimize it out.
+ * @param btimer_id Basic Timer ID 
+ * @return uint8_t 1(VALID) 
+ */
+static uint8_t btmr_valid(uint8_t btimer_id) { return 1; }
+
+#endif
+
+
+/* ---------------------------------------------------------------------- */
+/*                 Basic Timer Intitialization function                   */
+/* ---------------------------------------------------------------------- */
+
+/** Initialize specified timer
+ * @param btimer_id Basic Timer ID
+ * @param tmr_cntl Logical flags for Timer Control
+ * @param initial_count Initial Count
+ * @param preload_count Preload Count
+ * @note Performs a soft reset of the timer before configuration 
+ */
+void btimer_init(uint8_t btimer_id, 
+               uint16_t tmr_cntl,
+               uint16_t prescaler,
+               uint32_t initial_count,
+               uint32_t preload_count)
+{    
+	 uint32_t value;    
+
+    if (btmr_valid(btimer_id)) {
+			
+        btimer_reset(btimer_id); 
+        
+        // Ungate timer clocks and program prescale
+        value = ((uint32_t)prescaler << 16) + (BTIMER_CNTL_ENABLE);			  
+        p_btimer_ctrl_write(btimer_id, value);
+    
+        // Program Preload & initial counter value
+        p_btimer_preload_set(btimer_id, preload_count);
+        p_btimer_count_set(btimer_id, initial_count);			
+        
+        // Program control register, interrupt enable, and clear status
+        if (tmr_cntl & BTIMER_COUNT_UP) {					
+            p_btimer_ctrl_counter_dir_set(btimer_id);            
+        }
+        if (tmr_cntl & BTIMER_AUTO_RESTART) {
+            p_btimer_ctrl_auto_restart_set(btimer_id);             
+        }        
+        if (tmr_cntl & BTIMER_INT_EN) {					
+            p_btimer_int_enable_set(btimer_id); // enable first
+            p_btimer_int_status_clr(btimer_id); // clear status          
+        }
+    }
+}
+
+/* ---------------------------------------------------------------------- */
+/*          Functions to program and read the Basic Timer Counter         */
+/* ---------------------------------------------------------------------- */
+
+/** Program timer's counter register.
+ * @param btimer_id Basic Timer ID
+ * @param count new counter value 
+ * @note Timer hardware may implement a 16-bit or 32-bit 
+ *       hardware counter. If the timer is 16-bit only the lower
+ *       16-bits of the count paramter are used.
+ */
+void btimer_count_set(uint8_t btimer_id, uint32_t count)
+{
+    if ( btmr_valid(btimer_id) ) {       
+			
+        p_btimer_count_set(btimer_id, count);        
+    }
+}
+
+/** Return current value of timer's count register.
+ * @param btimer_id Basic Timer ID. 
+ * @return uint32_t timer count may be 32 or 16 bits depending 
+ *         upon the hardware.  Timers 0-3 are 16-bit
+ *         and Timers 4-5 are 32-bit.
+ */
+uint32_t btimer_count_get(uint8_t btimer_id)
+{    
+    uint32_t cnt;
+    
+    cnt = 0ul;
+    if ( btmr_valid(btimer_id) ) {        
+			
+        cnt = p_btimer_count_get(btimer_id);        
+    }
+    
+    return cnt;
+}
+
+/* ---------------------------------------------------------------------- */
+/*          Function to reload counter from Preload Register              */
+/* ---------------------------------------------------------------------- */
+
+/** Force timer to reload counter from preload 
+ * register.  
+ * @param btimer_id Basic Timer ID. 
+ * @note Hardware will only reload counter if timer is running. 
+ */
+void btimer_reload(uint8_t btimer_id)
+{
+    if ( btmr_valid(btimer_id) ) {        
+			
+        if (p_btimer_ctrl_start_get(btimer_id)) //Check if timer is running
+        {
+                p_btimer_ctrl_reload_set(btimer_id);
+        }
+    }
+}
+
+/* ---------------------------------------------------------------------- */
+/*           Functions for stopping and starting the basic Timer          */
+/* ---------------------------------------------------------------------- */
+
+/** Start timer counting.
+ * @param btimer_id Basic Timer ID.
+ */
+void btimer_start(uint8_t btimer_id)
+{
+    if ( btmr_valid(btimer_id) ) {
+            
+        p_btimer_ctrl_start_set(btimer_id);
+    }
+}
+
+/** Stop timer. 
+ * @param btimer_id Basic Timer ID. 
+ * @note When a stopped timer is started again it will reload 
+ *       the count register from preload value.
+ */
+void btimer_stop(uint8_t btimer_id)
+{
+    if ( btmr_valid(btimer_id) ) {        
+			
+        p_btimer_ctrl_start_clr(btimer_id);			
+        
+    }
+}
+
+/** Return state of timer's START bit. 
+ * @param btimer_id Basic Timer ID. 
+ * @return uint8_t 0(timer not started), 1 (timer started)
+ */
+uint8_t btimer_is_started(uint8_t btimer_id)
+{ 
+    uint8_t sts;
+    
+    sts = 0;
+    if ( btmr_valid(btimer_id) ) {	  
+ 			
+        if (p_btimer_ctrl_start_get(btimer_id))	
+        {
+            sts = 1;
+        }					
+    }
+    return sts;
+}
+
+/* ---------------------------------------------------------------------- */
+/*                Function to perform basic timer soft reset              */
+/* ---------------------------------------------------------------------- */
+
+/** Peform soft reset of specified timer. 
+ * @param btimer_id Basic Timer ID 
+ * @note Soft reset set all registers to POR values.
+ * Spins 256 times waiting on hardware to clear reset bit. 
+ */
+void btimer_reset(uint8_t btimer_id)
+{   
+    uint32_t wait_cnt;
+    uint8_t soft_reset_sts;
+
+    if (btmr_valid(btimer_id)) {      
+		 
+        p_btimer_ctrl_soft_reset_set(btimer_id);    
+
+        wait_cnt = 256ul;
+        do {
+            soft_reset_sts = p_btimer_ctrl_soft_reset_sts_get(btimer_id);
+            
+            if (0 == soft_reset_sts){          
+                break;
+            }
+        } 
+        while ( wait_cnt-- ); 
+    }      
+}
+
+/* ---------------------------------------------------------------------- */
+/*                Functions to halt/unhalt the timer counting             */
+/* ---------------------------------------------------------------------- */
+
+/** Halt timer counting with no reload on unhalt.   
+ * @param btimer_id Basic Timer ID. 
+ * @note A halted timer will not reload the count register when 
+ *       unhalted, it will continue counting from the current
+ *       count value.
+ */
+void btimer_halt(uint8_t btimer_id)
+{
+    if ( btmr_valid(btimer_id) ) {
+ 			
+        p_btimer_ctrl_halt_set(btimer_id);        
+    }
+}
+
+/** Unhalt timer counting. 
+ * @param btimer_id Basic Timer ID.
+ */
+void btimer_unhalt(uint8_t btimer_id)
+{
+    if ( btmr_valid(btimer_id) ) { 
+			
+        p_btimer_ctrl_halt_clr(btimer_id);
+    }
+}
+
+/* ---------------------------------------------------------------------- */
+/*                Functions for Basic Timer interrupt                     */
+/* ---------------------------------------------------------------------- */
+
+/** Enable specified timer's interrupt from the block. 
+ * @param btimer_id Basic Timer ID.
+ * @param ien Non-zero enable interrupt in timer block, 0 
+ *            disable.
+ */
+void btimer_interrupt_enable(uint8_t btimer_id, uint8_t ien)
+{    
+    if (btmr_valid(btimer_id)) {      
+			
+        p_btimer_int_enable_set(btimer_id);
+
+        if (ien) {
+             p_btimer_int_enable_set(btimer_id);
+        } else {
+             p_btimer_int_enable_clr(btimer_id);
+        }
+    }
+}
+
+/** Read Timer interrupt status and clear if set 
+ * @param btimer_id Basic Timer ID. 
+ * @return uint8_t 1 (Timer interrupt status set) else 0. 
+ * @note If timer interrupt status is set then clear it before 
+ *       returning.
+ */
+uint8_t btimer_interrupt_status_get_clr(uint8_t btimer_id)
+{    
+    uint8_t sts;
+
+    sts = 0;
+    if (btmr_valid(btimer_id)) {        
+				
+				sts = p_btimer_int_status_get(btimer_id);
+        if (sts) {
+					p_btimer_int_status_clr(btimer_id);            
+        }
+    }
+    return sts;
+}
+
+#if 0 //Temporary disable until interrupt module
+
+/* ---------------------------------------------------------------------- */
+/*                Functions for Basic Timer GIRQ                          */
+/* ---------------------------------------------------------------------- */
+
+/** Enables GIRQ enable bit for the timer 
+ * @param btimer_id Basic Timer ID.
+ */
+void btimer_girq_enable_set(uint8_t btimer_id)
+{
+    if (btmr_valid(btimer_id))
+    {
+        //Note: Bit Position is same as Timer ID			
+        p_ecia_girq_enable_set(BTIMER_GIRQ, btimer_id);
+    }		
+}
+
+/** Clears GIRQ enable bit for the timer 
+ * @param btimer_id Basic Timer ID.
+ */
+void btimer_girq_enable_clr(uint8_t btimer_id)
+{	
+    if (btmr_valid(btimer_id))
+    {			
+        //Note: Bit Position is same as Timer ID			
+        p_ecia_girq_enable_clr(BTIMER_GIRQ, btimer_id);
+    }	
+		
+}
+
+/** Returns GIRQ source bit for the timer 
+ * @param btimer_id Basic Timer ID.
+ * @return uint8_t 0(src bit not set), Non-zero (src bit set)
+ */
+uint8_t btimer_girq_src_get(uint8_t btimer_id)
+{
+    uint8_t retVal;
+
+    retVal = 0;
+    if (btmr_valid(btimer_id))
+    {
+        //Note: Bit Position is same as Timer ID			
+        retVal = p_ecia_girq_source_get(BTIMER_GIRQ, btimer_id);			
+    }
+
+    return retVal;
+}
+
+/** Clears GIRQ source bit for the timer 
+ * @param btimer_id Basic Timer ID.
+ */
+void btimer_girq_src_clr(uint8_t btimer_id)
+{
+    if (btmr_valid(btimer_id))
+    {
+        //Note: Bit Position is same as Timer ID			
+        p_ecia_girq_source_clr(BTIMER_GIRQ, btimer_id);				
+    }			
+}
+
+/** Returns GIRQ result bit for the timer 
+ * @param btimer_id Basic Timer ID.
+ * @return uint8_t 0(result bit not set), Non-zero (result bit set)
+ */
+uint8_t btimer_girq_result_get(uint8_t btimer_id)
+{
+    uint8_t retVal;
+
+    retVal = 0;
+    if (btmr_valid(btimer_id))
+    {
+        //Note: Bit Position is same as Timer ID			
+        retVal = p_ecia_girq_result_get(BTIMER_GIRQ, btimer_id);			
+    }
+
+    return retVal;			
+}
+#endif
+
+/* ---------------------------------------------------------------------- */
+/*                Functions for Basic Timer Sleep                         */
+/* ---------------------------------------------------------------------- */
+
+/** Enable/Disable clock gating on idle of a timer  
+ * @param btimer_id Basic Timer ID.
+ * @param sleep_en 1 = Sleep enable, 0 = Sleep disable
+ */
+void btimer_sleep(uint8_t btimer_id, uint8_t sleep_en)
+{
+    uint32_t pcr_blk_id;
+		
+    if ( btmr_valid(btimer_id) ) 
+    {				
+        pcr_blk_id = btmr_pcr_id[btimer_id];			
+			
+        pcr_sleep_enable(pcr_blk_id, sleep_en);        
+    }
+}
+
+/** Returns clk required status for the timer block
+ * @param btimer_id Basic Timer ID.
+ * @return Non-zero if clk required, else 0
+ */
+uint32_t btimer_clk_reqd_sts_get(uint8_t btimer_id)
+{
+    uint32_t retVal;
+    uint32_t pcr_blk_id;
+    	
+    retVal = 0ul;   
+    if ( btmr_valid(btimer_id) ) 
+    {			
+        pcr_blk_id = btmr_pcr_id[btimer_id];
+        
+        retVal = pcr_clock_reqd_status_get(pcr_blk_id);			       
+    }
+		
+    return retVal;
+}
+
+/** Enable/Disable reset on sleep for the timer block 
+ * @param btimer_id Basic Timer ID.
+ * @param reset_en 1 to enable, 0 to disable
+ */
+void btimer_reset_on_sleep(uint8_t btimer_id, uint8_t reset_en)
+{
+    uint32_t pcr_blk_id;   
+    
+    if ( btmr_valid(btimer_id) ) 
+    {			
+        pcr_blk_id = btmr_pcr_id[btimer_id];
+    
+        pcr_reset_enable(pcr_blk_id, reset_en);			
+    }
+}
+
+/* end btimer_api.c */
+
+/**   @} //Peripheral Basic_Timer
+ */
diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/basic_timer/btimer_perphl.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/basic_timer/btimer_perphl.c
index b2c9b97bc..def9c0828 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/basic_timer/btimer_perphl.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/basic_timer/btimer_perphl.c
@@ -1,287 +1,287 @@
-/*****************************************************************************
-* � 2015 Microchip Technology Inc. and its subsidiaries.
-* You may use this software and any derivatives exclusively with
-* Microchip products.
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
-* OF THESE TERMS.
-******************************************************************************
-
-Version Control Information (Perforce)
-******************************************************************************
-$Revision: #2 $ 
-$DateTime: 2015/11/24 06:27:00 $ 
-$Author: amohandas $
-Last Change:	Updated for tabs
-******************************************************************************/
-/** @file btimer_perphl.c
-* \brief Basic Timer Peripheral Source file
-* \author jvasanth
-* 
-* This file implements the Basic Timer Peripheral functions  
-******************************************************************************/
-
-/** @defgroup Basic_Timer
- *  @{
- */
-
-#include "common_lib.h"
-#include "btimer.h"
-
-/** Basic Timer Instance base addresses */
-static TIMER_16_0_Type * const btmr_inst[BTIMER_MAX_INSTANCE] = {
-    CEC1302_TIMER_16_0,
-    CEC1302_TIMER_16_1,
-    CEC1302_TIMER_16_2,
-    CEC1302_TIMER_16_3,
-    CEC1302_TIMER_32_0,
-    CEC1302_TIMER_32_1
-};
-
-/* ---------------------------------------------------------------------- */
-/*           Functions to set and read Timer Counter Register             */
-/* ---------------------------------------------------------------------- */
-
-/** Sets timer counter
- * @param btimer_id Basic Timer ID
- * @param count	- 32-bit counter  
- */
-void p_btimer_count_set(uint8_t btimer_id, uint32_t count)
-{
-    btmr_inst[btimer_id]->COUNT = count;					
-}
-
-/** Read the timer counter
- * @param btimer_id Basic Timer ID
- * @return count	- 32-bit counter  
- */
-uint32_t p_btimer_count_get(uint8_t btimer_id)
-{	
-    return btmr_inst[btimer_id]->COUNT;	
-}
-
-/* ---------------------------------------------------------------------- */
-/*                   Function to program the Preload                      */
-/* ---------------------------------------------------------------------- */
-
-/** Sets preload for the counter
- * @param btimer_id Basic Timer ID
- * @param preload_count	- 32-bit pre-load value 
- */
-void p_btimer_preload_set(uint8_t btimer_id, uint32_t preload_count)
-{
-    btmr_inst[btimer_id]->PRE_LOAD = preload_count;	
-}
-
-/* ---------------------------------------------------------------------- */
-/*                Functions for basic timer interrupts                    */
-/* ---------------------------------------------------------------------- */
-
-/** Reads the interrupt status bit in the timer block
- * @param btimer_id Basic Timer ID 
- * @return status - 1 if interrupt status set, else 0
- */
-uint8_t p_btimer_int_status_get(uint8_t btimer_id)
-{
-    return (uint8_t)(btmr_inst[btimer_id]->INTERRUPT_STATUS);
-}
-
-/** Clears interrupt status bit in the timer block
- * @param btimer_id Basic Timer ID 
- */
-void p_btimer_int_status_clr(uint8_t btimer_id)
-{
-    // Write 1 to clear
-    btmr_inst[btimer_id]->INTERRUPT_STATUS = 1;
-}
-
-/** Sets interrupt enable bit in the timer block
- * @param btimer_id Basic Timer ID  
- */
-void p_btimer_int_enable_set(uint8_t btimer_id)
-{		
-    btmr_inst[btimer_id]->INTERRUPT_ENABLE = 1;
-}
-
-/** Clears interrupt enable bit for the timer block
- * @param btimer_id Basic Timer ID  
- */
-void p_btimer_int_enable_clr(uint8_t btimer_id)
-{		
-    btmr_inst[btimer_id]->INTERRUPT_ENABLE = 0;
-}
-
-/* ---------------------------------------------------------------------- */
-/*                Functions for Control Register                          */
-/* ---------------------------------------------------------------------- */
-
-/** Writes the control register 32-bits
- * @param btimer_id Basic Timer ID
- * @param value	- 32-bit value to program
- */
-void p_btimer_ctrl_write(uint8_t btimer_id, uint32_t value)
-{		
-    btmr_inst[btimer_id]->CONTROL.w = value;
-}
-
-/** Reads the control register 
- * @param btimer_id Basic Timer ID
- * @return uint32_t	- 32-bit value
- */
-uint32_t p_btimer_ctrl_read(uint8_t btimer_id)
-{		
-    uint32_t retVal;
-
-    retVal = btmr_inst[btimer_id]->CONTROL.w;
-
-    return retVal;
-}
-
-/** Sets enable bit in the control register
- * @param btimer_id Basic Timer ID
- */
-void p_btimer_ctrl_enable_set(uint8_t btimer_id)
-{		
-    btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_ENABLE;
-}
-
-/** Clears enable bit in the control register
- * @param btimer_id Basic Timer ID
- */
-void p_btimer_ctrl_enable_clr(uint8_t btimer_id)
-{		
-    btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_ENABLE;
-}
-
-/** Sets counter direction bit in the control register
- * @param btimer_id Basic Timer ID
- */
-void p_btimer_ctrl_counter_dir_set(uint8_t btimer_id)
-{		
-    btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_COUNT_UP;
-}
-
-/** Clears counter direction bit in the control register
- * @param btimer_id Basic Timer ID
- */
-void p_btimer_ctrl_counter_dir_clr(uint8_t btimer_id)
-{		
-    btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_COUNT_UP;
-}
-
-/** Sets auto restart bit in the control register
- * @param btimer_id Basic Timer ID
- */
-void p_btimer_ctrl_auto_restart_set(uint8_t btimer_id)
-{		
-    btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_AUTO_RESTART;
-}
-
-/** Clears auto resetart bit in the control register
- * @param btimer_id Basic Timer ID
- */
-void p_btimer_ctrl_auto_restart_clr(uint8_t btimer_id)
-{		
-    btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_AUTO_RESTART;
-}
-
-/** Sets soft reset bit in the control register
- * @param btimer_id Basic Timer ID 
- */
-void p_btimer_ctrl_soft_reset_set(uint8_t btimer_id)
-{		
-    btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_SOFT_RESET;
-}
-
-/** Read Soft Reset bit 
- * @param btimer_id Basic Timer ID
- * @return 0 if soft reset status bit cleared; else non-zero value
- */
-uint8_t p_btimer_ctrl_soft_reset_sts_get(uint8_t btimer_id)
-{		
-    return (btmr_inst[btimer_id]->CONTROL.b[0] & BTIMER_CNTL_SOFT_RESET);
-}
-
-/** Sets start bit in the control register
- * @param btimer_id Basic Timer ID 
- */
-void p_btimer_ctrl_start_set(uint8_t btimer_id)
-{		
-    btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_START;
-}
-
-/** Read start bit in the control register
- * @param btimer_id Basic Timer ID 
- * @return 0 if start bit not set; else non-zero value
- */
-uint8_t p_btimer_ctrl_start_get(uint8_t btimer_id)
-{		
-    return (btmr_inst[btimer_id]->CONTROL.b[0] & BTIMER_CNTL_START);
-}
-
-/** Clears start bit in the control register
- * @param btimer_id Basic Timer ID 
- */
-void p_btimer_ctrl_start_clr(uint8_t btimer_id)
-{		
-    btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_START;
-}
-
-/** Sets reload bit in the control register
- * @param btimer_id Basic Timer ID 
- */
-void p_btimer_ctrl_reload_set(uint8_t btimer_id)
-{		
-    btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_RELOAD;
-}
-
-/** Clears reload bit in the control register
- * @param btimer_id Basic Timer ID 
- */
-void p_btimer_ctrl_reload_clr(uint8_t btimer_id)
-{		
-    btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_RELOAD;
-}
-
-/** Sets halt bit in the control register
- * @param btimer_id Basic Timer ID 
- */
-void p_btimer_ctrl_halt_set(uint8_t btimer_id)
-{		
-    btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_HALT;
-}
-
-/** Clears halt bit in the control register
- * @param btimer_id Basic Timer ID 
- */
-void p_btimer_ctrl_halt_clr(uint8_t btimer_id)
-{		
-    btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_HALT;
-}
-
-/** Sets prescale value
- * @param btimer_id Basic Timer ID
- * @param prescaler	- 16-bit pre-scale value 
- */
-void p_btimer_ctrl_prescale_set(uint8_t btimer_id, uint16_t prescaler)
-{		
-    btmr_inst[btimer_id]->CONTROL.h[1] = prescaler;
-}
-
-
-/* end btimer_perphl.c */
-
-/**   @} //Peripheral Basic_Timer
- */
-
+/*****************************************************************************
+* � 2015 Microchip Technology Inc. and its subsidiaries.
+* You may use this software and any derivatives exclusively with
+* Microchip products.
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
+* OF THESE TERMS.
+******************************************************************************
+
+Version Control Information (Perforce)
+******************************************************************************
+$Revision: #1 $ 
+$DateTime: 2016/04/08 10:18:28 $ 
+$Author: pramans $
+Last Change:	Updated for tabs
+******************************************************************************/
+/** @file btimer_perphl.c
+* \brief Basic Timer Peripheral Source file
+* \author jvasanth
+* 
+* This file implements the Basic Timer Peripheral functions  
+******************************************************************************/
+
+/** @defgroup Basic_Timer
+ *  @{
+ */
+
+#include "common_lib.h"
+#include "btimer.h"
+
+/** Basic Timer Instance base addresses */
+static TIMER_16_0_Type * const btmr_inst[BTIMER_MAX_INSTANCE] = {
+    CEC1302_TIMER_16_0,
+    CEC1302_TIMER_16_1,
+    CEC1302_TIMER_16_2,
+    CEC1302_TIMER_16_3,
+    CEC1302_TIMER_32_0,
+    CEC1302_TIMER_32_1
+};
+
+/* ---------------------------------------------------------------------- */
+/*           Functions to set and read Timer Counter Register             */
+/* ---------------------------------------------------------------------- */
+
+/** Sets timer counter
+ * @param btimer_id Basic Timer ID
+ * @param count	- 32-bit counter  
+ */
+void p_btimer_count_set(uint8_t btimer_id, uint32_t count)
+{
+    btmr_inst[btimer_id]->COUNT = count;					
+}
+
+/** Read the timer counter
+ * @param btimer_id Basic Timer ID
+ * @return count	- 32-bit counter  
+ */
+uint32_t p_btimer_count_get(uint8_t btimer_id)
+{	
+    return btmr_inst[btimer_id]->COUNT;	
+}
+
+/* ---------------------------------------------------------------------- */
+/*                   Function to program the Preload                      */
+/* ---------------------------------------------------------------------- */
+
+/** Sets preload for the counter
+ * @param btimer_id Basic Timer ID
+ * @param preload_count	- 32-bit pre-load value 
+ */
+void p_btimer_preload_set(uint8_t btimer_id, uint32_t preload_count)
+{
+    btmr_inst[btimer_id]->PRE_LOAD = preload_count;	
+}
+
+/* ---------------------------------------------------------------------- */
+/*                Functions for basic timer interrupts                    */
+/* ---------------------------------------------------------------------- */
+
+/** Reads the interrupt status bit in the timer block
+ * @param btimer_id Basic Timer ID 
+ * @return status - 1 if interrupt status set, else 0
+ */
+uint8_t p_btimer_int_status_get(uint8_t btimer_id)
+{
+    return (uint8_t)(btmr_inst[btimer_id]->INTERRUPT_STATUS);
+}
+
+/** Clears interrupt status bit in the timer block
+ * @param btimer_id Basic Timer ID 
+ */
+void p_btimer_int_status_clr(uint8_t btimer_id)
+{
+    // Write 1 to clear
+    btmr_inst[btimer_id]->INTERRUPT_STATUS = 1;
+}
+
+/** Sets interrupt enable bit in the timer block
+ * @param btimer_id Basic Timer ID  
+ */
+void p_btimer_int_enable_set(uint8_t btimer_id)
+{		
+    btmr_inst[btimer_id]->INTERRUPT_ENABLE = 1;
+}
+
+/** Clears interrupt enable bit for the timer block
+ * @param btimer_id Basic Timer ID  
+ */
+void p_btimer_int_enable_clr(uint8_t btimer_id)
+{		
+    btmr_inst[btimer_id]->INTERRUPT_ENABLE = 0;
+}
+
+/* ---------------------------------------------------------------------- */
+/*                Functions for Control Register                          */
+/* ---------------------------------------------------------------------- */
+
+/** Writes the control register 32-bits
+ * @param btimer_id Basic Timer ID
+ * @param value	- 32-bit value to program
+ */
+void p_btimer_ctrl_write(uint8_t btimer_id, uint32_t value)
+{		
+    btmr_inst[btimer_id]->CONTROL.w = value;
+}
+
+/** Reads the control register 
+ * @param btimer_id Basic Timer ID
+ * @return uint32_t	- 32-bit value
+ */
+uint32_t p_btimer_ctrl_read(uint8_t btimer_id)
+{		
+    uint32_t retVal;
+
+    retVal = btmr_inst[btimer_id]->CONTROL.w;
+
+    return retVal;
+}
+
+/** Sets enable bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_enable_set(uint8_t btimer_id)
+{		
+    btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_ENABLE;
+}
+
+/** Clears enable bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_enable_clr(uint8_t btimer_id)
+{		
+    btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_ENABLE;
+}
+
+/** Sets counter direction bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_counter_dir_set(uint8_t btimer_id)
+{		
+    btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_COUNT_UP;
+}
+
+/** Clears counter direction bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_counter_dir_clr(uint8_t btimer_id)
+{		
+    btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_COUNT_UP;
+}
+
+/** Sets auto restart bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_auto_restart_set(uint8_t btimer_id)
+{		
+    btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_AUTO_RESTART;
+}
+
+/** Clears auto resetart bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_auto_restart_clr(uint8_t btimer_id)
+{		
+    btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_AUTO_RESTART;
+}
+
+/** Sets soft reset bit in the control register
+ * @param btimer_id Basic Timer ID 
+ */
+void p_btimer_ctrl_soft_reset_set(uint8_t btimer_id)
+{		
+    btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_SOFT_RESET;
+}
+
+/** Read Soft Reset bit 
+ * @param btimer_id Basic Timer ID
+ * @return 0 if soft reset status bit cleared; else non-zero value
+ */
+uint8_t p_btimer_ctrl_soft_reset_sts_get(uint8_t btimer_id)
+{		
+    return (btmr_inst[btimer_id]->CONTROL.b[0] & BTIMER_CNTL_SOFT_RESET);
+}
+
+/** Sets start bit in the control register
+ * @param btimer_id Basic Timer ID 
+ */
+void p_btimer_ctrl_start_set(uint8_t btimer_id)
+{		
+    btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_START;
+}
+
+/** Read start bit in the control register
+ * @param btimer_id Basic Timer ID 
+ * @return 0 if start bit not set; else non-zero value
+ */
+uint8_t p_btimer_ctrl_start_get(uint8_t btimer_id)
+{		
+    return (btmr_inst[btimer_id]->CONTROL.b[0] & BTIMER_CNTL_START);
+}
+
+/** Clears start bit in the control register
+ * @param btimer_id Basic Timer ID 
+ */
+void p_btimer_ctrl_start_clr(uint8_t btimer_id)
+{		
+    btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_START;
+}
+
+/** Sets reload bit in the control register
+ * @param btimer_id Basic Timer ID 
+ */
+void p_btimer_ctrl_reload_set(uint8_t btimer_id)
+{		
+    btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_RELOAD;
+}
+
+/** Clears reload bit in the control register
+ * @param btimer_id Basic Timer ID 
+ */
+void p_btimer_ctrl_reload_clr(uint8_t btimer_id)
+{		
+    btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_RELOAD;
+}
+
+/** Sets halt bit in the control register
+ * @param btimer_id Basic Timer ID 
+ */
+void p_btimer_ctrl_halt_set(uint8_t btimer_id)
+{		
+    btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_HALT;
+}
+
+/** Clears halt bit in the control register
+ * @param btimer_id Basic Timer ID 
+ */
+void p_btimer_ctrl_halt_clr(uint8_t btimer_id)
+{		
+    btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_HALT;
+}
+
+/** Sets prescale value
+ * @param btimer_id Basic Timer ID
+ * @param prescaler	- 16-bit pre-scale value 
+ */
+void p_btimer_ctrl_prescale_set(uint8_t btimer_id, uint16_t prescaler)
+{		
+    btmr_inst[btimer_id]->CONTROL.h[1] = prescaler;
+}
+
+
+/* end btimer_perphl.c */
+
+/**   @} //Peripheral Basic_Timer
+ */
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/common.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/common.h
index f8fc613b6..2b9f7790b 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/common.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/common.h
@@ -1,71 +1,70 @@
-/*
- **********************************************************************************
-* � 2013 Microchip Technology Inc. and its subsidiaries.
-* You may use this software and any derivatives exclusively with
-* Microchip products.
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
-* OF THESE TERMS.
- **********************************************************************************
- *  common.h
- *      This is the header file including common headers from various modules
- **********************************************************************************
- *  $Revision: #1 $  $DateTime: 2015/12/23 15:37:58 $  $    $
- *  Description: added ict module
- **********************************************************************************
- *  #xx
- **********************************************************************************
- * $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/common.h $
- */
-
-/*********************************************************************************/
-/** @defgroup common common
- *  @{
- */
-
-/** @file common.h
-* \brief header file including common headers from various modules
-* \author App Firmware Team
-* 
-**********************************************************************************/
-#ifndef _COMMON_H_
-#define _COMMON_H_
-
-// Include common headers from various modules
-// !!! The include order is important !!!
-#include "cfg.h"
-#include "platform.h"
-#include "MCHP_CEC1302.h"
-#include "ARM_REG.h"
-/* Cortex-M4 processor and core peripherals */
-#include "core_cm4.h" 
-#include "MEC1322.h"
-
-#include "defs.h"
-#include "string.h"
-
-#include "kernel.h"
-#include "..\system\system.h"
-#include "..\debug\trace.h"
-#include "..\interrupt\interrupt.h"
-#include "..\timer\timer_app.h"
-
-#include "cec1302_crypto_api.h"
-
-#endif /*_COMMON_H_*/
-
-/**   @}
- */
-
-
+/*
+ **********************************************************************************
+* � 2013 Microchip Technology Inc. and its subsidiaries.
+* You may use this software and any derivatives exclusively with
+* Microchip products.
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
+* OF THESE TERMS.
+ **********************************************************************************
+ *  common.h
+ *      This is the header file including common headers from various modules
+ **********************************************************************************
+ *  $Revision: #1 $  $DateTime: 2016/04/08 10:18:28 $  $    $
+ *  Description: added ict module
+ **********************************************************************************
+ *  #xx
+ **********************************************************************************
+ * $File: //depot_pcs/FWEng/Release/projects/CEC1302_PLIB_CLIB/release5/Source/hw_blks/common/include/common.h $
+ */
+
+/*********************************************************************************/
+/** @defgroup common common
+ *  @{
+ */
+
+/** @file common.h
+* \brief header file including common headers from various modules
+* \author App Firmware Team
+* 
+**********************************************************************************/
+#ifndef _COMMON_H_
+#define _COMMON_H_
+
+// Include common headers from various modules
+// !!! The include order is important !!!
+#include "cfg.h"
+#include "platform.h"
+#include "MCHP_CEC1302.h"
+#include "ARM_REG.h"
+/* Cortex-M4 processor and core peripherals */
+#include "core_cm4.h" 
+
+#include "defs.h"
+#include "string.h"
+
+#include "kernel.h"
+#include "..\system\system.h"
+#include "..\debug\trace.h"
+#include "..\interrupt\irqhandler.h"
+#include "..\timer\timer_app.h"
+
+#include "cec1302_crypto_api.h"
+
+#endif /*_COMMON_H_*/
+
+/**   @}
+ */
+
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/common_lib.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/common_lib.h
index b97c5015e..6e34e02a7 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/common_lib.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/common_lib.h
@@ -1,64 +1,63 @@
-/*
- **********************************************************************************
-* � 2013 Microchip Technology Inc. and its subsidiaries.
-* You may use this software and any derivatives exclusively with
-* Microchip products.
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
-* OF THESE TERMS.
- **********************************************************************************
- *  common.h
- *      This is the header file including common headers from various modules
- **********************************************************************************
- *  $Revision: #1 $  $DateTime: 2015/12/23 15:37:58 $  $    $
- *  Description: added ict module
- **********************************************************************************
- *  #xx
- **********************************************************************************
- * $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/common_lib.h $
- */
-
-/*********************************************************************************/
-/** @defgroup common common
- *  @{
- */
-
-/** @file common.h
-* \brief header file including common headers from various modules
-* \author App Firmware Team
-* 
-**********************************************************************************/
-#ifndef _COMMON_LIB_H_
-#define _COMMON_LIB_H_
-
-// Include common headers from various modules
-// !!! The include order is important !!!
-#include "platform.h"
-#include "ARM_REG.h"
-#include "MCHP_CEC1302.h"
-/* Cortex-M4 processor and core peripherals */
-#include "core_cm4.h" 
-#include "MEC1322.h"
-#include "defs.h"
-#include "string.h"
-//_RB_#include "build.h"
-//_RB_#include "..\system\system.h"
-//_RB_#include "..\debug\trace.h"
-#include <stdbool.h>
-#endif /*_COMMON_LIB_H_*/
-
-/**   @}
- */
-
-
+/*
+ **********************************************************************************
+* � 2013 Microchip Technology Inc. and its subsidiaries.
+* You may use this software and any derivatives exclusively with
+* Microchip products.
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
+* OF THESE TERMS.
+ **********************************************************************************
+ *  common.h
+ *      This is the header file including common headers from various modules
+ **********************************************************************************
+ *  $Revision: #1 $  $DateTime: 2016/04/08 10:18:28 $  $    $
+ *  Description: added ict module
+ **********************************************************************************
+ *  #xx
+ **********************************************************************************
+ * $File: //depot_pcs/FWEng/Release/projects/CEC1302_PLIB_CLIB/release5/Source/hw_blks/common/include/common_lib.h $
+ */
+
+/*********************************************************************************/
+/** @defgroup common common
+ *  @{
+ */
+
+/** @file common.h
+* \brief header file including common headers from various modules
+* \author App Firmware Team
+* 
+**********************************************************************************/
+#ifndef _COMMON_LIB_H_
+#define _COMMON_LIB_H_
+
+// Include common headers from various modules
+// !!! The include order is important !!!
+#include "platform.h"
+#include "ARM_REG.h"
+#include "MCHP_CEC1302.h"
+/* Cortex-M4 processor and core peripherals */
+#include "core_cm4.h" 
+#include "defs.h"
+#include "string.h"
+//#include "build.h"
+//#include "..\system\system.h"
+//#include "..\debug\trace.h"
+#include <stdbool.h>
+#endif /*_COMMON_LIB_H_*/
+
+/**   @}
+ */
+
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/defs.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/defs.h
index d900fab29..e0de3eb49 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/defs.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/defs.h
@@ -1,54 +1,54 @@
-/*
- **********************************************************************************
-* � 2013 Microchip Technology Inc. and its subsidiaries.
-* You may use this software and any derivatives exclusively with
-* Microchip products.
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
-* OF THESE TERMS.
- **********************************************************************************
- *  defs.h
- *      This is the definition header file for generic usages
- **********************************************************************************
- *  #xx
- **********************************************************************************
- * $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/defs.h $
- */
-
-
-/*********************************************************************************/
-/** @defgroup defs defs
- *  @{
- */
-
-/** @file defs.h
-* \brief definition header file for generic usages
-* \author App Firmware Team
-* 
-**********************************************************************************/
-#ifndef _DEFS_H_
-#define _DEFS_H_
-
-/* bit operation MACRO, xvar could be byte, word or dword */
-#define mSET_BIT(x, xvar)		( xvar |= x )
-#define mCLR_BIT(x, xvar)		( xvar &= ~x )
-#define mGET_BIT(x, xvar)		( xvar & x )
-#define mCLR_SRC_BIT(x, xvar)	( xvar = x )
-#define mTOGGLE_BIT(x, xvar)	{if(mGET_BIT(x, xvar)){mCLR_BIT(x, xvar);}else{mSET_BIT(x, xvar);}}
-
-#endif /*_DEFS_H_*/
-
-/**   @}
- */
-
+/*
+ **********************************************************************************
+* � 2013 Microchip Technology Inc. and its subsidiaries.
+* You may use this software and any derivatives exclusively with
+* Microchip products.
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
+* OF THESE TERMS.
+ **********************************************************************************
+ *  defs.h
+ *      This is the definition header file for generic usages
+ **********************************************************************************
+ *  #xx
+ **********************************************************************************
+ * $File: //depot_pcs/FWEng/Release/projects/CEC1302_PLIB_CLIB/release5/Source/hw_blks/common/include/defs.h $
+ */
+
+
+/*********************************************************************************/
+/** @defgroup defs defs
+ *  @{
+ */
+
+/** @file defs.h
+* \brief definition header file for generic usages
+* \author App Firmware Team
+* 
+**********************************************************************************/
+#ifndef _DEFS_H_
+#define _DEFS_H_
+
+/* bit operation MACRO, xvar could be byte, word or dword */
+#define mSET_BIT(x, xvar)		( xvar |= x )
+#define mCLR_BIT(x, xvar)		( xvar &= ~x )
+#define mGET_BIT(x, xvar)		( xvar & x )
+#define mCLR_SRC_BIT(x, xvar)	( xvar = x )
+#define mTOGGLE_BIT(x, xvar)	{if(mGET_BIT(x, xvar)){mCLR_BIT(x, xvar);}else{mSET_BIT(x, xvar);}}
+
+#endif /*_DEFS_H_*/
+
+/**   @}
+ */
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/htimer/htimer.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/htimer/htimer.h
index cf94dd5eb..b39961219 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/htimer/htimer.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/htimer/htimer.h
@@ -1,111 +1,108 @@
-/*****************************************************************************
-* � 2015 Microchip Technology Inc. and its subsidiaries.
-* You may use this software and any derivatives exclusively with
-* Microchip products.
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
-* OF THESE TERMS.
-******************************************************************************
-
-Version Control Information (Perforce)
-******************************************************************************
-$Revision: #1 $ 
-$DateTime: 2015/12/17 01:09:00 $ 
-$Author: snakka $
-Last Change:  Updated for peripheral functions prefix p_
-******************************************************************************/
-/** @file btimer.h
-* \brief Hibernation Timer Peripheral Header file
-* \author jvasanth
-* 
-* This file is the header file for Hibernation Timer Peripheral 
-******************************************************************************/
-
-/** @defgroup Hibernation_Timer
- *  @{
- */
-
-#ifndef _HTIMER_H
-#define _HTIMER_H
-
-/******************************************************************************/
-/**  Logical Timer ID for APIs.
- * This is the timer IDs passed to Hibernation Timer function calls 
- *******************************************************************************/
-enum _PID_HTIMER_
-{
-	PID_HTIMER_0,	
-	PID_HTIMER_MAX	
-};
-
-#define HTIMER_MAX_INSTANCE			PID_HTIMER_MAX
-
-/* -------------------------------------------------------------------- */
-/*                Hibernation Timer APIs                                */
-/* -------------------------------------------------------------------- */
-/** Enables hibernation timer
- * @param htimer_id Hibernation Timer ID
- * @param preload_value	- 16-bit preload value 
- * @param resolution_mode 0 - resolution of 30.5us per LSB, 
- *        1 - resolution of 0.125s per LSB
- */
-void htimer_enable(uint8_t htimer_id, uint16_t preload_value, uint8_t resolution_mode);
-
-/** Disables the hibernation timer by programming the prelaod value as 0
- * @param htimer_id Hibernation Timer ID 
- */
-void htimer_disable(uint8_t htimer_id);
-
-
-/** Reloads new preload value for the hibernation timer
- * @param htimer_id Hibernation Timer ID
- * @param reload_value	- 16-bit preload value 
- */
-void htimer_reload(uint8_t htimer_id, uint16_t reload_value);
-
-
-/* -------------------------------------------------------------------- */
-/*             Hibernation Timer Peripheral Functions                   */
-/* -------------------------------------------------------------------- */
-/** Sets hibernation timer preload value
- * @param htimer_id Hibernation Timer ID
- * @param preload_value	- 16-bit preload value 
- */
-void p_htimer_preload_set(uint8_t htimer_id, uint16_t preload_value);
-
-/*_RB_ Added by RB. */
-uint16_t p_htimer_preload_get(uint8_t htimer_id);
-
-/** Sets hibernation timer resolution
- * @param htimer_id Hibernation Timer ID
- * @param resolution_mode 0 - resolution of 30.5us per LSB, 
- *        1 - resolution of 0.125s per LSB
- */
-void p_htimer_resolution_set(uint8_t htimer_id, uint8_t resolution_mode);
-
-
-/** Returns the Hibernation Timer current count value
- * @param htimer_id Hibernation Timer ID
- * @return 16-bit count value 
- */
-uint16_t p_htimer_count_get(uint8_t htimer_id);
-
-
-#endif // #ifndef _HTIMER_H
-
-/* end htimer.h */
-
-/**   @} //Peripherals Hibernation_Timer
- */
-
+/*****************************************************************************
+* � 2015 Microchip Technology Inc. and its subsidiaries.
+* You may use this software and any derivatives exclusively with
+* Microchip products.
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
+* OF THESE TERMS.
+******************************************************************************
+
+Version Control Information (Perforce)
+******************************************************************************
+$Revision: #1 $ 
+$DateTime: 2016/04/08 10:18:28 $ 
+$Author: pramans $
+Last Change:  Updated for peripheral functions prefix p_
+******************************************************************************/
+/** @file btimer.h
+* \brief Hibernation Timer Peripheral Header file
+* \author jvasanth
+* 
+* This file is the header file for Hibernation Timer Peripheral 
+******************************************************************************/
+
+/** @defgroup Hibernation_Timer
+ *  @{
+ */
+
+#ifndef _HTIMER_H
+#define _HTIMER_H
+
+/******************************************************************************/
+/**  Logical Timer ID for APIs.
+ * This is the timer IDs passed to Hibernation Timer function calls 
+ *******************************************************************************/
+enum _PID_HTIMER_
+{
+	PID_HTIMER_0,	
+	PID_HTIMER_MAX	
+};
+
+#define HTIMER_MAX_INSTANCE			PID_HTIMER_MAX
+
+/* -------------------------------------------------------------------- */
+/*                Hibernation Timer APIs                                */
+/* -------------------------------------------------------------------- */
+/** Enables hibernation timer
+ * @param htimer_id Hibernation Timer ID
+ * @param preload_value	- 16-bit preload value 
+ * @param resolution_mode 0 - resolution of 30.5us per LSB, 
+ *        1 - resolution of 0.125s per LSB
+ */
+void htimer_enable(uint8_t htimer_id, uint16_t preload_value, uint8_t resolution_mode);
+
+/** Disables the hibernation timer by programming the prelaod value as 0
+ * @param htimer_id Hibernation Timer ID 
+ */
+void htimer_disable(uint8_t htimer_id);
+
+
+/** Reloads new preload value for the hibernation timer
+ * @param htimer_id Hibernation Timer ID
+ * @param reload_value	- 16-bit preload value 
+ */
+void htimer_reload(uint8_t htimer_id, uint16_t reload_value);
+
+
+/* -------------------------------------------------------------------- */
+/*             Hibernation Timer Peripheral Functions                   */
+/* -------------------------------------------------------------------- */
+/** Sets hibernation timer preload value
+ * @param htimer_id Hibernation Timer ID
+ * @param preload_value	- 16-bit preload value 
+ */
+void p_htimer_preload_set(uint8_t htimer_id, uint16_t preload_value);
+
+/** Sets hibernation timer resolution
+ * @param htimer_id Hibernation Timer ID
+ * @param resolution_mode 0 - resolution of 30.5us per LSB, 
+ *        1 - resolution of 0.125s per LSB
+ */
+void p_htimer_resolution_set(uint8_t htimer_id, uint8_t resolution_mode);
+
+
+/** Returns the Hibernation Timer current count value
+ * @param htimer_id Hibernation Timer ID
+ * @return 16-bit count value 
+ */
+uint16_t p_htimer_count_get(uint8_t htimer_id);
+
+
+#endif // #ifndef _HTIMER_H
+
+/* end htimer.h */
+
+/**   @} //Peripherals Hibernation_Timer
+ */
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/htimer/htimer_api.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/htimer/htimer_api.c
index 1441bcf36..abc02fa90 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/htimer/htimer_api.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/htimer/htimer_api.c
@@ -1,112 +1,112 @@
-/*****************************************************************************
-* � 2015 Microchip Technology Inc. and its subsidiaries.
-* You may use this software and any derivatives exclusively with
-* Microchip products.
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
-* OF THESE TERMS.
-******************************************************************************
-
-Version Control Information (Perforce)
-******************************************************************************
-$Revision: #1 $ 
-$DateTime: 2015/12/17 01:09:00 $ 
-$Author: snakka $
-Last Change: Updated for peripheral functions prefix p_
-******************************************************************************/
-/** @file btimer_perphl.c
-* \brief Hibernation Timer API Source file
-* \author jvasanth
-* 
-* This file implements Hibernation Timer APIs   
-******************************************************************************/
-
-/** @defgroup Hibernation_Timer
- *  @{
- */
-
-#include "common_lib.h"
-#include "htimer.h"
-
-#ifdef PLIB_HTIMER_CHECK_ID
-
-/** Local helper that checks if logical Timer ID is valid.  
- * @param htimer_id Hibernation Timer ID 
- * @return uint8_t Non-zero(VALID), 0(Invalid)
- */
-static uint8_t htmr_valid(uint8_t htimer_id)
-{
-    if ( htimer_id < (PID_HTIMER_MAX ) ) {
-        return 1;
-    }
-    return 0;
-}
-
-#else
-
-
-/** This version of tmr_valid skips checking always returning 1.  
- *  Compiler may optimize it out.
- * @param htimer_id Hibernation Timer ID
- * @return uint8_t 1(VALID) 
- */
-static uint8_t htmr_valid(uint8_t htimer_id) { return 1; }
-
-#endif
-
-
-/** Enables hibernation timer
- * @param htimer_id Hibernation Timer ID
- * @param preload_value	- 16-bit preload value 
- * @param resolution_mode 0 - resolution of 30.5us per LSB, 
- *        1 - resolution of 0.125s per LSB
- */
-void htimer_enable(uint8_t htimer_id, uint16_t preload_value, uint8_t resolution_mode)
-{
-    if (htmr_valid(htimer_id)) 
-    {
-        p_htimer_preload_set(htimer_id, preload_value);
-        
-        p_htimer_resolution_set(htimer_id, resolution_mode);
-    }        
-}
-
-/** Disables the hibernation timer by programming the prelaod value as 0
- * @param htimer_id Hibernation Timer ID 
- */
-void htimer_disable(uint8_t htimer_id)
-{    
-    if (htmr_valid(htimer_id)) 
-    {
-        p_htimer_preload_set(htimer_id, 0);
-    }        
-}
-
-/** Reloads new preload value for the hibernation timer
- * @param htimer_id Hibernation Timer ID
- * @param reload_value	- 16-bit preload value 
- */
-void htimer_reload(uint8_t htimer_id, uint16_t reload_value)
-{    
-    if ( htmr_valid(htimer_id)) 
-    {
-        p_htimer_preload_set(htimer_id, reload_value);
-    }        
-}
-
-/* end htimer_api.c */
-
-/**   @} //APIs Hibernation_Timer
- */
-
+/*****************************************************************************
+* � 2015 Microchip Technology Inc. and its subsidiaries.
+* You may use this software and any derivatives exclusively with
+* Microchip products.
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
+* OF THESE TERMS.
+******************************************************************************
+
+Version Control Information (Perforce)
+******************************************************************************
+$Revision: #1 $ 
+$DateTime: 2016/04/08 10:18:28 $ 
+$Author: pramans $
+Last Change: Updated for peripheral functions prefix p_
+******************************************************************************/
+/** @file btimer_perphl.c
+* \brief Hibernation Timer API Source file
+* \author jvasanth
+* 
+* This file implements Hibernation Timer APIs   
+******************************************************************************/
+
+/** @defgroup Hibernation_Timer
+ *  @{
+ */
+
+#include "common_lib.h"
+#include "htimer.h"
+
+#ifdef PLIB_HTIMER_CHECK_ID
+
+/** Local helper that checks if logical Timer ID is valid.  
+ * @param htimer_id Hibernation Timer ID 
+ * @return uint8_t Non-zero(VALID), 0(Invalid)
+ */
+static uint8_t htmr_valid(uint8_t htimer_id)
+{
+    if ( htimer_id < (PID_HTIMER_MAX ) ) {
+        return 1;
+    }
+    return 0;
+}
+
+#else
+
+
+/** This version of tmr_valid skips checking always returning 1.  
+ *  Compiler may optimize it out.
+ * @param htimer_id Hibernation Timer ID
+ * @return uint8_t 1(VALID) 
+ */
+static uint8_t htmr_valid(uint8_t htimer_id) { return 1; }
+
+#endif
+
+
+/** Enables hibernation timer
+ * @param htimer_id Hibernation Timer ID
+ * @param preload_value	- 16-bit preload value 
+ * @param resolution_mode 0 - resolution of 30.5us per LSB, 
+ *        1 - resolution of 0.125s per LSB
+ */
+void htimer_enable(uint8_t htimer_id, uint16_t preload_value, uint8_t resolution_mode)
+{
+    if (htmr_valid(htimer_id)) 
+    {
+        p_htimer_preload_set(htimer_id, preload_value);
+        
+        p_htimer_resolution_set(htimer_id, resolution_mode);
+    }        
+}
+
+/** Disables the hibernation timer by programming the prelaod value as 0
+ * @param htimer_id Hibernation Timer ID 
+ */
+void htimer_disable(uint8_t htimer_id)
+{    
+    if (htmr_valid(htimer_id)) 
+    {
+        p_htimer_preload_set(htimer_id, 0);
+    }        
+}
+
+/** Reloads new preload value for the hibernation timer
+ * @param htimer_id Hibernation Timer ID
+ * @param reload_value	- 16-bit preload value 
+ */
+void htimer_reload(uint8_t htimer_id, uint16_t reload_value)
+{    
+    if ( htmr_valid(htimer_id)) 
+    {
+        p_htimer_preload_set(htimer_id, reload_value);
+    }        
+}
+
+/* end htimer_api.c */
+
+/**   @} //APIs Hibernation_Timer
+ */
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/htimer/htimer_perphl.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/htimer/htimer_perphl.c
index 64d632649..8320677fb 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/htimer/htimer_perphl.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/htimer/htimer_perphl.c
@@ -1,93 +1,87 @@
-/*****************************************************************************
-* � 2015 Microchip Technology Inc. and its subsidiaries.
-* You may use this software and any derivatives exclusively with
-* Microchip products.
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
-* OF THESE TERMS.
-******************************************************************************
-
-Version Control Information (Perforce)
-******************************************************************************
-$Revision: #1 $ 
-$DateTime: 2015/12/17 01:09:00 $ 
-$Author: snakka $
-Last Change: Updated for peripheral functions prefix p_
-******************************************************************************/
-/** @file btimer_perphl.c
-* \brief Hibernation Timer Peripheral Source file
-* \author jvasanth
-* 
-* This file implements Hibernation Timer Peripheral functions  
-******************************************************************************/
-
-/** @defgroup Hibernation_Timer
- *  @{
- */
-
-#include "common_lib.h"
-#include "htimer.h"
-
-/** Hibernation Timer Instance base addresses */
-static HTM_Type * const htmr_inst[HTIMER_MAX_INSTANCE] = {
-    CEC1302_HTM    
-};
-
-/** Sets hibernation timer preload value
- * @param htimer_id Hibernation Timer ID
- * @param preload_value	- 16-bit preload value 
- * @note Setting the preload with a non-zero value starts 
- * the hibernation timer to down count. Setting the preload 
- * to 0 disables the hibernation counter
- */
-void p_htimer_preload_set(uint8_t htimer_id, uint16_t preload_value)
-{
-    htmr_inst[htimer_id]->PRELOAD = preload_value;					
-}
-
-/** Sets hibernation timer resolution
- * @param htimer_id Hibernation Timer ID
- * @param resolution_mode 0 - resolution of 30.5us per LSB, 
- *        1 - resolution of 0.125s per LSB
- */
-void p_htimer_resolution_set(uint8_t htimer_id, uint8_t resolution_mode)
-{
-    htmr_inst[htimer_id]->CONTROL = resolution_mode;    
-}
-
-/** Returns the Hibernation Timer current count value
- * @param htimer_id Hibernation Timer ID
- * @return 16-bit count value 
- */
-uint16_t p_htimer_count_get(uint8_t htimer_id)
-{
-    uint16_t htimer_count;
-    
-    htimer_count = htmr_inst[htimer_id]->COUNT;
-    
-    return htimer_count;
-}
-
-/*_RB_ Added by RB. */
-uint16_t p_htimer_preload_get(uint8_t htimer_id)
-{
-    return htmr_inst[htimer_id]->PRELOAD;
-}
-
-
-/* end htimer_perphl.c */
-
-/**   @} //Peripheral Hibernation_Timer
- */
-
+/*****************************************************************************
+* � 2015 Microchip Technology Inc. and its subsidiaries.
+* You may use this software and any derivatives exclusively with
+* Microchip products.
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
+* OF THESE TERMS.
+******************************************************************************
+
+Version Control Information (Perforce)
+******************************************************************************
+$Revision: #1 $ 
+$DateTime: 2016/04/08 10:18:28 $ 
+$Author: pramans $
+Last Change: Updated for peripheral functions prefix p_
+******************************************************************************/
+/** @file btimer_perphl.c
+* \brief Hibernation Timer Peripheral Source file
+* \author jvasanth
+* 
+* This file implements Hibernation Timer Peripheral functions  
+******************************************************************************/
+
+/** @defgroup Hibernation_Timer
+ *  @{
+ */
+
+#include "common_lib.h"
+#include "htimer.h"
+
+/** Hibernation Timer Instance base addresses */
+static HTM_Type * const htmr_inst[HTIMER_MAX_INSTANCE] = {
+    CEC1302_HTM    
+};
+
+/** Sets hibernation timer preload value
+ * @param htimer_id Hibernation Timer ID
+ * @param preload_value	- 16-bit preload value 
+ * @note Setting the preload with a non-zero value starts 
+ * the hibernation timer to down count. Setting the preload 
+ * to 0 disables the hibernation counter
+ */
+void p_htimer_preload_set(uint8_t htimer_id, uint16_t preload_value)
+{
+    htmr_inst[htimer_id]->PRELOAD = preload_value;					
+}
+
+/** Sets hibernation timer resolution
+ * @param htimer_id Hibernation Timer ID
+ * @param resolution_mode 0 - resolution of 30.5us per LSB, 
+ *        1 - resolution of 0.125s per LSB
+ */
+void p_htimer_resolution_set(uint8_t htimer_id, uint8_t resolution_mode)
+{
+    htmr_inst[htimer_id]->CONTROL = resolution_mode;    
+}
+
+/** Returns the Hibernation Timer current count value
+ * @param htimer_id Hibernation Timer ID
+ * @return 16-bit count value 
+ */
+uint16_t p_htimer_count_get(uint8_t htimer_id)
+{
+    uint16_t htimer_count;
+    
+    htimer_count = htmr_inst[htimer_id]->COUNT;
+    
+    return htimer_count;
+}
+
+
+/* end htimer_perphl.c */
+
+/**   @} //Peripheral Hibernation_Timer
+ */
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/interrupt/interrupt.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/interrupt/interrupt.h
index 2b30af9eb..e5b8a3d5f 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/interrupt/interrupt.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/interrupt/interrupt.h
@@ -1,1176 +1,992 @@
-/****************************************************************************
-* � 2013 Microchip Technology Inc. and its subsidiaries.
-* You may use this software and any derivatives exclusively with
-* Microchip products.
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
-* OF THESE TERMS.
-*/
-
-/** @defgroup interrupt interrupt
- *  @{
- */
-/** @file interrupt.h
- \brief This is the header file for interrupt.c
- This program is designed to allow the other C programs to be able to use this component
-
- There are entry points for all C wrapper API implementation
-
-<b>Platform:</b> This is ARC-based component 
-
-<b>Toolset:</b> Metaware IDE(8.5.1)
-<b>Reference:</b> smsc_reusable_fw_requirement.doc */
-
-/*******************************************************************************
- *  SMSC version control information (Perforce):
- *
- *  FILE:     $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/kernel/skern/source/interrupt/interrupt.h $
- *  REVISION: $Revision: #1 $
- *  DATETIME: $DateTime: 2015/12/23 15:37:58 $
- *  AUTHOR:   $Author: akrishnan $
- *
- *  Revision history (latest first):
- *      #xx
- ***********************************************************************************
- */
-
-#ifndef _INTERRUPT_H_
-#define _INTERRUPT_H_
-
-
-/* public function prototypes */
-void interrupt_block_init(void);
-void null_handler(void);
-
-/* macro for interrupt control */
-/* 16-bit timers interrupt control */
-#define sbit_TIMER0				( 1UL << 0UL )
-#define sbit_TIMER1				( 1UL << 1UL )
-#define sbit_TIMER2				( 1UL << 2UL )
-#define sbit_TIMER3				( 1UL << 3Ul )
-
-#define disable_timer0_irq()	mCLR_BIT(sbit_TIMER0, MMCR_EC_GIRQ23_ENABLE_SET)
-#define enable_timer0_irq()		mSET_BIT(sbit_TIMER0, MMCR_EC_GIRQ23_ENABLE_SET)
-#define clear_timer0_source()	mCLR_SRC_BIT(sbit_TIMER0, MMCR_EC_GIRQ23_SOURCE)
-#define get_timer0_source()	    mGET_BIT(sbit_TIMER0, MMCR_EC_GIRQ23_SOURCE)
-
-#define disable_timer1_irq()	mCLR_BIT(sbit_TIMER1, MMCR_EC_GIRQ23_ENABLE_SET)
-#define enable_timer1_irq()		mSET_BIT(sbit_TIMER1, MMCR_EC_GIRQ23_ENABLE_SET)
-#define clear_timer1_source()	mCLR_SRC_BIT(sbit_TIMER1, MMCR_EC_GIRQ23_SOURCE)
-#define get_timer1_source()	    mGET_BIT(sbit_TIMER1, MMCR_EC_GIRQ23_SOURCE)
-
-#define disable_timer2_irq()	mCLR_BIT(sbit_TIMER2, MMCR_EC_GIRQ23_ENABLE_SET)
-#define enable_timer2_irq()		mSET_BIT(sbit_TIMER2, MMCR_EC_GIRQ23_ENABLE_SET)
-#define clear_timer2_source()	mCLR_SRC_BIT(sbit_TIMER2, MMCR_EC_GIRQ23_SOURCE)
-#define get_timer2_source()	    mGET_BIT(sbit_TIMER2, MMCR_EC_GIRQ23_SOURCE)
-
-#define disable_timer3_irq()	mCLR_BIT(sbit_TIMER3, MMCR_EC_GIRQ23_ENABLE_SET)
-#define enable_timer3_irq()		mSET_BIT(sbit_TIMER3, MMCR_EC_GIRQ23_ENABLE_SET)
-#define clear_timer3_source()	mCLR_SRC_BIT(sbit_TIMER3, MMCR_EC_GIRQ23_SOURCE)
-#define get_timer3_source()	    mGET_BIT(sbit_TIMER3, MMCR_EC_GIRQ23_SOURCE)
-
-
-/* hibernation timers interrupt control */
-#define sbit_HTIMER0			( 1UL << 20 )
-#define sbit_HTIMER1			b_bit14
-
-#define disable_htimer0_irq()	mCLR_BIT(sbit_HTIMER0, MMCR_EC_GIRQ17_ENABLE_SET)
-#define enable_htimer0_irq()	mSET_BIT(sbit_HTIMER0, MMCR_EC_GIRQ17_ENABLE_SET)
-#define clear_htimer0_source()	mCLR_SRC_BIT(sbit_HTIMER0, MMCR_EC_GIRQ17_SOURCE)
-#define get_htimer0_source()	mGET_BIT(sbit_HTIMER0, MMCR_EC_GIRQ17_SOURCE)
-
-#define disable_htimer1_irq()	mCLR_BIT(sbit_HTIMER1, MMCR_EC_GIRQ23_ENABLE_SET)
-#define enable_htimer1_irq()	mSET_BIT(sbit_HTIMER1, MMCR_EC_GIRQ23_ENABLE_SET)
-#define clear_htimer1_source()	mCLR_SRC_BIT(sbit_HTIMER1, MMCR_EC_GIRQ23_SOURCE)
-#define get_htimer1_source()	mGET_BIT(sbit_HTIMER1, MMCR_EC_GIRQ23_SOURCE)
-
-/* RTC  interrupt control */
-#define b_bit18 (1 << 18)
-#define b_bit19 (1 << 19)
-#define sbit_RTC_INT                   b_bit18
-#define disable_rtc_irq()              mCLR_BIT(sbit_RTC_INT, MMCR_EC_GIRQ17_ENABLE_SET)
-#define enable_rtc_irq()               mSET_BIT(sbit_RTC_INT, MMCR_EC_GIRQ17_ENABLE_SET)
-#define clear_rtc_irq_source()         mCLR_SRC_BIT(sbit_RTC_INT, MMCR_EC_GIRQ17_ENABLE_SET)
-#define get_rtc_irq_source()           mGET_BIT(sbit_RTC_INT, MMCR_EC_GIRQ17_ENABLE_SET)
-/* RTC  alarm interrupt control */
-#define sbit_RTC_ALM_INT               b_bit19
-#define disable_rtc_alm_irq()          mCLR_BIT(sbit_RTC_ALM_INT, MMCR_EC_GIRQ17_ENABLE_SET)
-#define enable_rtc_alm_irq()           mSET_BIT(sbit_RTC_ALM_INT, MMCR_EC_GIRQ17_ENABLE_SET)
-#define clear_rtc_irq_alm_source()     mCLR_SRC_BIT(sbit_RTC_ALM_INT, MMCR_EC_GIRQ17_ENABLE_SET)
-#define get_rtc_irq_alm_source()       mGET_BIT(sbit_RTC_ALM_INT, MMCR_EC_GIRQ17_ENABLE_SET)
-
-/* week timer interrupt control */
-#define sbit_WKTIMER			b_bit7
-
-#define disable_wktimer_irq()	mCLR_BIT(sbit_WKTIMER, MMCR_EC_GIRQ23_ENABLE_SET)
-#define enable_wktimer_irq()	mSET_BIT(sbit_WKTIMER, MMCR_EC_GIRQ23_ENABLE_SET)
-#define clear_wktimer_source()	mCLR_SRC_BIT(sbit_WKTIMER, MMCR_EC_GIRQ23_SOURCE)
-#define get_wktimer_source()	mGET_BIT(sbit_WKTIMER, MMCR_EC_GIRQ23_SOURCE)
-
-
-/* scan matrix interrupt control */
-#define sbit_SCANNER			b_bit16
-#define disable_scanner_irq()	mCLR_BIT(sbit_SCANNER, MMCR_EC_GIRQ18_ENABLE_SET)
-#define enable_scanner_irq()	mSET_BIT(sbit_SCANNER, MMCR_EC_GIRQ18_ENABLE_SET)
-#define clear_scanner_source()	mCLR_SRC_BIT(sbit_SCANNER, MMCR_EC_GIRQ18_SOURCE)
-#define get_scanner_source()	mGET_BIT(sbit_SCANNER, MMCR_EC_GIRQ18_SOURCE)
-
-
-/* PS2 interrupt control */
-/* PS2 activity interrupt */
-#define sbit_PS2_ACT_0			  b_bit13
-#define sbit_PS2_ACT_1			  b_bit14
-#define sbit_PS2_ACT_2			  b_bit15
-/* PS2 wakeup interrupt: detect start bit */
-#define sbit_PS2_WK_0A			  b_bit17
-#define sbit_PS2_WK_1B			  b_bit20
-#define sbit_PS2_WK_2			  b_bit21
-
-/* PS2 activity interrupt control */
-#define disable_ps2_act_0_irq()	  mCLR_BIT(sbit_PS2_ACT_0, MMCR_EC_GIRQ19_ENABLE_SET)
-#define enable_ps2_act_0_irq()	  mSET_BIT(sbit_PS2_ACT_0, MMCR_EC_GIRQ19_ENABLE_SET)
-#define clear_ps2_act_0_source()  mCLR_SRC_BIT(sbit_PS2_ACT_0, MMCR_EC_GIRQ19_SOURCE)
-#define get_ps2_act_0_source()    mGET_BIT(sbit_PS2_ACT_0, MMCR_EC_GIRQ19_SOURCE)
-
-#define disable_ps2_act_1_irq()	  mCLR_BIT(sbit_PS2_ACT_1, MMCR_EC_GIRQ19_ENABLE_SET)
-#define enable_ps2_act_1_irq()	  mSET_BIT(sbit_PS2_ACT_1, MMCR_EC_GIRQ19_ENABLE_SET)
-#define clear_ps2_act_1_source()  mCLR_SRC_BIT(sbit_PS2_ACT_1, MMCR_EC_GIRQ19_SOURCE)
-#define get_ps2_act_1_source()    mGET_BIT(sbit_PS2_ACT_1, MMCR_EC_GIRQ19_SOURCE)
-
-#define disable_ps2_act_2_irq()	  mCLR_BIT(sbit_PS2_ACT_2, MMCR_EC_GIRQ19_ENABLE_SET)
-#define enable_ps2_act_2_irq()	  mSET_BIT(sbit_PS2_ACT_2, MMCR_EC_GIRQ19_ENABLE_SET)
-#define clear_ps2_act_2_source()  mCLR_SRC_BIT(sbit_PS2_ACT_2, MMCR_EC_GIRQ19_SOURCE)
-#define get_ps2_act_2_source()    mGET_BIT(sbit_PS2_ACT_2, MMCR_EC_GIRQ19_SOURCE)
-
-/* PS2 wakeup interrupt control */
-#define disable_ps2_wk_0_irq()	  mCLR_BIT(sbit_PS2_WK_0A, MMCR_EC_GIRQ19_ENABLE_SET)
-#define enable_ps2_wk_0_irq()	  mSET_BIT(sbit_PS2_WK_0A, MMCR_EC_GIRQ19_ENABLE_SET)
-#define clear_ps2_wk_0_source()   mCLR_SRC_BIT(sbit_PS2_WK_0A, MMCR_EC_GIRQ19_SOURCE)
-#define get_ps2_wk_0_source()     mGET_BIT(sbit_PS2_WK_0A, MMCR_EC_GIRQ19_SOURCE)
-
-#define disable_ps2_wk_1_irq()	  mCLR_BIT(sbit_PS2_WK_1B, MMCR_EC_GIRQ19_ENABLE_SET)
-#define enable_ps2_wk_1_irq()	  mSET_BIT(sbit_PS2_WK_1B, MMCR_EC_GIRQ19_ENABLE_SET)
-#define clear_ps2_wk_1_source()   mCLR_SRC_BIT(sbit_PS2_WK_1B, MMCR_EC_GIRQ19_SOURCE)
-#define get_ps2_wk_1_source()     mGET_BIT(sbit_PS2_WK_1B, MMCR_EC_GIRQ19_SOURCE)
-
-#define disable_ps2_wk_2_irq()	  mCLR_BIT(sbit_PS2_WK_2, MMCR_EC_GIRQ19_ENABLE_SET)
-#define enable_ps2_wk_2_irq()	  mSET_BIT(sbit_PS2_WK_2, MMCR_EC_GIRQ19_ENABLE_SET)
-#define clear_ps2_wk_2_source()   mCLR_SRC_BIT(sbit_PS2_WK_2, MMCR_EC_GIRQ19_SOURCE)
-#define get_ps2_wk_2_source()     mGET_BIT(sbit_PS2_WK_2, MMCR_EC_GIRQ19_SOURCE)
-
-
-/* ICT interrupt control */
-/* capture 0~5 interrupt */
-#define sbit_ICT_CAPTURE0		  b_bit17
-#define sbit_ICT_CAPTURE1		  b_bit18
-#define sbit_ICT_CAPTURE2		  b_bit19
-#define sbit_ICT_CAPTURE3		  b_bit20
-#define sbit_ICT_CAPTURE4		  b_bit21
-#define sbit_ICT_CAPTURE5		  b_bit22
-
-/* capture 0 interrupt control */
-#define disable_capture0_irq()	  mCLR_BIT(sbit_ICT_CAPTURE0, MMCR_EC_GIRQ23_ENABLE_SET)
-#define enable_capture0_irq()	  mSET_BIT(sbit_ICT_CAPTURE0, MMCR_EC_GIRQ23_ENABLE_SET)
-#define clear_capture0_source()	  mCLR_SRC_BIT(sbit_ICT_CAPTURE0, MMCR_EC_GIRQ23_SOURCE)
-#define get_capture0_source()	  mGET_BIT(sbit_ICT_CAPTURE0, MMCR_EC_GIRQ23_SOURCE)
-
-
-/* SMBus interrupt control */
-
-
-/* GPIO interrupt control */
-
-
-/* BC link interrupt control */
-/* bclink A~D interrupt */
-#define sbit_BCLINK_A_BUSY		  b_bit0
-#define sbit_BCLINK_A_ERR		  b_bit1
-#define sbit_BCLINK_A_INT		  b_bit2
-#define sbit_BCLINK_B_BUSY		  b_bit3
-#define sbit_BCLINK_B_ERR		  b_bit4
-#define sbit_BCLINK_B_INT		  b_bit5
-#define sbit_BCLINK_C_BUSY		  b_bit6
-#define sbit_BCLINK_C_ERR		  b_bit7
-#define sbit_BCLINK_C_INT		  b_bit8
-#define sbit_BCLINK_D_BUSY		  b_bit9
-#define sbit_BCLINK_D_ERR		  b_bit10
-#define sbit_BCLINK_D_INT		  b_bit11
-
-/* bclink B interrupt control */
-#define disable_bclink_b_busy_irq()		mCLR_BIT(sbit_BCLINK_B_BUSY, MMCR_EC_GIRQ18_ENABLE_SET)
-#define enable_bclink_b_busy_irq()		mSET_BIT(sbit_BCLINK_B_BUSY, MMCR_EC_GIRQ18_ENABLE_SET)
-#define clear_bclink_b_busy_source()    mCLR_SRC_BIT(sbit_BCLINK_B_BUSY, MMCR_EC_GIRQ18_SOURCE)
-#define get_bclink_b_busy_source()      mGET_BIT(sbit_BCLINK_B_BUSY, MMCR_EC_GIRQ18_SOURCE)
-
-#define disable_bclink_b_err_irq()		mCLR_BIT(sbit_BCLINK_B_ERR, MMCR_EC_GIRQ18_ENABLE_SET)
-#define enable_bclink_b_err_irq()		mSET_BIT(sbit_BCLINK_B_ERR, MMCR_EC_GIRQ18_ENABLE_SET)
-#define clear_bclink_b_err_source()     mCLR_SRC_BIT(sbit_BCLINK_B_ERR, MMCR_EC_GIRQ18_SOURCE)
-#define get_bclink_b_err_source()       mGET_BIT(sbit_BCLINK_B_ERR, MMCR_EC_GIRQ18_SOURCE)
-
-#define disable_bclink_b_int_irq()		mCLR_BIT(sbit_BCLINK_B_INT, MMCR_EC_GIRQ18_ENABLE_SET)
-#define enable_bclink_b_int_irq()		mSET_BIT(sbit_BCLINK_B_INT, MMCR_EC_GIRQ18_ENABLE_SET)
-#define clear_bclink_b_int_source()     mCLR_SRC_BIT(sbit_BCLINK_B_INT, MMCR_EC_GIRQ18_SOURCE)
-#define get_bclink_b_int_source()       mGET_BIT(sbit_BCLINK_B_INT, MMCR_EC_GIRQ18_SOURCE)
-
-/* UART interrupt control */
-#define sbit_UART_INT                   b_bit0
-
-#define disable_uart_irq()              mCLR_BIT(sbit_UART_INT, MMCR_EC_GIRQ15_ENABLE_SET)
-#define enable_uart_irq()               mSET_BIT(sbit_UART_INT, MMCR_EC_GIRQ15_ENABLE_SET)
-#define clear_uart_irq_source()         mCLR_SRC_BIT(sbit_UART_INT, MMCR_EC_GIRQ15_SOURCE)
-#define get_uart_irq_source()           mGET_BIT(sbit_UART_INT, MMCR_EC_GIRQ15_SOURCE)
-
-// GIRQ IDs for EC Interrupt Aggregator
-enum MEC_GIRQ_IDS
-{
-    MEC_GIRQ08_ID = 0,
-    MEC_GIRQ09_ID,                  
-    MEC_GIRQ10_ID,                  
-    MEC_GIRQ11_ID,                  
-    MEC_GIRQ12_ID,                  
-    MEC_GIRQ13_ID,                  
-    MEC_GIRQ14_ID,                  
-    MEC_GIRQ15_ID,                  
-    MEC_GIRQ16_ID,                  
-    MEC_GIRQ17_ID,                  
-    MEC_GIRQ18_ID,                  
-    MEC_GIRQ19_ID,                  
-    MEC_GIRQ20_ID,                  
-    MEC_GIRQ21_ID,                  
-    MEC_GIRQ22_ID,                  
-    MEC_GIRQ23_ID,                                   
-    MEC_GIRQ_ID_MAX
-};
-
-//Bitmask of GIRQ in ECIA Block Registers
-#define MEC_GIRQ08_BITMASK          (1UL << (MEC_GIRQ08_ID + 8))
-#define MEC_GIRQ09_BITMASK          (1UL << (MEC_GIRQ09_ID + 8))  
-#define MEC_GIRQ10_BITMASK          (1UL << (MEC_GIRQ10_ID + 8))  
-#define MEC_GIRQ11_BITMASK          (1UL << (MEC_GIRQ11_ID + 8)) 
-#define MEC_GIRQ12_BITMASK          (1UL << (MEC_GIRQ12_ID + 8)) 
-#define MEC_GIRQ13_BITMASK          (1UL << (MEC_GIRQ13_ID + 8)) 
-#define MEC_GIRQ14_BITMASK          (1UL << (MEC_GIRQ14_ID + 8)) 
-#define MEC_GIRQ15_BITMASK          (1UL << (MEC_GIRQ15_ID + 8)) 
-#define MEC_GIRQ16_BITMASK          (1UL << (MEC_GIRQ16_ID + 8)) 
-#define MEC_GIRQ17_BITMASK          (1UL << (MEC_GIRQ17_ID + 8)) 
-#define MEC_GIRQ18_BITMASK          (1UL << (MEC_GIRQ18_ID + 8)) 
-#define MEC_GIRQ19_BITMASK          (1UL << (MEC_GIRQ19_ID + 8)) 
-#define MEC_GIRQ20_BITMASK          (1UL << (MEC_GIRQ20_ID + 8)) 
-#define MEC_GIRQ21_BITMASK          (1UL << (MEC_GIRQ21_ID + 8)) 
-#define MEC_GIRQ22_BITMASK          (1UL << (MEC_GIRQ22_ID + 8)) 
-#define MEC_GIRQ23_BITMASK          (1UL << (MEC_GIRQ23_ID + 8)) 
-
-#define INTERRUPT_MODE_ALL_AGGREGATED        (0u)
-#define INTERRUPT_MODE_DIRECT                (1u)
-
-// Bit map of GIRQs whose sources can be directly connected to the NVIC
-// GIRQs 12 - 18, 23
-#define ECIA_GIRQ_DIRECT_BITMAP     (0x0087F000ul)
-
-/*
- *  n = b[7:0]   = zero-based direct mapped NVIC ID
- *  m = b[15:8]  = zero-based aggregated NVIC ID
- *  a = b[23:16] = block Aggregator register block ID
- *  b = b[31:24] = block bit position in Aggregator registers
-*/
-#define IROUTE(b,a,m,n) 	(((uint32_t)(n)&0xFFul) + \
-                            (((uint32_t)(m)&0xFFul)<<8u) + \
-                            ((((uint32_t)(a)-8ul)&0x0F)<<16u) + \
-                            (((uint32_t)(b)&0x1Ful)<<24))
-
-#define ECIA_NVIC_ID_BITPOS             (0u)
-#define ECIA_IA_NVIC_ID_BITPOS          (8u)
-#define ECIA_GIRQ_ID_BITPOS             (16u)
-#define ECIA_GIRQ_BIT_BITPOS            (24u)
-
-//
-// GIRQ08
-//
-#define GPIO_0140_IROUTE                IROUTE(0,8,57,57)
-#define GPIO_0141_IROUTE                IROUTE(1,8,57,57)
-#define GPIO_0142_IROUTE                IROUTE(2,8,57,57)
-#define GPIO_0143_IROUTE                IROUTE(3,8,57,57)
-#define GPIO_0144_IROUTE                IROUTE(4,8,57,57)
-#define GPIO_0145_IROUTE                IROUTE(5,8,57,57)
-#define GPIO_0147_IROUTE                IROUTE(7,8,57,57)
-//
-#define GPIO_0150_IROUTE                IROUTE(8,8,57,57)
-#define GPIO_0151_IROUTE                IROUTE(9,8,57,57)
-#define GPIO_0152_IROUTE                IROUTE(10,8,57,57)
-#define GPIO_0153_IROUTE                IROUTE(11,8,57,57)
-#define GPIO_0154_IROUTE                IROUTE(12,8,57,57)
-#define GPIO_0155_IROUTE                IROUTE(13,8,57,57)
-#define GPIO_0156_IROUTE                IROUTE(14,8,57,57)
-#define GPIO_0157_IROUTE                IROUTE(15,8,57,57)
-//
-#define GPIO_0160_IROUTE                IROUTE(16,8,57,57)
-#define GPIO_0161_IROUTE                IROUTE(17,8,57,57)
-#define GPIO_0162_IROUTE                IROUTE(18,8,57,57)
-#define GPIO_0163_IROUTE                IROUTE(19,8,57,57)
-#define GPIO_0164_IROUTE                IROUTE(20,8,57,57)
-#define GPIO_0165_IROUTE                IROUTE(21,8,57,57)
-#define GPIO_0166_IROUTE                IROUTE(22,8,57,57)
-#define GPIO_0167_IROUTE                IROUTE(23,8,57,57)
-
-//
-// GIRQ09
-//
-#define GPIO_0100_IROUTE                IROUTE(0,9,58,58)
-#define GPIO_0101_IROUTE                IROUTE(1,9,58,58)
-#define GPIO_0102_IROUTE                IROUTE(2,9,58,58)
-#define GPIO_0103_IROUTE                IROUTE(3,9,58,58)
-#define GPIO_0104_IROUTE                IROUTE(4,9,58,58)
-#define GPIO_0105_IROUTE                IROUTE(5,9,58,58)
-#define GPIO_0105_IROUTE                IROUTE(5,9,58,58)
-#define GPIO_0107_IROUTE                IROUTE(7,9,58,58)
-//
-#define GPIO_0110_IROUTE                IROUTE(8,9,58,58)
-#define GPIO_0111_IROUTE                IROUTE(9,9,58,58)
-#define GPIO_0112_IROUTE                IROUTE(10,9,58,58)
-#define GPIO_0113_IROUTE                IROUTE(11,9,58,58)
-#define GPIO_0114_IROUTE                IROUTE(12,9,58,58)
-#define GPIO_0115_IROUTE                IROUTE(13,9,58,58)
-#define GPIO_0116_IROUTE                IROUTE(14,9,58,58)
-#define GPIO_0117_IROUTE                IROUTE(15,9,58,58)
-//
-#define GPIO_0120_IROUTE                IROUTE(16,9,58,58)
-#define GPIO_0121_IROUTE                IROUTE(17,9,58,58)
-#define GPIO_0122_IROUTE                IROUTE(18,9,58,58)
-#define GPIO_0124_IROUTE                IROUTE(20,9,58,58)
-#define GPIO_0125_IROUTE                IROUTE(21,9,58,58)
-#define GPIO_0126_IROUTE                IROUTE(22,9,58,58)
-#define GPIO_0127_IROUTE                IROUTE(23,9,58,58)
-//
-#define GPIO_0130_IROUTE                IROUTE(24,9,58,58)
-#define GPIO_0131_IROUTE                IROUTE(25,9,58,58)
-#define GPIO_0132_IROUTE                IROUTE(26,9,58,58)
-#define GPIO_0133_IROUTE                IROUTE(27,9,58,58)
-#define GPIO_0134_IROUTE                IROUTE(28,9,58,58)
-#define GPIO_0135_IROUTE                IROUTE(29,9,58,58)
-#define GPIO_0136_IROUTE                IROUTE(30,9,58,58)
-
-//
-// GIRQ10
-//
-#define GPIO_0040_IROUTE                IROUTE(0,10,59,59)
-#define GPIO_0041_IROUTE                IROUTE(1,10,59,59)
-#define GPIO_0042_IROUTE                IROUTE(2,10,59,59)
-#define GPIO_0043_IROUTE                IROUTE(3,10,59,59)
-#define GPIO_0044_IROUTE                IROUTE(4,10,59,59)
-#define GPIO_0045_IROUTE                IROUTE(5,10,59,59)
-#define GPIO_0045_IROUTE                IROUTE(5,10,59,59)
-#define GPIO_0047_IROUTE                IROUTE(7,10,59,59)
-//
-#define GPIO_0050_IROUTE                IROUTE(8,10,59,59)
-#define GPIO_0051_IROUTE                IROUTE(9,10,59,59)
-#define GPIO_0052_IROUTE                IROUTE(10,10,59,59)
-#define GPIO_0053_IROUTE                IROUTE(11,10,59,59)
-#define GPIO_0054_IROUTE                IROUTE(12,10,59,59)
-#define GPIO_0055_IROUTE                IROUTE(13,10,59,59)
-#define GPIO_0056_IROUTE                IROUTE(14,10,59,59)
-#define GPIO_0057_IROUTE                IROUTE(15,10,59,59)
-//
-#define GPIO_0060_IROUTE                IROUTE(16,10,59,59)
-#define GPIO_0061_IROUTE                IROUTE(17,10,59,59)
-#define GPIO_0062_IROUTE                IROUTE(18,10,59,59)
-#define GPIO_0063_IROUTE                IROUTE(19,10,59,59)
-#define GPIO_0064_IROUTE                IROUTE(20,10,59,59)
-#define GPIO_0065_IROUTE                IROUTE(21,10,59,59)
-#define GPIO_0066_IROUTE                IROUTE(22,10,59,59)
-#define GPIO_0067_IROUTE                IROUTE(23,10,59,59)
-//
-#define GPIO_0070_IROUTE                IROUTE(24,10,59,59)
-#define GPIO_0071_IROUTE                IROUTE(25,10,59,59)
-#define GPIO_0072_IROUTE                IROUTE(26,10,59,59)
-#define GPIO_0073_IROUTE                IROUTE(27,10,59,59)
-#define GPIO_0074_IROUTE                IROUTE(28,10,59,59)
-#define GPIO_0075_IROUTE                IROUTE(29,10,59,59)
-#define GPIO_0076_IROUTE                IROUTE(30,10,59,59)
-
-//
-// GIRQ11
-//
-#define GPIO_0000_IROUTE                IROUTE(0,11,60,60)
-#define GPIO_0001_IROUTE                IROUTE(1,11,60,60)
-#define GPIO_0002_IROUTE                IROUTE(2,11,60,60)
-#define GPIO_0003_IROUTE                IROUTE(3,11,60,60)
-#define GPIO_0004_IROUTE                IROUTE(4,11,60,60)
-#define GPIO_0005_IROUTE                IROUTE(5,11,60,60)
-#define GPIO_0006_IROUTE                IROUTE(6,11,60,60)
-#define GPIO_0007_IROUTE                IROUTE(7,11,60,60)
-//
-#define GPIO_0010_IROUTE                IROUTE(8,11,60,60)
-#define GPIO_0011_IROUTE                IROUTE(9,11,60,60)
-#define GPIO_0012_IROUTE                IROUTE(10,11,60,60)
-#define GPIO_0013_IROUTE                IROUTE(11,11,60,60)
-#define GPIO_0014_IROUTE                IROUTE(12,11,60,60)
-#define GPIO_0015_IROUTE                IROUTE(13,11,60,60)
-#define GPIO_0016_IROUTE                IROUTE(14,11,60,60)
-#define GPIO_0017_IROUTE                IROUTE(15,11,60,60)
-//
-#define GPIO_0020_IROUTE                IROUTE(16,11,60,60)
-#define GPIO_0021_IROUTE                IROUTE(17,11,60,60)
-#define GPIO_0022_IROUTE                IROUTE(18,11,60,60)
-#define GPIO_0023_IROUTE                IROUTE(19,11,60,60)
-#define GPIO_0024_IROUTE                IROUTE(20,11,60,60)
-#define GPIO_0025_IROUTE                IROUTE(21,11,60,60)
-#define GPIO_0026_IROUTE                IROUTE(22,11,60,60)
-#define GPIO_0027_IROUTE                IROUTE(23,11,60,60)
-//
-#define GPIO_0030_IROUTE                IROUTE(24,11,60,60)
-#define GPIO_0031_IROUTE                IROUTE(25,11,60,60)
-#define GPIO_0032_IROUTE                IROUTE(26,11,60,60)
-#define GPIO_0033_IROUTE                IROUTE(27,11,60,60)
-#define GPIO_0034_IROUTE                IROUTE(28,11,60,60)
-#define GPIO_0035_IROUTE                IROUTE(29,11,60,60)
-#define GPIO_0036_IROUTE                IROUTE(30,11,60,60)
-
-//
-// GIRQ12
-//
-#define SMB0_IROUTE                     IROUTE(0,12,61,0)
-#define SMB1_IROUTE                     IROUTE(1,12,61,1)
-#define SMB2_IROUTE                     IROUTE(2,12,61,2)
-#define SMB3_IROUTE                     IROUTE(3,12,61,3)
-// SMB wakes have no direct connection to NVIC, always aggregated
-#define SMB0_WAKE_IROUTE                IROUTE(4,12,61,61)
-#define SMB1_WAKE_IROUTE                IROUTE(5,12,61,61)
-#define SMB2_WAKE_IROUTE                IROUTE(6,12,61,61)
-#define SMB3_WAKE_IROUTE                IROUTE(7,12,61,61)
-#define SMB4_WAKE_IROUTE                IROUTE(8,12,61,61)
-
-//
-// GIRQ13
-//
-#define DMA0_IROUTE                     IROUTE(16,13,62,4)
-#define DMA1_IROUTE                     IROUTE(17,13,62,5)
-#define DMA2_IROUTE                     IROUTE(18,13,62,6)
-#define DMA3_IROUTE                     IROUTE(19,13,62,7)
-#define DMA4_IROUTE                     IROUTE(20,13,62,8)
-#define DMA5_IROUTE                     IROUTE(21,13,62,9)
-#define DMA6_IROUTE                     IROUTE(22,13,62,10)
-#define DMA7_IROUTE                     IROUTE(23,13,62,11)
-#define DMA8_IROUTE                     IROUTE(24,13,62,81)
-#define DMA9_IROUTE                     IROUTE(25,13,62,82)
-#define DMA10_IROUTE                    IROUTE(26,13,62,83)
-#define DMA11_IROUTE                    IROUTE(27,13,62,84)
-
-//
-// GIRQ14
-//
-#define LPC_BERR_IROUTE                 IROUTE(2,14,63,12)
-
-//
-// GIRQ15
-//
-#define UART0_IROUTE                    IROUTE(0,15,64,13)
-#define EMI0_IROUTE                     IROUTE(2,15,64,14)
-#define ACPI_EC0_IBF_IROUTE             IROUTE(6,15,64,15)
-#define ACPI_EC0_OBF_IROUTE             IROUTE(7,15,64,16)
-#define ACPI_EC1_IBF_IROUTE             IROUTE(8,15,64,17)
-#define ACPI_EC1_OBF_IROUTE             IROUTE(9,15,64,18)
-#define ACPI_PM1_CTL_IROUTE             IROUTE(10,15,64,19)
-#define ACPI_PM1_EN_IROUTE              IROUTE(11,15,64,20)
-#define ACPI_PM1_STS_IROUTE             IROUTE(12,15,64,21)
-#define EM8042_OBF_IROUTE               IROUTE(13,15,64,22)
-#define EM8042_IBF_IROUTE               IROUTE(14,15,64,23)
-#define MBOX_IROUTE                     IROUTE(15,15,64,24)
-#define MBOX_DATA_IROUTE                IROUTE(16,15,64,40) 
-
-//
-// GIRQ16
-//
-#define PECI_IROUTE                     IROUTE(3,16,65,25)
-
-//
-// GIRQ17
-//
-#define TACH0_IROUTE                    IROUTE(0,17,66,26)
-#define TACH1_IROUTE                    IROUTE(1,17,66,27)
-#define PS2_0_WAKE_IROUTE               IROUTE(2,17,66,66)
-#define PS2_1_WAKE_IROUTE               IROUTE(3,17,66,66)
-#define PS2_2_WAKE_IROUTE               IROUTE(4,17,66,66)
-#define PS2_3_WAKE_IROUTE               IROUTE(5,17,66,66)
-#define BC_WAKE_IROUTE                  IROUTE(6,17,66,66)
-#define ADC_SNGL_IROUTE                 IROUTE(10,17,66,28)
-#define ADC_RPT_IROUTE                  IROUTE(11,17,66,29)
-#define ADC2PWM1_IROUTE                 IROUTE(12,17,66,30)
-#define ADC2PWM2_IROUTE                 IROUTE(13,17,66,31)
-#define PS2_0_IROUTE                    IROUTE(14,17,66,32)
-#define PS2_1_IROUTE                    IROUTE(15,17,66,33)
-#define PS2_2_IROUTE                    IROUTE(16,17,66,34)
-#define PS2_3_IROUTE                    IROUTE(17,17,66,35)
-#define RTC_IROUTE                      IROUTE(18,17,66,91)
-#define RTC_ALARM_IROUTE                IROUTE(19,17,66,92)
-#define HTIMER_IROUTE                   IROUTE(20,17,66,38)
-#define KSC_IROUTE                      IROUTE(21,17,66,39)
-#define KSC_WAKE_IROUTE                 IROUTE(22,17,66,66)
-#define RPM_STALL_IROUTE                IROUTE(23,17,66,41)
-#define RPM_SPIN_IROUTE                 IROUTE(24,17,66,42)
-#define PFR_IROUTE                      IROUTE(25,17,66,43)
-#define LED0_IROUTE                     IROUTE(26,17,66,44)
-#define LED1_IROUTE                     IROUTE(27,17,66,45)
-#define LED2_IROUTE                     IROUTE(28,17,66,46)
-#define BCM_ERR_IROUTE                  IROUTE(29,17,66,47)
-#define BCM_BUSY_IROUTE                 IROUTE(30,17,66,48)
-
-//
-// GIRQ18
-//
-#define SPI0_TX_IROUTE                  IROUTE(0,18,67,36)
-#define SPI0_RX_IROUTE                  IROUTE(1,18,67,37)
-#define SPI1_TX_IROUTE                  IROUTE(2,18,67,55)
-#define SPI1_RX_IROUTE                  IROUTE(3,18,67,56)
-#define LED3_IROUTE                     IROUTE(4,18,67,85)
-#define PKE_ERR_IROUTE                  IROUTE(5,18,67,86)
-#define PKE_END_IROUTE                  IROUTE(6,18,67,87)
-#define NDRNG_IROUTE                    IROUTE(7,18,67,88)
-#define AES_IROUTE                      IROUTE(8,18,67,89)
-#define HASH_IROUTE                     IROUTE(9,18,67,90)
-
-//
-// GIRQ19, Aggregated only
-//
-#define LRESET_IROUTE                   IROUTE(0,19,68,68)
-#define VCC_PWRGD_IROUTE                IROUTE(1,19,68,68)
-
-//
-// GIRQ20, Aggregated only
-//
-#define GPIO_0200_IROUTE                IROUTE(0,20,69,69)
-#define GPIO_0201_IROUTE                IROUTE(1,20,69,69)
-#define GPIO_0202_IROUTE                IROUTE(2,20,69,69)
-#define GPIO_0203_IROUTE                IROUTE(3,20,69,69)
-#define GPIO_0204_IROUTE                IROUTE(4,20,69,69)
-#define GPIO_0206_IROUTE                IROUTE(6,20,69,69)
-//
-#define GPIO_0210_IROUTE                IROUTE(8,20,69,69)
-#define GPIO_0211_IROUTE                IROUTE(9,20,69,69)
-#define GPIO_0212_IROUTE                IROUTE(10,20,69,69)
-#define GPIO_0213_IROUTE                IROUTE(11,20,69,69)
-
-//
-// GIRQ21
-//
-// No sources
-
-//
-// GIRQ22
-//
-// No sources
-
-//
-// GIRQ23
-//
-#define BTMR0_IROUTE                    IROUTE(0,23,72,49)
-#define BTMR1_IROUTE                    IROUTE(1,23,72,50)
-#define BTMR2_IROUTE                    IROUTE(2,23,72,51)
-#define BTMR3_IROUTE                    IROUTE(3,23,72,52)
-#define BTMR4_IROUTE                    IROUTE(4,23,72,53)
-#define BTMR5_IROUTE                    IROUTE(5,23,72,54)
-
-// GIRQ08 Bit Positions 
-#define GIRQ08_GPIO_0140_BITPOS         (0)
-#define GIRQ08_GPIO_0141_BITPOS         (1)
-#define GIRQ08_GPIO_0142_BITPOS         (2)
-#define GIRQ08_GPIO_0143_BITPOS         (3)
-#define GIRQ08_GPIO_0144_BITPOS         (4)
-#define GIRQ08_GPIO_0145_BITPOS         (5)
-//#define GIRQ08_GPIO_0146_BITPOS       (6) RESERVED
-#define GIRQ08_GPIO_0147_BITPOS         (7)
-//
-#define GIRQ08_GPIO_0150_BITPOS         (8)
-#define GIRQ08_GPIO_0151_BITPOS         (9)
-#define GIRQ08_GPIO_0152_BITPOS         (10)
-#define GIRQ08_GPIO_0153_BITPOS         (11)
-#define GIRQ08_GPIO_0154_BITPOS         (12)
-#define GIRQ08_GPIO_0155_BITPOS         (13)
-#define GIRQ08_GPIO_0156_BITPOS         (14) 
-#define GIRQ08_GPIO_0157_BITPOS         (15)
-//
-#define GIRQ08_GPIO_0160_BITPOS         (16)
-#define GIRQ08_GPIO_0161_BITPOS         (17)
-#define GIRQ08_GPIO_0162_BITPOS         (18)
-#define GIRQ08_GPIO_0163_BITPOS         (19)
-#define GIRQ08_GPIO_0164_BITPOS         (20)
-#define GIRQ08_GPIO_0165_BITPOS         (21)
-#define GIRQ08_GPIO_0166_BITPOS         (22) 
-#define GIRQ08_GPIO_0167_BITPOS         (23)
-//
-#define GIRQ08_MASK                     (0x00FFFFBFul)
-#define GIRQ08_WAKE_CAPABLE_MASK        (0x00FFFFBFul)
-//
-
-// GIRQ09 Bit Positions 
-#define GIRQ09_GPIO_0100_BITPOS         (0)
-#define GIRQ09_GPIO_0101_BITPOS         (1)
-#define GIRQ09_GPIO_0102_BITPOS         (2)
-#define GIRQ09_GPIO_0103_BITPOS         (3)
-#define GIRQ09_GPIO_0104_BITPOS         (4)
-#define GIRQ09_GPIO_0105_BITPOS         (5)
-#define GIRQ09_GPIO_0106_BITPOS         (6) 
-#define GIRQ09_GPIO_0107_BITPOS         (7)
-//
-#define GIRQ09_GPIO_0110_BITPOS         (8)
-#define GIRQ09_GPIO_0111_BITPOS         (9)
-#define GIRQ09_GPIO_0112_BITPOS         (10)
-#define GIRQ09_GPIO_0113_BITPOS         (11)
-#define GIRQ09_GPIO_0114_BITPOS         (12)
-#define GIRQ09_GPIO_0115_BITPOS         (13)
-#define GIRQ09_GPIO_0116_BITPOS         (14) 
-#define GIRQ09_GPIO_0117_BITPOS         (15)
-//
-#define GIRQ09_GPIO_0120_BITPOS         (16)
-#define GIRQ09_GPIO_0121_BITPOS         (17)
-#define GIRQ09_GPIO_0122_BITPOS         (18)
-//#define GIRQ09_GPIO_0123_BITPOS       (19) RESERVED
-#define GIRQ09_GPIO_0124_BITPOS         (20)
-#define GIRQ09_GPIO_0125_BITPOS         (21)
-#define GIRQ09_GPIO_0126_BITPOS         (22) 
-#define GIRQ09_GPIO_0127_BITPOS         (23)
-//
-#define GIRQ09_GPIO_0130_BITPOS         (24)
-#define GIRQ09_GPIO_0131_BITPOS         (25)
-#define GIRQ09_GPIO_0132_BITPOS         (26)
-#define GIRQ09_GPIO_0133_BITPOS         (27)
-#define GIRQ09_GPIO_0134_BITPOS         (28)
-#define GIRQ09_GPIO_0135_BITPOS         (29)
-#define GIRQ09_GPIO_0136_BITPOS         (30) 
-//#define GIRQ09_GPIO_0137_BITPOS       (31) RESERVED
-//
-#define GIRQ09_MASK                     (0x7FF7FFFFul)
-#define GIRQ09_WAKE_CAPABLE_MASK        (0x7FF7FFFFul)
-//
-
-// GIRQ10 Bit Positions 
-#define GIRQ10_GPIO_0040_BITPOS         (0)
-#define GIRQ10_GPIO_0041_BITPOS         (1)
-#define GIRQ10_GPIO_0042_BITPOS         (2)
-#define GIRQ10_GPIO_0043_BITPOS         (3)
-#define GIRQ10_GPIO_0044_BITPOS         (4)
-#define GIRQ10_GPIO_0045_BITPOS         (5)
-#define GIRQ10_GPIO_0046_BITPOS         (6) 
-#define GIRQ10_GPIO_0047_BITPOS         (7)
-//
-#define GIRQ10_GPIO_0050_BITPOS         (8)
-#define GIRQ10_GPIO_0051_BITPOS         (9)
-#define GIRQ10_GPIO_0052_BITPOS         (10)
-#define GIRQ10_GPIO_0053_BITPOS         (11)
-#define GIRQ10_GPIO_0054_BITPOS         (12)
-#define GIRQ10_GPIO_0055_BITPOS         (13)
-#define GIRQ10_GPIO_0056_BITPOS         (14) 
-#define GIRQ10_GPIO_0057_BITPOS         (15)
-//
-#define GIRQ10_GPIO_0060_BITPOS         (16)
-#define GIRQ10_GPIO_0061_BITPOS         (17)
-#define GIRQ10_GPIO_0062_BITPOS         (18)
-#define GIRQ10_GPIO_0063_BITPOS         (19)
-#define GIRQ10_GPIO_0064_BITPOS         (20)
-#define GIRQ10_GPIO_0065_BITPOS         (21)
-#define GIRQ10_GPIO_0066_BITPOS         (22) 
-#define GIRQ10_GPIO_0067_BITPOS         (23)
-//
-#define GIRQ10_GPIO_0070_BITPOS         (24)
-#define GIRQ10_GPIO_0071_BITPOS         (25)
-#define GIRQ10_GPIO_0072_BITPOS         (26)
-#define GIRQ10_GPIO_0073_BITPOS         (27)
-#define GIRQ10_GPIO_0074_BITPOS         (28)
-#define GIRQ10_GPIO_0075_BITPOS         (29)
-#define GIRQ10_GPIO_0076_BITPOS         (30) 
-//#define GIRQ10_GPIO_0077_BITPOS       (31) RESERVED
-//
-#define GIRQ10_MASK                     (0x7FFFFFFFul)
-#define GIRQ10_WAKE_CAPABLE_MASK        (0x7FFFFFFFul)
-//
-
-// GIRQ11 Bit Positions 
-#define GIRQ11_GPIO_0000_BITPOS         (0)
-#define GIRQ11_GPIO_0001_BITPOS         (1)
-#define GIRQ11_GPIO_0002_BITPOS         (2)
-#define GIRQ11_GPIO_0003_BITPOS         (3)
-#define GIRQ11_GPIO_0004_BITPOS         (4)
-#define GIRQ11_GPIO_0005_BITPOS         (5)
-#define GIRQ11_GPIO_0006_BITPOS         (6) 
-#define GIRQ11_GPIO_0007_BITPOS         (7)
-//
-#define GIRQ11_GPIO_0010_BITPOS         (8)
-#define GIRQ11_GPIO_0011_BITPOS         (9)
-#define GIRQ11_GPIO_0012_BITPOS         (10)
-#define GIRQ11_GPIO_0013_BITPOS         (11)
-#define GIRQ11_GPIO_0014_BITPOS         (12)
-#define GIRQ11_GPIO_0015_BITPOS         (13)
-#define GIRQ11_GPIO_0016_BITPOS         (14) 
-#define GIRQ11_GPIO_0017_BITPOS         (15)
-//
-#define GIRQ11_GPIO_0020_BITPOS         (16)
-#define GIRQ11_GPIO_0021_BITPOS         (17)
-#define GIRQ11_GPIO_0022_BITPOS         (18)
-#define GIRQ11_GPIO_0023_BITPOS         (19)
-#define GIRQ11_GPIO_0024_BITPOS         (20)
-#define GIRQ11_GPIO_0025_BITPOS         (21)
-#define GIRQ11_GPIO_0026_BITPOS         (22) 
-#define GIRQ11_GPIO_0027_BITPOS         (23)
-//
-#define GIRQ11_GPIO_0030_BITPOS         (24)
-#define GIRQ11_GPIO_0031_BITPOS         (25)
-#define GIRQ11_GPIO_0032_BITPOS         (26)
-#define GIRQ11_GPIO_0033_BITPOS         (27)
-#define GIRQ11_GPIO_0034_BITPOS         (28)
-#define GIRQ11_GPIO_0035_BITPOS         (29)
-#define GIRQ11_GPIO_0036_BITPOS         (30) 
-//#define GIRQ11_GPIO_0037_BITPOS       (31) RESERVED
-//
-#define GIRQ11_MASK                     (0x7FFFFFFFul)
-#define GIRQ11_WAKE_CAPABLE_MASK        (0x7FFFFFFFul)
-//
-
-// GIRQ12 Bit Positions 
-#define GIRQ12_SMBUS0_BITPOS            (0)
-#define GIRQ12_SMBUS1_BITPOS            (1)
-#define GIRQ12_SMBUS2_BITPOS            (2)
-#define GIRQ12_SMBUS3_BITPOS            (3)
-#define GIRQ12_SMBUS0_WAKE_BITPOS       (4)
-#define GIRQ12_SMBUS1_WAKE_BITPOS       (5)
-#define GIRQ12_SMBUS2_WAKE_BITPOS       (6)
-#define GIRQ12_SMBUS3_WAKE_BITPOS       (7)
-#define GIRQ12_SMBUS4_WAKE_BITPOS       (8)
-// RESERVED bits[31:9]
-#define GIRQ12_MASK                     (0x01FFul)
-#define GIRQ12_WAKE_CAPABLE_MASK        (0x01F0ul)
-//
-
-// GIRQ13 Bit Positions 
-#define GIRQ13_DMA0_BITPOS              (16)
-#define GIRQ13_DMA1_BITPOS              (17)
-#define GIRQ13_DMA2_BITPOS              (18)
-#define GIRQ13_DMA3_BITPOS              (19)
-#define GIRQ13_DMA4_BITPOS              (20)
-#define GIRQ13_DMA5_BITPOS              (21)
-#define GIRQ13_DMA6_BITPOS              (22)
-#define GIRQ13_DMA7_BITPOS              (23)
-#define GIRQ13_DMA8_BITPOS              (24)
-#define GIRQ13_DMA9_BITPOS              (25)
-#define GIRQ13_DMA10_BITPOS             (26)
-#define GIRQ13_DMA11_BITPOS             (27)
-//
-#define GIRQ13_MASK                     (0x0FFF0000ul)
-#define GIRQ13_WAKE_CAPABLE_MASK        (0x00000000ul)
-//
-
-// GIRQ14 Bit Positions 
-#define GIRQ14_LPC_BITPOS               (2)
-//
-#define GIRQ14_MASK                     (0x04ul)
-#define GIRQ14_WAKE_CAPABLE_MASK        (0x00ul)
-//
-
-// GIRQ15 Bit Positions 
-#define GIRQ15_UART0_BITPOS             (0)
-#define GIRQ15_IMAP_BITPOS              (2)
-#define GIRQ15_KBD_K_BITPOS             (3)
-#define GIRQ15_KBD_M_BITPOS             (4)
-#define GIRQ15_ACPI0_IBF_BITPOS         (6)
-#define GIRQ15_ACPI0_OBF_BITPOS         (7)
-#define GIRQ15_ACPI1_IBF_BITPOS         (8)
-#define GIRQ15_ACPI1_OBF_BITPOS         (9)
-#define GIRQ15_ACPI_PM1CTL_BITPOS       (10)
-#define GIRQ15_ACPI_PM1EN_BITPOS        (11)
-#define GIRQ15_ACPI_PM1STS_BITPOS       (12)
-#define GIRQ15_MF8042_OBF_BITPOS        (13)
-#define GIRQ15_MF8042_IBF_BITPOS        (14)
-#define GIRQ15_MAILBOX_BITPOS           (15)
-#define GIRQ15_MAILBOX_DATA_BITPOS      (16)
-//
-#define GIRQ15_MASK                     (0x01FFDDul)
-#define GIRQ15_WAKE_CAPABLE_MASK        (0x000000ul)
-//
-
-// GIRQ16 Bit Positions 
-#define GIRQ16_PECI_BITPOS              (3)
-//
-#define GIRQ16_MASK                     (0x08ul)
-#define GIRQ16_WAKE_CAPABLE_MASK        (0x00ul)
-//
-
-// GIRQ17 Bit Positions 
-#define GIRQ17_TACH0_BITPOS             (0)
-#define GIRQ17_TACH1_BITPOS             (1)
-#define GIRQ17_PS2_0_WAKE_BITPOS        (2)
-#define GIRQ17_PS2_1_WAKE_BITPOS        (3)
-#define GIRQ17_PS2_2_WAKE_BITPOS        (4)
-#define GIRQ17_PS2_3_WAKE_BITPOS        (5)
-#define GIRQ17_BC_WAKE_BITPOS           (6)
-// RESERVED b[9:7]
-#define GIRQ17_ADC_INT0_BITPOS          (10)
-#define GIRQ17_ADC_INT1_BITPOS          (11)
-#define GIRQ17_V2P_INT0_BITPOS          (12)
-#define GIRQ17_V2P_INT1_BITPOS          (13)
-#define GIRQ17_PS2_0_BITPOS             (14)
-#define GIRQ17_PS2_1_BITPOS             (15)
-#define GIRQ17_PS2_2_BITPOS             (16)
-#define GIRQ17_PS2_3_BITPOS             (17)
-// RESERVED b[19:18]
-#define GIRQ17_HIBTMR_BITPOS            (20)
-#define GIRQ17_KEY_INT_BITPOS           (21)
-#define GIRQ17_KEY_INT_WAKE_BITPOS      (22)
-#define GIRQ17_RPM_STALL_BITPOS         (23)
-#define GIRQ17_RPM_SPIN_BITPOS          (24)
-#define GIRQ17_VBAT_BITPOS              (25)
-#define GIRQ17_LED0_BITPOS              (26)
-#define GIRQ17_LED1_BITPOS              (27)
-#define GIRQ17_LED2_BITPOS              (28)
-#define GIRQ17_MBC_ERR_BITPOS           (29)
-#define GIRQ17_MBC_BUSY_BITPOS          (30)
-//
-#define GIRQ17_MASK                     (0x7FF3FC7Ful)
-#define GIRQ17_WAKE_CAPABLE_MASK        (0x0230007Cul)
-//
-
-// GIRQ18 Bit Positions 
-#define GIRQ18_SPI0_TX_BITPOS           (0)
-#define GIRQ18_SPI0_RX_BITPOS           (1)
-#define GIRQ18_SPI1_TX_BITPOS           (2)
-#define GIRQ18_SPI1_RX_BITPOS           (3)
-#define GIRQ18_LED3_BITPOS              (4)  // NVIC 85
-#define GIRQ18_PKE_ERR_BITPOS           (5)  // NVIC 86
-#define GIRQ18_PKE_END_BITPOS           (6)  // NVIC 87
-#define GIRQ18_TRNG_BITPOS              (7)  // NVIC 88
-#define GIRQ18_AES_BITPOS               (8)  // NVIC 89
-#define GIRQ18_HASH_BITPOS              (9)  // NVIC 90
-//
-#define GIRQ18_MASK                     (0x0FFul)
-#define GIRQ18_WAKE_CAPABLE_MASK        (0x000ul)
-//
-
-// GIRQ19 Bit Positions 
-#define GIRQ19_LRESET_BITPOS            (0)
-#define GIRQ19_VCC_PWRGD_BITPOS         (1)
-//
-#define GIRQ19_MASK                     (0x03ul)
-#define GIRQ19_WAKE_CAPABLE_MASK        (0x03ul)
-//
-
-// GIRQ20 Bit Positions 
-#define GIRQ20_GPIO_0200_BITPOS         (0)
-#define GIRQ20_GPIO_0201_BITPOS         (1)
-#define GIRQ20_GPIO_0202_BITPOS         (2)
-#define GIRQ20_GPIO_0203_BITPOS         (3)
-#define GIRQ20_GPIO_0204_BITPOS         (4)
-//#define GIRQ20_GPIO_0205_BITPOS       (5)
-#define GIRQ20_GPIO_0206_BITPOS         (6)
-//#define GIRQ20_GPIO_0207_BITPOS       (7)
-//
-#define GIRQ20_GPIO_0210_BITPOS         (8)
-#define GIRQ20_GPIO_0211_BITPOS         (9)
-#define GIRQ20_GPIO_0212_BITPOS         (10)
-#define GIRQ20_GPIO_0213_BITPOS         (11)
-// 
-#define GIRQ20_MASK                     (0x0F5Ful)
-#define GIRQ20_WAKE_CAPABLE_MASK        (0x0F5Ful)
-//
-
-// GIRQ21 Bit Positions 
-#define GIRQ21_MASK                     (0x00ul)
-#define GIRQ21_WAKE_CAPABLE_MASK        (0x00ul)
-
-// GIRQ22 Bit Positions 
-#define GIRQ22_MASK                     (0x00ul)
-#define GIRQ22_WAKE_CAPABLE_MASK        (0x00ul)
-
-// GIRQ23 Bit Positions 
-#define GIRQ23_TMR0_BITPOS              (0)
-#define GIRQ23_TMR1_BITPOS              (1)
-#define GIRQ23_TMR2_BITPOS              (2)
-#define GIRQ23_TMR3_BITPOS              (3)
-#define GIRQ23_TMR4_BITPOS              (4)
-#define GIRQ23_TMR5_BITPOS              (5)
-//
-#define GIRQ23_MASK                     (0x03Ful)
-#define GIRQ23_WAKE_CAPABLE_MASK        (0x000ul)
-//
-
-/* ------------------------------------------------------------------------------- */
-/*                  NVIC,ECIA Routing Policy for Direct Mode                       */
-/* ------------------------------------------------------------------------------- */
-/* In Direct Mode, some interrupts could be configured to be used as aggregated.
- * Configuration:
- *      1. Always set ECS Interrupt Direct enable bit.         
- *      2. If GIRQn aggregated set Block Enable bit.
- *      3. If GIRQn direct then clear Block Enable bit and enable individual NVIC inputs.
- *  Switching issues:
- *  Aggregate enable/disable requires set/clear single GIRQn bit in GIRQ Block En/Clr registers.
- *  Also requires set/clear of individual NVIC Enables.
- *  
- * Note: interrupt_is_girq_direct() internal function uses this policy to detect 
- * if any interrupt is configured as direct or aggregated
-*/
-
-/** Initialize EC Interrupt Aggregator
- * @param mode 1 - Direct Map mode, 0 - Fully Aggregated Mode 
- * @param girq_bitmask - BitMask of GIRQ to be configured as aggregated 
- *                     This parameter is only applicable in direct mode.
- * @note All GPIO's and wake capable sources are always 
- * aggregated! GPIO's interrupts will still work in direct mode.
- * Block wakes are not be routed to the processor in direct 
- * mode. 
- * Note2: This function disables and enables global interrupt  
- */
-void interrupt_init(uint8_t mode, uint32_t girq_bitmask);
-
-/** Set interrupt routing mode to aggregated or direct. 
- * @param mode 1 = Direct (except GPIO & wake), 0 = All Aggregated 
- * @note In direct mode, one could enable certain GIRQs as aggregated using 
- * p_interrupt_ecia_block_enable_set function
- */
-void interrupt_mode_set(uint8_t mode);
-
-/** Clears all individual interrupts Enables and Source in ECIA,
- *  and Clears all NVIC external enables and pending bits  
- */
-void interrupt_reset(void);
-
-/** Enables interrupt for a device 
- * @param dev_iroute - source IROUTING information 
- * @note This function disables and enables global interrupt 
- */
-void interrupt_device_enable(uint32_t dev_iroute);
-
-/** Disables interrupt for a device
- * @param dev_iroute - source IROUTING information  
- * @note This function disables and enables global interrupt 
- */
-void interrupt_device_disable(uint32_t dev_iroute);
-
-/* ------------------------------------------------------------------------------- */
-/*                  ECIA APIs using device IROUTE() as input                       */ 
-/* ------------------------------------------------------------------------------- */
-
-/** Clear Source in the ECIA for the device  
- * @param devi - device IROUTING value  
- */
-void interrupt_device_ecia_source_clear(const uint32_t dev_iroute);
-
-/** Get the Source bit in the ECIA for the device  
- * @param devi - device IROUTING value  
- * @return 0 if source bit not set; else non-zero value
- */
-uint32_t interrupt_device_ecia_source_get(const uint32_t dev_iroute);
-
-/** Get the Result bit in the ECIA for the device  
- * @param devi - device IROUTING value  
- * @return 0 if result bit not set; else non-zero value
- */
-uint32_t interrupt_device_ecia_result_get(const uint32_t dev_iroute);
-
-/* ------------------------------------------------------------------------------- */
-/*                  NVIC APIs using device IROUTE() as input                       */ 
-/* ------------------------------------------------------------------------------- */
-/* Note that if the device interrupt is aggregated, then these APIs would affect the 
- * NVIC corresponding to the aggregated GIRQ 
- */
-
-/**  Enable/Disable the NVIC (in the NVIC controller) for the device
- * @param dev_iroute : source IROUTING information (encoded in a uint32_t)
- * @param en_flag : 1 = Enable the NVIC IRQ, 0 = Disable the NVIC IRQ 
- * @note Recommended to use interrupt_device_enable, interrupt_device_disable
- * to enable/disable interrupts for the device, since those APIs configure ECIA as well
- */
-void interrupt_device_nvic_enable(uint32_t dev_iroute, uint8_t en_flag);
-
-/** Set NVIC priority for specified peripheral interrupt source
- * @param dev_iroute - source IROUTING information (encoded in a uint32_t)
- * @param nvic_pri - NVIC Priority
- * @note 1. If ECIA is in aggregated mode, the priority affects all interrupt 
- * sources in the GIRQ. 
- * 2. This function disables and enables global interrupt    
- */
-void interrupt_device_nvic_priority_set(const uint32_t dev_iroute, const uint8_t nvic_pri);
-
-/** Return NVIC priority for interrupt source
- * @param dev_iroute - source IROUTING information 
- * @return uint32_t  NVIC priority 
- */
-uint32_t interrupt_device_nvic_priority_get(const uint32_t dev_iroute);
-
-/** Return NVIC pending for interrupt source
- * @param dev_iroute - source IROUTING information 
- * @return uint8_t 0(not pending), 1 (pending in NVIC) 
- *  
- */
-uint8_t interrupt_device_nvic_pending_get(const uint32_t dev_iroute);
-
-/** Set NVIC pending for interrupt source
- * @param dev_iroute - source IROUTING information   
- */
-void interrupt_device_nvic_pending_set(const uint32_t dev_iroute);
-
-/** Clears NVIC pending for interrupt source
- * @param dev_iroute - source IROUTING information 
- * @return uint8_t 0(not pending), 1 (pending in NVIC) - before clear 
- * @note This function disables and enables global interrupt    
- */
-uint8_t interrupt_device_nvic_pending_clear(const uint32_t dev_iroute);
-    
-/* ------------------------------------------------------------------------------- */
-/* Peripheral Functions - Operations on GIRQ Block Enable Set, Enable Clear        *
- * and Status Register                                                             */
-/* ------------------------------------------------------------------------------- */
-
-/** Enable specified GIRQ in ECIA block
- * @param girq_id - enum MEC_GIRQ_IDS 
- */
- void p_interrupt_ecia_block_enable_set(uint8_t girq_id);
-  
- /** Enable GIRQs in ECIA Block 
- * @param girq_bitmask - Bitmask of GIRQs to be enabled in ECIA Block  
- */
-void p_interrupt_ecia_block_enable_bitmask_set(uint32_t girq_bitmask);
-
-/** Check if specified GIRQ block enabled or not
- * @param girq_id - enum MEC_GIRQ_IDS 
- * @return retVal - 1 if the particular GIRQ block enabled, else 0
- */
-uint8_t p_interrupt_ecia_block_enable_get(uint8_t girq_id);
-
-/** Set all GIRQ block enables */
-void p_interrupt_ecia_block_enable_all_set(void);
-
-/** Clear specified GIRQ in ECIA Block 
- * @param girq_id - enum MEC_GIRQ_IDS 
- */
-void p_interrupt_ecia_block_enable_clr(uint8_t girq_id);
-
-/** Clear GIRQs in ECIA Block 
- * @param girq_bitmask - Bitmask of GIRQs to be cleared in ECIA Block  
- */
-void p_interrupt_ecia_block_enable_bitmask_clr(uint32_t girq_bitmask);
-
-/** p_interrupt_ecia_block_enable_all_clr - Clears all GIRQ block enables */
-void p_interrupt_ecia_block_enable_all_clr(void);
- 
- /** Get status of GIRQ in ECIA Block
- * @param girq_id - enum MEC_GIRQ_IDS  
- * @return 0 if status bit not set; else non-zero value
- */
-uint32_t p_interrupt_ecia_block_irq_status_get(uint8_t girq_id);
-
-/** Reads the Block IRQ Vector Register
-  * @return 32-bit value
- */
-uint32_t p_interrupt_ecia_block_irq_all_status_get(void);
-
-/* ---------------------------------------------------------------------------- */
-/* Peripheral Functions - Operations on GIRQx Source, Enable, Result            *
- * and Enable Registers                                                         */
-/* ---------------------------------------------------------------------------- */
-
-/** Clear specified interrupt source bit in GIRQx
- * @param girq_id - enum MEC_GIRQ_IDS
- * @param bitnum -[0, 31]
- */
-void p_interrupt_ecia_girq_source_clr(int16_t girq_id, uint8_t bitnum);
-
-/** Read the specified interrupt source bit in GIRQx
- * @param girq_id - enum MEC_GIRQ_IDS
- * @param bitnum -[0, 31]
- * @return 0 if source bit not set; else non-zero value
- */
-uint32_t p_interrupt_ecia_girq_source_get(int16_t girq_id, uint8_t bitnum);
-
-/** Enable the specified interrupt in GIRQx
- * girq_id - enum MEC_GIRQ_IDS
- * bitnum = [0, 31]
- */
-void p_interrupt_ecia_girq_enable_set(uint16_t girq_id, uint8_t bitnum);
-
-/** Disable the specified interrupt in GIRQx
- * girq_id - enum MEC_GIRQ_IDS
- * bitnum = [0, 31]
- */
-void p_interrupt_ecia_girq_enable_clr(uint16_t girq_id, uint8_t bitnum);
-
-/** Read the status of the specified interrupt in GIRQx
- * girq_id - enum MEC_GIRQ_IDS
- * bitnum = [0, 31]
- * @return 0 if enable bit not set; else non-zero value
- */
-uint32_t p_interrupt_ecia_girq_enable_get(uint16_t girq_id, uint8_t bitnum);
-
-/** Read the result bit of the interrupt in GIRQx
- * @param girq_id - enum MEC_GIRQ_IDS
- * @param bitnum -[0, 31]
- * @return 0 if enable bit not set; else non-zero value
- */
-uint32_t p_interrupt_ecia_girq_result_get(int16_t girq_id, uint8_t bitnum);
-
-/* ------------------------------------------------------------------------------- */
-/* Peripheral Function - Operations on all GIRQs                                   */
-/* ------------------------------------------------------------------------------- */
-
-/** Clear all aggregator GIRQn status registers */
-void p_interrupt_ecia_girqs_source_reset(void);
-
-/** Clear all aggregator GIRQn enables */
- void p_interrupt_ecia_girqs_enable_reset(void);
- 
-/* ------------------------------------------------------------------------------- */
-/* Peripheral Function - Function to set interrupt control                         */
-/* ------------------------------------------------------------------------------- */
-
-/** Set interrupt control 
- * @param nvic_en_flag : 0 = Alternate NVIC disabled, 1 = Alternate NVIC enabled
- */
- void p_interrupt_control_set(uint8_t nvic_en_flag);
-     
- /** Read interrupt control 
- * @return uint8_t - 0 = Alternate NVIC disabled, 1 = Alternate NVIC enabled
- */
-uint8_t p_interrupt_control_get(void);
-
-/* ------------------------------------------------------------------------------- */
-/* Peripheral Functions - NVIC                                                     */
-/* ------------------------------------------------------------------------------- */
-
-/**  Enable/Disable the NVIC IRQ in the NVIC interrupt controller
- * @param nvic_num : NVIC number (see enum IRQn_Type)
- * @param en_flag : 1 = Enable the NVIC IRQ, 0 = Disable the NVIC IRQ
- * @note Application should perform this operation
- */
- void p_interrupt_nvic_enable(IRQn_Type nvic_num, uint8_t en_flag);
-     
- /**  ecia_nvic_clr_en - Clear all NVIC external enables */ 
-void p_interrupt_nvic_extEnables_clr(void);
-
-/** Clear all NVIC external enables and pending bits */
-void p_interrupt_nvic_enpend_clr(void);
-
-/** Set NVIC external priorities to POR value */
-void p_interrupt_nvic_priorities_default_set(void);
-
-/** Set NVIC external priorities to specified priority (0 - 7)
- * @param zero-based 3-bit priority value: 0=highest, 7=lowest.
- * @note NVIC highest priority is the value 0, lowest is all 1's.
- * Each external interrupt has an 8-bit register and the priority 
- * is left justified in the registers. MECxxx implements 8 priority 
- * levels or bits [7:5] in the register. Lowest priority = 0xE0
- */
-void p_interrupt_nvic_priorities_set(uint8_t new_pri);
-
-#endif /*_INTERRUPT_H_*/
-
-/**   @}
- */
-
-
-
+/*****************************************************************************
+* � 2015 Microchip Technology Inc. and its subsidiaries.
+* You may use this software and any derivatives exclusively with
+* Microchip products.
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
+* OF THESE TERMS.
+******************************************************************************
+
+Version Control Information (Perforce)
+******************************************************************************
+$Revision: #1 $ 
+$DateTime: 2016/04/08 10:18:28 $ 
+$Author: pramans $
+Last Change: Corrected several header definations
+******************************************************************************/
+/** @file interrupt.h
+* \brief Interrupt Header File
+* \author jvasanth
+* 
+* This file implements the Interrupt Module Header file  
+******************************************************************************/
+
+/** @defgroup Interrupt
+ *  @{
+ */
+
+#ifndef _INTERRUPT_H
+#define _INTERRUPT_H
+
+// GIRQ IDs for EC Interrupt Aggregator
+enum MEC_GIRQ_IDS
+{
+    MEC_GIRQ08_ID = 0,
+    MEC_GIRQ09_ID,                  
+    MEC_GIRQ10_ID,                  
+    MEC_GIRQ11_ID,                  
+    MEC_GIRQ12_ID,                  
+    MEC_GIRQ13_ID,                  
+    MEC_GIRQ14_ID,                  
+    MEC_GIRQ15_ID,                  
+    MEC_GIRQ16_ID,                  
+    MEC_GIRQ17_ID,                  
+    MEC_GIRQ18_ID,                  
+    MEC_GIRQ19_ID,                  
+    MEC_GIRQ20_ID,                  
+    MEC_GIRQ21_ID,                  
+    MEC_GIRQ22_ID,                  
+    MEC_GIRQ23_ID,                                   
+    MEC_GIRQ_ID_MAX
+};
+
+//Bitmask of GIRQ in ECIA Block Registers
+#define MEC_GIRQ08_BITMASK          (1UL << (MEC_GIRQ08_ID + 8))
+#define MEC_GIRQ09_BITMASK          (1UL << (MEC_GIRQ09_ID + 8))  
+#define MEC_GIRQ10_BITMASK          (1UL << (MEC_GIRQ10_ID + 8))  
+#define MEC_GIRQ11_BITMASK          (1UL << (MEC_GIRQ11_ID + 8)) 
+#define MEC_GIRQ12_BITMASK          (1UL << (MEC_GIRQ12_ID + 8)) 
+#define MEC_GIRQ13_BITMASK          (1UL << (MEC_GIRQ13_ID + 8)) 
+#define MEC_GIRQ14_BITMASK          (1UL << (MEC_GIRQ14_ID + 8)) 
+#define MEC_GIRQ15_BITMASK          (1UL << (MEC_GIRQ15_ID + 8)) 
+#define MEC_GIRQ16_BITMASK          (1UL << (MEC_GIRQ16_ID + 8)) 
+#define MEC_GIRQ17_BITMASK          (1UL << (MEC_GIRQ17_ID + 8)) 
+#define MEC_GIRQ18_BITMASK          (1UL << (MEC_GIRQ18_ID + 8)) 
+#define MEC_GIRQ19_BITMASK          (1UL << (MEC_GIRQ19_ID + 8)) 
+#define MEC_GIRQ20_BITMASK          (1UL << (MEC_GIRQ20_ID + 8)) 
+#define MEC_GIRQ21_BITMASK          (1UL << (MEC_GIRQ21_ID + 8)) 
+#define MEC_GIRQ22_BITMASK          (1UL << (MEC_GIRQ22_ID + 8)) 
+#define MEC_GIRQ23_BITMASK          (1UL << (MEC_GIRQ23_ID + 8)) 
+
+#define INTERRUPT_MODE_ALL_AGGREGATED        (0u)
+#define INTERRUPT_MODE_DIRECT                (1u)
+
+// Bit map of GIRQs whose sources can be directly connected to the NVIC
+// GIRQs 12 - 18, 23
+#define ECIA_GIRQ_DIRECT_BITMAP     (0x0087F000ul)
+
+/*
+ *  n = b[7:0]   = zero-based direct mapped NVIC ID
+ *  m = b[15:8]  = zero-based aggregated NVIC ID
+ *  a = b[23:16] = block Aggregator register block ID
+ *  b = b[31:24] = block bit position in Aggregator registers
+*/
+#define IROUTE(b,a,m,n) 	(((uint32_t)(n)&0xFFul) + \
+                            (((uint32_t)(m)&0xFFul)<<8u) + \
+                            ((((uint32_t)(a)-8ul)&0x0F)<<16u) + \
+                            (((uint32_t)(b)&0x1Ful)<<24))
+
+#define ECIA_NVIC_ID_BITPOS             (0u)
+#define ECIA_IA_NVIC_ID_BITPOS          (8u)
+#define ECIA_GIRQ_ID_BITPOS             (16u)
+#define ECIA_GIRQ_BIT_BITPOS            (24u)
+
+//
+// GIRQ08
+//
+#define GPIO_0140_IROUTE                IROUTE(0,8,57,57)
+#define GPIO_0141_IROUTE                IROUTE(1,8,57,57)
+#define GPIO_0142_IROUTE                IROUTE(2,8,57,57)
+#define GPIO_0143_IROUTE                IROUTE(3,8,57,57)
+#define GPIO_0144_IROUTE                IROUTE(4,8,57,57)
+#define GPIO_0145_IROUTE                IROUTE(5,8,57,57)
+#define GPIO_0146_IROUTE                IROUTE(6,8,57,57)
+#define GPIO_0147_IROUTE                IROUTE(7,8,57,57)
+//
+#define GPIO_0150_IROUTE                IROUTE(8,8,57,57)
+#define GPIO_0151_IROUTE                IROUTE(9,8,57,57)
+#define GPIO_0152_IROUTE                IROUTE(10,8,57,57)
+#define GPIO_0153_IROUTE                IROUTE(11,8,57,57)
+#define GPIO_0154_IROUTE                IROUTE(12,8,57,57)
+#define GPIO_0155_IROUTE                IROUTE(13,8,57,57)
+#define GPIO_0156_IROUTE                IROUTE(14,8,57,57)
+#define GPIO_0157_IROUTE                IROUTE(15,8,57,57)
+//
+#define GPIO_0160_IROUTE                IROUTE(16,8,57,57)
+#define GPIO_0161_IROUTE                IROUTE(17,8,57,57)
+#define GPIO_0162_IROUTE                IROUTE(18,8,57,57)
+#define GPIO_0163_IROUTE                IROUTE(19,8,57,57)
+#define GPIO_0164_IROUTE                IROUTE(20,8,57,57)
+#define GPIO_0165_IROUTE                IROUTE(21,8,57,57)
+
+//
+// GIRQ09
+//
+#define GPIO_0100_IROUTE                IROUTE(0,9,58,58)
+#define GPIO_0101_IROUTE                IROUTE(1,9,58,58)
+#define GPIO_0102_IROUTE                IROUTE(2,9,58,58)
+#define GPIO_0103_IROUTE                IROUTE(3,9,58,58)
+#define GPIO_0104_IROUTE                IROUTE(4,9,58,58)
+#define GPIO_0105_IROUTE                IROUTE(5,9,58,58)
+#define GPIO_0106_IROUTE                IROUTE(6,9,58,58)
+#define GPIO_0107_IROUTE                IROUTE(7,9,58,58)
+//
+#define GPIO_0110_IROUTE                IROUTE(8,9,58,58)
+#define GPIO_0111_IROUTE                IROUTE(9,9,58,58)
+#define GPIO_0112_IROUTE                IROUTE(10,9,58,58)
+#define GPIO_0113_IROUTE                IROUTE(11,9,58,58)
+#define GPIO_0114_IROUTE                IROUTE(12,9,58,58)
+#define GPIO_0115_IROUTE                IROUTE(13,9,58,58)
+#define GPIO_0116_IROUTE                IROUTE(14,9,58,58)
+#define GPIO_0117_IROUTE                IROUTE(15,9,58,58)
+//
+#define GPIO_0120_IROUTE                IROUTE(16,9,58,58)
+#define GPIO_0121_IROUTE                IROUTE(17,9,58,58)
+#define GPIO_0122_IROUTE                IROUTE(18,9,58,58)
+#define GPIO_0124_IROUTE                IROUTE(20,9,58,58)
+#define GPIO_0125_IROUTE                IROUTE(21,9,58,58)
+#define GPIO_0126_IROUTE                IROUTE(22,9,58,58)
+#define GPIO_0127_IROUTE                IROUTE(23,9,58,58)
+//
+#define GPIO_0130_IROUTE                IROUTE(24,9,58,58)
+#define GPIO_0131_IROUTE                IROUTE(25,9,58,58)
+#define GPIO_0132_IROUTE                IROUTE(26,9,58,58)
+#define GPIO_0133_IROUTE                IROUTE(27,9,58,58)
+#define GPIO_0134_IROUTE                IROUTE(28,9,58,58)
+#define GPIO_0135_IROUTE                IROUTE(29,9,58,58)
+#define GPIO_0136_IROUTE                IROUTE(30,9,58,58)
+
+//
+// GIRQ10
+//
+#define GPIO_0040_IROUTE                IROUTE(0,10,59,59)
+#define GPIO_0041_IROUTE                IROUTE(1,10,59,59)
+#define GPIO_0042_IROUTE                IROUTE(2,10,59,59)
+#define GPIO_0043_IROUTE                IROUTE(3,10,59,59)
+#define GPIO_0044_IROUTE                IROUTE(4,10,59,59)
+#define GPIO_0045_IROUTE                IROUTE(5,10,59,59)
+#define GPIO_0046_IROUTE                IROUTE(6,10,59,59)
+#define GPIO_0047_IROUTE                IROUTE(7,10,59,59)
+//
+#define GPIO_0050_IROUTE                IROUTE(8,10,59,59)
+#define GPIO_0051_IROUTE                IROUTE(9,10,59,59)
+#define GPIO_0052_IROUTE                IROUTE(10,10,59,59)
+#define GPIO_0053_IROUTE                IROUTE(11,10,59,59)
+#define GPIO_0054_IROUTE                IROUTE(12,10,59,59)
+#define GPIO_0055_IROUTE                IROUTE(13,10,59,59)
+#define GPIO_0056_IROUTE                IROUTE(14,10,59,59)
+#define GPIO_0057_IROUTE                IROUTE(15,10,59,59)
+//
+#define GPIO_0060_IROUTE                IROUTE(16,10,59,59)
+#define GPIO_0061_IROUTE                IROUTE(17,10,59,59)
+#define GPIO_0062_IROUTE                IROUTE(18,10,59,59)
+#define GPIO_0063_IROUTE                IROUTE(19,10,59,59)
+#define GPIO_0064_IROUTE                IROUTE(20,10,59,59)
+#define GPIO_0065_IROUTE                IROUTE(21,10,59,59)
+#define GPIO_0066_IROUTE                IROUTE(22,10,59,59)
+#define GPIO_0067_IROUTE                IROUTE(23,10,59,59)
+
+//
+// GIRQ11
+//
+#define GPIO_0000_IROUTE                IROUTE(0,11,60,60)
+#define GPIO_0001_IROUTE                IROUTE(1,11,60,60)
+#define GPIO_0002_IROUTE                IROUTE(2,11,60,60)
+#define GPIO_0003_IROUTE                IROUTE(3,11,60,60)
+#define GPIO_0004_IROUTE                IROUTE(4,11,60,60)
+#define GPIO_0005_IROUTE                IROUTE(5,11,60,60)
+#define GPIO_0006_IROUTE                IROUTE(6,11,60,60)
+#define GPIO_0007_IROUTE                IROUTE(7,11,60,60)
+//
+#define GPIO_0010_IROUTE                IROUTE(8,11,60,60)
+#define GPIO_0011_IROUTE                IROUTE(9,11,60,60)
+#define GPIO_0012_IROUTE                IROUTE(10,11,60,60)
+#define GPIO_0013_IROUTE                IROUTE(11,11,60,60)
+#define GPIO_0014_IROUTE                IROUTE(12,11,60,60)
+#define GPIO_0015_IROUTE                IROUTE(13,11,60,60)
+#define GPIO_0016_IROUTE                IROUTE(14,11,60,60)
+#define GPIO_0017_IROUTE                IROUTE(15,11,60,60)
+//
+#define GPIO_0020_IROUTE                IROUTE(16,11,60,60)
+#define GPIO_0021_IROUTE                IROUTE(17,11,60,60)
+#define GPIO_0022_IROUTE                IROUTE(18,11,60,60)
+#define GPIO_0023_IROUTE                IROUTE(19,11,60,60)
+#define GPIO_0024_IROUTE                IROUTE(20,11,60,60)
+#define GPIO_0025_IROUTE                IROUTE(21,11,60,60)
+#define GPIO_0026_IROUTE                IROUTE(22,11,60,60)
+#define GPIO_0027_IROUTE                IROUTE(23,11,60,60)
+//
+#define GPIO_0030_IROUTE                IROUTE(24,11,60,60)
+#define GPIO_0031_IROUTE                IROUTE(25,11,60,60)
+#define GPIO_0032_IROUTE                IROUTE(26,11,60,60)
+#define GPIO_0033_IROUTE                IROUTE(27,11,60,60)
+#define GPIO_0034_IROUTE                IROUTE(28,11,60,60)
+#define GPIO_0035_IROUTE                IROUTE(29,11,60,60)
+#define GPIO_0036_IROUTE                IROUTE(30,11,60,60)
+
+//
+// GIRQ12
+//
+#define SMB0_IROUTE                     IROUTE(0,12,61,0)
+#define SMB1_IROUTE                     IROUTE(1,12,61,1)
+#define SMB2_IROUTE                     IROUTE(2,12,61,2)
+#define SMB3_IROUTE                     IROUTE(3,12,61,3)
+#define I2C0_0_WAKE_IROUTE              IROUTE(4,12,61,61)
+#define I2C0_1_WAKE_IROUTE              IROUTE(5,12,61,61)
+#define I2C2_0_WAKE_IROUTE              IROUTE(6,12,61,61)
+#define I2C1_0_WAKE_IROUTE              IROUTE(7,12,61,61)
+#define I2C3_0_WAKE_IROUTE              IROUTE(8,12,61,61)
+
+//
+// GIRQ13
+//
+#define DMA0_IROUTE                     IROUTE(16,13,62,4)
+#define DMA1_IROUTE                     IROUTE(17,13,62,5)
+#define DMA2_IROUTE                     IROUTE(18,13,62,6)
+#define DMA3_IROUTE                     IROUTE(19,13,62,7)
+#define DMA4_IROUTE                     IROUTE(20,13,62,8)
+#define DMA5_IROUTE                     IROUTE(21,13,62,9)
+#define DMA6_IROUTE                     IROUTE(22,13,62,10)
+#define DMA7_IROUTE                     IROUTE(23,13,62,11)
+#define DMA8_IROUTE                     IROUTE(24,13,62,81)
+#define DMA9_IROUTE                     IROUTE(25,13,62,82)
+#define DMA10_IROUTE                    IROUTE(26,13,62,83)
+#define DMA11_IROUTE                    IROUTE(27,13,62,84)
+
+//
+// GIRQ14
+//
+#define LPC_BERR_IROUTE                 IROUTE(2,14,63,12)
+
+//
+// GIRQ15
+//
+#define UART0_IROUTE                    IROUTE(0,15,64,13)
+#define EMI0_IROUTE                     IROUTE(2,15,64,14)
+#define ACPI_EC0_IBF_IROUTE             IROUTE(6,15,64,15)
+#define ACPI_EC0_OBF_IROUTE             IROUTE(7,15,64,16)
+#define ACPI_EC1_IBF_IROUTE             IROUTE(8,15,64,17)
+#define ACPI_EC1_OBF_IROUTE             IROUTE(9,15,64,18)
+#define ACPI_PM1_CTL_IROUTE             IROUTE(10,15,64,19)
+#define ACPI_PM1_EN_IROUTE              IROUTE(11,15,64,20)
+#define ACPI_PM1_STS_IROUTE             IROUTE(12,15,64,21)
+#define EM8042_OBF_IROUTE               IROUTE(13,15,64,22)
+#define EM8042_IBF_IROUTE               IROUTE(14,15,64,23)
+#define MBOX_IROUTE                     IROUTE(15,15,64,24)
+#define MBOX_DATA_IROUTE                IROUTE(16,15,64,40) 
+
+//
+// GIRQ16
+//
+#define PECI_IROUTE                     IROUTE(3,16,65,25)
+
+//
+// GIRQ17
+//
+#define TACH0_IROUTE                    IROUTE(0,17,66,26)
+#define TACH1_IROUTE                    IROUTE(1,17,66,27)
+#define PS2_0_WAKE_IROUTE               IROUTE(2,17,66,66)
+#define PS2_1_WAKE_IROUTE               IROUTE(3,17,66,66)
+#define PS2_2_WAKE_IROUTE               IROUTE(4,17,66,66)
+#define PS2_3_WAKE_IROUTE               IROUTE(5,17,66,66)
+#define BC_WAKE_IROUTE                  IROUTE(6,17,66,66)
+#define ADC_SNGL_IROUTE                 IROUTE(10,17,66,28)
+#define ADC_RPT_IROUTE                  IROUTE(11,17,66,29)
+#define ADC2PWM1_IROUTE                 IROUTE(12,17,66,30)
+#define ADC2PWM2_IROUTE                 IROUTE(13,17,66,31)
+#define PS2_0_IROUTE                    IROUTE(14,17,66,32)
+#define PS2_1_IROUTE                    IROUTE(15,17,66,33)
+#define PS2_2_IROUTE                    IROUTE(16,17,66,34)
+#define PS2_3_IROUTE                    IROUTE(17,17,66,35)
+#define RTC_IROUTE                      IROUTE(18,17,66,91)
+#define RTC_ALARM_IROUTE                IROUTE(19,17,66,92)
+#define HTIMER_IROUTE                   IROUTE(20,17,66,38)
+#define KSC_IROUTE                      IROUTE(21,17,66,39)
+#define KSC_WAKE_IROUTE                 IROUTE(22,17,66,66)
+#define RPM_STALL_IROUTE                IROUTE(23,17,66,41)
+#define RPM_SPIN_IROUTE                 IROUTE(24,17,66,42)
+#define PFR_IROUTE                      IROUTE(25,17,66,43)
+#define PWM_WDT_0_IROUTE                IROUTE(26,17,66,44)
+#define PWM_WDT_1_IROUTE                IROUTE(27,17,66,45)
+#define PWM_WDT_2_IROUTE                IROUTE(28,17,66,46)
+#define BCM_ERR_IROUTE                  IROUTE(29,17,66,47)
+#define BCM_BUSY_IROUTE                 IROUTE(30,17,66,48)
+
+//
+// GIRQ18
+//
+#define SPI0_TX_IROUTE                  IROUTE(0,18,67,36)
+#define SPI0_RX_IROUTE                  IROUTE(1,18,67,37)
+#define SPI1_TX_IROUTE                  IROUTE(2,18,67,55)
+#define SPI1_RX_IROUTE                  IROUTE(3,18,67,56)
+#define LED3_IROUTE                     IROUTE(4,18,67,85)
+#define PKE_ERR_IROUTE                  IROUTE(5,18,67,86)
+#define PKE_END_IROUTE                  IROUTE(6,18,67,87)
+#define NDRNG_IROUTE                    IROUTE(7,18,67,88)
+#define AES_IROUTE                      IROUTE(8,18,67,89)
+#define HASH_IROUTE                     IROUTE(9,18,67,90)
+
+//
+// GIRQ19, Aggregated only
+//
+#define VCC_PWRGD_IROUTE                IROUTE(0,19,68,68)
+#define LRESET_IROUTE                   IROUTE(1,19,68,68)
+
+//
+// GIRQ20, Aggregated only
+//
+#define GPIO_0200_IROUTE                IROUTE(0,20,69,69)
+#define GPIO_0201_IROUTE                IROUTE(1,20,69,69)
+#define GPIO_0202_IROUTE                IROUTE(2,20,69,69)
+#define GPIO_0203_IROUTE                IROUTE(3,20,69,69)
+#define GPIO_0204_IROUTE                IROUTE(4,20,69,69)
+//
+#define GPIO_0206_IROUTE                IROUTE(6,20,69,69)
+//
+#define GPIO_0210_IROUTE                IROUTE(8,20,69,69)
+#define GPIO_0211_IROUTE                IROUTE(9,20,69,69)
+#define GPIO_0212_IROUTE                IROUTE(10,20,69,69)
+#define GPIO_0213_IROUTE                IROUTE(11,20,69,69)
+
+//
+// GIRQ21
+//
+// No sources
+
+//
+// GIRQ22
+//
+// No sources
+
+//
+// GIRQ23
+//
+#define BTMR0_IROUTE                    IROUTE(0,23,72,49)
+#define BTMR1_IROUTE                    IROUTE(1,23,72,50)
+#define BTMR2_IROUTE                    IROUTE(2,23,72,51)
+#define BTMR3_IROUTE                    IROUTE(3,23,72,52)
+#define BTMR4_IROUTE                    IROUTE(4,23,72,53)
+#define BTMR5_IROUTE                    IROUTE(5,23,72,54)
+
+
+//
+// GIRQ08 Bit Positions
+//
+#define GIRQ08_GPIO_0140_BITPOS         (0)
+#define GIRQ08_GPIO_0141_BITPOS         (1)
+#define GIRQ08_GPIO_0142_BITPOS         (2)
+#define GIRQ08_GPIO_0143_BITPOS         (3)
+#define GIRQ08_GPIO_0144_BITPOS         (4)
+#define GIRQ08_GPIO_0145_BITPOS         (5)
+#define GIRQ08_GPIO_0146_BITPOS         (6)
+#define GIRQ08_GPIO_0147_BITPOS         (7)
+//
+#define GIRQ08_GPIO_0150_BITPOS         (8)
+#define GIRQ08_GPIO_0151_BITPOS         (9)
+#define GIRQ08_GPIO_0152_BITPOS         (10)
+#define GIRQ08_GPIO_0153_BITPOS         (11)
+#define GIRQ08_GPIO_0154_BITPOS         (12)
+#define GIRQ08_GPIO_0155_BITPOS         (13)
+#define GIRQ08_GPIO_0156_BITPOS         (14) 
+#define GIRQ08_GPIO_0157_BITPOS         (15)
+//
+#define GIRQ08_GPIO_0160_BITPOS         (16)
+#define GIRQ08_GPIO_0161_BITPOS         (17)
+#define GIRQ08_GPIO_0162_BITPOS         (18)
+#define GIRQ08_GPIO_0163_BITPOS         (19)
+#define GIRQ08_GPIO_0164_BITPOS         (20)
+#define GIRQ08_GPIO_0165_BITPOS         (21)
+#define GIRQ08_GPIO_0166_BITPOS         (22) 
+#define GIRQ08_GPIO_0167_BITPOS         (23)
+//
+#define GIRQ08_MASK                     (0x00FFFFBFul)
+#define GIRQ08_WAKE_CAPABLE_MASK        (0x00FFFFBFul)
+//
+
+//
+// GIRQ09 Bit Positions 
+//
+#define GIRQ09_GPIO_0100_BITPOS         (0)
+#define GIRQ09_GPIO_0101_BITPOS         (1)
+#define GIRQ09_GPIO_0102_BITPOS         (2)
+#define GIRQ09_GPIO_0103_BITPOS         (3)
+#define GIRQ09_GPIO_0104_BITPOS         (4)
+#define GIRQ09_GPIO_0105_BITPOS         (5)
+#define GIRQ09_GPIO_0106_BITPOS         (6) 
+#define GIRQ09_GPIO_0107_BITPOS         (7)
+//
+#define GIRQ09_GPIO_0110_BITPOS         (8)
+#define GIRQ09_GPIO_0111_BITPOS         (9)
+#define GIRQ09_GPIO_0112_BITPOS         (10)
+#define GIRQ09_GPIO_0113_BITPOS         (11)
+#define GIRQ09_GPIO_0114_BITPOS         (12)
+#define GIRQ09_GPIO_0115_BITPOS         (13)
+#define GIRQ09_GPIO_0116_BITPOS         (14) 
+#define GIRQ09_GPIO_0117_BITPOS         (15)
+//
+#define GIRQ09_GPIO_0120_BITPOS         (16)
+#define GIRQ09_GPIO_0121_BITPOS         (17)
+#define GIRQ09_GPIO_0122_BITPOS         (18)
+#define GIRQ09_GPIO_0123_BITPOS         (19)
+#define GIRQ09_GPIO_0124_BITPOS         (20)
+#define GIRQ09_GPIO_0125_BITPOS         (21)
+#define GIRQ09_GPIO_0126_BITPOS         (22) 
+#define GIRQ09_GPIO_0127_BITPOS         (23)
+//
+#define GIRQ09_GPIO_0130_BITPOS         (24)
+#define GIRQ09_GPIO_0131_BITPOS         (25)
+#define GIRQ09_GPIO_0132_BITPOS         (26)
+#define GIRQ09_GPIO_0133_BITPOS         (27)
+#define GIRQ09_GPIO_0134_BITPOS         (28)
+#define GIRQ09_GPIO_0135_BITPOS         (29)
+#define GIRQ09_GPIO_0136_BITPOS         (30) 
+//
+#define GIRQ09_MASK                     (0x7FF7FFFFul)
+#define GIRQ09_WAKE_CAPABLE_MASK        (0x7FF7FFFFul)
+//
+
+//
+// GIRQ10 Bit Positions 
+//
+#define GIRQ10_GPIO_0040_BITPOS         (0)
+#define GIRQ10_GPIO_0041_BITPOS         (1)
+#define GIRQ10_GPIO_0042_BITPOS         (2)
+#define GIRQ10_GPIO_0043_BITPOS         (3)
+#define GIRQ10_GPIO_0044_BITPOS         (4)
+#define GIRQ10_GPIO_0045_BITPOS         (5)
+#define GIRQ10_GPIO_0046_BITPOS         (6) 
+#define GIRQ10_GPIO_0047_BITPOS         (7)
+//
+#define GIRQ10_GPIO_0050_BITPOS         (8)
+#define GIRQ10_GPIO_0051_BITPOS         (9)
+#define GIRQ10_GPIO_0052_BITPOS         (10)
+#define GIRQ10_GPIO_0053_BITPOS         (11)
+#define GIRQ10_GPIO_0054_BITPOS         (12)
+#define GIRQ10_GPIO_0055_BITPOS         (13)
+#define GIRQ10_GPIO_0056_BITPOS         (14) 
+#define GIRQ10_GPIO_0057_BITPOS         (15)
+//
+#define GIRQ10_GPIO_0060_BITPOS         (16)
+#define GIRQ10_GPIO_0061_BITPOS         (17)
+#define GIRQ10_GPIO_0062_BITPOS         (18)
+#define GIRQ10_GPIO_0063_BITPOS         (19)
+#define GIRQ10_GPIO_0064_BITPOS         (20)
+#define GIRQ10_GPIO_0065_BITPOS         (21)
+#define GIRQ10_GPIO_0066_BITPOS         (22) 
+#define GIRQ10_GPIO_0067_BITPOS         (23)
+//
+#define GIRQ10_MASK                     (0x7FFFFFFFul)
+#define GIRQ10_WAKE_CAPABLE_MASK        (0x7FFFFFFFul)
+//
+
+// GIRQ11 Bit Positions 
+#define GIRQ11_GPIO_0000_BITPOS         (0)
+#define GIRQ11_GPIO_0001_BITPOS         (1)
+#define GIRQ11_GPIO_0002_BITPOS         (2)
+#define GIRQ11_GPIO_0003_BITPOS         (3)
+#define GIRQ11_GPIO_0004_BITPOS         (4)
+#define GIRQ11_GPIO_0005_BITPOS         (5)
+#define GIRQ11_GPIO_0006_BITPOS         (6) 
+#define GIRQ11_GPIO_0007_BITPOS         (7)
+//
+#define GIRQ11_GPIO_0010_BITPOS         (8)
+#define GIRQ11_GPIO_0011_BITPOS         (9)
+#define GIRQ11_GPIO_0012_BITPOS         (10)
+#define GIRQ11_GPIO_0013_BITPOS         (11)
+#define GIRQ11_GPIO_0014_BITPOS         (12)
+#define GIRQ11_GPIO_0015_BITPOS         (13)
+#define GIRQ11_GPIO_0016_BITPOS         (14) 
+#define GIRQ11_GPIO_0017_BITPOS         (15)
+//
+#define GIRQ11_GPIO_0020_BITPOS         (16)
+#define GIRQ11_GPIO_0021_BITPOS         (17)
+#define GIRQ11_GPIO_0022_BITPOS         (18)
+#define GIRQ11_GPIO_0023_BITPOS         (19)
+#define GIRQ11_GPIO_0024_BITPOS         (20)
+#define GIRQ11_GPIO_0025_BITPOS         (21)
+#define GIRQ11_GPIO_0026_BITPOS         (22) 
+#define GIRQ11_GPIO_0027_BITPOS         (23)
+//
+#define GIRQ11_GPIO_0030_BITPOS         (24)
+#define GIRQ11_GPIO_0031_BITPOS         (25)
+#define GIRQ11_GPIO_0032_BITPOS         (26)
+#define GIRQ11_GPIO_0033_BITPOS         (27)
+#define GIRQ11_GPIO_0034_BITPOS         (28)
+#define GIRQ11_GPIO_0035_BITPOS         (29)
+#define GIRQ11_GPIO_0036_BITPOS         (30) 
+//
+#define GIRQ11_MASK                     (0x7FFFFFFFul)
+#define GIRQ11_WAKE_CAPABLE_MASK        (0x7FFFFFFFul)
+//
+
+// GIRQ12 Bit Positions 
+#define GIRQ12_SMBUS0_BITPOS            (0)
+#define GIRQ12_SMBUS1_BITPOS            (1)
+#define GIRQ12_SMBUS2_BITPOS            (2)
+#define GIRQ12_SMBUS3_BITPOS            (3)
+#define GIRQ12_I2C0_0_WAKE_BITPOS       (4)
+#define GIRQ12_I2C0_1_WAKE_BITPOS       (5)
+#define GIRQ12_I2C2_0_WAKE_BITPOS       (6)
+#define GIRQ12_I2C1_0_WAKE_BITPOS       (7)
+#define GIRQ12_I2C3_0_WAKE_BITPOS       (8)
+//
+#define GIRQ12_MASK                     (0x01FFul)
+#define GIRQ12_WAKE_CAPABLE_MASK        (0x01F0ul)
+//
+
+//
+// GIRQ13 Bit Positions 
+//
+#define GIRQ13_DMA0_BITPOS              (16)
+#define GIRQ13_DMA1_BITPOS              (17)
+#define GIRQ13_DMA2_BITPOS              (18)
+#define GIRQ13_DMA3_BITPOS              (19)
+#define GIRQ13_DMA4_BITPOS              (20)
+#define GIRQ13_DMA5_BITPOS              (21)
+#define GIRQ13_DMA6_BITPOS              (22)
+#define GIRQ13_DMA7_BITPOS              (23)
+#define GIRQ13_DMA8_BITPOS              (24)
+#define GIRQ13_DMA9_BITPOS              (25)
+#define GIRQ13_DMA10_BITPOS             (26)
+#define GIRQ13_DMA11_BITPOS             (27)
+//
+#define GIRQ13_MASK                     (0x0FFF0000ul)
+#define GIRQ13_WAKE_CAPABLE_MASK        (0x00000000ul)
+//
+
+//
+// GIRQ14 Bit Positions 
+//
+#define GIRQ14_LPC_BITPOS               (2)
+//
+#define GIRQ14_MASK                     (0x04ul)
+#define GIRQ14_WAKE_CAPABLE_MASK        (0x00ul)
+//
+
+//
+// GIRQ15 Bit Positions 
+//
+#define GIRQ15_UART0_BITPOS             (0)
+#define GIRQ15_IMAP_BITPOS              (2)
+#define GIRQ15_ACPI0_IBF_BITPOS         (6)
+#define GIRQ15_ACPI0_OBF_BITPOS         (7)
+#define GIRQ15_ACPI1_IBF_BITPOS         (8)
+#define GIRQ15_ACPI1_OBF_BITPOS         (9)
+#define GIRQ15_ACPI_PM1CTL_BITPOS       (10)
+#define GIRQ15_ACPI_PM1EN_BITPOS        (11)
+#define GIRQ15_ACPI_PM1STS_BITPOS       (12)
+#define GIRQ15_MF8042_OBF_BITPOS        (13)
+#define GIRQ15_MF8042_IBF_BITPOS        (14)
+#define GIRQ15_MAILBOX_BITPOS           (15)
+#define GIRQ15_MAILBOX_DATA_BITPOS      (16)
+//
+#define GIRQ15_MASK                     (0x01FFDDul)
+#define GIRQ15_WAKE_CAPABLE_MASK        (0x000000ul)
+//
+
+//
+// GIRQ16 Bit Positions 
+//
+#define GIRQ16_PECI_BITPOS              (3)
+//
+#define GIRQ16_MASK                     (0x08ul)
+#define GIRQ16_WAKE_CAPABLE_MASK        (0x00ul)
+//
+
+//
+// GIRQ17 Bit Positions 
+//
+#define GIRQ17_TACH0_BITPOS             (0)
+#define GIRQ17_TACH1_BITPOS             (1)
+#define GIRQ17_PS2_0_WAKE_BITPOS        (2)
+#define GIRQ17_PS2_1_WAKE_BITPOS        (3)
+#define GIRQ17_PS2_2_WAKE_BITPOS        (4)
+#define GIRQ17_PS2_3_WAKE_BITPOS        (5)
+#define GIRQ17_BC_WAKE_BITPOS           (6)
+// RESERVED b[9:7]
+#define GIRQ17_ADC_INT0_BITPOS          (10)
+#define GIRQ17_ADC_INT1_BITPOS          (11)
+#define GIRQ17_V2P_INT0_BITPOS          (12)
+#define GIRQ17_V2P_INT1_BITPOS          (13)
+#define GIRQ17_PS2_0_BITPOS             (14)
+#define GIRQ17_PS2_1_BITPOS             (15)
+#define GIRQ17_PS2_2_BITPOS             (16)
+#define GIRQ17_PS2_3_BITPOS             (17)
+#define GIRQ17_RTC_BITPOS               (18)
+#define GIRQ17_RTC_ALARM_BITPOS         (19)
+#define GIRQ17_HIBTMR_BITPOS            (20)
+#define GIRQ17_KEY_INT_BITPOS           (21)
+#define GIRQ17_KEY_INT_WAKE_BITPOS      (22)
+#define GIRQ17_RPM_STALL_BITPOS         (23)
+#define GIRQ17_RPM_SPIN_BITPOS          (24)
+#define GIRQ17_VBAT_BITPOS              (25)
+#define GIRQ17_PWM_WDT_0_BITPOS         (26)
+#define GIRQ17_PWM_WDT_1_BITPOS         (27)
+#define GIRQ17_PWM_WDT_2_BITPOS         (28)
+#define GIRQ17_MBC_ERR_BITPOS           (29)
+#define GIRQ17_MBC_BUSY_BITPOS          (30)
+//
+#define GIRQ17_MASK                     (0x7FF3FC7Ful)
+#define GIRQ17_WAKE_CAPABLE_MASK        (0x0230007Cul)
+//
+
+//
+// GIRQ18 Bit Positions
+//
+#define GIRQ18_SPI0_TX_BITPOS           (0)
+#define GIRQ18_SPI0_RX_BITPOS           (1)
+#define GIRQ18_SPI1_TX_BITPOS           (2)
+#define GIRQ18_SPI1_RX_BITPOS           (3)
+#define GIRQ18_PWM_WDT_3_BITPOS         (4)  // NVIC 85
+#define GIRQ18_PKE_ERR_BITPOS           (5)  // NVIC 86
+#define GIRQ18_PKE_END_BITPOS           (6)  // NVIC 87
+#define GIRQ18_TRNG_BITPOS              (7)  // NVIC 88
+#define GIRQ18_AES_BITPOS               (8)  // NVIC 89
+#define GIRQ18_HASH_BITPOS              (9)  // NVIC 90
+//
+#define GIRQ18_MASK                     (0x0FFul)
+#define GIRQ18_WAKE_CAPABLE_MASK        (0x000ul)
+//
+
+//
+// GIRQ19 Bit Positions
+//
+#define GIRQ19_VCC_PWRGD_BITPOS         (0)
+#define GIRQ19_LRESET_BITPOS            (1)
+//
+#define GIRQ19_MASK                     (0x03ul)
+#define GIRQ19_WAKE_CAPABLE_MASK        (0x03ul)
+//
+
+//
+// GIRQ20 Bit Positions 
+//
+#define GIRQ20_GPIO_0200_BITPOS         (0)
+#define GIRQ20_GPIO_0201_BITPOS         (1)
+#define GIRQ20_GPIO_0202_BITPOS         (2)
+#define GIRQ20_GPIO_0203_BITPOS         (3)
+#define GIRQ20_GPIO_0204_BITPOS         (4)
+//
+#define GIRQ20_GPIO_0206_BITPOS         (6)
+//
+#define GIRQ20_GPIO_0210_BITPOS         (8)
+#define GIRQ20_GPIO_0211_BITPOS         (9)
+#define GIRQ20_GPIO_0212_BITPOS         (10)
+#define GIRQ20_GPIO_0213_BITPOS         (11)
+// 
+#define GIRQ20_MASK                     (0x0F5Ful)
+#define GIRQ20_WAKE_CAPABLE_MASK        (0x0F5Ful)
+//
+
+//
+// GIRQ21 Bit Positions 
+//
+#define GIRQ21_MASK                     (0x00ul)
+#define GIRQ21_WAKE_CAPABLE_MASK        (0x00ul)
+
+//
+// GIRQ22 Bit Positions 
+//
+#define GIRQ22_MASK                     (0x00ul)
+#define GIRQ22_WAKE_CAPABLE_MASK        (0x00ul)
+
+//
+// GIRQ23 Bit Positions 
+//
+#define GIRQ23_TMR0_BITPOS              (0)
+#define GIRQ23_TMR1_BITPOS              (1)
+#define GIRQ23_TMR2_BITPOS              (2)
+#define GIRQ23_TMR3_BITPOS              (3)
+#define GIRQ23_TMR4_BITPOS              (4)
+#define GIRQ23_TMR5_BITPOS              (5)
+//
+#define GIRQ23_MASK                     (0x03Ful)
+#define GIRQ23_WAKE_CAPABLE_MASK        (0x000ul)
+//
+
+
+/* ------------------------------------------------------------------------------- */
+/*                  NVIC,ECIA Routing Policy for Direct Mode                       */
+/* ------------------------------------------------------------------------------- */
+/* In Direct Mode, some interrupts could be configured to be used as aggregated.
+ * Configuration:
+ *      1. Always set ECS Interrupt Direct enable bit.         
+ *      2. If GIRQn aggregated set Block Enable bit.
+ *      3. If GIRQn direct then clear Block Enable bit and enable individual NVIC inputs.
+ *  Switching issues:
+ *  Aggregate enable/disable requires set/clear single GIRQn bit in GIRQ Block En/Clr registers.
+ *  Also requires set/clear of individual NVIC Enables.
+ *  
+ * Note: interrupt_is_girq_direct() internal function uses this policy to detect 
+ * if any interrupt is configured as direct or aggregated
+*/
+
+/** Initialize EC Interrupt Aggregator
+ * @param mode 1 - Direct Map mode, 0 - Fully Aggregated Mode 
+ * @param girq_bitmask - BitMask of GIRQ to be configured as aggregated 
+ *                     This parameter is only applicable in direct mode.
+ * @note All GPIO's and wake capable sources are always 
+ * aggregated! GPIO's interrupts will still work in direct mode.
+ * Block wakes are not be routed to the processor in direct 
+ * mode. 
+ * Note2: This function disables and enables global interrupt  
+ */
+void interrupt_init(uint8_t mode, uint32_t girq_bitmask);
+
+/** Set interrupt routing mode to aggregated or direct. 
+ * @param mode 1 = Direct (except GPIO & wake), 0 = All Aggregated 
+ * @note In direct mode, one could enable certain GIRQs as aggregated using 
+ * p_interrupt_ecia_block_enable_set function
+ */
+void interrupt_mode_set(uint8_t mode);
+
+/** Clears all individual interrupts Enables and Source in ECIA,
+ *  and Clears all NVIC external enables and pending bits  
+ */
+void interrupt_reset(void);
+
+/** Enables interrupt for a device 
+ * @param dev_iroute - source IROUTING information 
+ * @note This function disables and enables global interrupt 
+ */
+void interrupt_device_enable(uint32_t dev_iroute);
+
+/** Disables interrupt for a device
+ * @param dev_iroute - source IROUTING information  
+ * @note This function disables and enables global interrupt 
+ */
+void interrupt_device_disable(uint32_t dev_iroute);
+
+/* ------------------------------------------------------------------------------- */
+/*                  ECIA APIs using device IROUTE() as input                       */ 
+/* ------------------------------------------------------------------------------- */
+
+/** Clear Source in the ECIA for the device  
+ * @param devi - device IROUTING value  
+ */
+void interrupt_device_ecia_source_clear(const uint32_t dev_iroute);
+
+/** Get the Source bit in the ECIA for the device  
+ * @param devi - device IROUTING value  
+ * @return 0 if source bit not set; else non-zero value
+ */
+uint32_t interrupt_device_ecia_source_get(const uint32_t dev_iroute);
+
+/** Get the Result bit in the ECIA for the device  
+ * @param devi - device IROUTING value  
+ * @return 0 if result bit not set; else non-zero value
+ */
+uint32_t interrupt_device_ecia_result_get(const uint32_t dev_iroute);
+
+/* ------------------------------------------------------------------------------- */
+/*                  NVIC APIs using device IROUTE() as input                       */ 
+/* ------------------------------------------------------------------------------- */
+/* Note that if the device interrupt is aggregated, then these APIs would affect the 
+ * NVIC corresponding to the aggregated GIRQ 
+ */
+
+/**  Enable/Disable the NVIC (in the NVIC controller) for the device
+ * @param dev_iroute : source IROUTING information (encoded in a uint32_t)
+ * @param en_flag : 1 = Enable the NVIC IRQ, 0 = Disable the NVIC IRQ 
+ * @note Recommended to use interrupt_device_enable, interrupt_device_disable
+ * to enable/disable interrupts for the device, since those APIs configure ECIA as well
+ */
+void interrupt_device_nvic_enable(uint32_t dev_iroute, uint8_t en_flag);
+
+/** Set NVIC priority for specified peripheral interrupt source
+ * @param dev_iroute - source IROUTING information (encoded in a uint32_t)
+ * @param nvic_pri - NVIC Priority
+ * @note 1. If ECIA is in aggregated mode, the priority affects all interrupt 
+ * sources in the GIRQ. 
+ * 2. This function disables and enables global interrupt    
+ */
+void interrupt_device_nvic_priority_set(const uint32_t dev_iroute, const uint8_t nvic_pri);
+
+/** Return NVIC priority for interrupt source
+ * @param dev_iroute - source IROUTING information 
+ * @return uint32_t  NVIC priority 
+ */
+uint32_t interrupt_device_nvic_priority_get(const uint32_t dev_iroute);
+
+/** Return NVIC pending for interrupt source
+ * @param dev_iroute - source IROUTING information 
+ * @return uint8_t 0(not pending), 1 (pending in NVIC) 
+ *  
+ */
+uint8_t interrupt_device_nvic_pending_get(const uint32_t dev_iroute);
+
+/** Set NVIC pending for interrupt source
+ * @param dev_iroute - source IROUTING information   
+ */
+void interrupt_device_nvic_pending_set(const uint32_t dev_iroute);
+
+/** Clears NVIC pending for interrupt source
+ * @param dev_iroute - source IROUTING information 
+ * @return uint8_t 0(not pending), 1 (pending in NVIC) - before clear 
+ * @note This function disables and enables global interrupt    
+ */
+uint8_t interrupt_device_nvic_pending_clear(const uint32_t dev_iroute);
+    
+/* ------------------------------------------------------------------------------- */
+/* Peripheral Functions - Operations on GIRQ Block Enable Set, Enable Clear        *
+ * and Status Register                                                             */
+/* ------------------------------------------------------------------------------- */
+
+/** Enable specified GIRQ in ECIA block
+ * @param girq_id - enum MEC_GIRQ_IDS 
+ */
+ void p_interrupt_ecia_block_enable_set(uint8_t girq_id);
+  
+ /** Enable GIRQs in ECIA Block 
+ * @param girq_bitmask - Bitmask of GIRQs to be enabled in ECIA Block  
+ */
+void p_interrupt_ecia_block_enable_bitmask_set(uint32_t girq_bitmask);
+
+/** Check if specified GIRQ block enabled or not
+ * @param girq_id - enum MEC_GIRQ_IDS 
+ * @return retVal - 1 if the particular GIRQ block enabled, else 0
+ */
+uint8_t p_interrupt_ecia_block_enable_get(uint8_t girq_id);
+
+/** Set all GIRQ block enables */
+void p_interrupt_ecia_block_enable_all_set(void);
+
+/** Clear specified GIRQ in ECIA Block 
+ * @param girq_id - enum MEC_GIRQ_IDS 
+ */
+void p_interrupt_ecia_block_enable_clr(uint8_t girq_id);
+
+/** Clear GIRQs in ECIA Block 
+ * @param girq_bitmask - Bitmask of GIRQs to be cleared in ECIA Block  
+ */
+void p_interrupt_ecia_block_enable_bitmask_clr(uint32_t girq_bitmask);
+
+/** p_interrupt_ecia_block_enable_all_clr - Clears all GIRQ block enables */
+void p_interrupt_ecia_block_enable_all_clr(void);
+ 
+ /** Get status of GIRQ in ECIA Block
+ * @param girq_id - enum MEC_GIRQ_IDS  
+ * @return 0 if status bit not set; else non-zero value
+ */
+uint32_t p_interrupt_ecia_block_irq_status_get(uint8_t girq_id);
+
+/** Reads the Block IRQ Vector Register
+  * @return 32-bit value
+ */
+uint32_t p_interrupt_ecia_block_irq_all_status_get(void);
+
+/* ---------------------------------------------------------------------------- */
+/* Peripheral Functions - Operations on GIRQx Source, Enable, Result            *
+ * and Enable Registers                                                         */
+/* ---------------------------------------------------------------------------- */
+
+/** Clear specified interrupt source bit in GIRQx
+ * @param girq_id - enum MEC_GIRQ_IDS
+ * @param bitnum -[0, 31]
+ */
+void p_interrupt_ecia_girq_source_clr(int16_t girq_id, uint8_t bitnum);
+
+/** Read the specified interrupt source bit in GIRQx
+ * @param girq_id - enum MEC_GIRQ_IDS
+ * @param bitnum -[0, 31]
+ * @return 0 if source bit not set; else non-zero value
+ */
+uint32_t p_interrupt_ecia_girq_source_get(int16_t girq_id, uint8_t bitnum);
+
+/** Enable the specified interrupt in GIRQx
+ * girq_id - enum MEC_GIRQ_IDS
+ * bitnum = [0, 31]
+ */
+void p_interrupt_ecia_girq_enable_set(uint16_t girq_id, uint8_t bitnum);
+
+/** Disable the specified interrupt in GIRQx
+ * girq_id - enum MEC_GIRQ_IDS
+ * bitnum = [0, 31]
+ */
+void p_interrupt_ecia_girq_enable_clr(uint16_t girq_id, uint8_t bitnum);
+
+/** Read the status of the specified interrupt in GIRQx
+ * girq_id - enum MEC_GIRQ_IDS
+ * bitnum = [0, 31]
+ * @return 0 if enable bit not set; else non-zero value
+ */
+uint32_t p_interrupt_ecia_girq_enable_get(uint16_t girq_id, uint8_t bitnum);
+
+/** Read the result bit of the interrupt in GIRQx
+ * @param girq_id - enum MEC_GIRQ_IDS
+ * @param bitnum -[0, 31]
+ * @return 0 if enable bit not set; else non-zero value
+ */
+uint32_t p_interrupt_ecia_girq_result_get(int16_t girq_id, uint8_t bitnum);
+
+/* ------------------------------------------------------------------------------- */
+/* Peripheral Function - Operations on all GIRQs                                   */
+/* ------------------------------------------------------------------------------- */
+
+/** Clear all aggregator GIRQn status registers */
+void p_interrupt_ecia_girqs_source_reset(void);
+
+/** Clear all aggregator GIRQn enables */
+ void p_interrupt_ecia_girqs_enable_reset(void);
+ 
+/* ------------------------------------------------------------------------------- */
+/* Peripheral Function - Function to set interrupt control                         */
+/* ------------------------------------------------------------------------------- */
+
+/** Set interrupt control 
+ * @param nvic_en_flag : 0 = Alternate NVIC disabled, 1 = Alternate NVIC enabled
+ */
+void p_interrupt_control_set(uint8_t nvic_en_flag);
+     
+ /** Read interrupt control 
+ * @return uint8_t - 0 = Alternate NVIC disabled, 1 = Alternate NVIC enabled
+ */
+uint8_t p_interrupt_control_get(void);
+
+/* ------------------------------------------------------------------------------- */
+/* Peripheral Functions - NVIC                                                     */
+/* ------------------------------------------------------------------------------- */
+
+/**  Enable/Disable the NVIC IRQ in the NVIC interrupt controller
+ * @param nvic_num : NVIC number (see enum IRQn_Type)
+ * @param en_flag : 1 = Enable the NVIC IRQ, 0 = Disable the NVIC IRQ
+ * @note Application should perform this operation
+ */
+void p_interrupt_nvic_enable(IRQn_Type nvic_num, uint8_t en_flag);
+     
+ /**  ecia_nvic_clr_en - Clear all NVIC external enables */ 
+void p_interrupt_nvic_extEnables_clr(void);
+
+/** Clear all NVIC external enables and pending bits */
+void p_interrupt_nvic_enpend_clr(void);
+
+/** Set NVIC external priorities to POR value */
+void p_interrupt_nvic_priorities_default_set(void);
+
+/** Set NVIC external priorities to specified priority (0 - 7)
+ * @param zero-based 3-bit priority value: 0=highest, 7=lowest.
+ * @note NVIC highest priority is the value 0, lowest is all 1's.
+ * Each external interrupt has an 8-bit register and the priority 
+ * is left justified in the registers. MECxxx implements 8 priority 
+ * levels or bits [7:5] in the register. Lowest priority = 0xE0
+ */
+void p_interrupt_nvic_priorities_set(uint8_t new_pri);
+
+#endif // #ifndef _INTERRUPT_H
+/* end interrupt.h */
+/**   @}
+ */
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/pcr/pcr.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/pcr/pcr.h
index 10710ead3..f4d75862b 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/pcr/pcr.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/pcr/pcr.h
@@ -1,462 +1,462 @@
-/*****************************************************************************
-* � 2015 Microchip Technology Inc. and its subsidiaries.
-* You may use this software and any derivatives exclusively with
-* Microchip products.
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
-* OF THESE TERMS.
-******************************************************************************
-
-Version Control Information (Perforce)
-******************************************************************************
-$Revision: #1 $ 
-$DateTime: 2015/11/24 06:28:28 $ 
-$Author: amohandas $
-Last Change:	Updated for tabs
-******************************************************************************/
-/** @file pcr.h
-* \brief Power, Clocks, and Resets Header file
-* \author jvasanth
-* 
-* This file is the PCR header file  
-******************************************************************************/
-
-/** @defgroup PCR
- *  @{
- */
-
-#ifndef _PCR_H
-#define _PCR_H
-
-
-/******************************************************************************/
-/**  PCR Register IDS 
- *******************************************************************************/
-enum _PCR_REGSET_ID_
-{
-	PCR_REG_CHIP_SLEEP_ENABLE =0,
-	PCR_REG_CHIP_CLK_REQD_STS,
-	PCR_REG_EC_SLEEP_ENABLE,
-	PCR_REG_EC_CLK_REQD_STS,
-	PCR_REG_HOST_SLEEP_ENABLE,
-	PCR_REG_HOST_CLK_REQD_STS,
-	PCR_REG_SYSTEM_SLEEP_CTRL,	
-	PCR_REG_PROCESSOR_CLK_CTRL = 8,
-	PCR_REG_EC_SLEEP_ENABLE_2,
-	PCR_REG_EC_CLK_REQD_STS_2,
-	PCR_REG_SLOW_CLK_CTRL,
-	PCR_REG_OSCILLATOR_ID,
-	PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS,
-	PCR_REG_CHIP_RESET_ENABLE,
-	PCR_REG_HOST_RESET_ENABLE,
-	PCR_REG_EC_RESET_ENABLE,
-	PCR_REG_EC_RESET_ENABLE_2,
-	PCR_REG_PWR_RESET_CTRL
-};
-/* ---------------------------------------------------------------------- */
-
-// Encode the Register ids for Sleep Enable, Clock Required, Reset Enable
-//PCR register group 0 - CHIP
-#define PCR0_REGS_CHIP		(((uint32_t)(PCR_REG_CHIP_SLEEP_ENABLE) & 0xFF) + \
-							(((uint32_t)(PCR_REG_CHIP_CLK_REQD_STS) & 0xFF)<<8u) + \
-							(((uint32_t)(PCR_REG_CHIP_RESET_ENABLE) & 0xFF)<<16u))
-
-//PCR register group 1 - EC
-#define PCR1_REGS_EC		(((uint32_t)(PCR_REG_EC_SLEEP_ENABLE) & 0xFF) + \
-							(((uint32_t)(PCR_REG_EC_CLK_REQD_STS) & 0xFF)<<8u) + \
-							(((uint32_t)(PCR_REG_EC_RESET_ENABLE) & 0xFF)<<16u))
-
-//PCR register group 2 - HOST
-#define PCR2_REGS_HOST		(((uint32_t)(PCR_REG_EC_SLEEP_ENABLE) & 0xFF) + \
-							(((uint32_t)(PCR_REG_EC_CLK_REQD_STS) & 0xFF)<<8u) + \
-							(((uint32_t)(PCR_REG_EC_RESET_ENABLE) & 0xFF)<<16u))
-
-//PCR register group 3 - EC 2
-#define PCR3_REGS_EC2		(((uint32_t)(PCR_REG_EC_SLEEP_ENABLE_2) & 0xFF) + \
-							(((uint32_t)(PCR_REG_EC_CLK_REQD_STS_2) & 0xFF)<<8u) + \
-							(((uint32_t)(PCR_REG_EC_RESET_ENABLE_2) & 0xFF)<<16u))
-													
-												
-//PCR1_EC -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions
-#define PCR1_EC_INT_BITPOS           (0u)
-#define PCR1_EC_PECI_BITPOS          (1u)
-#define PCR1_EC_TACH0_BITPOS         (2u)
-#define PCR1_EC_PWM0_BITPOS          (4u)
-#define PCR1_EC_PMC_BITPOS           (5u)
-#define PCR1_EC_DMA_BITPOS           (6u)
-#define PCR1_EC_TFDP_BITPOS          (7u)
-#define PCR1_EC_CPU_BITPOS           (8u)
-#define PCR1_EC_WDT_BITPOS           (9u)
-#define PCR1_EC_SMB0_BITPOS          (10u)
-#define PCR1_EC_TACH1_BITPOS         (11u)
-#define PCR1_EC_PWM1_BITPOS          (20u)
-#define PCR1_EC_PWM2_BITPOS          (21u)
-#define PCR1_EC_PWM3_BITPOS          (22u)
-#define PCR1_EC_REG_BITPOS           (29u)
-#define PCR1_EC_BTIMER0_BITPOS       (30u)
-#define PCR1_EC_BTIMER1_BITPOS       (31u)
-
-//PCR2_HOST -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions
-#define PCR2_HOST_LPC_BITPOS      		  (0u)
-#define PCR2_HOST_UART0_BITPOS    		  (1u)
-#define PCR2_HOST_GLBL_CFG_BITPOS 		  (12u)
-#define PCR2_HOST_ACPI_EC0_BITPOS 		  (13u)
-#define PCR2_HOST_ACPI_EC1_BITPOS 		  (14u)
-#define PCR2_HOST_ACPI_PM1_BITPOS 		  (15u)
-#define PCR2_HOST_8042EM_BITPOS	  		  (16u)
-#define PCR2_HOST_RTC_BITPOS      		  (18u)
-
-//PCR3_EC2 -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions
-#define PCR3_EC2_ADC_BITPOS      		   (3u)
-#define PCR3_EC2_PS2_0_BITPOS    		   (5u)
-#define PCR3_EC2_PS2_1_BITPOS    		   (6u)
-#define PCR3_EC2_PS2_2_BITPOS    		   (7u)
-#define PCR3_EC2_PS2_3_BITPOS    		   (8u)
-#define PCR3_EC2_SPI0_BITPOS     		   (9u)
-#define PCR3_EC2_HTIMER_BITPOS   		   (10u)
-#define PCR3_EC2_KEYSCAN_BITPOS  		   (11u)
-#define PCR3_EC2_RPM_PWM_BITPOS  		   (12u)
-#define PCR3_EC2_SMB1_BITPOS     		   (13u)
-#define PCR3_EC2_SMB2_BITPOS     		   (14u)
-#define PCR3_EC2_SMB3_BITPOS     		   (15u)
-#define PCR3_EC2_LED0_BITPOS     		   (16u)
-#define PCR3_EC2_LED1_BITPOS     		   (17u)
-#define PCR3_EC2_LED2_BITPOS     		   (18u)
-#define PCR3_EC2_BCM_BITPOS      		   (19u)
-#define PCR3_EC2_SPI1_BITPOS     		   (20u)
-#define PCR3_EC2_BTIMER2_BITPOS  		   (21u)
-#define PCR3_EC2_BTIMER3_BITPOS  		   (22u)
-#define PCR3_EC2_BTIMER4_BITPOS  		   (23u)
-#define PCR3_EC2_BTIMER5_BITPOS  		   (24u)
-#define PCR3_EC2_LED3_BITPOS     		   (25u)
-
-/*
- *  n = b[7:0]   = PCR Reg Bit Position
- *  m = b[31:8]  = PCRx Regs IDs
- */
-//#define PCRx_REGS_BIT(m,n) ((((uint32_t)(m)&0xFFFFFFul)<<8u) + ((uint32_t)(n)&0xFFul)) 
-
-//PCRx_REGS_BIT positions 													
-#define	PCRx_REGS_POS_SLEEP_ENABLE				(8u)
-#define	PCRx_REGS_POS_CLK_REQD_STS				(16u)
-#define	PCRx_REGS_POS_RESET_ENABLE				(24u)													
-
-
-/******************************************************************************/
-/**  PCR Block IDS. 
- * These IDs are used to directly refer to a block 
- *******************************************************************************/
-typedef enum {
-	PCR_INT				= (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_INT_BITPOS & 0xFFu)),  	
-	PCR_PECI			= (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PECI_BITPOS & 0xFFu)), 	
-	PCR_TACH0			= (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TACH0_BITPOS & 0xFFu)), 	
-	PCR_PWM0			= (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM0_BITPOS & 0xFFu)),  	
-	PCR_PMC				= (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PMC_BITPOS & 0xFFu)),   	
-	PCR_DMA				= (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_DMA_BITPOS & 0xFFu)),  	
-	PCR_TFDP			= (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TFDP_BITPOS & 0xFFu)),  	
-	PCR_CPU				= (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_CPU_BITPOS & 0xFFu)),   	
-	PCR_WDT				= (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_WDT_BITPOS & 0xFFu)),   	
-	PCR_SMB0			= (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_SMB0_BITPOS & 0xFFu)), 	
-	PCR_TACH1			= (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TACH1_BITPOS & 0xFFu)), 	
-	PCR_PWM1			= (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM1_BITPOS & 0xFFu)),  	
-	PCR_PWM2			= (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM2_BITPOS & 0xFFu)),  	
-	PCR_PWM3			= (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM3_BITPOS & 0xFFu)),  	
-	PCR_REG				= (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_REG_BITPOS & 0xFFu)),   	
-	PCR_BTIMER0			= (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_BTIMER0_BITPOS & 0xFFu)),	
-	PCR_BTIMER1			= (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_BTIMER1_BITPOS & 0xFFu)),	
-	PCR_LPC				= (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_LPC_BITPOS & 0xFFu)),
-	PCR_UART0			= (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_UART0_BITPOS & 0xFFu)),
-	PCR_GLBL_CFG		= (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_GLBL_CFG_BITPOS & 0xFFu)),
-	PCR_ACPI_EC0		= (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_ACPI_EC0_BITPOS & 0xFFu)),
-	PCR_ACPI_EC1		= (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_ACPI_EC1_BITPOS & 0xFFu)),
-	PCR_ACPI_PM1		= (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_ACPI_PM1_BITPOS & 0xFFu)),
-	PCR_8042EM			= (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_8042EM_BITPOS & 0xFFu)),
-	PCR_RTC				= (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_RTC_BITPOS & 0xFFu)),
-	PCR_ADC				= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_ADC_BITPOS & 0xFFu)),
-	PCR_PS2_0			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_0_BITPOS & 0xFFu)),    	
-	PCR_PS2_1			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_1_BITPOS & 0xFFu)),    	
-	PCR_PS2_2			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_2_BITPOS & 0xFFu)),    	
-	PCR_PS2_3			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_3_BITPOS & 0xFFu)),    	
-	PCR_SPI0			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SPI0_BITPOS & 0xFFu)),     	
-	PCR_HTIMER			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_HTIMER_BITPOS & 0xFFu)),      	
-	PCR_KEYSCAN			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_KEYSCAN_BITPOS & 0xFFu)),      	
-	PCR_RPM_PWM			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_RPM_PWM_BITPOS & 0xFFu)),      	
-	PCR_SMB1			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SMB1_BITPOS & 0xFFu)),     	
-	PCR_SMB2			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SMB2_BITPOS & 0xFFu)),    	
-	PCR_SMB3			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SMB3_BITPOS & 0xFFu)),     	
-	PCR_LED0			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED0_BITPOS & 0xFFu)),     	
-	PCR_LED1			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED1_BITPOS & 0xFFu)),     	
-	PCR_LED2			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED2_BITPOS & 0xFFu)),     	
-	PCR_BCM				= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BCM_BITPOS & 0xFFu)),   
-	PCR_SPI1			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SPI1_BITPOS & 0xFFu)),     	
-	PCR_BTIMER2			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER2_BITPOS & 0xFFu)),   	
-	PCR_BTIMER3			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER3_BITPOS & 0xFFu)),   	
-	PCR_BTIMER4			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER4_BITPOS & 0xFFu)),   	
-	PCR_BTIMER5			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER5_BITPOS & 0xFFu)),   	
-	PCR_LED3			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED3_BITPOS & 0xFFu)),	
-} PCR_BLK_ID;
-
-
-/******************************************************************************/
-/**  PCR Processor ClK Divide Values 
- *******************************************************************************/
-enum PROCESSOR_CLK_DIVIDE_VALUE
-{
-	PCR_CPU_CLK_DIVIDE_1 = 1,
-	PCR_CPU_CLK_DIVIDE_4 = 4,
-	PCR_CPU_CLK_DIVIDE_16 = 16,
-	PCR_CPU_CLK_DIVIDE_48 = 48	
-};
-
-/******************************************************************************/
-/**  System Sleep Modes 
- *******************************************************************************/
-enum SYSTEM_SLEEP_MODES
-{
-	SYSTEM_HEAVY_SLEEP_1 = 0,	
-	SYSTEM_HEAVY_SLEEP_3 = 1,
-	SYSTEM_HEAVY_SLEEP_2 = 2,
-	SYSTEM_DEEPEST_SLEEP = 5	
-};
-
-/* Bitmask for System Sleep Control Register */
-#define PCR_SYS_SLP_CTRL_RING_OSC_PWR_DOWN_BITMASK			(1UL<<0)
-#define PCR_SYS_SLP_CTRL_RING_OSC_OUTPUT_GATE_BITMASK		(1UL<<1)
-#define PCR_SYS_SLP_CTRL_CORE_REGLTOR_STDBY_BITMASK			(1UL<<2)
-
-/* Bitmask for Chip Sub-system Power Reset Status Register */
-#define PCR_CHIP_SUBSYSTEM_VCC_RESET_STS_BITMASK			(1UL<<2)
-#define PCR_CHIP_SUBSYSTEM_SIO_RESET_STS_BITMASK			(1UL<<3)
-#define PCR_CHIP_SUBSYSTEM_VBAT_RESET_STS_BITMASK			(1UL<<5)
-#define PCR_CHIP_SUBSYSTEM_VCC1_RESET_STS_BITMASK			(1UL<<6)
-#define PCR_CHIP_SUBSYSTEM_32K_ACTIVE_STS_BITMASK			(1UL<<10)
-#define PCR_CHIP_SUBSYSTEM_PCICLK_ACTIVE_STS_BITMASK		(1UL<<11)
-
-/* Bitmask for Processor Clock Control Register */
-#define PCR_OSCILLATOR_LOCK_STATUS_BITMASK					(1UL<<8)
-
-/* Bitmask for Power Reset Control Register */
-#define PCR_iRESET_OUT_BITMASK								(1UL<<0)
-
-/* ---------------------------------------------------------------------- */
-/*  API - Functions to program Sleep Enable, CLK Reqd Status,             *
- *  Reset Enable for a block                                              *
- * ---------------------------------------------------------------------- */
- /** Sets or Clears block specific bit in PCR Sleep Enable Register
- * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT 
- * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Sleep Enable Register
- */
-void pcr_sleep_enable(uint32_t pcr_block_id, uint8_t set_clr_flag);
-
-/** Get Clock Required Status for the block
- * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT 
- * @return uint8_t - 1 if Clock Required Status set, else 0
- */
-uint8_t pcr_clock_reqd_status_get(uint32_t pcr_block_id);
-
-/** Sets or Clears Reset Enable register bit for the block
- * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT 
- * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Reset Enable Register
- */
-void pcr_reset_enable(uint32_t pcr_block_id, uint8_t set_clr_flag);
-
-/* ---------------------------------------------------------------------- */
-/*  API -   Functions for entering low power modes                        */
-/* ---------------------------------------------------------------------- */
-/** Instructs all blocks to sleep by setting the Sleep Enable bits */
-void pcr_all_blocks_sleep(void);
-
-/** Clears the Sleep Enable bits for all blocks */
-void pcr_all_blocks_wake(void);
-
-/** Programs required sleep mode in System Sleep Control Register
- * @param sleep_mode - see enum SYSTEM_SLEEP_MODES
- */
-void pcr_system_sleep(uint8_t sleep_mode);
-
-/* ---------------------------------------------------------------------- */
-/* Peripheral Function - Functions to program and read 32-bit values      *
- * from PCR Registers                                                     *
- * ---------------------------------------------------------------------- */
- /** Write 32-bit value in the PCR Register
- * @param pcr_reg_id - pcr register id 
- * @param value - 32-bit value
- */
-void p_pcr_reg_write(uint8_t pcr_reg_id, uint32_t value);
-
-/** Reads 32-bit value from the PCR Register
- * @param pcr_reg_id - pcr register id 
- * @return value - 32-bit value
- */
-uint32_t p_pcr_reg_read(uint8_t pcr_reg_id);
-
-/* ---------------------------------------------------------------------- */
-/* Peripheral Function - Functions to set, clr and get bits in            *
- * PCR Registers                                                          * 
- * ---------------------------------------------------------------------- */
- /** Sets bits in a PCR Register
- * @param pcr_reg_id - pcr register id 
- * @param bit_mask - Bit mask of bits to set 
- */
-void p_pcr_reg_set(uint8_t pcr_reg_id, uint32_t bit_mask);
-
-/** Clears bits in a PCR Register
- * @param pcr_reg_id - pcr register id 
- * @param bit_mask - Bit mask of bits to clear 
- */
-void p_pcr_reg_clr(uint8_t pcr_reg_id, uint32_t bit_mask);
-
-/** Read bits in a PCR Register
- * @param pcr_reg_id - pcr register id 
- * @param bit_mask - Bit mask of bits to read 
- * @return value - 32-bit value
- */
-uint32_t p_pcr_reg_get(uint8_t pcr_reg_id, uint32_t bit_mask);
-
-/** Sets or Clears bits in a PCR Register - Helper Function
- * @param pcr_reg_id - pcr register id 
- * @param bit_mask - Bit mask of bits to set or clear
- * @param set_clr_flag - Flag to set (1) or clear (0) bits in the PCR Register
- */
-void p_pcr_reg_update(uint8_t pcr_reg_id, uint32_t bit_mask, uint8_t set_clr_flag);
-	
-//Functions to operate on System Sleep Control Register	
-
-/* ---------------------------------------------------------------------- */
-/* Peripheral Function - Functions to operate on System Sleep Control     *
- * Register                                                               * 
- * ---------------------------------------------------------------------- */
-/** Sets/Clears the Ring oscillator power down bit 
- *         in System Sleep Control Register
- * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit
- */
-void p_pcr_system_sleep_ctrl_ring_osc_power_down(uint8_t set_clr_flag);
-
-/** Sets/Clears the Ring oscillator output gate bit 
- *         in System Sleep Control Register
- * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit
- */
-void p_pcr_system_sleep_ctrl_ring_osc_output_gate(uint8_t set_clr_flag);
-
-/** Sets/Clears the Core regulator standby bit 
- *         in System Sleep Control Register
- * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit
- */
-void p_pcr_system_sleep_ctrl_core_regulator_stdby(uint8_t set_clr_flag);
-
-/** Writes required sleep mode in System Sleep Control Register
- * @param sleep_value - System Sleep control value - [D2, D1, D0]
- */
-void p_pcr_system_sleep_ctrl_write(uint8_t sleep_value);
-
-/** Reads the System Sleep Control PCR Register
- * @return value - byte 0 of the system sleep control PCR register
- */
-uint8_t p_pcr_system_sleep_ctrl_read(void);
-
-/* ---------------------------------------------------------------------- */
-/* Peripheral Function - Function to program to CLK Divide Value          * 
- * ---------------------------------------------------------------------- */
- /** Writes the clock divide value in the Processor Clock Control Register
- * @param clk_divide_value - clk divide values, valid values in enum PROCESSOR_CLK_DIVIDE_VALUE
- */
-void p_pcr_processor_clk_ctrl_write(uint8_t clk_divide_value);
-
-/* ---------------------------------------------------------------------- */
-/* Peripheral Function - Function to program the Slow Clock Control       *
- * Register                                                               *
- * ---------------------------------------------------------------------- */
- /** Write the slow clock divide value in the Slow Clock Control Register
- * @param slow_clk_divide_value - slow clk divide value
- */
-void p_pcr_slow_clk_ctrl_write(uint8_t slow_clk_divide_value);
-
-/* ---------------------------------------------------------------------- */
-/* Peripheral Function - Function to read the Oscillator Lock Status      */ 
-/* ---------------------------------------------------------------------- */
-/** Reads the Oscillator Lock status bit in the Oscillator ID Register
- * @return 1 if Oscillator Lock Status bit is set, else 0
- */
-uint8_t p_pcr_oscillator_lock_sts_get(void);
-
-/* ---------------------------------------------------------------------- */
-/* Peripheral Function - Functions to read various power status in        *
- * Chip Sub-System register                                               *
- * ---------------------------------------------------------------------- */
- /** Reads the VCC Reset Status bit 
- *        in the Chip Subsystem Power Reset Status Register
- * @return 1 if VCC Reset Status bit is set, else 0
- */
-uint8_t p_pcr_chip_subsystem_vcc_reset_sts_get(void);
-
-/** Reads the SIO Reset Status bit 
- *        in the Chip Subsystem Power Reset Status Register
- * @return 1 if SIO Reset Status bit is set, else 0
- */
-uint8_t p_pcr_chip_subsystem_sio_reset_sts_get(void);
-
-/** Reads the VBAT Reset Status bit 
- *        in the Chip Subsystem Power Reset Status Register
- * @return 1 if VBAT Reset Status bit is set, else 0
- */
-uint8_t p_pcr_chip_subsystem_vbat_reset_sts_get(void);
-
-/** Clears the VBAT Reset Status bit 
- *        in the Chip Subsystem Power Reset Status Register 
- */
-void p_pcr_chip_subsystem_vbat_reset_sts_clr(void);
-
-/** Reads the VCC1 Reset Status bit 
- *        in the Chip Subsystem Power Reset Status Register
- * @return 1 if VCC1 Reset Status bit is set, else 0
- */
-uint8_t p_pcr_chip_subsystem_vcc1_reset_sts_get(void);
-
-/** Clears the VCC1 Reset Status bit 
- *        in the Chip Subsystem Power Reset Status Register 
- */
-void p_pcr_chip_subsystem_vcc1_reset_sts_clr(void);
-
-/** Reads the 32K_ACTIVE status bit 
- *        in the Chip Subsystem Power Reset Status Register
- * @return 1 if 32_ACTIVE bit is set, else 0
- */
-uint8_t p_pcr_chip_subsystem_32K_active_sts_get(void);
-
-/** Reads the PCICLK_ACTIVE status bit 
- *        in the Chip Subsystem Power Reset Status Register
- * @return 1 if CICLK_ACTIVE bit is set, else 0
- */
-uint8_t p_pcr_chip_subsystem_pciclk_active_sts_get(void);
-
-/* ---------------------------------------------------------------------- */
-/* Peripheral Function - Functions for Power Reset Control Register       */ 
-/* ---------------------------------------------------------------------- */
-/** Reads the iRESET_OUT bit in the Power Reset Control Register
- * @return 1 if iRESET_OUT bit is set, else 0
- */
-uint8_t p_pcr_iReset_Out_get(void);
-
-/** Sets/Clears the iRESET_OUT bit in the Power Reset Control Register
- * @param 1 Set iRESET_OUT bit; 0 - Clear the bit
- */
-void p_pcr_iReset_Out(uint8_t set_clr_flag);
-
-#endif // #ifndef _PCR_H
-/* end pcr.h */
-/**   @}
- */
-
-
-
+/*****************************************************************************
+* � 2015 Microchip Technology Inc. and its subsidiaries.
+* You may use this software and any derivatives exclusively with
+* Microchip products.
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
+* OF THESE TERMS.
+******************************************************************************
+
+Version Control Information (Perforce)
+******************************************************************************
+$Revision: #1 $ 
+$DateTime: 2016/04/08 10:18:28 $ 
+$Author: pramans $
+Last Change:	Updated for tabs
+******************************************************************************/
+/** @file pcr.h
+* \brief Power, Clocks, and Resets Header file
+* \author jvasanth
+* 
+* This file is the PCR header file  
+******************************************************************************/
+
+/** @defgroup PCR
+ *  @{
+ */
+
+#ifndef _PCR_H
+#define _PCR_H
+
+
+/******************************************************************************/
+/**  PCR Register IDS 
+ *******************************************************************************/
+enum _PCR_REGSET_ID_
+{
+	PCR_REG_CHIP_SLEEP_ENABLE =0,
+	PCR_REG_CHIP_CLK_REQD_STS,
+	PCR_REG_EC_SLEEP_ENABLE,
+	PCR_REG_EC_CLK_REQD_STS,
+	PCR_REG_HOST_SLEEP_ENABLE,
+	PCR_REG_HOST_CLK_REQD_STS,
+	PCR_REG_SYSTEM_SLEEP_CTRL,	
+	PCR_REG_PROCESSOR_CLK_CTRL = 8,
+	PCR_REG_EC_SLEEP_ENABLE_2,
+	PCR_REG_EC_CLK_REQD_STS_2,
+	PCR_REG_SLOW_CLK_CTRL,
+	PCR_REG_OSCILLATOR_ID,
+	PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS,
+	PCR_REG_CHIP_RESET_ENABLE,
+	PCR_REG_HOST_RESET_ENABLE,
+	PCR_REG_EC_RESET_ENABLE,
+	PCR_REG_EC_RESET_ENABLE_2,
+	PCR_REG_PWR_RESET_CTRL
+};
+/* ---------------------------------------------------------------------- */
+
+// Encode the Register ids for Sleep Enable, Clock Required, Reset Enable
+//PCR register group 0 - CHIP
+#define PCR0_REGS_CHIP		(((uint32_t)(PCR_REG_CHIP_SLEEP_ENABLE) & 0xFF) + \
+							(((uint32_t)(PCR_REG_CHIP_CLK_REQD_STS) & 0xFF)<<8u) + \
+							(((uint32_t)(PCR_REG_CHIP_RESET_ENABLE) & 0xFF)<<16u))
+
+//PCR register group 1 - EC
+#define PCR1_REGS_EC		(((uint32_t)(PCR_REG_EC_SLEEP_ENABLE) & 0xFF) + \
+							(((uint32_t)(PCR_REG_EC_CLK_REQD_STS) & 0xFF)<<8u) + \
+							(((uint32_t)(PCR_REG_EC_RESET_ENABLE) & 0xFF)<<16u))
+
+//PCR register group 2 - HOST
+#define PCR2_REGS_HOST		(((uint32_t)(PCR_REG_EC_SLEEP_ENABLE) & 0xFF) + \
+							(((uint32_t)(PCR_REG_EC_CLK_REQD_STS) & 0xFF)<<8u) + \
+							(((uint32_t)(PCR_REG_EC_RESET_ENABLE) & 0xFF)<<16u))
+
+//PCR register group 3 - EC 2
+#define PCR3_REGS_EC2		(((uint32_t)(PCR_REG_EC_SLEEP_ENABLE_2) & 0xFF) + \
+							(((uint32_t)(PCR_REG_EC_CLK_REQD_STS_2) & 0xFF)<<8u) + \
+							(((uint32_t)(PCR_REG_EC_RESET_ENABLE_2) & 0xFF)<<16u))
+													
+												
+//PCR1_EC -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions
+#define PCR1_EC_INT_BITPOS           (0u)
+#define PCR1_EC_PECI_BITPOS          (1u)
+#define PCR1_EC_TACH0_BITPOS         (2u)
+#define PCR1_EC_PWM0_BITPOS          (4u)
+#define PCR1_EC_PMC_BITPOS           (5u)
+#define PCR1_EC_DMA_BITPOS           (6u)
+#define PCR1_EC_TFDP_BITPOS          (7u)
+#define PCR1_EC_CPU_BITPOS           (8u)
+#define PCR1_EC_WDT_BITPOS           (9u)
+#define PCR1_EC_SMB0_BITPOS          (10u)
+#define PCR1_EC_TACH1_BITPOS         (11u)
+#define PCR1_EC_PWM1_BITPOS          (20u)
+#define PCR1_EC_PWM2_BITPOS          (21u)
+#define PCR1_EC_PWM3_BITPOS          (22u)
+#define PCR1_EC_REG_BITPOS           (29u)
+#define PCR1_EC_BTIMER0_BITPOS       (30u)
+#define PCR1_EC_BTIMER1_BITPOS       (31u)
+
+//PCR2_HOST -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions
+#define PCR2_HOST_LPC_BITPOS      		  (0u)
+#define PCR2_HOST_UART0_BITPOS    		  (1u)
+#define PCR2_HOST_GLBL_CFG_BITPOS 		  (12u)
+#define PCR2_HOST_ACPI_EC0_BITPOS 		  (13u)
+#define PCR2_HOST_ACPI_EC1_BITPOS 		  (14u)
+#define PCR2_HOST_ACPI_PM1_BITPOS 		  (15u)
+#define PCR2_HOST_8042EM_BITPOS	  		  (16u)
+#define PCR2_HOST_RTC_BITPOS      		  (18u)
+
+//PCR3_EC2 -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions
+#define PCR3_EC2_ADC_BITPOS      		   (3u)
+#define PCR3_EC2_PS2_0_BITPOS    		   (5u)
+#define PCR3_EC2_PS2_1_BITPOS    		   (6u)
+#define PCR3_EC2_PS2_2_BITPOS    		   (7u)
+#define PCR3_EC2_PS2_3_BITPOS    		   (8u)
+#define PCR3_EC2_SPI0_BITPOS     		   (9u)
+#define PCR3_EC2_HTIMER_BITPOS   		   (10u)
+#define PCR3_EC2_KEYSCAN_BITPOS  		   (11u)
+#define PCR3_EC2_RPM_PWM_BITPOS  		   (12u)
+#define PCR3_EC2_SMB1_BITPOS     		   (13u)
+#define PCR3_EC2_SMB2_BITPOS     		   (14u)
+#define PCR3_EC2_SMB3_BITPOS     		   (15u)
+#define PCR3_EC2_LED0_BITPOS     		   (16u)
+#define PCR3_EC2_LED1_BITPOS     		   (17u)
+#define PCR3_EC2_LED2_BITPOS     		   (18u)
+#define PCR3_EC2_BCM_BITPOS      		   (19u)
+#define PCR3_EC2_SPI1_BITPOS     		   (20u)
+#define PCR3_EC2_BTIMER2_BITPOS  		   (21u)
+#define PCR3_EC2_BTIMER3_BITPOS  		   (22u)
+#define PCR3_EC2_BTIMER4_BITPOS  		   (23u)
+#define PCR3_EC2_BTIMER5_BITPOS  		   (24u)
+#define PCR3_EC2_LED3_BITPOS     		   (25u)
+
+/*
+ *  n = b[7:0]   = PCR Reg Bit Position
+ *  m = b[31:8]  = PCRx Regs IDs
+ */
+//#define PCRx_REGS_BIT(m,n) ((((uint32_t)(m)&0xFFFFFFul)<<8u) + ((uint32_t)(n)&0xFFul)) 
+
+//PCRx_REGS_BIT positions 													
+#define	PCRx_REGS_POS_SLEEP_ENABLE				(8u)
+#define	PCRx_REGS_POS_CLK_REQD_STS				(16u)
+#define	PCRx_REGS_POS_RESET_ENABLE				(24u)													
+
+
+/******************************************************************************/
+/**  PCR Block IDS. 
+ * These IDs are used to directly refer to a block 
+ *******************************************************************************/
+typedef enum {
+	PCR_INT				= (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_INT_BITPOS & 0xFFu)),  	
+	PCR_PECI			= (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PECI_BITPOS & 0xFFu)), 	
+	PCR_TACH0			= (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TACH0_BITPOS & 0xFFu)), 	
+	PCR_PWM0			= (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM0_BITPOS & 0xFFu)),  	
+	PCR_PMC				= (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PMC_BITPOS & 0xFFu)),   	
+	PCR_DMA				= (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_DMA_BITPOS & 0xFFu)),  	
+	PCR_TFDP			= (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TFDP_BITPOS & 0xFFu)),  	
+	PCR_CPU				= (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_CPU_BITPOS & 0xFFu)),   	
+	PCR_WDT				= (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_WDT_BITPOS & 0xFFu)),   	
+	PCR_SMB0			= (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_SMB0_BITPOS & 0xFFu)), 	
+	PCR_TACH1			= (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TACH1_BITPOS & 0xFFu)), 	
+	PCR_PWM1			= (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM1_BITPOS & 0xFFu)),  	
+	PCR_PWM2			= (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM2_BITPOS & 0xFFu)),  	
+	PCR_PWM3			= (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM3_BITPOS & 0xFFu)),  	
+	PCR_REG				= (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_REG_BITPOS & 0xFFu)),   	
+	PCR_BTIMER0			= (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_BTIMER0_BITPOS & 0xFFu)),	
+	PCR_BTIMER1			= (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_BTIMER1_BITPOS & 0xFFu)),	
+	PCR_LPC				= (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_LPC_BITPOS & 0xFFu)),
+	PCR_UART0			= (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_UART0_BITPOS & 0xFFu)),
+	PCR_GLBL_CFG		= (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_GLBL_CFG_BITPOS & 0xFFu)),
+	PCR_ACPI_EC0		= (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_ACPI_EC0_BITPOS & 0xFFu)),
+	PCR_ACPI_EC1		= (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_ACPI_EC1_BITPOS & 0xFFu)),
+	PCR_ACPI_PM1		= (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_ACPI_PM1_BITPOS & 0xFFu)),
+	PCR_8042EM			= (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_8042EM_BITPOS & 0xFFu)),
+	PCR_RTC				= (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_RTC_BITPOS & 0xFFu)),
+	PCR_ADC				= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_ADC_BITPOS & 0xFFu)),
+	PCR_PS2_0			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_0_BITPOS & 0xFFu)),    	
+	PCR_PS2_1			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_1_BITPOS & 0xFFu)),    	
+	PCR_PS2_2			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_2_BITPOS & 0xFFu)),    	
+	PCR_PS2_3			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_3_BITPOS & 0xFFu)),    	
+	PCR_SPI0			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SPI0_BITPOS & 0xFFu)),     	
+	PCR_HTIMER			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_HTIMER_BITPOS & 0xFFu)),      	
+	PCR_KEYSCAN			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_KEYSCAN_BITPOS & 0xFFu)),      	
+	PCR_RPM_PWM			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_RPM_PWM_BITPOS & 0xFFu)),      	
+	PCR_SMB1			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SMB1_BITPOS & 0xFFu)),     	
+	PCR_SMB2			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SMB2_BITPOS & 0xFFu)),    	
+	PCR_SMB3			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SMB3_BITPOS & 0xFFu)),     	
+	PCR_LED0			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED0_BITPOS & 0xFFu)),     	
+	PCR_LED1			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED1_BITPOS & 0xFFu)),     	
+	PCR_LED2			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED2_BITPOS & 0xFFu)),     	
+	PCR_BCM				= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BCM_BITPOS & 0xFFu)),   
+	PCR_SPI1			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SPI1_BITPOS & 0xFFu)),     	
+	PCR_BTIMER2			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER2_BITPOS & 0xFFu)),   	
+	PCR_BTIMER3			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER3_BITPOS & 0xFFu)),   	
+	PCR_BTIMER4			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER4_BITPOS & 0xFFu)),   	
+	PCR_BTIMER5			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER5_BITPOS & 0xFFu)),   	
+	PCR_LED3			= (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED3_BITPOS & 0xFFu)),	
+} PCR_BLK_ID;
+
+
+/******************************************************************************/
+/**  PCR Processor ClK Divide Values 
+ *******************************************************************************/
+enum PROCESSOR_CLK_DIVIDE_VALUE
+{
+	PCR_CPU_CLK_DIVIDE_1 = 1,
+	PCR_CPU_CLK_DIVIDE_4 = 4,
+	PCR_CPU_CLK_DIVIDE_16 = 16,
+	PCR_CPU_CLK_DIVIDE_48 = 48	
+};
+
+/******************************************************************************/
+/**  System Sleep Modes 
+ *******************************************************************************/
+enum SYSTEM_SLEEP_MODES
+{
+	SYSTEM_HEAVY_SLEEP_1 = 0,	
+	SYSTEM_HEAVY_SLEEP_3 = 1,
+	SYSTEM_HEAVY_SLEEP_2 = 2,
+	SYSTEM_DEEPEST_SLEEP = 5	
+};
+
+/* Bitmask for System Sleep Control Register */
+#define PCR_SYS_SLP_CTRL_RING_OSC_PWR_DOWN_BITMASK			(1UL<<0)
+#define PCR_SYS_SLP_CTRL_RING_OSC_OUTPUT_GATE_BITMASK		(1UL<<1)
+#define PCR_SYS_SLP_CTRL_CORE_REGLTOR_STDBY_BITMASK			(1UL<<2)
+
+/* Bitmask for Chip Sub-system Power Reset Status Register */
+#define PCR_CHIP_SUBSYSTEM_VCC_RESET_STS_BITMASK			(1UL<<2)
+#define PCR_CHIP_SUBSYSTEM_SIO_RESET_STS_BITMASK			(1UL<<3)
+#define PCR_CHIP_SUBSYSTEM_VBAT_RESET_STS_BITMASK			(1UL<<5)
+#define PCR_CHIP_SUBSYSTEM_VCC1_RESET_STS_BITMASK			(1UL<<6)
+#define PCR_CHIP_SUBSYSTEM_32K_ACTIVE_STS_BITMASK			(1UL<<10)
+#define PCR_CHIP_SUBSYSTEM_PCICLK_ACTIVE_STS_BITMASK		(1UL<<11)
+
+/* Bitmask for Processor Clock Control Register */
+#define PCR_OSCILLATOR_LOCK_STATUS_BITMASK					(1UL<<8)
+
+/* Bitmask for Power Reset Control Register */
+#define PCR_iRESET_OUT_BITMASK								(1UL<<0)
+
+/* ---------------------------------------------------------------------- */
+/*  API - Functions to program Sleep Enable, CLK Reqd Status,             *
+ *  Reset Enable for a block                                              *
+ * ---------------------------------------------------------------------- */
+ /** Sets or Clears block specific bit in PCR Sleep Enable Register
+ * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT 
+ * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Sleep Enable Register
+ */
+void pcr_sleep_enable(uint32_t pcr_block_id, uint8_t set_clr_flag);
+
+/** Get Clock Required Status for the block
+ * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT 
+ * @return uint8_t - 1 if Clock Required Status set, else 0
+ */
+uint8_t pcr_clock_reqd_status_get(uint32_t pcr_block_id);
+
+/** Sets or Clears Reset Enable register bit for the block
+ * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT 
+ * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Reset Enable Register
+ */
+void pcr_reset_enable(uint32_t pcr_block_id, uint8_t set_clr_flag);
+
+/* ---------------------------------------------------------------------- */
+/*  API -   Functions for entering low power modes                        */
+/* ---------------------------------------------------------------------- */
+/** Instructs all blocks to sleep by setting the Sleep Enable bits */
+void pcr_all_blocks_sleep(void);
+
+/** Clears the Sleep Enable bits for all blocks */
+void pcr_all_blocks_wake(void);
+
+/** Programs required sleep mode in System Sleep Control Register
+ * @param sleep_mode - see enum SYSTEM_SLEEP_MODES
+ */
+void pcr_system_sleep(uint8_t sleep_mode);
+
+/* ---------------------------------------------------------------------- */
+/* Peripheral Function - Functions to program and read 32-bit values      *
+ * from PCR Registers                                                     *
+ * ---------------------------------------------------------------------- */
+ /** Write 32-bit value in the PCR Register
+ * @param pcr_reg_id - pcr register id 
+ * @param value - 32-bit value
+ */
+void p_pcr_reg_write(uint8_t pcr_reg_id, uint32_t value);
+
+/** Reads 32-bit value from the PCR Register
+ * @param pcr_reg_id - pcr register id 
+ * @return value - 32-bit value
+ */
+uint32_t p_pcr_reg_read(uint8_t pcr_reg_id);
+
+/* ---------------------------------------------------------------------- */
+/* Peripheral Function - Functions to set, clr and get bits in            *
+ * PCR Registers                                                          * 
+ * ---------------------------------------------------------------------- */
+ /** Sets bits in a PCR Register
+ * @param pcr_reg_id - pcr register id 
+ * @param bit_mask - Bit mask of bits to set 
+ */
+void p_pcr_reg_set(uint8_t pcr_reg_id, uint32_t bit_mask);
+
+/** Clears bits in a PCR Register
+ * @param pcr_reg_id - pcr register id 
+ * @param bit_mask - Bit mask of bits to clear 
+ */
+void p_pcr_reg_clr(uint8_t pcr_reg_id, uint32_t bit_mask);
+
+/** Read bits in a PCR Register
+ * @param pcr_reg_id - pcr register id 
+ * @param bit_mask - Bit mask of bits to read 
+ * @return value - 32-bit value
+ */
+uint32_t p_pcr_reg_get(uint8_t pcr_reg_id, uint32_t bit_mask);
+
+/** Sets or Clears bits in a PCR Register - Helper Function
+ * @param pcr_reg_id - pcr register id 
+ * @param bit_mask - Bit mask of bits to set or clear
+ * @param set_clr_flag - Flag to set (1) or clear (0) bits in the PCR Register
+ */
+void p_pcr_reg_update(uint8_t pcr_reg_id, uint32_t bit_mask, uint8_t set_clr_flag);
+	
+//Functions to operate on System Sleep Control Register	
+
+/* ---------------------------------------------------------------------- */
+/* Peripheral Function - Functions to operate on System Sleep Control     *
+ * Register                                                               * 
+ * ---------------------------------------------------------------------- */
+/** Sets/Clears the Ring oscillator power down bit 
+ *         in System Sleep Control Register
+ * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit
+ */
+void p_pcr_system_sleep_ctrl_ring_osc_power_down(uint8_t set_clr_flag);
+
+/** Sets/Clears the Ring oscillator output gate bit 
+ *         in System Sleep Control Register
+ * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit
+ */
+void p_pcr_system_sleep_ctrl_ring_osc_output_gate(uint8_t set_clr_flag);
+
+/** Sets/Clears the Core regulator standby bit 
+ *         in System Sleep Control Register
+ * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit
+ */
+void p_pcr_system_sleep_ctrl_core_regulator_stdby(uint8_t set_clr_flag);
+
+/** Writes required sleep mode in System Sleep Control Register
+ * @param sleep_value - System Sleep control value - [D2, D1, D0]
+ */
+void p_pcr_system_sleep_ctrl_write(uint8_t sleep_value);
+
+/** Reads the System Sleep Control PCR Register
+ * @return value - byte 0 of the system sleep control PCR register
+ */
+uint8_t p_pcr_system_sleep_ctrl_read(void);
+
+/* ---------------------------------------------------------------------- */
+/* Peripheral Function - Function to program to CLK Divide Value          * 
+ * ---------------------------------------------------------------------- */
+ /** Writes the clock divide value in the Processor Clock Control Register
+ * @param clk_divide_value - clk divide values, valid values in enum PROCESSOR_CLK_DIVIDE_VALUE
+ */
+void p_pcr_processor_clk_ctrl_write(uint8_t clk_divide_value);
+
+/* ---------------------------------------------------------------------- */
+/* Peripheral Function - Function to program the Slow Clock Control       *
+ * Register                                                               *
+ * ---------------------------------------------------------------------- */
+ /** Write the slow clock divide value in the Slow Clock Control Register
+ * @param slow_clk_divide_value - slow clk divide value
+ */
+void p_pcr_slow_clk_ctrl_write(uint8_t slow_clk_divide_value);
+
+/* ---------------------------------------------------------------------- */
+/* Peripheral Function - Function to read the Oscillator Lock Status      */ 
+/* ---------------------------------------------------------------------- */
+/** Reads the Oscillator Lock status bit in the Oscillator ID Register
+ * @return 1 if Oscillator Lock Status bit is set, else 0
+ */
+uint8_t p_pcr_oscillator_lock_sts_get(void);
+
+/* ---------------------------------------------------------------------- */
+/* Peripheral Function - Functions to read various power status in        *
+ * Chip Sub-System register                                               *
+ * ---------------------------------------------------------------------- */
+ /** Reads the VCC Reset Status bit 
+ *        in the Chip Subsystem Power Reset Status Register
+ * @return 1 if VCC Reset Status bit is set, else 0
+ */
+uint8_t p_pcr_chip_subsystem_vcc_reset_sts_get(void);
+
+/** Reads the SIO Reset Status bit 
+ *        in the Chip Subsystem Power Reset Status Register
+ * @return 1 if SIO Reset Status bit is set, else 0
+ */
+uint8_t p_pcr_chip_subsystem_sio_reset_sts_get(void);
+
+/** Reads the VBAT Reset Status bit 
+ *        in the Chip Subsystem Power Reset Status Register
+ * @return 1 if VBAT Reset Status bit is set, else 0
+ */
+uint8_t p_pcr_chip_subsystem_vbat_reset_sts_get(void);
+
+/** Clears the VBAT Reset Status bit 
+ *        in the Chip Subsystem Power Reset Status Register 
+ */
+void p_pcr_chip_subsystem_vbat_reset_sts_clr(void);
+
+/** Reads the VCC1 Reset Status bit 
+ *        in the Chip Subsystem Power Reset Status Register
+ * @return 1 if VCC1 Reset Status bit is set, else 0
+ */
+uint8_t p_pcr_chip_subsystem_vcc1_reset_sts_get(void);
+
+/** Clears the VCC1 Reset Status bit 
+ *        in the Chip Subsystem Power Reset Status Register 
+ */
+void p_pcr_chip_subsystem_vcc1_reset_sts_clr(void);
+
+/** Reads the 32K_ACTIVE status bit 
+ *        in the Chip Subsystem Power Reset Status Register
+ * @return 1 if 32_ACTIVE bit is set, else 0
+ */
+uint8_t p_pcr_chip_subsystem_32K_active_sts_get(void);
+
+/** Reads the PCICLK_ACTIVE status bit 
+ *        in the Chip Subsystem Power Reset Status Register
+ * @return 1 if CICLK_ACTIVE bit is set, else 0
+ */
+uint8_t p_pcr_chip_subsystem_pciclk_active_sts_get(void);
+
+/* ---------------------------------------------------------------------- */
+/* Peripheral Function - Functions for Power Reset Control Register       */ 
+/* ---------------------------------------------------------------------- */
+/** Reads the iRESET_OUT bit in the Power Reset Control Register
+ * @return 1 if iRESET_OUT bit is set, else 0
+ */
+uint8_t p_pcr_iReset_Out_get(void);
+
+/** Sets/Clears the iRESET_OUT bit in the Power Reset Control Register
+ * @param 1 Set iRESET_OUT bit; 0 - Clear the bit
+ */
+void p_pcr_iReset_Out(uint8_t set_clr_flag);
+
+#endif // #ifndef _PCR_H
+/* end pcr.h */
+/**   @}
+ */
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/pcr/pcr_api.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/pcr/pcr_api.c
index e7454d84e..3b8e5678c 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/pcr/pcr_api.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/pcr/pcr_api.c
@@ -1,133 +1,133 @@
-/*****************************************************************************
-* � 2015 Microchip Technology Inc. and its subsidiaries.
-* You may use this software and any derivatives exclusively with
-* Microchip products.
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
-* OF THESE TERMS.
-******************************************************************************
-
-Version Control Information (Perforce)
-******************************************************************************
-$Revision: #1 $ 
-$DateTime: 2015/11/24 06:28:28 $ 
-$Author: amohandas $
-Last Change:	Updated for tabs
-******************************************************************************/
-/** @file pcr_api.c
-* \brief Power, Clocks, and Resets API Source file
-* \author jvasanth
-* 
-* This file implements the PCR APIs  
-******************************************************************************/
-
-/** @defgroup PCR
- *  @{
- */
-
-#include "common_lib.h"
-#include "pcr.h"
-
-
-/* ------------------------------------------------------------------------------- */
-/*  Functions to program Sleep Enable, CLK Reqd Status, Reset Enable for a block   */
-/* ------------------------------------------------------------------------------- */
-
-/** Sets or Clears block specific bit in PCR Sleep Enable Register
- * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT 
- * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Sleep Enable Register
- */
-void pcr_sleep_enable(uint32_t pcr_block_id, uint8_t set_clr_flag)
-{
-    uint32_t bit_mask;
-    uint8_t pcr_reg_id;	
- 
-    bit_mask = 1UL<<(pcr_block_id & 0xFFu);
-    pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_SLEEP_ENABLE) & 0xFFu);
-
-    p_pcr_reg_update(pcr_reg_id, bit_mask, set_clr_flag);	
-}
-
-
-/** Get Clock Required Status for the block
- * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT 
- * @return uint8_t - 1 if Clock Required Status set, else 0
- */
-uint8_t pcr_clock_reqd_status_get(uint32_t pcr_block_id)
-{
-    uint32_t bit_mask;
-    uint8_t pcr_reg_id, retVal;	
- 
-    bit_mask = 1UL<<(pcr_block_id & 0xFFu);
-    pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_CLK_REQD_STS) & 0xFFu);
-
-    retVal = 0;
-    if (p_pcr_reg_get(pcr_reg_id, bit_mask))
-    {
-        retVal = 1;
-    }
-    
-    return retVal;
-}
-
-/** Sets or Clears Reset Enable register bit for the block
- * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT 
- * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Reset Enable Register
- */
-void pcr_reset_enable(uint32_t pcr_block_id, uint8_t set_clr_flag)
-{
-    uint32_t bit_mask;
-    uint8_t pcr_reg_id;	
- 
-    bit_mask = 1UL<<(pcr_block_id & 0xFFu);
-    pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_RESET_ENABLE) & 0xFFu);
-
-    p_pcr_reg_update(pcr_reg_id, bit_mask, set_clr_flag);					
-}
-
-
-/* ------------------------------------------------------------------------------- */
-/*                  Functions for entering low power modes                         */
-/* ------------------------------------------------------------------------------- */
-
-/** Instructs all blocks to sleep by setting the Sleep Enable bits */
-void pcr_all_blocks_sleep(void)
-{
-	p_pcr_reg_write(PCR_REG_CHIP_SLEEP_ENABLE, 0xFFFFFFFF);
-	p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE, 0xFFFFFFFF);
-	p_pcr_reg_write(PCR_REG_HOST_SLEEP_ENABLE, 0xFFFFFFFF);
-	p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_2, 0xFFFFFFFF);		
-}
-
-/** Clears the Sleep Enable bits for all blocks */
- void pcr_all_blocks_wake(void)
-{
-	p_pcr_reg_write(PCR_REG_CHIP_SLEEP_ENABLE, 0);
-	p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE, 0);
-	p_pcr_reg_write(PCR_REG_HOST_SLEEP_ENABLE, 0);
-	p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_2, 0);		
-}
-
-/** Programs required sleep mode in System Sleep Control Register
- * @param sleep_mode - see enum SYSTEM_SLEEP_MODES
- */
-void pcr_system_sleep(uint8_t sleep_mode)
-{
-    p_pcr_system_sleep_ctrl_write(sleep_mode);
-}
-
-
-/* end pcr_api.c */
-/**   @}
- */
+/*****************************************************************************
+* � 2015 Microchip Technology Inc. and its subsidiaries.
+* You may use this software and any derivatives exclusively with
+* Microchip products.
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
+* OF THESE TERMS.
+******************************************************************************
+
+Version Control Information (Perforce)
+******************************************************************************
+$Revision: #1 $ 
+$DateTime: 2016/04/08 10:18:28 $ 
+$Author: pramans $
+Last Change:	Updated for tabs
+******************************************************************************/
+/** @file pcr_api.c
+* \brief Power, Clocks, and Resets API Source file
+* \author jvasanth
+* 
+* This file implements the PCR APIs  
+******************************************************************************/
+
+/** @defgroup PCR
+ *  @{
+ */
+
+#include "common_lib.h"
+#include "pcr.h"
+
+
+/* ------------------------------------------------------------------------------- */
+/*  Functions to program Sleep Enable, CLK Reqd Status, Reset Enable for a block   */
+/* ------------------------------------------------------------------------------- */
+
+/** Sets or Clears block specific bit in PCR Sleep Enable Register
+ * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT 
+ * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Sleep Enable Register
+ */
+void pcr_sleep_enable(uint32_t pcr_block_id, uint8_t set_clr_flag)
+{
+    uint32_t bit_mask;
+    uint8_t pcr_reg_id;	
+ 
+    bit_mask = 1UL<<(pcr_block_id & 0xFFu);
+    pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_SLEEP_ENABLE) & 0xFFu);
+
+    p_pcr_reg_update(pcr_reg_id, bit_mask, set_clr_flag);	
+}
+
+
+/** Get Clock Required Status for the block
+ * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT 
+ * @return uint8_t - 1 if Clock Required Status set, else 0
+ */
+uint8_t pcr_clock_reqd_status_get(uint32_t pcr_block_id)
+{
+    uint32_t bit_mask;
+    uint8_t pcr_reg_id, retVal;	
+ 
+    bit_mask = 1UL<<(pcr_block_id & 0xFFu);
+    pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_CLK_REQD_STS) & 0xFFu);
+
+    retVal = 0;
+    if (p_pcr_reg_get(pcr_reg_id, bit_mask))
+    {
+        retVal = 1;
+    }
+    
+    return retVal;
+}
+
+/** Sets or Clears Reset Enable register bit for the block
+ * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT 
+ * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Reset Enable Register
+ */
+void pcr_reset_enable(uint32_t pcr_block_id, uint8_t set_clr_flag)
+{
+    uint32_t bit_mask;
+    uint8_t pcr_reg_id;	
+ 
+    bit_mask = 1UL<<(pcr_block_id & 0xFFu);
+    pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_RESET_ENABLE) & 0xFFu);
+
+    p_pcr_reg_update(pcr_reg_id, bit_mask, set_clr_flag);					
+}
+
+
+/* ------------------------------------------------------------------------------- */
+/*                  Functions for entering low power modes                         */
+/* ------------------------------------------------------------------------------- */
+
+/** Instructs all blocks to sleep by setting the Sleep Enable bits */
+void pcr_all_blocks_sleep(void)
+{
+	p_pcr_reg_write(PCR_REG_CHIP_SLEEP_ENABLE, 0xFFFFFFFF);
+	p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE, 0xFFFFFFFF);
+	p_pcr_reg_write(PCR_REG_HOST_SLEEP_ENABLE, 0xFFFFFFFF);
+	p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_2, 0xFFFFFFFF);		
+}
+
+/** Clears the Sleep Enable bits for all blocks */
+ void pcr_all_blocks_wake(void)
+{
+	p_pcr_reg_write(PCR_REG_CHIP_SLEEP_ENABLE, 0);
+	p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE, 0);
+	p_pcr_reg_write(PCR_REG_HOST_SLEEP_ENABLE, 0);
+	p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_2, 0);		
+}
+
+/** Programs required sleep mode in System Sleep Control Register
+ * @param sleep_mode - see enum SYSTEM_SLEEP_MODES
+ */
+void pcr_system_sleep(uint8_t sleep_mode)
+{
+    p_pcr_system_sleep_ctrl_write(sleep_mode);
+}
+
+
+/* end pcr_api.c */
+/**   @}
+ */
diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/pcr/pcr_perphl.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/pcr/pcr_perphl.c
index af43e5df4..9ce96834e 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/pcr/pcr_perphl.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/pcr/pcr_perphl.c
@@ -1,490 +1,490 @@
-/*****************************************************************************
-* � 2015 Microchip Technology Inc. and its subsidiaries.
-* You may use this software and any derivatives exclusively with
-* Microchip products.
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
-* OF THESE TERMS.
-******************************************************************************
-
-Version Control Information (Perforce)
-******************************************************************************
-$Revision: #1 $ 
-$DateTime: 2015/11/24 06:28:28 $ 
-$Author: amohandas $
-Last Change:	Updated for tabs
-******************************************************************************/
-/** @file pcr_perphl.c
-* \brief Power, Clocks, and Resets Peripheral Source file
-* \author jvasanth
-* 
-* This file implements the PCR Peripheral functions  
-******************************************************************************/
-
-/** @defgroup PCR
- *  @{
- */
-
-#include "common_lib.h"
-#include "pcr.h"
-
-/* ---------------------------------------------------------------------- */
-/* Generic functions to program and read 32-bit values from PCR Registers */
-/* ---------------------------------------------------------------------- */
-/** Writes 32-bit value in the PCR Register
- * @param pcr_reg_id - pcr register id 
- * @param value - 32-bit value
- */
-void p_pcr_reg_write(uint8_t pcr_reg_id, uint32_t value)
-{
-    __IO uint32_t *pPCR_Reg;
-
-    pPCR_Reg = (uint32_t *)(PCR_BASE);		
-
-    pPCR_Reg += pcr_reg_id;
-
-    *pPCR_Reg = value;			
-}
-
-/** Reads 32-bit value from the PCR Register
- * @param pcr_reg_id - pcr register id 
- * @return value - 32-bit value
- */
-uint32_t p_pcr_reg_read(uint8_t pcr_reg_id)
-{
-    __IO uint32_t *pPCR_Reg;
-    uint32_t retVal;
-
-    pPCR_Reg = (uint32_t *)(PCR_BASE);		
-
-    pPCR_Reg += pcr_reg_id;	
-
-    retVal = *pPCR_Reg;
-
-    return retVal;
-}
-
-/* ---------------------------------------------------------------------- */
-/*          Functions to set, clr and get bits in PCR Registers           */
-/* ---------------------------------------------------------------------- */
-
-/** Sets bits in a PCR Register
- * @param pcr_reg_id - pcr register id 
- * @param bit_mask - Bit mask of bits to set 
- */
-void p_pcr_reg_set(uint8_t pcr_reg_id, uint32_t bit_mask)
-{
-    __IO uint32_t *pPCR_Reg;
-
-    pPCR_Reg = (uint32_t *)(PCR_BASE);		
-
-    pPCR_Reg += pcr_reg_id;
-
-    *pPCR_Reg |= bit_mask;			
-}
-
-/** Clears bits in a PCR Register
- * @param pcr_reg_id - pcr register id 
- * @param bit_mask - Bit mask of bits to clear 
- */
-void p_pcr_reg_clr(uint8_t pcr_reg_id, uint32_t bit_mask)
-{
-    __IO uint32_t *pPCR_Reg;
-
-    pPCR_Reg = (uint32_t *)(PCR_BASE);		
-
-    pPCR_Reg += pcr_reg_id;
-
-    *pPCR_Reg &= ~bit_mask;			
-}
-
-/** Read bits in a PCR Register
- * @param pcr_reg_id - pcr register id 
- * @param bit_mask - Bit mask of bits to read 
- * @return value - 32-bit value
- */
-uint32_t p_pcr_reg_get(uint8_t pcr_reg_id, uint32_t bit_mask)
-{
-    __IO uint32_t *pPCR_Reg;
-    uint32_t retVal;
-
-    pPCR_Reg = (uint32_t *)(PCR_BASE);		
-
-    pPCR_Reg += pcr_reg_id;		
-
-    retVal = (*pPCR_Reg) & bit_mask;
-
-    return retVal;
-}
-
-/** Sets or Clears bits in a PCR Register - Helper Function
- * @param pcr_reg_id - pcr register id 
- * @param bit_mask - Bit mask of bits to set or clear
- * @param set_clr_flag - Flag to set (1) or clear (0) bits in the PCR Register
- */
-void p_pcr_reg_update(uint8_t pcr_reg_id, uint32_t bit_mask, uint8_t set_clr_flag)
-{
-    if (set_clr_flag)
-    {
-            p_pcr_reg_set(pcr_reg_id, bit_mask);
-    }
-    else
-    {
-            p_pcr_reg_clr(pcr_reg_id, bit_mask);
-    }        
-}
-
-/* ---------------------------------------------------------------------- */
-/*          Functions to operate on System Sleep Control Register         */
-/* ---------------------------------------------------------------------- */
-
-/**
- * Sets/Clears the Ring oscillator power down bit 
- *         in System Sleep Control Register
- * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit
- */
-void p_pcr_system_sleep_ctrl_ring_osc_power_down(uint8_t set_clr_flag)
-{
-	__IO uint32_t *pPCR_Reg;		
-		
-    pPCR_Reg = (uint32_t *)(PCR_BASE)	+ PCR_REG_SYSTEM_SLEEP_CTRL;
-
-    if (set_clr_flag)
-    {
-            *pPCR_Reg |= PCR_SYS_SLP_CTRL_RING_OSC_PWR_DOWN_BITMASK;			
-    }
-    else
-    {
-        *pPCR_Reg &= ~PCR_SYS_SLP_CTRL_RING_OSC_PWR_DOWN_BITMASK;			
-    }
-}
-
-/** Sets/Clears the Ring oscillator output gate bit 
- *         in System Sleep Control Register
- * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit
- */
-void p_pcr_system_sleep_ctrl_ring_osc_output_gate(uint8_t set_clr_flag)
-{
-	__IO uint32_t *pPCR_Reg;		
-		
-    pPCR_Reg = (uint32_t *)(PCR_BASE)	+ PCR_REG_SYSTEM_SLEEP_CTRL;
-
-    if (set_clr_flag)
-    {
-            *pPCR_Reg |= PCR_SYS_SLP_CTRL_RING_OSC_OUTPUT_GATE_BITMASK;			
-    }
-    else
-    {
-        *pPCR_Reg &= ~PCR_SYS_SLP_CTRL_RING_OSC_OUTPUT_GATE_BITMASK;			
-    }
-}
-
-/** Sets/Clears the Core regulator standby bit 
- *         in System Sleep Control Register
- * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit
- */
-void p_pcr_system_sleep_ctrl_core_regulator_stdby(uint8_t set_clr_flag)
-{
-	__IO uint32_t *pPCR_Reg;		
-		
-    pPCR_Reg = (uint32_t *)(PCR_BASE)	+ PCR_REG_SYSTEM_SLEEP_CTRL;
-
-    if (set_clr_flag)
-    {
-            *pPCR_Reg |= PCR_SYS_SLP_CTRL_CORE_REGLTOR_STDBY_BITMASK;			
-    }
-    else
-    {
-        *pPCR_Reg &= ~PCR_SYS_SLP_CTRL_CORE_REGLTOR_STDBY_BITMASK;			
-    }
-}
-
-/** Writes required sleep mode in System Sleep Control Register
- * @param sleep_value - System Sleep control value - [D2, D1, D0]
- */
-void p_pcr_system_sleep_ctrl_write(uint8_t sleep_value)
-{
-    __IO uint32_t *pPCR_Reg;		
-    
-    pPCR_Reg = (uint32_t *)(PCR_BASE)	+ PCR_REG_SYSTEM_SLEEP_CTRL;	
-
-    *pPCR_Reg = (sleep_value & 0x7);		
-}
-
-/** Reads the System Sleep Control PCR Register
- * @return value - byte 0 of the system sleep control PCR register
- */
-uint8_t p_pcr_system_sleep_ctrl_read(void)
-{
-    __IO uint32_t *pPCR_Reg;
-    uint8_t retVal;
-    
-    pPCR_Reg = (uint32_t *)(PCR_BASE)	+ PCR_REG_SYSTEM_SLEEP_CTRL;		
-
-    retVal = (uint8_t)((*pPCR_Reg) & 0xFF);
-
-    return retVal;
-}
-
-
-
-/* ---------------------------------------------------------------------- */
-/*          Function to program to CLK Divide Value                       */
-/* ---------------------------------------------------------------------- */
-
-/** Writes the clock divide value in the Processor Clock Control Register
- * @param clk_divide_value - clk divide values, valid values in enum PROCESSOR_CLK_DIVIDE_VALUE
- */
-void p_pcr_processor_clk_ctrl_write(uint8_t clk_divide_value)
-{
-    __IO uint32_t *pPCR_Reg;		
-
-    pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PROCESSOR_CLK_CTRL;		
-
-    *pPCR_Reg = (clk_divide_value & 0xFF);	
-	
-}
-
-/* ---------------------------------------------------------------------- */
-/*          Function to program the slow clock divide value           */
-/* ---------------------------------------------------------------------- */
-
-/** Write the slow clock divide value in the Slow Clock Control Register
- * @param slow_clk_divide_value - slow clk divide value
- */
-void p_pcr_slow_clk_ctrl_write(uint8_t slow_clk_divide_value)
-{
-    __IO uint32_t *pPCR_Reg;		
-
-    pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SLOW_CLK_CTRL;		
-
-    *pPCR_Reg = (slow_clk_divide_value & 0x3FF);	
-
-}
-
-/* ---------------------------------------------------------------------- */
-/*          Function to read the Oscillator Lock Status                   */
-/* ---------------------------------------------------------------------- */
-
-/** Reads the Oscillator Lock status bit in the Oscillator ID Register
- * @return 1 if Oscillator Lock Status bit is set, else 0
- */
-uint8_t p_pcr_oscillator_lock_sts_get(void)
-{
-    __IO uint32_t *pPCR_Reg;
-    uint8_t retVal;
-
-    pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_OSCILLATOR_ID;	
-
-    retVal = 0;
-    if (*pPCR_Reg & PCR_OSCILLATOR_LOCK_STATUS_BITMASK)
-    {
-            retVal = 1;
-    }
-    
-    return retVal;
-	
-}
-
-/* ---------------------------------------------------------------------- */
-/*  Functions to read various power status in Chip Sub-System register    */
-/* ---------------------------------------------------------------------- */
-
-/** Reads the VCC Reset Status bit 
- *        in the Chip Subsystem Power Reset Status Register
- * @return 1 if VCC Reset Status bit is set, else 0
- */
-uint8_t p_pcr_chip_subsystem_vcc_reset_sts_get(void)
-{
-    __IO uint32_t *pPCR_Reg;
-    uint8_t retVal;
-
-    pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;	
-
-    retVal = 0;
-    if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_VCC_RESET_STS_BITMASK)
-    {
-            retVal = 1;
-    }
-    
-    return retVal;	
-}
-
-/** Reads the SIO Reset Status bit 
- *        in the Chip Subsystem Power Reset Status Register
- * @return 1 if SIO Reset Status bit is set, else 0
- */
-uint8_t p_pcr_chip_subsystem_sio_reset_sts_get(void)
-{
-    __IO uint32_t *pPCR_Reg;
-    uint8_t retVal;
-
-    pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;	
-
-    retVal = 0;
-    if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_SIO_RESET_STS_BITMASK)
-    {
-            retVal = 1;
-    }
-    
-    return retVal;	
-}
-
-/** Reads the VBAT Reset Status bit 
- *        in the Chip Subsystem Power Reset Status Register
- * @return 1 if VBAT Reset Status bit is set, else 0
- */
-uint8_t p_pcr_chip_subsystem_vbat_reset_sts_get(void)
-{
-    __IO uint32_t *pPCR_Reg;
-    uint8_t retVal;
-
-    pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;	
-
-    retVal = 0;
-    if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_VBAT_RESET_STS_BITMASK)
-    {
-            retVal = 1;
-    }
-    
-    return retVal;	
-}
-
-/** Clears the VBAT Reset Status bit 
- *        in the Chip Subsystem Power Reset Status Register 
- */
-void p_pcr_chip_subsystem_vbat_reset_sts_clr(void)
-{
-    __IO uint32_t *pPCR_Reg;		
-
-    pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;
-
-    // Write to clear
-    *pPCR_Reg = PCR_CHIP_SUBSYSTEM_VBAT_RESET_STS_BITMASK;
-	
-}
-
-/** Reads the VCC1 Reset Status bit 
- *        in the Chip Subsystem Power Reset Status Register
- * @return 1 if VCC1 Reset Status bit is set, else 0
- */
-uint8_t p_pcr_chip_subsystem_vcc1_reset_sts_get(void)
-{
-    __IO uint32_t *pPCR_Reg;
-    uint8_t retVal;
-
-    pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;	
-
-    retVal = 0;
-    if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_VCC1_RESET_STS_BITMASK)
-    {
-            retVal = 1;
-    }
-    
-    return retVal;	
-}
-
-/** Clears the VCC1 Reset Status bit 
- *        in the Chip Subsystem Power Reset Status Register 
- */
-void p_pcr_chip_subsystem_vcc1_reset_sts_clr(void)
-{
-    __IO uint32_t *pPCR_Reg;		
-
-    pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;
-
-    // Write to clear
-    *pPCR_Reg = PCR_CHIP_SUBSYSTEM_VCC1_RESET_STS_BITMASK;
-	
-}
-
-/** Reads the 32K_ACTIVE status bit 
- *        in the Chip Subsystem Power Reset Status Register
- * @return 1 if 32_ACTIVE bit is set, else 0
- */
-uint8_t p_pcr_chip_subsystem_32K_active_sts_get(void)
-{
-    __IO uint32_t *pPCR_Reg;
-    uint8_t retVal;
-
-    pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;	
-
-    retVal = 0;
-    if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_32K_ACTIVE_STS_BITMASK)
-    {
-            retVal = 1;
-    }
-    
-    return retVal;	
-}
-
-/** Reads the PCICLK_ACTIVE status bit 
- *        in the Chip Subsystem Power Reset Status Register
- * @return 1 if CICLK_ACTIVE bit is set, else 0
- */
-uint8_t p_pcr_chip_subsystem_pciclk_active_sts_get(void)
-{
-    __IO uint32_t *pPCR_Reg;
-    uint8_t retVal;
-
-    pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;	
-
-    retVal = 0;
-    if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_PCICLK_ACTIVE_STS_BITMASK)
-    {
-            retVal = 1;
-    }		
-    return retVal;	
-}
-
-/* ---------------------------------------------------------------------- */
-/*           Functions for Power Reset Control Register                   */
-/* ---------------------------------------------------------------------- */
-
-/** Reads the iRESET_OUT bit in the Power Reset Control Register
- * @return 1 if iRESET_OUT bit is set, else 0
- */
-uint8_t p_pcr_iReset_Out_get(void)
-{
-    __IO uint32_t *pPCR_Reg;
-    uint8_t retVal;
-
-    pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_CTRL;	
-
-    retVal = 0;
-    if (*pPCR_Reg & PCR_iRESET_OUT_BITMASK)
-    {
-            retVal = 1;
-    }
-    
-    return retVal;
-	
-}
-
-/** Sets/Clears the iRESET_OUT bit in the Power Reset Control Register
- * @param 1 Set iRESET_OUT bit; 0 - Clear the bit
- */
-void p_pcr_iReset_Out(uint8_t set_clr_flag)
-{
-    __IO uint32_t *pPCR_Reg;		
-
-    pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_CTRL;
-
-    *pPCR_Reg	 = (set_clr_flag & 0x1);		
-}
-
-
-/* end pcr_perphl.c */
-/**   @}
- */
+/*****************************************************************************
+* � 2015 Microchip Technology Inc. and its subsidiaries.
+* You may use this software and any derivatives exclusively with
+* Microchip products.
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
+* OF THESE TERMS.
+******************************************************************************
+
+Version Control Information (Perforce)
+******************************************************************************
+$Revision: #1 $ 
+$DateTime: 2016/04/08 10:18:28 $ 
+$Author: pramans $
+Last Change:	Updated for tabs
+******************************************************************************/
+/** @file pcr_perphl.c
+* \brief Power, Clocks, and Resets Peripheral Source file
+* \author jvasanth
+* 
+* This file implements the PCR Peripheral functions  
+******************************************************************************/
+
+/** @defgroup PCR
+ *  @{
+ */
+
+#include "common_lib.h"
+#include "pcr.h"
+
+/* ---------------------------------------------------------------------- */
+/* Generic functions to program and read 32-bit values from PCR Registers */
+/* ---------------------------------------------------------------------- */
+/** Writes 32-bit value in the PCR Register
+ * @param pcr_reg_id - pcr register id 
+ * @param value - 32-bit value
+ */
+void p_pcr_reg_write(uint8_t pcr_reg_id, uint32_t value)
+{
+    __IO uint32_t *pPCR_Reg;
+
+    pPCR_Reg = (uint32_t *)(PCR_BASE);		
+
+    pPCR_Reg += pcr_reg_id;
+
+    *pPCR_Reg = value;			
+}
+
+/** Reads 32-bit value from the PCR Register
+ * @param pcr_reg_id - pcr register id 
+ * @return value - 32-bit value
+ */
+uint32_t p_pcr_reg_read(uint8_t pcr_reg_id)
+{
+    __IO uint32_t *pPCR_Reg;
+    uint32_t retVal;
+
+    pPCR_Reg = (uint32_t *)(PCR_BASE);		
+
+    pPCR_Reg += pcr_reg_id;	
+
+    retVal = *pPCR_Reg;
+
+    return retVal;
+}
+
+/* ---------------------------------------------------------------------- */
+/*          Functions to set, clr and get bits in PCR Registers           */
+/* ---------------------------------------------------------------------- */
+
+/** Sets bits in a PCR Register
+ * @param pcr_reg_id - pcr register id 
+ * @param bit_mask - Bit mask of bits to set 
+ */
+void p_pcr_reg_set(uint8_t pcr_reg_id, uint32_t bit_mask)
+{
+    __IO uint32_t *pPCR_Reg;
+
+    pPCR_Reg = (uint32_t *)(PCR_BASE);		
+
+    pPCR_Reg += pcr_reg_id;
+
+    *pPCR_Reg |= bit_mask;			
+}
+
+/** Clears bits in a PCR Register
+ * @param pcr_reg_id - pcr register id 
+ * @param bit_mask - Bit mask of bits to clear 
+ */
+void p_pcr_reg_clr(uint8_t pcr_reg_id, uint32_t bit_mask)
+{
+    __IO uint32_t *pPCR_Reg;
+
+    pPCR_Reg = (uint32_t *)(PCR_BASE);		
+
+    pPCR_Reg += pcr_reg_id;
+
+    *pPCR_Reg &= ~bit_mask;			
+}
+
+/** Read bits in a PCR Register
+ * @param pcr_reg_id - pcr register id 
+ * @param bit_mask - Bit mask of bits to read 
+ * @return value - 32-bit value
+ */
+uint32_t p_pcr_reg_get(uint8_t pcr_reg_id, uint32_t bit_mask)
+{
+    __IO uint32_t *pPCR_Reg;
+    uint32_t retVal;
+
+    pPCR_Reg = (uint32_t *)(PCR_BASE);		
+
+    pPCR_Reg += pcr_reg_id;		
+
+    retVal = (*pPCR_Reg) & bit_mask;
+
+    return retVal;
+}
+
+/** Sets or Clears bits in a PCR Register - Helper Function
+ * @param pcr_reg_id - pcr register id 
+ * @param bit_mask - Bit mask of bits to set or clear
+ * @param set_clr_flag - Flag to set (1) or clear (0) bits in the PCR Register
+ */
+void p_pcr_reg_update(uint8_t pcr_reg_id, uint32_t bit_mask, uint8_t set_clr_flag)
+{
+    if (set_clr_flag)
+    {
+            p_pcr_reg_set(pcr_reg_id, bit_mask);
+    }
+    else
+    {
+            p_pcr_reg_clr(pcr_reg_id, bit_mask);
+    }        
+}
+
+/* ---------------------------------------------------------------------- */
+/*          Functions to operate on System Sleep Control Register         */
+/* ---------------------------------------------------------------------- */
+
+/**
+ * Sets/Clears the Ring oscillator power down bit 
+ *         in System Sleep Control Register
+ * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit
+ */
+void p_pcr_system_sleep_ctrl_ring_osc_power_down(uint8_t set_clr_flag)
+{
+	__IO uint32_t *pPCR_Reg;		
+		
+    pPCR_Reg = (uint32_t *)(PCR_BASE)	+ PCR_REG_SYSTEM_SLEEP_CTRL;
+
+    if (set_clr_flag)
+    {
+            *pPCR_Reg |= PCR_SYS_SLP_CTRL_RING_OSC_PWR_DOWN_BITMASK;			
+    }
+    else
+    {
+        *pPCR_Reg &= ~PCR_SYS_SLP_CTRL_RING_OSC_PWR_DOWN_BITMASK;			
+    }
+}
+
+/** Sets/Clears the Ring oscillator output gate bit 
+ *         in System Sleep Control Register
+ * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit
+ */
+void p_pcr_system_sleep_ctrl_ring_osc_output_gate(uint8_t set_clr_flag)
+{
+	__IO uint32_t *pPCR_Reg;		
+		
+    pPCR_Reg = (uint32_t *)(PCR_BASE)	+ PCR_REG_SYSTEM_SLEEP_CTRL;
+
+    if (set_clr_flag)
+    {
+            *pPCR_Reg |= PCR_SYS_SLP_CTRL_RING_OSC_OUTPUT_GATE_BITMASK;			
+    }
+    else
+    {
+        *pPCR_Reg &= ~PCR_SYS_SLP_CTRL_RING_OSC_OUTPUT_GATE_BITMASK;			
+    }
+}
+
+/** Sets/Clears the Core regulator standby bit 
+ *         in System Sleep Control Register
+ * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit
+ */
+void p_pcr_system_sleep_ctrl_core_regulator_stdby(uint8_t set_clr_flag)
+{
+	__IO uint32_t *pPCR_Reg;		
+		
+    pPCR_Reg = (uint32_t *)(PCR_BASE)	+ PCR_REG_SYSTEM_SLEEP_CTRL;
+
+    if (set_clr_flag)
+    {
+            *pPCR_Reg |= PCR_SYS_SLP_CTRL_CORE_REGLTOR_STDBY_BITMASK;			
+    }
+    else
+    {
+        *pPCR_Reg &= ~PCR_SYS_SLP_CTRL_CORE_REGLTOR_STDBY_BITMASK;			
+    }
+}
+
+/** Writes required sleep mode in System Sleep Control Register
+ * @param sleep_value - System Sleep control value - [D2, D1, D0]
+ */
+void p_pcr_system_sleep_ctrl_write(uint8_t sleep_value)
+{
+    __IO uint32_t *pPCR_Reg;		
+    
+    pPCR_Reg = (uint32_t *)(PCR_BASE)	+ PCR_REG_SYSTEM_SLEEP_CTRL;	
+
+    *pPCR_Reg = (sleep_value & 0x7);		
+}
+
+/** Reads the System Sleep Control PCR Register
+ * @return value - byte 0 of the system sleep control PCR register
+ */
+uint8_t p_pcr_system_sleep_ctrl_read(void)
+{
+    __IO uint32_t *pPCR_Reg;
+    uint8_t retVal;
+    
+    pPCR_Reg = (uint32_t *)(PCR_BASE)	+ PCR_REG_SYSTEM_SLEEP_CTRL;		
+
+    retVal = (uint8_t)((*pPCR_Reg) & 0xFF);
+
+    return retVal;
+}
+
+
+
+/* ---------------------------------------------------------------------- */
+/*          Function to program to CLK Divide Value                       */
+/* ---------------------------------------------------------------------- */
+
+/** Writes the clock divide value in the Processor Clock Control Register
+ * @param clk_divide_value - clk divide values, valid values in enum PROCESSOR_CLK_DIVIDE_VALUE
+ */
+void p_pcr_processor_clk_ctrl_write(uint8_t clk_divide_value)
+{
+    __IO uint32_t *pPCR_Reg;		
+
+    pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PROCESSOR_CLK_CTRL;		
+
+    *pPCR_Reg = (clk_divide_value & 0xFF);	
+	
+}
+
+/* ---------------------------------------------------------------------- */
+/*          Function to program the slow clock divide value           */
+/* ---------------------------------------------------------------------- */
+
+/** Write the slow clock divide value in the Slow Clock Control Register
+ * @param slow_clk_divide_value - slow clk divide value
+ */
+void p_pcr_slow_clk_ctrl_write(uint8_t slow_clk_divide_value)
+{
+    __IO uint32_t *pPCR_Reg;		
+
+    pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SLOW_CLK_CTRL;		
+
+    *pPCR_Reg = (slow_clk_divide_value & 0x3FF);	
+
+}
+
+/* ---------------------------------------------------------------------- */
+/*          Function to read the Oscillator Lock Status                   */
+/* ---------------------------------------------------------------------- */
+
+/** Reads the Oscillator Lock status bit in the Oscillator ID Register
+ * @return 1 if Oscillator Lock Status bit is set, else 0
+ */
+uint8_t p_pcr_oscillator_lock_sts_get(void)
+{
+    __IO uint32_t *pPCR_Reg;
+    uint8_t retVal;
+
+    pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_OSCILLATOR_ID;	
+
+    retVal = 0;
+    if (*pPCR_Reg & PCR_OSCILLATOR_LOCK_STATUS_BITMASK)
+    {
+            retVal = 1;
+    }
+    
+    return retVal;
+	
+}
+
+/* ---------------------------------------------------------------------- */
+/*  Functions to read various power status in Chip Sub-System register    */
+/* ---------------------------------------------------------------------- */
+
+/** Reads the VCC Reset Status bit 
+ *        in the Chip Subsystem Power Reset Status Register
+ * @return 1 if VCC Reset Status bit is set, else 0
+ */
+uint8_t p_pcr_chip_subsystem_vcc_reset_sts_get(void)
+{
+    __IO uint32_t *pPCR_Reg;
+    uint8_t retVal;
+
+    pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;	
+
+    retVal = 0;
+    if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_VCC_RESET_STS_BITMASK)
+    {
+            retVal = 1;
+    }
+    
+    return retVal;	
+}
+
+/** Reads the SIO Reset Status bit 
+ *        in the Chip Subsystem Power Reset Status Register
+ * @return 1 if SIO Reset Status bit is set, else 0
+ */
+uint8_t p_pcr_chip_subsystem_sio_reset_sts_get(void)
+{
+    __IO uint32_t *pPCR_Reg;
+    uint8_t retVal;
+
+    pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;	
+
+    retVal = 0;
+    if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_SIO_RESET_STS_BITMASK)
+    {
+            retVal = 1;
+    }
+    
+    return retVal;	
+}
+
+/** Reads the VBAT Reset Status bit 
+ *        in the Chip Subsystem Power Reset Status Register
+ * @return 1 if VBAT Reset Status bit is set, else 0
+ */
+uint8_t p_pcr_chip_subsystem_vbat_reset_sts_get(void)
+{
+    __IO uint32_t *pPCR_Reg;
+    uint8_t retVal;
+
+    pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;	
+
+    retVal = 0;
+    if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_VBAT_RESET_STS_BITMASK)
+    {
+            retVal = 1;
+    }
+    
+    return retVal;	
+}
+
+/** Clears the VBAT Reset Status bit 
+ *        in the Chip Subsystem Power Reset Status Register 
+ */
+void p_pcr_chip_subsystem_vbat_reset_sts_clr(void)
+{
+    __IO uint32_t *pPCR_Reg;		
+
+    pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;
+
+    // Write to clear
+    *pPCR_Reg = PCR_CHIP_SUBSYSTEM_VBAT_RESET_STS_BITMASK;
+	
+}
+
+/** Reads the VCC1 Reset Status bit 
+ *        in the Chip Subsystem Power Reset Status Register
+ * @return 1 if VCC1 Reset Status bit is set, else 0
+ */
+uint8_t p_pcr_chip_subsystem_vcc1_reset_sts_get(void)
+{
+    __IO uint32_t *pPCR_Reg;
+    uint8_t retVal;
+
+    pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;	
+
+    retVal = 0;
+    if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_VCC1_RESET_STS_BITMASK)
+    {
+            retVal = 1;
+    }
+    
+    return retVal;	
+}
+
+/** Clears the VCC1 Reset Status bit 
+ *        in the Chip Subsystem Power Reset Status Register 
+ */
+void p_pcr_chip_subsystem_vcc1_reset_sts_clr(void)
+{
+    __IO uint32_t *pPCR_Reg;		
+
+    pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;
+
+    // Write to clear
+    *pPCR_Reg = PCR_CHIP_SUBSYSTEM_VCC1_RESET_STS_BITMASK;
+	
+}
+
+/** Reads the 32K_ACTIVE status bit 
+ *        in the Chip Subsystem Power Reset Status Register
+ * @return 1 if 32_ACTIVE bit is set, else 0
+ */
+uint8_t p_pcr_chip_subsystem_32K_active_sts_get(void)
+{
+    __IO uint32_t *pPCR_Reg;
+    uint8_t retVal;
+
+    pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;	
+
+    retVal = 0;
+    if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_32K_ACTIVE_STS_BITMASK)
+    {
+            retVal = 1;
+    }
+    
+    return retVal;	
+}
+
+/** Reads the PCICLK_ACTIVE status bit 
+ *        in the Chip Subsystem Power Reset Status Register
+ * @return 1 if CICLK_ACTIVE bit is set, else 0
+ */
+uint8_t p_pcr_chip_subsystem_pciclk_active_sts_get(void)
+{
+    __IO uint32_t *pPCR_Reg;
+    uint8_t retVal;
+
+    pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;	
+
+    retVal = 0;
+    if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_PCICLK_ACTIVE_STS_BITMASK)
+    {
+            retVal = 1;
+    }		
+    return retVal;	
+}
+
+/* ---------------------------------------------------------------------- */
+/*           Functions for Power Reset Control Register                   */
+/* ---------------------------------------------------------------------- */
+
+/** Reads the iRESET_OUT bit in the Power Reset Control Register
+ * @return 1 if iRESET_OUT bit is set, else 0
+ */
+uint8_t p_pcr_iReset_Out_get(void)
+{
+    __IO uint32_t *pPCR_Reg;
+    uint8_t retVal;
+
+    pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_CTRL;	
+
+    retVal = 0;
+    if (*pPCR_Reg & PCR_iRESET_OUT_BITMASK)
+    {
+            retVal = 1;
+    }
+    
+    return retVal;
+	
+}
+
+/** Sets/Clears the iRESET_OUT bit in the Power Reset Control Register
+ * @param 1 Set iRESET_OUT bit; 0 - Clear the bit
+ */
+void p_pcr_iReset_Out(uint8_t set_clr_flag)
+{
+    __IO uint32_t *pPCR_Reg;		
+
+    pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_CTRL;
+
+    *pPCR_Reg	 = (set_clr_flag & 0x1);		
+}
+
+
+/* end pcr_perphl.c */
+/**   @}
+ */
diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/platform.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/platform.h
index 2db4163c7..55768db5b 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/platform.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/platform.h
@@ -35,10 +35,10 @@
 /*******************************************************************************
  *  SMSC version control information (Perforce):
  *
- *  FILE:     $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/platform.h $
+ *  FILE:     $File: //depot_pcs/FWEng/Release/projects/CEC1302_PLIB_CLIB/release5/Source/hw_blks/common/include/platform.h $
  *  REVISION: $Revision: #1 $
- *  DATETIME: $DateTime: 2015/12/23 15:37:58 $
- *  AUTHOR:   $Author: akrishnan $
+ *  DATETIME: $DateTime: 2016/04/08 10:18:28 $
+ *  AUTHOR:   $Author: pramans $
  *
  *  Revision history (latest first):
  *      #xx
@@ -48,6 +48,12 @@
 #ifndef _PLATFORM_H_
 #define _PLATFORM_H_
 #include <stdint.h>
+
+/* Enable any one of the below flag which enables either Aggregated or Disaggregated Interrupts */
+#define DISAGGREGATED_INPT_DEFINED 		1
+//#define AGGREGATED_INPT_DEFINED			1
+
+
 /* Platform Configuration PreProcessor Conditions */
 #define TOOLKEIL    1
 #define TOOLPC      2
@@ -132,6 +138,10 @@ typedef signed long             INT32;
 
 typedef void                    VOID;
 
+typedef volatile unsigned char      VUINT8;
+typedef volatile unsigned short int VUINT16;
+typedef volatile unsigned long int  VUINT32;
+
 /* union types */
 typedef union _BITS_8
 {
@@ -189,7 +199,7 @@ typedef union _BITS_8
 #define FUNC_NEVER_RETURNS
 #define BEGIN_SMALL_DATA_BLOCK(x)
 #define END_SMALL_DATA_BLOCK()
-UINT32 soft_norm(UINT32 val);
+uint32_t soft_norm(uint32_t val);
 #define NORM(x) soft_norm(x)
 //
 #define USE_FUNC_REPLACEMENT    0
@@ -228,7 +238,7 @@ UINT32 soft_norm(UINT32 val);
 #define FUNC_NEVER_RETURNS
 #define BEGIN_SMALL_DATA_BLOCK(x)
 #define END_SMALL_DATA_BLOCK()
-UINT32 soft_norm(UINT32 val);
+uint32_t soft_norm(uint32_t val);
 #define NORM(x) soft_norm(x)
 //
 #define USE_FUNC_REPLACEMENT    0
@@ -335,7 +345,7 @@ UINT32 soft_norm(UINT32 val);
 #else
 /* for ARM MDK */
 #define FUNC_NEVER_RETURNS
-UINT32 soft_norm(UINT32 val);
+uint32_t soft_norm(uint32_t val);
 #define NORM(x) soft_norm(x)
 #endif
 #endif
author	rtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>	2016-04-18 15:52:19 +0000
committer	rtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>	2016-04-18 15:52:19 +0000
commit	ddcf4846caece581db4a9398c8f04909a9bad637 (patch)
tree	4725de7dddb41e0cb32788334f1fd21f61002bc1 /FreeRTOS/Demo
parent	3639e3a4bb1177bb09d790fb3a1260f57eaf6759 (diff)
download	freertos-ddcf4846caece581db4a9398c8f04909a9bad637.tar.gz