diff options
| author | rtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2> | 2020-02-07 01:56:25 +0000 |
|---|---|---|
| committer | rtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2> | 2020-02-07 01:56:25 +0000 |
| commit | bab0e46d7558c3002ccd949f68a66ecece6721b6 (patch) | |
| tree | f2ee4404d3588766a504cea45dd09e5defbbc18a /FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.c | |
| parent | 14ab00a72f72ddf9fc42269d6217cd9ec97a58fd (diff) | |
| download | freertos-bab0e46d7558c3002ccd949f68a66ecece6721b6.tar.gz | |
Add "is inside interrupt" function to MPU ports.
Make clock setup functions weak symbols in ARMv8-M ports.
Update Cortex-M33 ports to use an interrupt mask in place of globally disabling interrupts, as per the other Cortex-M ports.
git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2819 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
Diffstat (limited to 'FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.c')
| -rw-r--r-- | FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.c | 30 |
1 files changed, 20 insertions, 10 deletions
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.c b/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.c index dfec22dee..2aadacc79 100644 --- a/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.c +++ b/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.c @@ -176,24 +176,29 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ }
/*-----------------------------------------------------------*/
-uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
{
__asm volatile
(
- " mrs r0, PRIMASK \n"
- " cpsid i \n"
- " bx lr \n"
- ::: "memory"
+ " mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */
+ " mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " msr basepri, r1 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " dsb \n"
+ " isb \n"
+ " bx lr \n" /* Return. */
+ :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
);
}
/*-----------------------------------------------------------*/
-void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
{
__asm volatile
(
- " msr PRIMASK, r0 \n"
- " bx lr \n"
+ " msr basepri, r0 \n" /* basepri = ulMask. */
+ " dsb \n"
+ " isb \n"
+ " bx lr \n" /* Return. */
::: "memory"
);
}
@@ -266,9 +271,13 @@ void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ #endif /* configENABLE_MPU */
" \n"
" select_next_task: \n"
- " cpsid i \n"
+ " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+ " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " dsb \n"
+ " isb \n"
" bl vTaskSwitchContext \n"
- " cpsie i \n"
+ " mov r0, #0 \n" /* r0 = 0. */
+ " msr basepri, r0 \n" /* Enable interrupts. */
" \n"
" ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r3, [r2] \n" /* Read pxCurrentTCB. */
@@ -352,6 +361,7 @@ void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ "xRNRConst: .word 0xe000ed98 \n"
"xRBARConst: .word 0xe000ed9c \n"
#endif /* configENABLE_MPU */
+ :: "i"( configMAX_SYSCALL_INTERRUPT_PRIORITY )
);
}
/*-----------------------------------------------------------*/
|