diff options
Diffstat (limited to 'FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure')
4 files changed, 516 insertions, 467 deletions
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/.cproject b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/.cproject index cb21b7cb3..397054995 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/.cproject +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/.cproject @@ -1,8 +1,8 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
- <cconfiguration id="com.crt.advproject.config.exe.debug.1530580361">
- <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.crt.advproject.config.exe.debug.1530580361" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+ <cconfiguration id="com.crt.advproject.config.exe.debug.819597480">
+ <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.crt.advproject.config.exe.debug.819597480" moduleId="org.eclipse.cdt.core.settings" name="Debug">
<externalSettings/>
<extensions>
<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
@@ -15,63 +15,61 @@ </extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
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- <folderInfo id="com.crt.advproject.config.exe.debug.1530580361." name="/" resourcePath="">
- <toolChain id="com.crt.advproject.toolchain.exe.debug.288523768" name="NXP MCU Tools" superClass="com.crt.advproject.toolchain.exe.debug">
- <targetPlatform binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.GNU_ELF" id="com.crt.advproject.platform.exe.debug.1654957366" name="ARM-based MCU (Debug)" superClass="com.crt.advproject.platform.exe.debug"/>
- <builder buildPath="${workspace_loc:/FreeRTOSDemo_s}/Debug" id="com.crt.advproject.builder.exe.debug.1699471503" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.crt.advproject.builder.exe.debug"/>
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+ <folderInfo id="com.crt.advproject.config.exe.debug.819597480." name="/" resourcePath="">
+ <toolChain id="com.crt.advproject.toolchain.exe.debug.1828034875" name="NXP MCU Tools" superClass="com.crt.advproject.toolchain.exe.debug">
+ <targetPlatform binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.GNU_ELF" id="com.crt.advproject.platform.exe.debug.2103629328" name="ARM-based MCU (Debug)" superClass="com.crt.advproject.platform.exe.debug"/>
+ <builder buildPath="${workspace_loc:/FreeRTOSDemo_s}/Debug" id="com.crt.advproject.builder.exe.debug.942532416" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.crt.advproject.builder.exe.debug"/>
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+ <tool id="com.crt.advproject.gcc.exe.debug.1532884811" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.debug">
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+ <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="gnu.c.compiler.option.preprocessor.def.symbols.1271197465" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" useByScannerDiscovery="false" valueType="definedSymbols">
<listOptionValue builtIn="false" value="CPU_LPC55S69JBD100_cm33_core0"/>
<listOptionValue builtIn="false" value="ARM_MATH_CM33"/>
+ <listOptionValue builtIn="false" value="SERIAL_PORT_TYPE_UART=1"/>
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<listOptionValue builtIn="false" value="CPU_LPC55S69JBD100_cm33"/>
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@@ -80,10 +78,16 @@ <listOptionValue builtIn="false" value="__USE_CMSIS"/>
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- <inputType id="cdt.managedbuild.tool.gnu.c.linker.input.656036357" superClass="cdt.managedbuild.tool.gnu.c.linker.input">
+ <option id="gnu.c.link.option.userobjs.616633223" name="Other objects" superClass="gnu.c.link.option.userobjs"/>
+ <option id="gnu.c.link.option.shared.1397373631" name="Shared (-shared)" superClass="gnu.c.link.option.shared"/>
+ <option id="gnu.c.link.option.soname.1617499588" name="Shared object name (-Wl,-soname=)" superClass="gnu.c.link.option.soname"/>
+ <option id="gnu.c.link.option.implname.32513739" name="Import Library name (-Wl,--out-implib=)" superClass="gnu.c.link.option.implname"/>
+ <option id="gnu.c.link.option.defname.662377620" name="DEF file name (-Wl,--output-def=)" superClass="gnu.c.link.option.defname"/>
+ <option id="gnu.c.link.option.debugging.prof.1854291453" name="Generate prof information (-p)" superClass="gnu.c.link.option.debugging.prof"/>
+ <option id="gnu.c.link.option.debugging.gprof.342980955" name="Generate gprof information (-pg)" superClass="gnu.c.link.option.debugging.gprof"/>
+ <option id="gnu.c.link.option.debugging.codecov.461148228" name="Generate gcov information (-ftest-coverage -fprofile-arcs)" superClass="gnu.c.link.option.debugging.codecov"/>
+ <option id="com.crt.advproject.link.gcc.lto.1701040480" name="Enable Link-time optimization (-flto)" superClass="com.crt.advproject.link.gcc.lto"/>
+ <option id="com.crt.advproject.link.gcc.lto.optmization.level.1166617700" name="Link-time optimization level" superClass="com.crt.advproject.link.gcc.lto.optmization.level"/>
+ <option id="com.crt.advproject.link.manage.1632689644" name="Manage linker script" superClass="com.crt.advproject.link.manage" useByScannerDiscovery="false" value="false" valueType="boolean"/>
+ <option id="com.crt.advproject.link.script.1624597415" name="Linker script" superClass="com.crt.advproject.link.script" useByScannerDiscovery="false" value="../FreeRTOSDemo_s.ld" valueType="string"/>
+ <option id="com.crt.advproject.link.scriptdir.672613792" name="Script path" superClass="com.crt.advproject.link.scriptdir" useByScannerDiscovery="false" value="" valueType="string"/>
+ <option id="com.crt.advproject.link.crpenable.1893841501" name="Enable automatic placement of Code Read Protection field in image" superClass="com.crt.advproject.link.crpenable"/>
+ <option id="com.crt.advproject.link.flashconfigenable.2080130590" name="Enable automatic placement of Flash Configuration field in image" superClass="com.crt.advproject.link.flashconfigenable" value="true" valueType="boolean"/>
+ <option id="com.crt.advproject.link.ecrp.1207374060" name="Enhanced CRP" superClass="com.crt.advproject.link.ecrp"/>
+ <option id="com.crt.advproject.link.gcc.nanofloat.1447267720" name="Enable printf float " superClass="com.crt.advproject.link.gcc.nanofloat"/>
+ <option id="com.crt.advproject.link.gcc.nanofloat.scanf.792186062" name="Enable scanf float " superClass="com.crt.advproject.link.gcc.nanofloat.scanf"/>
+ <option id="com.crt.advproject.link.toram.1417602046" name="Link application to RAM" superClass="com.crt.advproject.link.toram"/>
+ <option id="com.crt.advproject.link.stackOffset.1363229835" name="Stack offset" superClass="com.crt.advproject.link.stackOffset"/>
+ <option id="com.crt.advproject.link.gcc.multicore.master.1940960886" name="Multicore master" superClass="com.crt.advproject.link.gcc.multicore.master"/>
+ <option id="com.crt.advproject.link.gcc.multicore.empty.754342398" name="No Multicore options for this project" superClass="com.crt.advproject.link.gcc.multicore.empty"/>
+ <option id="com.crt.advproject.link.config.1818581960" name="Obsolete (Config)" superClass="com.crt.advproject.link.config"/>
+ <option id="com.crt.advproject.link.store.1060722498" name="Obsolete (Store)" superClass="com.crt.advproject.link.store"/>
+ <option id="com.crt.advproject.link.securestate.168381216" name="TrustZone Project Type" superClass="com.crt.advproject.link.securestate" value="com.crt.advproject.link.securestate.secure" valueType="enumerated"/>
+ <option id="com.crt.advproject.link.sgstubs.placement.1807005268" name="Secure Gateway Placement" superClass="com.crt.advproject.link.sgstubs.placement"/>
+ <option id="com.crt.advproject.link.sgstubenable.589286154" name="Enable generation of Secure Gateway Import Library" superClass="com.crt.advproject.link.sgstubenable"/>
+ <option id="com.crt.advproject.link.nonsecureobject.249862774" name="Secure Gateway Import Library" superClass="com.crt.advproject.link.nonsecureobject"/>
+ <option id="com.crt.advproject.link.inimplib.1938303527" name="Input Secure Gateway Import Library" superClass="com.crt.advproject.link.inimplib"/>
+ <inputType id="cdt.managedbuild.tool.gnu.c.linker.input.927327018" superClass="cdt.managedbuild.tool.gnu.c.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
</inputType>
</tool>
- <tool id="com.crt.advproject.tool.debug.debug.1264514231" name="MCU Debugger" superClass="com.crt.advproject.tool.debug.debug">
- <option id="com.crt.advproject.linkserver.debug.prevent.debug.443329391" name="Prevent Debugging" superClass="com.crt.advproject.linkserver.debug.prevent.debug" useByScannerDiscovery="false"/>
+ <tool id="com.crt.advproject.tool.debug.debug.1557284651" name="MCU Debugger" superClass="com.crt.advproject.tool.debug.debug">
+ <option id="com.crt.advproject.linkserver.debug.prevent.debug.1709196565" name="Prevent Debugging" superClass="com.crt.advproject.linkserver.debug.prevent.debug"/>
+ <option id="com.crt.advproject.miscellaneous.end_of_heap.2322711" name="Last used address of the heap" superClass="com.crt.advproject.miscellaneous.end_of_heap"/>
+ <option id="com.crt.advproject.miscellaneous.pvHeapStart.138311563" name="First address of the heap" superClass="com.crt.advproject.miscellaneous.pvHeapStart"/>
+ <option id="com.crt.advproject.miscellaneous.pvHeapLimit.896955365" name="Maximum extent of heap" superClass="com.crt.advproject.miscellaneous.pvHeapLimit"/>
+ <option id="com.crt.advproject.debugger.security.nonsecureimageenable.1112624068" name="Enable pre-programming of Non-Secure Image" superClass="com.crt.advproject.debugger.security.nonsecureimageenable"/>
+ <option id="com.crt.advproject.debugger.security.nonsecureimage.216340770" name="Non-Secure Project" superClass="com.crt.advproject.debugger.security.nonsecureimage" value="FreeRTOSDemo_ns" valueType="string"/>
</tool>
</toolChain>
</folderInfo>
@@ -290,29 +311,29 @@ </cconfiguration>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
- <project id="FreeRTOSDemo_s.null.1784645050" name="FreeRTOSDemo_s" projectType="com.crt.advproject.projecttype.exe"/>
+ <project id="FreeRTOSDemo_s.null.1413959314" name="FreeRTOSDemo_s" projectType="com.crt.advproject.projecttype.exe"/>
</storageModule>
<storageModule moduleId="scannerConfiguration">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
- <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.debug.1530580361;com.crt.advproject.config.exe.debug.1530580361.;com.crt.advproject.gas.exe.debug.707764944;com.crt.advproject.assembler.input.1103847778">
+ <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.121728504;com.crt.advproject.config.exe.release.121728504.;com.crt.advproject.gcc.exe.release.439099755;com.crt.advproject.compiler.input.1792763292">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
- <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1938663963;com.crt.advproject.config.exe.release.1938663963.;com.crt.advproject.gcc.exe.release.1345590658;com.crt.advproject.compiler.input.459926266">
+ <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.121728504;com.crt.advproject.config.exe.release.121728504.;com.crt.advproject.gas.exe.release.438112624;com.crt.advproject.assembler.input.830191697">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
- <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1938663963;com.crt.advproject.config.exe.release.1938663963.;com.crt.advproject.gas.exe.release.2101154997;com.crt.advproject.assembler.input.76589641">
+ <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.debug.819597480;com.crt.advproject.config.exe.debug.819597480.;com.crt.advproject.gcc.exe.debug.1532884811;com.crt.advproject.compiler.input.1713049043">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
- <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.debug.1530580361;com.crt.advproject.config.exe.debug.1530580361.;com.crt.advproject.gcc.exe.debug.1335876398;com.crt.advproject.compiler.input.573563641">
+ <scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.debug.819597480;com.crt.advproject.config.exe.debug.819597480.;com.crt.advproject.gas.exe.debug.1771128662;com.crt.advproject.assembler.input.1819825019">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
<storageModule moduleId="com.nxp.mcuxpresso.core.datamodels">
- <sdkName>SDK_2.x_LPC55S69</sdkName>
+ <sdkName>SDK_2.x_LPCXpresso55S69</sdkName>
<sdkExample>FreeRTOSDemo_s</sdkExample>
- <sdkVersion>2.5.0</sdkVersion>
- <sdkComponents>platform.drivers.lpc_iocon.LPC55S69;platform.Include_common.LPC55S69;platform.Include_core_cm33.LPC55S69;platform.devices.LPC55S69_CMSIS.LPC55S69;platform.drivers.clock.LPC55S69;platform.drivers.common.LPC55S69;platform.drivers.power.LPC55S69;platform.drivers.reset.LPC55S69;platform.devices.LPC55S69_startup.LPC55S69;platform.drivers.flexcomm_usart.LPC55S69;platform.drivers.flexcomm.LPC55S69;platform.drivers.lpc_gpio.LPC55S69;platform.utilities.assert.LPC55S69;component.serial_manager.LPC55S69;utility.debug_console.LPC55S69;component.usart_adapter.LPC55S69;component.serial_manager_uart.LPC55S69;component.lists.LPC55S69;FreeRTOSDemo_s;</sdkComponents>
+ <sdkVersion>2.7.1</sdkVersion>
+ <sdkComponents>platform.drivers.power_s.LPC55S69;platform.drivers.common.LPC55S69;platform.drivers.clock.LPC55S69;platform.drivers.power.LPC55S69;platform.devices.LPC55S69_CMSIS.LPC55S69;platform.Include_core_cm33.LPC55S69;platform.Include_common.LPC55S69;platform.Include_dsp.LPC55S69;platform.drivers.reset.LPC55S69;platform.drivers.lpc_iocon.LPC55S69;platform.devices.LPC55S69_startup.LPC55S69;platform.drivers.flexcomm_usart.LPC55S69;platform.drivers.flexcomm.LPC55S69;platform.drivers.lpc_gpio.LPC55S69;platform.utilities.assert.LPC55S69;utility.debug_console.LPC55S69;component.serial_manager.LPC55S69;component.lists.LPC55S69;component.usart_adapter.LPC55S69;component.serial_manager_uart.LPC55S69;platform.utilities.misc_utilities.LPC55S69;FreeRTOSDemo_s;</sdkComponents>
<boardId>lpcxpresso55s69</boardId>
<package>LPC55S69JBD100</package>
<core>cm33</core>
@@ -321,7 +342,7 @@ <storageModule moduleId="com.crt.config">
<projectStorage><?xml version="1.0" encoding="UTF-8"?>
<TargetConfig>
-<Properties property_0="Master" property_3="NXP" property_4="LPC55S69" property_count="5" version="100300"/>
+<Properties property_3="NXP" property_4="LPC55S69" property_count="5" version="100300"/>
<infoList vendor="NXP">
<info chip="LPC55S69" name="LPC55S69">
<chip>
@@ -331,99 +352,8 @@ <memory can_program="true" id="Flash" is_ro="true" size="608" type="Flash"/>
<memory id="RAM" size="304" type="RAM"/>
<memoryInstance derived_from="Flash" driver="LPC55xx_S.cfx" edited="true" id="PROGRAM_FLASH" location="0x10000000" size="0xfe00"/>
-<memoryInstance derived_from="Flash" edited="true" id="veneer_table" location="0x1000fe00" size="0x200"/>
-<memoryInstance derived_from="RAM" edited="true" id="Ram0" location="0x30000000" size="0x7fff"/>
-<peripheralInstance derived_from="FLASH-CFPA0" id="FLASH-CFPA0" location="0x9E000"/>
-<peripheralInstance derived_from="FLASH-CFPA0" id="FLASH-CFPA-SCRATCH" location="0x9DE00"/>
-<peripheralInstance derived_from="FLASH-CFPA0" id="FLASH-CFPA1" location="0x9E200"/>
-<peripheralInstance derived_from="FLASH-CMPA" id="FLASH-CMPA" location="0x9E400"/>
-<peripheralInstance derived_from="FLASH-KEY-STORE" id="FLASH-KEY-STORE" location="0x9E600"/>
-<peripheralInstance derived_from="SYSCON" id="SYSCON" location="0x40000000"/>
-<peripheralInstance derived_from="IOCON" id="IOCON" location="0x40001000"/>
-<peripheralInstance derived_from="GINT0" id="GINT0" location="0x40002000"/>
-<peripheralInstance derived_from="GINT0" id="GINT1" location="0x40003000"/>
-<peripheralInstance derived_from="PINT" id="PINT" location="0x40004000"/>
-<peripheralInstance derived_from="PINT" id="SECPINT" location="0x40005000"/>
-<peripheralInstance derived_from="INPUTMUX" id="INPUTMUX" location="0x40006000"/>
-<peripheralInstance derived_from="CTIMER0" id="CTIMER0" location="0x40008000"/>
-<peripheralInstance derived_from="CTIMER0" id="CTIMER1" location="0x40009000"/>
-<peripheralInstance derived_from="CTIMER0" id="CTIMER2" location="0x40028000"/>
-<peripheralInstance derived_from="CTIMER0" id="CTIMER3" location="0x40029000"/>
-<peripheralInstance derived_from="CTIMER0" id="CTIMER4" location="0x4002A000"/>
-<peripheralInstance derived_from="WWDT" id="WWDT" location="0x4000C000"/>
-<peripheralInstance derived_from="MRT0" id="MRT0" location="0x4000D000"/>
-<peripheralInstance derived_from="UTICK0" id="UTICK0" location="0x4000E000"/>
-<peripheralInstance derived_from="ANACTRL" id="ANACTRL" location="0x40013000"/>
-<peripheralInstance derived_from="PMC" id="PMC" location="0x40020000"/>
-<peripheralInstance derived_from="SYSCTL" id="SYSCTL" location="0x40023000"/>
-<peripheralInstance derived_from="RTC" id="RTC" location="0x4002C000"/>
-<peripheralInstance derived_from="OSTIMER" id="OSTIMER" location="0x4002D000"/>
-<peripheralInstance derived_from="FLASH" id="FLASH" location="0x40034000"/>
-<peripheralInstance derived_from="PRINCE" id="PRINCE" location="0x40035000"/>
-<peripheralInstance derived_from="USBPHY" id="USBPHY" location="0x40038000"/>
-<peripheralInstance derived_from="RNG" id="RNG" location="0x4003A000"/>
-<peripheralInstance derived_from="PUF" id="PUF" location="0x4003B000"/>
-<peripheralInstance derived_from="PLU" id="PLU" location="0x4003D000"/>
-<peripheralInstance derived_from="DMA0" id="DMA0" location="0x40082000"/>
-<peripheralInstance derived_from="DMA0" id="DMA1" location="0x400A7000"/>
-<peripheralInstance derived_from="USB0" id="USB0" location="0x40084000"/>
-<peripheralInstance derived_from="SCT0" id="SCT0" location="0x40085000"/>
-<peripheralInstance derived_from="FLEXCOMM0" id="FLEXCOMM0" location="0x40086000"/>
-<peripheralInstance derived_from="FLEXCOMM0" id="FLEXCOMM1" location="0x40087000"/>
-<peripheralInstance derived_from="FLEXCOMM0" id="FLEXCOMM2" location="0x40088000"/>
-<peripheralInstance derived_from="FLEXCOMM0" id="FLEXCOMM3" location="0x40089000"/>
-<peripheralInstance derived_from="FLEXCOMM0" id="FLEXCOMM4" location="0x4008A000"/>
-<peripheralInstance derived_from="FLEXCOMM0" id="FLEXCOMM5" location="0x40096000"/>
-<peripheralInstance derived_from="FLEXCOMM0" id="FLEXCOMM6" location="0x40097000"/>
-<peripheralInstance derived_from="FLEXCOMM0" id="FLEXCOMM7" location="0x40098000"/>
-<peripheralInstance derived_from="FLEXCOMM0" id="FLEXCOMM8" location="0x4009F000"/>
-<peripheralInstance derived_from="I2C0" id="I2C0" location="0x40086000"/>
-<peripheralInstance derived_from="I2C0" id="I2C1" location="0x40087000"/>
-<peripheralInstance derived_from="I2C0" id="I2C2" location="0x40088000"/>
-<peripheralInstance derived_from="I2C0" id="I2C3" location="0x40089000"/>
-<peripheralInstance derived_from="I2C0" id="I2C4" location="0x4008A000"/>
-<peripheralInstance derived_from="I2C0" id="I2C5" location="0x40096000"/>
-<peripheralInstance derived_from="I2C0" id="I2C6" location="0x40097000"/>
-<peripheralInstance derived_from="I2C0" id="I2C7" location="0x40098000"/>
-<peripheralInstance derived_from="I2S0" id="I2S0" location="0x40086000"/>
-<peripheralInstance derived_from="I2S0" id="I2S1" location="0x40087000"/>
-<peripheralInstance derived_from="I2S0" id="I2S2" location="0x40088000"/>
-<peripheralInstance derived_from="I2S0" id="I2S3" location="0x40089000"/>
-<peripheralInstance derived_from="I2S0" id="I2S4" location="0x4008A000"/>
-<peripheralInstance derived_from="I2S0" id="I2S5" location="0x40096000"/>
-<peripheralInstance derived_from="I2S0" id="I2S6" location="0x40097000"/>
-<peripheralInstance derived_from="I2S0" id="I2S7" location="0x40098000"/>
-<peripheralInstance derived_from="SPI0" id="SPI0" location="0x40086000"/>
-<peripheralInstance derived_from="SPI0" id="SPI1" location="0x40087000"/>
-<peripheralInstance derived_from="SPI0" id="SPI2" location="0x40088000"/>
-<peripheralInstance derived_from="SPI0" id="SPI3" location="0x40089000"/>
-<peripheralInstance derived_from="SPI0" id="SPI4" location="0x4008A000"/>
-<peripheralInstance derived_from="SPI0" id="SPI5" location="0x40096000"/>
-<peripheralInstance derived_from="SPI0" id="SPI6" location="0x40097000"/>
-<peripheralInstance derived_from="SPI0" id="SPI7" location="0x40098000"/>
-<peripheralInstance derived_from="SPI0" id="SPI8" location="0x4009F000"/>
-<peripheralInstance derived_from="USART0" id="USART0" location="0x40086000"/>
-<peripheralInstance derived_from="USART0" id="USART1" location="0x40087000"/>
-<peripheralInstance derived_from="USART0" id="USART2" location="0x40088000"/>
-<peripheralInstance derived_from="USART0" id="USART3" location="0x40089000"/>
-<peripheralInstance derived_from="USART0" id="USART4" location="0x4008A000"/>
-<peripheralInstance derived_from="USART0" id="USART5" location="0x40096000"/>
-<peripheralInstance derived_from="USART0" id="USART6" location="0x40097000"/>
-<peripheralInstance derived_from="USART0" id="USART7" location="0x40098000"/>
-<peripheralInstance derived_from="MAILBOX" id="MAILBOX" location="0x4008B000"/>
-<peripheralInstance derived_from="GPIO" id="GPIO" location="0x4008C000"/>
-<peripheralInstance derived_from="GPIO" id="SECGPIO" location="0x400A8000"/>
-<peripheralInstance derived_from="USBHSD" id="USBHSD" location="0x40094000"/>
-<peripheralInstance derived_from="CRC-ENGINE" id="CRC-ENGINE" location="0x40095000"/>
-<peripheralInstance derived_from="SDIF" id="SDIF" location="0x4009B000"/>
-<peripheralInstance derived_from="DGBMAILBOX" id="DGBMAILBOX" location="0x4009C000"/>
-<peripheralInstance derived_from="ADC0" id="ADC0" location="0x400A0000"/>
-<peripheralInstance derived_from="USBFSH" id="USBFSH" location="0x400A2000"/>
-<peripheralInstance derived_from="USBHSH" id="USBHSH" location="0x400A3000"/>
-<peripheralInstance derived_from="HASHCRYPT" id="HASHCRYPT" location="0x400A4000"/>
-<peripheralInstance derived_from="CASPER" id="CASPER" location="0x400A5000"/>
-<peripheralInstance derived_from="POWERQUAD" id="POWERQUAD" location="0x400A6000"/>
-<peripheralInstance derived_from="AHB-SECURE-CTRL" id="AHB-SECURE-CTRL" location="0x400AC000"/>
+<memoryInstance derived_from="Flash" edited="true" id="SG_veneer_table" location="0x1000fe00" size="0x200"/>
+<memoryInstance derived_from="RAM" edited="true" id="Ram0" location="0x30000000" size="0x8000"/>
</chip>
<processor>
<name gcc_name="cortex-m33">Cortex-M33</name>
@@ -433,18 +363,9 @@ <name gcc_name="cortex-m33-nodsp">Cortex-M33 (No DSP)</name>
<family>Cortex-M</family>
</processor>
-<link href="LPC55S69_cm33_core0_internal_peripheral.xml" show="embed" type="simple"/>
</info>
</infoList>
</TargetConfig></projectStorage>
</storageModule>
- <storageModule moduleId="refreshScope" versionNumber="2">
- <configuration configurationName="Debug">
- <resource resourceType="PROJECT" workspacePath="/FreeRTOSDemo_s"/>
- </configuration>
- <configuration configurationName="Release">
- <resource resourceType="PROJECT" workspacePath="/FreeRTOSDemo_s"/>
- </configuration>
- </storageModule>
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
</cproject>
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/FreeRTOSDemo_s.ld b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/FreeRTOSDemo_s.ld index 91959cca8..899b266ca 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/FreeRTOSDemo_s.ld +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/FreeRTOSDemo_s.ld @@ -9,7 +9,7 @@ MEMORY {
/* Define each memory region. */
PROGRAM_FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0xfe00 /* 63.5K bytes (alias Flash). */
- veneer_table (rx) : ORIGIN = 0x1000fe00, LENGTH = 0x200 /* 0.5K bytes (alias Flash2). */
+ SG_veneer_table (rx): ORIGIN = 0x1000fe00, LENGTH = 0x200 /* 0.5K bytes (alias Flash2). */
Ram0 (rwx) : ORIGIN = 0x30000000, LENGTH = 0x8000 /* 32K bytes (alias RAM). */
}
@@ -19,9 +19,9 @@ __base_Flash = 0x10000000; /* Flash. */ __top_PROGRAM_FLASH = 0x10000000 + 0xfe00; /* 63.5K bytes */
__top_Flash = 0x10000000 + 0xfe00; /* 63.5K bytes */
-__base_veneer_table = 0x1000fe00; /* veneer_table. */
+__base_SG_veneer_table = 0x1000fe00; /* SG_veneer_table. */
__base_Flash2 = 0x1000fe00; /* Flash2. */
-__top_veneer_table = 0x1000fe00 + 0x200; /* 0.5K bytes. */
+__top_SG_veneer_table = 0x1000fe00 + 0x200; /* 0.5K bytes. */
__top_Flash2 = 0x1000fe00 + 0x200; /* 0.5K bytes. */
__base_Ram0 = 0x30000000; /* Ram0. */
@@ -34,17 +34,34 @@ ENTRY(ResetISR) SECTIONS
{
+ /* Place TrustZone Secure Gateway Stubs Section in SG_veneer_table'
+ * (Non-Secure Callable) memory. */
+ .gnu.sgstubs : ALIGN (32)
+ {
+ . = ALIGN(32);
+ _start_sg = .;
+ *(.gnu.sgstubs*)
+ . = ALIGN(32);
+ _end_sg = .;
+ } > SG_veneer_table
+
/* Veneer Table Section (Non-Secure Callable). */
.text_Flash2 : ALIGN(4)
{
FILL(0xff)
- *(.text_Flash2*) /* For compatibility with previous releases. */
- *(.text_veneer_table*) /* For compatibility with previous releases. */
- *(.text.$Flash2*)
- *(.text.$veneer_table*)
- *(.rodata.$Flash2*)
- *(.rodata.$veneer_table*)
- } > veneer_table
+ *(.text_Flash2) /* For compatibility with previous releases. */
+ *(.text_SG_veneer_table) /* For compatibility with previous releases. */
+ *(.text.$Flash2)
+ *(.text.$SG_veneer_table)
+ *(.text_Flash2.*) /* For compatibility with previous releases. */
+ *(.text_SG_veneer_table.*) /* For compatibility with previous releases. */
+ *(.text.$Flash2.*)
+ *(.text.$SG_veneer_table.*)
+ *(.rodata.$Flash2)
+ *(.rodata.$SG_veneer_table)
+ *(.rodata.$Flash2.*)
+ *(.rodata.$SG_veneer_table.*)
+ } > SG_veneer_table
/* Vector Table Section. */
.text : ALIGN(4)
@@ -89,21 +106,11 @@ SECTIONS *(.ARM.extab* .gnu.linkonce.armextab.*)
} > PROGRAM_FLASH
- __exidx_start = .;
.ARM.exidx : ALIGN(4)
{
+ __exidx_start = .;
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
- } > PROGRAM_FLASH
- __exidx_end = .;
-
- /* TrustZone Secure Gateway Stubs Section. */
- .gnu.sgstubs : ALIGN (32)
- {
- . = ALIGN(32);
- _start_sg = .;
- *(.gnu.sgstubs*)
- . = ALIGN(32);
- _end_sg = .;
+ __exidx_end = .;
} > PROGRAM_FLASH
/* Text Section End. */
@@ -112,42 +119,55 @@ SECTIONS /* Uninit Reserved Section. */
.uninit_RESERVED : ALIGN(4)
{
+ _start_uninit_RESERVED = .;
KEEP(*(.bss.$RESERVED*))
. = ALIGN(4);
_end_uninit_RESERVED = .;
- } > Ram0
+ } > Ram0 AT>Ram0
/* Main Data section (Ram0). */
.data : ALIGN(4)
{
FILL(0xff)
_data = .;
+ PROVIDE(__start_data_RAM = .);
+ PROVIDE(__start_data_Ram0 = .);
*(vtable)
*(.ramfunc*)
*(.data*)
. = ALIGN(4);
_edata = .;
+ PROVIDE(__end_data_RAM = .);
+ PROVIDE(__end_data_Ram0 = .);
} > Ram0 AT>PROGRAM_FLASH
/* Main BSS Section. */
.bss : ALIGN(4)
{
_bss = .;
+ PROVIDE(__start_bss_RAM = .);
+ PROVIDE(__start_bss_Ram0 = .);
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .;
+ PROVIDE(__end_bss_RAM = .);
+ PROVIDE(__end_bss_Ram0 = .);
PROVIDE(end = .);
- } > Ram0
+ } > Ram0 AT>Ram0
/* Default Noinit Section. */
.noinit (NOLOAD) : ALIGN(4)
{
_noinit = .;
+ PROVIDE(__start_noinit_RAM = .);
+ PROVIDE(__start_noinit_Ram0 = .);
*(.noinit*)
. = ALIGN(4);
_end_noinit = .;
- } > Ram0
+ PROVIDE(__end_noinit_RAM = .);
+ PROVIDE(__end_noinit_Ram0 = .);
+ } > Ram0 AT>Ram0
/* Reserve space and place heap in memory map. */
_HeapSize = 0x800;
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/tzm_config.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/tzm_config.c index 31ddc0b38..a69c769d6 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/tzm_config.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/tzm_config.c @@ -1,156 +1,261 @@ /*
- * Copyright 2018 NXP
+ * Copyright 2017-2019 NXP
+ * All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: TEE v1.0
+processor: LPC55S69
+package_id: LPC55S69JBD100
+mcu_data: ksdk2_0
+processor_version: 0.2.6
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
#include "fsl_common.h"
#include "tzm_config.h"
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-#define CODE_FLASH_START_NS 0x00010000
-#define CODE_FLASH_SIZE_NS 0x00072000
-#define CODE_FLASH_START_NSC 0x1000FE00
-#define CODE_FLASH_SIZE_NSC 0x200
-#define DATA_RAM_START_NS 0x20008000
-#define DATA_RAM_SIZE_NS 0x0002B000
-#define PERIPH_START_NS 0x40000000
-#define PERIPH_SIZE_NS 0x00100000
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-#if defined(__MCUXPRESSO)
-extern unsigned char _start_sg[];
-#endif
+//********************************************************************
+//*** Definitions ****************************************************
+//********************************************************************
+/* SAU region boundaries */
+#define REGION_0_BASE 0
+#define REGION_0_END 0x0FFFFFFFU
+#define REGION_1_BASE 0x20000000U
+#define REGION_1_END 0xFFFFFFFFU
+#define REGION_2_BASE 0x1000FE00U
+#define REGION_2_END 0x1000FFFFU
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+tee:
+- ahb:
+ - regions:
+ - relative_region: {memory: PROGRAM_FLASH, security: s_priv, start: '0x00000000', size: '0x00010000'}
+ - relative_region: {memory: PROGRAM_FLASH, security: ns_user, start: '0x00010000', size: '0x00090000'}
+ - relative_region: {memory: BootROM, security: ns_user, start: '0x00000000', size: '0x00020000'}
+ - relative_region: {memory: SRAMX, security: ns_user, start: '0x00000000', size: '0x00008000'}
+ - relative_region: {memory: SRAM0, security: s_priv, start: '0x00000000', size: '0x00008000'}
+ - relative_region: {memory: SRAM0, security: ns_user, start: '0x00008000', size: '0x00008000'}
+ - relative_region: {memory: SRAM1, security: ns_user, start: '0x00000000', size: '0x00010000'}
+ - relative_region: {memory: SRAM2, security: ns_user, start: '0x00000000', size: '0x00010000'}
+ - relative_region: {memory: SRAM3, security: ns_user, start: '0x00000000', size: '0x00010000'}
+ - relative_region: {memory: SRAM4, security: ns_user, start: '0x00000000', size: '0x00004000'}
+ - relative_region: {memory: USB_RAM, security: ns_user, start: '0x00000000', size: '0x00004000'}
+ - masters:
+ - ns_user: {id: HASH, id: MCM33C, id: MCM33S, id: PQ, id: SDIO, id: SDMA0, id: SDMA1, id: USBFSD, id: USBFSH}
+ - peripherals:
+ - ns_user: {id: ADC0, id: AHB_SECURE_CTRL, id: ANACTRL, id: CASPER, id: CRC_ENGINE, id: CTIMER0, id: CTIMER1, id: CTIMER2, id: CTIMER3, id: CTIMER4, id: DBGMAILBOX,
+ id: DMA0, id: DMA1, id: FLASH, id: FLEXCOMM1, id: FLEXCOMM2, id: FLEXCOMM3, id: FLEXCOMM4, id: FLEXCOMM5, id: FLEXCOMM6, id: FLEXCOMM7, id: GINT0, id: GINT1,
+ id: GPIO, id: HASHCRYPT, id: INPUTMUX, id: MAILBOX, id: MRT0, id: OSTIMER, id: PINT, id: PLU, id: PMC, id: POWERQUAD, id: PRINCE, id: PUF, id: RNG, id: RTC,
+ id: SCT0, id: SDIF, id: SECGPIO, id: SECPINT, id: SPI8, id: SYSCTL, id: USB0, id: USBFSH, id: USBHSD, id: USBHSH, id: USBPHY, id: UTICK0, id: WWDT}
+ - s_priv: {id: FLEXCOMM0, id: IOCON, id: SYSCON}
+ - interrupts:
+ - masking:
+ - Non-masked: {id: acmp_capt_irq, id: adc_irq, id: casper_irq, id: ctimer0_irq, id: ctimer1_irq, id: ctimer2_irq, id: ctimer3_irq, id: ctimer4_irq, id: flexcomm0_irq,
+ id: flexcomm1_irq, id: flexcomm2_irq, id: flexcomm3_irq, id: flexcomm4_irq, id: flexcomm5_irq, id: flexcomm6_irq, id: flexcomm7_irq, id: global_irq0, id: global_irq1,
+ id: lspi_hs_irq, id: mailbox_irq, id: mrt_irq, id: os_event_irq, id: pin_int4, id: pin_int5, id: pin_int6, id: pin_int7, id: pin_irq0, id: pin_irq1, id: pin_irq2,
+ id: pin_irq3, id: plu_irq, id: pq_irq, id: qddkey_irq, id: rtc_irq, id: sct_irq, id: sdio_irq, id: sdma0_irq, id: sdma1_irq, id: sec_hypervisor_call_irq,
+ id: sec_int0, id: sec_int1, id: sec_vio_irq, id: sha_irq, id: sys_irq, id: usb0_irq, id: usb0_needclk_irq, id: usb1_irq, id: usb1_needclk_irq, id: usb1_utmi_irq,
+ id: utick_irq}
+ - security:
+ - Secure: {id: acmp_capt_irq, id: adc_irq, id: casper_irq, id: ctimer0_irq, id: ctimer1_irq, id: ctimer2_irq, id: ctimer3_irq, id: ctimer4_irq, id: flexcomm0_irq,
+ id: flexcomm1_irq, id: flexcomm2_irq, id: flexcomm3_irq, id: flexcomm4_irq, id: flexcomm5_irq, id: flexcomm6_irq, id: flexcomm7_irq, id: global_irq0, id: global_irq1,
+ id: lspi_hs_irq, id: mailbox_irq, id: mrt_irq, id: os_event_irq, id: pin_int4, id: pin_int5, id: pin_int6, id: pin_int7, id: pin_irq0, id: pin_irq1, id: pin_irq2,
+ id: pin_irq3, id: plu_irq, id: pq_irq, id: qddkey_irq, id: rtc_irq, id: sct_irq, id: sdio_irq, id: sdma0_irq, id: sdma1_irq, id: sec_hypervisor_call_irq,
+ id: sec_int0, id: sec_int1, id: sec_vio_irq, id: sha_irq, id: sys_irq, id: usb0_irq, id: usb0_needclk_irq, id: usb1_irq, id: usb1_needclk_irq, id: usb1_utmi_irq,
+ id: utick_irq}
+ - pins_masks:
+ - pio0:
+ - Non-masked: {id: '0', id: '1', id: '10', id: '11', id: '12', id: '13', id: '14', id: '15', id: '16', id: '17', id: '18', id: '19', id: '2', id: '20', id: '21',
+ id: '22', id: '23', id: '24', id: '25', id: '26', id: '27', id: '28', id: '29', id: '3', id: '30', id: '31', id: '4', id: '5', id: '6', id: '7', id: '8',
+ id: '9'}
+ - pio1:
+ - Non-masked: {id: '0', id: '1', id: '10', id: '11', id: '12', id: '13', id: '14', id: '15', id: '16', id: '17', id: '18', id: '19', id: '2', id: '20', id: '21',
+ id: '22', id: '23', id: '24', id: '25', id: '26', id: '27', id: '28', id: '29', id: '3', id: '30', id: '31', id: '4', id: '5', id: '6', id: '7', id: '8',
+ id: '9'}
+- sau:
+ - enabled: 'true'
+ - generate_code_for_disabled_regions: 'false'
+ - regions:
+ - region: {index: '0', enabled: 'true', security: ns, start: '0x00000000', size: '0x10000000'}
+ - region: {index: '1', enabled: 'true', security: ns, start: '0x20000000', size: '0xE0000000'}
+ - region: {index: '2', enabled: 'true', security: nsc, start: '0x1000FE00', size: '0x00000200'}
+ - region: {index: '3', enabled: 'false', security: ns, start: '0x00000000', size: '0x00000020'}
+ - region: {index: '4', enabled: 'false', security: ns, start: '0x00000000', size: '0x00000020'}
+ - region: {index: '5', enabled: 'false', security: ns, start: '0x00000000', size: '0x00000020'}
+ - region: {index: '6', enabled: 'false', security: ns, start: '0x00000000', size: '0x00000020'}
+ - region: {index: '7', enabled: 'false', security: ns, start: '0x00000000', size: '0x00000020'}
+- global_options:
+ - no: {id: AIRCR_PRIS, id: AIRCR_BFHFNMINS, id: AIRCR_SYSRESETREQS, id: SCR_SLEEPDEEPS, id: SHCSR_SECUREFAULTENA, id: NSACR_CP2, id: NSACR_CP3, id: NSACR_CP4,
+ id: NSACR_CP5, id: NSACR_CP6, id: NSACR_CP7, id: CPPWR_SU0, id: CPPWR_SUS0, id: CPPWR_SU1, id: CPPWR_SUS1, id: CPPWR_SU2, id: CPPWR_SUS2, id: CPPWR_SU3, id: CPPWR_SUS3,
+ id: CPPWR_SU4, id: CPPWR_SUS4, id: CPPWR_SU5, id: CPPWR_SUS5, id: CPPWR_SU6, id: CPPWR_SUS6, id: CPPWR_SU7, id: CPPWR_SUS7, id: CPPWR_SU10, id: CPPWR_SUS10, id: CPPWR_SU11,
+ id: CPPWR_SUS11, id: SEC_GPIO_MASK0_LOCK, id: SEC_GPIO_MASK1_LOCK, id: SEC_CPU1_INT_MASK0_LOCK, id: SEC_CPU1_INT_MASK1_LOCK, id: MASTER_SEC_LEVEL_LOCK, id: CPU0_LOCK_NS_VTOR,
+ id: CPU0_LOCK_NS_MPU, id: CPU0_LOCK_S_VTAIRCR, id: CPU0_LOCK_S_MPU, id: CPU0_LOCK_SAU, id: CPU0_LOCK_REG_LOCK, id: CPU1_LOCK_NS_VTOR, id: CPU1_LOCK_NS_MPU, id: CPU1_LOCK_REG_LOCK,
+ id: AHB_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK, id: AHB_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK, id: AHB_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT, id: AHB_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE,
+ id: AHB_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE, id: AHB_MISC_CTRL_REG_IDAU_ALL_NS}
+ - yes: {id: NSACR_CP0, id: NSACR_CP1, id: NSACR_CP10, id: NSACR_CP11, id: AHB_MISC_CTRL_REG_ENABLE_SECURE_CHECKING, id: AHB_MISC_CTRL_REG_WRITE_LOCK}
+- user_memory_regions:
+ - user_memory_region: {id: Region_1, security: s_priv, name: Secure Code, start: '0x10000000', size: '0x0000FE00'}
+ - user_memory_region: {id: Region_2, security: nsc_priv, name: Veneer Table, start: '0x1000FE00', size: '0x00000200'}
+ - user_memory_region: {id: Region_3, security: s_priv, name: Secure Stack and Data, start: '0x30000000', size: '0x00008000'}
+ - user_memory_region: {id: Region_4, security: ns_user, name: Non-secure Code, description: Privilege check is disabled so reset value (NS-User) can be used,
+ start: '0x00010000', size: '0x00062000'}
+ - user_memory_region: {id: Region_5, security: ns_user, name: Non-secure Stack and Data, description: 'Privilege check is disabled so reset value (NS-User) can
+ be used. ', start: '0x20008000', size: '0x0002B000'}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
/*!
* @brief TrustZone initialization
*
- * SAU Configuration
- * This function configures 3 regions:
- * 0x00010000 - 0x00081FFF - non-secure for code execution
- * 0x1000FE00 - 0x1000FFFF - secure, non-secure callable for veneer table
- * 0x20000000 - 0x20032FFF - non-secure for data
- *
- * AHB secure controller settings
- * After RESET all memories and peripherals are set to user:non-secure access
- * This function configures following memories and peripherals as secure:
- * 0x00000000 - 0x0000FFFF - for secure code execution (this is physical FLASH address)
- * 0x00008000 - 0x20032FFF - for secure data (this is physical RAM address)
- *
- * Secure peripherals: SYSCON, IOCON, FLEXCOMM0
- * NOTE: This example configures necessary peripherals for this example.
- * User should configure all peripherals, which shouldn't be accessible
- * from normal world.
-*/
+ * The function configures SAU and AHB.
+ */
void BOARD_InitTrustZone()
{
- /* Disable SAU */
- SAU->CTRL = 0U;
-
- /* Configure SAU region 0 - Non-secure RAM for CODE execution*/
+ //####################################################################
+ //### SAU configuration ##############################################
+ //####################################################################
+
+ /* Set SAU Control register: Disable SAU and All Secure */
+ SAU->CTRL = 0;
+
/* Set SAU region number */
SAU->RNR = 0;
- /* Region base address */
- SAU->RBAR = (CODE_FLASH_START_NS & SAU_RBAR_BADDR_Msk);
- /* Region end address */
- SAU->RLAR = ((CODE_FLASH_START_NS + CODE_FLASH_SIZE_NS-1) & SAU_RLAR_LADDR_Msk) |
- /* Region memory attribute index */
- ((0U << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) |
- /* Enable region */
- ((1U << SAU_RLAR_ENABLE_Pos) & SAU_RLAR_ENABLE_Msk);
-
- /* Configure SAU region 1 - Non-secure RAM for DATA */
- /* Set SAU region number */
- SAU->RNR = 1;
- /* Region base address */
- SAU->RBAR = (DATA_RAM_START_NS & SAU_RBAR_BADDR_Msk);
+ /* Region base address */
+ SAU->RBAR = REGION_0_BASE & SAU_RBAR_BADDR_Msk;
/* Region end address */
- SAU->RLAR = ((DATA_RAM_START_NS + DATA_RAM_SIZE_NS-1) & SAU_RLAR_LADDR_Msk) |
- /* Region memory attribute index */
- ((0U << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) |
- /* Enable region */
- ((1U << SAU_RLAR_ENABLE_Pos) & SAU_RLAR_ENABLE_Msk);
-
- /* Configure SAU region 2 - Non-secure callable FLASH for CODE veneer table*/
+ SAU->RLAR = ((REGION_0_END & SAU_RLAR_LADDR_Msk) | ((0U << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk)) |
+ ((1U << SAU_RLAR_ENABLE_Pos) & SAU_RLAR_ENABLE_Msk);
+
/* Set SAU region number */
- SAU->RNR = 2;
- /* Region base address */
-#if defined(__MCUXPRESSO)
- SAU->RBAR = ((uint32_t)&_start_sg & SAU_RBAR_BADDR_Msk);
-#else
- SAU->RBAR = (CODE_FLASH_START_NSC & SAU_RBAR_BADDR_Msk);
-#endif
+ SAU->RNR = 0x00000001U;
+ /* Region base address */
+ SAU->RBAR = REGION_1_BASE & SAU_RBAR_BADDR_Msk;
/* Region end address */
-#if defined(__MCUXPRESSO)
- SAU->RLAR = (((uint32_t)&_start_sg + CODE_FLASH_SIZE_NSC-1) & SAU_RLAR_LADDR_Msk) |
- /* Region memory attribute index */
- ((1U << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) |
- /* Enable region */
- ((1U << SAU_RLAR_ENABLE_Pos) & SAU_RLAR_ENABLE_Msk);
-#else
- SAU->RLAR = ((CODE_FLASH_START_NSC + CODE_FLASH_SIZE_NSC-1) & SAU_RLAR_LADDR_Msk) |
- /* Region memory attribute index */
- ((1U << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) |
- /* Enable region */
- ((1U << SAU_RLAR_ENABLE_Pos) & SAU_RLAR_ENABLE_Msk);
-#endif
-
- /* Configure SAU region 3 - Non-secure peripherals address space */
+ SAU->RLAR = ((REGION_1_END & SAU_RLAR_LADDR_Msk) | ((0U << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk)) |
+ ((1U << SAU_RLAR_ENABLE_Pos) & SAU_RLAR_ENABLE_Msk);
+
/* Set SAU region number */
- SAU->RNR = 3;
+ SAU->RNR = 0x00000002U;
/* Region base address */
- SAU->RBAR = (PERIPH_START_NS & SAU_RBAR_BADDR_Msk);
+ SAU->RBAR = REGION_2_BASE & SAU_RBAR_BADDR_Msk;
/* Region end address */
- SAU->RLAR = ((PERIPH_START_NS + PERIPH_SIZE_NS-1) & SAU_RLAR_LADDR_Msk) |
- /* Region memory attribute index */
- ((0U << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) |
- /* Enable region */
- ((1U << SAU_RLAR_ENABLE_Pos) & SAU_RLAR_ENABLE_Msk);
+ SAU->RLAR = ((REGION_2_END & SAU_RLAR_LADDR_Msk) | ((1U << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk)) |
+ ((1U << SAU_RLAR_ENABLE_Pos) & SAU_RLAR_ENABLE_Msk);
/* Force memory writes before continuing */
__DSB();
/* Flush and refill pipeline with updated permissions */
- __ISB();
- /* Enable SAU */
- SAU->CTRL = 1U;
-
- /*Configuration of AHB Secure Controller
- * Possible values for every memory sector or peripheral rule:
- * 0b00 Non-secure and Non-priviledge user access allowed.
- * 0b01 Non-secure and Privilege access allowed.
- * 0b10 Secure and Non-priviledge user access allowed.
- * 0b11 Secure and Priviledge user access allowed. */
-
- /* FLASH memory configuration from 0x00000000 to 0x0000FFFF, sector size is 32kB */
+ __ISB();
+ /* Set SAU Control register: Enable SAU and All Secure (applied only if disabled) */
+ SAU->CTRL = 0x00000001U;
+
+ //####################################################################
+ //### AHB Configurations #############################################
+ //####################################################################
+
+ //--------------------------------------------------------------------
+ //--- AHB Security Level Configurations ------------------------------
+ //--------------------------------------------------------------------
+ /* Configuration of AHB Secure Controller
+ * Possible values for every memory sector or peripheral rule:
+ * 0 Non-secure, user access allowed.
+ * 1 Non-secure, privileged access allowed.
+ * 2 Secure, user access allowed.
+ * 3 Secure, privileged access allowed. */
+
+ //--- Security level configuration of memories -----------------------
AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[0] = 0x00000033U;
- AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[1] = 0x00000000U;
- AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[2] = 0x00000000U;
- /* RAM memory configuration from 0x20000000 to 0x20007FFF, sector size is 4kB */
- /* Memory settings for user non-secure access (0x0U) is mentioned for completness only. It is default RESET value. */
- AHB_SECURE_CTRL->SEC_CTRL_RAM0[0].MEM_RULE[0] = 0x33333333U;
- AHB_SECURE_CTRL->SEC_CTRL_RAM0[0].MEM_RULE[1] = 0x00000000U;
- AHB_SECURE_CTRL->SEC_CTRL_RAM1[0].MEM_RULE[0] = 0x00000000U;
- AHB_SECURE_CTRL->SEC_CTRL_RAM1[0].MEM_RULE[1] = 0x00000000U;
- AHB_SECURE_CTRL->SEC_CTRL_RAM2[0].MEM_RULE[0] = 0x00000000U;
- AHB_SECURE_CTRL->SEC_CTRL_RAM2[0].MEM_RULE[1] = 0x00000000U;
- AHB_SECURE_CTRL->SEC_CTRL_RAM3[0].MEM_RULE[0] = 0x00000000U;
- AHB_SECURE_CTRL->SEC_CTRL_RAM3[0].MEM_RULE[1] = 0x00000000U;
- AHB_SECURE_CTRL->SEC_CTRL_RAM4[0].MEM_RULE[0] = 0x00000000U;
-
- /* Set SYSCON and IOCON as secure */
- AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 = AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE(0x3U) |
- AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE(0x3U);
-
- /* Set FLEXCOMM0 as secure */
- AHB_SECURE_CTRL->SEC_CTRL_AHB0_0_SLAVE_RULE = AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE(0x3U);
-
- /* Enable AHB secure controller check and lock all rule registers */
- AHB_SECURE_CTRL->MISC_CTRL_DP_REG = (AHB_SECURE_CTRL->MISC_CTRL_DP_REG & ~(AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK |
- AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK)) |
- AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK(0x1U) |
- AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(0x1U);
+ AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[1] = 0;
+ AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[2] = 0;
+ AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_ROM_MEM_RULE[0] = 0;
+ AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_ROM_MEM_RULE[1] = 0;
+ AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_ROM_MEM_RULE[2] = 0;
+ AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_ROM_MEM_RULE[3] = 0;
+ AHB_SECURE_CTRL->SEC_CTRL_RAMX[0].MEM_RULE[0] = 0;
+ AHB_SECURE_CTRL->SEC_CTRL_RAM0[0].MEM_RULE[0] = 0x33333333U;
+ AHB_SECURE_CTRL->SEC_CTRL_RAM0[0].MEM_RULE[1] = 0;
+ AHB_SECURE_CTRL->SEC_CTRL_RAM1[0].MEM_RULE[0] = 0;
+ AHB_SECURE_CTRL->SEC_CTRL_RAM1[0].MEM_RULE[1] = 0;
+ AHB_SECURE_CTRL->SEC_CTRL_RAM2[0].MEM_RULE[0] = 0;
+ AHB_SECURE_CTRL->SEC_CTRL_RAM2[0].MEM_RULE[1] = 0;
+ AHB_SECURE_CTRL->SEC_CTRL_RAM3[0].MEM_RULE[0] = 0;
+ AHB_SECURE_CTRL->SEC_CTRL_RAM3[0].MEM_RULE[1] = 0;
+ AHB_SECURE_CTRL->SEC_CTRL_RAM4[0].MEM_RULE[0] = 0;
+ AHB_SECURE_CTRL->SEC_CTRL_USB_HS[0].MEM_RULE[0] = 0;
+
+ //--- Security level configuration of peripherals --------------------
+ AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 = 0x00000033U;
+ AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 = 0;
+ AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 = 0;
+ AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 = 0;
+ AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 = 0;
+ AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 = 0;
+ AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 = 0;
+ AHB_SECURE_CTRL->SEC_CTRL_AHB_PORT8_SLAVE0_RULE = 0x03000000U;
+ AHB_SECURE_CTRL->SEC_CTRL_AHB_PORT8_SLAVE1_RULE = 0;
+ AHB_SECURE_CTRL->SEC_CTRL_AHB_PORT9_SLAVE0_RULE = 0;
+ AHB_SECURE_CTRL->SEC_CTRL_AHB_PORT9_SLAVE1_RULE = 0;
+ AHB_SECURE_CTRL->SEC_CTRL_AHB_PORT10[0].SLAVE0_RULE = 0;
+ AHB_SECURE_CTRL->SEC_CTRL_AHB_PORT10[0].SLAVE1_RULE = 0;
+
+ //--- Security level configuration of masters ------------------------
+ AHB_SECURE_CTRL->MASTER_SEC_LEVEL = 0;
+ AHB_SECURE_CTRL->MASTER_SEC_ANTI_POL_REG = 0x3FFFFFFFU;
+
+ //--------------------------------------------------------------------
+ //--- Pins: Reading GPIO state ---------------------------------------
+ //--------------------------------------------------------------------
+ // Possible values for every pin:
+ // 0b0 Deny
+ // 0b1 Allow
+ //--------------------------------------------------------------------
+ AHB_SECURE_CTRL->SEC_GPIO_MASK0 = 0xFFFFFFFFU;
+ AHB_SECURE_CTRL->SEC_GPIO_MASK1 = 0xFFFFFFFFU;
+
+ //--------------------------------------------------------------------
+ //--- Interrupts: Interrupt handling by Core1 ------------------------
+ //--------------------------------------------------------------------
+ // Possible values for every interrupt:
+ // 0b0 Deny
+ // 0b1 Allow
+ //--------------------------------------------------------------------
+ AHB_SECURE_CTRL->SEC_CPU_INT_MASK0 = 0xFFFFFFFFU;
+ AHB_SECURE_CTRL->SEC_CPU_INT_MASK1 = 0xFFFFFFFFU;
+
+ //--------------------------------------------------------------------
+ //--- Interrupts: Interrupt security configuration -------------------
+ //--------------------------------------------------------------------
+ // Possible values for every interrupt:
+ // 0b0 Secure
+ // 0b1 Non-secure
+ //--------------------------------------------------------------------
+ NVIC->ITNS[0] = 0;
+ NVIC->ITNS[1] = 0;
+
+ //--------------------------------------------------------------------
+ //--- Global Options -------------------------------------------------
+ //--------------------------------------------------------------------
+ SCB->AIRCR = (SCB->AIRCR & 0x000009FF7U) | 0x005FA0000U;
+ SCB->SCR &= 0x0FFFFFFF7U;
+ SCB->SHCSR &= 0x0FFF7FFFFU;
+ SCB->NSACR = 0x00000C03U;
+ SCnSCB->CPPWR = 0;
+ AHB_SECURE_CTRL->SEC_MASK_LOCK = 0x00000AAAU;
+ AHB_SECURE_CTRL->MASTER_SEC_LEVEL = (AHB_SECURE_CTRL->MASTER_SEC_LEVEL & 0x03FFFFFFFU) | 0x080000000U;
+ AHB_SECURE_CTRL->MASTER_SEC_ANTI_POL_REG = (AHB_SECURE_CTRL->MASTER_SEC_ANTI_POL_REG & 0x03FFFFFFFU) | 0x080000000U;
+ AHB_SECURE_CTRL->CPU0_LOCK_REG = 0x800002AAU;
+ AHB_SECURE_CTRL->CPU1_LOCK_REG = 0x8000000AU;
+ AHB_SECURE_CTRL->MISC_CTRL_REG = (AHB_SECURE_CTRL->MISC_CTRL_REG & 0x0FFFF0003U) | 0x00000AAA4U;
+ AHB_SECURE_CTRL->MISC_CTRL_DP_REG = 0x0000AAA5U;
}
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/tzm_config.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/tzm_config.h index e21622654..9b2f90462 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/tzm_config.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/tzm_config.h @@ -1,9 +1,14 @@ /*
- * Copyright 2018 NXP
+ * Copyright 2017-2019 NXP
+ * All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
#ifndef _TZM_CONFIG_H_
#define _TZM_CONFIG_H_
@@ -12,8 +17,6 @@ * Definitions
**********************************************************************************************************************/
-
-
/***********************************************************************************************************************
* API
**********************************************************************************************************************/
|