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* Tag first release candidate for V8.2.0.V8.2.0rc1rtel2014-12-240-0/+0
* Release candidate - this will be tagged as FreeRTOS V8.2.0rc1 and a zip file ...rtel2014-12-246-87/+69
* Rename SAM4E demo directory to include the 'F' in 'M4F' - minor point for the...rtel2014-12-24167-0/+0
* Update version numbers in preparation for V8.2.0 release candidate 1.rtel2014-12-211280-23518/+60880
* Kernel changes:rtel2014-12-2124-323/+1899
* Kernel changes:rtel2014-12-1918-98/+327
* + Update demos that use FreeRTOS+Trace to work with the latest trace recorder...rtel2014-12-1851-884/+912
* + New feature added: Task notifications.rtel2014-12-1565-4393/+5390
* Core kernel code:rtel2014-10-1575-492/+12978
* Demo projects only:rtel2014-10-095-22/+59
* Core kernel files:rtel2014-10-08196-69/+70545
* MSP430 Demo projects only:rtel2014-10-0512-235/+1914
* Demo project only: rtel2014-10-0111-69/+2214
* Demo project only: Cyclone V SoC now running from external RAM.rtel2014-10-012-2/+14
* Added project for Altera Cyclone V SoC, currently running from internal RAM.rtel2014-09-30108-0/+431276
* Core kernel code:rtel2014-09-169-163/+493
* SAM4L tickless implementation: Bug fix and update the demo project to exerci...rtel2014-09-167-159/+715
* Demo project only:rtel2014-09-125-4/+14
* Demo tasks only, with the aim of improving test coverage:rtel2014-09-114-101/+488
* Update version number to 8.1.2 after moving the defaulting of configUSE_PORT_...rtel2014-09-021257-1267/+1321
* Demo code only:rtel2014-09-0211-411/+1409
* Correct potential compiler warning when configUSE_MUTEXES is set to 0.rtel2014-08-304-24/+25
* Update version number to 8.1.1 for patch release that re-enables mutexes to b...rtel2014-08-291264-1288/+12252
* Core kernel code:rtel2014-08-2913-173/+376
* Lower the minimum stack size used by the ATSAMA5 demo.rtel2014-08-261-2/+2
* Minor edits prior to tagging V8.1.0.rtel2014-08-2612-1398/+125
* ***IMMINENT RELEASE NOTICE***rtel2014-08-161293-1297/+1308
* Remove some irrelevant CyaSSL files.rtel2014-08-16128-78413/+1
* Demo application related:rtel2014-08-1637-120/+259
* General maintenance - changing comments and correcting spellings only.rtel2014-08-045-3/+14
* Common demo tasks:rtel2014-08-0421-596/+213
* Cortex-A5 IAR port:rtel2014-08-031-6/+5
* Cortex-A5 IAR port baseline prior to removing all SAMA5 specifics to make it ...rtel2014-08-034-14/+15
* Continue working on the GIC-less Cortex-A5 port for IAR:rtel2014-07-293-19/+26
* Carry on working on SAMA5D3 demo:rtel2014-07-2914-85/+205
* SAMA5D3 demo: Add CDC driver code and use CDC to create a simple command con...rtel2014-07-2350-509/+8851
* Update CyaSSL to latest version.rtel2014-07-18445-25369/+161562
* Re-test Zynq demo now it is using the latest tools.rtel2014-07-145-9/+12
* Add back Zynq demo - this time using SDK V14.2.rtel2014-07-14381-0/+269762
* Remove Zynq demo project ready to recreate the project using the 14.2 version...rtel2014-07-1481-182982/+0
* Add 'full' demo to the SAMA5 Xplained demo - but so far without interrupt nes...rtel2014-07-1211-39/+1270
* Rename ARM_CAx_No_GIC ARM_CA5_No_GIC and add FreeRTOSConfig setting to specif...rtel2014-07-124-0/+4
* SAMA5D3 Xplained demo blinky running.rtel2014-07-1215-368/+112
* Add new port layer for Cortex-A devices without the means to mask interrupt p...rtel2014-07-124-0/+856
* Start of SAMA5D3 XPlained demo.rtel2014-07-09277-0/+67714
* Make the parameters to vPortDefineHeapRegions() const.rtel2014-07-045-6/+44
* Update the MSVC simulator demo to demonstrate heap_5 allocator and pdTICKS_TO...rtel2014-07-035-30/+87
* Simply some of the alignment calculations in heap_4.c to match those used in ...rtel2014-07-033-38/+50
* Check in the portable.h version required to use heap_5.c.rtel2014-07-021-0/+21
* Check in the new memory allocator that allows the heap to span multiple blocks.rtel2014-07-021-0/+519
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