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* Update version number in readiness for V10.3.0 release. Sync SVN with ↵yuhzheng2020-02-078-16/+16
| | | | | | reviewed release candidate. git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2821 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Update version number ready for next release.rtel2019-05-118-8/+8
| | | | git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2662 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Update version number in readiness for V10.2.0 release.rtel2019-02-178-16/+16
| | | | git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2634 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Update version numbers ready for release.rtel2018-09-078-8/+8
| | | | git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2576 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Update copyright date ready for tagging V10.1.0.rtel2018-08-228-8/+8
| | | | git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2564 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Update version numbers in preparation for a new release.rtel2018-08-218-8/+8
| | | | git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2562 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Remove period from the URL that links to the web page that describes the ↵rtel2018-06-151-1/+1
| | | | | | FreeRTOSConfig.h parameters. git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2550 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Update Zynq, MPSoc Cortex-A53 and MPSoc Cortex-R5 demo projects to build ↵rtel2018-05-02293-74784/+116258
| | | | | | with the 18.1 version of the Xilinx SDK - building BUT NOT YET TESTED. git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2538 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Roll up the minor changes checked into svn since V10.0.0 into new V10.0.1 ↵rtel2017-12-188-24/+16
| | | | | | ready for release. git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2524 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Update to MIT licensed FreeRTOS V10.0.0 - see ↵rtel2017-11-298-541/+208
| | | | | | https://www.freertos.org/History.txt git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2519 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Update version number in preparation for maintenance release.rtel2017-01-228-8/+8
| | | | git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2483 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Update UltraScale R5 hardware definition and BSP for 2016.4 SDK tools.rtel2017-01-2111-2971/+10914
| | | | git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2482 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Update BSP source files for UltraScale Cortex-A53 and Cortex-R5 and ↵rtel2017-01-19228-1994/+7984
| | | | | | | | | | Microblaze to the 2016.4 versions. Correct alignment issue in GCC Cortex-R port that was preventing full floating point usage in interrupts (other ports will be updated likewise). Update the UltraScale R5 demo to test the GCC Cortex-A9 port layer modification mentioned on the line above. git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2480 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Prepare for V9.0.0 release:rtel2016-05-208-321/+321
| | | | | | + Change version number from V9.0.0rc2 to V9.0.0. git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2462 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Update some more standard demos for use on 64-bit architectures.rtel2016-05-06259-0/+193834
Update the Xilinx Ultrascale+ Cortex-A53 (64-bit) and Cortex-R5 (32-bit) demos to use version 2016.1 of the SDK. git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2455 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
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