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/*
FreeRTOS V8.2.0rc1 - Copyright (C) 2014 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?". Have you defined configASSERT()? *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
***************************************************************************
* *
* Investing in training allows your team to be as productive as *
* possible as early as possible, lowering your overall development *
* cost, and enabling you to bring a more robust product to market *
* earlier than would otherwise be possible. Richard Barry is both *
* the architect and key author of FreeRTOS, and so also the world's *
* leading authority on what is the world's most popular real time *
* kernel for deeply embedded MCU designs. Obtaining your training *
* from Richard ensures your team will gain directly from his in-depth *
* product knowledge and years of usage experience. Contact Real Time *
* Engineers Ltd to enquire about the FreeRTOS Masterclass, presented *
* by Richard Barry: http://www.FreeRTOS.org/contact
* *
***************************************************************************
***************************************************************************
* *
* You are receiving this top quality software for free. Please play *
* fair and reciprocate by reporting any suspected issues and *
* participating in the community forum: *
* http://www.FreeRTOS.org/support *
* *
* Thank you! *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/*
BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART
*/
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "queue.h"
#include "task.h"
/* Demo application includes. */
#include "serial.h"
/* Microblaze driver includes. */
#include "xuartlite_l.h"
#include "xintc_l.h"
/*-----------------------------------------------------------*/
/* Queues used to hold received characters, and characters waiting to be
transmitted. */
static QueueHandle_t xRxedChars;
static QueueHandle_t xCharsForTx;
/*-----------------------------------------------------------*/
xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
{
unsigned long ulControlReg, ulMask;
/* NOTE: The baud rate used by this driver is determined by the hardware
parameterization of the UART Lite peripheral, and the baud value passed to
this function has no effect. */
/* Create the queues used to hold Rx and Tx characters. */
xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
if( ( xRxedChars ) && ( xCharsForTx ) )
{
/* Disable the interrupt. */
XUartLite_mDisableIntr( XPAR_RS232_UART_BASEADDR );
/* Flush the fifos. */
ulControlReg = XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_STATUS_REG_OFFSET );
XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_CONTROL_REG_OFFSET, ulControlReg | XUL_CR_FIFO_TX_RESET | XUL_CR_FIFO_RX_RESET );
/* Enable the interrupt again. The interrupt controller has not yet been
initialised so there is no chance of receiving an interrupt until the
scheduler has been started. */
XUartLite_mEnableIntr( XPAR_RS232_UART_BASEADDR );
/* Enable the interrupt in the interrupt controller while maintaining
all the other bit settings. */
ulMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) );
ulMask |= XPAR_RS232_UART_INTERRUPT_MASK;
XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( ulMask ) );
XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 2 );
}
return ( xComPortHandle ) 0;
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, TickType_t xBlockTime )
{
/* The port handle is not required as this driver only supports one UART. */
( void ) pxPort;
/* Get the next character from the buffer. Return false if no characters
are available, or arrive before xBlockTime expires. */
if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
{
return pdTRUE;
}
else
{
return pdFALSE;
}
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, TickType_t xBlockTime )
{
portBASE_TYPE xReturn = pdTRUE;
portENTER_CRITICAL();
{
/* If the UART FIFO is full we can block posting the new data on the
Tx queue. */
if( XUartLite_mIsTransmitFull( XPAR_RS232_UART_BASEADDR ) )
{
if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
{
xReturn = pdFAIL;
}
}
/* Otherwise, if there is data already in the queue we should add the
new data to the back of the queue to ensure the sequencing is
maintained. */
else if( uxQueueMessagesWaiting( xCharsForTx ) )
{
if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
{
xReturn = pdFAIL;
}
}
/* If the UART FIFO is not full and there is no data already in the
queue we can write directly to the FIFO without disrupting the
sequence. */
else
{
XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cOutChar );
}
}
portEXIT_CRITICAL();
return xReturn;
}
/*-----------------------------------------------------------*/
void vSerialClose( xComPortHandle xPort )
{
/* Not supported as not required by the demo application. */
( void ) xPort;
}
/*-----------------------------------------------------------*/
void vSerialISR( void *pvBaseAddress )
{
unsigned long ulISRStatus;
portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
char cChar;
/* Determine the cause of the interrupt. */
ulISRStatus = XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_STATUS_REG_OFFSET );
if( ( ulISRStatus & ( XUL_SR_RX_FIFO_FULL | XUL_SR_RX_FIFO_VALID_DATA ) ) != 0 )
{
/* A character is available - place it in the queue of received
characters. This might wake a task that was blocked waiting for
data. */
cChar = ( char )XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_RX_FIFO_OFFSET );
xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken );
}
if( ( ulISRStatus & XUL_SR_TX_FIFO_EMPTY ) != 0 )
{
/* There is space in the FIFO - if there are any characters queue for
transmission they can be send to the UART now. This might unblock a
task that was waiting for space to become available on the Tx queue. */
if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE )
{
XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cChar );
}
}
/* If we woke any tasks we may require a context switch. */
if( xHigherPriorityTaskWoken )
{
portYIELD_FROM_ISR();
}
}
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