blob: 42bdf6e0dcd8a9aa7af51e72212c152c1d6915e2 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
|
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
#include <stddef.h>
#include <metal/privilege.h>
#define METAL_MSTATUS_MIE_OFFSET 3
#define METAL_MSTATUS_MPIE_OFFSET 7
#define METAL_MSTATUS_SIE_OFFSET 1
#define METAL_MSTATUS_SPIE_OFFSET 5
#define METAL_MSTATUS_UIE_OFFSET 0
#define METAL_MSTATUS_UPIE_OFFSET 4
#define METAL_MSTATUS_MPP_OFFSET 11
#define METAL_MSTATUS_MPP_MASK 3
void metal_privilege_drop_to_mode(enum metal_privilege_mode mode,
struct metal_register_file regfile,
metal_privilege_entry_point_t entry_point)
{
uintptr_t mstatus;
asm volatile("csrr %0, mstatus" : "=r" (mstatus));
/* Set xPIE bits based on current xIE bits */
if(mstatus && (1 << METAL_MSTATUS_MIE_OFFSET)) {
mstatus |= (1 << METAL_MSTATUS_MPIE_OFFSET);
} else {
mstatus &= ~(1 << METAL_MSTATUS_MPIE_OFFSET);
}
if(mstatus && (1 << METAL_MSTATUS_SIE_OFFSET)) {
mstatus |= (1 << METAL_MSTATUS_SPIE_OFFSET);
} else {
mstatus &= ~(1 << METAL_MSTATUS_SPIE_OFFSET);
}
if(mstatus && (1 << METAL_MSTATUS_UIE_OFFSET)) {
mstatus |= (1 << METAL_MSTATUS_UPIE_OFFSET);
} else {
mstatus &= ~(1 << METAL_MSTATUS_UPIE_OFFSET);
}
/* Set MPP to the requested privilege mode */
mstatus &= ~(METAL_MSTATUS_MPP_MASK << METAL_MSTATUS_MPP_OFFSET);
mstatus |= (mode << METAL_MSTATUS_MPP_OFFSET);
asm volatile("csrw mstatus, %0" :: "r" (mstatus));
/* Set the entry point in MEPC */
asm volatile("csrw mepc, %0" :: "r" (entry_point));
/* Set the register file */
asm volatile("mv ra, %0" :: "r" (regfile.ra));
asm volatile("mv sp, %0" :: "r" (regfile.sp));
asm volatile("mret");
}
|