diff options
author | mwahab <mwahab@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-11-26 13:50:47 +0000 |
---|---|---|
committer | mwahab <mwahab@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-11-26 13:50:47 +0000 |
commit | 030323259f46bb8f9087bbb6f07641d5e8f30d5a (patch) | |
tree | fa9c4a7d4e61e162278e00d2d185178a7cfc6693 | |
parent | fa3f4818542406961ac10040fb58b12c763f28ac (diff) | |
download | gcc-030323259f46bb8f9087bbb6f07641d5e8f30d5a.tar.gz |
[AArch64] Add sqrdmah, sqrdmsh instructions.
* config/aarch64/aarch64-simd.md
(aarch64_sqmovun<mode>): Fix some white-space.
(aarch64_<sur>qmovun<mode>): Likewise.
(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h<mode>): New.
(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>): New.
(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>): New.
* config/aarch64/iterators.md (UNSPEC_SQRDMLAH): New.
(UNSPEC_SQRDMLSH): New.
(SQRDMLH_AS): New.
(rdma_as): New.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@230959 138bc75d-0d04-0410-961f-82ee72b054a4
-rw-r--r-- | gcc/ChangeLog | 13 | ||||
-rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 94 | ||||
-rw-r--r-- | gcc/config/aarch64/iterators.md | 6 |
3 files changed, 111 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c626a6ce6c4..6c0d4d86427 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2015-11-26 Matthew Wahab <matthew.wahab@arm.com> + + * config/aarch64/aarch64-simd.md + (aarch64_sqmovun<mode>): Fix some white-space. + (aarch64_<sur>qmovun<mode>): Likewise. + (aarch64_sqrdml<SQRDMLH_AS:rdma_as>h<mode>): New. + (aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>): New. + (aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>): New. + * config/aarch64/iterators.md (UNSPEC_SQRDMLAH): New. + (UNSPEC_SQRDMLSH): New. + (SQRDMLH_AS): New. + (rdma_as): New. + 2015-11-26 Richard Biener <rguenther@suse.de> PR tree-optimization/66721 diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 79be6beec49..7910484baf0 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3081,7 +3081,7 @@ "TARGET_SIMD" "sqxtun\\t%<vn2>0<Vmntype>, %<v>1<Vmtype>" [(set_attr "type" "neon_sat_shift_imm_narrow_q")] - ) +) ;; sqmovn and uqmovn @@ -3092,7 +3092,7 @@ "TARGET_SIMD" "<sur>qxtn\\t%<vn2>0<Vmntype>, %<v>1<Vmtype>" [(set_attr "type" "neon_sat_shift_imm_narrow_q")] - ) +) ;; <su>q<absneg> @@ -3180,6 +3180,96 @@ [(set_attr "type" "neon_sat_mul_<Vetype>_scalar<q>")] ) +;; sqrdml[as]h. + +(define_insn "aarch64_sqrdml<SQRDMLH_AS:rdma_as>h<mode>" + [(set (match_operand:VSDQ_HSI 0 "register_operand" "=w") + (unspec:VSDQ_HSI + [(match_operand:VSDQ_HSI 1 "register_operand" "0") + (match_operand:VSDQ_HSI 2 "register_operand" "w") + (match_operand:VSDQ_HSI 3 "register_operand" "w")] + SQRDMLH_AS))] + "TARGET_SIMD_RDMA" + "sqrdml<SQRDMLH_AS:rdma_as>h\\t%<v>0<Vmtype>, %<v>2<Vmtype>, %<v>3<Vmtype>" + [(set_attr "type" "neon_sat_mla_<Vetype>_long")] +) + +;; sqrdml[as]h_lane. + +(define_insn "aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>" + [(set (match_operand:VDQHS 0 "register_operand" "=w") + (unspec:VDQHS + [(match_operand:VDQHS 1 "register_operand" "0") + (match_operand:VDQHS 2 "register_operand" "w") + (vec_select:<VEL> + (match_operand:<VCOND> 3 "register_operand" "w") + (parallel [(match_operand:SI 4 "immediate_operand" "i")]))] + SQRDMLH_AS))] + "TARGET_SIMD_RDMA" + { + operands[4] = GEN_INT (ENDIAN_LANE_N (<VCOND>mode, INTVAL (operands[4]))); + return + "sqrdml<SQRDMLH_AS:rdma_as>h\\t%0.<Vtype>, %2.<Vtype>, %3.<Vetype>[%4]"; + } + [(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")] +) + +(define_insn "aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>" + [(set (match_operand:SD_HSI 0 "register_operand" "=w") + (unspec:SD_HSI + [(match_operand:SD_HSI 1 "register_operand" "0") + (match_operand:SD_HSI 2 "register_operand" "w") + (vec_select:<VEL> + (match_operand:<VCOND> 3 "register_operand" "w") + (parallel [(match_operand:SI 4 "immediate_operand" "i")]))] + SQRDMLH_AS))] + "TARGET_SIMD_RDMA" + { + operands[4] = GEN_INT (ENDIAN_LANE_N (<VCOND>mode, INTVAL (operands[4]))); + return + "sqrdml<SQRDMLH_AS:rdma_as>h\\t%<v>0, %<v>2, %3.<Vetype>[%4]"; + } + [(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")] +) + +;; sqrdml[as]h_laneq. + +(define_insn "aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>" + [(set (match_operand:VDQHS 0 "register_operand" "=w") + (unspec:VDQHS + [(match_operand:VDQHS 1 "register_operand" "0") + (match_operand:VDQHS 2 "register_operand" "w") + (vec_select:<VEL> + (match_operand:<VCONQ> 3 "register_operand" "w") + (parallel [(match_operand:SI 4 "immediate_operand" "i")]))] + SQRDMLH_AS))] + "TARGET_SIMD_RDMA" + { + operands[4] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[4]))); + return + "sqrdml<SQRDMLH_AS:rdma_as>h\\t%0.<Vtype>, %2.<Vtype>, %3.<Vetype>[%4]"; + } + [(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")] +) + +(define_insn "aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>" + [(set (match_operand:SD_HSI 0 "register_operand" "=w") + (unspec:SD_HSI + [(match_operand:SD_HSI 1 "register_operand" "0") + (match_operand:SD_HSI 2 "register_operand" "w") + (vec_select:<VEL> + (match_operand:<VCONQ> 3 "register_operand" "w") + (parallel [(match_operand:SI 4 "immediate_operand" "i")]))] + SQRDMLH_AS))] + "TARGET_SIMD_RDMA" + { + operands[4] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[4]))); + return + "sqrdml<SQRDMLH_AS:rdma_as>h\\t%<v>0, %<v>2, %3.<v>[%4]"; + } + [(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")] +) + ;; vqdml[sa]l (define_insn "aarch64_sqdml<SBINQOPS:as>l<mode>" diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index d6a57f68b80..9343c9cd1c8 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -304,6 +304,8 @@ UNSPEC_PMULL2 ; Used in aarch64-simd.md. UNSPEC_REV_REGLIST ; Used in aarch64-simd.md. UNSPEC_VEC_SHR ; Used in aarch64-simd.md. + UNSPEC_SQRDMLAH ; Used in aarch64-simd.md. + UNSPEC_SQRDMLSH ; Used in aarch64-simd.md. ]) ;; ------------------------------------------------------------------ @@ -975,6 +977,8 @@ UNSPEC_SQSHRN UNSPEC_UQSHRN UNSPEC_SQRSHRN UNSPEC_UQRSHRN]) +(define_int_iterator SQRDMLH_AS [UNSPEC_SQRDMLAH UNSPEC_SQRDMLSH]) + (define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2 UNSPEC_TRN1 UNSPEC_TRN2 UNSPEC_UZP1 UNSPEC_UZP2]) @@ -1149,3 +1153,5 @@ (UNSPEC_SHA1M "m")]) (define_int_attr sha256_op [(UNSPEC_SHA256H "") (UNSPEC_SHA256H2 "2")]) + +(define_int_attr rdma_as [(UNSPEC_SQRDMLAH "a") (UNSPEC_SQRDMLSH "s")]) |