2015-01-23 Bernd Edlinger <bernd.edlinger@hotmail.de>

        PR target/50928
        * config/m32c/m32c.c (encode_pattern_1): Removed gcc_unreachable here.
        (DEBUG_RELOAD): Removed define.
        (m32c_limit_reload_class): Enable traces with if DEBUG0.
        (m32c_function_arg): Added a type cast.
        (m32c_legitimize_reload_address): Push A_REGS reload with PSImode.
        * config/m32c/addsub.md (addsi3_1): Specify the mode of all arguments.
        * config/m32c/bitops.md (andqi3_16): Likewise.
        * config/m32c/mov.md (m32c_immd_dbl_mov): Likewise.
        (push_a01_l): Likewise.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@220048 138bc75d-0d04-0410-961f-82ee72b054a4

5 files changed, 33 insertions, 14 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4931136ed64..e4a4cf0641f 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,16 @@
+2015-01-23  Bernd Edlinger  <bernd.edlinger@hotmail.de>
+
+	PR target/50928
+	* config/m32c/m32c.c (encode_pattern_1): Removed gcc_unreachable here.
+	(DEBUG_RELOAD): Removed define.
+	(m32c_limit_reload_class): Enable traces with if DEBUG0.
+	(m32c_function_arg): Added a type cast.
+	(m32c_legitimize_reload_address): Push A_REGS reload with PSImode.
+	* config/m32c/addsub.md (addsi3_1): Specify the mode of all arguments.
+	* config/m32c/bitops.md (andqi3_16): Likewise.
+	* config/m32c/mov.md (m32c_immd_dbl_mov): Likewise.
+	(push_a01_l): Likewise.
+
 2015-01-23  David Malcolm  <dmalcolm@redhat.com>
 
 	PR jit/64721
diff --git a/gcc/config/m32c/addsub.md b/gcc/config/m32c/addsub.md
index 764664fdab2..74cbd3b7cbd 100644
--- a/gcc/config/m32c/addsub.md
+++ b/gcc/config/m32c/addsub.md
@@ -81,7 +81,7 @@
 (define_insn "addsi3_1"
   [(set (match_operand:SI 0 "mra_operand" "=RsiSd,??Rmm,RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
         (plus:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0,0,0")
-                 (match_operand 2 "mrai_operand" "IU2,IU2,i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
+                 (match_operand:SI 2 "mrai_operand" "IU2,IU2,i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
   "TARGET_A16"
   "*
   
diff --git a/gcc/config/m32c/bitops.md b/gcc/config/m32c/bitops.md
index 7ba4e845d18..e75e6712dde 100644
--- a/gcc/config/m32c/bitops.md
+++ b/gcc/config/m32c/bitops.md
@@ -82,7 +82,7 @@
 (define_insn "andqi3_16"
   [(set (match_operand:QI 0 "mra_operand" "=Sp,Rqi,RhlSd,RhlSd,??Rmm,??Rmm")
 	(and:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
-		(match_operand 2 "mrai_operand" "Imb,Imb,iRhlSd,?Rmm,iRhlSd,?Rmm")))]
+		(match_operand:QI 2 "mrai_operand" "Imb,Imb,iRhlSd,?Rmm,iRhlSd,?Rmm")))]
   "TARGET_A16"
   "@
    bclr\t%B2,%0
@@ -178,7 +178,7 @@
 (define_insn "andqi3_24"
   [(set (match_operand:QI 0 "mra_operand" "=Sd,Rqi,RhlSd,RhlSd,??Rmm,??Rmm")
 	(and:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
-		(match_operand 2 "mrai_operand" "Imb,Imb,iRhlSd,?Rmm,iRhlSd,?Rmm")))]
+		(match_operand:QI 2 "mrai_operand" "Imb,Imb,iRhlSd,?Rmm,iRhlSd,?Rmm")))]
   "TARGET_A24"
   "@
    bclr\t%B2,%0
diff --git a/gcc/config/m32c/m32c.c b/gcc/config/m32c/m32c.c
index ffdeee0d08c..5e295655598 100644
--- a/gcc/config/m32c/m32c.c
+++ b/gcc/config/m32c/m32c.c
@@ -144,6 +144,7 @@ static bool m32c_get_pragma_address (const char *varname, unsigned *addr);
 #define DEBUG1 1
 
 #if DEBUG0
+#include "print-tree.h"
 /* This is needed by some of the commented-out debug statements
    below.  */
 static char const *class_names[LIM_REG_CLASSES] = REG_CLASS_NAMES;
@@ -290,7 +291,6 @@ encode_pattern_1 (rtx x)
       fprintf (stderr, "can't encode pattern %s\n",
 	       GET_RTX_NAME (GET_CODE (x)));
       debug_rtx (x);
-      gcc_unreachable ();
 #endif
       break;
     }
@@ -682,8 +682,6 @@ m32c_regno_ok_for_base_p (int regno)
   return 0;
 }
 
-#define DEBUG_RELOAD 0
-
 /* Implements TARGET_PREFERRED_RELOAD_CLASS.  In general, prefer general
    registers of the appropriate size.  */
 
@@ -695,7 +693,7 @@ m32c_preferred_reload_class (rtx x, reg_class_t rclass)
 {
   reg_class_t newclass = rclass;
 
-#if DEBUG_RELOAD
+#if DEBUG0
   fprintf (stderr, "\npreferred_reload_class for %s is ",
 	   class_names[rclass]);
 #endif
@@ -726,7 +724,7 @@ m32c_preferred_reload_class (rtx x, reg_class_t rclass)
   if (GET_MODE (x) == QImode)
     rclass = reduce_class (rclass, HL_REGS, rclass);
 
-#if DEBUG_RELOAD
+#if DEBUG0
   fprintf (stderr, "%s\n", class_names[rclass]);
   debug_rtx (x);
 
@@ -755,7 +753,7 @@ m32c_preferred_output_reload_class (rtx x, reg_class_t rclass)
 int
 m32c_limit_reload_class (machine_mode mode, int rclass)
 {
-#if DEBUG_RELOAD
+#if DEBUG0
   fprintf (stderr, "limit_reload_class for %s: %s ->",
 	   mode_name[mode], class_names[rclass]);
 #endif
@@ -770,7 +768,7 @@ m32c_limit_reload_class (machine_mode mode, int rclass)
   if (rclass != A_REGS)
     rclass = reduce_class (rclass, DI_REGS, rclass);
 
-#if DEBUG_RELOAD
+#if DEBUG0
   fprintf (stderr, " %s\n", class_names[rclass]);
 #endif
   return rclass;
@@ -1368,7 +1366,7 @@ m32c_function_arg (cumulative_args_t ca_v,
 #if DEBUG0
   fprintf (stderr, "func_arg %d (%s, %d)\n",
 	   ca->parm_num, mode_name[mode], named);
-  debug_tree (type);
+  debug_tree ((tree)type);
 #endif
 
   if (mode == VOIDmode)
@@ -1954,6 +1952,14 @@ m32c_legitimize_reload_address (rtx * x,
       return 1;
     }
 
+  if (TARGET_A24 && GET_MODE (*x) == PSImode)
+    {
+      push_reload (*x, NULL_RTX, x, NULL,
+		   A_REGS, PSImode, VOIDmode, 0, 0, opnum,
+		   (enum reload_type) type);
+      return 1;
+    }
+
   return 0;
 }
 
diff --git a/gcc/config/m32c/mov.md b/gcc/config/m32c/mov.md
index 97a74628352..356963add88 100644
--- a/gcc/config/m32c/mov.md
+++ b/gcc/config/m32c/mov.md
@@ -162,9 +162,9 @@
 ; immediate double data to a memory location.
 (define_peephole2
   [(set (match_operand:HI 0 "memory_operand" "")
-        (match_operand 1 "const_int_operand" ""))
+        (match_operand:HI 1 "const_int_operand" ""))
    (set (match_operand:HI 2 "memory_operand" "")
-        (match_operand 3 "const_int_operand" ""))]
+        (match_operand:HI 3 "const_int_operand" ""))]
    "TARGET_A24 && m32c_immd_dbl_mov (operands, HImode)"
    [(set (match_dup 4) (match_dup 5))]
    ""
@@ -213,7 +213,7 @@
 ; don't match.
 (define_insn "push_a01_l"
   [(set (mem:SI (pre_dec:PSI (reg:PSI SP_REGNO)))
-	(match_operand 0 "a_operand" "Raa"))]
+	(match_operand:SI 0 "a_operand" "Raa"))]
   ""
   "push.l\t%0"
   [(set_attr "flags" "n")]