diff options
| author | uros <uros@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-03-20 06:07:30 +0000 |
|---|---|---|
| committer | uros <uros@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-03-20 06:07:30 +0000 |
| commit | 6805b3109a3b0d6c512742b318ece286691cf31f (patch) | |
| tree | 58246ed0ed5b32420fbc749fa702d585f0674375 | |
| parent | b6c42921b4759b01f88cff6970fc4c065874bb4f (diff) | |
| download | gcc-6805b3109a3b0d6c512742b318ece286691cf31f.tar.gz | |
PR rtl-optimization/60851
* recog.c (constrain_operands): Accept a pseudo register before reload
for LRA enabled targets.
testsuite/ChangeLog:
PR rtl-optimization/60851
* gcc.target/i386/pr60851.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@221529 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/recog.c | 6 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr60851.c | 7 |
4 files changed, 24 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2b9f9d0e24a..30d6a5e74a2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2015-03-20 Uros Bizjak <ubizjak@gmail.com> + + PR rtl-optimization/60851 + * recog.c (constrain_operands): Accept a pseudo register before reload + for LRA enabled targets. + 2015-03-19 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/65240 diff --git a/gcc/recog.c b/gcc/recog.c index 7b5ca8b9f1e..a9d3b1f779b 100644 --- a/gcc/recog.c +++ b/gcc/recog.c @@ -2773,8 +2773,12 @@ constrain_operands (int strict, alternative_mask alternatives) /* Every memory operand can be reloaded to fit. */ && ((strict < 0 && MEM_P (op)) /* Before reload, accept what reload can turn - into mem. */ + into a mem. */ || (strict < 0 && CONSTANT_P (op)) + /* Before reload, accept a pseudo, + since LRA can turn it into a mem. */ + || (strict < 0 && targetm.lra_p () && REG_P (op) + && REGNO (op) >= FIRST_PSEUDO_REGISTER) /* During reload, accept a pseudo */ || (reload_in_progress && REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER))) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 3cf6e024f5b..77649009638 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,4 +1,9 @@ -2015-03-17 Michael Meissner <meissner@linux.vnet.ibm.com> +2015-03-20 Uros Bizjak <ubizjak@gmail.com> + + PR rtl-optimization/60851 + * gcc.target/i386/pr60851.c: New test. + +2015-03-19 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/65240 * gcc/testsuite/g++.dg/pr65240.h: Add tests for PR 65240. diff --git a/gcc/testsuite/gcc.target/i386/pr60851.c b/gcc/testsuite/gcc.target/i386/pr60851.c new file mode 100644 index 00000000000..3b8d35d74c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr60851.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -flive-range-shrinkage -mtune=bdver4 -mdispatch-scheduler" } */ + +long double ld (char c) +{ + return c; +} |