diff options
| author | Richard Earnshaw <rearnsha@arm.com> | 2021-06-11 17:18:12 +0100 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@arm.com> | 2021-08-24 14:25:50 +0100 |
| commit | 931d1c208a697b06aae9a7ba55e7a78981dcbccf (patch) | |
| tree | 160e5da0dcc14629ab04e49c8b119d697fabb168 | |
| parent | e527b92b183de8c887213ccf6b024ddb4e363865 (diff) | |
| download | gcc-931d1c208a697b06aae9a7ba55e7a78981dcbccf.tar.gz | |
arm: Fix general issues with patterns for VLLDM and VLSTM
Both lazy_store_multiple_insn and lazy_load_multiple_insn contain
invalid RTL (eg they contain a post_inc statement outside of a mem).
What's more, the instructions concerned do not modify their input
address register. We probably got away with this because they are
generated so late in the compilation that no subsequent pass needed to
understand them. Nevertheless, this could cause problems someday, so
fixed to use a simple legal unspec.
gcc:
* config/arm/vfp.md (lazy_store_multiple_insn): Rewrite as valid RTL.
(lazy_load_multiple_insn): Likewise.
(cherry picked from commit 4702d3cf044924970a9a00142542da1edacfd76c)
| -rw-r--r-- | gcc/config/arm/vfp.md | 21 |
1 files changed, 11 insertions, 10 deletions
diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index f97af92716b..6cf5a5d8b69 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -1703,12 +1703,15 @@ (set_attr "type" "mov_reg")] ) +;; Both this and the next instruction are treated by GCC in the same +;; way as a blockage pattern. That's perhaps stronger than it needs +;; to be, but we do not want accesses to the VFP register bank to be +;; moved across either instruction. + (define_insn "lazy_store_multiple_insn" - [(set (match_operand:SI 0 "s_register_operand" "+&rk") - (post_dec:SI (match_dup 0))) - (unspec_volatile [(const_int 0) - (mem:SI (post_dec:SI (match_dup 0)))] - VUNSPEC_VLSTM)] + [(unspec_volatile + [(mem:BLK (match_operand:SI 0 "s_register_operand" "rk"))] + VUNSPEC_VLSTM)] "use_cmse && reload_completed" "vlstm%?\\t%0" [(set_attr "predicable" "yes") @@ -1716,11 +1719,9 @@ ) (define_insn "lazy_load_multiple_insn" - [(set (match_operand:SI 0 "s_register_operand" "+&rk") - (post_inc:SI (match_dup 0))) - (unspec_volatile:SI [(const_int 0) - (mem:SI (match_dup 0))] - VUNSPEC_VLLDM)] + [(unspec_volatile + [(mem:BLK (match_operand:SI 0 "s_register_operand" "rk"))] + VUNSPEC_VLLDM)] "use_cmse && reload_completed" "vlldm%?\\t%0" [(set_attr "predicable" "yes") |