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authormeissner <meissner@138bc75d-0d04-0410-961f-82ee72b054a4>2017-01-19 23:31:20 +0000
committermeissner <meissner@138bc75d-0d04-0410-961f-82ee72b054a4>2017-01-19 23:31:20 +0000
commita8022fa7b7a929b924b2c928388bed896b465d27 (patch)
tree3b1acb80c0afb53671517731b0c2a94ceef334f8
parent4833bfef601fdd26f5430ab20bdd2025a3cf4d5c (diff)
downloadgcc-a8022fa7b7a929b924b2c928388bed896b465d27.tar.gz
[gcc]
2017-01-19 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Enable -mpower9-minmax by default for -mcpu=power9. (ISA_3_MASKS_IEEE): Require -mvsx-small-integer to enable IEEE 128-bit floating point. [gcc/testsuite] 2017-01-19 Michael Meissner <meissner@linux.vnet.ibm.com> * gcc.target/powerpc/float128-hw.c: Do not require IEEE 128-bit floating point hardware to run test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@244662 138bc75d-0d04-0410-961f-82ee72b054a4
-rw-r--r--gcc/ChangeLog7
-rw-r--r--gcc/config/rs6000/rs6000-cpus.def5
-rw-r--r--gcc/testsuite/ChangeLog5
-rw-r--r--gcc/testsuite/gcc.target/powerpc/float128-hw.c4
4 files changed, 17 insertions, 4 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d231ff49d5b..a50adfec17d 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2017-01-19 Michael Meissner <meissner@linux.vnet.ibm.com>
+
+ * config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Enable
+ -mpower9-minmax by default for -mcpu=power9.
+ (ISA_3_MASKS_IEEE): Require -mvsx-small-integer to enable IEEE
+ 128-bit floating point.
+
2017-01-20 Alan Modra <amodra@gmail.com>
* config/rs6000/rs6000.md (cmpstrnsi, cmpstrsi): Fail if
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index aaff84bdeff..8ce91473470 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -62,7 +62,6 @@
| OPTION_MASK_VSX_SMALL_INTEGER)
/* Add ISEL back into ISA 3.0, since it is supposed to be a win. Do not add
- P9_MINMAX until the hardware that supports it is available. Do not add
FLOAT128_HW here until we are ready to make -mfloat128 on by default. */
#define ISA_3_0_MASKS_SERVER (ISA_2_7_MASKS_SERVER \
| OPTION_MASK_ISEL \
@@ -70,6 +69,7 @@
| OPTION_MASK_P9_FUSION \
| OPTION_MASK_P9_DFORM_SCALAR \
| OPTION_MASK_P9_DFORM_VECTOR \
+ | OPTION_MASK_P9_MINMAX \
| OPTION_MASK_P9_MISC \
| OPTION_MASK_P9_VECTOR)
@@ -81,7 +81,8 @@
| OPTION_MASK_DIRECT_MOVE \
| OPTION_MASK_UPPER_REGS_DI \
| OPTION_MASK_UPPER_REGS_DF \
- | OPTION_MASK_UPPER_REGS_SF)
+ | OPTION_MASK_UPPER_REGS_SF \
+ | OPTION_MASK_VSX_SMALL_INTEGER)
#define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC)
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 1a3a521187e..0f1de62a926 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2017-01-19 Michael Meissner <meissner@linux.vnet.ibm.com>
+
+ * gcc.target/powerpc/float128-hw.c: Do not require IEEE 128-bit
+ floating point hardware to run test.
+
2017-01-19 Tamar Christina <tamar.christina@arm.com>
* gcc/testsuite/lib/target-supports.exp
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-hw.c b/gcc/testsuite/gcc.target/powerpc/float128-hw.c
index 71a0c24a2f2..65958bcac83 100644
--- a/gcc/testsuite/gcc.target/powerpc/float128-hw.c
+++ b/gcc/testsuite/gcc.target/powerpc/float128-hw.c
@@ -1,7 +1,7 @@
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-/* { dg-require-effective-target powerpc_float128_hw_ok } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-options "-mcpu=power9 -O2" } */
+/* { dg-options "-mcpu=power9 -O2 -mfloat128" } */
__float128 f128_add (__float128 a, __float128 b) { return a+b; }
__float128 f128_sub (__float128 a, __float128 b) { return a-b; }