diff options
| author | uros <uros@138bc75d-0d04-0410-961f-82ee72b054a4> | 2012-03-18 09:14:23 +0000 |
|---|---|---|
| committer | uros <uros@138bc75d-0d04-0410-961f-82ee72b054a4> | 2012-03-18 09:14:23 +0000 |
| commit | abd4f58bb28476345c7f3e3ba2d5ea91a6045f9f (patch) | |
| tree | 2b9e12933dd8cfaee94e3a8a3d8c74111986c58b | |
| parent | 721f9ccceb9d77d023838e1c2a9f42465a4d7d6b (diff) | |
| download | gcc-abd4f58bb28476345c7f3e3ba2d5ea91a6045f9f.tar.gz | |
* config/i386/i386.md: Remove empty predicates and/or constraints.
* config/i386/sync.md: Ditto.
* config/i386/sse.md: Ditto.
* config/i386/mmx.md: Ditto.
* config/i386/pentium.md: Ditto.
* config/i386/athlon.md: Ditto.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@185505 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog | 63 | ||||
| -rw-r--r-- | gcc/config/i386/athlon.md | 8 | ||||
| -rw-r--r-- | gcc/config/i386/i386.md | 2714 | ||||
| -rw-r--r-- | gcc/config/i386/mmx.md | 244 | ||||
| -rw-r--r-- | gcc/config/i386/pentium.md | 14 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 1232 | ||||
| -rw-r--r-- | gcc/config/i386/sync.md | 76 |
7 files changed, 2175 insertions, 2176 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9399c2de63d..c9744de7886 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2012-03-18 Uros Bizjak <ubizjak@gmail.com> + + * config/i386/i386.md: Remove empty predicates and/or constraints. + * config/i386/sync.md: Ditto. + * config/i386/sse.md: Ditto. + * config/i386/mmx.md: Ditto. + * config/i386/pentium.md: Ditto. + * config/i386/athlon.md: Ditto. + 2012-03-16 Richard Guenther <rguenther@suse.de> PR tree-optimization/52603 @@ -38,7 +47,7 @@ (vect_is_simple_use): Treat all constants as vec_constant_def. 2012-03-16 Richard Guenther <rguenther@suse.de> - Kai Tietz <ktietz@redhat.com> + Kai Tietz <ktietz@redhat.com> PR middle-end/48814 * gimplify.c (gimplify_self_mod_expr): Evaluate postfix @@ -131,8 +140,7 @@ 2012-03-15 Jakub Jelinek <jakub@redhat.com> PR target/52568 - * config/i386/i386.c (expand_vec_perm_vperm2f128_vblend): New - function. + * config/i386/i386.c (expand_vec_perm_vperm2f128_vblend): New function. (ix86_expand_vec_perm_const_1): Use it. PR target/52568 @@ -209,8 +217,8 @@ * config.gcc (target_type_format_char): New. Document it. Set it for arm*-*-* . - * configure.ac (gnu_unique_option): Use target_type_format_char in test. - Comment rationale. + * configure.ac (gnu_unique_option): Use target_type_format_char + in test. Comment rationale. * configure: Regenerate . 2012-03-15 Jakub Jelinek <jakub@redhat.com> @@ -363,8 +371,7 @@ * configure.ac (gcc_cv_ld_hidden): Remove *-*-solaris2.8*. (ld_tls_support): Remove Solaris 8 references. (lwp_dir, lwp_spec): Remove support for alternate thread library. - * acinclude.m4 (gcc_cv_initfini_array): Remove *-*-solaris2.* - tests. + * acinclude.m4 (gcc_cv_initfini_array): Remove *-*-solaris2.* tests. * configure: Regenerate. * config.in: Regenerate. @@ -435,8 +442,7 @@ 2012-03-14 Martin Jambor <mjambor@suse.cz> * expr.c (expand_assignment): Use expand_expr with EXPAND_WRITE - when expanding MEM_REFs, MEM_TARGET_REFs and handled_component - bases. + when expanding MEM_REFs, MEM_TARGET_REFs and handled_component bases. (expand_expr_real_1): Do not handle misalignment if modifier is EXPAND_WRITE. @@ -451,9 +457,8 @@ 2012-03-14 Richard Guenther <rguenther@suse.de> PR middle-end/52582 - * gimple-fold.c (canonicalize_constructor_val): Make sure - we have a cgraph node for a FUNCTION_DECL that comes from - a constructor. + * gimple-fold.c (canonicalize_constructor_val): Make sure we have + a cgraph node for a FUNCTION_DECL that comes from a constructor. (gimple_get_virt_method_for_binfo): Likewise. 2012-03-14 Richard Guenther <rguenther@suse.de> @@ -647,9 +652,8 @@ * config/i386/i386.c (ix86_option_override_internal): Properly set ix86_gen_leave and ix86_gen_monitor. Check Pmode == DImode, instead of TARGET_64BIT, to set ix86_gen_add3, ix86_gen_sub3, - ix86_gen_one_cmpl2, ix86_gen_andsp, - ix86_gen_allocate_stack_worker, ix86_gen_adjust_stack_and_probe - and ix86_gen_probe_stack_range. + ix86_gen_one_cmpl2, ix86_gen_andsp, ix86_gen_allocate_stack_worker, + ix86_gen_adjust_stack_and_probe and ix86_gen_probe_stack_range. * config/i386/sse.md (sse3_monitor64): Renamed to ... (sse3_monitor64_<mode>): This. @@ -691,9 +695,8 @@ (alpha*-dec-osf*): Remove. * configure: Regenerate. - * config/alpha/host-osf.c, config/alpha/osf5.h, - config/alpha/osf5.opt, config/alpha/va_list.h, config/alpha/x-osf: - Remove. + * config/alpha/host-osf.c, config/alpha/osf5.h, config/alpha/osf5.opt, + config/alpha/va_list.h, config/alpha/x-osf: Remove. * config/alpha/alpha.h (TARGET_LD_BUGGY_LDGP): Remove. * config/alpha/alpha.c (struct machine_function): Update comment. @@ -784,10 +787,9 @@ 2012-03-12 Richard Guenther <rguenther@suse.de> - * tree-sra.c (create_access_replacement): Only rename the - replacement if we can rewrite it into SSA form. Properly - mark register typed replacements that we cannot rewrite - with TREE_ADDRESSABLE. + * tree-sra.c (create_access_replacement): Only rename the replacement + if we can rewrite it into SSA form. Properly mark register typed + replacements that we cannot rewrite with TREE_ADDRESSABLE. * tree-cfg.c (verify_expr): Fix BIT_FIELD_REF verification for aggregate or BLKmode results. @@ -802,8 +804,7 @@ 2012-02-12 Kirill Yukhin <kirill.yukhin@intel.com> * doc/invoke.texi: Document -mrtm option. - * common/config/i386/i386-common.c (OPTION_MASK_ISA_RTM_SET): - New. + * common/config/i386/i386-common.c (OPTION_MASK_ISA_RTM_SET): New. (OPTION_MASK_ISA_RTM_UNSET): Ditto. (ix86_handle_option): Handle OPT_mrtm. * config.gcc (i[34567]86-*-*): Add rtmintrin.h and @@ -814,8 +815,8 @@ __RTM__ if needed. (ix86_target_string): Define -mrtm option. (PTA_RTM): New. - (ix86_option_override_internal): Extend "corei7-avx" with - RTM option. Handle new option. + (ix86_option_override_internal): Extend "corei7-avx" with RTM option. + Handle new option. (ix86_valid_target_attribute_inner_p): Add OPT_mrtm. (ix86_builtins): Add IX86_BUILTIN_XBEGIN, IX86_BUILTIN_XEND, IX86_BUILTIN_XTEST. @@ -835,15 +836,14 @@ (xtest): Ditto. (xtest_1): Ditto. * config/i386/i386.opt (mrtm): New. - * config/i386/immintrin.h: Include rtmintrin.h and - xtestintrin.h. + * config/i386/immintrin.h: Include rtmintrin.h and xtestintrin.h. * config/i386/rtmintrin.h: New header. * config/i386/xtestintrin.h: Ditto. 2012-03-12 Tristan Gingold <gingold@adacore.com> - * ginclude/stddef.h: Adjust previous patch. Use __VMS__ instead - of VMS. + * ginclude/stddef.h: Adjust previous patch. + Use __VMS__ instead of VMS. 2012-03-12 Uros Bizjak <ubizjak@gmail.com> @@ -857,8 +857,7 @@ (C Dialect Options): Move -no-integrated-cpp documentation from here... (Preprocessor Options): ...to here. Rewrite the description - so it makes more sense, and remove discussion of merging - front ends. + so it makes more sense, and remove discussion of merging front ends. 2012-03-11 H.J. Lu <hongjiu.lu@intel.com> diff --git a/gcc/config/i386/athlon.md b/gcc/config/i386/athlon.md index 2896a154d1e..401cb0daf76 100644 --- a/gcc/config/i386/athlon.md +++ b/gcc/config/i386/athlon.md @@ -40,7 +40,7 @@ (cond [(eq_attr "type" "call,imul,idiv,other,multi,fcmov,fpspc,str,pop,leave") (const_string "vector") (and (eq_attr "type" "push") - (match_operand 1 "memory_operand" "")) + (match_operand 1 "memory_operand")) (const_string "vector") (and (eq_attr "type" "fmov") (and (eq_attr "memory" "load,store") @@ -574,17 +574,17 @@ (define_insn_reservation "athlon_movlpd_load" 0 (and (eq_attr "cpu" "athlon") (and (eq_attr "type" "ssemov") - (match_operand:DF 1 "memory_operand" ""))) + (match_operand:DF 1 "memory_operand"))) "athlon-direct,athlon-fpload,athlon-fany") (define_insn_reservation "athlon_movlpd_load_k8" 2 (and (eq_attr "cpu" "k8") (and (eq_attr "type" "ssemov") - (match_operand:DF 1 "memory_operand" ""))) + (match_operand:DF 1 "memory_operand"))) "athlon-direct,athlon-fploadk8,athlon-fstore") (define_insn_reservation "athlon_movsd_load_generic64" 2 (and (eq_attr "cpu" "generic64") (and (eq_attr "type" "ssemov") - (match_operand:DF 1 "memory_operand" ""))) + (match_operand:DF 1 "memory_operand"))) "athlon-double,athlon-fploadk8,(athlon-fstore+athlon-fmul)") (define_insn_reservation "athlon_movaps_load_k8" 2 (and (eq_attr "cpu" "k8,generic64") diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index eae26aedef9..d23c67b38bc 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -363,11 +363,11 @@ (eq_attr "type" "imov,test") (symbol_ref "ix86_attr_length_immediate_default (insn, false)") (eq_attr "type" "call") - (if_then_else (match_operand 0 "constant_call_address_operand" "") + (if_then_else (match_operand 0 "constant_call_address_operand") (const_int 4) (const_int 0)) (eq_attr "type" "callv") - (if_then_else (match_operand 1 "constant_call_address_operand" "") + (if_then_else (match_operand 1 "constant_call_address_operand") (const_int 4) (const_int 0)) ;; We don't know the size before shorten_branches. Expect @@ -383,10 +383,10 @@ (cond [(eq_attr "type" "str,other,multi,fxch") (const_int 0) (and (eq_attr "type" "call") - (match_operand 0 "constant_call_address_operand" "")) + (match_operand 0 "constant_call_address_operand")) (const_int 0) (and (eq_attr "type" "callv") - (match_operand 1 "constant_call_address_operand" "")) + (match_operand 1 "constant_call_address_operand")) (const_int 0) ] (symbol_ref "ix86_attr_length_address_default (insn)"))) @@ -433,7 +433,7 @@ (match_test "x86_extended_reg_mentioned_p (insn)") (const_int 1) (and (eq_attr "type" "imovx") - (match_operand:QI 1 "ext_QIreg_operand" "")) + (match_operand:QI 1 "ext_QIreg_operand")) (const_int 1) ] (const_int 0))) @@ -481,32 +481,32 @@ (const_int 0) (and (eq_attr "type" "incdec") (and (not (match_test "TARGET_64BIT")) - (ior (match_operand:SI 1 "register_operand" "") - (match_operand:HI 1 "register_operand" "")))) + (ior (match_operand:SI 1 "register_operand") + (match_operand:HI 1 "register_operand")))) (const_int 0) (and (eq_attr "type" "push") - (not (match_operand 1 "memory_operand" ""))) + (not (match_operand 1 "memory_operand"))) (const_int 0) (and (eq_attr "type" "pop") - (not (match_operand 0 "memory_operand" ""))) + (not (match_operand 0 "memory_operand"))) (const_int 0) (and (eq_attr "type" "imov") (and (not (eq_attr "mode" "DI")) - (ior (and (match_operand 0 "register_operand" "") - (match_operand 1 "immediate_operand" "")) - (ior (and (match_operand 0 "ax_reg_operand" "") - (match_operand 1 "memory_displacement_only_operand" "")) - (and (match_operand 0 "memory_displacement_only_operand" "") - (match_operand 1 "ax_reg_operand" "")))))) + (ior (and (match_operand 0 "register_operand") + (match_operand 1 "immediate_operand")) + (ior (and (match_operand 0 "ax_reg_operand") + (match_operand 1 "memory_displacement_only_operand")) + (and (match_operand 0 "memory_displacement_only_operand") + (match_operand 1 "ax_reg_operand")))))) (const_int 0) (and (eq_attr "type" "call") - (match_operand 0 "constant_call_address_operand" "")) + (match_operand 0 "constant_call_address_operand")) (const_int 0) (and (eq_attr "type" "callv") - (match_operand 1 "constant_call_address_operand" "")) + (match_operand 1 "constant_call_address_operand")) (const_int 0) (and (eq_attr "type" "alu,alu1,icmp,test") - (match_operand 0 "ax_reg_operand" "")) + (match_operand 0 "ax_reg_operand")) (symbol_ref "(get_attr_length_immediate (insn) <= (get_attr_mode (insn) != MODE_QI))") ] (const_int 1))) @@ -555,43 +555,43 @@ (eq_attr "type" "frndint") (const_string "load") (eq_attr "type" "push") - (if_then_else (match_operand 1 "memory_operand" "") + (if_then_else (match_operand 1 "memory_operand") (const_string "both") (const_string "store")) (eq_attr "type" "pop") - (if_then_else (match_operand 0 "memory_operand" "") + (if_then_else (match_operand 0 "memory_operand") (const_string "both") (const_string "load")) (eq_attr "type" "setcc") - (if_then_else (match_operand 0 "memory_operand" "") + (if_then_else (match_operand 0 "memory_operand") (const_string "store") (const_string "none")) (eq_attr "type" "icmp,test,ssecmp,ssecomi,mmxcmp,fcmp") - (if_then_else (ior (match_operand 0 "memory_operand" "") - (match_operand 1 "memory_operand" "")) + (if_then_else (ior (match_operand 0 "memory_operand") + (match_operand 1 "memory_operand")) (const_string "load") (const_string "none")) (eq_attr "type" "ibr") - (if_then_else (match_operand 0 "memory_operand" "") + (if_then_else (match_operand 0 "memory_operand") (const_string "load") (const_string "none")) (eq_attr "type" "call") - (if_then_else (match_operand 0 "constant_call_address_operand" "") + (if_then_else (match_operand 0 "constant_call_address_operand") (const_string "none") (const_string "load")) (eq_attr "type" "callv") - (if_then_else (match_operand 1 "constant_call_address_operand" "") + (if_then_else (match_operand 1 "constant_call_address_operand") (const_string "none") (const_string "load")) (and (eq_attr "type" "alu1,negnot,ishift1,sselog1") - (match_operand 1 "memory_operand" "")) + (match_operand 1 "memory_operand")) (const_string "both") - (and (match_operand 0 "memory_operand" "") - (match_operand 1 "memory_operand" "")) + (and (match_operand 0 "memory_operand") + (match_operand 1 "memory_operand")) (const_string "both") - (match_operand 0 "memory_operand" "") + (match_operand 0 "memory_operand") (const_string "store") - (match_operand 1 "memory_operand" "") + (match_operand 1 "memory_operand") (const_string "load") (and (eq_attr "type" "!alu1,negnot,ishift1, @@ -599,10 +599,10 @@ fmov,fcmp,fsgn, sse,ssemov,ssecmp,ssecomi,ssecvt,ssecvt1,sseicvt,sselog1, sseiadd1,mmx,mmxmov,mmxcmp,mmxcvt") - (match_operand 2 "memory_operand" "")) + (match_operand 2 "memory_operand")) (const_string "load") (and (eq_attr "type" "icmov,ssemuladd,sse4arg") - (match_operand 3 "memory_operand" "")) + (match_operand 3 "memory_operand")) (const_string "load") ] (const_string "none"))) @@ -613,12 +613,12 @@ (cond [(eq_attr "type" "other,multi") (const_string "unknown") (and (eq_attr "type" "icmp,test,imov,alu1,ishift1,rotate1") - (and (match_operand 0 "memory_displacement_operand" "") - (match_operand 1 "immediate_operand" ""))) + (and (match_operand 0 "memory_displacement_operand") + (match_operand 1 "immediate_operand"))) (const_string "true") (and (eq_attr "type" "alu,ishift,ishiftx,rotate,rotatex,imul,idiv") - (and (match_operand 0 "memory_displacement_operand" "") - (match_operand 2 "immediate_operand" ""))) + (and (match_operand 0 "memory_displacement_operand") + (match_operand 2 "immediate_operand"))) (const_string "true") ] (const_string "false"))) @@ -936,12 +936,12 @@ (define_expand "cbranch<mode>4" [(set (reg:CC FLAGS_REG) - (compare:CC (match_operand:SDWIM 1 "nonimmediate_operand" "") - (match_operand:SDWIM 2 "<general_operand>" ""))) + (compare:CC (match_operand:SDWIM 1 "nonimmediate_operand") + (match_operand:SDWIM 2 "<general_operand>"))) (set (pc) (if_then_else (match_operator 0 "ordered_comparison_operator" [(reg:CC FLAGS_REG) (const_int 0)]) - (label_ref (match_operand 3 "" "")) + (label_ref (match_operand 3)) (pc)))] "" { @@ -954,9 +954,9 @@ (define_expand "cstore<mode>4" [(set (reg:CC FLAGS_REG) - (compare:CC (match_operand:SWIM 2 "nonimmediate_operand" "") - (match_operand:SWIM 3 "<general_operand>" ""))) - (set (match_operand:QI 0 "register_operand" "") + (compare:CC (match_operand:SWIM 2 "nonimmediate_operand") + (match_operand:SWIM 3 "<general_operand>"))) + (set (match_operand:QI 0 "register_operand") (match_operator 1 "ordered_comparison_operator" [(reg:CC FLAGS_REG) (const_int 0)]))] "" @@ -970,13 +970,13 @@ (define_expand "cmp<mode>_1" [(set (reg:CC FLAGS_REG) - (compare:CC (match_operand:SWI48 0 "nonimmediate_operand" "") - (match_operand:SWI48 1 "<general_operand>" "")))]) + (compare:CC (match_operand:SWI48 0 "nonimmediate_operand") + (match_operand:SWI48 1 "<general_operand>")))]) (define_insn "*cmp<mode>_ccno_1" [(set (reg FLAGS_REG) (compare (match_operand:SWI 0 "nonimmediate_operand" "<r>,?m<r>") - (match_operand:SWI 1 "const0_operand" "")))] + (match_operand:SWI 1 "const0_operand")))] "ix86_match_ccmode (insn, CCNOmode)" "@ test{<imodesuffix>}\t%0, %0 @@ -1041,7 +1041,7 @@ (match_operand 0 "ext_register_operand" "Q") (const_int 8) (const_int 8)) 0) - (match_operand:QI 1 "const0_operand" "")))] + (match_operand:QI 1 "const0_operand")))] "ix86_match_ccmode (insn, CCNOmode)" "test{b}\t%h0, %h0" [(set_attr "type" "test") @@ -1053,10 +1053,10 @@ (compare:CC (subreg:QI (zero_extract:SI - (match_operand 0 "ext_register_operand" "") + (match_operand 0 "ext_register_operand") (const_int 8) (const_int 8)) 0) - (match_operand:QI 1 "immediate_operand" "")))]) + (match_operand:QI 1 "immediate_operand")))]) (define_insn "*cmpqi_ext_3_insn" [(set (reg FLAGS_REG) @@ -1113,13 +1113,13 @@ (define_expand "cbranchxf4" [(set (reg:CC FLAGS_REG) - (compare:CC (match_operand:XF 1 "nonmemory_operand" "") - (match_operand:XF 2 "nonmemory_operand" ""))) + (compare:CC (match_operand:XF 1 "nonmemory_operand") + (match_operand:XF 2 "nonmemory_operand"))) (set (pc) (if_then_else (match_operator 0 "ix86_fp_comparison_operator" [(reg:CC FLAGS_REG) (const_int 0)]) - (label_ref (match_operand 3 "" "")) + (label_ref (match_operand 3)) (pc)))] "TARGET_80387" { @@ -1130,9 +1130,9 @@ (define_expand "cstorexf4" [(set (reg:CC FLAGS_REG) - (compare:CC (match_operand:XF 2 "nonmemory_operand" "") - (match_operand:XF 3 "nonmemory_operand" ""))) - (set (match_operand:QI 0 "register_operand" "") + (compare:CC (match_operand:XF 2 "nonmemory_operand") + (match_operand:XF 3 "nonmemory_operand"))) + (set (match_operand:QI 0 "register_operand") (match_operator 1 "ix86_fp_comparison_operator" [(reg:CC FLAGS_REG) (const_int 0)]))] @@ -1145,13 +1145,13 @@ (define_expand "cbranch<mode>4" [(set (reg:CC FLAGS_REG) - (compare:CC (match_operand:MODEF 1 "cmp_fp_expander_operand" "") - (match_operand:MODEF 2 "cmp_fp_expander_operand" ""))) + (compare:CC (match_operand:MODEF 1 "cmp_fp_expander_operand") + (match_operand:MODEF 2 "cmp_fp_expander_operand"))) (set (pc) (if_then_else (match_operator 0 "ix86_fp_comparison_operator" [(reg:CC FLAGS_REG) (const_int 0)]) - (label_ref (match_operand 3 "" "")) + (label_ref (match_operand 3)) (pc)))] "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)" { @@ -1162,9 +1162,9 @@ (define_expand "cstore<mode>4" [(set (reg:CC FLAGS_REG) - (compare:CC (match_operand:MODEF 2 "cmp_fp_expander_operand" "") - (match_operand:MODEF 3 "cmp_fp_expander_operand" ""))) - (set (match_operand:QI 0 "register_operand" "") + (compare:CC (match_operand:MODEF 2 "cmp_fp_expander_operand") + (match_operand:MODEF 3 "cmp_fp_expander_operand"))) + (set (match_operand:QI 0 "register_operand") (match_operator 1 "ix86_fp_comparison_operator" [(reg:CC FLAGS_REG) (const_int 0)]))] @@ -1178,9 +1178,9 @@ (define_expand "cbranchcc4" [(set (pc) (if_then_else (match_operator 0 "comparison_operator" - [(match_operand 1 "flags_reg_operand" "") - (match_operand 2 "const0_operand" "")]) - (label_ref (match_operand 3 "" "")) + [(match_operand 1 "flags_reg_operand") + (match_operand 2 "const0_operand")]) + (label_ref (match_operand 3)) (pc)))] "" { @@ -1190,10 +1190,10 @@ }) (define_expand "cstorecc4" - [(set (match_operand:QI 0 "register_operand" "") + [(set (match_operand:QI 0 "register_operand") (match_operator 1 "comparison_operator" - [(match_operand 2 "flags_reg_operand" "") - (match_operand 3 "const0_operand" "")]))] + [(match_operand 2 "flags_reg_operand") + (match_operand 3 "const0_operand")]))] "" { ix86_expand_setcc (operands[0], GET_CODE (operands[1]), @@ -1216,7 +1216,7 @@ (unspec:HI [(compare:CCFP (match_operand 1 "register_operand" "f") - (match_operand 2 "const0_operand" ""))] + (match_operand 2 "const0_operand"))] UNSPEC_FNSTSW))] "X87_FLOAT_MODE_P (GET_MODE (operands[1])) && GET_MODE (operands[1]) == GET_MODE (operands[2])" @@ -1224,9 +1224,9 @@ [(set_attr "type" "multi") (set_attr "unit" "i387") (set (attr "mode") - (cond [(match_operand:SF 1 "" "") + (cond [(match_operand:SF 1) (const_string "SF") - (match_operand:DF 1 "" "") + (match_operand:DF 1) (const_string "DF") ] (const_string "XF")))]) @@ -1235,7 +1235,7 @@ [(set (reg:CCFP FLAGS_REG) (compare:CCFP (match_operand 1 "register_operand" "f") - (match_operand 2 "const0_operand" ""))) + (match_operand 2 "const0_operand"))) (clobber (match_operand:HI 0 "register_operand" "=a"))] "X87_FLOAT_MODE_P (GET_MODE (operands[1])) && TARGET_SAHF && !TARGET_CMOVE @@ -1252,9 +1252,9 @@ [(set_attr "type" "multi") (set_attr "unit" "i387") (set (attr "mode") - (cond [(match_operand:SF 1 "" "") + (cond [(match_operand:SF 1) (const_string "SF") - (match_operand:DF 1 "" "") + (match_operand:DF 1) (const_string "DF") ] (const_string "XF")))]) @@ -1340,9 +1340,9 @@ [(set_attr "type" "multi") (set_attr "unit" "i387") (set (attr "mode") - (cond [(match_operand:SF 1 "" "") + (cond [(match_operand:SF 1) (const_string "SF") - (match_operand:DF 1 "" "") + (match_operand:DF 1) (const_string "DF") ] (const_string "XF")))]) @@ -1368,9 +1368,9 @@ [(set_attr "type" "multi") (set_attr "unit" "i387") (set (attr "mode") - (cond [(match_operand:SF 1 "" "") + (cond [(match_operand:SF 1) (const_string "SF") - (match_operand:DF 1 "" "") + (match_operand:DF 1) (const_string "DF") ] (const_string "XF")))]) @@ -1468,7 +1468,7 @@ [(set_attr "type" "fcmp,ssecomi") (set_attr "prefix" "orig,maybe_vex") (set (attr "mode") - (if_then_else (match_operand:SF 1 "" "") + (if_then_else (match_operand:SF 1) (const_string "SF") (const_string "DF"))) (set (attr "prefix_rep") @@ -1497,7 +1497,7 @@ [(set_attr "type" "ssecomi") (set_attr "prefix" "maybe_vex") (set (attr "mode") - (if_then_else (match_operand:SF 1 "" "") + (if_then_else (match_operand:SF 1) (const_string "SF") (const_string "DF"))) (set_attr "prefix_rep" "0") @@ -1520,9 +1520,9 @@ "* return output_fp_compare (insn, operands, true, false);" [(set_attr "type" "fcmp") (set (attr "mode") - (cond [(match_operand:SF 1 "" "") + (cond [(match_operand:SF 1) (const_string "SF") - (match_operand:DF 1 "" "") + (match_operand:DF 1) (const_string "DF") ] (const_string "XF"))) @@ -1541,7 +1541,7 @@ [(set_attr "type" "fcmp,ssecomi") (set_attr "prefix" "orig,maybe_vex") (set (attr "mode") - (if_then_else (match_operand:SF 1 "" "") + (if_then_else (match_operand:SF 1) (const_string "SF") (const_string "DF"))) (set (attr "prefix_rep") @@ -1570,7 +1570,7 @@ [(set_attr "type" "ssecomi") (set_attr "prefix" "maybe_vex") (set (attr "mode") - (if_then_else (match_operand:SF 1 "" "") + (if_then_else (match_operand:SF 1) (const_string "SF") (const_string "DF"))) (set_attr "prefix_rep" "0") @@ -1593,9 +1593,9 @@ "* return output_fp_compare (insn, operands, true, true);" [(set_attr "type" "fcmp") (set (attr "mode") - (cond [(match_operand:SF 1 "" "") + (cond [(match_operand:SF 1) (const_string "SF") - (match_operand:DF 1 "" "") + (match_operand:DF 1) (const_string "DF") ] (const_string "XF"))) @@ -1614,8 +1614,8 @@ (set_attr "mode" "<MODE>")]) (define_split - [(set (match_operand:TI 0 "push_operand" "") - (match_operand:TI 1 "general_operand" ""))] + [(set (match_operand:TI 0 "push_operand") + (match_operand:TI 1 "general_operand"))] "TARGET_64BIT && reload_completed && !SSE_REG_P (operands[1])" [(const_int 0)] @@ -1637,8 +1637,8 @@ ;; upper part by 32bit move. (define_peephole2 [(match_scratch:DI 2 "r") - (set (match_operand:DI 0 "push_operand" "") - (match_operand:DI 1 "immediate_operand" ""))] + (set (match_operand:DI 0 "push_operand") + (match_operand:DI 1 "immediate_operand"))] "TARGET_64BIT && !symbolic_operand (operands[1], DImode) && !x86_64_immediate_operand (operands[1], DImode)" [(set (match_dup 2) (match_dup 1)) @@ -1648,8 +1648,8 @@ ;; peephole2 pass is not run. ;; "&& 1" is needed to keep it from matching the previous pattern. (define_peephole2 - [(set (match_operand:DI 0 "push_operand" "") - (match_operand:DI 1 "immediate_operand" ""))] + [(set (match_operand:DI 0 "push_operand") + (match_operand:DI 1 "immediate_operand"))] "TARGET_64BIT && !symbolic_operand (operands[1], DImode) && !x86_64_immediate_operand (operands[1], DImode) && 1" [(set (match_dup 0) (match_dup 1)) @@ -1663,8 +1663,8 @@ }) (define_split - [(set (match_operand:DI 0 "push_operand" "") - (match_operand:DI 1 "immediate_operand" ""))] + [(set (match_operand:DI 0 "push_operand") + (match_operand:DI 1 "immediate_operand"))] "TARGET_64BIT && ((optimize > 0 && flag_peephole2) ? epilogue_completed : reload_completed) && !symbolic_operand (operands[1], DImode) @@ -1680,8 +1680,8 @@ }) (define_split - [(set (match_operand:DI 0 "push_operand" "") - (match_operand:DI 1 "general_operand" ""))] + [(set (match_operand:DI 0 "push_operand") + (match_operand:DI 1 "general_operand"))] "!TARGET_64BIT && reload_completed && !(MMX_REG_P (operands[1]) || SSE_REG_P (operands[1]))" [(const_int 0)] @@ -1745,14 +1745,14 @@ ;; Move instructions. (define_expand "movoi" - [(set (match_operand:OI 0 "nonimmediate_operand" "") - (match_operand:OI 1 "general_operand" ""))] + [(set (match_operand:OI 0 "nonimmediate_operand") + (match_operand:OI 1 "general_operand"))] "TARGET_AVX" "ix86_expand_move (OImode, operands); DONE;") (define_expand "movti" - [(set (match_operand:TI 0 "nonimmediate_operand" "") - (match_operand:TI 1 "nonimmediate_operand" ""))] + [(set (match_operand:TI 0 "nonimmediate_operand") + (match_operand:TI 1 "nonimmediate_operand"))] "TARGET_64BIT || TARGET_SSE" { if (TARGET_64BIT) @@ -1769,8 +1769,8 @@ ;; 32-bit targets when SSE is present, but doesn't seem to be harmful ;; to have around all the time. (define_expand "movcdi" - [(set (match_operand:CDI 0 "nonimmediate_operand" "") - (match_operand:CDI 1 "general_operand" ""))] + [(set (match_operand:CDI 0 "nonimmediate_operand") + (match_operand:CDI 1 "general_operand"))] "" { if (push_operand (operands[0], CDImode)) @@ -1781,14 +1781,14 @@ }) (define_expand "mov<mode>" - [(set (match_operand:SWI1248x 0 "nonimmediate_operand" "") - (match_operand:SWI1248x 1 "general_operand" ""))] + [(set (match_operand:SWI1248x 0 "nonimmediate_operand") + (match_operand:SWI1248x 1 "general_operand"))] "" "ix86_expand_move (<MODE>mode, operands); DONE;") (define_insn "*mov<mode>_xor" [(set (match_operand:SWI48 0 "register_operand" "=r") - (match_operand:SWI48 1 "const0_operand" "")) + (match_operand:SWI48 1 "const0_operand")) (clobber (reg:CC FLAGS_REG))] "reload_completed" "xor{l}\t%k0, %k0" @@ -1798,7 +1798,7 @@ (define_insn "*mov<mode>_or" [(set (match_operand:SWI48 0 "register_operand" "=r") - (match_operand:SWI48 1 "const_int_operand" "")) + (match_operand:SWI48 1 "const_int_operand")) (clobber (reg:CC FLAGS_REG))] "reload_completed && operands[1] == constm1_rtx" @@ -1883,8 +1883,8 @@ (const_string "DI")))]) (define_split - [(set (match_operand:TI 0 "nonimmediate_operand" "") - (match_operand:TI 1 "general_operand" ""))] + [(set (match_operand:TI 0 "nonimmediate_operand") + (match_operand:TI 1 "general_operand"))] "reload_completed && !SSE_REG_P (operands[0]) && !SSE_REG_P (operands[1])" [(const_int 0)] @@ -2002,7 +2002,7 @@ (const_string "ssemov") (eq_attr "alternative" "16,17") (const_string "ssecvt") - (match_operand 1 "pic_32bit_operand" "") + (match_operand 1 "pic_32bit_operand") (const_string "lea") ] (const_string "imov"))) @@ -2069,8 +2069,8 @@ ;; fails, move by 32bit parts. (define_peephole2 [(match_scratch:DI 2 "r") - (set (match_operand:DI 0 "memory_operand" "") - (match_operand:DI 1 "immediate_operand" ""))] + (set (match_operand:DI 0 "memory_operand") + (match_operand:DI 1 "immediate_operand"))] "TARGET_64BIT && !symbolic_operand (operands[1], DImode) && !x86_64_immediate_operand (operands[1], DImode)" [(set (match_dup 2) (match_dup 1)) @@ -2080,8 +2080,8 @@ ;; peephole2 pass is not run. ;; "&& 1" is needed to keep it from matching the previous pattern. (define_peephole2 - [(set (match_operand:DI 0 "memory_operand" "") - (match_operand:DI 1 "immediate_operand" ""))] + [(set (match_operand:DI 0 "memory_operand") + (match_operand:DI 1 "immediate_operand"))] "TARGET_64BIT && !symbolic_operand (operands[1], DImode) && !x86_64_immediate_operand (operands[1], DImode) && 1" [(set (match_dup 2) (match_dup 3)) @@ -2089,8 +2089,8 @@ "split_double_mode (DImode, &operands[0], 2, &operands[2], &operands[4]);") (define_split - [(set (match_operand:DI 0 "memory_operand" "") - (match_operand:DI 1 "immediate_operand" ""))] + [(set (match_operand:DI 0 "memory_operand") + (match_operand:DI 1 "immediate_operand"))] "TARGET_64BIT && ((optimize > 0 && flag_peephole2) ? epilogue_completed : reload_completed) && !symbolic_operand (operands[1], DImode) @@ -2172,8 +2172,8 @@ (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI,TI,DI,V4SF,V2SF,V4SF,V2SF,DI,DI")]) (define_split - [(set (match_operand:DI 0 "nonimmediate_operand" "") - (match_operand:DI 1 "general_operand" ""))] + [(set (match_operand:DI 0 "nonimmediate_operand") + (match_operand:DI 1 "general_operand"))] "!TARGET_64BIT && reload_completed && !(MMX_REG_P (operands[0]) || SSE_REG_P (operands[0])) && !(MMX_REG_P (operands[1]) || SSE_REG_P (operands[1]))" @@ -2235,7 +2235,7 @@ (const_string "sselog1") (eq_attr "alternative" "7,8,9,10,11") (const_string "ssemov") - (match_operand 1 "pic_32bit_operand" "") + (match_operand 1 "pic_32bit_operand") (const_string "lea") ] (const_string "imov"))) @@ -2287,7 +2287,7 @@ (not (match_test "TARGET_HIMODE_MATH")))) (const_string "imov") (and (eq_attr "alternative" "1,2") - (match_operand:HI 1 "aligned_operand" "")) + (match_operand:HI 1 "aligned_operand")) (const_string "imov") (and (match_test "TARGET_MOVX") (eq_attr "alternative" "0,2")) @@ -2298,7 +2298,7 @@ (cond [(eq_attr "type" "imovx") (const_string "SI") (and (eq_attr "alternative" "1,2") - (match_operand:HI 1 "aligned_operand" "")) + (match_operand:HI 1 "aligned_operand")) (const_string "SI") (and (eq_attr "alternative" "0") (ior (not (match_test "TARGET_PARTIAL_REG_STALL")) @@ -2336,7 +2336,7 @@ } [(set (attr "type") (cond [(and (eq_attr "alternative" "5") - (not (match_operand:QI 1 "aligned_operand" ""))) + (not (match_operand:QI 1 "aligned_operand"))) (const_string "imovx") (match_test "optimize_function_for_size_p (cfun)") (const_string "imov") @@ -2447,8 +2447,8 @@ (set_attr "athlon_decode" "vector")]) (define_expand "movstrict<mode>" - [(set (strict_low_part (match_operand:SWI12 0 "nonimmediate_operand" "")) - (match_operand:SWI12 1 "general_operand" ""))] + [(set (strict_low_part (match_operand:SWI12 0 "nonimmediate_operand")) + (match_operand:SWI12 1 "general_operand"))] "" { if (TARGET_PARTIAL_REG_STALL && optimize_function_for_speed_p (cfun)) @@ -2473,7 +2473,7 @@ (define_insn "*movstrict<mode>_xor" [(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+<r>")) - (match_operand:SWI12 1 "const0_operand" "")) + (match_operand:SWI12 1 "const0_operand")) (clobber (reg:CC FLAGS_REG))] "reload_completed" "xor{<imodesuffix>}\t%0, %0" @@ -2507,7 +2507,7 @@ } } [(set (attr "type") - (if_then_else (ior (not (match_operand:QI 0 "QIreg_operand" "")) + (if_then_else (ior (not (match_operand:QI 0 "QIreg_operand")) (match_test "TARGET_MOVX")) (const_string "imovx") (const_string "imov"))) @@ -2532,8 +2532,8 @@ } } [(set (attr "type") - (if_then_else (and (match_operand:QI 0 "register_operand" "") - (ior (not (match_operand:QI 0 "QIreg_operand" "")) + (if_then_else (and (match_operand:QI 0 "register_operand") + (ior (not (match_operand:QI 0 "QIreg_operand")) (match_test "TARGET_MOVX"))) (const_string "imovx") (const_string "imov"))) @@ -2569,7 +2569,7 @@ } } [(set (attr "type") - (if_then_else (ior (not (match_operand:QI 0 "QIreg_operand" "")) + (if_then_else (ior (not (match_operand:QI 0 "QIreg_operand")) (match_test "TARGET_MOVX")) (const_string "imovx") (const_string "imov"))) @@ -2595,8 +2595,8 @@ } } [(set (attr "type") - (if_then_else (and (match_operand:QI 0 "register_operand" "") - (ior (not (match_operand:QI 0 "QIreg_operand" "")) + (if_then_else (and (match_operand:QI 0 "register_operand") + (ior (not (match_operand:QI 0 "QIreg_operand")) (match_test "TARGET_MOVX"))) (const_string "imovx") (const_string "imov"))) @@ -2606,10 +2606,10 @@ (const_string "QI")))]) (define_expand "mov<mode>_insv_1" - [(set (zero_extract:SWI48 (match_operand 0 "ext_register_operand" "") + [(set (zero_extract:SWI48 (match_operand 0 "ext_register_operand") (const_int 8) (const_int 8)) - (match_operand:SWI48 1 "nonmemory_operand" ""))]) + (match_operand:SWI48 1 "nonmemory_operand"))]) (define_insn "*mov<mode>_insv_1_rex64" [(set (zero_extract:SWI48x (match_operand 0 "ext_register_operand" "+Q") @@ -2658,8 +2658,8 @@ ;; %%% Kill this when call knows how to work this out. (define_split - [(set (match_operand:TF 0 "push_operand" "") - (match_operand:TF 1 "sse_reg_operand" ""))] + [(set (match_operand:TF 0 "push_operand") + (match_operand:TF 1 "sse_reg_operand"))] "TARGET_SSE2 && reload_completed" [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (const_int -16))) (set (mem:TF (reg:P SP_REG)) (match_dup 1))]) @@ -2696,8 +2696,8 @@ ;; %%% Kill this when call knows how to work this out. (define_split - [(set (match_operand:XF 0 "push_operand" "") - (match_operand:XF 1 "fp_register_operand" ""))] + [(set (match_operand:XF 0 "push_operand") + (match_operand:XF 1 "fp_register_operand"))] "reload_completed" [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2))) (set (mem:XF (reg:P SP_REG)) (match_dup 1))] @@ -2734,8 +2734,8 @@ ;; %%% Kill this when call knows how to work this out. (define_split - [(set (match_operand:DF 0 "push_operand" "") - (match_operand:DF 1 "any_fp_register_operand" ""))] + [(set (match_operand:DF 0 "push_operand") + (match_operand:DF 1 "any_fp_register_operand"))] "reload_completed" [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (const_int -8))) (set (mem:DF (reg:P SP_REG)) (match_dup 1))]) @@ -2768,23 +2768,23 @@ ;; %%% Kill this when call knows how to work this out. (define_split - [(set (match_operand:SF 0 "push_operand" "") - (match_operand:SF 1 "any_fp_register_operand" ""))] + [(set (match_operand:SF 0 "push_operand") + (match_operand:SF 1 "any_fp_register_operand"))] "reload_completed" [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2))) (set (mem:SF (reg:P SP_REG)) (match_dup 1))] "operands[2] = GEN_INT (-GET_MODE_SIZE (<P:MODE>mode));") (define_split - [(set (match_operand:SF 0 "push_operand" "") - (match_operand:SF 1 "memory_operand" ""))] + [(set (match_operand:SF 0 "push_operand") + (match_operand:SF 1 "memory_operand"))] "reload_completed && (operands[2] = find_constant_src (insn))" [(set (match_dup 0) (match_dup 2))]) (define_split - [(set (match_operand 0 "push_operand" "") - (match_operand 1 "general_operand" ""))] + [(set (match_operand 0 "push_operand") + (match_operand 1 "general_operand"))] "reload_completed && (GET_MODE (operands[0]) == TFmode || GET_MODE (operands[0]) == XFmode @@ -2796,8 +2796,8 @@ ;; Floating point move instructions. (define_expand "movtf" - [(set (match_operand:TF 0 "nonimmediate_operand" "") - (match_operand:TF 1 "nonimmediate_operand" ""))] + [(set (match_operand:TF 0 "nonimmediate_operand") + (match_operand:TF 1 "nonimmediate_operand"))] "TARGET_SSE2" { ix86_expand_move (TFmode, operands); @@ -2805,8 +2805,8 @@ }) (define_expand "mov<mode>" - [(set (match_operand:X87MODEF 0 "nonimmediate_operand" "") - (match_operand:X87MODEF 1 "general_operand" ""))] + [(set (match_operand:X87MODEF 0 "nonimmediate_operand") + (match_operand:X87MODEF 1 "general_operand"))] "" "ix86_expand_move (<MODE>mode, operands); DONE;") @@ -3287,8 +3287,8 @@ (const_string "SF")))]) (define_split - [(set (match_operand 0 "any_fp_register_operand" "") - (match_operand 1 "memory_operand" ""))] + [(set (match_operand 0 "any_fp_register_operand") + (match_operand 1 "memory_operand"))] "reload_completed && (GET_MODE (operands[0]) == TFmode || GET_MODE (operands[0]) == XFmode @@ -3306,8 +3306,8 @@ }) (define_split - [(set (match_operand 0 "any_fp_register_operand" "") - (float_extend (match_operand 1 "memory_operand" "")))] + [(set (match_operand 0 "any_fp_register_operand") + (float_extend (match_operand 1 "memory_operand")))] "reload_completed && (GET_MODE (operands[0]) == TFmode || GET_MODE (operands[0]) == XFmode @@ -3325,8 +3325,8 @@ ;; Split the load of -0.0 or -1.0 into fldz;fchs or fld1;fchs sequence (define_split - [(set (match_operand:X87MODEF 0 "fp_register_operand" "") - (match_operand:X87MODEF 1 "immediate_operand" ""))] + [(set (match_operand:X87MODEF 0 "fp_register_operand") + (match_operand:X87MODEF 1 "immediate_operand"))] "reload_completed && (standard_80387_constant_p (operands[1]) == 8 || standard_80387_constant_p (operands[1]) == 9)" @@ -3344,8 +3344,8 @@ }) (define_split - [(set (match_operand 0 "nonimmediate_operand" "") - (match_operand 1 "general_operand" ""))] + [(set (match_operand 0 "nonimmediate_operand") + (match_operand 1 "general_operand"))] "reload_completed && (GET_MODE (operands[0]) == TFmode || GET_MODE (operands[0]) == XFmode @@ -3387,8 +3387,8 @@ ;; Zero extension instructions (define_expand "zero_extendsidi2" - [(set (match_operand:DI 0 "nonimmediate_operand" "") - (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]) + [(set (match_operand:DI 0 "nonimmediate_operand") + (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))]) (define_insn "*zero_extendsidi2_rex64" [(set (match_operand:DI 0 "nonimmediate_operand" @@ -3430,15 +3430,15 @@ (set_attr "mode" "SI,SI,SI,DI,DI,TI,TI")]) (define_split - [(set (match_operand:DI 0 "memory_operand" "") - (zero_extend:DI (match_operand:SI 1 "memory_operand" "")))] + [(set (match_operand:DI 0 "memory_operand") + (zero_extend:DI (match_operand:SI 1 "memory_operand")))] "reload_completed" [(set (match_dup 4) (const_int 0))] "split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);") (define_split - [(set (match_operand:DI 0 "register_operand" "") - (zero_extend:DI (match_operand:SI 1 "register_operand" "")))] + [(set (match_operand:DI 0 "register_operand") + (zero_extend:DI (match_operand:SI 1 "register_operand")))] "!TARGET_64BIT && reload_completed && !(MMX_REG_P (operands[0]) || SSE_REG_P (operands[0])) && true_regnum (operands[0]) == true_regnum (operands[1])" @@ -3446,8 +3446,8 @@ "split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);") (define_split - [(set (match_operand:DI 0 "nonimmediate_operand" "") - (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] + [(set (match_operand:DI 0 "nonimmediate_operand") + (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))] "!TARGET_64BIT && reload_completed && !(MEM_P (operands[0]) && MEM_P (operands[1])) && !(MMX_REG_P (operands[0]) || SSE_REG_P (operands[0]))" @@ -3465,8 +3465,8 @@ (set_attr "mode" "SI")]) (define_expand "zero_extend<mode>si2" - [(set (match_operand:SI 0 "register_operand" "") - (zero_extend:SI (match_operand:SWI12 1 "nonimmediate_operand" "")))] + [(set (match_operand:SI 0 "register_operand") + (zero_extend:SI (match_operand:SWI12 1 "nonimmediate_operand")))] "" { if (TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)) @@ -3513,8 +3513,8 @@ (set_attr "mode" "SI")]) (define_expand "zero_extendqihi2" - [(set (match_operand:HI 0 "register_operand" "") - (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))] + [(set (match_operand:HI 0 "register_operand") + (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))] "" { if (TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)) @@ -3562,8 +3562,8 @@ ;; Sign extension instructions (define_expand "extendsidi2" - [(set (match_operand:DI 0 "register_operand" "") - (sign_extend:DI (match_operand:SI 1 "register_operand" "")))] + [(set (match_operand:DI 0 "register_operand") + (sign_extend:DI (match_operand:SI 1 "register_operand")))] "" { if (!TARGET_64BIT) @@ -3595,10 +3595,10 @@ ;; Extend to memory case when source register does die. (define_split - [(set (match_operand:DI 0 "memory_operand" "") - (sign_extend:DI (match_operand:SI 1 "register_operand" ""))) + [(set (match_operand:DI 0 "memory_operand") + (sign_extend:DI (match_operand:SI 1 "register_operand"))) (clobber (reg:CC FLAGS_REG)) - (clobber (match_operand:SI 2 "register_operand" ""))] + (clobber (match_operand:SI 2 "register_operand"))] "(reload_completed && dead_or_set_p (insn, operands[1]) && !reg_mentioned_p (operands[1], operands[0]))" @@ -3610,10 +3610,10 @@ ;; Extend to memory case when source register does not die. (define_split - [(set (match_operand:DI 0 "memory_operand" "") - (sign_extend:DI (match_operand:SI 1 "register_operand" ""))) + [(set (match_operand:DI 0 "memory_operand") + (sign_extend:DI (match_operand:SI 1 "register_operand"))) (clobber (reg:CC FLAGS_REG)) - (clobber (match_operand:SI 2 "register_operand" ""))] + (clobber (match_operand:SI 2 "register_operand"))] "reload_completed" [(const_int 0)] { @@ -3640,10 +3640,10 @@ ;; Extend to register case. Optimize case where source and destination ;; registers match and cases where we can use cltd. (define_split - [(set (match_operand:DI 0 "register_operand" "") - (sign_extend:DI (match_operand:SI 1 "register_operand" ""))) + [(set (match_operand:DI 0 "register_operand") + (sign_extend:DI (match_operand:SI 1 "register_operand"))) (clobber (reg:CC FLAGS_REG)) - (clobber (match_scratch:SI 2 ""))] + (clobber (match_scratch:SI 2))] "reload_completed" [(const_int 0)] { @@ -3781,23 +3781,23 @@ ;; %%% Kill these when call knows how to work out a DFmode push earlier. (define_split - [(set (match_operand:DF 0 "push_operand" "") - (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))] + [(set (match_operand:DF 0 "push_operand") + (float_extend:DF (match_operand:SF 1 "fp_register_operand")))] "reload_completed" [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (const_int -8))) (set (mem:DF (reg:P SP_REG)) (float_extend:DF (match_dup 1)))]) (define_split - [(set (match_operand:XF 0 "push_operand" "") - (float_extend:XF (match_operand:MODEF 1 "fp_register_operand" "")))] + [(set (match_operand:XF 0 "push_operand") + (float_extend:XF (match_operand:MODEF 1 "fp_register_operand")))] "reload_completed" [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2))) (set (mem:XF (reg:P SP_REG)) (float_extend:XF (match_dup 1)))] "operands[2] = GEN_INT (-GET_MODE_SIZE (XFmode));") (define_expand "extendsfdf2" - [(set (match_operand:DF 0 "nonimmediate_operand" "") - (float_extend:DF (match_operand:SF 1 "general_operand" "")))] + [(set (match_operand:DF 0 "nonimmediate_operand") + (float_extend:DF (match_operand:SF 1 "general_operand")))] "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)" { /* ??? Needed for compress_float_constant since all fp constants @@ -3824,9 +3824,9 @@ that might lead to ICE on 32bit target. The sequence unlikely combine anyway. */ (define_split - [(set (match_operand:DF 0 "register_operand" "") + [(set (match_operand:DF 0 "register_operand") (float_extend:DF - (match_operand:SF 1 "nonimmediate_operand" "")))] + (match_operand:SF 1 "nonimmediate_operand")))] "TARGET_USE_VECTOR_FP_CONVERTS && optimize_insn_for_speed_p () && reload_completed && SSE_REG_P (operands[0])" @@ -3902,8 +3902,8 @@ (set_attr "mode" "SF,XF")]) (define_expand "extend<mode>xf2" - [(set (match_operand:XF 0 "nonimmediate_operand" "") - (float_extend:XF (match_operand:MODEF 1 "general_operand" "")))] + [(set (match_operand:XF 0 "nonimmediate_operand") + (float_extend:XF (match_operand:MODEF 1 "general_operand")))] "TARGET_80387" { /* ??? Needed for compress_float_constant since all fp constants @@ -3939,9 +3939,9 @@ ;; Conversion from DFmode to SFmode. (define_expand "truncdfsf2" - [(set (match_operand:SF 0 "nonimmediate_operand" "") + [(set (match_operand:SF 0 "nonimmediate_operand") (float_truncate:SF - (match_operand:DF 1 "nonimmediate_operand" "")))] + (match_operand:DF 1 "nonimmediate_operand")))] "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)" { if (TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_MIX_SSE_I387) @@ -3967,9 +3967,9 @@ that might lead to ICE on 32bit target. The sequence unlikely combine anyway. */ (define_split - [(set (match_operand:SF 0 "register_operand" "") + [(set (match_operand:SF 0 "register_operand") (float_truncate:SF - (match_operand:DF 1 "nonimmediate_operand" "")))] + (match_operand:DF 1 "nonimmediate_operand")))] "TARGET_USE_VECTOR_FP_CONVERTS && optimize_insn_for_speed_p () && reload_completed && SSE_REG_P (operands[0])" @@ -4006,9 +4006,9 @@ }) (define_expand "truncdfsf2_with_temp" - [(parallel [(set (match_operand:SF 0 "" "") - (float_truncate:SF (match_operand:DF 1 "" ""))) - (clobber (match_operand:SF 2 "" ""))])]) + [(parallel [(set (match_operand:SF 0) + (float_truncate:SF (match_operand:DF 1))) + (clobber (match_operand:SF 2))])]) (define_insn "*truncdfsf_fast_mixed" [(set (match_operand:SF 0 "nonimmediate_operand" "=fm,x") @@ -4107,10 +4107,10 @@ (set_attr "mode" "SF")]) (define_split - [(set (match_operand:SF 0 "register_operand" "") + [(set (match_operand:SF 0 "register_operand") (float_truncate:SF - (match_operand:DF 1 "fp_register_operand" ""))) - (clobber (match_operand 2 "" ""))] + (match_operand:DF 1 "fp_register_operand"))) + (clobber (match_operand 2))] "reload_completed" [(set (match_dup 2) (match_dup 1)) (set (match_dup 0) (match_dup 2))] @@ -4119,9 +4119,9 @@ ;; Conversion from XFmode to {SF,DF}mode (define_expand "truncxf<mode>2" - [(parallel [(set (match_operand:MODEF 0 "nonimmediate_operand" "") + [(parallel [(set (match_operand:MODEF 0 "nonimmediate_operand") (float_truncate:MODEF - (match_operand:XF 1 "register_operand" ""))) + (match_operand:XF 1 "register_operand"))) (clobber (match_dup 2))])] "TARGET_80387" { @@ -4190,27 +4190,27 @@ (set_attr "mode" "<MODE>")]) (define_split - [(set (match_operand:MODEF 0 "register_operand" "") + [(set (match_operand:MODEF 0 "register_operand") (float_truncate:MODEF - (match_operand:XF 1 "register_operand" ""))) - (clobber (match_operand:MODEF 2 "memory_operand" ""))] + (match_operand:XF 1 "register_operand"))) + (clobber (match_operand:MODEF 2 "memory_operand"))] "TARGET_80387 && reload_completed" [(set (match_dup 2) (float_truncate:MODEF (match_dup 1))) (set (match_dup 0) (match_dup 2))]) (define_split - [(set (match_operand:MODEF 0 "memory_operand" "") + [(set (match_operand:MODEF 0 "memory_operand") (float_truncate:MODEF - (match_operand:XF 1 "register_operand" ""))) - (clobber (match_operand:MODEF 2 "memory_operand" ""))] + (match_operand:XF 1 "register_operand"))) + (clobber (match_operand:MODEF 2 "memory_operand"))] "TARGET_80387" [(set (match_dup 0) (float_truncate:MODEF (match_dup 1)))]) ;; Signed conversion to DImode. (define_expand "fix_truncxfdi2" - [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "") - (fix:DI (match_operand:XF 1 "register_operand" ""))) + [(parallel [(set (match_operand:DI 0 "nonimmediate_operand") + (fix:DI (match_operand:XF 1 "register_operand"))) (clobber (reg:CC FLAGS_REG))])] "TARGET_80387" { @@ -4222,8 +4222,8 @@ }) (define_expand "fix_trunc<mode>di2" - [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "") - (fix:DI (match_operand:MODEF 1 "register_operand" ""))) + [(parallel [(set (match_operand:DI 0 "nonimmediate_operand") + (fix:DI (match_operand:MODEF 1 "register_operand"))) (clobber (reg:CC FLAGS_REG))])] "TARGET_80387 || (TARGET_64BIT && SSE_FLOAT_MODE_P (<MODE>mode))" { @@ -4246,8 +4246,8 @@ ;; Signed conversion to SImode. (define_expand "fix_truncxfsi2" - [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "") - (fix:SI (match_operand:XF 1 "register_operand" ""))) + [(parallel [(set (match_operand:SI 0 "nonimmediate_operand") + (fix:SI (match_operand:XF 1 "register_operand"))) (clobber (reg:CC FLAGS_REG))])] "TARGET_80387" { @@ -4259,8 +4259,8 @@ }) (define_expand "fix_trunc<mode>si2" - [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "") - (fix:SI (match_operand:MODEF 1 "register_operand" ""))) + [(parallel [(set (match_operand:SI 0 "nonimmediate_operand") + (fix:SI (match_operand:MODEF 1 "register_operand"))) (clobber (reg:CC FLAGS_REG))])] "TARGET_80387 || SSE_FLOAT_MODE_P (<MODE>mode)" { @@ -4283,8 +4283,8 @@ ;; Signed conversion to HImode. (define_expand "fix_trunc<mode>hi2" - [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "") - (fix:HI (match_operand:X87MODEF 1 "register_operand" ""))) + [(parallel [(set (match_operand:HI 0 "nonimmediate_operand") + (fix:HI (match_operand:X87MODEF 1 "register_operand"))) (clobber (reg:CC FLAGS_REG))])] "TARGET_80387 && !(SSE_FLOAT_MODE_P (<MODE>mode) && (!TARGET_FISTTP || TARGET_SSE_MATH))" @@ -4300,12 +4300,12 @@ (define_expand "fixuns_trunc<mode>si2" [(parallel - [(set (match_operand:SI 0 "register_operand" "") + [(set (match_operand:SI 0 "register_operand") (unsigned_fix:SI - (match_operand:MODEF 1 "nonimmediate_operand" ""))) + (match_operand:MODEF 1 "nonimmediate_operand"))) (use (match_dup 2)) - (clobber (match_scratch:<ssevecmode> 3 "")) - (clobber (match_scratch:<ssevecmode> 4 ""))])] + (clobber (match_scratch:<ssevecmode> 3)) + (clobber (match_scratch:<ssevecmode> 4))])] "!TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH" { enum machine_mode mode = <MODE>mode; @@ -4345,8 +4345,8 @@ (define_expand "fixuns_trunc<mode>hi2" [(set (match_dup 2) - (fix:SI (match_operand:MODEF 1 "nonimmediate_operand" ""))) - (set (match_operand:HI 0 "nonimmediate_operand" "") + (fix:SI (match_operand:MODEF 1 "nonimmediate_operand"))) + (set (match_operand:HI 0 "nonimmediate_operand") (subreg:HI (match_dup 2) 0))] "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH" "operands[2] = gen_reg_rtx (SImode);") @@ -4381,9 +4381,9 @@ ;; Shorten x87->SSE reload sequences of fix_trunc?f?i_sse patterns. (define_peephole2 - [(set (match_operand:MODEF 0 "register_operand" "") - (match_operand:MODEF 1 "memory_operand" "")) - (set (match_operand:SWI48x 2 "register_operand" "") + [(set (match_operand:MODEF 0 "register_operand") + (match_operand:MODEF 1 "memory_operand")) + (set (match_operand:SWI48x 2 "register_operand") (fix:SWI48x (match_dup 0)))] "TARGET_SHORTEN_X87_SSE && !(TARGET_AVOID_VECTOR_DECODE && optimize_insn_for_speed_p ()) @@ -4393,23 +4393,23 @@ ;; Avoid vector decoded forms of the instruction. (define_peephole2 [(match_scratch:DF 2 "x") - (set (match_operand:SWI48x 0 "register_operand" "") - (fix:SWI48x (match_operand:DF 1 "memory_operand" "")))] + (set (match_operand:SWI48x 0 "register_operand") + (fix:SWI48x (match_operand:DF 1 "memory_operand")))] "TARGET_SSE2 && TARGET_AVOID_VECTOR_DECODE && optimize_insn_for_speed_p ()" [(set (match_dup 2) (match_dup 1)) (set (match_dup 0) (fix:SWI48x (match_dup 2)))]) (define_peephole2 [(match_scratch:SF 2 "x") - (set (match_operand:SWI48x 0 "register_operand" "") - (fix:SWI48x (match_operand:SF 1 "memory_operand" "")))] + (set (match_operand:SWI48x 0 "register_operand") + (fix:SWI48x (match_operand:SF 1 "memory_operand")))] "TARGET_AVOID_VECTOR_DECODE && optimize_insn_for_speed_p ()" [(set (match_dup 2) (match_dup 1)) (set (match_dup 0) (fix:SWI48x (match_dup 2)))]) (define_insn_and_split "fix_trunc<mode>_fisttp_i387_1" - [(set (match_operand:SWI248x 0 "nonimmediate_operand" "") - (fix:SWI248x (match_operand 1 "register_operand" "")))] + [(set (match_operand:SWI248x 0 "nonimmediate_operand") + (fix:SWI248x (match_operand 1 "register_operand")))] "X87_FLOAT_MODE_P (GET_MODE (operands[1])) && TARGET_FISTTP && !((SSE_FLOAT_MODE_P (GET_MODE (operands[1])) @@ -4462,20 +4462,20 @@ (set_attr "mode" "<MODE>")]) (define_split - [(set (match_operand:SWI248x 0 "register_operand" "") - (fix:SWI248x (match_operand 1 "register_operand" ""))) - (clobber (match_operand:SWI248x 2 "memory_operand" "")) - (clobber (match_scratch 3 ""))] + [(set (match_operand:SWI248x 0 "register_operand") + (fix:SWI248x (match_operand 1 "register_operand"))) + (clobber (match_operand:SWI248x 2 "memory_operand")) + (clobber (match_scratch 3))] "reload_completed" [(parallel [(set (match_dup 2) (fix:SWI248x (match_dup 1))) (clobber (match_dup 3))]) (set (match_dup 0) (match_dup 2))]) (define_split - [(set (match_operand:SWI248x 0 "memory_operand" "") - (fix:SWI248x (match_operand 1 "register_operand" ""))) - (clobber (match_operand:SWI248x 2 "memory_operand" "")) - (clobber (match_scratch 3 ""))] + [(set (match_operand:SWI248x 0 "memory_operand") + (fix:SWI248x (match_operand 1 "register_operand"))) + (clobber (match_operand:SWI248x 2 "memory_operand")) + (clobber (match_scratch 3))] "reload_completed" [(parallel [(set (match_dup 0) (fix:SWI248x (match_dup 1))) (clobber (match_dup 3))])]) @@ -4486,8 +4486,8 @@ ;; clobbering insns can be used. Look at emit_i387_cw_initialization () ;; function in i386.c. (define_insn_and_split "*fix_trunc<mode>_i387_1" - [(set (match_operand:SWI248x 0 "nonimmediate_operand" "") - (fix:SWI248x (match_operand 1 "register_operand" ""))) + [(set (match_operand:SWI248x 0 "nonimmediate_operand") + (fix:SWI248x (match_operand 1 "register_operand"))) (clobber (reg:CC FLAGS_REG))] "X87_FLOAT_MODE_P (GET_MODE (operands[1])) && !TARGET_FISTTP @@ -4548,12 +4548,12 @@ (set_attr "mode" "DI")]) (define_split - [(set (match_operand:DI 0 "register_operand" "") - (fix:DI (match_operand 1 "register_operand" ""))) - (use (match_operand:HI 2 "memory_operand" "")) - (use (match_operand:HI 3 "memory_operand" "")) - (clobber (match_operand:DI 4 "memory_operand" "")) - (clobber (match_scratch 5 ""))] + [(set (match_operand:DI 0 "register_operand") + (fix:DI (match_operand 1 "register_operand"))) + (use (match_operand:HI 2 "memory_operand")) + (use (match_operand:HI 3 "memory_operand")) + (clobber (match_operand:DI 4 "memory_operand")) + (clobber (match_scratch 5))] "reload_completed" [(parallel [(set (match_dup 4) (fix:DI (match_dup 1))) (use (match_dup 2)) @@ -4562,12 +4562,12 @@ (set (match_dup 0) (match_dup 4))]) (define_split - [(set (match_operand:DI 0 "memory_operand" "") - (fix:DI (match_operand 1 "register_operand" ""))) - (use (match_operand:HI 2 "memory_operand" "")) - (use (match_operand:HI 3 "memory_operand" "")) - (clobber (match_operand:DI 4 "memory_operand" "")) - (clobber (match_scratch 5 ""))] + [(set (match_operand:DI 0 "memory_operand") + (fix:DI (match_operand 1 "register_operand"))) + (use (match_operand:HI 2 "memory_operand")) + (use (match_operand:HI 3 "memory_operand")) + (clobber (match_operand:DI 4 "memory_operand")) + (clobber (match_scratch 5))] "reload_completed" [(parallel [(set (match_dup 0) (fix:DI (match_dup 1))) (use (match_dup 2)) @@ -4602,11 +4602,11 @@ (set_attr "mode" "<MODE>")]) (define_split - [(set (match_operand:SWI24 0 "register_operand" "") - (fix:SWI24 (match_operand 1 "register_operand" ""))) - (use (match_operand:HI 2 "memory_operand" "")) - (use (match_operand:HI 3 "memory_operand" "")) - (clobber (match_operand:SWI24 4 "memory_operand" ""))] + [(set (match_operand:SWI24 0 "register_operand") + (fix:SWI24 (match_operand 1 "register_operand"))) + (use (match_operand:HI 2 "memory_operand")) + (use (match_operand:HI 3 "memory_operand")) + (clobber (match_operand:SWI24 4 "memory_operand"))] "reload_completed" [(parallel [(set (match_dup 4) (fix:SWI24 (match_dup 1))) (use (match_dup 2)) @@ -4614,11 +4614,11 @@ (set (match_dup 0) (match_dup 4))]) (define_split - [(set (match_operand:SWI24 0 "memory_operand" "") - (fix:SWI24 (match_operand 1 "register_operand" ""))) - (use (match_operand:HI 2 "memory_operand" "")) - (use (match_operand:HI 3 "memory_operand" "")) - (clobber (match_operand:SWI24 4 "memory_operand" ""))] + [(set (match_operand:SWI24 0 "memory_operand") + (fix:SWI24 (match_operand 1 "register_operand"))) + (use (match_operand:HI 2 "memory_operand")) + (use (match_operand:HI 3 "memory_operand")) + (clobber (match_operand:SWI24 4 "memory_operand"))] "reload_completed" [(parallel [(set (match_dup 0) (fix:SWI24 (match_dup 1))) (use (match_dup 2)) @@ -4654,16 +4654,16 @@ ;; wants to be able to do this between registers. (define_expand "floathi<mode>2" - [(set (match_operand:X87MODEF 0 "register_operand" "") - (float:X87MODEF (match_operand:HI 1 "nonimmediate_operand" "")))] + [(set (match_operand:X87MODEF 0 "register_operand") + (float:X87MODEF (match_operand:HI 1 "nonimmediate_operand")))] "TARGET_80387 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)") ;; Pre-reload splitter to add memory clobber to the pattern. (define_insn_and_split "*floathi<mode>2_1" - [(set (match_operand:X87MODEF 0 "register_operand" "") - (float:X87MODEF (match_operand:HI 1 "register_operand" "")))] + [(set (match_operand:X87MODEF 0 "register_operand") + (float:X87MODEF (match_operand:HI 1 "register_operand")))] "TARGET_80387 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -4700,9 +4700,9 @@ (set_attr "fp_int_src" "true")]) (define_split - [(set (match_operand:X87MODEF 0 "register_operand" "") - (float:X87MODEF (match_operand:HI 1 "register_operand" ""))) - (clobber (match_operand:HI 2 "memory_operand" ""))] + [(set (match_operand:X87MODEF 0 "register_operand") + (float:X87MODEF (match_operand:HI 1 "register_operand"))) + (clobber (match_operand:HI 2 "memory_operand"))] "TARGET_80387 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -4711,9 +4711,9 @@ (set (match_dup 0) (float:X87MODEF (match_dup 2)))]) (define_split - [(set (match_operand:X87MODEF 0 "register_operand" "") - (float:X87MODEF (match_operand:HI 1 "memory_operand" ""))) - (clobber (match_operand:HI 2 "memory_operand" ""))] + [(set (match_operand:X87MODEF 0 "register_operand") + (float:X87MODEF (match_operand:HI 1 "memory_operand"))) + (clobber (match_operand:HI 2 "memory_operand"))] "TARGET_80387 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -4721,9 +4721,9 @@ [(set (match_dup 0) (float:X87MODEF (match_dup 1)))]) (define_expand "float<SWI48x:mode><X87MODEF:mode>2" - [(set (match_operand:X87MODEF 0 "register_operand" "") + [(set (match_operand:X87MODEF 0 "register_operand") (float:X87MODEF - (match_operand:SWI48x 1 "nonimmediate_operand" "")))] + (match_operand:SWI48x 1 "nonimmediate_operand")))] "TARGET_80387 || ((<SWI48x:MODE>mode != DImode || TARGET_64BIT) && SSE_FLOAT_MODE_P (<X87MODEF:MODE>mode) && TARGET_SSE_MATH)" @@ -4751,8 +4751,8 @@ ;; Pre-reload splitter to add memory clobber to the pattern. (define_insn_and_split "*float<SWI48x:mode><X87MODEF:mode>2_1" - [(set (match_operand:X87MODEF 0 "register_operand" "") - (float:X87MODEF (match_operand:SWI48x 1 "register_operand" "")))] + [(set (match_operand:X87MODEF 0 "register_operand") + (float:X87MODEF (match_operand:SWI48x 1 "register_operand")))] "((TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SWI48x:MODE>mode) && (!((<SWI48x:MODE>mode != DImode || TARGET_64BIT) @@ -4836,9 +4836,9 @@ (set_attr "fp_int_src" "true")]) (define_split - [(set (match_operand:MODEF 0 "register_operand" "") - (float:MODEF (match_operand:SWI48x 1 "register_operand" ""))) - (clobber (match_operand:SWI48x 2 "memory_operand" ""))] + [(set (match_operand:MODEF 0 "register_operand") + (float:MODEF (match_operand:SWI48x 1 "register_operand"))) + (clobber (match_operand:SWI48x 2 "memory_operand"))] "(<SWI48x:MODE>mode != DImode || TARGET_64BIT) && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387 && TARGET_INTER_UNIT_CONVERSIONS @@ -4849,9 +4849,9 @@ [(set (match_dup 0) (float:MODEF (match_dup 1)))]) (define_split - [(set (match_operand:MODEF 0 "register_operand" "") - (float:MODEF (match_operand:SWI48x 1 "register_operand" ""))) - (clobber (match_operand:SWI48x 2 "memory_operand" ""))] + [(set (match_operand:MODEF 0 "register_operand") + (float:MODEF (match_operand:SWI48x 1 "register_operand"))) + (clobber (match_operand:SWI48x 2 "memory_operand"))] "(<SWI48x:MODE>mode != DImode || TARGET_64BIT) && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387 && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun)) @@ -4941,9 +4941,9 @@ (set_attr "fp_int_src" "true")]) (define_split - [(set (match_operand:MODEF 0 "register_operand" "") - (float:MODEF (match_operand:SI 1 "register_operand" ""))) - (clobber (match_operand:SI 2 "memory_operand" ""))] + [(set (match_operand:MODEF 0 "register_operand") + (float:MODEF (match_operand:SI 1 "register_operand"))) + (clobber (match_operand:SI 2 "memory_operand"))] "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun) && reload_completed @@ -4984,9 +4984,9 @@ }) (define_split - [(set (match_operand:MODEF 0 "register_operand" "") - (float:MODEF (match_operand:SI 1 "memory_operand" ""))) - (clobber (match_operand:SI 2 "memory_operand" ""))] + [(set (match_operand:MODEF 0 "register_operand") + (float:MODEF (match_operand:SI 1 "memory_operand"))) + (clobber (match_operand:SI 2 "memory_operand"))] "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun) && reload_completed @@ -5009,8 +5009,8 @@ }) (define_split - [(set (match_operand:MODEF 0 "register_operand" "") - (float:MODEF (match_operand:SI 1 "register_operand" "")))] + [(set (match_operand:MODEF 0 "register_operand") + (float:MODEF (match_operand:SI 1 "register_operand")))] "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun) && reload_completed @@ -5055,8 +5055,8 @@ }) (define_split - [(set (match_operand:MODEF 0 "register_operand" "") - (float:MODEF (match_operand:SI 1 "memory_operand" "")))] + [(set (match_operand:MODEF 0 "register_operand") + (float:MODEF (match_operand:SI 1 "memory_operand")))] "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun) && reload_completed @@ -5116,9 +5116,9 @@ (set_attr "fp_int_src" "true")]) (define_split - [(set (match_operand:MODEF 0 "register_operand" "") - (float:MODEF (match_operand:SWI48x 1 "nonimmediate_operand" ""))) - (clobber (match_operand:SWI48x 2 "memory_operand" ""))] + [(set (match_operand:MODEF 0 "register_operand") + (float:MODEF (match_operand:SWI48x 1 "nonimmediate_operand"))) + (clobber (match_operand:SWI48x 2 "memory_operand"))] "(<SWI48x:MODE>mode != DImode || TARGET_64BIT) && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH && (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun)) @@ -5151,9 +5151,9 @@ (set_attr "fp_int_src" "true")]) (define_split - [(set (match_operand:MODEF 0 "register_operand" "") - (float:MODEF (match_operand:SWI48x 1 "register_operand" ""))) - (clobber (match_operand:SWI48x 2 "memory_operand" ""))] + [(set (match_operand:MODEF 0 "register_operand") + (float:MODEF (match_operand:SWI48x 1 "register_operand"))) + (clobber (match_operand:SWI48x 2 "memory_operand"))] "(<SWI48x:MODE>mode != DImode || TARGET_64BIT) && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun)) @@ -5165,9 +5165,9 @@ (set (match_dup 0) (float:MODEF (match_dup 2)))]) (define_split - [(set (match_operand:MODEF 0 "register_operand" "") - (float:MODEF (match_operand:SWI48x 1 "memory_operand" ""))) - (clobber (match_operand:SWI48x 2 "memory_operand" ""))] + [(set (match_operand:MODEF 0 "register_operand") + (float:MODEF (match_operand:SWI48x 1 "memory_operand"))) + (clobber (match_operand:SWI48x 2 "memory_operand"))] "(<SWI48x:MODE>mode != DImode || TARGET_64BIT) && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH && reload_completed @@ -5203,9 +5203,9 @@ (set_attr "fp_int_src" "true")]) (define_split - [(set (match_operand:X87MODEF 0 "fp_register_operand" "") - (float:X87MODEF (match_operand:SWI48x 1 "register_operand" ""))) - (clobber (match_operand:SWI48x 2 "memory_operand" ""))] + [(set (match_operand:X87MODEF 0 "fp_register_operand") + (float:X87MODEF (match_operand:SWI48x 1 "register_operand"))) + (clobber (match_operand:SWI48x 2 "memory_operand"))] "TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SWI48x:MODE>mode) && reload_completed" @@ -5213,9 +5213,9 @@ (set (match_dup 0) (float:X87MODEF (match_dup 2)))]) (define_split - [(set (match_operand:X87MODEF 0 "fp_register_operand" "") - (float:X87MODEF (match_operand:SWI48x 1 "memory_operand" ""))) - (clobber (match_operand:SWI48x 2 "memory_operand" ""))] + [(set (match_operand:X87MODEF 0 "fp_register_operand") + (float:X87MODEF (match_operand:SWI48x 1 "memory_operand"))) + (clobber (match_operand:SWI48x 2 "memory_operand"))] "TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SWI48x:MODE>mode) && reload_completed" @@ -5241,11 +5241,11 @@ (set_attr "fp_int_src" "true")]) (define_split - [(set (match_operand:X87MODEF 0 "fp_register_operand" "") - (float:X87MODEF (match_operand:DI 1 "register_operand" ""))) - (clobber (match_scratch:V4SI 3 "")) - (clobber (match_scratch:V4SI 4 "")) - (clobber (match_operand:DI 2 "memory_operand" ""))] + [(set (match_operand:X87MODEF 0 "fp_register_operand") + (float:X87MODEF (match_operand:DI 1 "register_operand"))) + (clobber (match_scratch:V4SI 3)) + (clobber (match_scratch:V4SI 4)) + (clobber (match_operand:DI 2 "memory_operand"))] "TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode) && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES && !TARGET_64BIT && optimize_function_for_speed_p (cfun) @@ -5266,11 +5266,11 @@ }) (define_split - [(set (match_operand:X87MODEF 0 "fp_register_operand" "") - (float:X87MODEF (match_operand:DI 1 "memory_operand" ""))) - (clobber (match_scratch:V4SI 3 "")) - (clobber (match_scratch:V4SI 4 "")) - (clobber (match_operand:DI 2 "memory_operand" ""))] + [(set (match_operand:X87MODEF 0 "fp_register_operand") + (float:X87MODEF (match_operand:DI 1 "memory_operand"))) + (clobber (match_scratch:V4SI 3)) + (clobber (match_scratch:V4SI 4)) + (clobber (match_operand:DI 2 "memory_operand"))] "TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode) && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES && !TARGET_64BIT && optimize_function_for_speed_p (cfun) @@ -5297,11 +5297,11 @@ (set_attr "mode" "<MODE>")]) (define_split - [(set (match_operand:X87MODEF 0 "register_operand" "") + [(set (match_operand:X87MODEF 0 "register_operand") (unsigned_float:X87MODEF - (match_operand:SI 1 "register_operand" ""))) - (clobber (match_operand:DI 2 "memory_operand" "")) - (clobber (match_scratch:SI 3 ""))] + (match_operand:SI 1 "register_operand"))) + (clobber (match_operand:DI 2 "memory_operand")) + (clobber (match_scratch:SI 3))] "!TARGET_64BIT && TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode) && TARGET_SSE @@ -5312,11 +5312,11 @@ "operands[1] = simplify_gen_subreg (DImode, operands[1], SImode, 0);") (define_split - [(set (match_operand:X87MODEF 0 "register_operand" "") + [(set (match_operand:X87MODEF 0 "register_operand") (unsigned_float:X87MODEF - (match_operand:SI 1 "memory_operand" ""))) - (clobber (match_operand:DI 2 "memory_operand" "")) - (clobber (match_scratch:SI 3 ""))] + (match_operand:SI 1 "memory_operand"))) + (clobber (match_operand:DI 2 "memory_operand")) + (clobber (match_scratch:SI 3))] "!TARGET_64BIT && TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode) && TARGET_SSE @@ -5331,11 +5331,11 @@ (define_expand "floatunssi<mode>2" [(parallel - [(set (match_operand:X87MODEF 0 "register_operand" "") + [(set (match_operand:X87MODEF 0 "register_operand") (unsigned_float:X87MODEF - (match_operand:SI 1 "nonimmediate_operand" ""))) + (match_operand:SI 1 "nonimmediate_operand"))) (clobber (match_dup 2)) - (clobber (match_scratch:SI 3 ""))])] + (clobber (match_scratch:SI 3))])] "!TARGET_64BIT && ((TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode) && TARGET_SSE) @@ -5356,14 +5356,14 @@ }) (define_expand "floatunsdisf2" - [(use (match_operand:SF 0 "register_operand" "")) - (use (match_operand:DI 1 "nonimmediate_operand" ""))] + [(use (match_operand:SF 0 "register_operand")) + (use (match_operand:DI 1 "nonimmediate_operand"))] "TARGET_64BIT && TARGET_SSE_MATH" "x86_emit_floatuns (operands); DONE;") (define_expand "floatunsdidf2" - [(use (match_operand:DF 0 "register_operand" "")) - (use (match_operand:DI 1 "nonimmediate_operand" ""))] + [(use (match_operand:DF 0 "register_operand")) + (use (match_operand:DI 1 "nonimmediate_operand"))] "(TARGET_64BIT || TARGET_KEEPS_VECTOR_ALIGNED_STACK) && TARGET_SSE2 && TARGET_SSE_MATH" { @@ -5377,9 +5377,9 @@ ;; Add instructions (define_expand "add<mode>3" - [(set (match_operand:SDWIM 0 "nonimmediate_operand" "") - (plus:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand" "") - (match_operand:SDWIM 2 "<general_operand>" "")))] + [(set (match_operand:SDWIM 0 "nonimmediate_operand") + (plus:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand") + (match_operand:SDWIM 2 "<general_operand>")))] "" "ix86_expand_binary_operator (PLUS, <MODE>mode, operands); DONE;") @@ -5540,13 +5540,13 @@ [(set (attr "type") (cond [(eq_attr "alternative" "3") (const_string "lea") - (match_operand:SWI48 2 "incdec_operand" "") + (match_operand:SWI48 2 "incdec_operand") (const_string "incdec") ] (const_string "alu"))) (set (attr "length_immediate") (if_then_else - (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" "")) + (and (eq_attr "type" "alu") (match_operand 2 "const128_operand")) (const_string "1") (const_string "*"))) (set_attr "mode" "<MODE>")]) @@ -5597,13 +5597,13 @@ [(set (attr "type") (cond [(eq_attr "alternative" "2") (const_string "lea") - (match_operand:SI 2 "incdec_operand" "") + (match_operand:SI 2 "incdec_operand") (const_string "incdec") ] (const_string "alu"))) (set (attr "length_immediate") (if_then_else - (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" "")) + (and (eq_attr "type" "alu") (match_operand 2 "const128_operand")) (const_string "1") (const_string "*"))) (set_attr "mode" "SI")]) @@ -5649,13 +5649,13 @@ [(set (attr "type") (cond [(eq_attr "alternative" "3") (const_string "lea") - (match_operand:HI 2 "incdec_operand" "") + (match_operand:HI 2 "incdec_operand") (const_string "incdec") ] (const_string "alu"))) (set (attr "length_immediate") (if_then_else - (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" "")) + (and (eq_attr "type" "alu") (match_operand 2 "const128_operand")) (const_string "1") (const_string "*"))) (set_attr "mode" "HI,HI,HI,SI")]) @@ -5711,13 +5711,13 @@ [(set (attr "type") (cond [(eq_attr "alternative" "5") (const_string "lea") - (match_operand:QI 2 "incdec_operand" "") + (match_operand:QI 2 "incdec_operand") (const_string "incdec") ] (const_string "alu"))) (set (attr "length_immediate") (if_then_else - (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" "")) + (and (eq_attr "type" "alu") (match_operand 2 "const128_operand")) (const_string "1") (const_string "*"))) (set_attr "mode" "QI,QI,QI,SI,SI,SI")]) @@ -5749,20 +5749,20 @@ } } [(set (attr "type") - (if_then_else (match_operand:QI 1 "incdec_operand" "") + (if_then_else (match_operand:QI 1 "incdec_operand") (const_string "incdec") (const_string "alu1"))) (set (attr "memory") - (if_then_else (match_operand 1 "memory_operand" "") + (if_then_else (match_operand 1 "memory_operand") (const_string "load") (const_string "none"))) (set_attr "mode" "QI")]) ;; Split non destructive adds if we cannot use lea. (define_split - [(set (match_operand:SWI48 0 "register_operand" "") - (plus:SWI48 (match_operand:SWI48 1 "register_operand" "") - (match_operand:SWI48 2 "nonmemory_operand" ""))) + [(set (match_operand:SWI48 0 "register_operand") + (plus:SWI48 (match_operand:SWI48 1 "register_operand") + (match_operand:SWI48 2 "nonmemory_operand"))) (clobber (reg:CC FLAGS_REG))] "reload_completed && ix86_avoid_lea_for_add (insn, operands)" [(set (match_dup 0) (match_dup 1)) @@ -5771,9 +5771,9 @@ ;; Convert add to the lea pattern to avoid flags dependency. (define_split - [(set (match_operand:SWI 0 "register_operand" "") - (plus:SWI (match_operand:SWI 1 "register_operand" "") - (match_operand:SWI 2 "<nonmemory_operand>" ""))) + [(set (match_operand:SWI 0 "register_operand") + (plus:SWI (match_operand:SWI 1 "register_operand") + (match_operand:SWI 2 "<nonmemory_operand>"))) (clobber (reg:CC FLAGS_REG))] "reload_completed && ix86_lea_for_add_ok (insn, operands)" [(const_int 0)] @@ -5797,10 +5797,10 @@ ;; Convert add to the lea pattern to avoid flags dependency. (define_split - [(set (match_operand:DI 0 "register_operand" "") + [(set (match_operand:DI 0 "register_operand") (zero_extend:DI - (plus:SI (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "x86_64_nonmemory_operand" "")))) + (plus:SI (match_operand:SI 1 "register_operand") + (match_operand:SI 2 "x86_64_nonmemory_operand")))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && reload_completed && ix86_lea_for_add_ok (insn, operands)" [(set (match_dup 0) @@ -5837,12 +5837,12 @@ } } [(set (attr "type") - (if_then_else (match_operand:SWI 2 "incdec_operand" "") + (if_then_else (match_operand:SWI 2 "incdec_operand") (const_string "incdec") (const_string "alu"))) (set (attr "length_immediate") (if_then_else - (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" "")) + (and (eq_attr "type" "alu") (match_operand 2 "const128_operand")) (const_string "1") (const_string "*"))) (set_attr "mode" "<MODE>")]) @@ -5878,12 +5878,12 @@ } } [(set (attr "type") - (if_then_else (match_operand:SI 2 "incdec_operand" "") + (if_then_else (match_operand:SI 2 "incdec_operand") (const_string "incdec") (const_string "alu"))) (set (attr "length_immediate") (if_then_else - (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" "")) + (and (eq_attr "type" "alu") (match_operand 2 "const128_operand")) (const_string "1") (const_string "*"))) (set_attr "mode" "SI")]) @@ -5916,12 +5916,12 @@ } } [(set (attr "type") - (if_then_else (match_operand:SWI 2 "incdec_operand" "") + (if_then_else (match_operand:SWI 2 "incdec_operand") (const_string "incdec") (const_string "alu"))) (set (attr "length_immediate") (if_then_else - (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" "")) + (and (eq_attr "type" "alu") (match_operand 2 "const128_operand")) (const_string "1") (const_string "*"))) (set_attr "mode" "<MODE>")]) @@ -5956,12 +5956,12 @@ } } [(set (attr "type") - (if_then_else (match_operand:SI 2 "incdec_operand" "") + (if_then_else (match_operand:SI 2 "incdec_operand") (const_string "incdec") (const_string "alu"))) (set (attr "length_immediate") (if_then_else - (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" "")) + (and (eq_attr "type" "alu") (match_operand 2 "const128_operand")) (const_string "1") (const_string "*"))) (set_attr "mode" "SI")]) @@ -6001,12 +6001,12 @@ } } [(set (attr "type") - (if_then_else (match_operand:DI 2 "incdec_operand" "") + (if_then_else (match_operand:DI 2 "incdec_operand") (const_string "incdec") (const_string "alu"))) (set (attr "length_immediate") (if_then_else - (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" "")) + (and (eq_attr "type" "alu") (match_operand 2 "const128_operand")) (const_string "1") (const_string "*"))) (set_attr "mode" "DI")]) @@ -6045,12 +6045,12 @@ } } [(set (attr "type") - (if_then_else (match_operand:<MODE> 2 "incdec_operand" "") + (if_then_else (match_operand:<MODE> 2 "incdec_operand") (const_string "incdec") (const_string "alu"))) (set (attr "length_immediate") (if_then_else - (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" "")) + (and (eq_attr "type" "alu") (match_operand 2 "const128_operand")) (const_string "1") (const_string "*"))) (set_attr "mode" "<MODE>")]) @@ -6085,12 +6085,12 @@ } } [(set (attr "type") - (if_then_else (match_operand:SWI 2 "incdec_operand" "") + (if_then_else (match_operand:SWI 2 "incdec_operand") (const_string "incdec") (const_string "alu"))) (set (attr "length_immediate") (if_then_else - (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" "")) + (and (eq_attr "type" "alu") (match_operand 2 "const128_operand")) (const_string "1") (const_string "*"))) (set_attr "mode" "<MODE>")]) @@ -6124,7 +6124,7 @@ } } [(set (attr "type") - (if_then_else (match_operand:QI 2 "incdec_operand" "") + (if_then_else (match_operand:QI 2 "incdec_operand") (const_string "incdec") (const_string "alu"))) (set_attr "modrm" "1") @@ -6159,7 +6159,7 @@ } } [(set (attr "type") - (if_then_else (match_operand:QI 2 "incdec_operand" "") + (if_then_else (match_operand:QI 2 "incdec_operand") (const_string "incdec") (const_string "alu"))) (set_attr "modrm" "1") @@ -6322,16 +6322,16 @@ } [(set_attr "type" "lea") (set (attr "mode") - (if_then_else (match_operand:DI 0 "" "") + (if_then_else (match_operand:DI 0) (const_string "DI") (const_string "SI")))]) ;; Subtract instructions (define_expand "sub<mode>3" - [(set (match_operand:SDWIM 0 "nonimmediate_operand" "") - (minus:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand" "") - (match_operand:SDWIM 2 "<general_operand>" "")))] + [(set (match_operand:SDWIM 0 "nonimmediate_operand") + (minus:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand") + (match_operand:SDWIM 2 "<general_operand>")))] "" "ix86_expand_binary_operator (MINUS, <MODE>mode, operands); DONE;") @@ -6451,13 +6451,13 @@ (define_expand "<plusminus_insn><mode>3_carry" [(parallel - [(set (match_operand:SWI 0 "nonimmediate_operand" "") + [(set (match_operand:SWI 0 "nonimmediate_operand") (plusminus:SWI - (match_operand:SWI 1 "nonimmediate_operand" "") + (match_operand:SWI 1 "nonimmediate_operand") (plus:SWI (match_operator:SWI 4 "ix86_carry_flag_operator" - [(match_operand 3 "flags_reg_operand" "") + [(match_operand 3 "flags_reg_operand") (const_int 0)]) - (match_operand:SWI 2 "<general_operand>" "")))) + (match_operand:SWI 2 "<general_operand>")))) (clobber (reg:CC FLAGS_REG))])] "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)") @@ -6564,34 +6564,34 @@ ;; The patterns that match these are at the end of this file. (define_expand "<plusminus_insn>xf3" - [(set (match_operand:XF 0 "register_operand" "") + [(set (match_operand:XF 0 "register_operand") (plusminus:XF - (match_operand:XF 1 "register_operand" "") - (match_operand:XF 2 "register_operand" "")))] + (match_operand:XF 1 "register_operand") + (match_operand:XF 2 "register_operand")))] "TARGET_80387") (define_expand "<plusminus_insn><mode>3" - [(set (match_operand:MODEF 0 "register_operand" "") + [(set (match_operand:MODEF 0 "register_operand") (plusminus:MODEF - (match_operand:MODEF 1 "register_operand" "") - (match_operand:MODEF 2 "nonimmediate_operand" "")))] + (match_operand:MODEF 1 "register_operand") + (match_operand:MODEF 2 "nonimmediate_operand")))] "(TARGET_80387 && X87_ENABLE_ARITH (<MODE>mode)) || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)") ;; Multiply instructions (define_expand "mul<mode>3" - [(parallel [(set (match_operand:SWIM248 0 "register_operand" "") + [(parallel [(set (match_operand:SWIM248 0 "register_operand") (mult:SWIM248 - (match_operand:SWIM248 1 "register_operand" "") - (match_operand:SWIM248 2 "<general_operand>" ""))) + (match_operand:SWIM248 1 "register_operand") + (match_operand:SWIM248 2 "<general_operand>"))) (clobber (reg:CC FLAGS_REG))])]) (define_expand "mulqi3" - [(parallel [(set (match_operand:QI 0 "register_operand" "") + [(parallel [(set (match_operand:QI 0 "register_operand") (mult:QI - (match_operand:QI 1 "register_operand" "") - (match_operand:QI 2 "nonimmediate_operand" ""))) + (match_operand:QI 1 "register_operand") + (match_operand:QI 2 "nonimmediate_operand"))) (clobber (reg:CC FLAGS_REG))])] "TARGET_QIMODE_MATH") @@ -6624,12 +6624,12 @@ (eq_attr "alternative" "1") (const_string "vector") (and (eq_attr "alternative" "2") - (match_operand 1 "memory_operand" "")) + (match_operand 1 "memory_operand")) (const_string "vector")] (const_string "direct"))) (set (attr "amdfam10_decode") (cond [(and (eq_attr "alternative" "0,1") - (match_operand 1 "memory_operand" "")) + (match_operand 1 "memory_operand")) (const_string "vector")] (const_string "direct"))) (set_attr "bdver1_decode" "direct") @@ -6655,12 +6655,12 @@ (eq_attr "alternative" "1") (const_string "vector") (and (eq_attr "alternative" "2") - (match_operand 1 "memory_operand" "")) + (match_operand 1 "memory_operand")) (const_string "vector")] (const_string "direct"))) (set (attr "amdfam10_decode") (cond [(and (eq_attr "alternative" "0,1") - (match_operand 1 "memory_operand" "")) + (match_operand 1 "memory_operand")) (const_string "vector")] (const_string "direct"))) (set_attr "bdver1_decode" "direct") @@ -6725,21 +6725,21 @@ (set_attr "mode" "QI")]) (define_expand "<u>mul<mode><dwi>3" - [(parallel [(set (match_operand:<DWI> 0 "register_operand" "") + [(parallel [(set (match_operand:<DWI> 0 "register_operand") (mult:<DWI> (any_extend:<DWI> - (match_operand:DWIH 1 "nonimmediate_operand" "")) + (match_operand:DWIH 1 "nonimmediate_operand")) (any_extend:<DWI> - (match_operand:DWIH 2 "register_operand" "")))) + (match_operand:DWIH 2 "register_operand")))) (clobber (reg:CC FLAGS_REG))])]) (define_expand "<u>mulqihi3" - [(parallel [(set (match_operand:HI 0 "register_operand" "") + [(parallel [(set (match_operand:HI 0 "register_operand") (mult:HI (any_extend:HI - (match_operand:QI 1 "nonimmediate_operand" "")) + (match_operand:QI 1 "nonimmediate_operand")) (any_extend:HI - (match_operand:QI 2 "register_operand" "")))) + (match_operand:QI 2 "register_operand")))) (clobber (reg:CC FLAGS_REG))])] "TARGET_QIMODE_MATH") @@ -6807,12 +6807,12 @@ ;; Convert mul to the mulx pattern to avoid flags dependency. (define_split - [(set (match_operand:<DWI> 0 "register_operand" "") + [(set (match_operand:<DWI> 0 "register_operand") (mult:<DWI> (zero_extend:<DWI> - (match_operand:DWIH 1 "register_operand" "")) + (match_operand:DWIH 1 "register_operand")) (zero_extend:<DWI> - (match_operand:DWIH 2 "nonimmediate_operand" "")))) + (match_operand:DWIH 2 "nonimmediate_operand")))) (clobber (reg:CC FLAGS_REG))] "TARGET_BMI2 && reload_completed && true_regnum (operands[1]) == DX_REG" @@ -6872,16 +6872,16 @@ (set_attr "mode" "QI")]) (define_expand "<s>mul<mode>3_highpart" - [(parallel [(set (match_operand:SWI48 0 "register_operand" "") + [(parallel [(set (match_operand:SWI48 0 "register_operand") (truncate:SWI48 (lshiftrt:<DWI> (mult:<DWI> (any_extend:<DWI> - (match_operand:SWI48 1 "nonimmediate_operand" "")) + (match_operand:SWI48 1 "nonimmediate_operand")) (any_extend:<DWI> - (match_operand:SWI48 2 "register_operand" ""))) + (match_operand:SWI48 2 "register_operand"))) (match_dup 4)))) - (clobber (match_scratch:SWI48 3 "")) + (clobber (match_scratch:SWI48 3)) (clobber (reg:CC FLAGS_REG))])] "" "operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));") @@ -6962,15 +6962,15 @@ ;; The patterns that match these are at the end of this file. (define_expand "mulxf3" - [(set (match_operand:XF 0 "register_operand" "") - (mult:XF (match_operand:XF 1 "register_operand" "") - (match_operand:XF 2 "register_operand" "")))] + [(set (match_operand:XF 0 "register_operand") + (mult:XF (match_operand:XF 1 "register_operand") + (match_operand:XF 2 "register_operand")))] "TARGET_80387") (define_expand "mul<mode>3" - [(set (match_operand:MODEF 0 "register_operand" "") - (mult:MODEF (match_operand:MODEF 1 "register_operand" "") - (match_operand:MODEF 2 "nonimmediate_operand" "")))] + [(set (match_operand:MODEF 0 "register_operand") + (mult:MODEF (match_operand:MODEF 1 "register_operand") + (match_operand:MODEF 2 "nonimmediate_operand")))] "(TARGET_80387 && X87_ENABLE_ARITH (<MODE>mode)) || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)") @@ -6979,22 +6979,22 @@ ;; The patterns that match these are at the end of this file. (define_expand "divxf3" - [(set (match_operand:XF 0 "register_operand" "") - (div:XF (match_operand:XF 1 "register_operand" "") - (match_operand:XF 2 "register_operand" "")))] + [(set (match_operand:XF 0 "register_operand") + (div:XF (match_operand:XF 1 "register_operand") + (match_operand:XF 2 "register_operand")))] "TARGET_80387") (define_expand "divdf3" - [(set (match_operand:DF 0 "register_operand" "") - (div:DF (match_operand:DF 1 "register_operand" "") - (match_operand:DF 2 "nonimmediate_operand" "")))] + [(set (match_operand:DF 0 "register_operand") + (div:DF (match_operand:DF 1 "register_operand") + (match_operand:DF 2 "nonimmediate_operand")))] "(TARGET_80387 && X87_ENABLE_ARITH (DFmode)) || (TARGET_SSE2 && TARGET_SSE_MATH)") (define_expand "divsf3" - [(set (match_operand:SF 0 "register_operand" "") - (div:SF (match_operand:SF 1 "register_operand" "") - (match_operand:SF 2 "nonimmediate_operand" "")))] + [(set (match_operand:SF 0 "register_operand") + (div:SF (match_operand:SF 1 "register_operand") + (match_operand:SF 2 "nonimmediate_operand")))] "(TARGET_80387 && X87_ENABLE_ARITH (SFmode)) || TARGET_SSE_MATH" { @@ -7013,11 +7013,11 @@ ;; Divmod instructions. (define_expand "divmod<mode>4" - [(parallel [(set (match_operand:SWIM248 0 "register_operand" "") + [(parallel [(set (match_operand:SWIM248 0 "register_operand") (div:SWIM248 - (match_operand:SWIM248 1 "register_operand" "") - (match_operand:SWIM248 2 "nonimmediate_operand" ""))) - (set (match_operand:SWIM248 3 "register_operand" "") + (match_operand:SWIM248 1 "register_operand") + (match_operand:SWIM248 2 "nonimmediate_operand"))) + (set (match_operand:SWIM248 3 "register_operand") (mod:SWIM248 (match_dup 1) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])]) @@ -7027,10 +7027,10 @@ ;; else ;; use original integer divide (define_split - [(set (match_operand:SWI48 0 "register_operand" "") - (div:SWI48 (match_operand:SWI48 2 "register_operand" "") - (match_operand:SWI48 3 "nonimmediate_operand" ""))) - (set (match_operand:SWI48 1 "register_operand" "") + [(set (match_operand:SWI48 0 "register_operand") + (div:SWI48 (match_operand:SWI48 2 "register_operand") + (match_operand:SWI48 3 "nonimmediate_operand"))) + (set (match_operand:SWI48 1 "register_operand") (mod:SWI48 (match_dup 2) (match_dup 3))) (clobber (reg:CC FLAGS_REG))] "TARGET_USE_8BIT_IDIV @@ -7124,11 +7124,11 @@ (set_attr "mode" "<MODE>")]) (define_expand "divmodqi4" - [(parallel [(set (match_operand:QI 0 "register_operand" "") + [(parallel [(set (match_operand:QI 0 "register_operand") (div:QI - (match_operand:QI 1 "register_operand" "") - (match_operand:QI 2 "nonimmediate_operand" ""))) - (set (match_operand:QI 3 "register_operand" "") + (match_operand:QI 1 "register_operand") + (match_operand:QI 2 "nonimmediate_operand"))) + (set (match_operand:QI 3 "register_operand") (mod:QI (match_dup 1) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])] "TARGET_QIMODE_MATH" @@ -7186,11 +7186,11 @@ (set_attr "mode" "QI")]) (define_expand "udivmod<mode>4" - [(parallel [(set (match_operand:SWIM248 0 "register_operand" "") + [(parallel [(set (match_operand:SWIM248 0 "register_operand") (udiv:SWIM248 - (match_operand:SWIM248 1 "register_operand" "") - (match_operand:SWIM248 2 "nonimmediate_operand" ""))) - (set (match_operand:SWIM248 3 "register_operand" "") + (match_operand:SWIM248 1 "register_operand") + (match_operand:SWIM248 2 "nonimmediate_operand"))) + (set (match_operand:SWIM248 3 "register_operand") (umod:SWIM248 (match_dup 1) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])]) @@ -7200,10 +7200,10 @@ ;; else ;; use original integer divide (define_split - [(set (match_operand:SWI48 0 "register_operand" "") - (udiv:SWI48 (match_operand:SWI48 2 "register_operand" "") - (match_operand:SWI48 3 "nonimmediate_operand" ""))) - (set (match_operand:SWI48 1 "register_operand" "") + [(set (match_operand:SWI48 0 "register_operand") + (udiv:SWI48 (match_operand:SWI48 2 "register_operand") + (match_operand:SWI48 3 "nonimmediate_operand"))) + (set (match_operand:SWI48 1 "register_operand") (umod:SWI48 (match_dup 2) (match_dup 3))) (clobber (reg:CC FLAGS_REG))] "TARGET_USE_8BIT_IDIV @@ -7270,11 +7270,11 @@ (set_attr "mode" "<MODE>")]) (define_expand "udivmodqi4" - [(parallel [(set (match_operand:QI 0 "register_operand" "") + [(parallel [(set (match_operand:QI 0 "register_operand") (udiv:QI - (match_operand:QI 1 "register_operand" "") - (match_operand:QI 2 "nonimmediate_operand" ""))) - (set (match_operand:QI 3 "register_operand" "") + (match_operand:QI 1 "register_operand") + (match_operand:QI 2 "nonimmediate_operand"))) + (set (match_operand:QI 3 "register_operand") (umod:QI (match_dup 1) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])] "TARGET_QIMODE_MATH" @@ -7353,21 +7353,21 @@ (define_expand "testsi_ccno_1" [(set (reg:CCNO FLAGS_REG) (compare:CCNO - (and:SI (match_operand:SI 0 "nonimmediate_operand" "") - (match_operand:SI 1 "x86_64_nonmemory_operand" "")) + (and:SI (match_operand:SI 0 "nonimmediate_operand") + (match_operand:SI 1 "x86_64_nonmemory_operand")) (const_int 0)))]) (define_expand "testqi_ccz_1" [(set (reg:CCZ FLAGS_REG) - (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "") - (match_operand:QI 1 "nonmemory_operand" "")) + (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand") + (match_operand:QI 1 "nonmemory_operand")) (const_int 0)))]) (define_expand "testdi_ccno_1" [(set (reg:CCNO FLAGS_REG) (compare:CCNO - (and:DI (match_operand:DI 0 "nonimmediate_operand" "") - (match_operand:DI 1 "x86_64_szext_general_operand" "")) + (and:DI (match_operand:DI 0 "nonimmediate_operand") + (match_operand:DI 1 "x86_64_szext_general_operand")) (const_int 0)))] "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))") @@ -7435,10 +7435,10 @@ (compare:CCNO (and:SI (zero_extract:SI - (match_operand 0 "ext_register_operand" "") + (match_operand 0 "ext_register_operand") (const_int 8) (const_int 8)) - (match_operand 1 "const_int_operand" "")) + (match_operand 1 "const_int_operand")) (const_int 0)))]) (define_insn "*testqi_ext_0" @@ -7513,8 +7513,8 @@ [(set (reg FLAGS_REG) (compare (zero_extract:DI (match_operand 0 "nonimmediate_operand" "rm") - (match_operand:DI 1 "const_int_operand" "") - (match_operand:DI 2 "const_int_operand" "")) + (match_operand:DI 1 "const_int_operand") + (match_operand:DI 2 "const_int_operand")) (const_int 0)))] "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode) @@ -7535,8 +7535,8 @@ [(set (reg FLAGS_REG) (compare (zero_extract:SI (match_operand 0 "nonimmediate_operand" "rm") - (match_operand:SI 1 "const_int_operand" "") - (match_operand:SI 2 "const_int_operand" "")) + (match_operand:SI 1 "const_int_operand") + (match_operand:SI 2 "const_int_operand")) (const_int 0)))] "ix86_match_ccmode (insn, CCNOmode) && INTVAL (operands[1]) > 0 @@ -7549,12 +7549,12 @@ "#") (define_split - [(set (match_operand 0 "flags_reg_operand" "") + [(set (match_operand 0 "flags_reg_operand") (match_operator 1 "compare_operator" [(zero_extract - (match_operand 2 "nonimmediate_operand" "") - (match_operand 3 "const_int_operand" "") - (match_operand 4 "const_int_operand" "")) + (match_operand 2 "nonimmediate_operand") + (match_operand 3 "const_int_operand") + (match_operand 4 "const_int_operand")) (const_int 0)]))] "ix86_match_ccmode (insn, CCNOmode)" [(set (match_dup 0) (match_op_dup 1 [(match_dup 2) (const_int 0)]))] @@ -7608,10 +7608,10 @@ ;; Do the conversion only post-reload to avoid limiting of the register class ;; to QI regs. (define_split - [(set (match_operand 0 "flags_reg_operand" "") + [(set (match_operand 0 "flags_reg_operand") (match_operator 1 "compare_operator" - [(and (match_operand 2 "register_operand" "") - (match_operand 3 "const_int_operand" "")) + [(and (match_operand 2 "register_operand") + (match_operand 3 "const_int_operand")) (const_int 0)]))] "reload_completed && QI_REG_P (operands[2]) @@ -7631,10 +7631,10 @@ }) (define_split - [(set (match_operand 0 "flags_reg_operand" "") + [(set (match_operand 0 "flags_reg_operand") (match_operator 1 "compare_operator" - [(and (match_operand 2 "nonimmediate_operand" "") - (match_operand 3 "const_int_operand" "")) + [(and (match_operand 2 "nonimmediate_operand") + (match_operand 3 "const_int_operand")) (const_int 0)]))] "reload_completed && GET_MODE (operands[2]) != QImode @@ -7656,9 +7656,9 @@ ;; it should be done with splitters. (define_expand "and<mode>3" - [(set (match_operand:SWIM 0 "nonimmediate_operand" "") - (and:SWIM (match_operand:SWIM 1 "nonimmediate_operand" "") - (match_operand:SWIM 2 "<general_szext_operand>" "")))] + [(set (match_operand:SWIM 0 "nonimmediate_operand") + (and:SWIM (match_operand:SWIM 1 "nonimmediate_operand") + (match_operand:SWIM 2 "<general_szext_operand>")))] "" "ix86_expand_binary_operator (AND, <MODE>mode, operands); DONE;") @@ -7689,7 +7689,7 @@ (if_then_else (and (eq_attr "type" "imovx") (and (match_test "INTVAL (operands[2]) == 0xff") - (match_operand 1 "ext_QIreg_operand" ""))) + (match_operand 1 "ext_QIreg_operand"))) (const_string "1") (const_string "*"))) (set_attr "mode" "SI,DI,DI,SI")]) @@ -7716,7 +7716,7 @@ (if_then_else (and (eq_attr "type" "imovx") (and (match_test "INTVAL (operands[2]) == 0xff") - (match_operand 1 "ext_QIreg_operand" ""))) + (match_operand 1 "ext_QIreg_operand"))) (const_string "1") (const_string "*"))) (set_attr "length_immediate" "*,*,0") @@ -7756,7 +7756,7 @@ (set (attr "prefix_rex") (if_then_else (and (eq_attr "type" "imovx") - (match_operand 1 "ext_QIreg_operand" "")) + (match_operand 1 "ext_QIreg_operand")) (const_string "1") (const_string "*"))) (set_attr "mode" "HI,HI,SI")]) @@ -7787,9 +7787,9 @@ (set_attr "mode" "QI")]) (define_split - [(set (match_operand:SWI248 0 "register_operand" "") - (and:SWI248 (match_operand:SWI248 1 "nonimmediate_operand" "") - (match_operand:SWI248 2 "const_int_operand" ""))) + [(set (match_operand:SWI248 0 "register_operand") + (and:SWI248 (match_operand:SWI248 1 "nonimmediate_operand") + (match_operand:SWI248 2 "const_int_operand"))) (clobber (reg:CC FLAGS_REG))] "reload_completed && true_regnum (operands[0]) != true_regnum (operands[1])" @@ -7825,7 +7825,7 @@ }) (define_split - [(set (match_operand 0 "register_operand" "") + [(set (match_operand 0 "register_operand") (and (match_dup 0) (const_int -65536))) (clobber (reg:CC FLAGS_REG))] @@ -7835,7 +7835,7 @@ "operands[1] = gen_lowpart (HImode, operands[0]);") (define_split - [(set (match_operand 0 "ext_register_operand" "") + [(set (match_operand 0 "ext_register_operand") (and (match_dup 0) (const_int -256))) (clobber (reg:CC FLAGS_REG))] @@ -7845,7 +7845,7 @@ "operands[1] = gen_lowpart (QImode, operands[0]);") (define_split - [(set (match_operand 0 "ext_register_operand" "") + [(set (match_operand 0 "ext_register_operand") (and (match_dup 0) (const_int -65281))) (clobber (reg:CC FLAGS_REG))] @@ -8061,9 +8061,9 @@ ;; of memory mismatch stalls. We may want to do the splitting for optimizing ;; for size, but that can (should?) be handled by generic code instead. (define_split - [(set (match_operand 0 "register_operand" "") - (and (match_operand 1 "register_operand" "") - (match_operand 2 "const_int_operand" ""))) + [(set (match_operand 0 "register_operand") + (and (match_operand 1 "register_operand") + (match_operand 2 "const_int_operand"))) (clobber (reg:CC FLAGS_REG))] "reload_completed && QI_REG_P (operands[0]) @@ -8084,9 +8084,9 @@ ;; Since AND can be encoded with sign extended immediate, this is only ;; profitable when 7th bit is not set. (define_split - [(set (match_operand 0 "register_operand" "") - (and (match_operand 1 "general_operand" "") - (match_operand 2 "const_int_operand" ""))) + [(set (match_operand 0 "register_operand") + (and (match_operand 1 "general_operand") + (match_operand 2 "const_int_operand"))) (clobber (reg:CC FLAGS_REG))] "reload_completed && ANY_QI_REG_P (operands[0]) @@ -8110,9 +8110,9 @@ ;; If this is considered useful, it should be done with splitters. (define_expand "<code><mode>3" - [(set (match_operand:SWIM 0 "nonimmediate_operand" "") - (any_or:SWIM (match_operand:SWIM 1 "nonimmediate_operand" "") - (match_operand:SWIM 2 "<general_operand>" "")))] + [(set (match_operand:SWIM 0 "nonimmediate_operand") + (any_or:SWIM (match_operand:SWIM 1 "nonimmediate_operand") + (match_operand:SWIM 2 "<general_operand>")))] "" "ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;") @@ -8320,9 +8320,9 @@ (set_attr "mode" "QI")]) (define_split - [(set (match_operand 0 "register_operand" "") - (any_or (match_operand 1 "register_operand" "") - (match_operand 2 "const_int_operand" ""))) + [(set (match_operand 0 "register_operand") + (any_or (match_operand 1 "register_operand") + (match_operand 2 "const_int_operand"))) (clobber (reg:CC FLAGS_REG))] "reload_completed && QI_REG_P (operands[0]) @@ -8343,9 +8343,9 @@ ;; Since OR can be encoded with sign extended immediate, this is only ;; profitable when 7th bit is set. (define_split - [(set (match_operand 0 "register_operand" "") - (any_or (match_operand 1 "general_operand" "") - (match_operand 2 "const_int_operand" ""))) + [(set (match_operand 0 "register_operand") + (any_or (match_operand 1 "general_operand") + (match_operand 2 "const_int_operand"))) (clobber (reg:CC FLAGS_REG))] "reload_completed && ANY_QI_REG_P (operands[0]) @@ -8369,12 +8369,12 @@ (compare:CCNO (xor:SI (zero_extract:SI - (match_operand 1 "ext_register_operand" "") + (match_operand 1 "ext_register_operand") (const_int 8) (const_int 8)) - (match_operand:QI 2 "general_operand" "")) + (match_operand:QI 2 "general_operand")) (const_int 0))) - (set (zero_extract:SI (match_operand 0 "ext_register_operand" "") + (set (zero_extract:SI (match_operand 0 "ext_register_operand") (const_int 8) (const_int 8)) (xor:SI @@ -8437,8 +8437,8 @@ ;; Negation instructions (define_expand "neg<mode>2" - [(set (match_operand:SDWIM 0 "nonimmediate_operand" "") - (neg:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand" "")))] + [(set (match_operand:SDWIM 0 "nonimmediate_operand") + (neg:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand")))] "" "ix86_expand_unary_operator (NEG, <MODE>mode, operands); DONE;") @@ -8524,8 +8524,8 @@ ;; Changing of sign for FP values is doable using integer unit too. (define_expand "<code><mode>2" - [(set (match_operand:X87MODEF 0 "register_operand" "") - (absneg:X87MODEF (match_operand:X87MODEF 1 "register_operand" "")))] + [(set (match_operand:X87MODEF 0 "register_operand") + (absneg:X87MODEF (match_operand:X87MODEF 1 "register_operand")))] "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)" "ix86_expand_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;") @@ -8551,14 +8551,14 @@ [(set (match_operand:X87MODEF 0 "register_operand" "=f,!r") (match_operator:X87MODEF 3 "absneg_operator" [(match_operand:X87MODEF 1 "register_operand" "0,0")])) - (use (match_operand 2 "" "")) + (use (match_operand 2)) (clobber (reg:CC FLAGS_REG))] "TARGET_80387 && !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)" "#") (define_expand "<code>tf2" - [(set (match_operand:TF 0 "register_operand" "") - (absneg:TF (match_operand:TF 1 "register_operand" "")))] + [(set (match_operand:TF 0 "register_operand") + (absneg:TF (match_operand:TF 1 "register_operand")))] "TARGET_SSE2" "ix86_expand_fp_absneg_operator (<CODE>, TFmode, operands); DONE;") @@ -8574,18 +8574,18 @@ ;; Splitters for fp abs and neg. (define_split - [(set (match_operand 0 "fp_register_operand" "") + [(set (match_operand 0 "fp_register_operand") (match_operator 1 "absneg_operator" [(match_dup 0)])) - (use (match_operand 2 "" "")) + (use (match_operand 2)) (clobber (reg:CC FLAGS_REG))] "reload_completed" [(set (match_dup 0) (match_op_dup 1 [(match_dup 0)]))]) (define_split - [(set (match_operand 0 "register_operand" "") + [(set (match_operand 0 "register_operand") (match_operator 3 "absneg_operator" - [(match_operand 1 "register_operand" "")])) - (use (match_operand 2 "nonimmediate_operand" "")) + [(match_operand 1 "register_operand")])) + (use (match_operand 2 "nonimmediate_operand")) (clobber (reg:CC FLAGS_REG))] "reload_completed && SSE_REG_P (operands[0])" [(set (match_dup 0) (match_dup 3))] @@ -8610,9 +8610,9 @@ }) (define_split - [(set (match_operand:SF 0 "register_operand" "") + [(set (match_operand:SF 0 "register_operand") (match_operator:SF 1 "absneg_operator" [(match_dup 0)])) - (use (match_operand:V4SF 2 "" "")) + (use (match_operand:V4SF 2)) (clobber (reg:CC FLAGS_REG))] "reload_completed" [(parallel [(set (match_dup 0) (match_dup 1)) @@ -8634,9 +8634,9 @@ }) (define_split - [(set (match_operand:DF 0 "register_operand" "") + [(set (match_operand:DF 0 "register_operand") (match_operator:DF 1 "absneg_operator" [(match_dup 0)])) - (use (match_operand 2 "" "")) + (use (match_operand 2)) (clobber (reg:CC FLAGS_REG))] "reload_completed" [(parallel [(set (match_dup 0) (match_dup 1)) @@ -8672,9 +8672,9 @@ }) (define_split - [(set (match_operand:XF 0 "register_operand" "") + [(set (match_operand:XF 0 "register_operand") (match_operator:XF 1 "absneg_operator" [(match_dup 0)])) - (use (match_operand 2 "" "")) + (use (match_operand 2)) (clobber (reg:CC FLAGS_REG))] "reload_completed" [(parallel [(set (match_dup 0) (match_dup 1)) @@ -8743,9 +8743,9 @@ (define_mode_attr CSGNVMODE [(SF "V4SF") (DF "V2DF") (TF "TF")]) (define_expand "copysign<mode>3" - [(match_operand:CSGNMODE 0 "register_operand" "") - (match_operand:CSGNMODE 1 "nonmemory_operand" "") - (match_operand:CSGNMODE 2 "register_operand" "")] + [(match_operand:CSGNMODE 0 "register_operand") + (match_operand:CSGNMODE 1 "nonmemory_operand") + (match_operand:CSGNMODE 2 "register_operand")] "(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) || (TARGET_SSE2 && (<MODE>mode == TFmode))" "ix86_expand_copysign (operands); DONE;") @@ -8778,14 +8778,14 @@ "#") (define_split - [(set (match_operand:CSGNMODE 0 "register_operand" "") + [(set (match_operand:CSGNMODE 0 "register_operand") (unspec:CSGNMODE - [(match_operand:CSGNMODE 2 "register_operand" "") - (match_operand:CSGNMODE 3 "register_operand" "") - (match_operand:<CSGNVMODE> 4 "" "") - (match_operand:<CSGNVMODE> 5 "" "")] + [(match_operand:CSGNMODE 2 "register_operand") + (match_operand:CSGNMODE 3 "register_operand") + (match_operand:<CSGNVMODE> 4) + (match_operand:<CSGNVMODE> 5)] UNSPEC_COPYSIGN)) - (clobber (match_scratch:<CSGNVMODE> 1 ""))] + (clobber (match_scratch:<CSGNVMODE> 1))] "((SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) || (TARGET_SSE2 && (<MODE>mode == TFmode))) && reload_completed" @@ -8795,8 +8795,8 @@ ;; One complement instructions (define_expand "one_cmpl<mode>2" - [(set (match_operand:SWIM 0 "nonimmediate_operand" "") - (not:SWIM (match_operand:SWIM 1 "nonimmediate_operand" "")))] + [(set (match_operand:SWIM 0 "nonimmediate_operand") + (not:SWIM (match_operand:SWIM 1 "nonimmediate_operand")))] "" "ix86_expand_unary_operator (NOT, <MODE>mode, operands); DONE;") @@ -8842,11 +8842,11 @@ (set_attr "mode" "<MODE>")]) (define_split - [(set (match_operand 0 "flags_reg_operand" "") + [(set (match_operand 0 "flags_reg_operand") (match_operator 2 "compare_operator" - [(not:SWI (match_operand:SWI 3 "nonimmediate_operand" "")) + [(not:SWI (match_operand:SWI 3 "nonimmediate_operand")) (const_int 0)])) - (set (match_operand:SWI 1 "nonimmediate_operand" "") + (set (match_operand:SWI 1 "nonimmediate_operand") (not:SWI (match_dup 3)))] "ix86_match_ccmode (insn, CCNOmode)" [(parallel [(set (match_dup 0) @@ -8869,11 +8869,11 @@ (set_attr "mode" "SI")]) (define_split - [(set (match_operand 0 "flags_reg_operand" "") + [(set (match_operand 0 "flags_reg_operand") (match_operator 2 "compare_operator" - [(not:SI (match_operand:SI 3 "register_operand" "")) + [(not:SI (match_operand:SI 3 "register_operand")) (const_int 0)])) - (set (match_operand:DI 1 "register_operand" "") + (set (match_operand:DI 1 "register_operand") (zero_extend:DI (not:SI (match_dup 3))))] "ix86_match_ccmode (insn, CCNOmode)" [(parallel [(set (match_dup 0) @@ -8907,9 +8907,9 @@ ;; than 31. (define_expand "ashl<mode>3" - [(set (match_operand:SDWIM 0 "<shift_operand>" "") - (ashift:SDWIM (match_operand:SDWIM 1 "<ashl_input_operand>" "") - (match_operand:QI 2 "nonmemory_operand" "")))] + [(set (match_operand:SDWIM 0 "<shift_operand>") + (ashift:SDWIM (match_operand:SDWIM 1 "<ashl_input_operand>") + (match_operand:QI 2 "nonmemory_operand")))] "" "ix86_expand_binary_operator (ASHIFT, <MODE>mode, operands); DONE;") @@ -8923,9 +8923,9 @@ [(set_attr "type" "multi")]) (define_split - [(set (match_operand:DWI 0 "register_operand" "") - (ashift:DWI (match_operand:DWI 1 "nonmemory_operand" "") - (match_operand:QI 2 "nonmemory_operand" ""))) + [(set (match_operand:DWI 0 "register_operand") + (ashift:DWI (match_operand:DWI 1 "nonmemory_operand") + (match_operand:QI 2 "nonmemory_operand"))) (clobber (reg:CC FLAGS_REG))] "(optimize && flag_peephole2) ? epilogue_completed : reload_completed" [(const_int 0)] @@ -8937,10 +8937,10 @@ (define_peephole2 [(match_scratch:DWIH 3 "r") - (parallel [(set (match_operand:<DWI> 0 "register_operand" "") + (parallel [(set (match_operand:<DWI> 0 "register_operand") (ashift:<DWI> - (match_operand:<DWI> 1 "nonmemory_operand" "") - (match_operand:QI 2 "nonmemory_operand" ""))) + (match_operand:<DWI> 1 "nonmemory_operand") + (match_operand:QI 2 "nonmemory_operand"))) (clobber (reg:CC FLAGS_REG))]) (match_dup 3)] "TARGET_CMOVE" @@ -8982,24 +8982,24 @@ (define_expand "x86_shift<mode>_adj_1" [(set (reg:CCZ FLAGS_REG) - (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "") + (compare:CCZ (and:QI (match_operand:QI 2 "register_operand") (match_dup 4)) (const_int 0))) - (set (match_operand:SWI48 0 "register_operand" "") + (set (match_operand:SWI48 0 "register_operand") (if_then_else:SWI48 (ne (reg:CCZ FLAGS_REG) (const_int 0)) - (match_operand:SWI48 1 "register_operand" "") + (match_operand:SWI48 1 "register_operand") (match_dup 0))) (set (match_dup 1) (if_then_else:SWI48 (ne (reg:CCZ FLAGS_REG) (const_int 0)) - (match_operand:SWI48 3 "register_operand" "") + (match_operand:SWI48 3 "register_operand") (match_dup 1)))] "TARGET_CMOVE" "operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));") (define_expand "x86_shift<mode>_adj_2" - [(use (match_operand:SWI48 0 "register_operand" "")) - (use (match_operand:SWI48 1 "register_operand" "")) - (use (match_operand:QI 2 "register_operand" ""))] + [(use (match_operand:SWI48 0 "register_operand")) + (use (match_operand:SWI48 1 "register_operand")) + (use (match_operand:QI 2 "register_operand"))] "" { rtx label = gen_label_rtx (); @@ -9094,8 +9094,8 @@ (eq_attr "alternative" "2") (const_string "ishiftx") (and (and (match_test "TARGET_DOUBLE_WITH_ADD") - (match_operand 0 "register_operand" "")) - (match_operand 2 "const1_operand" "")) + (match_operand 0 "register_operand")) + (match_operand 2 "const1_operand")) (const_string "alu") ] (const_string "ishift"))) @@ -9103,7 +9103,7 @@ (if_then_else (ior (eq_attr "type" "alu") (and (eq_attr "type" "ishift") - (and (match_operand 2 "const1_operand" "") + (and (match_operand 2 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)"))))) (const_string "0") @@ -9112,9 +9112,9 @@ ;; Convert shift to the shiftx pattern to avoid flags dependency. (define_split - [(set (match_operand:SWI48 0 "register_operand" "") - (ashift:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "") - (match_operand:QI 2 "register_operand" ""))) + [(set (match_operand:SWI48 0 "register_operand") + (ashift:SWI48 (match_operand:SWI48 1 "nonimmediate_operand") + (match_operand:QI 2 "register_operand"))) (clobber (reg:CC FLAGS_REG))] "TARGET_BMI2 && reload_completed" [(set (match_dup 0) @@ -9164,7 +9164,7 @@ (eq_attr "alternative" "2") (const_string "ishiftx") (and (match_test "TARGET_DOUBLE_WITH_ADD") - (match_operand 2 "const1_operand" "")) + (match_operand 2 "const1_operand")) (const_string "alu") ] (const_string "ishift"))) @@ -9172,7 +9172,7 @@ (if_then_else (ior (eq_attr "type" "alu") (and (eq_attr "type" "ishift") - (and (match_operand 2 "const1_operand" "") + (and (match_operand 2 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)"))))) (const_string "0") @@ -9181,10 +9181,10 @@ ;; Convert shift to the shiftx pattern to avoid flags dependency. (define_split - [(set (match_operand:DI 0 "register_operand" "") + [(set (match_operand:DI 0 "register_operand") (zero_extend:DI - (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "") - (match_operand:QI 2 "register_operand" "")))) + (ashift:SI (match_operand:SI 1 "nonimmediate_operand") + (match_operand:QI 2 "register_operand")))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && TARGET_BMI2 && reload_completed" [(set (match_dup 0) @@ -9219,8 +9219,8 @@ (cond [(eq_attr "alternative" "1") (const_string "lea") (and (and (match_test "TARGET_DOUBLE_WITH_ADD") - (match_operand 0 "register_operand" "")) - (match_operand 2 "const1_operand" "")) + (match_operand 0 "register_operand")) + (match_operand 2 "const1_operand")) (const_string "alu") ] (const_string "ishift"))) @@ -9228,7 +9228,7 @@ (if_then_else (ior (eq_attr "type" "alu") (and (eq_attr "type" "ishift") - (and (match_operand 2 "const1_operand" "") + (and (match_operand 2 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)"))))) (const_string "0") @@ -9277,8 +9277,8 @@ (cond [(eq_attr "alternative" "2") (const_string "lea") (and (and (match_test "TARGET_DOUBLE_WITH_ADD") - (match_operand 0 "register_operand" "")) - (match_operand 2 "const1_operand" "")) + (match_operand 0 "register_operand")) + (match_operand 2 "const1_operand")) (const_string "alu") ] (const_string "ishift"))) @@ -9286,7 +9286,7 @@ (if_then_else (ior (eq_attr "type" "alu") (and (eq_attr "type" "ishift") - (and (match_operand 2 "const1_operand" "") + (and (match_operand 2 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)"))))) (const_string "0") @@ -9320,8 +9320,8 @@ } [(set (attr "type") (cond [(and (and (match_test "TARGET_DOUBLE_WITH_ADD") - (match_operand 0 "register_operand" "")) - (match_operand 1 "const1_operand" "")) + (match_operand 0 "register_operand")) + (match_operand 1 "const1_operand")) (const_string "alu") ] (const_string "ishift1"))) @@ -9329,7 +9329,7 @@ (if_then_else (ior (eq_attr "type" "alu") (and (eq_attr "type" "ishift1") - (and (match_operand 1 "const1_operand" "") + (and (match_operand 1 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)"))))) (const_string "0") @@ -9338,9 +9338,9 @@ ;; Convert ashift to the lea pattern to avoid flags dependency. (define_split - [(set (match_operand 0 "register_operand" "") - (ashift (match_operand 1 "index_register_operand" "") - (match_operand:QI 2 "const_int_operand" ""))) + [(set (match_operand 0 "register_operand") + (ashift (match_operand 1 "index_register_operand") + (match_operand:QI 2 "const_int_operand"))) (clobber (reg:CC FLAGS_REG))] "GET_MODE (operands[0]) == GET_MODE (operands[1]) && reload_completed @@ -9367,10 +9367,10 @@ ;; Convert ashift to the lea pattern to avoid flags dependency. (define_split - [(set (match_operand:DI 0 "register_operand" "") + [(set (match_operand:DI 0 "register_operand") (zero_extend:DI - (ashift:SI (match_operand:SI 1 "index_register_operand" "") - (match_operand:QI 2 "const_int_operand" "")))) + (ashift:SI (match_operand:SI 1 "index_register_operand") + (match_operand:QI 2 "const_int_operand")))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && reload_completed && true_regnum (operands[0]) != true_regnum (operands[1])" @@ -9416,8 +9416,8 @@ } [(set (attr "type") (cond [(and (and (match_test "TARGET_DOUBLE_WITH_ADD") - (match_operand 0 "register_operand" "")) - (match_operand 2 "const1_operand" "")) + (match_operand 0 "register_operand")) + (match_operand 2 "const1_operand")) (const_string "alu") ] (const_string "ishift"))) @@ -9425,7 +9425,7 @@ (if_then_else (ior (eq_attr "type" "alu") (and (eq_attr "type" "ishift") - (and (match_operand 2 "const1_operand" "") + (and (match_operand 2 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)"))))) (const_string "0") @@ -9465,7 +9465,7 @@ } [(set (attr "type") (cond [(and (match_test "TARGET_DOUBLE_WITH_ADD") - (match_operand 2 "const1_operand" "")) + (match_operand 2 "const1_operand")) (const_string "alu") ] (const_string "ishift"))) @@ -9473,7 +9473,7 @@ (if_then_else (ior (eq_attr "type" "alu") (and (eq_attr "type" "ishift") - (and (match_operand 2 "const1_operand" "") + (and (match_operand 2 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)"))))) (const_string "0") @@ -9510,8 +9510,8 @@ } [(set (attr "type") (cond [(and (and (match_test "TARGET_DOUBLE_WITH_ADD") - (match_operand 0 "register_operand" "")) - (match_operand 2 "const1_operand" "")) + (match_operand 0 "register_operand")) + (match_operand 2 "const1_operand")) (const_string "alu") ] (const_string "ishift"))) @@ -9519,7 +9519,7 @@ (if_then_else (ior (eq_attr "type" "alu") (and (eq_attr "type" "ishift") - (and (match_operand 2 "const1_operand" "") + (and (match_operand 2 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)"))))) (const_string "0") @@ -9529,9 +9529,9 @@ ;; See comment above `ashl<mode>3' about how this works. (define_expand "<shift_insn><mode>3" - [(set (match_operand:SDWIM 0 "<shift_operand>" "") - (any_shiftrt:SDWIM (match_operand:SDWIM 1 "<shift_operand>" "") - (match_operand:QI 2 "nonmemory_operand" "")))] + [(set (match_operand:SDWIM 0 "<shift_operand>") + (any_shiftrt:SDWIM (match_operand:SDWIM 1 "<shift_operand>") + (match_operand:QI 2 "nonmemory_operand")))] "" "ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;") @@ -9580,10 +9580,10 @@ (define_peephole2 [(match_scratch:DWIH 3 "r") - (parallel [(set (match_operand:<DWI> 0 "register_operand" "") + (parallel [(set (match_operand:<DWI> 0 "register_operand") (any_shiftrt:<DWI> - (match_operand:<DWI> 1 "register_operand" "") - (match_operand:QI 2 "nonmemory_operand" ""))) + (match_operand:<DWI> 1 "register_operand") + (match_operand:QI 2 "nonmemory_operand"))) (clobber (reg:CC FLAGS_REG))]) (match_dup 3)] "TARGET_CMOVE" @@ -9626,7 +9626,7 @@ (define_insn "ashrdi3_cvt" [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm") (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0") - (match_operand:QI 2 "const_int_operand" ""))) + (match_operand:QI 2 "const_int_operand"))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && INTVAL (operands[2]) == 63 && (TARGET_USE_CLTD || optimize_function_for_size_p (cfun)) @@ -9643,7 +9643,7 @@ (define_insn "ashrsi3_cvt" [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm") (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0") - (match_operand:QI 2 "const_int_operand" ""))) + (match_operand:QI 2 "const_int_operand"))) (clobber (reg:CC FLAGS_REG))] "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_function_for_size_p (cfun)) @@ -9661,7 +9661,7 @@ [(set (match_operand:DI 0 "register_operand" "=*d,r") (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0") - (match_operand:QI 2 "const_int_operand" "")))) + (match_operand:QI 2 "const_int_operand")))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_function_for_size_p (cfun)) @@ -9676,9 +9676,9 @@ (set_attr "mode" "SI")]) (define_expand "x86_shift<mode>_adj_3" - [(use (match_operand:SWI48 0 "register_operand" "")) - (use (match_operand:SWI48 1 "register_operand" "")) - (use (match_operand:QI 2 "register_operand" ""))] + [(use (match_operand:SWI48 0 "register_operand")) + (use (match_operand:SWI48 1 "register_operand")) + (use (match_operand:QI 2 "register_operand"))] "" { rtx label = gen_label_rtx (); @@ -9738,7 +9738,7 @@ (set_attr "type" "ishift,ishiftx") (set (attr "length_immediate") (if_then_else - (and (match_operand 2 "const1_operand" "") + (and (match_operand 2 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)"))) (const_string "0") @@ -9747,9 +9747,9 @@ ;; Convert shift to the shiftx pattern to avoid flags dependency. (define_split - [(set (match_operand:SWI48 0 "register_operand" "") - (any_shiftrt:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "") - (match_operand:QI 2 "register_operand" ""))) + [(set (match_operand:SWI48 0 "register_operand") + (any_shiftrt:SWI48 (match_operand:SWI48 1 "nonimmediate_operand") + (match_operand:QI 2 "register_operand"))) (clobber (reg:CC FLAGS_REG))] "TARGET_BMI2 && reload_completed" [(set (match_dup 0) @@ -9791,7 +9791,7 @@ (set_attr "type" "ishift,ishiftx") (set (attr "length_immediate") (if_then_else - (and (match_operand 2 "const1_operand" "") + (and (match_operand 2 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)"))) (const_string "0") @@ -9800,10 +9800,10 @@ ;; Convert shift to the shiftx pattern to avoid flags dependency. (define_split - [(set (match_operand:DI 0 "register_operand" "") + [(set (match_operand:DI 0 "register_operand") (zero_extend:DI - (any_shiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "") - (match_operand:QI 2 "register_operand" "")))) + (any_shiftrt:SI (match_operand:SI 1 "nonimmediate_operand") + (match_operand:QI 2 "register_operand")))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && TARGET_BMI2 && reload_completed" [(set (match_dup 0) @@ -9827,7 +9827,7 @@ [(set_attr "type" "ishift") (set (attr "length_immediate") (if_then_else - (and (match_operand 2 "const1_operand" "") + (and (match_operand 2 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)"))) (const_string "0") @@ -9853,7 +9853,7 @@ [(set_attr "type" "ishift1") (set (attr "length_immediate") (if_then_else - (and (match_operand 1 "const1_operand" "") + (and (match_operand 1 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)"))) (const_string "0") @@ -9888,7 +9888,7 @@ [(set_attr "type" "ishift") (set (attr "length_immediate") (if_then_else - (and (match_operand 2 "const1_operand" "") + (and (match_operand 2 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)"))) (const_string "0") @@ -9920,7 +9920,7 @@ [(set_attr "type" "ishift") (set (attr "length_immediate") (if_then_else - (and (match_operand 2 "const1_operand" "") + (and (match_operand 2 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)"))) (const_string "0") @@ -9950,7 +9950,7 @@ [(set_attr "type" "ishift") (set (attr "length_immediate") (if_then_else - (and (match_operand 2 "const1_operand" "") + (and (match_operand 2 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)"))) (const_string "0") @@ -9960,9 +9960,9 @@ ;; Rotate instructions (define_expand "<rotate_insn>ti3" - [(set (match_operand:TI 0 "register_operand" "") - (any_rotate:TI (match_operand:TI 1 "register_operand" "") - (match_operand:QI 2 "nonmemory_operand" "")))] + [(set (match_operand:TI 0 "register_operand") + (any_rotate:TI (match_operand:TI 1 "register_operand") + (match_operand:QI 2 "nonmemory_operand")))] "TARGET_64BIT" { if (const_1_to_63_operand (operands[2], VOIDmode)) @@ -9975,9 +9975,9 @@ }) (define_expand "<rotate_insn>di3" - [(set (match_operand:DI 0 "shiftdi_operand" "") - (any_rotate:DI (match_operand:DI 1 "shiftdi_operand" "") - (match_operand:QI 2 "nonmemory_operand" "")))] + [(set (match_operand:DI 0 "shiftdi_operand") + (any_rotate:DI (match_operand:DI 1 "shiftdi_operand") + (match_operand:QI 2 "nonmemory_operand")))] "" { if (TARGET_64BIT) @@ -9992,9 +9992,9 @@ }) (define_expand "<rotate_insn><mode>3" - [(set (match_operand:SWIM124 0 "nonimmediate_operand" "") - (any_rotate:SWIM124 (match_operand:SWIM124 1 "nonimmediate_operand" "") - (match_operand:QI 2 "nonmemory_operand" "")))] + [(set (match_operand:SWIM124 0 "nonimmediate_operand") + (any_rotate:SWIM124 (match_operand:SWIM124 1 "nonimmediate_operand") + (match_operand:QI 2 "nonmemory_operand")))] "" "ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;") @@ -10119,7 +10119,7 @@ (set (attr "length_immediate") (if_then_else (and (eq_attr "type" "rotate") - (and (match_operand 2 "const1_operand" "") + (and (match_operand 2 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)")))) (const_string "0") @@ -10128,9 +10128,9 @@ ;; Convert rotate to the rotatex pattern to avoid flags dependency. (define_split - [(set (match_operand:SWI48 0 "register_operand" "") - (rotate:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "") - (match_operand:QI 2 "immediate_operand" ""))) + [(set (match_operand:SWI48 0 "register_operand") + (rotate:SWI48 (match_operand:SWI48 1 "nonimmediate_operand") + (match_operand:QI 2 "immediate_operand"))) (clobber (reg:CC FLAGS_REG))] "TARGET_BMI2 && reload_completed" [(set (match_dup 0) @@ -10141,9 +10141,9 @@ }) (define_split - [(set (match_operand:SWI48 0 "register_operand" "") - (rotatert:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "") - (match_operand:QI 2 "immediate_operand" ""))) + [(set (match_operand:SWI48 0 "register_operand") + (rotatert:SWI48 (match_operand:SWI48 1 "nonimmediate_operand") + (match_operand:QI 2 "immediate_operand"))) (clobber (reg:CC FLAGS_REG))] "TARGET_BMI2 && reload_completed" [(set (match_dup 0) @@ -10185,7 +10185,7 @@ (set (attr "length_immediate") (if_then_else (and (eq_attr "type" "rotate") - (and (match_operand 2 "const1_operand" "") + (and (match_operand 2 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)")))) (const_string "0") @@ -10194,10 +10194,10 @@ ;; Convert rotate to the rotatex pattern to avoid flags dependency. (define_split - [(set (match_operand:DI 0 "register_operand" "") + [(set (match_operand:DI 0 "register_operand") (zero_extend:DI - (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "") - (match_operand:QI 2 "immediate_operand" "")))) + (rotate:SI (match_operand:SI 1 "nonimmediate_operand") + (match_operand:QI 2 "immediate_operand")))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && TARGET_BMI2 && reload_completed" [(set (match_dup 0) @@ -10208,10 +10208,10 @@ }) (define_split - [(set (match_operand:DI 0 "register_operand" "") + [(set (match_operand:DI 0 "register_operand") (zero_extend:DI - (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "") - (match_operand:QI 2 "immediate_operand" "")))) + (rotatert:SI (match_operand:SI 1 "nonimmediate_operand") + (match_operand:QI 2 "immediate_operand")))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && TARGET_BMI2 && reload_completed" [(set (match_dup 0) @@ -10233,7 +10233,7 @@ [(set_attr "type" "rotate") (set (attr "length_immediate") (if_then_else - (and (match_operand 2 "const1_operand" "") + (and (match_operand 2 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)"))) (const_string "0") @@ -10259,7 +10259,7 @@ [(set_attr "type" "rotate1") (set (attr "length_immediate") (if_then_else - (and (match_operand 1 "const1_operand" "") + (and (match_operand 1 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)"))) (const_string "0") @@ -10267,7 +10267,7 @@ (set_attr "mode" "QI")]) (define_split - [(set (match_operand:HI 0 "register_operand" "") + [(set (match_operand:HI 0 "register_operand") (any_rotate:HI (match_dup 0) (const_int 8))) (clobber (reg:CC FLAGS_REG))] "reload_completed @@ -10279,10 +10279,10 @@ ;; Bit set / bit test instructions (define_expand "extv" - [(set (match_operand:SI 0 "register_operand" "") - (sign_extract:SI (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "const8_operand" "") - (match_operand:SI 3 "const8_operand" "")))] + [(set (match_operand:SI 0 "register_operand") + (sign_extract:SI (match_operand:SI 1 "register_operand") + (match_operand:SI 2 "const8_operand") + (match_operand:SI 3 "const8_operand")))] "" { /* Handle extractions from %ah et al. */ @@ -10296,10 +10296,10 @@ }) (define_expand "extzv" - [(set (match_operand:SI 0 "register_operand" "") - (zero_extract:SI (match_operand 1 "ext_register_operand" "") - (match_operand:SI 2 "const8_operand" "") - (match_operand:SI 3 "const8_operand" "")))] + [(set (match_operand:SI 0 "register_operand") + (zero_extract:SI (match_operand 1 "ext_register_operand") + (match_operand:SI 2 "const8_operand") + (match_operand:SI 3 "const8_operand")))] "" { /* Handle extractions from %ah et al. */ @@ -10313,10 +10313,10 @@ }) (define_expand "insv" - [(set (zero_extract (match_operand 0 "register_operand" "") - (match_operand 1 "const_int_operand" "") - (match_operand 2 "const_int_operand" "")) - (match_operand 3 "register_operand" ""))] + [(set (zero_extract (match_operand 0 "register_operand") + (match_operand 1 "const_int_operand") + (match_operand 2 "const_int_operand")) + (match_operand 3 "register_operand"))] "" { rtx (*gen_mov_insv_1) (rtx, rtx); @@ -10356,7 +10356,7 @@ (define_insn "*btsq" [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r") (const_int 1) - (match_operand:DI 1 "const_0_to_63_operand" "")) + (match_operand:DI 1 "const_0_to_63_operand")) (const_int 1)) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && (TARGET_USE_BT || reload_completed)" @@ -10368,7 +10368,7 @@ (define_insn "*btrq" [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r") (const_int 1) - (match_operand:DI 1 "const_0_to_63_operand" "")) + (match_operand:DI 1 "const_0_to_63_operand")) (const_int 0)) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && (TARGET_USE_BT || reload_completed)" @@ -10380,7 +10380,7 @@ (define_insn "*btcq" [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r") (const_int 1) - (match_operand:DI 1 "const_0_to_63_operand" "")) + (match_operand:DI 1 "const_0_to_63_operand")) (not:DI (zero_extract:DI (match_dup 0) (const_int 1) (match_dup 1)))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && (TARGET_USE_BT || reload_completed)" @@ -10394,9 +10394,9 @@ (define_peephole2 [(match_scratch:DI 2 "r") (parallel [(set (zero_extract:DI - (match_operand:DI 0 "register_operand" "") + (match_operand:DI 0 "register_operand") (const_int 1) - (match_operand:DI 1 "const_0_to_63_operand" "")) + (match_operand:DI 1 "const_0_to_63_operand")) (const_int 1)) (clobber (reg:CC FLAGS_REG))])] "TARGET_64BIT && !TARGET_USE_BT" @@ -10426,9 +10426,9 @@ (define_peephole2 [(match_scratch:DI 2 "r") (parallel [(set (zero_extract:DI - (match_operand:DI 0 "register_operand" "") + (match_operand:DI 0 "register_operand") (const_int 1) - (match_operand:DI 1 "const_0_to_63_operand" "")) + (match_operand:DI 1 "const_0_to_63_operand")) (const_int 0)) (clobber (reg:CC FLAGS_REG))])] "TARGET_64BIT && !TARGET_USE_BT" @@ -10458,9 +10458,9 @@ (define_peephole2 [(match_scratch:DI 2 "r") (parallel [(set (zero_extract:DI - (match_operand:DI 0 "register_operand" "") + (match_operand:DI 0 "register_operand") (const_int 1) - (match_operand:DI 1 "const_0_to_63_operand" "")) + (match_operand:DI 1 "const_0_to_63_operand")) (not:DI (zero_extract:DI (match_dup 0) (const_int 1) (match_dup 1)))) (clobber (reg:CC FLAGS_REG))])] @@ -10580,7 +10580,7 @@ ;; sete %al (define_split - [(set (match_operand:QI 0 "nonimmediate_operand" "") + [(set (match_operand:QI 0 "nonimmediate_operand") (ne:QI (match_operator 1 "ix86_comparison_operator" [(reg FLAGS_REG) (const_int 0)]) (const_int 0)))] @@ -10589,7 +10589,7 @@ "PUT_MODE (operands[1], QImode);") (define_split - [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "")) + [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand")) (ne:QI (match_operator 1 "ix86_comparison_operator" [(reg FLAGS_REG) (const_int 0)]) (const_int 0)))] @@ -10598,7 +10598,7 @@ "PUT_MODE (operands[1], QImode);") (define_split - [(set (match_operand:QI 0 "nonimmediate_operand" "") + [(set (match_operand:QI 0 "nonimmediate_operand") (eq:QI (match_operator 1 "ix86_comparison_operator" [(reg FLAGS_REG) (const_int 0)]) (const_int 0)))] @@ -10618,7 +10618,7 @@ }) (define_split - [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "")) + [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand")) (eq:QI (match_operator 1 "ix86_comparison_operator" [(reg FLAGS_REG) (const_int 0)]) (const_int 0)))] @@ -10664,7 +10664,7 @@ [(set (pc) (if_then_else (match_operator 1 "ix86_comparison_operator" [(reg FLAGS_REG) (const_int 0)]) - (label_ref (match_operand 0 "" "")) + (label_ref (match_operand 0)) (pc)))] "" "%+j%C1\t%l0" @@ -10683,7 +10683,7 @@ (if_then_else (match_operator 1 "ix86_comparison_operator" [(reg FLAGS_REG) (const_int 0)]) (pc) - (label_ref (match_operand 0 "" ""))))] + (label_ref (match_operand 0))))] "" "%+j%c1\t%l0" [(set_attr "type" "ibr") @@ -10709,7 +10709,7 @@ (if_then_else (ne (match_operator 0 "ix86_comparison_operator" [(reg FLAGS_REG) (const_int 0)]) (const_int 0)) - (label_ref (match_operand 1 "" "")) + (label_ref (match_operand 1)) (pc)))] "" [(set (pc) @@ -10723,7 +10723,7 @@ (if_then_else (eq (match_operator 0 "ix86_comparison_operator" [(reg FLAGS_REG) (const_int 0)]) (const_int 0)) - (label_ref (match_operand 1 "" "")) + (label_ref (match_operand 1)) (pc)))] "" [(set (pc) @@ -10757,7 +10757,7 @@ (zero_extend:SI (match_operand:QI 2 "register_operand" "r"))) (const_int 0)]) - (label_ref (match_operand 3 "" "")) + (label_ref (match_operand 3)) (pc))) (clobber (reg:CC FLAGS_REG))] "TARGET_USE_BT || optimize_function_for_size_p (cfun)" @@ -10791,7 +10791,7 @@ (and:SI (match_operand:SI 2 "register_operand" "r") (match_operand:SI 3 "const_int_operand" "n")))]) - (label_ref (match_operand 4 "" "")) + (label_ref (match_operand 4)) (pc))) (clobber (reg:CC FLAGS_REG))] "(TARGET_USE_BT || optimize_function_for_size_p (cfun)) @@ -10825,7 +10825,7 @@ (match_operand:QI 2 "register_operand" "r")) (const_int 1)) (const_int 0)]) - (label_ref (match_operand 3 "" "")) + (label_ref (match_operand 3)) (pc))) (clobber (reg:CC FLAGS_REG))] "TARGET_USE_BT || optimize_function_for_size_p (cfun)" @@ -10862,7 +10862,7 @@ (match_operand:SI 3 "const_int_operand" "n")) 0)) (const_int 1)) (const_int 0)]) - (label_ref (match_operand 4 "" "")) + (label_ref (match_operand 4)) (pc))) (clobber (reg:CC FLAGS_REG))] "(TARGET_USE_BT || optimize_function_for_size_p (cfun)) @@ -10890,7 +10890,7 @@ (if_then_else (match_operator 0 "ix86_fp_comparison_operator" [(match_operand 1 "register_operand" "f") (match_operand 2 "nonimmediate_operand" "fm")]) - (label_ref (match_operand 3 "" "")) + (label_ref (match_operand 3)) (pc))) (clobber (reg:CCFP FPSR_REG)) (clobber (reg:CCFP FLAGS_REG)) @@ -10909,7 +10909,7 @@ [(match_operand 1 "register_operand" "f") (match_operand 2 "nonimmediate_operand" "fm")]) (pc) - (label_ref (match_operand 3 "" "")))) + (label_ref (match_operand 3)))) (clobber (reg:CCFP FPSR_REG)) (clobber (reg:CCFP FLAGS_REG)) (clobber (match_scratch:HI 4 "=a"))] @@ -10926,7 +10926,7 @@ (if_then_else (match_operator 0 "ix86_fp_comparison_operator" [(match_operand 1 "register_operand" "f") (match_operand 2 "register_operand" "f")]) - (label_ref (match_operand 3 "" "")) + (label_ref (match_operand 3)) (pc))) (clobber (reg:CCFP FPSR_REG)) (clobber (reg:CCFP FLAGS_REG)) @@ -10942,7 +10942,7 @@ [(match_operand 1 "register_operand" "f") (match_operand 2 "register_operand" "f")]) (pc) - (label_ref (match_operand 3 "" "")))) + (label_ref (match_operand 3)))) (clobber (reg:CCFP FPSR_REG)) (clobber (reg:CCFP FLAGS_REG)) (clobber (match_scratch:HI 4 "=a"))] @@ -10955,8 +10955,8 @@ [(set (pc) (if_then_else (match_operator 0 "ix86_fp_comparison_operator" [(match_operand 1 "register_operand" "f") - (match_operand 2 "const0_operand" "")]) - (label_ref (match_operand 3 "" "")) + (match_operand 2 "const0_operand")]) + (label_ref (match_operand 3)) (pc))) (clobber (reg:CCFP FPSR_REG)) (clobber (reg:CCFP FLAGS_REG)) @@ -10971,10 +10971,10 @@ (define_split [(set (pc) (if_then_else (match_operator 0 "ix86_fp_comparison_operator" - [(match_operand 1 "register_operand" "") - (match_operand 2 "nonimmediate_operand" "")]) - (match_operand 3 "" "") - (match_operand 4 "" ""))) + [(match_operand 1 "register_operand") + (match_operand 2 "nonimmediate_operand")]) + (match_operand 3) + (match_operand 4))) (clobber (reg:CCFP FPSR_REG)) (clobber (reg:CCFP FLAGS_REG))] "reload_completed" @@ -10988,10 +10988,10 @@ (define_split [(set (pc) (if_then_else (match_operator 0 "ix86_fp_comparison_operator" - [(match_operand 1 "register_operand" "") - (match_operand 2 "general_operand" "")]) - (match_operand 3 "" "") - (match_operand 4 "" ""))) + [(match_operand 1 "register_operand") + (match_operand 2 "general_operand")]) + (match_operand 3) + (match_operand 4))) (clobber (reg:CCFP FPSR_REG)) (clobber (reg:CCFP FLAGS_REG)) (clobber (match_scratch:HI 5 "=a"))] @@ -11015,7 +11015,7 @@ [(match_operator 1 "float_operator" [(match_operand:SWI24 2 "nonimmediate_operand" "m,?r")]) (match_operand 3 "register_operand" "f,f")]) - (label_ref (match_operand 4 "" "")) + (label_ref (match_operand 4)) (pc))) (clobber (reg:CCFP FPSR_REG)) (clobber (reg:CCFP FLAGS_REG)) @@ -11032,10 +11032,10 @@ (if_then_else (match_operator 0 "ix86_swapped_fp_comparison_operator" [(match_operator 1 "float_operator" - [(match_operand:SWI24 2 "memory_operand" "")]) - (match_operand 3 "register_operand" "")]) - (match_operand 4 "" "") - (match_operand 5 "" ""))) + [(match_operand:SWI24 2 "memory_operand")]) + (match_operand 3 "register_operand")]) + (match_operand 4) + (match_operand 5))) (clobber (reg:CCFP FPSR_REG)) (clobber (reg:CCFP FLAGS_REG)) (clobber (match_scratch:HI 6 "=a"))] @@ -11056,10 +11056,10 @@ (if_then_else (match_operator 0 "ix86_swapped_fp_comparison_operator" [(match_operator 1 "float_operator" - [(match_operand:SWI24 2 "register_operand" "")]) - (match_operand 3 "register_operand" "")]) - (match_operand 4 "" "") - (match_operand 5 "" ""))) + [(match_operand:SWI24 2 "register_operand")]) + (match_operand 3 "register_operand")]) + (match_operand 4) + (match_operand 5))) (clobber (reg:CCFP FPSR_REG)) (clobber (reg:CCFP FLAGS_REG)) (clobber (match_scratch:HI 6 "=a"))] @@ -11079,7 +11079,7 @@ (define_insn "jump" [(set (pc) - (label_ref (match_operand 0 "" "")))] + (label_ref (match_operand 0)))] "" "jmp\t%l0" [(set_attr "type" "ibr") @@ -11093,7 +11093,7 @@ (set_attr "modrm" "0")]) (define_expand "indirect_jump" - [(set (pc) (match_operand 0 "indirect_branch_operand" ""))] + [(set (pc) (match_operand 0 "indirect_branch_operand"))] "" { if (TARGET_X32) @@ -11108,8 +11108,8 @@ (set_attr "length_immediate" "0")]) (define_expand "tablejump" - [(parallel [(set (pc) (match_operand 0 "indirect_branch_operand" "")) - (use (label_ref (match_operand 1 "" "")))])] + [(parallel [(set (pc) (match_operand 0 "indirect_branch_operand")) + (use (label_ref (match_operand 1)))])] "" { /* In PIC mode, the table entries are stored GOT (32-bit) or PC (64-bit) @@ -11150,7 +11150,7 @@ (define_insn "*tablejump_1" [(set (pc) (match_operand:W 0 "indirect_branch_operand" "rw")) - (use (label_ref (match_operand 1 "" "")))] + (use (label_ref (match_operand 1)))] "" "jmp\t%A0" [(set_attr "type" "ibr") @@ -11159,11 +11159,11 @@ ;; Convert setcc + movzbl to xor + setcc if operands don't overlap. (define_peephole2 - [(set (reg FLAGS_REG) (match_operand 0 "" "")) - (set (match_operand:QI 1 "register_operand" "") + [(set (reg FLAGS_REG) (match_operand 0)) + (set (match_operand:QI 1 "register_operand") (match_operator:QI 2 "ix86_comparison_operator" [(reg FLAGS_REG) (const_int 0)])) - (set (match_operand 3 "q_regs_operand" "") + (set (match_operand 3 "q_regs_operand") (zero_extend (match_dup 1)))] "(peep2_reg_dead_p (3, operands[1]) || operands_match_p (operands[1], operands[3])) @@ -11178,12 +11178,12 @@ }) (define_peephole2 - [(parallel [(set (reg FLAGS_REG) (match_operand 0 "" "")) - (match_operand 4 "" "")]) - (set (match_operand:QI 1 "register_operand" "") + [(parallel [(set (reg FLAGS_REG) (match_operand 0)) + (match_operand 4)]) + (set (match_operand:QI 1 "register_operand") (match_operator:QI 2 "ix86_comparison_operator" [(reg FLAGS_REG) (const_int 0)])) - (set (match_operand 3 "q_regs_operand" "") + (set (match_operand 3 "q_regs_operand") (zero_extend (match_dup 1)))] "(peep2_reg_dead_p (3, operands[1]) || operands_match_p (operands[1], operands[3])) @@ -11201,11 +11201,11 @@ ;; Similar, but match zero extend with andsi3. (define_peephole2 - [(set (reg FLAGS_REG) (match_operand 0 "" "")) - (set (match_operand:QI 1 "register_operand" "") + [(set (reg FLAGS_REG) (match_operand 0)) + (set (match_operand:QI 1 "register_operand") (match_operator:QI 2 "ix86_comparison_operator" [(reg FLAGS_REG) (const_int 0)])) - (parallel [(set (match_operand:SI 3 "q_regs_operand" "") + (parallel [(set (match_operand:SI 3 "q_regs_operand") (and:SI (match_dup 3) (const_int 255))) (clobber (reg:CC FLAGS_REG))])] "REGNO (operands[1]) == REGNO (operands[3]) @@ -11220,12 +11220,12 @@ }) (define_peephole2 - [(parallel [(set (reg FLAGS_REG) (match_operand 0 "" "")) - (match_operand 4 "" "")]) - (set (match_operand:QI 1 "register_operand" "") + [(parallel [(set (reg FLAGS_REG) (match_operand 0)) + (match_operand 4)]) + (set (match_operand:QI 1 "register_operand") (match_operator:QI 2 "ix86_comparison_operator" [(reg FLAGS_REG) (const_int 0)])) - (parallel [(set (match_operand 3 "q_regs_operand" "") + (parallel [(set (match_operand 3 "q_regs_operand") (zero_extend (match_dup 1))) (clobber (reg:CC FLAGS_REG))])] "(peep2_reg_dead_p (3, operands[1]) @@ -11257,9 +11257,9 @@ ;; Call subroutine returning no value. (define_expand "call" - [(call (match_operand:QI 0 "" "") - (match_operand 1 "" "")) - (use (match_operand 2 "" ""))] + [(call (match_operand:QI 0) + (match_operand 1)) + (use (match_operand 2))] "" { ix86_expand_call (NULL, operands[0], operands[1], @@ -11268,9 +11268,9 @@ }) (define_expand "sibcall" - [(call (match_operand:QI 0 "" "") - (match_operand 1 "" "")) - (use (match_operand 2 "" ""))] + [(call (match_operand:QI 0) + (match_operand 1)) + (use (match_operand 2))] "" { ix86_expand_call (NULL, operands[0], operands[1], @@ -11280,8 +11280,8 @@ (define_insn_and_split "*call_vzeroupper" [(call (mem:QI (match_operand:W 0 "call_insn_operand" "<c>zw")) - (match_operand 1 "" "")) - (unspec [(match_operand 2 "const_int_operand" "")] + (match_operand 1)) + (unspec [(match_operand 2 "const_int_operand")] UNSPEC_CALL_NEEDS_VZEROUPPER)] "TARGET_VZEROUPPER && !SIBLING_CALL_P (insn)" "#" @@ -11292,14 +11292,14 @@ (define_insn "*call" [(call (mem:QI (match_operand:W 0 "call_insn_operand" "<c>zw")) - (match_operand 1 "" ""))] + (match_operand 1))] "!SIBLING_CALL_P (insn)" "* return ix86_output_call_insn (insn, operands[0]);" [(set_attr "type" "call")]) (define_insn_and_split "*call_rex64_ms_sysv_vzeroupper" [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rzw")) - (match_operand 1 "" "")) + (match_operand 1)) (unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL) (clobber (reg:TI XMM6_REG)) (clobber (reg:TI XMM7_REG)) @@ -11313,7 +11313,7 @@ (clobber (reg:TI XMM15_REG)) (clobber (reg:DI SI_REG)) (clobber (reg:DI DI_REG)) - (unspec [(match_operand 2 "const_int_operand" "")] + (unspec [(match_operand 2 "const_int_operand")] UNSPEC_CALL_NEEDS_VZEROUPPER)] "TARGET_VZEROUPPER && TARGET_64BIT && !SIBLING_CALL_P (insn)" "#" @@ -11324,7 +11324,7 @@ (define_insn "*call_rex64_ms_sysv" [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rzw")) - (match_operand 1 "" "")) + (match_operand 1)) (unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL) (clobber (reg:TI XMM6_REG)) (clobber (reg:TI XMM7_REG)) @@ -11344,8 +11344,8 @@ (define_insn_and_split "*sibcall_vzeroupper" [(call (mem:QI (match_operand:W 0 "sibcall_insn_operand" "Uz")) - (match_operand 1 "" "")) - (unspec [(match_operand 2 "const_int_operand" "")] + (match_operand 1)) + (unspec [(match_operand 2 "const_int_operand")] UNSPEC_CALL_NEEDS_VZEROUPPER)] "TARGET_VZEROUPPER && SIBLING_CALL_P (insn)" "#" @@ -11356,17 +11356,17 @@ (define_insn "*sibcall" [(call (mem:QI (match_operand:W 0 "sibcall_insn_operand" "Uz")) - (match_operand 1 "" ""))] + (match_operand 1))] "SIBLING_CALL_P (insn)" "* return ix86_output_call_insn (insn, operands[0]);" [(set_attr "type" "call")]) (define_expand "call_pop" - [(parallel [(call (match_operand:QI 0 "" "") - (match_operand:SI 1 "" "")) + [(parallel [(call (match_operand:QI 0) + (match_operand:SI 1)) (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) - (match_operand:SI 3 "" "")))])] + (match_operand:SI 3)))])] "!TARGET_64BIT" { ix86_expand_call (NULL, operands[0], operands[1], @@ -11376,11 +11376,11 @@ (define_insn_and_split "*call_pop_vzeroupper" [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lzm")) - (match_operand 1 "" "")) + (match_operand 1)) (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_operand:SI 2 "immediate_operand" "i"))) - (unspec [(match_operand 3 "const_int_operand" "")] + (unspec [(match_operand 3 "const_int_operand")] UNSPEC_CALL_NEEDS_VZEROUPPER)] "TARGET_VZEROUPPER && !TARGET_64BIT && !SIBLING_CALL_P (insn)" "#" @@ -11391,7 +11391,7 @@ (define_insn "*call_pop" [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lzm")) - (match_operand 1 "" "")) + (match_operand 1)) (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_operand:SI 2 "immediate_operand" "i")))] @@ -11401,11 +11401,11 @@ (define_insn_and_split "*sibcall_pop_vzeroupper" [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "Uz")) - (match_operand 1 "" "")) + (match_operand 1)) (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_operand:SI 2 "immediate_operand" "i"))) - (unspec [(match_operand 3 "const_int_operand" "")] + (unspec [(match_operand 3 "const_int_operand")] UNSPEC_CALL_NEEDS_VZEROUPPER)] "TARGET_VZEROUPPER && !TARGET_64BIT && SIBLING_CALL_P (insn)" "#" @@ -11416,7 +11416,7 @@ (define_insn "*sibcall_pop" [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "Uz")) - (match_operand 1 "" "")) + (match_operand 1)) (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_operand:SI 2 "immediate_operand" "i")))] @@ -11427,10 +11427,10 @@ ;; Call subroutine, returning value in operand 0 (define_expand "call_value" - [(set (match_operand 0 "" "") - (call (match_operand:QI 1 "" "") - (match_operand 2 "" ""))) - (use (match_operand 3 "" ""))] + [(set (match_operand 0) + (call (match_operand:QI 1) + (match_operand 2))) + (use (match_operand 3))] "" { ix86_expand_call (operands[0], operands[1], operands[2], @@ -11439,10 +11439,10 @@ }) (define_expand "sibcall_value" - [(set (match_operand 0 "" "") - (call (match_operand:QI 1 "" "") - (match_operand 2 "" ""))) - (use (match_operand 3 "" ""))] + [(set (match_operand 0) + (call (match_operand:QI 1) + (match_operand 2))) + (use (match_operand 3))] "" { ix86_expand_call (operands[0], operands[1], operands[2], @@ -11451,10 +11451,10 @@ }) (define_insn_and_split "*call_value_vzeroupper" - [(set (match_operand 0 "" "") + [(set (match_operand 0) (call (mem:QI (match_operand:W 1 "call_insn_operand" "<c>zw")) - (match_operand 2 "" ""))) - (unspec [(match_operand 3 "const_int_operand" "")] + (match_operand 2))) + (unspec [(match_operand 3 "const_int_operand")] UNSPEC_CALL_NEEDS_VZEROUPPER)] "TARGET_VZEROUPPER && !SIBLING_CALL_P (insn)" "#" @@ -11464,18 +11464,18 @@ [(set_attr "type" "callv")]) (define_insn "*call_value" - [(set (match_operand 0 "" "") + [(set (match_operand 0) (call (mem:QI (match_operand:W 1 "call_insn_operand" "<c>zw")) - (match_operand 2 "" "")))] + (match_operand 2)))] "!SIBLING_CALL_P (insn)" "* return ix86_output_call_insn (insn, operands[1]);" [(set_attr "type" "callv")]) (define_insn_and_split "*sibcall_value_vzeroupper" - [(set (match_operand 0 "" "") + [(set (match_operand 0) (call (mem:QI (match_operand:W 1 "sibcall_insn_operand" "Uz")) - (match_operand 2 "" ""))) - (unspec [(match_operand 3 "const_int_operand" "")] + (match_operand 2))) + (unspec [(match_operand 3 "const_int_operand")] UNSPEC_CALL_NEEDS_VZEROUPPER)] "TARGET_VZEROUPPER && SIBLING_CALL_P (insn)" "#" @@ -11485,17 +11485,17 @@ [(set_attr "type" "callv")]) (define_insn "*sibcall_value" - [(set (match_operand 0 "" "") + [(set (match_operand 0) (call (mem:QI (match_operand:W 1 "sibcall_insn_operand" "Uz")) - (match_operand 2 "" "")))] + (match_operand 2)))] "SIBLING_CALL_P (insn)" "* return ix86_output_call_insn (insn, operands[1]);" [(set_attr "type" "callv")]) (define_insn_and_split "*call_value_rex64_ms_sysv_vzeroupper" - [(set (match_operand 0 "" "") + [(set (match_operand 0) (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rzw")) - (match_operand 2 "" ""))) + (match_operand 2))) (unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL) (clobber (reg:TI XMM6_REG)) (clobber (reg:TI XMM7_REG)) @@ -11509,7 +11509,7 @@ (clobber (reg:TI XMM15_REG)) (clobber (reg:DI SI_REG)) (clobber (reg:DI DI_REG)) - (unspec [(match_operand 3 "const_int_operand" "")] + (unspec [(match_operand 3 "const_int_operand")] UNSPEC_CALL_NEEDS_VZEROUPPER)] "TARGET_VZEROUPPER && TARGET_64BIT && !SIBLING_CALL_P (insn)" "#" @@ -11519,9 +11519,9 @@ [(set_attr "type" "callv")]) (define_insn "*call_value_rex64_ms_sysv" - [(set (match_operand 0 "" "") + [(set (match_operand 0) (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rzw")) - (match_operand 2 "" ""))) + (match_operand 2))) (unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL) (clobber (reg:TI XMM6_REG)) (clobber (reg:TI XMM7_REG)) @@ -11540,12 +11540,12 @@ [(set_attr "type" "callv")]) (define_expand "call_value_pop" - [(parallel [(set (match_operand 0 "" "") - (call (match_operand:QI 1 "" "") - (match_operand:SI 2 "" ""))) + [(parallel [(set (match_operand 0) + (call (match_operand:QI 1) + (match_operand:SI 2))) (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) - (match_operand:SI 4 "" "")))])] + (match_operand:SI 4)))])] "!TARGET_64BIT" { ix86_expand_call (operands[0], operands[1], operands[2], @@ -11554,13 +11554,13 @@ }) (define_insn_and_split "*call_value_pop_vzeroupper" - [(set (match_operand 0 "" "") + [(set (match_operand 0) (call (mem:QI (match_operand:SI 1 "call_insn_operand" "lzm")) - (match_operand 2 "" ""))) + (match_operand 2))) (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_operand:SI 3 "immediate_operand" "i"))) - (unspec [(match_operand 4 "const_int_operand" "")] + (unspec [(match_operand 4 "const_int_operand")] UNSPEC_CALL_NEEDS_VZEROUPPER)] "TARGET_VZEROUPPER && !TARGET_64BIT && !SIBLING_CALL_P (insn)" "#" @@ -11570,9 +11570,9 @@ [(set_attr "type" "callv")]) (define_insn "*call_value_pop" - [(set (match_operand 0 "" "") + [(set (match_operand 0) (call (mem:QI (match_operand:SI 1 "call_insn_operand" "lzm")) - (match_operand 2 "" ""))) + (match_operand 2))) (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_operand:SI 3 "immediate_operand" "i")))] @@ -11581,13 +11581,13 @@ [(set_attr "type" "callv")]) (define_insn_and_split "*sibcall_value_pop_vzeroupper" - [(set (match_operand 0 "" "") + [(set (match_operand 0) (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "Uz")) - (match_operand 2 "" ""))) + (match_operand 2))) (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_operand:SI 3 "immediate_operand" "i"))) - (unspec [(match_operand 4 "const_int_operand" "")] + (unspec [(match_operand 4 "const_int_operand")] UNSPEC_CALL_NEEDS_VZEROUPPER)] "TARGET_VZEROUPPER && !TARGET_64BIT && SIBLING_CALL_P (insn)" "#" @@ -11597,9 +11597,9 @@ [(set_attr "type" "callv")]) (define_insn "*sibcall_value_pop" - [(set (match_operand 0 "" "") + [(set (match_operand 0) (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "Uz")) - (match_operand 2 "" ""))) + (match_operand 2))) (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_operand:SI 3 "immediate_operand" "i")))] @@ -11610,10 +11610,10 @@ ;; Call subroutine returning any type. (define_expand "untyped_call" - [(parallel [(call (match_operand 0 "" "") + [(parallel [(call (match_operand 0) (const_int 0)) - (match_operand 1 "" "") - (match_operand 2 "" "")])] + (match_operand 1) + (match_operand 2)])] "" { int i; @@ -11675,7 +11675,7 @@ }) (define_insn "*memory_blockage" - [(set (match_operand:BLK 0 "" "") + [(set (match_operand:BLK 0) (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BLOCKAGE))] "" "" @@ -11684,7 +11684,7 @@ ;; As USE insns aren't meaningful after reload, this is used instead ;; to prevent deleting instructions setting registers for PIC code (define_insn "prologue_use" - [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_PROLOGUE_USE)] + [(unspec_volatile [(match_operand 0)] UNSPECV_PROLOGUE_USE)] "" "" [(set_attr "length" "0")]) @@ -11748,7 +11748,7 @@ (define_insn "simple_return_pop_internal" [(simple_return) - (use (match_operand:SI 0 "const_int_operand" ""))] + (use (match_operand:SI 0 "const_int_operand"))] "reload_completed" "ret\t%0" [(set_attr "length" "3") @@ -11774,7 +11774,7 @@ ;; Generate nops. Operand 0 is the number of nops, up to 8. (define_insn "nops" - [(unspec_volatile [(match_operand 0 "const_int_operand" "")] + [(unspec_volatile [(match_operand 0 "const_int_operand")] UNSPECV_NOPS)] "reload_completed" { @@ -11796,7 +11796,7 @@ ;; block on K8. (define_insn "pad" - [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_ALIGN)] + [(unspec_volatile [(match_operand 0)] UNSPECV_ALIGN)] "" { #ifdef ASM_OUTPUT_MAX_SKIP_PAD @@ -11827,7 +11827,7 @@ (define_insn "set_got_labelled" [(set (match_operand:SI 0 "register_operand" "=r") - (unspec:SI [(label_ref (match_operand 1 "" ""))] + (unspec:SI [(label_ref (match_operand 1))] UNSPEC_SET_GOT)) (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT" @@ -11846,7 +11846,7 @@ (define_insn "set_rip_rex64" [(set (match_operand:DI 0 "register_operand" "=r") - (unspec:DI [(label_ref (match_operand 1 "" ""))] UNSPEC_SET_RIP))] + (unspec:DI [(label_ref (match_operand 1))] UNSPEC_SET_RIP))] "TARGET_64BIT" "lea{q}\t{%l1(%%rip), %0|%0, %l1[rip]}" [(set_attr "type" "lea") @@ -11856,7 +11856,7 @@ (define_insn "set_got_offset_rex64" [(set (match_operand:DI 0 "register_operand" "=r") (unspec:DI - [(label_ref (match_operand 1 "" ""))] + [(label_ref (match_operand 1))] UNSPEC_SET_GOT_OFFSET))] "TARGET_LP64" "movabs{q}\t{$_GLOBAL_OFFSET_TABLE_-%l1, %0|%0, OFFSET FLAT:_GLOBAL_OFFSET_TABLE_-%l1}" @@ -11876,7 +11876,7 @@ "ix86_expand_epilogue (0); DONE;") (define_expand "eh_return" - [(use (match_operand 0 "register_operand" ""))] + [(use (match_operand 0 "register_operand"))] "" { rtx tmp, sa = EH_RETURN_STACKADJ_RTX, ra = operands[0]; @@ -11931,7 +11931,7 @@ ;; In order to support the call/return predictor, we use a return ;; instruction which the middle-end doesn't see. (define_insn "split_stack_return" - [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "")] + [(unspec_volatile [(match_operand:SI 0 "const_int_operand")] UNSPECV_SPLIT_STACK_RETURN)] "" { @@ -11943,11 +11943,11 @@ [(set_attr "atom_unit" "jeu") (set_attr "modrm" "0") (set (attr "length") - (if_then_else (match_operand:SI 0 "const0_operand" "") + (if_then_else (match_operand:SI 0 "const0_operand") (const_int 1) (const_int 3))) (set (attr "length_immediate") - (if_then_else (match_operand:SI 0 "const0_operand" "") + (if_then_else (match_operand:SI 0 "const0_operand") (const_int 0) (const_int 2)))]) @@ -11957,9 +11957,9 @@ (define_expand "split_stack_space_check" [(set (pc) (if_then_else (ltu (minus (reg SP_REG) - (match_operand 0 "register_operand" "")) + (match_operand 0 "register_operand")) (unspec [(const_int 0)] UNSPEC_STACK_CHECK)) - (label_ref (match_operand 1 "" "")) + (label_ref (match_operand 1)) (pc)))] "" { @@ -11982,9 +11982,9 @@ [(set (match_dup 2) (const_int -1)) (parallel [(set (reg:CCZ FLAGS_REG) (compare:CCZ - (match_operand:SWI48 1 "nonimmediate_operand" "") + (match_operand:SWI48 1 "nonimmediate_operand") (const_int 0))) - (set (match_operand:SWI48 0 "register_operand" "") + (set (match_operand:SWI48 0 "register_operand") (ctz:SWI48 (match_dup 1)))]) (set (match_dup 0) (if_then_else:SWI48 (eq (reg:CCZ FLAGS_REG) (const_int 0)) @@ -12056,10 +12056,10 @@ (define_expand "clz<mode>2" [(parallel - [(set (match_operand:SWI248 0 "register_operand" "") + [(set (match_operand:SWI248 0 "register_operand") (minus:SWI248 (match_dup 2) - (clz:SWI248 (match_operand:SWI248 1 "nonimmediate_operand" "")))) + (clz:SWI248 (match_operand:SWI248 1 "nonimmediate_operand")))) (clobber (reg:CC FLAGS_REG))]) (parallel [(set (match_dup 0) (xor:SWI248 (match_dup 0) (match_dup 2))) @@ -12409,8 +12409,8 @@ (set_attr "mode" "SI")]) (define_expand "bswap<mode>2" - [(set (match_operand:SWI48 0 "register_operand" "") - (bswap:SWI48 (match_operand:SWI48 1 "register_operand" "")))] + [(set (match_operand:SWI48 0 "register_operand") + (bswap:SWI48 (match_operand:SWI48 1 "register_operand")))] "" { if (<MODE>mode == SImode && !(TARGET_BSWAP || TARGET_MOVBE)) @@ -12470,8 +12470,8 @@ (set_attr "mode" "HI")]) (define_expand "paritydi2" - [(set (match_operand:DI 0 "register_operand" "") - (parity:DI (match_operand:DI 1 "register_operand" "")))] + [(set (match_operand:DI 0 "register_operand") + (parity:DI (match_operand:DI 1 "register_operand")))] "! TARGET_POPCNT" { rtx scratch = gen_reg_rtx (QImode); @@ -12498,8 +12498,8 @@ }) (define_expand "paritysi2" - [(set (match_operand:SI 0 "register_operand" "") - (parity:SI (match_operand:SI 1 "register_operand" "")))] + [(set (match_operand:SI 0 "register_operand") + (parity:SI (match_operand:SI 1 "register_operand")))] "! TARGET_POPCNT" { rtx scratch = gen_reg_rtx (QImode); @@ -12591,7 +12591,7 @@ [(set (match_operand:SI 0 "register_operand" "=a") (unspec:SI [(match_operand:SI 1 "register_operand" "b") - (match_operand 2 "tls_symbolic_operand" "") + (match_operand 2 "tls_symbolic_operand") (match_operand 3 "constant_call_address_operand" "z")] UNSPEC_TLS_GD)) (clobber (match_scratch:SI 4 "=d")) @@ -12614,21 +12614,21 @@ (define_expand "tls_global_dynamic_32" [(parallel - [(set (match_operand:SI 0 "register_operand" "") - (unspec:SI [(match_operand:SI 2 "register_operand" "") - (match_operand 1 "tls_symbolic_operand" "") - (match_operand 3 "constant_call_address_operand" "")] + [(set (match_operand:SI 0 "register_operand") + (unspec:SI [(match_operand:SI 2 "register_operand") + (match_operand 1 "tls_symbolic_operand") + (match_operand 3 "constant_call_address_operand")] UNSPEC_TLS_GD)) - (clobber (match_scratch:SI 4 "")) - (clobber (match_scratch:SI 5 "")) + (clobber (match_scratch:SI 4)) + (clobber (match_scratch:SI 5)) (clobber (reg:CC FLAGS_REG))])]) (define_insn "*tls_global_dynamic_64_<mode>" [(set (match_operand:P 0 "register_operand" "=a") (call:P (mem:QI (match_operand 2 "constant_call_address_operand" "z")) - (match_operand 3 "" ""))) - (unspec:P [(match_operand 1 "tls_symbolic_operand" "")] + (match_operand 3))) + (unspec:P [(match_operand 1 "tls_symbolic_operand")] UNSPEC_TLS_GD)] "TARGET_64BIT" { @@ -12648,11 +12648,11 @@ (define_expand "tls_global_dynamic_64_<mode>" [(parallel - [(set (match_operand:P 0 "register_operand" "") + [(set (match_operand:P 0 "register_operand") (call:P - (mem:QI (match_operand 2 "constant_call_address_operand" "")) + (mem:QI (match_operand 2 "constant_call_address_operand")) (const_int 0))) - (unspec:P [(match_operand 1 "tls_symbolic_operand" "")] + (unspec:P [(match_operand 1 "tls_symbolic_operand")] UNSPEC_TLS_GD)])] "TARGET_64BIT") @@ -12682,20 +12682,20 @@ (define_expand "tls_local_dynamic_base_32" [(parallel - [(set (match_operand:SI 0 "register_operand" "") + [(set (match_operand:SI 0 "register_operand") (unspec:SI - [(match_operand:SI 1 "register_operand" "") - (match_operand 2 "constant_call_address_operand" "")] + [(match_operand:SI 1 "register_operand") + (match_operand 2 "constant_call_address_operand")] UNSPEC_TLS_LD_BASE)) - (clobber (match_scratch:SI 3 "")) - (clobber (match_scratch:SI 4 "")) + (clobber (match_scratch:SI 3)) + (clobber (match_scratch:SI 4)) (clobber (reg:CC FLAGS_REG))])]) (define_insn "*tls_local_dynamic_base_64_<mode>" [(set (match_operand:P 0 "register_operand" "=a") (call:P (mem:QI (match_operand 1 "constant_call_address_operand" "z")) - (match_operand 2 "" ""))) + (match_operand 2))) (unspec:P [(const_int 0)] UNSPEC_TLS_LD_BASE)] "TARGET_64BIT" { @@ -12710,9 +12710,9 @@ (define_expand "tls_local_dynamic_base_64_<mode>" [(parallel - [(set (match_operand:P 0 "register_operand" "") + [(set (match_operand:P 0 "register_operand") (call:P - (mem:QI (match_operand 1 "constant_call_address_operand" "")) + (mem:QI (match_operand 1 "constant_call_address_operand")) (const_int 0))) (unspec:P [(const_int 0)] UNSPEC_TLS_LD_BASE)])] "TARGET_64BIT") @@ -12727,7 +12727,7 @@ (match_operand 2 "constant_call_address_operand" "z")] UNSPEC_TLS_LD_BASE) (const:SI (unspec:SI - [(match_operand 3 "tls_symbolic_operand" "")] + [(match_operand 3 "tls_symbolic_operand")] UNSPEC_DTPOFF)))) (clobber (match_scratch:SI 4 "=d")) (clobber (match_scratch:SI 5 "=c")) @@ -12825,7 +12825,7 @@ (define_insn "tls_initial_exec_64_sun" [(set (match_operand:DI 0 "register_operand" "=a") (unspec:DI - [(match_operand 1 "tls_symbolic_operand" "")] + [(match_operand 1 "tls_symbolic_operand")] UNSPEC_TLS_IE_SUN)) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && TARGET_SUN_TLS" @@ -12847,7 +12847,7 @@ (define_insn "tls_initial_exec_x32" [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI - [(match_operand 1 "tls_symbolic_operand" "")] + [(match_operand 1 "tls_symbolic_operand")] UNSPEC_TLS_IE_X32)) (clobber (reg:CC FLAGS_REG))] "TARGET_X32" @@ -12862,12 +12862,12 @@ (define_expand "tls_dynamic_gnu2_32" [(set (match_dup 3) - (plus:SI (match_operand:SI 2 "register_operand" "") + (plus:SI (match_operand:SI 2 "register_operand") (const:SI - (unspec:SI [(match_operand 1 "tls_symbolic_operand" "")] + (unspec:SI [(match_operand 1 "tls_symbolic_operand")] UNSPEC_TLSDESC)))) (parallel - [(set (match_operand:SI 0 "register_operand" "") + [(set (match_operand:SI 0 "register_operand") (unspec:SI [(match_dup 1) (match_dup 3) (match_dup 2) (reg:SI SP_REG)] UNSPEC_TLSDESC)) @@ -12882,7 +12882,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (plus:SI (match_operand:SI 1 "register_operand" "b") (const:SI - (unspec:SI [(match_operand 2 "tls_symbolic_operand" "")] + (unspec:SI [(match_operand 2 "tls_symbolic_operand")] UNSPEC_TLSDESC))))] "!TARGET_64BIT && TARGET_GNU2_TLS" "lea{l}\t{%E2@TLSDESC(%1), %0|%0, %E2@TLSDESC[%1]}" @@ -12893,7 +12893,7 @@ (define_insn "*tls_dynamic_gnu2_call_32" [(set (match_operand:SI 0 "register_operand" "=a") - (unspec:SI [(match_operand 1 "tls_symbolic_operand" "") + (unspec:SI [(match_operand 1 "tls_symbolic_operand") (match_operand:SI 2 "register_operand" "0") ;; we have to make sure %ebx still points to the GOT (match_operand:SI 3 "register_operand" "b") @@ -12909,13 +12909,13 @@ (define_insn_and_split "*tls_dynamic_gnu2_combine_32" [(set (match_operand:SI 0 "register_operand" "=&a") (plus:SI - (unspec:SI [(match_operand 3 "tls_modbase_operand" "") - (match_operand:SI 4 "" "") + (unspec:SI [(match_operand 3 "tls_modbase_operand") + (match_operand:SI 4) (match_operand:SI 2 "register_operand" "b") (reg:SI SP_REG)] UNSPEC_TLSDESC) (const:SI (unspec:SI - [(match_operand 1 "tls_symbolic_operand" "")] + [(match_operand 1 "tls_symbolic_operand")] UNSPEC_DTPOFF)))) (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && TARGET_GNU2_TLS" @@ -12929,10 +12929,10 @@ (define_expand "tls_dynamic_gnu2_64" [(set (match_dup 2) - (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] + (unspec:DI [(match_operand 1 "tls_symbolic_operand")] UNSPEC_TLSDESC)) (parallel - [(set (match_operand:DI 0 "register_operand" "") + [(set (match_operand:DI 0 "register_operand") (unspec:DI [(match_dup 1) (match_dup 2) (reg:DI SP_REG)] UNSPEC_TLSDESC)) (clobber (reg:CC FLAGS_REG))])] @@ -12944,7 +12944,7 @@ (define_insn "*tls_dynamic_gnu2_lea_64" [(set (match_operand:DI 0 "register_operand" "=r") - (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] + (unspec:DI [(match_operand 1 "tls_symbolic_operand")] UNSPEC_TLSDESC))] "TARGET_64BIT && TARGET_GNU2_TLS" "lea{q}\t{%E1@TLSDESC(%%rip), %0|%0, %E1@TLSDESC[rip]}" @@ -12955,7 +12955,7 @@ (define_insn "*tls_dynamic_gnu2_call_64" [(set (match_operand:DI 0 "register_operand" "=a") - (unspec:DI [(match_operand 1 "tls_symbolic_operand" "") + (unspec:DI [(match_operand 1 "tls_symbolic_operand") (match_operand:DI 2 "register_operand" "0") (reg:DI SP_REG)] UNSPEC_TLSDESC)) @@ -12969,12 +12969,12 @@ (define_insn_and_split "*tls_dynamic_gnu2_combine_64" [(set (match_operand:DI 0 "register_operand" "=&a") (plus:DI - (unspec:DI [(match_operand 2 "tls_modbase_operand" "") - (match_operand:DI 3 "" "") + (unspec:DI [(match_operand 2 "tls_modbase_operand") + (match_operand:DI 3) (reg:DI SP_REG)] UNSPEC_TLSDESC) (const:DI (unspec:DI - [(match_operand 1 "tls_symbolic_operand" "")] + [(match_operand 1 "tls_symbolic_operand")] UNSPEC_DTPOFF)))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && TARGET_GNU2_TLS" @@ -13008,10 +13008,10 @@ "* return output_387_binary_op (insn, operands);" [(set (attr "type") (if_then_else (eq_attr "alternative" "1,2") - (if_then_else (match_operand:MODEF 3 "mult_operator" "") + (if_then_else (match_operand:MODEF 3 "mult_operator") (const_string "ssemul") (const_string "sseadd")) - (if_then_else (match_operand:MODEF 3 "mult_operator" "") + (if_then_else (match_operand:MODEF 3 "mult_operator") (const_string "fmul") (const_string "fop")))) (set_attr "isa" "*,noavx,avx") @@ -13028,7 +13028,7 @@ && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "* return output_387_binary_op (insn, operands);" [(set (attr "type") - (if_then_else (match_operand:MODEF 3 "mult_operator" "") + (if_then_else (match_operand:MODEF 3 "mult_operator") (const_string "ssemul") (const_string "sseadd"))) (set_attr "isa" "noavx,avx") @@ -13045,7 +13045,7 @@ && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "* return output_387_binary_op (insn, operands);" [(set (attr "type") - (if_then_else (match_operand:MODEF 3 "mult_operator" "") + (if_then_else (match_operand:MODEF 3 "mult_operator") (const_string "fmul") (const_string "fop"))) (set_attr "mode" "<MODE>")]) @@ -13061,16 +13061,16 @@ "* return output_387_binary_op (insn, operands);" [(set (attr "type") (cond [(and (eq_attr "alternative" "2,3") - (match_operand:MODEF 3 "mult_operator" "")) + (match_operand:MODEF 3 "mult_operator")) (const_string "ssemul") (and (eq_attr "alternative" "2,3") - (match_operand:MODEF 3 "div_operator" "")) + (match_operand:MODEF 3 "div_operator")) (const_string "ssediv") (eq_attr "alternative" "2,3") (const_string "sseadd") - (match_operand:MODEF 3 "mult_operator" "") + (match_operand:MODEF 3 "mult_operator") (const_string "fmul") - (match_operand:MODEF 3 "div_operator" "") + (match_operand:MODEF 3 "div_operator") (const_string "fdiv") ] (const_string "fop"))) @@ -13098,9 +13098,9 @@ && !COMMUTATIVE_ARITH_P (operands[3])" "* return output_387_binary_op (insn, operands);" [(set (attr "type") - (cond [(match_operand:MODEF 3 "mult_operator" "") + (cond [(match_operand:MODEF 3 "mult_operator") (const_string "ssemul") - (match_operand:MODEF 3 "div_operator" "") + (match_operand:MODEF 3 "div_operator") (const_string "ssediv") ] (const_string "sseadd"))) @@ -13120,9 +13120,9 @@ && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "* return output_387_binary_op (insn, operands);" [(set (attr "type") - (cond [(match_operand:MODEF 3 "mult_operator" "") + (cond [(match_operand:MODEF 3 "mult_operator") (const_string "fmul") - (match_operand:MODEF 3 "div_operator" "") + (match_operand:MODEF 3 "div_operator") (const_string "fdiv") ] (const_string "fop"))) @@ -13140,9 +13140,9 @@ && (TARGET_USE_<SWI24:MODE>MODE_FIOP || optimize_function_for_size_p (cfun))" "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);" [(set (attr "type") - (cond [(match_operand:MODEF 3 "mult_operator" "") + (cond [(match_operand:MODEF 3 "mult_operator") (const_string "fmul") - (match_operand:MODEF 3 "div_operator" "") + (match_operand:MODEF 3 "div_operator") (const_string "fdiv") ] (const_string "fop"))) @@ -13160,9 +13160,9 @@ && (TARGET_USE_<SWI24:MODE>MODE_FIOP || optimize_function_for_size_p (cfun))" "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);" [(set (attr "type") - (cond [(match_operand:MODEF 3 "mult_operator" "") + (cond [(match_operand:MODEF 3 "mult_operator") (const_string "fmul") - (match_operand:MODEF 3 "div_operator" "") + (match_operand:MODEF 3 "div_operator") (const_string "fdiv") ] (const_string "fop"))) @@ -13180,9 +13180,9 @@ && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "* return output_387_binary_op (insn, operands);" [(set (attr "type") - (cond [(match_operand:DF 3 "mult_operator" "") + (cond [(match_operand:DF 3 "mult_operator") (const_string "fmul") - (match_operand:DF 3 "div_operator" "") + (match_operand:DF 3 "div_operator") (const_string "fdiv") ] (const_string "fop"))) @@ -13198,9 +13198,9 @@ && !(TARGET_SSE2 && TARGET_SSE_MATH)" "* return output_387_binary_op (insn, operands);" [(set (attr "type") - (cond [(match_operand:DF 3 "mult_operator" "") + (cond [(match_operand:DF 3 "mult_operator") (const_string "fmul") - (match_operand:DF 3 "div_operator" "") + (match_operand:DF 3 "div_operator") (const_string "fdiv") ] (const_string "fop"))) @@ -13217,9 +13217,9 @@ && !(TARGET_SSE2 && TARGET_SSE_MATH)" "* return output_387_binary_op (insn, operands);" [(set (attr "type") - (cond [(match_operand:DF 3 "mult_operator" "") + (cond [(match_operand:DF 3 "mult_operator") (const_string "fmul") - (match_operand:DF 3 "div_operator" "") + (match_operand:DF 3 "div_operator") (const_string "fdiv") ] (const_string "fop"))) @@ -13234,7 +13234,7 @@ && COMMUTATIVE_ARITH_P (operands[3])" "* return output_387_binary_op (insn, operands);" [(set (attr "type") - (if_then_else (match_operand:XF 3 "mult_operator" "") + (if_then_else (match_operand:XF 3 "mult_operator") (const_string "fmul") (const_string "fop"))) (set_attr "mode" "XF")]) @@ -13248,9 +13248,9 @@ && !COMMUTATIVE_ARITH_P (operands[3])" "* return output_387_binary_op (insn, operands);" [(set (attr "type") - (cond [(match_operand:XF 3 "mult_operator" "") + (cond [(match_operand:XF 3 "mult_operator") (const_string "fmul") - (match_operand:XF 3 "div_operator" "") + (match_operand:XF 3 "div_operator") (const_string "fdiv") ] (const_string "fop"))) @@ -13265,9 +13265,9 @@ "TARGET_80387 && (TARGET_USE_<MODE>MODE_FIOP || optimize_function_for_size_p (cfun))" "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);" [(set (attr "type") - (cond [(match_operand:XF 3 "mult_operator" "") + (cond [(match_operand:XF 3 "mult_operator") (const_string "fmul") - (match_operand:XF 3 "div_operator" "") + (match_operand:XF 3 "div_operator") (const_string "fdiv") ] (const_string "fop"))) @@ -13283,9 +13283,9 @@ "TARGET_80387 && (TARGET_USE_<MODE>MODE_FIOP || optimize_function_for_size_p (cfun))" "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);" [(set (attr "type") - (cond [(match_operand:XF 3 "mult_operator" "") + (cond [(match_operand:XF 3 "mult_operator") (const_string "fmul") - (match_operand:XF 3 "div_operator" "") + (match_operand:XF 3 "div_operator") (const_string "fdiv") ] (const_string "fop"))) @@ -13301,9 +13301,9 @@ "TARGET_80387" "* return output_387_binary_op (insn, operands);" [(set (attr "type") - (cond [(match_operand:XF 3 "mult_operator" "") + (cond [(match_operand:XF 3 "mult_operator") (const_string "fmul") - (match_operand:XF 3 "div_operator" "") + (match_operand:XF 3 "div_operator") (const_string "fdiv") ] (const_string "fop"))) @@ -13318,9 +13318,9 @@ "TARGET_80387" "* return output_387_binary_op (insn, operands);" [(set (attr "type") - (cond [(match_operand:XF 3 "mult_operator" "") + (cond [(match_operand:XF 3 "mult_operator") (const_string "fmul") - (match_operand:XF 3 "div_operator" "") + (match_operand:XF 3 "div_operator") (const_string "fdiv") ] (const_string "fop"))) @@ -13336,19 +13336,19 @@ "TARGET_80387" "* return output_387_binary_op (insn, operands);" [(set (attr "type") - (cond [(match_operand:XF 3 "mult_operator" "") + (cond [(match_operand:XF 3 "mult_operator") (const_string "fmul") - (match_operand:XF 3 "div_operator" "") + (match_operand:XF 3 "div_operator") (const_string "fdiv") ] (const_string "fop"))) (set_attr "mode" "<MODE>")]) (define_split - [(set (match_operand 0 "register_operand" "") + [(set (match_operand 0 "register_operand") (match_operator 3 "binary_fp_operator" - [(float (match_operand:SWI24 1 "register_operand" "")) - (match_operand 2 "register_operand" "")]))] + [(float (match_operand:SWI24 1 "register_operand")) + (match_operand 2 "register_operand")]))] "reload_completed && X87_FLOAT_MODE_P (GET_MODE (operands[0])) && X87_ENABLE_FLOAT (GET_MODE (operands[0]), GET_MODE (operands[1]))" @@ -13366,10 +13366,10 @@ }) (define_split - [(set (match_operand 0 "register_operand" "") + [(set (match_operand 0 "register_operand") (match_operator 3 "binary_fp_operator" - [(match_operand 1 "register_operand" "") - (float (match_operand:SWI24 2 "register_operand" ""))]))] + [(match_operand 1 "register_operand") + (float (match_operand:SWI24 2 "register_operand"))]))] "reload_completed && X87_FLOAT_MODE_P (GET_MODE (operands[0])) && X87_ENABLE_FLOAT (GET_MODE (operands[0]), GET_MODE (operands[2]))" @@ -13436,8 +13436,8 @@ (set_attr "mode" "SF")]) (define_expand "rsqrtsf2" - [(set (match_operand:SF 0 "register_operand" "") - (unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "")] + [(set (match_operand:SF 0 "register_operand") + (unspec:SF [(match_operand:SF 1 "nonimmediate_operand")] UNSPEC_RSQRT))] "TARGET_SSE_MATH" { @@ -13460,9 +13460,9 @@ (set_attr "bdver1_decode" "*")]) (define_expand "sqrt<mode>2" - [(set (match_operand:MODEF 0 "register_operand" "") + [(set (match_operand:MODEF 0 "register_operand") (sqrt:MODEF - (match_operand:MODEF 1 "nonimmediate_operand" "")))] + (match_operand:MODEF 1 "nonimmediate_operand")))] "(TARGET_USE_FANCY_MATH_387 && X87_ENABLE_ARITH (<MODE>mode)) || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)" { @@ -13505,9 +13505,9 @@ (set_attr "mode" "XF")]) (define_expand "fmodxf3" - [(use (match_operand:XF 0 "register_operand" "")) - (use (match_operand:XF 1 "general_operand" "")) - (use (match_operand:XF 2 "general_operand" ""))] + [(use (match_operand:XF 0 "register_operand")) + (use (match_operand:XF 1 "general_operand")) + (use (match_operand:XF 2 "general_operand"))] "TARGET_USE_FANCY_MATH_387" { rtx label = gen_label_rtx (); @@ -13528,9 +13528,9 @@ }) (define_expand "fmod<mode>3" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "general_operand" "")) - (use (match_operand:MODEF 2 "general_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "general_operand")) + (use (match_operand:MODEF 2 "general_operand"))] "TARGET_USE_FANCY_MATH_387" { rtx (*gen_truncxf) (rtx, rtx); @@ -13576,9 +13576,9 @@ (set_attr "mode" "XF")]) (define_expand "remainderxf3" - [(use (match_operand:XF 0 "register_operand" "")) - (use (match_operand:XF 1 "general_operand" "")) - (use (match_operand:XF 2 "general_operand" ""))] + [(use (match_operand:XF 0 "register_operand")) + (use (match_operand:XF 1 "general_operand")) + (use (match_operand:XF 2 "general_operand"))] "TARGET_USE_FANCY_MATH_387" { rtx label = gen_label_rtx (); @@ -13599,9 +13599,9 @@ }) (define_expand "remainder<mode>3" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "general_operand" "")) - (use (match_operand:MODEF 2 "general_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "general_operand")) + (use (match_operand:MODEF 2 "general_operand"))] "TARGET_USE_FANCY_MATH_387" { rtx (*gen_truncxf) (rtx, rtx); @@ -13694,20 +13694,20 @@ (set_attr "mode" "XF")]) (define_split - [(set (match_operand:XF 0 "register_operand" "") - (unspec:XF [(match_operand:XF 2 "register_operand" "")] + [(set (match_operand:XF 0 "register_operand") + (unspec:XF [(match_operand:XF 2 "register_operand")] UNSPEC_SINCOS_COS)) - (set (match_operand:XF 1 "register_operand" "") + (set (match_operand:XF 1 "register_operand") (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))] "find_regno_note (insn, REG_UNUSED, REGNO (operands[0])) && can_create_pseudo_p ()" [(set (match_dup 1) (unspec:XF [(match_dup 2)] UNSPEC_SIN))]) (define_split - [(set (match_operand:XF 0 "register_operand" "") - (unspec:XF [(match_operand:XF 2 "register_operand" "")] + [(set (match_operand:XF 0 "register_operand") + (unspec:XF [(match_operand:XF 2 "register_operand")] UNSPEC_SINCOS_COS)) - (set (match_operand:XF 1 "register_operand" "") + (set (match_operand:XF 1 "register_operand") (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))] "find_regno_note (insn, REG_UNUSED, REGNO (operands[1])) && can_create_pseudo_p ()" @@ -13729,11 +13729,11 @@ (set_attr "mode" "XF")]) (define_split - [(set (match_operand:XF 0 "register_operand" "") + [(set (match_operand:XF 0 "register_operand") (unspec:XF [(float_extend:XF - (match_operand:MODEF 2 "register_operand" ""))] + (match_operand:MODEF 2 "register_operand"))] UNSPEC_SINCOS_COS)) - (set (match_operand:XF 1 "register_operand" "") + (set (match_operand:XF 1 "register_operand") (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SINCOS_SIN))] "find_regno_note (insn, REG_UNUSED, REGNO (operands[0])) && can_create_pseudo_p ()" @@ -13741,11 +13741,11 @@ (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SIN))]) (define_split - [(set (match_operand:XF 0 "register_operand" "") + [(set (match_operand:XF 0 "register_operand") (unspec:XF [(float_extend:XF - (match_operand:MODEF 2 "register_operand" ""))] + (match_operand:MODEF 2 "register_operand"))] UNSPEC_SINCOS_COS)) - (set (match_operand:XF 1 "register_operand" "") + (set (match_operand:XF 1 "register_operand") (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SINCOS_SIN))] "find_regno_note (insn, REG_UNUSED, REGNO (operands[1])) && can_create_pseudo_p ()" @@ -13753,9 +13753,9 @@ (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_COS))]) (define_expand "sincos<mode>3" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "register_operand" "")) - (use (match_operand:MODEF 2 "register_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "register_operand")) + (use (match_operand:MODEF 2 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -13800,8 +13800,8 @@ (set_attr "mode" "XF")]) (define_expand "tanxf2" - [(use (match_operand:XF 0 "register_operand" "")) - (use (match_operand:XF 1 "register_operand" ""))] + [(use (match_operand:XF 0 "register_operand")) + (use (match_operand:XF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { @@ -13813,8 +13813,8 @@ }) (define_expand "tan<mode>2" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "register_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -13860,18 +13860,18 @@ (set_attr "mode" "XF")]) (define_expand "atan2xf3" - [(parallel [(set (match_operand:XF 0 "register_operand" "") - (unspec:XF [(match_operand:XF 2 "register_operand" "") - (match_operand:XF 1 "register_operand" "")] + [(parallel [(set (match_operand:XF 0 "register_operand") + (unspec:XF [(match_operand:XF 2 "register_operand") + (match_operand:XF 1 "register_operand")] UNSPEC_FPATAN)) - (clobber (match_scratch:XF 3 ""))])] + (clobber (match_scratch:XF 3))])] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations") (define_expand "atan2<mode>3" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "register_operand" "")) - (use (match_operand:MODEF 2 "register_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "register_operand")) + (use (match_operand:MODEF 2 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -13885,11 +13885,11 @@ }) (define_expand "atanxf2" - [(parallel [(set (match_operand:XF 0 "register_operand" "") + [(parallel [(set (match_operand:XF 0 "register_operand") (unspec:XF [(match_dup 2) - (match_operand:XF 1 "register_operand" "")] + (match_operand:XF 1 "register_operand")] UNSPEC_FPATAN)) - (clobber (match_scratch:XF 3 ""))])] + (clobber (match_scratch:XF 3))])] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { @@ -13898,8 +13898,8 @@ }) (define_expand "atan<mode>2" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "register_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -13917,14 +13917,14 @@ (define_expand "asinxf2" [(set (match_dup 2) - (mult:XF (match_operand:XF 1 "register_operand" "") + (mult:XF (match_operand:XF 1 "register_operand") (match_dup 1))) (set (match_dup 4) (minus:XF (match_dup 3) (match_dup 2))) (set (match_dup 5) (sqrt:XF (match_dup 4))) - (parallel [(set (match_operand:XF 0 "register_operand" "") + (parallel [(set (match_operand:XF 0 "register_operand") (unspec:XF [(match_dup 5) (match_dup 1)] UNSPEC_FPATAN)) - (clobber (match_scratch:XF 6 ""))])] + (clobber (match_scratch:XF 6))])] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { @@ -13940,8 +13940,8 @@ }) (define_expand "asin<mode>2" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "general_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "general_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -13961,14 +13961,14 @@ (define_expand "acosxf2" [(set (match_dup 2) - (mult:XF (match_operand:XF 1 "register_operand" "") + (mult:XF (match_operand:XF 1 "register_operand") (match_dup 1))) (set (match_dup 4) (minus:XF (match_dup 3) (match_dup 2))) (set (match_dup 5) (sqrt:XF (match_dup 4))) - (parallel [(set (match_operand:XF 0 "register_operand" "") + (parallel [(set (match_operand:XF 0 "register_operand") (unspec:XF [(match_dup 1) (match_dup 5)] UNSPEC_FPATAN)) - (clobber (match_scratch:XF 6 ""))])] + (clobber (match_scratch:XF 6))])] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { @@ -13984,8 +13984,8 @@ }) (define_expand "acos<mode>2" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "general_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "general_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14031,10 +14031,10 @@ (set_attr "mode" "XF")]) (define_expand "logxf2" - [(parallel [(set (match_operand:XF 0 "register_operand" "") - (unspec:XF [(match_operand:XF 1 "register_operand" "") + [(parallel [(set (match_operand:XF 0 "register_operand") + (unspec:XF [(match_operand:XF 1 "register_operand") (match_dup 2)] UNSPEC_FYL2X)) - (clobber (match_scratch:XF 3 ""))])] + (clobber (match_scratch:XF 3))])] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { @@ -14043,8 +14043,8 @@ }) (define_expand "log<mode>2" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "register_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14061,10 +14061,10 @@ }) (define_expand "log10xf2" - [(parallel [(set (match_operand:XF 0 "register_operand" "") - (unspec:XF [(match_operand:XF 1 "register_operand" "") + [(parallel [(set (match_operand:XF 0 "register_operand") + (unspec:XF [(match_operand:XF 1 "register_operand") (match_dup 2)] UNSPEC_FYL2X)) - (clobber (match_scratch:XF 3 ""))])] + (clobber (match_scratch:XF 3))])] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { @@ -14073,8 +14073,8 @@ }) (define_expand "log10<mode>2" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "register_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14091,10 +14091,10 @@ }) (define_expand "log2xf2" - [(parallel [(set (match_operand:XF 0 "register_operand" "") - (unspec:XF [(match_operand:XF 1 "register_operand" "") + [(parallel [(set (match_operand:XF 0 "register_operand") + (unspec:XF [(match_operand:XF 1 "register_operand") (match_dup 2)] UNSPEC_FYL2X)) - (clobber (match_scratch:XF 3 ""))])] + (clobber (match_scratch:XF 3))])] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { @@ -14103,8 +14103,8 @@ }) (define_expand "log2<mode>2" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "register_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14148,8 +14148,8 @@ (set_attr "mode" "XF")]) (define_expand "log1pxf2" - [(use (match_operand:XF 0 "register_operand" "")) - (use (match_operand:XF 1 "register_operand" ""))] + [(use (match_operand:XF 0 "register_operand")) + (use (match_operand:XF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { @@ -14161,8 +14161,8 @@ }) (define_expand "log1p<mode>2" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "register_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14211,17 +14211,17 @@ (define_expand "logbxf2" [(parallel [(set (match_dup 2) - (unspec:XF [(match_operand:XF 1 "register_operand" "")] + (unspec:XF [(match_operand:XF 1 "register_operand")] UNSPEC_XTRACT_FRACT)) - (set (match_operand:XF 0 "register_operand" "") + (set (match_operand:XF 0 "register_operand") (unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))])] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" "operands[2] = gen_reg_rtx (XFmode);") (define_expand "logb<mode>2" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "register_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14236,8 +14236,8 @@ }) (define_expand "ilogbxf2" - [(use (match_operand:SI 0 "register_operand" "")) - (use (match_operand:XF 1 "register_operand" ""))] + [(use (match_operand:SI 0 "register_operand")) + (use (match_operand:XF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { @@ -14255,8 +14255,8 @@ }) (define_expand "ilogb<mode>2" - [(use (match_operand:SI 0 "register_operand" "")) - (use (match_operand:MODEF 1 "register_operand" ""))] + [(use (match_operand:SI 0 "register_operand")) + (use (match_operand:MODEF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14300,13 +14300,13 @@ (set_attr "mode" "XF")]) (define_expand "expNcorexf3" - [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "") - (match_operand:XF 2 "register_operand" ""))) + [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand") + (match_operand:XF 2 "register_operand"))) (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT)) (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4))) (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1)) (set (match_dup 8) (plus:XF (match_dup 6) (match_dup 7))) - (parallel [(set (match_operand:XF 0 "register_operand" "") + (parallel [(set (match_operand:XF 0 "register_operand") (unspec:XF [(match_dup 8) (match_dup 4)] UNSPEC_FSCALE_FRACT)) (set (match_dup 9) @@ -14327,8 +14327,8 @@ }) (define_expand "expxf2" - [(use (match_operand:XF 0 "register_operand" "")) - (use (match_operand:XF 1 "register_operand" ""))] + [(use (match_operand:XF 0 "register_operand")) + (use (match_operand:XF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { @@ -14345,8 +14345,8 @@ }) (define_expand "exp<mode>2" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "general_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "general_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14367,8 +14367,8 @@ }) (define_expand "exp10xf2" - [(use (match_operand:XF 0 "register_operand" "")) - (use (match_operand:XF 1 "register_operand" ""))] + [(use (match_operand:XF 0 "register_operand")) + (use (match_operand:XF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { @@ -14385,8 +14385,8 @@ }) (define_expand "exp10<mode>2" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "general_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "general_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14407,8 +14407,8 @@ }) (define_expand "exp2xf2" - [(use (match_operand:XF 0 "register_operand" "")) - (use (match_operand:XF 1 "register_operand" ""))] + [(use (match_operand:XF 0 "register_operand")) + (use (match_operand:XF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { @@ -14425,8 +14425,8 @@ }) (define_expand "exp2<mode>2" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "general_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "general_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14447,7 +14447,7 @@ }) (define_expand "expm1xf2" - [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "") + [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand") (match_dup 2))) (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT)) (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4))) @@ -14467,7 +14467,7 @@ UNSPEC_FSCALE_EXP))]) (set (match_dup 12) (minus:XF (match_dup 10) (float_extend:XF (match_dup 13)))) - (set (match_operand:XF 0 "register_operand" "") + (set (match_operand:XF 0 "register_operand") (plus:XF (match_dup 12) (match_dup 7)))] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" @@ -14487,8 +14487,8 @@ }) (define_expand "expm1<mode>2" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "general_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "general_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14510,9 +14510,9 @@ (define_expand "ldexpxf3" [(set (match_dup 3) - (float:XF (match_operand:SI 2 "register_operand" ""))) - (parallel [(set (match_operand:XF 0 " register_operand" "") - (unspec:XF [(match_operand:XF 1 "register_operand" "") + (float:XF (match_operand:SI 2 "register_operand"))) + (parallel [(set (match_operand:XF 0 " register_operand") + (unspec:XF [(match_operand:XF 1 "register_operand") (match_dup 3)] UNSPEC_FSCALE_FRACT)) (set (match_dup 4) @@ -14529,9 +14529,9 @@ }) (define_expand "ldexp<mode>3" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "general_operand" "")) - (use (match_operand:SI 2 "register_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "general_operand")) + (use (match_operand:SI 2 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14552,9 +14552,9 @@ }) (define_expand "scalbxf3" - [(parallel [(set (match_operand:XF 0 " register_operand" "") - (unspec:XF [(match_operand:XF 1 "register_operand" "") - (match_operand:XF 2 "register_operand" "")] + [(parallel [(set (match_operand:XF 0 " register_operand") + (unspec:XF [(match_operand:XF 1 "register_operand") + (match_operand:XF 2 "register_operand")] UNSPEC_FSCALE_FRACT)) (set (match_dup 3) (unspec:XF [(match_dup 1) (match_dup 2)] @@ -14569,9 +14569,9 @@ }) (define_expand "scalb<mode>3" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "general_operand" "")) - (use (match_operand:MODEF 2 "general_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "general_operand")) + (use (match_operand:MODEF 2 "general_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14594,8 +14594,8 @@ }) (define_expand "significandxf2" - [(parallel [(set (match_operand:XF 0 "register_operand" "") - (unspec:XF [(match_operand:XF 1 "register_operand" "")] + [(parallel [(set (match_operand:XF 0 "register_operand") + (unspec:XF [(match_operand:XF 1 "register_operand")] UNSPEC_XTRACT_FRACT)) (set (match_dup 2) (unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))])] @@ -14604,8 +14604,8 @@ "operands[2] = gen_reg_rtx (XFmode);") (define_expand "significand<mode>2" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "register_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14643,8 +14643,8 @@ (set_attr "mode" "XF")]) (define_expand "rint<mode>2" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "register_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "register_operand"))] "(TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14677,8 +14677,8 @@ }) (define_expand "round<mode>2" - [(match_operand:X87MODEF 0 "register_operand" "") - (match_operand:X87MODEF 1 "nonimmediate_operand" "")] + [(match_operand:X87MODEF 0 "register_operand") + (match_operand:X87MODEF 1 "nonimmediate_operand")] "(TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14711,8 +14711,8 @@ }) (define_insn_and_split "*fistdi2_1" - [(set (match_operand:DI 0 "nonimmediate_operand" "") - (unspec:DI [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:DI 0 "nonimmediate_operand") + (unspec:DI [(match_operand:XF 1 "register_operand")] UNSPEC_FIST))] "TARGET_USE_FANCY_MATH_387 && can_create_pseudo_p ()" @@ -14755,29 +14755,29 @@ (set_attr "mode" "DI")]) (define_split - [(set (match_operand:DI 0 "register_operand" "") - (unspec:DI [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:DI 0 "register_operand") + (unspec:DI [(match_operand:XF 1 "register_operand")] UNSPEC_FIST)) - (clobber (match_operand:DI 2 "memory_operand" "")) - (clobber (match_scratch 3 ""))] + (clobber (match_operand:DI 2 "memory_operand")) + (clobber (match_scratch 3))] "reload_completed" [(parallel [(set (match_dup 2) (unspec:DI [(match_dup 1)] UNSPEC_FIST)) (clobber (match_dup 3))]) (set (match_dup 0) (match_dup 2))]) (define_split - [(set (match_operand:DI 0 "memory_operand" "") - (unspec:DI [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:DI 0 "memory_operand") + (unspec:DI [(match_operand:XF 1 "register_operand")] UNSPEC_FIST)) - (clobber (match_operand:DI 2 "memory_operand" "")) - (clobber (match_scratch 3 ""))] + (clobber (match_operand:DI 2 "memory_operand")) + (clobber (match_scratch 3))] "reload_completed" [(parallel [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_FIST)) (clobber (match_dup 3))])]) (define_insn_and_split "*fist<mode>2_1" - [(set (match_operand:SWI24 0 "register_operand" "") - (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:SWI24 0 "register_operand") + (unspec:SWI24 [(match_operand:XF 1 "register_operand")] UNSPEC_FIST))] "TARGET_USE_FANCY_MATH_387 && can_create_pseudo_p ()" @@ -14813,38 +14813,38 @@ (set_attr "mode" "<MODE>")]) (define_split - [(set (match_operand:SWI24 0 "register_operand" "") - (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:SWI24 0 "register_operand") + (unspec:SWI24 [(match_operand:XF 1 "register_operand")] UNSPEC_FIST)) - (clobber (match_operand:SWI24 2 "memory_operand" ""))] + (clobber (match_operand:SWI24 2 "memory_operand"))] "reload_completed" [(set (match_dup 2) (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST)) (set (match_dup 0) (match_dup 2))]) (define_split - [(set (match_operand:SWI24 0 "memory_operand" "") - (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:SWI24 0 "memory_operand") + (unspec:SWI24 [(match_operand:XF 1 "register_operand")] UNSPEC_FIST)) - (clobber (match_operand:SWI24 2 "memory_operand" ""))] + (clobber (match_operand:SWI24 2 "memory_operand"))] "reload_completed" [(set (match_dup 0) (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST))]) (define_expand "lrintxf<mode>2" - [(set (match_operand:SWI248x 0 "nonimmediate_operand" "") - (unspec:SWI248x [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:SWI248x 0 "nonimmediate_operand") + (unspec:SWI248x [(match_operand:XF 1 "register_operand")] UNSPEC_FIST))] "TARGET_USE_FANCY_MATH_387") (define_expand "lrint<MODEF:mode><SWI48x:mode>2" - [(set (match_operand:SWI48x 0 "nonimmediate_operand" "") - (unspec:SWI48x [(match_operand:MODEF 1 "register_operand" "")] + [(set (match_operand:SWI48x 0 "nonimmediate_operand") + (unspec:SWI48x [(match_operand:MODEF 1 "register_operand")] UNSPEC_FIX_NOTRUNC))] "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH && ((<SWI48x:MODE>mode != DImode) || TARGET_64BIT)") (define_expand "lround<X87MODEF:mode><SWI248x:mode>2" - [(match_operand:SWI248x 0 "nonimmediate_operand" "") - (match_operand:X87MODEF 1 "register_operand" "")] + [(match_operand:SWI248x 0 "nonimmediate_operand") + (match_operand:X87MODEF 1 "register_operand")] "(TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (<X87MODEF:MODE>mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14869,8 +14869,8 @@ ;; Rounding mode control word calculation could clobber FLAGS_REG. (define_insn_and_split "frndintxf2_floor" - [(set (match_operand:XF 0 "register_operand" "") - (unspec:XF [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:XF 0 "register_operand") + (unspec:XF [(match_operand:XF 1 "register_operand")] UNSPEC_FRNDINT_FLOOR)) (clobber (reg:CC FLAGS_REG))] "TARGET_USE_FANCY_MATH_387 @@ -14907,8 +14907,8 @@ (set_attr "mode" "XF")]) (define_expand "floorxf2" - [(use (match_operand:XF 0 "register_operand" "")) - (use (match_operand:XF 1 "register_operand" ""))] + [(use (match_operand:XF 0 "register_operand")) + (use (match_operand:XF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { @@ -14919,8 +14919,8 @@ }) (define_expand "floor<mode>2" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "register_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "register_operand"))] "(TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14959,8 +14959,8 @@ }) (define_insn_and_split "*fist<mode>2_floor_1" - [(set (match_operand:SWI248x 0 "nonimmediate_operand" "") - (unspec:SWI248x [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:SWI248x 0 "nonimmediate_operand") + (unspec:SWI248x [(match_operand:XF 1 "register_operand")] UNSPEC_FIST_FLOOR)) (clobber (reg:CC FLAGS_REG))] "TARGET_USE_FANCY_MATH_387 @@ -15020,13 +15020,13 @@ (set_attr "mode" "DI")]) (define_split - [(set (match_operand:DI 0 "register_operand" "") - (unspec:DI [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:DI 0 "register_operand") + (unspec:DI [(match_operand:XF 1 "register_operand")] UNSPEC_FIST_FLOOR)) - (use (match_operand:HI 2 "memory_operand" "")) - (use (match_operand:HI 3 "memory_operand" "")) - (clobber (match_operand:DI 4 "memory_operand" "")) - (clobber (match_scratch 5 ""))] + (use (match_operand:HI 2 "memory_operand")) + (use (match_operand:HI 3 "memory_operand")) + (clobber (match_operand:DI 4 "memory_operand")) + (clobber (match_scratch 5))] "reload_completed" [(parallel [(set (match_dup 4) (unspec:DI [(match_dup 1)] UNSPEC_FIST_FLOOR)) @@ -15036,13 +15036,13 @@ (set (match_dup 0) (match_dup 4))]) (define_split - [(set (match_operand:DI 0 "memory_operand" "") - (unspec:DI [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:DI 0 "memory_operand") + (unspec:DI [(match_operand:XF 1 "register_operand")] UNSPEC_FIST_FLOOR)) - (use (match_operand:HI 2 "memory_operand" "")) - (use (match_operand:HI 3 "memory_operand" "")) - (clobber (match_operand:DI 4 "memory_operand" "")) - (clobber (match_scratch 5 ""))] + (use (match_operand:HI 2 "memory_operand")) + (use (match_operand:HI 3 "memory_operand")) + (clobber (match_operand:DI 4 "memory_operand")) + (clobber (match_scratch 5))] "reload_completed" [(parallel [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_FIST_FLOOR)) @@ -15078,12 +15078,12 @@ (set_attr "mode" "<MODE>")]) (define_split - [(set (match_operand:SWI24 0 "register_operand" "") - (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:SWI24 0 "register_operand") + (unspec:SWI24 [(match_operand:XF 1 "register_operand")] UNSPEC_FIST_FLOOR)) - (use (match_operand:HI 2 "memory_operand" "")) - (use (match_operand:HI 3 "memory_operand" "")) - (clobber (match_operand:SWI24 4 "memory_operand" ""))] + (use (match_operand:HI 2 "memory_operand")) + (use (match_operand:HI 3 "memory_operand")) + (clobber (match_operand:SWI24 4 "memory_operand"))] "reload_completed" [(parallel [(set (match_dup 4) (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST_FLOOR)) @@ -15092,12 +15092,12 @@ (set (match_dup 0) (match_dup 4))]) (define_split - [(set (match_operand:SWI24 0 "memory_operand" "") - (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:SWI24 0 "memory_operand") + (unspec:SWI24 [(match_operand:XF 1 "register_operand")] UNSPEC_FIST_FLOOR)) - (use (match_operand:HI 2 "memory_operand" "")) - (use (match_operand:HI 3 "memory_operand" "")) - (clobber (match_operand:SWI24 4 "memory_operand" ""))] + (use (match_operand:HI 2 "memory_operand")) + (use (match_operand:HI 3 "memory_operand")) + (clobber (match_operand:SWI24 4 "memory_operand"))] "reload_completed" [(parallel [(set (match_dup 0) (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST_FLOOR)) @@ -15105,8 +15105,8 @@ (use (match_dup 3))])]) (define_expand "lfloorxf<mode>2" - [(parallel [(set (match_operand:SWI248x 0 "nonimmediate_operand" "") - (unspec:SWI248x [(match_operand:XF 1 "register_operand" "")] + [(parallel [(set (match_operand:SWI248x 0 "nonimmediate_operand") + (unspec:SWI248x [(match_operand:XF 1 "register_operand")] UNSPEC_FIST_FLOOR)) (clobber (reg:CC FLAGS_REG))])] "TARGET_USE_FANCY_MATH_387 @@ -15114,8 +15114,8 @@ && flag_unsafe_math_optimizations") (define_expand "lfloor<MODEF:mode><SWI48:mode>2" - [(match_operand:SWI48 0 "nonimmediate_operand" "") - (match_operand:MODEF 1 "register_operand" "")] + [(match_operand:SWI48 0 "nonimmediate_operand") + (match_operand:MODEF 1 "register_operand")] "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH && !flag_trapping_math" { @@ -15127,8 +15127,8 @@ ;; Rounding mode control word calculation could clobber FLAGS_REG. (define_insn_and_split "frndintxf2_ceil" - [(set (match_operand:XF 0 "register_operand" "") - (unspec:XF [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:XF 0 "register_operand") + (unspec:XF [(match_operand:XF 1 "register_operand")] UNSPEC_FRNDINT_CEIL)) (clobber (reg:CC FLAGS_REG))] "TARGET_USE_FANCY_MATH_387 @@ -15165,8 +15165,8 @@ (set_attr "mode" "XF")]) (define_expand "ceilxf2" - [(use (match_operand:XF 0 "register_operand" "")) - (use (match_operand:XF 1 "register_operand" ""))] + [(use (match_operand:XF 0 "register_operand")) + (use (match_operand:XF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { @@ -15177,8 +15177,8 @@ }) (define_expand "ceil<mode>2" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "register_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "register_operand"))] "(TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -15217,8 +15217,8 @@ }) (define_insn_and_split "*fist<mode>2_ceil_1" - [(set (match_operand:SWI248x 0 "nonimmediate_operand" "") - (unspec:SWI248x [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:SWI248x 0 "nonimmediate_operand") + (unspec:SWI248x [(match_operand:XF 1 "register_operand")] UNSPEC_FIST_CEIL)) (clobber (reg:CC FLAGS_REG))] "TARGET_USE_FANCY_MATH_387 @@ -15278,13 +15278,13 @@ (set_attr "mode" "DI")]) (define_split - [(set (match_operand:DI 0 "register_operand" "") - (unspec:DI [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:DI 0 "register_operand") + (unspec:DI [(match_operand:XF 1 "register_operand")] UNSPEC_FIST_CEIL)) - (use (match_operand:HI 2 "memory_operand" "")) - (use (match_operand:HI 3 "memory_operand" "")) - (clobber (match_operand:DI 4 "memory_operand" "")) - (clobber (match_scratch 5 ""))] + (use (match_operand:HI 2 "memory_operand")) + (use (match_operand:HI 3 "memory_operand")) + (clobber (match_operand:DI 4 "memory_operand")) + (clobber (match_scratch 5))] "reload_completed" [(parallel [(set (match_dup 4) (unspec:DI [(match_dup 1)] UNSPEC_FIST_CEIL)) @@ -15294,13 +15294,13 @@ (set (match_dup 0) (match_dup 4))]) (define_split - [(set (match_operand:DI 0 "memory_operand" "") - (unspec:DI [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:DI 0 "memory_operand") + (unspec:DI [(match_operand:XF 1 "register_operand")] UNSPEC_FIST_CEIL)) - (use (match_operand:HI 2 "memory_operand" "")) - (use (match_operand:HI 3 "memory_operand" "")) - (clobber (match_operand:DI 4 "memory_operand" "")) - (clobber (match_scratch 5 ""))] + (use (match_operand:HI 2 "memory_operand")) + (use (match_operand:HI 3 "memory_operand")) + (clobber (match_operand:DI 4 "memory_operand")) + (clobber (match_scratch 5))] "reload_completed" [(parallel [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_FIST_CEIL)) @@ -15336,12 +15336,12 @@ (set_attr "mode" "<MODE>")]) (define_split - [(set (match_operand:SWI24 0 "register_operand" "") - (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:SWI24 0 "register_operand") + (unspec:SWI24 [(match_operand:XF 1 "register_operand")] UNSPEC_FIST_CEIL)) - (use (match_operand:HI 2 "memory_operand" "")) - (use (match_operand:HI 3 "memory_operand" "")) - (clobber (match_operand:SWI24 4 "memory_operand" ""))] + (use (match_operand:HI 2 "memory_operand")) + (use (match_operand:HI 3 "memory_operand")) + (clobber (match_operand:SWI24 4 "memory_operand"))] "reload_completed" [(parallel [(set (match_dup 4) (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST_CEIL)) @@ -15350,12 +15350,12 @@ (set (match_dup 0) (match_dup 4))]) (define_split - [(set (match_operand:SWI24 0 "memory_operand" "") - (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:SWI24 0 "memory_operand") + (unspec:SWI24 [(match_operand:XF 1 "register_operand")] UNSPEC_FIST_CEIL)) - (use (match_operand:HI 2 "memory_operand" "")) - (use (match_operand:HI 3 "memory_operand" "")) - (clobber (match_operand:SWI24 4 "memory_operand" ""))] + (use (match_operand:HI 2 "memory_operand")) + (use (match_operand:HI 3 "memory_operand")) + (clobber (match_operand:SWI24 4 "memory_operand"))] "reload_completed" [(parallel [(set (match_dup 0) (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST_CEIL)) @@ -15363,8 +15363,8 @@ (use (match_dup 3))])]) (define_expand "lceilxf<mode>2" - [(parallel [(set (match_operand:SWI248x 0 "nonimmediate_operand" "") - (unspec:SWI248x [(match_operand:XF 1 "register_operand" "")] + [(parallel [(set (match_operand:SWI248x 0 "nonimmediate_operand") + (unspec:SWI248x [(match_operand:XF 1 "register_operand")] UNSPEC_FIST_CEIL)) (clobber (reg:CC FLAGS_REG))])] "TARGET_USE_FANCY_MATH_387 @@ -15372,8 +15372,8 @@ && flag_unsafe_math_optimizations") (define_expand "lceil<MODEF:mode><SWI48:mode>2" - [(match_operand:SWI48 0 "nonimmediate_operand" "") - (match_operand:MODEF 1 "register_operand" "")] + [(match_operand:SWI48 0 "nonimmediate_operand") + (match_operand:MODEF 1 "register_operand")] "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH && !flag_trapping_math" { @@ -15383,8 +15383,8 @@ ;; Rounding mode control word calculation could clobber FLAGS_REG. (define_insn_and_split "frndintxf2_trunc" - [(set (match_operand:XF 0 "register_operand" "") - (unspec:XF [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:XF 0 "register_operand") + (unspec:XF [(match_operand:XF 1 "register_operand")] UNSPEC_FRNDINT_TRUNC)) (clobber (reg:CC FLAGS_REG))] "TARGET_USE_FANCY_MATH_387 @@ -15421,8 +15421,8 @@ (set_attr "mode" "XF")]) (define_expand "btruncxf2" - [(use (match_operand:XF 0 "register_operand" "")) - (use (match_operand:XF 1 "register_operand" ""))] + [(use (match_operand:XF 0 "register_operand")) + (use (match_operand:XF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { @@ -15433,8 +15433,8 @@ }) (define_expand "btrunc<mode>2" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "register_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "register_operand"))] "(TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -15474,8 +15474,8 @@ ;; Rounding mode control word calculation could clobber FLAGS_REG. (define_insn_and_split "frndintxf2_mask_pm" - [(set (match_operand:XF 0 "register_operand" "") - (unspec:XF [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:XF 0 "register_operand") + (unspec:XF [(match_operand:XF 1 "register_operand")] UNSPEC_FRNDINT_MASK_PM)) (clobber (reg:CC FLAGS_REG))] "TARGET_USE_FANCY_MATH_387 @@ -15512,8 +15512,8 @@ (set_attr "mode" "XF")]) (define_expand "nearbyintxf2" - [(use (match_operand:XF 0 "register_operand" "")) - (use (match_operand:XF 1 "register_operand" ""))] + [(use (match_operand:XF 0 "register_operand")) + (use (match_operand:XF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { @@ -15522,8 +15522,8 @@ }) (define_expand "nearbyint<mode>2" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "register_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -15552,9 +15552,9 @@ (set_attr "mode" "<MODE>")]) (define_insn_and_split "fxam<mode>2_i387_with_temp" - [(set (match_operand:HI 0 "register_operand" "") + [(set (match_operand:HI 0 "register_operand") (unspec:HI - [(match_operand:MODEF 1 "memory_operand" "")] + [(match_operand:MODEF 1 "memory_operand")] UNSPEC_FXAM_MEM))] "TARGET_USE_FANCY_MATH_387 && can_create_pseudo_p ()" @@ -15573,8 +15573,8 @@ (set_attr "mode" "<MODE>")]) (define_expand "isinfxf2" - [(use (match_operand:SI 0 "register_operand" "")) - (use (match_operand:XF 1 "register_operand" ""))] + [(use (match_operand:SI 0 "register_operand")) + (use (match_operand:XF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && TARGET_C99_FUNCTIONS" { @@ -15599,8 +15599,8 @@ }) (define_expand "isinf<mode>2" - [(use (match_operand:SI 0 "register_operand" "")) - (use (match_operand:MODEF 1 "nonimmediate_operand" ""))] + [(use (match_operand:SI 0 "register_operand")) + (use (match_operand:MODEF 1 "nonimmediate_operand"))] "TARGET_USE_FANCY_MATH_387 && TARGET_C99_FUNCTIONS && !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)" @@ -15638,8 +15638,8 @@ }) (define_expand "signbitxf2" - [(use (match_operand:SI 0 "register_operand" "")) - (use (match_operand:XF 1 "register_operand" ""))] + [(use (match_operand:SI 0 "register_operand")) + (use (match_operand:XF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387" { rtx scratch = gen_reg_rtx (HImode); @@ -15664,8 +15664,8 @@ ;; Use movmskpd in SSE mode to avoid store forwarding stall ;; for 32bit targets and movq+shrq sequence for 64bit targets. (define_expand "signbitdf2" - [(use (match_operand:SI 0 "register_operand" "")) - (use (match_operand:DF 1 "register_operand" ""))] + [(use (match_operand:SI 0 "register_operand")) + (use (match_operand:DF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 || (SSE_FLOAT_MODE_P (DFmode) && TARGET_SSE_MATH)" { @@ -15686,8 +15686,8 @@ }) (define_expand "signbitsf2" - [(use (match_operand:SI 0 "register_operand" "")) - (use (match_operand:SF 1 "register_operand" ""))] + [(use (match_operand:SI 0 "register_operand")) + (use (match_operand:SF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && !(SSE_FLOAT_MODE_P (SFmode) && TARGET_SSE_MATH)" { @@ -15710,12 +15710,12 @@ (set_attr "modrm" "0")]) (define_expand "movmem<mode>" - [(use (match_operand:BLK 0 "memory_operand" "")) - (use (match_operand:BLK 1 "memory_operand" "")) - (use (match_operand:SWI48 2 "nonmemory_operand" "")) - (use (match_operand:SWI48 3 "const_int_operand" "")) - (use (match_operand:SI 4 "const_int_operand" "")) - (use (match_operand:SI 5 "const_int_operand" ""))] + [(use (match_operand:BLK 0 "memory_operand")) + (use (match_operand:BLK 1 "memory_operand")) + (use (match_operand:SWI48 2 "nonmemory_operand")) + (use (match_operand:SWI48 3 "const_int_operand")) + (use (match_operand:SI 4 "const_int_operand")) + (use (match_operand:SI 5 "const_int_operand"))] "" { if (ix86_expand_movmem (operands[0], operands[1], operands[2], operands[3], @@ -15729,11 +15729,11 @@ ;; Handle this case here to simplify previous expander. (define_expand "strmov" - [(set (match_dup 4) (match_operand 3 "memory_operand" "")) - (set (match_operand 1 "memory_operand" "") (match_dup 4)) - (parallel [(set (match_operand 0 "register_operand" "") (match_dup 5)) + [(set (match_dup 4) (match_operand 3 "memory_operand")) + (set (match_operand 1 "memory_operand") (match_dup 4)) + (parallel [(set (match_operand 0 "register_operand") (match_dup 5)) (clobber (reg:CC FLAGS_REG))]) - (parallel [(set (match_operand 2 "register_operand" "") (match_dup 6)) + (parallel [(set (match_operand 2 "register_operand") (match_dup 6)) (clobber (reg:CC FLAGS_REG))])] "" { @@ -15758,12 +15758,12 @@ }) (define_expand "strmov_singleop" - [(parallel [(set (match_operand 1 "memory_operand" "") - (match_operand 3 "memory_operand" "")) - (set (match_operand 0 "register_operand" "") - (match_operand 4 "" "")) - (set (match_operand 2 "register_operand" "") - (match_operand 5 "" ""))])] + [(parallel [(set (match_operand 1 "memory_operand") + (match_operand 3 "memory_operand")) + (set (match_operand 0 "register_operand") + (match_operand 4)) + (set (match_operand 2 "register_operand") + (match_operand 5))])] "" "ix86_current_function_needs_cld = 1;") @@ -15834,13 +15834,13 @@ (set_attr "mode" "QI")]) (define_expand "rep_mov" - [(parallel [(set (match_operand 4 "register_operand" "") (const_int 0)) - (set (match_operand 0 "register_operand" "") - (match_operand 5 "" "")) - (set (match_operand 2 "register_operand" "") - (match_operand 6 "" "")) - (set (match_operand 1 "memory_operand" "") - (match_operand 3 "memory_operand" "")) + [(parallel [(set (match_operand 4 "register_operand") (const_int 0)) + (set (match_operand 0 "register_operand") + (match_operand 5)) + (set (match_operand 2 "register_operand") + (match_operand 6)) + (set (match_operand 1 "memory_operand") + (match_operand 3 "memory_operand")) (use (match_dup 4))])] "" "ix86_current_function_needs_cld = 1;") @@ -15902,12 +15902,12 @@ (set_attr "mode" "QI")]) (define_expand "setmem<mode>" - [(use (match_operand:BLK 0 "memory_operand" "")) - (use (match_operand:SWI48 1 "nonmemory_operand" "")) - (use (match_operand:QI 2 "nonmemory_operand" "")) - (use (match_operand 3 "const_int_operand" "")) - (use (match_operand:SI 4 "const_int_operand" "")) - (use (match_operand:SI 5 "const_int_operand" ""))] + [(use (match_operand:BLK 0 "memory_operand")) + (use (match_operand:SWI48 1 "nonmemory_operand")) + (use (match_operand:QI 2 "nonmemory_operand")) + (use (match_operand 3 "const_int_operand")) + (use (match_operand:SI 4 "const_int_operand")) + (use (match_operand:SI 5 "const_int_operand"))] "" { if (ix86_expand_setmem (operands[0], operands[1], @@ -15922,9 +15922,9 @@ ;; Handle this case here to simplify previous expander. (define_expand "strset" - [(set (match_operand 1 "memory_operand" "") - (match_operand 2 "register_operand" "")) - (parallel [(set (match_operand 0 "register_operand" "") + [(set (match_operand 1 "memory_operand") + (match_operand 2 "register_operand")) + (parallel [(set (match_operand 0 "register_operand") (match_dup 3)) (clobber (reg:CC FLAGS_REG))])] "" @@ -15948,10 +15948,10 @@ }) (define_expand "strset_singleop" - [(parallel [(set (match_operand 1 "memory_operand" "") - (match_operand 2 "register_operand" "")) - (set (match_operand 0 "register_operand" "") - (match_operand 3 "" ""))])] + [(parallel [(set (match_operand 1 "memory_operand") + (match_operand 2 "register_operand")) + (set (match_operand 0 "register_operand") + (match_operand 3))])] "" "ix86_current_function_needs_cld = 1;") @@ -16010,11 +16010,11 @@ (set_attr "mode" "QI")]) (define_expand "rep_stos" - [(parallel [(set (match_operand 1 "register_operand" "") (const_int 0)) - (set (match_operand 0 "register_operand" "") - (match_operand 4 "" "")) - (set (match_operand 2 "memory_operand" "") (const_int 0)) - (use (match_operand 3 "register_operand" "")) + [(parallel [(set (match_operand 1 "register_operand") (const_int 0)) + (set (match_operand 0 "register_operand") + (match_operand 4)) + (set (match_operand 2 "memory_operand") (const_int 0)) + (use (match_operand 3 "register_operand")) (use (match_dup 1))])] "" "ix86_current_function_needs_cld = 1;") @@ -16076,11 +16076,11 @@ (set_attr "mode" "QI")]) (define_expand "cmpstrnsi" - [(set (match_operand:SI 0 "register_operand" "") - (compare:SI (match_operand:BLK 1 "general_operand" "") - (match_operand:BLK 2 "general_operand" ""))) - (use (match_operand 3 "general_operand" "")) - (use (match_operand 4 "immediate_operand" ""))] + [(set (match_operand:SI 0 "register_operand") + (compare:SI (match_operand:BLK 1 "general_operand") + (match_operand:BLK 2 "general_operand"))) + (use (match_operand 3 "general_operand")) + (use (match_operand 4 "immediate_operand"))] "" { rtx addr1, addr2, out, outlow, count, countreg, align; @@ -16150,7 +16150,7 @@ (gtu:QI (reg:CC FLAGS_REG) (const_int 0))) (set (match_dup 2) (ltu:QI (reg:CC FLAGS_REG) (const_int 0))) - (parallel [(set (match_operand:QI 0 "register_operand" "") + (parallel [(set (match_operand:QI 0 "register_operand") (minus:QI (match_dup 1) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])] @@ -16165,12 +16165,12 @@ (define_expand "cmpstrnqi_nz_1" [(parallel [(set (reg:CC FLAGS_REG) - (compare:CC (match_operand 4 "memory_operand" "") - (match_operand 5 "memory_operand" ""))) - (use (match_operand 2 "register_operand" "")) - (use (match_operand:SI 3 "immediate_operand" "")) - (clobber (match_operand 0 "register_operand" "")) - (clobber (match_operand 1 "register_operand" "")) + (compare:CC (match_operand 4 "memory_operand") + (match_operand 5 "memory_operand"))) + (use (match_operand 2 "register_operand")) + (use (match_operand:SI 3 "immediate_operand")) + (clobber (match_operand 0 "register_operand")) + (clobber (match_operand 1 "register_operand")) (clobber (match_dup 2))])] "" "ix86_current_function_needs_cld = 1;") @@ -16199,15 +16199,15 @@ (define_expand "cmpstrnqi_1" [(parallel [(set (reg:CC FLAGS_REG) - (if_then_else:CC (ne (match_operand 2 "register_operand" "") + (if_then_else:CC (ne (match_operand 2 "register_operand") (const_int 0)) - (compare:CC (match_operand 4 "memory_operand" "") - (match_operand 5 "memory_operand" "")) + (compare:CC (match_operand 4 "memory_operand") + (match_operand 5 "memory_operand")) (const_int 0))) - (use (match_operand:SI 3 "immediate_operand" "")) + (use (match_operand:SI 3 "immediate_operand")) (use (reg:CC FLAGS_REG)) - (clobber (match_operand 0 "register_operand" "")) - (clobber (match_operand 1 "register_operand" "")) + (clobber (match_operand 0 "register_operand")) + (clobber (match_operand 1 "register_operand")) (clobber (match_dup 2))])] "" "ix86_current_function_needs_cld = 1;") @@ -16236,10 +16236,10 @@ (set_attr "prefix_rep" "1")]) (define_expand "strlen<mode>" - [(set (match_operand:P 0 "register_operand" "") - (unspec:P [(match_operand:BLK 1 "general_operand" "") - (match_operand:QI 2 "immediate_operand" "") - (match_operand 3 "immediate_operand" "")] + [(set (match_operand:P 0 "register_operand") + (unspec:P [(match_operand:BLK 1 "general_operand") + (match_operand:QI 2 "immediate_operand") + (match_operand 3 "immediate_operand")] UNSPEC_SCAS))] "" { @@ -16250,9 +16250,9 @@ }) (define_expand "strlenqi_1" - [(parallel [(set (match_operand 0 "register_operand" "") - (match_operand 2 "" "")) - (clobber (match_operand 1 "register_operand" "")) + [(parallel [(set (match_operand 0 "register_operand") + (match_operand 2)) + (clobber (match_operand 1 "register_operand")) (clobber (reg:CC FLAGS_REG))])] "" "ix86_current_function_needs_cld = 1;") @@ -16293,16 +16293,16 @@ (define_peephole2 [(parallel[ (set (reg:CC FLAGS_REG) - (compare:CC (mem:BLK (match_operand 4 "register_operand" "")) - (mem:BLK (match_operand 5 "register_operand" "")))) - (use (match_operand 6 "register_operand" "")) - (use (match_operand:SI 3 "immediate_operand" "")) - (clobber (match_operand 0 "register_operand" "")) - (clobber (match_operand 1 "register_operand" "")) - (clobber (match_operand 2 "register_operand" ""))]) - (set (match_operand:QI 7 "register_operand" "") + (compare:CC (mem:BLK (match_operand 4 "register_operand")) + (mem:BLK (match_operand 5 "register_operand")))) + (use (match_operand 6 "register_operand")) + (use (match_operand:SI 3 "immediate_operand")) + (clobber (match_operand 0 "register_operand")) + (clobber (match_operand 1 "register_operand")) + (clobber (match_operand 2 "register_operand"))]) + (set (match_operand:QI 7 "register_operand") (gtu:QI (reg:CC FLAGS_REG) (const_int 0))) - (set (match_operand:QI 8 "register_operand" "") + (set (match_operand:QI 8 "register_operand") (ltu:QI (reg:CC FLAGS_REG) (const_int 0))) (set (reg FLAGS_REG) (compare (match_dup 7) (match_dup 8))) @@ -16322,19 +16322,19 @@ (define_peephole2 [(parallel[ (set (reg:CC FLAGS_REG) - (if_then_else:CC (ne (match_operand 6 "register_operand" "") + (if_then_else:CC (ne (match_operand 6 "register_operand") (const_int 0)) - (compare:CC (mem:BLK (match_operand 4 "register_operand" "")) - (mem:BLK (match_operand 5 "register_operand" ""))) + (compare:CC (mem:BLK (match_operand 4 "register_operand")) + (mem:BLK (match_operand 5 "register_operand"))) (const_int 0))) - (use (match_operand:SI 3 "immediate_operand" "")) + (use (match_operand:SI 3 "immediate_operand")) (use (reg:CC FLAGS_REG)) - (clobber (match_operand 0 "register_operand" "")) - (clobber (match_operand 1 "register_operand" "")) - (clobber (match_operand 2 "register_operand" ""))]) - (set (match_operand:QI 7 "register_operand" "") + (clobber (match_operand 0 "register_operand")) + (clobber (match_operand 1 "register_operand")) + (clobber (match_operand 2 "register_operand"))]) + (set (match_operand:QI 7 "register_operand") (gtu:QI (reg:CC FLAGS_REG) (const_int 0))) - (set (match_operand:QI 8 "register_operand" "") + (set (match_operand:QI 8 "register_operand") (ltu:QI (reg:CC FLAGS_REG) (const_int 0))) (set (reg FLAGS_REG) (compare (match_dup 7) (match_dup 8))) @@ -16356,10 +16356,10 @@ ;; Conditional move instructions. (define_expand "mov<mode>cc" - [(set (match_operand:SWIM 0 "register_operand" "") - (if_then_else:SWIM (match_operand 1 "ordered_comparison_operator" "") - (match_operand:SWIM 2 "<general_operand>" "") - (match_operand:SWIM 3 "<general_operand>" "")))] + [(set (match_operand:SWIM 0 "register_operand") + (if_then_else:SWIM (match_operand 1 "ordered_comparison_operator") + (match_operand:SWIM 2 "<general_operand>") + (match_operand:SWIM 3 "<general_operand>")))] "" "if (ix86_expand_int_movcc (operands)) DONE; else FAIL;") @@ -16369,10 +16369,10 @@ (define_expand "x86_mov<mode>cc_0_m1" [(parallel - [(set (match_operand:SWI48 0 "register_operand" "") + [(set (match_operand:SWI48 0 "register_operand") (if_then_else:SWI48 (match_operator:SWI48 2 "ix86_carry_flag_operator" - [(match_operand 1 "flags_reg_operand" "") + [(match_operand 1 "flags_reg_operand") (const_int 0)]) (const_int -1) (const_int 0))) @@ -16444,7 +16444,7 @@ (define_insn_and_split "*movqicc_noc" [(set (match_operand:QI 0 "register_operand" "=r,r") (if_then_else:QI (match_operator 1 "ix86_comparison_operator" - [(match_operand 4 "flags_reg_operand" "") + [(match_operand 4 "flags_reg_operand") (const_int 0)]) (match_operand:QI 2 "register_operand" "r,0") (match_operand:QI 3 "register_operand" "0,r")))] @@ -16462,11 +16462,11 @@ (set_attr "mode" "SI")]) (define_expand "mov<mode>cc" - [(set (match_operand:X87MODEF 0 "register_operand" "") + [(set (match_operand:X87MODEF 0 "register_operand") (if_then_else:X87MODEF - (match_operand 1 "ix86_fp_comparison_operator" "") - (match_operand:X87MODEF 2 "register_operand" "") - (match_operand:X87MODEF 3 "register_operand" "")))] + (match_operand 1 "ix86_fp_comparison_operator") + (match_operand:X87MODEF 2 "register_operand") + (match_operand:X87MODEF 3 "register_operand")))] "(TARGET_80387 && TARGET_CMOVE) || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)" "if (ix86_expand_fp_movcc (operands)) DONE; else FAIL;") @@ -16517,12 +16517,12 @@ (set_attr "mode" "DF,DF,DI,DI")]) (define_split - [(set (match_operand:DF 0 "register_and_not_any_fp_reg_operand" "") + [(set (match_operand:DF 0 "register_and_not_any_fp_reg_operand") (if_then_else:DF (match_operator 1 "fcmov_comparison_operator" - [(match_operand 4 "flags_reg_operand" "") + [(match_operand 4 "flags_reg_operand") (const_int 0)]) - (match_operand:DF 2 "nonimmediate_operand" "") - (match_operand:DF 3 "nonimmediate_operand" "")))] + (match_operand:DF 2 "nonimmediate_operand") + (match_operand:DF 3 "nonimmediate_operand")))] "!TARGET_64BIT && reload_completed" [(set (match_dup 2) (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)]) @@ -16629,12 +16629,12 @@ ;; ;; Actually we only match the last two instructions for simplicity. (define_peephole2 - [(set (match_operand 0 "fp_register_operand" "") - (match_operand 1 "fp_register_operand" "")) + [(set (match_operand 0 "fp_register_operand") + (match_operand 1 "fp_register_operand")) (set (match_dup 0) (match_operator 2 "binary_fp_operator" [(match_dup 0) - (match_operand 3 "memory_operand" "")]))] + (match_operand 3 "memory_operand")]))] "REGNO (operands[0]) != REGNO (operands[1])" [(set (match_dup 0) (match_dup 3)) (set (match_dup 0) (match_dup 4))] @@ -16656,10 +16656,10 @@ ;; Conditional addition patterns (define_expand "add<mode>cc" - [(match_operand:SWI 0 "register_operand" "") - (match_operand 1 "ordered_comparison_operator" "") - (match_operand:SWI 2 "register_operand" "") - (match_operand:SWI 3 "const_int_operand" "")] + [(match_operand:SWI 0 "register_operand") + (match_operand 1 "ordered_comparison_operator") + (match_operand:SWI 2 "register_operand") + (match_operand:SWI 3 "const_int_operand")] "" "if (ix86_expand_int_addcc (operands)) DONE; else FAIL;") @@ -16704,7 +16704,7 @@ (cond [(and (eq_attr "alternative" "0") (not (match_test "TARGET_OPT_AGU"))) (const_string "alu") - (match_operand:<MODE> 2 "const0_operand" "") + (match_operand:<MODE> 2 "const0_operand") (const_string "imov") ] (const_string "lea"))) @@ -16712,7 +16712,7 @@ (cond [(eq_attr "type" "imov") (const_string "0") (and (eq_attr "type" "alu") - (match_operand 2 "const128_operand" "")) + (match_operand 2 "const128_operand")) (const_string "1") ] (const_string "*"))) @@ -16740,8 +16740,8 @@ (set_attr "length" "5")]) (define_expand "allocate_stack" - [(match_operand 0 "register_operand" "") - (match_operand 1 "general_operand" "")] + [(match_operand 0 "register_operand") + (match_operand 1 "general_operand")] "ix86_target_stack_probe ()" { rtx x; @@ -16777,7 +16777,7 @@ ;; Use IOR for stack probes, this is shorter. (define_expand "probe_stack" - [(match_operand 0 "memory_operand" "")] + [(match_operand 0 "memory_operand")] "" { rtx (*gen_ior3) (rtx, rtx, rtx); @@ -16812,7 +16812,7 @@ [(set_attr "type" "multi")]) (define_expand "builtin_setjmp_receiver" - [(label_ref (match_operand 0 "" ""))] + [(label_ref (match_operand 0))] "!TARGET_64BIT && flag_pic" { #if TARGET_MACHO @@ -16835,10 +16835,10 @@ ;; Avoid redundant prefixes by splitting HImode arithmetic to SImode. (define_split - [(set (match_operand 0 "register_operand" "") + [(set (match_operand 0 "register_operand") (match_operator 3 "promotable_binary_operator" - [(match_operand 1 "register_operand" "") - (match_operand 2 "aligned_operand" "")])) + [(match_operand 1 "register_operand") + (match_operand 2 "aligned_operand")])) (clobber (reg:CC FLAGS_REG))] "! TARGET_PARTIAL_REG_STALL && reload_completed && ((GET_MODE (operands[0]) == HImode @@ -16864,12 +16864,12 @@ ; instruction size is unchanged, except in the %eax case for ; which it is increased by one byte, hence the ! optimize_size. (define_split - [(set (match_operand 0 "flags_reg_operand" "") + [(set (match_operand 0 "flags_reg_operand") (match_operator 2 "compare_operator" - [(and (match_operand 3 "aligned_operand" "") - (match_operand 4 "const_int_operand" "")) + [(and (match_operand 3 "aligned_operand") + (match_operand 4 "const_int_operand")) (const_int 0)])) - (set (match_operand 1 "register_operand" "") + (set (match_operand 1 "register_operand") (and (match_dup 3) (match_dup 4)))] "! TARGET_PARTIAL_REG_STALL && reload_completed && optimize_insn_for_speed_p () @@ -16895,10 +16895,10 @@ ; the instruction size would at least double, which is not what we ; want even with ! optimize_size. (define_split - [(set (match_operand 0 "flags_reg_operand" "") + [(set (match_operand 0 "flags_reg_operand") (match_operator 1 "compare_operator" - [(and (match_operand:HI 2 "aligned_operand" "") - (match_operand:HI 3 "const_int_operand" "")) + [(and (match_operand:HI 2 "aligned_operand") + (match_operand:HI 3 "const_int_operand")) (const_int 0)]))] "! TARGET_PARTIAL_REG_STALL && reload_completed && ! TARGET_FAST_PREFIX @@ -16916,8 +16916,8 @@ }) (define_split - [(set (match_operand 0 "register_operand" "") - (neg (match_operand 1 "register_operand" ""))) + [(set (match_operand 0 "register_operand") + (neg (match_operand 1 "register_operand"))) (clobber (reg:CC FLAGS_REG))] "! TARGET_PARTIAL_REG_STALL && reload_completed && (GET_MODE (operands[0]) == HImode @@ -16933,8 +16933,8 @@ }) (define_split - [(set (match_operand 0 "register_operand" "") - (not (match_operand 1 "register_operand" "")))] + [(set (match_operand 0 "register_operand") + (not (match_operand 1 "register_operand")))] "! TARGET_PARTIAL_REG_STALL && reload_completed && (GET_MODE (operands[0]) == HImode || (GET_MODE (operands[0]) == QImode @@ -16948,11 +16948,11 @@ }) (define_split - [(set (match_operand 0 "register_operand" "") + [(set (match_operand 0 "register_operand") (if_then_else (match_operator 1 "ordered_comparison_operator" [(reg FLAGS_REG) (const_int 0)]) - (match_operand 2 "register_operand" "") - (match_operand 3 "register_operand" "")))] + (match_operand 2 "register_operand") + (match_operand 3 "register_operand")))] "! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE && (GET_MODE (operands[0]) == HImode || (GET_MODE (operands[0]) == QImode @@ -16971,8 +16971,8 @@ ;; Don't push memory operands (define_peephole2 - [(set (match_operand:SWI 0 "push_operand" "") - (match_operand:SWI 1 "memory_operand" "")) + [(set (match_operand:SWI 0 "push_operand") + (match_operand:SWI 1 "memory_operand")) (match_scratch:SWI 2 "<r>")] "!(TARGET_PUSH_MEMORY || optimize_insn_for_size_p ()) && !RTX_FRAME_RELATED_P (peep2_next_insn (0))" @@ -16982,8 +16982,8 @@ ;; We need to handle SFmode only, because DFmode and XFmode are split to ;; SImode pushes. (define_peephole2 - [(set (match_operand:SF 0 "push_operand" "") - (match_operand:SF 1 "memory_operand" "")) + [(set (match_operand:SF 0 "push_operand") + (match_operand:SF 1 "memory_operand")) (match_scratch:SF 2 "r")] "!(TARGET_PUSH_MEMORY || optimize_insn_for_size_p ()) && !RTX_FRAME_RELATED_P (peep2_next_insn (0))" @@ -16994,7 +16994,7 @@ ;; gets too big. (define_peephole2 [(match_scratch:SWI124 1 "<r>") - (set (match_operand:SWI124 0 "memory_operand" "") + (set (match_operand:SWI124 0 "memory_operand") (const_int 0))] "optimize_insn_for_speed_p () && !TARGET_USE_MOV0 @@ -17008,8 +17008,8 @@ (define_peephole2 [(match_scratch:SWI124 2 "<r>") - (set (match_operand:SWI124 0 "memory_operand" "") - (match_operand:SWI124 1 "immediate_operand" ""))] + (set (match_operand:SWI124 0 "memory_operand") + (match_operand:SWI124 1 "immediate_operand"))] "optimize_insn_for_speed_p () && TARGET_SPLIT_LONG_MOVES && get_attr_length (insn) >= ix86_cur_cost ()->large_insn" @@ -17018,9 +17018,9 @@ ;; Don't compare memory with zero, load and use a test instead. (define_peephole2 - [(set (match_operand 0 "flags_reg_operand" "") + [(set (match_operand 0 "flags_reg_operand") (match_operator 1 "compare_operator" - [(match_operand:SI 2 "memory_operand" "") + [(match_operand:SI 2 "memory_operand") (const_int 0)])) (match_scratch:SI 3 "r")] "optimize_insn_for_speed_p () && ix86_match_ccmode (insn, CCNOmode)" @@ -17039,8 +17039,8 @@ ;; lifetime information then. (define_peephole2 - [(set (match_operand:SWI124 0 "nonimmediate_operand" "") - (not:SWI124 (match_operand:SWI124 1 "nonimmediate_operand" "")))] + [(set (match_operand:SWI124 0 "nonimmediate_operand") + (not:SWI124 (match_operand:SWI124 1 "nonimmediate_operand")))] "optimize_insn_for_speed_p () && ((TARGET_NOT_UNPAIRABLE && (!MEM_P (operands[0]) @@ -17060,10 +17060,10 @@ ;; versions if we're concerned about partial register stalls. (define_peephole2 - [(set (match_operand 0 "flags_reg_operand" "") + [(set (match_operand 0 "flags_reg_operand") (match_operator 1 "compare_operator" - [(and:SI (match_operand:SI 2 "register_operand" "") - (match_operand:SI 3 "immediate_operand" "")) + [(and:SI (match_operand:SI 2 "register_operand") + (match_operand:SI 3 "immediate_operand")) (const_int 0)]))] "ix86_match_ccmode (insn, CCNOmode) && (true_regnum (operands[2]) != AX_REG @@ -17080,10 +17080,10 @@ ;; on ! TARGET_PARTIAL_REG_STALL (define_peephole2 - [(set (match_operand 0 "flags_reg_operand" "") + [(set (match_operand 0 "flags_reg_operand") (match_operator 1 "compare_operator" - [(and:QI (match_operand:QI 2 "register_operand" "") - (match_operand:QI 3 "immediate_operand" "")) + [(and:QI (match_operand:QI 2 "register_operand") + (match_operand:QI 3 "immediate_operand")) (const_int 0)]))] "! TARGET_PARTIAL_REG_STALL && ix86_match_ccmode (insn, CCNOmode) @@ -17097,14 +17097,14 @@ (and:QI (match_dup 2) (match_dup 3)))])]) (define_peephole2 - [(set (match_operand 0 "flags_reg_operand" "") + [(set (match_operand 0 "flags_reg_operand") (match_operator 1 "compare_operator" [(and:SI (zero_extract:SI - (match_operand 2 "ext_register_operand" "") + (match_operand 2 "ext_register_operand") (const_int 8) (const_int 8)) - (match_operand 3 "const_int_operand" "")) + (match_operand 3 "const_int_operand")) (const_int 0)]))] "! TARGET_PARTIAL_REG_STALL && ix86_match_ccmode (insn, CCNOmode) @@ -17132,10 +17132,10 @@ ;; Don't do logical operations with memory inputs. (define_peephole2 [(match_scratch:SI 2 "r") - (parallel [(set (match_operand:SI 0 "register_operand" "") + (parallel [(set (match_operand:SI 0 "register_operand") (match_operator:SI 3 "arith_or_logical_operator" [(match_dup 0) - (match_operand:SI 1 "memory_operand" "")])) + (match_operand:SI 1 "memory_operand")])) (clobber (reg:CC FLAGS_REG))])] "!(TARGET_READ_MODIFY || optimize_insn_for_size_p ())" [(set (match_dup 2) (match_dup 1)) @@ -17145,9 +17145,9 @@ (define_peephole2 [(match_scratch:SI 2 "r") - (parallel [(set (match_operand:SI 0 "register_operand" "") + (parallel [(set (match_operand:SI 0 "register_operand") (match_operator:SI 3 "arith_or_logical_operator" - [(match_operand:SI 1 "memory_operand" "") + [(match_operand:SI 1 "memory_operand") (match_dup 0)])) (clobber (reg:CC FLAGS_REG))])] "!(TARGET_READ_MODIFY || optimize_insn_for_size_p ())" @@ -17160,12 +17160,12 @@ ;; refers to the destination of the load! (define_peephole2 - [(set (match_operand:SI 0 "register_operand" "") - (match_operand:SI 1 "register_operand" "")) + [(set (match_operand:SI 0 "register_operand") + (match_operand:SI 1 "register_operand")) (parallel [(set (match_dup 0) (match_operator:SI 3 "commutative_operator" [(match_dup 0) - (match_operand:SI 2 "memory_operand" "")])) + (match_operand:SI 2 "memory_operand")])) (clobber (reg:CC FLAGS_REG))])] "REGNO (operands[0]) != REGNO (operands[1]) && GENERAL_REGNO_P (REGNO (operands[0])) @@ -17177,12 +17177,12 @@ "operands[4] = replace_rtx (operands[2], operands[0], operands[1]);") (define_peephole2 - [(set (match_operand 0 "register_operand" "") - (match_operand 1 "register_operand" "")) + [(set (match_operand 0 "register_operand") + (match_operand 1 "register_operand")) (set (match_dup 0) (match_operator 3 "commutative_operator" [(match_dup 0) - (match_operand 2 "memory_operand" "")]))] + (match_operand 2 "memory_operand")]))] "REGNO (operands[0]) != REGNO (operands[1]) && ((MMX_REG_P (operands[0]) && MMX_REG_P (operands[1])) || (SSE_REG_P (operands[0]) && SSE_REG_P (operands[1])))" @@ -17198,10 +17198,10 @@ (define_peephole2 [(match_scratch:SI 2 "r") - (parallel [(set (match_operand:SI 0 "memory_operand" "") + (parallel [(set (match_operand:SI 0 "memory_operand") (match_operator:SI 3 "arith_or_logical_operator" [(match_dup 0) - (match_operand:SI 1 "nonmemory_operand" "")])) + (match_operand:SI 1 "nonmemory_operand")])) (clobber (reg:CC FLAGS_REG))])] "!(TARGET_READ_MODIFY_WRITE || optimize_insn_for_size_p ()) /* Do not split stack checking probes. */ @@ -17214,9 +17214,9 @@ (define_peephole2 [(match_scratch:SI 2 "r") - (parallel [(set (match_operand:SI 0 "memory_operand" "") + (parallel [(set (match_operand:SI 0 "memory_operand") (match_operator:SI 3 "arith_or_logical_operator" - [(match_operand:SI 1 "nonmemory_operand" "") + [(match_operand:SI 1 "nonmemory_operand") (match_dup 0)])) (clobber (reg:CC FLAGS_REG))])] "!(TARGET_READ_MODIFY_WRITE || optimize_insn_for_size_p ()) @@ -17231,12 +17231,12 @@ ;; Attempt to use arith or logical operations with memory outputs with ;; setting of flags. (define_peephole2 - [(set (match_operand:SWI 0 "register_operand" "") - (match_operand:SWI 1 "memory_operand" "")) + [(set (match_operand:SWI 0 "register_operand") + (match_operand:SWI 1 "memory_operand")) (parallel [(set (match_dup 0) (match_operator:SWI 3 "plusminuslogic_operator" [(match_dup 0) - (match_operand:SWI 2 "<nonmemory_operand>" "")])) + (match_operand:SWI 2 "<nonmemory_operand>")])) (clobber (reg:CC FLAGS_REG))]) (set (match_dup 1) (match_dup 0)) (set (reg FLAGS_REG) (compare (match_dup 0) (const_int 0)))] @@ -17260,10 +17260,10 @@ }) (define_peephole2 - [(parallel [(set (match_operand:SWI 0 "register_operand" "") + [(parallel [(set (match_operand:SWI 0 "register_operand") (match_operator:SWI 2 "plusminuslogic_operator" [(match_dup 0) - (match_operand:SWI 1 "memory_operand" "")])) + (match_operand:SWI 1 "memory_operand")])) (clobber (reg:CC FLAGS_REG))]) (set (match_dup 1) (match_dup 0)) (set (reg FLAGS_REG) (compare (match_dup 0) (const_int 0)))] @@ -17287,12 +17287,12 @@ }) (define_peephole2 - [(set (match_operand:SWI12 0 "register_operand" "") - (match_operand:SWI12 1 "memory_operand" "")) - (parallel [(set (match_operand:SI 4 "register_operand" "") + [(set (match_operand:SWI12 0 "register_operand") + (match_operand:SWI12 1 "memory_operand")) + (parallel [(set (match_operand:SI 4 "register_operand") (match_operator:SI 3 "plusminuslogic_operator" [(match_dup 4) - (match_operand:SI 2 "nonmemory_operand" "")])) + (match_operand:SI 2 "nonmemory_operand")])) (clobber (reg:CC FLAGS_REG))]) (set (match_dup 1) (match_dup 0)) (set (reg FLAGS_REG) (compare (match_dup 0) (const_int 0)))] @@ -17324,8 +17324,8 @@ ;; Attempt to always use XOR for zeroing registers. (define_peephole2 - [(set (match_operand 0 "register_operand" "") - (match_operand 1 "const0_operand" ""))] + [(set (match_operand 0 "register_operand") + (match_operand 1 "const0_operand"))] "GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD && (! TARGET_USE_MOV0 || optimize_insn_for_size_p ()) && GENERAL_REG_P (operands[0]) @@ -17335,7 +17335,7 @@ "operands[0] = gen_lowpart (word_mode, operands[0]);") (define_peephole2 - [(set (strict_low_part (match_operand 0 "register_operand" "")) + [(set (strict_low_part (match_operand 0 "register_operand")) (const_int 0))] "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode) @@ -17346,7 +17346,7 @@ ;; For HI, SI and DI modes, or $-1,reg is smaller than mov $-1,reg. (define_peephole2 - [(set (match_operand:SWI248 0 "register_operand" "") + [(set (match_operand:SWI248 0 "register_operand") (const_int -1))] "(optimize_insn_for_size_p () || TARGET_MOVE_M1_VIA_OR) && peep2_regno_dead_p (0, FLAGS_REG)" @@ -17361,17 +17361,17 @@ ;; These can be created by move expanders. (define_peephole2 - [(set (match_operand:SWI48 0 "register_operand" "") + [(set (match_operand:SWI48 0 "register_operand") (plus:SWI48 (match_dup 0) - (match_operand:SWI48 1 "<nonmemory_operand>" "")))] + (match_operand:SWI48 1 "<nonmemory_operand>")))] "peep2_regno_dead_p (0, FLAGS_REG)" [(parallel [(set (match_dup 0) (plus:SWI48 (match_dup 0) (match_dup 1))) (clobber (reg:CC FLAGS_REG))])]) (define_peephole2 - [(set (match_operand:SI 0 "register_operand" "") - (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "") - (match_operand:DI 2 "nonmemory_operand" "")) 0))] + [(set (match_operand:SI 0 "register_operand") + (subreg:SI (plus:DI (match_operand:DI 1 "register_operand") + (match_operand:DI 2 "nonmemory_operand")) 0))] "TARGET_64BIT && peep2_regno_dead_p (0, FLAGS_REG) && REGNO (operands[0]) == REGNO (operands[1])" @@ -17380,9 +17380,9 @@ "operands[2] = gen_lowpart (SImode, operands[2]);") (define_peephole2 - [(set (match_operand:SWI48 0 "register_operand" "") + [(set (match_operand:SWI48 0 "register_operand") (mult:SWI48 (match_dup 0) - (match_operand:SWI48 1 "const_int_operand" "")))] + (match_operand:SWI48 1 "const_int_operand")))] "exact_log2 (INTVAL (operands[1])) >= 0 && peep2_regno_dead_p (0, FLAGS_REG)" [(parallel [(set (match_dup 0) (ashift:SWI48 (match_dup 0) (match_dup 2))) @@ -17390,9 +17390,9 @@ "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));") (define_peephole2 - [(set (match_operand:SI 0 "register_operand" "") - (subreg:SI (mult:DI (match_operand:DI 1 "register_operand" "") - (match_operand:DI 2 "const_int_operand" "")) 0))] + [(set (match_operand:SI 0 "register_operand") + (subreg:SI (mult:DI (match_operand:DI 1 "register_operand") + (match_operand:DI 2 "const_int_operand")) 0))] "TARGET_64BIT && exact_log2 (INTVAL (operands[2])) >= 0 && REGNO (operands[0]) == REGNO (operands[1]) @@ -17425,7 +17425,7 @@ [(match_scratch:W 1 "r") (parallel [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) - (match_operand:P 0 "const_int_operand" ""))) + (match_operand:P 0 "const_int_operand"))) (clobber (reg:CC FLAGS_REG)) (clobber (mem:BLK (scratch)))])] "(TARGET_SINGLE_PUSH || optimize_insn_for_size_p ()) @@ -17438,7 +17438,7 @@ [(match_scratch:W 1 "r") (parallel [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) - (match_operand:P 0 "const_int_operand" ""))) + (match_operand:P 0 "const_int_operand"))) (clobber (reg:CC FLAGS_REG)) (clobber (mem:BLK (scratch)))])] "(TARGET_DOUBLE_PUSH || optimize_insn_for_size_p ()) @@ -17453,7 +17453,7 @@ [(match_scratch:W 1 "r") (parallel [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) - (match_operand:P 0 "const_int_operand" ""))) + (match_operand:P 0 "const_int_operand"))) (clobber (reg:CC FLAGS_REG))])] "(TARGET_SINGLE_PUSH || optimize_insn_for_size_p ()) && INTVAL (operands[0]) == -GET_MODE_SIZE (word_mode)" @@ -17464,7 +17464,7 @@ [(match_scratch:W 1 "r") (parallel [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) - (match_operand:P 0 "const_int_operand" ""))) + (match_operand:P 0 "const_int_operand"))) (clobber (reg:CC FLAGS_REG))])] "(TARGET_DOUBLE_PUSH || optimize_insn_for_size_p ()) && INTVAL (operands[0]) == -2*GET_MODE_SIZE (word_mode)" @@ -17477,7 +17477,7 @@ [(match_scratch:W 1 "r") (parallel [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) - (match_operand:P 0 "const_int_operand" ""))) + (match_operand:P 0 "const_int_operand"))) (clobber (reg:CC FLAGS_REG)) (clobber (mem:BLK (scratch)))])] "(TARGET_SINGLE_POP || optimize_insn_for_size_p ()) @@ -17492,7 +17492,7 @@ (match_scratch:W 2 "r") (parallel [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) - (match_operand:P 0 "const_int_operand" ""))) + (match_operand:P 0 "const_int_operand"))) (clobber (reg:CC FLAGS_REG)) (clobber (mem:BLK (scratch)))])] "(TARGET_DOUBLE_POP || optimize_insn_for_size_p ()) @@ -17505,7 +17505,7 @@ [(match_scratch:W 1 "r") (parallel [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) - (match_operand:P 0 "const_int_operand" ""))) + (match_operand:P 0 "const_int_operand"))) (clobber (reg:CC FLAGS_REG)) (clobber (mem:BLK (scratch)))])] "optimize_insn_for_size_p () @@ -17519,7 +17519,7 @@ [(match_scratch:W 1 "r") (parallel [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) - (match_operand:P 0 "const_int_operand" ""))) + (match_operand:P 0 "const_int_operand"))) (clobber (reg:CC FLAGS_REG))])] "INTVAL (operands[0]) == GET_MODE_SIZE (word_mode)" [(set (match_dup 1) (mem:W (post_inc:P (reg:P SP_REG))))]) @@ -17531,7 +17531,7 @@ (match_scratch:W 2 "r") (parallel [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) - (match_operand:P 0 "const_int_operand" ""))) + (match_operand:P 0 "const_int_operand"))) (clobber (reg:CC FLAGS_REG))])] "INTVAL (operands[0]) == 2*GET_MODE_SIZE (word_mode)" [(set (match_dup 1) (mem:W (post_inc:P (reg:P SP_REG)))) @@ -17541,7 +17541,7 @@ [(match_scratch:W 1 "r") (parallel [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) - (match_operand:P 0 "const_int_operand" ""))) + (match_operand:P 0 "const_int_operand"))) (clobber (reg:CC FLAGS_REG))])] "optimize_insn_for_size_p () && INTVAL (operands[0]) == 2*GET_MODE_SIZE (word_mode)" @@ -17551,10 +17551,10 @@ ;; Convert compares with 1 to shorter inc/dec operations when CF is not ;; required and register dies. Similarly for 128 to -128. (define_peephole2 - [(set (match_operand 0 "flags_reg_operand" "") + [(set (match_operand 0 "flags_reg_operand") (match_operator 1 "compare_operator" - [(match_operand 2 "register_operand" "") - (match_operand 3 "const_int_operand" "")]))] + [(match_operand 2 "register_operand") + (match_operand 3 "const_int_operand")]))] "(((!TARGET_FUSE_CMP_AND_BRANCH || optimize_insn_for_size_p ()) && incdec_operand (operands[3], GET_MODE (operands[3]))) || (!TARGET_FUSE_CMP_AND_BRANCH @@ -17568,9 +17568,9 @@ ;; Convert imul by three, five and nine into lea (define_peephole2 [(parallel - [(set (match_operand:SWI48 0 "register_operand" "") - (mult:SWI48 (match_operand:SWI48 1 "register_operand" "") - (match_operand:SWI48 2 "const359_operand" ""))) + [(set (match_operand:SWI48 0 "register_operand") + (mult:SWI48 (match_operand:SWI48 1 "register_operand") + (match_operand:SWI48 2 "const359_operand"))) (clobber (reg:CC FLAGS_REG))])] "!TARGET_PARTIAL_REG_STALL || <MODE>mode == SImode @@ -17582,9 +17582,9 @@ (define_peephole2 [(parallel - [(set (match_operand:SWI48 0 "register_operand" "") - (mult:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "") - (match_operand:SWI48 2 "const359_operand" ""))) + [(set (match_operand:SWI48 0 "register_operand") + (mult:SWI48 (match_operand:SWI48 1 "nonimmediate_operand") + (match_operand:SWI48 2 "const359_operand"))) (clobber (reg:CC FLAGS_REG))])] "optimize_insn_for_speed_p () && (!TARGET_PARTIAL_REG_STALL || <MODE>mode == SImode)" @@ -17598,9 +17598,9 @@ ;; imul $32bit_imm, reg, reg is direct decoded. (define_peephole2 [(match_scratch:SWI48 3 "r") - (parallel [(set (match_operand:SWI48 0 "register_operand" "") - (mult:SWI48 (match_operand:SWI48 1 "memory_operand" "") - (match_operand:SWI48 2 "immediate_operand" ""))) + (parallel [(set (match_operand:SWI48 0 "register_operand") + (mult:SWI48 (match_operand:SWI48 1 "memory_operand") + (match_operand:SWI48 2 "immediate_operand"))) (clobber (reg:CC FLAGS_REG))])] "TARGET_SLOW_IMUL_IMM32_MEM && optimize_insn_for_speed_p () && !satisfies_constraint_K (operands[2])" @@ -17610,10 +17610,10 @@ (define_peephole2 [(match_scratch:SI 3 "r") - (parallel [(set (match_operand:DI 0 "register_operand" "") + (parallel [(set (match_operand:DI 0 "register_operand") (zero_extend:DI - (mult:SI (match_operand:SI 1 "memory_operand" "") - (match_operand:SI 2 "immediate_operand" "")))) + (mult:SI (match_operand:SI 1 "memory_operand") + (match_operand:SI 2 "immediate_operand")))) (clobber (reg:CC FLAGS_REG))])] "TARGET_64BIT && TARGET_SLOW_IMUL_IMM32_MEM && optimize_insn_for_speed_p () @@ -17628,10 +17628,10 @@ ;; It would be better to force assembler to encode instruction using long ;; immediate, but there is apparently no way to do so. (define_peephole2 - [(parallel [(set (match_operand:SWI248 0 "register_operand" "") + [(parallel [(set (match_operand:SWI248 0 "register_operand") (mult:SWI248 - (match_operand:SWI248 1 "nonimmediate_operand" "") - (match_operand:SWI248 2 "const_int_operand" ""))) + (match_operand:SWI248 1 "nonimmediate_operand") + (match_operand:SWI248 2 "const_int_operand"))) (clobber (reg:CC FLAGS_REG))]) (match_scratch:SWI248 3 "r")] "TARGET_SLOW_IMUL_IMM8 && optimize_insn_for_speed_p () @@ -17658,13 +17658,13 @@ (define_peephole2 [(match_scratch:W 5 "r") - (parallel [(set (match_operand 0 "register_operand" "") - (ashift (match_operand 1 "register_operand" "") - (match_operand 2 "const_int_operand" ""))) + (parallel [(set (match_operand 0 "register_operand") + (ashift (match_operand 1 "register_operand") + (match_operand 2 "const_int_operand"))) (clobber (reg:CC FLAGS_REG))]) - (parallel [(set (match_operand 3 "register_operand" "") + (parallel [(set (match_operand 3 "register_operand") (plus (match_dup 0) - (match_operand 4 "x86_64_general_operand" ""))) + (match_operand 4 "x86_64_general_operand"))) (clobber (reg:CC FLAGS_REG))])] "IN_RANGE (INTVAL (operands[2]), 1, 3) /* Validate MODE for lea. */ @@ -17709,9 +17709,9 @@ [(set_attr "length" "2")]) (define_expand "prefetch" - [(prefetch (match_operand 0 "address_operand" "") - (match_operand:SI 1 "const_int_operand" "") - (match_operand:SI 2 "const_int_operand" ""))] + [(prefetch (match_operand 0 "address_operand") + (match_operand:SI 1 "const_int_operand") + (match_operand:SI 2 "const_int_operand"))] "TARGET_PREFETCH_SSE || TARGET_3DNOW" { int rw = INTVAL (operands[1]); @@ -17735,7 +17735,7 @@ (define_insn "*prefetch_sse_<mode>" [(prefetch (match_operand:P 0 "address_operand" "p") (const_int 0) - (match_operand:SI 1 "const_int_operand" ""))] + (match_operand:SI 1 "const_int_operand"))] "TARGET_PREFETCH_SSE" { static const char * const patterns[4] = { @@ -17770,8 +17770,8 @@ (set_attr "memory" "none")]) (define_expand "stack_protect_set" - [(match_operand 0 "memory_operand" "") - (match_operand 1 "memory_operand" "")] + [(match_operand 0 "memory_operand") + (match_operand 1 "memory_operand")] "" { rtx (*insn)(rtx, rtx); @@ -17812,9 +17812,9 @@ [(set_attr "type" "multi")]) (define_expand "stack_protect_test" - [(match_operand 0 "memory_operand" "") - (match_operand 1 "memory_operand" "") - (match_operand 2 "" "")] + [(match_operand 0 "memory_operand") + (match_operand 1 "memory_operand") + (match_operand 2)] "" { rtx flags = gen_rtx_REG (CCZmode, FLAGS_REG); @@ -17840,7 +17840,7 @@ }) (define_insn "stack_protect_test_<mode>" - [(set (match_operand:CCZ 0 "flags_reg_operand" "") + [(set (match_operand:CCZ 0 "flags_reg_operand") (unspec:CCZ [(match_operand:PTR 1 "memory_operand" "m") (match_operand:PTR 2 "memory_operand" "m")] UNSPEC_SP_TEST)) @@ -17850,7 +17850,7 @@ [(set_attr "type" "multi")]) (define_insn "stack_tls_protect_test_<mode>" - [(set (match_operand:CCZ 0 "flags_reg_operand" "") + [(set (match_operand:CCZ 0 "flags_reg_operand") (unspec:CCZ [(match_operand:PTR 1 "memory_operand" "m") (match_operand:PTR 2 "const_int_operand" "i")] UNSPEC_SP_TLS_TEST)) @@ -17871,11 +17871,11 @@ (set_attr "prefix_rep" "1") (set_attr "prefix_extra" "1") (set (attr "prefix_data16") - (if_then_else (match_operand:HI 2 "" "") + (if_then_else (match_operand:HI 2) (const_string "1") (const_string "*"))) (set (attr "prefix_rex") - (if_then_else (match_operand:QI 2 "ext_QIreg_operand" "") + (if_then_else (match_operand:QI 2 "ext_QIreg_operand") (const_string "1") (const_string "*"))) (set_attr "mode" "SI")]) @@ -17894,8 +17894,8 @@ (set_attr "mode" "DI")]) (define_expand "rdpmc" - [(match_operand:DI 0 "register_operand" "") - (match_operand:SI 1 "register_operand" "")] + [(match_operand:DI 0 "register_operand") + (match_operand:SI 1 "register_operand")] "" { rtx reg = gen_reg_rtx (DImode); @@ -17950,7 +17950,7 @@ (set_attr "length" "2")]) (define_expand "rdtsc" - [(set (match_operand:DI 0 "register_operand" "") + [(set (match_operand:DI 0 "register_operand") (unspec_volatile:DI [(const_int 0)] UNSPECV_RDTSC))] "" { @@ -17994,8 +17994,8 @@ (set_attr "length" "2")]) (define_expand "rdtscp" - [(match_operand:DI 0 "register_operand" "") - (match_operand:SI 1 "memory_operand" "")] + [(match_operand:DI 0 "register_operand") + (match_operand:SI 1 "memory_operand")] "" { rtx di = gen_rtx_UNSPEC_VOLATILE (DImode, @@ -18198,7 +18198,7 @@ ;; Use "rep; nop", instead of "pause", to support older assemblers. ;; They have the same encoding. (define_insn "*pause" - [(set (match_operand:BLK 0 "" "") + [(set (match_operand:BLK 0) (unspec:BLK [(match_dup 0)] UNSPEC_PAUSE))] "" "rep; nop" @@ -18206,7 +18206,7 @@ (set_attr "memory" "unknown")]) (define_expand "xbegin" - [(set (match_operand:SI 0 "register_operand" "") + [(set (match_operand:SI 0 "register_operand") (unspec_volatile:SI [(match_dup 1)] UNSPECV_XBEGIN))] "TARGET_RTM" { @@ -18226,7 +18226,7 @@ [(set (pc) (if_then_else (ne (unspec [(const_int 0)] UNSPEC_XBEGIN_ABORT) (const_int 0)) - (label_ref (match_operand 2 "" "")) + (label_ref (match_operand 2)) (pc))) (set (match_operand:SI 0 "register_operand" "=a") (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "0")] @@ -18252,7 +18252,7 @@ (set_attr "length" "3")]) (define_expand "xtest" - [(set (match_operand:QI 0 "register_operand" "") + [(set (match_operand:QI 0 "register_operand") (unspec_volatile:QI [(const_int 0)] UNSPECV_XTEST))] "TARGET_RTM" { diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index e859b9f1bed..f06deb1fedf 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -69,8 +69,8 @@ ;; This is essential for maintaining stable calling conventions. (define_expand "mov<mode>" - [(set (match_operand:MMXMODEI8 0 "nonimmediate_operand" "") - (match_operand:MMXMODEI8 1 "nonimmediate_operand" ""))] + [(set (match_operand:MMXMODEI8 0 "nonimmediate_operand") + (match_operand:MMXMODEI8 1 "nonimmediate_operand"))] "TARGET_MMX" { ix86_expand_vector_move (<MODE>mode, operands); @@ -201,8 +201,8 @@ (set_attr "mode" "DI,DI,DI,DI,DI,DI,TI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")]) (define_expand "movv2sf" - [(set (match_operand:V2SF 0 "nonimmediate_operand" "") - (match_operand:V2SF 1 "nonimmediate_operand" ""))] + [(set (match_operand:V2SF 0 "nonimmediate_operand") + (match_operand:V2SF 1 "nonimmediate_operand"))] "TARGET_MMX" { ix86_expand_vector_move (V2SFmode, operands); @@ -318,8 +318,8 @@ ;; %%% This multiword shite has got to go. (define_split - [(set (match_operand:MMXMODE 0 "nonimmediate_operand" "") - (match_operand:MMXMODE 1 "general_operand" ""))] + [(set (match_operand:MMXMODE 0 "nonimmediate_operand") + (match_operand:MMXMODE 1 "general_operand"))] "!TARGET_64BIT && reload_completed && !(MMX_REG_P (operands[0]) || SSE_REG_P (operands[0]) || MMX_REG_P (operands[1]) || SSE_REG_P (operands[1]))" @@ -327,7 +327,7 @@ "ix86_split_long_move (operands); DONE;") (define_expand "push<mode>1" - [(match_operand:MMXMODE 0 "register_operand" "")] + [(match_operand:MMXMODE 0 "register_operand")] "TARGET_MMX" { ix86_expand_push (<MODE>mode, operands[0]); @@ -335,8 +335,8 @@ }) (define_expand "movmisalign<mode>" - [(set (match_operand:MMXMODE 0 "nonimmediate_operand" "") - (match_operand:MMXMODE 1 "nonimmediate_operand" ""))] + [(set (match_operand:MMXMODE 0 "nonimmediate_operand") + (match_operand:MMXMODE 1 "nonimmediate_operand"))] "TARGET_MMX" { ix86_expand_vector_move (<MODE>mode, operands); @@ -359,10 +359,10 @@ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (define_expand "mmx_addv2sf3" - [(set (match_operand:V2SF 0 "register_operand" "") + [(set (match_operand:V2SF 0 "register_operand") (plus:V2SF - (match_operand:V2SF 1 "nonimmediate_operand" "") - (match_operand:V2SF 2 "nonimmediate_operand" "")))] + (match_operand:V2SF 1 "nonimmediate_operand") + (match_operand:V2SF 2 "nonimmediate_operand")))] "TARGET_3DNOW" "ix86_fixup_binary_operands_no_copy (PLUS, V2SFmode, operands);") @@ -377,15 +377,15 @@ (set_attr "mode" "V2SF")]) (define_expand "mmx_subv2sf3" - [(set (match_operand:V2SF 0 "register_operand" "") - (minus:V2SF (match_operand:V2SF 1 "register_operand" "") - (match_operand:V2SF 2 "nonimmediate_operand" "")))] + [(set (match_operand:V2SF 0 "register_operand") + (minus:V2SF (match_operand:V2SF 1 "register_operand") + (match_operand:V2SF 2 "nonimmediate_operand")))] "TARGET_3DNOW") (define_expand "mmx_subrv2sf3" - [(set (match_operand:V2SF 0 "register_operand" "") - (minus:V2SF (match_operand:V2SF 2 "register_operand" "") - (match_operand:V2SF 1 "nonimmediate_operand" "")))] + [(set (match_operand:V2SF 0 "register_operand") + (minus:V2SF (match_operand:V2SF 2 "register_operand") + (match_operand:V2SF 1 "nonimmediate_operand")))] "TARGET_3DNOW") (define_insn "*mmx_subv2sf3" @@ -401,9 +401,9 @@ (set_attr "mode" "V2SF")]) (define_expand "mmx_mulv2sf3" - [(set (match_operand:V2SF 0 "register_operand" "") - (mult:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "") - (match_operand:V2SF 2 "nonimmediate_operand" "")))] + [(set (match_operand:V2SF 0 "register_operand") + (mult:V2SF (match_operand:V2SF 1 "nonimmediate_operand") + (match_operand:V2SF 2 "nonimmediate_operand")))] "TARGET_3DNOW" "ix86_fixup_binary_operands_no_copy (MULT, V2SFmode, operands);") @@ -422,10 +422,10 @@ ;; applied to NaNs. Hopefully the optimizers won't get too smart on us. (define_expand "mmx_<code>v2sf3" - [(set (match_operand:V2SF 0 "register_operand" "") + [(set (match_operand:V2SF 0 "register_operand") (smaxmin:V2SF - (match_operand:V2SF 1 "nonimmediate_operand" "") - (match_operand:V2SF 2 "nonimmediate_operand" "")))] + (match_operand:V2SF 1 "nonimmediate_operand") + (match_operand:V2SF 2 "nonimmediate_operand")))] "TARGET_3DNOW" { if (!flag_finite_math_only) @@ -568,9 +568,9 @@ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (define_expand "mmx_eqv2sf3" - [(set (match_operand:V2SI 0 "register_operand" "") - (eq:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "") - (match_operand:V2SF 2 "nonimmediate_operand" "")))] + [(set (match_operand:V2SI 0 "register_operand") + (eq:V2SI (match_operand:V2SF 1 "nonimmediate_operand") + (match_operand:V2SF 2 "nonimmediate_operand")))] "TARGET_3DNOW" "ix86_fixup_binary_operands_no_copy (EQ, V2SFmode, operands);") @@ -690,9 +690,9 @@ (set_attr "mode" "DI")]) (define_expand "vec_setv2sf" - [(match_operand:V2SF 0 "register_operand" "") - (match_operand:SF 1 "register_operand" "") - (match_operand 2 "const_int_operand" "")] + [(match_operand:V2SF 0 "register_operand") + (match_operand:SF 1 "register_operand") + (match_operand 2 "const_int_operand")] "TARGET_MMX" { ix86_expand_vector_set (false, operands[0], operands[1], @@ -740,9 +740,9 @@ (set_attr "mode" "DI,V4SF,SF,SF,SF,SF")]) (define_split - [(set (match_operand:SF 0 "register_operand" "") + [(set (match_operand:SF 0 "register_operand") (vec_select:SF - (match_operand:V2SF 1 "memory_operand" "") + (match_operand:V2SF 1 "memory_operand") (parallel [(const_int 1)])))] "TARGET_MMX && reload_completed" [(const_int 0)] @@ -753,9 +753,9 @@ }) (define_expand "vec_extractv2sf" - [(match_operand:SF 0 "register_operand" "") - (match_operand:V2SF 1 "register_operand" "") - (match_operand 2 "const_int_operand" "")] + [(match_operand:SF 0 "register_operand") + (match_operand:V2SF 1 "register_operand") + (match_operand 2 "const_int_operand")] "TARGET_MMX" { ix86_expand_vector_extract (false, operands[0], operands[1], @@ -764,8 +764,8 @@ }) (define_expand "vec_initv2sf" - [(match_operand:V2SF 0 "register_operand" "") - (match_operand 1 "" "")] + [(match_operand:V2SF 0 "register_operand") + (match_operand 1)] "TARGET_SSE" { ix86_expand_vector_init (false, operands[0], operands[1]); @@ -779,10 +779,10 @@ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (define_expand "mmx_<plusminus_insn><mode>3" - [(set (match_operand:MMXMODEI8 0 "register_operand" "") + [(set (match_operand:MMXMODEI8 0 "register_operand") (plusminus:MMXMODEI8 - (match_operand:MMXMODEI8 1 "nonimmediate_operand" "") - (match_operand:MMXMODEI8 2 "nonimmediate_operand" "")))] + (match_operand:MMXMODEI8 1 "nonimmediate_operand") + (match_operand:MMXMODEI8 2 "nonimmediate_operand")))] "TARGET_MMX || (TARGET_SSE2 && <MODE>mode == V1DImode)" "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") @@ -798,10 +798,10 @@ (set_attr "mode" "DI")]) (define_expand "mmx_<plusminus_insn><mode>3" - [(set (match_operand:MMXMODE12 0 "register_operand" "") + [(set (match_operand:MMXMODE12 0 "register_operand") (sat_plusminus:MMXMODE12 - (match_operand:MMXMODE12 1 "nonimmediate_operand" "") - (match_operand:MMXMODE12 2 "nonimmediate_operand" "")))] + (match_operand:MMXMODE12 1 "nonimmediate_operand") + (match_operand:MMXMODE12 2 "nonimmediate_operand")))] "TARGET_MMX" "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") @@ -816,9 +816,9 @@ (set_attr "mode" "DI")]) (define_expand "mmx_mulv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "") - (mult:V4HI (match_operand:V4HI 1 "nonimmediate_operand" "") - (match_operand:V4HI 2 "nonimmediate_operand" "")))] + [(set (match_operand:V4HI 0 "register_operand") + (mult:V4HI (match_operand:V4HI 1 "nonimmediate_operand") + (match_operand:V4HI 2 "nonimmediate_operand")))] "TARGET_MMX" "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);") @@ -832,14 +832,14 @@ (set_attr "mode" "DI")]) (define_expand "mmx_smulv4hi3_highpart" - [(set (match_operand:V4HI 0 "register_operand" "") + [(set (match_operand:V4HI 0 "register_operand") (truncate:V4HI (lshiftrt:V4SI (mult:V4SI (sign_extend:V4SI - (match_operand:V4HI 1 "nonimmediate_operand" "")) + (match_operand:V4HI 1 "nonimmediate_operand")) (sign_extend:V4SI - (match_operand:V4HI 2 "nonimmediate_operand" ""))) + (match_operand:V4HI 2 "nonimmediate_operand"))) (const_int 16))))] "TARGET_MMX" "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);") @@ -860,14 +860,14 @@ (set_attr "mode" "DI")]) (define_expand "mmx_umulv4hi3_highpart" - [(set (match_operand:V4HI 0 "register_operand" "") + [(set (match_operand:V4HI 0 "register_operand") (truncate:V4HI (lshiftrt:V4SI (mult:V4SI (zero_extend:V4SI - (match_operand:V4HI 1 "nonimmediate_operand" "")) + (match_operand:V4HI 1 "nonimmediate_operand")) (zero_extend:V4SI - (match_operand:V4HI 2 "nonimmediate_operand" ""))) + (match_operand:V4HI 2 "nonimmediate_operand"))) (const_int 16))))] "TARGET_SSE || TARGET_3DNOW_A" "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);") @@ -889,16 +889,16 @@ (set_attr "mode" "DI")]) (define_expand "mmx_pmaddwd" - [(set (match_operand:V2SI 0 "register_operand" "") + [(set (match_operand:V2SI 0 "register_operand") (plus:V2SI (mult:V2SI (sign_extend:V2SI (vec_select:V2HI - (match_operand:V4HI 1 "nonimmediate_operand" "") + (match_operand:V4HI 1 "nonimmediate_operand") (parallel [(const_int 0) (const_int 2)]))) (sign_extend:V2SI (vec_select:V2HI - (match_operand:V4HI 2 "nonimmediate_operand" "") + (match_operand:V4HI 2 "nonimmediate_operand") (parallel [(const_int 0) (const_int 2)])))) (mult:V2SI (sign_extend:V2SI @@ -935,15 +935,15 @@ (set_attr "mode" "DI")]) (define_expand "mmx_pmulhrwv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "") + [(set (match_operand:V4HI 0 "register_operand") (truncate:V4HI (lshiftrt:V4SI (plus:V4SI (mult:V4SI (sign_extend:V4SI - (match_operand:V4HI 1 "nonimmediate_operand" "")) + (match_operand:V4HI 1 "nonimmediate_operand")) (sign_extend:V4SI - (match_operand:V4HI 2 "nonimmediate_operand" ""))) + (match_operand:V4HI 2 "nonimmediate_operand"))) (const_vector:V4SI [(const_int 32768) (const_int 32768) (const_int 32768) (const_int 32768)])) (const_int 16))))] @@ -970,15 +970,15 @@ (set_attr "mode" "DI")]) (define_expand "sse2_umulv1siv1di3" - [(set (match_operand:V1DI 0 "register_operand" "") + [(set (match_operand:V1DI 0 "register_operand") (mult:V1DI (zero_extend:V1DI (vec_select:V1SI - (match_operand:V2SI 1 "nonimmediate_operand" "") + (match_operand:V2SI 1 "nonimmediate_operand") (parallel [(const_int 0)]))) (zero_extend:V1DI (vec_select:V1SI - (match_operand:V2SI 2 "nonimmediate_operand" "") + (match_operand:V2SI 2 "nonimmediate_operand") (parallel [(const_int 0)])))))] "TARGET_SSE2" "ix86_fixup_binary_operands_no_copy (MULT, V2SImode, operands);") @@ -1000,10 +1000,10 @@ (set_attr "mode" "DI")]) (define_expand "mmx_<code>v4hi3" - [(set (match_operand:V4HI 0 "register_operand" "") + [(set (match_operand:V4HI 0 "register_operand") (smaxmin:V4HI - (match_operand:V4HI 1 "nonimmediate_operand" "") - (match_operand:V4HI 2 "nonimmediate_operand" "")))] + (match_operand:V4HI 1 "nonimmediate_operand") + (match_operand:V4HI 2 "nonimmediate_operand")))] "TARGET_SSE || TARGET_3DNOW_A" "ix86_fixup_binary_operands_no_copy (<CODE>, V4HImode, operands);") @@ -1019,10 +1019,10 @@ (set_attr "mode" "DI")]) (define_expand "mmx_<code>v8qi3" - [(set (match_operand:V8QI 0 "register_operand" "") + [(set (match_operand:V8QI 0 "register_operand") (umaxmin:V8QI - (match_operand:V8QI 1 "nonimmediate_operand" "") - (match_operand:V8QI 2 "nonimmediate_operand" "")))] + (match_operand:V8QI 1 "nonimmediate_operand") + (match_operand:V8QI 2 "nonimmediate_operand")))] "TARGET_SSE || TARGET_3DNOW_A" "ix86_fixup_binary_operands_no_copy (<CODE>, V8QImode, operands);") @@ -1046,7 +1046,7 @@ "psra<mmxvecsize>\t{%2, %0|%0, %2}" [(set_attr "type" "mmxshft") (set (attr "length_immediate") - (if_then_else (match_operand 2 "const_int_operand" "") + (if_then_else (match_operand 2 "const_int_operand") (const_string "1") (const_string "0"))) (set_attr "mode" "DI")]) @@ -1060,7 +1060,7 @@ "p<vshift><mmxvecsize>\t{%2, %0|%0, %2}" [(set_attr "type" "mmxshft") (set (attr "length_immediate") - (if_then_else (match_operand 2 "const_int_operand" "") + (if_then_else (match_operand 2 "const_int_operand") (const_string "1") (const_string "0"))) (set_attr "mode" "DI")]) @@ -1072,10 +1072,10 @@ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (define_expand "mmx_eq<mode>3" - [(set (match_operand:MMXMODEI 0 "register_operand" "") + [(set (match_operand:MMXMODEI 0 "register_operand") (eq:MMXMODEI - (match_operand:MMXMODEI 1 "nonimmediate_operand" "") - (match_operand:MMXMODEI 2 "nonimmediate_operand" "")))] + (match_operand:MMXMODEI 1 "nonimmediate_operand") + (match_operand:MMXMODEI 2 "nonimmediate_operand")))] "TARGET_MMX" "ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);") @@ -1116,10 +1116,10 @@ (set_attr "mode" "DI")]) (define_expand "mmx_<code><mode>3" - [(set (match_operand:MMXMODEI 0 "register_operand" "") + [(set (match_operand:MMXMODEI 0 "register_operand") (any_logic:MMXMODEI - (match_operand:MMXMODEI 1 "nonimmediate_operand" "") - (match_operand:MMXMODEI 2 "nonimmediate_operand" "")))] + (match_operand:MMXMODEI 1 "nonimmediate_operand") + (match_operand:MMXMODEI 2 "nonimmediate_operand")))] "TARGET_MMX" "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") @@ -1258,12 +1258,12 @@ (set_attr "mode" "DI")]) (define_expand "mmx_pinsrw" - [(set (match_operand:V4HI 0 "register_operand" "") + [(set (match_operand:V4HI 0 "register_operand") (vec_merge:V4HI (vec_duplicate:V4HI - (match_operand:SI 2 "nonimmediate_operand" "")) - (match_operand:V4HI 1 "register_operand" "") - (match_operand:SI 3 "const_0_to_3_operand" "")))] + (match_operand:SI 2 "nonimmediate_operand")) + (match_operand:V4HI 1 "register_operand") + (match_operand:SI 3 "const_0_to_3_operand")))] "TARGET_SSE || TARGET_3DNOW_A" { operands[2] = gen_lowpart (HImode, operands[2]); @@ -1276,7 +1276,7 @@ (vec_duplicate:V4HI (match_operand:HI 2 "nonimmediate_operand" "rm")) (match_operand:V4HI 1 "register_operand" "0") - (match_operand:SI 3 "const_int_operand" "")))] + (match_operand:SI 3 "const_int_operand")))] "(TARGET_SSE || TARGET_3DNOW_A) && ((unsigned) exact_log2 (INTVAL (operands[3])) < GET_MODE_NUNITS (V4HImode))" @@ -1304,9 +1304,9 @@ (set_attr "mode" "DI")]) (define_expand "mmx_pshufw" - [(match_operand:V4HI 0 "register_operand" "") - (match_operand:V4HI 1 "nonimmediate_operand" "") - (match_operand:SI 2 "const_int_operand" "")] + [(match_operand:V4HI 0 "register_operand") + (match_operand:V4HI 1 "nonimmediate_operand") + (match_operand:SI 2 "const_int_operand")] "TARGET_SSE || TARGET_3DNOW_A" { int mask = INTVAL (operands[2]); @@ -1322,10 +1322,10 @@ [(set (match_operand:V4HI 0 "register_operand" "=y") (vec_select:V4HI (match_operand:V4HI 1 "nonimmediate_operand" "ym") - (parallel [(match_operand 2 "const_0_to_3_operand" "") - (match_operand 3 "const_0_to_3_operand" "") - (match_operand 4 "const_0_to_3_operand" "") - (match_operand 5 "const_0_to_3_operand" "")])))] + (parallel [(match_operand 2 "const_0_to_3_operand") + (match_operand 3 "const_0_to_3_operand") + (match_operand 4 "const_0_to_3_operand") + (match_operand 5 "const_0_to_3_operand")])))] "TARGET_SSE || TARGET_3DNOW_A" { int mask = 0; @@ -1385,9 +1385,9 @@ (set_attr "mode" "DI")]) (define_expand "vec_setv2si" - [(match_operand:V2SI 0 "register_operand" "") - (match_operand:SI 1 "register_operand" "") - (match_operand 2 "const_int_operand" "")] + [(match_operand:V2SI 0 "register_operand") + (match_operand:SI 1 "register_operand") + (match_operand 2 "const_int_operand")] "TARGET_MMX" { ix86_expand_vector_set (false, operands[0], operands[1], @@ -1441,9 +1441,9 @@ (set_attr "mode" "DI,TI,TI,V4SF,SI,SI,SI")]) (define_split - [(set (match_operand:SI 0 "register_operand" "") + [(set (match_operand:SI 0 "register_operand") (vec_select:SI - (match_operand:V2SI 1 "memory_operand" "") + (match_operand:V2SI 1 "memory_operand") (parallel [(const_int 1)])))] "TARGET_MMX && reload_completed" [(const_int 0)] @@ -1454,9 +1454,9 @@ }) (define_expand "vec_extractv2si" - [(match_operand:SI 0 "register_operand" "") - (match_operand:V2SI 1 "register_operand" "") - (match_operand 2 "const_int_operand" "")] + [(match_operand:SI 0 "register_operand") + (match_operand:V2SI 1 "register_operand") + (match_operand 2 "const_int_operand")] "TARGET_MMX" { ix86_expand_vector_extract (false, operands[0], operands[1], @@ -1465,8 +1465,8 @@ }) (define_expand "vec_initv2si" - [(match_operand:V2SI 0 "register_operand" "") - (match_operand 1 "" "")] + [(match_operand:V2SI 0 "register_operand") + (match_operand 1)] "TARGET_SSE" { ix86_expand_vector_init (false, operands[0], operands[1]); @@ -1474,9 +1474,9 @@ }) (define_expand "vec_setv4hi" - [(match_operand:V4HI 0 "register_operand" "") - (match_operand:HI 1 "register_operand" "") - (match_operand 2 "const_int_operand" "")] + [(match_operand:V4HI 0 "register_operand") + (match_operand:HI 1 "register_operand") + (match_operand 2 "const_int_operand")] "TARGET_MMX" { ix86_expand_vector_set (false, operands[0], operands[1], @@ -1485,9 +1485,9 @@ }) (define_expand "vec_extractv4hi" - [(match_operand:HI 0 "register_operand" "") - (match_operand:V4HI 1 "register_operand" "") - (match_operand 2 "const_int_operand" "")] + [(match_operand:HI 0 "register_operand") + (match_operand:V4HI 1 "register_operand") + (match_operand 2 "const_int_operand")] "TARGET_MMX" { ix86_expand_vector_extract (false, operands[0], operands[1], @@ -1496,8 +1496,8 @@ }) (define_expand "vec_initv4hi" - [(match_operand:V4HI 0 "register_operand" "") - (match_operand 1 "" "")] + [(match_operand:V4HI 0 "register_operand") + (match_operand 1)] "TARGET_SSE" { ix86_expand_vector_init (false, operands[0], operands[1]); @@ -1505,9 +1505,9 @@ }) (define_expand "vec_setv8qi" - [(match_operand:V8QI 0 "register_operand" "") - (match_operand:QI 1 "register_operand" "") - (match_operand 2 "const_int_operand" "")] + [(match_operand:V8QI 0 "register_operand") + (match_operand:QI 1 "register_operand") + (match_operand 2 "const_int_operand")] "TARGET_MMX" { ix86_expand_vector_set (false, operands[0], operands[1], @@ -1516,9 +1516,9 @@ }) (define_expand "vec_extractv8qi" - [(match_operand:QI 0 "register_operand" "") - (match_operand:V8QI 1 "register_operand" "") - (match_operand 2 "const_int_operand" "")] + [(match_operand:QI 0 "register_operand") + (match_operand:V8QI 1 "register_operand") + (match_operand 2 "const_int_operand")] "TARGET_MMX" { ix86_expand_vector_extract (false, operands[0], operands[1], @@ -1527,8 +1527,8 @@ }) (define_expand "vec_initv8qi" - [(match_operand:V8QI 0 "register_operand" "") - (match_operand 1 "" "")] + [(match_operand:V8QI 0 "register_operand") + (match_operand 1)] "TARGET_SSE" { ix86_expand_vector_init (false, operands[0], operands[1]); @@ -1542,15 +1542,15 @@ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (define_expand "mmx_uavgv8qi3" - [(set (match_operand:V8QI 0 "register_operand" "") + [(set (match_operand:V8QI 0 "register_operand") (truncate:V8QI (lshiftrt:V8HI (plus:V8HI (plus:V8HI (zero_extend:V8HI - (match_operand:V8QI 1 "nonimmediate_operand" "")) + (match_operand:V8QI 1 "nonimmediate_operand")) (zero_extend:V8HI - (match_operand:V8QI 2 "nonimmediate_operand" ""))) + (match_operand:V8QI 2 "nonimmediate_operand"))) (const_vector:V8HI [(const_int 1) (const_int 1) (const_int 1) (const_int 1) (const_int 1) (const_int 1) @@ -1594,15 +1594,15 @@ (set_attr "mode" "DI")]) (define_expand "mmx_uavgv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "") + [(set (match_operand:V4HI 0 "register_operand") (truncate:V4HI (lshiftrt:V4SI (plus:V4SI (plus:V4SI (zero_extend:V4SI - (match_operand:V4HI 1 "nonimmediate_operand" "")) + (match_operand:V4HI 1 "nonimmediate_operand")) (zero_extend:V4SI - (match_operand:V4HI 2 "nonimmediate_operand" ""))) + (match_operand:V4HI 2 "nonimmediate_operand"))) (const_vector:V4SI [(const_int 1) (const_int 1) (const_int 1) (const_int 1)])) (const_int 1))))] @@ -1648,9 +1648,9 @@ (set_attr "mode" "DI")]) (define_expand "mmx_maskmovq" - [(set (match_operand:V8QI 0 "memory_operand" "") - (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "") - (match_operand:V8QI 2 "register_operand" "") + [(set (match_operand:V8QI 0 "memory_operand") + (unspec:V8QI [(match_operand:V8QI 1 "register_operand") + (match_operand:V8QI 2 "register_operand") (match_dup 0)] UNSPEC_MASKMOV))] "TARGET_SSE || TARGET_3DNOW_A") diff --git a/gcc/config/i386/pentium.md b/gcc/config/i386/pentium.md index c6c5bd55ff1..91a5dd03d6a 100644 --- a/gcc/config/i386/pentium.md +++ b/gcc/config/i386/pentium.md @@ -47,22 +47,22 @@ (eq_attr "type" "ibr") (const_string "pv") (and (eq_attr "type" "ishift") - (match_operand 2 "const_int_operand" "")) + (match_operand 2 "const_int_operand")) (const_string "pu") (and (eq_attr "type" "rotate") - (match_operand 2 "const1_operand" "")) + (match_operand 2 "const1_operand")) (const_string "pu") (and (eq_attr "type" "ishift1") - (match_operand 1 "const_int_operand" "")) + (match_operand 1 "const_int_operand")) (const_string "pu") (and (eq_attr "type" "rotate1") - (match_operand 1 "const1_operand" "")) + (match_operand 1 "const1_operand")) (const_string "pu") (and (eq_attr "type" "call") - (match_operand 0 "constant_call_address_operand" "")) + (match_operand 0 "constant_call_address_operand")) (const_string "pv") (and (eq_attr "type" "callv") - (match_operand 1 "constant_call_address_operand" "")) + (match_operand 1 "constant_call_address_operand")) (const_string "pv") ] (const_string "np"))) @@ -167,7 +167,7 @@ (define_insn_reservation "pent_fpstore" 2 (and (eq_attr "cpu" "pentium") (and (eq_attr "type" "fmov") - (ior (match_operand 1 "immediate_operand" "") + (ior (match_operand 1 "immediate_operand") (eq_attr "memory" "store")))) "(pentium-fp+pentium-np)*2") diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 71e8e6d5aba..6b79a080cb4 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -412,8 +412,8 @@ ;; This is essential for maintaining stable calling conventions. (define_expand "mov<mode>" - [(set (match_operand:V16 0 "nonimmediate_operand" "") - (match_operand:V16 1 "nonimmediate_operand" ""))] + [(set (match_operand:V16 0 "nonimmediate_operand") + (match_operand:V16 1 "nonimmediate_operand"))] "TARGET_SSE" { ix86_expand_vector_move (<MODE>mode, operands); @@ -541,8 +541,8 @@ }) (define_split - [(set (match_operand:V4SF 0 "register_operand" "") - (match_operand:V4SF 1 "zero_extended_scalar_load_operand" ""))] + [(set (match_operand:V4SF 0 "register_operand") + (match_operand:V4SF 1 "zero_extended_scalar_load_operand"))] "TARGET_SSE && reload_completed" [(set (match_dup 0) (vec_merge:V4SF @@ -555,8 +555,8 @@ }) (define_split - [(set (match_operand:V2DF 0 "register_operand" "") - (match_operand:V2DF 1 "zero_extended_scalar_load_operand" ""))] + [(set (match_operand:V2DF 0 "register_operand") + (match_operand:V2DF 1 "zero_extended_scalar_load_operand"))] "TARGET_SSE2 && reload_completed" [(set (match_dup 0) (vec_concat:V2DF (match_dup 1) (match_dup 2)))] { @@ -565,7 +565,7 @@ }) (define_expand "push<mode>1" - [(match_operand:V16 0 "register_operand" "")] + [(match_operand:V16 0 "register_operand")] "TARGET_SSE" { ix86_expand_push (<MODE>mode, operands[0]); @@ -573,8 +573,8 @@ }) (define_expand "movmisalign<mode>" - [(set (match_operand:V16 0 "nonimmediate_operand" "") - (match_operand:V16 1 "nonimmediate_operand" ""))] + [(set (match_operand:V16 0 "nonimmediate_operand") + (match_operand:V16 1 "nonimmediate_operand"))] "TARGET_SSE" { ix86_expand_vector_move_misalign (<MODE>mode, operands); @@ -582,9 +582,9 @@ }) (define_expand "<sse>_movu<ssemodesuffix><avxsizesuffix>" - [(set (match_operand:VF 0 "nonimmediate_operand" "") + [(set (match_operand:VF 0 "nonimmediate_operand") (unspec:VF - [(match_operand:VF 1 "nonimmediate_operand" "")] + [(match_operand:VF 1 "nonimmediate_operand")] UNSPEC_MOVU))] "TARGET_SSE" { @@ -605,8 +605,8 @@ (set_attr "mode" "<MODE>")]) (define_expand "<sse2>_movdqu<avxsizesuffix>" - [(set (match_operand:VI1 0 "nonimmediate_operand" "") - (unspec:VI1 [(match_operand:VI1 1 "nonimmediate_operand" "")] + [(set (match_operand:VI1 0 "nonimmediate_operand") + (unspec:VI1 [(match_operand:VI1 1 "nonimmediate_operand")] UNSPEC_MOVU))] "TARGET_SSE2" { @@ -699,9 +699,9 @@ (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")]) (define_expand "storent<mode>" - [(set (match_operand:STORENT_MODE 0 "memory_operand" "") + [(set (match_operand:STORENT_MODE 0 "memory_operand") (unspec:STORENT_MODE - [(match_operand:STORENT_MODE 1 "register_operand" "")] + [(match_operand:STORENT_MODE 1 "register_operand")] UNSPEC_MOVNT))] "TARGET_SSE") @@ -712,9 +712,9 @@ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (define_expand "<code><mode>2" - [(set (match_operand:VF 0 "register_operand" "") + [(set (match_operand:VF 0 "register_operand") (absneg:VF - (match_operand:VF 1 "register_operand" "")))] + (match_operand:VF 1 "register_operand")))] "TARGET_SSE" "ix86_expand_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;") @@ -757,10 +757,10 @@ [(set_attr "isa" "noavx,noavx,avx,avx")]) (define_expand "<plusminus_insn><mode>3" - [(set (match_operand:VF 0 "register_operand" "") + [(set (match_operand:VF 0 "register_operand") (plusminus:VF - (match_operand:VF 1 "nonimmediate_operand" "") - (match_operand:VF 2 "nonimmediate_operand" "")))] + (match_operand:VF 1 "nonimmediate_operand") + (match_operand:VF 2 "nonimmediate_operand")))] "TARGET_SSE" "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") @@ -796,10 +796,10 @@ (set_attr "mode" "<ssescalarmode>")]) (define_expand "mul<mode>3" - [(set (match_operand:VF 0 "register_operand" "") + [(set (match_operand:VF 0 "register_operand") (mult:VF - (match_operand:VF 1 "nonimmediate_operand" "") - (match_operand:VF 2 "nonimmediate_operand" "")))] + (match_operand:VF 1 "nonimmediate_operand") + (match_operand:VF 2 "nonimmediate_operand")))] "TARGET_SSE" "ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands);") @@ -835,16 +835,16 @@ (set_attr "mode" "<ssescalarmode>")]) (define_expand "div<mode>3" - [(set (match_operand:VF2 0 "register_operand" "") - (div:VF2 (match_operand:VF2 1 "register_operand" "") - (match_operand:VF2 2 "nonimmediate_operand" "")))] + [(set (match_operand:VF2 0 "register_operand") + (div:VF2 (match_operand:VF2 1 "register_operand") + (match_operand:VF2 2 "nonimmediate_operand")))] "TARGET_SSE2" "ix86_fixup_binary_operands_no_copy (DIV, <MODE>mode, operands);") (define_expand "div<mode>3" - [(set (match_operand:VF1 0 "register_operand" "") - (div:VF1 (match_operand:VF1 1 "register_operand" "") - (match_operand:VF1 2 "nonimmediate_operand" "")))] + [(set (match_operand:VF1 0 "register_operand") + (div:VF1 (match_operand:VF1 1 "register_operand") + (match_operand:VF1 2 "nonimmediate_operand")))] "TARGET_SSE" { ix86_fixup_binary_operands_no_copy (DIV, <MODE>mode, operands); @@ -920,13 +920,13 @@ (set_attr "mode" "SF")]) (define_expand "sqrt<mode>2" - [(set (match_operand:VF2 0 "register_operand" "") - (sqrt:VF2 (match_operand:VF2 1 "nonimmediate_operand" "")))] + [(set (match_operand:VF2 0 "register_operand") + (sqrt:VF2 (match_operand:VF2 1 "nonimmediate_operand")))] "TARGET_SSE2") (define_expand "sqrt<mode>2" - [(set (match_operand:VF1 0 "register_operand" "") - (sqrt:VF1 (match_operand:VF1 1 "nonimmediate_operand" "")))] + [(set (match_operand:VF1 0 "register_operand") + (sqrt:VF1 (match_operand:VF1 1 "nonimmediate_operand")))] "TARGET_SSE" { if (TARGET_SSE_MATH @@ -968,9 +968,9 @@ (set_attr "mode" "<ssescalarmode>")]) (define_expand "rsqrt<mode>2" - [(set (match_operand:VF1 0 "register_operand" "") + [(set (match_operand:VF1 0 "register_operand") (unspec:VF1 - [(match_operand:VF1 1 "nonimmediate_operand" "")] UNSPEC_RSQRT))] + [(match_operand:VF1 1 "nonimmediate_operand")] UNSPEC_RSQRT))] "TARGET_SSE_MATH" { ix86_emit_swsqrtsf (operands[0], operands[1], <MODE>mode, true); @@ -1008,10 +1008,10 @@ ;; applied to NaNs. Hopefully the optimizers won't get too smart on us. (define_expand "<code><mode>3" - [(set (match_operand:VF 0 "register_operand" "") + [(set (match_operand:VF 0 "register_operand") (smaxmin:VF - (match_operand:VF 1 "nonimmediate_operand" "") - (match_operand:VF 2 "nonimmediate_operand" "")))] + (match_operand:VF 1 "nonimmediate_operand") + (match_operand:VF 2 "nonimmediate_operand")))] "TARGET_SSE" { if (!flag_finite_math_only) @@ -1290,8 +1290,8 @@ (set_attr "mode" "V4SF")]) (define_expand "reduc_splus_v4df" - [(match_operand:V4DF 0 "register_operand" "") - (match_operand:V4DF 1 "register_operand" "")] + [(match_operand:V4DF 0 "register_operand") + (match_operand:V4DF 1 "register_operand")] "TARGET_AVX" { rtx tmp = gen_reg_rtx (V4DFmode); @@ -1303,8 +1303,8 @@ }) (define_expand "reduc_splus_v2df" - [(match_operand:V2DF 0 "register_operand" "") - (match_operand:V2DF 1 "register_operand" "")] + [(match_operand:V2DF 0 "register_operand") + (match_operand:V2DF 1 "register_operand")] "TARGET_SSE3" { emit_insn (gen_sse3_haddv2df3 (operands[0], operands[1], operands[1])); @@ -1312,8 +1312,8 @@ }) (define_expand "reduc_splus_v8sf" - [(match_operand:V8SF 0 "register_operand" "") - (match_operand:V8SF 1 "register_operand" "")] + [(match_operand:V8SF 0 "register_operand") + (match_operand:V8SF 1 "register_operand")] "TARGET_AVX" { rtx tmp = gen_reg_rtx (V8SFmode); @@ -1326,8 +1326,8 @@ }) (define_expand "reduc_splus_v4sf" - [(match_operand:V4SF 0 "register_operand" "") - (match_operand:V4SF 1 "register_operand" "")] + [(match_operand:V4SF 0 "register_operand") + (match_operand:V4SF 1 "register_operand")] "TARGET_SSE" { if (TARGET_SSE3) @@ -1350,8 +1350,8 @@ (define_expand "reduc_<code>_<mode>" [(smaxmin:REDUC_SMINMAX_MODE - (match_operand:REDUC_SMINMAX_MODE 0 "register_operand" "") - (match_operand:REDUC_SMINMAX_MODE 1 "register_operand" ""))] + (match_operand:REDUC_SMINMAX_MODE 0 "register_operand") + (match_operand:REDUC_SMINMAX_MODE 1 "register_operand"))] "" { ix86_expand_reduc (gen_<code><mode>3, operands[0], operands[1]); @@ -1360,8 +1360,8 @@ (define_expand "reduc_<code>_<mode>" [(umaxmin:VI_256 - (match_operand:VI_256 0 "register_operand" "") - (match_operand:VI_256 1 "register_operand" ""))] + (match_operand:VI_256 0 "register_operand") + (match_operand:VI_256 1 "register_operand"))] "TARGET_AVX2" { ix86_expand_reduc (gen_<code><mode>3, operands[0], operands[1]); @@ -1370,8 +1370,8 @@ (define_expand "reduc_umin_v8hi" [(umin:V8HI - (match_operand:V8HI 0 "register_operand" "") - (match_operand:V8HI 1 "register_operand" ""))] + (match_operand:V8HI 0 "register_operand") + (match_operand:V8HI 1 "register_operand"))] "TARGET_SSE4_1" { ix86_expand_reduc (gen_uminv8hi3, operands[0], operands[1]); @@ -1505,13 +1505,13 @@ (set_attr "mode" "<MODE>")]) (define_expand "vcond<V_256:mode><VF_256:mode>" - [(set (match_operand:V_256 0 "register_operand" "") + [(set (match_operand:V_256 0 "register_operand") (if_then_else:V_256 (match_operator 3 "" - [(match_operand:VF_256 4 "nonimmediate_operand" "") - (match_operand:VF_256 5 "nonimmediate_operand" "")]) - (match_operand:V_256 1 "general_operand" "") - (match_operand:V_256 2 "general_operand" "")))] + [(match_operand:VF_256 4 "nonimmediate_operand") + (match_operand:VF_256 5 "nonimmediate_operand")]) + (match_operand:V_256 1 "general_operand") + (match_operand:V_256 2 "general_operand")))] "TARGET_AVX && (GET_MODE_NUNITS (<V_256:MODE>mode) == GET_MODE_NUNITS (<VF_256:MODE>mode))" @@ -1522,13 +1522,13 @@ }) (define_expand "vcond<V_128:mode><VF_128:mode>" - [(set (match_operand:V_128 0 "register_operand" "") + [(set (match_operand:V_128 0 "register_operand") (if_then_else:V_128 (match_operator 3 "" - [(match_operand:VF_128 4 "nonimmediate_operand" "") - (match_operand:VF_128 5 "nonimmediate_operand" "")]) - (match_operand:V_128 1 "general_operand" "") - (match_operand:V_128 2 "general_operand" "")))] + [(match_operand:VF_128 4 "nonimmediate_operand") + (match_operand:VF_128 5 "nonimmediate_operand")]) + (match_operand:V_128 1 "general_operand") + (match_operand:V_128 2 "general_operand")))] "TARGET_SSE && (GET_MODE_NUNITS (<V_128:MODE>mode) == GET_MODE_NUNITS (<VF_128:MODE>mode))" @@ -1578,10 +1578,10 @@ (set_attr "mode" "<MODE>")]) (define_expand "<code><mode>3" - [(set (match_operand:VF 0 "register_operand" "") + [(set (match_operand:VF 0 "register_operand") (any_logic:VF - (match_operand:VF 1 "nonimmediate_operand" "") - (match_operand:VF 2 "nonimmediate_operand" "")))] + (match_operand:VF 1 "nonimmediate_operand") + (match_operand:VF 2 "nonimmediate_operand")))] "TARGET_SSE" "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") @@ -1621,11 +1621,11 @@ [(set (match_dup 4) (and:VF (not:VF (match_dup 3)) - (match_operand:VF 1 "nonimmediate_operand" ""))) + (match_operand:VF 1 "nonimmediate_operand"))) (set (match_dup 5) (and:VF (match_dup 3) - (match_operand:VF 2 "nonimmediate_operand" ""))) - (set (match_operand:VF 0 "register_operand" "") + (match_operand:VF 2 "nonimmediate_operand"))) + (set (match_operand:VF 0 "register_operand") (ior:VF (match_dup 4) (match_dup 5)))] "TARGET_SSE" { @@ -1927,7 +1927,7 @@ (match_operand:VF_128 1 "nonimmediate_operand" "%x,x") (match_operand:VF_128 2 "nonimmediate_operand" " x,m") (match_operand:VF_128 3 "nonimmediate_operand" "xm,x")) - (match_operand:VF_128 4 "const0_operand" "") + (match_operand:VF_128 4 "const0_operand") (const_int 1)))] "TARGET_FMA4" "vfmadd<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}" @@ -1942,7 +1942,7 @@ (match_operand:VF_128 2 "nonimmediate_operand" " x,m") (neg:VF_128 (match_operand:VF_128 3 "nonimmediate_operand" "xm,x"))) - (match_operand:VF_128 4 "const0_operand" "") + (match_operand:VF_128 4 "const0_operand") (const_int 1)))] "TARGET_FMA4" "vfmsub<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}" @@ -1957,7 +1957,7 @@ (match_operand:VF_128 1 "nonimmediate_operand" "%x,x")) (match_operand:VF_128 2 "nonimmediate_operand" " x,m") (match_operand:VF_128 3 "nonimmediate_operand" "xm,x")) - (match_operand:VF_128 4 "const0_operand" "") + (match_operand:VF_128 4 "const0_operand") (const_int 1)))] "TARGET_FMA4" "vfnmadd<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}" @@ -1973,7 +1973,7 @@ (match_operand:VF_128 2 "nonimmediate_operand" " x,m") (neg:VF_128 (match_operand:VF_128 3 "nonimmediate_operand" "xm,x"))) - (match_operand:VF_128 4 "const0_operand" "") + (match_operand:VF_128 4 "const0_operand") (const_int 1)))] "TARGET_FMA4" "vfnmsub<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}" @@ -2313,8 +2313,8 @@ (set_attr "mode" "<sseinsnmode>")]) (define_expand "floatuns<sseintvecmodelower><mode>2" - [(match_operand:VF1 0 "register_operand" "") - (match_operand:<sseintvecmode> 1 "register_operand" "")] + [(match_operand:VF1 0 "register_operand") + (match_operand:<sseintvecmode> 1 "register_operand")] "TARGET_SSE2 && (<MODE>mode == V4SFmode || TARGET_AVX2)" { ix86_expand_vector_convert_uns_vsivsf (operands[0], operands[1]); @@ -2376,8 +2376,8 @@ (set_attr "mode" "TI")]) (define_expand "fixuns_trunc<mode><sseintvecmodelower>2" - [(match_operand:<sseintvecmode> 0 "register_operand" "") - (match_operand:VF1 1 "register_operand" "")] + [(match_operand:<sseintvecmode> 0 "register_operand") + (match_operand:VF1 1 "register_operand")] "TARGET_SSE2" { rtx tmp[3]; @@ -2606,9 +2606,9 @@ (set_attr "mode" "OI")]) (define_expand "avx_cvtpd2dq256_2" - [(set (match_operand:V8SI 0 "register_operand" "") + [(set (match_operand:V8SI 0 "register_operand") (vec_concat:V8SI - (unspec:V4SI [(match_operand:V4DF 1 "nonimmediate_operand" "")] + (unspec:V4SI [(match_operand:V4DF 1 "nonimmediate_operand")] UNSPEC_FIX_NOTRUNC) (match_dup 2)))] "TARGET_AVX" @@ -2619,7 +2619,7 @@ (vec_concat:V8SI (unspec:V4SI [(match_operand:V4DF 1 "nonimmediate_operand" "xm")] UNSPEC_FIX_NOTRUNC) - (match_operand:V4SI 2 "const0_operand" "")))] + (match_operand:V4SI 2 "const0_operand")))] "TARGET_AVX" "vcvtpd2dq{y}\t{%1, %x0|%x0, %1}" [(set_attr "type" "ssecvt") @@ -2627,9 +2627,9 @@ (set_attr "mode" "OI")]) (define_expand "sse2_cvtpd2dq" - [(set (match_operand:V4SI 0 "register_operand" "") + [(set (match_operand:V4SI 0 "register_operand") (vec_concat:V4SI - (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "")] + (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand")] UNSPEC_FIX_NOTRUNC) (match_dup 2)))] "TARGET_SSE2" @@ -2640,7 +2640,7 @@ (vec_concat:V4SI (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")] UNSPEC_FIX_NOTRUNC) - (match_operand:V2SI 2 "const0_operand" "")))] + (match_operand:V2SI 2 "const0_operand")))] "TARGET_SSE2" { if (TARGET_AVX) @@ -2667,9 +2667,9 @@ (set_attr "mode" "OI")]) (define_expand "avx_cvttpd2dq256_2" - [(set (match_operand:V8SI 0 "register_operand" "") + [(set (match_operand:V8SI 0 "register_operand") (vec_concat:V8SI - (fix:V4SI (match_operand:V4DF 1 "nonimmediate_operand" "")) + (fix:V4SI (match_operand:V4DF 1 "nonimmediate_operand")) (match_dup 2)))] "TARGET_AVX" "operands[2] = CONST0_RTX (V4SImode);") @@ -2678,7 +2678,7 @@ [(set (match_operand:V8SI 0 "register_operand" "=x") (vec_concat:V8SI (fix:V4SI (match_operand:V4DF 1 "nonimmediate_operand" "xm")) - (match_operand:V4SI 2 "const0_operand" "")))] + (match_operand:V4SI 2 "const0_operand")))] "TARGET_AVX" "vcvttpd2dq{y}\t{%1, %x0|%x0, %1}" [(set_attr "type" "ssecvt") @@ -2686,9 +2686,9 @@ (set_attr "mode" "OI")]) (define_expand "sse2_cvttpd2dq" - [(set (match_operand:V4SI 0 "register_operand" "") + [(set (match_operand:V4SI 0 "register_operand") (vec_concat:V4SI - (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "")) + (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand")) (match_dup 2)))] "TARGET_SSE2" "operands[2] = CONST0_RTX (V2SImode);") @@ -2697,7 +2697,7 @@ [(set (match_operand:V4SI 0 "register_operand" "=x") (vec_concat:V4SI (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm")) - (match_operand:V2SI 2 "const0_operand" "")))] + (match_operand:V2SI 2 "const0_operand")))] "TARGET_SSE2" { if (TARGET_AVX) @@ -2766,10 +2766,10 @@ (set_attr "mode" "V4SF")]) (define_expand "sse2_cvtpd2ps" - [(set (match_operand:V4SF 0 "register_operand" "") + [(set (match_operand:V4SF 0 "register_operand") (vec_concat:V4SF (float_truncate:V2SF - (match_operand:V2DF 1 "nonimmediate_operand" "")) + (match_operand:V2DF 1 "nonimmediate_operand")) (match_dup 2)))] "TARGET_SSE2" "operands[2] = CONST0_RTX (V2SFmode);") @@ -2779,7 +2779,7 @@ (vec_concat:V4SF (float_truncate:V2SF (match_operand:V2DF 1 "nonimmediate_operand" "xm")) - (match_operand:V2SF 2 "const0_operand" "")))] + (match_operand:V2SF 2 "const0_operand")))] "TARGET_SSE2" { if (TARGET_AVX) @@ -2839,10 +2839,10 @@ (vec_select:V4SF (vec_concat:V8SF (match_dup 2) - (match_operand:V4SF 1 "nonimmediate_operand" "")) + (match_operand:V4SF 1 "nonimmediate_operand")) (parallel [(const_int 6) (const_int 7) (const_int 2) (const_int 3)]))) - (set (match_operand:V2DF 0 "register_operand" "") + (set (match_operand:V2DF 0 "register_operand") (float_extend:V2DF (vec_select:V2SF (match_dup 2) @@ -2853,28 +2853,28 @@ (define_expand "vec_unpacks_hi_v8sf" [(set (match_dup 2) (vec_select:V4SF - (match_operand:V8SF 1 "nonimmediate_operand" "") + (match_operand:V8SF 1 "nonimmediate_operand") (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7)]))) - (set (match_operand:V4DF 0 "register_operand" "") + (set (match_operand:V4DF 0 "register_operand") (float_extend:V4DF (match_dup 2)))] "TARGET_AVX" "operands[2] = gen_reg_rtx (V4SFmode);") (define_expand "vec_unpacks_lo_v4sf" - [(set (match_operand:V2DF 0 "register_operand" "") + [(set (match_operand:V2DF 0 "register_operand") (float_extend:V2DF (vec_select:V2SF - (match_operand:V4SF 1 "nonimmediate_operand" "") + (match_operand:V4SF 1 "nonimmediate_operand") (parallel [(const_int 0) (const_int 1)]))))] "TARGET_SSE2") (define_expand "vec_unpacks_lo_v8sf" - [(set (match_operand:V4DF 0 "register_operand" "") + [(set (match_operand:V4DF 0 "register_operand") (float_extend:V4DF (vec_select:V4SF - (match_operand:V8SF 1 "nonimmediate_operand" "") + (match_operand:V8SF 1 "nonimmediate_operand") (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)]))))] "TARGET_AVX") @@ -2883,8 +2883,8 @@ [(V8HI "V4SF") (V4SI "V2DF") (V16HI "V8SF") (V8SI "V4DF")]) (define_expand "vec_unpacks_float_hi_<mode>" - [(match_operand:<sseunpackfltmode> 0 "register_operand" "") - (match_operand:VI2_AVX2 1 "register_operand" "")] + [(match_operand:<sseunpackfltmode> 0 "register_operand") + (match_operand:VI2_AVX2 1 "register_operand")] "TARGET_SSE2" { rtx tmp = gen_reg_rtx (<sseunpackmode>mode); @@ -2896,8 +2896,8 @@ }) (define_expand "vec_unpacks_float_lo_<mode>" - [(match_operand:<sseunpackfltmode> 0 "register_operand" "") - (match_operand:VI2_AVX2 1 "register_operand" "")] + [(match_operand:<sseunpackfltmode> 0 "register_operand") + (match_operand:VI2_AVX2 1 "register_operand")] "TARGET_SSE2" { rtx tmp = gen_reg_rtx (<sseunpackmode>mode); @@ -2909,8 +2909,8 @@ }) (define_expand "vec_unpacku_float_hi_<mode>" - [(match_operand:<sseunpackfltmode> 0 "register_operand" "") - (match_operand:VI2_AVX2 1 "register_operand" "")] + [(match_operand:<sseunpackfltmode> 0 "register_operand") + (match_operand:VI2_AVX2 1 "register_operand")] "TARGET_SSE2" { rtx tmp = gen_reg_rtx (<sseunpackmode>mode); @@ -2922,8 +2922,8 @@ }) (define_expand "vec_unpacku_float_lo_<mode>" - [(match_operand:<sseunpackfltmode> 0 "register_operand" "") - (match_operand:VI2_AVX2 1 "register_operand" "")] + [(match_operand:<sseunpackfltmode> 0 "register_operand") + (match_operand:VI2_AVX2 1 "register_operand")] "TARGET_SSE2" { rtx tmp = gen_reg_rtx (<sseunpackmode>mode); @@ -2937,10 +2937,10 @@ (define_expand "vec_unpacks_float_hi_v4si" [(set (match_dup 2) (vec_select:V4SI - (match_operand:V4SI 1 "nonimmediate_operand" "") + (match_operand:V4SI 1 "nonimmediate_operand") (parallel [(const_int 2) (const_int 3) (const_int 2) (const_int 3)]))) - (set (match_operand:V2DF 0 "register_operand" "") + (set (match_operand:V2DF 0 "register_operand") (float:V2DF (vec_select:V2SI (match_dup 2) @@ -2949,30 +2949,30 @@ "operands[2] = gen_reg_rtx (V4SImode);") (define_expand "vec_unpacks_float_lo_v4si" - [(set (match_operand:V2DF 0 "register_operand" "") + [(set (match_operand:V2DF 0 "register_operand") (float:V2DF (vec_select:V2SI - (match_operand:V4SI 1 "nonimmediate_operand" "") + (match_operand:V4SI 1 "nonimmediate_operand") (parallel [(const_int 0) (const_int 1)]))))] "TARGET_SSE2") (define_expand "vec_unpacks_float_hi_v8si" [(set (match_dup 2) (vec_select:V4SI - (match_operand:V8SI 1 "nonimmediate_operand" "") + (match_operand:V8SI 1 "nonimmediate_operand") (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7)]))) - (set (match_operand:V4DF 0 "register_operand" "") + (set (match_operand:V4DF 0 "register_operand") (float:V4DF (match_dup 2)))] "TARGET_AVX" "operands[2] = gen_reg_rtx (V4SImode);") (define_expand "vec_unpacks_float_lo_v8si" - [(set (match_operand:V4DF 0 "register_operand" "") + [(set (match_operand:V4DF 0 "register_operand") (float:V4DF (vec_select:V4SI - (match_operand:V8SI 1 "nonimmediate_operand" "") + (match_operand:V8SI 1 "nonimmediate_operand") (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)]))))] "TARGET_AVX") @@ -2980,7 +2980,7 @@ (define_expand "vec_unpacku_float_hi_v4si" [(set (match_dup 5) (vec_select:V4SI - (match_operand:V4SI 1 "nonimmediate_operand" "") + (match_operand:V4SI 1 "nonimmediate_operand") (parallel [(const_int 2) (const_int 3) (const_int 2) (const_int 3)]))) (set (match_dup 6) @@ -2992,7 +2992,7 @@ (lt:V2DF (match_dup 6) (match_dup 3))) (set (match_dup 8) (and:V2DF (match_dup 7) (match_dup 4))) - (set (match_operand:V2DF 0 "register_operand" "") + (set (match_operand:V2DF 0 "register_operand") (plus:V2DF (match_dup 6) (match_dup 8)))] "TARGET_SSE2" { @@ -3017,13 +3017,13 @@ [(set (match_dup 5) (float:V2DF (vec_select:V2SI - (match_operand:V4SI 1 "nonimmediate_operand" "") + (match_operand:V4SI 1 "nonimmediate_operand") (parallel [(const_int 0) (const_int 1)])))) (set (match_dup 6) (lt:V2DF (match_dup 5) (match_dup 3))) (set (match_dup 7) (and:V2DF (match_dup 6) (match_dup 4))) - (set (match_operand:V2DF 0 "register_operand" "") + (set (match_operand:V2DF 0 "register_operand") (plus:V2DF (match_dup 5) (match_dup 7)))] "TARGET_SSE2" { @@ -3043,8 +3043,8 @@ }) (define_expand "vec_unpacku_float_hi_v8si" - [(match_operand:V4DF 0 "register_operand" "") - (match_operand:V8SI 1 "register_operand" "")] + [(match_operand:V4DF 0 "register_operand") + (match_operand:V8SI 1 "register_operand")] "TARGET_AVX" { REAL_VALUE_TYPE TWO32r; @@ -3070,8 +3070,8 @@ }) (define_expand "vec_unpacku_float_lo_v8si" - [(match_operand:V4DF 0 "register_operand" "") - (match_operand:V8SI 1 "nonimmediate_operand" "")] + [(match_operand:V4DF 0 "register_operand") + (match_operand:V8SI 1 "nonimmediate_operand")] "TARGET_AVX" { REAL_VALUE_TYPE TWO32r; @@ -3097,11 +3097,11 @@ (define_expand "vec_pack_trunc_v4df" [(set (match_dup 3) (float_truncate:V4SF - (match_operand:V4DF 1 "nonimmediate_operand" ""))) + (match_operand:V4DF 1 "nonimmediate_operand"))) (set (match_dup 4) (float_truncate:V4SF - (match_operand:V4DF 2 "nonimmediate_operand" ""))) - (set (match_operand:V8SF 0 "register_operand" "") + (match_operand:V4DF 2 "nonimmediate_operand"))) + (set (match_operand:V8SF 0 "register_operand") (vec_concat:V8SF (match_dup 3) (match_dup 4)))] @@ -3112,9 +3112,9 @@ }) (define_expand "vec_pack_trunc_v2df" - [(match_operand:V4SF 0 "register_operand" "") - (match_operand:V2DF 1 "nonimmediate_operand" "") - (match_operand:V2DF 2 "nonimmediate_operand" "")] + [(match_operand:V4SF 0 "register_operand") + (match_operand:V2DF 1 "nonimmediate_operand") + (match_operand:V2DF 2 "nonimmediate_operand")] "TARGET_SSE2" { rtx tmp0, tmp1; @@ -3140,9 +3140,9 @@ }) (define_expand "vec_pack_sfix_trunc_v4df" - [(match_operand:V8SI 0 "register_operand" "") - (match_operand:V4DF 1 "nonimmediate_operand" "") - (match_operand:V4DF 2 "nonimmediate_operand" "")] + [(match_operand:V8SI 0 "register_operand") + (match_operand:V4DF 1 "nonimmediate_operand") + (match_operand:V4DF 2 "nonimmediate_operand")] "TARGET_AVX" { rtx r1, r2; @@ -3157,9 +3157,9 @@ }) (define_expand "vec_pack_sfix_trunc_v2df" - [(match_operand:V4SI 0 "register_operand" "") - (match_operand:V2DF 1 "nonimmediate_operand" "") - (match_operand:V2DF 2 "nonimmediate_operand" "")] + [(match_operand:V4SI 0 "register_operand") + (match_operand:V2DF 1 "nonimmediate_operand") + (match_operand:V2DF 2 "nonimmediate_operand")] "TARGET_SSE2" { rtx tmp0, tmp1; @@ -3191,9 +3191,9 @@ [(V4DF "V8SI") (V2DF "V4SI")]) (define_expand "vec_pack_ufix_trunc_<mode>" - [(match_operand:<ssepackfltmode> 0 "register_operand" "") - (match_operand:VF2 1 "register_operand" "") - (match_operand:VF2 2 "register_operand" "")] + [(match_operand:<ssepackfltmode> 0 "register_operand") + (match_operand:VF2 1 "register_operand") + (match_operand:VF2 2 "register_operand")] "TARGET_SSE2" { rtx tmp[7]; @@ -3221,9 +3221,9 @@ }) (define_expand "vec_pack_sfix_v4df" - [(match_operand:V8SI 0 "register_operand" "") - (match_operand:V4DF 1 "nonimmediate_operand" "") - (match_operand:V4DF 2 "nonimmediate_operand" "")] + [(match_operand:V8SI 0 "register_operand") + (match_operand:V4DF 1 "nonimmediate_operand") + (match_operand:V4DF 2 "nonimmediate_operand")] "TARGET_AVX" { rtx r1, r2; @@ -3238,9 +3238,9 @@ }) (define_expand "vec_pack_sfix_v2df" - [(match_operand:V4SI 0 "register_operand" "") - (match_operand:V2DF 1 "nonimmediate_operand" "") - (match_operand:V2DF 2 "nonimmediate_operand" "")] + [(match_operand:V4SI 0 "register_operand") + (match_operand:V2DF 1 "nonimmediate_operand") + (match_operand:V2DF 2 "nonimmediate_operand")] "TARGET_SSE2" { rtx tmp0, tmp1; @@ -3275,11 +3275,11 @@ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (define_expand "sse_movhlps_exp" - [(set (match_operand:V4SF 0 "nonimmediate_operand" "") + [(set (match_operand:V4SF 0 "nonimmediate_operand") (vec_select:V4SF (vec_concat:V8SF - (match_operand:V4SF 1 "nonimmediate_operand" "") - (match_operand:V4SF 2 "nonimmediate_operand" "")) + (match_operand:V4SF 1 "nonimmediate_operand") + (match_operand:V4SF 2 "nonimmediate_operand")) (parallel [(const_int 6) (const_int 7) (const_int 2) @@ -3320,11 +3320,11 @@ (set_attr "mode" "V4SF,V4SF,V2SF,V2SF,V2SF")]) (define_expand "sse_movlhps_exp" - [(set (match_operand:V4SF 0 "nonimmediate_operand" "") + [(set (match_operand:V4SF 0 "nonimmediate_operand") (vec_select:V4SF (vec_concat:V8SF - (match_operand:V4SF 1 "nonimmediate_operand" "") - (match_operand:V4SF 2 "nonimmediate_operand" "")) + (match_operand:V4SF 1 "nonimmediate_operand") + (match_operand:V4SF 2 "nonimmediate_operand")) (parallel [(const_int 0) (const_int 1) (const_int 4) @@ -3400,7 +3400,7 @@ (const_int 3) (const_int 11) (const_int 6) (const_int 14) (const_int 7) (const_int 15)]))) - (set (match_operand:V8SF 0 "register_operand" "") + (set (match_operand:V8SF 0 "register_operand") (vec_select:V8SF (vec_concat:V16SF (match_dup 3) @@ -3468,7 +3468,7 @@ (const_int 3) (const_int 11) (const_int 6) (const_int 14) (const_int 7) (const_int 15)]))) - (set (match_operand:V8SF 0 "register_operand" "") + (set (match_operand:V8SF 0 "register_operand") (vec_select:V8SF (vec_concat:V16SF (match_dup 3) @@ -3569,10 +3569,10 @@ (set_attr "mode" "V4SF")]) (define_expand "avx_shufps256" - [(match_operand:V8SF 0 "register_operand" "") - (match_operand:V8SF 1 "register_operand" "") - (match_operand:V8SF 2 "nonimmediate_operand" "") - (match_operand:SI 3 "const_int_operand" "")] + [(match_operand:V8SF 0 "register_operand") + (match_operand:V8SF 1 "register_operand") + (match_operand:V8SF 2 "nonimmediate_operand") + (match_operand:SI 3 "const_int_operand")] "TARGET_AVX" { int mask = INTVAL (operands[3]); @@ -3595,14 +3595,14 @@ (vec_concat:V16SF (match_operand:V8SF 1 "register_operand" "x") (match_operand:V8SF 2 "nonimmediate_operand" "xm")) - (parallel [(match_operand 3 "const_0_to_3_operand" "") - (match_operand 4 "const_0_to_3_operand" "") - (match_operand 5 "const_8_to_11_operand" "") - (match_operand 6 "const_8_to_11_operand" "") - (match_operand 7 "const_4_to_7_operand" "") - (match_operand 8 "const_4_to_7_operand" "") - (match_operand 9 "const_12_to_15_operand" "") - (match_operand 10 "const_12_to_15_operand" "")])))] + (parallel [(match_operand 3 "const_0_to_3_operand" ) + (match_operand 4 "const_0_to_3_operand" ) + (match_operand 5 "const_8_to_11_operand" ) + (match_operand 6 "const_8_to_11_operand" ) + (match_operand 7 "const_4_to_7_operand" ) + (match_operand 8 "const_4_to_7_operand" ) + (match_operand 9 "const_12_to_15_operand") + (match_operand 10 "const_12_to_15_operand")])))] "TARGET_AVX && (INTVAL (operands[3]) == (INTVAL (operands[7]) - 4) && INTVAL (operands[4]) == (INTVAL (operands[8]) - 4) @@ -3624,10 +3624,10 @@ (set_attr "mode" "V8SF")]) (define_expand "sse_shufps" - [(match_operand:V4SF 0 "register_operand" "") - (match_operand:V4SF 1 "register_operand" "") - (match_operand:V4SF 2 "nonimmediate_operand" "") - (match_operand:SI 3 "const_int_operand" "")] + [(match_operand:V4SF 0 "register_operand") + (match_operand:V4SF 1 "register_operand") + (match_operand:V4SF 2 "nonimmediate_operand") + (match_operand:SI 3 "const_int_operand")] "TARGET_SSE" { int mask = INTVAL (operands[3]); @@ -3645,10 +3645,10 @@ (vec_concat:<ssedoublevecmode> (match_operand:VI4F_128 1 "register_operand" "0,x") (match_operand:VI4F_128 2 "nonimmediate_operand" "xm,xm")) - (parallel [(match_operand 3 "const_0_to_3_operand" "") - (match_operand 4 "const_0_to_3_operand" "") - (match_operand 5 "const_4_to_7_operand" "") - (match_operand 6 "const_4_to_7_operand" "")])))] + (parallel [(match_operand 3 "const_0_to_3_operand") + (match_operand 4 "const_0_to_3_operand") + (match_operand 5 "const_4_to_7_operand") + (match_operand 6 "const_4_to_7_operand")])))] "TARGET_SSE" { int mask = 0; @@ -3689,12 +3689,12 @@ (set_attr "mode" "V2SF,V4SF,V2SF")]) (define_expand "sse_loadhps_exp" - [(set (match_operand:V4SF 0 "nonimmediate_operand" "") + [(set (match_operand:V4SF 0 "nonimmediate_operand") (vec_concat:V4SF (vec_select:V2SF - (match_operand:V4SF 1 "nonimmediate_operand" "") + (match_operand:V4SF 1 "nonimmediate_operand") (parallel [(const_int 0) (const_int 1)])) - (match_operand:V2SF 2 "nonimmediate_operand" "")))] + (match_operand:V2SF 2 "nonimmediate_operand")))] "TARGET_SSE" { rtx dst = ix86_fixup_binary_operands (UNKNOWN, V4SFmode, operands); @@ -3742,11 +3742,11 @@ (set_attr "mode" "V2SF,V4SF,V2SF")]) (define_expand "sse_loadlps_exp" - [(set (match_operand:V4SF 0 "nonimmediate_operand" "") + [(set (match_operand:V4SF 0 "nonimmediate_operand") (vec_concat:V4SF - (match_operand:V2SF 2 "nonimmediate_operand" "") + (match_operand:V2SF 2 "nonimmediate_operand") (vec_select:V2SF - (match_operand:V4SF 1 "nonimmediate_operand" "") + (match_operand:V4SF 1 "nonimmediate_operand") (parallel [(const_int 2) (const_int 3)]))))] "TARGET_SSE" { @@ -3882,8 +3882,8 @@ (set_attr "mode" "V4SF,V4SF,V2SF,V2SF")]) (define_expand "vec_init<mode>" - [(match_operand:V_128 0 "register_operand" "") - (match_operand 1 "" "")] + [(match_operand:V_128 0 "register_operand") + (match_operand 1)] "TARGET_SSE" { ix86_expand_vector_init (false, operands[0], operands[1]); @@ -3937,7 +3937,7 @@ (vec_duplicate:V4SF (match_operand:SF 2 "nonimmediate_operand" "xm,xm")) (match_operand:V4SF 1 "register_operand" "0,x") - (match_operand:SI 3 "const_int_operand" "")))] + (match_operand:SI 3 "const_int_operand")))] "TARGET_SSE4_1 && ((unsigned) exact_log2 (INTVAL (operands[3])) < GET_MODE_NUNITS (V4SFmode))" @@ -3995,10 +3995,10 @@ (set_attr "mode" "V4SF")]) (define_split - [(set (match_operand:VI4F_128 0 "memory_operand" "") + [(set (match_operand:VI4F_128 0 "memory_operand") (vec_merge:VI4F_128 (vec_duplicate:VI4F_128 - (match_operand:<ssescalarmode> 1 "nonmemory_operand" "")) + (match_operand:<ssescalarmode> 1 "nonmemory_operand")) (match_dup 0) (const_int 1)))] "TARGET_SSE && reload_completed" @@ -4010,9 +4010,9 @@ }) (define_expand "vec_set<mode>" - [(match_operand:V 0 "register_operand" "") - (match_operand:<ssescalarmode> 1 "register_operand" "") - (match_operand 2 "const_int_operand" "")] + [(match_operand:V 0 "register_operand") + (match_operand:<ssescalarmode> 1 "register_operand") + (match_operand 2 "const_int_operand")] "TARGET_SSE" { ix86_expand_vector_set (false, operands[0], operands[1], @@ -4096,9 +4096,9 @@ }) (define_expand "avx_vextractf128<mode>" - [(match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "") - (match_operand:V_256 1 "register_operand" "") - (match_operand:SI 2 "const_0_to_1_operand" "")] + [(match_operand:<ssehalfvecmode> 0 "nonimmediate_operand") + (match_operand:V_256 1 "register_operand") + (match_operand:SI 2 "const_0_to_1_operand")] "TARGET_AVX" { rtx (*insn)(rtx, rtx); @@ -4283,9 +4283,9 @@ (V4DF "TARGET_AVX") V2DF]) (define_expand "vec_extract<mode>" - [(match_operand:<ssescalarmode> 0 "register_operand" "") - (match_operand:VEC_EXTRACT_MODE 1 "register_operand" "") - (match_operand 2 "const_int_operand" "")] + [(match_operand:<ssescalarmode> 0 "register_operand") + (match_operand:VEC_EXTRACT_MODE 1 "register_operand") + (match_operand 2 "const_int_operand")] "TARGET_SSE" { ix86_expand_vector_extract (false, operands[0], operands[1], @@ -4329,7 +4329,7 @@ (match_dup 2)) (parallel [(const_int 1) (const_int 5) (const_int 3) (const_int 7)]))) - (set (match_operand:V4DF 0 "register_operand" "") + (set (match_operand:V4DF 0 "register_operand") (vec_select:V4DF (vec_concat:V8DF (match_dup 3) @@ -4344,11 +4344,11 @@ (define_expand "vec_interleave_highv2df" - [(set (match_operand:V2DF 0 "register_operand" "") + [(set (match_operand:V2DF 0 "register_operand") (vec_select:V2DF (vec_concat:V4DF - (match_operand:V2DF 1 "nonimmediate_operand" "") - (match_operand:V2DF 2 "nonimmediate_operand" "")) + (match_operand:V2DF 1 "nonimmediate_operand") + (match_operand:V2DF 2 "nonimmediate_operand")) (parallel [(const_int 1) (const_int 3)])))] "TARGET_SSE2" @@ -4381,21 +4381,21 @@ ;; Recall that the 256-bit unpck insns only shuffle within their lanes. (define_expand "avx_movddup256" - [(set (match_operand:V4DF 0 "register_operand" "") + [(set (match_operand:V4DF 0 "register_operand") (vec_select:V4DF (vec_concat:V8DF - (match_operand:V4DF 1 "nonimmediate_operand" "") + (match_operand:V4DF 1 "nonimmediate_operand") (match_dup 1)) (parallel [(const_int 0) (const_int 4) (const_int 2) (const_int 6)])))] "TARGET_AVX") (define_expand "avx_unpcklpd256" - [(set (match_operand:V4DF 0 "register_operand" "") + [(set (match_operand:V4DF 0 "register_operand") (vec_select:V4DF (vec_concat:V8DF - (match_operand:V4DF 1 "register_operand" "") - (match_operand:V4DF 2 "nonimmediate_operand" "")) + (match_operand:V4DF 1 "register_operand") + (match_operand:V4DF 2 "nonimmediate_operand")) (parallel [(const_int 0) (const_int 4) (const_int 2) (const_int 6)])))] "TARGET_AVX") @@ -4431,7 +4431,7 @@ (match_dup 2)) (parallel [(const_int 1) (const_int 5) (const_int 3) (const_int 7)]))) - (set (match_operand:V4DF 0 "register_operand" "") + (set (match_operand:V4DF 0 "register_operand") (vec_select:V4DF (vec_concat:V8DF (match_dup 3) @@ -4445,11 +4445,11 @@ }) (define_expand "vec_interleave_lowv2df" - [(set (match_operand:V2DF 0 "register_operand" "") + [(set (match_operand:V2DF 0 "register_operand") (vec_select:V2DF (vec_concat:V4DF - (match_operand:V2DF 1 "nonimmediate_operand" "") - (match_operand:V2DF 2 "nonimmediate_operand" "")) + (match_operand:V2DF 1 "nonimmediate_operand") + (match_operand:V2DF 2 "nonimmediate_operand")) (parallel [(const_int 0) (const_int 2)])))] "TARGET_SSE2" @@ -4481,10 +4481,10 @@ (set_attr "mode" "V2DF,V2DF,V2DF,V1DF,V1DF,V1DF")]) (define_split - [(set (match_operand:V2DF 0 "memory_operand" "") + [(set (match_operand:V2DF 0 "memory_operand") (vec_select:V2DF (vec_concat:V4DF - (match_operand:V2DF 1 "register_operand" "") + (match_operand:V2DF 1 "register_operand") (match_dup 1)) (parallel [(const_int 0) (const_int 2)])))] @@ -4498,13 +4498,13 @@ }) (define_split - [(set (match_operand:V2DF 0 "register_operand" "") + [(set (match_operand:V2DF 0 "register_operand") (vec_select:V2DF (vec_concat:V4DF - (match_operand:V2DF 1 "memory_operand" "") + (match_operand:V2DF 1 "memory_operand") (match_dup 1)) - (parallel [(match_operand:SI 2 "const_0_to_1_operand" "") - (match_operand:SI 3 "const_int_operand" "")])))] + (parallel [(match_operand:SI 2 "const_0_to_1_operand") + (match_operand:SI 3 "const_int_operand")])))] "TARGET_SSE3 && INTVAL (operands[2]) + 2 == INTVAL (operands[3])" [(set (match_dup 0) (vec_duplicate:V2DF (match_dup 1)))] { @@ -4512,10 +4512,10 @@ }) (define_expand "avx_shufpd256" - [(match_operand:V4DF 0 "register_operand" "") - (match_operand:V4DF 1 "register_operand" "") - (match_operand:V4DF 2 "nonimmediate_operand" "") - (match_operand:SI 3 "const_int_operand" "")] + [(match_operand:V4DF 0 "register_operand") + (match_operand:V4DF 1 "register_operand") + (match_operand:V4DF 2 "nonimmediate_operand") + (match_operand:SI 3 "const_int_operand")] "TARGET_AVX" { int mask = INTVAL (operands[3]); @@ -4533,10 +4533,10 @@ (vec_concat:V8DF (match_operand:V4DF 1 "register_operand" "x") (match_operand:V4DF 2 "nonimmediate_operand" "xm")) - (parallel [(match_operand 3 "const_0_to_1_operand" "") - (match_operand 4 "const_4_to_5_operand" "") - (match_operand 5 "const_2_to_3_operand" "") - (match_operand 6 "const_6_to_7_operand" "")])))] + (parallel [(match_operand 3 "const_0_to_1_operand") + (match_operand 4 "const_4_to_5_operand") + (match_operand 5 "const_2_to_3_operand") + (match_operand 6 "const_6_to_7_operand")])))] "TARGET_AVX" { int mask; @@ -4554,10 +4554,10 @@ (set_attr "mode" "V4DF")]) (define_expand "sse2_shufpd" - [(match_operand:V2DF 0 "register_operand" "") - (match_operand:V2DF 1 "register_operand" "") - (match_operand:V2DF 2 "nonimmediate_operand" "") - (match_operand:SI 3 "const_int_operand" "")] + [(match_operand:V2DF 0 "register_operand") + (match_operand:V2DF 1 "register_operand") + (match_operand:V2DF 2 "nonimmediate_operand") + (match_operand:SI 3 "const_int_operand")] "TARGET_SSE2" { int mask = INTVAL (operands[3]); @@ -4642,8 +4642,8 @@ (vec_concat:<ssedoublevecmode> (match_operand:VI8F_128 1 "register_operand" "0,x") (match_operand:VI8F_128 2 "nonimmediate_operand" "xm,xm")) - (parallel [(match_operand 3 "const_0_to_1_operand" "") - (match_operand 4 "const_2_to_3_operand" "")])))] + (parallel [(match_operand 3 "const_0_to_1_operand") + (match_operand 4 "const_2_to_3_operand")])))] "TARGET_SSE2" { int mask; @@ -4694,9 +4694,9 @@ (set_attr "mode" "V1DF,V1DF,V2DF,DF,DF,DF")]) (define_split - [(set (match_operand:DF 0 "register_operand" "") + [(set (match_operand:DF 0 "register_operand") (vec_select:DF - (match_operand:V2DF 1 "memory_operand" "") + (match_operand:V2DF 1 "memory_operand") (parallel [(const_int 1)])))] "TARGET_SSE2 && reload_completed" [(set (match_dup 0) (match_dup 1))] @@ -4736,9 +4736,9 @@ (set_attr "mode" "V1DF,DF,DF,DF,DF")]) (define_split - [(set (match_operand:DF 0 "register_operand" "") + [(set (match_operand:DF 0 "register_operand") (vec_select:DF - (match_operand:V2DF 1 "nonimmediate_operand" "") + (match_operand:V2DF 1 "nonimmediate_operand") (parallel [(const_int 0)])))] "TARGET_SSE2 && reload_completed" [(const_int 0)] @@ -4767,12 +4767,12 @@ (set_attr "mode" "V2SF,V4SF,V2SF")]) (define_expand "sse2_loadhpd_exp" - [(set (match_operand:V2DF 0 "nonimmediate_operand" "") + [(set (match_operand:V2DF 0 "nonimmediate_operand") (vec_concat:V2DF (vec_select:DF - (match_operand:V2DF 1 "nonimmediate_operand" "") + (match_operand:V2DF 1 "nonimmediate_operand") (parallel [(const_int 0)])) - (match_operand:DF 2 "nonimmediate_operand" "")))] + (match_operand:DF 2 "nonimmediate_operand")))] "TARGET_SSE2" { rtx dst = ix86_fixup_binary_operands (UNKNOWN, V2DFmode, operands); @@ -4814,20 +4814,20 @@ (set_attr "mode" "V1DF,V1DF,V2DF,V2DF,DF,DF,DF")]) (define_split - [(set (match_operand:V2DF 0 "memory_operand" "") + [(set (match_operand:V2DF 0 "memory_operand") (vec_concat:V2DF (vec_select:DF (match_dup 0) (parallel [(const_int 0)])) - (match_operand:DF 1 "register_operand" "")))] + (match_operand:DF 1 "register_operand")))] "TARGET_SSE2 && reload_completed" [(set (match_dup 0) (match_dup 1))] "operands[0] = adjust_address (operands[0], DFmode, 8);") (define_expand "sse2_loadlpd_exp" - [(set (match_operand:V2DF 0 "nonimmediate_operand" "") + [(set (match_operand:V2DF 0 "nonimmediate_operand") (vec_concat:V2DF - (match_operand:DF 2 "nonimmediate_operand" "") + (match_operand:DF 2 "nonimmediate_operand") (vec_select:DF - (match_operand:V2DF 1 "nonimmediate_operand" "") + (match_operand:V2DF 1 "nonimmediate_operand") (parallel [(const_int 1)]))))] "TARGET_SSE2" { @@ -4883,9 +4883,9 @@ (set_attr "mode" "DF,V1DF,V1DF,V1DF,V1DF,V2DF,V1DF,V1DF,DF,DF,DF")]) (define_split - [(set (match_operand:V2DF 0 "memory_operand" "") + [(set (match_operand:V2DF 0 "memory_operand") (vec_concat:V2DF - (match_operand:DF 1 "register_operand" "") + (match_operand:DF 1 "register_operand") (vec_select:DF (match_dup 0) (parallel [(const_int 1)]))))] "TARGET_SSE2 && reload_completed" [(set (match_dup 0) (match_dup 1))] @@ -4969,18 +4969,18 @@ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (define_expand "neg<mode>2" - [(set (match_operand:VI_AVX2 0 "register_operand" "") + [(set (match_operand:VI_AVX2 0 "register_operand") (minus:VI_AVX2 (match_dup 2) - (match_operand:VI_AVX2 1 "nonimmediate_operand" "")))] + (match_operand:VI_AVX2 1 "nonimmediate_operand")))] "TARGET_SSE2" "operands[2] = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode));") (define_expand "<plusminus_insn><mode>3" - [(set (match_operand:VI_AVX2 0 "register_operand" "") + [(set (match_operand:VI_AVX2 0 "register_operand") (plusminus:VI_AVX2 - (match_operand:VI_AVX2 1 "nonimmediate_operand" "") - (match_operand:VI_AVX2 2 "nonimmediate_operand" "")))] + (match_operand:VI_AVX2 1 "nonimmediate_operand") + (match_operand:VI_AVX2 2 "nonimmediate_operand")))] "TARGET_SSE2" "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") @@ -5000,10 +5000,10 @@ (set_attr "mode" "<sseinsnmode>")]) (define_expand "<sse2_avx2>_<plusminus_insn><mode>3" - [(set (match_operand:VI12_AVX2 0 "register_operand" "") + [(set (match_operand:VI12_AVX2 0 "register_operand") (sat_plusminus:VI12_AVX2 - (match_operand:VI12_AVX2 1 "nonimmediate_operand" "") - (match_operand:VI12_AVX2 2 "nonimmediate_operand" "")))] + (match_operand:VI12_AVX2 1 "nonimmediate_operand") + (match_operand:VI12_AVX2 2 "nonimmediate_operand")))] "TARGET_SSE2" "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") @@ -5023,9 +5023,9 @@ (set_attr "mode" "TI")]) (define_insn_and_split "mul<mode>3" - [(set (match_operand:VI1_AVX2 0 "register_operand" "") - (mult:VI1_AVX2 (match_operand:VI1_AVX2 1 "register_operand" "") - (match_operand:VI1_AVX2 2 "register_operand" "")))] + [(set (match_operand:VI1_AVX2 0 "register_operand") + (mult:VI1_AVX2 (match_operand:VI1_AVX2 1 "register_operand") + (match_operand:VI1_AVX2 2 "register_operand")))] "TARGET_SSE2 && can_create_pseudo_p ()" "#" @@ -5090,9 +5090,9 @@ }) (define_expand "mul<mode>3" - [(set (match_operand:VI2_AVX2 0 "register_operand" "") - (mult:VI2_AVX2 (match_operand:VI2_AVX2 1 "nonimmediate_operand" "") - (match_operand:VI2_AVX2 2 "nonimmediate_operand" "")))] + [(set (match_operand:VI2_AVX2 0 "register_operand") + (mult:VI2_AVX2 (match_operand:VI2_AVX2 1 "nonimmediate_operand") + (match_operand:VI2_AVX2 2 "nonimmediate_operand")))] "TARGET_SSE2" "ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands);") @@ -5111,14 +5111,14 @@ (set_attr "mode" "<sseinsnmode>")]) (define_expand "<s>mul<mode>3_highpart" - [(set (match_operand:VI2_AVX2 0 "register_operand" "") + [(set (match_operand:VI2_AVX2 0 "register_operand") (truncate:VI2_AVX2 (lshiftrt:<ssedoublemode> (mult:<ssedoublemode> (any_extend:<ssedoublemode> - (match_operand:VI2_AVX2 1 "nonimmediate_operand" "")) + (match_operand:VI2_AVX2 1 "nonimmediate_operand")) (any_extend:<ssedoublemode> - (match_operand:VI2_AVX2 2 "nonimmediate_operand" ""))) + (match_operand:VI2_AVX2 2 "nonimmediate_operand"))) (const_int 16))))] "TARGET_SSE2" "ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands);") @@ -5144,16 +5144,16 @@ (set_attr "mode" "<sseinsnmode>")]) (define_expand "avx2_umulv4siv4di3" - [(set (match_operand:V4DI 0 "register_operand" "") + [(set (match_operand:V4DI 0 "register_operand") (mult:V4DI (zero_extend:V4DI (vec_select:V4SI - (match_operand:V8SI 1 "nonimmediate_operand" "") + (match_operand:V8SI 1 "nonimmediate_operand") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)]))) (zero_extend:V4DI (vec_select:V4SI - (match_operand:V8SI 2 "nonimmediate_operand" "") + (match_operand:V8SI 2 "nonimmediate_operand") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)])))))] "TARGET_AVX2" @@ -5179,15 +5179,15 @@ (set_attr "mode" "OI")]) (define_expand "sse2_umulv2siv2di3" - [(set (match_operand:V2DI 0 "register_operand" "") + [(set (match_operand:V2DI 0 "register_operand") (mult:V2DI (zero_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 1 "nonimmediate_operand" "") + (match_operand:V4SI 1 "nonimmediate_operand") (parallel [(const_int 0) (const_int 2)]))) (zero_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 2 "nonimmediate_operand" "") + (match_operand:V4SI 2 "nonimmediate_operand") (parallel [(const_int 0) (const_int 2)])))))] "TARGET_SSE2" "ix86_fixup_binary_operands_no_copy (MULT, V4SImode, operands);") @@ -5214,16 +5214,16 @@ (set_attr "mode" "TI")]) (define_expand "avx2_mulv4siv4di3" - [(set (match_operand:V4DI 0 "register_operand" "") + [(set (match_operand:V4DI 0 "register_operand") (mult:V4DI (sign_extend:V4DI (vec_select:V4SI - (match_operand:V8SI 1 "nonimmediate_operand" "") + (match_operand:V8SI 1 "nonimmediate_operand") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)]))) (sign_extend:V4DI (vec_select:V4SI - (match_operand:V8SI 2 "nonimmediate_operand" "") + (match_operand:V8SI 2 "nonimmediate_operand") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)])))))] "TARGET_AVX2" @@ -5251,15 +5251,15 @@ (set_attr "mode" "OI")]) (define_expand "sse4_1_mulv2siv2di3" - [(set (match_operand:V2DI 0 "register_operand" "") + [(set (match_operand:V2DI 0 "register_operand") (mult:V2DI (sign_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 1 "nonimmediate_operand" "") + (match_operand:V4SI 1 "nonimmediate_operand") (parallel [(const_int 0) (const_int 2)]))) (sign_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 2 "nonimmediate_operand" "") + (match_operand:V4SI 2 "nonimmediate_operand") (parallel [(const_int 0) (const_int 2)])))))] "TARGET_SSE4_1" "ix86_fixup_binary_operands_no_copy (MULT, V4SImode, operands);") @@ -5287,12 +5287,12 @@ (set_attr "mode" "TI")]) (define_expand "avx2_pmaddwd" - [(set (match_operand:V8SI 0 "register_operand" "") + [(set (match_operand:V8SI 0 "register_operand") (plus:V8SI (mult:V8SI (sign_extend:V8SI (vec_select:V8HI - (match_operand:V16HI 1 "nonimmediate_operand" "") + (match_operand:V16HI 1 "nonimmediate_operand") (parallel [(const_int 0) (const_int 2) (const_int 4) @@ -5303,7 +5303,7 @@ (const_int 14)]))) (sign_extend:V8SI (vec_select:V8HI - (match_operand:V16HI 2 "nonimmediate_operand" "") + (match_operand:V16HI 2 "nonimmediate_operand") (parallel [(const_int 0) (const_int 2) (const_int 4) @@ -5337,19 +5337,19 @@ "ix86_fixup_binary_operands_no_copy (MULT, V16HImode, operands);") (define_expand "sse2_pmaddwd" - [(set (match_operand:V4SI 0 "register_operand" "") + [(set (match_operand:V4SI 0 "register_operand") (plus:V4SI (mult:V4SI (sign_extend:V4SI (vec_select:V4HI - (match_operand:V8HI 1 "nonimmediate_operand" "") + (match_operand:V8HI 1 "nonimmediate_operand") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)]))) (sign_extend:V4SI (vec_select:V4HI - (match_operand:V8HI 2 "nonimmediate_operand" "") + (match_operand:V8HI 2 "nonimmediate_operand") (parallel [(const_int 0) (const_int 2) (const_int 4) @@ -5466,9 +5466,9 @@ (set_attr "mode" "TI")]) (define_expand "mul<mode>3" - [(set (match_operand:VI4_AVX2 0 "register_operand" "") - (mult:VI4_AVX2 (match_operand:VI4_AVX2 1 "register_operand" "") - (match_operand:VI4_AVX2 2 "register_operand" "")))] + [(set (match_operand:VI4_AVX2 0 "register_operand") + (mult:VI4_AVX2 (match_operand:VI4_AVX2 1 "register_operand") + (match_operand:VI4_AVX2 2 "register_operand")))] "TARGET_SSE2" { if (TARGET_SSE4_1 || TARGET_AVX) @@ -5490,9 +5490,9 @@ (set_attr "mode" "<sseinsnmode>")]) (define_insn_and_split "*sse2_mulv4si3" - [(set (match_operand:V4SI 0 "register_operand" "") - (mult:V4SI (match_operand:V4SI 1 "register_operand" "") - (match_operand:V4SI 2 "register_operand" "")))] + [(set (match_operand:V4SI 0 "register_operand") + (mult:V4SI (match_operand:V4SI 1 "register_operand") + (match_operand:V4SI 2 "register_operand")))] "TARGET_SSE2 && !TARGET_SSE4_1 && !TARGET_AVX && can_create_pseudo_p ()" "#" @@ -5546,9 +5546,9 @@ }) (define_insn_and_split "mul<mode>3" - [(set (match_operand:VI8_AVX2 0 "register_operand" "") - (mult:VI8_AVX2 (match_operand:VI8_AVX2 1 "register_operand" "") - (match_operand:VI8_AVX2 2 "register_operand" "")))] + [(set (match_operand:VI8_AVX2 0 "register_operand") + (mult:VI8_AVX2 (match_operand:VI8_AVX2 1 "register_operand") + (match_operand:VI8_AVX2 2 "register_operand")))] "TARGET_SSE2 && can_create_pseudo_p ()" "#" @@ -5634,10 +5634,10 @@ }) (define_expand "vec_widen_<s>mult_hi_<mode>" - [(match_operand:<sseunpackmode> 0 "register_operand" "") + [(match_operand:<sseunpackmode> 0 "register_operand") (any_extend:<sseunpackmode> - (match_operand:VI2_AVX2 1 "register_operand" "")) - (match_operand:VI2_AVX2 2 "register_operand" "")] + (match_operand:VI2_AVX2 1 "register_operand")) + (match_operand:VI2_AVX2 2 "register_operand")] "TARGET_SSE2" { rtx op1, op2, t1, t2, dest; @@ -5655,10 +5655,10 @@ }) (define_expand "vec_widen_<s>mult_lo_<mode>" - [(match_operand:<sseunpackmode> 0 "register_operand" "") + [(match_operand:<sseunpackmode> 0 "register_operand") (any_extend:<sseunpackmode> - (match_operand:VI2_AVX2 1 "register_operand" "")) - (match_operand:VI2_AVX2 2 "register_operand" "")] + (match_operand:VI2_AVX2 1 "register_operand")) + (match_operand:VI2_AVX2 2 "register_operand")] "TARGET_SSE2" { rtx op1, op2, t1, t2, dest; @@ -5676,9 +5676,9 @@ }) (define_expand "vec_widen_<s>mult_hi_v8si" - [(match_operand:V4DI 0 "register_operand" "") - (any_extend:V4DI (match_operand:V8SI 1 "nonimmediate_operand" "")) - (match_operand:V8SI 2 "nonimmediate_operand" "")] + [(match_operand:V4DI 0 "register_operand") + (any_extend:V4DI (match_operand:V8SI 1 "nonimmediate_operand")) + (match_operand:V8SI 2 "nonimmediate_operand")] "TARGET_AVX2" { rtx t1, t2, t3, t4; @@ -5702,9 +5702,9 @@ }) (define_expand "vec_widen_<s>mult_lo_v8si" - [(match_operand:V4DI 0 "register_operand" "") - (any_extend:V4DI (match_operand:V8SI 1 "nonimmediate_operand" "")) - (match_operand:V8SI 2 "nonimmediate_operand" "")] + [(match_operand:V4DI 0 "register_operand") + (any_extend:V4DI (match_operand:V8SI 1 "nonimmediate_operand")) + (match_operand:V8SI 2 "nonimmediate_operand")] "TARGET_AVX2" { rtx t1, t2, t3, t4; @@ -5728,9 +5728,9 @@ }) (define_expand "vec_widen_smult_hi_v4si" - [(match_operand:V2DI 0 "register_operand" "") - (match_operand:V4SI 1 "register_operand" "") - (match_operand:V4SI 2 "register_operand" "")] + [(match_operand:V2DI 0 "register_operand") + (match_operand:V4SI 1 "register_operand") + (match_operand:V4SI 2 "register_operand")] "TARGET_SSE4_1" { rtx op1, op2, t1, t2; @@ -5757,9 +5757,9 @@ }) (define_expand "vec_widen_smult_lo_v4si" - [(match_operand:V2DI 0 "register_operand" "") - (match_operand:V4SI 1 "register_operand" "") - (match_operand:V4SI 2 "register_operand" "")] + [(match_operand:V2DI 0 "register_operand") + (match_operand:V4SI 1 "register_operand") + (match_operand:V4SI 2 "register_operand")] "TARGET_SSE4_1" { rtx op1, op2, t1, t2; @@ -5786,9 +5786,9 @@ }) (define_expand "vec_widen_umult_hi_v4si" - [(match_operand:V2DI 0 "register_operand" "") - (match_operand:V4SI 1 "register_operand" "") - (match_operand:V4SI 2 "register_operand" "")] + [(match_operand:V2DI 0 "register_operand") + (match_operand:V4SI 1 "register_operand") + (match_operand:V4SI 2 "register_operand")] "TARGET_SSE2" { rtx op1, op2, t1, t2; @@ -5805,9 +5805,9 @@ }) (define_expand "vec_widen_umult_lo_v4si" - [(match_operand:V2DI 0 "register_operand" "") - (match_operand:V4SI 1 "register_operand" "") - (match_operand:V4SI 2 "register_operand" "")] + [(match_operand:V2DI 0 "register_operand") + (match_operand:V4SI 1 "register_operand") + (match_operand:V4SI 2 "register_operand")] "TARGET_SSE2" { rtx op1, op2, t1, t2; @@ -5824,10 +5824,10 @@ }) (define_expand "sdot_prod<mode>" - [(match_operand:<sseunpackmode> 0 "register_operand" "") - (match_operand:VI2_AVX2 1 "register_operand" "") - (match_operand:VI2_AVX2 2 "register_operand" "") - (match_operand:<sseunpackmode> 3 "register_operand" "")] + [(match_operand:<sseunpackmode> 0 "register_operand") + (match_operand:VI2_AVX2 1 "register_operand") + (match_operand:VI2_AVX2 2 "register_operand") + (match_operand:<sseunpackmode> 3 "register_operand")] "TARGET_SSE2" { rtx t = gen_reg_rtx (<sseunpackmode>mode); @@ -5842,10 +5842,10 @@ [(zero_extend "sse2") (sign_extend "sse4_1")]) (define_expand "<s>dot_prodv4si" - [(match_operand:V2DI 0 "register_operand" "") - (any_extend:V2DI (match_operand:V4SI 1 "register_operand" "")) - (match_operand:V4SI 2 "register_operand" "") - (match_operand:V2DI 3 "register_operand" "")] + [(match_operand:V2DI 0 "register_operand") + (any_extend:V2DI (match_operand:V4SI 1 "register_operand")) + (match_operand:V4SI 2 "register_operand") + (match_operand:V2DI 3 "register_operand")] "<CODE> == ZERO_EXTEND ? TARGET_SSE2 : TARGET_SSE4_1" { rtx t1, t2, t3, t4; @@ -5871,10 +5871,10 @@ }) (define_expand "<s>dot_prodv8si" - [(match_operand:V4DI 0 "register_operand" "") - (any_extend:V4DI (match_operand:V8SI 1 "register_operand" "")) - (match_operand:V8SI 2 "register_operand" "") - (match_operand:V4DI 3 "register_operand" "")] + [(match_operand:V4DI 0 "register_operand") + (any_extend:V4DI (match_operand:V8SI 1 "register_operand")) + (match_operand:V8SI 2 "register_operand") + (match_operand:V4DI 3 "register_operand")] "TARGET_AVX2" { rtx t1, t2, t3, t4; @@ -5911,7 +5911,7 @@ [(set_attr "isa" "noavx,avx") (set_attr "type" "sseishft") (set (attr "length_immediate") - (if_then_else (match_operand 2 "const_int_operand" "") + (if_then_else (match_operand 2 "const_int_operand") (const_string "1") (const_string "0"))) (set_attr "prefix_data16" "1,*") @@ -5930,7 +5930,7 @@ [(set_attr "isa" "noavx,avx") (set_attr "type" "sseishft") (set (attr "length_immediate") - (if_then_else (match_operand 2 "const_int_operand" "") + (if_then_else (match_operand 2 "const_int_operand") (const_string "1") (const_string "0"))) (set_attr "prefix_data16" "1,*") @@ -5938,10 +5938,10 @@ (set_attr "mode" "<sseinsnmode>")]) (define_expand "vec_shl_<mode>" - [(set (match_operand:VI_128 0 "register_operand" "") + [(set (match_operand:VI_128 0 "register_operand") (ashift:V1TI - (match_operand:VI_128 1 "register_operand" "") - (match_operand:SI 2 "const_0_to_255_mul_8_operand" "")))] + (match_operand:VI_128 1 "register_operand") + (match_operand:SI 2 "const_0_to_255_mul_8_operand")))] "TARGET_SSE2" { operands[0] = gen_lowpart (V1TImode, operands[0]); @@ -5975,10 +5975,10 @@ (set_attr "mode" "<sseinsnmode>")]) (define_expand "vec_shr_<mode>" - [(set (match_operand:VI_128 0 "register_operand" "") + [(set (match_operand:VI_128 0 "register_operand") (lshiftrt:V1TI - (match_operand:VI_128 1 "register_operand" "") - (match_operand:SI 2 "const_0_to_255_mul_8_operand" "")))] + (match_operand:VI_128 1 "register_operand") + (match_operand:SI 2 "const_0_to_255_mul_8_operand")))] "TARGET_SSE2" { operands[0] = gen_lowpart (V1TImode, operands[0]); @@ -6014,10 +6014,10 @@ (define_expand "<code><mode>3" - [(set (match_operand:VI124_256 0 "register_operand" "") + [(set (match_operand:VI124_256 0 "register_operand") (maxmin:VI124_256 - (match_operand:VI124_256 1 "nonimmediate_operand" "") - (match_operand:VI124_256 2 "nonimmediate_operand" "")))] + (match_operand:VI124_256 1 "nonimmediate_operand") + (match_operand:VI124_256 2 "nonimmediate_operand")))] "TARGET_AVX2" "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") @@ -6034,10 +6034,10 @@ (set_attr "mode" "OI")]) (define_expand "<code><mode>3" - [(set (match_operand:VI8_AVX2 0 "register_operand" "") + [(set (match_operand:VI8_AVX2 0 "register_operand") (maxmin:VI8_AVX2 - (match_operand:VI8_AVX2 1 "register_operand" "") - (match_operand:VI8_AVX2 2 "register_operand" "")))] + (match_operand:VI8_AVX2 1 "register_operand") + (match_operand:VI8_AVX2 2 "register_operand")))] "TARGET_SSE4_2" { enum rtx_code code; @@ -6069,10 +6069,10 @@ }) (define_expand "<code><mode>3" - [(set (match_operand:VI124_128 0 "register_operand" "") + [(set (match_operand:VI124_128 0 "register_operand") (smaxmin:VI124_128 - (match_operand:VI124_128 1 "nonimmediate_operand" "") - (match_operand:VI124_128 2 "nonimmediate_operand" "")))] + (match_operand:VI124_128 1 "nonimmediate_operand") + (match_operand:VI124_128 2 "nonimmediate_operand")))] "TARGET_SSE2" { if (TARGET_SSE4_1 || <MODE>mode == V8HImode) @@ -6139,10 +6139,10 @@ (set_attr "mode" "TI")]) (define_expand "<code><mode>3" - [(set (match_operand:VI124_128 0 "register_operand" "") + [(set (match_operand:VI124_128 0 "register_operand") (umaxmin:VI124_128 - (match_operand:VI124_128 1 "nonimmediate_operand" "") - (match_operand:VI124_128 2 "nonimmediate_operand" "")))] + (match_operand:VI124_128 1 "nonimmediate_operand") + (match_operand:VI124_128 2 "nonimmediate_operand")))] "TARGET_SSE2" { if (TARGET_SSE4_1 || <MODE>mode == V16QImode) @@ -6226,10 +6226,10 @@ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (define_expand "avx2_eq<mode>3" - [(set (match_operand:VI_256 0 "register_operand" "") + [(set (match_operand:VI_256 0 "register_operand") (eq:VI_256 - (match_operand:VI_256 1 "nonimmediate_operand" "") - (match_operand:VI_256 2 "nonimmediate_operand" "")))] + (match_operand:VI_256 1 "nonimmediate_operand") + (match_operand:VI_256 2 "nonimmediate_operand")))] "TARGET_AVX2" "ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);") @@ -6277,18 +6277,18 @@ (set_attr "mode" "TI")]) (define_expand "sse2_eq<mode>3" - [(set (match_operand:VI124_128 0 "register_operand" "") + [(set (match_operand:VI124_128 0 "register_operand") (eq:VI124_128 - (match_operand:VI124_128 1 "nonimmediate_operand" "") - (match_operand:VI124_128 2 "nonimmediate_operand" "")))] + (match_operand:VI124_128 1 "nonimmediate_operand") + (match_operand:VI124_128 2 "nonimmediate_operand")))] "TARGET_SSE2 && !TARGET_XOP " "ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);") (define_expand "sse4_1_eqv2di3" - [(set (match_operand:V2DI 0 "register_operand" "") + [(set (match_operand:V2DI 0 "register_operand") (eq:V2DI - (match_operand:V2DI 1 "nonimmediate_operand" "") - (match_operand:V2DI 2 "nonimmediate_operand" "")))] + (match_operand:V2DI 1 "nonimmediate_operand") + (match_operand:V2DI 2 "nonimmediate_operand")))] "TARGET_SSE4_1" "ix86_fixup_binary_operands_no_copy (EQ, V2DImode, operands);") @@ -6335,13 +6335,13 @@ (set_attr "mode" "TI")]) (define_expand "vcond<V_256:mode><VI_256:mode>" - [(set (match_operand:V_256 0 "register_operand" "") + [(set (match_operand:V_256 0 "register_operand") (if_then_else:V_256 (match_operator 3 "" - [(match_operand:VI_256 4 "nonimmediate_operand" "") - (match_operand:VI_256 5 "general_operand" "")]) - (match_operand:V_256 1 "" "") - (match_operand:V_256 2 "" "")))] + [(match_operand:VI_256 4 "nonimmediate_operand") + (match_operand:VI_256 5 "general_operand")]) + (match_operand:V_256 1) + (match_operand:V_256 2)))] "TARGET_AVX2 && (GET_MODE_NUNITS (<V_256:MODE>mode) == GET_MODE_NUNITS (<VI_256:MODE>mode))" @@ -6352,13 +6352,13 @@ }) (define_expand "vcond<V_128:mode><VI124_128:mode>" - [(set (match_operand:V_128 0 "register_operand" "") + [(set (match_operand:V_128 0 "register_operand") (if_then_else:V_128 (match_operator 3 "" - [(match_operand:VI124_128 4 "nonimmediate_operand" "") - (match_operand:VI124_128 5 "general_operand" "")]) - (match_operand:V_128 1 "" "") - (match_operand:V_128 2 "" "")))] + [(match_operand:VI124_128 4 "nonimmediate_operand") + (match_operand:VI124_128 5 "general_operand")]) + (match_operand:V_128 1) + (match_operand:V_128 2)))] "TARGET_SSE2 && (GET_MODE_NUNITS (<V_128:MODE>mode) == GET_MODE_NUNITS (<VI124_128:MODE>mode))" @@ -6369,13 +6369,13 @@ }) (define_expand "vcond<VI8F_128:mode>v2di" - [(set (match_operand:VI8F_128 0 "register_operand" "") + [(set (match_operand:VI8F_128 0 "register_operand") (if_then_else:VI8F_128 (match_operator 3 "" - [(match_operand:V2DI 4 "nonimmediate_operand" "") - (match_operand:V2DI 5 "general_operand" "")]) - (match_operand:VI8F_128 1 "" "") - (match_operand:VI8F_128 2 "" "")))] + [(match_operand:V2DI 4 "nonimmediate_operand") + (match_operand:V2DI 5 "general_operand")]) + (match_operand:VI8F_128 1) + (match_operand:VI8F_128 2)))] "TARGET_SSE4_2" { bool ok = ix86_expand_int_vcond (operands); @@ -6384,13 +6384,13 @@ }) (define_expand "vcondu<V_256:mode><VI_256:mode>" - [(set (match_operand:V_256 0 "register_operand" "") + [(set (match_operand:V_256 0 "register_operand") (if_then_else:V_256 (match_operator 3 "" - [(match_operand:VI_256 4 "nonimmediate_operand" "") - (match_operand:VI_256 5 "nonimmediate_operand" "")]) - (match_operand:V_256 1 "general_operand" "") - (match_operand:V_256 2 "general_operand" "")))] + [(match_operand:VI_256 4 "nonimmediate_operand") + (match_operand:VI_256 5 "nonimmediate_operand")]) + (match_operand:V_256 1 "general_operand") + (match_operand:V_256 2 "general_operand")))] "TARGET_AVX2 && (GET_MODE_NUNITS (<V_256:MODE>mode) == GET_MODE_NUNITS (<VI_256:MODE>mode))" @@ -6401,13 +6401,13 @@ }) (define_expand "vcondu<V_128:mode><VI124_128:mode>" - [(set (match_operand:V_128 0 "register_operand" "") + [(set (match_operand:V_128 0 "register_operand") (if_then_else:V_128 (match_operator 3 "" - [(match_operand:VI124_128 4 "nonimmediate_operand" "") - (match_operand:VI124_128 5 "nonimmediate_operand" "")]) - (match_operand:V_128 1 "general_operand" "") - (match_operand:V_128 2 "general_operand" "")))] + [(match_operand:VI124_128 4 "nonimmediate_operand") + (match_operand:VI124_128 5 "nonimmediate_operand")]) + (match_operand:V_128 1 "general_operand") + (match_operand:V_128 2 "general_operand")))] "TARGET_SSE2 && (GET_MODE_NUNITS (<V_128:MODE>mode) == GET_MODE_NUNITS (<VI124_128:MODE>mode))" @@ -6418,13 +6418,13 @@ }) (define_expand "vcondu<VI8F_128:mode>v2di" - [(set (match_operand:VI8F_128 0 "register_operand" "") + [(set (match_operand:VI8F_128 0 "register_operand") (if_then_else:VI8F_128 (match_operator 3 "" - [(match_operand:V2DI 4 "nonimmediate_operand" "") - (match_operand:V2DI 5 "nonimmediate_operand" "")]) - (match_operand:VI8F_128 1 "general_operand" "") - (match_operand:VI8F_128 2 "general_operand" "")))] + [(match_operand:V2DI 4 "nonimmediate_operand") + (match_operand:V2DI 5 "nonimmediate_operand")]) + (match_operand:VI8F_128 1 "general_operand") + (match_operand:VI8F_128 2 "general_operand")))] "TARGET_SSE4_2" { bool ok = ix86_expand_int_vcond (operands); @@ -6439,10 +6439,10 @@ (V8SF "TARGET_AVX2") (V4DF "TARGET_AVX2")]) (define_expand "vec_perm<mode>" - [(match_operand:VEC_PERM_AVX2 0 "register_operand" "") - (match_operand:VEC_PERM_AVX2 1 "register_operand" "") - (match_operand:VEC_PERM_AVX2 2 "register_operand" "") - (match_operand:<sseintvecmode> 3 "register_operand" "")] + [(match_operand:VEC_PERM_AVX2 0 "register_operand") + (match_operand:VEC_PERM_AVX2 1 "register_operand") + (match_operand:VEC_PERM_AVX2 2 "register_operand") + (match_operand:<sseintvecmode> 3 "register_operand")] "TARGET_SSSE3 || TARGET_AVX || TARGET_XOP" { ix86_expand_vec_perm (operands); @@ -6458,10 +6458,10 @@ (V32QI "TARGET_AVX2") (V16HI "TARGET_AVX2")]) (define_expand "vec_perm_const<mode>" - [(match_operand:VEC_PERM_CONST 0 "register_operand" "") - (match_operand:VEC_PERM_CONST 1 "register_operand" "") - (match_operand:VEC_PERM_CONST 2 "register_operand" "") - (match_operand:<sseintvecmode> 3 "" "")] + [(match_operand:VEC_PERM_CONST 0 "register_operand") + (match_operand:VEC_PERM_CONST 1 "register_operand") + (match_operand:VEC_PERM_CONST 2 "register_operand") + (match_operand:<sseintvecmode> 3)] "" { if (ix86_expand_vec_perm_const (operands)) @@ -6477,8 +6477,8 @@ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (define_expand "one_cmpl<mode>2" - [(set (match_operand:VI 0 "register_operand" "") - (xor:VI (match_operand:VI 1 "nonimmediate_operand" "") + [(set (match_operand:VI 0 "register_operand") + (xor:VI (match_operand:VI 1 "nonimmediate_operand") (match_dup 2)))] "TARGET_SSE" { @@ -6492,10 +6492,10 @@ }) (define_expand "<sse2_avx2>_andnot<mode>3" - [(set (match_operand:VI_AVX2 0 "register_operand" "") + [(set (match_operand:VI_AVX2 0 "register_operand") (and:VI_AVX2 - (not:VI_AVX2 (match_operand:VI_AVX2 1 "register_operand" "")) - (match_operand:VI_AVX2 2 "nonimmediate_operand" "")))] + (not:VI_AVX2 (match_operand:VI_AVX2 1 "register_operand")) + (match_operand:VI_AVX2 2 "nonimmediate_operand")))] "TARGET_SSE2") (define_insn "*andnot<mode>3" @@ -6565,10 +6565,10 @@ (const_string "<sseinsnmode>")))]) (define_expand "<code><mode>3" - [(set (match_operand:VI 0 "register_operand" "") + [(set (match_operand:VI 0 "register_operand") (any_logic:VI - (match_operand:VI 1 "nonimmediate_operand" "") - (match_operand:VI 2 "nonimmediate_operand" "")))] + (match_operand:VI 1 "nonimmediate_operand") + (match_operand:VI 2 "nonimmediate_operand")))] "TARGET_SSE" "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") @@ -6655,10 +6655,10 @@ (set_attr "mode" "TI")]) (define_expand "<code>tf3" - [(set (match_operand:TF 0 "register_operand" "") + [(set (match_operand:TF 0 "register_operand") (any_logic:TF - (match_operand:TF 1 "nonimmediate_operand" "") - (match_operand:TF 2 "nonimmediate_operand" "")))] + (match_operand:TF 1 "nonimmediate_operand") + (match_operand:TF 2 "nonimmediate_operand")))] "TARGET_SSE2" "ix86_fixup_binary_operands_no_copy (<CODE>, TFmode, operands);") @@ -6685,9 +6685,9 @@ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (define_expand "vec_pack_trunc_<mode>" - [(match_operand:<ssepackmode> 0 "register_operand" "") - (match_operand:VI248_AVX2 1 "register_operand" "") - (match_operand:VI248_AVX2 2 "register_operand" "")] + [(match_operand:<ssepackmode> 0 "register_operand") + (match_operand:VI248_AVX2 1 "register_operand") + (match_operand:VI248_AVX2 2 "register_operand")] "TARGET_SSE2" { rtx op1 = gen_lowpart (<ssepackmode>mode, operands[1]); @@ -7048,7 +7048,7 @@ (vec_duplicate:PINSR_MODE (match_operand:<ssescalarmode> 2 "nonimmediate_operand" "r,m,r,m")) (match_operand:PINSR_MODE 1 "register_operand" "0,0,x,x") - (match_operand:SI 3 "const_int_operand" "")))] + (match_operand:SI 3 "const_int_operand")))] "TARGET_SSE2 && ((unsigned) exact_log2 (INTVAL (operands[3])) < GET_MODE_NUNITS (<MODE>mode))" @@ -7194,9 +7194,9 @@ (set_attr "mode" "TI")]) (define_expand "avx2_pshufdv3" - [(match_operand:V8SI 0 "register_operand" "") - (match_operand:V8SI 1 "nonimmediate_operand" "") - (match_operand:SI 2 "const_0_to_255_operand" "")] + [(match_operand:V8SI 0 "register_operand") + (match_operand:V8SI 1 "nonimmediate_operand") + (match_operand:SI 2 "const_0_to_255_operand")] "TARGET_AVX2" { int mask = INTVAL (operands[2]); @@ -7216,14 +7216,14 @@ [(set (match_operand:V8SI 0 "register_operand" "=x") (vec_select:V8SI (match_operand:V8SI 1 "nonimmediate_operand" "xm") - (parallel [(match_operand 2 "const_0_to_3_operand" "") - (match_operand 3 "const_0_to_3_operand" "") - (match_operand 4 "const_0_to_3_operand" "") - (match_operand 5 "const_0_to_3_operand" "") - (match_operand 6 "const_4_to_7_operand" "") - (match_operand 7 "const_4_to_7_operand" "") - (match_operand 8 "const_4_to_7_operand" "") - (match_operand 9 "const_4_to_7_operand" "")])))] + (parallel [(match_operand 2 "const_0_to_3_operand") + (match_operand 3 "const_0_to_3_operand") + (match_operand 4 "const_0_to_3_operand") + (match_operand 5 "const_0_to_3_operand") + (match_operand 6 "const_4_to_7_operand") + (match_operand 7 "const_4_to_7_operand") + (match_operand 8 "const_4_to_7_operand") + (match_operand 9 "const_4_to_7_operand")])))] "TARGET_AVX2 && INTVAL (operands[2]) + 4 == INTVAL (operands[6]) && INTVAL (operands[3]) + 4 == INTVAL (operands[7]) @@ -7245,9 +7245,9 @@ (set_attr "mode" "OI")]) (define_expand "sse2_pshufd" - [(match_operand:V4SI 0 "register_operand" "") - (match_operand:V4SI 1 "nonimmediate_operand" "") - (match_operand:SI 2 "const_int_operand" "")] + [(match_operand:V4SI 0 "register_operand") + (match_operand:V4SI 1 "nonimmediate_operand") + (match_operand:SI 2 "const_int_operand")] "TARGET_SSE2" { int mask = INTVAL (operands[2]); @@ -7263,10 +7263,10 @@ [(set (match_operand:V4SI 0 "register_operand" "=x") (vec_select:V4SI (match_operand:V4SI 1 "nonimmediate_operand" "xm") - (parallel [(match_operand 2 "const_0_to_3_operand" "") - (match_operand 3 "const_0_to_3_operand" "") - (match_operand 4 "const_0_to_3_operand" "") - (match_operand 5 "const_0_to_3_operand" "")])))] + (parallel [(match_operand 2 "const_0_to_3_operand") + (match_operand 3 "const_0_to_3_operand") + (match_operand 4 "const_0_to_3_operand") + (match_operand 5 "const_0_to_3_operand")])))] "TARGET_SSE2" { int mask = 0; @@ -7285,9 +7285,9 @@ (set_attr "mode" "TI")]) (define_expand "avx2_pshuflwv3" - [(match_operand:V16HI 0 "register_operand" "") - (match_operand:V16HI 1 "nonimmediate_operand" "") - (match_operand:SI 2 "const_0_to_255_operand" "")] + [(match_operand:V16HI 0 "register_operand") + (match_operand:V16HI 1 "nonimmediate_operand") + (match_operand:SI 2 "const_0_to_255_operand")] "TARGET_AVX2" { int mask = INTVAL (operands[2]); @@ -7307,18 +7307,18 @@ [(set (match_operand:V16HI 0 "register_operand" "=x") (vec_select:V16HI (match_operand:V16HI 1 "nonimmediate_operand" "xm") - (parallel [(match_operand 2 "const_0_to_3_operand" "") - (match_operand 3 "const_0_to_3_operand" "") - (match_operand 4 "const_0_to_3_operand" "") - (match_operand 5 "const_0_to_3_operand" "") + (parallel [(match_operand 2 "const_0_to_3_operand") + (match_operand 3 "const_0_to_3_operand") + (match_operand 4 "const_0_to_3_operand") + (match_operand 5 "const_0_to_3_operand") (const_int 4) (const_int 5) (const_int 6) (const_int 7) - (match_operand 6 "const_8_to_11_operand" "") - (match_operand 7 "const_8_to_11_operand" "") - (match_operand 8 "const_8_to_11_operand" "") - (match_operand 9 "const_8_to_11_operand" "") + (match_operand 6 "const_8_to_11_operand") + (match_operand 7 "const_8_to_11_operand") + (match_operand 8 "const_8_to_11_operand") + (match_operand 9 "const_8_to_11_operand") (const_int 12) (const_int 13) (const_int 14) @@ -7344,9 +7344,9 @@ (set_attr "mode" "OI")]) (define_expand "sse2_pshuflw" - [(match_operand:V8HI 0 "register_operand" "") - (match_operand:V8HI 1 "nonimmediate_operand" "") - (match_operand:SI 2 "const_int_operand" "")] + [(match_operand:V8HI 0 "register_operand") + (match_operand:V8HI 1 "nonimmediate_operand") + (match_operand:SI 2 "const_int_operand")] "TARGET_SSE2" { int mask = INTVAL (operands[2]); @@ -7362,10 +7362,10 @@ [(set (match_operand:V8HI 0 "register_operand" "=x") (vec_select:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "xm") - (parallel [(match_operand 2 "const_0_to_3_operand" "") - (match_operand 3 "const_0_to_3_operand" "") - (match_operand 4 "const_0_to_3_operand" "") - (match_operand 5 "const_0_to_3_operand" "") + (parallel [(match_operand 2 "const_0_to_3_operand") + (match_operand 3 "const_0_to_3_operand") + (match_operand 4 "const_0_to_3_operand") + (match_operand 5 "const_0_to_3_operand") (const_int 4) (const_int 5) (const_int 6) @@ -7389,9 +7389,9 @@ (set_attr "mode" "TI")]) (define_expand "avx2_pshufhwv3" - [(match_operand:V16HI 0 "register_operand" "") - (match_operand:V16HI 1 "nonimmediate_operand" "") - (match_operand:SI 2 "const_0_to_255_operand" "")] + [(match_operand:V16HI 0 "register_operand") + (match_operand:V16HI 1 "nonimmediate_operand") + (match_operand:SI 2 "const_0_to_255_operand")] "TARGET_AVX2" { int mask = INTVAL (operands[2]); @@ -7415,18 +7415,18 @@ (const_int 1) (const_int 2) (const_int 3) - (match_operand 2 "const_4_to_7_operand" "") - (match_operand 3 "const_4_to_7_operand" "") - (match_operand 4 "const_4_to_7_operand" "") - (match_operand 5 "const_4_to_7_operand" "") + (match_operand 2 "const_4_to_7_operand") + (match_operand 3 "const_4_to_7_operand") + (match_operand 4 "const_4_to_7_operand") + (match_operand 5 "const_4_to_7_operand") (const_int 8) (const_int 9) (const_int 10) (const_int 11) - (match_operand 6 "const_12_to_15_operand" "") - (match_operand 7 "const_12_to_15_operand" "") - (match_operand 8 "const_12_to_15_operand" "") - (match_operand 9 "const_12_to_15_operand" "")])))] + (match_operand 6 "const_12_to_15_operand") + (match_operand 7 "const_12_to_15_operand") + (match_operand 8 "const_12_to_15_operand") + (match_operand 9 "const_12_to_15_operand")])))] "TARGET_AVX2 && INTVAL (operands[2]) + 8 == INTVAL (operands[6]) && INTVAL (operands[3]) + 8 == INTVAL (operands[7]) @@ -7448,9 +7448,9 @@ (set_attr "mode" "OI")]) (define_expand "sse2_pshufhw" - [(match_operand:V8HI 0 "register_operand" "") - (match_operand:V8HI 1 "nonimmediate_operand" "") - (match_operand:SI 2 "const_int_operand" "")] + [(match_operand:V8HI 0 "register_operand") + (match_operand:V8HI 1 "nonimmediate_operand") + (match_operand:SI 2 "const_int_operand")] "TARGET_SSE2" { int mask = INTVAL (operands[2]); @@ -7470,10 +7470,10 @@ (const_int 1) (const_int 2) (const_int 3) - (match_operand 2 "const_4_to_7_operand" "") - (match_operand 3 "const_4_to_7_operand" "") - (match_operand 4 "const_4_to_7_operand" "") - (match_operand 5 "const_4_to_7_operand" "")])))] + (match_operand 2 "const_4_to_7_operand") + (match_operand 3 "const_4_to_7_operand") + (match_operand 4 "const_4_to_7_operand") + (match_operand 5 "const_4_to_7_operand")])))] "TARGET_SSE2" { int mask = 0; @@ -7493,10 +7493,10 @@ (set_attr "mode" "TI")]) (define_expand "sse2_loadd" - [(set (match_operand:V4SI 0 "register_operand" "") + [(set (match_operand:V4SI 0 "register_operand") (vec_merge:V4SI (vec_duplicate:V4SI - (match_operand:SI 1 "nonimmediate_operand" "")) + (match_operand:SI 1 "nonimmediate_operand")) (match_dup 2) (const_int 1)))] "TARGET_SSE" @@ -7539,7 +7539,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (vec_select:SI (match_operand:V4SI 1 "memory_operand" "o") - (parallel [(match_operand 2 "const_0_to_3_operand" "")])))] + (parallel [(match_operand 2 "const_0_to_3_operand")])))] "" "#" "reload_completed" @@ -7552,9 +7552,9 @@ }) (define_expand "sse_storeq" - [(set (match_operand:DI 0 "nonimmediate_operand" "") + [(set (match_operand:DI 0 "nonimmediate_operand") (vec_select:DI - (match_operand:V2DI 1 "register_operand" "") + (match_operand:V2DI 1 "register_operand") (parallel [(const_int 0)])))] "TARGET_SSE") @@ -7580,9 +7580,9 @@ "#") (define_split - [(set (match_operand:DI 0 "nonimmediate_operand" "") + [(set (match_operand:DI 0 "nonimmediate_operand") (vec_select:DI - (match_operand:V2DI 1 "register_operand" "") + (match_operand:V2DI 1 "register_operand") (parallel [(const_int 0)])))] "TARGET_SSE && reload_completed @@ -7789,26 +7789,26 @@ (set_attr "mode" "TI,TI,TI,TI,V4SF,V2SF,V2SF")]) (define_expand "vec_unpacks_lo_<mode>" - [(match_operand:<sseunpackmode> 0 "register_operand" "") - (match_operand:VI124_AVX2 1 "register_operand" "")] + [(match_operand:<sseunpackmode> 0 "register_operand") + (match_operand:VI124_AVX2 1 "register_operand")] "TARGET_SSE2" "ix86_expand_sse_unpack (operands, false, false); DONE;") (define_expand "vec_unpacks_hi_<mode>" - [(match_operand:<sseunpackmode> 0 "register_operand" "") - (match_operand:VI124_AVX2 1 "register_operand" "")] + [(match_operand:<sseunpackmode> 0 "register_operand") + (match_operand:VI124_AVX2 1 "register_operand")] "TARGET_SSE2" "ix86_expand_sse_unpack (operands, false, true); DONE;") (define_expand "vec_unpacku_lo_<mode>" - [(match_operand:<sseunpackmode> 0 "register_operand" "") - (match_operand:VI124_AVX2 1 "register_operand" "")] + [(match_operand:<sseunpackmode> 0 "register_operand") + (match_operand:VI124_AVX2 1 "register_operand")] "TARGET_SSE2" "ix86_expand_sse_unpack (operands, true, false); DONE;") (define_expand "vec_unpacku_hi_<mode>" - [(match_operand:<sseunpackmode> 0 "register_operand" "") - (match_operand:VI124_AVX2 1 "register_operand" "")] + [(match_operand:<sseunpackmode> 0 "register_operand") + (match_operand:VI124_AVX2 1 "register_operand")] "TARGET_SSE2" "ix86_expand_sse_unpack (operands, true, true); DONE;") @@ -7819,15 +7819,15 @@ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (define_expand "avx2_uavgv32qi3" - [(set (match_operand:V32QI 0 "register_operand" "") + [(set (match_operand:V32QI 0 "register_operand") (truncate:V32QI (lshiftrt:V32HI (plus:V32HI (plus:V32HI (zero_extend:V32HI - (match_operand:V32QI 1 "nonimmediate_operand" "")) + (match_operand:V32QI 1 "nonimmediate_operand")) (zero_extend:V32HI - (match_operand:V32QI 2 "nonimmediate_operand" ""))) + (match_operand:V32QI 2 "nonimmediate_operand"))) (const_vector:V32QI [(const_int 1) (const_int 1) (const_int 1) (const_int 1) (const_int 1) (const_int 1) @@ -7849,15 +7849,15 @@ "ix86_fixup_binary_operands_no_copy (PLUS, V32QImode, operands);") (define_expand "sse2_uavgv16qi3" - [(set (match_operand:V16QI 0 "register_operand" "") + [(set (match_operand:V16QI 0 "register_operand") (truncate:V16QI (lshiftrt:V16HI (plus:V16HI (plus:V16HI (zero_extend:V16HI - (match_operand:V16QI 1 "nonimmediate_operand" "")) + (match_operand:V16QI 1 "nonimmediate_operand")) (zero_extend:V16HI - (match_operand:V16QI 2 "nonimmediate_operand" ""))) + (match_operand:V16QI 2 "nonimmediate_operand"))) (const_vector:V16QI [(const_int 1) (const_int 1) (const_int 1) (const_int 1) (const_int 1) (const_int 1) @@ -7933,15 +7933,15 @@ (set_attr "mode" "TI")]) (define_expand "avx2_uavgv16hi3" - [(set (match_operand:V16HI 0 "register_operand" "") + [(set (match_operand:V16HI 0 "register_operand") (truncate:V16HI (lshiftrt:V16SI (plus:V16SI (plus:V16SI (zero_extend:V16SI - (match_operand:V16HI 1 "nonimmediate_operand" "")) + (match_operand:V16HI 1 "nonimmediate_operand")) (zero_extend:V16SI - (match_operand:V16HI 2 "nonimmediate_operand" ""))) + (match_operand:V16HI 2 "nonimmediate_operand"))) (const_vector:V16HI [(const_int 1) (const_int 1) (const_int 1) (const_int 1) (const_int 1) (const_int 1) @@ -7955,15 +7955,15 @@ "ix86_fixup_binary_operands_no_copy (PLUS, V16HImode, operands);") (define_expand "sse2_uavgv8hi3" - [(set (match_operand:V8HI 0 "register_operand" "") + [(set (match_operand:V8HI 0 "register_operand") (truncate:V8HI (lshiftrt:V8SI (plus:V8SI (plus:V8SI (zero_extend:V8SI - (match_operand:V8HI 1 "nonimmediate_operand" "")) + (match_operand:V8HI 1 "nonimmediate_operand")) (zero_extend:V8SI - (match_operand:V8HI 2 "nonimmediate_operand" ""))) + (match_operand:V8HI 2 "nonimmediate_operand"))) (const_vector:V8HI [(const_int 1) (const_int 1) (const_int 1) (const_int 1) (const_int 1) (const_int 1) @@ -8073,9 +8073,9 @@ (set_attr "mode" "SI")]) (define_expand "sse2_maskmovdqu" - [(set (match_operand:V16QI 0 "memory_operand" "") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "") - (match_operand:V16QI 2 "register_operand" "") + [(set (match_operand:V16QI 0 "memory_operand") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand") + (match_operand:V16QI 2 "register_operand") (match_dup 0)] UNSPEC_MASKMOV))] "TARGET_SSE2") @@ -9162,16 +9162,16 @@ (set_attr "mode" "DI")]) (define_expand "avx2_umulhrswv16hi3" - [(set (match_operand:V16HI 0 "register_operand" "") + [(set (match_operand:V16HI 0 "register_operand") (truncate:V16HI (lshiftrt:V16SI (plus:V16SI (lshiftrt:V16SI (mult:V16SI (sign_extend:V16SI - (match_operand:V16HI 1 "nonimmediate_operand" "")) + (match_operand:V16HI 1 "nonimmediate_operand")) (sign_extend:V16SI - (match_operand:V16HI 2 "nonimmediate_operand" ""))) + (match_operand:V16HI 2 "nonimmediate_operand"))) (const_int 14)) (const_vector:V16HI [(const_int 1) (const_int 1) (const_int 1) (const_int 1) @@ -9214,16 +9214,16 @@ (set_attr "mode" "OI")]) (define_expand "ssse3_pmulhrswv8hi3" - [(set (match_operand:V8HI 0 "register_operand" "") + [(set (match_operand:V8HI 0 "register_operand") (truncate:V8HI (lshiftrt:V8SI (plus:V8SI (lshiftrt:V8SI (mult:V8SI (sign_extend:V8SI - (match_operand:V8HI 1 "nonimmediate_operand" "")) + (match_operand:V8HI 1 "nonimmediate_operand")) (sign_extend:V8SI - (match_operand:V8HI 2 "nonimmediate_operand" ""))) + (match_operand:V8HI 2 "nonimmediate_operand"))) (const_int 14)) (const_vector:V8HI [(const_int 1) (const_int 1) (const_int 1) (const_int 1) @@ -9262,16 +9262,16 @@ (set_attr "mode" "TI")]) (define_expand "ssse3_pmulhrswv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "") + [(set (match_operand:V4HI 0 "register_operand") (truncate:V4HI (lshiftrt:V4SI (plus:V4SI (lshiftrt:V4SI (mult:V4SI (sign_extend:V4SI - (match_operand:V4HI 1 "nonimmediate_operand" "")) + (match_operand:V4HI 1 "nonimmediate_operand")) (sign_extend:V4SI - (match_operand:V4HI 2 "nonimmediate_operand" ""))) + (match_operand:V4HI 2 "nonimmediate_operand"))) (const_int 14)) (const_vector:V4HI [(const_int 1) (const_int 1) (const_int 1) (const_int 1)])) @@ -9461,8 +9461,8 @@ (define_insn "sse4a_extrqi" [(set (match_operand:V2DI 0 "register_operand" "=x") (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0") - (match_operand 2 "const_0_to_255_operand" "") - (match_operand 3 "const_0_to_255_operand" "")] + (match_operand 2 "const_0_to_255_operand") + (match_operand 3 "const_0_to_255_operand")] UNSPEC_EXTRQI))] "TARGET_SSE4A" "extrq\t{%3, %2, %0|%0, %2, %3}" @@ -9486,8 +9486,8 @@ [(set (match_operand:V2DI 0 "register_operand" "=x") (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0") (match_operand:V2DI 2 "register_operand" "x") - (match_operand 3 "const_0_to_255_operand" "") - (match_operand 4 "const_0_to_255_operand" "")] + (match_operand 3 "const_0_to_255_operand") + (match_operand 4 "const_0_to_255_operand")] UNSPEC_INSERTQI))] "TARGET_SSE4A" "insertq\t{%4, %3, %2, %0|%0, %2, %3, %4}" @@ -9520,7 +9520,7 @@ (vec_merge:VF (match_operand:VF 2 "nonimmediate_operand" "xm,xm") (match_operand:VF 1 "register_operand" "0,x") - (match_operand:SI 3 "const_0_to_<blendbits>_operand" "")))] + (match_operand:SI 3 "const_0_to_<blendbits>_operand")))] "TARGET_SSE4_1" "@ blend<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3} @@ -9667,11 +9667,11 @@ ;; The builtin uses an 8-bit immediate. Expand that. (define_expand "avx2_pblendw" - [(set (match_operand:V16HI 0 "register_operand" "") + [(set (match_operand:V16HI 0 "register_operand") (vec_merge:V16HI - (match_operand:V16HI 2 "nonimmediate_operand" "") - (match_operand:V16HI 1 "register_operand" "") - (match_operand:SI 3 "const_0_to_255_operand" "")))] + (match_operand:V16HI 2 "nonimmediate_operand") + (match_operand:V16HI 1 "register_operand") + (match_operand:SI 3 "const_0_to_255_operand")))] "TARGET_AVX2" { HOST_WIDE_INT val = INTVAL (operands[3]) & 0xff; @@ -9958,9 +9958,9 @@ (set_attr "mode" "<MODE>")]) (define_expand "<sse4_1>_round<ssemodesuffix>_sfix<avxsizesuffix>" - [(match_operand:<sseintvecmode> 0 "register_operand" "") - (match_operand:VF1 1 "nonimmediate_operand" "") - (match_operand:SI 2 "const_0_to_15_operand" "")] + [(match_operand:<sseintvecmode> 0 "register_operand") + (match_operand:VF1 1 "nonimmediate_operand") + (match_operand:SI 2 "const_0_to_15_operand")] "TARGET_ROUND" { rtx tmp = gen_reg_rtx (<MODE>mode); @@ -9974,10 +9974,10 @@ }) (define_expand "<sse4_1>_round<ssemodesuffix>_vec_pack_sfix<avxsizesuffix>" - [(match_operand:<ssepackfltmode> 0 "register_operand" "") - (match_operand:VF2 1 "nonimmediate_operand" "") - (match_operand:VF2 2 "nonimmediate_operand" "") - (match_operand:SI 3 "const_0_to_15_operand" "")] + [(match_operand:<ssepackfltmode> 0 "register_operand") + (match_operand:VF2 1 "nonimmediate_operand") + (match_operand:VF2 2 "nonimmediate_operand") + (match_operand:SI 3 "const_0_to_15_operand")] "TARGET_ROUND" { rtx tmp0, tmp1; @@ -10035,9 +10035,9 @@ (define_expand "round<mode>2" [(set (match_dup 4) (plus:VF - (match_operand:VF 1 "register_operand" "") + (match_operand:VF 1 "register_operand") (match_dup 3))) - (set (match_operand:VF 0 "register_operand" "") + (set (match_operand:VF 0 "register_operand") (unspec:VF [(match_dup 4) (match_dup 5)] UNSPEC_ROUND))] @@ -10067,8 +10067,8 @@ }) (define_expand "round<mode>2_sfix" - [(match_operand:<sseintvecmode> 0 "register_operand" "") - (match_operand:VF1 1 "register_operand" "")] + [(match_operand:<sseintvecmode> 0 "register_operand") + (match_operand:VF1 1 "register_operand")] "TARGET_ROUND && !flag_trapping_math" { rtx tmp = gen_reg_rtx (<MODE>mode); @@ -10081,9 +10081,9 @@ }) (define_expand "round<mode>2_vec_pack_sfix" - [(match_operand:<ssepackfltmode> 0 "register_operand" "") - (match_operand:VF2 1 "register_operand" "") - (match_operand:VF2 2 "register_operand" "")] + [(match_operand:<ssepackfltmode> 0 "register_operand") + (match_operand:VF2 1 "register_operand") + (match_operand:VF2 2 "register_operand")] "TARGET_ROUND && !flag_trapping_math" { rtx tmp0, tmp1; @@ -11233,9 +11233,9 @@ ;; XOP packed rotate instructions (define_expand "rotl<mode>3" - [(set (match_operand:VI_128 0 "register_operand" "") + [(set (match_operand:VI_128 0 "register_operand") (rotate:VI_128 - (match_operand:VI_128 1 "nonimmediate_operand" "") + (match_operand:VI_128 1 "nonimmediate_operand") (match_operand:SI 2 "general_operand")))] "TARGET_XOP" { @@ -11264,9 +11264,9 @@ }) (define_expand "rotr<mode>3" - [(set (match_operand:VI_128 0 "register_operand" "") + [(set (match_operand:VI_128 0 "register_operand") (rotatert:VI_128 - (match_operand:VI_128 1 "nonimmediate_operand" "") + (match_operand:VI_128 1 "nonimmediate_operand") (match_operand:SI 2 "general_operand")))] "TARGET_XOP" { @@ -11322,9 +11322,9 @@ (set_attr "mode" "TI")]) (define_expand "vrotr<mode>3" - [(match_operand:VI_128 0 "register_operand" "") - (match_operand:VI_128 1 "register_operand" "") - (match_operand:VI_128 2 "register_operand" "")] + [(match_operand:VI_128 0 "register_operand") + (match_operand:VI_128 1 "register_operand") + (match_operand:VI_128 2 "register_operand")] "TARGET_XOP" { rtx reg = gen_reg_rtx (<MODE>mode); @@ -11334,9 +11334,9 @@ }) (define_expand "vrotl<mode>3" - [(match_operand:VI_128 0 "register_operand" "") - (match_operand:VI_128 1 "register_operand" "") - (match_operand:VI_128 2 "register_operand" "")] + [(match_operand:VI_128 0 "register_operand") + (match_operand:VI_128 1 "register_operand") + (match_operand:VI_128 2 "register_operand")] "TARGET_XOP" { emit_insn (gen_xop_vrotl<mode>3 (operands[0], operands[1], operands[2])); @@ -11364,10 +11364,10 @@ ;; XOP packed shift instructions. (define_expand "vlshr<mode>3" - [(set (match_operand:VI12_128 0 "register_operand" "") + [(set (match_operand:VI12_128 0 "register_operand") (lshiftrt:VI12_128 - (match_operand:VI12_128 1 "register_operand" "") - (match_operand:VI12_128 2 "nonimmediate_operand" "")))] + (match_operand:VI12_128 1 "register_operand") + (match_operand:VI12_128 2 "nonimmediate_operand")))] "TARGET_XOP" { rtx neg = gen_reg_rtx (<MODE>mode); @@ -11377,10 +11377,10 @@ }) (define_expand "vlshr<mode>3" - [(set (match_operand:VI48_128 0 "register_operand" "") + [(set (match_operand:VI48_128 0 "register_operand") (lshiftrt:VI48_128 - (match_operand:VI48_128 1 "register_operand" "") - (match_operand:VI48_128 2 "nonimmediate_operand" "")))] + (match_operand:VI48_128 1 "register_operand") + (match_operand:VI48_128 2 "nonimmediate_operand")))] "TARGET_AVX2 || TARGET_XOP" { if (!TARGET_AVX2) @@ -11393,17 +11393,17 @@ }) (define_expand "vlshr<mode>3" - [(set (match_operand:VI48_256 0 "register_operand" "") + [(set (match_operand:VI48_256 0 "register_operand") (lshiftrt:VI48_256 - (match_operand:VI48_256 1 "register_operand" "") - (match_operand:VI48_256 2 "nonimmediate_operand" "")))] + (match_operand:VI48_256 1 "register_operand") + (match_operand:VI48_256 2 "nonimmediate_operand")))] "TARGET_AVX2") (define_expand "vashr<mode>3" - [(set (match_operand:VI128_128 0 "register_operand" "") + [(set (match_operand:VI128_128 0 "register_operand") (ashiftrt:VI128_128 - (match_operand:VI128_128 1 "register_operand" "") - (match_operand:VI128_128 2 "nonimmediate_operand" "")))] + (match_operand:VI128_128 1 "register_operand") + (match_operand:VI128_128 2 "nonimmediate_operand")))] "TARGET_XOP" { rtx neg = gen_reg_rtx (<MODE>mode); @@ -11413,9 +11413,9 @@ }) (define_expand "vashrv4si3" - [(set (match_operand:V4SI 0 "register_operand" "") - (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "") - (match_operand:V4SI 2 "nonimmediate_operand" "")))] + [(set (match_operand:V4SI 0 "register_operand") + (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand") + (match_operand:V4SI 2 "nonimmediate_operand")))] "TARGET_AVX2 || TARGET_XOP" { if (!TARGET_AVX2) @@ -11428,16 +11428,16 @@ }) (define_expand "vashrv8si3" - [(set (match_operand:V8SI 0 "register_operand" "") - (ashiftrt:V8SI (match_operand:V8SI 1 "register_operand" "") - (match_operand:V8SI 2 "nonimmediate_operand" "")))] + [(set (match_operand:V8SI 0 "register_operand") + (ashiftrt:V8SI (match_operand:V8SI 1 "register_operand") + (match_operand:V8SI 2 "nonimmediate_operand")))] "TARGET_AVX2") (define_expand "vashl<mode>3" - [(set (match_operand:VI12_128 0 "register_operand" "") + [(set (match_operand:VI12_128 0 "register_operand") (ashift:VI12_128 - (match_operand:VI12_128 1 "register_operand" "") - (match_operand:VI12_128 2 "nonimmediate_operand" "")))] + (match_operand:VI12_128 1 "register_operand") + (match_operand:VI12_128 2 "nonimmediate_operand")))] "TARGET_XOP" { emit_insn (gen_xop_sha<mode>3 (operands[0], operands[1], operands[2])); @@ -11445,10 +11445,10 @@ }) (define_expand "vashl<mode>3" - [(set (match_operand:VI48_128 0 "register_operand" "") + [(set (match_operand:VI48_128 0 "register_operand") (ashift:VI48_128 - (match_operand:VI48_128 1 "register_operand" "") - (match_operand:VI48_128 2 "nonimmediate_operand" "")))] + (match_operand:VI48_128 1 "register_operand") + (match_operand:VI48_128 2 "nonimmediate_operand")))] "TARGET_AVX2 || TARGET_XOP" { if (!TARGET_AVX2) @@ -11460,10 +11460,10 @@ }) (define_expand "vashl<mode>3" - [(set (match_operand:VI48_256 0 "register_operand" "") + [(set (match_operand:VI48_256 0 "register_operand") (ashift:VI48_256 - (match_operand:VI48_256 1 "register_operand" "") - (match_operand:VI48_256 2 "nonimmediate_operand" "")))] + (match_operand:VI48_256 1 "register_operand") + (match_operand:VI48_256 2 "nonimmediate_operand")))] "TARGET_AVX2") (define_insn "xop_sha<mode>3" @@ -11506,10 +11506,10 @@ ;; SSE2 doesn't have some shift variants, so define versions for XOP (define_expand "ashlv16qi3" - [(set (match_operand:V16QI 0 "register_operand" "") + [(set (match_operand:V16QI 0 "register_operand") (ashift:V16QI - (match_operand:V16QI 1 "register_operand" "") - (match_operand:SI 2 "nonmemory_operand" "")))] + (match_operand:V16QI 1 "register_operand") + (match_operand:SI 2 "nonmemory_operand")))] "TARGET_XOP" { rtx reg = gen_reg_rtx (V16QImode); @@ -11526,10 +11526,10 @@ }) (define_expand "<shift_insn>v16qi3" - [(set (match_operand:V16QI 0 "register_operand" "") + [(set (match_operand:V16QI 0 "register_operand") (any_shiftrt:V16QI - (match_operand:V16QI 1 "register_operand" "") - (match_operand:SI 2 "nonmemory_operand" "")))] + (match_operand:V16QI 1 "register_operand") + (match_operand:SI 2 "nonmemory_operand")))] "TARGET_XOP" { rtx reg = gen_reg_rtx (V16QImode); @@ -11562,10 +11562,10 @@ }) (define_expand "ashrv2di3" - [(set (match_operand:V2DI 0 "register_operand" "") + [(set (match_operand:V2DI 0 "register_operand") (ashiftrt:V2DI - (match_operand:V2DI 1 "register_operand" "") - (match_operand:DI 2 "nonmemory_operand" "")))] + (match_operand:V2DI 1 "register_operand") + (match_operand:DI 2 "nonmemory_operand")))] "TARGET_XOP" { rtx reg = gen_reg_rtx (V2DImode); @@ -11847,7 +11847,7 @@ ;; Clear the upper 128bits of AVX registers, equivalent to a NOP ;; if the upper 128bits are unused. (define_insn "avx_vzeroupper" - [(unspec_volatile [(match_operand 0 "const_int_operand" "")] + [(unspec_volatile [(match_operand 0 "const_int_operand")] UNSPECV_VZEROUPPER)] "TARGET_AVX" "vzeroupper" @@ -11901,9 +11901,9 @@ (set_attr "mode" "OI")]) (define_expand "avx2_perm<mode>" - [(match_operand:VI8F_256 0 "register_operand" "") - (match_operand:VI8F_256 1 "nonimmediate_operand" "") - (match_operand:SI 2 "const_0_to_255_operand" "")] + [(match_operand:VI8F_256 0 "register_operand") + (match_operand:VI8F_256 1 "nonimmediate_operand") + (match_operand:SI 2 "const_0_to_255_operand")] "TARGET_AVX2" { int mask = INTVAL (operands[2]); @@ -11919,10 +11919,10 @@ [(set (match_operand:VI8F_256 0 "register_operand" "=x") (vec_select:VI8F_256 (match_operand:VI8F_256 1 "nonimmediate_operand" "xm") - (parallel [(match_operand 2 "const_0_to_3_operand" "") - (match_operand 3 "const_0_to_3_operand" "") - (match_operand 4 "const_0_to_3_operand" "") - (match_operand 5 "const_0_to_3_operand" "")])))] + (parallel [(match_operand 2 "const_0_to_3_operand") + (match_operand 3 "const_0_to_3_operand") + (match_operand 4 "const_0_to_3_operand") + (match_operand 5 "const_0_to_3_operand")])))] "TARGET_AVX2" { int mask = 0; @@ -11992,9 +11992,9 @@ (set_attr "mode" "OI")]) (define_split - [(set (match_operand:AVX_VEC_DUP_MODE 0 "register_operand" "") + [(set (match_operand:AVX_VEC_DUP_MODE 0 "register_operand") (vec_duplicate:AVX_VEC_DUP_MODE - (match_operand:<ssescalarmode> 1 "register_operand" "")))] + (match_operand:<ssescalarmode> 1 "register_operand")))] "TARGET_AVX && reload_completed" [(set (match_dup 2) (vec_duplicate:<ssehalfvecmode> (match_dup 1))) @@ -12086,10 +12086,10 @@ }) (define_expand "avx_vpermil<mode>" - [(set (match_operand:VF2 0 "register_operand" "") + [(set (match_operand:VF2 0 "register_operand") (vec_select:VF2 - (match_operand:VF2 1 "nonimmediate_operand" "") - (match_operand:SI 2 "const_0_to_255_operand" "")))] + (match_operand:VF2 1 "nonimmediate_operand") + (match_operand:SI 2 "const_0_to_255_operand")))] "TARGET_AVX" { int mask = INTVAL (operands[2]); @@ -12108,10 +12108,10 @@ }) (define_expand "avx_vpermil<mode>" - [(set (match_operand:VF1 0 "register_operand" "") + [(set (match_operand:VF1 0 "register_operand") (vec_select:VF1 - (match_operand:VF1 1 "nonimmediate_operand" "") - (match_operand:SI 2 "const_0_to_255_operand" "")))] + (match_operand:VF1 1 "nonimmediate_operand") + (match_operand:SI 2 "const_0_to_255_operand")))] "TARGET_AVX" { int mask = INTVAL (operands[2]); @@ -12138,7 +12138,7 @@ (vec_select:VF (match_operand:VF 1 "nonimmediate_operand" "xm") (match_parallel 2 "" - [(match_operand 3 "const_int_operand" "")])))] + [(match_operand 3 "const_int_operand")])))] "TARGET_AVX && avx_vpermilp_parallel (operands[2], <MODE>mode)" { @@ -12166,11 +12166,11 @@ (set_attr "mode" "<MODE>")]) (define_expand "avx_vperm2f128<mode>3" - [(set (match_operand:AVX256MODE2P 0 "register_operand" "") + [(set (match_operand:AVX256MODE2P 0 "register_operand") (unspec:AVX256MODE2P - [(match_operand:AVX256MODE2P 1 "register_operand" "") - (match_operand:AVX256MODE2P 2 "nonimmediate_operand" "") - (match_operand:SI 3 "const_0_to_255_operand" "")] + [(match_operand:AVX256MODE2P 1 "register_operand") + (match_operand:AVX256MODE2P 2 "nonimmediate_operand") + (match_operand:SI 3 "const_0_to_255_operand")] UNSPEC_VPERMIL2F128))] "TARGET_AVX" { @@ -12224,7 +12224,7 @@ (match_operand:AVX256MODE2P 1 "register_operand" "x") (match_operand:AVX256MODE2P 2 "nonimmediate_operand" "xm")) (match_parallel 3 "" - [(match_operand 4 "const_int_operand" "")])))] + [(match_operand 4 "const_int_operand")])))] "TARGET_AVX && avx_vperm2f128_parallel (operands[3], <MODE>mode)" { @@ -12243,10 +12243,10 @@ (set_attr "mode" "<sseinsnmode>")]) (define_expand "avx_vinsertf128<mode>" - [(match_operand:V_256 0 "register_operand" "") - (match_operand:V_256 1 "register_operand" "") - (match_operand:<ssehalfvecmode> 2 "nonimmediate_operand" "") - (match_operand:SI 3 "const_0_to_1_operand" "")] + [(match_operand:V_256 0 "register_operand") + (match_operand:V_256 1 "register_operand") + (match_operand:<ssehalfvecmode> 2 "nonimmediate_operand") + (match_operand:SI 3 "const_0_to_1_operand")] "TARGET_AVX" { rtx (*insn)(rtx, rtx, rtx); @@ -12487,8 +12487,8 @@ }) (define_expand "vec_init<mode>" - [(match_operand:V_256 0 "register_operand" "") - (match_operand 1 "" "")] + [(match_operand:V_256 0 "register_operand") + (match_operand 1)] "TARGET_AVX" { ix86_expand_vector_init (false, operands[0], operands[1]); @@ -12496,9 +12496,9 @@ }) (define_expand "avx2_extracti128" - [(match_operand:V2DI 0 "nonimmediate_operand" "") - (match_operand:V4DI 1 "register_operand" "") - (match_operand:SI 2 "const_0_to_1_operand" "")] + [(match_operand:V2DI 0 "nonimmediate_operand") + (match_operand:V4DI 1 "register_operand") + (match_operand:SI 2 "const_0_to_1_operand")] "TARGET_AVX2" { rtx (*insn)(rtx, rtx); @@ -12520,10 +12520,10 @@ }) (define_expand "avx2_inserti128" - [(match_operand:V4DI 0 "register_operand" "") - (match_operand:V4DI 1 "register_operand" "") - (match_operand:V2DI 2 "nonimmediate_operand" "") - (match_operand:SI 3 "const_0_to_1_operand" "")] + [(match_operand:V4DI 0 "register_operand") + (match_operand:V4DI 1 "register_operand") + (match_operand:V2DI 2 "nonimmediate_operand") + (match_operand:SI 3 "const_0_to_1_operand")] "TARGET_AVX2" { rtx (*insn)(rtx, rtx, rtx); @@ -12631,10 +12631,10 @@ (set_attr "mode" "V8SF")]) (define_expand "vcvtps2ph" - [(set (match_operand:V8HI 0 "register_operand" "") + [(set (match_operand:V8HI 0 "register_operand") (vec_concat:V8HI - (unspec:V4HI [(match_operand:V4SF 1 "register_operand" "") - (match_operand:SI 2 "const_0_to_255_operand" "")] + (unspec:V4HI [(match_operand:V4SF 1 "register_operand") + (match_operand:SI 2 "const_0_to_255_operand")] UNSPEC_VCVTPS2PH) (match_dup 3)))] "TARGET_F16C" @@ -12646,7 +12646,7 @@ (unspec:V4HI [(match_operand:V4SF 1 "register_operand" "x") (match_operand:SI 2 "const_0_to_255_operand" "N")] UNSPEC_VCVTPS2PH) - (match_operand:V4HI 3 "const0_operand" "")))] + (match_operand:V4HI 3 "const0_operand")))] "TARGET_F16C" "vcvtps2ph\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "ssecvt") @@ -12695,19 +12695,19 @@ (V8SI "V4SI") (V8SF "V4SF")]) (define_expand "avx2_gathersi<mode>" - [(parallel [(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "") + [(parallel [(set (match_operand:VEC_GATHER_MODE 0 "register_operand") (unspec:VEC_GATHER_MODE - [(match_operand:VEC_GATHER_MODE 1 "register_operand" "") + [(match_operand:VEC_GATHER_MODE 1 "register_operand") (mem:<ssescalarmode> (match_par_dup 7 - [(match_operand 2 "vsib_address_operand" "") + [(match_operand 2 "vsib_address_operand") (match_operand:<VEC_GATHER_IDXSI> - 3 "register_operand" "") - (match_operand:SI 5 "const1248_operand " "")])) + 3 "register_operand") + (match_operand:SI 5 "const1248_operand ")])) (mem:BLK (scratch)) - (match_operand:VEC_GATHER_MODE 4 "register_operand" "")] + (match_operand:VEC_GATHER_MODE 4 "register_operand")] UNSPEC_GATHER)) - (clobber (match_scratch:VEC_GATHER_MODE 6 ""))])] + (clobber (match_scratch:VEC_GATHER_MODE 6))])] "TARGET_AVX2" { operands[7] @@ -12756,20 +12756,20 @@ (set_attr "mode" "<sseinsnmode>")]) (define_expand "avx2_gatherdi<mode>" - [(parallel [(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "") + [(parallel [(set (match_operand:VEC_GATHER_MODE 0 "register_operand") (unspec:VEC_GATHER_MODE - [(match_operand:<VEC_GATHER_SRCDI> 1 "register_operand" "") + [(match_operand:<VEC_GATHER_SRCDI> 1 "register_operand") (mem:<ssescalarmode> (match_par_dup 7 - [(match_operand 2 "vsib_address_operand" "") + [(match_operand 2 "vsib_address_operand") (match_operand:<VEC_GATHER_IDXDI> - 3 "register_operand" "") - (match_operand:SI 5 "const1248_operand " "")])) + 3 "register_operand") + (match_operand:SI 5 "const1248_operand ")])) (mem:BLK (scratch)) (match_operand:<VEC_GATHER_SRCDI> - 4 "register_operand" "")] + 4 "register_operand")] UNSPEC_GATHER)) - (clobber (match_scratch:VEC_GATHER_MODE 6 ""))])] + (clobber (match_scratch:VEC_GATHER_MODE 6))])] "TARGET_AVX2" { operands[7] diff --git a/gcc/config/i386/sync.md b/gcc/config/i386/sync.md index 9f9134486c4..18ccabfc112 100644 --- a/gcc/config/i386/sync.md +++ b/gcc/config/i386/sync.md @@ -46,7 +46,7 @@ }) (define_insn "*sse2_lfence" - [(set (match_operand:BLK 0 "" "") + [(set (match_operand:BLK 0) (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))] "TARGET_SSE2" "lfence" @@ -65,7 +65,7 @@ }) (define_insn "*sse_sfence" - [(set (match_operand:BLK 0 "" "") + [(set (match_operand:BLK 0) (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))] "TARGET_SSE || TARGET_3DNOW_A" "sfence" @@ -84,7 +84,7 @@ }) (define_insn "mfence_sse2" - [(set (match_operand:BLK 0 "" "") + [(set (match_operand:BLK 0) (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))] "TARGET_64BIT || TARGET_SSE2" "mfence" @@ -94,7 +94,7 @@ (set_attr "memory" "unknown")]) (define_insn "mfence_nosse" - [(set (match_operand:BLK 0 "" "") + [(set (match_operand:BLK 0) (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE)) (clobber (reg:CC FLAGS_REG))] "!(TARGET_64BIT || TARGET_SSE2)" @@ -102,7 +102,7 @@ [(set_attr "memory" "unknown")]) (define_expand "mem_thread_fence" - [(match_operand:SI 0 "const_int_operand" "")] ;; model + [(match_operand:SI 0 "const_int_operand")] ;; model "" { /* Unless this is a SEQ_CST fence, the i386 memory model is strong @@ -142,9 +142,9 @@ ]) (define_expand "atomic_load<mode>" - [(set (match_operand:ATOMIC 0 "register_operand" "") - (unspec:ATOMIC [(match_operand:ATOMIC 1 "memory_operand" "") - (match_operand:SI 2 "const_int_operand" "")] + [(set (match_operand:ATOMIC 0 "register_operand") + (unspec:ATOMIC [(match_operand:ATOMIC 1 "memory_operand") + (match_operand:SI 2 "const_int_operand")] UNSPEC_MOVA))] "" { @@ -200,9 +200,9 @@ }) (define_expand "atomic_store<mode>" - [(set (match_operand:ATOMIC 0 "memory_operand" "") - (unspec:ATOMIC [(match_operand:ATOMIC 1 "register_operand" "") - (match_operand:SI 2 "const_int_operand" "")] + [(set (match_operand:ATOMIC 0 "memory_operand") + (unspec:ATOMIC [(match_operand:ATOMIC 1 "register_operand") + (match_operand:SI 2 "const_int_operand")] UNSPEC_MOVA))] "" { @@ -305,14 +305,14 @@ (set_attr "mode" "DI")]) (define_expand "atomic_compare_and_swap<mode>" - [(match_operand:QI 0 "register_operand" "") ;; bool success output - (match_operand:SWI124 1 "register_operand" "") ;; oldval output - (match_operand:SWI124 2 "memory_operand" "") ;; memory - (match_operand:SWI124 3 "register_operand" "") ;; expected input - (match_operand:SWI124 4 "register_operand" "") ;; newval input - (match_operand:SI 5 "const_int_operand" "") ;; is_weak - (match_operand:SI 6 "const_int_operand" "") ;; success model - (match_operand:SI 7 "const_int_operand" "")] ;; failure model + [(match_operand:QI 0 "register_operand") ;; bool success output + (match_operand:SWI124 1 "register_operand") ;; oldval output + (match_operand:SWI124 2 "memory_operand") ;; memory + (match_operand:SWI124 3 "register_operand") ;; expected input + (match_operand:SWI124 4 "register_operand") ;; newval input + (match_operand:SI 5 "const_int_operand") ;; is_weak + (match_operand:SI 6 "const_int_operand") ;; success model + (match_operand:SI 7 "const_int_operand")] ;; failure model "TARGET_CMPXCHG" { emit_insn (gen_atomic_compare_and_swap_single<mode> @@ -332,14 +332,14 @@ (define_mode_attr DCASHMODE [(DI "SI") (TI "DI")]) (define_expand "atomic_compare_and_swap<mode>" - [(match_operand:QI 0 "register_operand" "") ;; bool success output - (match_operand:CASMODE 1 "register_operand" "") ;; oldval output - (match_operand:CASMODE 2 "memory_operand" "") ;; memory - (match_operand:CASMODE 3 "register_operand" "") ;; expected input - (match_operand:CASMODE 4 "register_operand" "") ;; newval input - (match_operand:SI 5 "const_int_operand" "") ;; is_weak - (match_operand:SI 6 "const_int_operand" "") ;; success model - (match_operand:SI 7 "const_int_operand" "")] ;; failure model + [(match_operand:QI 0 "register_operand") ;; bool success output + (match_operand:CASMODE 1 "register_operand") ;; oldval output + (match_operand:CASMODE 2 "memory_operand") ;; memory + (match_operand:CASMODE 3 "register_operand") ;; expected input + (match_operand:CASMODE 4 "register_operand") ;; newval input + (match_operand:SI 5 "const_int_operand") ;; is_weak + (match_operand:SI 6 "const_int_operand") ;; success model + (match_operand:SI 7 "const_int_operand")] ;; failure model "TARGET_CMPXCHG" { if (<MODE>mode == DImode && TARGET_64BIT) @@ -448,7 +448,7 @@ [(set (match_operand:SWI 0 "register_operand" "=<r>") (unspec_volatile:SWI [(match_operand:SWI 1 "memory_operand" "+m") - (match_operand:SI 3 "const_int_operand" "")] ;; model + (match_operand:SI 3 "const_int_operand")] ;; model UNSPECV_XCHG)) (set (match_dup 1) (plus:SWI (match_dup 1) @@ -461,12 +461,12 @@ ;; __sync_fetch_and_add (x, -N) == N into just lock {add,sub,inc,dec} ;; followed by testing of flags instead of lock xadd and comparisons. (define_peephole2 - [(set (match_operand:SWI 0 "register_operand" "") - (match_operand:SWI 2 "const_int_operand" "")) + [(set (match_operand:SWI 0 "register_operand") + (match_operand:SWI 2 "const_int_operand")) (parallel [(set (match_dup 0) (unspec_volatile:SWI - [(match_operand:SWI 1 "memory_operand" "") - (match_operand:SI 4 "const_int_operand" "")] + [(match_operand:SWI 1 "memory_operand") + (match_operand:SI 4 "const_int_operand")] UNSPECV_XCHG)) (set (match_dup 1) (plus:SWI (match_dup 1) @@ -474,7 +474,7 @@ (clobber (reg:CC FLAGS_REG))]) (set (reg:CCZ FLAGS_REG) (compare:CCZ (match_dup 0) - (match_operand:SWI 3 "const_int_operand" "")))] + (match_operand:SWI 3 "const_int_operand")))] "peep2_reg_dead_p (3, operands[0]) && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) == -(unsigned HOST_WIDE_INT) INTVAL (operands[3]) @@ -492,7 +492,7 @@ [(set (reg:CCZ FLAGS_REG) (compare:CCZ (unspec_volatile:SWI [(match_operand:SWI 0 "memory_operand" "+m") - (match_operand:SI 3 "const_int_operand" "")] + (match_operand:SI 3 "const_int_operand")] UNSPECV_XCHG) (match_operand:SWI 2 "const_int_operand" "i"))) (set (match_dup 0) @@ -521,7 +521,7 @@ [(set (match_operand:SWI 0 "register_operand" "=<r>") ;; output (unspec_volatile:SWI [(match_operand:SWI 1 "memory_operand" "+m") ;; memory - (match_operand:SI 3 "const_int_operand" "")] ;; model + (match_operand:SI 3 "const_int_operand")] ;; model UNSPECV_XCHG)) (set (match_dup 1) (match_operand:SWI 2 "register_operand" "0"))] ;; input @@ -533,7 +533,7 @@ (unspec_volatile:SWI [(plus:SWI (match_dup 0) (match_operand:SWI 1 "nonmemory_operand" "<r><i>")) - (match_operand:SI 2 "const_int_operand" "")] ;; model + (match_operand:SI 2 "const_int_operand")] ;; model UNSPECV_LOCK)) (clobber (reg:CC FLAGS_REG))] "" @@ -557,7 +557,7 @@ (unspec_volatile:SWI [(minus:SWI (match_dup 0) (match_operand:SWI 1 "nonmemory_operand" "<r><i>")) - (match_operand:SI 2 "const_int_operand" "")] ;; model + (match_operand:SI 2 "const_int_operand")] ;; model UNSPECV_LOCK)) (clobber (reg:CC FLAGS_REG))] "" @@ -581,7 +581,7 @@ (unspec_volatile:SWI [(any_logic:SWI (match_dup 0) (match_operand:SWI 1 "nonmemory_operand" "<r><i>")) - (match_operand:SI 2 "const_int_operand" "")] ;; model + (match_operand:SI 2 "const_int_operand")] ;; model UNSPECV_LOCK)) (clobber (reg:CC FLAGS_REG))] "" |