diff options
| author | Kito Cheng <kito.cheng@sifive.com> | 2020-02-18 13:47:50 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2020-02-19 13:03:51 +0800 |
| commit | bfe78b08471fa6daffb8e8e8e70bd5b1d3071ff6 (patch) | |
| tree | 08b3bf5f5cc03b417b6ffc596ba93c0173404012 | |
| parent | 242b4fb7f4e6c6224e727fa5e9ed8a776d16ccf9 (diff) | |
| download | gcc-bfe78b08471fa6daffb8e8e8e70bd5b1d3071ff6.tar.gz | |
RISC-V: Using fmv.x.w/fmv.w.x rather than fmv.x.s/fmv.s.x
- fmv.x.s/fmv.s.x renamed to fmv.x.w/fmv.w.x in the latest RISC-V ISA
manual.
- Tested rv32gc/rv64gc on bare-metal with qemu.
ChangeLog
gcc/
Kito Cheng <kito.cheng@sifive.com>
* config/riscv/riscv.c (riscv_output_move) Using fmv.x.w/fmv.w.x
rather than fmv.x.s/fmv.s.x.
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv.c | 4 |
2 files changed, 7 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c2778e1d9d3..77c2a9ad810 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2020-01-21 Kito Cheng <kito.cheng@sifive.com> + + * config/riscv/riscv.c (riscv_output_move) Using fmv.x.w/fmv.w.x + rather than fmv.x.s/fmv.s.x. + 2020-02-18 James Greenhalgh <james.greenhalgh@arm.com> * config/aarch64/aarch64-simd-builtins.def diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index e0205c66f26..54de0a667a4 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -1917,7 +1917,7 @@ riscv_output_move (rtx dest, rtx src) if (dest_code == REG && GP_REG_P (REGNO (dest))) { if (src_code == REG && FP_REG_P (REGNO (src))) - return dbl_p ? "fmv.x.d\t%0,%1" : "fmv.x.s\t%0,%1"; + return dbl_p ? "fmv.x.d\t%0,%1" : "fmv.x.w\t%0,%1"; if (src_code == MEM) switch (GET_MODE_SIZE (mode)) @@ -1954,7 +1954,7 @@ riscv_output_move (rtx dest, rtx src) if (FP_REG_P (REGNO (dest))) { if (!dbl_p) - return "fmv.s.x\t%0,%z1"; + return "fmv.w.x\t%0,%z1"; if (TARGET_64BIT) return "fmv.d.x\t%0,%z1"; /* in RV32, we can emulate fmv.d.x %0, x0 using fcvt.d.w */ |