[AARCH64][Insn classification unification 3/N] ALU/shift types

2013-09-05  James Greenhalgh  <james.greenhalgh@arm.com>
	    Sofiane Naci  <sofiane.naci@arm.com>

	* config/arm/types.md (define_attr "type"):
	Expand "arlo_imm"
	into "adr", "alu_imm", "alus_imm", "logic_imm", "logics_imm".
	Expand "arlo_reg"
	into "adc_reg", "adc_imm", "adcs_reg", "adcs_imm", "alu_ext",
	"alu_reg", "alus_ext", "alus_reg", "bfm", "csel", "logic_reg",
	"logics_reg", "rev".
	Expand "arlo_shift"
	into "alu_shift_imm", "alus_shift_imm", "logic_shift_imm",
	"logics_shift_imm".
	Expand "arlo_shift_reg"
	into "alu_shift_reg", "alus_shift_reg", "logic_shift_reg",
	"logics_shift_reg".
	Expand "clz" into "clz, "rbit".
	Rename "shift" to "shift_imm".
	* config/arm/arm.md (define_attr "core_cycles"): Update for attribute
	changes.
	Update for attribute changes all occurrences of arlo_* and
	shift* types.
	* config/arm/arm-fixed.md: Update for attribute changes
	all occurrences of arlo_* types.
	* config/arm/thumb2.md: Update for attribute changes all occurrences
	of arlo_* types.
	* config/arm/arm.c (xscale_sched_adjust_cost):  (rtx insn, rtx
	(cortexa7_older_only): Likewise.
	(cortexa7_younger):  Likewise.
	* config/arm/arm1020e.md (1020alu_op): Update for attribute changes.
	(1020alu_shift_op): Likewise.
	(1020alu_shift_reg_op): Likewise.
	* config/arm/arm1026ejs.md (alu_op): Update for attribute changes.
	(alu_shift_op): Likewise.
	(alu_shift_reg_op): Likewise.
	* config/arm/arm1136jfs.md (11_alu_op): Update for
	attribute changes.
	(11_alu_shift_op): Likewise.
	(11_alu_shift_reg_op): Likewise.
	* config/arm/arm926ejs.md (9_alu_op): Update for attribute changes.
	(9_alu_shift_reg_op): Likewise.
	* config/arm/cortex-a15.md (cortex_a15_alu): Update for
	attribute changes.
	(cortex_a15_alu_shift): Likewise.
	(cortex_a15_alu_shift_reg): Likewise.
	* config/arm/cortex-a5.md (cortex_a5_alu): Update for
	attribute changes.
	(cortex_a5_alu_shift): Likewise.
	* config/arm/cortex-a53.md
	(cortex_a53_alu): Update for attribute changes.
	(cortex_a53_alu_shift): Likewise.
	* config/arm/cortex-a7.md
	(cortex_a7_alu_imm): Update for attribute changes.
	(cortex_a7_alu_reg): Likewise.
	(cortex_a7_alu_shift): Likewise.
	* config/arm/cortex-a8.md
	(cortex_a8_alu): Update for attribute changes.
	(cortex_a8_alu_shift): Likewise.
	(cortex_a8_alu_shift_reg): Likewise.
	* config/arm/cortex-a9.md
	(cortex_a9_dp): Update for attribute changes.
	(cortex_a9_dp_shift): Likewise.
	* config/arm/cortex-m4.md
	(cortex_m4_alu): Update for attribute changes.
	* config/arm/cortex-r4.md
	(cortex_r4_alu): Update for attribute changes.
	(cortex_r4_mov): Likewise.
	(cortex_r4_alu_shift_reg): Likewise.
	* config/arm/fa526.md
	(526_alu_op): Update for attribute changes.
	(526_alu_shift_op): Likewise.
	* config/arm/fa606te.md
	(606te_alu_op): Update for attribute changes.
	* config/arm/fa626te.md
	(626te_alu_op): Update for attribute changes.
	(626te_alu_shift_op): Likewise.
	* config/arm/fa726te.md
	(726te_alu_op): Update for attribute changes.
	(726te_alu_shift_op): Likewise.
	(726te_alu_shift_reg_op): Likewise.
	* config/arm/fmp626.md (mp626_alu_op): Update for attribute changes.
	(mp626_alu_shift_op): Likewise.
	* config/arm/marvell-pj4.md (pj4_alu): Update for attribute changes.
	(pj4_alu_conds): Likewise.
	(pj4_shift): Likewise.
	(pj4_shift_conds): Likewise.
	(pj4_alu_shift): Likewise.
	(pj4_alu_shift_conds): Likewise.
	* config/aarch64/aarch64.md: Update for attribute change
	all occurrences of arlo_* and shift* types.




git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@202291 138bc75d-0d04-0410-961f-82ee72b054a4

25 files changed, 619 insertions, 299 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 8aec62f724e..f6c6b3bb496 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,94 @@
+2013-09-05  James Greenhalgh  <james.greenhalgh@arm.com>
+	    Sofiane Naci  <sofiane.naci@arm.com>
+
+	* config/arm/types.md (define_attr "type"):
+	Expand "arlo_imm"
+	into "adr", "alu_imm", "alus_imm", "logic_imm", "logics_imm".
+	Expand "arlo_reg"
+	into "adc_reg", "adc_imm", "adcs_reg", "adcs_imm", "alu_ext",
+	"alu_reg", "alus_ext", "alus_reg", "bfm", "csel", "logic_reg",
+	"logics_reg", "rev".
+	Expand "arlo_shift"
+	into "alu_shift_imm", "alus_shift_imm", "logic_shift_imm",
+	"logics_shift_imm".
+	Expand "arlo_shift_reg"
+	into "alu_shift_reg", "alus_shift_reg", "logic_shift_reg",
+	"logics_shift_reg".
+	Expand "clz" into "clz, "rbit".
+	Rename "shift" to "shift_imm".
+	* config/arm/arm.md (define_attr "core_cycles"): Update for attribute
+	changes.
+	Update for attribute changes all occurrences of arlo_* and
+	shift* types.
+	* config/arm/arm-fixed.md: Update for attribute changes
+	all occurrences of arlo_* types.
+	* config/arm/thumb2.md: Update for attribute changes all occurrences
+	of arlo_* types.
+	* config/arm/arm.c (xscale_sched_adjust_cost):  (rtx insn, rtx
+	(cortexa7_older_only): Likewise.
+	(cortexa7_younger):  Likewise.
+	* config/arm/arm1020e.md (1020alu_op): Update for attribute changes.
+	(1020alu_shift_op): Likewise.
+	(1020alu_shift_reg_op): Likewise.
+	* config/arm/arm1026ejs.md (alu_op): Update for attribute changes.
+	(alu_shift_op): Likewise.
+	(alu_shift_reg_op): Likewise.
+	* config/arm/arm1136jfs.md (11_alu_op): Update for
+	attribute changes.
+	(11_alu_shift_op): Likewise.
+	(11_alu_shift_reg_op): Likewise.
+	* config/arm/arm926ejs.md (9_alu_op): Update for attribute changes.
+	(9_alu_shift_reg_op): Likewise.
+	* config/arm/cortex-a15.md (cortex_a15_alu): Update for
+	attribute changes.
+	(cortex_a15_alu_shift): Likewise.
+	(cortex_a15_alu_shift_reg): Likewise.
+	* config/arm/cortex-a5.md (cortex_a5_alu): Update for
+	attribute changes.
+	(cortex_a5_alu_shift): Likewise.
+	* config/arm/cortex-a53.md
+	(cortex_a53_alu): Update for attribute changes.
+	(cortex_a53_alu_shift): Likewise.
+	* config/arm/cortex-a7.md
+	(cortex_a7_alu_imm): Update for attribute changes.
+	(cortex_a7_alu_reg): Likewise.
+	(cortex_a7_alu_shift): Likewise.
+	* config/arm/cortex-a8.md
+	(cortex_a8_alu): Update for attribute changes.
+	(cortex_a8_alu_shift): Likewise.
+	(cortex_a8_alu_shift_reg): Likewise.
+	* config/arm/cortex-a9.md
+	(cortex_a9_dp): Update for attribute changes.
+	(cortex_a9_dp_shift): Likewise.
+	* config/arm/cortex-m4.md
+	(cortex_m4_alu): Update for attribute changes.
+	* config/arm/cortex-r4.md
+	(cortex_r4_alu): Update for attribute changes.
+	(cortex_r4_mov): Likewise.
+	(cortex_r4_alu_shift_reg): Likewise.
+	* config/arm/fa526.md
+	(526_alu_op): Update for attribute changes.
+	(526_alu_shift_op): Likewise.
+	* config/arm/fa606te.md
+	(606te_alu_op): Update for attribute changes.
+	* config/arm/fa626te.md
+	(626te_alu_op): Update for attribute changes.
+	(626te_alu_shift_op): Likewise.
+	* config/arm/fa726te.md
+	(726te_alu_op): Update for attribute changes.
+	(726te_alu_shift_op): Likewise.
+	(726te_alu_shift_reg_op): Likewise.
+	* config/arm/fmp626.md (mp626_alu_op): Update for attribute changes.
+	(mp626_alu_shift_op): Likewise.
+	* config/arm/marvell-pj4.md (pj4_alu): Update for attribute changes.
+	(pj4_alu_conds): Likewise.
+	(pj4_shift): Likewise.
+	(pj4_shift_conds): Likewise.
+	(pj4_alu_shift): Likewise.
+	(pj4_alu_shift_conds): Likewise.
+	* config/aarch64/aarch64.md: Update for attribute change
+	all occurrences of arlo_* and shift* types.
+
 2013-09-05  Mike Stump  <mikestump@comcast.net>
 
 	* tree.h: Move documentation for tree_function_decl to tree-core.h
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index d0321b3ef73..6cdff8735e0 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -833,8 +833,8 @@
    fmov\\t%w0, %s1
    fmov\\t%s0, %s1"
   [(set_attr "v8type" "move,move,move,alu,load1,load1,store1,store1,adr,adr,fmov,fmov,fmov")
-   (set_attr "type" "mov_reg,mov_reg,mov_reg,arlo_reg,load1,load1,store1,store1,\
-                     mov_reg,mov_reg,mov_reg,mov_reg,mov_reg")
+   (set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,load1,load1,store1,store1,\
+                     adr,adr,mov_reg,mov_reg,mov_reg")
    (set_attr "mode" "SI")
    (set_attr "fp" "*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes")]
 )
@@ -861,7 +861,7 @@
    movi\\t%d0, %1"
   [(set_attr "v8type" "move,move,move,alu,load1,load1,store1,store1,adr,adr,fmov,fmov,fmov,fmov")
    (set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,load1,load1,store1,store1,\
-                     mov_reg,mov_reg,mov_reg,mov_reg,mov_reg,mov_reg")
+                     adr,adr,mov_reg,mov_reg,mov_reg,mov_reg")
    (set_attr "mode" "DI")
    (set_attr "fp" "*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*")
    (set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,yes")]
@@ -1027,7 +1027,7 @@
    ldp\\t%0, %H0, %1
    stp\\t%1, %H1, %0"
   [(set_attr "v8type" "logic,move2,fmovi2f,fmovf2i,fconst,fconst,fpsimd_load,fpsimd_store,fpsimd_load2,fpsimd_store2")
-   (set_attr "type" "arlo_reg,mov_reg,f_mcr,f_mrc,fconstd,fconstd,\
+   (set_attr "type" "logic_reg,mov_reg,f_mcr,f_mrc,fconstd,fconstd,\
                      f_loadd,f_stored,f_loadd,f_stored")
    (set_attr "mode" "DF,DF,DF,DF,DF,DF,TF,TF,DF,DF")
    (set_attr "length" "4,8,8,8,4,4,4,4,4,4")
@@ -1278,7 +1278,7 @@
   add\\t%w0, %w1, %w2
   sub\\t%w0, %w1, #%n2"
   [(set_attr "v8type" "alu")
-   (set_attr "type" "arlo_imm,arlo_reg,arlo_imm")
+   (set_attr "type" "alu_imm,alu_reg,alu_imm")
    (set_attr "mode" "SI")]
 )
 
@@ -1295,7 +1295,7 @@
   add\\t%w0, %w1, %w2
   sub\\t%w0, %w1, #%n2"
   [(set_attr "v8type" "alu")
-   (set_attr "type" "arlo_imm,arlo_reg,arlo_imm")
+   (set_attr "type" "alu_imm,alu_reg,alu_imm")
    (set_attr "mode" "SI")]
 )
 
@@ -1312,7 +1312,7 @@
   sub\\t%x0, %x1, #%n2
   add\\t%d0, %d1, %d2"
   [(set_attr "v8type" "alu")
-   (set_attr "type" "arlo_imm,arlo_reg,arlo_imm,arlo_reg")
+   (set_attr "type" "alu_imm,alu_reg,alu_imm,alu_reg")
    (set_attr "mode" "DI")
    (set_attr "simd" "*,*,*,yes")]
 )
@@ -1331,7 +1331,7 @@
   adds\\t%<w>0, %<w>1, %<w>2
   subs\\t%<w>0, %<w>1, #%n2"
   [(set_attr "v8type" "alus")
-   (set_attr "type" "arlo_reg,arlo_imm,arlo_imm")
+   (set_attr "type" "alus_reg,alus_imm,alus_imm")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -1350,7 +1350,7 @@
   adds\\t%w0, %w1, %w2
   subs\\t%w0, %w1, #%n2"
   [(set_attr "v8type" "alus")
-   (set_attr "type" "arlo_reg,arlo_imm,arlo_imm")
+   (set_attr "type" "alus_reg,alus_imm,alus_imm")
    (set_attr "mode" "SI")]
 )
 
@@ -1368,7 +1368,7 @@
   ""
   "adds\\t%<w>0, %<w>3, %<w>1, lsl %p2"
   [(set_attr "v8type" "alus_shift")
-   (set_attr "type" "arlo_shift")
+   (set_attr "type" "alus_shift_imm")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -1386,7 +1386,7 @@
   ""
   "subs\\t%<w>0, %<w>1, %<w>2, lsl %p3"
   [(set_attr "v8type" "alus_shift")
-   (set_attr "type" "arlo_shift")
+   (set_attr "type" "alus_shift_imm")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -1402,7 +1402,7 @@
   ""
   "adds\\t%<GPI:w>0, %<GPI:w>2, %<GPI:w>1, <su>xt<ALLX:size>"
   [(set_attr "v8type" "alus_ext")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alus_ext")
    (set_attr "mode" "<GPI:MODE>")]
 )
 
@@ -1418,7 +1418,7 @@
   ""
   "subs\\t%<GPI:w>0, %<GPI:w>1, %<GPI:w>2, <su>xt<ALLX:size>"
   [(set_attr "v8type" "alus_ext")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alus_ext")
    (set_attr "mode" "<GPI:MODE>")]
 )
 
@@ -1440,7 +1440,7 @@
   "aarch64_is_extend_from_extract (<MODE>mode, operands[2], operands[3])"
   "adds\\t%<w>0, %<w>4, %<w>1, <su>xt%e3 %p2"
   [(set_attr "v8type" "alus_ext")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alus_ext")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -1462,7 +1462,7 @@
   "aarch64_is_extend_from_extract (<MODE>mode, operands[2], operands[3])"
   "subs\\t%<w>0, %<w>4, %<w>1, <su>xt%e3 %p2"
   [(set_attr "v8type" "alus_ext")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alus_ext")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -1478,7 +1478,7 @@
   cmn\\t%<w>0, %<w>1
   cmp\\t%<w>0, #%n1"
   [(set_attr "v8type" "alus")
-   (set_attr "type" "arlo_reg,arlo_imm,arlo_imm")
+   (set_attr "type" "alus_reg,alus_imm,alus_imm")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -1490,7 +1490,7 @@
   ""
   "cmn\\t%<w>0, %<w>1"
   [(set_attr "v8type" "alus")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alus_reg")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -1502,7 +1502,7 @@
   ""
   "add\\t%<w>0, %<w>3, %<w>1, <shift> %2"
   [(set_attr "v8type" "alu_shift")
-   (set_attr "type" "arlo_shift")
+   (set_attr "type" "alu_shift_imm")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -1516,7 +1516,7 @@
   ""
   "add\\t%w0, %w3, %w1, <shift> %2"
   [(set_attr "v8type" "alu_shift")
-   (set_attr "type" "arlo_shift")
+   (set_attr "type" "alu_shift_imm")
    (set_attr "mode" "SI")]
 )
 
@@ -1528,7 +1528,7 @@
   ""
   "add\\t%<w>0, %<w>3, %<w>1, lsl %p2"
   [(set_attr "v8type" "alu_shift")
-   (set_attr "type" "arlo_shift")
+   (set_attr "type" "alu_shift_imm")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -1539,7 +1539,7 @@
   ""
   "add\\t%<GPI:w>0, %<GPI:w>2, %<GPI:w>1, <su>xt<ALLX:size>"
   [(set_attr "v8type" "alu_ext")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alu_ext")
    (set_attr "mode" "<GPI:MODE>")]
 )
 
@@ -1552,7 +1552,7 @@
   ""
   "add\\t%w0, %w2, %w1, <su>xt<SHORT:size>"
   [(set_attr "v8type" "alu_ext")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alu_ext")
    (set_attr "mode" "SI")]
 )
 
@@ -1565,7 +1565,7 @@
   ""
   "add\\t%<GPI:w>0, %<GPI:w>3, %<GPI:w>1, <su>xt<ALLX:size> %2"
   [(set_attr "v8type" "alu_ext")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alu_ext")
    (set_attr "mode" "<GPI:MODE>")]
 )
 
@@ -1580,7 +1580,7 @@
   ""
   "add\\t%w0, %w3, %w1, <su>xt<SHORT:size> %2"
   [(set_attr "v8type" "alu_ext")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alu_ext")
    (set_attr "mode" "SI")]
 )
 
@@ -1593,7 +1593,7 @@
   ""
   "add\\t%<GPI:w>0, %<GPI:w>3, %<GPI:w>1, <su>xt<ALLX:size> %p2"
   [(set_attr "v8type" "alu_ext")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alu_ext")
    (set_attr "mode" "<GPI:MODE>")]
 )
 
@@ -1607,7 +1607,7 @@
   ""
   "add\\t%w0, %w3, %w1, <su>xt<SHORT:size> %p2"
   [(set_attr "v8type" "alu_ext")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alu_ext")
    (set_attr "mode" "SI")]
 )
 
@@ -1622,7 +1622,7 @@
   "aarch64_is_extend_from_extract (<MODE>mode, operands[2], operands[3])"
   "add\\t%<w>0, %<w>4, %<w>1, <su>xt%e3 %p2"
   [(set_attr "v8type" "alu_ext")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alu_ext")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -1639,7 +1639,7 @@
   "aarch64_is_extend_from_extract (SImode, operands[2], operands[3])"
   "add\\t%w0, %w4, %w1, <su>xt%e3 %p2"
   [(set_attr "v8type" "alu_ext")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alu_ext")
    (set_attr "mode" "SI")]
 )
 
@@ -1653,7 +1653,7 @@
    ""
    "adc\\t%<w>0, %<w>1, %<w>2"
   [(set_attr "v8type" "adc")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "adc_reg")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -1669,7 +1669,7 @@
    ""
    "adc\\t%w0, %w1, %w2"
   [(set_attr "v8type" "adc")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "adc_reg")
    (set_attr "mode" "SI")]
 )
 
@@ -1683,7 +1683,7 @@
    ""
    "adc\\t%<w>0, %<w>1, %<w>2"
   [(set_attr "v8type" "adc")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "adc_reg")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -1699,7 +1699,7 @@
    ""
    "adc\\t%w0, %w1, %w2"
   [(set_attr "v8type" "adc")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "adc_reg")
    (set_attr "mode" "SI")]
 )
 
@@ -1713,7 +1713,7 @@
    ""
    "adc\\t%<w>0, %<w>1, %<w>2"
   [(set_attr "v8type" "adc")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "adc_reg")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -1729,7 +1729,7 @@
    ""
    "adc\\t%w0, %w1, %w2"
   [(set_attr "v8type" "adc")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "adc_reg")
    (set_attr "mode" "SI")]
 )
 
@@ -1743,7 +1743,7 @@
    ""
    "adc\\t%<w>0, %<w>1, %<w>2"
   [(set_attr "v8type" "adc")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "adc_reg")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -1759,7 +1759,7 @@
    ""
    "adc\\t%w0, %w1, %w2"
   [(set_attr "v8type" "adc")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "adc_reg")
    (set_attr "mode" "SI")]
 )
 
@@ -1776,7 +1776,7 @@
 					   INTVAL (operands[3])));
   return \"add\t%<w>0, %<w>4, %<w>1, uxt%e3 %p2\";"
   [(set_attr "v8type" "alu_ext")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alu_ext")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -1795,7 +1795,7 @@
 					   INTVAL (operands[3])));
   return \"add\t%w0, %w4, %w1, uxt%e3 %p2\";"
   [(set_attr "v8type" "alu_ext")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alu_ext")
    (set_attr "mode" "SI")]
 )
 
@@ -1806,7 +1806,7 @@
   ""
   "sub\\t%w0, %w1, %w2"
   [(set_attr "v8type" "alu")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alu_reg")
    (set_attr "mode" "SI")]
 )
 
@@ -1819,7 +1819,7 @@
   ""
   "sub\\t%w0, %w1, %w2"
   [(set_attr "v8type" "alu")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alu_reg")
    (set_attr "mode" "SI")]
 )
 
@@ -1832,7 +1832,7 @@
    sub\\t%x0, %x1, %x2
    sub\\t%d0, %d1, %d2"
   [(set_attr "v8type" "alu")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alu_reg")
    (set_attr "mode" "DI")
    (set_attr "simd" "*,yes")]
 )
@@ -1848,7 +1848,7 @@
   ""
   "subs\\t%<w>0, %<w>1, %<w>2"
   [(set_attr "v8type" "alus")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alus_reg")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -1863,7 +1863,7 @@
   ""
   "subs\\t%w0, %w1, %w2"
   [(set_attr "v8type" "alus")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alus_reg")
    (set_attr "mode" "SI")]
 )
 
@@ -1876,7 +1876,7 @@
   ""
   "sub\\t%<w>0, %<w>3, %<w>1, <shift> %2"
   [(set_attr "v8type" "alu_shift")
-   (set_attr "type" "arlo_shift")
+   (set_attr "type" "alu_shift_imm")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -1891,7 +1891,7 @@
   ""
   "sub\\t%w0, %w3, %w1, <shift> %2"
   [(set_attr "v8type" "alu_shift")
-   (set_attr "type" "arlo_shift")
+   (set_attr "type" "alu_shift_imm")
    (set_attr "mode" "SI")]
 )
 
@@ -1904,7 +1904,7 @@
   ""
   "sub\\t%<w>0, %<w>3, %<w>1, lsl %p2"
   [(set_attr "v8type" "alu_shift")
-   (set_attr "type" "arlo_shift")
+   (set_attr "type" "alu_shift_imm")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -1919,7 +1919,7 @@
   ""
   "sub\\t%w0, %w3, %w1, lsl %p2"
   [(set_attr "v8type" "alu_shift")
-   (set_attr "type" "arlo_shift")
+   (set_attr "type" "alu_shift_imm")
    (set_attr "mode" "SI")]
 )
 
@@ -1931,7 +1931,7 @@
   ""
   "sub\\t%<GPI:w>0, %<GPI:w>1, %<GPI:w>2, <su>xt<ALLX:size>"
   [(set_attr "v8type" "alu_ext")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alu_ext")
    (set_attr "mode" "<GPI:MODE>")]
 )
 
@@ -1945,7 +1945,7 @@
   ""
   "sub\\t%w0, %w1, %w2, <su>xt<SHORT:size>"
   [(set_attr "v8type" "alu_ext")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alu_ext")
    (set_attr "mode" "SI")]
 )
 
@@ -1958,7 +1958,7 @@
   ""
   "sub\\t%<GPI:w>0, %<GPI:w>1, %<GPI:w>2, <su>xt<ALLX:size> %3"
   [(set_attr "v8type" "alu_ext")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alu_ext")
    (set_attr "mode" "<GPI:MODE>")]
 )
 
@@ -1973,7 +1973,7 @@
   ""
   "sub\\t%w0, %w1, %w2, <su>xt<SHORT:size> %3"
   [(set_attr "v8type" "alu_ext")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alu_ext")
    (set_attr "mode" "SI")]
 )
 
@@ -1988,7 +1988,7 @@
   "aarch64_is_extend_from_extract (<MODE>mode, operands[2], operands[3])"
   "sub\\t%<w>0, %<w>4, %<w>1, <su>xt%e3 %p2"
   [(set_attr "v8type" "alu_ext")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alu_ext")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -2005,7 +2005,7 @@
   "aarch64_is_extend_from_extract (SImode, operands[2], operands[3])"
   "sub\\t%w0, %w4, %w1, <su>xt%e3 %p2"
   [(set_attr "v8type" "alu_ext")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alu_ext")
    (set_attr "mode" "SI")]
 )
 
@@ -2019,7 +2019,7 @@
    ""
    "sbc\\t%<w>0, %<w>1, %<w>2"
   [(set_attr "v8type" "adc")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "adc_reg")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -2035,7 +2035,7 @@
    ""
    "sbc\\t%w0, %w1, %w2"
   [(set_attr "v8type" "adc")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "adc_reg")
    (set_attr "mode" "SI")]
 )
 
@@ -2052,7 +2052,7 @@
 					   INTVAL (operands[3])));
   return \"sub\t%<w>0, %<w>4, %<w>1, uxt%e3 %p2\";"
   [(set_attr "v8type" "alu_ext")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alu_ext")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -2071,7 +2071,7 @@
 					   INTVAL (operands[3])));
   return \"sub\t%w0, %w4, %w1, uxt%e3 %p2\";"
   [(set_attr "v8type" "alu_ext")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alu_ext")
    (set_attr "mode" "SI")]
 )
 
@@ -2104,7 +2104,7 @@
     DONE;
   }
   [(set_attr "v8type" "alu")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alu_reg")
    (set_attr "mode" "DI")]
 )
 
@@ -2116,7 +2116,7 @@
    neg\\t%<w>0, %<w>1
    neg\\t%<rtn>0<vas>, %<rtn>1<vas>"
   [(set_attr "v8type" "alu")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alu_reg")
    (set_attr "simd_type" "*,simd_negabs")
    (set_attr "simd" "*,yes")
    (set_attr "mode" "<MODE>")
@@ -2130,7 +2130,7 @@
   ""
   "neg\\t%w0, %w1"
   [(set_attr "v8type" "alu")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alu_reg")
    (set_attr "mode" "SI")]
 )
 
@@ -2141,7 +2141,7 @@
   ""
   "ngc\\t%<w>0, %<w>1"
   [(set_attr "v8type" "adc")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "adc_reg")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -2153,7 +2153,7 @@
   ""
   "ngc\\t%w0, %w1"
   [(set_attr "v8type" "adc")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "adc_reg")
    (set_attr "mode" "SI")]
 )
 
@@ -2166,7 +2166,7 @@
   ""
   "negs\\t%<w>0, %<w>1"
   [(set_attr "v8type" "alus")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alus_reg")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -2180,7 +2180,7 @@
   ""
   "negs\\t%w0, %w1"
   [(set_attr "v8type" "alus")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alus_reg")
    (set_attr "mode" "SI")]
 )
 
@@ -2196,7 +2196,7 @@
   ""
   "negs\\t%<w>0, %<w>1, <shift> %2"
   [(set_attr "v8type" "alus_shift")
-   (set_attr "type" "arlo_shift")
+   (set_attr "type" "alus_shift_imm")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -2208,7 +2208,7 @@
   ""
   "neg\\t%<w>0, %<w>1, <shift> %2"
   [(set_attr "v8type" "alu_shift")
-   (set_attr "type" "arlo_shift")
+   (set_attr "type" "alu_shift_imm")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -2222,7 +2222,7 @@
   ""
   "neg\\t%w0, %w1, <shift> %2"
   [(set_attr "v8type" "alu_shift")
-   (set_attr "type" "arlo_shift")
+   (set_attr "type" "alu_shift_imm")
    (set_attr "mode" "SI")]
 )
 
@@ -2234,7 +2234,7 @@
   ""
   "neg\\t%<w>0, %<w>1, lsl %p2"
   [(set_attr "v8type" "alu_shift")
-   (set_attr "type" "arlo_shift")
+   (set_attr "type" "alu_shift_imm")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -2248,7 +2248,7 @@
   ""
   "neg\\t%w0, %w1, lsl %p2"
   [(set_attr "v8type" "alu_shift")
-   (set_attr "type" "arlo_shift")
+   (set_attr "type" "alu_shift_imm")
    (set_attr "mode" "SI")]
 )
 
@@ -2459,7 +2459,7 @@
    cmp\\t%<w>0, %<w>1
    cmn\\t%<w>0, #%n1"
   [(set_attr "v8type" "alus")
-   (set_attr "type" "arlo_reg,arlo_imm,arlo_imm")
+   (set_attr "type" "alus_reg,alus_imm,alus_imm")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -2498,7 +2498,7 @@
   ""
   "cmp\\t%<w>2, %<w>0, <shift> %1"
   [(set_attr "v8type" "alus_shift")
-   (set_attr "type" "arlo_shift")
+   (set_attr "type" "alus_shift_imm")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -2510,7 +2510,7 @@
   ""
   "cmp\\t%<GPI:w>1, %<GPI:w>0, <su>xt<ALLX:size>"
   [(set_attr "v8type" "alus_ext")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alus_ext")
    (set_attr "mode" "<GPI:MODE>")]
 )
 
@@ -2524,7 +2524,7 @@
   ""
   "cmp\\t%<GPI:w>2, %<GPI:w>0, <su>xt<ALLX:size> %1"
   [(set_attr "v8type" "alus_ext")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alus_ext")
    (set_attr "mode" "<GPI:MODE>")]
 )
 
@@ -2565,7 +2565,7 @@
   ""
   "cset\\t%<w>0, %m1"
   [(set_attr "v8type" "csel")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "csel")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -2578,7 +2578,7 @@
   ""
   "cset\\t%w0, %m1"
   [(set_attr "v8type" "csel")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "csel")
    (set_attr "mode" "SI")]
 )
 
@@ -2589,7 +2589,7 @@
   ""
   "csetm\\t%<w>0, %m1"
   [(set_attr "v8type" "csel")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "csel")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -2602,7 +2602,7 @@
   ""
   "csetm\\t%w0, %m1"
   [(set_attr "v8type" "csel")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "csel")
    (set_attr "mode" "SI")]
 )
 
@@ -2657,7 +2657,7 @@
    mov\\t%<w>0, -1
    mov\\t%<w>0, 1"
   [(set_attr "v8type" "csel")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "csel")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -2682,7 +2682,7 @@
    mov\\t%w0, -1
    mov\\t%w0, 1"
   [(set_attr "v8type" "csel")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "csel")
    (set_attr "mode" "SI")]
 )
 
@@ -2696,7 +2696,7 @@
   "TARGET_FLOAT"
   "fcsel\\t%<s>0, %<s>3, %<s>4, %m1"
   [(set_attr "v8type" "fcsel")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "fcsel")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -2746,7 +2746,7 @@
   ""
   "csinc\\t%<w>0, %<w>1, %<w>1, %M2"
   [(set_attr "v8type" "csel")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "csel")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "csinc3<mode>_insn"
@@ -2760,7 +2760,7 @@
   ""
   "csinc\\t%<w>0, %<w>4, %<w>3, %M1"
   [(set_attr "v8type" "csel")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "csel")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -2774,7 +2774,7 @@
   ""
   "csinv\\t%<w>0, %<w>4, %<w>3, %M1"
   [(set_attr "v8type" "csel")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "csel")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "*csneg3<mode>_insn"
@@ -2787,7 +2787,7 @@
   ""
   "csneg\\t%<w>0, %<w>4, %<w>3, %M1"
   [(set_attr "v8type" "csel")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "csel")
    (set_attr "mode" "<MODE>")])
 
 ;; -------------------------------------------------------------------
@@ -2801,7 +2801,7 @@
   ""
   "<logical>\\t%<w>0, %<w>1, %<w>2"
   [(set_attr "v8type" "logic,logic_imm")
-   (set_attr "type" "arlo_reg,arlo_imm")
+   (set_attr "type" "logic_reg,logic_imm")
    (set_attr "mode" "<MODE>")])
 
 ;; zero_extend version of above
@@ -2813,7 +2813,7 @@
   ""
   "<logical>\\t%w0, %w1, %w2"
   [(set_attr "v8type" "logic,logic_imm")
-   (set_attr "type" "arlo_reg,arlo_imm")
+   (set_attr "type" "logic_reg,logic_imm")
    (set_attr "mode" "SI")])
 
 (define_insn "*and<mode>3_compare0"
@@ -2827,7 +2827,7 @@
   ""
   "ands\\t%<w>0, %<w>1, %<w>2"
   [(set_attr "v8type" "logics,logics_imm")
-   (set_attr "type" "arlo_reg,arlo_imm")
+   (set_attr "type" "logics_reg,logics_imm")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -2843,7 +2843,7 @@
   ""
   "ands\\t%w0, %w1, %w2"
   [(set_attr "v8type" "logics,logics_imm")
-   (set_attr "type" "arlo_reg,arlo_imm")
+   (set_attr "type" "logics_reg,logics_imm")
    (set_attr "mode" "SI")]
 )
 
@@ -2860,7 +2860,7 @@
   ""
   "ands\\t%<w>0, %<w>3, %<w>1, <SHIFT:shift> %2"
   [(set_attr "v8type" "logics_shift")
-   (set_attr "type" "arlo_shift")
+   (set_attr "type" "logics_shift_imm")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -2879,7 +2879,7 @@
   ""
   "ands\\t%w0, %w3, %w1, <SHIFT:shift> %2"
   [(set_attr "v8type" "logics_shift")
-   (set_attr "type" "arlo_shift")
+   (set_attr "type" "logics_shift_imm")
    (set_attr "mode" "SI")]
 )
 
@@ -2892,7 +2892,7 @@
   ""
   "<LOGICAL:logical>\\t%<w>0, %<w>3, %<w>1, <SHIFT:shift> %2"
   [(set_attr "v8type" "logic_shift")
-   (set_attr "type" "arlo_shift")
+   (set_attr "type" "logic_shift_imm")
    (set_attr "mode" "<MODE>")])
 
 ;; zero_extend version of above
@@ -2906,7 +2906,7 @@
   ""
   "<LOGICAL:logical>\\t%w0, %w3, %w1, <SHIFT:shift> %2"
   [(set_attr "v8type" "logic_shift")
-   (set_attr "type" "arlo_shift")
+   (set_attr "type" "logic_shift_imm")
    (set_attr "mode" "SI")])
 
 (define_insn "one_cmpl<mode>2"
@@ -2915,7 +2915,7 @@
   ""
   "mvn\\t%<w>0, %<w>1"
   [(set_attr "v8type" "logic")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "logic_reg")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "*one_cmpl_<optab><mode>2"
@@ -2925,7 +2925,7 @@
   ""
   "mvn\\t%<w>0, %<w>1, <shift> %2"
   [(set_attr "v8type" "logic_shift")
-   (set_attr "type" "arlo_shift")
+   (set_attr "type" "logic_shift_imm")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "*<LOGICAL:optab>_one_cmpl<mode>3"
@@ -2936,7 +2936,7 @@
   ""
   "<LOGICAL:nlogical>\\t%<w>0, %<w>2, %<w>1"
   [(set_attr "v8type" "logic")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "logic_reg")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "*and_one_cmpl<mode>3_compare0"
@@ -2951,7 +2951,7 @@
   ""
   "bics\\t%<w>0, %<w>2, %<w>1"
   [(set_attr "v8type" "logics")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "logics_reg")
    (set_attr "mode" "<MODE>")])
 
 ;; zero_extend version of above
@@ -2967,7 +2967,7 @@
   ""
   "bics\\t%w0, %w2, %w1"
   [(set_attr "v8type" "logics")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "logics_reg")
    (set_attr "mode" "SI")])
 
 (define_insn "*<LOGICAL:optab>_one_cmpl_<SHIFT:optab><mode>3"
@@ -2980,7 +2980,7 @@
   ""
   "<LOGICAL:nlogical>\\t%<w>0, %<w>3, %<w>1, <SHIFT:shift> %2"
   [(set_attr "v8type" "logic_shift")
-   (set_attr "type" "arlo_shift")
+   (set_attr "type" "logics_shift_imm")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "*and_one_cmpl_<SHIFT:optab><mode>3_compare0"
@@ -2999,7 +2999,7 @@
   ""
   "bics\\t%<w>0, %<w>3, %<w>1, <SHIFT:shift> %2"
   [(set_attr "v8type" "logics_shift")
-   (set_attr "type" "arlo_shift")
+   (set_attr "type" "logics_shift_imm")
    (set_attr "mode" "<MODE>")])
 
 ;; zero_extend version of above
@@ -3019,7 +3019,7 @@
   ""
   "bics\\t%w0, %w3, %w1, <SHIFT:shift> %2"
   [(set_attr "v8type" "logics_shift")
-   (set_attr "type" "arlo_shift")
+   (set_attr "type" "logics_shift_imm")
    (set_attr "mode" "SI")])
 
 (define_insn "clz<mode>2"
@@ -3061,7 +3061,7 @@
   ""
   "rbit\\t%<w>0, %<w>1"
   [(set_attr "v8type" "rbit")
-   (set_attr "type" "clz")
+   (set_attr "type" "rbit")
    (set_attr "mode" "<MODE>")])
 
 (define_expand "ctz<mode>2"
@@ -3084,7 +3084,7 @@
   ""
   "tst\\t%<w>0, %<w>1"
   [(set_attr "v8type" "logics")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "logics_reg")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "*and_<SHIFT:optab><mode>3nr_compare0"
@@ -3098,7 +3098,7 @@
   ""
   "tst\\t%<w>2, %<w>0, <SHIFT:shift> %1"
   [(set_attr "v8type" "logics_shift")
-   (set_attr "type" "arlo_shift")
+   (set_attr "type" "logics_shift_imm")
    (set_attr "mode" "<MODE>")])
 
 ;; -------------------------------------------------------------------
@@ -3203,7 +3203,7 @@
    (set_attr "simd_type" "simd_shift_imm,simd_shift,*")
    (set_attr "simd_mode" "<MODE>,<MODE>,*")
    (set_attr "v8type" "*,*,shift")
-   (set_attr "type" "*,*,shift")
+   (set_attr "type" "*,*,shift_reg")
    (set_attr "mode" "*,*,<MODE>")]
 )
 
@@ -3222,7 +3222,7 @@
    (set_attr "simd_type" "simd_shift_imm,simd_shift,*")
    (set_attr "simd_mode" "<MODE>,<MODE>,*")
    (set_attr "v8type" "*,*,shift")
-   (set_attr "type" "*,*,shift")
+   (set_attr "type" "*,*,shift_reg")
    (set_attr "mode" "*,*,<MODE>")]
 )
 
@@ -3267,7 +3267,7 @@
    (set_attr "simd_type" "simd_shift_imm,simd_shift,*")
    (set_attr "simd_mode" "<MODE>,<MODE>,*")
    (set_attr "v8type" "*,*,shift")
-   (set_attr "type" "*,*,shift")
+   (set_attr "type" "*,*,shift_reg")
    (set_attr "mode" "*,*,<MODE>")]
 )
 
@@ -3365,7 +3365,7 @@
   ""
   "ror\\t%<w>0, %<w>1, %<w>2"
   [(set_attr "v8type" "shift")
-   (set_attr "type" "shift")
+   (set_attr "type" "shift_reg")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -3378,7 +3378,7 @@
   ""
   "<shift>\\t%w0, %w1, %w2"
   [(set_attr "v8type" "shift")
-   (set_attr "type" "shift")
+   (set_attr "type" "shift_reg")
    (set_attr "mode" "SI")]
 )
 
@@ -3389,7 +3389,7 @@
   ""
   "lsl\\t%<w>0, %<w>1, %<w>2"
   [(set_attr "v8type" "shift")
-   (set_attr "type" "shift")
+   (set_attr "type" "shift_reg")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -3403,7 +3403,7 @@
   return "<bfshift>\t%w0, %w1, %2, %3";
 }
   [(set_attr "v8type" "bfm")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "bfm")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -3417,7 +3417,7 @@
    (UINTVAL (operands[3]) + UINTVAL (operands[4]) == GET_MODE_BITSIZE (<MODE>mode))"
   "extr\\t%<w>0, %<w>1, %<w>2, %4"
   [(set_attr "v8type" "shift")
-   (set_attr "type" "shift")
+   (set_attr "type" "shift_imm")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -3433,7 +3433,7 @@
    (UINTVAL (operands[3]) + UINTVAL (operands[4]) == 32)"
   "extr\\t%w0, %w1, %w2, %4"
   [(set_attr "v8type" "shift")
-   (set_attr "type" "shift")
+   (set_attr "type" "shift_imm")
    (set_attr "mode" "SI")]
 )
 
@@ -3447,7 +3447,7 @@
   return "ror\\t%<w>0, %<w>1, %3";
 }
   [(set_attr "v8type" "shift")
-   (set_attr "type" "shift")
+   (set_attr "type" "shift_imm")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -3463,7 +3463,7 @@
   return "ror\\t%w0, %w1, %3";
 }
   [(set_attr "v8type" "shift")
-   (set_attr "type" "shift")
+   (set_attr "type" "shift_imm")
    (set_attr "mode" "SI")]
 )
 
@@ -3478,7 +3478,7 @@
   return "<su>bfiz\t%<GPI:w>0, %<GPI:w>1, %2, %3";
 }
   [(set_attr "v8type" "bfm")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "bfm")
    (set_attr "mode" "<GPI:MODE>")]
 )
 
@@ -3493,7 +3493,7 @@
   return "ubfx\t%<GPI:w>0, %<GPI:w>1, %2, %3";
 }
   [(set_attr "v8type" "bfm")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "bfm")
    (set_attr "mode" "<GPI:MODE>")]
 )
 
@@ -3508,7 +3508,7 @@
   return "sbfx\\t%<GPI:w>0, %<GPI:w>1, %2, %3";
 }
   [(set_attr "v8type" "bfm")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "bfm")
    (set_attr "mode" "<GPI:MODE>")]
 )
 
@@ -3533,7 +3533,7 @@
   ""
   "<su>bfx\\t%<w>0, %<w>1, %3, %2"
   [(set_attr "v8type" "bfm")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "bfm")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -3578,7 +3578,7 @@
 	 > GET_MODE_BITSIZE (<MODE>mode)))"
   "bfi\\t%<w>0, %<w>3, %2, %1"
   [(set_attr "v8type" "bfm")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "bfm")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -3594,7 +3594,7 @@
 	 > GET_MODE_BITSIZE (<MODE>mode)))"
   "bfxil\\t%<w>0, %<w>2, %3, %1"
   [(set_attr "v8type" "bfm")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "bfm")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -3611,7 +3611,7 @@
   return "<su>bfiz\t%<GPI:w>0, %<GPI:w>1, %2, %3";
 }
   [(set_attr "v8type" "bfm")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "bfm")
    (set_attr "mode" "<GPI:MODE>")]
 )
 
@@ -3626,7 +3626,7 @@
    && (INTVAL (operands[3]) & ((1 << INTVAL (operands[2])) - 1)) == 0"
   "ubfiz\\t%<w>0, %<w>1, %2, %P3"
   [(set_attr "v8type" "bfm")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "bfm")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -3636,7 +3636,7 @@
   ""
   "rev\\t%<w>0, %<w>1"
   [(set_attr "v8type" "rev")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "rev")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -3646,7 +3646,7 @@
   ""
   "rev16\\t%w0, %w1"
   [(set_attr "v8type" "rev")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "rev")
    (set_attr "mode" "HI")]
 )
 
@@ -3657,7 +3657,7 @@
   ""
   "rev\\t%w0, %w1"
   [(set_attr "v8type" "rev")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "rev")
    (set_attr "mode" "SI")]
 )
 
@@ -4112,7 +4112,7 @@
   ""
   "add\\t%<w>0, %<w>1, :lo12:%a2"
   [(set_attr "v8type" "alu")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alu_reg")
    (set_attr "mode" "<MODE>")]
 )
 
@@ -4209,7 +4209,7 @@
   ""
   "add\\t%0, %1, #%G2\;add\\t%0, %0, #%L2"
   [(set_attr "v8type" "alu")
-   (set_attr "type" "arlo_reg")
+   (set_attr "type" "alu_reg")
    (set_attr "mode" "DI")
    (set_attr "length" "8")]
 )
diff --git a/gcc/config/arm/arm-fixed.md b/gcc/config/arm/arm-fixed.md
index dc8e7ac8c14..f17fa884e31 100644
--- a/gcc/config/arm/arm-fixed.md
+++ b/gcc/config/arm/arm-fixed.md
@@ -406,7 +406,7 @@
   [(set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no")
    (set_attr "shift" "1")
-   (set_attr "type" "arlo_shift")])
+   (set_attr "type" "alu_shift_imm")])
 
 (define_insn "arm_usatsihi"
   [(set (match_operand:HI 0 "s_register_operand" "=r")
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index db34b961016..cac98cc97aa 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -8664,8 +8664,14 @@ xscale_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost)
 	 instruction we depend on is another ALU instruction, then we may
 	 have to account for an additional stall.  */
       if (shift_opnum != 0
-	  && (attr_type == TYPE_ARLO_SHIFT
-	      || attr_type == TYPE_ARLO_SHIFT_REG
+	  && (attr_type == TYPE_ALU_SHIFT_IMM
+	      || attr_type == TYPE_ALUS_SHIFT_IMM
+	      || attr_type == TYPE_LOGIC_SHIFT_IMM
+	      || attr_type == TYPE_LOGICS_SHIFT_IMM
+	      || attr_type == TYPE_ALU_SHIFT_REG
+	      || attr_type == TYPE_ALUS_SHIFT_REG
+	      || attr_type == TYPE_LOGIC_SHIFT_REG
+	      || attr_type == TYPE_LOGICS_SHIFT_REG
 	      || attr_type == TYPE_MOV_SHIFT
 	      || attr_type == TYPE_MVN_SHIFT
 	      || attr_type == TYPE_MOV_SHIFT_REG
@@ -8952,9 +8958,17 @@ cortexa7_older_only (rtx insn)
 
   switch (get_attr_type (insn))
     {
-    case TYPE_ARLO_REG:
+    case TYPE_ALU_REG:
+    case TYPE_ALUS_REG:
+    case TYPE_LOGIC_REG:
+    case TYPE_LOGICS_REG:
+    case TYPE_ADC_REG:
+    case TYPE_ADCS_REG:
+    case TYPE_ADR:
+    case TYPE_BFM:
+    case TYPE_REV:
     case TYPE_MVN_REG:
-    case TYPE_SHIFT:
+    case TYPE_SHIFT_IMM:
     case TYPE_SHIFT_REG:
     case TYPE_LOAD_BYTE:
     case TYPE_LOAD1:
@@ -8999,7 +9013,10 @@ cortexa7_younger (FILE *file, int verbose, rtx insn)
 
   switch (get_attr_type (insn))
     {
-    case TYPE_ARLO_IMM:
+    case TYPE_ALU_IMM:
+    case TYPE_ALUS_IMM:
+    case TYPE_LOGIC_IMM:
+    case TYPE_LOGICS_IMM:
     case TYPE_EXTEND:
     case TYPE_MVN_IMM:
     case TYPE_MOV_IMM:
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 744f60607cb..4fb12aac35b 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -330,8 +330,12 @@
 ; than one on the main cpu execution unit.
 (define_attr "core_cycles" "single,multi"
   (if_then_else (eq_attr "type"
-    "arlo_imm, arlo_reg,\
-    extend, shift, arlo_shift, float, fdivd, fdivs,\
+    "adc_imm, adc_reg, adcs_imm, adcs_reg, adr, alu_ext, alu_imm, alu_reg,\
+    alu_shift_imm, alu_shift_reg, alus_ext, alus_imm, alus_reg,\
+    alus_shift_imm, alus_shift_reg, bfm, csel, rev, logic_imm, logic_reg,\
+    logic_shift_imm, logic_shift_reg, logics_imm, logics_reg,\
+    logics_shift_imm, logics_shift_reg, extend, shift_imm, float, fcsel,\
+    fdivd, fdivs,\
     wmmx_wor, wmmx_wxor, wmmx_wand, wmmx_wandn, wmmx_wmov, wmmx_tmcrr,\
     wmmx_tmrrc, wmmx_wldr, wmmx_wstr, wmmx_tmcr, wmmx_tmrc, wmmx_wadd,\
     wmmx_wsub, wmmx_wmul, wmmx_wmac, wmmx_wavg2, wmmx_tinsr, wmmx_textrm,\
@@ -616,8 +620,8 @@
    (set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no,no,no,no,no,no,no")
    (set_attr "arch" "t2,t2,t2,t2,*,*,*,t2,t2,*,*,a,t2,t2,*")
    (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
-		      (const_string "arlo_imm")
-		      (const_string "arlo_reg")))
+		      (const_string "alu_imm")
+		      (const_string "alu_reg")))
  ]
 )
 
@@ -698,7 +702,7 @@
    sub%.\\t%0, %1, #%n2
    add%.\\t%0, %1, %2"
   [(set_attr "conds" "set")
-   (set_attr "type" "arlo_imm,arlo_imm,*")]
+   (set_attr "type" "alus_imm,alus_imm,*")]
 )
 
 (define_insn "*addsi3_compare0_scratch"
@@ -714,7 +718,7 @@
    cmn%?\\t%0, %1"
   [(set_attr "conds" "set")
    (set_attr "predicable" "yes")
-   (set_attr "type" "arlo_imm,arlo_imm,*")
+   (set_attr "type" "alus_imm,alus_imm,*")
    ]
 )
 
@@ -804,7 +808,7 @@
    sub%.\\t%0, %1, #%n2
    add%.\\t%0, %1, %2"
   [(set_attr "conds" "set")
-   (set_attr "type"  "arlo_imm,arlo_imm,*")]
+   (set_attr "type"  "alus_imm,alus_imm,alus_reg")]
 )
 
 (define_insn "*addsi3_compare_op2"
@@ -821,7 +825,7 @@
    add%.\\t%0, %1, %2
    sub%.\\t%0, %1, #%n2"
   [(set_attr "conds" "set")
-   (set_attr "type" "arlo_imm,arlo_imm,*")]
+   (set_attr "type" "alus_imm,alus_imm,alus_reg")]
 )
 
 (define_insn "*compare_addsi2_op0"
@@ -842,7 +846,7 @@
    (set_attr "arch" "t2,t2,*,*,*")
    (set_attr "predicable_short_it" "yes,yes,no,no,no")
    (set_attr "length" "2,2,4,4,4")
-   (set_attr "type" "arlo_imm,*,arlo_imm,arlo_imm,*")]
+   (set_attr "type" "alus_imm,alus_reg,alus_imm,alus_imm,alus_reg")]
 )
 
 (define_insn "*compare_addsi2_op1"
@@ -863,8 +867,7 @@
    (set_attr "arch" "t2,t2,*,*,*")
    (set_attr "predicable_short_it" "yes,yes,no,no,no")
    (set_attr "length" "2,2,4,4,4")
-   (set_attr "type"
-      "arlo_imm,*,arlo_imm,arlo_imm,*")]
+   (set_attr "type" "alus_imm,alus_reg,alus_imm,alus_imm,alus_reg")]
  )
 
 (define_insn "*addsi3_carryin_<optab>"
@@ -915,8 +918,8 @@
    (set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no")
    (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
-		      (const_string "arlo_shift")
-		      (const_string "arlo_shift_reg")))]
+		      (const_string "alu_shift_imm")
+		      (const_string "alu_shift_reg")))]
 )
 
 (define_insn "*addsi3_carryin_clobercc_<optab>"
@@ -994,8 +997,8 @@
   [(set_attr "conds" "use")
    (set_attr "predicable" "yes")
    (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
-		      (const_string "arlo_shift")
-                     (const_string "arlo_shift_reg")))]
+		      (const_string "alu_shift_imm")
+                     (const_string "alu_shift_reg")))]
 )
 
 (define_insn "*rsbsi3_carryin_shift"
@@ -1011,8 +1014,8 @@
   [(set_attr "conds" "use")
    (set_attr "predicable" "yes")
    (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
-		      (const_string "arlo_shift")
-		      (const_string "arlo_shift_reg")))]
+		      (const_string "alu_shift_imm")
+		      (const_string "alu_shift_reg")))]
 )
 
 ; transform ((x << y) - 1) to ~(~(x-1) << y)  Where X is a constant.
@@ -1285,7 +1288,7 @@
    (set_attr "arch" "t2,t2,t2,t2,*,*,*,*,*")
    (set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no")
-   (set_attr "type"  "*,*,*,*,arlo_imm,arlo_imm,*,*,arlo_imm")]
+   (set_attr "type"  "*,*,*,*,alu_imm,alu_imm,*,*,alu_imm")]
 )
 
 (define_peephole2
@@ -1315,7 +1318,7 @@
    sub%.\\t%0, %1, %2
    rsb%.\\t%0, %2, %1"
   [(set_attr "conds" "set")
-   (set_attr "type"  "arlo_imm,*,*")]
+   (set_attr "type"  "alus_imm,alus_reg,alus_reg")]
 )
 
 (define_insn "subsi3_compare"
@@ -1330,7 +1333,7 @@
    sub%.\\t%0, %1, %2
    rsb%.\\t%0, %2, %1"
   [(set_attr "conds" "set")
-   (set_attr "type" "arlo_imm,*,*")]
+   (set_attr "type" "alus_imm,alus_reg,alus_reg")]
 )
 
 (define_expand "subsf3"
@@ -2279,8 +2282,7 @@
   [(set_attr "length" "4,4,4,4,16")
    (set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no,yes,no,no,no")
-   (set_attr "type"
-     "arlo_imm,arlo_imm,*,*,arlo_imm")]
+   (set_attr "type" "logic_imm,logic_imm,logic_reg,logic_reg,logic_imm")]
 )
 
 (define_insn "*thumb1_andsi3_insn"
@@ -2290,7 +2292,7 @@
   "TARGET_THUMB1"
   "and\\t%0, %2"
   [(set_attr "length" "2")
-   (set_attr "type"  "arlo_imm")
+   (set_attr "type"  "logic_imm")
    (set_attr "conds" "set")])
 
 (define_insn "*andsi3_compare0"
@@ -2307,7 +2309,7 @@
    bic%.\\t%0, %1, #%B2
    and%.\\t%0, %1, %2"
   [(set_attr "conds" "set")
-   (set_attr "type" "arlo_imm,arlo_imm,*")]
+   (set_attr "type" "logics_imm,logics_imm,logics_reg")]
 )
 
 (define_insn "*andsi3_compare0_scratch"
@@ -2323,7 +2325,7 @@
    bic%.\\t%2, %0, #%B1
    tst%?\\t%0, %1"
   [(set_attr "conds" "set")
-   (set_attr "type"  "arlo_imm,arlo_imm,*")]
+   (set_attr "type"  "logics_imm,logics_imm,logics_reg")]
 )
 
 (define_insn "*zeroextractsi_compare0_scratch"
@@ -2347,7 +2349,7 @@
   [(set_attr "conds" "set")
    (set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no")
-   (set_attr "type" "arlo_imm")]
+   (set_attr "type" "logics_imm")]
 )
 
 (define_insn_and_split "*ne_zeroextractsi"
@@ -2775,7 +2777,8 @@
   "bfc%?\t%0, %2, %1"
   [(set_attr "length" "4")
    (set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "no")]
+   (set_attr "predicable_short_it" "no")
+   (set_attr "type" "bfm")]
 )
 
 (define_insn "insv_t2"
@@ -2787,7 +2790,8 @@
   "bfi%?\t%0, %3, %2, %1"
   [(set_attr "length" "4")
    (set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "no")]
+   (set_attr "predicable_short_it" "no")
+   (set_attr "type" "bfm")]
 )
 
 ; constants for op 2 will never be given to these patterns.
@@ -2897,8 +2901,8 @@
   [(set_attr "predicable" "yes")
    (set_attr "shift" "2")
    (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
-		      (const_string "arlo_shift")
-		      (const_string "arlo_shift_reg")))]
+		      (const_string "logic_shift_imm")
+		      (const_string "logic_shift_reg")))]
 )
 
 (define_insn "*andsi_notsi_si_compare0"
@@ -2911,7 +2915,8 @@
 	(and:SI (not:SI (match_dup 2)) (match_dup 1)))]
   "TARGET_32BIT"
   "bic%.\\t%0, %1, %2"
-  [(set_attr "conds" "set")]
+  [(set_attr "conds" "set")
+   (set_attr "type" "logics_shift_reg")]
 )
 
 (define_insn "*andsi_notsi_si_compare0_scratch"
@@ -2923,7 +2928,8 @@
    (clobber (match_scratch:SI 0 "=r"))]
   "TARGET_32BIT"
   "bic%.\\t%0, %1, %2"
-  [(set_attr "conds" "set")]
+  [(set_attr "conds" "set")
+   (set_attr "type" "logics_shift_reg")]
 )
 
 (define_expand "iordi3"
@@ -3057,7 +3063,7 @@
    (set_attr "arch" "32,t2,t2,32,32")
    (set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no,yes,no,no,no")
-   (set_attr "type" "arlo_imm,*,arlo_imm,*,*")]
+   (set_attr "type" "logic_imm,logic_reg,logic_imm,logic_reg,logic_reg")]
 )
 
 (define_insn "*thumb1_iorsi3_insn"
@@ -3092,7 +3098,7 @@
   "TARGET_32BIT"
   "orr%.\\t%0, %1, %2"
   [(set_attr "conds" "set")
-   (set_attr "type" "arlo_imm,*")]
+   (set_attr "type" "logics_imm,logics_reg")]
 )
 
 (define_insn "*iorsi3_compare0_scratch"
@@ -3104,7 +3110,7 @@
   "TARGET_32BIT"
   "orr%.\\t%0, %1, %2"
   [(set_attr "conds" "set")
-   (set_attr "type" "arlo_imm,*")]
+   (set_attr "type" "logics_imm,logics_reg")]
 )
 
 (define_expand "xordi3"
@@ -3230,7 +3236,7 @@
   [(set_attr "length" "4,4,4,16")
    (set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no,yes,no,no")
-   (set_attr "type"  "arlo_imm,*,*,*")]
+   (set_attr "type"  "logic_imm,logic_reg,logic_reg,logic_reg")]
 )
 
 (define_insn "*thumb1_xorsi3_insn"
@@ -3241,7 +3247,7 @@
   "eor\\t%0, %2"
   [(set_attr "length" "2")
    (set_attr "conds" "set")
-   (set_attr "type" "arlo_imm")]
+   (set_attr "type" "logics_reg")]
 )
 
 (define_insn "*xorsi3_compare0"
@@ -3254,7 +3260,7 @@
   "TARGET_32BIT"
   "eor%.\\t%0, %1, %2"
   [(set_attr "conds" "set")
-   (set_attr "type" "arlo_imm,*")]
+   (set_attr "type" "logics_imm,logics_reg")]
 )
 
 (define_insn "*xorsi3_compare0_scratch"
@@ -3265,7 +3271,7 @@
   "TARGET_32BIT"
   "teq%?\\t%0, %1"
   [(set_attr "conds" "set")
-   (set_attr "type" "arlo_imm,*")]
+   (set_attr "type" "logics_imm,logics_reg")]
 )
 
 ; By splitting (IOR (AND (NOT A) (NOT B)) C) as D = AND (IOR A B) (NOT C), 
@@ -3754,7 +3760,7 @@
   [(set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no")
    (set_attr "shift" "3")
-   (set_attr "type" "arlo_shift")])
+   (set_attr "type" "logic_shift_reg")])
 
 ;; Shift and rotation insns
 
@@ -3857,7 +3863,7 @@
   "TARGET_THUMB1"
   "lsl\\t%0, %1, %2"
   [(set_attr "length" "2")
-   (set_attr "type" "shift,shift_reg")
+   (set_attr "type" "shift_imm,shift_reg")
    (set_attr "conds" "set")])
 
 (define_expand "ashrdi3"
@@ -3962,7 +3968,7 @@
   "TARGET_THUMB1"
   "asr\\t%0, %1, %2"
   [(set_attr "length" "2")
-   (set_attr "type" "shift,shift_reg")
+   (set_attr "type" "shift_imm,shift_reg")
    (set_attr "conds" "set")])
 
 (define_expand "lshrdi3"
@@ -4059,7 +4065,7 @@
   "TARGET_THUMB1"
   "lsr\\t%0, %1, %2"
   [(set_attr "length" "2")
-   (set_attr "type" "shift,shift_reg")
+   (set_attr "type" "shift_imm,shift_reg")
    (set_attr "conds" "set")])
 
 (define_expand "rotlsi3"
@@ -4121,7 +4127,7 @@
    (set_attr "predicable_short_it" "yes,no,no")
    (set_attr "length" "4")
    (set_attr "shift" "1")
-   (set_attr "type" "arlo_shift_reg,arlo_shift,arlo_shift_reg")]
+   (set_attr "type" "alu_shift_reg,alu_shift_imm,alu_shift_reg")]
 )
 
 (define_insn "*shiftsi3_compare"
@@ -4136,7 +4142,7 @@
   "* return arm_output_shift(operands, 1);"
   [(set_attr "conds" "set")
    (set_attr "shift" "1")
-   (set_attr "type"  "arlo_shift,arlo_shift_reg")]
+   (set_attr "type"  "alus_shift_imm,alus_shift_reg")]
 )
 
 (define_insn "*shiftsi3_compare0"
@@ -4151,7 +4157,7 @@
   "* return arm_output_shift(operands, 1);"
   [(set_attr "conds" "set")
    (set_attr "shift" "1")
-   (set_attr "type" "arlo_shift,arlo_shift_reg")]
+   (set_attr "type" "alus_shift_imm,alus_shift_reg")]
 )
 
 (define_insn "*shiftsi3_compare0_scratch"
@@ -4165,7 +4171,7 @@
   "* return arm_output_shift(operands, 1);"
   [(set_attr "conds" "set")
    (set_attr "shift" "1")
-   (set_attr "type" "shift,shift_reg")]
+   (set_attr "type" "shift_imm,shift_reg")]
 )
 
 (define_insn "*not_shiftsi"
@@ -4507,7 +4513,8 @@
   "sbfx%?\t%0, %1, %3, %2"
   [(set_attr "length" "4")
    (set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "no")]
+   (set_attr "predicable_short_it" "no")
+   (set_attr "type" "bfm")]
 )
 
 (define_insn "extzv_t2"
@@ -4519,7 +4526,8 @@
   "ubfx%?\t%0, %1, %3, %2"
   [(set_attr "length" "4")
    (set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "no")]
+   (set_attr "predicable_short_it" "no")
+   (set_attr "type" "bfm")]
 )
 
 
@@ -5241,7 +5249,7 @@
   "@
    #
    ldr%(h%)\\t%0, %1"
-  [(set_attr "type" "arlo_shift,load_byte")
+  [(set_attr "type" "alu_shift_reg,load_byte")
    (set_attr "predicable" "yes")]
 )
 
@@ -5262,7 +5270,7 @@
 		 (match_operand:SI 2 "s_register_operand" "r")))]
   "TARGET_INT_SIMD"
   "uxtah%?\\t%0, %2, %1"
-  [(set_attr "type" "arlo_shift")
+  [(set_attr "type" "alu_shift_reg")
    (set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no")]
 )
@@ -5312,7 +5320,7 @@
    #
    ldrb\\t%0, %1"
   [(set_attr "length" "4,2")
-   (set_attr "type" "arlo_shift,load_byte")
+   (set_attr "type" "alu_shift_reg,load_byte")
    (set_attr "pool_range" "*,32")]
 )
 
@@ -5335,7 +5343,7 @@
    #
    ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
   [(set_attr "length" "8,4")
-   (set_attr "type" "arlo_shift,load_byte")
+   (set_attr "type" "alu_shift_reg,load_byte")
    (set_attr "predicable" "yes")]
 )
 
@@ -5358,7 +5366,7 @@
   "uxtab%?\\t%0, %2, %1"
   [(set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no")
-   (set_attr "type" "arlo_shift")]
+   (set_attr "type" "alu_shift_reg")]
 )
 
 (define_split
@@ -5580,7 +5588,7 @@
    #
    ldr%(sh%)\\t%0, %1"
   [(set_attr "length" "8,4")
-   (set_attr "type" "arlo_shift,load_byte")
+   (set_attr "type" "alu_shift_reg,load_byte")
    (set_attr "predicable" "yes")
    (set_attr "pool_range" "*,256")
    (set_attr "neg_pool_range" "*,244")]
@@ -5681,7 +5689,7 @@
    #
    ldr%(sb%)\\t%0, %1"
   [(set_attr "length" "8,4")
-   (set_attr "type" "arlo_shift,load_byte")
+   (set_attr "type" "alu_shift_reg,load_byte")
    (set_attr "predicable" "yes")
    (set_attr "pool_range" "*,256")
    (set_attr "neg_pool_range" "*,244")]
@@ -5707,7 +5715,7 @@
 		 (match_operand:SI 2 "s_register_operand" "r")))]
   "TARGET_INT_SIMD"
   "sxtab%?\\t%0, %2, %1"
-  [(set_attr "type" "arlo_shift")
+  [(set_attr "type" "alu_shift_reg")
    (set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no")]
 )
@@ -6484,7 +6492,7 @@
    cmp%?\\t%0, #0
    sub%.\\t%0, %1, #0"
   [(set_attr "conds" "set")
-   (set_attr "type" "arlo_imm,arlo_imm")]
+   (set_attr "type" "alus_imm,alus_imm")]
 )
 
 ;; Subroutine to store a half word from a register into memory.
@@ -7078,7 +7086,7 @@
    mov\\t%0, %1
    mov\\t%0, %1"
   [(set_attr "length" "2")
-   (set_attr "type" "arlo_imm,load1,store1,mov_reg,mov_imm,mov_imm")
+   (set_attr "type" "alu_imm,load1,store1,mov_reg,mov_imm,mov_imm")
    (set_attr "pool_range" "*,32,*,*,*,*")
    (set_attr "conds" "clob,nocond,nocond,nocond,nocond,clob")])
 
@@ -8164,34 +8172,34 @@
    (set_attr "arch" "t2,t2,any,any")
    (set_attr "length" "2,2,4,4")
    (set_attr "predicable" "yes")
-   (set_attr "type" "*,*,*,arlo_imm")]
+   (set_attr "type" "alus_reg,alus_reg,alus_reg,alus_imm")]
 )
 
 (define_insn "*cmpsi_shiftsi"
   [(set (reg:CC CC_REGNUM)
-	(compare:CC (match_operand:SI   0 "s_register_operand" "r,r")
+	(compare:CC (match_operand:SI   0 "s_register_operand" "r,r,r")
 		    (match_operator:SI  3 "shift_operator"
-		     [(match_operand:SI 1 "s_register_operand" "r,r")
-		      (match_operand:SI 2 "shift_amount_operand" "M,rM")])))]
+		     [(match_operand:SI 1 "s_register_operand" "r,r,r")
+		      (match_operand:SI 2 "shift_amount_operand" "M,r,M")])))]
   "TARGET_32BIT"
   "cmp%?\\t%0, %1%S3"
   [(set_attr "conds" "set")
    (set_attr "shift" "1")
-   (set_attr "arch" "32,a")
-   (set_attr "type" "arlo_shift,arlo_shift_reg")])
+   (set_attr "arch" "32,a,a")
+   (set_attr "type" "alus_shift_imm,alu_shift_reg,alus_shift_imm")])
 
 (define_insn "*cmpsi_shiftsi_swp"
   [(set (reg:CC_SWP CC_REGNUM)
 	(compare:CC_SWP (match_operator:SI 3 "shift_operator"
-			 [(match_operand:SI 1 "s_register_operand" "r,r")
-			  (match_operand:SI 2 "shift_amount_operand" "M,rM")])
-			(match_operand:SI 0 "s_register_operand" "r,r")))]
+			 [(match_operand:SI 1 "s_register_operand" "r,r,r")
+			  (match_operand:SI 2 "shift_amount_operand" "M,r,M")])
+			(match_operand:SI 0 "s_register_operand" "r,r,r")))]
   "TARGET_32BIT"
   "cmp%?\\t%0, %1%S3"
   [(set_attr "conds" "set")
    (set_attr "shift" "1")
-   (set_attr "arch" "32,a")
-   (set_attr "type" "arlo_shift,arlo_shift_reg")])
+   (set_attr "arch" "32,a,a")
+   (set_attr "type" "alus_shift_imm,alu_shift_reg,alus_shift_imm")])
 
 (define_insn "*arm_cmpsi_negshiftsi_si"
   [(set (reg:CC_Z CC_REGNUM)
@@ -8204,8 +8212,8 @@
   "cmn%?\\t%0, %2%S1"
   [(set_attr "conds" "set")
    (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
-				    (const_string "arlo_shift")
-				    (const_string "arlo_shift_reg")))
+				    (const_string "alus_shift_imm")
+				    (const_string "alus_shift_reg")))
    (set_attr "predicable" "yes")]
 )
 
@@ -9747,7 +9755,7 @@
 			  (if_then_else
 			   (match_operand:SI 3 "mult_operator" "")
 			   (const_string "no") (const_string "yes"))])
-   (set_attr "type" "arlo_shift,arlo_shift,arlo_shift,arlo_shift_reg")])
+   (set_attr "type" "alu_shift_imm,alu_shift_imm,alu_shift_imm,alu_shift_reg")])
 
 (define_split
   [(set (match_operand:SI 0 "s_register_operand" "")
@@ -9784,7 +9792,7 @@
   [(set_attr "conds" "set")
    (set_attr "shift" "4")
    (set_attr "arch" "32,a")
-   (set_attr "type" "arlo_shift,arlo_shift_reg")])
+   (set_attr "type" "alus_shift_imm,alus_shift_reg")])
 
 (define_insn "*arith_shiftsi_compare0_scratch"
   [(set (reg:CC_NOOV CC_REGNUM)
@@ -9801,7 +9809,7 @@
   [(set_attr "conds" "set")
    (set_attr "shift" "4")
    (set_attr "arch" "32,a")
-   (set_attr "type" "arlo_shift,arlo_shift_reg")])
+   (set_attr "type" "alus_shift_imm,alus_shift_reg")])
 
 (define_insn "*sub_shiftsi"
   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
@@ -9814,41 +9822,41 @@
   [(set_attr "predicable" "yes")
    (set_attr "shift" "3")
    (set_attr "arch" "32,a")
-   (set_attr "type" "arlo_shift,arlo_shift_reg")])
+   (set_attr "type" "alus_shift_imm,alus_shift_reg")])
 
 (define_insn "*sub_shiftsi_compare0"
   [(set (reg:CC_NOOV CC_REGNUM)
 	(compare:CC_NOOV
-	 (minus:SI (match_operand:SI 1 "s_register_operand" "r,r")
+	 (minus:SI (match_operand:SI 1 "s_register_operand" "r,r,r")
 		   (match_operator:SI 2 "shift_operator"
-		    [(match_operand:SI 3 "s_register_operand" "r,r")
-		     (match_operand:SI 4 "shift_amount_operand" "M,rM")]))
+		    [(match_operand:SI 3 "s_register_operand" "r,r,r")
+		     (match_operand:SI 4 "shift_amount_operand" "M,r,M")]))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "s_register_operand" "=r,r")
+   (set (match_operand:SI 0 "s_register_operand" "=r,r,r")
 	(minus:SI (match_dup 1)
 		  (match_op_dup 2 [(match_dup 3) (match_dup 4)])))]
   "TARGET_32BIT"
   "sub%.\\t%0, %1, %3%S2"
   [(set_attr "conds" "set")
    (set_attr "shift" "3")
-   (set_attr "arch" "32,a")
-   (set_attr "type" "arlo_shift,arlo_shift_reg")])
+   (set_attr "arch" "32,a,a")
+   (set_attr "type" "alus_shift_imm,alus_shift_reg,alus_shift_imm")])
 
 (define_insn "*sub_shiftsi_compare0_scratch"
   [(set (reg:CC_NOOV CC_REGNUM)
 	(compare:CC_NOOV
-	 (minus:SI (match_operand:SI 1 "s_register_operand" "r,r")
+	 (minus:SI (match_operand:SI 1 "s_register_operand" "r,r,r")
 		   (match_operator:SI 2 "shift_operator"
-		    [(match_operand:SI 3 "s_register_operand" "r,r")
-		     (match_operand:SI 4 "shift_amount_operand" "M,rM")]))
+		    [(match_operand:SI 3 "s_register_operand" "r,r,r")
+		     (match_operand:SI 4 "shift_amount_operand" "M,r,M")]))
 	 (const_int 0)))
-   (clobber (match_scratch:SI 0 "=r,r"))]
+   (clobber (match_scratch:SI 0 "=r,r,r"))]
   "TARGET_32BIT"
   "sub%.\\t%0, %1, %3%S2"
   [(set_attr "conds" "set")
    (set_attr "shift" "3")
-   (set_attr "arch" "32,a")
-   (set_attr "type" "arlo_shift,arlo_shift_reg")])
+   (set_attr "arch" "32,a,a")
+   (set_attr "type" "alus_shift_imm,alus_shift_reg,alus_shift_imm")])
 
 
 (define_insn_and_split "*and_scc"
@@ -10900,9 +10908,9 @@
    (set_attr "length" "4,4,8,8")
    (set_attr_alternative "type"
                          [(if_then_else (match_operand 3 "const_int_operand" "")
-                                        (const_string "arlo_imm" )
+                                        (const_string "alu_imm" )
                                         (const_string "*"))
-                          (const_string "arlo_imm")
+                          (const_string "alu_imm")
                           (const_string "*")
                           (const_string "*")])]
 )
@@ -10942,9 +10950,9 @@
    (set_attr "length" "4,4,8,8")
    (set_attr_alternative "type"
                          [(if_then_else (match_operand 3 "const_int_operand" "")
-                                        (const_string "arlo_imm" )
+                                        (const_string "alu_imm" )
                                         (const_string "*"))
-                          (const_string "arlo_imm")
+                          (const_string "alu_imm")
                           (const_string "*")
                           (const_string "*")])]
 )
diff --git a/gcc/config/arm/arm1020e.md b/gcc/config/arm/arm1020e.md
index 3a5e08fb7e5..ce89f1db02a 100644
--- a/gcc/config/arm/arm1020e.md
+++ b/gcc/config/arm/arm1020e.md
@@ -66,14 +66,20 @@
 ;; ALU operations with no shifted operand
 (define_insn_reservation "1020alu_op" 1 
  (and (eq_attr "tune" "arm1020e,arm1022e")
-      (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
+      (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+                       alu_reg,alus_reg,logic_reg,logics_reg,\
+                       adc_imm,adcs_imm,adc_reg,adcs_reg,\
+                       adr,bfm,rev,\
+                       shift_imm,shift_reg,\
                        mov_imm,mov_reg,mvn_imm,mvn_reg"))
  "1020a_e,1020a_m,1020a_w")
 
 ;; ALU operations with a shift-by-constant operand
 (define_insn_reservation "1020alu_shift_op" 1 
  (and (eq_attr "tune" "arm1020e,arm1022e")
-      (eq_attr "type" "extend,arlo_shift,mov_shift,mvn_shift"))
+      (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
+                       logic_shift_imm,logics_shift_imm,\
+                       extend,mov_shift,mvn_shift"))
  "1020a_e,1020a_m,1020a_w")
 
 ;; ALU operations with a shift-by-register operand
@@ -82,7 +88,9 @@
 ;; the execute stage.
 (define_insn_reservation "1020alu_shift_reg_op" 2 
  (and (eq_attr "tune" "arm1020e,arm1022e")
-      (eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg"))
+      (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
+                       logic_shift_reg,logics_shift_reg,\
+                       mov_shift_reg,mvn_shift_reg"))
  "1020a_e*2,1020a_m,1020a_w")
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
diff --git a/gcc/config/arm/arm1026ejs.md b/gcc/config/arm/arm1026ejs.md
index 9112122d67b..6f4a8fa76e1 100644
--- a/gcc/config/arm/arm1026ejs.md
+++ b/gcc/config/arm/arm1026ejs.md
@@ -66,14 +66,20 @@
 ;; ALU operations with no shifted operand
 (define_insn_reservation "alu_op" 1 
  (and (eq_attr "tune" "arm1026ejs")
-      (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
+      (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+                       alu_reg,alus_reg,logic_reg,logics_reg,\
+                       adc_imm,adcs_imm,adc_reg,adcs_reg,\
+                       adr,bfm,rev,\
+                       shift_imm,shift_reg,\
                        mov_imm,mov_reg,mvn_imm,mvn_reg"))
  "a_e,a_m,a_w")
 
 ;; ALU operations with a shift-by-constant operand
 (define_insn_reservation "alu_shift_op" 1 
  (and (eq_attr "tune" "arm1026ejs")
-      (eq_attr "type" "extend,arlo_shift,mov_shift,mvn_shift"))
+      (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
+                       logic_shift_imm,logics_shift_imm,\
+                       extend,mov_shift,mvn_shift"))
  "a_e,a_m,a_w")
 
 ;; ALU operations with a shift-by-register operand
@@ -82,7 +88,9 @@
 ;; the execute stage.
 (define_insn_reservation "alu_shift_reg_op" 2 
  (and (eq_attr "tune" "arm1026ejs")
-      (eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg"))
+      (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
+                       logic_shift_reg,logics_shift_reg,\
+                       mov_shift_reg,mvn_shift_reg"))
  "a_e*2,a_m,a_w")
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
diff --git a/gcc/config/arm/arm1136jfs.md b/gcc/config/arm/arm1136jfs.md
index f83b9d14f2b..7d39f12d08a 100644
--- a/gcc/config/arm/arm1136jfs.md
+++ b/gcc/config/arm/arm1136jfs.md
@@ -75,14 +75,20 @@
 ;; ALU operations with no shifted operand
 (define_insn_reservation "11_alu_op" 2
  (and (eq_attr "tune" "arm1136js,arm1136jfs")
-      (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
+      (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+                       alu_reg,alus_reg,logic_reg,logics_reg,\
+                       adc_imm,adcs_imm,adc_reg,adcs_reg,\
+                       adr,bfm,rev,\
+                       shift_imm,shift_reg,\
                        mov_imm,mov_reg,mvn_imm,mvn_reg"))
  "e_1,e_2,e_3,e_wb")
 
 ;; ALU operations with a shift-by-constant operand
 (define_insn_reservation "11_alu_shift_op" 2
  (and (eq_attr "tune" "arm1136js,arm1136jfs")
-      (eq_attr "type" "extend,arlo_shift,mov_shift,mvn_shift"))
+      (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
+                       logic_shift_imm,logics_shift_imm,\
+                       extend,mov_shift,mvn_shift"))
  "e_1,e_2,e_3,e_wb")
 
 ;; ALU operations with a shift-by-register operand
@@ -91,7 +97,9 @@
 ;; the shift stage.
 (define_insn_reservation "11_alu_shift_reg_op" 3
  (and (eq_attr "tune" "arm1136js,arm1136jfs")
-      (eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg"))
+      (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
+                       logic_shift_reg,logics_shift_reg,\
+                       mov_shift_reg,mvn_shift_reg"))
  "e_1*2,e_2,e_3,e_wb")
 
 ;; alu_ops can start sooner, if there is no shifter dependency
diff --git a/gcc/config/arm/arm926ejs.md b/gcc/config/arm/arm926ejs.md
index 8c38e86ce66..7c2d52e8073 100644
--- a/gcc/config/arm/arm926ejs.md
+++ b/gcc/config/arm/arm926ejs.md
@@ -58,7 +58,13 @@
 ;; ALU operations with no shifted operand
 (define_insn_reservation "9_alu_op" 1 
  (and (eq_attr "tune" "arm926ejs")
-      (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,extend,arlo_shift,\
+      (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+                       alu_reg,alus_reg,logic_reg,logics_reg,\
+                       adc_imm,adcs_imm,adc_reg,adcs_reg,\
+                       adr,bfm,rev,\
+                       alu_shift_imm,alus_shift_imm,\
+                       logic_shift_imm,logics_shift_imm,\
+                       shift_imm,shift_reg,extend,\
                        mov_imm,mov_reg,mov_shift,\
                        mvn_imm,mvn_reg,mvn_shift"))
  "e,m,w")
@@ -69,7 +75,9 @@
 ;; the execute stage.
 (define_insn_reservation "9_alu_shift_reg_op" 2 
  (and (eq_attr "tune" "arm926ejs")
-      (eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg"))
+      (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
+                       logic_shift_reg,logics_shift_reg,\
+                       mov_shift_reg,mvn_shift_reg"))
  "e*2,m,w")
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
diff --git a/gcc/config/arm/cortex-a15.md b/gcc/config/arm/cortex-a15.md
index a816e29a3cb..382a3dc73d4 100644
--- a/gcc/config/arm/cortex-a15.md
+++ b/gcc/config/arm/cortex-a15.md
@@ -61,22 +61,31 @@
 ;; Simple ALU without shift
 (define_insn_reservation "cortex_a15_alu" 2
   (and (eq_attr "tune" "cortexa15")
-       (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
-                             mov_imm,mov_reg,\
-                             mvn_imm,mvn_reg"))
+       (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+                        alu_reg,alus_reg,logic_reg,logics_reg,\
+                        adc_imm,adcs_imm,adc_reg,adcs_reg,\
+                        adr,bfm,rev,\
+                        shift_imm,shift_reg,\
+                        mov_imm,mov_reg,\
+                        mvn_imm,mvn_reg"))
   "ca15_issue1,(ca15_sx1,ca15_sx1_alu)|(ca15_sx2,ca15_sx2_alu)")
 
 ;; ALU ops with immediate shift
 (define_insn_reservation "cortex_a15_alu_shift" 3
   (and (eq_attr "tune" "cortexa15")
-       (eq_attr "type" "extend,arlo_shift,,mov_shift,mvn_shift"))
+       (eq_attr "type" "extend,\
+                        alu_shift_imm,alus_shift_imm,\
+                        logic_shift_imm,logics_shift_imm,\
+                        mov_shift,mvn_shift"))
   "ca15_issue1,(ca15_sx1,ca15_sx1+ca15_sx1_shf,ca15_sx1_alu)\
 	       |(ca15_sx2,ca15_sx2+ca15_sx2_shf,ca15_sx2_alu)")
 
 ;; ALU ops with register controlled shift
 (define_insn_reservation "cortex_a15_alu_shift_reg" 3
   (and (eq_attr "tune" "cortexa15")
-       (eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg"))
+       (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
+                        logic_shift_reg,logics_shift_reg,\
+                        mov_shift_reg,mvn_shift_reg"))
   "(ca15_issue2,ca15_sx1+ca15_sx2,ca15_sx1_shf,ca15_sx2_alu)\
    |(ca15_issue1,(ca15_issue1+ca15_sx2,ca15_sx1+ca15_sx2_shf)\
    |(ca15_issue1+ca15_sx1,ca15_sx1+ca15_sx1_shf),ca15_sx1_alu)")
diff --git a/gcc/config/arm/cortex-a5.md b/gcc/config/arm/cortex-a5.md
index 67f641c174b..19738e6d56f 100644
--- a/gcc/config/arm/cortex-a5.md
+++ b/gcc/config/arm/cortex-a5.md
@@ -58,13 +58,21 @@
 
 (define_insn_reservation "cortex_a5_alu" 2
   (and (eq_attr "tune" "cortexa5")
-       (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
+       (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+                        alu_reg,alus_reg,logic_reg,logics_reg,\
+                        adc_imm,adcs_imm,adc_reg,adcs_reg,\
+                        adr,bfm,rev,\
+                        shift_imm,shift_reg,\
                         mov_imm,mov_reg,mvn_imm,mvn_reg"))
   "cortex_a5_ex1")
 
 (define_insn_reservation "cortex_a5_alu_shift" 2
   (and (eq_attr "tune" "cortexa5")
-       (eq_attr "type" "extend,arlo_shift,arlo_shift_reg,\
+       (eq_attr "type" "extend,\
+                        alu_shift_imm,alus_shift_imm,\
+                        logic_shift_imm,logics_shift_imm,\
+                        alu_shift_reg,alus_shift_reg,\
+                        logic_shift_reg,logics_shift_reg,\
                         mov_shift,mov_shift_reg,\
                         mvn_shift,mvn_shift_reg"))
   "cortex_a5_ex1")
diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md
index 5bb8ab02a33..9331eceb2ed 100644
--- a/gcc/config/arm/cortex-a53.md
+++ b/gcc/config/arm/cortex-a53.md
@@ -67,13 +67,20 @@
 
 (define_insn_reservation "cortex_a53_alu" 2
   (and (eq_attr "tune" "cortexa53")
-       (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
+       (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+                        alu_reg,alus_reg,logic_reg,logics_reg,\
+                        adc_imm,adcs_imm,adc_reg,adcs_reg,\
+                        adr,bfm,csel,rev,\
+                        shift_imm,shift_reg,\
                         mov_imm,mov_reg,mvn_imm,mvn_reg"))
   "cortex_a53_slot_any")
 
 (define_insn_reservation "cortex_a53_alu_shift" 2
   (and (eq_attr "tune" "cortexa53")
-       (eq_attr "type" "arlo_shift,arlo_shift_reg,\
+       (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
+                        logic_shift_imm,logics_shift_imm,\
+                        alu_shift_reg,alus_shift_reg,\
+                        logic_shift_reg,logics_shift_reg,\
                         mov_shift,mov_shift_reg,\
                         mvn_shift,mvn_shift_reg"))
   "cortex_a53_slot_any")
@@ -202,7 +209,7 @@
 (define_insn_reservation "cortex_a53_fpalu" 4
   (and (eq_attr "tune" "cortexa53")
        (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls, f_cvt,\
-			fcmps, fcmpd"))
+			fcmps, fcmpd, fcsel"))
   "cortex_a53_slot0+cortex_a53_fpadd_pipe")
 
 (define_insn_reservation "cortex_a53_fconst" 2
diff --git a/gcc/config/arm/cortex-a7.md b/gcc/config/arm/cortex-a7.md
index cb1f7cff264..9373077b754 100644
--- a/gcc/config/arm/cortex-a7.md
+++ b/gcc/config/arm/cortex-a7.md
@@ -86,7 +86,8 @@
 ;; ALU instruction with an immediate operand can dual-issue.
 (define_insn_reservation "cortex_a7_alu_imm" 2
   (and (eq_attr "tune" "cortexa7")
-       (ior (eq_attr "type" "arlo_imm,mov_imm,mvn_imm,extend")
+       (ior (eq_attr "type" "adr,alu_imm,alus_imm,logic_imm,logics_imm,\
+                             mov_imm,mvn_imm,extend")
             (and (eq_attr "type" "mov_reg,mov_shift,mov_shift_reg")
                  (not (eq_attr "length" "8")))))
   "cortex_a7_ex2|cortex_a7_ex1")
@@ -95,12 +96,18 @@
 ;; with a younger immediate-based instruction.
 (define_insn_reservation "cortex_a7_alu_reg" 2
   (and (eq_attr "tune" "cortexa7")
-       (eq_attr "type" "arlo_reg,shift,shift_reg,mov_reg,mvn_reg"))
+       (eq_attr "type" "alu_reg,alus_reg,logic_reg,logics_reg,\
+                        adc_imm,adcs_imm,adc_reg,adcs_reg,\
+                        bfm,rev,\
+                        shift_imm,shift_reg,mov_reg,mvn_reg"))
   "cortex_a7_ex1")
 
 (define_insn_reservation "cortex_a7_alu_shift" 2
   (and (eq_attr "tune" "cortexa7")
-       (eq_attr "type" "arlo_shift,arlo_shift_reg,\
+       (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
+                        logic_shift_imm,logics_shift_imm,\
+                        alu_shift_reg,alus_shift_reg,\
+                        logic_shift_reg,logics_shift_reg,\
                         mov_shift,mov_shift_reg,\
                         mvn_shift,mvn_shift_reg"))
   "cortex_a7_ex1")
diff --git a/gcc/config/arm/cortex-a8.md b/gcc/config/arm/cortex-a8.md
index acbfef587b0..22f9ee92bde 100644
--- a/gcc/config/arm/cortex-a8.md
+++ b/gcc/config/arm/cortex-a8.md
@@ -85,17 +85,24 @@
 ;; (source read in E2 and destination available at the end of that cycle).
 (define_insn_reservation "cortex_a8_alu" 2
   (and (eq_attr "tune" "cortexa8")
-       (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,clz"))
+       (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+                        alu_reg,alus_reg,logic_reg,logics_reg,\
+                        adc_imm,adcs_imm,adc_reg,adcs_reg,\
+                        adr,bfm,clz,rbit,rev,\
+                        shift_imm,shift_reg"))
   "cortex_a8_default")
 
 (define_insn_reservation "cortex_a8_alu_shift" 2
   (and (eq_attr "tune" "cortexa8")
-       (eq_attr "type" "extend,arlo_shift"))
+       (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
+                        logic_shift_imm,logics_shift_imm,\
+                        extend"))
   "cortex_a8_default")
 
 (define_insn_reservation "cortex_a8_alu_shift_reg" 2
   (and (eq_attr "tune" "cortexa8")
-       (eq_attr "type" "arlo_shift_reg"))
+       (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
+                        logic_shift_reg,logics_shift_reg"))
   "cortex_a8_default")
 
 ;; Move instructions.
diff --git a/gcc/config/arm/cortex-a9.md b/gcc/config/arm/cortex-a9.md
index 198e8de80cf..e5788b6b872 100644
--- a/gcc/config/arm/cortex-a9.md
+++ b/gcc/config/arm/cortex-a9.md
@@ -80,7 +80,11 @@ cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1")
 ;; which can go down E2 without any problem.
 (define_insn_reservation "cortex_a9_dp" 2
   (and (eq_attr "tune" "cortexa9")
-       (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
+       (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+                        alu_reg,alus_reg,logic_reg,logics_reg,\
+                        adc_imm,adcs_imm,adc_reg,adcs_reg,\
+                        adr,bfm,rev,\
+                        shift_imm,shift_reg,\
                         mov_imm,mov_reg,mvn_imm,mvn_reg,\
                         mov_shift_reg,mov_shift"))
   "cortex_a9_p0_default|cortex_a9_p1_default")
@@ -88,8 +92,11 @@ cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1")
 ;; An instruction using the shifter will go down E1.
 (define_insn_reservation "cortex_a9_dp_shift" 3
    (and (eq_attr "tune" "cortexa9")
-        (eq_attr "type" "arlo_shift_reg,extend,arlo_shift,\
-                         mvn_shift,mvn_shift_reg"))
+        (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
+                         logic_shift_imm,logics_shift_imm,\
+                         alu_shift_reg,alus_shift_reg,\
+                         logic_shift_reg,logics_shift_reg,\
+                         extend,mvn_shift,mvn_shift_reg"))
    "cortex_a9_p0_shift | cortex_a9_p1_shift")
 
 ;; Loads have a latency of 4 cycles.
diff --git a/gcc/config/arm/cortex-m4.md b/gcc/config/arm/cortex-m4.md
index 53bd60cd98f..0c628f08b5f 100644
--- a/gcc/config/arm/cortex-m4.md
+++ b/gcc/config/arm/cortex-m4.md
@@ -31,8 +31,15 @@
 ;; ALU and multiply is one cycle.
 (define_insn_reservation "cortex_m4_alu" 1
   (and (eq_attr "tune" "cortexm4")
-       (ior (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,extend,\
-                             arlo_shift,arlo_shift_reg,\
+       (ior (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+                             alu_reg,alus_reg,logic_reg,logics_reg,\
+                             adc_imm,adcs_imm,adc_reg,adcs_reg,\
+                             adr,bfm,rev,\
+                             shift_imm,shift_reg,extend,\
+                             alu_shift_imm,alus_shift_imm,\
+                             logic_shift_imm,logics_shift_imm,\
+                             alu_shift_reg,alus_shift_reg,\
+                             logic_shift_reg,logics_shift_reg,\
                              mov_imm,mov_reg,mov_shift,mov_shift_reg,\
                              mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg")
 	    (ior (eq_attr "mul32" "yes")
diff --git a/gcc/config/arm/cortex-r4.md b/gcc/config/arm/cortex-r4.md
index 597774dbd89..83745c1b4c7 100644
--- a/gcc/config/arm/cortex-r4.md
+++ b/gcc/config/arm/cortex-r4.md
@@ -78,7 +78,11 @@
 ;; for the purposes of the dual-issue constraints above.
 (define_insn_reservation "cortex_r4_alu" 2
   (and (eq_attr "tune_cortexr4" "yes")
-       (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,mvn_imm,mvn_reg"))
+       (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+                        alu_reg,alus_reg,logic_reg,logics_reg,\
+                        adc_imm,adcs_imm,adc_reg,adcs_reg,\
+                        adr,bfm,rev,\
+                        shift_imm,shift_reg,mvn_imm,mvn_reg"))
   "cortex_r4_alu")
 
 (define_insn_reservation "cortex_r4_mov" 2
@@ -88,12 +92,16 @@
 
 (define_insn_reservation "cortex_r4_alu_shift" 2
   (and (eq_attr "tune_cortexr4" "yes")
-       (eq_attr "type" "extend,arlo_shift,mov_shift,mvn_shift"))
+       (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
+                        logic_shift_imm,logics_shift_imm,\
+                        extend,mov_shift,mvn_shift"))
   "cortex_r4_alu")
 
 (define_insn_reservation "cortex_r4_alu_shift_reg" 2
   (and (eq_attr "tune_cortexr4" "yes")
-       (eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg"))
+       (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
+                       logic_shift_reg,logics_shift_reg,\
+                       mov_shift_reg,mvn_shift_reg"))
   "cortex_r4_alu_shift_reg")
 
 ;; An ALU instruction followed by an ALU instruction with no early dep.
diff --git a/gcc/config/arm/fa526.md b/gcc/config/arm/fa526.md
index 9ec92d60dc5..90abf6cb859 100644
--- a/gcc/config/arm/fa526.md
+++ b/gcc/config/arm/fa526.md
@@ -62,13 +62,21 @@
 ;; ALU operations
 (define_insn_reservation "526_alu_op" 1
  (and (eq_attr "tune" "fa526")
-      (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
+      (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+                       alu_reg,alus_reg,logic_reg,logics_reg,\
+                       adc_imm,adcs_imm,adc_reg,adcs_reg,\
+                       adr,bfm,rev,\
+                       shift_imm,shift_reg,\
                        mov_imm,mov_reg,mvn_imm,mvn_reg"))
  "fa526_core")
 
 (define_insn_reservation "526_alu_shift_op" 2
  (and (eq_attr "tune" "fa526")
-      (eq_attr "type" "extend,arlo_shift,arlo_shift_reg,\
+      (eq_attr "type" "extend,\
+                       alu_shift_imm,alus_shift_imm,\
+                       logic_shift_imm,logics_shift_imm,\
+                       alu_shift_reg,alus_shift_reg,\
+                       logic_shift_reg,logics_shift_reg,\
                        mov_shift,mov_shift_reg,\
                        mvn_shift,mvn_shift_reg"))
  "fa526_core")
diff --git a/gcc/config/arm/fa606te.md b/gcc/config/arm/fa606te.md
index e61242886d7..20f66e6ae19 100644
--- a/gcc/config/arm/fa606te.md
+++ b/gcc/config/arm/fa606te.md
@@ -62,8 +62,15 @@
 ;; ALU operations
 (define_insn_reservation "606te_alu_op" 1
  (and (eq_attr "tune" "fa606te")
-      (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,
-                       extend,arlo_shift,arlo_shift_reg,\
+      (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+                       alu_reg,alus_reg,logic_reg,logics_reg,\
+                       adc_imm,adcs_imm,adc_reg,adcs_reg,\
+                       adr,bfm,rev,\
+                       shift_imm,shift_reg,extend,\
+                       alu_shift_imm,alus_shift_imm,\
+                       logic_shift_imm,logics_shift_imm,\
+                       alu_shift_reg,alus_shift_reg,\
+                       logic_shift_reg,logics_shift_reg,\
                        mov_imm,mov_reg,mov_shift,mov_shift_reg,\
                        mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg"))
  "fa606te_core")
diff --git a/gcc/config/arm/fa626te.md b/gcc/config/arm/fa626te.md
index 04d2a5cf33f..c5b841c3630 100644
--- a/gcc/config/arm/fa626te.md
+++ b/gcc/config/arm/fa626te.md
@@ -68,13 +68,21 @@
 ;; ALU operations
 (define_insn_reservation "626te_alu_op" 1
  (and (eq_attr "tune" "fa626,fa626te")
-      (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
+      (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+                       alu_reg,alus_reg,logic_reg,logics_reg,\
+                       adc_imm,adcs_imm,adc_reg,adcs_reg,\
+                       adr,bfm,rev,\
+                       shift_imm,shift_reg,\
                        mov_imm,mov_reg,mvn_imm,mvn_reg"))
  "fa626te_core")
 
 (define_insn_reservation "626te_alu_shift_op" 2
  (and (eq_attr "tune" "fa626,fa626te")
-      (eq_attr "type" "extend,arlo_shift,arlo_shift_reg,\
+      (eq_attr "type" "extend,\
+                       alu_shift_imm,alus_shift_imm,\
+                       logic_shift_imm,logics_shift_imm,\
+                       alu_shift_reg,alus_shift_reg,\
+                       logic_shift_reg,logics_shift_reg,\
                        mov_shift,mov_shift_reg,\
                        mvn_shift,mvn_shift_reg"))
  "fa626te_core")
diff --git a/gcc/config/arm/fa726te.md b/gcc/config/arm/fa726te.md
index 342b9bf5d33..1947d36ec09 100644
--- a/gcc/config/arm/fa726te.md
+++ b/gcc/config/arm/fa726te.md
@@ -86,7 +86,11 @@
 ;; Other ALU instructions 2 cycles.
 (define_insn_reservation "726te_alu_op" 1
  (and (eq_attr "tune" "fa726te")
-      (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
+      (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+                       alu_reg,alus_reg,logic_reg,logics_reg,\
+                       adc_imm,adcs_imm,adc_reg,adcs_reg,\
+                       adr,bfm,rev,\
+                       shift_imm,shift_reg"))
   "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
 
 ;; ALU operations with a shift-by-register operand.
@@ -95,12 +99,14 @@
 ;; it takes 3 cycles.
 (define_insn_reservation "726te_alu_shift_op" 3
  (and (eq_attr "tune" "fa726te")
-      (eq_attr "type" "extend,arlo_shift"))
+      (eq_attr "type" "extend,alu_shift_imm,alus_shift_imm,\
+                       logic_shift_imm,logics_shift_imm"))
   "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
 
 (define_insn_reservation "726te_alu_shift_reg_op" 3
  (and (eq_attr "tune" "fa726te")
-      (eq_attr "type" "arlo_shift_reg"))
+      (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
+                       logic_shift_reg,logics_shift_reg"))
   "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;; Multiplication Instructions
diff --git a/gcc/config/arm/fmp626.md b/gcc/config/arm/fmp626.md
index 944645b9ead..ffb68570e37 100644
--- a/gcc/config/arm/fmp626.md
+++ b/gcc/config/arm/fmp626.md
@@ -63,13 +63,19 @@
 ;; ALU operations
 (define_insn_reservation "mp626_alu_op" 1
  (and (eq_attr "tune" "fmp626")
-      (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
+      (eq_attr "type" "alu_imm,alus_imm,alu_reg,alus_reg,\
+                       logic_imm,logics_imm,logic_reg,logics_reg,\
+                       adc_imm,adcs_imm,adc_reg,adcs_reg,\
+                       adr,bfm,rev,\
+                       shift_imm,shift_reg,\
                        mov_imm,mov_reg,mvn_imm,mvn_reg"))
  "fmp626_core")
 
 (define_insn_reservation "mp626_alu_shift_op" 2
  (and (eq_attr "tune" "fmp626")
-      (eq_attr "type" "extend,arlo_shift,arlo_shift_reg,\
+      (eq_attr "type" "alu_shift_imm,logic_shift_imm,alus_shift_imm,logics_shift_imm,\
+                       alu_shift_reg,logic_shift_reg,alus_shift_reg,logics_shift_reg,\
+                       extend,\
                        mov_shift,mov_shift_reg,\
                        mvn_shift,mvn_shift_reg"))
  "fmp626_core")
diff --git a/gcc/config/arm/marvell-pj4.md b/gcc/config/arm/marvell-pj4.md
index 3d1bf596f86..f6e4e011c33 100644
--- a/gcc/config/arm/marvell-pj4.md
+++ b/gcc/config/arm/marvell-pj4.md
@@ -53,26 +53,42 @@
 
 (define_insn_reservation "pj4_alu" 1
   (and (eq_attr "tune" "marvell_pj4")
-       (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
+       (eq_attr "type" "alu_imm,alus_imm,alu_reg,alus_reg,\
+                        logic_imm,logics_imm,logic_reg,logics_reg,\
+                        adc_imm,adcs_imm,adc_reg,adcs_reg,\
+                        adr,bfm,rev,\
+                        shift_imm,shift_reg")
        (not (eq_attr "conds" "set")))
                                "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
 
 (define_insn_reservation "pj4_alu_conds" 4
   (and (eq_attr "tune" "marvell_pj4")
-       (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
+       (eq_attr "type" "alu_imm,alus_imm,alu_reg,alus_reg,\
+                        logic_imm,logics_imm,logic_reg,logics_reg,\
+                        adc_imm,adcs_imm,adc_reg,adcs_reg,\
+                        adr,bfm,rev,\
+                        shift_imm,shift_reg")
        (eq_attr "conds" "set"))
                                "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
 
 (define_insn_reservation "pj4_shift" 1
   (and (eq_attr "tune" "marvell_pj4")
-       (eq_attr "type" "arlo_shift,arlo_shift_reg,extend,\
+       (eq_attr "type" "alu_shift_imm,logic_shift_imm,\
+                        alus_shift_imm,logics_shift_imm,\
+                        alu_shift_reg,logic_shift_reg,\
+                        alus_shift_reg,logics_shift_reg,\
+                        extend,\
                         mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg")
        (not (eq_attr "conds" "set"))
        (eq_attr "shift" "1"))  "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
 
 (define_insn_reservation "pj4_shift_conds" 4
   (and (eq_attr "tune" "marvell_pj4")
-       (eq_attr "type" "arlo_shift,arlo_shift_reg,extend,\
+       (eq_attr "type" "alu_shift_imm,logic_shift_imm,\
+                        alus_shift_imm,logics_shift_imm,\
+                        alu_shift_reg,logic_shift_reg,\
+                        alus_shift_reg,logics_shift_reg,\
+                        extend,\
                         mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg")
        (eq_attr "conds" "set")
        (eq_attr "shift" "1"))  "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
@@ -80,14 +96,20 @@
 (define_insn_reservation "pj4_alu_shift" 1
   (and (eq_attr "tune" "marvell_pj4")
        (not (eq_attr "conds" "set"))
-       (eq_attr "type" "arlo_shift,arlo_shift_reg,extend,\
+       (eq_attr "type" "alu_shift_imm,logic_shift_imm,\
+                        alus_shift_imm,logics_shift_imm,\
+                        alu_shift_reg,logic_shift_reg,\
+                        alus_shift_reg,logics_shift_reg,\
+                        extend,\
                         mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg"))
                                "pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)")
 
 (define_insn_reservation "pj4_alu_shift_conds" 4
   (and (eq_attr "tune" "marvell_pj4")
        (eq_attr "conds" "set")
-       (eq_attr "type" "arlo_shift,arlo_shift_reg,extend,\
+       (eq_attr "type" "alu_shift_imm,logic_shift_imm,alus_shift_imm,logics_shift_imm,\
+                        alu_shift_reg,logic_shift_reg,alus_shift_reg,logics_shift_reg,\
+                        extend,\
                         mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg"))
                                "pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)")
 
diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md
index ab46658edc0..613d0a10a69 100644
--- a/gcc/config/arm/thumb2.md
+++ b/gcc/config/arm/thumb2.md
@@ -36,7 +36,7 @@
   [(set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no")
    (set_attr "shift" "2")
-   (set_attr "type" "arlo_shift")]
+   (set_attr "type" "alu_shift_imm")]
 )
 
 ;; We use the '0' constraint for operand 1 because reload should
@@ -282,7 +282,7 @@
    ldr%?\\t%0, %1
    str%?\\t%1, %0
    str%?\\t%1, %0"
-  [(set_attr "type" "*,arlo_imm,arlo_imm,arlo_imm,*,load1,load1,store1,store1")
+  [(set_attr "type" "*,alu_imm,alu_imm,alu_imm,*,load1,load1,store1,store1")
    (set_attr "length" "2,4,2,4,4,4,4,4,4")
    (set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no")
@@ -350,7 +350,7 @@
   "cmn%?\\t%0, %1%S3"
   [(set_attr "conds" "set")
    (set_attr "shift" "1")
-   (set_attr "type" "arlo_shift")]
+   (set_attr "type" "alus_shift_imm")]
 )
 
 (define_insn_and_split "*thumb2_mov_scc"
@@ -1102,8 +1102,8 @@
    (set_attr "shift" "1")
    (set_attr "length" "2")
    (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
-		      (const_string "arlo_shift")
-		      (const_string "arlo_shift_reg")))]
+		      (const_string "alu_shift_imm")
+		      (const_string "alu_shift_reg")))]
 )
 
 (define_insn "*thumb2_mov<mode>_shortim"
@@ -1225,7 +1225,7 @@
   "
   [(set_attr "conds" "set")
    (set_attr "length" "2,2,4,4")
-   (set_attr "type"   "arlo_imm,*,arlo_imm,*")]
+   (set_attr "type" "alus_imm,alus_reg,alus_imm,alus_reg")]
 )
 
 (define_insn "*thumb2_mulsi_short"
@@ -1351,7 +1351,7 @@
   [(set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no")
    (set_attr "shift" "2")
-   (set_attr "type" "arlo_shift")]
+   (set_attr "type" "alu_shift_imm")]
 )
 
 (define_peephole2
diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md
index 1b7db65f228..14d2bee82ca 100644
--- a/gcc/config/arm/types.md
+++ b/gcc/config/arm/types.md
@@ -23,21 +23,37 @@
 ;
 ; Instruction classification:
 ;
-; arlo_imm           any arithmetic or logical instruction that doesn't have
-;                    a shifted operand and has an immediate operand.  This
+; adc_imm            add/subtract with carry and with an immediate operand.
+; adc_reg            add/subtract with carry and no immediate operand.
+; adcs_imm           as adc_imm, setting condition flags.
+; adcs_reg           as adc_reg, setting condition flags.
+; adr                calculate address.
+; alu_ext            From ARMv8-A: any arithmetic instruction that has a
+;                    sign/zero-extended.
+;                    AArch64 Only.
+;                    source operand
+; alu_imm            any arithmetic instruction that doesn't have a shifted
+;                    operand and has an immediate operand.  This
 ;                    excludes MOV, MVN and RSB(S) immediate.
-; arlo_reg           any arithmetic or logical instruction that doesn't have
-;                    a shifted or an immediate operand.  This excludes
+; alu_reg            any arithmetic instruction that doesn't have a shifted
+;                    or an immediate operand.  This excludes
 ;                    MOV and MVN but includes MOVT.  This is also the default.
-; arlo_shift         any arithmetic or logical instruction that has a source
-;                    operand shifted by a constant.  This excludes
-;                    simple shifts.
-; arlo_shift_reg     as arlo_shift, with the shift amount specified in a
+; alu_shift_imm      any arithmetic instruction that has a source operand
+;                    shifted by a constant.  This excludes simple shifts.
+; alu_shift_reg      as alu_shift_imm, with the shift amount specified in a
 ;                    register.
+; alus_ext           From ARMv8-A: as alu_ext, setting condition flags.
+;                    AArch64 Only.
+; alus_imm           as alu_imm, setting condition flags.
+; alus_reg           as alu_reg, setting condition flags.
+; alus_shift_imm     as alu_shift_imm, setting condition flags.
+; alus_shift_reg     as alu_shift_reg, setting condition flags.
+; bfm                bitfield move operation.
 ; block              blockage insn, this blocks all functional units.
 ; branch             branch.
 ; call               subroutine call.
 ; clz                count leading zeros (CLZ).
+; csel               From ARMv8-A: conditional select.
 ; extend             extend instruction (SXTB, SXTH, UXTB, UXTH).
 ; f_cvt              conversion between float and integral.
 ; f_flag             transfer of co-processor flags to the CPSR.
@@ -54,6 +70,7 @@
 ; fcmp[d,s]          double/single floating-point compare.
 ; fconst[d,s]        double/single load immediate.
 ; fcpys              single precision floating point cpy.
+; fcsel              From ARMv8-A: Floating-point conditional select.
 ; fdiv[d,s]          double/single precision floating point division.
 ; ffarith[d,s]       double/single floating point abs/neg/cpy.
 ; ffma[d,s]          double/single floating point fused multiply-accumulate.
@@ -66,6 +83,18 @@
 ; load2              load 2 words from memory to arm registers.
 ; load3              load 3 words from memory to arm registers.
 ; load4              load 4 words from memory to arm registers.
+; logic_imm          any logical instruction that doesn't have a shifted
+;                    operand and has an immediate operand.
+; logic_reg          any logical instruction that doesn't have a shifted
+;                    operand or an immediate operand.
+; logic_shift_imm    any logical instruction that has a source operand
+;                    shifted by a constant.  This excludes simple shifts.
+; logic_shift_reg    as logic_shift_imm, with the shift amount specified in a
+;                    register.
+; logics_imm         as logic_imm, setting condition flags.
+; logics_reg         as logic_reg, setting condition flags.
+; logics_shift_imm   as logic_shift_imm, setting condition flags.
+; logics_shift_reg   as logic_shift_reg, setting condition flags.
 ; mla                integer multiply accumulate.
 ; mlas               integer multiply accumulate, flag setting.
 ; mov_imm            simple MOV instruction that moves an immediate to
@@ -80,8 +109,10 @@
 ; mvn_reg            inverting move instruction, register.
 ; mvn_shift          inverting move instruction, shifted operand by a constant.
 ; mvn_shift_reg      inverting move instruction, shifted operand by a register.
+; rbit               reverse bits.
+; rev                reverse bytes.
 ; sdiv               signed division.
-; shift              simple shift operation (LSL, LSR, ASR, ROR) with an
+; shift_imm          simple shift operation (LSL, LSR, ASR, ROR) with an
 ;                    immediate.
 ; shift_reg          simple shift by a register.
 ; smlad              signed multiply accumulate dual.
@@ -250,14 +281,27 @@
 ; neon_vst3_vst4
 
 (define_attr "type"
- "arlo_imm,\
-  arlo_reg,\
-  arlo_shift,\
-  arlo_shift_reg,\
+ "adc_imm,\
+  adc_reg,\
+  adcs_imm,\
+  adcs_reg,\
+  adr,\
+  alu_ext,\
+  alu_imm,\
+  alu_reg,\
+  alu_shift_imm,\
+  alu_shift_reg,\
+  alus_ext,\
+  alus_imm,\
+  alus_reg,\
+  alus_shift_imm,\
+  alus_shift_reg,\
+  bfm,\
   block,\
   branch,\
   call,\
   clz,\
+  csel,\
   extend,\
   f_cvt,\
   f_flag,\
@@ -282,6 +326,7 @@
   fconstd,\
   fconsts,\
   fcpys,\
+  fcsel,\
   fdivd,\
   fdivs,\
   ffarithd,\
@@ -299,6 +344,14 @@
   load2,\
   load3,\
   load4,\
+  logic_imm,\
+  logic_reg,\
+  logic_shift_imm,\
+  logic_shift_reg,\
+  logics_imm,\
+  logics_reg,\
+  logics_shift_imm,\
+  logics_shift_reg,\
   mla,\
   mlas,\
   mov_imm,\
@@ -311,8 +364,10 @@
   mvn_reg,\
   mvn_shift,\
   mvn_shift_reg,\
+  rbit,\
+  rev,\
   sdiv,\
-  shift,\
+  shift_imm,\
   shift_reg,\
   smlad,\
   smladx,\
@@ -469,7 +524,7 @@
   neon_vst2_4_regs_vst3_vst4,\
   neon_vst3_vst4_lane,\
   neon_vst3_vst4"
-    (const_string "arlo_reg"))
+    (const_string "alu_imm"))
 
 ; Is this an (integer side) multiply with a 32-bit (or smaller) result?
 (define_attr "mul32" "no,yes"