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authoreager <eager@138bc75d-0d04-0410-961f-82ee72b054a4>2013-02-27 17:21:40 +0000
committereager <eager@138bc75d-0d04-0410-961f-82ee72b054a4>2013-02-27 17:21:40 +0000
commite249ec67f2b6d42ff354f7545296d1bc23bdc379 (patch)
treefabd4d89ef4b2a9e7a14dd6c7eb4d3bdaffcb7e3
parentdcd56d11f3153d8a82722fca448dd20ff6169bd9 (diff)
downloadgcc-e249ec67f2b6d42ff354f7545296d1bc23bdc379.tar.gz
Avoid pcmpe insns when not valuable.
* gcc/config/microblaze/microblaze.c (microblaze_emit_compare): Use xor for EQ/NE comparisions * gcc/config/microblaze/microblaze.md (cstoresf4): Add constraints (cbranchsf4): Adjust operator to comparison_operator git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196315 138bc75d-0d04-0410-961f-82ee72b054a4
-rw-r--r--gcc/ChangeLog7
-rw-r--r--gcc/config/microblaze/microblaze.c17
-rw-r--r--gcc/config/microblaze/microblaze.md10
3 files changed, 14 insertions, 20 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 51a19f56aaa..4ebe5039cd2 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2013-02-27 Edgar E. Iglesias <edgar.iglesias@gmail.com>
+
+ * config/microblaze/microblaze.c (microblaze_emit_compare):
+ Use xor for EQ/NE comparisions
+ * config/microblaze/microblaze.md (cstoresf4): Add constraints
+ (cbranchsf4): Adjust operator to comparison_operator
+
2013-02-27 Jakub Jelinek <jakub@redhat.com>
PR middle-end/56461
diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
index fc0296e2c15..f45d30cf450 100644
--- a/gcc/config/microblaze/microblaze.c
+++ b/gcc/config/microblaze/microblaze.c
@@ -2842,21 +2842,8 @@ microblaze_emit_compare (enum machine_mode mode, rtx cmp, enum rtx_code *cmp_cod
if (code == EQ || code == NE)
{
- if (TARGET_PATTERN_COMPARE && GET_CODE(cmp_op1) == REG)
- {
- if (code == EQ)
- {
- emit_insn (gen_seq_internal_pat (comp_reg, cmp_op0, cmp_op1));
- *cmp_code = NE;
- }
- else
- {
- emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0, cmp_op1));
- }
- }
- else
- /* Use xor for equal/not-equal comparison. */
- emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1));
+ /* Use xor for equal/not-equal comparison. */
+ emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1));
}
else if (code == GT || code == GTU || code == LE || code == LEU)
{
diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
index 1b4200307cb..339186455ba 100644
--- a/gcc/config/microblaze/microblaze.md
+++ b/gcc/config/microblaze/microblaze.md
@@ -1637,10 +1637,10 @@
;; Setting a register from an floating point comparison.
;;----------------------------------------------------------------
(define_insn "cstoresf4"
- [(set (match_operand:SI 0 "register_operand")
- (match_operator:SI 1 "ordered_comparison_operator"
- [(match_operand:SF 2 "register_operand")
- (match_operand:SF 3 "register_operand")]))]
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (match_operator 1 "comparison_operator"
+ [(match_operand:SF 2 "register_operand" "r")
+ (match_operand:SF 3 "register_operand" "r")]))]
"TARGET_HARD_FLOAT"
"fcmp.%C1\t%0,%3,%2"
[(set_attr "type" "fcmp")
@@ -1667,7 +1667,7 @@
(define_expand "cbranchsf4"
[(set (pc)
- (if_then_else (match_operator:SI 0 "ordered_comparison_operator"
+ (if_then_else (match_operator 0 "comparison_operator"
[(match_operand:SF 1 "register_operand")
(match_operand:SF 2 "register_operand")])
(label_ref (match_operand 3 ""))