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| author | Ju-Zhe Zhong <juzhe.zhong@rivai.ai> | 2022-10-17 16:36:42 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2022-10-21 11:56:21 +0800 |
| commit | f56d48b2471c388401174029324e1f4c4b84fcdb (patch) | |
| tree | 86ef65fb9129a3b6deb076a687bbdfa2ed93ad45 /configure.ac | |
| parent | cbd505700e09cfea8bdaa93ad6bd0514372e9034 (diff) | |
| download | gcc-f56d48b2471c388401174029324e1f4c4b84fcdb.tar.gz | |
RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests.
gcc/ChangeLog:
* config.gcc: Add riscv-vector-builtins-bases.o and riscv-vector-builtins-shapes.o
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_I_OPS): New macro.
(DEF_RVV_FUNCTION): Ditto.
(handle_pragma_vector): Add intrinsic framework.
* config/riscv/riscv.cc (riscv_print_operand): Add operand print for vsetvl/vsetvlmax.
* config/riscv/riscv.md: include vector.md.
* config/riscv/t-riscv: Add riscv-vector-builtins-bases.o and riscv-vector-builtins-shapes.o
* config/riscv/riscv-vector-builtins-bases.cc: New file.
* config/riscv/riscv-vector-builtins-bases.h: New file.
* config/riscv/riscv-vector-builtins-functions.def: New file.
* config/riscv/riscv-vector-builtins-shapes.cc: New file.
* config/riscv/riscv-vector-builtins-shapes.h: New file.
* config/riscv/riscv-vector-builtins-types.def: New file.
* config/riscv/vector.md: New file.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vsetvl-1.c: New test.
Diffstat (limited to 'configure.ac')
0 files changed, 0 insertions, 0 deletions