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| author | GCC Administrator <gccadmin@gcc.gnu.org> | 2023-04-17 00:17:00 +0000 |
|---|---|---|
| committer | GCC Administrator <gccadmin@gcc.gnu.org> | 2023-04-17 00:17:00 +0000 |
| commit | a167416a239a4afcc7e89d2ccdea3ffa318defac (patch) | |
| tree | bee7349e3e37cebab2400b00341491b4dca7f1ca /gcc/ChangeLog | |
| parent | a647198fcf7463a42c8e035a429200e7998735dc (diff) | |
| download | gcc-a167416a239a4afcc7e89d2ccdea3ffa318defac.tar.gz | |
Daily bump.
Diffstat (limited to 'gcc/ChangeLog')
| -rw-r--r-- | gcc/ChangeLog | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c6cdcc3a1db..33e4b506765 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2023-04-16 Jeff Law <jlaw@ventanamicro> + + PR target/109508 + * config/riscv/riscv.cc (riscv_expand_conditional_move): For + TARGET_SFB_ALU, force the true arm into a register. + 2023-04-15 John David Anglin <danglin@gcc.gnu.org> PR target/104989 |