summaryrefslogtreecommitdiff
path: root/gcc/config/aarch64
diff options
context:
space:
mode:
authormrs <mrs@138bc75d-0d04-0410-961f-82ee72b054a4>2013-10-20 23:47:35 +0000
committermrs <mrs@138bc75d-0d04-0410-961f-82ee72b054a4>2013-10-20 23:47:35 +0000
commit6b40961666f073231ed8a76e6e33deeda063cde7 (patch)
tree8247eb4232e8be98b7f61bd68bab2fd1a9f06ca3 /gcc/config/aarch64
parente6b1b76450af5f98696ecedd4bd9a0ed18cdb2a6 (diff)
parentfc1ce0cf396bf638746d546a557158d87f13849b (diff)
downloadgcc-6b40961666f073231ed8a76e6e33deeda063cde7.tar.gz
Merge in trunk.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/wide-int@203881 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/aarch64')
-rw-r--r--gcc/config/aarch64/aarch64-simd-builtins.def2
-rw-r--r--gcc/config/aarch64/aarch64-simd.md302
-rw-r--r--gcc/config/aarch64/aarch64.c81
-rw-r--r--gcc/config/aarch64/aarch64.h20
-rw-r--r--gcc/config/aarch64/aarch64.md58
-rw-r--r--gcc/config/aarch64/aarch64.opt4
-rw-r--r--gcc/config/aarch64/arm_neon.h435
-rw-r--r--gcc/config/aarch64/iterators.md19
8 files changed, 503 insertions, 418 deletions
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index 35897f39395..c18b150a1f5 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -45,7 +45,7 @@
BUILTIN_VDQF (UNOP, sqrt, 2)
BUILTIN_VD_BHSI (BINOP, addp, 0)
VAR1 (UNOP, addp, 0, di)
- VAR1 (UNOP, clz, 2, v4si)
+ BUILTIN_VDQ_BHSI (UNOP, clz, 2)
BUILTIN_VALL (GETLANE, get_lane, 0)
VAR1 (GETLANE, get_lane, 0, di)
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index f13cd5b7cdb..a747ee8d7ba 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -238,80 +238,6 @@
none"
(const_string "none"))
-
-; The "neon_type" attribute is used by the AArch32 backend. Below is a mapping
-; from "simd_type" to "neon_type".
-
-(define_attr "neon_type"
- "neon_int_1,neon_int_2,neon_int_3,neon_int_4,neon_int_5,neon_vqneg_vqabs,
- neon_vmov,neon_vaba,neon_vsma,neon_vaba_qqq,
- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,neon_mul_qqq_8_16_32_ddd_32,
- neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar,
- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,neon_mla_qqq_8_16,
- neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long,
- neon_mla_qqq_32_qqd_32_scalar,neon_mul_ddd_16_scalar_32_16_long_scalar,
- neon_mul_qqd_32_scalar,neon_mla_ddd_16_scalar_qdd_32_16_long_scalar,
- neon_shift_1,neon_shift_2,neon_shift_3,neon_vshl_ddd,
- neon_vqshl_vrshl_vqrshl_qqq,neon_vsra_vrsra,neon_fp_vadd_ddd_vabs_dd,
- neon_fp_vadd_qqq_vabs_qq,neon_fp_vsum,neon_fp_vmul_ddd,neon_fp_vmul_qqd,
- neon_fp_vmla_ddd,neon_fp_vmla_qqq,neon_fp_vmla_ddd_scalar,
- neon_fp_vmla_qqq_scalar,neon_fp_vrecps_vrsqrts_ddd,
- neon_fp_vrecps_vrsqrts_qqq,neon_bp_simple,neon_bp_2cycle,neon_bp_3cycle,
- neon_ldr,neon_str,neon_vld1_1_2_regs,neon_vld1_3_4_regs,
- neon_vld2_2_regs_vld1_vld2_all_lanes,neon_vld2_4_regs,neon_vld3_vld4,
- neon_vst1_1_2_regs_vst2_2_regs,neon_vst1_3_4_regs,
- neon_vst2_4_regs_vst3_vst4,neon_vst3_vst4,neon_vld1_vld2_lane,
- neon_vld3_vld4_lane,neon_vst1_vst2_lane,neon_vst3_vst4_lane,
- neon_vld3_vld4_all_lanes,neon_mcr,neon_mcr_2_mcrr,neon_mrc,neon_mrrc,
- neon_ldm_2,neon_stm_2,none,unknown"
- (cond [
- (eq_attr "simd_type" "simd_dup") (const_string "neon_bp_simple")
- (eq_attr "simd_type" "simd_movgp") (const_string "neon_bp_simple")
- (eq_attr "simd_type" "simd_add,simd_logic,simd_logic_imm") (const_string "neon_int_1")
- (eq_attr "simd_type" "simd_negabs,simd_addlv") (const_string "neon_int_3")
- (eq_attr "simd_type" "simd_addn,simd_addn2,simd_addl,simd_sat_add,simd_sat_negabs") (const_string "neon_int_4")
- (eq_attr "simd_type" "simd_move") (const_string "neon_vmov")
- (eq_attr "simd_type" "simd_ins") (const_string "neon_mcr")
- (and (eq_attr "simd_type" "simd_mul,simd_sat_mul") (eq_attr "simd_mode" "V8QI,V4HI")) (const_string "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long")
- (and (eq_attr "simd_type" "simd_mul,simd_sat_mul") (eq_attr "simd_mode" "V2SI,V8QI,V16QI,V2SI")) (const_string "neon_mul_qqq_8_16_32_ddd_32")
- (and (eq_attr "simd_type" "simd_mull,simd_sat_mull") (eq_attr "simd_mode" "V8QI,V16QI,V4HI,V8HI")) (const_string "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long")
- (and (eq_attr "simd_type" "simd_mull,simd_sat_mull") (eq_attr "simd_mode" "V2SI,V4SI,V2DI")) (const_string "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")
- (and (eq_attr "simd_type" "simd_mla,simd_sat_mlal") (eq_attr "simd_mode" "V8QI,V4HI")) (const_string "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")
- (and (eq_attr "simd_type" "simd_mla,simd_sat_mlal") (eq_attr "simd_mode" "V2SI")) (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")
- (and (eq_attr "simd_type" "simd_mla,simd_sat_mlal") (eq_attr "simd_mode" "V16QI,V8HI")) (const_string "neon_mla_qqq_8_16")
- (and (eq_attr "simd_type" "simd_mla,simd_sat_mlal") (eq_attr "simd_mode" "V4SI")) (const_string "neon_mla_qqq_32_qqd_32_scalar")
- (and (eq_attr "simd_type" "simd_mlal") (eq_attr "simd_mode" "V8QI,V16QI,V4HI,V8HI")) (const_string "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")
- (and (eq_attr "simd_type" "simd_mlal") (eq_attr "simd_mode" "V2SI,V4SI,V2DI")) (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")
- (and (eq_attr "simd_type" "simd_fmla") (eq_attr "simd_mode" "V2SF")) (const_string "neon_fp_vmla_ddd")
- (and (eq_attr "simd_type" "simd_fmla") (eq_attr "simd_mode" "V4SF,V2DF")) (const_string "neon_fp_vmla_qqq")
- (and (eq_attr "simd_type" "simd_fmla_elt") (eq_attr "simd_mode" "V2SF")) (const_string "neon_fp_vmla_ddd_scalar")
- (and (eq_attr "simd_type" "simd_fmla_elt") (eq_attr "simd_mode" "V4SF,V2DF")) (const_string "neon_fp_vmla_qqq_scalar")
- (and (eq_attr "simd_type" "simd_fmul,simd_fmul_elt,simd_fdiv,simd_fsqrt") (eq_attr "simd_mode" "V2SF")) (const_string "neon_fp_vmul_ddd")
- (and (eq_attr "simd_type" "simd_fmul,simd_fmul_elt,simd_fdiv,simd_fsqrt") (eq_attr "simd_mode" "V4SF,V2DF")) (const_string "neon_fp_vmul_qqd")
- (and (eq_attr "simd_type" "simd_fadd") (eq_attr "simd_mode" "V2SF")) (const_string "neon_fp_vadd_ddd_vabs_dd")
- (and (eq_attr "simd_type" "simd_fadd") (eq_attr "simd_mode" "V4SF,V2DF")) (const_string "neon_fp_vadd_qqq_vabs_qq")
- (and (eq_attr "simd_type" "simd_fnegabs,simd_fminmax,simd_fminmaxv") (eq_attr "simd_mode" "V2SF")) (const_string "neon_fp_vadd_ddd_vabs_dd")
- (and (eq_attr "simd_type" "simd_fnegabs,simd_fminmax,simd_fminmaxv") (eq_attr "simd_mode" "V4SF,V2DF")) (const_string "neon_fp_vadd_qqq_vabs_qq")
- (and (eq_attr "simd_type" "simd_shift,simd_shift_acc") (eq_attr "simd_mode" "V8QI,V4HI,V2SI")) (const_string "neon_vshl_ddd")
- (and (eq_attr "simd_type" "simd_shift,simd_shift_acc") (eq_attr "simd_mode" "V16QI,V8HI,V4SI,V2DI")) (const_string "neon_shift_3")
- (eq_attr "simd_type" "simd_minmax,simd_minmaxv") (const_string "neon_int_5")
- (eq_attr "simd_type" "simd_shiftn_imm,simd_shiftn2_imm,simd_shiftl_imm,") (const_string "neon_shift_1")
- (eq_attr "simd_type" "simd_load1,simd_load2") (const_string "neon_vld1_1_2_regs")
- (eq_attr "simd_type" "simd_load3,simd_load3") (const_string "neon_vld1_3_4_regs")
- (eq_attr "simd_type" "simd_load1r,simd_load2r,simd_load3r,simd_load4r") (const_string "neon_vld2_2_regs_vld1_vld2_all_lanes")
- (eq_attr "simd_type" "simd_load1s,simd_load2s") (const_string "neon_vld1_vld2_lane")
- (eq_attr "simd_type" "simd_load3s,simd_load4s") (const_string "neon_vld3_vld4_lane")
- (eq_attr "simd_type" "simd_store1,simd_store2") (const_string "neon_vst1_1_2_regs_vst2_2_regs")
- (eq_attr "simd_type" "simd_store3,simd_store4") (const_string "neon_vst1_3_4_regs")
- (eq_attr "simd_type" "simd_store1s,simd_store2s") (const_string "neon_vst1_vst2_lane")
- (eq_attr "simd_type" "simd_store3s,simd_store4s") (const_string "neon_vst3_vst4_lane")
- (and (eq_attr "simd_type" "simd_frecpe,simd_frecps") (eq_attr "simd_mode" "V2SF")) (const_string "neon_fp_vrecps_vrsqrts_ddd")
- (and (eq_attr "simd_type" "simd_frecpe,simd_frecps") (eq_attr "simd_mode" "V4SF,V2DF")) (const_string "neon_fp_vrecps_vrsqrts_qqq")
- (eq_attr "simd_type" "none") (const_string "none")
- ]
- (const_string "unknown")))
-
-
(define_expand "mov<mode>"
[(set (match_operand:VALL 0 "aarch64_simd_nonimmediate_operand" "")
(match_operand:VALL 1 "aarch64_simd_general_operand" ""))]
@@ -343,6 +269,7 @@
dup\\t%0.<Vtype>, %<vw>1
dup\\t%0.<Vtype>, %1.<Vetype>[0]"
[(set_attr "simd_type" "simd_dupgp, simd_dup")
+ (set_attr "type" "neon_from_gp<q>, neon_dup<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -352,6 +279,7 @@
"TARGET_SIMD"
"dup\\t%0.<Vtype>, %1.<Vetype>[0]"
[(set_attr "simd_type" "simd_dup")
+ (set_attr "type" "neon_dup<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -365,6 +293,7 @@
"TARGET_SIMD"
"dup\\t%0.<Vtype>, %1.<Vetype>[%2]"
[(set_attr "simd_type" "simd_dup")
+ (set_attr "type" "neon_dup<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -378,6 +307,7 @@
"TARGET_SIMD"
"dup\\t%0.<Vtype>, %1.<Vetype>[%2]"
[(set_attr "simd_type" "simd_dup")
+ (set_attr "type" "neon_dup<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -405,6 +335,9 @@
}
}
[(set_attr "simd_type" "simd_load1,simd_store1,simd_move,simd_movgp,simd_insgp,simd_move,simd_move_imm")
+ (set_attr "type" "neon_load1_1reg<q>, neon_store1_1reg<q>,\
+ neon_logic<q>, neon_to_gp<q>, neon_from_gp<q>,\
+ mov_reg, neon_move<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -436,6 +369,9 @@
}
}
[(set_attr "simd_type" "simd_load1,simd_store1,simd_move,simd_movgp,simd_insgp,simd_move,simd_move_imm")
+ (set_attr "type" "neon_load1_1reg<q>, neon_store1_1reg<q>,\
+ neon_logic<q>, multiple, multiple, multiple,\
+ neon_move<q>")
(set_attr "simd_mode" "<MODE>")
(set_attr "length" "4,4,4,8,8,8,4")]
)
@@ -516,6 +452,7 @@
"TARGET_SIMD && reload_completed"
"umov\t%0, %1.d[0]"
[(set_attr "simd_type" "simd_movgp")
+ (set_attr "type" "neon_to_gp<q>")
(set_attr "simd_mode" "<MODE>")
(set_attr "length" "4")
])
@@ -528,6 +465,7 @@
"TARGET_SIMD && reload_completed"
"umov\t%0, %1.d[1]"
[(set_attr "simd_type" "simd_movgp")
+ (set_attr "type" "neon_to_gp<q>")
(set_attr "simd_mode" "<MODE>")
(set_attr "length" "4")
])
@@ -539,6 +477,7 @@
"TARGET_SIMD"
"orn\t%0.<Vbtype>, %2.<Vbtype>, %1.<Vbtype>"
[(set_attr "simd_type" "simd_logic")
+ (set_attr "type" "neon_logic<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -549,6 +488,7 @@
"TARGET_SIMD"
"bic\t%0.<Vbtype>, %2.<Vbtype>, %1.<Vbtype>"
[(set_attr "simd_type" "simd_logic")
+ (set_attr "type" "neon_logic<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -559,6 +499,7 @@
"TARGET_SIMD"
"add\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
[(set_attr "simd_type" "simd_add")
+ (set_attr "type" "neon_add<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -569,6 +510,7 @@
"TARGET_SIMD"
"sub\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
[(set_attr "simd_type" "simd_add")
+ (set_attr "type" "neon_sub<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -579,6 +521,7 @@
"TARGET_SIMD"
"mul\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
[(set_attr "simd_type" "simd_mul")
+ (set_attr "type" "neon_mul_<Vetype><q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -593,6 +536,7 @@
"TARGET_SIMD"
"<f>mul\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]"
[(set_attr "simd_type" "simd_<f>mul_elt")
+ (set_attr "type" "neon<fp>_mul_<Vetype>_scalar<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -607,6 +551,7 @@
"TARGET_SIMD"
"<f>mul\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]"
[(set_attr "simd_type" "simd_<f>mul_elt")
+ (set_attr "type" "neon<fp>_mul_<Vetype>_scalar<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -619,6 +564,7 @@
"TARGET_SIMD"
"fmul\\t%0.2d, %1.2d, %2.d[0]"
[(set_attr "simd_type" "simd_fmul_elt")
+ (set_attr "type" "neon_fp_mul_d_scalar_q")
(set_attr "simd_mode" "V2DF")]
)
@@ -632,6 +578,7 @@
"TARGET_SIMD"
"fmul\\t%0.2d, %3.2d, %1.d[%2]"
[(set_attr "simd_type" "simd_fmul_elt")
+ (set_attr "type" "neon_fp_mul_d_scalar_q")
(set_attr "simd_mode" "V2DF")]
)
@@ -641,6 +588,7 @@
"TARGET_SIMD"
"neg\t%0.<Vtype>, %1.<Vtype>"
[(set_attr "simd_type" "simd_negabs")
+ (set_attr "type" "neon_neg<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -650,6 +598,7 @@
"TARGET_SIMD"
"abs\t%0.<Vtype>, %1.<Vtype>"
[(set_attr "simd_type" "simd_negabs")
+ (set_attr "type" "neon_abs<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -661,6 +610,7 @@
"TARGET_SIMD"
"sabd\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
[(set_attr "simd_type" "simd_abd")
+ (set_attr "type" "neon_abd<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -673,6 +623,7 @@
"TARGET_SIMD"
"saba\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
[(set_attr "simd_type" "simd_abd")
+ (set_attr "type" "neon_arith_acc<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -684,6 +635,7 @@
"TARGET_SIMD"
"fabd\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
[(set_attr "simd_type" "simd_fabd")
+ (set_attr "type" "neon_fp_abd_<Vetype><q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -695,6 +647,7 @@
"TARGET_SIMD"
"fabd\t%<s>0, %<s>1, %<s>2"
[(set_attr "simd_type" "simd_fabd")
+ (set_attr "type" "neon_fp_abd_<Vetype><q>")
(set_attr "mode" "<MODE>")]
)
@@ -705,6 +658,7 @@
"TARGET_SIMD"
"and\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>"
[(set_attr "simd_type" "simd_logic")
+ (set_attr "type" "neon_logic<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -715,6 +669,7 @@
"TARGET_SIMD"
"orr\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>"
[(set_attr "simd_type" "simd_logic")
+ (set_attr "type" "neon_logic<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -725,6 +680,7 @@
"TARGET_SIMD"
"eor\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>"
[(set_attr "simd_type" "simd_logic")
+ (set_attr "type" "neon_logic<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -734,6 +690,7 @@
"TARGET_SIMD"
"not\t%0.<Vbtype>, %1.<Vbtype>"
[(set_attr "simd_type" "simd_logic")
+ (set_attr "type" "neon_logic<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -747,6 +704,7 @@
"TARGET_SIMD"
"ins\t%0.<Vetype>[%p2], %w1";
[(set_attr "simd_type" "simd_insgp")
+ (set_attr "type" "neon_from_gp<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -757,6 +715,7 @@
"TARGET_SIMD"
"ushr\t%0.<Vtype>, %1.<Vtype>, %2"
[(set_attr "simd_type" "simd_shift_imm")
+ (set_attr "type" "neon_shift_imm<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -767,6 +726,7 @@
"TARGET_SIMD"
"sshr\t%0.<Vtype>, %1.<Vtype>, %2"
[(set_attr "simd_type" "simd_shift_imm")
+ (set_attr "type" "neon_shift_imm<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -777,6 +737,7 @@
"TARGET_SIMD"
"shl\t%0.<Vtype>, %1.<Vtype>, %2"
[(set_attr "simd_type" "simd_shift_imm")
+ (set_attr "type" "neon_shift_imm<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -787,6 +748,7 @@
"TARGET_SIMD"
"sshl\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
[(set_attr "simd_type" "simd_shift")
+ (set_attr "type" "neon_shift_reg<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -798,6 +760,7 @@
"TARGET_SIMD"
"ushl\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
[(set_attr "simd_type" "simd_shift")
+ (set_attr "type" "neon_shift_reg<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -809,6 +772,7 @@
"TARGET_SIMD"
"sshl\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
[(set_attr "simd_type" "simd_shift")
+ (set_attr "type" "neon_shift_reg<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1016,6 +980,7 @@
"TARGET_SIMD"
"ins\t%0.d[%p2], %1";
[(set_attr "simd_type" "simd_insgp")
+ (set_attr "type" "neon_from_gp")
(set_attr "simd_mode" "V2DI")]
)
@@ -1042,6 +1007,7 @@
"TARGET_SIMD"
"ins\t%0.<Vetype>[%p2], %1.<Vetype>[0]";
[(set_attr "simd_type" "simd_ins")
+ (set_attr "type" "neon_ins<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1067,6 +1033,7 @@
"TARGET_SIMD"
"mla\t%0.<Vtype>, %2.<Vtype>, %3.<Vtype>"
[(set_attr "simd_type" "simd_mla")
+ (set_attr "type" "neon_mla_<Vetype><q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1083,6 +1050,7 @@
"TARGET_SIMD"
"mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
[(set_attr "simd_type" "simd_mla")
+ (set_attr "type" "neon_mla_<Vetype>_scalar<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1099,6 +1067,7 @@
"TARGET_SIMD"
"mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
[(set_attr "simd_type" "simd_mla")
+ (set_attr "type" "neon_mla_<Vetype>_scalar<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1110,6 +1079,7 @@
"TARGET_SIMD"
"mls\t%0.<Vtype>, %2.<Vtype>, %3.<Vtype>"
[(set_attr "simd_type" "simd_mla")
+ (set_attr "type" "neon_mla_<Vetype><q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1126,6 +1096,7 @@
"TARGET_SIMD"
"mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
[(set_attr "simd_type" "simd_mla")
+ (set_attr "type" "neon_mla_<Vetype>_scalar<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1142,6 +1113,7 @@
"TARGET_SIMD"
"mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
[(set_attr "simd_type" "simd_mla")
+ (set_attr "type" "neon_mla_<Vetype>_scalar<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1153,6 +1125,7 @@
"TARGET_SIMD"
"<su><maxmin>\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
[(set_attr "simd_type" "simd_minmax")
+ (set_attr "type" "neon_minmax<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1169,7 +1142,7 @@
fmov\\t%d0, %1
dup\\t%d0, %1"
[(set_attr "v8type" "*,fmov,*")
- (set_attr "type" "*,fmov,*")
+ (set_attr "type" "neon_dup<q>,fmov,neon_dup<q>")
(set_attr "simd_type" "simd_dup,*,simd_dup")
(set_attr "simd_mode" "<MODE>")
(set_attr "simd" "yes,*,yes")
@@ -1191,6 +1164,7 @@
ins\\t%0.d[1], %1.d[0]
ins\\t%0.d[1], %1"
[(set_attr "simd_type" "simd_ins,simd_ins")
+ (set_attr "type" "neon_ins")
(set_attr "simd_mode" "<MODE>")
(set_attr "length" "4")]
)
@@ -1215,6 +1189,7 @@
"TARGET_SIMD"
"xtn\\t%0.<Vntype>, %1.<Vtype>"
[(set_attr "simd_type" "simd_shiftn_imm")
+ (set_attr "type" "neon_shift_imm_narrow_q")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1242,6 +1217,7 @@
"TARGET_SIMD"
"xtn\\t%0.<Vntype>, %1.<Vtype>\;xtn2\\t%0.<V2ntype>, %2.<Vtype>"
[(set_attr "simd_type" "simd_shiftn2_imm")
+ (set_attr "type" "multiple")
(set_attr "simd_mode" "<MODE>")
(set_attr "length" "8")]
)
@@ -1257,6 +1233,7 @@
"TARGET_SIMD"
"<su>shll %0.<Vwtype>, %1.<Vhalftype>, 0"
[(set_attr "simd_type" "simd_shiftl_imm")
+ (set_attr "type" "neon_shift_imm_long")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1269,6 +1246,7 @@
"TARGET_SIMD"
"<su>shll2 %0.<Vwtype>, %1.<Vtype>, 0"
[(set_attr "simd_type" "simd_shiftl_imm")
+ (set_attr "type" "neon_shift_imm_long")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1312,6 +1290,7 @@
"TARGET_SIMD"
"<su>mlal\t%0.<Vwtype>, %2.<Vhalftype>, %4.<Vhalftype>"
[(set_attr "simd_type" "simd_mlal")
+ (set_attr "type" "neon_mla_<Vetype>_long")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1329,6 +1308,7 @@
"TARGET_SIMD"
"<su>mlal2\t%0.<Vwtype>, %2.<Vtype>, %4.<Vtype>"
[(set_attr "simd_type" "simd_mlal")
+ (set_attr "type" "neon_mla_<Vetype>_long")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1346,6 +1326,7 @@
"TARGET_SIMD"
"<su>mlsl\t%0.<Vwtype>, %2.<Vhalftype>, %4.<Vhalftype>"
[(set_attr "simd_type" "simd_mlal")
+ (set_attr "type" "neon_mla_<Vetype>_long")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1363,6 +1344,7 @@
"TARGET_SIMD"
"<su>mlsl2\t%0.<Vwtype>, %2.<Vtype>, %4.<Vtype>"
[(set_attr "simd_type" "simd_mlal")
+ (set_attr "type" "neon_mla_<Vetype>_long")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1378,6 +1360,7 @@
"TARGET_SIMD"
"<su>mlal\t%0.<Vwtype>, %1.<Vtype>, %2.<Vtype>"
[(set_attr "simd_type" "simd_mlal")
+ (set_attr "type" "neon_mla_<Vetype>_long")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1393,6 +1376,7 @@
"TARGET_SIMD"
"<su>mlsl\t%0.<Vwtype>, %2.<Vtype>, %3.<Vtype>"
[(set_attr "simd_type" "simd_mlal")
+ (set_attr "type" "neon_mla_<Vetype>_long")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1407,6 +1391,7 @@
"TARGET_SIMD"
"<su>mull\\t%0.<Vwtype>, %1.<Vhalftype>, %2.<Vhalftype>"
[(set_attr "simd_type" "simd_mull")
+ (set_attr "type" "neon_mul_<Vetype>_long")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1435,6 +1420,7 @@
"TARGET_SIMD"
"<su>mull2\\t%0.<Vwtype>, %1.<Vtype>, %2.<Vtype>"
[(set_attr "simd_type" "simd_mull")
+ (set_attr "type" "neon_mul_<Vetype>_long")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1485,6 +1471,7 @@
"TARGET_SIMD"
"fadd\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
[(set_attr "simd_type" "simd_fadd")
+ (set_attr "type" "neon_fp_addsub_<Vetype><q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1495,6 +1482,7 @@
"TARGET_SIMD"
"fsub\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
[(set_attr "simd_type" "simd_fadd")
+ (set_attr "type" "neon_fp_addsub_<Vetype><q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1505,6 +1493,7 @@
"TARGET_SIMD"
"fmul\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
[(set_attr "simd_type" "simd_fmul")
+ (set_attr "type" "neon_fp_mul_<Vetype><q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1515,6 +1504,7 @@
"TARGET_SIMD"
"fdiv\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
[(set_attr "simd_type" "simd_fdiv")
+ (set_attr "type" "neon_fp_div_<Vetype><q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1524,6 +1514,7 @@
"TARGET_SIMD"
"fneg\\t%0.<Vtype>, %1.<Vtype>"
[(set_attr "simd_type" "simd_fnegabs")
+ (set_attr "type" "neon_fp_neg_<Vetype><q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1533,6 +1524,7 @@
"TARGET_SIMD"
"fabs\\t%0.<Vtype>, %1.<Vtype>"
[(set_attr "simd_type" "simd_fnegabs")
+ (set_attr "type" "neon_fp_abs_<Vetype><q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1544,6 +1536,7 @@
"TARGET_SIMD"
"fmla\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
[(set_attr "simd_type" "simd_fmla")
+ (set_attr "type" "neon_fp_mla_<Vetype><q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1559,6 +1552,7 @@
"TARGET_SIMD"
"fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
[(set_attr "simd_type" "simd_fmla_elt")
+ (set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1574,6 +1568,7 @@
"TARGET_SIMD"
"fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
[(set_attr "simd_type" "simd_fmla_elt")
+ (set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1587,6 +1582,7 @@
"TARGET_SIMD"
"fmla\\t%0.2d, %2.2d, %1.2d[0]"
[(set_attr "simd_type" "simd_fmla_elt")
+ (set_attr "type" "neon_fp_mla_d_scalar_q")
(set_attr "simd_mode" "V2DF")]
)
@@ -1601,6 +1597,7 @@
"TARGET_SIMD"
"fmla\\t%0.2d, %3.2d, %1.2d[%2]"
[(set_attr "simd_type" "simd_fmla_elt")
+ (set_attr "type" "neon_fp_mla_d_scalar_q")
(set_attr "simd_mode" "V2DF")]
)
@@ -1614,6 +1611,7 @@
"TARGET_SIMD"
"fmls\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
[(set_attr "simd_type" "simd_fmla")
+ (set_attr "type" "neon_fp_mla_<Vetype><q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1630,6 +1628,7 @@
"TARGET_SIMD"
"fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
[(set_attr "simd_type" "simd_fmla_elt")
+ (set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1646,6 +1645,7 @@
"TARGET_SIMD"
"fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
[(set_attr "simd_type" "simd_fmla_elt")
+ (set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1660,6 +1660,7 @@
"TARGET_SIMD"
"fmls\\t%0.2d, %2.2d, %1.2d[0]"
[(set_attr "simd_type" "simd_fmla_elt")
+ (set_attr "type" "neon_fp_mla_d_scalar_q")
(set_attr "simd_mode" "V2DF")]
)
@@ -1675,6 +1676,7 @@
"TARGET_SIMD"
"fmls\\t%0.2d, %3.2d, %1.2d[%2]"
[(set_attr "simd_type" "simd_fmla_elt")
+ (set_attr "type" "neon_fp_mla_d_scalar_q")
(set_attr "simd_mode" "V2DF")]
)
@@ -1687,6 +1689,7 @@
"TARGET_SIMD"
"frint<frint_suffix>\\t%0.<Vtype>, %1.<Vtype>"
[(set_attr "simd_type" "simd_frint")
+ (set_attr "type" "neon_fp_round_<Vetype><q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1700,6 +1703,7 @@
"TARGET_SIMD"
"fcvt<frint_suffix><su>\\t%0.<Vtype>, %1.<Vtype>"
[(set_attr "simd_type" "simd_fcvti")
+ (set_attr "type" "neon_fp_to_int_<Vetype><q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1733,6 +1737,7 @@
"TARGET_SIMD"
"<su_optab>cvtf\\t%0.<Vtype>, %1.<Vtype>"
[(set_attr "simd_type" "simd_icvtf")
+ (set_attr "type" "neon_int_to_fp_<Vetype><q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1752,6 +1757,7 @@
"TARGET_SIMD"
"fcvtl\\t%0.2d, %1.2s"
[(set_attr "simd_type" "simd_fcvtl")
+ (set_attr "type" "neon_fp_cvt_widen_s")
(set_attr "simd_mode" "V2DF")]
)
@@ -1762,6 +1768,7 @@
"TARGET_SIMD"
"fcvtl\\t%0.2d, %1.2s"
[(set_attr "simd_type" "simd_fcvtl")
+ (set_attr "type" "neon_fp_cvt_widen_s")
(set_attr "simd_mode" "V2DF")]
)
@@ -1775,6 +1782,7 @@
"TARGET_SIMD"
"fcvtl2\\t%0.2d, %1.4s"
[(set_attr "simd_type" "simd_fcvtl")
+ (set_attr "type" "neon_fp_cvt_widen_s")
(set_attr "simd_mode" "V2DF")]
)
@@ -1787,6 +1795,7 @@
"TARGET_SIMD"
"fcvtn\\t%0.2s, %1.2d"
[(set_attr "simd_type" "simd_fcvtl")
+ (set_attr "type" "neon_fp_cvt_narrow_d_q")
(set_attr "simd_mode" "V2SF")]
)
@@ -1799,6 +1808,7 @@
"TARGET_SIMD"
"fcvtn2\\t%0.4s, %2.2d"
[(set_attr "simd_type" "simd_fcvtl")
+ (set_attr "type" "neon_fp_cvt_narrow_d_q")
(set_attr "simd_mode" "V4SF")]
)
@@ -1846,6 +1856,7 @@
"TARGET_SIMD"
"fmls\\t%0.<Vtype>, %2.<Vtype>, %3.<Vtype>"
[(set_attr "simd_type" "simd_fmla")
+ (set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1870,6 +1881,7 @@
"TARGET_SIMD"
"f<maxmin>nm\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
[(set_attr "simd_type" "simd_fminmax")
+ (set_attr "type" "neon_fp_minmax_<Vetype><q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1881,6 +1893,7 @@
"TARGET_SIMD"
"<maxmin_uns_op>\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
[(set_attr "simd_type" "simd_fminmax")
+ (set_attr "type" "neon_fp_minmax_<Vetype><q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1893,6 +1906,7 @@
"TARGET_SIMD"
"addv\\t%<Vetype>0, %1.<Vtype>"
[(set_attr "simd_type" "simd_addv")
+ (set_attr "type" "neon_reduc_add<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1903,6 +1917,7 @@
"TARGET_SIMD"
"addp\\t%d0, %1.2d"
[(set_attr "simd_type" "simd_addv")
+ (set_attr "type" "neon_reduc_add_q")
(set_attr "simd_mode" "V2DI")]
)
@@ -1913,6 +1928,7 @@
"TARGET_SIMD"
"addp\\t%0.2s, %1.2s, %1.2s"
[(set_attr "simd_type" "simd_addv")
+ (set_attr "type" "neon_reduc_add")
(set_attr "simd_mode" "V2SI")]
)
@@ -1923,6 +1939,7 @@
"TARGET_SIMD"
"faddp\\t%<Vetype>0, %1.<Vtype>"
[(set_attr "simd_type" "simd_fadd")
+ (set_attr "type" "neon_fp_reduc_add_<Vetype><q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1933,6 +1950,7 @@
"TARGET_SIMD"
"faddp\\t%0.4s, %1.4s, %1.4s"
[(set_attr "simd_type" "simd_fadd")
+ (set_attr "type" "neon_fp_reduc_add_s_q")
(set_attr "simd_mode" "V4SF")]
)
@@ -1954,6 +1972,7 @@
"TARGET_SIMD"
"clz\\t%0.<Vtype>, %1.<Vtype>"
[(set_attr "simd_type" "simd_cls")
+ (set_attr "type" "neon_cls<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1966,6 +1985,7 @@
"TARGET_SIMD"
"<maxmin_uns_op>v\\t%<Vetype>0, %1.<Vtype>"
[(set_attr "simd_type" "simd_minmaxv")
+ (set_attr "type" "neon_reduc_minmax<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -1976,6 +1996,7 @@
"TARGET_SIMD"
"<maxmin_uns_op>p\\t%d0, %1.2d"
[(set_attr "simd_type" "simd_minmaxv")
+ (set_attr "type" "neon_reduc_minmax_q")
(set_attr "simd_mode" "V2DI")]
)
@@ -1986,6 +2007,7 @@
"TARGET_SIMD"
"<maxmin_uns_op>p\\t%0.2s, %1.2s, %1.2s"
[(set_attr "simd_type" "simd_minmaxv")
+ (set_attr "type" "neon_reduc_minmax")
(set_attr "simd_mode" "V2SI")]
)
@@ -1996,6 +2018,7 @@
"TARGET_SIMD"
"<maxmin_uns_op>p\\t%<Vetype>0, %1.<Vtype>"
[(set_attr "simd_type" "simd_fminmaxv")
+ (set_attr "type" "neon_fp_reduc_minmax_<Vetype><q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -2006,6 +2029,7 @@
"TARGET_SIMD"
"<maxmin_uns_op>v\\t%s0, %1.4s"
[(set_attr "simd_type" "simd_fminmaxv")
+ (set_attr "type" "neon_fp_reduc_minmax_s_q")
(set_attr "simd_mode" "V4SF")]
)
@@ -2041,6 +2065,8 @@
bsl\\t%0.<Vbtype>, %2.<Vbtype>, %3.<Vbtype>
bit\\t%0.<Vbtype>, %2.<Vbtype>, %1.<Vbtype>
bif\\t%0.<Vbtype>, %3.<Vbtype>, %1.<Vbtype>"
+ [(set_attr "simd_mode" "<MODE>")
+ (set_attr "type" "neon_bsl<q>")]
)
(define_expand "aarch64_simd_bsl<mode>"
@@ -2406,6 +2432,7 @@
"TARGET_SIMD"
"smov\\t%<GPI:w>0, %1.<VDQQH:Vetype>[%2]"
[(set_attr "simd_type" "simd_movgp")
+ (set_attr "type" "neon_to_gp<q>")
(set_attr "simd_mode" "<VDQQH:MODE>")]
)
@@ -2418,6 +2445,7 @@
"TARGET_SIMD"
"umov\\t%w0, %1.<Vetype>[%2]"
[(set_attr "simd_type" "simd_movgp")
+ (set_attr "type" "neon_to_gp<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -2433,6 +2461,7 @@
umov\\t%<vwcore>0, %1.<Vetype>[%2]
dup\\t%<Vetype>0, %1.<Vetype>[%2]"
[(set_attr "simd_type" "simd_movgp, simd_dup")
+ (set_attr "type" "neon_to_gp<q>, neon_dup<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -2557,6 +2586,7 @@
"TARGET_SIMD"
"mov\\t%0.8b, %1.8b"
[(set_attr "simd_type" "simd_move")
+ (set_attr "type" "neon_move<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -2571,7 +2601,9 @@
{
aarch64_split_simd_combine (operands[0], operands[1], operands[2]);
DONE;
-})
+}
+[(set_attr "type" "multiple")]
+)
(define_expand "aarch64_simd_combine<mode>"
[(set (match_operand:<VDBL> 0 "register_operand" "=&w")
@@ -2582,11 +2614,13 @@
emit_insn (gen_move_lo_quad_<Vdbl> (operands[0], operands[1]));
emit_insn (gen_move_hi_quad_<Vdbl> (operands[0], operands[2]));
DONE;
- })
+ }
+[(set_attr "type" "multiple")]
+)
;; <su><addsub>l<q>.
-(define_insn "aarch64_<ANY_EXTEND:su><ADDSUB:optab>l2<mode>_internal"
+(define_insn "aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>_hi_internal"
[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
(ADDSUB:<VWIDE> (ANY_EXTEND:<VWIDE> (vec_select:<VHALF>
(match_operand:VQW 1 "register_operand" "w")
@@ -2595,11 +2629,28 @@
(match_operand:VQW 2 "register_operand" "w")
(match_dup 3)))))]
"TARGET_SIMD"
- "<ANY_EXTEND:su><ADDSUB:optab>l2 %0.<Vwtype>, %1.<Vtype>, %2.<Vtype>"
+ "<ANY_EXTEND:su><ADDSUB:optab>l2\t%0.<Vwtype>, %1.<Vtype>, %2.<Vtype>"
+ [(set_attr "simd_type" "simd_addl")
+ (set_attr "type" "neon_<ADDSUB:optab>_long")
+ (set_attr "simd_mode" "<MODE>")]
+)
+
+(define_insn "aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>_lo_internal"
+ [(set (match_operand:<VWIDE> 0 "register_operand" "=w")
+ (ADDSUB:<VWIDE> (ANY_EXTEND:<VWIDE> (vec_select:<VHALF>
+ (match_operand:VQW 1 "register_operand" "w")
+ (match_operand:VQW 3 "vect_par_cnst_lo_half" "")))
+ (ANY_EXTEND:<VWIDE> (vec_select:<VHALF>
+ (match_operand:VQW 2 "register_operand" "w")
+ (match_dup 3)))))]
+ "TARGET_SIMD"
+ "<ANY_EXTEND:su><ADDSUB:optab>l\t%0.<Vwtype>, %1.<Vhalftype>, %2.<Vhalftype>"
[(set_attr "simd_type" "simd_addl")
+ (set_attr "type" "neon_<ADDSUB:optab>_long")
(set_attr "simd_mode" "<MODE>")]
)
+
(define_expand "aarch64_saddl2<mode>"
[(match_operand:<VWIDE> 0 "register_operand" "=w")
(match_operand:VQW 1 "register_operand" "w")
@@ -2607,8 +2658,8 @@
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
- emit_insn (gen_aarch64_saddl2<mode>_internal (operands[0], operands[1],
- operands[2], p));
+ emit_insn (gen_aarch64_saddl<mode>_hi_internal (operands[0], operands[1],
+ operands[2], p));
DONE;
})
@@ -2619,8 +2670,8 @@
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
- emit_insn (gen_aarch64_uaddl2<mode>_internal (operands[0], operands[1],
- operands[2], p));
+ emit_insn (gen_aarch64_uaddl<mode>_hi_internal (operands[0], operands[1],
+ operands[2], p));
DONE;
})
@@ -2631,7 +2682,7 @@
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
- emit_insn (gen_aarch64_ssubl2<mode>_internal (operands[0], operands[1],
+ emit_insn (gen_aarch64_ssubl<mode>_hi_internal (operands[0], operands[1],
operands[2], p));
DONE;
})
@@ -2643,7 +2694,7 @@
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
- emit_insn (gen_aarch64_usubl2<mode>_internal (operands[0], operands[1],
+ emit_insn (gen_aarch64_usubl<mode>_hi_internal (operands[0], operands[1],
operands[2], p));
DONE;
})
@@ -2657,6 +2708,7 @@
"TARGET_SIMD"
"<ANY_EXTEND:su><ADDSUB:optab>l %0.<Vwtype>, %1.<Vtype>, %2.<Vtype>"
[(set_attr "simd_type" "simd_addl")
+ (set_attr "type" "neon_<ADDSUB:optab>_long")
(set_attr "simd_mode" "<MODE>")]
)
@@ -2670,6 +2722,7 @@
"TARGET_SIMD"
"<ANY_EXTEND:su><ADDSUB:optab>w\\t%0.<Vwtype>, %1.<Vwtype>, %2.<Vtype>"
[(set_attr "simd_type" "simd_addl")
+ (set_attr "type" "neon_<ADDSUB:optab>_widen")
(set_attr "simd_mode" "<MODE>")]
)
@@ -2683,6 +2736,7 @@
"TARGET_SIMD"
"<ANY_EXTEND:su><ADDSUB:optab>w2\\t%0.<Vwtype>, %1.<Vwtype>, %2.<Vtype>"
[(set_attr "simd_type" "simd_addl")
+ (set_attr "type" "neon_<ADDSUB:optab>_widen")
(set_attr "simd_mode" "<MODE>")]
)
@@ -2745,6 +2799,7 @@
"TARGET_SIMD"
"<sur>h<addsub>\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
[(set_attr "simd_type" "simd_add")
+ (set_attr "type" "neon_<addsub>_halve<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -2758,6 +2813,7 @@
"TARGET_SIMD"
"<sur><addsub>hn\\t%0.<Vntype>, %1.<Vtype>, %2.<Vtype>"
[(set_attr "simd_type" "simd_addn")
+ (set_attr "type" "neon_<addsub>_halve_narrow_q")
(set_attr "simd_mode" "<MODE>")]
)
@@ -2770,6 +2826,7 @@
"TARGET_SIMD"
"<sur><addsub>hn2\\t%0.<V2ntype>, %2.<Vtype>, %3.<Vtype>"
[(set_attr "simd_type" "simd_addn2")
+ (set_attr "type" "neon_<addsub>_halve_narrow_q")
(set_attr "simd_mode" "<MODE>")]
)
@@ -2783,6 +2840,7 @@
"TARGET_SIMD"
"pmul\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
[(set_attr "simd_type" "simd_mul")
+ (set_attr "type" "neon_mul_<Vetype><q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -2795,6 +2853,7 @@
"TARGET_SIMD"
"<su_optab><optab>\\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>"
[(set_attr "simd_type" "simd_add")
+ (set_attr "type" "neon_<optab><q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -2808,6 +2867,7 @@
"TARGET_SIMD"
"<sur>qadd\\t%<v>0<Vmtype>, %<v>2<Vmtype>"
[(set_attr "simd_type" "simd_sat_add")
+ (set_attr "type" "neon_qadd<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -2820,6 +2880,7 @@
"TARGET_SIMD"
"sqxtun\\t%<vn2>0<Vmntype>, %<v>1<Vmtype>"
[(set_attr "simd_type" "simd_sat_shiftn_imm")
+ (set_attr "type" "neon_sat_shift_imm_narrow_q")
(set_attr "simd_mode" "<MODE>")]
)
@@ -2832,6 +2893,7 @@
"TARGET_SIMD"
"<sur>qxtn\\t%<vn2>0<Vmntype>, %<v>1<Vmtype>"
[(set_attr "simd_type" "simd_sat_shiftn_imm")
+ (set_attr "type" "neon_sat_shift_imm_narrow_q")
(set_attr "simd_mode" "<MODE>")]
)
@@ -2844,6 +2906,7 @@
"TARGET_SIMD"
"s<optab>\\t%<v>0<Vmtype>, %<v>1<Vmtype>"
[(set_attr "simd_type" "simd_sat_negabs")
+ (set_attr "type" "neon_<optab><q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -2858,6 +2921,7 @@
"TARGET_SIMD"
"sq<r>dmulh\\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>"
[(set_attr "simd_type" "simd_sat_mul")
+ (set_attr "type" "neon_sat_mul_<Vetype><q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -2876,6 +2940,7 @@
aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCOND>mode));
return \"sq<r>dmulh\\t%0.<Vtype>, %1.<Vtype>, %2.<Vetype>[%3]\";"
[(set_attr "simd_type" "simd_sat_mul")
+ (set_attr "type" "neon_sat_mul_<Vetype>_scalar<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -2892,6 +2957,7 @@
aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCONQ>mode));
return \"sq<r>dmulh\\t%0.<Vtype>, %1.<Vtype>, %2.<Vetype>[%3]\";"
[(set_attr "simd_type" "simd_sat_mul")
+ (set_attr "type" "neon_sat_mul_<Vetype>_scalar<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -2908,6 +2974,7 @@
aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCONQ>mode));
return \"sq<r>dmulh\\t%<v>0, %<v>1, %2.<v>[%3]\";"
[(set_attr "simd_type" "simd_sat_mul")
+ (set_attr "type" "neon_sat_mul_<Vetype>_scalar<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -2927,6 +2994,7 @@
"TARGET_SIMD"
"sqdml<SBINQOPS:as>l\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %<v>3<Vmtype>"
[(set_attr "simd_type" "simd_sat_mlal")
+ (set_attr "type" "neon_sat_mla_<Vetype>_long")
(set_attr "simd_mode" "<MODE>")]
)
@@ -2950,6 +3018,7 @@
"TARGET_SIMD"
"sqdml<SBINQOPS:as>l\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]"
[(set_attr "simd_type" "simd_sat_mlal")
+ (set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")
(set_attr "simd_mode" "<MODE>")]
)
@@ -2970,6 +3039,7 @@
"TARGET_SIMD"
"sqdml<SBINQOPS:as>l\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]"
[(set_attr "simd_type" "simd_sat_mlal")
+ (set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")
(set_attr "simd_mode" "<MODE>")]
)
@@ -3050,6 +3120,7 @@
"TARGET_SIMD"
"sqdml<SBINQOPS:as>l\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[0]"
[(set_attr "simd_type" "simd_sat_mlal")
+ (set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")
(set_attr "simd_mode" "<MODE>")]
)
@@ -3073,6 +3144,7 @@
"TARGET_SIMD"
"sqdml<SBINQOPS:as>l2\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %<v>3<Vmtype>"
[(set_attr "simd_type" "simd_sat_mlal")
+ (set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")
(set_attr "simd_mode" "<MODE>")]
)
@@ -3124,6 +3196,7 @@
"TARGET_SIMD"
"sqdml<SBINQOPS:as>l2\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]"
[(set_attr "simd_type" "simd_sat_mlal")
+ (set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")
(set_attr "simd_mode" "<MODE>")]
)
@@ -3208,6 +3281,7 @@
"TARGET_SIMD"
"sqdml<SBINQOPS:as>l2\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[0]"
[(set_attr "simd_type" "simd_sat_mlal")
+ (set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")
(set_attr "simd_mode" "<MODE>")]
)
@@ -3253,6 +3327,7 @@
"TARGET_SIMD"
"sqdmull\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %<v>2<Vmtype>"
[(set_attr "simd_type" "simd_sat_mul")
+ (set_attr "type" "neon_sat_mul_<Vetype>_long")
(set_attr "simd_mode" "<MODE>")]
)
@@ -3274,6 +3349,7 @@
"TARGET_SIMD"
"sqdmull\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]"
[(set_attr "simd_type" "simd_sat_mul")
+ (set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")
(set_attr "simd_mode" "<MODE>")]
)
@@ -3292,6 +3368,7 @@
"TARGET_SIMD"
"sqdmull\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]"
[(set_attr "simd_type" "simd_sat_mul")
+ (set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")
(set_attr "simd_mode" "<MODE>")]
)
@@ -3337,6 +3414,7 @@
"TARGET_SIMD"
"sqdmull\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[0]"
[(set_attr "simd_type" "simd_sat_mul")
+ (set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")
(set_attr "simd_mode" "<MODE>")]
)
@@ -3361,6 +3439,7 @@
"TARGET_SIMD"
"sqdmull2\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %<v>2<Vmtype>"
[(set_attr "simd_type" "simd_sat_mul")
+ (set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")
(set_attr "simd_mode" "<MODE>")]
)
@@ -3396,6 +3475,7 @@
"TARGET_SIMD"
"sqdmull2\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]"
[(set_attr "simd_type" "simd_sat_mul")
+ (set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")
(set_attr "simd_mode" "<MODE>")]
)
@@ -3447,6 +3527,7 @@
"TARGET_SIMD"
"sqdmull2\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[0]"
[(set_attr "simd_type" "simd_sat_mul")
+ (set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")
(set_attr "simd_mode" "<MODE>")]
)
@@ -3473,6 +3554,7 @@
"TARGET_SIMD"
"<sur>shl\\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>";
[(set_attr "simd_type" "simd_shift")
+ (set_attr "type" "neon_shift_reg<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -3488,6 +3570,7 @@
"TARGET_SIMD"
"<sur>q<r>shl\\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>";
[(set_attr "simd_type" "simd_sat_shift")
+ (set_attr "type" "neon_sat_shift_reg<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -3510,6 +3593,7 @@
return \"<sur>shll\\t%0.<Vwtype>, %1.<Vtype>, %2\";
}"
[(set_attr "simd_type" "simd_shift_imm")
+ (set_attr "type" "neon_shift_imm_long")
(set_attr "simd_mode" "<MODE>")]
)
@@ -3532,6 +3616,7 @@
return \"<sur>shll2\\t%0.<Vwtype>, %1.<Vtype>, %2\";
}"
[(set_attr "simd_type" "simd_shift_imm")
+ (set_attr "type" "neon_shift_imm_long")
(set_attr "simd_mode" "<MODE>")]
)
@@ -3548,6 +3633,7 @@
aarch64_simd_const_bounds (operands[2], 1, bit_width + 1);
return \"<sur>shr\\t%<v>0<Vmtype>, %<v>1<Vmtype>, %2\";"
[(set_attr "simd_type" "simd_shift_imm")
+ (set_attr "type" "neon_sat_shift_imm<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -3565,6 +3651,7 @@
aarch64_simd_const_bounds (operands[3], 1, bit_width + 1);
return \"<sur>sra\\t%<v>0<Vmtype>, %<v>2<Vmtype>, %3\";"
[(set_attr "simd_type" "simd_shift_imm_acc")
+ (set_attr "type" "neon_shift_acc<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -3583,6 +3670,7 @@
bit_width - <VSLRI:offsetlr> + 1);
return \"s<lr>i\\t%<v>0<Vmtype>, %<v>2<Vmtype>, %3\";"
[(set_attr "simd_type" "simd_shift_imm")
+ (set_attr "type" "neon_shift_imm<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -3599,6 +3687,7 @@
aarch64_simd_const_bounds (operands[2], 0, bit_width);
return \"<sur>qshl<u>\\t%<v>0<Vmtype>, %<v>1<Vmtype>, %2\";"
[(set_attr "simd_type" "simd_sat_shift_imm")
+ (set_attr "type" "neon_sat_shift_imm<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -3616,6 +3705,7 @@
aarch64_simd_const_bounds (operands[2], 1, bit_width + 1);
return \"<sur>q<r>shr<u>n\\t%<vn2>0<Vmntype>, %<v>1<Vmtype>, %2\";"
[(set_attr "simd_type" "simd_sat_shiftn_imm")
+ (set_attr "type" "neon_sat_shift_imm_narrow_q")
(set_attr "simd_mode" "<MODE>")]
)
@@ -3636,6 +3726,7 @@
cm<n_optab>\t%<v>0<Vmtype>, %<v><cmp_1><Vmtype>, %<v><cmp_2><Vmtype>
cm<optab>\t%<v>0<Vmtype>, %<v>1<Vmtype>, #0"
[(set_attr "simd_type" "simd_cmp")
+ (set_attr "type" "neon_compare<q>, neon_compare_zero<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -3666,6 +3757,7 @@
DONE;
}
[(set_attr "simd_type" "simd_cmp")
+ (set_attr "type" "neon_compare, neon_compare_zero, multiple")
(set_attr "simd_mode" "DI")]
)
@@ -3681,6 +3773,7 @@
"TARGET_SIMD"
"cm<n_optab>\t%<v>0<Vmtype>, %<v><cmp_1><Vmtype>, %<v><cmp_2><Vmtype>"
[(set_attr "simd_type" "simd_cmp")
+ (set_attr "type" "neon_compare<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -3710,6 +3803,7 @@
DONE;
}
[(set_attr "simd_type" "simd_cmp")
+ (set_attr "type" "neon_compare, neon_compare_zero")
(set_attr "simd_mode" "DI")]
)
@@ -3726,6 +3820,7 @@
"TARGET_SIMD"
"cmtst\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>"
[(set_attr "simd_type" "simd_cmp")
+ (set_attr "type" "neon_tst<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -3757,6 +3852,7 @@
DONE;
}
[(set_attr "simd_type" "simd_cmp")
+ (set_attr "type" "neon_tst")
(set_attr "simd_mode" "DI")]
)
@@ -3774,6 +3870,7 @@
fcm<n_optab>\t%<v>0<Vmtype>, %<v><cmp_1><Vmtype>, %<v><cmp_2><Vmtype>
fcm<optab>\t%<v>0<Vmtype>, %<v>1<Vmtype>, 0"
[(set_attr "simd_type" "simd_fcmp")
+ (set_attr "type" "neon_fp_compare_<Vetype><q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -3791,6 +3888,7 @@
"TARGET_SIMD"
"fac<n_optab>\t%<v>0<Vmtype>, %<v><cmp_1><Vmtype>, %<v><cmp_2><Vmtype>"
[(set_attr "simd_type" "simd_fcmp")
+ (set_attr "type" "neon_fp_compare_<Vetype><q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -3805,6 +3903,7 @@
"TARGET_SIMD"
"addp\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>"
[(set_attr "simd_type" "simd_add")
+ (set_attr "type" "neon_reduc_add<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -3816,6 +3915,7 @@
"TARGET_SIMD"
"addp\t%d0, %1.2d"
[(set_attr "simd_type" "simd_add")
+ (set_attr "type" "neon_reduc_add")
(set_attr "simd_mode" "DI")]
)
@@ -3827,6 +3927,7 @@
"TARGET_SIMD"
"fsqrt\\t%0.<Vtype>, %1.<Vtype>"
[(set_attr "simd_type" "simd_fsqrt")
+ (set_attr "type" "neon_fp_sqrt_<Vetype><q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -3840,6 +3941,7 @@
"TARGET_SIMD"
"ld2\\t{%S0.<Vtype> - %T0.<Vtype>}, %1"
[(set_attr "simd_type" "simd_load2")
+ (set_attr "type" "neon_load2_2reg<q>")
(set_attr "simd_mode" "<MODE>")])
(define_insn "vec_store_lanesoi<mode>"
@@ -3850,6 +3952,7 @@
"TARGET_SIMD"
"st2\\t{%S1.<Vtype> - %T1.<Vtype>}, %0"
[(set_attr "simd_type" "simd_store2")
+ (set_attr "type" "neon_store2_2reg<q>")
(set_attr "simd_mode" "<MODE>")])
(define_insn "vec_load_lanesci<mode>"
@@ -3860,6 +3963,7 @@
"TARGET_SIMD"
"ld3\\t{%S0.<Vtype> - %U0.<Vtype>}, %1"
[(set_attr "simd_type" "simd_load3")
+ (set_attr "type" "neon_load3_3reg<q>")
(set_attr "simd_mode" "<MODE>")])
(define_insn "vec_store_lanesci<mode>"
@@ -3870,6 +3974,7 @@
"TARGET_SIMD"
"st3\\t{%S1.<Vtype> - %U1.<Vtype>}, %0"
[(set_attr "simd_type" "simd_store3")
+ (set_attr "type" "neon_store3_3reg<q>")
(set_attr "simd_mode" "<MODE>")])
(define_insn "vec_load_lanesxi<mode>"
@@ -3880,6 +3985,7 @@
"TARGET_SIMD"
"ld4\\t{%S0.<Vtype> - %V0.<Vtype>}, %1"
[(set_attr "simd_type" "simd_load4")
+ (set_attr "type" "neon_load4_4reg<q>")
(set_attr "simd_mode" "<MODE>")])
(define_insn "vec_store_lanesxi<mode>"
@@ -3890,6 +3996,7 @@
"TARGET_SIMD"
"st4\\t{%S1.<Vtype> - %V1.<Vtype>}, %0"
[(set_attr "simd_type" "simd_store4")
+ (set_attr "type" "neon_store4_4reg<q>")
(set_attr "simd_mode" "<MODE>")])
;; Reload patterns for AdvSIMD register list operands.
@@ -3923,6 +4030,8 @@
}
}
[(set_attr "simd_type" "simd_move,simd_store<nregs>,simd_load<nregs>")
+ (set_attr "type" "neon_move,neon_store<nregs>_<nregs>reg_q,\
+ neon_load<nregs>_<nregs>reg_q")
(set (attr "length") (symbol_ref "aarch64_simd_attr_length_move (insn)"))
(set_attr "simd_mode" "<MODE>")])
@@ -4007,6 +4116,7 @@
"TARGET_SIMD"
"ld2\\t{%S0.<Vtype> - %T0.<Vtype>}, %1"
[(set_attr "simd_type" "simd_load2")
+ (set_attr "type" "neon_load2_2reg<q>")
(set_attr "simd_mode" "<MODE>")])
(define_insn "aarch64_ld2<mode>_dreg"
@@ -4024,6 +4134,7 @@
"TARGET_SIMD"
"ld1\\t{%S0.1d - %T0.1d}, %1"
[(set_attr "simd_type" "simd_load2")
+ (set_attr "type" "neon_load1_2reg<q>")
(set_attr "simd_mode" "<MODE>")])
(define_insn "aarch64_ld3<mode>_dreg"
@@ -4046,6 +4157,7 @@
"TARGET_SIMD"
"ld3\\t{%S0.<Vtype> - %U0.<Vtype>}, %1"
[(set_attr "simd_type" "simd_load3")
+ (set_attr "type" "neon_load3_3reg<q>")
(set_attr "simd_mode" "<MODE>")])
(define_insn "aarch64_ld3<mode>_dreg"
@@ -4068,6 +4180,7 @@
"TARGET_SIMD"
"ld1\\t{%S0.1d - %U0.1d}, %1"
[(set_attr "simd_type" "simd_load3")
+ (set_attr "type" "neon_load1_3reg<q>")
(set_attr "simd_mode" "<MODE>")])
(define_insn "aarch64_ld4<mode>_dreg"
@@ -4095,6 +4208,7 @@
"TARGET_SIMD"
"ld4\\t{%S0.<Vtype> - %V0.<Vtype>}, %1"
[(set_attr "simd_type" "simd_load4")
+ (set_attr "type" "neon_load4_4reg<q>")
(set_attr "simd_mode" "<MODE>")])
(define_insn "aarch64_ld4<mode>_dreg"
@@ -4122,6 +4236,7 @@
"TARGET_SIMD"
"ld1\\t{%S0.1d - %V0.1d}, %1"
[(set_attr "simd_type" "simd_load4")
+ (set_attr "type" "neon_load1_4reg<q>")
(set_attr "simd_mode" "<MODE>")])
(define_expand "aarch64_ld<VSTRUCT:nregs><VDC:mode>"
@@ -4237,6 +4352,7 @@
"TARGET_SIMD"
"tbl\\t%0.<Vtype>, {%1.16b}, %2.<Vtype>"
[(set_attr "simd_type" "simd_tbl")
+ (set_attr "type" "neon_tbl1<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -4250,6 +4366,7 @@
"TARGET_SIMD"
"tbl\\t%0.16b, {%S1.16b - %T1.16b}, %2.16b"
[(set_attr "simd_type" "simd_tbl")
+ (set_attr "type" "neon_tbl2_q")
(set_attr "simd_mode" "V16QI")]
)
@@ -4265,7 +4382,9 @@
{
aarch64_split_combinev16qi (operands);
DONE;
-})
+}
+[(set_attr "type" "multiple")]
+)
(define_insn "aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>"
[(set (match_operand:VALL 0 "register_operand" "=w")
@@ -4275,6 +4394,7 @@
"TARGET_SIMD"
"<PERMUTE:perm_insn><PERMUTE:perm_hilo>\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
[(set_attr "simd_type" "simd_<PERMUTE:perm_insn>")
+ (set_attr "type" "neon_permute<q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -4286,6 +4406,7 @@
"TARGET_SIMD"
"st2\\t{%S1.<Vtype> - %T1.<Vtype>}, %0"
[(set_attr "simd_type" "simd_store2")
+ (set_attr "type" "neon_store2_2reg")
(set_attr "simd_mode" "<MODE>")])
(define_insn "aarch64_st2<mode>_dreg"
@@ -4296,6 +4417,7 @@
"TARGET_SIMD"
"st1\\t{%S1.1d - %T1.1d}, %0"
[(set_attr "simd_type" "simd_store2")
+ (set_attr "type" "neon_store1_2reg")
(set_attr "simd_mode" "<MODE>")])
(define_insn "aarch64_st3<mode>_dreg"
@@ -4306,6 +4428,7 @@
"TARGET_SIMD"
"st3\\t{%S1.<Vtype> - %U1.<Vtype>}, %0"
[(set_attr "simd_type" "simd_store3")
+ (set_attr "type" "neon_store3_3reg")
(set_attr "simd_mode" "<MODE>")])
(define_insn "aarch64_st3<mode>_dreg"
@@ -4316,6 +4439,7 @@
"TARGET_SIMD"
"st1\\t{%S1.1d - %U1.1d}, %0"
[(set_attr "simd_type" "simd_store3")
+ (set_attr "type" "neon_store1_3reg")
(set_attr "simd_mode" "<MODE>")])
(define_insn "aarch64_st4<mode>_dreg"
@@ -4326,6 +4450,7 @@
"TARGET_SIMD"
"st4\\t{%S1.<Vtype> - %V1.<Vtype>}, %0"
[(set_attr "simd_type" "simd_store4")
+ (set_attr "type" "neon_store4_4reg")
(set_attr "simd_mode" "<MODE>")])
(define_insn "aarch64_st4<mode>_dreg"
@@ -4336,6 +4461,7 @@
"TARGET_SIMD"
"st1\\t{%S1.1d - %V1.1d}, %0"
[(set_attr "simd_type" "simd_store4")
+ (set_attr "type" "neon_store1_4reg")
(set_attr "simd_mode" "<MODE>")])
(define_expand "aarch64_st<VSTRUCT:nregs><VDC:mode>"
@@ -4415,6 +4541,7 @@
"TARGET_SIMD"
"ld1r\\t{%0.<Vtype>}, %1"
[(set_attr "simd_type" "simd_load1r")
+ (set_attr "type" "neon_load1_all_lanes")
(set_attr "simd_mode" "<MODE>")])
(define_insn "aarch64_frecpe<mode>"
@@ -4424,6 +4551,7 @@
"TARGET_SIMD"
"frecpe\\t%0.<Vtype>, %1.<Vtype>"
[(set_attr "simd_type" "simd_frecpe")
+ (set_attr "type" "neon_fp_recpe_<Vetype><q>")
(set_attr "simd_mode" "<MODE>")]
)
@@ -4434,6 +4562,7 @@
"TARGET_SIMD"
"frecp<FRECP:frecp_suffix>\\t%<s>0, %<s>1"
[(set_attr "simd_type" "simd_frecp<FRECP:frecp_suffix>")
+ (set_attr "type" "neon_fp_recp<FRECP:frecp_suffix>_<GPF:Vetype><GPF:q>")
(set_attr "mode" "<MODE>")]
)
@@ -4445,6 +4574,7 @@
"TARGET_SIMD"
"frecps\\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>"
[(set_attr "simd_type" "simd_frecps")
+ (set_attr "type" "neon_fp_recps_<Vetype><q>")
(set_attr "simd_mode" "<MODE>")]
)
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 2df7a6426fd..a0b532ce81e 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -109,6 +109,7 @@ enum aarch64_code_model aarch64_cmodel;
#define TARGET_HAVE_TLS 1
#endif
+static bool aarch64_lra_p (void);
static bool aarch64_composite_type_p (const_tree, enum machine_mode);
static bool aarch64_vfp_is_call_or_return_candidate (enum machine_mode,
const_tree,
@@ -3439,6 +3440,32 @@ aarch64_print_operand (FILE *f, rtx x, char code)
{
switch (code)
{
+ /* An integer or symbol address without a preceding # sign. */
+ case 'c':
+ switch (GET_CODE (x))
+ {
+ case CONST_INT:
+ fprintf (f, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
+ break;
+
+ case SYMBOL_REF:
+ output_addr_const (f, x);
+ break;
+
+ case CONST:
+ if (GET_CODE (XEXP (x, 0)) == PLUS
+ && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
+ {
+ output_addr_const (f, x);
+ break;
+ }
+ /* Fall through. */
+
+ default:
+ output_operand_lossage ("Unsupported operand for code '%c'", code);
+ }
+ break;
+
case 'e':
/* Print the sign/zero-extend size as a character 8->b, 16->h, 32->w. */
{
@@ -3857,13 +3884,6 @@ aarch64_print_operand_address (FILE *f, rtx x)
output_addr_const (f, x);
}
-void
-aarch64_function_profiler (FILE *f ATTRIBUTE_UNUSED,
- int labelno ATTRIBUTE_UNUSED)
-{
- sorry ("function profiling");
-}
-
bool
aarch64_label_mentioned_p (rtx x)
{
@@ -3910,7 +3930,7 @@ aarch64_regno_regclass (unsigned regno)
if (regno == FRAME_POINTER_REGNUM
|| regno == ARG_POINTER_REGNUM)
- return CORE_REGS;
+ return POINTER_REGS;
if (FP_REGNUM_P (regno))
return FP_LO_REGNUM_P (regno) ? FP_LO_REGS : FP_REGS;
@@ -4014,9 +4034,9 @@ aarch64_legitimize_reload_address (rtx *x_p,
/* Reload high part into base reg, leaving the low part
in the mem instruction. */
- x = plus_constant (xmode,
- gen_rtx_PLUS (xmode, XEXP (x, 0), cst),
- low);
+ x = gen_rtx_PLUS (xmode,
+ gen_rtx_PLUS (xmode, XEXP (x, 0), cst),
+ GEN_INT (low));
push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
BASE_REG_CLASS, xmode, VOIDmode, 0, 0,
@@ -4034,20 +4054,6 @@ aarch64_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x,
enum machine_mode mode,
secondary_reload_info *sri)
{
- /* Address expressions of the form PLUS (SP, large_offset) need two
- scratch registers, one for the constant, and one for holding a
- copy of SP, since SP cannot be used on the RHS of an add-reg
- instruction. */
- if (mode == DImode
- && GET_CODE (x) == PLUS
- && XEXP (x, 0) == stack_pointer_rtx
- && CONST_INT_P (XEXP (x, 1))
- && !aarch64_uimm12_shift (INTVAL (XEXP (x, 1))))
- {
- sri->icode = CODE_FOR_reload_sp_immediate;
- return NO_REGS;
- }
-
/* Without the TARGET_SIMD instructions we cannot move a Q register
to a Q register directly. We need a scratch. */
if (REG_P (x) && (mode == TFmode || mode == TImode) && mode == GET_MODE (x)
@@ -4239,9 +4245,18 @@ aarch64_class_max_nregs (reg_class_t regclass, enum machine_mode mode)
static reg_class_t
aarch64_preferred_reload_class (rtx x, reg_class_t regclass)
{
- if (regclass == POINTER_REGS || regclass == STACK_REG)
+ if (regclass == POINTER_REGS)
return GENERAL_REGS;
+ if (regclass == STACK_REG)
+ {
+ if (REG_P(x)
+ && reg_class_subset_p (REGNO_REG_CLASS (REGNO (x)), POINTER_REGS))
+ return regclass;
+
+ return NO_REGS;
+ }
+
/* If it's an integer immediate that MOVI can't handle, then
FP_REGS is not an option, so we return NO_REGS instead. */
if (CONST_INT_P (x) && reg_class_subset_p (regclass, FP_REGS)
@@ -6092,6 +6107,13 @@ aapcs_vfp_sub_candidate (const_tree type, enum machine_mode *modep)
return -1;
}
+/* Return true if we use LRA instead of reload pass. */
+static bool
+aarch64_lra_p (void)
+{
+ return aarch64_lra_flag;
+}
+
/* Return TRUE if the type, as described by TYPE and MODE, is a composite
type as described in AAPCS64 \S 4.3. This includes aggregate, union and
array types. The C99 floating-point complex types are also considered
@@ -7162,10 +7184,10 @@ aarch64_emit_store_exclusive (enum machine_mode mode, rtx bval,
static void
aarch64_emit_unlikely_jump (rtx insn)
{
- rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
+ int very_unlikely = REG_BR_PROB_BASE / 100 - 1;
insn = emit_jump_insn (insn);
- add_reg_note (insn, REG_BR_PROB, very_unlikely);
+ add_int_reg_note (insn, REG_BR_PROB, very_unlikely);
}
/* Expand a compare and swap pattern. */
@@ -8268,6 +8290,9 @@ aarch64_vectorize_vec_perm_const_ok (enum machine_mode vmode,
#undef TARGET_LIBGCC_CMP_RETURN_MODE
#define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
+#undef TARGET_LRA_P
+#define TARGET_LRA_P aarch64_lra_p
+
#undef TARGET_MANGLE_TYPE
#define TARGET_MANGLE_TYPE aarch64_mangle_type
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index d8012f88049..7a80e96385f 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -739,7 +739,7 @@ do { \
: reverse_condition (CODE))
#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
- ((VALUE) = ((MODE) == SImode ? 32 : 64), 2)
+ ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE))
#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
((VALUE) = ((MODE) == SImode ? 32 : 64), 2)
@@ -783,8 +783,22 @@ do { \
#define PRINT_OPERAND_ADDRESS(STREAM, X) \
aarch64_print_operand_address (STREAM, X)
-#define FUNCTION_PROFILER(STREAM, LABELNO) \
- aarch64_function_profiler (STREAM, LABELNO)
+#define MCOUNT_NAME "_mcount"
+
+#define NO_PROFILE_COUNTERS 1
+
+/* Emit rtl for profiling. Output assembler code to FILE
+ to call "_mcount" for profiling a function entry. */
+#define PROFILE_HOOK(LABEL) \
+{ \
+ rtx fun,lr; \
+ lr = get_hard_reg_initial_val (Pmode, LR_REGNUM); \
+ fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME); \
+ emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lr, Pmode); \
+}
+
+/* All the work done in PROFILE_HOOK, but still required. */
+#define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0)
/* For some reason, the Linux headers think they know how to define
these macros. They don't!!! */
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 797c9f422c4..758be47420e 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -789,7 +789,7 @@
case 8:
return "dup\t%0.<Vallxd>, %w1";
case 9:
- return "dup\t%0, %1.<v>[0]";
+ return "dup\t%<Vetype>0, %1.<v>[0]";
default:
gcc_unreachable ();
}
@@ -1033,7 +1033,7 @@
stp\\t%1, %H1, %0"
[(set_attr "v8type" "logic,move2,fmovi2f,fmovf2i,fconst,fconst,fpsimd_load,fpsimd_store,fpsimd_load2,fpsimd_store2")
(set_attr "type" "logic_reg,multiple,f_mcr,f_mrc,fconstd,fconstd,\
- f_loadd,f_stored,neon_ldm_2,neon_stm_2")
+ f_loadd,f_stored,neon_load1_2reg,neon_store1_2reg")
(set_attr "mode" "DF,DF,DF,DF,DF,DF,TF,TF,DF,DF")
(set_attr "length" "4,8,8,8,4,4,4,4,4,4")
(set_attr "fp" "*,*,yes,yes,*,yes,yes,yes,*,*")
@@ -1098,7 +1098,7 @@
GET_MODE_SIZE (<MODE>mode)))"
"ldp\\t%<w>0, %<w>2, %1"
[(set_attr "v8type" "fpsimd_load2")
- (set_attr "type" "neon_ldm_2")
+ (set_attr "type" "neon_load1_2reg<q>")
(set_attr "mode" "<MODE>")]
)
@@ -1115,7 +1115,7 @@
GET_MODE_SIZE (<MODE>mode)))"
"stp\\t%<w>1, %<w>3, %0"
[(set_attr "v8type" "fpsimd_store2")
- (set_attr "type" "neon_stm_2")
+ (set_attr "type" "neon_store1_2reg<q>")
(set_attr "mode" "<MODE>")]
)
@@ -1365,7 +1365,7 @@
(plus:GPI (mult:GPI
(match_operand:GPI 1 "register_operand" "r")
(match_operand:QI 2 "aarch64_pwr_2_<mode>" "n"))
- (match_operand:GPI 3 "register_operand" "rk"))
+ (match_operand:GPI 3 "register_operand" "r"))
(const_int 0)))
(set (match_operand:GPI 0 "register_operand" "=r")
(plus:GPI (mult:GPI (match_dup 1) (match_dup 2))
@@ -1380,7 +1380,7 @@
(define_insn "*subs_mul_imm_<mode>"
[(set (reg:CC_NZ CC_REGNUM)
(compare:CC_NZ
- (minus:GPI (match_operand:GPI 1 "register_operand" "rk")
+ (minus:GPI (match_operand:GPI 1 "register_operand" "r")
(mult:GPI
(match_operand:GPI 2 "register_operand" "r")
(match_operand:QI 3 "aarch64_pwr_2_<mode>" "n")))
@@ -1500,7 +1500,7 @@
)
(define_insn "*add_<shift>_<mode>"
- [(set (match_operand:GPI 0 "register_operand" "=rk")
+ [(set (match_operand:GPI 0 "register_operand" "=r")
(plus:GPI (ASHIFT:GPI (match_operand:GPI 1 "register_operand" "r")
(match_operand:QI 2 "aarch64_shift_imm_<mode>" "n"))
(match_operand:GPI 3 "register_operand" "r")))]
@@ -1513,7 +1513,7 @@
;; zero_extend version of above
(define_insn "*add_<shift>_si_uxtw"
- [(set (match_operand:DI 0 "register_operand" "=rk")
+ [(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
(plus:SI (ASHIFT:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:QI 2 "aarch64_shift_imm_si" "n"))
@@ -1526,7 +1526,7 @@
)
(define_insn "*add_mul_imm_<mode>"
- [(set (match_operand:GPI 0 "register_operand" "=rk")
+ [(set (match_operand:GPI 0 "register_operand" "=r")
(plus:GPI (mult:GPI (match_operand:GPI 1 "register_operand" "r")
(match_operand:QI 2 "aarch64_pwr_2_<mode>" "n"))
(match_operand:GPI 3 "register_operand" "r")))]
@@ -1873,7 +1873,7 @@
)
(define_insn "*sub_<shift>_<mode>"
- [(set (match_operand:GPI 0 "register_operand" "=rk")
+ [(set (match_operand:GPI 0 "register_operand" "=r")
(minus:GPI (match_operand:GPI 3 "register_operand" "r")
(ASHIFT:GPI
(match_operand:GPI 1 "register_operand" "r")
@@ -1887,7 +1887,7 @@
;; zero_extend version of above
(define_insn "*sub_<shift>_si_uxtw"
- [(set (match_operand:DI 0 "register_operand" "=rk")
+ [(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
(minus:SI (match_operand:SI 3 "register_operand" "r")
(ASHIFT:SI
@@ -1901,7 +1901,7 @@
)
(define_insn "*sub_mul_imm_<mode>"
- [(set (match_operand:GPI 0 "register_operand" "=rk")
+ [(set (match_operand:GPI 0 "register_operand" "=r")
(minus:GPI (match_operand:GPI 3 "register_operand" "r")
(mult:GPI
(match_operand:GPI 1 "register_operand" "r")
@@ -1915,7 +1915,7 @@
;; zero_extend version of above
(define_insn "*sub_mul_imm_si_uxtw"
- [(set (match_operand:DI 0 "register_operand" "=rk")
+ [(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
(minus:SI (match_operand:SI 3 "register_operand" "r")
(mult:SI
@@ -3955,38 +3955,6 @@
;; Reload support
;; -------------------------------------------------------------------
-;; Reload SP+imm where imm cannot be handled by a single ADD instruction.
-;; Must load imm into a scratch register and copy SP to the dest reg before
-;; adding, since SP cannot be used as a source register in an ADD
-;; instruction.
-(define_expand "reload_sp_immediate"
- [(parallel [(set (match_operand:DI 0 "register_operand" "=r")
- (match_operand:DI 1 "" ""))
- (clobber (match_operand:TI 2 "register_operand" "=&r"))])]
- ""
- {
- rtx sp = XEXP (operands[1], 0);
- rtx val = XEXP (operands[1], 1);
- unsigned regno = REGNO (operands[2]);
- rtx scratch = operands[1];
- gcc_assert (GET_CODE (operands[1]) == PLUS);
- gcc_assert (sp == stack_pointer_rtx);
- gcc_assert (CONST_INT_P (val));
-
- /* It is possible that one of the registers we got for operands[2]
- might coincide with that of operands[0] (which is why we made
- it TImode). Pick the other one to use as our scratch. */
- if (regno == REGNO (operands[0]))
- regno++;
- scratch = gen_rtx_REG (DImode, regno);
-
- emit_move_insn (scratch, val);
- emit_move_insn (operands[0], sp);
- emit_insn (gen_adddi3 (operands[0], operands[0], scratch));
- DONE;
- }
-)
-
(define_expand "aarch64_reload_mov<mode>"
[(set (match_operand:TX 0 "register_operand" "=w")
(match_operand:TX 1 "register_operand" "w"))
diff --git a/gcc/config/aarch64/aarch64.opt b/gcc/config/aarch64/aarch64.opt
index 8ff6ca12592..3b3e6c3b94d 100644
--- a/gcc/config/aarch64/aarch64.opt
+++ b/gcc/config/aarch64/aarch64.opt
@@ -103,6 +103,10 @@ mabi=
Target RejectNegative Joined Enum(aarch64_abi) Var(aarch64_abi) Init(AARCH64_ABI_DEFAULT)
-mabi=ABI Generate code that conforms to the specified ABI
+mlra
+Target Report Var(aarch64_lra_flag) Init(1) Save
+Use LRA instead of reload (transitional)
+
Enum
Name(aarch64_abi) Type(int)
Known AArch64 ABIs (for use with the -mabi= option):
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index cb5860206a1..15d1ed96584 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -634,6 +634,12 @@ vadd_f32 (float32x2_t __a, float32x2_t __b)
return __a + __b;
}
+__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+vadd_f64 (float64x1_t __a, float64x1_t __b)
+{
+ return __a + __b;
+}
+
__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
vadd_u8 (uint8x8_t __a, uint8x8_t __b)
{
@@ -1204,6 +1210,12 @@ vdiv_f32 (float32x2_t __a, float32x2_t __b)
return __a / __b;
}
+__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+vdiv_f64 (float64x1_t __a, float64x1_t __b)
+{
+ return __a / __b;
+}
+
__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
vdivq_f32 (float32x4_t __a, float32x4_t __b)
{
@@ -1824,6 +1836,12 @@ vsub_f32 (float32x2_t __a, float32x2_t __b)
return __a - __b;
}
+__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+vsub_f64 (float64x1_t __a, float64x1_t __b)
+{
+ return __a - __b;
+}
+
__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
vsub_u8 (uint8x8_t __a, uint8x8_t __b)
{
@@ -5140,138 +5158,6 @@ vclsq_s32 (int32x4_t a)
return result;
}
-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
-vclz_s8 (int8x8_t a)
-{
- int8x8_t result;
- __asm__ ("clz %0.8b,%1.8b"
- : "=w"(result)
- : "w"(a)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
-vclz_s16 (int16x4_t a)
-{
- int16x4_t result;
- __asm__ ("clz %0.4h,%1.4h"
- : "=w"(result)
- : "w"(a)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
-vclz_s32 (int32x2_t a)
-{
- int32x2_t result;
- __asm__ ("clz %0.2s,%1.2s"
- : "=w"(result)
- : "w"(a)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
-vclz_u8 (uint8x8_t a)
-{
- uint8x8_t result;
- __asm__ ("clz %0.8b,%1.8b"
- : "=w"(result)
- : "w"(a)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
-vclz_u16 (uint16x4_t a)
-{
- uint16x4_t result;
- __asm__ ("clz %0.4h,%1.4h"
- : "=w"(result)
- : "w"(a)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
-vclz_u32 (uint32x2_t a)
-{
- uint32x2_t result;
- __asm__ ("clz %0.2s,%1.2s"
- : "=w"(result)
- : "w"(a)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
-vclzq_s8 (int8x16_t a)
-{
- int8x16_t result;
- __asm__ ("clz %0.16b,%1.16b"
- : "=w"(result)
- : "w"(a)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
-vclzq_s16 (int16x8_t a)
-{
- int16x8_t result;
- __asm__ ("clz %0.8h,%1.8h"
- : "=w"(result)
- : "w"(a)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
-vclzq_s32 (int32x4_t a)
-{
- int32x4_t result;
- __asm__ ("clz %0.4s,%1.4s"
- : "=w"(result)
- : "w"(a)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
-vclzq_u8 (uint8x16_t a)
-{
- uint8x16_t result;
- __asm__ ("clz %0.16b,%1.16b"
- : "=w"(result)
- : "w"(a)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
-vclzq_u16 (uint16x8_t a)
-{
- uint16x8_t result;
- __asm__ ("clz %0.8h,%1.8h"
- : "=w"(result)
- : "w"(a)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
-vclzq_u32 (uint32x4_t a)
-{
- uint32x4_t result;
- __asm__ ("clz %0.4s,%1.4s"
- : "=w"(result)
- : "w"(a)
- : /* No clobbers */);
- return result;
-}
-
__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
vcnt_p8 (poly8x8_t a)
{
@@ -5556,7 +5442,7 @@ static float32x2_t vdup_n_f32 (float32_t);
__extension__ \
({ \
int64_t a_ = (a); \
- int64_t result; \
+ float64_t result; \
__asm__ ("scvtf %d0,%d1,%2" \
: "=w"(result) \
: "w"(a_), "i"(b) \
@@ -5568,7 +5454,7 @@ static float32x2_t vdup_n_f32 (float32_t);
__extension__ \
({ \
uint64_t a_ = (a); \
- uint64_t result; \
+ float64_t result; \
__asm__ ("ucvtf %d0,%d1,%2" \
: "=w"(result) \
: "w"(a_), "i"(b) \
@@ -5580,7 +5466,7 @@ static float32x2_t vdup_n_f32 (float32_t);
__extension__ \
({ \
float64_t a_ = (a); \
- float64_t result; \
+ int64_t result; \
__asm__ ("fcvtzs %d0,%d1,%2" \
: "=w"(result) \
: "w"(a_), "i"(b) \
@@ -5592,7 +5478,7 @@ static float32x2_t vdup_n_f32 (float32_t);
__extension__ \
({ \
float64_t a_ = (a); \
- float64_t result; \
+ uint64_t result; \
__asm__ ("fcvtzu %d0,%d1,%2" \
: "=w"(result) \
: "w"(a_), "i"(b) \
@@ -5700,7 +5586,7 @@ static float32x2_t vdup_n_f32 (float32_t);
__extension__ \
({ \
int32_t a_ = (a); \
- int32_t result; \
+ float32_t result; \
__asm__ ("scvtf %s0,%s1,%2" \
: "=w"(result) \
: "w"(a_), "i"(b) \
@@ -5712,7 +5598,7 @@ static float32x2_t vdup_n_f32 (float32_t);
__extension__ \
({ \
uint32_t a_ = (a); \
- uint32_t result; \
+ float32_t result; \
__asm__ ("ucvtf %s0,%s1,%2" \
: "=w"(result) \
: "w"(a_), "i"(b) \
@@ -5724,7 +5610,7 @@ static float32x2_t vdup_n_f32 (float32_t);
__extension__ \
({ \
float32_t a_ = (a); \
- float32_t result; \
+ int32_t result; \
__asm__ ("fcvtzs %s0,%s1,%2" \
: "=w"(result) \
: "w"(a_), "i"(b) \
@@ -5736,7 +5622,7 @@ static float32x2_t vdup_n_f32 (float32_t);
__extension__ \
({ \
float32_t a_ = (a); \
- float32_t result; \
+ uint32_t result; \
__asm__ ("fcvtzu %s0,%s1,%2" \
: "=w"(result) \
: "w"(a_), "i"(b) \
@@ -9785,115 +9671,6 @@ vmvnq_u32 (uint32x4_t a)
return result;
}
-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
-vneg_f32 (float32x2_t a)
-{
- float32x2_t result;
- __asm__ ("fneg %0.2s,%1.2s"
- : "=w"(result)
- : "w"(a)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
-vneg_s8 (int8x8_t a)
-{
- int8x8_t result;
- __asm__ ("neg %0.8b,%1.8b"
- : "=w"(result)
- : "w"(a)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
-vneg_s16 (int16x4_t a)
-{
- int16x4_t result;
- __asm__ ("neg %0.4h,%1.4h"
- : "=w"(result)
- : "w"(a)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
-vneg_s32 (int32x2_t a)
-{
- int32x2_t result;
- __asm__ ("neg %0.2s,%1.2s"
- : "=w"(result)
- : "w"(a)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
-vnegq_f32 (float32x4_t a)
-{
- float32x4_t result;
- __asm__ ("fneg %0.4s,%1.4s"
- : "=w"(result)
- : "w"(a)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
-vnegq_f64 (float64x2_t a)
-{
- float64x2_t result;
- __asm__ ("fneg %0.2d,%1.2d"
- : "=w"(result)
- : "w"(a)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
-vnegq_s8 (int8x16_t a)
-{
- int8x16_t result;
- __asm__ ("neg %0.16b,%1.16b"
- : "=w"(result)
- : "w"(a)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
-vnegq_s16 (int16x8_t a)
-{
- int16x8_t result;
- __asm__ ("neg %0.8h,%1.8h"
- : "=w"(result)
- : "w"(a)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
-vnegq_s32 (int32x4_t a)
-{
- int32x4_t result;
- __asm__ ("neg %0.4s,%1.4s"
- : "=w"(result)
- : "w"(a)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
-vnegq_s64 (int64x2_t a)
-{
- int64x2_t result;
- __asm__ ("neg %0.2d,%1.2d"
- : "=w"(result)
- : "w"(a)
- : /* No clobbers */);
- return result;
-}
__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
vpadal_s8 (int16x4_t a, int8x8_t b)
@@ -15859,7 +15636,7 @@ vtbx1_s8 (int8x8_t r, int8x8_t tab, int8x8_t idx)
"cmhs %0.8b, %3.8b, %0.8b\n\t"
"tbl %1.8b, {%2.16b}, %3.8b\n\t"
"bsl %0.8b, %4.8b, %1.8b\n\t"
- : "+w"(result), "=w"(tmp1)
+ : "+w"(result), "=&w"(tmp1)
: "w"(temp), "w"(idx), "w"(r)
: /* No clobbers */);
return result;
@@ -15875,7 +15652,7 @@ vtbx1_u8 (uint8x8_t r, uint8x8_t tab, uint8x8_t idx)
"cmhs %0.8b, %3.8b, %0.8b\n\t"
"tbl %1.8b, {%2.16b}, %3.8b\n\t"
"bsl %0.8b, %4.8b, %1.8b\n\t"
- : "+w"(result), "=w"(tmp1)
+ : "+w"(result), "=&w"(tmp1)
: "w"(temp), "w"(idx), "w"(r)
: /* No clobbers */);
return result;
@@ -15891,7 +15668,7 @@ vtbx1_p8 (poly8x8_t r, poly8x8_t tab, uint8x8_t idx)
"cmhs %0.8b, %3.8b, %0.8b\n\t"
"tbl %1.8b, {%2.16b}, %3.8b\n\t"
"bsl %0.8b, %4.8b, %1.8b\n\t"
- : "+w"(result), "=w"(tmp1)
+ : "+w"(result), "=&w"(tmp1)
: "w"(temp), "w"(idx), "w"(r)
: /* No clobbers */);
return result;
@@ -15946,7 +15723,7 @@ vtbx3_s8 (int8x8_t r, int8x8x3_t tab, int8x8_t idx)
"cmhs %0.8b, %3.8b, %0.8b\n\t"
"tbl %1.8b, {v16.16b - v17.16b}, %3.8b\n\t"
"bsl %0.8b, %4.8b, %1.8b\n\t"
- : "+w"(result), "=w"(tmp1)
+ : "+w"(result), "=&w"(tmp1)
: "Q"(temp), "w"(idx), "w"(r)
: "v16", "v17", "memory");
return result;
@@ -15965,7 +15742,7 @@ vtbx3_u8 (uint8x8_t r, uint8x8x3_t tab, uint8x8_t idx)
"cmhs %0.8b, %3.8b, %0.8b\n\t"
"tbl %1.8b, {v16.16b - v17.16b}, %3.8b\n\t"
"bsl %0.8b, %4.8b, %1.8b\n\t"
- : "+w"(result), "=w"(tmp1)
+ : "+w"(result), "=&w"(tmp1)
: "Q"(temp), "w"(idx), "w"(r)
: "v16", "v17", "memory");
return result;
@@ -15984,7 +15761,7 @@ vtbx3_p8 (poly8x8_t r, poly8x8x3_t tab, uint8x8_t idx)
"cmhs %0.8b, %3.8b, %0.8b\n\t"
"tbl %1.8b, {v16.16b - v17.16b}, %3.8b\n\t"
"bsl %0.8b, %4.8b, %1.8b\n\t"
- : "+w"(result), "=w"(tmp1)
+ : "+w"(result), "=&w"(tmp1)
: "Q"(temp), "w"(idx), "w"(r)
: "v16", "v17", "memory");
return result;
@@ -18025,6 +17802,80 @@ vcltzd_f64 (float64_t __a)
return __a < 0.0 ? -1ll : 0ll;
}
+/* vclz. */
+
+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+vclz_s8 (int8x8_t __a)
+{
+ return __builtin_aarch64_clzv8qi (__a);
+}
+
+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+vclz_s16 (int16x4_t __a)
+{
+ return __builtin_aarch64_clzv4hi (__a);
+}
+
+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+vclz_s32 (int32x2_t __a)
+{
+ return __builtin_aarch64_clzv2si (__a);
+}
+
+__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+vclz_u8 (uint8x8_t __a)
+{
+ return (uint8x8_t)__builtin_aarch64_clzv8qi ((int8x8_t)__a);
+}
+
+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+vclz_u16 (uint16x4_t __a)
+{
+ return (uint16x4_t)__builtin_aarch64_clzv4hi ((int16x4_t)__a);
+}
+
+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+vclz_u32 (uint32x2_t __a)
+{
+ return (uint32x2_t)__builtin_aarch64_clzv2si ((int32x2_t)__a);
+}
+
+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+vclzq_s8 (int8x16_t __a)
+{
+ return __builtin_aarch64_clzv16qi (__a);
+}
+
+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+vclzq_s16 (int16x8_t __a)
+{
+ return __builtin_aarch64_clzv8hi (__a);
+}
+
+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+vclzq_s32 (int32x4_t __a)
+{
+ return __builtin_aarch64_clzv4si (__a);
+}
+
+__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+vclzq_u8 (uint8x16_t __a)
+{
+ return (uint8x16_t)__builtin_aarch64_clzv16qi ((int8x16_t)__a);
+}
+
+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+vclzq_u16 (uint16x8_t __a)
+{
+ return (uint16x8_t)__builtin_aarch64_clzv8hi ((int16x8_t)__a);
+}
+
+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+vclzq_u32 (uint32x4_t __a)
+{
+ return (uint32x4_t)__builtin_aarch64_clzv4si ((int32x4_t)__a);
+}
+
/* vcvt (double -> float). */
__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
@@ -21241,6 +21092,80 @@ vmulq_laneq_u32 (uint32x4_t __a, uint32x4_t __b, const int __lane)
return __a * __aarch64_vgetq_lane_u32 (__b, __lane);
}
+/* vneg */
+
+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+vneg_f32 (float32x2_t __a)
+{
+ return -__a;
+}
+
+__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+vneg_f64 (float64x1_t __a)
+{
+ return -__a;
+}
+
+__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+vneg_s8 (int8x8_t __a)
+{
+ return -__a;
+}
+
+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+vneg_s16 (int16x4_t __a)
+{
+ return -__a;
+}
+
+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+vneg_s32 (int32x2_t __a)
+{
+ return -__a;
+}
+
+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+vneg_s64 (int64x1_t __a)
+{
+ return -__a;
+}
+
+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+vnegq_f32 (float32x4_t __a)
+{
+ return -__a;
+}
+
+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+vnegq_f64 (float64x2_t __a)
+{
+ return -__a;
+}
+
+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+vnegq_s8 (int8x16_t __a)
+{
+ return -__a;
+}
+
+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+vnegq_s16 (int16x8_t __a)
+{
+ return -__a;
+}
+
+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+vnegq_s32 (int32x4_t __a)
+{
+ return -__a;
+}
+
+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+vnegq_s64 (int64x2_t __a)
+{
+ return -__a;
+}
+
/* vqabs */
__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index ec8d813fa3f..50bdac9b6a8 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -351,6 +351,7 @@
(V2SI "s") (V4SI "s")
(V2DI "d") (V2SF "s")
(V4SF "s") (V2DF "d")
+ (SF "s") (DF "d")
(QI "b") (HI "h")
(SI "s") (DI "d")])
@@ -566,6 +567,24 @@
(V2SF "f") (V4SF "f")
(V2DF "f") (DF "f")])
+;; Defined to '_fp' for types whose element type is a float type.
+(define_mode_attr fp [(V8QI "") (V16QI "")
+ (V4HI "") (V8HI "")
+ (V2SI "") (V4SI "")
+ (DI "") (V2DI "")
+ (V2SF "_fp") (V4SF "_fp")
+ (V2DF "_fp") (DF "_fp")
+ (SF "_fp")])
+
+;; Defined to '_q' for 128-bit types.
+(define_mode_attr q [(V8QI "") (V16QI "_q")
+ (V4HI "") (V8HI "_q")
+ (V2SI "") (V4SI "_q")
+ (DI "") (V2DI "_q")
+ (V2SF "") (V4SF "_q")
+ (V2DF "_q")
+ (QI "") (HI "") (SI "") (DI "") (SF "") (DF "")])
+
;; -------------------------------------------------------------------
;; Code Iterators
;; -------------------------------------------------------------------
View Lorry Controller Status