[arm][4/X] Add initial support for GE-setting SIMD32 intrinsics

This patch adds in plumbing for the ACLE intrinsics that set the GE bits in
APSR.  These are special SIMD instructions in Armv6 that pack bytes or
halfwords into the 32-bit general-purpose registers and set the GE bits in
APSR to indicate if some of the "lanes" of the result have overflowed or
have some other instruction-specific property.
These bits can then be used by the SEL instruction (accessed through the
__sel intrinsic) to select lanes for further processing.

This situation is similar to the Q-setting intrinsics: we have to track
the GE fake register, detect when a function reads it through __sel and restrict
existing patterns that may generate GE-clobbering instruction from
straight-line C code when reading the GE bits matters.

	* config/arm/aout.h (REGISTER_NAMES): Add apsrge.
	* config/arm/arm.md (APSRGE_REGNUM): Define.
	(arm_<simd32_op>): New define_insn.
	(arm_sel): Likewise.
	* config/arm/arm.h (FIXED_REGISTERS): Add entry for apsrge.
	(CALL_USED_REGISTERS): Likewise.
	(REG_ALLOC_ORDER): Likewise.
	(FIRST_PSEUDO_REGISTER): Update value.
	(ARM_GE_BITS_READ): Define.
	* config/arm/arm.c (arm_conditional_register_usage): Clear
	APSRGE_REGNUM from operand_reg_set.
	(arm_ge_bits_access): Define.
	* config/arm/arm-builtins.c (arm_check_builtin_call): Handle
	ARM_BUIILTIN_sel.
	* config/arm/arm-protos.h (arm_ge_bits_access): Declare prototype.
	* config/arm/arm-fixed.md (add<mode>3): Convert to define_expand.
	FAIL if ARM_GE_BITS_READ.
	(*arm_add<mode>3): New define_insn.
	(sub<mode>3): Convert to define_expand.  FAIL if ARM_GE_BITS_READ.
	(*arm_sub<mode>3): New define_insn.
	* config/arm/arm_acle.h (__sel, __sadd8, __ssub8, __uadd8, __usub8,
	__sadd16, __sasx, __ssax, __ssub16, __uadd16, __uasx, __usax,
	__usub16): Define.
	* config/arm/arm_acle_builtins.def: Define builtins for the above.
	* config/arm/iterators.md (SIMD32_GE): New int_iterator.
	(simd32_op): Handle the above.
	* config/arm/unspecs.md (UNSPEC_GE_SET): Define.
	(UNSPEC_SEL, UNSPEC_SADD8, UNSPEC_SSUB8, UNSPEC_UADD8, UNSPEC_USUB8,
	UNSPEC_SADD16, UNSPEC_SASX, UNSPEC_SSAX, UNSPEC_SSUB16, UNSPEC_UADD16,
	UNSPEC_UASX, UNSPEC_USAX, UNSPEC_USUB16): Define.

	* gcc.target/arm/acle/simd32.c: Update test.
	* gcc.target/arm/acle/simd32_sel.c: New test.

From-SVN: r277917

1 files changed, 7 insertions, 0 deletions

diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
index 995f50785f6..2d902d0b325 100644
--- a/gcc/config/arm/arm-builtins.c
+++ b/gcc/config/arm/arm-builtins.c
@@ -3370,6 +3370,13 @@ arm_check_builtin_call (location_t , vec<location_t> , tree fndecl,
 	  = tree_cons (get_identifier ("acle qbit"), NULL_TREE,
 		       DECL_ATTRIBUTES (cfun->decl));
     }
+  if (fcode == ARM_BUILTIN_sel)
+    {
+      if (cfun && cfun->decl)
+	DECL_ATTRIBUTES (cfun->decl)
+	  = tree_cons (get_identifier ("acle gebits"), NULL_TREE,
+		       DECL_ATTRIBUTES (cfun->decl));
+    }
   return true;
 }