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authorbstarynk <bstarynk@138bc75d-0d04-0410-961f-82ee72b054a4>2011-12-21 09:07:52 +0000
committerbstarynk <bstarynk@138bc75d-0d04-0410-961f-82ee72b054a4>2011-12-21 09:07:52 +0000
commitc376c8d3136602addba5a4e49dcc3f920999069e (patch)
tree46f42fd6a5ffbbc0708e3f6c9dbb4f490f663b39 /gcc/config/arm/arm.c
parent4a5d167df1662b4f709186178aa8ab842dd87a8b (diff)
downloadgcc-c376c8d3136602addba5a4e49dcc3f920999069e.tar.gz
2011-12-21 Basile Starynkevitch <basile@starynkevitch.net>
MELT branch merged with trunk rev 182564 using svnmerge git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/melt-branch@182569 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/arm/arm.c')
-rw-r--r--gcc/config/arm/arm.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 3d3c4523c75..b682a9f0d9d 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -1989,7 +1989,8 @@ arm_option_override (void)
global_options_set.x_param_values);
/* ARM EABI defaults to strict volatile bitfields. */
- if (TARGET_AAPCS_BASED && flag_strict_volatile_bitfields < 0)
+ if (TARGET_AAPCS_BASED && flag_strict_volatile_bitfields < 0
+ && abi_version_at_least(2))
flag_strict_volatile_bitfields = 1;
/* Enable sw prefetching at -O3 for CPUS that have prefetch, and we have deemed
@@ -11671,7 +11672,7 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
return CC_Zmode;
/* We can do an equality test in three Thumb instructions. */
- if (!TARGET_ARM)
+ if (!TARGET_32BIT)
return CC_Zmode;
/* FALLTHROUGH */
@@ -11683,7 +11684,7 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
/* DImode unsigned comparisons can be implemented by cmp +
cmpeq without a scratch register. Not worth doing in
Thumb-2. */
- if (TARGET_ARM)
+ if (TARGET_32BIT)
return CC_CZmode;
/* FALLTHROUGH */