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| author | Richard Sandiford <richard.sandiford@arm.com> | 2019-09-17 17:00:58 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2019-09-17 17:00:58 +0000 |
| commit | f62281dc1b3d751977266d8c30b4488833fcb9dd (patch) | |
| tree | e9e12be32b1c09ea846e54abb2e6168375fdc862 /gcc/config/arm/cortex-a9.md | |
| parent | 5d4efa795e09a17e1773e8862db8f55aa7fe90c5 (diff) | |
| download | gcc-f62281dc1b3d751977266d8c30b4488833fcb9dd.tar.gz | |
[arm][aarch64] Make no_insn issue to nothing
no_insn is documented as:
an insn which does not represent an instruction in the final output,
thus having no impact on scheduling.
and is used in that way by the arm port (e.g. for define_insns that
expand to comments). However, most scheduling descriptions instead
assigned units to no_insn patterns, in some cases treating them as more
expensive than a plain move.
This patch removes the no_insn handling from individual scheduling
descriptions and uses a common define_insn_reservation for all CPUs.
2019-09-17 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/arm/types.md (no_reservation): New reservation.
* config/aarch64/falkor.md (falkor_other_0_nothing): Don't handle
no_insn here.
* config/aarch64/saphira.md (saphira_other_0_nothing): Likewise.
* config/aarch64/thunderx2t99.md (thunderx2t99_nothing): Likewise.
* config/aarch64/tsv110.md (tsv110_alu): Likewise.
* config/arm/arm1020e.md (1020alu_op): Likewise.
* config/arm/arm1026ejs.md (alu_op): Likewise.
* config/arm/arm1136jfs.md (11_alu_op): Likewise.
* config/arm/arm926ejs.md (9_alu_op): Likewise.
* config/arm/cortex-a15.md (cortex_a15_alu): Likewise.
* config/arm/cortex-a17.md (cortex_a17_alu): Likewise.
* config/arm/cortex-a5.md (cortex_a5_alu): Likewise.
* config/arm/cortex-a53.md (cortex_a53_alu): Likewise.
* config/arm/cortex-a57.md (cortex_a57_alu): Likewise.
* config/arm/cortex-a7.md (cortex_a7_alu_shift): Likewise.
* config/arm/cortex-a8.md (cortex_a8_alu): Likewise.
* config/arm/cortex-a9.md (cortex_a9_dp): Likewise.
* config/arm/cortex-m4.md (cortex_m4_alu): Likewise.
* config/arm/cortex-m7.md (cortex_m7_alu_simple): Likewise.
* config/arm/cortex-r4.md (cortex_r4_alu_shift_reg): Likewise.
* config/arm/fa526.md (526_alu_op): Likewise.
* config/arm/fa606te.md (606te_alu_op): Likewise.
* config/arm/fa626te.md (626te_alu_op): Likewise.
* config/arm/fa726te.md (726te_alu_op): Likewise.
* config/arm/xgene1.md (xgene1_nop): Likewise.
From-SVN: r275807
Diffstat (limited to 'gcc/config/arm/cortex-a9.md')
| -rw-r--r-- | gcc/config/arm/cortex-a9.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/config/arm/cortex-a9.md b/gcc/config/arm/cortex-a9.md index 6402a44387a..c8474152cc6 100644 --- a/gcc/config/arm/cortex-a9.md +++ b/gcc/config/arm/cortex-a9.md @@ -87,7 +87,7 @@ cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1") shift_imm,shift_reg,\ mov_imm,mov_reg,mvn_imm,mvn_reg,\ mov_shift_reg,mov_shift,\ - mrs,multiple,no_insn")) + mrs,multiple")) "cortex_a9_p0_default|cortex_a9_p1_default") ;; An instruction using the shifter will go down E1. |