diff options
| author | Christophe Lyon <christophe.lyon@linaro.org> | 2020-11-13 12:34:12 +0000 |
|---|---|---|
| committer | Christophe Lyon <christophe.lyon@linaro.org> | 2020-12-11 16:22:28 +0000 |
| commit | 75de6a2895f503905589934e30c68b9a5ec41f2f (patch) | |
| tree | c9afb08bd9a03561439f0b5299ef3a1c437adce1 /gcc/config/arm/mve.md | |
| parent | f7ad4446274831234e5acd3506fd2e01c7594c6a (diff) | |
| download | gcc-75de6a2895f503905589934e30c68b9a5ec41f2f.tar.gz | |
arm: Auto-vectorization for MVE: vorr
This patch enables MVE vorrq instructions for auto-vectorization. MVE
vorrq insns in mve.md are modified to use ior instead of unspec
expression to support ior<mode>3. The ior<mode>3 expander is added to
vec-common.md
2020-12-03 Christophe Lyon <christophe.lyon@linaro.org>
gcc/
* config/arm/iterators.md (supf): Remove VORRQ_S and VORRQ_U.
(VORRQ): Remove.
* config/arm/mve.md (mve_vorrq_s<mode>): New entry for vorr
instruction using expression ior.
(mve_vorrq_u<mode>): New expander.
(mve_vorrq_f<mode>): Use ior code instead of unspec.
* config/arm/neon.md (ior<mode>3): Renamed into ior<mode>3_neon.
* config/arm/predicates.md (imm_for_neon_logic_operand): Enable
for MVE.
* config/arm/unspecs.md (VORRQ_S, VORRQ_U, VORRQ_F): Remove.
* config/arm/vec-common.md (ior<mode>3): New expander.
gcc/testsuite/
* gcc.target/arm/simd/mve-vorr.c: Add vorr tests.
Diffstat (limited to 'gcc/config/arm/mve.md')
| -rw-r--r-- | gcc/config/arm/mve.md | 30 |
1 files changed, 21 insertions, 9 deletions
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 1ec0d1aa323..4b2e46afc19 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -1613,17 +1613,30 @@ ;; ;; [vorrq_s, vorrq_u]) ;; -(define_insn "mve_vorrq_<supf><mode>" +;; signed and unsigned versions are the same: define the unsigned +;; insn, and use an expander for the signed one as we still reference +;; both names from arm_mve.h. +;; We use the same code as in neon.md (TODO: avoid this duplication). +(define_insn "mve_vorrq_s<mode>" [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:MVE_2 2 "s_register_operand" "w")] - VORRQ)) + (set (match_operand:MVE_2 0 "s_register_operand" "=w,w") + (ior:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w,0") + (match_operand:MVE_2 2 "neon_logic_op2" "w,Dl"))) ] "TARGET_HAVE_MVE" - "vorr %q0, %q1, %q2" + "@ + vorr\t%q0, %q1, %q2 + * return neon_output_logic_immediate (\"vorr\", &operands[2], <MODE>mode, 0, VALID_NEON_QREG_MODE (<MODE>mode));" [(set_attr "type" "mve_move") ]) +(define_expand "mve_vorrq_u<mode>" + [ + (set (match_operand:MVE_2 0 "s_register_operand") + (ior:MVE_2 (match_operand:MVE_2 1 "s_register_operand") + (match_operand:MVE_2 2 "neon_logic_op2"))) + ] + "TARGET_HAVE_MVE" +) ;; ;; [vqaddq_n_s, vqaddq_n_u]) @@ -2658,9 +2671,8 @@ (define_insn "mve_vorrq_f<mode>" [ (set (match_operand:MVE_0 0 "s_register_operand" "=w") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand:MVE_0 2 "s_register_operand" "w")] - VORRQ_F)) + (ior:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vorr %q0, %q1, %q2" |