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| author | James Greenhalgh <james.greenhalgh@arm.com> | 2013-09-06 11:02:52 +0000 |
|---|---|---|
| committer | James Greenhalgh <jgreenhalgh@gcc.gnu.org> | 2013-09-06 11:02:52 +0000 |
| commit | 1c83b6738a30cff17008d301bfe4cdd9ae45e727 (patch) | |
| tree | e4d27587879ef34d237340636fafbe6e7933a3c6 /gcc/config/arm/vfp.md | |
| parent | bb1ae543739b50a8559f52ce3760af6bb2e090e2 (diff) | |
| download | gcc-1c83b6738a30cff17008d301bfe4cdd9ae45e727.tar.gz | |
[Patch AArch64] Fix register constraints for lane intrinsics.
gcc/
* config/aarch64/aarch64-simd.md
(aarch64_sqdml<SBINQOPS:as>l_n<mode>_internal): Use
<vwx> iterator to ensure correct register choice.
(aarch64_sqdml<SBINQOPS:as>l2_n<mode>_internal): Likewise.
(aarch64_sqdmull_n<mode>): Likewise.
(aarch64_sqdmull2_n<mode>_internal): Likewise.
* config/aarch64/arm_neon.h
(vml<as><q>_lane<q>_<su>16): Use 'x' constraint for element vector.
(vml<as><q>_n_<su>16): Likewise.
(vml<as>l_high_lane<q>_<su>16): Likewise.
(vml<as>l_high_n_<su>16): Likewise.
(vml<as>l_lane<q>_<su>16): Likewise.
(vml<as>l_n_<su>16): Likewise.
(vmul<q>_lane<q>_<su>16): Likewise.
(vmul<q>_n_<su>16): Likewise.
(vmull_lane<q>_<su>16): Likewise.
(vmull_n_<su>16): Likewise.
(vmull_high_lane<q>_<su>16): Likewise.
(vmull_high_n_<su>16): Likewise.
(vqrdmulh<q>_n_s16): Likewise.
From-SVN: r202322
Diffstat (limited to 'gcc/config/arm/vfp.md')
0 files changed, 0 insertions, 0 deletions