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| author | Matthew Gretton-Dann <matthew.gretton-dann@arm.com> | 2012-07-05 09:07:00 +0000 |
|---|---|---|
| committer | Matthew Gretton-Dann <mgretton@gcc.gnu.org> | 2012-07-05 09:07:00 +0000 |
| commit | 76f722f45208538637e8d3c3d5ea0717b3bcdf8b (patch) | |
| tree | 298c739f6cfbbc7b572a60db39a1a030bb380ab7 /gcc/config/arm/vfp.md | |
| parent | 4b68f9ee5a9569a22522ab0b82d603e2ceacb35d (diff) | |
| download | gcc-76f722f45208538637e8d3c3d5ea0717b3bcdf8b.tar.gz | |
iterators.md (SDF): New mode iterator.
* gcc/config/arm/iterators.md (SDF): New mode iterator.
(V_if_elem): Add support for SF and DF modes.
(V_reg): Likewise.
(F_constraint): New mode iterator attribute.
(F_fma_type): Likewise.
config/arm/vfp.md (fma<SDF:mode>4): New pattern.
(*fmsub<SDF:mode>4): Likewise.
(*fmnsub<SDF:mode>4): Likewise.
(*fmnadd<SDF:mode>4): Likewise.
* gcc/testsuite/gcc.target/arm/fma-sp.c: New testcase.
* gcc/testsuite/gcc.target/arm/fma.c: Likewise.
* gcc/testsuite/gcc.target/arm/fma.h: Likewise.
From-SVN: r189283
Diffstat (limited to 'gcc/config/arm/vfp.md')
| -rw-r--r-- | gcc/config/arm/vfp.md | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index 20614144d29..3d18ecbc337 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -890,6 +890,54 @@ (set_attr "type" "fmacd")] ) +;; Fused-multiply-accumulate + +(define_insn "fma<SDF:mode>4" + [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>") + (fma:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>") + (match_operand:SDF 2 "register_operand" "<F_constraint>") + (match_operand:SDF 3 "register_operand" "0")))] + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA" + "vfma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" + [(set_attr "predicable" "yes") + (set_attr "type" "<F_fma_type>")] +) + +(define_insn "*fmsub<SDF:mode>4" + [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>") + (fma:SDF (neg:SDF (match_operand:SDF 1 "register_operand" + "<F_constraint>")) + (match_operand:SDF 2 "register_operand" "<F_constraint>") + (match_operand:SDF 3 "register_operand" "0")))] + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA" + "vfms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" + [(set_attr "predicable" "yes") + (set_attr "type" "<F_fma_type>")] +) + +(define_insn "*fnmsub<SDF:mode>4" + [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>") + (fma:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>") + (match_operand:SDF 2 "register_operand" "<F_constraint>") + (neg:SDF (match_operand:SDF 3 "register_operand" "0"))))] + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA" + "vfnms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" + [(set_attr "predicable" "yes") + (set_attr "type" "<F_fma_type>")] +) + +(define_insn "*fnmadd<SDF:mode>4" + [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>") + (fma:SDF (neg:SDF (match_operand:SDF 1 "register_operand" + "<F_constraint>")) + (match_operand:SDF 2 "register_operand" "<F_constraint>") + (neg:SDF (match_operand:SDF 3 "register_operand" "0"))))] + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA" + "vfnma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" + [(set_attr "predicable" "yes") + (set_attr "type" "<F_fma_type>")] +) + ;; Conversion routines |