entered into RCS

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@2482 138bc75d-0d04-0410-961f-82ee72b054a4

4 files changed, 2467 insertions, 0 deletions

diff --git a/gcc/config/elxsi/elxsi.h b/gcc/config/elxsi/elxsi.h
new file mode 100644
index 00000000000..027740a3ccb
--- /dev/null
+++ b/gcc/config/elxsi/elxsi.h
@@ -0,0 +1,976 @@
+/* Definitions of target machine for GNU compiler.  Elxsi version.
+   Copyright (C) 1987, 1988, 1992 Free Software Foundation, Inc.
+   This port, done by Mike Stump <mrs@cygnus.com> in 1988, and is the first
+   64 bit port of GNU CC.
+   Based upon the VAX port.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 1, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+
+/* Names to predefine in the preprocessor for this target machine.  */
+
+#define CPP_PREDEFINES "-Delxsi -Dunix"
+
+/* Print subsidiary information on the compiler version in use.  */
+
+#define TARGET_VERSION fprintf (stderr, " (elxsi)");
+
+/* Run-time compilation parameters selecting different hardware subsets.  */
+
+extern int target_flags;
+
+/* Macros used in the machine description to test the flags.  */
+
+/* Nonzero if compiling code that Unix assembler can assemble.  */
+#define TARGET_UNIX_ASM (target_flags & 1)
+
+
+/* Macro to define tables used to set the flags.
+   This is a list in braces of pairs in braces,
+   each pair being { "NAME", VALUE }
+   where VALUE is the bits to set or minus the bits to clear.
+   An empty string NAME is used to identify the default VALUE.  */
+
+#define TARGET_SWITCHES  \
+  { {"unix", 1},  \
+    {"embos", -1},  \
+    { "", TARGET_DEFAULT}}
+
+/* Default target_flags if no switches specified.  */
+
+#ifndef TARGET_DEFAULT
+#define TARGET_DEFAULT 1
+#endif
+
+/* Target machine storage layout */
+
+/* Define this if most significant bit is lowest numbered
+   in instructions that operate on numbered bit-fields.
+   This is not true on the vax.  */
+/* #define BITS_BIG_ENDIAN */
+
+/* Define this if most significant byte of a word is the lowest numbered.  */
+#define BYTES_BIG_ENDIAN 1
+
+/* Define this if most significant word of a multiword number is numbered.  */
+#define WORDS_BIG_ENDIAN 1
+
+/* Number of bits in an addressible storage unit */
+#define BITS_PER_UNIT 8
+
+/* Width in bits of a "word", which is the contents of a machine register.
+   Note that this is not necessarily the width of data type `int';
+   if using 16-bit ints on a 68000, this would still be 32.
+   But on a machine with 16-bit registers, this would be 16.  */
+#define BITS_PER_WORD 64
+#define Rmode DImode
+
+#define INT_TYPE_SIZE 32
+
+#define LONG_TYPE_SIZE 32
+
+#define LONG_LONG_TYPE_SIZE 64
+
+#define FLOAT_TYPE_SIZE 32
+
+#define DOUBLE_TYPE_SIZE 64
+
+#define LONG_DOUBLE_TYPE_SIZE 64
+
+/* Width of a word, in units (bytes).  */
+#define UNITS_PER_WORD 8
+
+/* Width in bits of a pointer.
+   See also the macro `Pmode' defined below.  */
+#define POINTER_SIZE 32
+
+/* Allocation boundary (in *bits*) for storing pointers in memory.  */
+#define POINTER_BOUNDARY 32
+
+/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
+#define PARM_BOUNDARY 32
+
+/* Allocation boundary (in *bits*) for the code of a function.  */
+#define FUNCTION_BOUNDARY 8
+
+/* Alignment of field after `int : 0' in a structure.  */
+#define EMPTY_FIELD_BOUNDARY 8
+
+/* Every structure's size must be a multiple of this.  */
+#define STRUCTURE_SIZE_BOUNDARY 32
+
+/* A bitfield declared as `int' forces `int' alignment for the struct.  */
+#define PCC_BITFIELD_TYPE_MATTERS 1
+
+/* No data type wants to be aligned rounder than this.  */
+#define BIGGEST_ALIGNMENT 32
+
+/* Define this if move instructions will actually fail to work
+   when given unaligned data.  */
+#define STRICT_ALIGNMENT 0
+
+/* Standard register usage.  */
+
+/* Number of actual hardware registers.
+   The hardware registers are assigned numbers for the compiler
+   from 0 to just below FIRST_PSEUDO_REGISTER.
+   All registers that the compiler knows about must be given numbers,
+   even those that are not normally considered general registers.  */
+#define FIRST_PSEUDO_REGISTER 16
+
+/* 1 for registers that have pervasive standard uses
+   and are not available for the register allocator.
+   On the elxsi, these is the .r15 (aka .sp).  */
+#define FIXED_REGISTERS {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1}
+
+/* 1 for registers not available across function calls.
+   These must include the FIXED_REGISTERS and also any
+   registers that can be used without being saved.
+   The latter must include the registers where values are returned
+   and the register where structure-value addresses are passed.
+   Aside from that, you can include as many other registers as you like.  */
+#define CALL_USED_REGISTERS {1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1}
+
+/* Return number of consecutive hard regs needed starting at reg REGNO
+   to hold something of mode MODE.
+   This is ordinarily the length in words of a value of mode MODE
+   but can be less for certain modes in special long registers.
+   On the vax, all registers are one word long.  */
+#define HARD_REGNO_NREGS(REGNO, MODE)   \
+ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
+
+/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
+#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
+
+/* Value is 1 if it is a good idea to tie two pseudo registers
+   when one has mode MODE1 and one has mode MODE2.
+   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
+   for any hard reg, then this must be 0 for correct output.  */
+#define MODES_TIEABLE_P(MODE1, MODE2)  1
+
+/* Specify the registers used for certain standard purposes.
+   The values of these macros are register numbers.  */
+
+/* Register to use for pushing function arguments.  */
+#define STACK_POINTER_REGNUM 15
+
+/* Base register for access to local variables of the function.  */
+#define FRAME_POINTER_REGNUM 14
+
+/* Value should be nonzero if functions must have frame pointers.
+   Zero means the frame pointer need not be set up (and parms
+   may be accessed via the stack pointer) in functions that seem suitable.
+   This is computed in `reload', in reload1.c.  */
+#define FRAME_POINTER_REQUIRED 0
+
+#define INITIAL_FRAME_POINTER_OFFSET(DEPTH)			\
+{ int regno;							\
+  int offset = 0;						\
+  for( regno=0; regno < FIRST_PSEUDO_REGISTER;  regno++ )	\
+    if( regs_ever_live[regno] && !call_used_regs[regno] )	\
+      offset += 8;						\
+  (DEPTH) = (offset + ((get_frame_size() + 3) & ~3) );		\
+  (DEPTH) = 0;							\
+}
+
+/* Base register for access to arguments of the function.  */
+#define ARG_POINTER_REGNUM 14
+
+/* Register in which static-chain is passed to a function.  */
+#define STATIC_CHAIN_REGNUM 0
+
+/* Register in which address to store a structure value
+   is passed to a function.  */
+#define STRUCT_VALUE_REGNUM 1
+
+/* Define the classes of registers for register constraints in the
+   machine description.  Also define ranges of constants.
+
+   One of the classes must always be named ALL_REGS and include all hard regs.
+   If there is more than one class, another class must be named NO_REGS
+   and contain no registers.
+
+   The name GENERAL_REGS must be the name of a class (or an alias for
+   another name such as ALL_REGS).  This is the class of registers
+   that is allowed by "g" or "r" in a register constraint.
+   Also, registers outside this class are allocated only when
+   instructions express preferences for them.
+
+   The classes must be numbered in nondecreasing order; that is,
+   a larger-numbered class must never be contained completely
+   in a smaller-numbered class.
+
+   For any two classes, it is very desirable that there be another
+   class that represents their union.  */
+   
+/* The vax has only one kind of registers, so NO_REGS and ALL_REGS
+   are the only classes.  */
+
+enum reg_class { NO_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES };
+
+#define N_REG_CLASSES (int) LIM_REG_CLASSES
+
+/* Give names of register classes as strings for dump file.   */
+
+#define REG_CLASS_NAMES \
+ {"NO_REGS", "GENERAL_REGS", "ALL_REGS" }
+
+/* Define which registers fit in which classes.
+   This is an initializer for a vector of HARD_REG_SET
+   of length N_REG_CLASSES.  */
+
+#define REG_CLASS_CONTENTS {0, 0x07fff, 0xffff}
+
+/* The same information, inverted:
+   Return the class number of the smallest class containing
+   reg number REGNO.  This could be a conditional expression
+   or could index an array.  */
+
+#define REGNO_REG_CLASS(REGNO) (REGNO == 15 ? ALL_REGS : GENERAL_REGS)
+
+/* The class value for index registers, and the one for base regs.  */
+
+#define INDEX_REG_CLASS GENERAL_REGS
+#define BASE_REG_CLASS GENERAL_REGS
+
+/* Get reg_class from a letter such as appears in the machine description.  */
+
+#define REG_CLASS_FROM_LETTER(C) NO_REGS
+
+/* The letters I, J, K, L and M in a register constraint string
+   can be used to stand for particular ranges of immediate operands.
+   This macro defines what the ranges are.
+   C is the letter, and VALUE is a constant value.
+   Return 1 if VALUE is in the range specified by C.  */
+
+#define CONST_OK_FOR_LETTER_P(VALUE, C)  \
+    ((C) == 'I' ? (VALUE) >=-16 && (VALUE) <=15 : 0)
+
+/* Similar, but for floating constants, and defining letters G and H.
+   Here VALUE is the CONST_DOUBLE rtx itself.  */
+
+#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 1
+
+/* Given an rtx X being reloaded into a reg required to be
+   in class CLASS, return the class of reg to actually use.
+   In general this is just CLASS; but on some machines
+   in some cases it is preferable to use a more restrictive class.  */
+
+#define PREFERRED_RELOAD_CLASS(X,CLASS)  (CLASS)
+
+/* Return the maximum number of consecutive registers
+   needed to represent mode MODE in a register of class CLASS.  */
+/* On the vax, this is always the size of MODE in words,
+   since all registers are the same size.  */
+#define CLASS_MAX_NREGS(CLASS, MODE)	\
+ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
+
+/* Stack layout; function entry, exit and calling.  */
+
+/* Define this if pushing a word on the stack
+   makes the stack pointer a smaller address.  */
+#define STACK_GROWS_DOWNWARD
+
+/* Define this if the nominal address of the stack frame
+   is at the high-address end of the local variables;
+   that is, each additional local variable allocated
+   goes at a more negative offset in the frame.  */
+#define FRAME_GROWS_DOWNWARD
+
+/* Offset within stack frame to start allocating local variables at.
+   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
+   first local allocated.  Otherwise, it is the offset to the BEGINNING
+   of the first local allocated.  */
+#define STARTING_FRAME_OFFSET -4
+
+/* Offset of first parameter from the argument pointer register value.  */
+#define FIRST_PARM_OFFSET(FNDECL) 4
+
+/* Value is 1 if returning from a function call automatically
+   pops the arguments described by the number-of-args field in the call.
+   FUNTYPE is the data type of the function (as a tree),
+   or for a library call it is an identifier node for the subroutine name.
+
+   On the Vax, the RET insn always pops all the args for any function.  */
+
+#define RETURN_POPS_ARGS(FUNTYPE,SIZE) (SIZE)
+
+/* Define how to find the value returned by a function.
+   VALTYPE is the data type of the value (as a tree).
+   If the precise function being called is known, FUNC is its FUNCTION_DECL;
+   otherwise, FUNC is 0.  */
+
+/* On the Vax the return value is in R0 regardless.  */   
+
+#define FUNCTION_VALUE(VALTYPE, FUNC)  \
+  gen_rtx (REG, TYPE_MODE (VALTYPE), 0)
+
+/* Define how to find the value returned by a library function
+   assuming the value has mode MODE.  */
+
+/* On the Vax the return value is in R0 regardless.  */   
+
+#define LIBCALL_VALUE(MODE)  gen_rtx (REG, MODE, 0)
+
+/* Define this if PCC uses the nonreentrant convention for returning
+   structure and union values.  */
+
+#define PCC_STATIC_STRUCT_RETURN
+
+/* 1 if N is a possible register number for a function value.
+   On the Vax, R0 is the only register thus used.  */
+
+#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
+
+/* 1 if N is a possible register number for function argument passing.
+   On the Vax, no registers are used in this way.  */
+
+#define FUNCTION_ARG_REGNO_P(N) 0
+
+/* Define a data type for recording info about an argument list
+   during the scan of that argument list.  This data type should
+   hold all necessary information about the function itself
+   and about the args processed so far, enough to enable macros
+   such as FUNCTION_ARG to determine where the next arg should go.
+
+   On the vax, this is a single integer, which is a number of bytes
+   of arguments scanned so far.  */
+
+#define CUMULATIVE_ARGS int
+
+/* Initialize a variable CUM of type CUMULATIVE_ARGS
+   for a call to a function whose data type is FNTYPE.
+   For a library call, FNTYPE is 0.
+
+   On the vax, the offset starts at 0.  */
+
+#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,x)	\
+ ((CUM) = 0)
+
+/* Update the data in CUM to advance over an argument
+   of mode MODE and data type TYPE.
+   (TYPE is null for libcalls where that information may not be available.)  */
+
+#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
+ ((CUM) += ((MODE) != BLKmode			\
+	    ? (GET_MODE_SIZE (MODE) + 3) & ~3	\
+	    : (int_size_in_bytes (TYPE) + 3) & ~3))
+
+/* Define where to put the arguments to a function.
+   Value is zero to push the argument on the stack,
+   or a hard register in which to store the argument.
+
+   MODE is the argument's machine mode.
+   TYPE is the data type of the argument (as a tree).
+    This is null for libcalls where that information may
+    not be available.
+   CUM is a variable of type CUMULATIVE_ARGS which gives info about
+    the preceding args and about the function being called.
+   NAMED is nonzero if this argument is a named parameter
+    (otherwise it is an extra parameter matching an ellipsis).  */
+
+/* On the vax all args are pushed.  */   
+
+#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
+
+/* This macro generates the assembly code for function entry.
+   FILE is a stdio stream to output the code to.
+   SIZE is an int: how many units of temporary storage to allocate.
+   Refer to the array `regs_ever_live' to determine which registers
+   to save; `regs_ever_live[I]' is nonzero if register number I
+   is ever used in the function.  This macro is responsible for
+   knowing which registers should not be saved even if used.  */
+
+#define FUNCTION_PROLOGUE(FILE, SIZE)					\
+{ register int regno;							\
+  register int cnt = 0;							\
+  extern char call_used_regs[];						\
+  /* the below two lines are a HACK, and should be deleted, but 	\
+     for now are very much needed (1.35) */				\
+  if (frame_pointer_needed)						\
+    regs_ever_live[14]=1, call_used_regs[14]=0;				\
+  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)		\
+    if (regs_ever_live[regno] && !call_used_regs[regno])		\
+	cnt+=8;								\
+  if ((SIZE)+cnt)							\
+    fprintf (FILE, "\tadd.64\t.sp,=%d\n", -(SIZE)-cnt);			\
+  cnt = 0;								\
+  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)		\
+    if (regs_ever_live[regno] && !call_used_regs[regno])		\
+      fprintf (FILE, "\tst.64\t.r%d,[.sp]%d\n", regno, (cnt+=8)-12); 	\
+  if (frame_pointer_needed)						\
+    fprintf (FILE, "\tadd.64\t.r14,.sp,=%d\n", (SIZE)+cnt);		\
+}
+
+/* Output assembler code to FILE to increment profiler label # LABELNO
+   for profiling a function entry.  */
+
+#define FUNCTION_PROFILER(FILE, LABELNO)  \
+   fprintf (FILE, "\tld.64\t.r0,.LP%d\n\tcall\tmcount\n", (LABELNO));
+
+/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
+   the stack pointer does not matter.  The value is tested only in
+   functions that have frame pointers.
+   No definition is equivalent to always zero.  */
+
+#define EXIT_IGNORE_STACK 0
+
+/* This macro generates the assembly code for function exit,
+   on machines that need it.  If FUNCTION_EPILOGUE is not defined
+   then individual return instructions are generated for each
+   return statement.  Args are same as for FUNCTION_PROLOGUE.  */
+
+#define FUNCTION_EPILOGUE(FILE, SIZE)					\
+{ register int regno;							\
+  register int cnt = 0;							\
+  extern char call_used_regs[];						\
+  extern int current_function_calls_alloca;						\
+  /* this conditional is ONLY here because there is a BUG;		\
+	     EXIT_IGNORE_STACK is ignored itself when the first part of		\
+	     the condition is true! (atleast in version 1.35) */		\
+  /* the 8*10 is for 64 bits of .r5 - .r14 */				\
+  if (current_function_calls_alloca || (SIZE)>=(256-8*10)) {		\
+    /* use .r4 as a temporary! Ok for now.... */			\
+    fprintf (FILE, "\tld.64\t.r4,.r14\n");				\
+    for (regno = FIRST_PSEUDO_REGISTER-1; regno >= 0; --regno)		\
+      if (regs_ever_live[regno] && !call_used_regs[regno])		\
+       	cnt+=8;								\
+    for (regno = 0; regno < FIRST_PSEUDO_REGISTER; ++regno)		\
+      if (regs_ever_live[regno] && !call_used_regs[regno])		\
+       fprintf (FILE, "\tld.64\t.r%d,[.r14]%d\n", regno,		\
+		-((cnt-=8) + 8)-4-(SIZE));				\
+    fprintf (FILE, "\tld.64\t.sp,.r4\n\texit\t0\n");			\
+  } else {								\
+    for (regno = 0; regno < FIRST_PSEUDO_REGISTER; ++regno)		\
+      if (regs_ever_live[regno] && !call_used_regs[regno])		\
+         fprintf (FILE, "\tld.64\t.r%d,[.sp]%d\n", regno, (cnt+=8)-12);	\
+    fprintf (FILE, "\texit\t%d\n", (SIZE)+cnt);				\
+  } }
+
+/* If the memory address ADDR is relative to the frame pointer,
+   correct it to be relative to the stack pointer instead.
+   This is for when we don't use a frame pointer.
+   ADDR should be a variable name.  */
+
+#define FIX_FRAME_POINTER_ADDRESS(ADDR,DEPTH) \
+{ int offset = -1;							\
+  rtx regs = stack_pointer_rtx;						\
+  if (ADDR == frame_pointer_rtx)					\
+    offset = 0;								\
+  else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 1) == frame_pointer_rtx \
+	   && GET_CODE (XEXP (ADDR, 0)) == CONST_INT)			\
+    offset = INTVAL (XEXP (ADDR, 0));					\
+  else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 0) == frame_pointer_rtx \
+	   && GET_CODE (XEXP (ADDR, 1)) == CONST_INT)			\
+    offset = INTVAL (XEXP (ADDR, 1));					\
+  else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 0) == frame_pointer_rtx) \
+    { rtx other_reg = XEXP (ADDR, 1);					\
+      offset = 0;							\
+      regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); }	\
+  else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 1) == frame_pointer_rtx) \
+    { rtx other_reg = XEXP (ADDR, 0);					\
+      offset = 0;							\
+      regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); }	\
+  if (offset >= 0)							\
+    { int regno;							\
+      extern char call_used_regs[];					\
+      offset += 4; /* I don't know why??? */				\
+      for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)		\
+        if (regs_ever_live[regno] && ! call_used_regs[regno])		\
+          offset += 8;							\
+      ADDR = plus_constant (regs, offset + (DEPTH)); } }
+
+
+/* Addressing modes, and classification of registers for them.  */
+
+/* #define HAVE_POST_INCREMENT */
+/* #define HAVE_POST_DECREMENT */
+
+/* #define HAVE_PRE_DECREMENT */
+/* #define HAVE_PRE_INCREMENT */
+
+/* Macros to check register numbers against specific register classes.  */
+
+/* These assume that REGNO is a hard or pseudo reg number.
+   They give nonzero only if REGNO is a hard reg of the suitable class
+   or a pseudo reg currently allocated to a suitable hard reg.
+   Since they use reg_renumber, they are safe only once reg_renumber
+   has been allocated, which happens in local-alloc.c.  */
+
+#define REGNO_OK_FOR_INDEX_P(regno)  \
+((regno) < FIRST_PSEUDO_REGISTER || reg_renumber[regno] >= 0)
+#define REGNO_OK_FOR_BASE_P(regno) \
+((regno) < FIRST_PSEUDO_REGISTER || reg_renumber[regno] >= 0)
+
+/* Maximum number of registers that can appear in a valid memory address.  */
+
+#define MAX_REGS_PER_ADDRESS 2
+
+/* 1 if X is an rtx for a constant that is a valid address.  */
+
+#define CONSTANT_ADDRESS_P(X) CONSTANT_P (X)
+
+/* Nonzero if the constant value X is a legitimate general operand.
+   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
+
+#define LEGITIMATE_CONSTANT_P(X) \
+    (GET_CODE (X) != CONST_DOUBLE)
+
+/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
+   and check its validity for a certain class.
+   We have two alternate definitions for each of them.
+   The usual definition accepts all pseudo regs; the other rejects
+   them unless they have been allocated suitable hard regs.
+   The symbol REG_OK_STRICT causes the latter definition to be used.
+
+   Most source files want to accept pseudo regs in the hope that
+   they will get allocated to the class that the insn wants them to be in.
+   Source files for reload pass need to be strict.
+   After reload, it makes no difference, since pseudo regs have
+   been eliminated by then.  */
+
+#ifndef REG_OK_STRICT
+
+/* Nonzero if X is a hard reg that can be used as an index
+   or if it is a pseudo reg.  */
+#define REG_OK_FOR_INDEX_P(X) 1
+/* Nonzero if X is a hard reg that can be used as a base reg
+   or if it is a pseudo reg.  */
+#define REG_OK_FOR_BASE_P(X) 1
+
+#else
+
+/* Nonzero if X is a hard reg that can be used as an index.  */
+#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
+/* Nonzero if X is a hard reg that can be used as a base reg.  */
+#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
+
+#endif
+
+/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
+   that is a valid memory address for an instruction.
+   The MODE argument is the machine mode for the MEM expression
+   that wants to use this address.
+
+   CONSTANT_ADDRESS_P is actually machine-independent.  */
+
+#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)  \
+{ 									\
+  if (GET_CODE (X) == REG) goto ADDR;					\
+  if (CONSTANT_ADDRESS_P (X)) goto ADDR; 				\
+  if (GET_CODE (X) == PLUS)						\
+    { /* Handle [index]<address> represented with index-sum outermost */\
+      if (GET_CODE (XEXP (X, 0)) == REG && \
+	  GET_CODE (XEXP (X, 1)) == CONST_INT) \
+	goto ADDR;							\
+      if (GET_CODE (XEXP (X, 1)) == REG && \
+	  GET_CODE (XEXP (X, 0)) == CONST_INT) \
+	goto ADDR; } \
+ }
+
+
+/* Try machine-dependent ways of modifying an illegitimate address
+   to be legitimate.  If we find one, return the new, valid address.
+   This macro is used in only one place: `memory_address' in explow.c.
+
+   OLDX is the address as it was before break_out_memory_refs was called.
+   In some cases it is useful to look at this to decide what needs to be done.
+
+   MODE and WIN are passed so that this macro can use
+   GO_IF_LEGITIMATE_ADDRESS.
+
+   It is always safe for this macro to do nothing.  It exists to recognize
+   opportunities to optimize the output.
+
+   For the vax, nothing needs to be done.  */
+
+#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)  {}
+
+/* Go to LABEL if ADDR (a legitimate address expression)
+   has an effect that depends on the machine mode it is used for. */
+#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
+
+
+/* Specify the machine mode that this machine uses
+   for the index in the tablejump instruction.  */
+#define CASE_VECTOR_MODE SImode
+
+/* Define this if the case instruction expects the table
+   to contain offsets from the address of the table.
+   Do not define this if the table should contain absolute addresses.  */
+/* #define CASE_VECTOR_PC_RELATIVE */
+
+/* Specify the tree operation to be used to convert reals to integers.  */
+#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
+
+/* This is the kind of divide that is easiest to do in the general case.  */
+#define EASY_DIV_EXPR TRUNC_DIV_EXPR
+
+/* Define this as 1 if `char' should by default be signed; else as 0.  */
+#define DEFAULT_SIGNED_CHAR 1
+
+/* This flag, if defined, says the same insns that convert to a signed fixnum
+   also convert validly to an unsigned one.  */
+#define FIXUNS_TRUNC_LIKE_FIX_TRUNC
+
+/* Max number of bytes we can move from memory to memory
+   in one reasonably fast instruction.  */
+#define MOVE_MAX 8
+
+/* Define this if zero-extension is slow (more than one real instruction).  */
+/* #define SLOW_ZERO_EXTEND */
+
+/* Nonzero if access to memory by bytes is slow and undesirable.  */
+#define SLOW_BYTE_ACCESS 0
+
+/* Define if shifts truncate the shift count
+   which implies one can omit a sign-extension or zero-extension
+   of a shift count.  */
+/* #define SHIFT_COUNT_TRUNCATED */
+
+/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
+   is done just by pretending it is already truncated.  */
+#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
+
+/* Specify the machine mode that pointers have.
+   After generation of rtl, the compiler makes no further distinction
+   between pointers and any other objects of this machine mode.  */
+#define Pmode SImode
+
+/* A function address in a call instruction
+   is a byte address (for indexing purposes)
+   so give the MEM rtx a byte's mode.  */
+#define FUNCTION_MODE QImode
+
+/* Compute the cost of computing a constant rtl expression RTX
+   whose rtx-code is CODE.  The body of this macro is a portion
+   of a switch statement.  If the code is computed here,
+   return it with a return statement.  Otherwise, break from the switch.  */
+
+#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
+  case CONST_INT:						\
+    /* Constant zero is super cheap due to clr instruction.  */	\
+    if (RTX == const0_rtx) return 0;				\
+    if ((unsigned) INTVAL (RTX) < 077) return 1;		\
+  case CONST:							\
+  case LABEL_REF:						\
+  case SYMBOL_REF:						\
+    return 3;							\
+  case CONST_DOUBLE:						\
+    return 5;
+
+/*
+ * We can use the BSD C library routines for the gnulib calls that are
+ * still generated, since that's what they boil down to anyways.
+ */
+
+/* #define UDIVSI3_LIBCALL "*udiv" */
+/* #define UMODSI3_LIBCALL "*urem" */
+
+/* Check a `double' value for validity for a particular machine mode.  */
+
+/* note that it is very hard to accidently create a number that fits in a
+   double but not in a float, since their ranges are almost the same */
+#define CHECK_FLOAT_VALUE(mode, d) \
+  if ((mode) == SFmode) \
+    { \
+      if ((d) > 1.7014117331926443e+38) \
+	{ error ("magnitude of constant too large for `float'"); \
+	  (d) = 1.7014117331926443e+38; } \
+      else if ((d) < -1.7014117331926443e+38) \
+	{ error ("magnitude of constant too large for `float'"); \
+	  (d) = -1.7014117331926443e+38; } \
+      else if (((d) > 0) && ((d) < 2.9387358770557188e-39)) \
+	{ warning ("`float' constant truncated to zero"); \
+	  (d) = 0.0; } \
+      else if (((d) < 0) && ((d) > -2.9387358770557188e-39)) \
+	{ warning ("`float' constant truncated to zero"); \
+	  (d) = 0.0; } \
+    }
+
+/* Tell final.c how to eliminate redundant test instructions.  */
+
+/* Here we define machine-dependent flags and fields in cc_status
+   (see `conditions.h').  No extra ones are needed for the vax.  */
+
+/* Store in cc_status the expressions
+   that the condition codes will describe
+   after execution of an instruction whose pattern is EXP.
+   Do not alter them if the instruction would not alter the cc's.  */
+
+#define NOTICE_UPDATE_CC(EXP, INSN) \
+	CC_STATUS_INIT;
+
+
+/* Control the assembler format that we output.  */
+
+/* Output the name of the file we are compiling.  */
+#define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
+    fprintf(STREAM, "\t.file\t\"%s\"\n", NAME);
+
+/* Output at beginning of assembler file.  */
+#define ASM_FILE_START(FILE) fprintf (FILE, "");
+
+/* Output to assembler file text saying following lines
+   may contain character constants, extra white space, comments, etc.  */
+
+#define ASM_APP_ON ""
+
+/* Output to assembler file text saying following lines
+   no longer contain unusual constructs.  */
+
+#define ASM_APP_OFF ""
+
+/* Output before read-only data.  */
+
+#define TEXT_SECTION_ASM_OP "\t.inst"
+
+/* Output before writable data.  */
+
+#define DATA_SECTION_ASM_OP "\t.var"
+
+/* How to refer to registers in assembler output.
+   This sequence is indexed by compiler's hard-register-number (see above).  */
+
+#define REGISTER_NAMES \
+{".r0", ".r1", ".r2", ".r3", ".r4", ".r5", ".r6", ".r7", ".r8", \
+ ".r9", ".r10", ".r11", ".r12", ".r13", ".r14", ".sp"}
+
+/* This is BSD, so it wants DBX format.  */
+
+/* #define DBX_DEBUGGING_INFO */
+
+/* How to renumber registers for dbx and gdb.
+   Vax needs no change in the numeration.  */
+
+#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
+
+/* Do not break .stabs pseudos into continuations.  */
+
+#define DBX_CONTIN_LENGTH 0
+
+/* This is the char to use for continuation (in case we need to turn
+   continuation back on).  */
+
+#define DBX_CONTIN_CHAR '?'
+
+/* Don't use the `xsfoo;' construct in DBX output; this system
+   doesn't support it.  */
+
+#define DBX_NO_XREFS
+
+/* This is how to output the definition of a user-level label named NAME,
+   such as the label on a static function or variable NAME.  */
+
+#define ASM_OUTPUT_LABEL(FILE,NAME)	\
+  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
+
+/* This is how to output a command to make the user-level label named NAME
+   defined for reference from other files.  */
+
+#define ASM_GLOBALIZE_LABEL(FILE,NAME)	\
+  do { fputs ("\t.extdef\t", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
+
+/* This is how to output a reference to a user-level label named NAME.  */
+
+#define ASM_OUTPUT_LABELREF(FILE,NAME)	\
+  fprintf (FILE, "%s", NAME)
+
+/* This is how to output an internal numbered label where
+   PREFIX is the class of label and NUM is the number within the class.  */
+
+#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
+  fprintf (FILE, ".%s%d:\n", PREFIX, NUM)
+
+/* This is how to store into the string LABEL
+   the symbol_ref name of an internal numbered label where
+   PREFIX is the class of label and NUM is the number within the class.
+   This is suitable for output with `assemble_name'.  */
+
+#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
+  sprintf (LABEL, ".%s%d", PREFIX, NUM)
+
+/* This is how to output an assembler line defining a `double' constant.
+   It is .dfloat or .gfloat, depending.  */
+
+#define ASM_OUTPUT_DOUBLE(FILE,VALUE)  \
+{ union {double d; int i[2]; } tem;				\
+  tem.d = (VALUE);						\
+  fprintf (FILE, "\t.data\t%d{32}, %d{32}\n", tem.i[0], tem.i[1]); }
+
+/* This is how to output an assembler line defining a `float' constant.  */
+
+#define ASM_OUTPUT_FLOAT(FILE,VALUE)  \
+{ union {float f; int i; } tem;					\
+  tem.f = (VALUE);						\
+  fprintf (FILE, "\t.data %d{32}\n", tem.i); }
+
+/* This is how to output an assembler line defining an `int' constant.  */
+
+#define ASM_OUTPUT_INT(FILE,VALUE)  \
+( \
+	fprintf (FILE, "\t.data\t"),			\
+  output_addr_const (FILE, (VALUE)),		\
+  fprintf (FILE, "{32}\n"))
+
+#define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE)			\
+{								\
+	fprintf (FILE, "\t.data\t");				\
+	if (GET_CODE (VALUE) == CONST_DOUBLE)			\
+	{							\
+		fprintf (FILE, "%d", CONST_DOUBLE_HIGH (VALUE)); \
+		fprintf (FILE, "{32}, ");			\
+		fprintf (FILE, "%d", CONST_DOUBLE_LOW (VALUE)); \
+		fprintf (FILE, "{32}\n");			\
+	} else if (GET_CODE (VALUE) == CONST_INT)		\
+	{							\
+		int val = INTVAL (VALUE);			\
+		fprintf (FILE, "%d", val < 0 ? -1 : 0);		\
+		fprintf (FILE, "{32}, ");			\
+		fprintf (FILE, "%d", val);			\
+		fprintf (FILE, "{32}\n");			\
+	} else abort ();					\
+}
+
+/* Likewise for `char' and `short' constants.  */
+
+#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
+( fprintf (FILE, "\t.data\t"),			\
+  output_addr_const (FILE, (VALUE)),		\
+  fprintf (FILE, "{16}\n"))
+
+#define ASM_OUTPUT_CHAR(FILE,VALUE)  \
+( fprintf (FILE, "\t.data\t"),			\
+  output_addr_const (FILE, (VALUE)),		\
+  fprintf (FILE, "{8}\n"))
+
+/* This is how to output an assembler line for a numeric constant byte.  */
+
+#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
+  fprintf (FILE, "\t.data\t%d{8}\n", (VALUE))
+
+/* This is how to output an insn to push a register on the stack.
+   It need not be very fast code.  */
+
+#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)  \
+  fprintf (FILE, "\tsubi.64\t4,.sp\n\tst.32\t%s,[.sp]\n", reg_names[REGNO])
+
+/* This is how to output an insn to pop a register from the stack.
+   It need not be very fast code.  */
+
+#define ASM_OUTPUT_REG_POP(FILE,REGNO)  \
+  fprintf (FILE, "\tld.32\t%s,[.sp]\n\taddi.64\t4,.sp\n", reg_names[REGNO])
+
+/* This is how to output an element of a case-vector that is absolute.
+   (The Vax does not use such vectors,
+   but we must define this macro anyway.)  */
+
+#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
+  fprintf (FILE, "\t.data .L%d{32}\n", VALUE)
+
+/* This is how to output an element of a case-vector that is relative.  */
+
+#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL)  \
+  fprintf (FILE, "\t.data .L%d-.L%d{32}\n", VALUE, REL)
+
+/* This is how to output an assembler line
+   that says to advance the location counter
+   to a multiple of 2**LOG bytes.  */
+
+#define ASM_OUTPUT_ALIGN(FILE,LOG)  \
+  if (LOG!=0) fprintf (FILE, "\t.align\t%d\n", (LOG)); else 0
+
+/* This is how to output an assembler line
+   that says to advance the location counter by SIZE bytes.  */
+
+#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
+  fprintf (FILE, "\t.space %d\n", (SIZE))
+
+/* This says how to output an assembler line
+   to define a global common symbol.  */
+
+#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
+( fputs (".comm ", (FILE)),			\
+  assemble_name ((FILE), (NAME)),		\
+  fprintf ((FILE), ",%d\n", (ROUNDED)))
+
+/* This says how to output an assembler line
+   to define a local common symbol.  */
+
+#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
+( fputs (".bss ", (FILE)),			\
+  assemble_name ((FILE), (NAME)),		\
+  fprintf ((FILE), ",%d,%d\n", (SIZE),(ROUNDED)))
+
+/* Store in OUTPUT a string (made with alloca) containing
+   an assembler-name for a local static variable named NAME.
+   LABELNO is an integer which is different for each call.  */
+
+#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
+( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
+  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
+
+/* Define the parentheses used to group arithmetic operations
+   in assembler code.  */
+
+#define ASM_OPEN_PAREN "("
+#define ASM_CLOSE_PAREN ")"
+
+/* Define results of standard character escape sequences.  */
+#define TARGET_BELL 007
+#define TARGET_BS 010
+#define TARGET_TAB 011
+#define TARGET_NEWLINE 012
+#define TARGET_VT 013
+#define TARGET_FF 014
+#define TARGET_CR 015
+
+/* Print an instruction operand X on file FILE.
+   CODE is the code from the %-spec that requested printing this operand;
+   if `%z3' was used to print operand 3, then CODE is 'z'.  */
+
+#define PRINT_OPERAND(FILE, X, CODE)  \
+{ \
+  if (CODE == 'r' && GET_CODE (X) == MEM && GET_CODE (XEXP (X, 0)) == REG)							\
+    fprintf (FILE, "%s", reg_names[REGNO (XEXP (X, 0))]);		\
+  else if (GET_CODE (X) == REG)						\
+    fprintf (FILE, "%s", reg_names[REGNO (X)]);				\
+  else if (GET_CODE (X) == MEM)						\
+    output_address (XEXP (X, 0));					\
+  else \
+  { \
+	/*debug_rtx(X);*/ \
+	putc ('=', FILE); \
+	output_addr_const (FILE, X); } \
+   }
+
+/* Print a memory operand whose address is X, on file FILE.
+   This uses a function in output-vax.c.  */
+
+#define PRINT_OPERAND_ADDRESS(FILE, ADDR)  \
+ print_operand_address (FILE, ADDR)
+
+/* Functions used in the md file. */
+
+extern char *cmp_set();
+extern char *cmp_jmp();
+
+/* These are stubs, and have yet to bee written. */
+
+#define TRAMPOLINE_SIZE 26
+#define TRAMPOLINE_TEMPLATE(FILE)
+#define  INITIALIZE_TRAMPOLINE(TRAMP,FNADDR,CXT)
diff --git a/gcc/config/elxsi/elxsi.md b/gcc/config/elxsi/elxsi.md
new file mode 100644
index 00000000000..f9a0cb69939
--- /dev/null
+++ b/gcc/config/elxsi/elxsi.md
@@ -0,0 +1,1440 @@
+;;- Machine description for GNU compiler
+;;- Elxsi Version
+;;   Copyright (C) 1987, 1988, 1992 Free Software Foundation, Inc.
+;;  This port done by Mike Stump <mrs@cygnus.com> in 1988, and is the first
+;;  64 bit port of GNU CC.
+;;  Based upon the VAX port.
+
+;; This file is part of GNU CC.
+
+;; GNU CC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 1, or (at your option)
+;; any later version.
+
+;; GNU CC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GNU CC; see the file COPYING.  If not, write to
+;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
+
+
+;;- Instruction patterns.  When multiple patterns apply,
+;;- the first one in the file is chosen.
+;;-
+;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
+;;-
+;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
+;;- updates for most instructions.
+
+
+(define_insn ""
+  [(set (reg:SI 15)
+	 (plus:SI (reg:SI 15)
+		  (match_operand:SI 0 "general_operand" "g")))]
+  ""
+  "add.64\\t.sp,%0")
+
+(define_insn ""
+  [(set (reg:SI 15)
+	 (plus:SI (match_operand:SI 0 "general_operand" "g")
+		  (reg:SI 15)))]
+  ""
+  "add.64\\t.sp,%0")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "r")
+	 (plus:SI (reg:SI 15)
+		  (match_operand:SI 1 "general_operand" "g")))]
+  ""
+  "ld.32\\t%0,.sp\;add.64\\t%0,%1")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "r")
+	 (plus:SI (match_operand:SI 1 "general_operand" "g")
+		  (reg:SI 15)))]
+  ""
+  "ld.32\\t%0,.sp\;add.64\\t%0,%1")
+
+(define_insn ""
+  [(set (reg:SI 15)
+	 (minus:SI (reg:SI 15)
+		   (match_operand:SI 0 "general_operand" "g")))]
+  ""
+  "sub.64\\t.sp,%0")
+
+(define_insn ""
+  [(set (reg:SI 15)
+	 (match_operand:SI 0 "general_operand" "rm"))]
+  ""
+  "ld.32\\t.sp,%0")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "m,r")
+	 (reg:SI 15))]
+  ""
+  "*
+  if (which_alternative == 0)
+    return \"st.32\\t.sp,%0\";
+  return \"ld.32\\t%0,.sp\";
+")
+
+; tstdi is first test insn so that it is the one to match
+; a constant argument.
+
+(define_insn "tstdi"
+  [(set (cc0)
+	(match_operand:DI 0 "register_operand" "r"))]
+  ""
+  "*
+    extern rtx cmp_op0, cmp_op1;
+    cmp_op0=operands[0]; cmp_op1=0;
+    return \";\\ttstdi\\t%0\";
+")
+
+(define_insn "tstdf"
+  [(set (cc0)
+	(match_operand:DF 0 "register_operand" "r"))]
+  ""
+  "*
+    extern rtx cmp_op0, cmp_op1;
+    cmp_op0=operands[0]; cmp_op1=0;
+    return \";\\ttstdf\\t%0\";
+")
+
+(define_insn "tstsf"
+  [(set (cc0)
+	(match_operand:SF 0 "register_operand" "r"))]
+  ""
+  "*
+    extern rtx cmp_op0, cmp_op1;
+    cmp_op0=operands[0]; cmp_op1=0;
+    return \";\\ttstsf\\t%0\";
+")
+
+(define_insn "cmpdi"
+  [(set (cc0)
+	(compare (match_operand:DI 0 "register_operand" "r")
+		 (match_operand:DI 1 "general_operand" "rm")))]
+  ""
+  "*
+    extern rtx cmp_op0, cmp_op1;
+    cmp_op0=operands[0]; cmp_op1=operands[1];
+    return \";\\tcmpdi\\t%0,%1\";
+")
+
+(define_insn "cmpdf"
+  [(set (cc0)
+	(compare (match_operand:DF 0 "register_operand" "r")
+		 (match_operand:DF 1 "general_operand" "rm")))]
+  ""
+  "*
+    extern rtx cmp_op0, cmp_op1;
+    cmp_op0=operands[0]; cmp_op1=operands[1];
+    return \";\\tcmpdf\\t%0,%1\";
+")
+
+(define_insn "cmpsf"
+  [(set (cc0)
+	(compare (match_operand:SF 0 "register_operand" "r")
+		 (match_operand:SF 1 "general_operand" "rm")))]
+  ""
+  "*
+    extern rtx cmp_op0, cmp_op1;
+    cmp_op0=operands[0]; cmp_op1=operands[1];
+    return \";\\tcmpsf\\t%0,%1\";
+")
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (eq (match_operand:DI 1 "register_operand" "r")
+	         (match_operand:DI 2 "general_operand" "g")))]
+  ""
+  "cmp.64\\t%0,%1,%2:eq")
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (ne (match_operand:DI 1 "register_operand" "r")
+	         (match_operand:DI 2 "general_operand" "g")))]
+  ""
+  "cmp.64\\t%0,%1,%2:ne")
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (le (match_operand:DI 1 "register_operand" "r")
+	         (match_operand:DI 2 "general_operand" "g")))]
+  ""
+  "cmp.64\\t%0,%1,%2:le")
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (leu (match_operand:DI 1 "register_operand" "r")
+	         (match_operand:DI 2 "general_operand" "g")))]
+  ""
+  "cmpu.64\\t%0,%1,%2:le")
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (lt (match_operand:DI 1 "register_operand" "r")
+	         (match_operand:DI 2 "general_operand" "g")))]
+  ""
+  "cmp.64\\t%0,%1,%2:lt")
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (ltu (match_operand:DI 1 "register_operand" "r")
+	         (match_operand:DI 2 "general_operand" "g")))]
+  ""
+  "cmpu.64\\t%0,%1,%2:lt")
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (ge (match_operand:DI 1 "register_operand" "r")
+	         (match_operand:DI 2 "general_operand" "g")))]
+  ""
+  "cmp.64\\t%0,%1,%2:ge")
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (geu (match_operand:DI 1 "register_operand" "r")
+	         (match_operand:DI 2 "general_operand" "g")))]
+  ""
+  "cmpu.64\\t%0,%1,%2:ge")
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (gt (match_operand:DI 1 "register_operand" "r")
+	         (match_operand:DI 2 "general_operand" "g")))]
+  ""
+  "cmp.64\\t%0,%1,%2:gt")
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (gtu (match_operand:DI 1 "register_operand" "r")
+	         (match_operand:DI 2 "general_operand" "g")))]
+  ""
+  "cmpu.64\\t%0,%1,%2:gt")
+
+(define_insn "seq"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(eq (cc0) (const_int 0)))]
+  ""
+  "* return cmp_set(\"\", \"eq\", operands[0]); ")
+
+(define_insn "sne"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(ne (cc0) (const_int 0)))]
+  ""
+  "* return cmp_set(\"\", \"ne\", operands[0]); ")
+
+(define_insn "sle"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(le (cc0) (const_int 0)))]
+  ""
+  "* return cmp_set(\"\", \"le\", operands[0]); ")
+
+(define_insn "sleu"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(leu (cc0) (const_int 0)))]
+  ""
+  "* return cmp_set(\"u\", \"le\", operands[0]); ")
+
+(define_insn "slt"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(lt (cc0) (const_int 0)))]
+  ""
+  "* return cmp_set(\"\", \"lt\", operands[0]); ")
+
+(define_insn "sltu"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(ltu (cc0) (const_int 0)))]
+  ""
+  "* return cmp_set(\"u\", \"lt\", operands[0]); ")
+
+(define_insn "sge"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(ge (cc0) (const_int 0)))]
+  ""
+  "* return cmp_set(\"\", \"ge\", operands[0]); ")
+
+(define_insn "sgeu"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(geu (cc0) (const_int 0)))]
+  ""
+  "* return cmp_set(\"u\", \"ge\", operands[0]); ")
+
+(define_insn "sgt"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(gt (cc0) (const_int 0)))]
+  ""
+  "* return cmp_set(\"\", \"gt\", operands[0]); ")
+
+(define_insn "sgtu"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(gtu (cc0) (const_int 0)))]
+  ""
+  "* return cmp_set(\"u\", \"gt\", operands[0]); ")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(eq (match_operand:SI 1 "register_operand" "r")
+	    (match_operand:SI 2 "general_operand" "m")))]
+  ""
+  "cmp.32\\t%0,%1,%2:eq")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(ne (match_operand:SI 1 "register_operand" "r")
+	    (match_operand:SI 2 "general_operand" "m")))]
+  ""
+  "cmp.32\\t%0,%1,%2:ne")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(le (match_operand:SI 1 "register_operand" "r")
+	    (match_operand:SI 2 "general_operand" "m")))]
+  ""
+  "cmp.32\\t%0,%1,%2:le")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(leu (match_operand:SI 1 "register_operand" "r")
+	    (match_operand:SI 2 "general_operand" "m")))]
+  ""
+  "cmpu.32\\t%0,%1,%2:le")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(lt (match_operand:SI 1 "register_operand" "r")
+	    (match_operand:SI 2 "general_operand" "m")))]
+  ""
+  "cmp.32\\t%0,%1,%2:lt")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(ltu (match_operand:SI 1 "register_operand" "r")
+	    (match_operand:SI 2 "general_operand" "m")))]
+  ""
+  "cmpu.32\\t%0,%1,%2:lt")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(ge (match_operand:SI 1 "register_operand" "r")
+	    (match_operand:SI 2 "general_operand" "m")))]
+  ""
+  "cmp.32\\t%0,%1,%2:ge")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(geu (match_operand:SI 1 "register_operand" "r")
+	    (match_operand:SI 2 "general_operand" "m")))]
+  ""
+  "cmpu.32\\t%0,%1,%2:ge")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(gt (match_operand:SI 1 "register_operand" "r")
+	    (match_operand:SI 2 "general_operand" "m")))]
+  ""
+  "cmp.32\\t%0,%1,%2:gt")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(gtu (match_operand:SI 1 "register_operand" "r")
+	    (match_operand:SI 2 "general_operand" "m")))]
+  ""
+  "cmpu.32\\t%0,%1,%2:gt")
+
+(define_insn ""
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(eq (match_operand:HI 1 "register_operand" "r")
+	    (match_operand:HI 2 "general_operand" "m")))]
+  ""
+  "cmp.16\\t%0,%1,%2:eq")
+
+(define_insn ""
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(ne (match_operand:HI 1 "register_operand" "r")
+	    (match_operand:HI 2 "general_operand" "m")))]
+  ""
+  "cmp.16\\t%0,%1,%2:ne")
+
+(define_insn ""
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(le (match_operand:HI 1 "register_operand" "r")
+	    (match_operand:HI 2 "general_operand" "m")))]
+  ""
+  "cmp.16\\t%0,%1,%2:le")
+
+(define_insn ""
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(leu (match_operand:HI 1 "register_operand" "r")
+	    (match_operand:HI 2 "general_operand" "m")))]
+  ""
+  "cmpu.16\\t%0,%1,%2:le")
+
+(define_insn ""
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(lt (match_operand:HI 1 "register_operand" "r")
+	    (match_operand:HI 2 "general_operand" "m")))]
+  ""
+  "cmp.16\\t%0,%1,%2:lt")
+
+(define_insn ""
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(ltu (match_operand:HI 1 "register_operand" "r")
+	    (match_operand:HI 2 "general_operand" "m")))]
+  ""
+  "cmpu.16\\t%0,%1,%2:lt")
+
+(define_insn ""
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(ge (match_operand:HI 1 "register_operand" "r")
+	    (match_operand:HI 2 "general_operand" "m")))]
+  ""
+  "cmp.16\\t%0,%1,%2:ge")
+
+(define_insn ""
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(geu (match_operand:HI 1 "register_operand" "r")
+	    (match_operand:HI 2 "general_operand" "m")))]
+  ""
+  "cmpu.16\\t%0,%1,%2:ge")
+
+(define_insn ""
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(gt (match_operand:HI 1 "register_operand" "r")
+	    (match_operand:HI 2 "general_operand" "m")))]
+  ""
+  "cmp.16\\t%0,%1,%2:gt")
+
+(define_insn ""
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(gtu (match_operand:HI 1 "register_operand" "r")
+	    (match_operand:HI 2 "general_operand" "m")))]
+  ""
+  "cmpu.16\\t%0,%1,%2:gt")
+
+(define_insn ""
+  [(set (match_operand:QI 0 "register_operand" "=r")
+	(eq (match_operand:QI 1 "register_operand" "r")
+	    (match_operand:QI 2 "general_operand" "m")))]
+  ""
+  "cmp.8\\t%0,%1,%2:eq")
+
+(define_insn ""
+  [(set (match_operand:QI 0 "register_operand" "=r")
+	(ne (match_operand:QI 1 "register_operand" "r")
+	    (match_operand:QI 2 "general_operand" "m")))]
+  ""
+  "cmp.8\\t%0,%1,%2:ne")
+
+(define_insn ""
+  [(set (match_operand:QI 0 "register_operand" "=r")
+	(le (match_operand:QI 1 "register_operand" "r")
+	    (match_operand:QI 2 "general_operand" "m")))]
+  ""
+  "cmp.8\\t%0,%1,%2:le")
+
+(define_insn ""
+  [(set (match_operand:QI 0 "register_operand" "=r")
+	(leu (match_operand:QI 1 "register_operand" "r")
+	    (match_operand:QI 2 "general_operand" "m")))]
+  ""
+  "cmpu.8\\t%0,%1,%2:le")
+
+(define_insn ""
+  [(set (match_operand:QI 0 "register_operand" "=r")
+	(lt (match_operand:QI 1 "register_operand" "r")
+	    (match_operand:QI 2 "general_operand" "m")))]
+  ""
+  "cmp.8\\t%0,%1,%2:lt")
+
+(define_insn ""
+  [(set (match_operand:QI 0 "register_operand" "=r")
+	(ltu (match_operand:QI 1 "register_operand" "r")
+	    (match_operand:QI 2 "general_operand" "m")))]
+  ""
+  "cmpu.8\\t%0,%1,%2:lt")
+
+(define_insn ""
+  [(set (match_operand:QI 0 "register_operand" "=r")
+	(ge (match_operand:QI 1 "register_operand" "r")
+	    (match_operand:QI 2 "general_operand" "m")))]
+  ""
+  "cmp.8\\t%0,%1,%2:ge")
+
+(define_insn ""
+  [(set (match_operand:QI 0 "register_operand" "=r")
+	(geu (match_operand:QI 1 "register_operand" "r")
+	    (match_operand:QI 2 "general_operand" "m")))]
+  ""
+  "cmpu.8\\t%0,%1,%2:ge")
+
+(define_insn ""
+  [(set (match_operand:QI 0 "register_operand" "=r")
+	(gt (match_operand:QI 1 "register_operand" "r")
+	    (match_operand:QI 2 "general_operand" "m")))]
+  ""
+  "cmp.8\\t%0,%1,%2:gt")
+
+(define_insn ""
+  [(set (match_operand:QI 0 "register_operand" "=r")
+	(gtu (match_operand:QI 1 "register_operand" "r")
+	    (match_operand:QI 2 "general_operand" "m")))]
+  ""
+  "cmpu.8\\t%0,%1,%2:gt")
+
+
+
+(define_insn "movdf"  [(set (match_operand:DF 0 "general_operand" "=r,m")
+	(match_operand:DF 1 "general_operand" "rm,r"))]
+  ""
+  "*
+{
+  if (which_alternative == 0)
+    return \"ld.64\\t%0,%1\";
+  return \"st.64\\t%1,%0\";
+}")
+
+(define_insn "movsf"
+  [(set (match_operand:SF 0 "general_operand" "=r,m")
+	(match_operand:SF 1 "general_operand" "rm,r"))]
+  ""
+  "*
+{
+  if (which_alternative == 0)
+    return \"ld.32\\t%0,%1\";
+  return \"st.32\\t%1,%0\";
+}")
+
+(define_insn "movdi"
+  [(set (match_operand:DI 0 "general_operand" "=r,m,rm")
+	(match_operand:DI 1 "general_operand" "g,r,I"))]
+  ""
+  "*
+  if (which_alternative == 0)
+    return \"ld.64\\t%0,%1\";
+  else if (which_alternative == 1)
+    return \"st.64\\t%1,%0\";
+  else
+    if (GET_CODE(operands[1])==CONST_INT) {
+      if (INTVAL(operands[1]) >= 0)
+        return \"sti.64\\t%c1,%0\";
+      else
+        return \"stin.64\\t%n1,%0\";
+    }
+")
+
+(define_insn "movsi"
+  [(set (match_operand:SI 0 "general_operand" "=r,m,r")
+	(match_operand:SI 1 "general_operand" "rm,rI,i"))]
+  ""
+  "*
+  if (which_alternative == 0)
+    return \"ld.32\\t%0,%1\";
+  else if (which_alternative == 1) {
+    if (GET_CODE(operands[1])==CONST_INT) {
+      if (INTVAL(operands[1]) >= 0)
+        return \"sti.32\\t%c1,%0\";
+      else
+        return \"stin.32\\t%n1,%0\";
+    }
+    return \"st.32\\t%1,%0\";
+  } else
+    return \"ld.64\\t%0,%1 ; I only want 32\";
+")
+
+(define_insn "movhi"
+  [(set (match_operand:HI 0 "general_operand" "=r,m,r")
+	(match_operand:HI 1 "general_operand" "m,rI,ri"))]
+  ""
+  "*
+{
+  if (which_alternative == 0)
+    return \"ld.16\\t%0,%1\";
+  if (which_alternative == 2)
+    return \"ld.64\\t%0,%1\\t; I only want 16\";
+  if (GET_CODE(operands[1])==CONST_INT) {
+    if (INTVAL(operands[1]) >= 0)
+      return \"sti.16\\t%c1,%0\";
+    else
+      return \"stin.16\\t%n1,%0\";
+  }
+  return \"st.16\\t%1,%0\";
+}")
+
+(define_insn "movqi"
+  [(set (match_operand:QI 0 "general_operand" "=r,m,r")
+	(match_operand:QI 1 "general_operand" "m,rI,ri"))]
+  ""
+  "*
+{
+  if (which_alternative == 0)
+    return \"ld.8\\t%0,%1\";
+  if (which_alternative == 2)
+    return \"ld.64\\t%0,%1\\t; I only want 8\";
+  if (GET_CODE(operands[1])==CONST_INT) {
+    if (INTVAL(operands[1]) >= 0)
+      return \"sti.8\\t%c1,%0\";
+    else
+      return \"stin.8\\t%n1,%0\";
+  }
+  return \"st.8\\t%1,%0\";
+}")
+
+;; Extension and truncation insns.
+;; Those for integer source operand
+;; are ordered widest source type first.
+
+(define_insn "truncdfsf2"
+  [(set (match_operand:SF 0 "register_operand" "=r")
+	(truncate:SF (match_operand:DF 1 "general_operand" "rm")))]
+  ""
+  "cvt.ds\\t%0,%1")
+
+(define_insn "truncdiqi2"
+  [(set (match_operand:QI 0 "general_operand" "=r,m,r")
+	(truncate:QI (match_operand:DI 1 "general_operand" "m,r,0")))]
+  ""
+  "*
+{
+  if (which_alternative == 0)
+    return \"ld.8\\t%0,%1\";
+  else if (which_alternative == 1)
+    return \"st.8\\t%1,%0\";
+  return \"\";
+}")
+
+(define_insn "truncdihi2"
+  [(set (match_operand:HI 0 "general_operand" "=r,m,r")
+	(truncate:HI (match_operand:DI 1 "general_operand" "m,r,0")))]
+  ""
+  "*
+{
+  if (which_alternative == 0)
+    return \"ld.16\\t%0,%1\";
+  if (which_alternative == 1)
+    return \"st.16\\t%1,%0\";
+  return \"\";
+}")
+
+(define_insn "truncdisi2"
+  [(set (match_operand:SI 0 "general_operand" "=r,m")
+	(truncate:SI (match_operand:DI 1 "general_operand" "rm,r")))]
+  ""
+  "*
+{
+  if (which_alternative == 0)
+    return \"ld.32\\t%0,%1\";
+  return \"st.32\\t%1,%0\";
+}")
+
+(define_insn "truncsiqi2"
+  [(set (match_operand:QI 0 "general_operand" "=r,m,r")
+	(truncate:QI (match_operand:SI 1 "general_operand" "m,r,0")))]
+  ""
+  "*
+{
+  if (which_alternative == 0)
+    return \"ld.8\\t%0,%1\";
+  if (which_alternative == 1)
+    return \"st.8\\t%1,%0\";
+  return \"\";
+}")
+
+(define_insn "truncsihi2"
+  [(set (match_operand:HI 0 "general_operand" "=r,m,r")
+	(truncate:HI (match_operand:SI 1 "general_operand" "m,r,0")))]
+  ""
+  "*
+{
+  if (which_alternative == 0)
+    return \"ld.16\\t%0,%1\";
+  if (which_alternative == 1)
+    return \"st.16\\t%1,%0\";
+  return \"\";
+}")
+
+(define_insn "trunchiqi2"
+  [(set (match_operand:QI 0 "general_operand" "=r,m,r")
+	(truncate:QI (match_operand:HI 1 "general_operand" "m,r,0")))]
+  ""
+  "*
+{
+  if (which_alternative == 0)
+    return \"ld.8\\t%0,%1\";
+  if (which_alternative == 1)
+    return \"st.8\\t%1,%0\";
+  return \"\";
+}")
+
+(define_insn "extendsfdf2"
+  [(set (match_operand:DF 0 "register_operand" "=r")
+	(sign_extend:DF (match_operand:SF 1 "general_operand" "rm")))]
+  ""
+  "cvt.sd\\t%0,%1")
+
+(define_insn "extendsidi2"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(sign_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
+  ""
+  "ld.32\\t%0,%1")
+
+(define_insn "extendhisi2"
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
+	(sign_extend:SI (match_operand:HI 1 "general_operand" "m,r")))]
+  ""
+  "*
+     if (which_alternative==0)
+       return \"ld.16\\t%0,%1\";
+     return \"extract\\t%0,%1:bit 48,16\";
+")
+
+(define_insn "extendhidi2"
+  [(set (match_operand:DI 0 "register_operand" "=r,r")
+	(sign_extend:DI (match_operand:HI 1 "general_operand" "m,r")))]
+  ""
+  "*
+     if (which_alternative==0)
+       return \"ld.16\\t%0,%1\";
+     return \"extract\\t%0,%1:bit 48,16\";
+")
+
+(define_insn "extendqihi2"
+  [(set (match_operand:HI 0 "register_operand" "=r,r")
+	(sign_extend:HI (match_operand:QI 1 "general_operand" "m,r")))]
+  ""
+  "*
+     if (which_alternative==0)
+       return \"ld.8\\t%0,%1\";
+     return \"extract\\t%0,%1:bit 56,8\";
+")
+
+(define_insn "extendqisi2"
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
+	(sign_extend:SI (match_operand:QI 1 "general_operand" "m,r")))]
+  ""
+  "*
+     if (which_alternative==0)
+       return \"ld.8\\t%0,%1\";
+     return \"extract\\t%0,%1:bit 56,8\";
+")
+
+(define_insn "extendqidi2"
+  [(set (match_operand:DI 0 "register_operand" "=r,r")
+	(sign_extend:DI (match_operand:QI 1 "general_operand" "m,r")))]
+  ""
+  "*
+     if (which_alternative==0)
+       return \"ld.8\\t%0,%1\";
+     return \"extract\\t%0,%1:bit 56,8\";
+")
+
+(define_insn "zero_extendsidi2"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
+  ""
+  "ldz.32\\t%0,%1")
+
+
+(define_insn "zero_extendhisi2"
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
+	(zero_extend:SI (match_operand:HI 1 "general_operand" "m,r")))]
+  ""
+  "*
+     if (which_alternative==0)
+       return \"ldz.16\\t%0,%1\";
+     return \"extractz\\t%0,%1:bit 48,16\";
+")
+
+(define_insn "zero_extendhidi2"
+  [(set (match_operand:DI 0 "register_operand" "=r,r")
+	(zero_extend:DI (match_operand:HI 1 "general_operand" "m,r")))]
+  ""
+  "*
+     if (which_alternative==0)
+       return \"ldz.16\\t%0,%1\";
+     return \"extractz\\t%0,%1:bit 48,16\";
+")
+
+(define_insn "zero_extendqihi2"
+  [(set (match_operand:HI 0 "register_operand" "=r,r")
+	(zero_extend:HI (match_operand:QI 1 "general_operand" "m,r")))]
+  ""
+  "*
+     if (which_alternative==0)
+       return \"ldz.8\\t%0,%1\";
+     return \"extractz\\t%0,%1:bit 56,8\";
+")
+
+(define_insn "zero_extendqisi2"
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
+	(zero_extend:SI (match_operand:QI 1 "general_operand" "m,r")))]
+  ""
+  "*
+     if (which_alternative==0)
+       return \"ldz.8\\t%0,%1\";
+     return \"extractz\\t%0,%1:bit 56,8\";
+")
+
+(define_insn "zero_extendqidi2"
+  [(set (match_operand:DI 0 "register_operand" "=r,r")
+	(zero_extend:DI (match_operand:QI 1 "general_operand" "m,r")))]
+  ""
+  "*
+     if (which_alternative==0)
+       return \"ldz.8\\t%0,%1\";
+     return \"extractz\\t%0,%1:bit 56,8\";
+")
+
+
+
+(define_insn "lshldi3"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(lshift:DI (match_operand:DI 1 "register_operand" "r")
+		   (match_operand:SI 2 "general_operand" "rn")))]
+  ""
+  "sll\\t%0,%1,%2")
+
+(define_insn "ashrdi3"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
+		   (match_operand:SI 2 "general_operand" "rn")))]
+  ""
+  "sra\\t%0,%1,%2")
+
+(define_insn "lshrdi3"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
+		   (match_operand:SI 2 "general_operand" "rn")))]
+  ""
+  "srl\\t%0,%1,%2")
+
+(define_insn "ashldi3"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(ashift:DI (match_operand:DI 1 "register_operand" "r")
+		   (match_operand:SI 2 "general_operand" "rn")))]
+  ""
+  "sla\\t%0,%1,%2")
+
+(define_insn "anddi3"
+  [(set (match_operand:DI 0 "register_operand" "=r,r")
+	(and:DI (match_operand:DI 1 "general_operand" "%0,r")
+		(match_operand:DI 2 "general_operand" "g,g")))]
+  "1 /*which_alternative == 0 || check356(operands[2])*/"
+  "*
+    if (which_alternative == 0)
+      return \"and\\t%0,%2\";
+    return \"and\\t%0,%1,%2\";
+")
+
+(define_insn "iordi3"
+  [(set (match_operand:DI 0 "register_operand" "=r,r")
+	(ior:DI (match_operand:DI 1 "general_operand" "%0,r")
+		(match_operand:DI 2 "general_operand" "g,g")))]
+  "1 /*which_alternative == 0 || check356(operands[2])*/"
+  "*
+    if (which_alternative == 0)
+      return \"or\\t%0,%2\";
+    return \"or\\t%0,%1,%2\";
+")
+
+(define_insn "xordi3"
+  [(set (match_operand:DI 0 "register_operand" "=r,r")
+	(xor:DI (match_operand:DI 1 "general_operand" "%0,r")
+		(match_operand:DI 2 "general_operand" "g,g")))]
+  "1 /*which_alternative == 0 || check356(operands[2])*/"
+  "*
+    if (which_alternative == 0)
+      return \"xor\\t%0,%2\";
+    return \"xor\\t%0,%1,%2\";
+")
+
+(define_insn "one_cmpldi2"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(not:DI (match_operand:DI 1 "general_operand" "rm")))]
+  ""
+  "not\\t%0,%1")
+
+;; gcc 2.1 does not widen ~si into ~di.
+(define_insn "one_cmplsi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(not:DI (match_operand:SI 1 "register_operand" "r")))]
+  ""
+  "not\\t%0,%1")
+
+(define_insn "negdi2"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(neg:DI (match_operand:DI 1 "general_operand" "rm")))]
+  ""
+  "neg.64\\t%0,%1")
+
+(define_insn "negsi2"
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
+	(neg:SI (match_operand:SI 1 "general_operand" "m,r")))]
+  ""
+  "*
+    if (which_alternative == 0)
+      return \"neg.32\\t%0,%1\";
+    return \"neg.64\\t%0,%1 ; I only want 32\";
+")
+
+(define_insn "neghi2"
+  [(set (match_operand:HI 0 "register_operand" "=r,r")
+	(neg:HI (match_operand:HI 1 "general_operand" "m,r")))]
+  ""
+  "*
+    if (which_alternative == 0)
+      return \"neg.16\\t%0,%1\";
+    return \"neg.64\\t%0,%1 ; I only want 16\";
+")
+
+(define_insn "adddf3"
+  [(set (match_operand:DF 0 "register_operand" "=r")
+	(plus:DF (match_operand:DF 1 "general_operand" "%0")
+		  (match_operand:DF 2 "general_operand" "rm")))]
+  ""
+  "fadd.64\\t%0,%2")
+
+(define_insn "addsf3"
+  [(set (match_operand:SF 0 "register_operand" "=r")
+	(plus:SF (match_operand:SF 1 "general_operand" "%0")
+		 (match_operand:SF 2 "general_operand" "rm")))]
+  ""
+  "fadd.32\\t%0,%2")
+
+;; There is also an addi.64  4,.r0'' optimization
+(define_insn "adddi3"
+  [(set (match_operand:DI 0 "register_operand" "=r,r")
+	(plus:DI (match_operand:DI 1 "general_operand" "%0,r")
+		 (match_operand:DI 2 "general_operand" "g,g")))]
+  "1 /*which_alternative == 0 || check356(operands[2])*/"
+  "*
+    if (which_alternative == 0)
+      return \"add.64\\t%0,%2\";
+    return \"add.64\\t%0,%1,%2\";
+")
+
+(define_insn "addsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
+	(plus:SI (match_operand:SI 1 "general_operand" "%0,r,0")
+		 (match_operand:SI 2 "general_operand" "m,m,g")))]
+  "1 /*which_alternative != 1 || check356(operands[2])*/"
+  "*
+    if (which_alternative == 0)
+      return \"add.32\\t%0,%2\";
+    if (which_alternative == 1)
+      return \"add.32\\t%0,%1,%2\";
+    return \"add.64\\t%0,%2 ; I only want 32\";
+")
+
+(define_insn "addhi3"
+  [(set (match_operand:HI 0 "register_operand" "=r,r,r")
+	(plus:HI (match_operand:HI 1 "general_operand" "%0,r,0")
+		 (match_operand:HI 2 "general_operand" "m,m,g")))]
+  "1 /*which_alternative != 1 || check356(operands[2])*/"
+  "*
+    if (which_alternative == 0)
+      return \"add.16\\t%0,%2\";
+    if (which_alternative == 1)
+      return \"add.16\\t%0,%1,%2\";
+    return \"add.64\\t%0,%2 ; I only want 16\";
+")
+
+(define_insn "subdf3"
+  [(set (match_operand:DF 0 "register_operand" "=r")
+	(minus:DF (match_operand:DF 1 "general_operand" "0")
+		  (match_operand:DF 2 "general_operand" "rm")))]
+  ""
+  "fsub.64\\t%0,%2")
+
+(define_insn "subsf3"
+  [(set (match_operand:SF 0 "register_operand" "=r")
+	(minus:SF (match_operand:SF 1 "general_operand" "0")
+		  (match_operand:SF 2 "general_operand" "rm")))]
+  ""
+  "fsub.32\\t%0,%2")
+
+(define_insn "subdi3"
+  [(set (match_operand:DI 0 "register_operand" "=r,r,r")
+	(minus:DI (match_operand:DI 1 "general_operand" "0,g,r")
+		  (match_operand:DI 2 "general_operand" "g,r,g")))]
+  "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
+  "*
+    if (which_alternative == 0)
+      return \"sub.64\\t%0,%2\";
+    else if (which_alternative == 1)
+      return \"subr.64\\t%0,%2,%1\";
+    else
+      return \"sub.64\\t%0,%1,%2\";
+")
+
+(define_insn "subsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
+	(minus:SI (match_operand:SI 1 "general_operand" "0,m,r,0")
+		  (match_operand:SI 2 "general_operand" "m,r,m,g")))]
+  "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
+  "*
+    if (which_alternative == 0)
+      return \"sub.32\\t%0,%2\";
+    else if (which_alternative == 1)
+      return \"subr.32\\t%0,%2,%1\";
+    else if (which_alternative == 2)
+      return \"sub.32\\t%0,%1,%2\";
+    else
+      return \"sub.64\\t%0,%2 ; I only want 32\";
+")
+
+(define_insn "subhi3"
+  [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
+	(minus:HI (match_operand:HI 1 "general_operand" "0,m,r,0")
+		  (match_operand:HI 2 "general_operand" "m,r,m,g")))]
+  "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
+  "*
+    if (which_alternative == 0)
+      return \"sub.16\\t%0,%2\";
+    else if (which_alternative == 1)
+      return \"subr.16\\t%0,%2,%1\";
+    else if (which_alternative == 2)
+      return \"sub.16\\t%0,%1,%2\";
+    else
+      return \"sub.64\\t%0,%2 ; I only want 16\";
+")
+
+(define_insn "muldf3"
+  [(set (match_operand:DF 0 "register_operand" "=r")
+	(mult:DF (match_operand:DF 1 "general_operand" "%0")
+		 (match_operand:DF 2 "general_operand" "rm")))]
+  ""
+  "fmul.64\\t%0,%2")
+
+(define_insn "mulsf3"
+  [(set (match_operand:SF 0 "register_operand" "=r")
+	(mult:SF (match_operand:SF 1 "general_operand" "%0")
+		 (match_operand:SF 2 "general_operand" "rm")))]
+  ""
+  "fmul.32\\t%0,%2")
+
+(define_insn "muldi3"
+  [(set (match_operand:DI 0 "register_operand" "=r,r")
+	(mult:DI (match_operand:DI 1 "general_operand" "%0,r")
+		 (match_operand:DI 2 "general_operand" "g,g")))]
+  "1 /*which_alternative == 0 || check356(operands[2])*/"
+  "*
+    if (which_alternative == 0)
+      return \"mul.64\\t%0,%2\";
+    return \"mul.64\\t%0,%1,%2\";
+")
+
+(define_insn "mulsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
+	(mult:SI (match_operand:SI 1 "general_operand" "%0,r,0")
+		 (match_operand:SI 2 "general_operand" "m,m,g")))]
+  "1 /*which_alternative == 0 || check356(operands[2])*/"
+  "*
+    if (which_alternative == 0)
+      return \"mul.32\\t%0,%2\";
+    else if (which_alternative == 1)
+      return \"mul.32\\t%0,%1,%2\";
+    else
+      return \"mul.64\\t%0,%2 ; I only want 32\";
+")
+
+(define_insn "mulhi3"
+  [(set (match_operand:HI 0 "register_operand" "=r,r,r")
+	(mult:HI (match_operand:HI 1 "general_operand" "%0,r,0")
+		 (match_operand:HI 2 "general_operand" "m,m,g")))]
+  "1 /*which_alternative == 0 || check356(operands[2])*/"
+  "*
+    if (which_alternative == 0)
+      return \"mul.16\\t%0,%2\";
+    else if (which_alternative == 1)
+      return \"mul.16\\t%0,%1,%2\";
+    else
+      return \"mul.64\\t%0,%2 ; I only want 16\";
+")
+
+(define_insn "divdf3"
+  [(set (match_operand:DF 0 "register_operand" "=r")
+	(div:DF (match_operand:DF 1 "general_operand" "0")
+		(match_operand:DF 2 "general_operand" "rm")))]
+  ""
+  "fdiv.64\\t%0,%2")
+
+(define_insn "divsf3"
+  [(set (match_operand:SF 0 "register_operand" "=r")
+	(div:SF (match_operand:SF 1 "general_operand" "0")
+		(match_operand:SF 2 "general_operand" "rm")))]
+  ""
+  "fdiv.32\\t%0,%2")
+
+(define_insn "divdi3"
+  [(set (match_operand:DI 0 "register_operand" "=r,r,r")
+	(div:DI (match_operand:DI 1 "general_operand" "0,g,r")
+		(match_operand:DI 2 "general_operand" "g,r,g")))]
+  "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
+  "*
+    if (which_alternative == 0)
+      return \"div.64\\t%0,%2\";
+    else if (which_alternative == 1)
+      return \"divr.64\\t%0,%2,%1\";
+    else
+      return \"div.64\\t%0,%1,%2\";
+")
+
+(define_insn "divsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
+	(div:SI (match_operand:SI 1 "general_operand" "0,m,r,0")
+		(match_operand:SI 2 "general_operand" "m,r,m,g")))]
+  "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
+  "*
+/* We don't ignore high bits. */
+if (0) {
+    if (which_alternative == 0)
+      return \"div.32\\t%0,%2\";
+    else if (which_alternative == 1)
+      return \"divr.32\\t%0,%2,%1\";
+    else if (which_alternative == 2)
+      return \"div.32\\t%0,%1,%2\";
+    else
+      return \"ld.32\\t%0,%0\;div.64\\t%0,%2 ; I only want 32\";
+} else {
+    if (which_alternative == 0)
+      return \"ld.32\\t%0,%0\;div.32\\t%0,%2\";
+    else if (which_alternative == 1)
+      return \"ld.32\\t%2,%2\;divr.32\\t%0,%2,%1\";
+    else if (which_alternative == 2)
+      return \"ld.32\\t%1,%1\;div.32\\t%0,%1,%2\";
+    else
+      return \"ld.32\\t%0,%0\;div.64\\t%0,%2 ; I only want 32\";
+}
+")
+
+(define_insn "divhi3"
+  [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
+	(div:HI (match_operand:HI 1 "general_operand" "0,m,r,0,0")
+		(match_operand:HI 2 "general_operand" "m,r,m,r,i")))]
+  "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
+  "*
+    if (which_alternative == 0)
+      return \"extract\\t%0,%0:bit 48,16\;div.16\\t%0,%2\";
+    else if (which_alternative == 1)
+      return \"extract\\t%2,%2:bit 48,16\;divr.16\\t%0,%2,%1\";
+    else if (which_alternative == 2)
+      return \"extract\\t%1,%1:bit 48,16\;div.16\\t%0,%1,%2\";
+    else if (which_alternative == 3)
+      return \"extract\\t%0,%0:bit 48,16\;extract\\t%2,%2:bit 48,16\;div.64\\t%0,%2 ; I only want 16\";
+    else
+      return \"extract\\t%0,%0:bit 48,16\;div.64\\t%0,%2 ; I only want 16\";
+")
+
+(define_insn "modhi3"
+  [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
+	(mod:HI (match_operand:HI 1 "general_operand" "0,m,r,0,0")
+		(match_operand:HI 2 "general_operand" "m,r,m,r,i")))]
+  "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
+  "*
+    if (which_alternative == 0)
+      return \"extract\\t%0,%0:bit 48,16\;rem.16\\t%0,%2\";
+    else if (which_alternative == 1)
+      return \"extract\\t%2,%2:bit 48,16\;remr.16\\t%0,%2,%1\";
+    else if (which_alternative == 2)
+      return \"extract\\t%1,%1:bit 48,16\;rem.16\\t%0,%1,%2\";
+    else if (which_alternative == 3)
+      return \"extract\\t%0,%0:bit 48,16\;extract\\t%2,%2:bit 48,16\;rem.64\\t%0,%2 ; I only want 16\";
+    else
+      return \"extract\\t%0,%0:bit 48,16\;rem.64\\t%0,%2 ; I only want 16\";
+")
+
+(define_insn "moddi3"
+  [(set (match_operand:DI 0 "register_operand" "=r,r,r")
+	(mod:DI (match_operand:DI 1 "general_operand" "0,g,r")
+		(match_operand:DI 2 "general_operand" "g,r,g")))]
+  "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
+  "*
+    if (which_alternative == 0)
+      return \"rem.64\\t%0,%2\";
+    else if (which_alternative == 1)
+      return \"remr.64\\t%0,%2,%1\";
+    else
+      return \"rem.64\\t%0,%1,%2\";
+")
+
+(define_insn "modsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
+	(mod:SI (match_operand:SI 1 "general_operand" "0,m,r,0")
+		(match_operand:SI 2 "general_operand" "m,r,m,g")))]
+  "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
+  "*
+/* There is a micro code bug with the below... */
+if (0) {
+    if (which_alternative == 0)
+      return \"rem.32\\t%0,%2\";
+    else if (which_alternative == 1)
+      return \"remr.32\\t%0,%2,%1\";
+    else if (which_alternative == 2)
+      return \"rem.32\\t%0,%1,%2\";
+    else
+      return \"ld.32\\t%0,%0\;rem.64\\t%0,%2 ; I only want 32\";
+} else {
+    if (which_alternative == 0)
+      return \"ld.32\\t%0,%0\;rem.32\\t%0,%2\";
+    else if (which_alternative == 1)
+      return \"ld.32\\t%2,%2\;remr.32\\t%0,%2,%1\";
+    else if (which_alternative == 2)
+      return \"ld.32\\t%1,%1\;rem.32\\t%0,%1,%2\";
+    else
+      return \"ld.32\\t%0,%0\;rem.64\\t%0,%2 ; I only want 32\";
+}
+")
+
+
+(define_insn "jump"
+  [(set (pc)
+	(label_ref (match_operand 0 "" "")))]
+  ""
+  "jmp\\t%l0")
+
+(define_insn "indirect_jump"
+  [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
+  ""
+;; Maybe %l0 is better, maybe we can relax register only.
+  "verify this before use ld.32\\t.r0,%0\;br.reg\\t.r0")
+
+(define_insn "beq"
+  [(set (pc)
+	(if_then_else (eq (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "* return cmp_jmp(\"\", 2, operands[0]); ")
+
+(define_insn "bne"
+  [(set (pc)
+	(if_then_else (ne (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "* return cmp_jmp(\"\", 8, operands[0]); ")
+
+(define_insn "bgt"
+  [(set (pc)
+	(if_then_else (gt (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "* return cmp_jmp(\"\", 0, operands[0]); ")
+
+(define_insn "bgtu"
+  [(set (pc)
+	(if_then_else (gtu (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "* return cmp_jmp(\"u\", 0, operands[0]); ")
+
+(define_insn "blt"
+  [(set (pc)
+	(if_then_else (lt (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "* return cmp_jmp(\"\", 6, operands[0]); ")
+
+(define_insn "bltu"
+  [(set (pc)
+	(if_then_else (ltu (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "* return cmp_jmp(\"u\", 6, operands[0]); ")
+
+(define_insn "bge"
+  [(set (pc)
+	(if_then_else (ge (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "* return cmp_jmp(\"\", 4, operands[0]); ")
+
+(define_insn "bgeu"
+  [(set (pc)
+	(if_then_else (geu (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "* return cmp_jmp(\"u\", 4, operands[0]); ")
+
+(define_insn "ble"
+  [(set (pc)
+	(if_then_else (le (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "* return cmp_jmp(\"\", 10, operands[0]); ")
+
+(define_insn "bleu"
+  [(set (pc)
+	(if_then_else (leu (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "* return cmp_jmp(\"u\", 10, operands[0]); ")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (eq (cc0)
+			  (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "* return cmp_jmp(\"\", 8, operands[0]); ")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (ne (cc0)
+			  (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "* return cmp_jmp(\"\", 2, operands[0]); ")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (gt (cc0)
+			  (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "* return cmp_jmp(\"\", 10, operands[0]); ")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (gtu (cc0)
+			  (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "* return cmp_jmp(\"u\", 10, operands[0]); ")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (lt (cc0)
+			  (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "* return cmp_jmp(\"\", 4, operands[0]); ")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (ltu (cc0)
+			  (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "* return cmp_jmp(\"u\", 4, operands[0]); ")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (ge (cc0)
+			  (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "* return cmp_jmp(\"\", 6, operands[0]); ")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (geu (cc0)
+			  (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "* return cmp_jmp(\"u\", 6, operands[0]); ")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (le (cc0)
+			  (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "* return cmp_jmp(\"\", 0, operands[0]); ")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (leu (cc0)
+			  (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "* return cmp_jmp(\"u\", 0, operands[0]); ")
+
+;; Note that operand 1 is total size of args, in bytes,
+;; and what the call insn wants is the number of words.
+(define_insn "call"
+  [(call (match_operand:QI 0 "general_operand" "m")
+	 (match_operand:QI 1 "general_operand" "g"))]
+  ""
+  "*
+  if (GET_CODE (operands[0]) == MEM && GET_CODE (XEXP (operands[0], 0)) == REG)
+    if (REGNO (XEXP (operands[0], 0)) != 0)
+      return \"add.64\\t.sp,=-4\;ld.64\\t.r0,=.+11\;st.32\\t.r0,[.sp]\;br.reg\\t%r0\;add.64\\t.sp,=4\;add.64\\t.sp,%1\";
+    else
+      return \"add.64\\t.sp,=-4\;ld.64\\t.r1,=.+11\;st.32\\t.r1,[.sp]\;br.reg\\t%r0\;add.64\\t.sp,=4\;add.64\\t.sp,%1\";
+  else
+    return \"add.64\\t.sp,=-4\;call\\t%0\;add.64\\t.sp,=4\;add.64\\t.sp,%1\";
+  ")
+
+(define_insn "call_value"
+  [(set (match_operand 0 "" "g")
+	(call (match_operand:QI 1 "general_operand" "m")
+	      (match_operand:QI 2 "general_operand" "g")))]
+  ""
+  "*
+  if (GET_CODE (operands[1]) == MEM && GET_CODE (XEXP (operands[1], 0)) == REG)
+    if (REGNO (XEXP (operands[1], 0)) != 0)
+      return \"add.64\\t.sp,=-4\;ld.64\\t.r0,=.+11\;st.32\\t.r0,[.sp]\;br.reg\\t%r1\;add.64\\t.sp,=4\;add.64\\t.sp,%2\";
+    else
+      return \"add.64\\t.sp,=-4\;ld.64\\t.r1,=.+11\;st.32\\t.r1,[.sp]\;br.reg\\t%r1\;add.64\\t.sp,=4\;add.64\\t.sp,%2\";
+  else
+    return \"add.64\\t.sp,=-4\;call\\t%1\;add.64\\t.sp,=4\;add.64\\t.sp,%2\";
+  ")
+
+(define_insn "tablejump"
+  [(set (pc) (match_operand:SI 0 "register_operand" "r"))
+   (use (label_ref (match_operand 1 "" "")))]
+  ""
+  "br.reg\\t%0")
+
+(define_insn "nop"
+  [(const_int 0)]
+  ""
+  "nop")
+
+
+
+;;- Local variables:
+;;- mode:emacs-lisp
+;;- comment-start: "!;;- "
+;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
+;;- eval: (modify-syntax-entry ?[ "(]")
+;;- eval: (modify-syntax-entry ?] ")[")
+;;- eval: (modify-syntax-entry ?{ "(}")
+;;- eval: (modify-syntax-entry ?} "){")
+;;- End:
diff --git a/gcc/config/elxsi/x-elxsi b/gcc/config/elxsi/x-elxsi
new file mode 100644
index 00000000000..30a458d87b4
--- /dev/null
+++ b/gcc/config/elxsi/x-elxsi
@@ -0,0 +1,9 @@
+# Our make needs a little help...
+MAKE=make
+
+# We don't support -g yet, so don't try and use it.
+CFLAGS =
+LIBGCC2_CFLAGS = -O2 $(GCC_CFLAGS)
+
+# Hide xmalloc so that it does not conflict with the one in libc.a, Ick!
+X_CFLAGS = -Dxmalloc=my_xmalloc
diff --git a/gcc/config/elxsi/xm-elxsi.h b/gcc/config/elxsi/xm-elxsi.h
new file mode 100644
index 00000000000..86bfca11ebb
--- /dev/null
+++ b/gcc/config/elxsi/xm-elxsi.h
@@ -0,0 +1,42 @@
+/* Configuration for GNU C-compiler for Elxsi.
+   Copyright (C) 1987 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 1, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+/* #defines that need visibility everywhere.  */
+#define FALSE 0
+#define TRUE 1
+
+/* target machine dependencies.
+   tm.h is a symbolic link to the actual target specific file.   */
+#include "tm.h"
+
+/* This describes the machine the compiler is hosted on.  */
+#define HOST_BITS_PER_CHAR 8
+#define HOST_BITS_PER_SHORT 16
+#define HOST_BITS_PER_INT 32
+#define HOST_BITS_PER_LONG 32
+
+/* Arguments to use with `exit'.  */
+#define SUCCESS_EXIT_CODE 0
+#define FATAL_EXIT_CODE 33
+
+/* If compiled with GNU C, use the built-in alloca */
+#ifdef __GNUC__
+#define alloca __builtin_alloca
+#endif
+