2008-04-05 Basile Starynkevitch <basile@starynkevitch.net>

	MELT branch merged with trunk r133930



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/melt-branch@133932 138bc75d-0d04-0410-961f-82ee72b054a4

5 files changed, 21 insertions, 9 deletions

diff --git a/gcc/config/ia64/constraints.md b/gcc/config/ia64/constraints.md
index 0e6c232e358..0c24536c9aa 100644
--- a/gcc/config/ia64/constraints.md
+++ b/gcc/config/ia64/constraints.md
@@ -52,6 +52,12 @@
   (and (match_code "const_int")
        (match_test "(unsigned HOST_WIDE_INT)ival + 0x200000 < 0x400000")))
 
+(define_constraint "j"
+  "(2**32-2**13)..(2**32-1) for addp4 instructions"
+  (and (match_code "const_int")
+       (match_test "(unsigned HOST_WIDE_INT)ival >= 0xffffe000
+		    && (unsigned HOST_WIDE_INT)ival <= 0xffffffff")))
+
 (define_constraint "K"
   "8 bit signed immediate for logical instructions"
   (and (match_code "const_int")
diff --git a/gcc/config/ia64/div.md b/gcc/config/ia64/div.md
index a6547a680ff..45e745963c2 100644
--- a/gcc/config/ia64/div.md
+++ b/gcc/config/ia64/div.md
@@ -199,8 +199,9 @@
 
 (define_insn "recip_approx_rf"
   [(set (match_operand:RF 0 "fr_register_operand" "=f")
-        (div:RF (match_operand:RF 1 "fr_register_operand" "f")
-                (match_operand:RF 2 "fr_register_operand" "f")))
+        (unspec:RF [(match_operand:RF 1 "fr_register_operand" "f")
+		    (match_operand:RF 2 "fr_register_operand" "f")]
+		   UNSPEC_FR_RECIP_APPROX_RES))
    (set (match_operand:BI 3 "register_operand" "=c")
         (unspec:BI [(match_dup 1) (match_dup 2)] UNSPEC_FR_RECIP_APPROX))
    (use (match_operand:SI 4 "const_int_operand" ""))]
diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c
index f2d00cf3cc8..ceda8833db3 100644
--- a/gcc/config/ia64/ia64.c
+++ b/gcc/config/ia64/ia64.c
@@ -5898,6 +5898,7 @@ rtx_needs_barrier (rtx x, struct reg_flags flags, int pred)
 	case UNSPEC_FR_RECIP_APPROX:
 	case UNSPEC_SHRP:
 	case UNSPEC_COPYSIGN:
+	case UNSPEC_FR_RECIP_APPROX_RES:
 	  need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
 	  need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
 	  break;
@@ -9693,6 +9694,7 @@ ia64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
   final_start_function (insn, file, 1);
   final (insn, file, 1);
   final_end_function ();
+  free_after_compilation (cfun);
 
   reload_completed = 0;
   epilogue_completed = 0;
diff --git a/gcc/config/ia64/ia64.h b/gcc/config/ia64/ia64.h
index 5f0c28ce706..618ba24814b 100644
--- a/gcc/config/ia64/ia64.h
+++ b/gcc/config/ia64/ia64.h
@@ -982,7 +982,7 @@ enum reg_class
 #define INIT_EXPANDERS					\
   do {							\
     ia64_init_expanders ();                             \
-    if (cfun && cfun->emit->regno_pointer_align)	\
+    if (rtl.emit.regno_pointer_align)	\
       REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = 64;	\
   } while (0)
 
diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md
index 52f26aa84ab..068e607c1e9 100644
--- a/gcc/config/ia64/ia64.md
+++ b/gcc/config/ia64/ia64.md
@@ -86,6 +86,7 @@
    (UNSPEC_LDCCLR               43)
    (UNSPEC_CHKACLR              45)
    (UNSPEC_CHKS                 47)	
+   (UNSPEC_FR_RECIP_APPROX_RES  48)
   ])
 
 (define_constants
@@ -322,12 +323,13 @@
 })
 
 (define_insn "*movsi_internal"
-  [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f, r,*d")
-	(match_operand:SI 1 "move_operand"        "rO,J,i,m,rO,*f,rO,*f,*d,rK"))]
+  [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r,r, m, r,*f,*f, r,*d")
+	(match_operand:SI 1 "move_operand"        "rO,J,j,i,m,rO,*f,rO,*f,*d,rK"))]
   "ia64_move_ok (operands[0], operands[1])"
   "@
   mov %0 = %r1
   addl %0 = %1, r0
+  addp4 %0 = %1 - 0x100000000, r0
   movl %0 = %1
   ld4%O1 %0 = %1%P1
   st4%Q0 %0 = %r1%P0
@@ -337,7 +339,7 @@
   mov %0 = %1
   mov %0 = %r1"
   ;; frar_m, toar_m ??? why not frar_i and toar_i
-  [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")])
+  [(set_attr "itanium_class" "ialu,ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")])
 
 (define_expand "movdi"
   [(set (match_operand:DI 0 "general_operand" "")
@@ -352,14 +354,15 @@
 
 (define_insn "*movdi_internal"
   [(set (match_operand:DI 0 "destination_operand"
-		    "=r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c")
+		    "=r,r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c")
 	(match_operand:DI 1 "move_operand"
-		    "rO,JT,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))]
+		    "rO,JT,j,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))]
   "ia64_move_ok (operands[0], operands[1])"
 {
   static const char * const alt[] = {
     "%,mov %0 = %r1",
     "%,addl %0 = %1, r0",
+    "%,addp4 %0 = %1 - 0x100000000, r0",
     "%,movl %0 = %1",
     "%,ld8%O1 %0 = %1%P1",
     "%,st8%Q0 %0 = %r1%P0",
@@ -383,7 +386,7 @@
 
   return alt[which_alternative];
 }
-  [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")])
+  [(set_attr "itanium_class" "ialu,ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")])
 
 (define_mode_iterator MODE [BI QI HI SI DI SF DF XF TI])
 (define_mode_iterator MODE_FOR_EXTEND [QI HI SI])