2007-06-19 Rask Ingemann Lambertsen <rask@sygehus.dk>

	PR target/32335
	* config/m32c/m32c.c: Include dataflow header file.
	(m32c_emit_prologue): Adjust for prologue insn change.
	* config/m32c/prologue.md (prologue_enter_16): Only modify SP_REGNO
	once inside a PARALLEL. Assume frame size passed in operand 0
	includes space to save the fb register.
	(prologue_enter_24): Likewise.
	(epilogue_exitd): Only modify SP_REGNO once inside a PARALLEL.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@125853 138bc75d-0d04-0410-961f-82ee72b054a4

2 files changed, 21 insertions, 12 deletions

diff --git a/gcc/config/m32c/m32c.c b/gcc/config/m32c/m32c.c
index f48b252926e..097c3a3a83d 100644
--- a/gcc/config/m32c/m32c.c
+++ b/gcc/config/m32c/m32c.c
@@ -49,6 +49,7 @@
 #include "tm_p.h"
 #include "langhooks.h"
 #include "tree-gimple.h"
+#include "df.h"
 
 /* Prototypes */
 
@@ -3977,8 +3978,8 @@ m32c_emit_prologue (void)
   if (cfun->machine->use_rts == 0)
     F (emit_insn (m32c_all_frame_related
 		  (TARGET_A16
-		   ? gen_prologue_enter_16 (GEN_INT (frame_size))
-		   : gen_prologue_enter_24 (GEN_INT (frame_size)))));
+		   ? gen_prologue_enter_16 (GEN_INT (frame_size + 2))
+		   : gen_prologue_enter_24 (GEN_INT (frame_size + 4)))));
 
   if (extra_frame_size)
     {
diff --git a/gcc/config/m32c/prologue.md b/gcc/config/m32c/prologue.md
index 98c40acc3ca..81d35a1c965 100644
--- a/gcc/config/m32c/prologue.md
+++ b/gcc/config/m32c/prologue.md
@@ -1,5 +1,5 @@
 ;; Machine Descriptions for R8C/M16C/M32C
-;; Copyright (C) 2005
+;; Copyright (C) 2005, 2007
 ;; Free Software Foundation, Inc.
 ;; Contributed by Red Hat.
 ;;
@@ -33,7 +33,7 @@
 
 ; We assume dwarf2out will process each set in sequence.
 (define_insn "prologue_enter_16"
-  [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNO)))
+  [(set (mem:HI (plus:HI (reg:HI SP_REGNO) (const_int -2)))
 	(reg:HI FB_REGNO))
    (set (reg:HI FB_REGNO)
 	(reg:HI SP_REGNO))
@@ -42,12 +42,17 @@
 	           (match_operand 0 "const_int_operand" "i")))
    ]
   "TARGET_A16"
-  "enter\t%0"
+  {
+    /* This is due to binutils bug gas/4659.  */
+    if (INTVAL (operands[0]) == 2)
+      return "enter\t#0";
+    return "enter\t%0-2";
+  }
   [(set_attr "flags" "x")]
   )
 
 (define_insn "prologue_enter_24"
-  [(set (mem:SI (pre_dec:PSI (reg:PSI SP_REGNO)))
+  [(set (mem:SI (plus:PSI (reg:PSI SP_REGNO) (const_int -4)))
 	(reg:SI FB_REGNO))
    (set (reg:PSI FB_REGNO)
 	(reg:PSI SP_REGNO))
@@ -56,7 +61,12 @@
 	           (match_operand 0 "const_int_operand" "i")))
    ]
   "TARGET_A24"
-  "enter\t%0"
+  {
+    /* This is due to binutils bug gas/4659.  */
+    if (INTVAL (operands[0]) == 4)
+      return "enter\t#0";
+    return "enter\t%0-4";
+  }
   [(set_attr "flags" "x")]
   )
 
@@ -94,12 +104,10 @@
 
 (define_insn "epilogue_exitd"
   [(set (reg:PSI SP_REGNO)
-	(reg:PSI FB_REGNO))
-   (set (reg:PSI FB_REGNO)
-	(mem:PSI (reg:PSI SP_REGNO)))
-   (set (reg:PSI SP_REGNO)
-	(plus:PSI (reg:PSI SP_REGNO)
+	(plus:PSI (reg:PSI FB_REGNO)
 	      (match_operand 0 "const_int_operand" "i")))
+   (set (reg:PSI FB_REGNO)
+	(mem:PSI (reg:PSI FB_REGNO)))
    (return)
    ]
   ""