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| author | wilson <wilson@138bc75d-0d04-0410-961f-82ee72b054a4> | 2005-08-17 21:43:49 +0000 |
|---|---|---|
| committer | wilson <wilson@138bc75d-0d04-0410-961f-82ee72b054a4> | 2005-08-17 21:43:49 +0000 |
| commit | 2f0df5e3126baf3597dfa6d4ebd11b1274c8718b (patch) | |
| tree | c8d27614713d44d1a41d9835b3c2b26a8cce3b7d /gcc/config/mcore/mcore.h | |
| parent | 7dd5e78f772f55f8eca4d242fa8cabce1eaeff50 (diff) | |
| download | gcc-2f0df5e3126baf3597dfa6d4ebd11b1274c8718b.tar.gz | |
Fix misoptimization of mask and shift.
PR target/21684
* config/mcore/mcore.h (SHIFT_COUNT_TRUNCATED): Define to 0.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@103228 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/mcore/mcore.h')
| -rw-r--r-- | gcc/config/mcore/mcore.h | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/gcc/config/mcore/mcore.h b/gcc/config/mcore/mcore.h index f0afa88191b..d9960dc0edb 100644 --- a/gcc/config/mcore/mcore.h +++ b/gcc/config/mcore/mcore.h @@ -820,12 +820,10 @@ extern const enum reg_class reg_class_from_letter[]; /* Nonzero if access to memory by bytes is slow and undesirable. */ #define SLOW_BYTE_ACCESS TARGET_SLOW_BYTES -/* Immediate shift counts are truncated by the output routines (or was it - the assembler?). Shift counts in a register are truncated by ARM. Note - that the native compiler puts too large (> 32) immediate shift counts - into a register and shifts by the register, letting the ARM decide what - to do instead of doing that itself. */ -#define SHIFT_COUNT_TRUNCATED 1 +/* Shift counts are truncated to 6-bits (0 to 63) instead of the expected + 5-bits, so we can not define SHIFT_COUNT_TRUNCATED to true for this + target. */ +#define SHIFT_COUNT_TRUNCATED 0 /* All integers have the same format so truncation is easy. */ #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1 |