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authorMingjie Xing <mingjie.xing@gmail.com>2010-09-08 00:55:04 +0000
committerMingjie Xing <xmj@gcc.gnu.org>2010-09-08 00:55:04 +0000
commit59bdeecb0b6f482ca57b90faec9872f92a4d9a7d (patch)
tree7ccc05461320fcb7adf4b6756d6759a8d83c9d05 /gcc/config/mips/loongson.md
parent82acc0474e7c5374173ceba9edc4ce99f117a3b7 (diff)
downloadgcc-59bdeecb0b6f482ca57b90faec9872f92a4d9a7d.tar.gz
Rename loongson vector shift insns
From-SVN: r163986
Diffstat (limited to 'gcc/config/mips/loongson.md')
-rw-r--r--gcc/config/mips/loongson.md6
1 files changed, 3 insertions, 3 deletions
diff --git a/gcc/config/mips/loongson.md b/gcc/config/mips/loongson.md
index 11b197b3780..4f95c285ce5 100644
--- a/gcc/config/mips/loongson.md
+++ b/gcc/config/mips/loongson.md
@@ -411,7 +411,7 @@
[(set_attr "type" "fmul")])
;; Shift left logical.
-(define_insn "loongson_psll<V_suffix>"
+(define_insn "ashl<mode>3"
[(set (match_operand:VWH 0 "register_operand" "=f")
(ashift:VWH (match_operand:VWH 1 "register_operand" "f")
(match_operand:SI 2 "register_operand" "f")))]
@@ -420,7 +420,7 @@
[(set_attr "type" "fmul")])
;; Shift right arithmetic.
-(define_insn "loongson_psra<V_suffix>"
+(define_insn "ashr<mode>3"
[(set (match_operand:VWH 0 "register_operand" "=f")
(ashiftrt:VWH (match_operand:VWH 1 "register_operand" "f")
(match_operand:SI 2 "register_operand" "f")))]
@@ -429,7 +429,7 @@
[(set_attr "type" "fdiv")])
;; Shift right logical.
-(define_insn "loongson_psrl<V_suffix>"
+(define_insn "lshr<mode>3"
[(set (match_operand:VWH 0 "register_operand" "=f")
(lshiftrt:VWH (match_operand:VWH 1 "register_operand" "f")
(match_operand:SI 2 "register_operand" "f")))]