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| author | bstarynk <bstarynk@138bc75d-0d04-0410-961f-82ee72b054a4> | 2010-11-05 22:25:29 +0000 |
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| committer | bstarynk <bstarynk@138bc75d-0d04-0410-961f-82ee72b054a4> | 2010-11-05 22:25:29 +0000 |
| commit | 7deddfded2d013c07a639873a4c90bfed40fd03e (patch) | |
| tree | 3df2a52207fec5bec55c28303aa57a8bd9b4e620 /gcc/config/mips/mips-dspr2.md | |
| parent | c79b54af83c8031caac515081fb7c56a127b90e3 (diff) | |
| download | gcc-7deddfded2d013c07a639873a4c90bfed40fd03e.tar.gz | |
2010-11-05 Basile Starynkevitch <basile@starynkevitch.net>
MELT branch merged with trunk rev 166377
2010-11-05 Basile Starynkevitch <basile@starynkevitch.net>
MELT branch merged with trunk rev 166377
* gcc/Makefile.in (MELT_RAW_CFLAGS): removed LIBELFINC
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/melt-branch@166380 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/mips/mips-dspr2.md')
| -rw-r--r-- | gcc/config/mips/mips-dspr2.md | 36 |
1 files changed, 0 insertions, 36 deletions
diff --git a/gcc/config/mips/mips-dspr2.md b/gcc/config/mips/mips-dspr2.md index 9c3cbd58435..3a5c7d2ce34 100644 --- a/gcc/config/mips/mips-dspr2.md +++ b/gcc/config/mips/mips-dspr2.md @@ -224,22 +224,6 @@ [(set_attr "type" "imadd") (set_attr "mode" "SI")]) -(define_expand "mips_madd<u>" - [(set (match_operand:DI 0 "register_operand") - (plus:DI - (mult:DI (any_extend:DI (match_operand:SI 2 "register_operand")) - (any_extend:DI (match_operand:SI 3 "register_operand"))) - (match_operand:DI 1 "register_operand")))] - "ISA_HAS_DSPR2 && !TARGET_64BIT") - -(define_expand "mips_msub<u>" - [(set (match_operand:DI 0 "register_operand") - (minus:DI - (match_operand:DI 1 "register_operand") - (mult:DI (any_extend:DI (match_operand:SI 2 "register_operand")) - (any_extend:DI (match_operand:SI 3 "register_operand")))))] - "ISA_HAS_DSPR2 && !TARGET_64BIT") - (define_insn "mulv2hi3" [(parallel [(set (match_operand:V2HI 0 "register_operand" "=d") @@ -320,26 +304,6 @@ [(set_attr "type" "imadd") (set_attr "mode" "SI")]) -(define_insn "mips_mult" - [(set (match_operand:DI 0 "register_operand" "=a") - (mult:DI - (sign_extend:DI (match_operand:SI 1 "register_operand" "d")) - (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))] - "ISA_HAS_DSPR2 && !TARGET_64BIT" - "mult\t%q0,%1,%2" - [(set_attr "type" "imul") - (set_attr "mode" "SI")]) - -(define_insn "mips_multu" - [(set (match_operand:DI 0 "register_operand" "=a") - (mult:DI - (zero_extend:DI (match_operand:SI 1 "register_operand" "d")) - (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))] - "ISA_HAS_DSPR2 && !TARGET_64BIT" - "multu\t%q0,%1,%2" - [(set_attr "type" "imul") - (set_attr "mode" "SI")]) - (define_insn "mips_precr_qb_ph" [(set (match_operand:V4QI 0 "register_operand" "=d") (unspec:V4QI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG") |