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authorrsandifo <rsandifo@138bc75d-0d04-0410-961f-82ee72b054a4>2007-04-24 05:51:57 +0000
committerrsandifo <rsandifo@138bc75d-0d04-0410-961f-82ee72b054a4>2007-04-24 05:51:57 +0000
commit7e564f7304a4050ea56fed5b6d3158e48b6d0389 (patch)
tree414ebf4e011654eddd3531c3e652690d778992c9 /gcc/config/mips/mips-dspr2.md
parent32201e9aeb52a4eef9ba61c156399f0090a98023 (diff)
downloadgcc-7e564f7304a4050ea56fed5b6d3158e48b6d0389.tar.gz
gcc/
2007-xx-xx Chao-ying Fu <fu@mips.com> Richard Sandiford <richard@nildram.co.uk> * doc/md.texi (madd@var{m}@var{n}4, umadd@var{m}@var{n}4): Document. * optabs.h (OTI_smadd_widen, OTI_umadd_widen): New optab_indexes. (smadd_widen_optab, umadd_widen_optab): Define. * optabs.c (init_optabs): Initialize smadd_widen_optab and umadd_widen_optab. * genopinit.c (optabs): Fill in smadd_widen_optab and umadd_widen_optab. * expr.c (expand_expr_real_1): Try to use smadd_widen_optab and umadd_widen_optab to implement multiply-add sequences. * config/mips/mips.md (*<su>mul_acc_di): Rename to... (<u>maddsidi4): ...this. Extend condition to include GENERATE_MADD_MSUB and TARGET_DSPR2. Change the constraint of operand 0 to "ka" and use the three-operand form of madd<u> for TARGET_DSPR2. * config/mips/mips-dspr2.md (mips_madd, mips_maddu): Convert to define_expands. * config/mips/constraints.md (ka): New register constraint. gcc/testsuite/ 2007-xx-xx Richard Sandiford <richard@nildram.co.uk> * gcc.target/mips/madd-1.c, gcc.target/mips/madd-2.c, * gcc.target/mips/madd-3.c, gcc.target/mips/madd-4.c, * gcc.target/mips/maddu-1.c, gcc.target/mips/maddu-2.c, * gcc.target/mips/maddu-3.c, gcc.target/mips/maddu-4.c: New tests. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@124095 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/mips/mips-dspr2.md')
-rw-r--r--gcc/config/mips/mips-dspr2.md31
1 files changed, 6 insertions, 25 deletions
diff --git a/gcc/config/mips/mips-dspr2.md b/gcc/config/mips/mips-dspr2.md
index 948c693c7d8..dd0aab553a1 100644
--- a/gcc/config/mips/mips-dspr2.md
+++ b/gcc/config/mips/mips-dspr2.md
@@ -154,31 +154,13 @@
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
-(define_insn "mips_madd"
- [(set (match_operand:DI 0 "register_operand" "=a")
+(define_expand "mips_madd<u>"
+ [(set (match_operand:DI 0 "register_operand")
(plus:DI
- (mult:DI (sign_extend:DI
- (match_operand:SI 2 "register_operand" "d"))
- (sign_extend:DI
- (match_operand:SI 3 "register_operand" "d")))
- (match_operand:DI 1 "register_operand" "0")))]
- "TARGET_DSPR2 && !TARGET_64BIT"
- "madd\t%q0,%2,%3"
- [(set_attr "type" "imadd")
- (set_attr "mode" "SI")])
-
-(define_insn "mips_maddu"
- [(set (match_operand:DI 0 "register_operand" "=a")
- (plus:DI
- (mult:DI (zero_extend:DI
- (match_operand:SI 2 "register_operand" "d"))
- (zero_extend:DI
- (match_operand:SI 3 "register_operand" "d")))
- (match_operand:DI 1 "register_operand" "0")))]
- "TARGET_DSPR2 && !TARGET_64BIT"
- "maddu\t%q0,%2,%3"
- [(set_attr "type" "imadd")
- (set_attr "mode" "SI")])
+ (mult:DI (any_extend:DI (match_operand:SI 2 "register_operand"))
+ (any_extend:DI (match_operand:SI 3 "register_operand")))
+ (match_operand:DI 1 "register_operand")))]
+ "TARGET_DSPR2 && !TARGET_64BIT")
(define_insn "mips_msub"
[(set (match_operand:DI 0 "register_operand" "=a")
@@ -623,4 +605,3 @@
"dpsqx_sa.w.ph\t%q0,%z2,%z3"
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
-