RISC-V: Support RVV VREINTERPRET from v{u}int*_t to vbool1_t

This patch support the RVV VREINTERPRET from the int to the vbool1_t.  Aka:

vbool1_t __riscv_vreinterpret_xx_xx(v{u}int[8|16|32|64]_t);

These APIs help the users to convert vector LMUL=1 integer to vbool1_t.
According to the RVV intrinsic SPEC as below, the reinterpret intrinsics
only change the types of the underlying contents.

https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#reinterpret-vbool-o-vintm1

For example, given below code.
vbool1_t test_vreinterpret_v_i8m1_b1(vint8m1_t src) {
  return __riscv_vreinterpret_v_i8m1_b1(src);
}

It will generate the assembly code similar as below:
vsetvli a5,zero,e8,m8,ta,ma
vlm.v   v1,0(a1)
vsm.v   v1,0(a0)
ret

The rest intrinsic bool size APIs will be prepared in other PATCH.

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/ChangeLog:

	* config/riscv/genrvv-type-indexer.cc (BOOL_SIZE_LIST): New
	macro.
	(main): Add bool1 to the type indexer.
	* config/riscv/riscv-vector-builtins-functions.def
	(vreinterpret): Register vbool1 interpret function.
	* config/riscv/riscv-vector-builtins-types.def
	(DEF_RVV_BOOL1_INTERPRET_OPS): New macro.
	(vint8m1_t): Add the type to bool1_interpret_ops.
	(vint16m1_t): Ditto.
	(vint32m1_t): Ditto.
	(vint64m1_t): Ditto.
	(vuint8m1_t): Ditto.
	(vuint16m1_t): Ditto.
	(vuint32m1_t): Ditto.
	(vuint64m1_t): Ditto.
	* config/riscv/riscv-vector-builtins.cc
	(DEF_RVV_BOOL1_INTERPRET_OPS): New macro.
	(required_extensions_p): Add bool1 interpret case.
	* config/riscv/riscv-vector-builtins.def
	(bool1_interpret): Add bool1 interpret to base type.
	* config/riscv/vector.md (@vreinterpret<mode>): Add new expand
	with VB dest for vreinterpret.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c: New test.

1 files changed, 1 insertions, 0 deletions

diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 7200036d853..72032c6a52c 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -508,6 +508,7 @@ DEF_RVV_FUNCTION (vreinterpret, misc, none_preds, iu_v_eew8_interpret_ops)
 DEF_RVV_FUNCTION (vreinterpret, misc, none_preds, iu_v_eew16_interpret_ops)
 DEF_RVV_FUNCTION (vreinterpret, misc, none_preds, iu_v_eew32_interpret_ops)
 DEF_RVV_FUNCTION (vreinterpret, misc, none_preds, iu_v_eew64_interpret_ops)
+DEF_RVV_FUNCTION (vreinterpret, misc, none_preds, iu_v_bool1_interpret_ops)
 DEF_RVV_FUNCTION (vlmul_ext, misc, none_preds, all_v_vlmul_ext_x2_ops)
 DEF_RVV_FUNCTION (vlmul_ext, misc, none_preds, all_v_vlmul_ext_x4_ops)
 DEF_RVV_FUNCTION (vlmul_ext, misc, none_preds, all_v_vlmul_ext_x8_ops)