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authorbstarynk <bstarynk@138bc75d-0d04-0410-961f-82ee72b054a4>2008-10-15 18:36:10 +0000
committerbstarynk <bstarynk@138bc75d-0d04-0410-961f-82ee72b054a4>2008-10-15 18:36:10 +0000
commitbcdb555cd759a0a9670f385e1dcefeca4f1a1812 (patch)
treee89d039fcda847debfabc35e4a6e1f2cb81b9732 /gcc/config/rs6000/predicates.md
parent23720eba56f66cf1a62af6a9b49dded63ff9e49d (diff)
downloadgcc-bcdb555cd759a0a9670f385e1dcefeca4f1a1812.tar.gz
2008-10-15 Basile Starynkevitch <basile@starynkevitch.net>
MELT branch merged with trunk r141146 git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/melt-branch@141150 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/rs6000/predicates.md')
-rw-r--r--gcc/config/rs6000/predicates.md8
1 files changed, 8 insertions, 0 deletions
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 90ab0810fc1..a04a7d8cdbd 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -104,6 +104,14 @@
|| REGNO (op) > LAST_VIRTUAL_REGISTER
|| CR_REGNO_NOT_CR0_P (REGNO (op))")))
+;; Return 1 if op is a register that is a condition register field and if generating microcode, not cr0.
+(define_predicate "cc_reg_not_micro_cr0_operand"
+ (and (match_operand 0 "register_operand")
+ (match_test "GET_CODE (op) != REG
+ || REGNO (op) > LAST_VIRTUAL_REGISTER
+ || (rs6000_gen_cell_microcode && CR_REGNO_NOT_CR0_P (REGNO (op)))
+ || (!rs6000_gen_cell_microcode && CR_REGNO_P (REGNO (op)))")))
+
;; Return 1 if op is a constant integer valid for D field
;; or non-special register register.
(define_predicate "reg_or_short_operand"