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authorjsm28 <jsm28@138bc75d-0d04-0410-961f-82ee72b054a4>2006-11-22 16:41:29 +0000
committerjsm28 <jsm28@138bc75d-0d04-0410-961f-82ee72b054a4>2006-11-22 16:41:29 +0000
commitfdf1c510def4296bef86b7a4f95e96f4f78f5746 (patch)
tree91ff68afec415ea5b2e524162f6383539ae2a334 /gcc/config/rs6000/predicates.md
parentb50e8f459a18daa7de22703d0fad66573ad76f5b (diff)
downloadgcc-fdf1c510def4296bef86b7a4f95e96f4f78f5746.tar.gz
* config/rs6000/spe.md (SPE64): New mode macro.
(mov_sidf_e500_subreg0): Change to mov_si<mode>_e500_subreg0. Add memory load. (mov_si<mode>_e500_subreg0_2): New. (mov_sidf_e500_subreg4): Change to mov_si<mode>_e500_subreg4. Add memory load. (mov_si<mode>_e500_subreg4_2): New. * config/rs6000/predicates.md (input_operand): Do not allow invalid E500 subregs. (rs6000_nonimmediate_operand): Check for invalid E500 subregs also if TARGET_SPE. * config/rs6000/rs6000.c (invalid_e500_subreg): Check for subregs involving DFmode if TARGET_E500_DOUBLE. Check for subregs involving vector modes if TARGET_SPE. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@119094 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/rs6000/predicates.md')
-rw-r--r--gcc/config/rs6000/predicates.md8
1 files changed, 7 insertions, 1 deletions
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index f8e00ffecbe..2ff0ba77b85 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -722,6 +722,12 @@
&& easy_vector_constant (op, mode))
return 1;
+ /* Do not allow invalid E500 subregs. */
+ if ((TARGET_E500_DOUBLE || TARGET_SPE)
+ && GET_CODE (op) == SUBREG
+ && invalid_e500_subreg (op, mode))
+ return 0;
+
/* For floating-point or multi-word mode, the only remaining valid type
is a register. */
if (SCALAR_FLOAT_MODE_P (mode)
@@ -756,7 +762,7 @@
(define_predicate "rs6000_nonimmediate_operand"
(match_code "reg,subreg,mem")
{
- if (TARGET_E500_DOUBLE
+ if ((TARGET_E500_DOUBLE || TARGET_SPE)
&& GET_CODE (op) == SUBREG
&& invalid_e500_subreg (op, mode))
return 0;