diff options
| author | Eric Christopher <echristo@gcc.gnu.org> | 2004-08-24 00:30:52 +0000 |
|---|---|---|
| committer | Eric Christopher <echristo@gcc.gnu.org> | 2004-08-24 00:30:52 +0000 |
| commit | f676971a92dcc163394d15c819e904cbed2438d6 (patch) | |
| tree | 7636aad680528291a6fa22918ea3a0c18c83943b /gcc/config/rs6000/rs6000.c | |
| parent | a43b7e0fd7e33918218b26302e1bac209f76cd07 (diff) | |
| download | gcc-f676971a92dcc163394d15c819e904cbed2438d6.tar.gz | |
defaults.h (VECTOR_MODE_SUPPORTED_P): Remove macro.
2004-08-23 Eric Christopher <echristo@redhat.com>
* defaults.h (VECTOR_MODE_SUPPORTED_P): Remove macro.
* system.h (VECTOR_MODE_SUPPORTED_P): Poison.
* target-def.h (TARGET_VECTOR_MODE_SUPPORTED_P): Define.
* target.h: Ditto.
* hooks.h: Include machmode.h.
(hook_bool_mode_false): Declare.
* hooks.c (hook_bool_mode_false): Define.
* expr.c (vector_mode_valid_p): Use targetm.vector_mode_supported_p.
* stor-layout.c (layout_type): Ditto.
* config/alpha/alpha.c (alpha_vector_mode_supported_p): New function.
Define to target macro.
* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): Delete.
* config/arm/arm.c: Ditto. Use.
* config/arm/arm.h: Ditto.
* config/arm/arm-protos.h: Ditto.
* config/i386/i386.c: Ditto.
* config/i386/i386.h: Ditto.
* config/rs6000/rs6000.c: Ditto.
* config/rs6000/rs6000.h: Ditto.
* config/sh/sh.c: Ditto.
* config/sh/sh.h: Ditto.
* config/sh/sh-protos.h: Ditto.
* config/sh/sh.md: Use.
* doc/tm.texi: Move documentation for VECTOR_MODE_SUPPORTED_P
to TARGET_VECTOR_MODE_SUPPORTED_P.
2004-08-23 Eric Christopher <echristo@redhat.com>
* trans-types.c (gfc_type_for_mode): Remove VECTOR_TYPE_SUPPORTED_P
usage. Use build_vector_type_for_mode for vector types.
From-SVN: r86453
Diffstat (limited to 'gcc/config/rs6000/rs6000.c')
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 765 |
1 files changed, 392 insertions, 373 deletions
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 16bf38b1f5e..9da6d2636ae 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation on IBM RS/6000. - Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, + Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) @@ -130,7 +130,7 @@ static GTY(()) bool rs6000_always_hint; /* Schedule instructions for group formation. */ static GTY(()) bool rs6000_sched_groups; -/* Support adjust_priority scheduler hook +/* Support adjust_priority scheduler hook and -mprioritize-restricted-insns= option. */ const char *rs6000_sched_restricted_insns_priority_str; int rs6000_sched_restricted_insns_priority; @@ -709,7 +709,7 @@ static rtx altivec_expand_ld_builtin (tree, rtx, bool *); static rtx altivec_expand_st_builtin (tree, rtx, bool *); static rtx altivec_expand_dst_builtin (tree, rtx, bool *); static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx); -static rtx altivec_expand_predicate_builtin (enum insn_code, +static rtx altivec_expand_predicate_builtin (enum insn_code, const char *, tree, rtx); static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx); static rtx altivec_expand_stv_builtin (enum insn_code, tree); @@ -753,6 +753,7 @@ static tree get_prev_label (tree function_name); static tree rs6000_build_builtin_va_list (void); static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *); static bool rs6000_must_pass_in_stack (enum machine_mode, tree); +static bool rs6000_vector_mode_supported_p (enum machine_mode); static enum machine_mode rs6000_eh_return_filter_mode (void); @@ -896,7 +897,7 @@ static const char alt_reg_names[][8] = #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost #undef TARGET_SCHED_ADJUST_PRIORITY #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority -#undef TARGET_SCHED_IS_COSTLY_DEPENDENCE +#undef TARGET_SCHED_IS_COSTLY_DEPENDENCE #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence #undef TARGET_SCHED_FINISH #define TARGET_SCHED_FINISH rs6000_sched_finish @@ -975,6 +976,9 @@ static const char alt_reg_names[][8] = #undef TARGET_EH_RETURN_FILTER_MODE #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode +#undef TARGET_VECTOR_MODE_SUPPORTED_P +#define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p + struct gcc_target targetm = TARGET_INITIALIZER; @@ -1056,7 +1060,7 @@ rs6000_override_options (const char *default_cpu) /* This table occasionally claims that a processor does not support a particular feature even though it does, but the feature is slower than the alternative. Thus, it shouldn't be relied on as a - complete description of the processor's support. + complete description of the processor's support. Please keep this list in order, and don't forget to update the documentation in invoke.texi when adding a new processor or @@ -1134,7 +1138,7 @@ rs6000_override_options (const char *default_cpu) enum { POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING, - POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT + POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC | MASK_MFCRF) }; @@ -1362,7 +1366,7 @@ rs6000_override_options (const char *default_cpu) = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly); if (rs6000_sched_costly_dep_str) { - if (! strcmp (rs6000_sched_costly_dep_str, "no")) + if (! strcmp (rs6000_sched_costly_dep_str, "no")) rs6000_sched_costly_dep = no_dep_costly; else if (! strcmp (rs6000_sched_costly_dep_str, "all")) rs6000_sched_costly_dep = all_deps_costly; @@ -1370,7 +1374,7 @@ rs6000_override_options (const char *default_cpu) rs6000_sched_costly_dep = true_store_to_load_dep_costly; else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load")) rs6000_sched_costly_dep = store_to_load_dep_costly; - else + else rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str); } @@ -1414,7 +1418,7 @@ rs6000_override_options (const char *default_cpu) /* Allocate an alias set for register saves & restores from stack. */ rs6000_sr_alias_set = new_alias_set (); - if (TARGET_TOC) + if (TARGET_TOC) ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1); /* We can only guarantee the availability of DI pseudo-ops when @@ -1556,7 +1560,7 @@ rs6000_parse_abi_options (void) if (!TARGET_SPE_ABI) error ("not configured for ABI: '%s'", rs6000_abi_string); } - + else if (! strcmp (rs6000_abi_string, "no-spe")) rs6000_spe_abi = 0; else @@ -1681,7 +1685,7 @@ direct_return (void) /* Returns 1 always. */ int -any_operand (rtx op ATTRIBUTE_UNUSED, +any_operand (rtx op ATTRIBUTE_UNUSED, enum machine_mode mode ATTRIBUTE_UNUSED) { return 1; @@ -1690,7 +1694,7 @@ any_operand (rtx op ATTRIBUTE_UNUSED, /* Returns 1 always. */ int -any_parallel_operand (rtx op ATTRIBUTE_UNUSED, +any_parallel_operand (rtx op ATTRIBUTE_UNUSED, enum machine_mode mode ATTRIBUTE_UNUSED) { return 1; @@ -1718,7 +1722,7 @@ count_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) int altivec_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) { - + return (register_operand (op, mode) && (GET_CODE (op) != REG || REGNO (op) > FIRST_PSEUDO_REGISTER @@ -1793,7 +1797,7 @@ gpc_reg_operand (rtx op, enum machine_mode mode) { return (register_operand (op, mode) && (GET_CODE (op) != REG - || (REGNO (op) >= ARG_POINTER_REGNUM + || (REGNO (op) >= ARG_POINTER_REGNUM && !XER_REGNO_P (REGNO (op))) || REGNO (op) < MQ_REGNO)); } @@ -1958,7 +1962,7 @@ reg_or_logical_cint_operand (rtx op, enum machine_mode mode) return CONST_DOUBLE_HIGH (op) == 0; } - else + else return gpc_reg_operand (op, mode); } @@ -2172,27 +2176,27 @@ easy_fp_constant (rtx op, enum machine_mode mode) static int easy_vector_splat_const (int cst, enum machine_mode mode) { - switch (mode) + switch (mode) { case V4SImode: - if (EASY_VECTOR_15 (cst) - || EASY_VECTOR_15_ADD_SELF (cst)) + if (EASY_VECTOR_15 (cst) + || EASY_VECTOR_15_ADD_SELF (cst)) return cst; if ((cst & 0xffff) != ((cst >> 16) & 0xffff)) break; cst = cst >> 16; case V8HImode: - if (EASY_VECTOR_15 (cst) - || EASY_VECTOR_15_ADD_SELF (cst)) + if (EASY_VECTOR_15 (cst) + || EASY_VECTOR_15_ADD_SELF (cst)) return cst; if ((cst & 0xff) != ((cst >> 8) & 0xff)) break; cst = cst >> 8; case V16QImode: - if (EASY_VECTOR_15 (cst) - || EASY_VECTOR_15_ADD_SELF (cst)) + if (EASY_VECTOR_15 (cst) + || EASY_VECTOR_15_ADD_SELF (cst)) return cst; - default: + default: break; } return 0; @@ -2258,14 +2262,14 @@ easy_vector_constant (rtx op, enum machine_mode mode) && cst2 >= -0x7fff && cst2 <= 0x7fff) return 1; - if (TARGET_ALTIVEC + if (TARGET_ALTIVEC && easy_vector_same (op, mode)) { cst = easy_vector_splat_const (cst, mode); - if (EASY_VECTOR_15_ADD_SELF (cst) + if (EASY_VECTOR_15_ADD_SELF (cst) || EASY_VECTOR_15 (cst)) return 1; - } + } return 0; } @@ -2281,14 +2285,14 @@ easy_vector_constant_add_self (rtx op, enum machine_mode mode) { cst = easy_vector_splat_const (INTVAL (CONST_VECTOR_ELT (op, 0)), mode); if (EASY_VECTOR_15_ADD_SELF (cst)) - return 1; + return 1; } return 0; } /* Generate easy_vector_constant out of a easy_vector_constant_add_self. */ -rtx +rtx gen_easy_vector_constant_add_self (rtx op) { int i, units; @@ -2297,7 +2301,7 @@ gen_easy_vector_constant_add_self (rtx op) v = rtvec_alloc (units); for (i = 0; i < units; i++) - RTVEC_ELT (v, i) = + RTVEC_ELT (v, i) = GEN_INT (INTVAL (CONST_VECTOR_ELT (op, i)) >> 1); return gen_rtx_raw_CONST_VECTOR (GET_MODE (op), v); } @@ -2789,7 +2793,7 @@ lwa_operand (rtx op, enum machine_mode mode) if (reload_completed && GET_CODE (inner) == SUBREG) inner = SUBREG_REG (inner); - + return gpc_reg_operand (inner, mode) || (memory_operand (inner, mode) && GET_CODE (XEXP (inner, 0)) != PRE_INC @@ -2831,7 +2835,7 @@ call_operand (rtx op, enum machine_mode mode) this file. */ int -current_file_function_operand (rtx op, +current_file_function_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) { return (GET_CODE (op) == SYMBOL_REF @@ -2919,7 +2923,7 @@ rs6000_special_round_type_align (tree type, int computed, int specified) /* Return 1 for an operand in small memory on V.4/eabi. */ int -small_data_operand (rtx op ATTRIBUTE_UNUSED, +small_data_operand (rtx op ATTRIBUTE_UNUSED, enum machine_mode mode ATTRIBUTE_UNUSED) { #if TARGET_ELF @@ -2993,10 +2997,10 @@ gpr_or_gpr_p (rtx op0, rtx op1) /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */ -static int -constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc) +static int +constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc) { - switch (GET_CODE(op)) + switch (GET_CODE(op)) { case SYMBOL_REF: if (RS6000_SYMBOL_REF_TLS_P (op)) @@ -3238,11 +3242,11 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, return rs6000_legitimize_tls_address (x, model); } - if (GET_CODE (x) == PLUS + if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == REG && GET_CODE (XEXP (x, 1)) == CONST_INT && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000) - { + { HOST_WIDE_INT high_int, low_int; rtx sum; low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000; @@ -3251,7 +3255,7 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, GEN_INT (high_int)), 0); return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int)); } - else if (GET_CODE (x) == PLUS + else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == REG && GET_CODE (XEXP (x, 1)) != CONST_INT && GET_MODE_NUNITS (mode) == 1 @@ -3302,7 +3306,7 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, && TARGET_NO_TOC && ! flag_pic && GET_CODE (x) != CONST_INT - && GET_CODE (x) != CONST_DOUBLE + && GET_CODE (x) != CONST_DOUBLE && CONSTANT_P (x) && GET_MODE_NUNITS (mode) == 1 && (GET_MODE_BITSIZE (mode) <= 32 @@ -3318,17 +3322,17 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, && ! MACHO_DYNAMIC_NO_PIC_P #endif && GET_CODE (x) != CONST_INT - && GET_CODE (x) != CONST_DOUBLE + && GET_CODE (x) != CONST_DOUBLE && CONSTANT_P (x) && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode) - && mode != DImode + && mode != DImode && mode != TImode) { rtx reg = gen_reg_rtx (Pmode); emit_insn (gen_macho_high (reg, x)); return gen_rtx_LO_SUM (Pmode, reg, x); } - else if (TARGET_TOC + else if (TARGET_TOC && constant_pool_expr_p (x) && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode)) { @@ -3382,7 +3386,7 @@ rs6000_got_sym (void) rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL; SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL; - } + } return rs6000_got_symbol; } @@ -3622,10 +3626,10 @@ rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED) The Darwin code is inside #if TARGET_MACHO because only then is machopic_function_base_name() defined. */ rtx -rs6000_legitimize_reload_address (rtx x, enum machine_mode mode, +rs6000_legitimize_reload_address (rtx x, enum machine_mode mode, int opnum, int type, int ind_levels ATTRIBUTE_UNUSED, int *win) { - /* We must recognize output that we have already generated ourselves. */ + /* We must recognize output that we have already generated ourselves. */ if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG @@ -3732,7 +3736,7 @@ rs6000_legitimize_reload_address (rtx x, enum machine_mode mode, } *win = 0; return x; -} +} /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid memory address for an instruction. @@ -3799,7 +3803,7 @@ rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict) ??? Except that due to conceptual problems in offsettable_address_p we can't really report the problems of integral offsets. So leave - this assuming that the adjustable offset must be valid for the + this assuming that the adjustable offset must be valid for the sub-words of a TFmode operand, which is what we had before. */ bool @@ -3933,7 +3937,7 @@ rs6000_conditional_register_usage (void) insns, zero is returned and no insns and emitted. */ rtx -rs6000_emit_set_const (rtx dest, enum machine_mode mode, +rs6000_emit_set_const (rtx dest, enum machine_mode mode, rtx source, int n ATTRIBUTE_UNUSED) { rtx result, insn, set; @@ -4021,7 +4025,7 @@ rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2) ud3 = c2 & 0xffff; ud4 = (c2 & 0xffff0000) >> 16; - if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000)) + if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000)) || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000))) { if (ud1 & 0x8000) @@ -4030,22 +4034,22 @@ rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2) emit_move_insn (dest, GEN_INT (ud1)); } - else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000)) + else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000)) || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000))) { if (ud2 & 0x8000) - emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000) + emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000) - 0x80000000)); else emit_move_insn (dest, GEN_INT (ud2 << 16)); if (ud1 != 0) emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); } - else if ((ud4 == 0xffff && (ud3 & 0x8000)) + else if ((ud4 == 0xffff && (ud3 & 0x8000)) || (ud4 == 0 && ! (ud3 & 0x8000))) { if (ud3 & 0x8000) - emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000) + emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000) - 0x80000000)); else emit_move_insn (dest, GEN_INT (ud3 << 16)); @@ -4056,10 +4060,10 @@ rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2) if (ud1 != 0) emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); } - else + else { if (ud4 & 0x8000) - emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000) + emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000) - 0x80000000)); else emit_move_insn (dest, GEN_INT (ud4 << 16)); @@ -4069,8 +4073,8 @@ rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2) emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32))); if (ud2 != 0) - emit_move_insn (dest, gen_rtx_IOR (DImode, dest, - GEN_INT (ud2 << 16))); + emit_move_insn (dest, gen_rtx_IOR (DImode, dest, + GEN_INT (ud2 << 16))); if (ud1 != 0) emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); } @@ -4106,7 +4110,7 @@ rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode) rtx operands[2]; operands[0] = dest; operands[1] = source; - + /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */ if (GET_CODE (operands[1]) == CONST_DOUBLE && ! FLOAT_MODE_P (mode) @@ -4135,7 +4139,7 @@ rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode) && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32 ? 32 : MEM_ALIGN (operands[0]))) || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32 - ? 32 + ? 32 : MEM_ALIGN (operands[1])))) && ! MEM_VOLATILE_P (operands [0]) && ! MEM_VOLATILE_P (operands [1])) @@ -4176,7 +4180,7 @@ rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode) regnum = REGNO (operands[1]); else regnum = -1; - + /* If operands[1] is a register, on POWER it may have double-precision data in it, so truncate it to single precision. */ @@ -4241,11 +4245,11 @@ rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode) case DFmode: case SFmode: - if (CONSTANT_P (operands[1]) + if (CONSTANT_P (operands[1]) && ! easy_fp_constant (operands[1], mode)) operands[1] = force_const_mem (mode, operands[1]); break; - + case V16QImode: case V8HImode: case V4SFmode: @@ -4258,14 +4262,14 @@ rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode) && !easy_vector_constant (operands[1], mode)) operands[1] = force_const_mem (mode, operands[1]); break; - + case SImode: case DImode: /* Use default pattern for address of ELF small data */ if (TARGET_ELF && mode == Pmode && DEFAULT_ABI == ABI_V4 - && (GET_CODE (operands[1]) == SYMBOL_REF + && (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST) && small_data_operand (operands[1], mode)) { @@ -4413,7 +4417,7 @@ rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode) operands[1] = force_const_mem (mode, operands[1]); - if (TARGET_TOC + if (TARGET_TOC && constant_pool_expr_p (XEXP (operands[1], 0)) && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( get_pool_constant (XEXP (operands[1], 0)), @@ -4510,7 +4514,7 @@ rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED) so we never return a PARALLEL. */ void -init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, +init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, rtx libname ATTRIBUTE_UNUSED, int incoming, int libcall, int n_named_args) { @@ -4555,9 +4559,9 @@ init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, fprintf (stderr, " proto = %d, nargs = %d\n", cum->prototype, cum->nargs_prototype); } - - if (fntype - && !TARGET_ALTIVEC + + if (fntype + && !TARGET_ALTIVEC && TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype)))) { @@ -4637,9 +4641,9 @@ function_arg_padding (enum machine_mode mode, tree type) } /* If defined, a C expression that gives the alignment boundary, in bits, - of an argument with the specified mode and type. If it is not defined, + of an argument with the specified mode and type. If it is not defined, PARM_BOUNDARY is used for all arguments. - + V.4 wants long longs to be double word aligned. */ int @@ -4682,7 +4686,7 @@ rs6000_arg_size (enum machine_mode mode, tree type) itself. */ void -function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, +function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type, int named) { cum->nargs_prototype--; @@ -4700,7 +4704,7 @@ function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, " to enable them."); /* PowerPC64 Linux and AIX allocate GPRs for a vector argument - even if it is going to be passed in a vector register. + even if it is going to be passed in a vector register. Darwin does the same for variable-argument functions. */ if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT) || (cum->stdarg && DEFAULT_ABI != ABI_V4)) @@ -4712,7 +4716,7 @@ function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, if (stack) { int align; - + /* Vector parameters must be 16-byte aligned. This places them at 2 mod 4 in terms of words in 32-bit mode, since the parameter save area starts at offset 24 from the @@ -4725,13 +4729,13 @@ function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, else align = cum->words & 1; cum->words += align + rs6000_arg_size (mode, type); - + if (TARGET_DEBUG_ARG) { - fprintf (stderr, "function_adv: words = %2d, align=%d, ", + fprintf (stderr, "function_adv: words = %2d, align=%d, ", cum->words, align); fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n", - cum->nargs_prototype, cum->prototype, + cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode)); } } @@ -4823,7 +4827,7 @@ function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, /* Determine where to put a SIMD argument on the SPE. */ static rtx -rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, +rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type) { if (cum->stdarg) @@ -4934,7 +4938,7 @@ rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words) itself. */ struct rtx_def * -function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, +function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type, int named) { enum rs6000_abi abi = DEFAULT_ABI; @@ -5162,7 +5166,7 @@ function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, number of registers used by the first element of the PARALLEL. */ int -function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode, +function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type, int named) { int ret = 0; @@ -5222,8 +5226,8 @@ function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode, reference. */ static bool -rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, - enum machine_mode mode ATTRIBUTE_UNUSED, +rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, + enum machine_mode mode ATTRIBUTE_UNUSED, tree type, bool named ATTRIBUTE_UNUSED) { if ((DEFAULT_ABI == ABI_V4 @@ -5257,7 +5261,7 @@ rs6000_move_block_from_reg (int regno, rtx x, int nregs) if (! strict_memory_address_p (reg_mode, XEXP (tem, 0))) tem = NULL_RTX; else - tem = simplify_gen_subreg (reg_mode, x, BLKmode, + tem = simplify_gen_subreg (reg_mode, x, BLKmode, i * GET_MODE_SIZE(reg_mode)); } else @@ -5272,7 +5276,7 @@ rs6000_move_block_from_reg (int regno, rtx x, int nregs) /* Perform any needed actions needed for a function that is receiving a - variable number of arguments. + variable number of arguments. CUM is as above. @@ -5286,7 +5290,7 @@ rs6000_move_block_from_reg (int regno, rtx x, int nregs) stack and set PRETEND_SIZE to the length of the registers pushed. */ static void -setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode, +setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type, int *pretend_size ATTRIBUTE_UNUSED, int no_rtl) { CUMULATIVE_ARGS next_cum; @@ -5327,7 +5331,7 @@ setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode, set_mem_alias_set (mem, set); set_mem_align (mem, BITS_PER_WORD); - rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem, + rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem, GP_ARG_NUM_REG - first_reg_offset); } @@ -5378,9 +5382,9 @@ rs6000_build_builtin_va_list (void) record = (*lang_hooks.types.make_type) (RECORD_TYPE); type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record); - f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"), + f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"), unsigned_char_type_node); - f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"), + f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"), unsigned_char_type_node); /* Give the two bytes of padding a name, so that -Wpadded won't warn on every user file. */ @@ -5673,7 +5677,7 @@ static const struct builtin_description bdesc_3arg[] = { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM }, { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS }, { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS }, - { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP }, + { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP }, { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF }, { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI }, { MASK_ALTIVEC, CODE_FOR_altivec_vperm_8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI }, @@ -6251,7 +6255,7 @@ rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target) } static rtx -altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode, +altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode, tree arglist, rtx target) { rtx pat, scratch; @@ -6353,7 +6357,7 @@ altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target) || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) target = gen_reg_rtx (tmode); - op1 = copy_to_mode_reg (mode1, op1); + op1 = copy_to_mode_reg (mode1, op1); if (op0 == const0_rtx) { @@ -6430,7 +6434,7 @@ altivec_expand_stv_builtin (enum insn_code icode, tree arglist) if (! (*insn_data[icode].operand[1].predicate) (op0, tmode)) op0 = copy_to_mode_reg (tmode, op0); - op2 = copy_to_mode_reg (mode2, op2); + op2 = copy_to_mode_reg (mode2, op2); if (op1 == const0_rtx) { @@ -6563,7 +6567,7 @@ altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp) /* Expand the stvx builtins. */ static rtx -altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, +altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, bool *expandedp) { tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); @@ -6615,7 +6619,7 @@ altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, /* Expand the dst builtins. */ static rtx -altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, +altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, bool *expandedp) { tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); @@ -6725,7 +6729,7 @@ altivec_expand_builtin (tree exp, rtx target, bool *expandedp) || GET_MODE (target) != tmode || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) target = gen_reg_rtx (tmode); - + pat = GEN_FCN (icode) (target); if (! pat) return 0; @@ -6777,7 +6781,7 @@ altivec_expand_builtin (tree exp, rtx target, bool *expandedp) emit_insn (gen_altivec_dss (op0)); return NULL_RTX; - + case ALTIVEC_BUILTIN_COMPILETIME_ERROR: arg0 = TREE_VALUE (arglist); while (TREE_CODE (arg0) == NOP_EXPR || TREE_CODE (arg0) == ADDR_EXPR) @@ -6969,7 +6973,7 @@ spe_expand_builtin (tree exp, rtx target, bool *expandedp) || GET_MODE (target) != tmode || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) target = gen_reg_rtx (tmode); - + pat = GEN_FCN (icode) (target); if (! pat) return 0; @@ -7167,7 +7171,7 @@ spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target) static rtx rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, - enum machine_mode mode ATTRIBUTE_UNUSED, + enum machine_mode mode ATTRIBUTE_UNUSED, int ignore ATTRIBUTE_UNUSED) { tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); @@ -7177,7 +7181,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, size_t i; rtx ret; bool success; - + if (TARGET_ALTIVEC) { ret = altivec_expand_builtin (exp, target, &success); @@ -7324,7 +7328,7 @@ rs6000_init_builtins (void) END is the builtin enum at which to end. */ static void enable_mask_for_builtins (struct builtin_description *desc, int size, - enum rs6000_builtins start, + enum rs6000_builtins start, enum rs6000_builtins end) { int i; @@ -7477,7 +7481,7 @@ spe_init_builtins (void) opaque_V2SI_type_node)); /* Initialize irregular SPE builtins. */ - + def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR); def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR); def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX); @@ -7735,7 +7739,7 @@ altivec_init_builtins (void) default: abort (); } - + def_builtin (dp->mask, dp->name, type, dp->code); } @@ -7765,7 +7769,7 @@ altivec_init_builtins (void) default: abort (); } - + def_builtin (d->mask, d->name, type, d->code); } } @@ -7825,7 +7829,7 @@ rs6000_common_init_builtins (void) tree v2sf_ftype_v2sf = build_function_type_list (opaque_V2SF_type_node, opaque_V2SF_type_node, NULL_TREE); - + tree v2sf_ftype_v2si = build_function_type_list (opaque_V2SF_type_node, opaque_V2SI_type_node, NULL_TREE); @@ -7897,7 +7901,7 @@ rs6000_common_init_builtins (void) = build_function_type_list (V4SF_type_node, V4SF_type_node, V4SF_type_node, V4SF_type_node, NULL_TREE); - tree v4si_ftype_v4si_v4si_v4si + tree v4si_ftype_v4si_v4si_v4si = build_function_type_list (V4SI_type_node, V4SI_type_node, V4SI_type_node, V4SI_type_node, NULL_TREE); @@ -7962,18 +7966,18 @@ rs6000_common_init_builtins (void) d = (struct builtin_description *) bdesc_3arg; for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) { - + enum machine_mode mode0, mode1, mode2, mode3; tree type; if (d->name == 0 || d->icode == CODE_FOR_nothing) continue; - + mode0 = insn_data[d->icode].operand[0].mode; mode1 = insn_data[d->icode].operand[1].mode; mode2 = insn_data[d->icode].operand[2].mode; mode3 = insn_data[d->icode].operand[3].mode; - + /* When all four are of the same mode. */ if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3) { @@ -7987,12 +7991,12 @@ rs6000_common_init_builtins (void) break; case V8HImode: type = v8hi_ftype_v8hi_v8hi_v8hi; - break; + break; case V16QImode: type = v16qi_ftype_v16qi_v16qi_v16qi; - break; + break; default: - abort(); + abort(); } } else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode) @@ -8007,21 +8011,21 @@ rs6000_common_init_builtins (void) break; case V8HImode: type = v8hi_ftype_v8hi_v8hi_v16qi; - break; + break; case V16QImode: type = v16qi_ftype_v16qi_v16qi_v16qi; - break; + break; default: - abort(); + abort(); } } - else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode + else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode && mode3 == V4SImode) type = v4si_ftype_v16qi_v16qi_v4si; - else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode + else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode && mode3 == V4SImode) type = v4si_ftype_v8hi_v8hi_v4si; - else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode + else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode && mode3 == V4SImode) type = v4sf_ftype_v4sf_v4sf_v4si; @@ -8060,7 +8064,7 @@ rs6000_common_init_builtins (void) if (d->name == 0 || d->icode == CODE_FOR_nothing) continue; - + mode0 = insn_data[d->icode].operand[0].mode; mode1 = insn_data[d->icode].operand[1].mode; mode2 = insn_data[d->icode].operand[2].mode; @@ -8129,15 +8133,15 @@ rs6000_common_init_builtins (void) /* vint, vshort, vint. */ else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode) type = v4si_ftype_v8hi_v4si; - + /* vint, vint, 5 bit literal. */ else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode) type = v4si_ftype_v4si_int; - + /* vshort, vshort, 5 bit literal. */ else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode) type = v8hi_ftype_v8hi_int; - + /* vchar, vchar, 5 bit literal. */ else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode) type = v16qi_ftype_v16qi_int; @@ -8145,7 +8149,7 @@ rs6000_common_init_builtins (void) /* vfloat, vint, 5 bit literal. */ else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode) type = v4sf_ftype_v4si_int; - + /* vint, vfloat, 5 bit literal. */ else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode) type = v4si_ftype_v4sf_int; @@ -8196,7 +8200,7 @@ rs6000_common_init_builtins (void) if (d->name == 0 || d->icode == CODE_FOR_nothing) continue; - + mode0 = insn_data[d->icode].operand[0].mode; mode1 = insn_data[d->icode].operand[1].mode; @@ -8326,7 +8330,7 @@ expand_block_clear (rtx operands[]) rtx (*mov) (rtx, rtx); enum machine_mode mode = BLKmode; rtx dest; - + if (bytes >= 8 && TARGET_POWERPC64 /* 64-bit loads and stores require word-aligned displacements. */ @@ -8354,9 +8358,9 @@ expand_block_clear (rtx operands[]) mode = QImode; mov = gen_movqi; } - + dest = adjust_address (orig_dest, mode, offset); - + emit_insn ((*mov) (dest, const0_rtx)); } @@ -8404,7 +8408,7 @@ expand_block_move (rtx operands[]) return 1; /* store_one_arg depends on expand_block_move to handle at least the size of - reg_parm_stack_space. */ + reg_parm_stack_space. */ if (bytes > (TARGET_POWERPC64 ? 64 : 32)) return 0; @@ -8416,7 +8420,7 @@ expand_block_move (rtx operands[]) } gen_func; enum machine_mode mode = BLKmode; rtx src, dest; - + if (TARGET_STRING && bytes > 24 /* move up to 32 bytes at a time */ && ! fixed_regs[5] @@ -8490,14 +8494,14 @@ expand_block_move (rtx operands[]) mode = QImode; gen_func.mov = gen_movqi; } - + src = adjust_address (orig_src, mode, offset); dest = adjust_address (orig_dest, mode, offset); - - if (mode != BLKmode) + + if (mode != BLKmode) { rtx tmp_reg = gen_reg_rtx (mode); - + emit_insn ((*gen_func.mov) (tmp_reg, src)); stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg); } @@ -8520,14 +8524,14 @@ expand_block_move (rtx operands[]) src = replace_equiv_address (src, src_reg); } set_mem_size (src, GEN_INT (move_bytes)); - + if (!REG_P (XEXP (dest, 0))) { rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0)); dest = replace_equiv_address (dest, dest_reg); } set_mem_size (dest, GEN_INT (move_bytes)); - + emit_insn ((*gen_func.movmemsi) (dest, src, GEN_INT (move_bytes & 31), align_rtx)); @@ -8912,7 +8916,7 @@ mtcrf_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) return 0; src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0); - + if (GET_CODE (src_reg) != REG || GET_MODE (src_reg) != SImode || ! INT_REGNO_P (REGNO (src_reg))) @@ -8923,7 +8927,7 @@ mtcrf_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) rtx exp = XVECEXP (op, 0, i); rtx unspec; int maskval; - + if (GET_CODE (exp) != SET || GET_CODE (SET_DEST (exp)) != REG || GET_MODE (SET_DEST (exp)) != CCmode @@ -8931,7 +8935,7 @@ mtcrf_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) return 0; unspec = SET_SRC (exp); maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp))); - + if (GET_CODE (unspec) != UNSPEC || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR || XVECLEN (unspec, 0) != 2 @@ -9122,8 +9126,8 @@ validate_condition_mode (enum rtx_code code, enum machine_mode mode) || code == UNGT || code == UNLT || code == UNGE || code == UNLE)) abort (); - - /* These should never be generated except for + + /* These should never be generated except for flag_finite_math_only. */ if (mode == CCFPmode && ! flag_finite_math_only @@ -9133,7 +9137,7 @@ validate_condition_mode (enum rtx_code code, enum machine_mode mode) abort (); /* These are invalid; the information is not there. */ - if (mode == CCEQmode + if (mode == CCEQmode && code != EQ && code != NE) abort (); } @@ -9431,9 +9435,9 @@ int registers_ok_for_quad_peep (rtx reg1, rtx reg2) { /* We might have been passed a SUBREG. */ - if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) + if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) return 0; - + /* We might have been passed non floating point registers. */ if (!FP_REGNO_P (REGNO (reg1)) || !FP_REGNO_P (REGNO (reg2))) @@ -9456,7 +9460,7 @@ mems_ok_for_quad_peep (rtx mem1, rtx mem2) /* The mems cannot be volatile. */ if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2)) return 0; - + addr1 = XEXP (mem1, 0); addr2 = XEXP (mem2, 0); @@ -9485,7 +9489,7 @@ mems_ok_for_quad_peep (rtx mem1, rtx mem2) } /* Make sure the second address is a (mem (plus (reg) (const_int))) - or if it is (mem (reg)) then make sure that offset1 is -8 and the same + or if it is (mem (reg)) then make sure that offset1 is -8 and the same register as addr1. */ if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2)) return 1; @@ -9513,7 +9517,7 @@ mems_ok_for_quad_peep (rtx mem1, rtx mem2) NO_REGS is returned. */ enum reg_class -secondary_reload_class (enum reg_class class, +secondary_reload_class (enum reg_class class, enum machine_mode mode ATTRIBUTE_UNUSED, rtx in) { @@ -9529,7 +9533,7 @@ secondary_reload_class (enum reg_class class, other than BASE_REGS for TARGET_ELF. So indicate that a register from BASE_REGS is needed as an intermediate register. - + On Darwin, pic addresses require a load from memory, which needs a base register. */ if (class != BASE_REGS @@ -9585,7 +9589,7 @@ secondary_reload_class (enum reg_class class, } /* Given a comparison operation, return the bit number in CCR to test. We - know this is a valid comparison. + know this is a valid comparison. SCC_P is 1 if this is for an scc. That means that %D will have been used instead of %C, so the bits will be in different places. @@ -9621,7 +9625,7 @@ ccr_bit (rtx op, int scc_p) if (scc_p && code != EQ && code != GT && code != LT && code != UNORDERED && code != GTU && code != LTU) abort (); - + switch (code) { case NE: @@ -10038,7 +10042,7 @@ print_operand (FILE *file, rtx x, int code) reg_names[SMALL_DATA_REG]); } return; - + case 'm': /* MB value for a mask operand. */ if (! mask_operand (x, SImode)) @@ -10126,7 +10130,7 @@ print_operand (FILE *file, rtx x, int code) else s = t[1]; } - + fputs (s, file); } return; @@ -10213,7 +10217,7 @@ print_operand (FILE *file, rtx x, int code) if (! INT_P (x)) output_operand_lossage ("invalid %%u value"); else - fprintf (file, HOST_WIDE_INT_PRINT_HEX, + fprintf (file, HOST_WIDE_INT_PRINT_HEX, (INT_LOWPART (x) >> 16) & 0xffff); return; @@ -10277,7 +10281,7 @@ print_operand (FILE *file, rtx x, int code) /* If constant, low-order 16 bits of constant, signed. Otherwise, write normally. */ if (INT_P (x)) - fprintf (file, HOST_WIDE_INT_PRINT_DEC, + fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000); else print_operand (file, x, 0); @@ -10338,7 +10342,7 @@ print_operand (FILE *file, rtx x, int code) reg_names[SMALL_DATA_REG]); } return; - + case 'z': /* X is a SYMBOL_REF. Write out the name preceded by a period and without any trailing data in brackets. Used for function @@ -10435,7 +10439,7 @@ print_operand (FILE *file, rtx x, int code) abort (); break; } - + case 0: if (GET_CODE (x) == REG) fprintf (file, "%s", reg_names[REGNO (x)]); @@ -10518,7 +10522,7 @@ print_operand_address (FILE *file, rtx x) rtx contains_minus = XEXP (x, 1); rtx minus, symref; const char *name; - + /* Find the (minus (sym) (toc)) buried in X, and temporarily turn it into (sym) for output_addr_const. */ while (GET_CODE (XEXP (contains_minus, 0)) != MINUS) @@ -10565,7 +10569,7 @@ rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p) { extern int in_toc_section (void); static int recurse = 0; - + /* For -mrelocatable, we mark all addresses that need to be fixed up in the .fixup section. */ if (TARGET_RELOCATABLE @@ -10649,7 +10653,7 @@ rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code) { /* Reversal of FP compares takes care -- an ordered compare becomes an unordered compare and vice versa. */ - if (mode == CCFPmode + if (mode == CCFPmode && (!flag_finite_math_only || code == UNLT || code == UNLE || code == UNGT || code == UNGE || code == UNEQ || code == LTGT)) @@ -10765,9 +10769,9 @@ rs6000_generate_compare (enum rtx_code code) else emit_insn (gen_rtx_SET (VOIDmode, compare_result, gen_rtx_COMPARE (comp_mode, - rs6000_compare_op0, + rs6000_compare_op0, rs6000_compare_op1))); - + /* Some kinds of FP comparisons need an OR operation; under flag_finite_math_only we don't bother. */ if (rs6000_compare_fp_p @@ -10780,7 +10784,7 @@ rs6000_generate_compare (enum rtx_code code) enum rtx_code or1, or2; rtx or1_rtx, or2_rtx, compare2_rtx; rtx or_result = gen_reg_rtx (CCEQmode); - + switch (code) { case LE: or1 = LT; or2 = EQ; break; @@ -10805,7 +10809,7 @@ rs6000_generate_compare (enum rtx_code code) } validate_condition_mode (code, GET_MODE (compare_result)); - + return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx); } @@ -10848,7 +10852,7 @@ rs6000_emit_sCOND (enum rtx_code code, rtx result) rtx not_result = gen_reg_rtx (CCEQmode); rtx not_op, rev_cond_rtx; enum machine_mode cc_mode; - + cc_mode = GET_MODE (XEXP (condition_rtx, 0)); rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code), @@ -10890,7 +10894,7 @@ rs6000_emit_cbranch (enum rtx_code code, rtx loc) /* Return the string to output a conditional branch to LABEL, which is the operand number of the label, or -1 if the branch is really a - conditional return. + conditional return. OP is the conditional expression. XEXP (OP, 0) is assumed to be a condition code register and its mode specifies what kind of @@ -10951,13 +10955,13 @@ output_cbranch (rtx op, const char *label, int reversed, rtx insn) ccode = "ne"; break; case EQ: case UNEQ: ccode = "eq"; break; - case GE: case GEU: + case GE: case GEU: ccode = "ge"; break; - case GT: case GTU: case UNGT: + case GT: case GTU: case UNGT: ccode = "gt"; break; - case LE: case LEU: + case LE: case LEU: ccode = "le"; break; - case LT: case LTU: case UNLT: + case LT: case LTU: case UNLT: ccode = "lt"; break; case UNORDERED: ccode = "un"; break; case ORDERED: ccode = "nu"; break; @@ -10966,8 +10970,8 @@ output_cbranch (rtx op, const char *label, int reversed, rtx insn) default: abort (); } - - /* Maybe we have a guess as to how likely the branch is. + + /* Maybe we have a guess as to how likely the branch is. The old mnemonics don't have a way to specify this information. */ pred = ""; note = find_reg_note (insn, REG_BR_PROB, NULL_RTX); @@ -10981,7 +10985,7 @@ output_cbranch (rtx op, const char *label, int reversed, rtx insn) prediction. For older cpus we may as well always hint, but assume not taken for branches that are very close to 50% as a mispredicted taken branch is more expensive than a - mispredicted not-taken branch. */ + mispredicted not-taken branch. */ if (rs6000_always_hint || abs (prob) > REG_BR_PROB_BASE / 100 * 48) { @@ -11089,10 +11093,10 @@ rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) it'll probably be faster to use a branch here too. */ if (code == UNEQ && HONOR_NANS (compare_mode)) return 0; - + if (GET_CODE (op1) == CONST_DOUBLE) REAL_VALUE_FROM_CONST_DOUBLE (c1, op1); - + /* We're going to try to implement comparisons by performing a subtract, then comparing against zero. Unfortunately, Inf - Inf is NaN which is not zero, and so if we don't @@ -11103,7 +11107,7 @@ rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1)) /* Constructs of the form (a OP b ? a : b) are safe. */ && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond)) - || (! rtx_equal_p (op0, true_cond) + || (! rtx_equal_p (op0, true_cond) && ! rtx_equal_p (op1, true_cond)))) return 0; /* At this point we know we can use fsel. */ @@ -11156,7 +11160,7 @@ rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) case EQ: temp = gen_reg_rtx (compare_mode); - emit_insn (gen_rtx_SET (VOIDmode, temp, + emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, gen_rtx_ABS (compare_mode, op0)))); op0 = temp; @@ -11182,7 +11186,7 @@ rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) /* a GT 0 <-> (a GE 0 && -a UNLT 0) */ temp = gen_reg_rtx (result_mode); emit_insn (gen_rtx_SET (VOIDmode, temp, - gen_rtx_IF_THEN_ELSE (result_mode, + gen_rtx_IF_THEN_ELSE (result_mode, gen_rtx_GE (VOIDmode, op0, op1), true_cond, false_cond))); @@ -11261,10 +11265,10 @@ rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1) c = GEU; if (code == SMAX || code == UMAX) - target = emit_conditional_move (dest, c, op0, op1, mode, + target = emit_conditional_move (dest, c, op0, op1, mode, op0, op1, mode, 0); else - target = emit_conditional_move (dest, c, op0, op1, mode, + target = emit_conditional_move (dest, c, op0, op1, mode, op1, op0, mode, 0); if (target == NULL_RTX) abort (); @@ -11301,17 +11305,17 @@ rs6000_split_multireg_move (rtx dst, rtx src) else reg_mode = word_mode; reg_mode_size = GET_MODE_SIZE (reg_mode); - + if (reg_mode_size * nregs != GET_MODE_SIZE (mode)) abort (); - + if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst))) { /* Move register range backwards, if we might have destructive overlap. */ int i; for (i = nregs - 1; i >= 0; i--) - emit_insn (gen_rtx_SET (VOIDmode, + emit_insn (gen_rtx_SET (VOIDmode, simplify_gen_subreg (reg_mode, dst, mode, i * reg_mode_size), simplify_gen_subreg (reg_mode, src, mode, @@ -11332,9 +11336,9 @@ rs6000_split_multireg_move (rtx dst, rtx src) { rtx delta_rtx; breg = XEXP (XEXP (src, 0), 0); - delta_rtx = GET_CODE (XEXP (src, 0)) == PRE_INC - ? GEN_INT (GET_MODE_SIZE (GET_MODE (src))) - : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))); + delta_rtx = GET_CODE (XEXP (src, 0)) == PRE_INC + ? GEN_INT (GET_MODE_SIZE (GET_MODE (src))) + : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))); emit_insn (TARGET_32BIT ? gen_addsi3 (breg, breg, delta_rtx) : gen_adddi3 (breg, breg, delta_rtx)); @@ -11351,7 +11355,7 @@ rs6000_split_multireg_move (rtx dst, rtx src) } /* We have now address involving an base register only. - If we use one of the registers to address memory, + If we use one of the registers to address memory, we have change that register last. */ breg = (GET_CODE (XEXP (src, 0)) == PLUS @@ -11361,7 +11365,7 @@ rs6000_split_multireg_move (rtx dst, rtx src) if (!REG_P (breg)) abort(); - if (REGNO (breg) >= REGNO (dst) + if (REGNO (breg) >= REGNO (dst) && REGNO (breg) < REGNO (dst) + nregs) j = REGNO (breg) - REGNO (dst); } @@ -11375,9 +11379,9 @@ rs6000_split_multireg_move (rtx dst, rtx src) { rtx delta_rtx; breg = XEXP (XEXP (dst, 0), 0); - delta_rtx = GET_CODE (XEXP (dst, 0)) == PRE_INC - ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst))) - : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))); + delta_rtx = GET_CODE (XEXP (dst, 0)) == PRE_INC + ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst))) + : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))); /* We have to update the breg before doing the store. Use store with update, if available. */ @@ -11401,17 +11405,17 @@ rs6000_split_multireg_move (rtx dst, rtx src) } for (i = 0; i < nregs; i++) - { + { /* Calculate index to next subword. */ ++j; - if (j == nregs) + if (j == nregs) j = 0; - /* If compiler already emited move of first word by + /* If compiler already emited move of first word by store with update, no need to do anything. */ if (j == 0 && used_update) continue; - + emit_insn (gen_rtx_SET (VOIDmode, simplify_gen_subreg (reg_mode, dst, mode, j * reg_mode_size), @@ -11435,7 +11439,7 @@ first_reg_to_save (void) /* Find lowest numbered live register. */ for (first_reg = 13; first_reg <= 31; first_reg++) - if (regs_ever_live[first_reg] + if (regs_ever_live[first_reg] && (! call_used_regs[first_reg] || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) @@ -11537,21 +11541,21 @@ compute_save_world_info(rs6000_stack_t *info_ptr) && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO && info_ptr->cr_save_p; - + /* This will not work in conjunction with sibcalls. Make sure there are none. (This check is expensive, but seldom executed.) */ if ( info_ptr->world_save_p ) - { + { rtx insn; for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn)) if ( GET_CODE (insn) == CALL_INSN && SIBLING_CALL_P (insn)) - { + { info_ptr->world_save_p = 0; break; } } - + if (info_ptr->world_save_p) { /* Even if we're not touching VRsave, make sure there's room on the @@ -11566,11 +11570,11 @@ compute_save_world_info(rs6000_stack_t *info_ptr) /* Because the Darwin register save/restore routines only handle F14 .. F31 and V20 .. V31 as per the ABI, perform a consistancy check and abort if there's something worng. */ - if (info_ptr->first_fp_reg_save < FIRST_SAVED_FP_REGNO + if (info_ptr->first_fp_reg_save < FIRST_SAVED_FP_REGNO || info_ptr->first_altivec_reg_save < FIRST_SAVED_ALTIVEC_REGNO) abort (); } - return; + return; } @@ -11637,11 +11641,11 @@ is_altivec_return_reg (rtx reg, void *xyes) | Parameter save area (P) | 8 +---------------------------------------+ | Alloca space (A) | 8+P - +---------------------------------------+ + +---------------------------------------+ | Varargs save area (V) | 8+P+A - +---------------------------------------+ + +---------------------------------------+ | Local variable space (L) | 8+P+A+V - +---------------------------------------+ + +---------------------------------------+ | Float/int conversion temporary (X) | 8+P+A+V+L +---------------------------------------+ | Save area for AltiVec registers (W) | 8+P+A+V+L+X @@ -11655,9 +11659,9 @@ is_altivec_return_reg (rtx reg, void *xyes) | SPE alignment padding | +---------------------------------------+ | saved CR (C) | 8+P+A+V+L+X+W+Y+Z - +---------------------------------------+ + +---------------------------------------+ | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C - +---------------------------------------+ + +---------------------------------------+ | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G +---------------------------------------+ old SP->| back chain to caller's caller | @@ -11707,7 +11711,7 @@ rs6000_stack_info (void) /* Calculate which registers need to be saved & save area size. */ info_ptr->first_gp_reg_save = first_reg_to_save (); - /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM, + /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM, even if it currently looks like we won't. */ if (((TARGET_TOC && TARGET_MINIMAL_TOC) || (flag_pic == 1 && DEFAULT_ABI == ABI_V4) @@ -11765,7 +11769,7 @@ rs6000_stack_info (void) } /* Determine if we need to save the condition code registers. */ - if (regs_ever_live[CR2_REGNO] + if (regs_ever_live[CR2_REGNO] || regs_ever_live[CR3_REGNO] || regs_ever_live[CR4_REGNO]) { @@ -12249,7 +12253,7 @@ rs6000_ra_ever_killed (void) When we're called from the epilogue, we need to avoid counting this as a store. */ - + push_topmost_sequence (); top = get_insns (); pop_topmost_sequence (); @@ -12261,7 +12265,7 @@ rs6000_ra_ever_killed (void) { if (FIND_REG_INC_NOTE (insn, reg)) return 1; - else if (GET_CODE (insn) == CALL_INSN + else if (GET_CODE (insn) == CALL_INSN && !SIBLING_CALL_P (insn)) return 1; else if (set_of (reg, insn) != NULL_RTX @@ -12422,20 +12426,20 @@ rs6000_emit_eh_reg_restore (rtx source, rtx scratch) static GTY(()) int set = -1; -int +int get_TOC_alias_set (void) { if (set == -1) set = new_alias_set (); return set; -} +} /* This returns nonzero if the current function uses the TOC. This is determined by the presence of (use (unspec ... UNSPEC_TOC)), which is generated by the ABI_V4 load_toc_* patterns. */ #if TARGET_ELF static int -uses_TOC (void) +uses_TOC (void) { rtx insn; @@ -12445,7 +12449,7 @@ uses_TOC (void) rtx pat = PATTERN (insn); int i; - if (GET_CODE (pat) == PARALLEL) + if (GET_CODE (pat) == PARALLEL) for (i = 0; i < XVECLEN (pat, 0); i++) { rtx sub = XVECEXP (pat, 0, i); @@ -12463,12 +12467,12 @@ uses_TOC (void) #endif rtx -create_TOC_reference (rtx symbol) +create_TOC_reference (rtx symbol) { - return gen_rtx_PLUS (Pmode, + return gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, TOC_REGISTER), - gen_rtx_CONST (Pmode, - gen_rtx_MINUS (Pmode, symbol, + gen_rtx_CONST (Pmode, + gen_rtx_MINUS (Pmode, symbol, gen_rtx_SYMBOL_REF (Pmode, toc_label_name)))); } @@ -12535,7 +12539,7 @@ rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12) if (current_function_limit_stack) { if (REG_P (stack_limit_rtx) - && REGNO (stack_limit_rtx) > 1 + && REGNO (stack_limit_rtx) > 1 && REGNO (stack_limit_rtx) <= 31) { emit_insn (TARGET_32BIT @@ -12554,8 +12558,8 @@ rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12) && DEFAULT_ABI == ABI_V4) { rtx toload = gen_rtx_CONST (VOIDmode, - gen_rtx_PLUS (Pmode, - stack_limit_rtx, + gen_rtx_PLUS (Pmode, + stack_limit_rtx, GEN_INT (size))); emit_insn (gen_elf_high (tmp_reg, toload)); @@ -12585,7 +12589,7 @@ rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12) insn = emit_insn (TARGET_32BIT ? gen_movsi_update (stack_reg, stack_reg, todec, stack_reg) - : gen_movdi_update (stack_reg, stack_reg, + : gen_movdi_update (stack_reg, stack_reg, todec, stack_reg)); } else @@ -12596,11 +12600,11 @@ rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12) emit_move_insn (gen_rtx_MEM (Pmode, stack_reg), gen_rtx_REG (Pmode, 12)); } - + RTX_FRAME_RELATED_P (insn) = 1; - REG_NOTES (insn) = + REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, - gen_rtx_SET (VOIDmode, stack_reg, + gen_rtx_SET (VOIDmode, stack_reg, gen_rtx_PLUS (Pmode, stack_reg, GEN_INT (-size))), REG_NOTES (insn)); @@ -12613,7 +12617,7 @@ rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12) its hand so much. */ static void -rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val, +rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val, rtx reg2, rtx rreg) { rtx real, temp; @@ -12630,12 +12634,12 @@ rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val, if (reg2 != NULL_RTX) real = replace_rtx (real, reg2, rreg); - - real = replace_rtx (real, reg, + + real = replace_rtx (real, reg, gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM), GEN_INT (val))); - + /* We expect that 'real' is either a SET or a PARALLEL containing SETs (and possibly other stuff). In a PARALLEL, all the SETs are important so they all have to be marked RTX_FRAME_RELATED_P. */ @@ -12643,7 +12647,7 @@ rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val, if (GET_CODE (real) == SET) { rtx set = real; - + temp = simplify_rtx (SET_SRC (set)); if (temp) SET_SRC (set) = temp; @@ -12664,7 +12668,7 @@ rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val, if (GET_CODE (XVECEXP (real, 0, i)) == SET) { rtx set = XVECEXP (real, 0, i); - + temp = simplify_rtx (SET_SRC (set)); if (temp) SET_SRC (set) = temp; @@ -12818,7 +12822,7 @@ generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep) Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */ static void -emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode, +emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode, unsigned int regno, int offset, HOST_WIDE_INT total_size) { rtx reg, offset_rtx, insn, mem, addr, int_rtx; @@ -12898,7 +12902,7 @@ rs6000_emit_prologue (void) int saving_FPRs_inline; int using_store_multiple; HOST_WIDE_INT sp_offset = 0; - + if (TARGET_FIX_AND_CONTINUE) { /* gdb on darwin arranges to forward a function from the old @@ -12936,7 +12940,7 @@ rs6000_emit_prologue (void) sp_offset = info->total_size; else frame_reg_rtx = frame_ptr_rtx; - rs6000_emit_allocate_stack (info->total_size, + rs6000_emit_allocate_stack (info->total_size, (frame_reg_rtx != sp_reg_rtx && (info->cr_save_p || info->lr_save_p @@ -13091,7 +13095,7 @@ rs6000_emit_prologue (void) /* AltiVec addressing mode is [reg+reg]. */ mem = gen_rtx_MEM (V4SImode, gen_rtx_PLUS (Pmode, frame_reg_rtx, areg)); - + set_mem_alias_set (mem, rs6000_sr_alias_set); insn = emit_move_insn (mem, savereg); @@ -13148,7 +13152,7 @@ rs6000_emit_prologue (void) if (! info->world_save_p && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx) { rtx set; - + cr_save_rtx = gen_rtx_REG (SImode, 12); insn = emit_insn (gen_movesi_from_cr (cr_save_rtx)); RTX_FRAME_RELATED_P (insn) = 1; @@ -13171,7 +13175,7 @@ rs6000_emit_prologue (void) { int i; for (i = 0; i < 64 - info->first_fp_reg_save; i++) - if ((regs_ever_live[info->first_fp_reg_save+i] + if ((regs_ever_live[info->first_fp_reg_save+i] && ! call_used_regs[info->first_fp_reg_save+i])) emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode, info->first_fp_reg_save + i, @@ -13185,9 +13189,9 @@ rs6000_emit_prologue (void) const char *alloc_rname; rtvec p; p = rtvec_alloc (2 + 64 - info->first_fp_reg_save); - - RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode, - gen_rtx_REG (Pmode, + + RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode, + gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); sprintf (rname, "%s%d%s", SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX); @@ -13200,7 +13204,7 @@ rs6000_emit_prologue (void) rtx addr, reg, mem; reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, - GEN_INT (info->fp_save_offset + GEN_INT (info->fp_save_offset + sp_offset + 8*i)); mem = gen_rtx_MEM (DFmode, addr); set_mem_alias_set (mem, rs6000_sr_alias_set); @@ -13208,7 +13212,7 @@ rs6000_emit_prologue (void) RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg); } insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); - rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, + rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, NULL_RTX, NULL_RTX); } @@ -13223,9 +13227,9 @@ rs6000_emit_prologue (void) { rtx addr, reg, mem; reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); - addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, - GEN_INT (info->gp_save_offset - + sp_offset + addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, + GEN_INT (info->gp_save_offset + + sp_offset + reg_size * i)); mem = gen_rtx_MEM (reg_mode, addr); set_mem_alias_set (mem, rs6000_sr_alias_set); @@ -13233,14 +13237,14 @@ rs6000_emit_prologue (void) RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg); } insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); - rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, + rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, NULL_RTX, NULL_RTX); } else if (! info->world_save_p) { int i; for (i = 0; i < 32 - info->first_gp_reg_save; i++) - if ((regs_ever_live[info->first_gp_reg_save+i] + if ((regs_ever_live[info->first_gp_reg_save+i] && (! call_used_regs[info->first_gp_reg_save+i] || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM @@ -13279,15 +13283,15 @@ rs6000_emit_prologue (void) } else { - addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, - GEN_INT (info->gp_save_offset - + sp_offset + addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, + GEN_INT (info->gp_save_offset + + sp_offset + reg_size * i)); mem = gen_rtx_MEM (reg_mode, addr); set_mem_alias_set (mem, rs6000_sr_alias_set); insn = emit_move_insn (mem, reg); - rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, + rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, NULL_RTX, NULL_RTX); } } @@ -13311,7 +13315,7 @@ rs6000_emit_prologue (void) set_mem_alias_set (mem, rs6000_sr_alias_set); insn = emit_move_insn (mem, reg); - rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, + rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, NULL_RTX, NULL_RTX); PATTERN (insn) = gen_blockage (); } @@ -13338,9 +13342,9 @@ rs6000_emit_prologue (void) rtx mem = gen_rtx_MEM (Pmode, addr); /* This should not be of rs6000_sr_alias_set, because of __builtin_return_address. */ - + insn = emit_move_insn (mem, reg); - rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, + rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, NULL_RTX, NULL_RTX); } @@ -13368,15 +13372,15 @@ rs6000_emit_prologue (void) REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, set, REG_NOTES (insn)); - + } insn = emit_move_insn (mem, cr_save_rtx); - rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, + rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, NULL_RTX, NULL_RTX); } - /* Update stack and set back pointer unless this is V.4, + /* Update stack and set back pointer unless this is V.4, for which it was done previously. */ if (! info->world_save_p && info->push_p && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return)) @@ -13385,7 +13389,7 @@ rs6000_emit_prologue (void) /* Set frame pointer, if needed. */ if (frame_pointer_needed) { - insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM), + insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM), sp_reg_rtx); RTX_FRAME_RELATED_P (insn) = 1; } @@ -13431,7 +13435,7 @@ rs6000_emit_prologue (void) rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src))); - insn = emit_move_insn (gen_rtx_REG (Pmode, + insn = emit_move_insn (gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM), lr); rs6000_maybe_dead (insn); @@ -13442,7 +13446,7 @@ rs6000_emit_prologue (void) /* Write function prologue. */ static void -rs6000_output_function_prologue (FILE *file, +rs6000_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) { rs6000_stack_t *info = rs6000_stack_info (); @@ -13500,7 +13504,7 @@ rs6000_output_function_prologue (FILE *file, rs6000_pic_labelno++; } - + /* Emit function epilogue as insns. At present, dwarf2out_frame_debug_expr doesn't understand @@ -13539,7 +13543,7 @@ rs6000_emit_epilogue (int sibcall) || current_function_calls_eh_return || info->first_fp_reg_save == 64 || FP_SAVE_INLINE (info->first_fp_reg_save)); - use_backchain_to_restore_sp = (frame_pointer_needed + use_backchain_to_restore_sp = (frame_pointer_needed || current_function_calls_alloca || info->total_size > 32767); using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601 @@ -13563,7 +13567,7 @@ rs6000_emit_epilogue (int sibcall) p = rtvec_alloc (9 + 1 - + 32 - info->first_gp_reg_save + + 32 - info->first_gp_reg_save + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save + 63 + 1 - info->first_fp_reg_save); @@ -13654,7 +13658,7 @@ rs6000_emit_epilogue (int sibcall) emit_move_insn (frame_reg_rtx, gen_rtx_MEM (Pmode, sp_reg_rtx)); - + } else if (info->push_p) { @@ -13670,7 +13674,7 @@ rs6000_emit_epilogue (int sibcall) GEN_INT (info->total_size))); } } - + /* Restore AltiVec registers if needed. */ if (TARGET_ALTIVEC_ABI && info->altivec_size != 0) { @@ -13722,7 +13726,7 @@ rs6000_emit_epilogue (int sibcall) emit_move_insn (gen_rtx_REG (Pmode, 0), mem); } - + /* Get the old cr if we saved it. */ if (info->cr_save_p) { @@ -13734,12 +13738,12 @@ rs6000_emit_epilogue (int sibcall) emit_move_insn (gen_rtx_REG (SImode, 12), mem); } - + /* Set LR here to try to overlap restores below. */ if (info->lr_save_p) emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), gen_rtx_REG (Pmode, 0)); - + /* Load exception handler data registers, if needed. */ if (current_function_calls_eh_return) { @@ -13772,7 +13776,7 @@ rs6000_emit_epilogue (int sibcall) emit_move_insn (gen_rtx_REG (reg_mode, regno), mem); } } - + /* Restore GPRs. This is done as a PARALLEL if we are using the load-multiple instructions. */ if (using_load_multiple) @@ -13781,15 +13785,15 @@ rs6000_emit_epilogue (int sibcall) p = rtvec_alloc (32 - info->first_gp_reg_save); for (i = 0; i < 32 - info->first_gp_reg_save; i++) { - rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, - GEN_INT (info->gp_save_offset - + sp_offset + rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, + GEN_INT (info->gp_save_offset + + sp_offset + reg_size * i)); rtx mem = gen_rtx_MEM (reg_mode, addr); set_mem_alias_set (mem, rs6000_sr_alias_set); - RTVEC_ELT (p, i) = + RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, gen_rtx_REG (reg_mode, info->first_gp_reg_save + i), mem); @@ -13798,7 +13802,7 @@ rs6000_emit_epilogue (int sibcall) } else for (i = 0; i < 32 - info->first_gp_reg_save; i++) - if ((regs_ever_live[info->first_gp_reg_save+i] + if ((regs_ever_live[info->first_gp_reg_save+i] && (! call_used_regs[info->first_gp_reg_save+i] || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM && TARGET_TOC && TARGET_MINIMAL_TOC))) @@ -13806,9 +13810,9 @@ rs6000_emit_epilogue (int sibcall) && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) { - rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, - GEN_INT (info->gp_save_offset - + sp_offset + rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, + GEN_INT (info->gp_save_offset + + sp_offset + reg_size * i)); rtx mem = gen_rtx_MEM (reg_mode, addr); @@ -13832,25 +13836,25 @@ rs6000_emit_epilogue (int sibcall) set_mem_alias_set (mem, rs6000_sr_alias_set); - emit_move_insn (gen_rtx_REG (reg_mode, + emit_move_insn (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i), mem); } /* Restore fpr's if we need to do it without calling a function. */ if (restoring_FPRs_inline) for (i = 0; i < 64 - info->first_fp_reg_save; i++) - if ((regs_ever_live[info->first_fp_reg_save+i] + if ((regs_ever_live[info->first_fp_reg_save+i] && ! call_used_regs[info->first_fp_reg_save+i])) { rtx addr, mem; addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, - GEN_INT (info->fp_save_offset - + sp_offset + GEN_INT (info->fp_save_offset + + sp_offset + 8 * i)); mem = gen_rtx_MEM (DFmode, addr); set_mem_alias_set (mem, rs6000_sr_alias_set); - emit_move_insn (gen_rtx_REG (DFmode, + emit_move_insn (gen_rtx_REG (DFmode, info->first_fp_reg_save + i), mem); } @@ -13860,7 +13864,7 @@ rs6000_emit_epilogue (int sibcall) { rtx r12_rtx = gen_rtx_REG (SImode, 12); int count = 0; - + if (using_mfcr_multiple) { for (i = 0; i < 8; i++) @@ -13874,7 +13878,7 @@ rs6000_emit_epilogue (int sibcall) { rtvec p; int ndx; - + p = rtvec_alloc (count); ndx = 0; @@ -13885,7 +13889,7 @@ rs6000_emit_epilogue (int sibcall) RTVEC_ELT (r, 0) = r12_rtx; RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i)); RTVEC_ELT (p, ndx) = - gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i), + gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i), gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR)); ndx++; } @@ -13897,7 +13901,7 @@ rs6000_emit_epilogue (int sibcall) for (i = 0; i < 8; i++) if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) { - emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode, + emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode, CR0_REGNO+i), r12_rtx)); } @@ -13946,8 +13950,8 @@ rs6000_emit_epilogue (int sibcall) p = rtvec_alloc (2); RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode); - RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, - gen_rtx_REG (Pmode, + RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, + gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); /* If we have to restore more than two FP registers, branch to the @@ -13958,7 +13962,7 @@ rs6000_emit_epilogue (int sibcall) char rname[30]; const char *alloc_rname; - sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX, + sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); alloc_rname = ggc_strdup (rname); RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, @@ -13973,13 +13977,13 @@ rs6000_emit_epilogue (int sibcall) mem = gen_rtx_MEM (DFmode, addr); set_mem_alias_set (mem, rs6000_sr_alias_set); - RTVEC_ELT (p, i+3) = + RTVEC_ELT (p, i+3) = gen_rtx_SET (VOIDmode, gen_rtx_REG (DFmode, info->first_fp_reg_save + i), mem); } } - + emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); } } @@ -13987,7 +13991,7 @@ rs6000_emit_epilogue (int sibcall) /* Write function epilogue. */ static void -rs6000_output_function_epilogue (FILE *file, +rs6000_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) { rs6000_stack_t *info = rs6000_stack_info (); @@ -14039,8 +14043,8 @@ rs6000_output_function_epilogue (FILE *file, && NOTE_P (insn) && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL) insn = PREV_INSN (insn); - if (insn - && (LABEL_P (insn) + if (insn + && (LABEL_P (insn) || (NOTE_P (insn) && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL))) fputs ("\tnop\n", file); @@ -14302,8 +14306,8 @@ rs6000_output_function_epilogue (FILE *file, not support varargs. */ static void -rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, - HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, +rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, + HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, tree function) { rtx this, insn, funexp; @@ -14405,7 +14409,7 @@ rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, /* A quick summary of the various types of 'constant-pool tables' under PowerPC: - Target Flags Name One table per + Target Flags Name One table per AIX (none) AIX TOC object file AIX -mfull-toc AIX TOC object file AIX -mminimal-toc AIX minimal TOC translation unit @@ -14414,7 +14418,7 @@ rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, SVR4/EABI -fPIC SVR4 PIC translation unit SVR4/EABI -mrelocatable EABI TOC function SVR4/EABI -maix AIX TOC object file - SVR4/EABI -maix -mminimal-toc + SVR4/EABI -maix -mminimal-toc AIX minimal TOC translation unit Name Reg. Set by entries contains: @@ -14439,7 +14443,7 @@ rs6000_hash_constant (rtx k) unsigned result = (code << 3) ^ mode; const char *format; int flen, fidx; - + format = GET_RTX_FORMAT (code); flen = strlen (format); fidx = 0; @@ -14507,7 +14511,7 @@ rs6000_hash_constant (rtx k) static unsigned toc_hash_function (const void *hash_entry) { - const struct toc_hash_struct *thc = + const struct toc_hash_struct *thc = (const struct toc_hash_struct *) hash_entry; return rs6000_hash_constant (thc->key) ^ thc->key_mode; } @@ -14537,7 +14541,7 @@ toc_hash_eq (const void *h1, const void *h2) || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \ || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \ || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \ - || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0) + || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0) void rs6000_output_symbol_ref (FILE *file, rtx x) @@ -14545,12 +14549,12 @@ rs6000_output_symbol_ref (FILE *file, rtx x) /* Currently C++ toc references to vtables can be emitted before it is decided whether the vtable is public or private. If this is the case, then the linker will eventually complain that there is - a reference to an unknown section. Thus, for vtables only, + a reference to an unknown section. Thus, for vtables only, we emit the TOC reference to reference the symbol and not the section. */ const char *name = XSTR (x, 0); - if (VTABLE_NAME_P (name)) + if (VTABLE_NAME_P (name)) { RS6000_OUTPUT_BASENAME (file, name); } @@ -14581,29 +14585,29 @@ output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode) { struct toc_hash_struct *h; void * * found; - + /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS time because GGC is not initialized at that point. */ if (toc_hash_table == NULL) - toc_hash_table = htab_create_ggc (1021, toc_hash_function, + toc_hash_table = htab_create_ggc (1021, toc_hash_function, toc_hash_eq, NULL); h = ggc_alloc (sizeof (*h)); h->key = x; h->key_mode = mode; h->labelno = labelno; - + found = htab_find_slot (toc_hash_table, h, 1); if (*found == NULL) *found = h; - else /* This is indeed a duplicate. + else /* This is indeed a duplicate. Set this label equal to that label. */ { fputs ("\t.set ", file); ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); fprintf (file, "%d,", labelno); ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); - fprintf (file, "%d\n", ((*(const struct toc_hash_struct **) + fprintf (file, "%d\n", ((*(const struct toc_hash_struct **) found)->labelno)); return; } @@ -14809,7 +14813,7 @@ output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode) base = XEXP (XEXP (x, 0), 0); offset = INTVAL (XEXP (XEXP (x, 0), 1)); } - + if (GET_CODE (base) == SYMBOL_REF) name = XSTR (base, 0); else if (GET_CODE (base) == LABEL_REF) @@ -14933,7 +14937,7 @@ output_ascii (FILE *file, const char *p, int n) the name. */ void -rs6000_gen_section_name (char **buf, const char *filename, +rs6000_gen_section_name (char **buf, const char *filename, const char *section_desc) { const char *q, *after_last_slash, *last_period = 0; @@ -14987,7 +14991,7 @@ output_profile_hook (int labelno ATTRIBUTE_UNUSED) #ifndef NO_PROFILE_COUNTERS # define NO_PROFILE_COUNTERS 0 #endif - if (NO_PROFILE_COUNTERS) + if (NO_PROFILE_COUNTERS) emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0); else { @@ -15065,7 +15069,7 @@ output_function_profiler (FILE *file, int labelno) assemble_name (file, buf); fputs ("-.\n1:", file); asm_fprintf (file, "\tmflr %s\n", reg_names[11]); - asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n", + asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n", reg_names[0], reg_names[11]); asm_fprintf (file, "\t{cax|add} %s,%s,%s\n", reg_names[0], reg_names[0], reg_names[11]); @@ -15124,8 +15128,8 @@ output_function_profiler (FILE *file, int labelno) instructions to issue in this cycle. */ static int -rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED, - int verbose ATTRIBUTE_UNUSED, +rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED, + int verbose ATTRIBUTE_UNUSED, rtx insn, int more) { if (GET_CODE (PATTERN (insn)) == USE @@ -15147,7 +15151,7 @@ rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED, a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ static int -rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn ATTRIBUTE_UNUSED, +rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn ATTRIBUTE_UNUSED, int cost) { if (! recog_memoized (insn)) @@ -15314,7 +15318,7 @@ is_branch_slot_insn (rtx insn) { enum attr_type type = get_attr_type (insn); if (type == TYPE_BRANCH || type == TYPE_JMPREG) - return true; + return true; return false; } @@ -15362,22 +15366,22 @@ rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority) if (is_dispatch_slot_restricted (insn) && reload_completed - && current_sched_info->sched_max_insns_priority + && current_sched_info->sched_max_insns_priority && rs6000_sched_restricted_insns_priority) { /* Prioritize insns that can be dispatched only in the first dispatch slot. */ if (rs6000_sched_restricted_insns_priority == 1) - /* Attach highest priority to insn. This means that in - haifa-sched.c:ready_sort(), dispatch-slot restriction considerations + /* Attach highest priority to insn. This means that in + haifa-sched.c:ready_sort(), dispatch-slot restriction considerations precede 'priority' (critical path) considerations. */ - return current_sched_info->sched_max_insns_priority; + return current_sched_info->sched_max_insns_priority; else if (rs6000_sched_restricted_insns_priority == 2) - /* Increase priority of insn by a minimal amount. This means that in + /* Increase priority of insn by a minimal amount. This means that in haifa-sched.c:ready_sort(), only 'priority' (critical path) considerations precede dispatch-slot restriction considerations. */ - return (priority + 1); - } + return (priority + 1); + } return priority; } @@ -15402,7 +15406,7 @@ rs6000_issue_rate (void) case CPU_PPC750: case CPU_PPC7400: case CPU_PPC8540: - return 2; + return 2; case CPU_RIOS2: case CPU_PPC604: case CPU_PPC604E: @@ -15456,7 +15460,7 @@ is_mem_ref (rtx pat) } /* Determine if PAT is a PATTERN of a load insn. */ - + static bool is_load_insn1 (rtx pat) { @@ -15531,33 +15535,33 @@ is_store_insn (rtx insn) static bool rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost, int distance) -{ +{ /* If the flag is not enbled - no dependence is considered costly; - allow all dependent insns in the same group. + allow all dependent insns in the same group. This is the most aggressive option. */ if (rs6000_sched_costly_dep == no_dep_costly) return false; - /* If the flag is set to 1 - a dependence is always considered costly; + /* If the flag is set to 1 - a dependence is always considered costly; do not allow dependent instructions in the same group. This is the most conservative option. */ if (rs6000_sched_costly_dep == all_deps_costly) - return true; + return true; - if (rs6000_sched_costly_dep == store_to_load_dep_costly - && is_load_insn (next) + if (rs6000_sched_costly_dep == store_to_load_dep_costly + && is_load_insn (next) && is_store_insn (insn)) /* Prevent load after store in the same group. */ return true; if (rs6000_sched_costly_dep == true_store_to_load_dep_costly - && is_load_insn (next) + && is_load_insn (next) && is_store_insn (insn) && (!link || (int) REG_NOTE_KIND (link) == 0)) /* Prevent load after store in the same group if it is a true dependence. */ return true; - - /* The flag is set to X; dependences with latency >= X are considered costly, + + /* The flag is set to X; dependences with latency >= X are considered costly, and will not be scheduled in the same group. */ if (rs6000_sched_costly_dep <= max_dep_latency && ((cost - distance) >= (int)rs6000_sched_costly_dep)) @@ -15566,7 +15570,7 @@ rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost, int distanc return false; } -/* Return the next insn after INSN that is found before TAIL is reached, +/* Return the next insn after INSN that is found before TAIL is reached, skipping any "non-active" insns - insns that will not actually occupy an issue slot. Return NULL_RTX if such an insn is not found. */ @@ -15668,7 +15672,7 @@ is_costly_group (rtx *group_insns, rtx next_insn) return false; } -/* Utility of the function redefine_groups. +/* Utility of the function redefine_groups. Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS in the same dispatch group. If so, insert nops before NEXT_INSN, in order to keep it "far" (in a separate group) from GROUP_INSNS, following @@ -15676,12 +15680,12 @@ is_costly_group (rtx *group_insns, rtx next_insn) -minsert_sched_nops = X: (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed in order to force NEXT_INSN into a separate group. - (2) X < sched_finish_regroup_exact: insert exactly X nops. - GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop + (2) X < sched_finish_regroup_exact: insert exactly X nops. + GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop insertion (has a group just ended, how many vacant issue slots remain in the last group, and how many dispatch groups were encountered so far). */ -static int +static int force_new_group (int sched_verbose, FILE *dump, rtx *group_insns, rtx next_insn, bool *group_end, int can_issue_more, int *group_count) { @@ -15727,13 +15731,13 @@ force_new_group (int sched_verbose, FILE *dump, rtx *group_insns, rtx next_insn, *group_end = true; return 0; - } + } if (rs6000_sched_insert_nops < sched_finish_regroup_exact) { int n_nops = rs6000_sched_insert_nops; - /* Nops can't be issued from the branch slot, so the effective + /* Nops can't be issued from the branch slot, so the effective issue_rate for nops is 'issue_rate - 1'. */ if (can_issue_more == 0) can_issue_more = issue_rate; @@ -15764,16 +15768,16 @@ force_new_group (int sched_verbose, FILE *dump, rtx *group_insns, rtx next_insn, for (i = 0; i < issue_rate; i++) { group_insns[i] = 0; - } - } + } + } n_nops--; } /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */ - can_issue_more++; + can_issue_more++; *group_end = /* Is next_insn going to start a new group? */ - (end + (end || (can_issue_more == 1 && !is_branch_slot_insn (next_insn)) || (can_issue_more <= 2 && is_cracked_insn (next_insn)) || (can_issue_more < issue_rate && @@ -15784,14 +15788,14 @@ force_new_group (int sched_verbose, FILE *dump, rtx *group_insns, rtx next_insn, if (sched_verbose > 6) fprintf (dump, "done force: group count = %d, can_issue_more = %d\n", *group_count, can_issue_more); - return can_issue_more; - } + return can_issue_more; + } return can_issue_more; } /* This function tries to synch the dispatch groups that the compiler "sees" - with the dispatch groups that the processor dispatcher is expected to + with the dispatch groups that the processor dispatcher is expected to form in practice. It tries to achieve this synchronization by forcing the estimated processor grouping on the compiler (as opposed to the function 'pad_goups' which tries to force the scheduler's grouping on the processor). @@ -15815,7 +15819,7 @@ force_new_group (int sched_verbose, FILE *dump, rtx *group_insns, rtx next_insn, - only the last 2 or less issue slots, including the branch slot, are vacant, which means that a cracked insn (which occupies two issue slots) can't be issued in this group. - - less than 'issue_rate' slots are vacant, and the next insn always needs to + - less than 'issue_rate' slots are vacant, and the next insn always needs to start a new group. */ static int @@ -15832,7 +15836,7 @@ redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail) /* Initialize. */ issue_rate = rs6000_issue_rate (); group_insns = alloca (issue_rate * sizeof (rtx)); - for (i = 0; i < issue_rate; i++) + for (i = 0; i < issue_rate; i++) { group_insns[i] = 0; } @@ -15861,7 +15865,7 @@ redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail) || (can_issue_more < issue_rate && insn_terminates_group_p (next_insn, previous_group))); - can_issue_more = force_new_group (sched_verbose, dump, group_insns, + can_issue_more = force_new_group (sched_verbose, dump, group_insns, next_insn, &group_end, can_issue_more, &group_count); if (group_end) @@ -16075,7 +16079,7 @@ const struct attribute_spec rs6000_attribute_table[] = /* Handle the "altivec" attribute. The attribute may have arguments as follows: - + __attribute__((altivec(vector__))) __attribute__((altivec(pixel__))) (always followed by 'unsigned short') __attribute__((altivec(bool__))) (always followed by 'unsigned') @@ -16095,7 +16099,7 @@ rs6000_handle_altivec_attribute (tree *node, tree name, tree args, = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args) && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE) ? *IDENTIFIER_POINTER (TREE_VALUE (args)) - : '?'); + : '?'); while (POINTER_TYPE_P (type) || TREE_CODE (type) == FUNCTION_TYPE @@ -16182,9 +16186,9 @@ rs6000_mangle_fundamental_type (tree type) struct attribute_spec.handler. */ static tree -rs6000_handle_longcall_attribute (tree *node, tree name, - tree args ATTRIBUTE_UNUSED, - int flags ATTRIBUTE_UNUSED, +rs6000_handle_longcall_attribute (tree *node, tree name, + tree args ATTRIBUTE_UNUSED, + int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) { if (TREE_CODE (*node) != FUNCTION_TYPE @@ -16250,7 +16254,7 @@ rs6000_longcall_ref (rtx call_ref) data section. */ static void -rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x, +rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x, unsigned HOST_WIDE_INT align) { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) @@ -16265,7 +16269,7 @@ rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x, the initial value of DECL requires link-time relocations. */ static void -rs6000_elf_select_section (tree decl, int reloc, +rs6000_elf_select_section (tree decl, int reloc, unsigned HOST_WIDE_INT align) { /* Pretend that we're always building for a shared library when @@ -16424,7 +16428,7 @@ static tree branch_island_list = 0; /* Remember to generate a branch island for far calls to the given function. */ -static void +static void add_compiler_branch_island (tree label_name, tree function_name, int line_number) { tree branch_island = build_tree_list (function_name, label_name); @@ -16481,21 +16485,21 @@ macho_branch_islands (void) strcat (tmp_buf, "_pic\n"); strcat (tmp_buf, label); strcat (tmp_buf, "_pic:\n\tmflr r11\n"); - + strcat (tmp_buf, "\taddis r11,r11,ha16("); strcat (tmp_buf, name_buf); strcat (tmp_buf, " - "); strcat (tmp_buf, label); strcat (tmp_buf, "_pic)\n"); - + strcat (tmp_buf, "\tmtlr r0\n"); - + strcat (tmp_buf, "\taddi r12,r11,lo16("); strcat (tmp_buf, name_buf); strcat (tmp_buf, " - "); strcat (tmp_buf, label); strcat (tmp_buf, "_pic)\n"); - + strcat (tmp_buf, "\tmtctr r12\n\tbctr\n"); } else @@ -16548,7 +16552,7 @@ get_prev_label (tree function_name) } /* INSN is either a function call or a millicode call. It may have an - unconditional jump in its delay slot. + unconditional jump in its delay slot. CALL_DEST is the routine we are calling. */ @@ -16561,7 +16565,7 @@ output_call (rtx insn, rtx *operands, int dest_operand_number, int cookie_operan { tree labelname; tree funname = get_identifier (XSTR (operands[dest_operand_number], 0)); - + if (no_previous_def (funname)) { int line_number = 0; @@ -16630,7 +16634,7 @@ machopic_output_stub (FILE *file, const char *symb, const char *stub) label++; local_label_0 = alloca (sizeof("\"L0000000000$spb\"")); sprintf (local_label_0, "\"L%011d$spb\"", label); - + fprintf (file, "\tmflr r0\n"); fprintf (file, "\tbcl 20,31,%s\n", local_label_0); fprintf (file, "%s:\n\tmflr r11\n", local_label_0); @@ -16654,7 +16658,7 @@ machopic_output_stub (FILE *file, const char *symb, const char *stub) fprintf (file, "\tmtctr r12\n"); fprintf (file, "\tbctr\n"); } - + machopic_lazy_symbol_ptr_section (); fprintf (file, "%s:\n", lazy_ptr_name); fprintf (file, "\t.indirect_symbol %s\n", symbol_name); @@ -16670,7 +16674,7 @@ machopic_output_stub (FILE *file, const char *symb, const char *stub) #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x8000) < 0x10000) rtx -rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode, +rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) { rtx base, offset; @@ -16908,7 +16912,7 @@ rs6000_xcoff_asm_named_section (const char *name, unsigned int flags) } static void -rs6000_xcoff_select_section (tree decl, int reloc, +rs6000_xcoff_select_section (tree decl, int reloc, unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) { if (decl_readonly_section_1 (decl, reloc, 1)) @@ -16953,7 +16957,7 @@ rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED) toc entry. */ static void -rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x, +rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x, unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) @@ -17062,7 +17066,7 @@ rs6000_binds_local_p (tree decl) scanned. In either case, *TOTAL contains the cost result. */ static bool -rs6000_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, +rs6000_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, int *total) { enum machine_mode mode = GET_MODE (x); @@ -17382,7 +17386,7 @@ rs6000_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, CLASS1 to one of CLASS2. */ int -rs6000_register_move_cost (enum machine_mode mode, +rs6000_register_move_cost (enum machine_mode mode, enum reg_class from, enum reg_class to) { /* Moves from/to GENERAL_REGS. */ @@ -17411,7 +17415,7 @@ rs6000_register_move_cost (enum machine_mode mode, /* Everything else has to go through GENERAL_REGS. */ else - return (rs6000_register_move_cost (mode, GENERAL_REGS, to) + return (rs6000_register_move_cost (mode, GENERAL_REGS, to) + rs6000_register_move_cost (mode, from, GENERAL_REGS)); } @@ -17419,7 +17423,7 @@ rs6000_register_move_cost (enum machine_mode mode, or from memory. */ int -rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class, +rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class, int in ATTRIBUTE_UNUSED) { if (reg_classes_intersect_p (class, GENERAL_REGS)) @@ -17629,10 +17633,25 @@ rs6000_dbx_register_number (unsigned int regno) } /* target hook eh_return_filter_mode */ -static enum machine_mode +static enum machine_mode rs6000_eh_return_filter_mode (void) { return TARGET_32BIT ? SImode : word_mode; } +/* Target hook for vector_mode_supported_p. */ +static bool +rs6000_vector_mode_supported_p (enum machine_mode mode) +{ + + if (TARGET_SPE && SPE_VECTOR_MODE (mode)) + return true; + + else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode)) + return true; + + else + return false; +} + #include "gt-rs6000.h" |