diff options
| author | dje <dje@138bc75d-0d04-0410-961f-82ee72b054a4> | 2005-11-16 15:59:27 +0000 |
|---|---|---|
| committer | dje <dje@138bc75d-0d04-0410-961f-82ee72b054a4> | 2005-11-16 15:59:27 +0000 |
| commit | a9b1984c577e8a64b88260a8ba6129ce2e8e72ad (patch) | |
| tree | c17d43e8a7bb3ce4036e30bc924f210bb0efa6c0 /gcc/config/rs6000 | |
| parent | 11bb91b91ca4a67d3cb2a26161118ae626166f43 (diff) | |
| download | gcc-a9b1984c577e8a64b88260a8ba6129ce2e8e72ad.tar.gz | |
PR target/24772
* config/rs6000/predicates.md (vrsave_operation): SET_SRC is a VEC.
* config/rs6000/rs6000.md (btruncsf2, ceilsf2, floorsf2,
roundsf2): Remove "s" from mnemonic.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@107085 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/rs6000')
| -rw-r--r-- | gcc/config/rs6000/predicates.md | 5 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 10 |
2 files changed, 7 insertions, 8 deletions
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 4ce00b0674d..0ede69dcd1f 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -1038,10 +1038,9 @@ return 0; dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); - src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); + src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1)); - if (dest_regno != VRSAVE_REGNO - && src_regno != VRSAVE_REGNO) + if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO) return 0; for (i = 1; i < count; i++) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index ee9cc427524..935775aef3f 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -5332,7 +5332,7 @@ [(set (match_operand:SF 0 "gpc_reg_operand" "=f") (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))] "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS" - "frizs %0,%1" + "friz %0,%1" [(set_attr "type" "fp")]) (define_insn "ceildf2" @@ -5343,10 +5343,10 @@ [(set_attr "type" "fp")]) (define_insn "ceilsf2" - [(set (match_operand:SF 0 "gpc_reg_operand" "=f") + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))] "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS" - "frips %0,%1" + "frip %0,%1" [(set_attr "type" "fp")]) (define_insn "floordf2" @@ -5360,7 +5360,7 @@ [(set (match_operand:SF 0 "gpc_reg_operand" "=f") (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))] "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS" - "frims %0,%1" + "frim %0,%1" [(set_attr "type" "fp")]) (define_insn "rounddf2" @@ -5374,7 +5374,7 @@ [(set (match_operand:SF 0 "gpc_reg_operand" "=f") (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))] "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS" - "frins %0,%1" + "frin %0,%1" [(set_attr "type" "fp")]) ; An UNSPEC is used so we don't have to support SImode in FP registers. |