* rx/rx.h (TARGET_CPU_CPP_BUILTINS): Add macros for RX100, RX200,

	and RX600.
	* rx/rx.opt: Add macro for rx100 with string rx100 and value
	RX100.
	* rx/rx-opts.h (rx_cpu_types): Add new cpu type rx100.
	* rx/t-rx: Add rx100 under multi library matches option for nofpu
	option.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@199417 138bc75d-0d04-0410-961f-82ee72b054a4

6 files changed, 87 insertions, 11 deletions

diff --git a/gcc/config/rx/rx-opts.h b/gcc/config/rx/rx-opts.h
index f00de76a901..4d5455e8d8d 100644
--- a/gcc/config/rx/rx-opts.h
+++ b/gcc/config/rx/rx-opts.h
@@ -24,7 +24,8 @@ enum rx_cpu_types
 {
   RX600,
   RX610,
-  RX200
+  RX200,
+  RX100
 };
 
 #endif
diff --git a/gcc/config/rx/rx.c b/gcc/config/rx/rx.c
index 15d5359ea1d..d781bb73d28 100644
--- a/gcc/config/rx/rx.c
+++ b/gcc/config/rx/rx.c
@@ -975,6 +975,8 @@ rx_gen_move_template (rtx * operands, bool is_movu)
 	   loading an immediate into a register.  */
 	extension = ".W";
       break;
+    case DFmode:
+    case DImode:
     case SFmode:
     case SImode:
       extension = ".L";
@@ -988,19 +990,44 @@ rx_gen_move_template (rtx * operands, bool is_movu)
     }
 
   if (MEM_P (src) && rx_pid_data_operand (XEXP (src, 0)) == PID_UNENCODED)
-    src_template = "(%A1-__pid_base)[%P1]";
+    {
+      gcc_assert (GET_MODE (src) != DImode);
+      gcc_assert (GET_MODE (src) != DFmode);
+      
+      src_template = "(%A1 - __pid_base)[%P1]";
+    }
   else if (MEM_P (src) && rx_small_data_operand (XEXP (src, 0)))
-    src_template = "%%gp(%A1)[%G1]";
+    {
+      gcc_assert (GET_MODE (src) != DImode);
+      gcc_assert (GET_MODE (src) != DFmode);
+      
+      src_template = "%%gp(%A1)[%G1]";
+    }
   else
     src_template = "%1";
 
   if (MEM_P (dest) && rx_small_data_operand (XEXP (dest, 0)))
-    dst_template = "%%gp(%A0)[%G0]";
+    {
+      gcc_assert (GET_MODE (dest) != DImode);
+      gcc_assert (GET_MODE (dest) != DFmode);
+      
+      dst_template = "%%gp(%A0)[%G0]";
+    }
   else
     dst_template = "%0";
 
-  sprintf (out_template, "%s%s\t%s, %s", is_movu ? "movu" : "mov",
-	   extension, src_template, dst_template);
+  if (GET_MODE (dest) == DImode || GET_MODE (dest) == DFmode)
+    {
+      gcc_assert (! is_movu);
+
+      if (REG_P (src) && REG_P (dest) && (REGNO (dest) == REGNO (src) + 1))
+	sprintf (out_template, "mov.L\t%H1, %H0 | mov.L\t%1, %0");
+      else
+	sprintf (out_template, "mov.L\t%1, %0 | mov.L\t%H1, %H0");
+    }
+  else
+    sprintf (out_template, "%s%s\t%s, %s", is_movu ? "movu" : "mov",
+	     extension, src_template, dst_template);
   return out_template;
 }
 
@@ -3240,6 +3267,12 @@ rx_ok_to_inline (tree caller, tree callee)
     || lookup_attribute ("gnu_inline", DECL_ATTRIBUTES (callee)) != NULL_TREE;
 }
 
+static bool
+rx_enable_lra (void)
+{
+  return TARGET_ENABLE_LRA || 1;
+}
+
 
 #undef  TARGET_NARROW_VOLATILE_BITFIELD
 #define TARGET_NARROW_VOLATILE_BITFIELD		rx_narrow_volatile_bitfield
@@ -3391,6 +3424,9 @@ rx_ok_to_inline (tree caller, tree callee)
 #undef  TARGET_WARN_FUNC_RETURN
 #define TARGET_WARN_FUNC_RETURN 		rx_warn_func_return
 
+#undef  TARGET_LRA_P
+#define TARGET_LRA_P 				rx_enable_lra
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 #include "gt-rx.h"
diff --git a/gcc/config/rx/rx.h b/gcc/config/rx/rx.h
index 092fd7659a2..72aee2fe214 100644
--- a/gcc/config/rx/rx.h
+++ b/gcc/config/rx/rx.h
@@ -29,9 +29,22 @@
           builtin_define ("__RX610__");		\
           builtin_assert ("machine=RX610");	\
 	}					\
-     else					\
-        builtin_assert ("machine=RX600");	\
-      						\
+      else if (rx_cpu_type == RX100)		\
+	{					\
+          builtin_define ("__RX100__");		\
+          builtin_assert ("machine=RX100");	\
+	}					\
+      else if (rx_cpu_type == RX200)		\
+	{					\
+          builtin_define ("__RX200__");		\
+          builtin_assert ("machine=RX200");	\
+        }					\
+      else if (rx_cpu_type == RX600)		\
+        {					\
+          builtin_define ("__RX600__");		\
+          builtin_assert ("machine=RX600");	\
+        }					\
+						\
       if (TARGET_BIG_ENDIAN_DATA)		\
 	builtin_define ("__RX_BIG_ENDIAN__");	\
       else					\
@@ -60,6 +73,7 @@
 #undef  CC1_SPEC
 #define CC1_SPEC "\
   %{mas100-syntax:%{gdwarf*:%e-mas100-syntax is incompatible with -gdwarf}} \
+  %{mcpu=rx100:%{fpu:%erx100 cpu does not have FPU hardware}} \
   %{mcpu=rx200:%{fpu:%erx200 cpu does not have FPU hardware}}"
 
 #undef  STARTFILE_SPEC
diff --git a/gcc/config/rx/rx.md b/gcc/config/rx/rx.md
index 3a95567a43f..692b7d220a3 100644
--- a/gcc/config/rx/rx.md
+++ b/gcc/config/rx/rx.md
@@ -30,7 +30,7 @@
 ;; then all operations on doubles have to be handled by
 ;; library functions.
 (define_mode_iterator register_modes
-  [(SF "ALLOW_RX_FPU_INSNS") (SI "") (HI "") (QI "")])
+  [(SF "") (SI "") (HI "") (QI "")])
 
 (define_constants
   [
@@ -2621,3 +2621,21 @@
   ""
   ""
 )
+
+(define_insn "movdi"
+  [(set:DI (match_operand:DI 0 "nonimmediate_operand" "=rm")
+	   (match_operand:DI 1 "general_operand"      "rmi"))]
+  "TARGET_ENABLE_LRA || 1"
+  { return rx_gen_move_template (operands, false); }
+  [(set_attr "length" "16")
+   (set_attr "timings" "22")]
+)
+
+(define_insn "movdf"
+  [(set:DF (match_operand:DF 0 "nonimmediate_operand" "=rm")
+	   (match_operand:DF 1 "general_operand"      "rmi"))]
+  "TARGET_ENABLE_LRA || 1"
+  { return rx_gen_move_template (operands, false); }
+  [(set_attr "length" "16")
+   (set_attr "timings" "22")]
+)
diff --git a/gcc/config/rx/rx.opt b/gcc/config/rx/rx.opt
index 09d93c3e5f1..12312cfef6b 100644
--- a/gcc/config/rx/rx.opt
+++ b/gcc/config/rx/rx.opt
@@ -61,6 +61,9 @@ Enum(rx_cpu_types) String(rx200) Value(RX200)
 EnumValue
 Enum(rx_cpu_types) String(rx600) Value(RX600)
 
+EnumValue
+Enum(rx_cpu_types) String(rx100) Value(RX100)
+
 ;---------------------------------------------------
 
 mbig-endian-data
@@ -132,3 +135,7 @@ Enable the use of the old, broken, ABI where all stacked function arguments are
 mrx-abi
 Target RejectNegative Report InverseMask(GCC_ABI)
 Enable the use the standard RX ABI where all stacked function arguments are naturally aligned.  This is the default.
+
+mlra
+Target Report Mask(ENABLE_LRA)
+Enable the use of the LRA register allocator.
diff --git a/gcc/config/rx/t-rx b/gcc/config/rx/t-rx
index 97079859240..41a3d3a98dc 100644
--- a/gcc/config/rx/t-rx
+++ b/gcc/config/rx/t-rx
@@ -28,7 +28,7 @@ MULTILIB_DIRNAMES   =  64-bit-double  no-fpu-libs   big-endian-data   pid
 # MULTILIB_OPTIONS    += mgcc-abi
 # MULTILIB_DIRNAMES   +=  gcc-abi
 
-MULTILIB_MATCHES    = nofpu=mnofpu  nofpu=mcpu?rx200
+MULTILIB_MATCHES    = nofpu=mnofpu  nofpu=mcpu?rx200  nofpu=mcpu?rx100
 
 MULTILIB_EXCEPTIONS =
 MULTILIB_EXTRA_OPTS =