2003-10-10 Eric Christopher <echristo@redhat.com>

        * lcm.c (optimize_mode_switching): Change NORMAL_MODE
        to MODE_ENTRY and MODE_EXIT. Add MODE_AFTER for insns
        that set mode.
        * config/sh/sh.h (MODE_ENTRY): New macro.
        (MODE_EXIT): Ditto.
        (MODE_AFTER): Ditto.
        * config/sh/sh.md: Change for MODE_AFTER. Add
        fp_set attribute.
        * doc/tm.texi: Document MODE_AFTER, MODE_ENTRY, and MODE_EXIT.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@72315 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 54 insertions, 39 deletions

diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
index adbd4b8e25a..bad8c66edc9 100644
--- a/gcc/config/sh/sh.md
+++ b/gcc/config/sh/sh.md
@@ -152,7 +152,7 @@
   (UNSPECV_CONST8	6)
   (UNSPECV_WINDOW_END	10)
   (UNSPECV_CONST_END	11)
-])  
+])
 
 ;; -------------------------------------------------------------------------
 ;; Attributes
@@ -218,7 +218,7 @@
 ;; ftrc_s	fix_truncsfsi2_i4
 ;; dfdiv	double precision floating point divide (or square root)
 ;; cwb		ic_invalidate_line_i
-;; tls_load     load TLS related address 
+;; tls_load     load TLS related address
 ;; arith_media	SHmedia arithmetic, logical, and shift instructions
 ;; cbranch_media SHmedia conditional branch instructions
 ;; cmp_media	SHmedia compare instructions
@@ -280,6 +280,14 @@
 
 (define_attr "fp_mode" "single,double,none" (const_string "none"))
 
+;; Indicate if the fpu mode is set by this instruction
+;; "unknown" must have the value as "none" in fp_mode, and means
+;; that the instruction/abi has left the processor in an unknown
+;; state.
+;; "none" means that nothing has changed and no mode is set.
+;; This attribute is only used for the Renesas ABI.
+(define_attr "fp_set" "single,double,unknown,none" (const_string "none"))
+
 ; If a conditional branch destination is within -252..258 bytes away
 ; from the instruction it can be 2 bytes long.  Something in the
 ; range -4090..4100 bytes can be 6 bytes long.  All other conditional
@@ -5065,7 +5073,7 @@
 ;; delay slot scheduling from the target.
 (define_insn "indirect_jump_scratch"
   [(set (match_operand:SI 0 "register_operand" "=r")
-	(unspec:SI [(match_operand 1 "const_int_operand" "")] UNSPEC_BBR)) 
+	(unspec:SI [(match_operand 1 "const_int_operand" "")] UNSPEC_BBR))
    (set (pc) (unspec [(const_int 0)] UNSPEC_BBR))]
   "TARGET_SH1"
   ""
@@ -5562,7 +5570,8 @@
    (set (attr "fp_mode")
 	(if_then_else (eq_attr "fpu_single" "yes")
 		      (const_string "single") (const_string "double")))
-   (set_attr "needs_delay_slot" "yes")])
+   (set_attr "needs_delay_slot" "yes")
+   (set_attr "fp_set" "unknown")])
 
 ;; This is a pc-rel call, using bsrf, for use with PIC.
 
@@ -5579,7 +5588,8 @@
    (set (attr "fp_mode")
 	(if_then_else (eq_attr "fpu_single" "yes")
 		      (const_string "single") (const_string "double")))
-   (set_attr "needs_delay_slot" "yes")])
+   (set_attr "needs_delay_slot" "yes")
+   (set_attr "fp_set" "unknown")])
 
 (define_insn_and_split "call_pcrel"
   [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
@@ -5607,7 +5617,8 @@
    (set (attr "fp_mode")
 	(if_then_else (eq_attr "fpu_single" "yes")
 		      (const_string "single") (const_string "double")))
-   (set_attr "needs_delay_slot" "yes")])
+   (set_attr "needs_delay_slot" "yes")
+   (set_attr "fp_set" "unknown")])
 
 (define_insn "call_compact"
   [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
@@ -5662,7 +5673,8 @@
    (set (attr "fp_mode")
 	(if_then_else (eq_attr "fpu_single" "yes")
 		      (const_string "single") (const_string "double")))
-   (set_attr "needs_delay_slot" "yes")])
+   (set_attr "needs_delay_slot" "yes")
+   (set_attr "fp_set" "unknown")])
 
 (define_insn "call_valuei_pcrel"
   [(set (match_operand 0 "" "=rf")
@@ -5678,7 +5690,8 @@
    (set (attr "fp_mode")
 	(if_then_else (eq_attr "fpu_single" "yes")
 		      (const_string "single") (const_string "double")))
-   (set_attr "needs_delay_slot" "yes")])
+   (set_attr "needs_delay_slot" "yes")
+   (set_attr "fp_set" "unknown")])
 
 (define_insn_and_split "call_value_pcrel"
   [(set (match_operand 0 "" "=rf")
@@ -5708,7 +5721,8 @@
    (set (attr "fp_mode")
 	(if_then_else (eq_attr "fpu_single" "yes")
 		      (const_string "single") (const_string "double")))
-   (set_attr "needs_delay_slot" "yes")])
+   (set_attr "needs_delay_slot" "yes")
+   (set_attr "fp_set" "unknown")])
 
 (define_insn "call_value_compact"
   [(set (match_operand 0 "" "=rf")
@@ -8169,7 +8183,8 @@ mov.l\\t1f,r0\\n\\
   [(set (reg:PSI FPSCR_REG)
 	(xor:PSI (reg:PSI FPSCR_REG) (const_int 1048576)))]
   "TARGET_SH4"
-  "fschg")
+  "fschg"
+  [(set_attr "fp_set" "unknown")])
 
 (define_expand "addsf3"
   [(set (match_operand:SF 0 "arith_reg_operand" "")
@@ -10359,7 +10374,7 @@ mov.l\\t1f,r0\\n\\
 			(const_int 4294967295))
 		(ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
                            (const_int 32))))]
-				
+
   "TARGET_SHMEDIA"
   "mshflo.l	%N1, %N2, %0"
   [(set_attr "type" "arith_media")])
@@ -10370,7 +10385,7 @@ mov.l\\t1f,r0\\n\\
                            (const_int 32))
 		(and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
 			(const_int 4294967295))))]
-				
+
   "TARGET_SHMEDIA"
   "mshflo.l	%N2, %N1, %0"
   [(set_attr "type" "arith_media")])
@@ -10404,7 +10419,7 @@ mov.l\\t1f,r0\\n\\
 				 "rZ"))
 		(ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
                            (const_int 32))))]
-				
+
   "TARGET_SHMEDIA"
   "mshflo.l	%N1, %N2, %0"
   [(set_attr "type" "arith_media")])
@@ -10414,7 +10429,7 @@ mov.l\\t1f,r0\\n\\
 ;;	(vec_concat:V2SF (match_operand:SF 1 "register_operand" "rZ,0,f")
 	(vec_concat:V2SF (match_operand:SF 1 "register_operand" "rZ,f,f")
 			 (match_operand:SF 2 "register_operand" "rZ,f,f")))]
-				
+
   "TARGET_SHMEDIA"
   "@
 	mshflo.l	%N1, %N2, %0
@@ -10436,7 +10451,7 @@ mov.l\\t1f,r0\\n\\
 	(ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
                            (const_int 32))
 		(zero_extend:DI (match_operand:SI 2 "extend_reg_or_0_operand" "rZ"))))]
-				
+
   "TARGET_SHMEDIA"
   "mshflo.l	%N2, %N1, %0"
   [(set_attr "type" "arith_media")])
@@ -10675,16 +10690,16 @@ mov.l\\t1f,r0\\n\\
   [(set_attr "type" "arith_media")])
 
 ;; The following description  models the
-;; SH4 pipeline using the DFA based scheduler. 
-;; The DFA based description is better way to model 
+;; SH4 pipeline using the DFA based scheduler.
+;; The DFA based description is better way to model
 ;; a superscalar pipeline as compared to function unit
-;; reservation model.   
-;; 1. The function unit based model is oriented to describe at most one 
-;;    unit reservation by each insn. It is difficult to model unit reservations in multiple 
+;; reservation model.
+;; 1. The function unit based model is oriented to describe at most one
+;;    unit reservation by each insn. It is difficult to model unit reservations in multiple
 ;;    pipeline units by same insn. This can be done using DFA based description.
 ;; 2. The execution performance of DFA based scheduler does not depend on processor complexity.
-;; 3. Writing all unit reservations for an instruction class is more natural description 
-;;    of the pipeline and makes interface of the hazard recognizer simpler than the 
+;; 3. Writing all unit reservations for an instruction class is more natural description
+;;    of the pipeline and makes interface of the hazard recognizer simpler than the
 ;;    old function unit based model.
 ;; 4. The DFA model is richer and is a part of greater overall framework of RCSP.
 
@@ -10695,7 +10710,7 @@ mov.l\\t1f,r0\\n\\
 (define_automaton "inst_pipeline,fpu_pipe")
 
 ;; This unit is basically the decode unit of the processor.
-;; Since SH4 is a dual issue machine,it is as if there are two 
+;; Since SH4 is a dual issue machine,it is as if there are two
 ;; units so that any insn can be processed by either one
 ;; of the decoding unit.
 
@@ -10728,8 +10743,8 @@ mov.l\\t1f,r0\\n\\
 
 ;; The address calculator used for branch instructions.
 ;; This will be reserved after "issue" of branch instructions
-;; and this is to make sure that no two branch instructions 
-;; can be issued in parallel. 
+;; and this is to make sure that no two branch instructions
+;; can be issued in parallel.
 
 (define_cpu_unit "pcr_addrcalc" "inst_pipeline")
 
@@ -10751,14 +10766,14 @@ mov.l\\t1f,r0\\n\\
 
 (define_reservation "fpu" "F1+F2")
 
-;; This is to highlight the fact that f1 
+;; This is to highlight the fact that f1
 ;; cannot overlap with F1.
 
 (exclusion_set  "f1_1,f1_2" "F1")
 
 (define_insn_reservation "nil" 0 (eq_attr "type" "nil") "nothing")
 
-;; Although reg moves have a latency of zero 
+;; Although reg moves have a latency of zero
 ;; we need to highlight that they use D stage
 ;; for one cycle.
 
@@ -10806,7 +10821,7 @@ mov.l\\t1f,r0\\n\\
 ;; Latency: 	1
 ;; Issue Rate: 	1
 
-(define_insn_reservation "sh4_simple_arith" 1 
+(define_insn_reservation "sh4_simple_arith" 1
   (and (eq_attr "pipe_model" "sh4")
        (eq_attr "insn_class" "ex_group"))
   "issue,int")
@@ -10913,7 +10928,7 @@ mov.l\\t1f,r0\\n\\
 ;; Group:	CO
 ;; Latency: 	5
 ;; Issue Rate: 	5
-;; this instruction can be executed in any of the pipelines 
+;; this instruction can be executed in any of the pipelines
 ;; and blocks the pipeline for next 4 stages.
 
 (define_insn_reservation "sh4_return_from_exp" 5
@@ -10932,7 +10947,7 @@ mov.l\\t1f,r0\\n\\
   (and (eq_attr "pipe_model" "sh4")
        (eq_attr "type" "cwb"))
   "d_lock*2,(d_lock+memory)*3,issue+load_store+memory,memory*2")
-		
+
 ;; LDS to PR,JSR
 ;; Group:	CO
 ;; Latency: 	3
@@ -10944,7 +10959,7 @@ mov.l\\t1f,r0\\n\\
 ;; scheduling.  For the function call case, it's really best that we end with
 ;; something that models an rts.
 
-(define_insn_reservation "sh4_lds_to_pr" 3 
+(define_insn_reservation "sh4_lds_to_pr" 3
   (and (eq_attr "pipe_model" "sh4")
        (eq_attr "type" "prset") )
   "d_lock*2")
@@ -10957,17 +10972,17 @@ mov.l\\t1f,r0\\n\\
 ;; We could, of course, provide exact scheduling information for specific
 ;; sfuncs, if that should prove useful.
 
-(define_insn_reservation "sh4_call" 16 
+(define_insn_reservation "sh4_call" 16
   (and (eq_attr "pipe_model" "sh4")
        (eq_attr "type" "call,sfunc"))
   "d_lock*16")
 
-;; LDS.L to PR 
+;; LDS.L to PR
 ;; Group:	CO
 ;; Latency: 	3
 ;; Issue Rate: 	2
 ;; The SX unit is blocked for last 2 cycles.
- 
+
 (define_insn_reservation "ldsmem_to_pr"  3
   (and (eq_attr "pipe_model" "sh4")
        (eq_attr "type" "pload"))
@@ -10989,7 +11004,7 @@ mov.l\\t1f,r0\\n\\
 ;; Latency: 	2
 ;; Issue Rate: 	2
 
-(define_insn_reservation "sh4_prstore_mem" 2 
+(define_insn_reservation "sh4_prstore_mem" 2
   (and (eq_attr "pipe_model" "sh4")
        (eq_attr "type" "pstore"))
   "d_lock*2,nothing,memory")
@@ -10998,7 +11013,7 @@ mov.l\\t1f,r0\\n\\
 ;; Group:	CO
 ;; Latency: 	4
 ;; Issue Rate: 	1
-;; F1 is blocked for last three cycles. 
+;; F1 is blocked for last three cycles.
 
 (define_insn_reservation "fpscr_load" 4
   (and (eq_attr "pipe_model" "sh4")
@@ -11079,7 +11094,7 @@ mov.l\\t1f,r0\\n\\
        (eq_attr "type" "dfp_conv"))
   "issue,F01,F1+F2,F2")
 
-;; Double-precision floating-point (FADD,FMUL,FSUB) 
+;; Double-precision floating-point (FADD,FMUL,FSUB)
 ;; Group:	FE
 ;; Latency: 	(7,8)/9
 ;; Issue Rate: 	1
@@ -11089,12 +11104,12 @@ mov.l\\t1f,r0\\n\\
        (eq_attr "type" "dfp_arith"))
   "issue,F01,F1+F2,fpu*4,F2")
 
-;; Double-precision FCMP (FCMP/EQ,FCMP/GT) 
+;; Double-precision FCMP (FCMP/EQ,FCMP/GT)
 ;; Group:	CO
 ;; Latency: 	3/5
 ;; Issue Rate: 	2
 
-(define_insn_reservation "fp_double_cmp" 3 
+(define_insn_reservation "fp_double_cmp" 3
   (and (eq_attr "pipe_model" "sh4")
        (eq_attr "type" "dfp_cmp"))
   "d_lock,(d_lock+F01),F1+F2,F2")