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authorhp <hp@138bc75d-0d04-0410-961f-82ee72b054a4>2007-08-22 20:32:18 +0000
committerhp <hp@138bc75d-0d04-0410-961f-82ee72b054a4>2007-08-22 20:32:18 +0000
commitfd781bb230ca112b33c622e2661d7a3c0cc114e0 (patch)
tree7fbbcdd05392c2049de5126469da5fdfd30bc229 /gcc/config/sparc/sparc.md
parent3a1b426e9cf94138914295b629314b35c1a38c33 (diff)
downloadgcc-fd781bb230ca112b33c622e2661d7a3c0cc114e0.tar.gz
* doc/md.texi (Iterators): Renamed from Macros. All contents
changed to reflect rename of respectively define_code_macro and define_mode_macro to define_code_iterator and define_mode_iterator. (Mode Iterators, Code Iterators): Similar. * read-rtl.c (struct iterator_group, struct iterator_traverse_data) (uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p) (apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse) (initialize_iterators, find_iterator, check_code_iterator) (map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping) (read_mapping, read_rtx_1): Similar. * config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md, config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md, config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md, config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md, config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md, config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md, config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md, config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md, config/rs6000/sync.md, config/rs6000/rs6000.md, config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md, config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md, config/vax/vax.md, config/bfin/bfin.md: Similar. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@127715 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/sparc/sparc.md')
-rw-r--r--gcc/config/sparc/sparc.md10
1 files changed, 5 insertions, 5 deletions
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 05370fcfe14..329dd1a7ab1 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -1701,7 +1701,7 @@
(set_attr "branch_type" "reg")])
-(define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
+(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
;; Load in operand 0 the (absolute) address of operand 1, which is a symbolic
;; value subject to a PC-relative relocation. Operand 2 is a helper function
@@ -2340,7 +2340,7 @@
;; Floating point and vector move instructions
;; We don't define V1SI because SI should work just fine.
-(define_mode_macro V32 [SF V2HI V4QI])
+(define_mode_iterator V32 [SF V2HI V4QI])
;; Yes, you guessed it right, the former movsf expander.
(define_expand "mov<V32:mode>"
@@ -2476,7 +2476,7 @@
[(set (match_dup 0) (high:SF (match_dup 1)))
(set (match_dup 0) (lo_sum:SF (match_dup 0) (match_dup 1)))])
-(define_mode_macro V64 [DF V2SI V4HI V8QI])
+(define_mode_iterator V64 [DF V2SI V4HI V8QI])
;; Yes, you again guessed it right, the former movdf expander.
(define_expand "mov<V64:mode>"
@@ -5276,8 +5276,8 @@
;; We define DImode `and' so with DImode `not' we can get
;; DImode `andn'. Other combinations are possible.
-(define_mode_macro V64I [DI V2SI V4HI V8QI])
-(define_mode_macro V32I [SI V2HI V4QI])
+(define_mode_iterator V64I [DI V2SI V4HI V8QI])
+(define_mode_iterator V32I [SI V2HI V4QI])
(define_expand "and<V64I:mode>3"
[(set (match_operand:V64I 0 "register_operand" "")