2012-10-31 Basile Starynkevitch <basile@starynkevitch.net>

	MELT branch merged with trunk rev 193029 using svnmerge.py



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/melt-branch@193030 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 15 insertions, 7 deletions

diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 88e1ca7c4f6..bca0d8fa656 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3219,6 +3219,9 @@ when the Visual Instruction Set is available.
 @item h
 64-bit global or out register for the SPARC-V8+ architecture.
 
+@item C
+The constant all-ones, for floating-point.
+
 @item D
 A vector constant
 
@@ -3233,10 +3236,12 @@ Zero
 loaded with the @code{sethi} instruction)
 
 @item L
-A constant in the range supported by @code{movcc} instructions
+A constant in the range supported by @code{movcc} instructions (11-bit
+signed immediate)
 
 @item M
-A constant in the range supported by @code{movrcc} instructions
+A constant in the range supported by @code{movrcc} instructions (10-bit
+signed immediate)
 
 @item N
 Same as @samp{K}, except that it verifies that bits that are not in the
@@ -3252,6 +3257,9 @@ Floating-point zero
 @item H
 Signed 13-bit constant, sign-extended to 32 or 64 bits
 
+@item P
+The constant -1
+
 @item Q
 Floating-point constant whose integral representation can
 be moved into an integer register using a single sethi
@@ -3270,12 +3278,12 @@ instruction sequence
 @item T
 Memory address aligned to an 8-byte boundary
 
-@item U
-Even register
-
 @item W
 Memory address for @samp{e} constraint registers
 
+@item w
+Memory address with only a base register
+
 @item Y
 Vector zero
 
@@ -4475,8 +4483,8 @@ means of constraints requiring operands 1 and 0 to be the same location.
 @cindex @code{ior@var{m}3} instruction pattern
 @cindex @code{xor@var{m}3} instruction pattern
 @item @samp{ssadd@var{m}3}, @samp{usadd@var{m}3}
-@item @samp{sub@var{m}3}, @samp{sssub@var{m}3}, @samp{ussub@var{m}3}
-@item @samp{mul@var{m}3}, @samp{ssmul@var{m}3}, @samp{usmul@var{m}3}
+@itemx @samp{sub@var{m}3}, @samp{sssub@var{m}3}, @samp{ussub@var{m}3}
+@itemx @samp{mul@var{m}3}, @samp{ssmul@var{m}3}, @samp{usmul@var{m}3}
 @itemx @samp{div@var{m}3}, @samp{ssdiv@var{m}3}
 @itemx @samp{udiv@var{m}3}, @samp{usdiv@var{m}3}
 @itemx @samp{mod@var{m}3}, @samp{umod@var{m}3}