gcc/

    * Makefile.in (TEXI_GCC_FILES): Add arm-neon-intrinsics.texi.
    * config.gcc (arm*-*-*): Add arm_neon.h to extra headers.
    (with_fpu): Allow --with-fpu=neon.
    * config/arm/aof.h (ADDITIONAL_REGISTER_NAMES): Add Q0-Q15.
    * config/arm/aout.h (ADDITIONAL_REGISTER_NAMES): Add Q0-Q15.
    * config/arm/arm-modes.def (EI, OI, CI, XI): New modes.
    * config/arm/arm-protos.h (neon_immediate_valid_for_move)
    (neon_immediate_valid_for_logic, neon_output_logic_immediate)
    (neon_pairwise_reduce, neon_expand_vector_init, neon_reinterpret)
    (neon_emit_pair_result_insn, neon_disambiguate_copy)
    (neon_vector_mem_operand, neon_struct_mem_operand, output_move_quad)
    (output_move_neon): Add prototypes.
    * config/arm/arm.c (FL_NEON): New flag for NEON processor capability.
    (all_fpus): Add FPUTYPE_NEON.
    (fp_model_for_fpu): Add NEON field.
    (arm_return_in_memory): Return vectors <= 16 bytes in ARM registers.
    (arm_arg_partial_bytes): Allow NEON vectors to be passed partially
    in registers.
    (arm_legitimate_address_p): Don't support fancy addressing for NEON
    structure moves.
    (thumb2_legitimate_address_p): Likewise.
    (neon_valid_immediate): Recognize and prepare constants suitable for
    NEON instructions.
    (neon_immediate_valid_for_move): New function. Recognize and prepare
    immediates for NEON move instructions.
    (neon_immediate_valid_for_logic): New function. Recognize and
    prepare immediates for NEON logic instructions.
    (neon_output_logic_immediate): New function. Create asm string
    suitable for outputting immediate logic instructions.
    (neon_pairwise_reduce): New function. Implement reduction using
    pairwise operations.
    (neon_expand_vector_init): New function. Expand a (possibly
    non-constant) vector initialization.
    (neon_vector_mem_operand): New function. Memory operands supported
    for quad-word loads/stores to/from ARM or NEON registers. Don't
    allow base+offset addressing for core regs.
    (neon_struct_mem_operand): New function. Valid mems for NEON
    structure moves.
    (coproc_secondary_reload_class): Enable NEON registers to be loaded
    from neon_vector_mem_operand addresses without a secondary register.
    (add_minipool_forward_ref): Handle >8-byte minipool entries.
    (add_minipool_backward_ref): Likewise.
    (dump_minipool): Likewise.
    (push_minipool_fix): Likewise.
    (output_move_quad): New function. Output quad-word moves, loads and
    stores using ARM registers.
    (output_move_vfp): Add support for vectors in VFP (NEON) D
    registers.
    (output_move_neon): Output a NEON load/store to/from a quadword
    register.
    (arm_print_operand): Implement new codes:
    - 'c' for unadorned integers (without a # sign).
    - 'J', 'K' for reg+2/reg+3, reg+3/reg+2 in little/big-endian
    mode.
    - 'e', 'f' for the low and high D parts of a NEON Q register.
    - 'q' outputs a NEON Q register.
    - 'h' outputs ranges of D registers for VLDM/VSTM etc.
    - 'T' prints NEON opcode features from a coded bitmask.
    - 'F' is similar to T, but signed/unsigned codes both print as
    'i'.
    - 't' is similar to T, but 'u' is printed instead of 'p'.
    - 'O' prints 'r' if NEON instruction should perform rounding (as
    specified by bitmask), else prints nothing.
    - '#' is a punctuation character to stop operand numbers from
    running together with following digits in the assembler
    strings for instructions (when using mode attributes).
    (arm_assemble_integer): Handle extra NEON vector modes. Permute
    constant vectors in big-endian mode, where necessary.
    (arm_hard_regno_mode_ok): Allow vectors in VFP/NEON registers.
    Handle EI, OI, CI, XI modes.
    (ashlv4hi3, ashlv2si3, lshrv4hi3, lshrv2si3, ashrv4hi3)
    (ashrv2si3): Rename IWMMXT2_BUILTINs to...
    (ashlv4hi3_iwmmxt, ashlv2si3_iwmmxt, lshrv4hi3_iwmmxt)
    (lshrv2si3_iwmmxt, ashrv4hi3_iwmmxt, ashrv2si3_iwmmxt): New names.
    (neon_builtin_type_bits): Add enumeration, one bit for each vector
    type.
    (v8qi_UP, v4hi_UP, v2si_UP, v2sf_UP, di_UP, v16qi_UP, v8hi_UP)
    (v4si_UP, v4sf_UP, v2di_UP, ti_UP, ei_UP, oi_UP, UP): Define macros
    to turn v8qi, etc. into bits defined above.
    (neon_itype): New enumeration. Classifications of NEON builtins.
    (neon_builtin_datum): Define struct. Contains information about
    a single builtin (with multiple modes).
    (CF): Define helper macro for...
    (VAR1...VAR10): Define builtins with a type, name and 1-10 different
    modes.
    (neon_builtin_data): New array. Define information about builtins
    for use during initialization/expansion.
    (arm_init_neon_builtins): New function.
    (arm_init_builtins): Call arm_init_neon_builtins if TARGET_NEON is
    true.
    (neon_builtin_compare): New function.
    (locate_neon_builtin_icode): New function. Find an insn code for a
    builtin given a function code for that builtin. Also return type of
    builtin (NEON_BINOP, NEON_UNOP etc.).
    (builtin_arg): New enumeration. Types of arguments for builtins.
    (arm_expand_neon_args): New function. Expand a generic NEON builtin.
    Takes a variable argument list of builtin_arg types, terminated by
    NEON_ARG_STOP.
    (arm_expand_neon_builtin): New function. Expand a NEON builtin.
    (neon_reinterpret): New function. Expand NEON reinterpret intrinsic.
    (neon_emit_pair_result_insn): New function. Support returning pairs
    of vectors via a pointer.
    (neon_disambiguate_copy): New function. Set up operands for a
    multi-word copy such that registers do not get clobbered.
    (arm_expand_builtin): Call arm_expand_neon_builtin if fcode >=
    ARM_BUILTIN_NEON_BASE.
    (arm_file_start): Set float-abi attribute for NEON.
    (arm_vector_mode_supported_p): Enable NEON vector modes.
    (arm_mangle_map_entry): New.
    (arm_mangle_map): New.
    (arm_mangle_vector_type): New.
    * config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Define __ARM_NEON__
    when appropriate.
    (TARGET_NEON): New macro. Target supports NEON.
    (fputype): Add FPUTYPE_NEON.
    (UNITS_PER_SIMD_WORD): Define. Allow quad-word registers to be used
    for vectorization based on command-line arg.
    (NEON_REGNO_OK_FOR_NREGS): Define.
    (VALID_NEON_DREG_MODE, VALID_NEON_QREG_MODE)
    (VALID_NEON_STRUCT_MODE): Define.
    (PRINT_OPERAND_PUNCT_VALID_P): '#' is valid punctuation.
    (arm_builtins): Add ARM_BUILTIN_NEON_BASE.
    * config/arm/arm.md (VUNSPEC_POOL_16): Insert constant for unspec.
    (consttable_16): Add pattern for outputting 16-byte minipool
    entries.
    (movv2si, movv4hi, movv8qi): Remove blank expanders (redefined in
    vec-common.md).
    (vec-common.md, neon.md): Include md files.
    * config/arm/arm.opt (mvectorize-with-neon-quad): Add option.
    * config/arm/constraints.md (constraint "Dn", "Dl", "DL"): Define.
    (memory_constraint "Ut", "Un", "Us"): Define.
    * config/arm/iwmmxt.md (VMMX, VSHFT): New mode macros.
    (MMX_char): New mode attribute.
    (addv8qi3, addv4hi3, addv2si3): Remove. Replace with...
    (*add<mode>3_iwmmxt): New insn pattern.
    (subv8qi3, subv4hi3, subv2si3): Remove. Replace with...
    (*sub<mode>3_iwmmxt): New insn pattern.
    (mulv4hi3): Rename to...
    (*mulv4hi3_iwmmxt): This.
    (smaxv8qi3, smaxv4hi3, smaxv2si3, umaxv8qi3, umaxv4hi3)
    (umaxv2si3, sminv8qi3, sminv4hi3, sminv2si3, uminv8qi3)
    (uminv4hi3, uminv2si3): Remove. Replace with...
    (*smax<mode>3_iwmmxt, *umax<mode>3_iwmmxt, *smin<mode>3_iwmmxt)
    (*umin<mode>3_iwmmxt): These.
    (ashrv4hi3, ashrv2si3, ashrdi3_iwmmxt): Replace with...
    (ashr<mode>3_iwmmxt): This new pattern.
    (lshrv4hi3, lshrv2si3, lshrdi3_iwmmxt): Replace with...
    (lshr<mode>3_iwmmxt): This new pattern.
    (ashlv4hi3, ashlv2si3, ashldi3_iwmmxt): Replace with...
    (ashl<mode>3_iwmmxt): This new pattern.
    * config/arm/neon-docgen.ml: New file. Generate documentation for
    intrinsics.
    * config/arm/neon-gen.ml: New file. Generate arm_neon.h header.
    * config/arm/arm_neon.h: New (autogenerated).
    * config/arm/neon-testgen.ml: New file. Generate NEON tests
    automatically.
    * config/arm/neon.md: New file. Define NEON instructions.
    * config/arm/neon.ml: New file. Abstract description of NEON
    instructions, used to generate arm_neon.h header, documentation and tests.
    * config/arm/t-arm (MD_INCLUDES): Add vec-common.md, neon.md.
    * vec-common.md: New file. Shared parts for iWMMXt and NEON vector
    support.
    * doc/extend.texi (ARM Built-in Functions): Rename and remove
    extraneous comma.
    (ARM NEON Intrinsics): New subsection.
    * doc/arm-neon-intrinsics.texi: New (autogenerated).

    gcc/testsuite/
    * gcc.dg/vect/vect.exp: Check is-effective-target arm_neon_hw.
    * gcc.dg/vect/tree-vect.h: Check for NEON SIMD support.
    * lib/gcc-dg.exp (cleanup-saved-temps): Fix comment.
    * lib/target-supports.exp (check_effective_target_arm_neon_ok)
    (check_effective_target_arm_neon_hw): New.
    * gcc.target/arm/neon/neon.exp: New file.
    * gcc.target/arm/neon/polytypes.c: New file.
    * gcc.target/arm/neon/v*.c (1870 files): New (autogenerated).



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@126911 138bc75d-0d04-0410-961f-82ee72b054a4

2 files changed, 11306 insertions, 4 deletions

diff --git a/gcc/doc/arm-neon-intrinsics.texi b/gcc/doc/arm-neon-intrinsics.texi
new file mode 100644
index 00000000000..c35662c01e9
--- /dev/null
+++ b/gcc/doc/arm-neon-intrinsics.texi
@@ -0,0 +1,11293 @@
+@c Copyright (C) 2006 Free Software Foundation, Inc.
+@c This is part of the GCC manual.
+@c For copying conditions, see the file gcc.texi.
+
+@c This file is generated automatically using gcc/config/arm/neon-docgen.ml
+@c Please do not edit manually.
+@subsubsection Addition
+
+@itemize @bullet
+@item uint32x2_t vadd_u32 (uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vadd_u16 (uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vadd_u8 (uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vadd_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vadd_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vadd_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vadd_u64 (uint64x1_t, uint64x1_t)
+@*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vadd_s64 (int64x1_t, int64x1_t)
+@*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vadd_f32 (float32x2_t, float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vadd.f32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vaddq_u32 (uint32x4_t, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vaddq_u16 (uint16x8_t, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vaddq_u8 (uint8x16_t, uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vaddq_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vaddq_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vaddq_s8 (int8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vaddq_u64 (uint64x2_t, uint64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vaddq_s64 (int64x2_t, int64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vaddq_f32 (float32x4_t, float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vadd.f32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vaddl_u32 (uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vaddl.u32 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vaddl_u16 (uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vaddl.u16 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vaddl_u8 (uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vaddl.u8 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vaddl_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vaddl.s32 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vaddl_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vaddl.s16 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vaddl_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vaddl.s8 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vaddw_u32 (uint64x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vaddw.u32 @var{q0}, @var{q0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vaddw_u16 (uint32x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vaddw.u16 @var{q0}, @var{q0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vaddw_u8 (uint16x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vaddw.u8 @var{q0}, @var{q0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vaddw_s32 (int64x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vaddw.s32 @var{q0}, @var{q0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vaddw_s16 (int32x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vaddw.s16 @var{q0}, @var{q0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vaddw_s8 (int16x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vaddw.s8 @var{q0}, @var{q0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vhadd_u32 (uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vhadd.u32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vhadd_u16 (uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vhadd.u16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vhadd_u8 (uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vhadd.u8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vhadd_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vhadd.s32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vhadd_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vhadd.s16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vhadd_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vhadd.s8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vhaddq_u32 (uint32x4_t, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vhadd.u32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vhaddq_u16 (uint16x8_t, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vhadd.u16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vhaddq_u8 (uint8x16_t, uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vhadd.u8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vhaddq_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vhadd.s32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vhaddq_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vhadd.s16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vhaddq_s8 (int8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vhadd.s8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vrhadd_u32 (uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vrhadd.u32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vrhadd_u16 (uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vrhadd.u16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vrhadd_u8 (uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vrhadd.u8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vrhadd_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vrhadd.s32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vrhadd_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vrhadd.s16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vrhadd_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vrhadd.s8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vrhaddq_u32 (uint32x4_t, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vrhadd.u32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vrhaddq_u16 (uint16x8_t, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vrhadd.u16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vrhaddq_u8 (uint8x16_t, uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vrhadd.u8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vrhaddq_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vrhadd.s32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vrhaddq_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vrhadd.s16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vrhaddq_s8 (int8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vrhadd.s8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vqadd_u32 (uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vqadd.u32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vqadd_u16 (uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vqadd.u16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vqadd_u8 (uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vqadd.u8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vqadd_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vqadd.s32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vqadd_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vqadd.s16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vqadd_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vqadd.s8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vqadd_u64 (uint64x1_t, uint64x1_t)
+@*@emph{Form of expected instruction(s):} @code{vqadd.u64 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vqadd_s64 (int64x1_t, int64x1_t)
+@*@emph{Form of expected instruction(s):} @code{vqadd.s64 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vqaddq_u32 (uint32x4_t, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vqadd.u32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vqaddq_u16 (uint16x8_t, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vqadd.u16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vqaddq_u8 (uint8x16_t, uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vqadd.u8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vqaddq_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vqadd.s32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vqaddq_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vqadd.s16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vqaddq_s8 (int8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vqadd.s8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vqaddq_u64 (uint64x2_t, uint64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vqadd.u64 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vqaddq_s64 (int64x2_t, int64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vqadd.s64 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vaddhn_u64 (uint64x2_t, uint64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vaddhn.i64 @var{d0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vaddhn_u32 (uint32x4_t, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vaddhn.i32 @var{d0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vaddhn_u16 (uint16x8_t, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vaddhn.i16 @var{d0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vaddhn_s64 (int64x2_t, int64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vaddhn.i64 @var{d0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vaddhn_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vaddhn.i32 @var{d0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vaddhn_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vaddhn.i16 @var{d0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vraddhn_u64 (uint64x2_t, uint64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vraddhn.i64 @var{d0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vraddhn_u32 (uint32x4_t, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vraddhn.i32 @var{d0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vraddhn_u16 (uint16x8_t, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vraddhn.i16 @var{d0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vraddhn_s64 (int64x2_t, int64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vraddhn.i64 @var{d0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vraddhn_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vraddhn.i32 @var{d0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vraddhn_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vraddhn.i16 @var{d0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Multiplication
+
+@itemize @bullet
+@item uint32x2_t vmul_u32 (uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vmul_u16 (uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vmul_u8 (uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vmul_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vmul_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vmul_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vmul_f32 (float32x2_t, float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vmul_p8 (poly8x8_t, poly8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmul.p8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vmulq_u32 (uint32x4_t, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vmulq_u16 (uint16x8_t, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vmulq_u8 (uint8x16_t, uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vmulq_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vmulq_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vmulq_s8 (int8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vmulq_f32 (float32x4_t, float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x16_t vmulq_p8 (poly8x16_t, poly8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vmul.p8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vqdmulh_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vqdmulh_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vqdmulhq_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vqdmulhq_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vqrdmulh_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vqrdmulh_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vqrdmulhq_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vqrdmulhq_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vmull_u32 (uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vmull.u32 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vmull_u16 (uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmull.u16 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vmull_u8 (uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmull.u8 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vmull_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vmull.s32 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vmull_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmull.s16 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vmull_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmull.s8 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x8_t vmull_p8 (poly8x8_t, poly8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmull.p8 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vqdmull_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vqdmull.s32 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vqdmull_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vqdmull.s16 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+
+
+@subsubsection Multiply-accumulate
+
+@itemize @bullet
+@item uint32x2_t vmla_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vmla_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vmla_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vmla_s32 (int32x2_t, int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vmla_s16 (int16x4_t, int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vmla_s8 (int8x8_t, int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vmla_f32 (float32x2_t, float32x2_t, float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vmlaq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vmlaq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vmlaq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vmlaq_s32 (int32x4_t, int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vmlaq_s16 (int16x8_t, int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vmlaq_s8 (int8x16_t, int8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vmlaq_f32 (float32x4_t, float32x4_t, float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vmlal_u32 (uint64x2_t, uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vmlal.u32 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vmlal_u16 (uint32x4_t, uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmlal.u16 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vmlal_u8 (uint16x8_t, uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmlal.u8 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vmlal_s32 (int64x2_t, int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vmlal.s32 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vmlal_s16 (int32x4_t, int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmlal.s16 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vmlal_s8 (int16x8_t, int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmlal.s8 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vqdmlal_s32 (int64x2_t, int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vqdmlal.s32 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vqdmlal_s16 (int32x4_t, int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vqdmlal.s16 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+
+
+@subsubsection Multiply-subtract
+
+@itemize @bullet
+@item uint32x2_t vmls_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vmls_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vmls_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vmls_s32 (int32x2_t, int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vmls_s16 (int16x4_t, int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vmls_s8 (int8x8_t, int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vmls_f32 (float32x2_t, float32x2_t, float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vmlsq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vmlsq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vmlsq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vmlsq_s32 (int32x4_t, int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vmlsq_s16 (int16x8_t, int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vmlsq_s8 (int8x16_t, int8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vmlsq_f32 (float32x4_t, float32x4_t, float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vmlsl_u32 (uint64x2_t, uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vmlsl.u32 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vmlsl_u16 (uint32x4_t, uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmlsl.u16 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vmlsl_u8 (uint16x8_t, uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmlsl.u8 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vmlsl_s32 (int64x2_t, int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vmlsl.s32 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vmlsl_s16 (int32x4_t, int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmlsl.s16 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vmlsl_s8 (int16x8_t, int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmlsl.s8 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vqdmlsl_s32 (int64x2_t, int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vqdmlsl.s32 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vqdmlsl_s16 (int32x4_t, int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vqdmlsl.s16 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+
+
+@subsubsection Subtraction
+
+@itemize @bullet
+@item uint32x2_t vsub_u32 (uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vsub_u16 (uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vsub_u8 (uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vsub_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vsub_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vsub_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vsub_u64 (uint64x1_t, uint64x1_t)
+@*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vsub_s64 (int64x1_t, int64x1_t)
+@*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vsub_f32 (float32x2_t, float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vsub.f32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vsubq_u32 (uint32x4_t, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vsubq_u16 (uint16x8_t, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vsubq_u8 (uint8x16_t, uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vsubq_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vsubq_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vsubq_s8 (int8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vsubq_u64 (uint64x2_t, uint64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vsubq_s64 (int64x2_t, int64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vsubq_f32 (float32x4_t, float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vsub.f32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vsubl_u32 (uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vsubl.u32 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vsubl_u16 (uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vsubl.u16 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vsubl_u8 (uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vsubl.u8 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vsubl_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vsubl.s32 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vsubl_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vsubl.s16 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vsubl_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vsubl.s8 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vsubw_u32 (uint64x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vsubw.u32 @var{q0}, @var{q0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vsubw_u16 (uint32x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vsubw.u16 @var{q0}, @var{q0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vsubw_u8 (uint16x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vsubw.u8 @var{q0}, @var{q0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vsubw_s32 (int64x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vsubw.s32 @var{q0}, @var{q0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vsubw_s16 (int32x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vsubw.s16 @var{q0}, @var{q0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vsubw_s8 (int16x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vsubw.s8 @var{q0}, @var{q0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vhsub_u32 (uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vhsub.u32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vhsub_u16 (uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vhsub.u16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vhsub_u8 (uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vhsub.u8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vhsub_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vhsub.s32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vhsub_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vhsub.s16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vhsub_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vhsub.s8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vhsubq_u32 (uint32x4_t, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vhsub.u32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vhsubq_u16 (uint16x8_t, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vhsub.u16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vhsubq_u8 (uint8x16_t, uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vhsub.u8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vhsubq_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vhsub.s32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vhsubq_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vhsub.s16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vhsubq_s8 (int8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vhsub.s8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vqsub_u32 (uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vqsub.u32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vqsub_u16 (uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vqsub.u16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vqsub_u8 (uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vqsub.u8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vqsub_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vqsub.s32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vqsub_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vqsub.s16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vqsub_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vqsub.s8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vqsub_u64 (uint64x1_t, uint64x1_t)
+@*@emph{Form of expected instruction(s):} @code{vqsub.u64 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vqsub_s64 (int64x1_t, int64x1_t)
+@*@emph{Form of expected instruction(s):} @code{vqsub.s64 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vqsubq_u32 (uint32x4_t, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vqsub.u32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vqsubq_u16 (uint16x8_t, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vqsub.u16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vqsubq_u8 (uint8x16_t, uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vqsub.u8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vqsubq_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vqsub.s32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vqsubq_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vqsub.s16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vqsubq_s8 (int8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vqsub.s8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vqsubq_u64 (uint64x2_t, uint64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vqsub.u64 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vqsubq_s64 (int64x2_t, int64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vqsub.s64 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vsubhn_u64 (uint64x2_t, uint64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vsubhn_u32 (uint32x4_t, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vsubhn_u16 (uint16x8_t, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vsubhn_s64 (int64x2_t, int64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vsubhn_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vsubhn_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vrsubhn_u64 (uint64x2_t, uint64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vrsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vrsubhn_u32 (uint32x4_t, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vrsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vrsubhn_u16 (uint16x8_t, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vrsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vrsubhn_s64 (int64x2_t, int64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vrsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vrsubhn_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vrsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vrsubhn_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vrsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Comparison (equal-to)
+
+@itemize @bullet
+@item uint32x2_t vceq_u32 (uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vceq_u16 (uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vceq_u8 (uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vceq_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vceq_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vceq_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vceq_f32 (float32x2_t, float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vceq.f32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vceq_p8 (poly8x8_t, poly8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vceqq_u32 (uint32x4_t, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vceqq_u16 (uint16x8_t, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vceqq_u8 (uint8x16_t, uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vceqq_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vceqq_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vceqq_s8 (int8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vceqq_f32 (float32x4_t, float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vceq.f32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vceqq_p8 (poly8x16_t, poly8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Comparison (greater-than-or-equal-to)
+
+@itemize @bullet
+@item uint32x2_t vcge_u32 (uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vcge_u16 (uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vcge_u8 (uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vcge_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vcge_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vcge_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vcge_f32 (float32x2_t, float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vcgeq_u32 (uint32x4_t, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vcgeq_u16 (uint16x8_t, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vcgeq_u8 (uint8x16_t, uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vcgeq_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vcgeq_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vcgeq_s8 (int8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vcgeq_f32 (float32x4_t, float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Comparison (less-than-or-equal-to)
+
+@itemize @bullet
+@item uint32x2_t vcle_u32 (uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vcle_u16 (uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vcle_u8 (uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vcle_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vcle_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vcle_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vcle_f32 (float32x2_t, float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vcleq_u32 (uint32x4_t, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vcleq_u16 (uint16x8_t, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vcleq_u8 (uint8x16_t, uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vcleq_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vcleq_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vcleq_s8 (int8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vcleq_f32 (float32x4_t, float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Comparison (greater-than)
+
+@itemize @bullet
+@item uint32x2_t vcgt_u32 (uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vcgt_u16 (uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vcgt_u8 (uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vcgt_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vcgt_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vcgt_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vcgt_f32 (float32x2_t, float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vcgtq_u32 (uint32x4_t, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vcgtq_u16 (uint16x8_t, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vcgtq_u8 (uint8x16_t, uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vcgtq_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vcgtq_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vcgtq_s8 (int8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vcgtq_f32 (float32x4_t, float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Comparison (less-than)
+
+@itemize @bullet
+@item uint32x2_t vclt_u32 (uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vclt_u16 (uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vclt_u8 (uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vclt_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vclt_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vclt_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vclt_f32 (float32x2_t, float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vcltq_u32 (uint32x4_t, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vcltq_u16 (uint16x8_t, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vcltq_u8 (uint8x16_t, uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vcltq_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vcltq_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vcltq_s8 (int8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vcltq_f32 (float32x4_t, float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Comparison (absolute greater-than-or-equal-to)
+
+@itemize @bullet
+@item uint32x2_t vcage_f32 (float32x2_t, float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vcageq_f32 (float32x4_t, float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Comparison (absolute less-than-or-equal-to)
+
+@itemize @bullet
+@item uint32x2_t vcale_f32 (float32x2_t, float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vcaleq_f32 (float32x4_t, float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Comparison (absolute greater-than)
+
+@itemize @bullet
+@item uint32x2_t vcagt_f32 (float32x2_t, float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vcagtq_f32 (float32x4_t, float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Comparison (absolute less-than)
+
+@itemize @bullet
+@item uint32x2_t vcalt_f32 (float32x2_t, float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vcaltq_f32 (float32x4_t, float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Test bits
+
+@itemize @bullet
+@item uint32x2_t vtst_u32 (uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vtst.32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vtst_u16 (uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vtst.16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vtst_u8 (uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtst.8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vtst_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vtst.32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vtst_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vtst.16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vtst_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtst.8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vtst_p8 (poly8x8_t, poly8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtst.8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vtstq_u32 (uint32x4_t, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vtst.32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vtstq_u16 (uint16x8_t, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtst.16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vtstq_u8 (uint8x16_t, uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vtst.8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vtstq_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vtst.32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vtstq_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtst.16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vtstq_s8 (int8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vtst.8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vtstq_p8 (poly8x16_t, poly8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vtst.8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Absolute difference
+
+@itemize @bullet
+@item uint32x2_t vabd_u32 (uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vabd.u32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vabd_u16 (uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vabd.u16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vabd_u8 (uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vabd.u8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vabd_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vabd.s32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vabd_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vabd.s16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vabd_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vabd.s8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vabd_f32 (float32x2_t, float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vabd.f32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vabdq_u32 (uint32x4_t, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vabd.u32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vabdq_u16 (uint16x8_t, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vabd.u16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vabdq_u8 (uint8x16_t, uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vabd.u8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vabdq_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vabd.s32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vabdq_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vabd.s16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vabdq_s8 (int8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vabd.s8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vabdq_f32 (float32x4_t, float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vabd.f32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vabdl_u32 (uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vabdl.u32 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vabdl_u16 (uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vabdl.u16 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vabdl_u8 (uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vabdl.u8 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vabdl_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vabdl.s32 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vabdl_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vabdl.s16 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vabdl_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vabdl.s8 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+
+
+@subsubsection Absolute difference and accumulate
+
+@itemize @bullet
+@item uint32x2_t vaba_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vaba.u32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vaba_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vaba.u16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vaba_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vaba.u8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vaba_s32 (int32x2_t, int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vaba.s32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vaba_s16 (int16x4_t, int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vaba.s16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vaba_s8 (int8x8_t, int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vaba.s8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vabaq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vaba.u32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vabaq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vaba.u16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vabaq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vaba.u8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vabaq_s32 (int32x4_t, int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vaba.s32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vabaq_s16 (int16x8_t, int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vaba.s16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vabaq_s8 (int8x16_t, int8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vaba.s8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vabal_u32 (uint64x2_t, uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vabal.u32 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vabal_u16 (uint32x4_t, uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vabal.u16 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vabal_u8 (uint16x8_t, uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vabal.u8 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vabal_s32 (int64x2_t, int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vabal.s32 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vabal_s16 (int32x4_t, int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vabal.s16 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vabal_s8 (int16x8_t, int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vabal.s8 @var{q0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+
+
+@subsubsection Maximum
+
+@itemize @bullet
+@item uint32x2_t vmax_u32 (uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vmax.u32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vmax_u16 (uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmax.u16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vmax_u8 (uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmax.u8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vmax_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vmax.s32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vmax_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmax.s16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vmax_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmax.s8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vmax_f32 (float32x2_t, float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vmax.f32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vmaxq_u32 (uint32x4_t, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmax.u32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vmaxq_u16 (uint16x8_t, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmax.u16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vmaxq_u8 (uint8x16_t, uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vmax.u8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vmaxq_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmax.s32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vmaxq_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmax.s16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vmaxq_s8 (int8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vmax.s8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vmaxq_f32 (float32x4_t, float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmax.f32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Minimum
+
+@itemize @bullet
+@item uint32x2_t vmin_u32 (uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vmin.u32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vmin_u16 (uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmin.u16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vmin_u8 (uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmin.u8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vmin_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vmin.s32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vmin_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmin.s16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vmin_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmin.s8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vmin_f32 (float32x2_t, float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vmin.f32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vminq_u32 (uint32x4_t, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmin.u32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vminq_u16 (uint16x8_t, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmin.u16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vminq_u8 (uint8x16_t, uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vmin.u8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vminq_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmin.s32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vminq_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmin.s16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vminq_s8 (int8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vmin.s8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vminq_f32 (float32x4_t, float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmin.f32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Pairwise add
+
+@itemize @bullet
+@item uint32x2_t vpadd_u32 (uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vpadd.i32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vpadd_u16 (uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vpadd.i16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vpadd_u8 (uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vpadd.i8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vpadd_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vpadd.i32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vpadd_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vpadd.i16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vpadd_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vpadd.i8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vpadd_f32 (float32x2_t, float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vpadd.f32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vpaddl_u32 (uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vpaddl.u32 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vpaddl_u16 (uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vpaddl.u16 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vpaddl_u8 (uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vpaddl.u8 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vpaddl_s32 (int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vpaddl.s32 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vpaddl_s16 (int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vpaddl.s16 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vpaddl_s8 (int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vpaddl.s8 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vpaddlq_u32 (uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vpaddl.u32 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vpaddlq_u16 (uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vpaddl.u16 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vpaddlq_u8 (uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vpaddl.u8 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vpaddlq_s32 (int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vpaddl.s32 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vpaddlq_s16 (int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vpaddl.s16 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vpaddlq_s8 (int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vpaddl.s8 @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Pairwise add, single_opcode widen and accumulate
+
+@itemize @bullet
+@item uint64x1_t vpadal_u32 (uint64x1_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vpadal.u32 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vpadal_u16 (uint32x2_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vpadal.u16 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vpadal_u8 (uint16x4_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vpadal.u8 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vpadal_s32 (int64x1_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vpadal.s32 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vpadal_s16 (int32x2_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vpadal.s16 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vpadal_s8 (int16x4_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vpadal.s8 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vpadalq_u32 (uint64x2_t, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vpadal.u32 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vpadalq_u16 (uint32x4_t, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vpadal.u16 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vpadalq_u8 (uint16x8_t, uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vpadal.u8 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vpadalq_s32 (int64x2_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vpadal.s32 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vpadalq_s16 (int32x4_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vpadal.s16 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vpadalq_s8 (int16x8_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vpadal.s8 @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Folding maximum
+
+@itemize @bullet
+@item uint32x2_t vpmax_u32 (uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vpmax.u32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vpmax_u16 (uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vpmax.u16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vpmax_u8 (uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vpmax.u8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vpmax_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vpmax.s32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vpmax_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vpmax.s16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vpmax_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vpmax.s8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vpmax_f32 (float32x2_t, float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vpmax.f32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+
+
+@subsubsection Folding minimum
+
+@itemize @bullet
+@item uint32x2_t vpmin_u32 (uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vpmin.u32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vpmin_u16 (uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vpmin.u16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vpmin_u8 (uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vpmin.u8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vpmin_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vpmin.s32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vpmin_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vpmin.s16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vpmin_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vpmin.s8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vpmin_f32 (float32x2_t, float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vpmin.f32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+
+
+@subsubsection Reciprocal step
+
+@itemize @bullet
+@item float32x2_t vrecps_f32 (float32x2_t, float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vrecps.f32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vrecpsq_f32 (float32x4_t, float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vrecps.f32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vrsqrts_f32 (float32x2_t, float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vrsqrts.f32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vrsqrtsq_f32 (float32x4_t, float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vrsqrts.f32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Vector shift left
+
+@itemize @bullet
+@item uint32x2_t vshl_u32 (uint32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vshl.u32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vshl_u16 (uint16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vshl.u16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vshl_u8 (uint8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vshl.u8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vshl_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vshl.s32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vshl_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vshl.s16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vshl_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vshl.s8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vshl_u64 (uint64x1_t, int64x1_t)
+@*@emph{Form of expected instruction(s):} @code{vshl.u64 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vshl_s64 (int64x1_t, int64x1_t)
+@*@emph{Form of expected instruction(s):} @code{vshl.s64 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vshlq_u32 (uint32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vshl.u32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vshlq_u16 (uint16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vshl.u16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vshlq_u8 (uint8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vshl.u8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vshlq_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vshl.s32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vshlq_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vshl.s16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vshlq_s8 (int8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vshl.s8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vshlq_u64 (uint64x2_t, int64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vshl.u64 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vshlq_s64 (int64x2_t, int64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vshl.s64 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vrshl_u32 (uint32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vrshl.u32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vrshl_u16 (uint16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vrshl.u16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vrshl_u8 (uint8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vrshl.u8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vrshl_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vrshl.s32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vrshl_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vrshl.s16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vrshl_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vrshl.s8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vrshl_u64 (uint64x1_t, int64x1_t)
+@*@emph{Form of expected instruction(s):} @code{vrshl.u64 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vrshl_s64 (int64x1_t, int64x1_t)
+@*@emph{Form of expected instruction(s):} @code{vrshl.s64 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vrshlq_u32 (uint32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vrshl.u32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vrshlq_u16 (uint16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vrshl.u16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vrshlq_u8 (uint8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vrshl.u8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vrshlq_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vrshl.s32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vrshlq_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vrshl.s16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vrshlq_s8 (int8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vrshl.s8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vrshlq_u64 (uint64x2_t, int64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vrshl.u64 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vrshlq_s64 (int64x2_t, int64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vrshl.s64 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vqshl_u32 (uint32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vqshl_u16 (uint16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vqshl_u8 (uint8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vqshl_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vqshl_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vqshl_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vqshl_u64 (uint64x1_t, int64x1_t)
+@*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vqshl_s64 (int64x1_t, int64x1_t)
+@*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vqshlq_u32 (uint32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vqshlq_u16 (uint16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vqshlq_u8 (uint8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vqshlq_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vqshlq_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vqshlq_s8 (int8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vqshlq_u64 (uint64x2_t, int64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vqshlq_s64 (int64x2_t, int64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vqrshl_u32 (uint32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vqrshl.u32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vqrshl_u16 (uint16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vqrshl.u16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vqrshl_u8 (uint8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vqrshl.u8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vqrshl_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vqrshl.s32 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vqrshl_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vqrshl.s16 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vqrshl_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vqrshl.s8 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vqrshl_u64 (uint64x1_t, int64x1_t)
+@*@emph{Form of expected instruction(s):} @code{vqrshl.u64 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vqrshl_s64 (int64x1_t, int64x1_t)
+@*@emph{Form of expected instruction(s):} @code{vqrshl.s64 @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vqrshlq_u32 (uint32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vqrshl.u32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vqrshlq_u16 (uint16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vqrshl.u16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vqrshlq_u8 (uint8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vqrshl.u8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vqrshlq_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vqrshl.s32 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vqrshlq_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vqrshl.s16 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vqrshlq_s8 (int8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vqrshl.s8 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vqrshlq_u64 (uint64x2_t, int64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vqrshl.u64 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vqrshlq_s64 (int64x2_t, int64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vqrshl.s64 @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Vector shift left by constant
+
+@itemize @bullet
+@item uint32x2_t vshl_n_u32 (uint32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vshl_n_u16 (uint16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vshl_n_u8 (uint8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vshl_n_s32 (int32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vshl_n_s16 (int16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vshl_n_s8 (int8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vshl_n_u64 (uint64x1_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vshl_n_s64 (int64x1_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vshlq_n_u32 (uint32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vshlq_n_u16 (uint16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vshlq_n_u8 (uint8x16_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vshlq_n_s32 (int32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vshlq_n_s16 (int16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vshlq_n_s8 (int8x16_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vshlq_n_u64 (uint64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vshlq_n_s64 (int64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vqshl_n_u32 (uint32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vqshl_n_u16 (uint16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vqshl_n_u8 (uint8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vqshl_n_s32 (int32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vqshl_n_s16 (int16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vqshl_n_s8 (int8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vqshl_n_u64 (uint64x1_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vqshl_n_s64 (int64x1_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vqshlq_n_u32 (uint32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vqshlq_n_u16 (uint16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vqshlq_n_u8 (uint8x16_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vqshlq_n_s32 (int32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vqshlq_n_s16 (int16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vqshlq_n_s8 (int8x16_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vqshlq_n_u64 (uint64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vqshlq_n_s64 (int64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vqshlu_n_s64 (int64x1_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqshlu.s64 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vqshlu_n_s32 (int32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqshlu.s32 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vqshlu_n_s16 (int16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqshlu.s16 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vqshlu_n_s8 (int8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqshlu.s8 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vqshluq_n_s64 (int64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqshlu.s64 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vqshluq_n_s32 (int32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqshlu.s32 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vqshluq_n_s16 (int16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqshlu.s16 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vqshluq_n_s8 (int8x16_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqshlu.s8 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vshll_n_u32 (uint32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshll.u32 @var{q0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vshll_n_u16 (uint16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshll.u16 @var{q0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vshll_n_u8 (uint8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshll.u8 @var{q0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vshll_n_s32 (int32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshll.s32 @var{q0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vshll_n_s16 (int16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshll.s16 @var{q0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vshll_n_s8 (int8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshll.s8 @var{q0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+
+
+@subsubsection Vector shift right by constant
+
+@itemize @bullet
+@item uint32x2_t vshr_n_u32 (uint32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshr.u32 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vshr_n_u16 (uint16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshr.u16 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vshr_n_u8 (uint8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshr.u8 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vshr_n_s32 (int32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshr.s32 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vshr_n_s16 (int16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshr.s16 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vshr_n_s8 (int8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshr.s8 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vshr_n_u64 (uint64x1_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshr.u64 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vshr_n_s64 (int64x1_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshr.s64 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vshrq_n_u32 (uint32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshr.u32 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vshrq_n_u16 (uint16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshr.u16 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vshrq_n_u8 (uint8x16_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshr.u8 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vshrq_n_s32 (int32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshr.s32 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vshrq_n_s16 (int16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshr.s16 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vshrq_n_s8 (int8x16_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshr.s8 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vshrq_n_u64 (uint64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshr.u64 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vshrq_n_s64 (int64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshr.s64 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vrshr_n_u32 (uint32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrshr.u32 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vrshr_n_u16 (uint16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrshr.u16 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vrshr_n_u8 (uint8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrshr.u8 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vrshr_n_s32 (int32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrshr.s32 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vrshr_n_s16 (int16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrshr.s16 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vrshr_n_s8 (int8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrshr.s8 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vrshr_n_u64 (uint64x1_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrshr.u64 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vrshr_n_s64 (int64x1_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrshr.s64 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vrshrq_n_u32 (uint32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrshr.u32 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vrshrq_n_u16 (uint16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrshr.u16 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vrshrq_n_u8 (uint8x16_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrshr.u8 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vrshrq_n_s32 (int32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrshr.s32 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vrshrq_n_s16 (int16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrshr.s16 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vrshrq_n_s8 (int8x16_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrshr.s8 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vrshrq_n_u64 (uint64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrshr.u64 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vrshrq_n_s64 (int64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrshr.s64 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vshrn_n_u64 (uint64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshrn.i64 @var{d0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vshrn_n_u32 (uint32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshrn.i32 @var{d0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vshrn_n_u16 (uint16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshrn.i16 @var{d0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vshrn_n_s64 (int64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshrn.i64 @var{d0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vshrn_n_s32 (int32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshrn.i32 @var{d0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vshrn_n_s16 (int16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vshrn.i16 @var{d0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vrshrn_n_u64 (uint64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrshrn.i64 @var{d0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vrshrn_n_u32 (uint32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrshrn.i32 @var{d0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vrshrn_n_u16 (uint16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrshrn.i16 @var{d0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vrshrn_n_s64 (int64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrshrn.i64 @var{d0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vrshrn_n_s32 (int32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrshrn.i32 @var{d0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vrshrn_n_s16 (int16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrshrn.i16 @var{d0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vqshrn_n_u64 (uint64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqshrn.u64 @var{d0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vqshrn_n_u32 (uint32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqshrn.u32 @var{d0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vqshrn_n_u16 (uint16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqshrn.u16 @var{d0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vqshrn_n_s64 (int64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqshrn.s64 @var{d0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vqshrn_n_s32 (int32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqshrn.s32 @var{d0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vqshrn_n_s16 (int16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqshrn.s16 @var{d0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vqrshrn_n_u64 (uint64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqrshrn.u64 @var{d0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vqrshrn_n_u32 (uint32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqrshrn.u32 @var{d0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vqrshrn_n_u16 (uint16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqrshrn.u16 @var{d0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vqrshrn_n_s64 (int64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqrshrn.s64 @var{d0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vqrshrn_n_s32 (int32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqrshrn.s32 @var{d0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vqrshrn_n_s16 (int16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqrshrn.s16 @var{d0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vqshrun_n_s64 (int64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqshrun.s64 @var{d0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vqshrun_n_s32 (int32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqshrun.s32 @var{d0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vqshrun_n_s16 (int16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqshrun.s16 @var{d0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vqrshrun_n_s64 (int64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqrshrun.s64 @var{d0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vqrshrun_n_s32 (int32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqrshrun.s32 @var{d0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vqrshrun_n_s16 (int16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqrshrun.s16 @var{d0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+
+
+@subsubsection Vector shift right by constant and accumulate
+
+@itemize @bullet
+@item uint32x2_t vsra_n_u32 (uint32x2_t, uint32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsra.u32 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vsra_n_u16 (uint16x4_t, uint16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsra.u16 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vsra_n_u8 (uint8x8_t, uint8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsra.u8 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vsra_n_s32 (int32x2_t, int32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsra.s32 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vsra_n_s16 (int16x4_t, int16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsra.s16 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vsra_n_s8 (int8x8_t, int8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsra.s8 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vsra_n_u64 (uint64x1_t, uint64x1_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsra.u64 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vsra_n_s64 (int64x1_t, int64x1_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsra.s64 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vsraq_n_u32 (uint32x4_t, uint32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsra.u32 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vsraq_n_u16 (uint16x8_t, uint16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsra.u16 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vsraq_n_u8 (uint8x16_t, uint8x16_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsra.u8 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vsraq_n_s32 (int32x4_t, int32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsra.s32 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vsraq_n_s16 (int16x8_t, int16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsra.s16 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vsraq_n_s8 (int8x16_t, int8x16_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsra.s8 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vsraq_n_u64 (uint64x2_t, uint64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsra.u64 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vsraq_n_s64 (int64x2_t, int64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsra.s64 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vrsra_n_u32 (uint32x2_t, uint32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrsra.u32 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vrsra_n_u16 (uint16x4_t, uint16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrsra.u16 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vrsra_n_u8 (uint8x8_t, uint8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrsra.u8 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vrsra_n_s32 (int32x2_t, int32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrsra.s32 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vrsra_n_s16 (int16x4_t, int16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrsra.s16 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vrsra_n_s8 (int8x8_t, int8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrsra.s8 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vrsra_n_u64 (uint64x1_t, uint64x1_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrsra.u64 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vrsra_n_s64 (int64x1_t, int64x1_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrsra.s64 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vrsraq_n_u32 (uint32x4_t, uint32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrsra.u32 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vrsraq_n_u16 (uint16x8_t, uint16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrsra.u16 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vrsraq_n_u8 (uint8x16_t, uint8x16_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrsra.u8 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vrsraq_n_s32 (int32x4_t, int32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrsra.s32 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vrsraq_n_s16 (int16x8_t, int16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrsra.s16 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vrsraq_n_s8 (int8x16_t, int8x16_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrsra.s8 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vrsraq_n_u64 (uint64x2_t, uint64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrsra.u64 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vrsraq_n_s64 (int64x2_t, int64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vrsra.s64 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+
+
+@subsubsection Vector shift right and insert
+
+@itemize @bullet
+@item uint32x2_t vsri_n_u32 (uint32x2_t, uint32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsri.32 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vsri_n_u16 (uint16x4_t, uint16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsri.16 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vsri_n_u8 (uint8x8_t, uint8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsri.8 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vsri_n_s32 (int32x2_t, int32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsri.32 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vsri_n_s16 (int16x4_t, int16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsri.16 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vsri_n_s8 (int8x8_t, int8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsri.8 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vsri_n_u64 (uint64x1_t, uint64x1_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsri.64 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vsri_n_s64 (int64x1_t, int64x1_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsri.64 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4_t vsri_n_p16 (poly16x4_t, poly16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsri.16 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vsri_n_p8 (poly8x8_t, poly8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsri.8 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vsriq_n_u32 (uint32x4_t, uint32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsri.32 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vsriq_n_u16 (uint16x8_t, uint16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsri.16 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vsriq_n_u8 (uint8x16_t, uint8x16_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsri.8 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vsriq_n_s32 (int32x4_t, int32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsri.32 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vsriq_n_s16 (int16x8_t, int16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsri.16 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vsriq_n_s8 (int8x16_t, int8x16_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsri.8 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vsriq_n_u64 (uint64x2_t, uint64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsri.64 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vsriq_n_s64 (int64x2_t, int64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsri.64 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x8_t vsriq_n_p16 (poly16x8_t, poly16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsri.16 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x16_t vsriq_n_p8 (poly8x16_t, poly8x16_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsri.8 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+
+
+@subsubsection Vector shift left and insert
+
+@itemize @bullet
+@item uint32x2_t vsli_n_u32 (uint32x2_t, uint32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsli.32 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vsli_n_u16 (uint16x4_t, uint16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsli.16 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vsli_n_u8 (uint8x8_t, uint8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsli.8 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vsli_n_s32 (int32x2_t, int32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsli.32 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vsli_n_s16 (int16x4_t, int16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsli.16 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vsli_n_s8 (int8x8_t, int8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsli.8 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vsli_n_u64 (uint64x1_t, uint64x1_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsli.64 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vsli_n_s64 (int64x1_t, int64x1_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsli.64 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4_t vsli_n_p16 (poly16x4_t, poly16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsli.16 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vsli_n_p8 (poly8x8_t, poly8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsli.8 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vsliq_n_u32 (uint32x4_t, uint32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsli.32 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vsliq_n_u16 (uint16x8_t, uint16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsli.16 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vsliq_n_u8 (uint8x16_t, uint8x16_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsli.8 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vsliq_n_s32 (int32x4_t, int32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsli.32 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vsliq_n_s16 (int16x8_t, int16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsli.16 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vsliq_n_s8 (int8x16_t, int8x16_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsli.8 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vsliq_n_u64 (uint64x2_t, uint64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsli.64 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vsliq_n_s64 (int64x2_t, int64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsli.64 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x8_t vsliq_n_p16 (poly16x8_t, poly16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsli.16 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x16_t vsliq_n_p8 (poly8x16_t, poly8x16_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vsli.8 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+
+
+@subsubsection Absolute value
+
+@itemize @bullet
+@item float32x2_t vabs_f32 (float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vabs.f32 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vabs_s32 (int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vabs.s32 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vabs_s16 (int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vabs.s16 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vabs_s8 (int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vabs.s8 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vabsq_f32 (float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vabs.f32 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vabsq_s32 (int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vabs.s32 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vabsq_s16 (int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vabs.s16 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vabsq_s8 (int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vabs.s8 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vqabs_s32 (int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vqabs.s32 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vqabs_s16 (int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vqabs.s16 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vqabs_s8 (int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vqabs.s8 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vqabsq_s32 (int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vqabs.s32 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vqabsq_s16 (int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vqabs.s16 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vqabsq_s8 (int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vqabs.s8 @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Negation
+
+@itemize @bullet
+@item float32x2_t vneg_f32 (float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vneg.f32 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vneg_s32 (int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vneg.s32 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vneg_s16 (int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vneg.s16 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vneg_s8 (int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vneg.s8 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vnegq_f32 (float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vneg.f32 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vnegq_s32 (int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vneg.s32 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vnegq_s16 (int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vneg.s16 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vnegq_s8 (int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vneg.s8 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vqneg_s32 (int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vqneg.s32 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vqneg_s16 (int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vqneg.s16 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vqneg_s8 (int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vqneg.s8 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vqnegq_s32 (int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vqneg.s32 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vqnegq_s16 (int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vqneg.s16 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vqnegq_s8 (int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vqneg.s8 @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Bitwise not
+
+@itemize @bullet
+@item uint32x2_t vmvn_u32 (uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vmvn_u16 (uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vmvn_u8 (uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vmvn_s32 (int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vmvn_s16 (int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vmvn_s8 (int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vmvn_p8 (poly8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vmvnq_u32 (uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vmvnq_u16 (uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vmvnq_u8 (uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vmvnq_s32 (int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vmvnq_s16 (int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vmvnq_s8 (int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x16_t vmvnq_p8 (poly8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Count leading sign bits
+
+@itemize @bullet
+@item int32x2_t vcls_s32 (int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vcls.s32 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vcls_s16 (int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vcls.s16 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vcls_s8 (int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vcls.s8 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vclsq_s32 (int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vcls.s32 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vclsq_s16 (int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vcls.s16 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vclsq_s8 (int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vcls.s8 @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Count leading zeros
+
+@itemize @bullet
+@item uint32x2_t vclz_u32 (uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vclz_u16 (uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vclz_u8 (uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vclz_s32 (int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vclz_s16 (int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vclz_s8 (int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vclzq_u32 (uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vclzq_u16 (uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vclzq_u8 (uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vclzq_s32 (int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vclzq_s16 (int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vclzq_s8 (int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Count number of set bits
+
+@itemize @bullet
+@item uint8x8_t vcnt_u8 (uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vcnt_s8 (int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vcnt_p8 (poly8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vcntq_u8 (uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vcntq_s8 (int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x16_t vcntq_p8 (poly8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Reciprocal estimate
+
+@itemize @bullet
+@item float32x2_t vrecpe_f32 (float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vrecpe.f32 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vrecpe_u32 (uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vrecpe.u32 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vrecpeq_f32 (float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vrecpe.f32 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vrecpeq_u32 (uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vrecpe.u32 @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Reciprocal square-root estimate
+
+@itemize @bullet
+@item float32x2_t vrsqrte_f32 (float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vrsqrte.f32 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vrsqrte_u32 (uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vrsqrte.u32 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vrsqrteq_f32 (float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vrsqrte.f32 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vrsqrteq_u32 (uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vrsqrte.u32 @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Get lanes from a vector
+
+@itemize @bullet
+@item uint32_t vget_lane_u32 (uint32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.u32 @var{r0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16_t vget_lane_u16 (uint16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint8_t vget_lane_u8 (uint8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32_t vget_lane_s32 (int32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.s32 @var{r0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16_t vget_lane_s16 (int16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.s16 @var{r0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int8_t vget_lane_s8 (int8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.s8 @var{r0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item float32_t vget_lane_f32 (float32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.f32 @var{r0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly16_t vget_lane_p16 (poly16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly8_t vget_lane_p8 (poly8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint64_t vget_lane_u64 (uint64x1_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64_t vget_lane_s64 (int64x1_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32_t vgetq_lane_u32 (uint32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.u32 @var{r0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16_t vgetq_lane_u16 (uint16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint8_t vgetq_lane_u8 (uint8x16_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32_t vgetq_lane_s32 (int32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.s32 @var{r0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16_t vgetq_lane_s16 (int16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.s16 @var{r0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int8_t vgetq_lane_s8 (int8x16_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.s8 @var{r0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item float32_t vgetq_lane_f32 (float32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.f32 @var{r0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly16_t vgetq_lane_p16 (poly16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly8_t vgetq_lane_p8 (poly8x16_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint64_t vgetq_lane_u64 (uint64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64_t vgetq_lane_s64 (int64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}}
+@end itemize
+
+
+
+
+@subsubsection Set lanes in a vector
+
+@itemize @bullet
+@item uint32x2_t vset_lane_u32 (uint32_t, uint32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vset_lane_u16 (uint16_t, uint16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vset_lane_u8 (uint8_t, uint8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vset_lane_s32 (int32_t, int32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vset_lane_s16 (int16_t, int16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vset_lane_s8 (int8_t, int8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vset_lane_f32 (float32_t, float32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4_t vset_lane_p16 (poly16_t, poly16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vset_lane_p8 (poly8_t, poly8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vset_lane_u64 (uint64_t, uint64x1_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vset_lane_s64 (int64_t, int64x1_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vsetq_lane_u32 (uint32_t, uint32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vsetq_lane_u16 (uint16_t, uint16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vsetq_lane_u8 (uint8_t, uint8x16_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vsetq_lane_s32 (int32_t, int32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vsetq_lane_s16 (int16_t, int16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vsetq_lane_s8 (int8_t, int8x16_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vsetq_lane_f32 (float32_t, float32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x8_t vsetq_lane_p16 (poly16_t, poly16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x16_t vsetq_lane_p8 (poly8_t, poly8x16_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vsetq_lane_u64 (uint64_t, uint64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vsetq_lane_s64 (int64_t, int64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
+@end itemize
+
+
+
+
+@subsubsection Create vector from literal bit pattern
+
+@itemize @bullet
+@item uint32x2_t vcreate_u32 (uint64_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vcreate_u16 (uint64_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vcreate_u8 (uint64_t)
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vcreate_s32 (uint64_t)
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vcreate_s16 (uint64_t)
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vcreate_s8 (uint64_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vcreate_u64 (uint64_t)
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vcreate_s64 (uint64_t)
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vcreate_f32 (uint64_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4_t vcreate_p16 (uint64_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vcreate_p8 (uint64_t)
+@end itemize
+
+
+
+
+@subsubsection Set all lanes to the same value
+
+@itemize @bullet
+@item uint32x2_t vdup_n_u32 (uint32_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vdup_n_u16 (uint16_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vdup_n_u8 (uint8_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vdup_n_s32 (int32_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vdup_n_s16 (int16_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vdup_n_s8 (int8_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vdup_n_f32 (float32_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4_t vdup_n_p16 (poly16_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vdup_n_p8 (poly8_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vdup_n_u64 (uint64_t)
+@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vdup_n_s64 (int64_t)
+@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vdupq_n_u32 (uint32_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vdupq_n_u16 (uint16_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vdupq_n_u8 (uint8_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vdupq_n_s32 (int32_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vdupq_n_s16 (int16_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vdupq_n_s8 (int8_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vdupq_n_f32 (float32_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x8_t vdupq_n_p16 (poly16_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x16_t vdupq_n_p8 (poly8_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vdupq_n_u64 (uint64_t)
+@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vdupq_n_s64 (int64_t)
+@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vmov_n_u32 (uint32_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vmov_n_u16 (uint16_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vmov_n_u8 (uint8_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vmov_n_s32 (int32_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vmov_n_s16 (int16_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vmov_n_s8 (int8_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vmov_n_f32 (float32_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4_t vmov_n_p16 (poly16_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vmov_n_p8 (poly8_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vmov_n_u64 (uint64_t)
+@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vmov_n_s64 (int64_t)
+@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vmovq_n_u32 (uint32_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vmovq_n_u16 (uint16_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vmovq_n_u8 (uint8_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vmovq_n_s32 (int32_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vmovq_n_s16 (int16_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vmovq_n_s8 (int8_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vmovq_n_f32 (float32_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x8_t vmovq_n_p16 (poly16_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x16_t vmovq_n_p8 (poly8_t)
+@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vmovq_n_u64 (uint64_t)
+@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vmovq_n_s64 (int64_t)
+@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vdup_lane_u32 (uint32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vdup_lane_u16 (uint16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vdup_lane_u8 (uint8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vdup_lane_s32 (int32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vdup_lane_s16 (int16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vdup_lane_s8 (int8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vdup_lane_f32 (float32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4_t vdup_lane_p16 (poly16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vdup_lane_p8 (poly8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vdup_lane_u64 (uint64x1_t, const int)
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vdup_lane_s64 (int64x1_t, const int)
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vdupq_lane_u32 (uint32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vdupq_lane_u16 (uint16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vdupq_lane_u8 (uint8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vdupq_lane_s32 (int32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vdupq_lane_s16 (int16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vdupq_lane_s8 (int8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vdupq_lane_f32 (float32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x8_t vdupq_lane_p16 (poly16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x16_t vdupq_lane_p8 (poly8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vdupq_lane_u64 (uint64x1_t, const int)
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vdupq_lane_s64 (int64x1_t, const int)
+@end itemize
+
+
+
+
+@subsubsection Combining vectors
+
+@itemize @bullet
+@item uint32x4_t vcombine_u32 (uint32x2_t, uint32x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vcombine_u16 (uint16x4_t, uint16x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vcombine_u8 (uint8x8_t, uint8x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vcombine_s32 (int32x2_t, int32x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vcombine_s16 (int16x4_t, int16x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vcombine_s8 (int8x8_t, int8x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vcombine_u64 (uint64x1_t, uint64x1_t)
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vcombine_s64 (int64x1_t, int64x1_t)
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vcombine_f32 (float32x2_t, float32x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly16x8_t vcombine_p16 (poly16x4_t, poly16x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly8x16_t vcombine_p8 (poly8x8_t, poly8x8_t)
+@end itemize
+
+
+
+
+@subsubsection Splitting vectors
+
+@itemize @bullet
+@item uint32x2_t vget_high_u32 (uint32x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vget_high_u16 (uint16x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vget_high_u8 (uint8x16_t)
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vget_high_s32 (int32x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vget_high_s16 (int16x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vget_high_s8 (int8x16_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vget_high_u64 (uint64x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vget_high_s64 (int64x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vget_high_f32 (float32x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4_t vget_high_p16 (poly16x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vget_high_p8 (poly8x16_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vget_low_u32 (uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vget_low_u16 (uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vget_low_u8 (uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vget_low_s32 (int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vget_low_s16 (int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vget_low_s8 (int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vget_low_u64 (uint64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vget_low_s64 (int64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vget_low_f32 (float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4_t vget_low_p16 (poly16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vget_low_p8 (poly8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
+@end itemize
+
+
+
+
+@subsubsection Conversions
+
+@itemize @bullet
+@item float32x2_t vcvt_f32_u32 (uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vcvt_f32_s32 (int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vcvt_u32_f32 (float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vcvt_s32_f32 (float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vcvtq_f32_u32 (uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vcvtq_f32_s32 (int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vcvtq_u32_f32 (float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vcvtq_s32_f32 (float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vcvt_n_f32_u32 (uint32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vcvt_n_f32_s32 (int32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vcvt_n_u32_f32 (float32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vcvt_n_s32_f32 (float32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vcvtq_n_f32_u32 (uint32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vcvtq_n_f32_s32 (int32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vcvtq_n_u32_f32 (float32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vcvtq_n_s32_f32 (float32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+
+
+@subsubsection Move, single_opcode narrowing
+
+@itemize @bullet
+@item uint32x2_t vmovn_u64 (uint64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vmovn.i64 @var{d0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vmovn_u32 (uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmovn.i32 @var{d0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vmovn_u16 (uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmovn.i16 @var{d0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vmovn_s64 (int64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vmovn.i64 @var{d0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vmovn_s32 (int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmovn.i32 @var{d0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vmovn_s16 (int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmovn.i16 @var{d0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vqmovn_u64 (uint64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vqmovn.u64 @var{d0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vqmovn_u32 (uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vqmovn.u32 @var{d0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vqmovn_u16 (uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vqmovn.u16 @var{d0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vqmovn_s64 (int64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vqmovn.s64 @var{d0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vqmovn_s32 (int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vqmovn.s32 @var{d0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vqmovn_s16 (int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vqmovn.s16 @var{d0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vqmovun_s64 (int64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vqmovun.s64 @var{d0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vqmovun_s32 (int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vqmovun.s32 @var{d0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vqmovun_s16 (int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vqmovun.s16 @var{d0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Move, single_opcode long
+
+@itemize @bullet
+@item uint64x2_t vmovl_u32 (uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vmovl.u32 @var{q0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vmovl_u16 (uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmovl.u16 @var{q0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vmovl_u8 (uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmovl.u8 @var{q0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vmovl_s32 (int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vmovl.s32 @var{q0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vmovl_s16 (int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vmovl.s16 @var{q0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vmovl_s8 (int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vmovl.s8 @var{q0}, @var{d0}}
+@end itemize
+
+
+
+
+@subsubsection Table lookup
+
+@itemize @bullet
+@item poly8x8_t vtbl1_p8 (poly8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}@}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vtbl1_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}@}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vtbl1_u8 (uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}@}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vtbl2_p8 (poly8x8x2_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vtbl2_s8 (int8x8x2_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vtbl2_u8 (uint8x8x2_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vtbl3_p8 (poly8x8x3_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vtbl3_s8 (int8x8x3_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vtbl3_u8 (uint8x8x3_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vtbl4_p8 (poly8x8x4_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vtbl4_s8 (int8x8x4_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vtbl4_u8 (uint8x8x4_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
+@end itemize
+
+
+
+
+@subsubsection Extended table lookup
+
+@itemize @bullet
+@item poly8x8_t vtbx1_p8 (poly8x8_t, poly8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}@}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vtbx1_s8 (int8x8_t, int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}@}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vtbx1_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}@}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vtbx2_p8 (poly8x8_t, poly8x8x2_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vtbx2_s8 (int8x8_t, int8x8x2_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vtbx2_u8 (uint8x8_t, uint8x8x2_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vtbx3_p8 (poly8x8_t, poly8x8x3_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vtbx3_s8 (int8x8_t, int8x8x3_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vtbx3_u8 (uint8x8_t, uint8x8x3_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vtbx4_p8 (poly8x8_t, poly8x8x4_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vtbx4_s8 (int8x8_t, int8x8x4_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vtbx4_u8 (uint8x8_t, uint8x8x4_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
+@end itemize
+
+
+
+
+@subsubsection Multiply, lane
+
+@itemize @bullet
+@item float32x2_t vmul_lane_f32 (float32x2_t, float32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vmul_lane_u32 (uint32x2_t, uint32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vmul_lane_u16 (uint16x4_t, uint16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vmul_lane_s32 (int32x2_t, int32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vmul_lane_s16 (int16x4_t, int16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vmulq_lane_f32 (float32x4_t, float32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vmulq_lane_u32 (uint32x4_t, uint32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vmulq_lane_u16 (uint16x8_t, uint16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vmulq_lane_s32 (int32x4_t, int32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vmulq_lane_s16 (int16x8_t, int16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+
+
+@subsubsection Long multiply, lane
+
+@itemize @bullet
+@item uint64x2_t vmull_lane_u32 (uint32x2_t, uint32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmull.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vmull_lane_u16 (uint16x4_t, uint16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmull.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vmull_lane_s32 (int32x2_t, int32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vmull_lane_s16 (int16x4_t, int16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+
+
+@subsubsection Saturating doubling long multiply, lane
+
+@itemize @bullet
+@item int64x2_t vqdmull_lane_s32 (int32x2_t, int32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqdmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vqdmull_lane_s16 (int16x4_t, int16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqdmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+
+
+@subsubsection Saturating doubling multiply high, lane
+
+@itemize @bullet
+@item int32x4_t vqdmulhq_lane_s32 (int32x4_t, int32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vqdmulhq_lane_s16 (int16x8_t, int16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vqdmulh_lane_s32 (int32x2_t, int32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vqdmulh_lane_s16 (int16x4_t, int16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vqrdmulhq_lane_s32 (int32x4_t, int32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vqrdmulhq_lane_s16 (int16x8_t, int16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vqrdmulh_lane_s32 (int32x2_t, int32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vqrdmulh_lane_s16 (int16x4_t, int16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+
+
+@subsubsection Multiply-accumulate, lane
+
+@itemize @bullet
+@item float32x2_t vmla_lane_f32 (float32x2_t, float32x2_t, float32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vmla_lane_u32 (uint32x2_t, uint32x2_t, uint32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vmla_lane_u16 (uint16x4_t, uint16x4_t, uint16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vmla_lane_s32 (int32x2_t, int32x2_t, int32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vmla_lane_s16 (int16x4_t, int16x4_t, int16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vmlaq_lane_f32 (float32x4_t, float32x4_t, float32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vmlaq_lane_u32 (uint32x4_t, uint32x4_t, uint32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vmlaq_lane_u16 (uint16x8_t, uint16x8_t, uint16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vmlaq_lane_s32 (int32x4_t, int32x4_t, int32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vmlaq_lane_s16 (int16x8_t, int16x8_t, int16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vmlal_lane_u32 (uint64x2_t, uint32x2_t, uint32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmlal.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vmlal_lane_u16 (uint32x4_t, uint16x4_t, uint16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmlal.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vmlal_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vmlal_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vqdmlal_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqdmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vqdmlal_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqdmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+
+
+@subsubsection Multiply-subtract, lane
+
+@itemize @bullet
+@item float32x2_t vmls_lane_f32 (float32x2_t, float32x2_t, float32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vmls_lane_u32 (uint32x2_t, uint32x2_t, uint32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vmls_lane_u16 (uint16x4_t, uint16x4_t, uint16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vmls_lane_s32 (int32x2_t, int32x2_t, int32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vmls_lane_s16 (int16x4_t, int16x4_t, int16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vmlsq_lane_f32 (float32x4_t, float32x4_t, float32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vmlsq_lane_u32 (uint32x4_t, uint32x4_t, uint32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vmlsq_lane_u16 (uint16x8_t, uint16x8_t, uint16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vmlsq_lane_s32 (int32x4_t, int32x4_t, int32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vmlsq_lane_s16 (int16x8_t, int16x8_t, int16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vmlsl_lane_u32 (uint64x2_t, uint32x2_t, uint32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmlsl.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vmlsl_lane_u16 (uint32x4_t, uint16x4_t, uint16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmlsl.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vmlsl_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vmlsl_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vqdmlsl_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqdmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vqdmlsl_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vqdmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+
+
+@subsubsection Vector multiply by scalar
+
+@itemize @bullet
+@item float32x2_t vmul_n_f32 (float32x2_t, float32_t)
+@*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vmul_n_u32 (uint32x2_t, uint32_t)
+@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vmul_n_u16 (uint16x4_t, uint16_t)
+@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vmul_n_s32 (int32x2_t, int32_t)
+@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vmul_n_s16 (int16x4_t, int16_t)
+@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vmulq_n_f32 (float32x4_t, float32_t)
+@*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vmulq_n_u32 (uint32x4_t, uint32_t)
+@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vmulq_n_u16 (uint16x8_t, uint16_t)
+@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vmulq_n_s32 (int32x4_t, int32_t)
+@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vmulq_n_s16 (int16x8_t, int16_t)
+@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+
+
+@subsubsection Vector long multiply by scalar
+
+@itemize @bullet
+@item uint64x2_t vmull_n_u32 (uint32x2_t, uint32_t)
+@*@emph{Form of expected instruction(s):} @code{vmull.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vmull_n_u16 (uint16x4_t, uint16_t)
+@*@emph{Form of expected instruction(s):} @code{vmull.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vmull_n_s32 (int32x2_t, int32_t)
+@*@emph{Form of expected instruction(s):} @code{vmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vmull_n_s16 (int16x4_t, int16_t)
+@*@emph{Form of expected instruction(s):} @code{vmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+
+
+@subsubsection Vector saturating doubling long multiply by scalar
+
+@itemize @bullet
+@item int64x2_t vqdmull_n_s32 (int32x2_t, int32_t)
+@*@emph{Form of expected instruction(s):} @code{vqdmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vqdmull_n_s16 (int16x4_t, int16_t)
+@*@emph{Form of expected instruction(s):} @code{vqdmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+
+
+@subsubsection Vector saturating doubling multiply high by scalar
+
+@itemize @bullet
+@item int32x4_t vqdmulhq_n_s32 (int32x4_t, int32_t)
+@*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vqdmulhq_n_s16 (int16x8_t, int16_t)
+@*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vqdmulh_n_s32 (int32x2_t, int32_t)
+@*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vqdmulh_n_s16 (int16x4_t, int16_t)
+@*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vqrdmulhq_n_s32 (int32x4_t, int32_t)
+@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vqrdmulhq_n_s16 (int16x8_t, int16_t)
+@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vqrdmulh_n_s32 (int32x2_t, int32_t)
+@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vqrdmulh_n_s16 (int16x4_t, int16_t)
+@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+
+
+@subsubsection Vector multiply-accumulate by scalar
+
+@itemize @bullet
+@item float32x2_t vmla_n_f32 (float32x2_t, float32x2_t, float32_t)
+@*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vmla_n_u32 (uint32x2_t, uint32x2_t, uint32_t)
+@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vmla_n_u16 (uint16x4_t, uint16x4_t, uint16_t)
+@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vmla_n_s32 (int32x2_t, int32x2_t, int32_t)
+@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vmla_n_s16 (int16x4_t, int16x4_t, int16_t)
+@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vmlaq_n_f32 (float32x4_t, float32x4_t, float32_t)
+@*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vmlaq_n_u32 (uint32x4_t, uint32x4_t, uint32_t)
+@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vmlaq_n_u16 (uint16x8_t, uint16x8_t, uint16_t)
+@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vmlaq_n_s32 (int32x4_t, int32x4_t, int32_t)
+@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vmlaq_n_s16 (int16x8_t, int16x8_t, int16_t)
+@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vmlal_n_u32 (uint64x2_t, uint32x2_t, uint32_t)
+@*@emph{Form of expected instruction(s):} @code{vmlal.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vmlal_n_u16 (uint32x4_t, uint16x4_t, uint16_t)
+@*@emph{Form of expected instruction(s):} @code{vmlal.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vmlal_n_s32 (int64x2_t, int32x2_t, int32_t)
+@*@emph{Form of expected instruction(s):} @code{vmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vmlal_n_s16 (int32x4_t, int16x4_t, int16_t)
+@*@emph{Form of expected instruction(s):} @code{vmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vqdmlal_n_s32 (int64x2_t, int32x2_t, int32_t)
+@*@emph{Form of expected instruction(s):} @code{vqdmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vqdmlal_n_s16 (int32x4_t, int16x4_t, int16_t)
+@*@emph{Form of expected instruction(s):} @code{vqdmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+
+
+@subsubsection Vector multiply-subtract by scalar
+
+@itemize @bullet
+@item float32x2_t vmls_n_f32 (float32x2_t, float32x2_t, float32_t)
+@*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vmls_n_u32 (uint32x2_t, uint32x2_t, uint32_t)
+@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vmls_n_u16 (uint16x4_t, uint16x4_t, uint16_t)
+@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vmls_n_s32 (int32x2_t, int32x2_t, int32_t)
+@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vmls_n_s16 (int16x4_t, int16x4_t, int16_t)
+@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vmlsq_n_f32 (float32x4_t, float32x4_t, float32_t)
+@*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vmlsq_n_u32 (uint32x4_t, uint32x4_t, uint32_t)
+@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vmlsq_n_u16 (uint16x8_t, uint16x8_t, uint16_t)
+@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vmlsq_n_s32 (int32x4_t, int32x4_t, int32_t)
+@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vmlsq_n_s16 (int16x8_t, int16x8_t, int16_t)
+@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vmlsl_n_u32 (uint64x2_t, uint32x2_t, uint32_t)
+@*@emph{Form of expected instruction(s):} @code{vmlsl.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vmlsl_n_u16 (uint32x4_t, uint16x4_t, uint16_t)
+@*@emph{Form of expected instruction(s):} @code{vmlsl.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vmlsl_n_s32 (int64x2_t, int32x2_t, int32_t)
+@*@emph{Form of expected instruction(s):} @code{vmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vmlsl_n_s16 (int32x4_t, int16x4_t, int16_t)
+@*@emph{Form of expected instruction(s):} @code{vmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vqdmlsl_n_s32 (int64x2_t, int32x2_t, int32_t)
+@*@emph{Form of expected instruction(s):} @code{vqdmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vqdmlsl_n_s16 (int32x4_t, int16x4_t, int16_t)
+@*@emph{Form of expected instruction(s):} @code{vqdmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
+@end itemize
+
+
+
+
+@subsubsection Vector extract
+
+@itemize @bullet
+@item uint32x2_t vext_u32 (uint32x2_t, uint32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vext.32 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vext_u16 (uint16x4_t, uint16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vext.16 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vext_u8 (uint8x8_t, uint8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vext.8 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vext_s32 (int32x2_t, int32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vext.32 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vext_s16 (int16x4_t, int16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vext.16 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vext_s8 (int8x8_t, int8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vext.8 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vext_u64 (uint64x1_t, uint64x1_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vext.64 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vext_s64 (int64x1_t, int64x1_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vext.64 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vext_f32 (float32x2_t, float32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vext.32 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4_t vext_p16 (poly16x4_t, poly16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vext.16 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vext_p8 (poly8x8_t, poly8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vext.8 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vextq_u32 (uint32x4_t, uint32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vext.32 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vextq_u16 (uint16x8_t, uint16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vext.16 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vextq_u8 (uint8x16_t, uint8x16_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vext.8 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vextq_s32 (int32x4_t, int32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vext.32 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vextq_s16 (int16x8_t, int16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vext.16 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vextq_s8 (int8x16_t, int8x16_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vext.8 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vextq_u64 (uint64x2_t, uint64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vext.64 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vextq_s64 (int64x2_t, int64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vext.64 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vextq_f32 (float32x4_t, float32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vext.32 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x8_t vextq_p16 (poly16x8_t, poly16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vext.16 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x16_t vextq_p8 (poly8x16_t, poly8x16_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vext.8 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
+@end itemize
+
+
+
+
+@subsubsection Reverse elements
+
+@itemize @bullet
+@item uint32x2_t vrev64_u32 (uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vrev64_u16 (uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vrev64_u8 (uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vrev64_s32 (int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vrev64_s16 (int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vrev64_s8 (int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vrev64_f32 (float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4_t vrev64_p16 (poly16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vrev64_p8 (poly8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vrev64q_u32 (uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vrev64q_u16 (uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vrev64q_u8 (uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vrev64q_s32 (int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vrev64q_s16 (int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vrev64q_s8 (int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vrev64q_f32 (float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x8_t vrev64q_p16 (poly16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x16_t vrev64q_p8 (poly8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vrev32_u16 (uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vrev32_s16 (int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vrev32_u8 (uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vrev32_s8 (int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4_t vrev32_p16 (poly16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vrev32_p8 (poly8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vrev32q_u16 (uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vrev32q_s16 (int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vrev32q_u8 (uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vrev32q_s8 (int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x8_t vrev32q_p16 (poly16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x16_t vrev32q_p8 (poly8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vrev16_u8 (uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vrev16_s8 (int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vrev16_p8 (poly8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vrev16q_u8 (uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vrev16q_s8 (int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x16_t vrev16q_p8 (poly8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Bit selection
+
+@itemize @bullet
+@item uint32x2_t vbsl_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vbsl_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vbsl_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vbsl_s32 (uint32x2_t, int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vbsl_s16 (uint16x4_t, int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vbsl_s8 (uint8x8_t, int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vbsl_u64 (uint64x1_t, uint64x1_t, uint64x1_t)
+@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vbsl_s64 (uint64x1_t, int64x1_t, int64x1_t)
+@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vbsl_f32 (uint32x2_t, float32x2_t, float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4_t vbsl_p16 (uint16x4_t, poly16x4_t, poly16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vbsl_p8 (uint8x8_t, poly8x8_t, poly8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vbslq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vbslq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vbslq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vbslq_s32 (uint32x4_t, int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vbslq_s16 (uint16x8_t, int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vbslq_s8 (uint8x16_t, int8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vbslq_u64 (uint64x2_t, uint64x2_t, uint64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vbslq_s64 (uint64x2_t, int64x2_t, int64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vbslq_f32 (uint32x4_t, float32x4_t, float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x8_t vbslq_p16 (uint16x8_t, poly16x8_t, poly16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x16_t vbslq_p8 (uint8x16_t, poly8x16_t, poly8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Transpose elements
+
+@itemize @bullet
+@item uint32x2x2_t vtrn_u32 (uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{d0}, @var{d1}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4x2_t vtrn_u16 (uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{d0}, @var{d1}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8x2_t vtrn_u8 (uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{d0}, @var{d1}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2x2_t vtrn_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{d0}, @var{d1}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4x2_t vtrn_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{d0}, @var{d1}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8x2_t vtrn_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{d0}, @var{d1}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2x2_t vtrn_f32 (float32x2_t, float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{d0}, @var{d1}}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4x2_t vtrn_p16 (poly16x4_t, poly16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{d0}, @var{d1}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8x2_t vtrn_p8 (poly8x8_t, poly8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{d0}, @var{d1}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4x2_t vtrnq_u32 (uint32x4_t, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{q0}, @var{q1}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8x2_t vtrnq_u16 (uint16x8_t, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{q0}, @var{q1}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16x2_t vtrnq_u8 (uint8x16_t, uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{q0}, @var{q1}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4x2_t vtrnq_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{q0}, @var{q1}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8x2_t vtrnq_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{q0}, @var{q1}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16x2_t vtrnq_s8 (int8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{q0}, @var{q1}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4x2_t vtrnq_f32 (float32x4_t, float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{q0}, @var{q1}}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x8x2_t vtrnq_p16 (poly16x8_t, poly16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{q0}, @var{q1}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x16x2_t vtrnq_p8 (poly8x16_t, poly8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{q0}, @var{q1}}
+@end itemize
+
+
+
+
+@subsubsection Zip elements
+
+@itemize @bullet
+@item uint32x2x2_t vzip_u32 (uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vzip.32 @var{d0}, @var{d1}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4x2_t vzip_u16 (uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vzip.16 @var{d0}, @var{d1}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8x2_t vzip_u8 (uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vzip.8 @var{d0}, @var{d1}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2x2_t vzip_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vzip.32 @var{d0}, @var{d1}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4x2_t vzip_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vzip.16 @var{d0}, @var{d1}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8x2_t vzip_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vzip.8 @var{d0}, @var{d1}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2x2_t vzip_f32 (float32x2_t, float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vzip.32 @var{d0}, @var{d1}}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4x2_t vzip_p16 (poly16x4_t, poly16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vzip.16 @var{d0}, @var{d1}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8x2_t vzip_p8 (poly8x8_t, poly8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vzip.8 @var{d0}, @var{d1}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4x2_t vzipq_u32 (uint32x4_t, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vzip.32 @var{q0}, @var{q1}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8x2_t vzipq_u16 (uint16x8_t, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vzip.16 @var{q0}, @var{q1}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16x2_t vzipq_u8 (uint8x16_t, uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vzip.8 @var{q0}, @var{q1}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4x2_t vzipq_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vzip.32 @var{q0}, @var{q1}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8x2_t vzipq_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vzip.16 @var{q0}, @var{q1}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16x2_t vzipq_s8 (int8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vzip.8 @var{q0}, @var{q1}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4x2_t vzipq_f32 (float32x4_t, float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vzip.32 @var{q0}, @var{q1}}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x8x2_t vzipq_p16 (poly16x8_t, poly16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vzip.16 @var{q0}, @var{q1}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x16x2_t vzipq_p8 (poly8x16_t, poly8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vzip.8 @var{q0}, @var{q1}}
+@end itemize
+
+
+
+
+@subsubsection Unzip elements
+
+@itemize @bullet
+@item uint32x2x2_t vuzp_u32 (uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4x2_t vuzp_u16 (uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{d0}, @var{d1}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8x2_t vuzp_u8 (uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{d0}, @var{d1}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2x2_t vuzp_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4x2_t vuzp_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{d0}, @var{d1}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8x2_t vuzp_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{d0}, @var{d1}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2x2_t vuzp_f32 (float32x2_t, float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4x2_t vuzp_p16 (poly16x4_t, poly16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{d0}, @var{d1}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8x2_t vuzp_p8 (poly8x8_t, poly8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{d0}, @var{d1}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4x2_t vuzpq_u32 (uint32x4_t, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{q0}, @var{q1}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8x2_t vuzpq_u16 (uint16x8_t, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{q0}, @var{q1}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16x2_t vuzpq_u8 (uint8x16_t, uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{q0}, @var{q1}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4x2_t vuzpq_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{q0}, @var{q1}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8x2_t vuzpq_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{q0}, @var{q1}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16x2_t vuzpq_s8 (int8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{q0}, @var{q1}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4x2_t vuzpq_f32 (float32x4_t, float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{q0}, @var{q1}}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x8x2_t vuzpq_p16 (poly16x8_t, poly16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{q0}, @var{q1}}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x16x2_t vuzpq_p8 (poly8x16_t, poly8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{q0}, @var{q1}}
+@end itemize
+
+
+
+
+@subsubsection Element/structure loads, VLD1 variants
+
+@itemize @bullet
+@item uint32x2_t vld1_u32 (const uint32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vld1_u16 (const uint16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vld1_u8 (const uint8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vld1_s32 (const int32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vld1_s16 (const int16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vld1_s8 (const int8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vld1_u64 (const uint64_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vld1_s64 (const int64_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vld1_f32 (const float32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4_t vld1_p16 (const poly16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vld1_p8 (const poly8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vld1q_u32 (const uint32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vld1q_u16 (const uint16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vld1q_u8 (const uint8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vld1q_s32 (const int32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vld1q_s16 (const int16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vld1q_s8 (const int8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vld1q_u64 (const uint64_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vld1q_s64 (const int64_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vld1q_f32 (const float32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x8_t vld1q_p16 (const poly16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x16_t vld1q_p8 (const poly8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vld1_lane_u32 (const uint32_t *, uint32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vld1_lane_u16 (const uint16_t *, uint16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vld1_lane_u8 (const uint8_t *, uint8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vld1_lane_s32 (const int32_t *, int32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vld1_lane_s16 (const int16_t *, int16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vld1_lane_s8 (const int8_t *, int8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vld1_lane_f32 (const float32_t *, float32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4_t vld1_lane_p16 (const poly16_t *, poly16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vld1_lane_p8 (const poly8_t *, poly8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vld1_lane_u64 (const uint64_t *, uint64x1_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vld1_lane_s64 (const int64_t *, int64x1_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vld1q_lane_u32 (const uint32_t *, uint32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vld1q_lane_u16 (const uint16_t *, uint16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vld1q_lane_u8 (const uint8_t *, uint8x16_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vld1q_lane_s32 (const int32_t *, int32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vld1q_lane_s16 (const int16_t *, int16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vld1q_lane_s8 (const int8_t *, int8x16_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vld1q_lane_f32 (const float32_t *, float32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x8_t vld1q_lane_p16 (const poly16_t *, poly16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x16_t vld1q_lane_p8 (const poly8_t *, poly8x16_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vld1q_lane_u64 (const uint64_t *, uint64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vld1q_lane_s64 (const int64_t *, int64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vld1_dup_u32 (const uint32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vld1_dup_u16 (const uint16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vld1_dup_u8 (const uint8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vld1_dup_s32 (const int32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vld1_dup_s16 (const int16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vld1_dup_s8 (const int8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vld1_dup_f32 (const float32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4_t vld1_dup_p16 (const poly16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vld1_dup_p8 (const poly8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vld1_dup_u64 (const uint64_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vld1_dup_s64 (const int64_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vld1q_dup_u32 (const uint32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vld1q_dup_u16 (const uint16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vld1q_dup_u8 (const uint8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vld1q_dup_s32 (const int32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vld1q_dup_s16 (const int16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vld1q_dup_s8 (const int8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vld1q_dup_f32 (const float32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x8_t vld1q_dup_p16 (const poly16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x16_t vld1q_dup_p8 (const poly8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vld1q_dup_u64 (const uint64_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vld1q_dup_s64 (const int64_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+
+
+@subsubsection Element/structure stores, VST1 variants
+
+@itemize @bullet
+@item void vst1_u32 (uint32_t *, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1_u16 (uint16_t *, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1_u8 (uint8_t *, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1_s32 (int32_t *, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1_s16 (int16_t *, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1_s8 (int8_t *, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1_u64 (uint64_t *, uint64x1_t)
+@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1_s64 (int64_t *, int64x1_t)
+@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1_f32 (float32_t *, float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1_p16 (poly16_t *, poly16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1_p8 (poly8_t *, poly8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1q_u32 (uint32_t *, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1q_u16 (uint16_t *, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1q_u8 (uint8_t *, uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1q_s32 (int32_t *, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1q_s16 (int16_t *, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1q_s8 (int8_t *, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1q_u64 (uint64_t *, uint64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1q_s64 (int64_t *, int64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1q_f32 (float32_t *, float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1q_p16 (poly16_t *, poly16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1q_p8 (poly8_t *, poly8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1_lane_u32 (uint32_t *, uint32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1_lane_u16 (uint16_t *, uint16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1_lane_u8 (uint8_t *, uint8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1_lane_s32 (int32_t *, int32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1_lane_s16 (int16_t *, int16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1_lane_s8 (int8_t *, int8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1_lane_f32 (float32_t *, float32x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1_lane_p16 (poly16_t *, poly16x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1_lane_p8 (poly8_t *, poly8x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1_lane_s64 (int64_t *, int64x1_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1_lane_u64 (uint64_t *, uint64x1_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1q_lane_u32 (uint32_t *, uint32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1q_lane_u16 (uint16_t *, uint16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1q_lane_u8 (uint8_t *, uint8x16_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1q_lane_s32 (int32_t *, int32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1q_lane_s16 (int16_t *, int16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1q_lane_s8 (int8_t *, int8x16_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1q_lane_f32 (float32_t *, float32x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1q_lane_p16 (poly16_t *, poly16x8_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1q_lane_p8 (poly8_t *, poly8x16_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1q_lane_s64 (int64_t *, int64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst1q_lane_u64 (uint64_t *, uint64x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
+@end itemize
+
+
+
+
+@subsubsection Element/structure loads, VLD2 variants
+
+@itemize @bullet
+@item uint32x2x2_t vld2_u32 (const uint32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4x2_t vld2_u16 (const uint16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8x2_t vld2_u8 (const uint8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2x2_t vld2_s32 (const int32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4x2_t vld2_s16 (const int16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8x2_t vld2_s8 (const int8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2x2_t vld2_f32 (const float32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4x2_t vld2_p16 (const poly16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8x2_t vld2_p8 (const poly8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1x2_t vld2_u64 (const uint64_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1x2_t vld2_s64 (const int64_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4x2_t vld2q_u32 (const uint32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8x2_t vld2q_u16 (const uint16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16x2_t vld2q_u8 (const uint8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4x2_t vld2q_s32 (const int32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8x2_t vld2q_s16 (const int16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16x2_t vld2q_s8 (const int8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4x2_t vld2q_f32 (const float32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x8x2_t vld2q_p16 (const poly16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x16x2_t vld2q_p8 (const poly8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2x2_t vld2_lane_u32 (const uint32_t *, uint32x2x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4x2_t vld2_lane_u16 (const uint16_t *, uint16x4x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8x2_t vld2_lane_u8 (const uint8_t *, uint8x8x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2x2_t vld2_lane_s32 (const int32_t *, int32x2x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4x2_t vld2_lane_s16 (const int16_t *, int16x4x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8x2_t vld2_lane_s8 (const int8_t *, int8x8x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2x2_t vld2_lane_f32 (const float32_t *, float32x2x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4x2_t vld2_lane_p16 (const poly16_t *, poly16x4x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8x2_t vld2_lane_p8 (const poly8_t *, poly8x8x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4x2_t vld2q_lane_s32 (const int32_t *, int32x4x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8x2_t vld2q_lane_s16 (const int16_t *, int16x8x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4x2_t vld2q_lane_u32 (const uint32_t *, uint32x4x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8x2_t vld2q_lane_u16 (const uint16_t *, uint16x8x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4x2_t vld2q_lane_f32 (const float32_t *, float32x4x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x8x2_t vld2q_lane_p16 (const poly16_t *, poly16x8x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2x2_t vld2_dup_u32 (const uint32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4x2_t vld2_dup_u16 (const uint16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8x2_t vld2_dup_u8 (const uint8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2x2_t vld2_dup_s32 (const int32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4x2_t vld2_dup_s16 (const int16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8x2_t vld2_dup_s8 (const int8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2x2_t vld2_dup_f32 (const float32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4x2_t vld2_dup_p16 (const poly16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8x2_t vld2_dup_p8 (const poly8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1x2_t vld2_dup_u64 (const uint64_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1x2_t vld2_dup_s64 (const int64_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+
+
+@subsubsection Element/structure stores, VST2 variants
+
+@itemize @bullet
+@item void vst2_u32 (uint32_t *, uint32x2x2_t)
+@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst2_u16 (uint16_t *, uint16x4x2_t)
+@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst2_u8 (uint8_t *, uint8x8x2_t)
+@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst2_s32 (int32_t *, int32x2x2_t)
+@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst2_s16 (int16_t *, int16x4x2_t)
+@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst2_s8 (int8_t *, int8x8x2_t)
+@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst2_f32 (float32_t *, float32x2x2_t)
+@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst2_p16 (poly16_t *, poly16x4x2_t)
+@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst2_p8 (poly8_t *, poly8x8x2_t)
+@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst2_u64 (uint64_t *, uint64x1x2_t)
+@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst2_s64 (int64_t *, int64x1x2_t)
+@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst2q_u32 (uint32_t *, uint32x4x2_t)
+@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst2q_u16 (uint16_t *, uint16x8x2_t)
+@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst2q_u8 (uint8_t *, uint8x16x2_t)
+@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst2q_s32 (int32_t *, int32x4x2_t)
+@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst2q_s16 (int16_t *, int16x8x2_t)
+@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst2q_s8 (int8_t *, int8x16x2_t)
+@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst2q_f32 (float32_t *, float32x4x2_t)
+@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst2q_p16 (poly16_t *, poly16x8x2_t)
+@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst2q_p8 (poly8_t *, poly8x16x2_t)
+@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst2_lane_u32 (uint32_t *, uint32x2x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst2_lane_u16 (uint16_t *, uint16x4x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst2_lane_u8 (uint8_t *, uint8x8x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst2_lane_s32 (int32_t *, int32x2x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst2_lane_s16 (int16_t *, int16x4x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst2_lane_s8 (int8_t *, int8x8x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst2_lane_f32 (float32_t *, float32x2x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst2_lane_p16 (poly16_t *, poly16x4x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst2_lane_p8 (poly8_t *, poly8x8x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst2q_lane_s32 (int32_t *, int32x4x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst2q_lane_s16 (int16_t *, int16x8x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst2q_lane_u32 (uint32_t *, uint32x4x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst2q_lane_u16 (uint16_t *, uint16x8x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst2q_lane_f32 (float32_t *, float32x4x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst2q_lane_p16 (poly16_t *, poly16x8x2_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+
+
+@subsubsection Element/structure loads, VLD3 variants
+
+@itemize @bullet
+@item uint32x2x3_t vld3_u32 (const uint32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4x3_t vld3_u16 (const uint16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8x3_t vld3_u8 (const uint8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2x3_t vld3_s32 (const int32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4x3_t vld3_s16 (const int16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8x3_t vld3_s8 (const int8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2x3_t vld3_f32 (const float32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4x3_t vld3_p16 (const poly16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8x3_t vld3_p8 (const poly8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1x3_t vld3_u64 (const uint64_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1x3_t vld3_s64 (const int64_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4x3_t vld3q_u32 (const uint32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8x3_t vld3q_u16 (const uint16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16x3_t vld3q_u8 (const uint8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4x3_t vld3q_s32 (const int32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8x3_t vld3q_s16 (const int16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16x3_t vld3q_s8 (const int8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4x3_t vld3q_f32 (const float32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x8x3_t vld3q_p16 (const poly16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x16x3_t vld3q_p8 (const poly8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2x3_t vld3_lane_u32 (const uint32_t *, uint32x2x3_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4x3_t vld3_lane_u16 (const uint16_t *, uint16x4x3_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8x3_t vld3_lane_u8 (const uint8_t *, uint8x8x3_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2x3_t vld3_lane_s32 (const int32_t *, int32x2x3_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4x3_t vld3_lane_s16 (const int16_t *, int16x4x3_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8x3_t vld3_lane_s8 (const int8_t *, int8x8x3_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2x3_t vld3_lane_f32 (const float32_t *, float32x2x3_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4x3_t vld3_lane_p16 (const poly16_t *, poly16x4x3_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8x3_t vld3_lane_p8 (const poly8_t *, poly8x8x3_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4x3_t vld3q_lane_s32 (const int32_t *, int32x4x3_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8x3_t vld3q_lane_s16 (const int16_t *, int16x8x3_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4x3_t vld3q_lane_u32 (const uint32_t *, uint32x4x3_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8x3_t vld3q_lane_u16 (const uint16_t *, uint16x8x3_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4x3_t vld3q_lane_f32 (const float32_t *, float32x4x3_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x8x3_t vld3q_lane_p16 (const poly16_t *, poly16x8x3_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2x3_t vld3_dup_u32 (const uint32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4x3_t vld3_dup_u16 (const uint16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8x3_t vld3_dup_u8 (const uint8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2x3_t vld3_dup_s32 (const int32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4x3_t vld3_dup_s16 (const int16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8x3_t vld3_dup_s8 (const int8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2x3_t vld3_dup_f32 (const float32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4x3_t vld3_dup_p16 (const poly16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8x3_t vld3_dup_p8 (const poly8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1x3_t vld3_dup_u64 (const uint64_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1x3_t vld3_dup_s64 (const int64_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
+@end itemize
+
+
+
+
+@subsubsection Element/structure stores, VST3 variants
+
+@itemize @bullet
+@item void vst3_u32 (uint32_t *, uint32x2x3_t)
+@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst3_u16 (uint16_t *, uint16x4x3_t)
+@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst3_u8 (uint8_t *, uint8x8x3_t)
+@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst3_s32 (int32_t *, int32x2x3_t)
+@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst3_s16 (int16_t *, int16x4x3_t)
+@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst3_s8 (int8_t *, int8x8x3_t)
+@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst3_f32 (float32_t *, float32x2x3_t)
+@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst3_p16 (poly16_t *, poly16x4x3_t)
+@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst3_p8 (poly8_t *, poly8x8x3_t)
+@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst3_u64 (uint64_t *, uint64x1x3_t)
+@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst3_s64 (int64_t *, int64x1x3_t)
+@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst3q_u32 (uint32_t *, uint32x4x3_t)
+@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst3q_u16 (uint16_t *, uint16x8x3_t)
+@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst3q_u8 (uint8_t *, uint8x16x3_t)
+@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst3q_s32 (int32_t *, int32x4x3_t)
+@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst3q_s16 (int16_t *, int16x8x3_t)
+@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst3q_s8 (int8_t *, int8x16x3_t)
+@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst3q_f32 (float32_t *, float32x4x3_t)
+@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst3q_p16 (poly16_t *, poly16x8x3_t)
+@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst3q_p8 (poly8_t *, poly8x16x3_t)
+@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst3_lane_u32 (uint32_t *, uint32x2x3_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst3_lane_u16 (uint16_t *, uint16x4x3_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst3_lane_u8 (uint8_t *, uint8x8x3_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst3_lane_s32 (int32_t *, int32x2x3_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst3_lane_s16 (int16_t *, int16x4x3_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst3_lane_s8 (int8_t *, int8x8x3_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst3_lane_f32 (float32_t *, float32x2x3_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst3_lane_p16 (poly16_t *, poly16x4x3_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst3_lane_p8 (poly8_t *, poly8x8x3_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst3q_lane_s32 (int32_t *, int32x4x3_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst3q_lane_s16 (int16_t *, int16x8x3_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst3q_lane_u32 (uint32_t *, uint32x4x3_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst3q_lane_u16 (uint16_t *, uint16x8x3_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst3q_lane_f32 (float32_t *, float32x4x3_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst3q_lane_p16 (poly16_t *, poly16x8x3_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+
+
+@subsubsection Element/structure loads, VLD4 variants
+
+@itemize @bullet
+@item uint32x2x4_t vld4_u32 (const uint32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4x4_t vld4_u16 (const uint16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8x4_t vld4_u8 (const uint8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2x4_t vld4_s32 (const int32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4x4_t vld4_s16 (const int16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8x4_t vld4_s8 (const int8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2x4_t vld4_f32 (const float32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4x4_t vld4_p16 (const poly16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8x4_t vld4_p8 (const poly8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1x4_t vld4_u64 (const uint64_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1x4_t vld4_s64 (const int64_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4x4_t vld4q_u32 (const uint32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8x4_t vld4q_u16 (const uint16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16x4_t vld4q_u8 (const uint8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4x4_t vld4q_s32 (const int32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8x4_t vld4q_s16 (const int16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16x4_t vld4q_s8 (const int8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4x4_t vld4q_f32 (const float32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x8x4_t vld4q_p16 (const poly16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x16x4_t vld4q_p8 (const poly8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2x4_t vld4_lane_u32 (const uint32_t *, uint32x2x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4x4_t vld4_lane_u16 (const uint16_t *, uint16x4x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8x4_t vld4_lane_u8 (const uint8_t *, uint8x8x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2x4_t vld4_lane_s32 (const int32_t *, int32x2x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4x4_t vld4_lane_s16 (const int16_t *, int16x4x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8x4_t vld4_lane_s8 (const int8_t *, int8x8x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2x4_t vld4_lane_f32 (const float32_t *, float32x2x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4x4_t vld4_lane_p16 (const poly16_t *, poly16x4x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8x4_t vld4_lane_p8 (const poly8_t *, poly8x8x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4x4_t vld4q_lane_s32 (const int32_t *, int32x4x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8x4_t vld4q_lane_s16 (const int16_t *, int16x8x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4x4_t vld4q_lane_u32 (const uint32_t *, uint32x4x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8x4_t vld4q_lane_u16 (const uint16_t *, uint16x8x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4x4_t vld4q_lane_f32 (const float32_t *, float32x4x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x8x4_t vld4q_lane_p16 (const poly16_t *, poly16x8x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2x4_t vld4_dup_u32 (const uint32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4x4_t vld4_dup_u16 (const uint16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8x4_t vld4_dup_u8 (const uint8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2x4_t vld4_dup_s32 (const int32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4x4_t vld4_dup_s16 (const int16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8x4_t vld4_dup_s8 (const int8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item float32x2x4_t vld4_dup_f32 (const float32_t *)
+@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4x4_t vld4_dup_p16 (const poly16_t *)
+@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8x4_t vld4_dup_p8 (const poly8_t *)
+@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1x4_t vld4_dup_u64 (const uint64_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1x4_t vld4_dup_s64 (const int64_t *)
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+
+
+@subsubsection Element/structure stores, VST4 variants
+
+@itemize @bullet
+@item void vst4_u32 (uint32_t *, uint32x2x4_t)
+@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst4_u16 (uint16_t *, uint16x4x4_t)
+@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst4_u8 (uint8_t *, uint8x8x4_t)
+@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst4_s32 (int32_t *, int32x2x4_t)
+@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst4_s16 (int16_t *, int16x4x4_t)
+@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst4_s8 (int8_t *, int8x8x4_t)
+@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst4_f32 (float32_t *, float32x2x4_t)
+@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst4_p16 (poly16_t *, poly16x4x4_t)
+@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst4_p8 (poly8_t *, poly8x8x4_t)
+@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst4_u64 (uint64_t *, uint64x1x4_t)
+@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst4_s64 (int64_t *, int64x1x4_t)
+@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst4q_u32 (uint32_t *, uint32x4x4_t)
+@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst4q_u16 (uint16_t *, uint16x8x4_t)
+@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst4q_u8 (uint8_t *, uint8x16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst4q_s32 (int32_t *, int32x4x4_t)
+@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst4q_s16 (int16_t *, int16x8x4_t)
+@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst4q_s8 (int8_t *, int8x16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst4q_f32 (float32_t *, float32x4x4_t)
+@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst4q_p16 (poly16_t *, poly16x8x4_t)
+@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst4q_p8 (poly8_t *, poly8x16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst4_lane_u32 (uint32_t *, uint32x2x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst4_lane_u16 (uint16_t *, uint16x4x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst4_lane_u8 (uint8_t *, uint8x8x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst4_lane_s32 (int32_t *, int32x2x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst4_lane_s16 (int16_t *, int16x4x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst4_lane_s8 (int8_t *, int8x8x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst4_lane_f32 (float32_t *, float32x2x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst4_lane_p16 (poly16_t *, poly16x4x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst4_lane_p8 (poly8_t *, poly8x8x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst4q_lane_s32 (int32_t *, int32x4x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst4q_lane_s16 (int16_t *, int16x8x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst4q_lane_u32 (uint32_t *, uint32x4x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst4q_lane_u16 (uint16_t *, uint16x8x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst4q_lane_f32 (float32_t *, float32x4x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+@itemize @bullet
+@item void vst4q_lane_p16 (poly16_t *, poly16x8x4_t, const int)
+@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
+@end itemize
+
+
+
+
+@subsubsection Logical operations (AND)
+
+@itemize @bullet
+@item uint32x2_t vand_u32 (uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vand_u16 (uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vand_u8 (uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vand_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vand_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vand_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vand_u64 (uint64x1_t, uint64x1_t)
+@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vand_s64 (int64x1_t, int64x1_t)
+@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vandq_u32 (uint32x4_t, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vandq_u16 (uint16x8_t, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vandq_u8 (uint8x16_t, uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vandq_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vandq_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vandq_s8 (int8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vandq_u64 (uint64x2_t, uint64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vandq_s64 (int64x2_t, int64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Logical operations (OR)
+
+@itemize @bullet
+@item uint32x2_t vorr_u32 (uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vorr_u16 (uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vorr_u8 (uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vorr_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vorr_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vorr_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vorr_u64 (uint64x1_t, uint64x1_t)
+@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vorr_s64 (int64x1_t, int64x1_t)
+@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vorrq_u32 (uint32x4_t, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vorrq_u16 (uint16x8_t, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vorrq_u8 (uint8x16_t, uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vorrq_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vorrq_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vorrq_s8 (int8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vorrq_u64 (uint64x2_t, uint64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vorrq_s64 (int64x2_t, int64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Logical operations (exclusive OR)
+
+@itemize @bullet
+@item uint32x2_t veor_u32 (uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t veor_u16 (uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t veor_u8 (uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t veor_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t veor_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t veor_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t veor_u64 (uint64x1_t, uint64x1_t)
+@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t veor_s64 (int64x1_t, int64x1_t)
+@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t veorq_u32 (uint32x4_t, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t veorq_u16 (uint16x8_t, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t veorq_u8 (uint8x16_t, uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t veorq_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t veorq_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t veorq_s8 (int8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t veorq_u64 (uint64x2_t, uint64x2_t)
+@*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t veorq_s64 (int64x2_t, int64x2_t)
+@*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Logical operations (AND-NOT)
+
+@itemize @bullet
+@item uint32x2_t vbic_u32 (uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vbic_u16 (uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vbic_u8 (uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vbic_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vbic_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vbic_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vbic_u64 (uint64x1_t, uint64x1_t)
+@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vbic_s64 (int64x1_t, int64x1_t)
+@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vbicq_u32 (uint32x4_t, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vbicq_u16 (uint16x8_t, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vbicq_u8 (uint8x16_t, uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vbicq_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vbicq_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vbicq_s8 (int8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vbicq_u64 (uint64x2_t, uint64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vbicq_s64 (int64x2_t, int64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Logical operations (OR-NOT)
+
+@itemize @bullet
+@item uint32x2_t vorn_u32 (uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vorn_u16 (uint16x4_t, uint16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vorn_u8 (uint8x8_t, uint8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vorn_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vorn_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vorn_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vorn_u64 (uint64x1_t, uint64x1_t)
+@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vorn_s64 (int64x1_t, int64x1_t)
+@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vornq_u32 (uint32x4_t, uint32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vornq_u16 (uint16x8_t, uint16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vornq_u8 (uint8x16_t, uint8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vornq_s32 (int32x4_t, int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vornq_s16 (int16x8_t, int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vornq_s8 (int8x16_t, int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vornq_u64 (uint64x2_t, uint64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vornq_s64 (int64x2_t, int64x2_t)
+@*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Reinterpret casts
+
+@itemize @bullet
+@item poly8x8_t vreinterpret_p8_u32 (uint32x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vreinterpret_p8_u16 (uint16x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vreinterpret_p8_u8 (uint8x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vreinterpret_p8_s32 (int32x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vreinterpret_p8_s16 (int16x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vreinterpret_p8_s8 (int8x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vreinterpret_p8_u64 (uint64x1_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vreinterpret_p8_s64 (int64x1_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vreinterpret_p8_f32 (float32x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly8x8_t vreinterpret_p8_p16 (poly16x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly8x16_t vreinterpretq_p8_u32 (uint32x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly8x16_t vreinterpretq_p8_u16 (uint16x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly8x16_t vreinterpretq_p8_u8 (uint8x16_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly8x16_t vreinterpretq_p8_s32 (int32x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly8x16_t vreinterpretq_p8_s16 (int16x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly8x16_t vreinterpretq_p8_s8 (int8x16_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly8x16_t vreinterpretq_p8_u64 (uint64x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly8x16_t vreinterpretq_p8_s64 (int64x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly8x16_t vreinterpretq_p8_f32 (float32x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly8x16_t vreinterpretq_p8_p16 (poly16x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4_t vreinterpret_p16_u32 (uint32x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4_t vreinterpret_p16_u16 (uint16x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4_t vreinterpret_p16_u8 (uint8x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4_t vreinterpret_p16_s32 (int32x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4_t vreinterpret_p16_s16 (int16x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4_t vreinterpret_p16_s8 (int8x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4_t vreinterpret_p16_u64 (uint64x1_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4_t vreinterpret_p16_s64 (int64x1_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4_t vreinterpret_p16_f32 (float32x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4_t vreinterpret_p16_p8 (poly8x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly16x8_t vreinterpretq_p16_u32 (uint32x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly16x8_t vreinterpretq_p16_u16 (uint16x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly16x8_t vreinterpretq_p16_u8 (uint8x16_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly16x8_t vreinterpretq_p16_s32 (int32x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly16x8_t vreinterpretq_p16_s16 (int16x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly16x8_t vreinterpretq_p16_s8 (int8x16_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly16x8_t vreinterpretq_p16_u64 (uint64x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly16x8_t vreinterpretq_p16_s64 (int64x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly16x8_t vreinterpretq_p16_f32 (float32x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item poly16x8_t vreinterpretq_p16_p8 (poly8x16_t)
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vreinterpret_f32_u32 (uint32x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vreinterpret_f32_u16 (uint16x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vreinterpret_f32_u8 (uint8x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vreinterpret_f32_s32 (int32x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vreinterpret_f32_s16 (int16x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vreinterpret_f32_s8 (int8x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vreinterpret_f32_u64 (uint64x1_t)
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vreinterpret_f32_s64 (int64x1_t)
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vreinterpret_f32_p16 (poly16x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item float32x2_t vreinterpret_f32_p8 (poly8x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vreinterpretq_f32_u32 (uint32x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vreinterpretq_f32_u16 (uint16x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vreinterpretq_f32_u8 (uint8x16_t)
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vreinterpretq_f32_s32 (int32x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vreinterpretq_f32_s16 (int16x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vreinterpretq_f32_s8 (int8x16_t)
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vreinterpretq_f32_u64 (uint64x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vreinterpretq_f32_s64 (int64x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vreinterpretq_f32_p16 (poly16x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vreinterpretq_f32_p8 (poly8x16_t)
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vreinterpret_s64_u32 (uint32x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vreinterpret_s64_u16 (uint16x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vreinterpret_s64_u8 (uint8x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vreinterpret_s64_s32 (int32x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vreinterpret_s64_s16 (int16x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vreinterpret_s64_s8 (int8x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vreinterpret_s64_u64 (uint64x1_t)
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vreinterpret_s64_f32 (float32x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vreinterpret_s64_p16 (poly16x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item int64x1_t vreinterpret_s64_p8 (poly8x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vreinterpretq_s64_u32 (uint32x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vreinterpretq_s64_u16 (uint16x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vreinterpretq_s64_u8 (uint8x16_t)
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vreinterpretq_s64_s32 (int32x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vreinterpretq_s64_s16 (int16x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vreinterpretq_s64_s8 (int8x16_t)
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vreinterpretq_s64_u64 (uint64x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vreinterpretq_s64_f32 (float32x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vreinterpretq_s64_p16 (poly16x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item int64x2_t vreinterpretq_s64_p8 (poly8x16_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vreinterpret_u64_u32 (uint32x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vreinterpret_u64_u16 (uint16x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vreinterpret_u64_u8 (uint8x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vreinterpret_u64_s32 (int32x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vreinterpret_u64_s16 (int16x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vreinterpret_u64_s8 (int8x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vreinterpret_u64_s64 (int64x1_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vreinterpret_u64_f32 (float32x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vreinterpret_u64_p16 (poly16x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint64x1_t vreinterpret_u64_p8 (poly8x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vreinterpretq_u64_u32 (uint32x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vreinterpretq_u64_u16 (uint16x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vreinterpretq_u64_u8 (uint8x16_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vreinterpretq_u64_s32 (int32x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vreinterpretq_u64_s16 (int16x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vreinterpretq_u64_s8 (int8x16_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vreinterpretq_u64_s64 (int64x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vreinterpretq_u64_f32 (float32x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vreinterpretq_u64_p16 (poly16x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint64x2_t vreinterpretq_u64_p8 (poly8x16_t)
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vreinterpret_s8_u32 (uint32x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vreinterpret_s8_u16 (uint16x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vreinterpret_s8_u8 (uint8x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vreinterpret_s8_s32 (int32x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vreinterpret_s8_s16 (int16x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vreinterpret_s8_u64 (uint64x1_t)
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vreinterpret_s8_s64 (int64x1_t)
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vreinterpret_s8_f32 (float32x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vreinterpret_s8_p16 (poly16x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item int8x8_t vreinterpret_s8_p8 (poly8x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vreinterpretq_s8_u32 (uint32x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vreinterpretq_s8_u16 (uint16x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vreinterpretq_s8_u8 (uint8x16_t)
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vreinterpretq_s8_s32 (int32x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vreinterpretq_s8_s16 (int16x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vreinterpretq_s8_u64 (uint64x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vreinterpretq_s8_s64 (int64x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vreinterpretq_s8_f32 (float32x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vreinterpretq_s8_p16 (poly16x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item int8x16_t vreinterpretq_s8_p8 (poly8x16_t)
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vreinterpret_s16_u32 (uint32x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vreinterpret_s16_u16 (uint16x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vreinterpret_s16_u8 (uint8x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vreinterpret_s16_s32 (int32x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vreinterpret_s16_s8 (int8x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vreinterpret_s16_u64 (uint64x1_t)
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vreinterpret_s16_s64 (int64x1_t)
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vreinterpret_s16_f32 (float32x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vreinterpret_s16_p16 (poly16x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item int16x4_t vreinterpret_s16_p8 (poly8x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vreinterpretq_s16_u32 (uint32x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vreinterpretq_s16_u16 (uint16x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vreinterpretq_s16_u8 (uint8x16_t)
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vreinterpretq_s16_s32 (int32x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vreinterpretq_s16_s8 (int8x16_t)
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vreinterpretq_s16_u64 (uint64x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vreinterpretq_s16_s64 (int64x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vreinterpretq_s16_f32 (float32x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vreinterpretq_s16_p16 (poly16x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item int16x8_t vreinterpretq_s16_p8 (poly8x16_t)
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vreinterpret_s32_u32 (uint32x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vreinterpret_s32_u16 (uint16x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vreinterpret_s32_u8 (uint8x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vreinterpret_s32_s16 (int16x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vreinterpret_s32_s8 (int8x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vreinterpret_s32_u64 (uint64x1_t)
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vreinterpret_s32_s64 (int64x1_t)
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vreinterpret_s32_f32 (float32x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vreinterpret_s32_p16 (poly16x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item int32x2_t vreinterpret_s32_p8 (poly8x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vreinterpretq_s32_u32 (uint32x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vreinterpretq_s32_u16 (uint16x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vreinterpretq_s32_u8 (uint8x16_t)
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vreinterpretq_s32_s16 (int16x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vreinterpretq_s32_s8 (int8x16_t)
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vreinterpretq_s32_u64 (uint64x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vreinterpretq_s32_s64 (int64x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vreinterpretq_s32_f32 (float32x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vreinterpretq_s32_p16 (poly16x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item int32x4_t vreinterpretq_s32_p8 (poly8x16_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vreinterpret_u8_u32 (uint32x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vreinterpret_u8_u16 (uint16x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vreinterpret_u8_s32 (int32x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vreinterpret_u8_s16 (int16x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vreinterpret_u8_s8 (int8x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vreinterpret_u8_u64 (uint64x1_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vreinterpret_u8_s64 (int64x1_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vreinterpret_u8_f32 (float32x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vreinterpret_u8_p16 (poly16x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint8x8_t vreinterpret_u8_p8 (poly8x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vreinterpretq_u8_u32 (uint32x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vreinterpretq_u8_u16 (uint16x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vreinterpretq_u8_s32 (int32x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vreinterpretq_u8_s16 (int16x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vreinterpretq_u8_s8 (int8x16_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vreinterpretq_u8_u64 (uint64x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vreinterpretq_u8_s64 (int64x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vreinterpretq_u8_f32 (float32x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vreinterpretq_u8_p16 (poly16x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint8x16_t vreinterpretq_u8_p8 (poly8x16_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vreinterpret_u16_u32 (uint32x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vreinterpret_u16_u8 (uint8x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vreinterpret_u16_s32 (int32x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vreinterpret_u16_s16 (int16x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vreinterpret_u16_s8 (int8x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vreinterpret_u16_u64 (uint64x1_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vreinterpret_u16_s64 (int64x1_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vreinterpret_u16_f32 (float32x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vreinterpret_u16_p16 (poly16x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint16x4_t vreinterpret_u16_p8 (poly8x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vreinterpretq_u16_u32 (uint32x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vreinterpretq_u16_u8 (uint8x16_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vreinterpretq_u16_s32 (int32x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vreinterpretq_u16_s16 (int16x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vreinterpretq_u16_s8 (int8x16_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vreinterpretq_u16_u64 (uint64x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vreinterpretq_u16_s64 (int64x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vreinterpretq_u16_f32 (float32x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vreinterpretq_u16_p16 (poly16x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint16x8_t vreinterpretq_u16_p8 (poly8x16_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vreinterpret_u32_u16 (uint16x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vreinterpret_u32_u8 (uint8x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vreinterpret_u32_s32 (int32x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vreinterpret_u32_s16 (int16x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vreinterpret_u32_s8 (int8x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vreinterpret_u32_u64 (uint64x1_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vreinterpret_u32_s64 (int64x1_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vreinterpret_u32_f32 (float32x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vreinterpret_u32_p16 (poly16x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint32x2_t vreinterpret_u32_p8 (poly8x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vreinterpretq_u32_u16 (uint16x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vreinterpretq_u32_u8 (uint8x16_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vreinterpretq_u32_s32 (int32x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vreinterpretq_u32_s16 (int16x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vreinterpretq_u32_s8 (int8x16_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vreinterpretq_u32_u64 (uint64x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vreinterpretq_u32_s64 (int64x2_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vreinterpretq_u32_f32 (float32x4_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vreinterpretq_u32_p16 (poly16x8_t)
+@end itemize
+
+
+@itemize @bullet
+@item uint32x4_t vreinterpretq_u32_p8 (poly8x16_t)
+@end itemize
+
+
+
+
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 5c74b840131..95d25caa235 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -6404,7 +6404,8 @@ instructions, but allow the compiler to schedule those calls.
 
 @menu
 * Alpha Built-in Functions::
-* ARM Built-in Functions::
+* ARM iWMMXt Built-in Functions::
+* ARM NEON Intrinsics::
 * Blackfin Built-in Functions::
 * FR-V Built-in Functions::
 * X86 Built-in Functions::
@@ -6497,11 +6498,11 @@ void *__builtin_thread_pointer (void)
 void __builtin_set_thread_pointer (void *)
 @end smallexample
 
-@node ARM Built-in Functions
-@subsection ARM Built-in Functions
+@node ARM iWMMXt Built-in Functions
+@subsection ARM iWMMXt Built-in Functions
 
 These built-in functions are available for the ARM family of
-processors, when the @option{-mcpu=iwmmxt} switch is used:
+processors when the @option{-mcpu=iwmmxt} switch is used:
 
 @smallexample
 typedef int v2si __attribute__ ((vector_size (8)));
@@ -6644,6 +6645,14 @@ long long __builtin_arm_wxor (long long, long long)
 long long __builtin_arm_wzero ()
 @end smallexample
 
+@node ARM NEON Intrinsics
+@subsection ARM NEON Intrinsics
+
+These built-in intrinsics for the ARM Advanced SIMD extension are available
+when the @option{-mfpu=neon} switch is used:
+
+@include arm-neon-intrinsics.texi
+
 @node Blackfin Built-in Functions
 @subsection Blackfin Built-in Functions