RISC-V: Introduce rounding mode operand into fixed-point intrinsics

According to new comming fixed-point API:
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/222

Introduce vxrm argument:
- vint32m1_t __riscv_vsadd_vv_i32m1 (vint32m1_t op1, vint32m1_t op2, size_t vl);
+ vint32m1_t __riscv_vsadd_vv_i32m1 (vint32m1_t op1, vint32m1_t op2, size_t vxrm, size_t vl);

This patch doesn't insert vxrm csrw configuration instruction yet.
Will support automatically insert csrw vxrm instruction in the next patch.

This patch does this following:
1. Only extend the vxrm argument.
2. Check vxrm argument is invalid immediate and report error message if it is invalid.

gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins-bases.cc: Introduce rounding mode.
	* config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Ditto.
	(struct narrow_alu_def): Ditto.
	* config/riscv/riscv-vector-builtins.cc (function_builder::apply_predication): Ditto.
	(function_expander::use_exact_insn): Ditto.
	* config/riscv/riscv-vector-builtins.h (function_checker::arg_num): New function.
	(function_base::has_rounding_mode_operand_p): New function.

gcc/testsuite/ChangeLog:

	* g++.target/riscv/rvv/base/bug-11.C: Adapt testcase.
	* g++.target/riscv/rvv/base/bug-12.C: Ditto.
	* g++.target/riscv/rvv/base/bug-14.C: Ditto.
	* g++.target/riscv/rvv/base/bug-15.C: Ditto.
	* g++.target/riscv/rvv/base/bug-16.C: Ditto.
	* g++.target/riscv/rvv/base/bug-17.C: Ditto.
	* g++.target/riscv/rvv/base/bug-18.C: Ditto.
	* g++.target/riscv/rvv/base/bug-19.C: Ditto.
	* g++.target/riscv/rvv/base/bug-20.C: Ditto.
	* g++.target/riscv/rvv/base/bug-21.C: Ditto.
	* g++.target/riscv/rvv/base/bug-22.C: Ditto.
	* g++.target/riscv/rvv/base/bug-23.C: Ditto.
	* g++.target/riscv/rvv/base/bug-3.C: Ditto.
	* g++.target/riscv/rvv/base/bug-5.C: Ditto.
	* g++.target/riscv/rvv/base/bug-6.C: Ditto.
	* g++.target/riscv/rvv/base/bug-8.C: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-100.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-101.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-102.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-103.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-104.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-105.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-106.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-107.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-108.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-109.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-110.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-111.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-112.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-113.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-114.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-115.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-116.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-117.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-118.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-119.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-122.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-97.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-98.c: Ditto.
	* gcc.target/riscv/rvv/base/merge_constraint-1.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-6.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-7.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-8.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-9.c: Ditto.
	* gcc.target/riscv/rvv/base/vxrm-2.c: New test.
	* gcc.target/riscv/rvv/base/vxrm-3.c: New test.
	* gcc.target/riscv/rvv/base/vxrm-4.c: New test.
	* gcc.target/riscv/rvv/base/vxrm-5.c: New test.

1 files changed, 4 insertions, 4 deletions

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-16.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-16.C
index c19d6062483..d90d2d4dc01 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-16.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-16.C
@@ -351,7 +351,7 @@ vbool1_t var_66 = __riscv_vmseq_vx_i8m8_b1(var_68, var_69, 98);
 // 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
 
 __riscv_vsetvl_e8mf2(8);
-vuint8mf2_t var_19 = __riscv_vasubu_vx_u8mf2_tumu(var_20, var_21, var_22, var_75, 8);
+vuint8mf2_t var_19 = __riscv_vasubu_vx_u8mf2_tumu(var_20, var_21, var_22, var_75, 0, 8);
 // 197, 206, 42, 228, 104, 250, 255, 186
 
 vbool16_t var_18 = __riscv_vmfle_vv_f64m4_b16_mu(var_24, var_25, var_26, var_27, 8);
@@ -395,11 +395,11 @@ __riscv_vsetvl_e8m8(120);
 vint8m8_t var_1 = __riscv_vxor_vv_i8m8_tumu(var_11, var_0, var_2, var_2, 120);
 // 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
 
-vuint8m8_t var_8 = __riscv_vasubu_vx_u8m8(var_59, var_13, 120);
+vuint8m8_t var_8 = __riscv_vasubu_vx_u8m8(var_59, var_13, 0, 120);
 // 218, 246, 239, 246, 238, 166, 19, 14, 242, 1, 241, 218, 249, 179, 214, 204, 166, 219, 245, 179, 179, 4, 224, 178, 202, 253, 206, 163, 230, 251, 213, 25, 19, 195, 239, 168, 239, 17, 239, 205, 173, 251, 241, 202, 219, 223, 17, 162, 3, 6, 13, 17, 170, 229, 178, 246, 180, 249, 195, 250, 241, 229, 20, 249, 19, 174, 198, 221, 200, 11, 177, 160, 180, 216, 11, 19, 163, 17, 209, 174, 1, 9, 208, 241, 169, 190, 176, 19, 187, 198, 213, 208, 22, 4, 237, 180, 0, 188, 204, 203, 173, 188, 28, 180, 162, 218, 227, 160, 230, 214, 177, 172, 255, 15, 207, 199, 20, 165, 180, 206
 
 __riscv_vsetvl_e8m8(31);
-vint8m8_t var_17 = __riscv_vssra_vx_i8m8_tumu(var_31, var_12, var_32, var_76, 31);
+vint8m8_t var_17 = __riscv_vssra_vx_i8m8_tumu(var_31, var_12, var_32, var_76, 0, 31);
 // 41, 69, -57, 102, 86, 103, -128, 4, -118, -1, 109, 40, 7, 27, 79, -63, 35, 73, 1, 42, -85, 126, 107, 53, -114, 39, 53, 10, -94, -20, 125, -46, -52, 94, 14, -74, -97, 25, -59, 3, 68, -15, -60, 83, 80, -113, -90, -118, 7, -38, -57, -114, 88, -76, 8, 44, 45, 12, -27, 83, 43, 77, -93, 79, 6, -17, 93, 33, 22, 6, 113, -5, -13, 20, -106, -36, -57, -21, -127, -89, 102, -62, -92, -124, 73, 118, 41, -120, 94, -100, 13, -34, -86, -103, 26, -57, -16, 22, -48, -71, 15, 40, 27, -125, -94, -93, -93, -3, -33, 60, 15, -29, -16, 70, -15, 30, 108, -105, 30, -65
 
 __riscv_vsetvl_e8m8(98);
@@ -407,7 +407,7 @@ vbool1_t var_6 = __riscv_vmseq_vv_i8m8_b1(var_5, var_10, 98);
 // 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
 
 __riscv_vsetvl_e8m8(120);
-vint8m8_t var_4 = __riscv_vssra_vv_i8m8_tumu(var_63, var_1, var_10, var_8, 120);
+vint8m8_t var_4 = __riscv_vssra_vv_i8m8_tumu(var_63, var_1, var_10, var_8, 0, 120);
 // 15, -2, 0, 0, -1, 0, 0, -2, 18, 0, 1, 0, 2, 10, 2, 0, 0, -9, 0, 0, 0, 0, 1, 0, 31, 2, 0, -5, 0, 3, -2, -17, -12, 0, 0, -1, 1, 47, -1, 0, 0, -1, 33, 0, 0, 1, 0, 0, -10, 0, 0, 61, 18, -3, 0, -1, 0, 0, 0, 14, 0, 3, 0, 0, 0, 0, 0, 0, -59, 0, 0, 55, 0, 11, 14, 0, 0, 0, 1, 0, 0, 0, -1, 17, 0, 2, 0, 0, -5, -1, 1, 0, 1, 6, 0, 0, 107, 0, 7, 0, 0, 0, 5, 7, 0, 0, 0, -1, 0, 0, -8, 0, 0, 0, -1, 0, -8, 1, 0, 0
 
 __riscv_vsetvl_e8m8(31);